summaryrefslogtreecommitdiff
path: root/arch/parisc/include/asm/cache.h
diff options
context:
space:
mode:
authorStefan Agner <stefan.agner@toradex.com>2019-06-03 10:59:09 +0200
committerStefan Agner <stefan.agner@toradex.com>2019-06-03 10:59:09 +0200
commit2115c1bc6e396d5ffe9ecbe394d1c50a6e25c404 (patch)
tree20fff445991414f23c0a29237940b75cd756de86 /arch/parisc/include/asm/cache.h
parentb794ea49ba3816c0d5cf05506964a8e69ce4efa3 (diff)
parent3f7c1cab1a61108821cf47dda8a32ed25cc3588b (diff)
Merge tag 'v5.0.19' into toradex_5.0.ytoradex_5.0.y
This is the 5.0.19 stable release
Diffstat (limited to 'arch/parisc/include/asm/cache.h')
-rw-r--r--arch/parisc/include/asm/cache.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h
index 006fb939cac8..4016fe1c65a9 100644
--- a/arch/parisc/include/asm/cache.h
+++ b/arch/parisc/include/asm/cache.h
@@ -44,22 +44,22 @@ void parisc_setup_cache_timing(void);
#define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" \
ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
- : : "r" (addr))
+ : : "r" (addr) : "memory")
#define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" \
ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
ALTERNATIVE(ALT_COND_NO_SPLIT_TLB, INSN_NOP) \
- : : "r" (addr))
+ : : "r" (addr) : "memory")
#define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" \
ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
- : : "r" (addr))
+ : : "r" (addr) : "memory")
#define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \
ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) \
- : : "r" (addr))
+ : : "r" (addr) : "memory")
#define asm_io_sync() asm volatile("sync" \
ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
- ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :: )
+ ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :::"memory")
#endif /* ! __ASSEMBLY__ */