diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2019-11-12 13:57:30 +0100 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2019-11-12 13:57:30 +0100 |
| commit | 401bf3f29b1aa6d9ca32bd3252fc9beabe93d80b (patch) | |
| tree | 6dd86325823a9b44b6e696acbd077e68c47d3108 /arch/arm64/Kconfig | |
| parent | 5a9c845fe261dec87f892f3fd3c2e32604d952c0 (diff) | |
| parent | b260a0862e3a9fccdac23ec3b783911b098c1c74 (diff) | |
Merge tag 'v5.3.10' into toradex_5.3.ytoradex_5.3.y
This is the 5.3.10 stable release
Diffstat (limited to 'arch/arm64/Kconfig')
| -rw-r--r-- | arch/arm64/Kconfig | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 3adcec05b1f6..f63b824cdc2d 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -111,7 +111,7 @@ config ARM64 select GENERIC_STRNLEN_USER select GENERIC_TIME_VSYSCALL select GENERIC_GETTIMEOFDAY - select GENERIC_COMPAT_VDSO if (!CPU_BIG_ENDIAN && COMPAT) + select GENERIC_COMPAT_VDSO if (!CPU_BIG_ENDIAN && COMPAT && "$(CROSS_COMPILE_COMPAT)" != "") select HANDLE_DOMAIN_IRQ select HARDIRQS_SW_RESEND select HAVE_PCI @@ -601,6 +601,23 @@ config CAVIUM_ERRATUM_30115 If unsure, say Y. +config CAVIUM_TX2_ERRATUM_219 + bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" + default y + help + On Cavium ThunderX2, a load, store or prefetch instruction between a + TTBR update and the corresponding context synchronizing operation can + cause a spurious Data Abort to be delivered to any hardware thread in + the CPU core. + + Work around the issue by avoiding the problematic code sequence and + trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The + trap handler performs the corresponding register access, skips the + instruction and ensures context synchronization by virtue of the + exception return. + + If unsure, say Y. + config QCOM_FALKOR_ERRATUM_1003 bool "Falkor E1003: Incorrect translation due to ASID change" default y |