diff options
| author | Parth Pancholi <parth.pancholi@toradex.com> | 2024-04-16 10:36:58 +0200 |
|---|---|---|
| committer | Parth Pancholi <parth.pancholi@toradex.com> | 2024-04-16 19:01:42 +0200 |
| commit | f94654d97f056f4fc8f8b5bf622b7dd98beda706 (patch) | |
| tree | 4175da92e0f35f1d795a1b57ff6620a96f291c7a | |
| parent | be2eaebf08c7789142595b73910ebf1d12d1ef0f (diff) | |
phy: ti: gmii-sel: Enable SGMII mode for J784S4
TI's J784S4 SoC supports SGMII mode for CPSW9G instance's MAC ports.
Add SGMII mode to the extra_modes member of J784S4's SoC data.
Upstream-Status: Pending
Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com>
| -rw-r--r-- | drivers/phy/ti/phy-gmii-sel.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index 2828f888ad92..df8b41fb3731 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -249,6 +249,7 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = { .use_of_data = true, .regfields = phy_gmii_sel_fields_am654, .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | + BIT(PHY_INTERFACE_MODE_SGMII) | BIT(PHY_INTERFACE_MODE_USXGMII), .num_ports = 8, .num_qsgmii_main_ports = 2, |