From f94654d97f056f4fc8f8b5bf622b7dd98beda706 Mon Sep 17 00:00:00 2001 From: Parth Pancholi Date: Tue, 16 Apr 2024 10:36:58 +0200 Subject: phy: ti: gmii-sel: Enable SGMII mode for J784S4 TI's J784S4 SoC supports SGMII mode for CPSW9G instance's MAC ports. Add SGMII mode to the extra_modes member of J784S4's SoC data. Upstream-Status: Pending Signed-off-by: Parth Pancholi --- drivers/phy/ti/phy-gmii-sel.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index 2828f888ad92..df8b41fb3731 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -249,6 +249,7 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = { .use_of_data = true, .regfields = phy_gmii_sel_fields_am654, .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | + BIT(PHY_INTERFACE_MODE_SGMII) | BIT(PHY_INTERFACE_MODE_USXGMII), .num_ports = 8, .num_qsgmii_main_ports = 2, -- cgit v1.2.3