diff options
author | Parth Pancholi <parth.pancholi@toradex.com> | 2024-04-16 10:26:56 +0200 |
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committer | Parth Pancholi <parth.pancholi@toradex.com> | 2024-04-16 19:01:21 +0200 |
commit | be2eaebf08c7789142595b73910ebf1d12d1ef0f (patch) | |
tree | 3c9203b2b7749eda628f7923b826175632e17823 | |
parent | 0a98d809cd93e2e8340de7b99af0e32a4c9ae7c6 (diff) |
net: ethernet: ti: am65-cpsw: Enable SGMII mode for J784S4 CPSW9G
TI's J784S4 SoC supports SGMII mode. Add SGMII mode to the
extra_modes member of the J784S4 SoC data.
Upstream-Status: Pending
Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com>
-rw-r--r-- | drivers/net/ethernet/ti/am65-cpsw-nuss.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 684c6e120e1c..b5f1e6f5d5af 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -2899,7 +2899,8 @@ static const struct am65_cpsw_pdata j784s4_cpswxg_pdata = { .quirks = 0, .ale_dev_id = "am64-cpswxg", .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, - .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_USXGMII), + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | + BIT(PHY_INTERFACE_MODE_USXGMII), }; static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { |