diff options
| author | Troy Kisky <troy.kisky@boundarydevices.com> | 2012-12-01 20:51:28 -0700 |
|---|---|---|
| committer | Eric Nelson <eric.nelson@boundarydevices.com> | 2013-02-12 10:46:55 -0700 |
| commit | 253d398c00df00d4d13d5f0bf5140729472a94be (patch) | |
| tree | eb39b438cbddb7a8370b2dffab48d211cfbe819f | |
| parent | 1276603865e7f4a36f68a01b4fec79c44156956a (diff) | |
fec: enable tx/rx of pause frames for mx6q
I don't know what ticket TKT116501 is but
I don't see a problem with pause frame
enabled on rev 1.0 silicon.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| -rw-r--r-- | drivers/net/fec.c | 36 |
1 files changed, 17 insertions, 19 deletions
diff --git a/drivers/net/fec.c b/drivers/net/fec.c index 35a6ee6d9661..780614710b59 100644 --- a/drivers/net/fec.c +++ b/drivers/net/fec.c @@ -1040,9 +1040,10 @@ static int fec_enet_mii_probe(struct net_device *ndev) } /* mask with MAC supported features */ - if (cpu_is_mx6q() || cpu_is_mx6dl()) - phy_dev->supported &= PHY_GBIT_FEATURES; - else + if (cpu_is_mx6q() || cpu_is_mx6dl()) { + /* SUPPORTED_Asym_Pause prevents my switch from linking up */ + phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause; + } else phy_dev->supported &= PHY_BASIC_FEATURES; /* enable phy pause frame for any platform */ @@ -1657,12 +1658,9 @@ fec_restart(struct net_device *dev, int duplex) * ENET pause frame has two issues as ticket TKT116501 * The issues have been fixed on Rigel TO1.1 and Arik TO1.2 */ - if ((cpu_is_mx6q() && - (mx6q_revision() >= IMX_CHIP_REVISION_1_2)) || - (cpu_is_mx6dl() && - (mx6dl_revision() >= IMX_CHIP_REVISION_1_1))) + if (cpu_is_mx6q() || (cpu_is_mx6dl() + && (mx6dl_revision() >= IMX_CHIP_REVISION_1_1))) val |= FEC_ENET_FCE; - writel(val, fep->hwp + FEC_R_CNTRL); } @@ -1716,24 +1714,24 @@ fec_restart(struct net_device *dev, int duplex) fep->phy_dev->speed == SPEED_1000) val |= (0x1 << 5); - /* RX FIFO threshold setting for ENET pause frame feature - * Only set the parameters after ticket TKT116501 fixed. - * The issue has been fixed on Rigel TO1.1 and Arik TO1.2 - */ - if ((cpu_is_mx6q() && - (mx6q_revision() >= IMX_CHIP_REVISION_1_2)) || - (cpu_is_mx6dl() && - (mx6dl_revision() >= IMX_CHIP_REVISION_1_1))) { - writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); + if (cpu_is_mx6q() || cpu_is_mx6dl()) { + u32 rsem_val = 0; + /* RX FIFO threshold setting for ENET pause frame feature + * Only set the parameters after ticket TKT116501 fixed. + * The issue has been fixed on Rigel TO1.1 and Arik TO1.2 + */ + if (cpu_is_mx6q() || (cpu_is_mx6dl() + && (mx6dl_revision() >= IMX_CHIP_REVISION_1_1))) + rsem_val = FEC_ENET_RSEM_V; + + writel(rsem_val, fep->hwp + FEC_R_FIFO_RSEM); writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); /* OPD */ writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); - } - if (cpu_is_mx6q() || cpu_is_mx6dl()) { /* enable endian swap */ val |= (0x1 << 8); /* enable ENET store and forward mode */ |