/hal/cortexm/vybrid/../vybrid_misc.c

Added new functions for easier GPIO handling

1 files changed, 23 insertions, 0 deletions

diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c
index aa0e4fa..2d0f666 100644
--- a/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c
@@ -196,6 +196,29 @@ hal_dump_pin_function(cyg_uint32 pin)
 	diag_printf("Pin PT%c%d: IOMUX=0x08%x\n",0x41+port,bit,mux_val);
 }
 
+inline void
+hal_gpio_set_pin(cyg_uint32 pin)
+{
+	CYGHWR_HAL_VYBRID_GPIO_SET_PIN(vf61_pads[CYGHWR_HAL_VYBRID_PIN_PORT(pin)*32+CYGHWR_HAL_VYBRID_PIN_BIT(pin)]);
+}
+
+inline void
+hal_gpio_clear_pin(cyg_uint32 pin)
+{
+	CYGHWR_HAL_VYBRID_GPIO_CLEAR_PIN(vf61_pads[CYGHWR_HAL_VYBRID_PIN_PORT(pin)*32+CYGHWR_HAL_VYBRID_PIN_BIT(pin)]);
+}
+
+inline void
+hal_gpio_toggle_pin(cyg_uint32 pin)
+{
+	CYGHWR_HAL_VYBRID_GPIO_TOGGLE_PIN(vf61_pads[CYGHWR_HAL_VYBRID_PIN_PORT(pin)*32+CYGHWR_HAL_VYBRID_PIN_BIT(pin)]);
+}
+
+inline cyg_uint32
+hal_gpio_get_pin(cyg_uint32 pin)
+{
+	return CYGHWR_HAL_VYBRID_GPIO_GET_PIN(vf61_pads[CYGHWR_HAL_VYBRID_PIN_PORT(pin)*32+CYGHWR_HAL_VYBRID_PIN_BIT(pin)])?1:0;
+}
 //==========================================================================
 // VYBRID Clock distribution
 //==========================================================================