From 7c786065b12344ada19e11fa1043555dfeda478a Mon Sep 17 00:00:00 2001 From: Nithin Sujir Date: Fri, 6 Dec 2013 09:53:17 -0800 Subject: tg3: Add flag to disable 1G Half Duplex advertisement Some link partners have issues if the non-standard 1G half duplex is advertised. This patch adds support for an nvram setting to disable the advertisement. Signed-off-by: Nithin Nayak Sujir Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/ethernet/broadcom/tg3.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/net/ethernet/broadcom/tg3.h') diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h index 5c3835aa1e1b..e128f37282d7 100644 --- a/drivers/net/ethernet/broadcom/tg3.h +++ b/drivers/net/ethernet/broadcom/tg3.h @@ -2226,6 +2226,9 @@ #define NIC_SRAM_CPMUSTAT_SIG 0x0000362c #define NIC_SRAM_CPMUSTAT_SIG_MSK 0x0000ffff +#define NIC_SRAM_DATA_CFG_5 0x00000e0c +#define NIC_SRAM_DISABLE_1G_HALF_ADV 0x00000002 + #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 @@ -3325,6 +3328,7 @@ struct tg3 { #define TG3_PHYFLG_1G_ON_VAUX_OK 0x00080000 #define TG3_PHYFLG_KEEP_LINK_ON_PWRDN 0x00100000 #define TG3_PHYFLG_MDIX_STATE 0x00200000 +#define TG3_PHYFLG_DISABLE_1G_HD_ADV 0x00400000 u32 led_ctrl; u32 phy_otp; -- cgit v1.2.3 From efe8f0eaaed3c5ebc19cc34ddf012dfdf6f3747d Mon Sep 17 00:00:00 2001 From: Nithin Sujir Date: Fri, 6 Dec 2013 09:53:18 -0800 Subject: tg3: Fix bit definition for the nvram Auto Power Down setting The APD bit is 14 and not bit 10. Signed-off-by: Nithin Nayak Sujir Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/ethernet/broadcom/tg3.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/net/ethernet/broadcom/tg3.h') diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h index e128f37282d7..e4da9d7834ce 100644 --- a/drivers/net/ethernet/broadcom/tg3.h +++ b/drivers/net/ethernet/broadcom/tg3.h @@ -2204,7 +2204,7 @@ #define NIC_SRAM_DATA_CFG_2 0x00000d38 -#define NIC_SRAM_DATA_CFG_2_APD_EN 0x00000400 +#define NIC_SRAM_DATA_CFG_2_APD_EN 0x00004000 #define SHASTA_EXT_LED_MODE_MASK 0x00018000 #define SHASTA_EXT_LED_LEGACY 0x00000000 #define SHASTA_EXT_LED_SHARED 0x00008000 -- cgit v1.2.3 From f82995b65c44f353358179f4e2745cf967e00b31 Mon Sep 17 00:00:00 2001 From: Nithin Sujir Date: Fri, 3 Jan 2014 10:09:13 -0800 Subject: tg3: Set the MAC clock to the fastest speed during boot code load On the 5717, 5718 and 5719 devices, the bootcode runs slower when any port doesn't have a link due to clock speed slowing down as part of the link-aware feature. This leads to the driver timing out waiting for the bootcode signature. This patch overrides the clock policy to the highest frequency just before reset and restores it after the bootcode is up. Signed-off-by: Nithin Nayak Sujir Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/ethernet/broadcom/tg3.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/net/ethernet/broadcom/tg3.h') diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h index e4da9d7834ce..9e31eccc250b 100644 --- a/drivers/net/ethernet/broadcom/tg3.h +++ b/drivers/net/ethernet/broadcom/tg3.h @@ -1146,6 +1146,9 @@ #define TG3_CPMU_CLCK_ORIDE 0x00003624 #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 +#define TG3_CPMU_CLCK_ORIDE_ENABLE 0x00003628 +#define TG3_CPMU_MAC_ORIDE_ENABLE (1 << 13) + #define TG3_CPMU_STATUS 0x0000362c #define TG3_CPMU_STATUS_FMSK_5717 0x20000000 #define TG3_CPMU_STATUS_FMSK_5719 0xc0000000 -- cgit v1.2.3 From 1743b83c86b5dc525463a1bc9c701b4d9e428c5b Mon Sep 17 00:00:00 2001 From: Nithin Sujir Date: Fri, 3 Jan 2014 10:09:14 -0800 Subject: tg3: Poll cpmu link state on APE + ASF enabled devices On ASF enabled devices where the mgmt firmware runs on the application processing engine, there is a race between the tg3 driver processing a link change event and the ASF firmware clearing the link changed bit in the EMAC status register. This leads to link notifications to the driver sometimes getting lost. Poll the CPMU link state as a backup for the normal interrupt path update if ASF is enabled. Signed-off-by: Nithin Nayak Sujir Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/ethernet/broadcom/tg3.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/net/ethernet/broadcom/tg3.h') diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h index 9e31eccc250b..ef472385bce4 100644 --- a/drivers/net/ethernet/broadcom/tg3.h +++ b/drivers/net/ethernet/broadcom/tg3.h @@ -1153,6 +1153,7 @@ #define TG3_CPMU_STATUS_FMSK_5717 0x20000000 #define TG3_CPMU_STATUS_FMSK_5719 0xc0000000 #define TG3_CPMU_STATUS_FSHFT_5719 30 +#define TG3_CPMU_STATUS_LINK_MASK 0x180000 #define TG3_CPMU_CLCK_STAT 0x00003630 #define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000 @@ -3020,6 +3021,7 @@ enum TG3_FLAGS { TG3_FLAG_ENABLE_ASF, TG3_FLAG_ASPM_WORKAROUND, TG3_FLAG_POLL_SERDES, + TG3_FLAG_POLL_CPMU_LINK, TG3_FLAG_MBOX_WRITE_REORDER, TG3_FLAG_PCIX_TARGET_HWBUG, TG3_FLAG_WOL_SPEED_100MB, -- cgit v1.2.3