From f27f47ef5b67106ff1cdeebf061387a7b30c12bc Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 26 May 2010 14:41:53 -0700 Subject: sdhci: implement CAP_CLOCK_BASE_BROKEN quirk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some hosts (e.g. as found in CNS3xxx SOCs) report wrong value in CLOCK_BASE capability field, and currently there is no way to force the SDHCI core to use the platform-provided base clock value. This patch implements CAP_CLOCK_BASE_BROKEN quirk. When enabled, the SDHCI core will always use base clock frequency provided by the platform. Signed-off-by: Anton Vorontsov Cc: Richard Röjfors Cc: David Vrabel Cc: Pierre Ossman Cc: Ben Dooks Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/sdhci.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/mmc/host/sdhci.h') diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 842f46f94284..831bf7f137f6 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -236,6 +236,8 @@ struct sdhci_host { #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) /* Controller uses SDCLK instead of TMCLK for data timeouts */ #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) +/* Controller reports wrong base clock capability */ +#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) int irq; /* Device IRQ */ void __iomem * ioaddr; /* Mapped address */ -- cgit v1.2.3 From a751a7d69fe91e4640884ae02fe44ddceb7f4cd8 Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Wed, 26 May 2010 14:42:02 -0700 Subject: mmc: SDHCI_INT_DATA_MASK typo error Signed-off-by: Zhangfei Gao Reviewed-by: Matt Fleming Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/sdhci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mmc/host/sdhci.h') diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 831bf7f137f6..47c1360cc2a3 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -127,7 +127,7 @@ #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ - SDHCI_INT_DATA_END_BIT | SDHCI_ADMA_ERROR) + SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) #define SDHCI_INT_ALL_MASK ((unsigned int)-1) #define SDHCI_ACMD12_ERR 0x3C -- cgit v1.2.3 From dc297c92e6e63af5cbd7e7d2f377247f5664a378 Mon Sep 17 00:00:00 2001 From: Matt Fleming Date: Wed, 26 May 2010 14:42:03 -0700 Subject: sdhci: build fix: rename SDHCI I/O accessor functions Unfortunately some architectures #define their read{b,w,l} and write{b,w,l} I/O accessors which makes the SDHCI I/O accessor functions of the same names subject to preprocessing. This leads to the following compiler error, In file included from drivers/mmc/host/sdhci.c:26: drivers/mmc/host/sdhci.h:318:35: error: macro "writel" passed 3 arguments, but takes just 2 Rename the SDHCI I/O functions so that CONFIG_MMC_SDHCI_IO_ACCESSORS can be enabled for architectures that implement their read{b,w,l} and write{b,w,l} functions with macros. Signed-off-by: Matt Fleming Cc: Zhangfei Gao Acked-by: Anton Vorontsov Acked-by: Wolfram Sang Acked-by: Ben Dooks Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/sdhci.h | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) (limited to 'drivers/mmc/host/sdhci.h') diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 47c1360cc2a3..af08a1935b06 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -296,12 +296,12 @@ struct sdhci_host { struct sdhci_ops { #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS - u32 (*readl)(struct sdhci_host *host, int reg); - u16 (*readw)(struct sdhci_host *host, int reg); - u8 (*readb)(struct sdhci_host *host, int reg); - void (*writel)(struct sdhci_host *host, u32 val, int reg); - void (*writew)(struct sdhci_host *host, u16 val, int reg); - void (*writeb)(struct sdhci_host *host, u8 val, int reg); + u32 (*read_l)(struct sdhci_host *host, int reg); + u16 (*read_w)(struct sdhci_host *host, int reg); + u8 (*read_b)(struct sdhci_host *host, int reg); + void (*write_l)(struct sdhci_host *host, u32 val, int reg); + void (*write_w)(struct sdhci_host *host, u16 val, int reg); + void (*write_b)(struct sdhci_host *host, u8 val, int reg); #endif void (*set_clock)(struct sdhci_host *host, unsigned int clock); @@ -316,48 +316,48 @@ struct sdhci_ops { static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) { - if (unlikely(host->ops->writel)) - host->ops->writel(host, val, reg); + if (unlikely(host->ops->write_l)) + host->ops->write_l(host, val, reg); else writel(val, host->ioaddr + reg); } static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) { - if (unlikely(host->ops->writew)) - host->ops->writew(host, val, reg); + if (unlikely(host->ops->write_w)) + host->ops->write_w(host, val, reg); else writew(val, host->ioaddr + reg); } static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) { - if (unlikely(host->ops->writeb)) - host->ops->writeb(host, val, reg); + if (unlikely(host->ops->write_b)) + host->ops->write_b(host, val, reg); else writeb(val, host->ioaddr + reg); } static inline u32 sdhci_readl(struct sdhci_host *host, int reg) { - if (unlikely(host->ops->readl)) - return host->ops->readl(host, reg); + if (unlikely(host->ops->read_l)) + return host->ops->read_l(host, reg); else return readl(host->ioaddr + reg); } static inline u16 sdhci_readw(struct sdhci_host *host, int reg) { - if (unlikely(host->ops->readw)) - return host->ops->readw(host, reg); + if (unlikely(host->ops->read_w)) + return host->ops->read_w(host, reg); else return readw(host->ioaddr + reg); } static inline u8 sdhci_readb(struct sdhci_host *host, int reg) { - if (unlikely(host->ops->readb)) - return host->ops->readb(host, reg); + if (unlikely(host->ops->read_b)) + return host->ops->read_b(host, reg); else return readb(host->ioaddr + reg); } -- cgit v1.2.3 From 70764a905785ebacc8d44fed7a12fba3db267ae6 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Wed, 26 May 2010 14:42:04 -0700 Subject: mmc: s3c6410: add new quirk in sdhci driver and update ADMA descriptor build The s3c6410 sdhci controller does not support the 'End' attribute and NOP attribute in the same 8-Byte ADMA descriptor. This patch adds a new quirk to identify sdhci host contollers with such behaviour. In addition to this, for controllers using the new quirk, the last entry in the ADMA descritor table is marked with the 'End' attribute (instead of using a NOP descriptor with 'End' attribute). Signed-off-by: Maurus Cuelenaere Signed-off-by: Thomas Abraham Acked-by: Ben Dooks Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/sdhci.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/mmc/host/sdhci.h') diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index af08a1935b06..c8468134adc9 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -238,6 +238,8 @@ struct sdhci_host { #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) /* Controller reports wrong base clock capability */ #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) +/* Controller cannot support End Attribute in NOP ADMA descriptor */ +#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) int irq; /* Device IRQ */ void __iomem * ioaddr; /* Mapped address */ -- cgit v1.2.3