From 32231a66b4e1b649c346dc76b7d191f7e64a663a Mon Sep 17 00:00:00 2001 From: Al Viro Date: Sat, 21 Jul 2007 19:18:57 -0700 Subject: [SPARC32]: clean include/asm-sparc/irq.h Move stuff used only by arch/sparc/kernel/* into arch/sparc/kernel/irq.h and into individual files in there (e.g. macros internal to sun4m_irq.c, etc.) Signed-off-by: Al Viro Signed-off-by: David S. Miller --- arch/sparc/kernel/sun4c_irq.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/sparc/kernel/sun4c_irq.c') diff --git a/arch/sparc/kernel/sun4c_irq.c b/arch/sparc/kernel/sun4c_irq.c index 009e891a4329..c6ac9fc52563 100644 --- a/arch/sparc/kernel/sun4c_irq.c +++ b/arch/sparc/kernel/sun4c_irq.c @@ -18,6 +18,7 @@ #include #include #include +#include "irq.h" #include #include @@ -40,6 +41,20 @@ static struct resource sun4c_timer_eb = { "sun4c_timer" }; static struct resource sun4c_intr_eb = { "sun4c_intr" }; #endif +/* + * Bit field defines for the interrupt registers on various + * Sparc machines. + */ + +/* The sun4c interrupt register. */ +#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */ +#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */ +#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */ +#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */ +#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */ +#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */ +#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */ + /* Pointer to the interrupt enable byte * * Dave Redman (djhr@tadpole.co.uk) -- cgit v1.2.3