From 9584c55a5cc0db82329dd1142ca570e2d64ea491 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:41:01 +0000 Subject: MIPS: Netlogic: Split reset code out of smpboot.S The reset and core initialization code should be available for uniprocessor as well. This changes is just to take out the code into a different file, without any change to the logic. The change for uniprocessor initialization code is in a later patch. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5423/ Signed-off-by: Ralf Baechle --- arch/mips/netlogic/xlp/wakeup.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/mips/netlogic/xlp/wakeup.c') diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c index abb3e08cc052..1a7d529fcec0 100644 --- a/arch/mips/netlogic/xlp/wakeup.c +++ b/arch/mips/netlogic/xlp/wakeup.c @@ -137,6 +137,7 @@ void xlp_wakeup_secondary_cpus() * In case of u-boot, the secondaries are in reset * first wakeup core 0 threads */ + nlm_init_boot_cpu(); xlp_boot_core0_siblings(); /* now get other cores out of reset */ -- cgit v1.2.3 From 571886b2a52395f030d439c6259663a033e11e6a Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:41:02 +0000 Subject: MIPS: Netlogic: Initialization when !CONFIG_SMP The core initialization and reset vector setup needs to be done even when booting uniprocessor. Move this code from smp.c to setup.c Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5428/ Signed-off-by: Ralf Baechle --- arch/mips/netlogic/xlp/wakeup.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/mips/netlogic/xlp/wakeup.c') diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c index 1a7d529fcec0..abb3e08cc052 100644 --- a/arch/mips/netlogic/xlp/wakeup.c +++ b/arch/mips/netlogic/xlp/wakeup.c @@ -137,7 +137,6 @@ void xlp_wakeup_secondary_cpus() * In case of u-boot, the secondaries are in reset * first wakeup core 0 threads */ - nlm_init_boot_cpu(); xlp_boot_core0_siblings(); /* now get other cores out of reset */ -- cgit v1.2.3 From 919f9abb3723f088290c62648b12fbfc7600d923 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:41:04 +0000 Subject: MIPS: Netlogic: move cpu_ready array to boot area Move the nlm_cpu_ready[] array used by the cpu wakeup code to the boot area, along with rest of the boot parameter code. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5425/ Signed-off-by: Ralf Baechle --- arch/mips/netlogic/xlp/wakeup.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/mips/netlogic/xlp/wakeup.c') diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c index abb3e08cc052..feb573670f90 100644 --- a/arch/mips/netlogic/xlp/wakeup.c +++ b/arch/mips/netlogic/xlp/wakeup.c @@ -82,6 +82,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) struct nlm_soc_info *nodep; uint64_t syspcibase; uint32_t syscoremask; + volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); int core, n, cpu, count, val; for (n = 0; n < NLM_NR_NODES; n++) { @@ -125,7 +126,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) /* spin until the first hw thread sets its ready */ count = 0x20000000; do { - val = *(volatile int *)&nlm_cpu_ready[cpu]; + val = cpu_ready[cpu]; } while (val == 0 && --count > 0); } } -- cgit v1.2.3 From 4033d38ceb9d84ed66b925c1740c1a88f8a4a8f9 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Mon, 10 Jun 2013 06:41:07 +0000 Subject: MIPS: Netlogic: wait for all hardware threads Earlier we just waited for the first thread of the CPU to come online before proceeding to wake up others. Update it to wait for all the CPUs in the core. This will be useful when the boot-up is slow, like while debugging or when running in a simulator. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5429/ Signed-off-by: Ralf Baechle --- arch/mips/netlogic/xlp/wakeup.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) (limited to 'arch/mips/netlogic/xlp/wakeup.c') diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c index feb573670f90..0cce37cbffef 100644 --- a/arch/mips/netlogic/xlp/wakeup.c +++ b/arch/mips/netlogic/xlp/wakeup.c @@ -77,13 +77,28 @@ static int xlp_wakeup_core(uint64_t sysbase, int node, int core) return count != 0; } +static int wait_for_cpus(int cpu, int bootcpu) +{ + volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); + int i, count, notready; + + count = 0x20000000; + do { + notready = nlm_threads_per_core; + for (i = 0; i < nlm_threads_per_core; i++) + if (cpu_ready[cpu + i] || cpu == bootcpu) + --notready; + } while (notready != 0 && --count > 0); + + return count != 0; +} + static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) { struct nlm_soc_info *nodep; uint64_t syspcibase; uint32_t syscoremask; - volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); - int core, n, cpu, count, val; + int core, n, cpu; for (n = 0; n < NLM_NR_NODES; n++) { syspcibase = nlm_get_sys_pcibase(n); @@ -123,11 +138,8 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) /* core is up */ nodep->coremask |= 1u << core; - /* spin until the first hw thread sets its ready */ - count = 0x20000000; - do { - val = cpu_ready[cpu]; - } while (val == 0 && --count > 0); + /* spin until the hw threads sets their ready */ + wait_for_cpus(cpu, 0); } } } @@ -139,6 +151,7 @@ void xlp_wakeup_secondary_cpus() * first wakeup core 0 threads */ xlp_boot_core0_siblings(); + wait_for_cpus(0, 0); /* now get other cores out of reset */ xlp_enable_secondary_cores(&nlm_cpumask); -- cgit v1.2.3