From 0c9654072a6e15aa3da9b314f0c5c01e90938268 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Fri, 11 Nov 2011 17:08:29 +0530 Subject: MIPS: Netlogic: Move code common with XLP to common/ - Move code that can be shared with XLP (irq.c, smp.c, time.c and xlr_console.c) to arch/mips/netlogic/common - Add asm/netlogic/haldefs.h and asm/netlogic/common.h for common and io functions shared with XLP - remove type 'nlm_reg_t *' and use uint64_t for mmio offsets - Move XLR specific code in smp.c to xlr/wakeup.c - Move XLR specific PCI code from irq.c to mips/pci/pci-xlr.c - Provide API for pic functions called from common/irq.c Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2964/ Signed-off-by: Ralf Baechle --- arch/mips/netlogic/common/smp.c | 188 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 188 insertions(+) create mode 100644 arch/mips/netlogic/common/smp.c (limited to 'arch/mips/netlogic/common/smp.c') diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c new file mode 100644 index 000000000000..3b32c834d14c --- /dev/null +++ b/arch/mips/netlogic/common/smp.c @@ -0,0 +1,188 @@ +/* + * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights + * reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the NetLogic + * license below: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include +#include + +void nlm_send_ipi_single(int logical_cpu, unsigned int action) +{ + int cpu = cpu_logical_map(logical_cpu); + + if (action & SMP_CALL_FUNCTION) + nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_FUNCTION, 0); + if (action & SMP_RESCHEDULE_YOURSELF) + nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_RESCHEDULE, 0); +} + +void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) +{ + int cpu; + + for_each_cpu(cpu, mask) { + nlm_send_ipi_single(cpu, action); + } +} + +/* IRQ_IPI_SMP_FUNCTION Handler */ +void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc) +{ + smp_call_function_interrupt(); + write_c0_eirr(1ull << irq); +} + +/* IRQ_IPI_SMP_RESCHEDULE handler */ +void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc) +{ + scheduler_ipi(); + write_c0_eirr(1ull << irq); +} + +/* + * Called before going into mips code, early cpu init + */ +void nlm_early_init_secondary(int cpu) +{ + write_c0_ebase((uint32_t)nlm_common_ebase); +#ifdef NLM_XLP + if (cpu % 4 == 0) + xlp_mmu_init(); +#endif +} + +/* + * Code to run on secondary just after probing the CPU + */ +static void __cpuinit nlm_init_secondary(void) +{ + nlm_smp_irq_init(); +} + +void nlm_smp_finish(void) +{ +#ifdef notyet + nlm_common_msgring_cpu_init(); +#endif + local_irq_enable(); +} + +void nlm_cpus_done(void) +{ +} + +/* + * Boot all other cpus in the system, initialize them, and bring them into + * the boot function + */ +int nlm_cpu_unblock[NR_CPUS]; +int nlm_cpu_ready[NR_CPUS]; +unsigned long nlm_next_gp; +unsigned long nlm_next_sp; +cpumask_t phys_cpu_present_map; + +void nlm_boot_secondary(int logical_cpu, struct task_struct *idle) +{ + unsigned long gp = (unsigned long)task_thread_info(idle); + unsigned long sp = (unsigned long)__KSTK_TOS(idle); + int cpu = cpu_logical_map(logical_cpu); + + nlm_next_sp = sp; + nlm_next_gp = gp; + + /* barrier */ + __sync(); + nlm_cpu_unblock[cpu] = 1; +} + +void __init nlm_smp_setup(void) +{ + unsigned int boot_cpu; + int num_cpus, i; + + boot_cpu = hard_smp_processor_id(); + cpus_clear(phys_cpu_present_map); + + cpu_set(boot_cpu, phys_cpu_present_map); + __cpu_number_map[boot_cpu] = 0; + __cpu_logical_map[0] = boot_cpu; + cpu_set(0, cpu_possible_map); + + num_cpus = 1; + for (i = 0; i < NR_CPUS; i++) { + /* + * nlm_cpu_ready array is not set for the boot_cpu, + * it is only set for ASPs (see smpboot.S) + */ + if (nlm_cpu_ready[i]) { + cpu_set(i, phys_cpu_present_map); + __cpu_number_map[i] = num_cpus; + __cpu_logical_map[num_cpus] = i; + cpu_set(num_cpus, cpu_possible_map); + ++num_cpus; + } + } + + pr_info("Phys CPU present map: %lx, possible map %lx\n", + (unsigned long)phys_cpu_present_map.bits[0], + (unsigned long)cpu_possible_map.bits[0]); + + pr_info("Detected %i Slave CPU(s)\n", num_cpus); +} + +void nlm_prepare_cpus(unsigned int max_cpus) +{ +} + +struct plat_smp_ops nlm_smp_ops = { + .send_ipi_single = nlm_send_ipi_single, + .send_ipi_mask = nlm_send_ipi_mask, + .init_secondary = nlm_init_secondary, + .smp_finish = nlm_smp_finish, + .cpus_done = nlm_cpus_done, + .boot_secondary = nlm_boot_secondary, + .smp_setup = nlm_smp_setup, + .prepare_cpus = nlm_prepare_cpus, +}; -- cgit v1.2.3 From 65040e224e5b214a93fa0c790add5d69b054ecae Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Wed, 16 Nov 2011 00:21:28 +0000 Subject: MIPS: Netlogic: Add XLP platform files for XLP SoC - Update common files to support XLP. - Add arch/mips/include/asm/netlogic/xlp-hal for register definitions and access macros - Add arch/mips/netlogic/xlp/ for XLP specific files. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2967/ Signed-off-by: Ralf Baechle --- arch/mips/netlogic/common/smp.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) (limited to 'arch/mips/netlogic/common/smp.c') diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c index 3b32c834d14c..c1960439f7e1 100644 --- a/arch/mips/netlogic/common/smp.c +++ b/arch/mips/netlogic/common/smp.c @@ -45,8 +45,15 @@ #include #include +#if defined(CONFIG_CPU_XLP) +#include +#include +#elif defined(CONFIG_CPU_XLR) #include #include +#else +#error "Unknown CPU" +#endif void nlm_send_ipi_single(int logical_cpu, unsigned int action) { @@ -70,15 +77,15 @@ void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) /* IRQ_IPI_SMP_FUNCTION Handler */ void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc) { - smp_call_function_interrupt(); write_c0_eirr(1ull << irq); + smp_call_function_interrupt(); } /* IRQ_IPI_SMP_RESCHEDULE handler */ void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc) { - scheduler_ipi(); write_c0_eirr(1ull << irq); + scheduler_ipi(); } /* @@ -86,9 +93,10 @@ void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc) */ void nlm_early_init_secondary(int cpu) { + change_c0_config(CONF_CM_CMASK, 0x3); write_c0_ebase((uint32_t)nlm_common_ebase); -#ifdef NLM_XLP - if (cpu % 4 == 0) +#ifdef CONFIG_CPU_XLP + if (hard_smp_processor_id() % 4 == 0) xlp_mmu_init(); #endif } -- cgit v1.2.3 From 66d29985fab8207b1b2c03ac34a2c294c5b47a30 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Wed, 16 Nov 2011 00:21:29 +0000 Subject: MIPS: Netlogic: Merge some of XLR/XLP wakup code Create a common NMI and reset handler in smpboot.S and use this for both XLR and XLP. In the earlier code, the woken up CPUs would busy wait until released, switch this to wakeup by NMI. The initial wakeup code or XLR and XLP are differ since they are started from different bootloaders (XLP from u-boot and XLR from netlogic bootloader). But in both platforms the woken up CPUs wait and are released by sending an NMI. Add support for starting XLR and XLP in 1/2/4 threads per core. Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2970/ Signed-off-by: Ralf Baechle --- arch/mips/netlogic/common/smp.c | 75 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 73 insertions(+), 2 deletions(-) (limited to 'arch/mips/netlogic/common/smp.c') diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c index c1960439f7e1..476c93ef3037 100644 --- a/arch/mips/netlogic/common/smp.c +++ b/arch/mips/netlogic/common/smp.c @@ -47,10 +47,12 @@ #if defined(CONFIG_CPU_XLP) #include +#include #include #elif defined(CONFIG_CPU_XLR) #include #include +#include #else #error "Unknown CPU" #endif @@ -125,10 +127,10 @@ void nlm_cpus_done(void) * Boot all other cpus in the system, initialize them, and bring them into * the boot function */ -int nlm_cpu_unblock[NR_CPUS]; int nlm_cpu_ready[NR_CPUS]; unsigned long nlm_next_gp; unsigned long nlm_next_sp; + cpumask_t phys_cpu_present_map; void nlm_boot_secondary(int logical_cpu, struct task_struct *idle) @@ -142,7 +144,7 @@ void nlm_boot_secondary(int logical_cpu, struct task_struct *idle) /* barrier */ __sync(); - nlm_cpu_unblock[cpu] = 1; + nlm_pic_send_ipi(nlm_pic_base, cpu, 1, 1); } void __init nlm_smp_setup(void) @@ -178,12 +180,81 @@ void __init nlm_smp_setup(void) (unsigned long)cpu_possible_map.bits[0]); pr_info("Detected %i Slave CPU(s)\n", num_cpus); + nlm_set_nmi_handler(nlm_boot_secondary_cpus); } void nlm_prepare_cpus(unsigned int max_cpus) { } +static int nlm_parse_cpumask(u32 cpu_mask) +{ + uint32_t core0_thr_mask, core_thr_mask; + int threadmode, i; + + core0_thr_mask = cpu_mask & 0xf; + switch (core0_thr_mask) { + case 1: + nlm_threads_per_core = 1; + threadmode = 0; + break; + case 3: + nlm_threads_per_core = 2; + threadmode = 2; + break; + case 0xf: + nlm_threads_per_core = 4; + threadmode = 3; + break; + default: + goto unsupp; + } + + /* Verify other cores CPU masks */ + nlm_coremask = 1; + nlm_cpumask = core0_thr_mask; + for (i = 1; i < 8; i++) { + core_thr_mask = (cpu_mask >> (i * 4)) & 0xf; + if (core_thr_mask) { + if (core_thr_mask != core0_thr_mask) + goto unsupp; + nlm_coremask |= 1 << i; + nlm_cpumask |= core0_thr_mask << (4 * i); + } + } + return threadmode; + +unsupp: + panic("Unsupported CPU mask %x\n", cpu_mask); + return 0; +} + +int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask) +{ + unsigned long reset_vec; + char *reset_data; + int threadmode; + + /* Update reset entry point with CPU init code */ + reset_vec = CKSEG1ADDR(RESET_VEC_PHYS); + memcpy((void *)reset_vec, (void *)nlm_reset_entry, + (nlm_reset_entry_end - nlm_reset_entry)); + + /* verify the mask and setup core config variables */ + threadmode = nlm_parse_cpumask(wakeup_mask); + + /* Setup CPU init parameters */ + reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS); + *(int *)(reset_data + BOOT_THREAD_MODE) = threadmode; + +#ifdef CONFIG_CPU_XLP + xlp_wakeup_secondary_cpus(); +#else + xlr_wakeup_secondary_cpus(); +#endif + return 0; +} + struct plat_smp_ops nlm_smp_ops = { .send_ipi_single = nlm_send_ipi_single, .send_ipi_mask = nlm_send_ipi_mask, -- cgit v1.2.3 From b3ea581834c1e36cc76589e63dedcd99fd6abf51 Mon Sep 17 00:00:00 2001 From: Hillf Danton Date: Wed, 16 Nov 2011 00:21:29 +0000 Subject: MIPS: Netlogic: Mark Netlogic chips as SMT capable Netlogic XLR chip has multiple cores. Each core includes four integrated hardware threads, and they share L1 data and instruction caches. If the chip is marked to be SMT capable, scheduler then could do more, say, idle load balancing. Changes are now confined only to the code of XLR, and hardware is probed to get core ID for correct setup. [jayachandranc: simplified and adapted for new merged XLR/XLP code] Signed-off-by: Hillf Danton Signed-off-by: Jayachandran C Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2972/ Signed-off-by: Ralf Baechle --- arch/mips/netlogic/common/smp.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'arch/mips/netlogic/common/smp.c') diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c index 476c93ef3037..db17f49886c2 100644 --- a/arch/mips/netlogic/common/smp.c +++ b/arch/mips/netlogic/common/smp.c @@ -108,9 +108,16 @@ void nlm_early_init_secondary(int cpu) */ static void __cpuinit nlm_init_secondary(void) { + current_cpu_data.core = hard_smp_processor_id() / 4; nlm_smp_irq_init(); } +void nlm_prepare_cpus(unsigned int max_cpus) +{ + /* declare we are SMT capable */ + smp_num_siblings = nlm_threads_per_core; +} + void nlm_smp_finish(void) { #ifdef notyet @@ -183,10 +190,6 @@ void __init nlm_smp_setup(void) nlm_set_nmi_handler(nlm_boot_secondary_cpus); } -void nlm_prepare_cpus(unsigned int max_cpus) -{ -} - static int nlm_parse_cpumask(u32 cpu_mask) { uint32_t core0_thr_mask, core_thr_mask; -- cgit v1.2.3