From b5ee9002583fc14e6d45a04c18f208987a8fbced Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Fri, 5 Sep 2008 21:53:30 -0400 Subject: [ARM] remove a common set of __virt_to_bus definitions Let's provide an overridable default instead of having every machine class define __virt_to_bus and __bus_to_virt to the same thing. What most platforms are using is bus_addr == phys_addr so such is the default. One exception is ebsa110 which has no DMA what so ever, so the actual definition is not important except only for proper compilation. Also added a comment about the special footbridge bus translation. Let's also remove comments alluding to set_dma_addr which is not (and should not) be commonly used. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/plat-mxc/include/mach/memory.h | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index d7a8d3ebed57..203688e6164e 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -13,17 +13,4 @@ #include -/* - * Virtual view <-> DMA view memory address translations - * This macro is used to translate the virtual address to an address - * suitable to be passed to set_dma_addr() - */ -#define __virt_to_bus(a) __virt_to_phys(a) - -/* - * Used to convert an address for DMA operations to an address that the - * kernel can use. - */ -#define __bus_to_virt(a) __phys_to_virt(a) - #endif /* __ASM_ARCH_MXC_MEMORY_H__ */ -- cgit v1.2.3 From dcea83adc666061864b82c96e059dffe7268b512 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 29 Nov 2008 11:40:28 +0000 Subject: [ARM] Hide ISA DMA API when ISA_DMA_API is unset When ISA_DMA_API is unset, we're not implementing the ISA DMA API, so there's no point in publishing the prototypes via asm/dma.h, nor including the machine dependent parts of that API. This allows us to remove a lot of mach/dma.h files which don't contain any useful code. Unfortunately though, some platforms put their own private non-ISA definitions into mach/dma.h, so we leave these behind and fix the appropriate #include statments. Signed-off-by: Russell King --- arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h | 2 +- arch/arm/plat-mxc/include/mach/dma.h | 14 -------------- 2 files changed, 1 insertion(+), 15 deletions(-) delete mode 100644 arch/arm/plat-mxc/include/mach/dma.h (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h index e85fd946116c..6cc6f0c8cb25 100644 --- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h +++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h @@ -22,7 +22,7 @@ * MA 02110-1301, USA. */ -#include +#include #ifndef __ASM_ARCH_MXC_DMA_H #define __ASM_ARCH_MXC_DMA_H diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h deleted file mode 100644 index c822d569a05e..000000000000 --- a/arch/arm/plat-mxc/include/mach/dma.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_DMA_H__ -#define __ASM_ARCH_MXC_DMA_H__ - -#endif -- cgit v1.2.3 From 0560cf5aa51216b06874333a2fa26ca034d97bdb Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 30 Nov 2008 11:45:54 +0000 Subject: [ARM] Add a common typesafe __io implementation As Al did for Versatile in 2ad4f86b60b649fd7428265c08d73a3bd360c81b, add a typesafe __io implementation for platforms to use. Convert platforms to use this new simple typesafe implementation. Signed-off-by: Russell King --- arch/arm/plat-mxc/include/mach/io.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h index 5d4cb1196441..c0cb267e7403 100644 --- a/arch/arm/plat-mxc/include/mach/io.h +++ b/arch/arm/plat-mxc/include/mach/io.h @@ -35,8 +35,8 @@ __mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) #endif /* io address mapping macro */ -#define __io(a) ((void __iomem *)(a)) +#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) +#define __mem_pci(a) (a) #endif -- cgit v1.2.3 From 33ebc19d5448aadb2ce4a865d7118f1c2f23fafe Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 16 Dec 2008 12:17:47 +0100 Subject: [ARM] MX2: DMA updates This one updates DMA support on MX2 which got broken in: [ARM] Hide ISA DMA API when ISA_DMA_API is unset Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h index 6cc6f0c8cb25..b3876cc238ca 100644 --- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h +++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h @@ -22,13 +22,15 @@ * MA 02110-1301, USA. */ -#include - #ifndef __ASM_ARCH_MXC_DMA_H #define __ASM_ARCH_MXC_DMA_H #define IMX_DMA_CHANNELS 16 +#define DMA_MODE_READ 0 +#define DMA_MODE_WRITE 1 +#define DMA_MODE_MASK 1 + #define DMA_BASE IO_ADDRESS(DMA_BASE_ADDR) #define IMX_DMA_MEMSIZE_32 (0 << 4) @@ -54,12 +56,12 @@ imx_dma_config_burstlen(int channel, unsigned int burstlen); int imx_dma_setup_single(int channel, dma_addr_t dma_address, unsigned int dma_length, unsigned int dev_addr, - dmamode_t dmamode); + unsigned int dmamode); int imx_dma_setup_sg(int channel, struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, - unsigned int dev_addr, dmamode_t dmamode); + unsigned int dev_addr, unsigned int dmamode); int imx_dma_setup_handlers(int channel, -- cgit v1.2.3 From 619e15508b9926951d239f28ed77420aa9d00a62 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 7 Oct 2008 10:31:07 +0200 Subject: MX27: Fix EMMA Base addresses The EMMA (Enhanced Multimedia Engine) is divided into two parts, the postprocessor and the preprocessor. Fix the base addresses. Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/mx27.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index a86db64744a1..aade46d90e73 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -72,7 +72,8 @@ /* for mx27*/ #define OTG_BASE_ADDR USBOTG_BASE_ADDR #define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000) -#define EMMA_BASE_ADDR (AIPI_BASE_ADDR + 0x26400) +#define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000) +#define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400) #define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000) #define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800) #define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000) -- cgit v1.2.3 From 7cb3f6d268d9a016554435bf93a818cbde342980 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 14 Oct 2008 14:51:25 +0200 Subject: [ARM] MX2: Add IRQ_GPIOE definition The MX2 has 5 gpio ports, IRQ_GPIOE was missing so far. Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h index 3d09bfd6c53d..59233e2d9ca0 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h @@ -392,5 +392,6 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, #define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) #define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) #define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) +#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x) #endif /* _MXC_GPIO_MX1_MX2_H */ -- cgit v1.2.3 From 8c8409539b1c2e0f803893ee9b8128ff855ec19b Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 5 Nov 2008 18:27:14 +0100 Subject: [ARM] MX27ads: remove unused define Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/board-mx27ads.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h index 61e66dac90ef..0c748a8e157b 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h +++ b/arch/arm/plat-mxc/include/mach/board-mx27ads.h @@ -28,11 +28,6 @@ /* * MXC UART EVB board level configurations */ - -#define MXC_LL_EXTUART_PADDR (CS4_BASE_ADDR + 0x20000) -#define MXC_LL_EXTUART_VADDR (CS4_BASE_ADDR_VIRT + 0x20000) -#define MXC_LL_EXTUART_16BIT_BUS - #define MXC_LL_UART_PADDR UART1_BASE_ADDR #define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR) -- cgit v1.2.3 From 1e7f3f48b31c42b4fbb306fd1099f9d23f2407d9 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 29 Sep 2008 15:02:17 +0200 Subject: MX27: Add USB pin function defines Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h index 59233e2d9ca0..f604ec7bf97d 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h @@ -315,6 +315,13 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, #define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 31) #define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_IN | GPIO_PF | 5) #define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_IN | GPIO_PF | 6) +#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7) +#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8) +#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9) +#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10) +#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11) +#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12) +#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13) #define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 16) #define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 17) #define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 18) @@ -365,6 +372,9 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, #define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_IN | GPIO_PF | 30) #define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_OUT | GPIO_PF | 31) #define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) +#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0) +#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1) +#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2) #define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) #define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) #define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) @@ -383,6 +393,8 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, #define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21) #define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22) #define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23) +#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24) +#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25) #endif /* decode irq number to use with IMR(x), ISR(x) and friends */ -- cgit v1.2.3 From d1900d3a18b114eabc15f6369f64439c248d55f3 Mon Sep 17 00:00:00 2001 From: Julien Boibessot Date: Thu, 23 Oct 2008 14:45:10 +0200 Subject: [ARM] MX27: add i.MX27 SDHC1 and SDHC2 GPIO declarations Signed-off-by: Julien Boibessot Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h index f604ec7bf97d..f49d798c5c3c 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h @@ -279,6 +279,12 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, #define PA29_PF_VSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29) #define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30) #define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31) +#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) +#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) +#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) +#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) +#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) +#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) #define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10) #define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10) #define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11) @@ -389,9 +395,15 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, #define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) #define PE16_AF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 16) #define PE16_PF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 16) +#define PE18_PF_SDHC1_D0 (GPIO_PORTE | GPIO_PF | 18) #define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_IN | GPIO_AF | 18) +#define PE19_PF_SDHC1_D1 (GPIO_PORTE | GPIO_PF | 19) +#define PE20_PF_SDHC1_D2 (GPIO_PORTE | GPIO_PF | 20) +#define PE21_PF_SDHC1_D3 (GPIO_PORTE | GPIO_PF | 21) #define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21) +#define PE22_PF_SDHC1_CMD (GPIO_PORTE | GPIO_PF | 22) #define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22) +#define PE22_PF_SDHC1_CLK (GPIO_PORTE | GPIO_PF | 23) #define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23) #define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24) #define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25) -- cgit v1.2.3 From 7bd1822135175354e1662cc890a156f1d89dc211 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 4 Nov 2008 16:48:46 +0100 Subject: [ARM] MX1/MX2: simplify mxc_gpio_setup_multiple_pins mxc_gpio_setup_multiple_pins used to take several ALLOC_MODE flags. Most of them are unused, so simplify the function by removing the flags. Also, instead of using a confusing MXC_GPIO_ALLOC_MODE_RELEASE flag in a function having alloc in its name, add a mxc_gpio_release_multiple_pins function. Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h index f49d798c5c3c..6c331c939c00 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h @@ -21,12 +21,6 @@ #include -#define MXC_GPIO_ALLOC_MODE_NORMAL 0 -#define MXC_GPIO_ALLOC_MODE_NO_ALLOC 1 -#define MXC_GPIO_ALLOC_MODE_TRY_ALLOC 2 -#define MXC_GPIO_ALLOC_MODE_ALLOC_ONLY 4 -#define MXC_GPIO_ALLOC_MODE_RELEASE 8 - /* * GPIO Module and I/O Multiplexer * x = 0..3 for reg_A, reg_B, reg_C, reg_D @@ -103,7 +97,8 @@ extern void mxc_gpio_mode(int gpio_mode); extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, - int alloc_mode, const char *label); + const char *label); +extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); /*-------------------------------------------------------------------------*/ -- cgit v1.2.3 From 1d5aa17be13bafa6b104f4b46c958be3470b28ec Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 13 Nov 2008 13:37:12 +0100 Subject: [ARM] MX3 iomux: add more pin definitions Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx3.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index c9f39c2fb8c6..36acad2eadf3 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -509,6 +509,15 @@ enum iomux_pins { #define MX31_PIN_CSPI3_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI3_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC) +#define MX31_PIN_BATT_LINE__OWIRE IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CS4__CS4 IOMUX_MODE(MX31_PIN_CS4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_DATA3__SD1_DATA3 IOMUX_MODE(MX31_PIN_SD1_DATA3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_DATA2__SD1_DATA2 IOMUX_MODE(MX31_PIN_SD1_DATA2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_DATA1__SD1_DATA1 IOMUX_MODE(MX31_PIN_SD1_DATA1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC) + /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 * cspi1_ss1*/ -- cgit v1.2.3 From 1553a1ec833ddda51d57f66f8e00904b64b954c8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 12 Nov 2008 15:38:39 +0100 Subject: Add basic support for MX31PDK board. Add basic support to the MX31PDK development board, also known as MX31 3DS or MX31 3-stack board (http://www.freescale.com/imx31pdk). Signed-off-by: Fabio Estevam Signed-off-by: sascha Hauer --- arch/arm/plat-mxc/include/mach/board-mx31pdk.h | 19 +++++++++++++++++++ arch/arm/plat-mxc/include/mach/debug-macro.S | 3 +++ 2 files changed, 22 insertions(+) create mode 100644 arch/arm/plat-mxc/include/mach/board-mx31pdk.h (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h new file mode 100644 index 000000000000..2b6b316d0f51 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h @@ -0,0 +1,19 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__ +#define __ASM_ARCH_MXC_BOARD_MX31PDK_H__ + +/* mandatory for CONFIG_LL_DEBUG */ + +#define MXC_LL_UART_PADDR UART1_BASE_ADDR +#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) + +#endif /* __ASM_ARCH_MXC_BOARD_MX31PDK_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index b9907bebba3b..602768b427e2 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -27,6 +27,9 @@ #endif #ifdef CONFIG_MACH_PCM038 #include +#endif +#ifdef CONFIG_MACH_MX31_3DS +#include #endif .macro addruart,rx mrc p15, 0, \rx, c1, c0 -- cgit v1.2.3 From d1b3cc6de8a145beabe62bde7999c61f63864eeb Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 24 Oct 2008 15:09:06 +0200 Subject: MX31: definitions for UART2 pins UART2 pins when used in functionnal mode Signed-off-by: Valentin Longchamp Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx3.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index 36acad2eadf3..f36305a661f4 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -491,6 +491,10 @@ enum iomux_pins { #define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) #define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) #define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI1_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI1_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI1_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC) -- cgit v1.2.3 From a3cce2a8e2e7b09911ea97dbdd5236c60f202a16 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 24 Oct 2008 15:10:32 +0200 Subject: MX31: UART5 pins definition pins definition for UART5 when used in alternate mode 2 Signed-off-by: Valentin Longchamp Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx3.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index f36305a661f4..20e5c4c63314 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -495,6 +495,10 @@ enum iomux_pins { #define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) #define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) #define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2) +#define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2) +#define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2) +#define MX31_PIN_PC_BVD1__RXD5 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT2) #define MX31_PIN_CSPI1_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI1_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI1_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC) -- cgit v1.2.3 From d133d6a89340b7438038ed0407221c5277cb8a0e Mon Sep 17 00:00:00 2001 From: Darius Augulis Date: Fri, 14 Nov 2008 11:01:38 +0100 Subject: patch-iomux-mx1-mx2-cleanup Fix GIUS register setup in the mxc_gpio_mode(). Signed-off-by: Darius Augulis Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h | 34 +++++++++++++------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h index 6c331c939c00..60b3c9b6ef7d 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h @@ -108,9 +108,9 @@ extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); * missing on some (many) pins */ #ifdef CONFIG_ARCH_MX1 -#define PA0_AIN_SPI2_CLK (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0) +#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_OUT | 0) #define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0) -#define PA1_AOUT_SPI2_RXD (GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1) +#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_IN | 1) #define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1) #define PA2_PF_PWM0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2) #define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3) @@ -128,7 +128,7 @@ extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); #define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15) #define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16) #define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17) -#define PA17_AIN_SPI2_SS (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17) +#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_OUT | 17) #define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18) #define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19) #define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20) @@ -196,27 +196,27 @@ extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); #define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15) #define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16) #define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17) -#define PC24_BIN_UART3_RI (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24) -#define PC25_BIN_UART3_DSR (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25) -#define PC26_AOUT_UART3_DTR (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26) -#define PC27_BIN_UART3_DCD (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27) -#define PC28_BIN_UART3_CTS (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28) -#define PC29_AOUT_UART3_RTS (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29) -#define PC30_BIN_UART3_TX (GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30) -#define PC31_AOUT_UART3_RX (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31) +#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24) +#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25) +#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_IN | 26) +#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27) +#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28) +#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_IN | 29) +#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30) +#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_IN | 31) #define PD6_PF_LSCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6) #define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7) -#define PD7_AF_UART2_DTR (GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7) -#define PD7_AIN_SPI2_SCLK (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7) +#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_IN | GPIO_AF | 7) +#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7) #define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8) #define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8) -#define PD8_AIN_SPI2_SS (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8) +#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8) #define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9) #define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9) -#define PD9_AOUT_SPI2_RXD (GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9) +#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_IN | 9) #define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10) #define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10) -#define PD10_AIN_SPI2_TXD (GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10) +#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_OUT | 10) #define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11) #define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12) #define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13) @@ -238,7 +238,7 @@ extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); #define PD29_PF_LD14 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29) #define PD30_PF_LD15 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30) #define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31) -#define PD31_BIN_SPI2_TXD (GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31) +#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31) #endif #ifdef CONFIG_ARCH_MX2 -- cgit v1.2.3 From cfca8b539f53114fb6a6de091987a984c8013d96 Mon Sep 17 00:00:00 2001 From: Paulius Zaleckas Date: Fri, 14 Nov 2008 11:01:38 +0100 Subject: patch-mxc-add-ARCH_MX1 Adds MX1 architecture to platform MXC. It will supersede mach-imx and let it die. Signed-off-by: Paulius Zaleckas Signed-off-by: Darius Augulis Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/hardware.h | 4 + arch/arm/plat-mxc/include/mach/mx1.h | 197 +++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/mxc_timer.h | 4 +- 3 files changed, 203 insertions(+), 2 deletions(-) create mode 100644 arch/arm/plat-mxc/include/mach/mx1.h (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index 3caadeeda701..a612d8bb73c8 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -32,6 +32,10 @@ # endif #endif +#ifdef CONFIG_ARCH_MX1 +# include +#endif + #include #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h new file mode 100644 index 000000000000..e7f6d00009a7 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -0,0 +1,197 @@ +/* + * Copyright (C) 1997,1998 Russell King + * Copyright (C) 1999 ARM Limited + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (c) 2008 Paulius Zaleckas + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_MX1_H__ +#define __ASM_ARCH_MXC_MX1_H__ + +#ifndef __ASM_ARCH_MXC_HARDWARE_H__ +#error "Do not include directly." +#endif + +#include + +/* + * defines the hardware clock tick rate + */ +#define CLOCK_TICK_RATE 16000000 + +#define PHYS_OFFSET UL(0x08000000) + +/* + * Memory map + */ +#define IMX_IO_PHYS 0x00200000 +#define IMX_IO_SIZE 0x00100000 +#define IMX_IO_BASE VMALLOC_END + +#define IMX_CS0_PHYS 0x10000000 +#define IMX_CS0_SIZE 0x02000000 + +#define IMX_CS1_PHYS 0x12000000 +#define IMX_CS1_SIZE 0x01000000 + +#define IMX_CS2_PHYS 0x13000000 +#define IMX_CS2_SIZE 0x01000000 + +#define IMX_CS3_PHYS 0x14000000 +#define IMX_CS3_SIZE 0x01000000 + +#define IMX_CS4_PHYS 0x15000000 +#define IMX_CS4_SIZE 0x01000000 + +#define IMX_CS5_PHYS 0x16000000 +#define IMX_CS5_SIZE 0x01000000 + +/* + * Register BASEs, based on OFFSETs + */ +#define AIPI1_BASE_ADDR (0x00000 + IMX_IO_PHYS) +#define WDT_BASE_ADDR (0x01000 + IMX_IO_PHYS) +#define TIM1_BASE_ADDR (0x02000 + IMX_IO_PHYS) +#define TIM2_BASE_ADDR (0x03000 + IMX_IO_PHYS) +#define RTC_BASE_ADDR (0x04000 + IMX_IO_PHYS) +#define LCDC_BASE_ADDR (0x05000 + IMX_IO_PHYS) +#define UART1_BASE_ADDR (0x06000 + IMX_IO_PHYS) +#define UART2_BASE_ADDR (0x07000 + IMX_IO_PHYS) +#define PWM_BASE_ADDR (0x08000 + IMX_IO_PHYS) +#define DMA_BASE_ADDR (0x09000 + IMX_IO_PHYS) +#define AIPI2_BASE_ADDR (0x10000 + IMX_IO_PHYS) +#define SIM_BASE_ADDR (0x11000 + IMX_IO_PHYS) +#define USBD_BASE_ADDR (0x12000 + IMX_IO_PHYS) +#define SPI1_BASE_ADDR (0x13000 + IMX_IO_PHYS) +#define MMC_BASE_ADDR (0x14000 + IMX_IO_PHYS) +#define ASP_BASE_ADDR (0x15000 + IMX_IO_PHYS) +#define BTA_BASE_ADDR (0x16000 + IMX_IO_PHYS) +#define I2C_BASE_ADDR (0x17000 + IMX_IO_PHYS) +#define SSI_BASE_ADDR (0x18000 + IMX_IO_PHYS) +#define SPI2_BASE_ADDR (0x19000 + IMX_IO_PHYS) +#define MSHC_BASE_ADDR (0x1A000 + IMX_IO_PHYS) +#define CCM_BASE_ADDR (0x1B000 + IMX_IO_PHYS) +#define SCM_BASE_ADDR (0x1B804 + IMX_IO_PHYS) +#define GPIO_BASE_ADDR (0x1C000 + IMX_IO_PHYS) +#define EIM_BASE_ADDR (0x20000 + IMX_IO_PHYS) +#define SDRAMC_BASE_ADDR (0x21000 + IMX_IO_PHYS) +#define MMA_BASE_ADDR (0x22000 + IMX_IO_PHYS) +#define AVIC_BASE_ADDR (0x23000 + IMX_IO_PHYS) +#define CSI_BASE_ADDR (0x24000 + IMX_IO_PHYS) + +/* macro to get at IO space when running virtually */ +#define IO_ADDRESS(x) ((x) - IMX_IO_PHYS + IMX_IO_BASE) + +/* define macros needed for entry-macro.S */ +#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x) + +/* fixed interrput numbers */ +#define INT_SOFTINT 0 +#define CSI_INT 6 +#define DSPA_MAC_INT 7 +#define DSPA_INT 8 +#define COMP_INT 9 +#define MSHC_XINT 10 +#define GPIO_INT_PORTA 11 +#define GPIO_INT_PORTB 12 +#define GPIO_INT_PORTC 13 +#define LCDC_INT 14 +#define SIM_INT 15 +#define SIM_DATA_INT 16 +#define RTC_INT 17 +#define RTC_SAMINT 18 +#define UART2_MINT_PFERR 19 +#define UART2_MINT_RTS 20 +#define UART2_MINT_DTR 21 +#define UART2_MINT_UARTC 22 +#define UART2_MINT_TX 23 +#define UART2_MINT_RX 24 +#define UART1_MINT_PFERR 25 +#define UART1_MINT_RTS 26 +#define UART1_MINT_DTR 27 +#define UART1_MINT_UARTC 28 +#define UART1_MINT_TX 29 +#define UART1_MINT_RX 30 +#define VOICE_DAC_INT 31 +#define VOICE_ADC_INT 32 +#define PEN_DATA_INT 33 +#define PWM_INT 34 +#define SDHC_INT 35 +#define I2C_INT 39 +#define CSPI_INT 41 +#define SSI_TX_INT 42 +#define SSI_TX_ERR_INT 43 +#define SSI_RX_INT 44 +#define SSI_RX_ERR_INT 45 +#define TOUCH_INT 46 +#define USBD_INT0 47 +#define USBD_INT1 48 +#define USBD_INT2 49 +#define USBD_INT3 50 +#define USBD_INT4 51 +#define USBD_INT5 52 +#define USBD_INT6 53 +#define BTSYS_INT 55 +#define BTTIM_INT 56 +#define BTWUI_INT 57 +#define TIM2_INT 58 +#define TIM1_INT 59 +#define DMA_ERR 60 +#define DMA_INT 61 +#define GPIO_INT_PORTD 62 +#define WDT_INT 63 + +#define MXC_MAX_INT_LINES 64 + +#define NR_IRQS 256 + +/* gpio and gpio based interrupt handling */ +#define GPIO_DR 0x1C +#define GPIO_GDIR 0x00 +#define GPIO_PSR 0x24 +#define GPIO_ICR1 0x28 +#define GPIO_ICR2 0x2C +#define GPIO_IMR 0x30 +#define GPIO_ISR 0x34 +#define GPIO_INT_LOW_LEV 0x3 +#define GPIO_INT_HIGH_LEV 0x2 +#define GPIO_INT_RISE_EDGE 0x0 +#define GPIO_INT_FALL_EDGE 0x1 +#define GPIO_INT_NONE 0x4 + +/* DMA */ +#define DMA_REQ_UART3_T 2 +#define DMA_REQ_UART3_R 3 +#define DMA_REQ_SSI2_T 4 +#define DMA_REQ_SSI2_R 5 +#define DMA_REQ_CSI_STAT 6 +#define DMA_REQ_CSI_R 7 +#define DMA_REQ_MSHC 8 +#define DMA_REQ_DSPA_DCT_DOUT 9 +#define DMA_REQ_DSPA_DCT_DIN 10 +#define DMA_REQ_DSPA_MAC 11 +#define DMA_REQ_EXT 12 +#define DMA_REQ_SDHC 13 +#define DMA_REQ_SPI1_R 14 +#define DMA_REQ_SPI1_T 15 +#define DMA_REQ_SSI_T 16 +#define DMA_REQ_SSI_R 17 +#define DMA_REQ_ASP_DAC 18 +#define DMA_REQ_ASP_ADC 19 +#define DMA_REQ_USP_EP(x) (20 + (x)) +#define DMA_REQ_SPI2_R 26 +#define DMA_REQ_SPI2_T 27 +#define DMA_REQ_UART2_T 28 +#define DMA_REQ_UART2_R 29 +#define DMA_REQ_UART1_T 30 +#define DMA_REQ_UART1_R 31 + +/* mandatory for CONFIG_LL_DEBUG */ +#define MXC_LL_UART_PADDR UART1_BASE_ADDR +#define MXC_LL_UART_VADDR IO_ADDRESS(UART1_BASE_ADDR) + +#endif /* __ASM_ARCH_MXC_MX1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc_timer.h b/arch/arm/plat-mxc/include/mach/mxc_timer.h index 130aebfbe168..6c19a134744b 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_timer.h +++ b/arch/arm/plat-mxc/include/mach/mxc_timer.h @@ -26,7 +26,7 @@ #include #include -#ifdef CONFIG_ARCH_IMX +#ifdef CONFIG_ARCH_MX1 #define TIMER_BASE IO_ADDRESS(TIM1_BASE_ADDR) #define TIMER_INTERRUPT TIM1_INT @@ -65,7 +65,7 @@ static void gpt_irq_acknowledge(void) { __raw_writel(0, TIMER_BASE + MXC_TSTAT); } -#endif /* CONFIG_ARCH_IMX */ +#endif /* CONFIG_ARCH_MX1 */ #ifdef CONFIG_ARCH_MX2 #define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR) -- cgit v1.2.3 From 5032630f398a4e30371dd39fce28778eedcbb5b5 Mon Sep 17 00:00:00 2001 From: Darius Augulis Date: Fri, 14 Nov 2008 11:01:39 +0100 Subject: patch-mx1-mtd-xip Adds MTD XIP support for ARCH_MX1. Signed-off-by: Darius Augulis Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/mtd-xip.h | 34 ++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 arch/arm/plat-mxc/include/mach/mtd-xip.h (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/mtd-xip.h b/arch/arm/plat-mxc/include/mach/mtd-xip.h new file mode 100644 index 000000000000..1ab1bba5688d --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mtd-xip.h @@ -0,0 +1,34 @@ +/* + * MTD primitives for XIP support. Architecture specific functions + * + * Do not include this file directly. It's included from linux/mtd/xip.h + * + * Copyright (C) 2008 Darius Augulis , Teltonika, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include + +#ifndef __ARCH_IMX_MTD_XIP_H__ +#define __ARCH_IMX_MTD_XIP_H__ + +#ifdef CONFIG_ARCH_MX1 +/* AITC registers */ +#define AITC_BASE IO_ADDRESS(AVIC_BASE_ADDR) +#define NIPNDH (AITC_BASE + 0x58) +#define NIPNDL (AITC_BASE + 0x5C) +#define INTENABLEH (AITC_BASE + 0x10) +#define INTENABLEL (AITC_BASE + 0x14) +/* MTD macros */ +#define xip_irqpending() ((__raw_readl(INTENABLEH) & __raw_readl(NIPNDH)) \ + || (__raw_readl(INTENABLEL) & __raw_readl(NIPNDL))) +#define xip_currtime() (__raw_readl(TIMER_BASE + MXC_TCN)) +#define xip_elapsed_since(x) (signed)((__raw_readl(TIMER_BASE + MXC_TCN) - (x)) / 96) +#define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (0)) +#endif /* CONFIG_ARCH_MX1 */ + +#endif /* __ARCH_IMX_MTD_XIP_H__ */ -- cgit v1.2.3 From d7927e19167680053f282fb4007e81c244ebf465 Mon Sep 17 00:00:00 2001 From: Paulius Zaleckas Date: Fri, 14 Nov 2008 11:01:39 +0100 Subject: patch-mxc-fiq Drivers which are going to use it will have to select it and use mxc_set_irq_fiq() to set FIQ mode for this interrupt. Signed-off-by: Paulius Zaleckas Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/irqs.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index b55bba35e18a..b8ac91608a4f 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -14,4 +14,9 @@ #include extern void imx_irq_set_priority(unsigned char irq, unsigned char prio); +/* all normal IRQs can be FIQs */ +#define FIQ_START 0 +/* switch betwean IRQ and FIQ */ +extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type); + #endif /* __ASM_ARCH_MXC_IRQS_H__ */ -- cgit v1.2.3 From 9d631b835f518848b7f3ce803bfd00dc1bb8a5b1 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 18 Dec 2008 11:08:55 +0100 Subject: [ARM] MXC: remove dependency to other include files from irqs.h This patch removes the inclusion of mach/hardware.h from mach/irqs.h and switches to more meaningful names for the irq related macros. Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/board-mx27ads.h | 2 +- arch/arm/plat-mxc/include/mach/board-mx31ads.h | 2 +- arch/arm/plat-mxc/include/mach/gpio.h | 4 ++-- arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h | 4 ++-- arch/arm/plat-mxc/include/mach/iomux-mx3.h | 2 +- arch/arm/plat-mxc/include/mach/irqs.h | 27 +++++++++++++++++++++++++- arch/arm/plat-mxc/include/mach/mx1.h | 4 ---- arch/arm/plat-mxc/include/mach/mx27.h | 6 ------ arch/arm/plat-mxc/include/mach/mx31.h | 17 ---------------- 9 files changed, 33 insertions(+), 35 deletions(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h index 0c748a8e157b..8f34a05afc87 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h +++ b/arch/arm/plat-mxc/include/mach/board-mx27ads.h @@ -15,7 +15,7 @@ #define __ASM_ARCH_MXC_BOARD_MX27ADS_H__ /* external interrupt multiplexer */ -#define MXC_EXP_IO_BASE (MXC_GPIO_BASE + MXC_MAX_GPIO_LINES) +#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) #define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES) #define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h index 745b48864f93..451d510d08c3 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h @@ -90,7 +90,7 @@ #define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) -#define MXC_EXP_IO_BASE (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES) +#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) #define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) #define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0) diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index 65eedc0d196f..ea509f1090fb 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -27,8 +27,8 @@ #define gpio_set_value __gpio_set_value #define gpio_cansleep __gpio_cansleep -#define gpio_to_irq(gpio) (MXC_MAX_INT_LINES + (gpio)) -#define irq_to_gpio(irq) ((irq) - MXC_MAX_INT_LINES) +#define gpio_to_irq(gpio) (MXC_GPIO_IRQ_START + (gpio)) +#define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START) struct mxc_gpio_port { void __iomem *base; diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h index 60b3c9b6ef7d..95a383be628e 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h @@ -405,9 +405,9 @@ extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); #endif /* decode irq number to use with IMR(x), ISR(x) and friends */ -#define IRQ_TO_REG(irq) ((irq - MXC_MAX_INT_LINES) >> 5) +#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5) -#define IRQ_GPIOA(x) (MXC_MAX_INT_LINES + x) +#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x) #define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) #define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) #define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index 20e5c4c63314..c9198c0aea18 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -141,7 +141,7 @@ void mxc_iomux_set_gpr(enum iomux_gp_func, bool); ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) #define IOMUX_TO_IRQ(iomux_pin) \ (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \ - MXC_GPIO_INT_BASE) + MXC_GPIO_IRQ_START) /* * This enumeration is constructed based on the Section diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index b8ac91608a4f..e06d3cb0ee11 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -11,7 +11,32 @@ #ifndef __ASM_ARCH_MXC_IRQS_H__ #define __ASM_ARCH_MXC_IRQS_H__ -#include +/* + * So far all i.MX SoCs have 64 internal interrupts + */ +#define MXC_INTERNAL_IRQS 64 + +#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS + +#if defined CONFIG_ARCH_MX1 +#define MXC_GPIO_IRQS (32 * 4) +#elif defined CONFIG_ARCH_MX2 +#define MXC_GPIO_IRQS (32 * 6) +#elif defined CONFIG_ARCH_MX3 +#define MXC_GPIO_IRQS (32 * 3) +#endif + +/* + * The next 16 interrupts are for board specific purposes. Since + * the kernel can only run on one machine at a time, we can re-use + * these. If you need more, increase MXC_BOARD_IRQS, but keep it + * within sensible limits. + */ +#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS) +#define MXC_BOARD_IRQS 16 + +#define NR_IRQS (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS) + extern void imx_irq_set_priority(unsigned char irq, unsigned char prio); /* all normal IRQs can be FIQs */ diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index e7f6d00009a7..c45bf5f5b90c 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -145,10 +145,6 @@ #define GPIO_INT_PORTD 62 #define WDT_INT 63 -#define MXC_MAX_INT_LINES 64 - -#define NR_IRQS 256 - /* gpio and gpio based interrupt handling */ #define GPIO_DR 0x1C #define GPIO_GDIR 0x00 diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index aade46d90e73..55bcbd5e073a 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -295,10 +295,4 @@ extern int mx27_revision(void); /* Start of RAM */ #define PHYS_OFFSET SDRAM_BASE_ADDR -/* max interrupt lines count */ -#define NR_IRQS 256 - -/* count of internal interrupt sources */ -#define MXC_MAX_INT_LINES 64 - #endif /* __ASM_ARCH_MXC_MX27_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 0536f8917bc0..65c3109b5192 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -315,23 +315,6 @@ #define MXC_INT_EXT_WDOG 62 #define MXC_INT_EXT_TV 63 -#define MXC_MAX_INT_LINES 64 - -#define MXC_GPIO_INT_BASE MXC_MAX_INT_LINES -#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM) -#define MXC_MAX_VIRTUAL_INTS 16 - -#define NR_IRQS (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES + MXC_MAX_VIRTUAL_INTS) - -/*! - * Number of GPIO port as defined in the IC Spec - */ -#define GPIO_PORT_NUM 3 -/*! - * Number of GPIO pins per port - */ -#define GPIO_NUM_PIN 32 - #define PROD_SIGNATURE 0x1 /* For MX31 */ /* silicon revisions specific to i.MX31 */ -- cgit v1.2.3 From 44421e42587125acf70771436bcd6af06e1261a3 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 18 Dec 2008 11:24:03 +0100 Subject: [ARM] MXC: do not include mach/hardware.h from mach/timex.h Instead of including other header files, define CLOCK_TICK_RATE directly Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/mx1.h | 5 ----- arch/arm/plat-mxc/include/mach/mx27.h | 3 --- arch/arm/plat-mxc/include/mach/mx31.h | 5 ----- arch/arm/plat-mxc/include/mach/timex.h | 8 +++++++- 4 files changed, 7 insertions(+), 14 deletions(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index c45bf5f5b90c..8476a15dbfc0 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -18,11 +18,6 @@ #include -/* - * defines the hardware clock tick rate - */ -#define CLOCK_TICK_RATE 16000000 - #define PHYS_OFFSET UL(0x08000000) /* diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 55bcbd5e073a..ae8637471ae8 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -289,9 +289,6 @@ extern int mx27_revision(void); /* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */ #define ARCH_NR_GPIOS (192 + 16) -/* OS clock tick rate */ -#define CLOCK_TICK_RATE 13300000 - /* Start of RAM */ #define PHYS_OFFSET SDRAM_BASE_ADDR diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 65c3109b5192..2f6d9fc0ab23 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -15,11 +15,6 @@ #error "Do not include directly." #endif -/*! - * defines the hardware clock tick rate - */ -#define CLOCK_TICK_RATE 16625000 - /* * MX31 memory map: * diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h index 0b0af0253e91..07b4a73c9d2f 100644 --- a/arch/arm/plat-mxc/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -20,6 +20,12 @@ #ifndef __ASM_ARCH_MXC_TIMEX_H__ #define __ASM_ARCH_MXC_TIMEX_H__ -#include /* for CLOCK_TICK_RATE */ +#if defined CONFIG_ARCH_MX1 +#define CLOCK_TICK_RATE 16000000 +#elif defined CONFIG_ARCH_MX2 +#define CLOCK_TICK_RATE 13300000 +#elif defined CONFIG_ARCH_MX3 +#define CLOCK_TICK_RATE 16625000 +#endif #endif /* __ASM_ARCH_MXC_TIMEX_H__ */ -- cgit v1.2.3 From a2449091522990e9746a3f1420b9041d9669590c Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 18 Dec 2008 11:51:57 +0100 Subject: [ARM] MXC: do not include mach/hardware.h from mach/memory.h Instead of including other header files, define PHYS_OFFSET directly Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/entry-macro.S | 2 ++ arch/arm/plat-mxc/include/mach/io.h | 4 ++-- arch/arm/plat-mxc/include/mach/memory.h | 8 +++++++- arch/arm/plat-mxc/include/mach/mx1.h | 2 -- arch/arm/plat-mxc/include/mach/mx27.h | 3 --- arch/arm/plat-mxc/include/mach/mx31.h | 3 --- 6 files changed, 11 insertions(+), 11 deletions(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S index 11632028f7d1..5f01d60da845 100644 --- a/arch/arm/plat-mxc/include/mach/entry-macro.S +++ b/arch/arm/plat-mxc/include/mach/entry-macro.S @@ -9,6 +9,8 @@ * published by the Free Software Foundation. */ +#include + #define AVIC_NIMASK 0x04 @ this macro disables fast irq (not implemented) diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h index c0cb267e7403..b4f2de769466 100644 --- a/arch/arm/plat-mxc/include/mach/io.h +++ b/arch/arm/plat-mxc/include/mach/io.h @@ -25,8 +25,8 @@ __mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) /* Access all peripherals below 0x80000000 as nonshared device * but leave l2cc alone. */ - if ((phys_addr < 0x80000000) && ((phys_addr < L2CC_BASE_ADDR) || - (phys_addr >= L2CC_BASE_ADDR + L2CC_SIZE))) + if ((phys_addr < 0x80000000) && ((phys_addr < 0x30000000) || + (phys_addr >= 0x30000000 + SZ_1M))) mtype = MT_DEVICE_NONSHARED; } diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 203688e6164e..0b808399097f 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -11,6 +11,12 @@ #ifndef __ASM_ARCH_MXC_MEMORY_H__ #define __ASM_ARCH_MXC_MEMORY_H__ -#include +#if defined CONFIG_ARCH_MX1 +#define PHYS_OFFSET UL(0x08000000) +#elif defined CONFIG_ARCH_MX2 +#define PHYS_OFFSET UL(0xA0000000) +#elif defined CONFIG_ARCH_MX3 +#define PHYS_OFFSET UL(0x80000000) +#endif #endif /* __ASM_ARCH_MXC_MEMORY_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 8476a15dbfc0..b92e02324d8e 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -18,8 +18,6 @@ #include -#define PHYS_OFFSET UL(0x08000000) - /* * Memory map */ diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index ae8637471ae8..0313be720552 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -289,7 +289,4 @@ extern int mx27_revision(void); /* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */ #define ARCH_NR_GPIOS (192 + 16) -/* Start of RAM */ -#define PHYS_OFFSET SDRAM_BASE_ADDR - #endif /* __ASM_ARCH_MXC_MX27_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 2f6d9fc0ab23..de026654b00e 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -239,9 +239,6 @@ #define PCMCIA_IO_ADDRESS(x) \ (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) -/* Start of physical RAM - On many MX31 platforms, this is the first SDRAM bank (CSD0) */ -#define PHYS_OFFSET CSD0_BASE_ADDR - /* * Interrupt numbers */ -- cgit v1.2.3