From a003708ad4ee9384226251431c7953a24079ff80 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Thu, 3 Dec 2009 22:36:41 +0200 Subject: mxc: TrustZone interrupt controller (TZIC) for Freescale i.MX5 family Freescale i.MX51 processor uses a new interrupt controller. Add driver for TrustZone Interrupt Controller Signed-off-by: Amit Kucheria --- arch/arm/plat-mxc/include/mach/irqs.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-mxc/include/mach/irqs.h') diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 0cb347645db4..38f150162e45 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -12,9 +12,13 @@ #define __ASM_ARCH_MXC_IRQS_H__ /* - * So far all i.MX SoCs have 64 internal interrupts + * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64 */ +#ifdef CONFIG_MXC_TZIC +#define MXC_INTERNAL_IRQS 128 +#else #define MXC_INTERNAL_IRQS 64 +#endif #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS -- cgit v1.2.3 From 438caa3f6c91ba21c539a8547c4075b619dc6500 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Thu, 4 Feb 2010 12:09:40 -0800 Subject: mxc: changes to common plat-mxc code to add support for i.MX5 Prepare for i.MX5 SoC code by adding the relevant macros to common plat-mxc code. Signed-off-by: Amit Kucheria --- arch/arm/plat-mxc/include/mach/irqs.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/plat-mxc/include/mach/irqs.h') diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 38f150162e45..a3ad643de5a1 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -30,6 +30,8 @@ #define MXC_GPIO_IRQS (32 * 3) #elif defined CONFIG_ARCH_MX25 #define MXC_GPIO_IRQS (32 * 4) +#elif defined CONFIG_ARCH_MX5 +#define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MXC91231 #define MXC_GPIO_IRQS (32 * 4) #endif @@ -55,6 +57,7 @@ #else #define MX3_IPU_IRQS 0 #endif +/* REVISIT: Add IPU irqs on IMX51 */ #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) -- cgit v1.2.3 From abf61632884ae6bfd1e7b967d5254fa7b5191e7b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 17 Feb 2010 21:08:00 +0100 Subject: arm/imx/irq: order definitions of MXC_GPIO_IRQS numerically MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is important for kernels supporting more than one SoC. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/irqs.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'arch/arm/plat-mxc/include/mach/irqs.h') diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 0cb347645db4..7ebdd7191495 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -18,16 +18,17 @@ #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS -#if defined CONFIG_ARCH_MX1 -#define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_ARCH_MX2 +/* these are ordered by size to support multi-SoC kernels */ +#if defined CONFIG_ARCH_MX2 #define MXC_GPIO_IRQS (32 * 6) -#elif defined CONFIG_ARCH_MX3 -#define MXC_GPIO_IRQS (32 * 3) +#elif defined CONFIG_ARCH_MX1 +#define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MX25 #define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MXC91231 #define MXC_GPIO_IRQS (32 * 4) +#elif defined CONFIG_ARCH_MX3 +#define MXC_GPIO_IRQS (32 * 3) #endif /* -- cgit v1.2.3