From ff6fd1478c531a40279cf013227279f31ff90b41 Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Mon, 21 Mar 2016 11:01:45 -0500 Subject: ARM: socfpga: Enable Arria10 L2 cache ECC on startup Enable ECC for Arria10 L2 cache on machine startup. The ECC has to be enabled before data is stored in memory otherwise the ECC will fail on reads. Use DT_MACHINE to select Arria10 L2 cache function. Signed-off-by: Thor Thayer Acked-by: Dinh Nguyen Cc: devicetree@vger.kernel.org Cc: dinguyen@opensource.altera.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux@arm.linux.org.uk Cc: linux-edac Link: http://lkml.kernel.org/r/1458576106-24505-9-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov --- arch/arm/mach-socfpga/socfpga.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-socfpga/socfpga.c') diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 7e0aad2ec3d1..e9b5b603df4b 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -66,6 +66,14 @@ static void __init socfpga_init_irq(void) socfpga_init_ocram_ecc(); } +static void __init socfpga_arria10_init_irq(void) +{ + irqchip_init(); + socfpga_sysmgr_init(); + if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C)) + socfpga_init_arria10_l2_ecc(); +} + static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd) { u32 temp; @@ -113,7 +121,7 @@ static const char *altera_a10_dt_match[] = { DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10") .l2c_aux_val = 0, .l2c_aux_mask = ~0, - .init_irq = socfpga_init_irq, + .init_irq = socfpga_arria10_init_irq, .restart = socfpga_arria10_restart, .dt_compat = altera_a10_dt_match, MACHINE_END -- cgit v1.2.3 From c5fb04cc96c1812eb09a3b0f3672f4a00d76730c Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Mon, 11 Apr 2016 12:01:34 -0500 Subject: ARM: socfpga: Initialize Arria10 OCRAM ECC on startup Initialize ECC for Arria10 On-Chip RAM on machine startup. The OCRAM memory must be initialized before data is stored in memory otherwise the ECC will fail on reads. The previous check-in 2364d423a7b3 ("ARM: socfpga: Enable Arria10 OCRAM ECC on startup") added the OCRAM enable and initialization code but was not called on startup. Signed-off-by: Thor Thayer Acked-by: Dinh Nguyen Cc: Russell King Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac Link: http://lkml.kernel.org/r/1460394094-23326-1-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov --- arch/arm/mach-socfpga/socfpga.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-socfpga/socfpga.c') diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index e9b5b603df4b..dde14f7bf2c3 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -72,6 +72,8 @@ static void __init socfpga_arria10_init_irq(void) socfpga_sysmgr_init(); if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C)) socfpga_init_arria10_l2_ecc(); + if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM)) + socfpga_init_arria10_ocram_ecc(); } static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd) -- cgit v1.2.3