From d08cce6a1d6952a7774e4b61066d469c16d47a11 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Mon, 29 Oct 2012 20:55:46 -0600 Subject: ARM: OMAP2/3: PRM: add SoC reset functions (using the CORE DPLL method) Add SoC reset functions into the PRM code. These functions are based on code from mach-omap2/prcm.c. They reset the SoC using the CORE DPLL reset method (as opposed to one of the other two or three chip reset methods). Adding them here will facilitate their removal from arch/arm/mach-omap2/prcm.c. (prcm.c is deprecated.) Signed-off-by: Paul Walmsley Tested-by: Vaibhav Hiremath --- arch/arm/mach-omap2/prm3xxx.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/mach-omap2/prm3xxx.c') diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c index 1fea656b2ca8..5435673ac9ce 100644 --- a/arch/arm/mach-omap2/prm3xxx.c +++ b/arch/arm/mach-omap2/prm3xxx.c @@ -122,6 +122,21 @@ u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset); } +/** + * omap3xxx_prm_dpll3_reset - use DPLL3 reset to reboot the OMAP SoC + * + * Set the DPLL3 reset bit, which should reboot the SoC. This is the + * recommended way to restart the SoC, considering Errata i520. No + * return value. + */ +void omap3xxx_prm_dpll3_reset(void) +{ + omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, OMAP3430_GR_MOD, + OMAP2_RM_RSTCTRL); + /* OCP barrier */ + omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP2_RM_RSTCTRL); +} + /** * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events * @events: ptr to a u32, preallocated by caller -- cgit v1.2.3