From dea0853cd59f41ebdfede390db71ae745a2767af Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Thu, 27 Mar 2014 19:51:15 +0800 Subject: ENGR00305648-5 ARM: imx6sx: set Audio clocks to 24.576MHz This patch sets a default clock 24.576MHz for ESAI clock and swtich the source of external AUDIO clock from pll4 to pll3 since 24.0Mhz would be more likely recommanded than 24.576MHz to WM8962 audio codec. Acked-by: Wang Shengjiu Signed-off-by: Nicolin Chen --- arch/arm/mach-imx/clk-imx6sx.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index c4b333bdef8d..1b44eec131db 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c @@ -471,10 +471,14 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000); /* Audio clocks */ - clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); - clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 24000000); + clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000); + + clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]); clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000); + clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); + clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000); + /* default parent of can_sel clock is invalid, manually set it here */ clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]); -- cgit v1.2.3