| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-08-29 | ARM: uniphier: remove SoC-specific SMP code | Masahiro Yamada | |
| The UniPhier architecture (32bit) switched over to PSCI. Remove the SoC-specific SMP operations. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> | |||
| 2015-10-27 | ARM: uniphier: add outer cache support | Masahiro Yamada | |
| This commit adds support for UniPhier outer cache controller. All the UniPhier SoCs are equipped with the L2 cache, while the L3 cache is currently only integrated on PH1-Pro5 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net> | |||
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index : linux-toradex.git | |
| Linux kernel for Apalis, Colibri and Verdin modules | Toradex |
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