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2011-11-30ARM: tegra: power: Add TWD context save/restoreScott Williams
Change-Id: I629f77041ce444dfff32b563795573174afea3a1 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R7a21e91127b44461d219a8bfd388f99ba7a72b53
2011-11-30ARM: tegra3: power: Add LP2 power mode support for CPU 0Scott Williams
Add support for forced Tegra3 LP2 low power mode on the boot processor (CPU 0) via the cluster control interface when all others are offline. Switching to the LP CPU mode is also enabled with this change. LP2 in idle and LP2 mode on the secondary processors is not yet supported. Change-Id: Icb898729f093be5e006c413f701532dd45228687 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd5d8c2b0addfd6853033670b992ae082e4a0d9c8
2011-11-30ARM: tegra: cardhu: Disable power management featuresScott Williams
Tegra3 power management features have not been fully ported to Linux 2.6.39 yet. Disable them temporarily. Change-Id: Id9e1ebcab5f665845e6d1b685364f9cea9fe7329 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd813fa7d2be0ae8eec44c02834e21c2a47b5a846
2011-11-30ARM: tegra: power: Clean up cluster control definitionsScott Williams
Reduce the complexity of the cluster control compile-time conditionals. Also disable DEBUG_CLUSTER_SWITCH because it invokes clock code that takes a mutex when taking of a mutex is disallowed. Change-Id: I9b614d4b0189fbb01d0b7f8af7053c7586d9515b Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R412820dc2fd9f0c9cc7b1e3ad7ead7e2e68a0ff3
2011-11-30ARM: tegra: power: Fix CPU complex suspend/resumeScott Williams
- Invoke cpu_pm_enter()/cpu_pm_exit() to save/restore the GIC processor interface registers for the last processor standing from the cluster control interface. - Disable the GIC processor interface on the last processor standing before shutting down the CPU complex so that wakeup interrupts get routed from the legacy interrupt controller to the flow controller. - For Tegra3 enable GIC pass-through mode to prevent WFI failures. Change-Id: Ia866b17bef47fc8e9e75d4e353394b2d1a09259c Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R249fb53a2622218a7128646d68d8a3552268b4f1
2011-11-30ARM: tegra: power: Fix incorrect flow controller programmingScott Williams
Errors and invalid assumptions about how the flow controller should be programmed were introduced in the port to Linux 2.6.39. - Do not touch the flow controller HALT_EVENTS register for any of the secondary CPUs in suspend_cpu_complex(). Doing so can cause the flow controller state machine to prematurely abort resulting in fatal errors when power gating the CPU complex. - Do not touch the flow controller CSR register for any of the secondary CPUs in restore_cpu_complex(). Doing so can cause the flow controller state machine to prematurely abort resulting in the secondary CPUs waking up before they're supposed to. - suspend_cpu_complex() and restore_cpu_complex() can only be invoked from CPU 0. The hardware does not allow the CPU complex to be suspended from any other CPU. Change-Id: I89546bf53f8f6f12c0e62ce49fc99a46244fa57f Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rf61122cb730d852179d8e2d9e667ae7c65b09c58
2011-11-30ARM: tegra: power: Fix TEGRA_SUSPEND_NONE handlingScott Williams
- Do not assert in tegra_pm_set() if the platform suspend mode is set to TEGRA_SUSPEND_NONE. Just return. - Do not override the platform suspend mode to a deeper power saving mode if the SDRAM refresh context save area cannot be obtained. Change-Id: I1ebceef715f9175b8db25af3df28c48582ec0815 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rfe888ac904de11cb5a63475dc95ab736a39f5c4b
2011-11-30ARM: tegra: Add Tegra 3 CPU hotplug supportScott Williams
Change-Id: Ie43f4efdf884a916c6bc9737157091c35dc44501 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R1f023651504a7d336f7e98921f6372bee0aa1341
2011-11-30ARM: tegra: power: Consolidate power management flagsScott Williams
Consolidate all of the power management control flags in one header and adjust the values of the software flags so that they do not conflict with the values of the hardware flags. Change-Id: I7971d274946d84dcc50bd9d9e0190091ebbefa2e Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R29d2420a74f977c16f73b1abd9ca7470695a53f4
2011-11-30ARM: tegra: Rename tegra<n>_sleep_resetScott Williams
Rename tegra<n>_sleep_reset to tegra<n>_hotplug_shutdown since that is more descriptive of their actual function. Change-Id: I411e2474bd35a799d5367a182809d17933238612 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R72bf50004ab3fcdde5485b84b7ba008247d1bf4c
2011-11-30ARM: tegra: power: Align MMU shutdown code to L1 cache lineScott Williams
The MMU shutdown code must be aligned to an L1 cache line boundary. Change-Id: Ib6c976470983b7f69b45e720104fc65cae54e162 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R305325117ba1debc8d112b4c3596c158df98d75e
2011-11-30ARM: tegra: Remove obsolete filesScott Williams
Change-Id: I92b35e1a9966023be98e532de8f89b6b0497a005 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Raf0dfd3a5ae967563885b05c2e8b03916439dfff
2011-11-30ARM: tegra: clock: Don't require DVFS for setting LP CPU clockScott Williams
If DVFS tables do not exist, assume the CPU power rail is at it's nominal voltage and permit the rate for the LP mode clock to be set normally. Change-Id: I29f592ab1f1b44ed07c187f48cd7eb9de1b6db3d Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R14a4fc8e7c53070afdf29ca9e0c7bfb2269a380d
2011-11-30ARM: v7: Save CP14 registers across suspendScott Williams
Change-Id: I48bd9ddf9f0a65b1754560bae261d0b3faa69e06 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rbbd2387b98c81919b3a8bf9782828c8b4ef33f45
2011-11-30ARM: v7: Save CP15 diagnostic register across suspendScott Williams
Change-Id: I7d0efeb53e41722f92f9373785045ccc61e56adf Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R6ab8cf0cfe2930330b49d3fccee65d8366ef909d
2011-11-30ARM: tegra: power: Disallow LP2 in idle if permanently disabledScott Williams
For a variety of reasons, it is possible that LP2 in idle can never be allowed. If one of these conditions exists, do not allow LP2 in idle to be re-enabled via the module_param interface. Change-Id: I980f147844ad9374c218bfb2a25c0d91dad85281 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rb897f6dc8245e525fd9ac90c9243e290307c4e58
2011-11-30ARM: tegra: power: Eliminate extraneous PMC register writesScott Williams
Writes to PMC registers in the 32 KHz domain are extremely slow. Write PMC SCRATCH0/SCRATCH1 regsiters only when entering LP0. Change-Id: Ib85b436330a8a9a0dc7fbc56889a375a534b8d10 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R8267387cbe889727ca429c2c6dc44630a061c808
2011-11-30ARM: tegra3: Add LP2 TimersScott Williams
Change-Id: I121c8aff9c4cb212ac625ef7751d8cf6b8093068 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes, move hotplug notifier to timer-t3.c Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rbfbfdb1720960dd9ce2847fb16daa932bebb16d2
2011-11-30ARM: tegra2: Update LP2 timersDan Willemsen
Clean up conditionals for LP2 timers Register an interrupt handler for the LP2 timer Change-Id: I6ee6b6971f45f33d5d9295a462778af1d1c9843b Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R6cec04d1c66dc3af22cb9ab7afe0dffaba891cea
2011-11-30ARM: tegra: Move common timer code into timer.cScott Williams
The system timer initialization code for Tegra2 and Tegra3 is essentially the same except for the actual physical timer used and the range of possible reference clock frequencies. This change removes the needless duplication of code and restructures the system timer code into common and SOC-specific parts. Change-Id: Icb6e4c0e2b218c67667be9450e10326e1e42945b Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rbd3fc10b2a6935dd1ca9272695fd0133e0ca4f15
2011-11-30ARM: tegra: Add Tegra GIC extensionsScott Williams
Implement extensions to the standard ARM GIC API for Tegra3 power management. Change-Id: If8b2ce2b366e48bb5ca82d3de2acab1fd0a81bb9 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd7527cd57edf054c871f5d04d7e9185643f79843
2011-11-30ARM: tegra: Redesign Tegra CPU reset handlingScott Williams
- Add a single unified handler for all CPU resets that is copied to IRAM. - Add state information to direct the flow of execution through the reset handler based on the reason a CPU was reset. - Write the EVP CPU reset vector only once per cold/warm boot session. - Prevent modification of the EVP CPU reset vector in Tegra3. Bug 786290 Bug 790458 Change-Id: Ica6707f3514986ee914e73a2d9766a4e06ce2d29 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R7b9859a83717e76c3c083bdde724bd5fef9ce089
2011-11-30ARM: tegra: Trivial changesScott Williams
Change-Id: Id45f6be8336370bf011484bea0a90e7e9f49f026 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R06af455b61cb70a1a7dc18b38ad3f816d4ccba63
2011-11-30ARM: tegra: Consolidate flow control registersScott Williams
Change-Id: I07ffcffafcf47fd7539b22d4829712e041293bf3 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R34a7800e24254d54b499411652d59421be703619
2011-11-30ARM: tegra: Rename flow control registersScott Williams
Change-Id: Ibb4f62697819bd3e15164b4e639ff4bc180f92bf Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R5d91fec25c89725ed35166dcf3fc3cced3acdc7f
2011-11-30ARM: tegra: whistler: Use common IRAM carveoutScott Williams
Change-Id: I17abffdfc338d5e8a6e678fa38605b1aeee651fa Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R56b6dbaecbd330a0f547375c4680dee6217f04c3
2011-11-30ARM: tegra: ventana: Use common IRAM carveoutScott Williams
Change-Id: Ie6d888cfea36c53ad8d5fe47217a18e48e13cb76 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rb6a71f84da11bbd4eebe19611cbbd776a1fdd425
2011-11-30ARM: tegra: enterprise: Use common IRAM carveoutScott Williams
Change-Id: I6e05d75a0c806fabbfebd78929323b8fa200ee52 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R9d382296e2fa0e4264d4b293b6beb84876f2d724
2011-11-30ARM: tegra: cardhu: Use common IRAM carveoutScott Williams
Change-Id: I9dcd5b3c9351f191b23ee79da18ace1fc9fc471c Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R7c407cef86d974e412761c2ba693047088d9bcf2
2011-11-30ARM: tegra: aruba: Use common IRAM carveoutScott Williams
Change-Id: I10ea888d3082bd16fb7e373ea653b9674e6bc81b Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Re464d6e2f18b4347a37967f910515a00a93ee9f8
2011-11-30media: tegra: avp: Reserve beginning of IRAM for cpu reset handlerScott Williams
Change-Id: Ib6fb0663f0a325aa0552f2625a93464648102e02 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R55b2be7cdb1ababff5de8dfa24d63d2ad8a2f140
2011-11-30ARM: tegra: Reserve first 1K of IRAM for cpu reset handlerScott Williams
Change-Id: I377cb69b07071511de7b1a1de8d315e6bf1919b0 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rcd9cc391e18aebc6485698a73347a1e8c458c4c5
2011-11-30ARM: tegra: Don't die if L2X0 cache is turned offScott Williams
Change-Id: I1e065ae03da74d1ebf3327f8e29df7f81aa512a8 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd5df55e4c8afeea439ef6003fdf2b89064753bd2
2011-11-30ARM: tegra3: Cluster Switch and LP0 require PM_SLEEPScott Williams
Change-Id: If3d4fa59cf6d7cd8692f6e5b59414a923abcfd0d Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rec3560499e4c64fd76a873689691cbae59f7602b
2011-11-30ARM: tegra: LP2: Update statisticsScott Williams
Change-Id: Ic878edc316865df79a571255fd0462360599472a Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R206b2c1cd07c360ea2f5be1a54c9b29944bc1df3
2011-11-30ARM: tegra: LP2: Choose the earliest wakeup requestScott Williams
This will wake up earlier if the other CPU's request is shorter. Change-Id: I0abf20d482e5bd28893b2e014fcf50e6ac557241 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R65c18d77baf7b49be32bb7eb6825af2d1865d356
2011-11-30ARM: tegra: Add LP2 exit latency correctionScott Williams
Change-Id: I37cb57f8674d8ddea3861fdc59543c3dfa8498db Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R0a1d0c79e22f9191bde70b8b05541c5bfe26f4df
2011-11-30ARM: tegra: Keep track of actual LP2 timeScott Williams
Change-Id: I570b771b67f76123fb81b41ceb27bebb9c9e011f Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R5cace01cb03450d21fda2aca33ea806f13cc3015
2011-11-30ARM: tegra: Catch early LP2 exitsScott Williams
Change-Id: I107d301ec8e8cd3b69ea293faab15b8d766e38f4 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R9f8f016c1850e2c65f30f2f67241a94acf8a7755
2011-11-30ARM: tegra: Prevent LP2 if request is less than target residencyScott Williams
Change-Id: Icc7409b611439ba94ec504579c00ab9227c9a857 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R4b56e98c821627de480a67c241363608ebfc2f07
2011-11-30ARM: tegra: Idle event wakeup timerScott Williams
Change-Id: If072ef10f02d5be7560fdf42584ab11b2a863481 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rf1ace67e281b1581501aaa936cd9137d326f2c4a
2011-11-30ARM: tegra2: Fix CONFIG_HOTPLUG_CPU dependenciesScott Williams
Change-Id: I54fab1134f2c51337da6f7b2ccc5ab304b600dea Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R45b2521f5d574774f1db13f6ef9ade5c116da9b4
2011-11-30ARM: tegra: Remove LP0/1/2 dependence on CONFIG_SMPScott Williams
LP0/1/2 do not require SMP. Change-Id: I85572da9056a5120c13cd7e65a8062309541b52a Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rf20625360cc8926949283b8cb477cf596f7fc3e9
2011-11-30ARM: tegra: Update tegra_lp0_suspend_init stubbingScott Williams
Change-Id: I961125e938e72506dc304025b418e80387a5062e Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R393c5a77803f276467d2974041653eb92026601e
2011-11-30ARM: tegra: Rename flow control registersScott Williams
Change-Id: I2647718dc9c9420e57b24a810738c33ef05bcf61 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R6d5c6a52a2b0fd1dafd021d4a187528aeca26516
2011-11-30ARM: tegra: Always compile sleep.SScott Williams
Decouple LP3 (WFI) mode and CPU hotplug shutdown from CONFIG_PM_SLEEP. Change-Id: Ie959fa5e044ab4a7f84772d3b743ce2680465acc Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R8f01e646e7bf65350db44557de87c4c2a33d8059
2011-11-30ARM: tegra: sleep: Remove hard-coded register offsetScott Williams
Change-Id: I0fb4dc6ff2158d2d9661e3a231e02fc3ae0cc86e Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Ra4a5d9780d6329b2d029e3391c5d5145940c29c7
2011-11-30ARM: tegra: Rearrange pm.c for cleaner ifdefsScott Williams
Change-Id: I02a8a10ee842bcc02d590f116484f4ff8d0705b0 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R1105e3976f266bf4e229510c8c5ae876f900b2ce
2011-11-30ARM: tegra: Fail when tegra2_cpu_reset is called by CPU 0Scott Williams
CPU 0 must be the last CPU to shutdown since it's the only one that can perform CPU power gating or rail gating. Therefore, CPU 0 can reset CPU 1, but the reverse is not allowed. Change-Id: I61296ee49d219a67c1fb864badc1170cd4684f8e Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R722033713d671fe702d9a7c0813993f9c7e6bd01
2011-11-30ARM: tegra2: Don't use tegra_cpu_save to exit coherency on resetScott Williams
Change tegra2_sleep_reset not to depend on tegra_cpu_save to exit coherency. Now tegra2_sleep_reset no longer depends on CONFIG_PM_SLEEP Change-Id: I478e723e826fd3ddbd6a6e8bceaedf795bd2ee26 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R2138dcf60971f7a9ad78e6a39fc2206c99faf7b5
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