1449 files changed, 23498 insertions, 124470 deletions

diff --git a/include/acpi/acconfig.h b/include/acpi/acconfig.h
index 4eb75a88795a..29feee27f0ea 100644
--- a/include/acpi/acconfig.h
+++ b/include/acpi/acconfig.h
@@ -63,7 +63,7 @@
 
 /* Current ACPICA subsystem version in YYYYMMDD format */
 
-#define ACPI_CA_VERSION 		0x20080609
+#define ACPI_CA_VERSION                 0x20080926
 
 /*
  * OS name, used for the _OS object.  The _OS object is essentially obsolete,
diff --git a/include/acpi/acdebug.h b/include/acpi/acdebug.h
index c5a1b50d8d94..62c59df3b86c 100644
--- a/include/acpi/acdebug.h
+++ b/include/acpi/acdebug.h
@@ -123,6 +123,10 @@ void acpi_db_check_integrity(void);
 
 void acpi_db_generate_gpe(char *gpe_arg, char *block_arg);
 
+void acpi_db_check_predefined_names(void);
+
+void acpi_db_batch_execute(void);
+
 /*
  * dbdisply - debug display commands
  */
@@ -150,6 +154,10 @@ void
 acpi_db_display_argument_object(union acpi_operand_object *obj_desc,
 				struct acpi_walk_state *walk_state);
 
+void acpi_db_check_predefined_names(void);
+
+void acpi_db_batch_execute(void);
+
 /*
  * dbexec - debugger control method execution
  */
diff --git a/include/acpi/acdisasm.h b/include/acpi/acdisasm.h
index f53faca8ec80..0c1ed387073c 100644
--- a/include/acpi/acdisasm.h
+++ b/include/acpi/acdisasm.h
@@ -186,6 +186,8 @@ extern struct acpi_dmtable_info acpi_dm_table_info_madt5[];
 extern struct acpi_dmtable_info acpi_dm_table_info_madt6[];
 extern struct acpi_dmtable_info acpi_dm_table_info_madt7[];
 extern struct acpi_dmtable_info acpi_dm_table_info_madt8[];
+extern struct acpi_dmtable_info acpi_dm_table_info_madt9[];
+extern struct acpi_dmtable_info acpi_dm_table_info_madt10[];
 extern struct acpi_dmtable_info acpi_dm_table_info_madt_hdr[];
 extern struct acpi_dmtable_info acpi_dm_table_info_mcfg[];
 extern struct acpi_dmtable_info acpi_dm_table_info_mcfg0[];
@@ -197,8 +199,10 @@ extern struct acpi_dmtable_info acpi_dm_table_info_slit[];
 extern struct acpi_dmtable_info acpi_dm_table_info_spcr[];
 extern struct acpi_dmtable_info acpi_dm_table_info_spmi[];
 extern struct acpi_dmtable_info acpi_dm_table_info_srat[];
+extern struct acpi_dmtable_info acpi_dm_table_info_srat_hdr[];
 extern struct acpi_dmtable_info acpi_dm_table_info_srat0[];
 extern struct acpi_dmtable_info acpi_dm_table_info_srat1[];
+extern struct acpi_dmtable_info acpi_dm_table_info_srat2[];
 extern struct acpi_dmtable_info acpi_dm_table_info_tcpa[];
 extern struct acpi_dmtable_info acpi_dm_table_info_wdrt[];
 
diff --git a/include/acpi/acdispat.h b/include/acpi/acdispat.h
index 21a73a105d0a..6291904be01e 100644
--- a/include/acpi/acdispat.h
+++ b/include/acpi/acdispat.h
@@ -157,7 +157,7 @@ acpi_ds_init_callbacks(struct acpi_walk_state *walk_state, u32 pass_number);
  * dsmthdat - method data (locals/args)
  */
 acpi_status
-acpi_ds_store_object_to_local(u16 opcode,
+acpi_ds_store_object_to_local(u8 type,
 			      u32 index,
 			      union acpi_operand_object *src_desc,
 			      struct acpi_walk_state *walk_state);
@@ -173,7 +173,7 @@ void acpi_ds_method_data_delete_all(struct acpi_walk_state *walk_state);
 u8 acpi_ds_is_method_value(union acpi_operand_object *obj_desc);
 
 acpi_status
-acpi_ds_method_data_get_value(u16 opcode,
+acpi_ds_method_data_get_value(u8 type,
 			      u32 index,
 			      struct acpi_walk_state *walk_state,
 			      union acpi_operand_object **dest_desc);
@@ -184,7 +184,7 @@ acpi_ds_method_data_init_args(union acpi_operand_object **params,
 			      struct acpi_walk_state *walk_state);
 
 acpi_status
-acpi_ds_method_data_get_node(u16 opcode,
+acpi_ds_method_data_get_node(u8 type,
 			     u32 index,
 			     struct acpi_walk_state *walk_state,
 			     struct acpi_namespace_node **node);
diff --git a/include/acpi/acexcep.h b/include/acpi/acexcep.h
index e5a890ffeb02..84f5cb242863 100644
--- a/include/acpi/acexcep.h
+++ b/include/acpi/acexcep.h
@@ -76,25 +76,21 @@
 #define AE_STACK_OVERFLOW               (acpi_status) (0x000C | AE_CODE_ENVIRONMENTAL)
 #define AE_STACK_UNDERFLOW              (acpi_status) (0x000D | AE_CODE_ENVIRONMENTAL)
 #define AE_NOT_IMPLEMENTED              (acpi_status) (0x000E | AE_CODE_ENVIRONMENTAL)
-#define AE_VERSION_MISMATCH             (acpi_status) (0x000F | AE_CODE_ENVIRONMENTAL)
-#define AE_SUPPORT                      (acpi_status) (0x0010 | AE_CODE_ENVIRONMENTAL)
-#define AE_SHARE                        (acpi_status) (0x0011 | AE_CODE_ENVIRONMENTAL)
-#define AE_LIMIT                        (acpi_status) (0x0012 | AE_CODE_ENVIRONMENTAL)
-#define AE_TIME                         (acpi_status) (0x0013 | AE_CODE_ENVIRONMENTAL)
-#define AE_UNKNOWN_STATUS               (acpi_status) (0x0014 | AE_CODE_ENVIRONMENTAL)
-#define AE_ACQUIRE_DEADLOCK             (acpi_status) (0x0015 | AE_CODE_ENVIRONMENTAL)
-#define AE_RELEASE_DEADLOCK             (acpi_status) (0x0016 | AE_CODE_ENVIRONMENTAL)
-#define AE_NOT_ACQUIRED                 (acpi_status) (0x0017 | AE_CODE_ENVIRONMENTAL)
-#define AE_ALREADY_ACQUIRED             (acpi_status) (0x0018 | AE_CODE_ENVIRONMENTAL)
-#define AE_NO_HARDWARE_RESPONSE         (acpi_status) (0x0019 | AE_CODE_ENVIRONMENTAL)
-#define AE_NO_GLOBAL_LOCK               (acpi_status) (0x001A | AE_CODE_ENVIRONMENTAL)
-#define AE_LOGICAL_ADDRESS              (acpi_status) (0x001B | AE_CODE_ENVIRONMENTAL)
-#define AE_ABORT_METHOD                 (acpi_status) (0x001C | AE_CODE_ENVIRONMENTAL)
-#define AE_SAME_HANDLER                 (acpi_status) (0x001D | AE_CODE_ENVIRONMENTAL)
-#define AE_WAKE_ONLY_GPE                (acpi_status) (0x001E | AE_CODE_ENVIRONMENTAL)
-#define AE_OWNER_ID_LIMIT               (acpi_status) (0x001F | AE_CODE_ENVIRONMENTAL)
+#define AE_SUPPORT                      (acpi_status) (0x000F | AE_CODE_ENVIRONMENTAL)
+#define AE_LIMIT                        (acpi_status) (0x0010 | AE_CODE_ENVIRONMENTAL)
+#define AE_TIME                         (acpi_status) (0x0011 | AE_CODE_ENVIRONMENTAL)
+#define AE_ACQUIRE_DEADLOCK             (acpi_status) (0x0012 | AE_CODE_ENVIRONMENTAL)
+#define AE_RELEASE_DEADLOCK             (acpi_status) (0x0013 | AE_CODE_ENVIRONMENTAL)
+#define AE_NOT_ACQUIRED                 (acpi_status) (0x0014 | AE_CODE_ENVIRONMENTAL)
+#define AE_ALREADY_ACQUIRED             (acpi_status) (0x0015 | AE_CODE_ENVIRONMENTAL)
+#define AE_NO_HARDWARE_RESPONSE         (acpi_status) (0x0016 | AE_CODE_ENVIRONMENTAL)
+#define AE_NO_GLOBAL_LOCK               (acpi_status) (0x0017 | AE_CODE_ENVIRONMENTAL)
+#define AE_ABORT_METHOD                 (acpi_status) (0x0018 | AE_CODE_ENVIRONMENTAL)
+#define AE_SAME_HANDLER                 (acpi_status) (0x0019 | AE_CODE_ENVIRONMENTAL)
+#define AE_WAKE_ONLY_GPE                (acpi_status) (0x001A | AE_CODE_ENVIRONMENTAL)
+#define AE_OWNER_ID_LIMIT               (acpi_status) (0x001B | AE_CODE_ENVIRONMENTAL)
 
-#define AE_CODE_ENV_MAX                 0x001F
+#define AE_CODE_ENV_MAX                 0x001B
 
 /*
  * Programmer exceptions
@@ -103,14 +99,12 @@
 #define AE_BAD_CHARACTER                (acpi_status) (0x0002 | AE_CODE_PROGRAMMER)
 #define AE_BAD_PATHNAME                 (acpi_status) (0x0003 | AE_CODE_PROGRAMMER)
 #define AE_BAD_DATA                     (acpi_status) (0x0004 | AE_CODE_PROGRAMMER)
-#define AE_BAD_ADDRESS                  (acpi_status) (0x0005 | AE_CODE_PROGRAMMER)
-#define AE_ALIGNMENT                    (acpi_status) (0x0006 | AE_CODE_PROGRAMMER)
-#define AE_BAD_HEX_CONSTANT             (acpi_status) (0x0007 | AE_CODE_PROGRAMMER)
-#define AE_BAD_OCTAL_CONSTANT           (acpi_status) (0x0008 | AE_CODE_PROGRAMMER)
-#define AE_BAD_DECIMAL_CONSTANT         (acpi_status) (0x0009 | AE_CODE_PROGRAMMER)
-#define AE_MISSING_ARGUMENTS		(acpi_status) (0x000A | AE_CODE_PROGRAMMER)
+#define AE_BAD_HEX_CONSTANT             (acpi_status) (0x0005 | AE_CODE_PROGRAMMER)
+#define AE_BAD_OCTAL_CONSTANT           (acpi_status) (0x0006 | AE_CODE_PROGRAMMER)
+#define AE_BAD_DECIMAL_CONSTANT         (acpi_status) (0x0007 | AE_CODE_PROGRAMMER)
+#define AE_MISSING_ARGUMENTS            (acpi_status) (0x0008 | AE_CODE_PROGRAMMER)
 
-#define AE_CODE_PGM_MAX 		0x000A
+#define AE_CODE_PGM_MAX                 0x0008
 
 /*
  * Acpi table exceptions
@@ -119,51 +113,48 @@
 #define AE_BAD_HEADER                   (acpi_status) (0x0002 | AE_CODE_ACPI_TABLES)
 #define AE_BAD_CHECKSUM                 (acpi_status) (0x0003 | AE_CODE_ACPI_TABLES)
 #define AE_BAD_VALUE                    (acpi_status) (0x0004 | AE_CODE_ACPI_TABLES)
-#define AE_TABLE_NOT_SUPPORTED          (acpi_status) (0x0005 | AE_CODE_ACPI_TABLES)
-#define AE_INVALID_TABLE_LENGTH         (acpi_status) (0x0006 | AE_CODE_ACPI_TABLES)
+#define AE_INVALID_TABLE_LENGTH         (acpi_status) (0x0005 | AE_CODE_ACPI_TABLES)
 
-#define AE_CODE_TBL_MAX                 0x0006
+#define AE_CODE_TBL_MAX                 0x0005
 
 /*
  * AML exceptions.  These are caused by problems with
  * the actual AML byte stream
  */
-#define AE_AML_ERROR                    (acpi_status) (0x0001 | AE_CODE_AML)
-#define AE_AML_PARSE                    (acpi_status) (0x0002 | AE_CODE_AML)
-#define AE_AML_BAD_OPCODE               (acpi_status) (0x0003 | AE_CODE_AML)
-#define AE_AML_NO_OPERAND               (acpi_status) (0x0004 | AE_CODE_AML)
-#define AE_AML_OPERAND_TYPE             (acpi_status) (0x0005 | AE_CODE_AML)
-#define AE_AML_OPERAND_VALUE            (acpi_status) (0x0006 | AE_CODE_AML)
-#define AE_AML_UNINITIALIZED_LOCAL      (acpi_status) (0x0007 | AE_CODE_AML)
-#define AE_AML_UNINITIALIZED_ARG        (acpi_status) (0x0008 | AE_CODE_AML)
-#define AE_AML_UNINITIALIZED_ELEMENT    (acpi_status) (0x0009 | AE_CODE_AML)
-#define AE_AML_NUMERIC_OVERFLOW         (acpi_status) (0x000A | AE_CODE_AML)
-#define AE_AML_REGION_LIMIT             (acpi_status) (0x000B | AE_CODE_AML)
-#define AE_AML_BUFFER_LIMIT             (acpi_status) (0x000C | AE_CODE_AML)
-#define AE_AML_PACKAGE_LIMIT            (acpi_status) (0x000D | AE_CODE_AML)
-#define AE_AML_DIVIDE_BY_ZERO           (acpi_status) (0x000E | AE_CODE_AML)
-#define AE_AML_BAD_NAME                 (acpi_status) (0x000F | AE_CODE_AML)
-#define AE_AML_NAME_NOT_FOUND           (acpi_status) (0x0010 | AE_CODE_AML)
-#define AE_AML_INTERNAL                 (acpi_status) (0x0011 | AE_CODE_AML)
-#define AE_AML_INVALID_SPACE_ID         (acpi_status) (0x0012 | AE_CODE_AML)
-#define AE_AML_STRING_LIMIT             (acpi_status) (0x0013 | AE_CODE_AML)
-#define AE_AML_NO_RETURN_VALUE          (acpi_status) (0x0014 | AE_CODE_AML)
-#define AE_AML_METHOD_LIMIT             (acpi_status) (0x0015 | AE_CODE_AML)
-#define AE_AML_NOT_OWNER                (acpi_status) (0x0016 | AE_CODE_AML)
-#define AE_AML_MUTEX_ORDER              (acpi_status) (0x0017 | AE_CODE_AML)
-#define AE_AML_MUTEX_NOT_ACQUIRED       (acpi_status) (0x0018 | AE_CODE_AML)
-#define AE_AML_INVALID_RESOURCE_TYPE    (acpi_status) (0x0019 | AE_CODE_AML)
-#define AE_AML_INVALID_INDEX            (acpi_status) (0x001A | AE_CODE_AML)
-#define AE_AML_REGISTER_LIMIT           (acpi_status) (0x001B | AE_CODE_AML)
-#define AE_AML_NO_WHILE                 (acpi_status) (0x001C | AE_CODE_AML)
-#define AE_AML_ALIGNMENT                (acpi_status) (0x001D | AE_CODE_AML)
-#define AE_AML_NO_RESOURCE_END_TAG      (acpi_status) (0x001E | AE_CODE_AML)
-#define AE_AML_BAD_RESOURCE_VALUE       (acpi_status) (0x001F | AE_CODE_AML)
-#define AE_AML_CIRCULAR_REFERENCE       (acpi_status) (0x0020 | AE_CODE_AML)
-#define AE_AML_BAD_RESOURCE_LENGTH      (acpi_status) (0x0021 | AE_CODE_AML)
-#define AE_AML_ILLEGAL_ADDRESS          (acpi_status) (0x0022 | AE_CODE_AML)
+#define AE_AML_BAD_OPCODE               (acpi_status) (0x0001 | AE_CODE_AML)
+#define AE_AML_NO_OPERAND               (acpi_status) (0x0002 | AE_CODE_AML)
+#define AE_AML_OPERAND_TYPE             (acpi_status) (0x0003 | AE_CODE_AML)
+#define AE_AML_OPERAND_VALUE            (acpi_status) (0x0004 | AE_CODE_AML)
+#define AE_AML_UNINITIALIZED_LOCAL      (acpi_status) (0x0005 | AE_CODE_AML)
+#define AE_AML_UNINITIALIZED_ARG        (acpi_status) (0x0006 | AE_CODE_AML)
+#define AE_AML_UNINITIALIZED_ELEMENT    (acpi_status) (0x0007 | AE_CODE_AML)
+#define AE_AML_NUMERIC_OVERFLOW         (acpi_status) (0x0008 | AE_CODE_AML)
+#define AE_AML_REGION_LIMIT             (acpi_status) (0x0009 | AE_CODE_AML)
+#define AE_AML_BUFFER_LIMIT             (acpi_status) (0x000A | AE_CODE_AML)
+#define AE_AML_PACKAGE_LIMIT            (acpi_status) (0x000B | AE_CODE_AML)
+#define AE_AML_DIVIDE_BY_ZERO           (acpi_status) (0x000C | AE_CODE_AML)
+#define AE_AML_BAD_NAME                 (acpi_status) (0x000D | AE_CODE_AML)
+#define AE_AML_NAME_NOT_FOUND           (acpi_status) (0x000E | AE_CODE_AML)
+#define AE_AML_INTERNAL                 (acpi_status) (0x000F | AE_CODE_AML)
+#define AE_AML_INVALID_SPACE_ID         (acpi_status) (0x0010 | AE_CODE_AML)
+#define AE_AML_STRING_LIMIT             (acpi_status) (0x0011 | AE_CODE_AML)
+#define AE_AML_NO_RETURN_VALUE          (acpi_status) (0x0012 | AE_CODE_AML)
+#define AE_AML_METHOD_LIMIT             (acpi_status) (0x0013 | AE_CODE_AML)
+#define AE_AML_NOT_OWNER                (acpi_status) (0x0014 | AE_CODE_AML)
+#define AE_AML_MUTEX_ORDER              (acpi_status) (0x0015 | AE_CODE_AML)
+#define AE_AML_MUTEX_NOT_ACQUIRED       (acpi_status) (0x0016 | AE_CODE_AML)
+#define AE_AML_INVALID_RESOURCE_TYPE    (acpi_status) (0x0017 | AE_CODE_AML)
+#define AE_AML_INVALID_INDEX            (acpi_status) (0x0018 | AE_CODE_AML)
+#define AE_AML_REGISTER_LIMIT           (acpi_status) (0x0019 | AE_CODE_AML)
+#define AE_AML_NO_WHILE                 (acpi_status) (0x001A | AE_CODE_AML)
+#define AE_AML_ALIGNMENT                (acpi_status) (0x001B | AE_CODE_AML)
+#define AE_AML_NO_RESOURCE_END_TAG      (acpi_status) (0x001C | AE_CODE_AML)
+#define AE_AML_BAD_RESOURCE_VALUE       (acpi_status) (0x001D | AE_CODE_AML)
+#define AE_AML_CIRCULAR_REFERENCE       (acpi_status) (0x001E | AE_CODE_AML)
+#define AE_AML_BAD_RESOURCE_LENGTH      (acpi_status) (0x001F | AE_CODE_AML)
+#define AE_AML_ILLEGAL_ADDRESS          (acpi_status) (0x0020 | AE_CODE_AML)
 
-#define AE_CODE_AML_MAX                 0x0022
+#define AE_CODE_AML_MAX                 0x0020
 
 /*
  * Internal exceptions used for control
@@ -206,19 +197,15 @@ char const *acpi_gbl_exception_names_env[] = {
 	"AE_STACK_OVERFLOW",
 	"AE_STACK_UNDERFLOW",
 	"AE_NOT_IMPLEMENTED",
-	"AE_VERSION_MISMATCH",
 	"AE_SUPPORT",
-	"AE_SHARE",
 	"AE_LIMIT",
 	"AE_TIME",
-	"AE_UNKNOWN_STATUS",
 	"AE_ACQUIRE_DEADLOCK",
 	"AE_RELEASE_DEADLOCK",
 	"AE_NOT_ACQUIRED",
 	"AE_ALREADY_ACQUIRED",
 	"AE_NO_HARDWARE_RESPONSE",
 	"AE_NO_GLOBAL_LOCK",
-	"AE_LOGICAL_ADDRESS",
 	"AE_ABORT_METHOD",
 	"AE_SAME_HANDLER",
 	"AE_WAKE_ONLY_GPE",
@@ -231,8 +218,6 @@ char const *acpi_gbl_exception_names_pgm[] = {
 	"AE_BAD_CHARACTER",
 	"AE_BAD_PATHNAME",
 	"AE_BAD_DATA",
-	"AE_BAD_ADDRESS",
-	"AE_ALIGNMENT",
 	"AE_BAD_HEX_CONSTANT",
 	"AE_BAD_OCTAL_CONSTANT",
 	"AE_BAD_DECIMAL_CONSTANT",
@@ -245,14 +230,11 @@ char const *acpi_gbl_exception_names_tbl[] = {
 	"AE_BAD_HEADER",
 	"AE_BAD_CHECKSUM",
 	"AE_BAD_VALUE",
-	"AE_TABLE_NOT_SUPPORTED",
 	"AE_INVALID_TABLE_LENGTH"
 };
 
 char const *acpi_gbl_exception_names_aml[] = {
 	NULL,
-	"AE_AML_ERROR",
-	"AE_AML_PARSE",
 	"AE_AML_BAD_OPCODE",
 	"AE_AML_NO_OPERAND",
 	"AE_AML_OPERAND_TYPE",
@@ -284,7 +266,7 @@ char const *acpi_gbl_exception_names_aml[] = {
 	"AE_AML_BAD_RESOURCE_VALUE",
 	"AE_AML_CIRCULAR_REFERENCE",
 	"AE_AML_BAD_RESOURCE_LENGTH",
-	"AE_AML_ILLEGAL_ADDRESS"
+	"AE_AML_ILLEGAL_ADDRESS",
 };
 
 char const *acpi_gbl_exception_names_ctrl[] = {
diff --git a/include/acpi/aclocal.h b/include/acpi/aclocal.h
index b221c8583ddd..ecab527cf78e 100644
--- a/include/acpi/aclocal.h
+++ b/include/acpi/aclocal.h
@@ -208,6 +208,7 @@ struct acpi_namespace_node {
 #define ANOBJ_METHOD_ARG                0x04	/* Node is a method argument */
 #define ANOBJ_METHOD_LOCAL              0x08	/* Node is a method local */
 #define ANOBJ_SUBTREE_HAS_INI           0x10	/* Used to optimize device initialization */
+#define ANOBJ_EVALUATED                 0x20	/* Set on first evaluation of node */
 
 #define ANOBJ_IS_EXTERNAL               0x08	/* i_aSL only: This object created via External() */
 #define ANOBJ_METHOD_NO_RETVAL          0x10	/* i_aSL only: Method has no return value */
@@ -340,6 +341,82 @@ acpi_status(*ACPI_INTERNAL_METHOD) (struct acpi_walk_state * walk_state);
 #define ACPI_BTYPE_OBJECTS_AND_REFS     0x0001FFFF	/* ARG or LOCAL */
 #define ACPI_BTYPE_ALL_OBJECTS          0x0000FFFF
 
+/*
+ * Information structure for ACPI predefined names.
+ * Each entry in the table contains the following items:
+ *
+ * Name                 - The ACPI reserved name
+ * param_count          - Number of arguments to the method
+ * expected_return_btypes - Allowed type(s) for the return value
+ */
+struct acpi_name_info {
+	char name[ACPI_NAME_SIZE];
+	u8 param_count;
+	u8 expected_btypes;
+};
+
+/*
+ * Secondary information structures for ACPI predefined objects that return
+ * package objects. This structure appears as the next entry in the table
+ * after the NAME_INFO structure above.
+ *
+ * The reason for this is to minimize the size of the predefined name table.
+ */
+
+/*
+ * Used for ACPI_PTYPE1_FIXED, ACPI_PTYPE1_VAR, ACPI_PTYPE2,
+ * ACPI_PTYPE2_MIN, ACPI_PTYPE2_PKG_COUNT, ACPI_PTYPE2_COUNT
+ */
+struct acpi_package_info {
+	u8 type;
+	u8 object_type1;
+	u8 count1;
+	u8 object_type2;
+	u8 count2;
+	u8 reserved;
+};
+
+/* Used for ACPI_PTYPE2_FIXED */
+
+struct acpi_package_info2 {
+	u8 type;
+	u8 count;
+	u8 object_type[4];
+};
+
+/* Used for ACPI_PTYPE1_OPTION */
+
+struct acpi_package_info3 {
+	u8 type;
+	u8 count;
+	u8 object_type[2];
+	u8 tail_object_type;
+	u8 reserved;
+};
+
+union acpi_predefined_info {
+	struct acpi_name_info info;
+	struct acpi_package_info ret_info;
+	struct acpi_package_info2 ret_info2;
+	struct acpi_package_info3 ret_info3;
+};
+
+/*
+ * Bitmapped return value types
+ * Note: the actual data types must be contiguous, a loop in nspredef.c
+ * depends on this.
+ */
+#define ACPI_RTYPE_ANY                  0x00
+#define ACPI_RTYPE_NONE                 0x01
+#define ACPI_RTYPE_INTEGER              0x02
+#define ACPI_RTYPE_STRING               0x04
+#define ACPI_RTYPE_BUFFER               0x08
+#define ACPI_RTYPE_PACKAGE              0x10
+#define ACPI_RTYPE_REFERENCE            0x20
+#define ACPI_RTYPE_ALL                  0x3F
+
+#define ACPI_NUM_RTYPES                 5	/* Number of actual object types */
+
 /*****************************************************************************
  *
  * Event typedefs and structs
diff --git a/include/acpi/acmacros.h b/include/acpi/acmacros.h
index 57ab9e9d7593..a597207e2835 100644
--- a/include/acpi/acmacros.h
+++ b/include/acpi/acmacros.h
@@ -62,7 +62,7 @@
 #define ACPI_ARRAY_LENGTH(x)            (sizeof(x) / sizeof((x)[0]))
 
 /*
- * Extract data using a pointer.  Any more than a byte and we
+ * Extract data using a pointer. Any more than a byte and we
  * get into potential aligment issues -- see the STORE macros below.
  * Use with care.
  */
@@ -80,21 +80,21 @@
  */
 #define ACPI_CAST_PTR(t, p)             ((t *) (acpi_uintptr_t) (p))
 #define ACPI_CAST_INDIRECT_PTR(t, p)    ((t **) (acpi_uintptr_t) (p))
-#define ACPI_ADD_PTR(t, a, b)		ACPI_CAST_PTR (t, (ACPI_CAST_PTR (u8,(a)) + (acpi_size)(b)))
-#define ACPI_PTR_DIFF(a, b)		(acpi_size) (ACPI_CAST_PTR (u8,(a)) - ACPI_CAST_PTR (u8,(b)))
+#define ACPI_ADD_PTR(t, a, b)		ACPI_CAST_PTR (t, (ACPI_CAST_PTR (u8, (a)) + (acpi_size)(b)))
+#define ACPI_PTR_DIFF(a, b)		(acpi_size) (ACPI_CAST_PTR (u8, (a)) - ACPI_CAST_PTR (u8, (b)))
 
 /* Pointer/Integer type conversions */
 
 #define ACPI_TO_POINTER(i)		ACPI_ADD_PTR (void, (void *) NULL, (acpi_size) i)
-#define ACPI_TO_INTEGER(p)              ACPI_PTR_DIFF (p,(void *) NULL)
-#define ACPI_OFFSET(d,f)                (acpi_size) ACPI_PTR_DIFF (&(((d *)0)->f),(void *) NULL)
+#define ACPI_TO_INTEGER(p)              ACPI_PTR_DIFF (p, (void *) NULL)
+#define ACPI_OFFSET(d, f)               (acpi_size) ACPI_PTR_DIFF (&(((d *)0)->f), (void *) NULL)
 #define ACPI_PHYSADDR_TO_PTR(i)         ACPI_TO_POINTER(i)
 #define ACPI_PTR_TO_PHYSADDR(i)         ACPI_TO_INTEGER(i)
 
 #ifndef ACPI_MISALIGNMENT_NOT_SUPPORTED
-#define ACPI_COMPARE_NAME(a,b)          (*ACPI_CAST_PTR (u32,(a)) == *ACPI_CAST_PTR (u32,(b)))
+#define ACPI_COMPARE_NAME(a, b)         (*ACPI_CAST_PTR (u32, (a)) == *ACPI_CAST_PTR (u32, (b)))
 #else
-#define ACPI_COMPARE_NAME(a,b)          (!ACPI_STRNCMP (ACPI_CAST_PTR (char,(a)), ACPI_CAST_PTR (char,(b)), ACPI_NAME_SIZE))
+#define ACPI_COMPARE_NAME(a, b)         (!ACPI_STRNCMP (ACPI_CAST_PTR (char, (a)), ACPI_CAST_PTR (char, (b)), ACPI_NAME_SIZE))
 #endif
 
 /*
@@ -114,7 +114,7 @@ struct acpi_integer_overlay {
 
 /* Split 64-bit integer into two 32-bit values. Use with %8.8_x%8.8_x */
 
-#define ACPI_FORMAT_UINT64(i)           ACPI_HIDWORD(i),ACPI_LODWORD(i)
+#define ACPI_FORMAT_UINT64(i)           ACPI_HIDWORD(i), ACPI_LODWORD(i)
 
 #if ACPI_MACHINE_WIDTH == 64
 #define ACPI_FORMAT_NATIVE_UINT(i)      ACPI_FORMAT_UINT64(i)
@@ -132,37 +132,33 @@ struct acpi_integer_overlay {
  * Macros for big-endian machines
  */
 
-/* This macro sets a buffer index, starting from the end of the buffer */
-
-#define ACPI_BUFFER_INDEX(buf_len,buf_offset,byte_gran) ((buf_len) - (((buf_offset)+1) * (byte_gran)))
-
 /* These macros reverse the bytes during the move, converting little-endian to big endian */
 
 			  /* Big Endian      <==        Little Endian */
 			  /*  Hi...Lo                     Lo...Hi     */
 /* 16-bit source, 16/32/64 destination */
 
-#define ACPI_MOVE_16_TO_16(d,s)         {((  u8 *)(void *)(d))[0] = ((u8 *)(void *)(s))[1];\
+#define ACPI_MOVE_16_TO_16(d, s)        {((  u8 *)(void *)(d))[0] = ((u8 *)(void *)(s))[1];\
 					   ((  u8 *)(void *)(d))[1] = ((u8 *)(void *)(s))[0];}
 
-#define ACPI_MOVE_16_TO_32(d,s)         {(*(u32 *)(void *)(d))=0;\
+#define ACPI_MOVE_16_TO_32(d, s)        {(*(u32 *)(void *)(d))=0;\
 							   ((u8 *)(void *)(d))[2] = ((u8 *)(void *)(s))[1];\
 							   ((u8 *)(void *)(d))[3] = ((u8 *)(void *)(s))[0];}
 
-#define ACPI_MOVE_16_TO_64(d,s)         {(*(u64 *)(void *)(d))=0;\
+#define ACPI_MOVE_16_TO_64(d, s)        {(*(u64 *)(void *)(d))=0;\
 									 ((u8 *)(void *)(d))[6] = ((u8 *)(void *)(s))[1];\
 									 ((u8 *)(void *)(d))[7] = ((u8 *)(void *)(s))[0];}
 
 /* 32-bit source, 16/32/64 destination */
 
-#define ACPI_MOVE_32_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s)	/* Truncate to 16 */
+#define ACPI_MOVE_32_TO_16(d, s)        ACPI_MOVE_16_TO_16(d, s)	/* Truncate to 16 */
 
-#define ACPI_MOVE_32_TO_32(d,s)         {((  u8 *)(void *)(d))[0] = ((u8 *)(void *)(s))[3];\
+#define ACPI_MOVE_32_TO_32(d, s)        {((  u8 *)(void *)(d))[0] = ((u8 *)(void *)(s))[3];\
 										 ((  u8 *)(void *)(d))[1] = ((u8 *)(void *)(s))[2];\
 										 ((  u8 *)(void *)(d))[2] = ((u8 *)(void *)(s))[1];\
 										 ((  u8 *)(void *)(d))[3] = ((u8 *)(void *)(s))[0];}
 
-#define ACPI_MOVE_32_TO_64(d,s)         {(*(u64 *)(void *)(d))=0;\
+#define ACPI_MOVE_32_TO_64(d, s)        {(*(u64 *)(void *)(d))=0;\
 										   ((u8 *)(void *)(d))[4] = ((u8 *)(void *)(s))[3];\
 										   ((u8 *)(void *)(d))[5] = ((u8 *)(void *)(s))[2];\
 										   ((u8 *)(void *)(d))[6] = ((u8 *)(void *)(s))[1];\
@@ -170,11 +166,11 @@ struct acpi_integer_overlay {
 
 /* 64-bit source, 16/32/64 destination */
 
-#define ACPI_MOVE_64_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s)	/* Truncate to 16 */
+#define ACPI_MOVE_64_TO_16(d, s)        ACPI_MOVE_16_TO_16(d, s)	/* Truncate to 16 */
 
-#define ACPI_MOVE_64_TO_32(d,s)         ACPI_MOVE_32_TO_32(d,s)	/* Truncate to 32 */
+#define ACPI_MOVE_64_TO_32(d, s)        ACPI_MOVE_32_TO_32(d, s)	/* Truncate to 32 */
 
-#define ACPI_MOVE_64_TO_64(d,s)         {((  u8 *)(void *)(d))[0] = ((u8 *)(void *)(s))[7];\
+#define ACPI_MOVE_64_TO_64(d, s)        {((  u8 *)(void *)(d))[0] = ((u8 *)(void *)(s))[7];\
 										 ((  u8 *)(void *)(d))[1] = ((u8 *)(void *)(s))[6];\
 										 ((  u8 *)(void *)(d))[2] = ((u8 *)(void *)(s))[5];\
 										 ((  u8 *)(void *)(d))[3] = ((u8 *)(void *)(s))[4];\
@@ -187,63 +183,59 @@ struct acpi_integer_overlay {
  * Macros for little-endian machines
  */
 
-/* This macro sets a buffer index, starting from the beginning of the buffer */
-
-#define ACPI_BUFFER_INDEX(buf_len,buf_offset,byte_gran) (buf_offset)
-
 #ifndef ACPI_MISALIGNMENT_NOT_SUPPORTED
 
 /* The hardware supports unaligned transfers, just do the little-endian move */
 
 /* 16-bit source, 16/32/64 destination */
 
-#define ACPI_MOVE_16_TO_16(d,s)         *(u16 *)(void *)(d) = *(u16 *)(void *)(s)
-#define ACPI_MOVE_16_TO_32(d,s)         *(u32 *)(void *)(d) = *(u16 *)(void *)(s)
-#define ACPI_MOVE_16_TO_64(d,s)         *(u64 *)(void *)(d) = *(u16 *)(void *)(s)
+#define ACPI_MOVE_16_TO_16(d, s)        *(u16 *)(void *)(d) = *(u16 *)(void *)(s)
+#define ACPI_MOVE_16_TO_32(d, s)        *(u32 *)(void *)(d) = *(u16 *)(void *)(s)
+#define ACPI_MOVE_16_TO_64(d, s)        *(u64 *)(void *)(d) = *(u16 *)(void *)(s)
 
 /* 32-bit source, 16/32/64 destination */
 
-#define ACPI_MOVE_32_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s)	/* Truncate to 16 */
-#define ACPI_MOVE_32_TO_32(d,s)         *(u32 *)(void *)(d) = *(u32 *)(void *)(s)
-#define ACPI_MOVE_32_TO_64(d,s)         *(u64 *)(void *)(d) = *(u32 *)(void *)(s)
+#define ACPI_MOVE_32_TO_16(d, s)        ACPI_MOVE_16_TO_16(d, s)	/* Truncate to 16 */
+#define ACPI_MOVE_32_TO_32(d, s)        *(u32 *)(void *)(d) = *(u32 *)(void *)(s)
+#define ACPI_MOVE_32_TO_64(d, s)        *(u64 *)(void *)(d) = *(u32 *)(void *)(s)
 
 /* 64-bit source, 16/32/64 destination */
 
-#define ACPI_MOVE_64_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s)	/* Truncate to 16 */
-#define ACPI_MOVE_64_TO_32(d,s)         ACPI_MOVE_32_TO_32(d,s)	/* Truncate to 32 */
-#define ACPI_MOVE_64_TO_64(d,s)         *(u64 *)(void *)(d) = *(u64 *)(void *)(s)
+#define ACPI_MOVE_64_TO_16(d, s)        ACPI_MOVE_16_TO_16(d, s)	/* Truncate to 16 */
+#define ACPI_MOVE_64_TO_32(d, s)        ACPI_MOVE_32_TO_32(d, s)	/* Truncate to 32 */
+#define ACPI_MOVE_64_TO_64(d, s)        *(u64 *)(void *)(d) = *(u64 *)(void *)(s)
 
 #else
 /*
- * The hardware does not support unaligned transfers.  We must move the
- * data one byte at a time.  These macros work whether the source or
+ * The hardware does not support unaligned transfers. We must move the
+ * data one byte at a time. These macros work whether the source or
  * the destination (or both) is/are unaligned.  (Little-endian move)
  */
 
 /* 16-bit source, 16/32/64 destination */
 
-#define ACPI_MOVE_16_TO_16(d,s)         {((  u8 *)(void *)(d))[0] = ((u8 *)(void *)(s))[0];\
+#define ACPI_MOVE_16_TO_16(d, s)        {((  u8 *)(void *)(d))[0] = ((u8 *)(void *)(s))[0];\
 										 ((  u8 *)(void *)(d))[1] = ((u8 *)(void *)(s))[1];}
 
-#define ACPI_MOVE_16_TO_32(d,s)         {(*(u32 *)(void *)(d)) = 0; ACPI_MOVE_16_TO_16(d,s);}
-#define ACPI_MOVE_16_TO_64(d,s)         {(*(u64 *)(void *)(d)) = 0; ACPI_MOVE_16_TO_16(d,s);}
+#define ACPI_MOVE_16_TO_32(d, s)        {(*(u32 *)(void *)(d)) = 0; ACPI_MOVE_16_TO_16(d, s);}
+#define ACPI_MOVE_16_TO_64(d, s)        {(*(u64 *)(void *)(d)) = 0; ACPI_MOVE_16_TO_16(d, s);}
 
 /* 32-bit source, 16/32/64 destination */
 
-#define ACPI_MOVE_32_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s)	/* Truncate to 16 */
+#define ACPI_MOVE_32_TO_16(d, s)        ACPI_MOVE_16_TO_16(d, s)	/* Truncate to 16 */
 
-#define ACPI_MOVE_32_TO_32(d,s)         {((  u8 *)(void *)(d))[0] = ((u8 *)(void *)(s))[0];\
+#define ACPI_MOVE_32_TO_32(d, s)        {((  u8 *)(void *)(d))[0] = ((u8 *)(void *)(s))[0];\
 										 ((  u8 *)(void *)(d))[1] = ((u8 *)(void *)(s))[1];\
 										 ((  u8 *)(void *)(d))[2] = ((u8 *)(void *)(s))[2];\
 										 ((  u8 *)(void *)(d))[3] = ((u8 *)(void *)(s))[3];}
 
-#define ACPI_MOVE_32_TO_64(d,s)         {(*(u64 *)(void *)(d)) = 0; ACPI_MOVE_32_TO_32(d,s);}
+#define ACPI_MOVE_32_TO_64(d, s)        {(*(u64 *)(void *)(d)) = 0; ACPI_MOVE_32_TO_32(d, s);}
 
 /* 64-bit source, 16/32/64 destination */
 
-#define ACPI_MOVE_64_TO_16(d,s)         ACPI_MOVE_16_TO_16(d,s)	/* Truncate to 16 */
-#define ACPI_MOVE_64_TO_32(d,s)         ACPI_MOVE_32_TO_32(d,s)	/* Truncate to 32 */
-#define ACPI_MOVE_64_TO_64(d,s)         {((  u8 *)(void *)(d))[0] = ((u8 *)(void *)(s))[0];\
+#define ACPI_MOVE_64_TO_16(d, s)        ACPI_MOVE_16_TO_16(d, s)	/* Truncate to 16 */
+#define ACPI_MOVE_64_TO_32(d, s)        ACPI_MOVE_32_TO_32(d, s)	/* Truncate to 32 */
+#define ACPI_MOVE_64_TO_64(d, s)        {((  u8 *)(void *)(d))[0] = ((u8 *)(void *)(s))[0];\
 										 ((  u8 *)(void *)(d))[1] = ((u8 *)(void *)(s))[1];\
 										 ((  u8 *)(void *)(d))[2] = ((u8 *)(void *)(s))[2];\
 										 ((  u8 *)(void *)(d))[3] = ((u8 *)(void *)(s))[3];\
@@ -257,10 +249,10 @@ struct acpi_integer_overlay {
 /* Macros based on machine integer width */
 
 #if ACPI_MACHINE_WIDTH == 32
-#define ACPI_MOVE_SIZE_TO_16(d,s)       ACPI_MOVE_32_TO_16(d,s)
+#define ACPI_MOVE_SIZE_TO_16(d, s)       ACPI_MOVE_32_TO_16(d, s)
 
 #elif ACPI_MACHINE_WIDTH == 64
-#define ACPI_MOVE_SIZE_TO_16(d,s)       ACPI_MOVE_64_TO_16(d,s)
+#define ACPI_MOVE_SIZE_TO_16(d, s)       ACPI_MOVE_64_TO_16(d, s)
 
 #else
 #error unknown ACPI_MACHINE_WIDTH
@@ -269,29 +261,29 @@ struct acpi_integer_overlay {
 /*
  * Fast power-of-two math macros for non-optimized compilers
  */
-#define _ACPI_DIV(value,power_of2)      ((u32) ((value) >> (power_of2)))
-#define _ACPI_MUL(value,power_of2)      ((u32) ((value) << (power_of2)))
-#define _ACPI_MOD(value,divisor)        ((u32) ((value) & ((divisor) -1)))
+#define _ACPI_DIV(value, power_of2)      ((u32) ((value) >> (power_of2)))
+#define _ACPI_MUL(value, power_of2)      ((u32) ((value) << (power_of2)))
+#define _ACPI_MOD(value, divisor)        ((u32) ((value) & ((divisor) -1)))
 
-#define ACPI_DIV_2(a)                   _ACPI_DIV(a,1)
-#define ACPI_MUL_2(a)                   _ACPI_MUL(a,1)
-#define ACPI_MOD_2(a)                   _ACPI_MOD(a,2)
+#define ACPI_DIV_2(a)                   _ACPI_DIV(a, 1)
+#define ACPI_MUL_2(a)                   _ACPI_MUL(a, 1)
+#define ACPI_MOD_2(a)                   _ACPI_MOD(a, 2)
 
-#define ACPI_DIV_4(a)                   _ACPI_DIV(a,2)
-#define ACPI_MUL_4(a)                   _ACPI_MUL(a,2)
-#define ACPI_MOD_4(a)                   _ACPI_MOD(a,4)
+#define ACPI_DIV_4(a)                   _ACPI_DIV(a, 2)
+#define ACPI_MUL_4(a)                   _ACPI_MUL(a, 2)
+#define ACPI_MOD_4(a)                   _ACPI_MOD(a, 4)
 
-#define ACPI_DIV_8(a)                   _ACPI_DIV(a,3)
-#define ACPI_MUL_8(a)                   _ACPI_MUL(a,3)
-#define ACPI_MOD_8(a)                   _ACPI_MOD(a,8)
+#define ACPI_DIV_8(a)                   _ACPI_DIV(a, 3)
+#define ACPI_MUL_8(a)                   _ACPI_MUL(a, 3)
+#define ACPI_MOD_8(a)                   _ACPI_MOD(a, 8)
 
-#define ACPI_DIV_16(a)                  _ACPI_DIV(a,4)
-#define ACPI_MUL_16(a)                  _ACPI_MUL(a,4)
-#define ACPI_MOD_16(a)                  _ACPI_MOD(a,16)
+#define ACPI_DIV_16(a)                  _ACPI_DIV(a, 4)
+#define ACPI_MUL_16(a)                  _ACPI_MUL(a, 4)
+#define ACPI_MOD_16(a)                  _ACPI_MOD(a, 16)
 
-#define ACPI_DIV_32(a)                  _ACPI_DIV(a,5)
-#define ACPI_MUL_32(a)                  _ACPI_MUL(a,5)
-#define ACPI_MOD_32(a)                  _ACPI_MOD(a,32)
+#define ACPI_DIV_32(a)                  _ACPI_DIV(a, 5)
+#define ACPI_MUL_32(a)                  _ACPI_MUL(a, 5)
+#define ACPI_MOD_32(a)                  _ACPI_MOD(a, 32)
 
 /*
  * Rounding macros (Power of two boundaries only)
@@ -305,13 +297,13 @@ struct acpi_integer_overlay {
 
 /* Note: sizeof(acpi_size) evaluates to either 4 or 8 (32- vs 64-bit mode) */
 
-#define ACPI_ROUND_DOWN_TO_32BIT(a)         ACPI_ROUND_DOWN(a,4)
-#define ACPI_ROUND_DOWN_TO_64BIT(a)         ACPI_ROUND_DOWN(a,8)
-#define ACPI_ROUND_DOWN_TO_NATIVE_WORD(a)   ACPI_ROUND_DOWN(a,sizeof(acpi_size))
+#define ACPI_ROUND_DOWN_TO_32BIT(a)         ACPI_ROUND_DOWN(a, 4)
+#define ACPI_ROUND_DOWN_TO_64BIT(a)         ACPI_ROUND_DOWN(a, 8)
+#define ACPI_ROUND_DOWN_TO_NATIVE_WORD(a)   ACPI_ROUND_DOWN(a, sizeof(acpi_size))
 
-#define ACPI_ROUND_UP_TO_32BIT(a)           ACPI_ROUND_UP(a,4)
-#define ACPI_ROUND_UP_TO_64BIT(a)           ACPI_ROUND_UP(a,8)
-#define ACPI_ROUND_UP_TO_NATIVE_WORD(a)     ACPI_ROUND_UP(a,sizeof(acpi_size))
+#define ACPI_ROUND_UP_TO_32BIT(a)           ACPI_ROUND_UP(a, 4)
+#define ACPI_ROUND_UP_TO_64BIT(a)           ACPI_ROUND_UP(a, 8)
+#define ACPI_ROUND_UP_TO_NATIVE_WORD(a)     ACPI_ROUND_UP(a, sizeof(acpi_size))
 
 #define ACPI_ROUND_BITS_UP_TO_BYTES(a)      ACPI_DIV_8((a) + 7)
 #define ACPI_ROUND_BITS_DOWN_TO_BYTES(a)    ACPI_DIV_8((a))
@@ -320,9 +312,9 @@ struct acpi_integer_overlay {
 
 /* Generic (non-power-of-two) rounding */
 
-#define ACPI_ROUND_UP_TO(value,boundary)    (((value) + ((boundary)-1)) / (boundary))
+#define ACPI_ROUND_UP_TO(value, boundary)   (((value) + ((boundary)-1)) / (boundary))
 
-#define ACPI_IS_MISALIGNED(value)	    (((acpi_size)value) & (sizeof(acpi_size)-1))
+#define ACPI_IS_MISALIGNED(value)	    (((acpi_size) value) & (sizeof(acpi_size)-1))
 
 /*
  * Bitmask creation
@@ -333,8 +325,6 @@ struct acpi_integer_overlay {
 #define ACPI_MASK_BITS_ABOVE(position)      (~((ACPI_INTEGER_MAX) << ((u32) (position))))
 #define ACPI_MASK_BITS_BELOW(position)      ((ACPI_INTEGER_MAX) << ((u32) (position)))
 
-#define ACPI_IS_OCTAL_DIGIT(d)              (((char)(d) >= '0') && ((char)(d) <= '7'))
-
 /* Bitfields within ACPI registers */
 
 #define ACPI_REGISTER_PREPARE_BITS(val, pos, mask)      ((val << pos) & mask)
@@ -342,39 +332,29 @@ struct acpi_integer_overlay {
 
 #define ACPI_INSERT_BITS(target, mask, source)          target = ((target & (~(mask))) | (source & mask))
 
-/* Generate a UUID */
-
-#define ACPI_INIT_UUID(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7) \
-	(a) & 0xFF, ((a) >> 8) & 0xFF, ((a) >> 16) & 0xFF, ((a) >> 24) & 0xFF, \
-	(b) & 0xFF, ((b) >> 8) & 0xFF, \
-	(c) & 0xFF, ((c) >> 8) & 0xFF, \
-	(d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7)
-
 /*
- * An struct acpi_namespace_node * can appear in some contexts,
- * where a pointer to an union acpi_operand_object    can also
- * appear.  This macro is used to distinguish them.
+ * An struct acpi_namespace_node can appear in some contexts
+ * where a pointer to an union acpi_operand_object can also
+ * appear. This macro is used to distinguish them.
  *
  * The "Descriptor" field is the first field in both structures.
  */
 #define ACPI_GET_DESCRIPTOR_TYPE(d)     (((union acpi_descriptor *)(void *)(d))->common.descriptor_type)
-#define ACPI_SET_DESCRIPTOR_TYPE(d,t)   (((union acpi_descriptor *)(void *)(d))->common.descriptor_type = t)
+#define ACPI_SET_DESCRIPTOR_TYPE(d, t)  (((union acpi_descriptor *)(void *)(d))->common.descriptor_type = t)
 
 /* Macro to test the object type */
 
 #define ACPI_GET_OBJECT_TYPE(d)         (((union acpi_operand_object *)(void *)(d))->common.type)
 
-/* Macro to check the table flags for SINGLE or MULTIPLE tables are allowed */
-
-#define ACPI_IS_SINGLE_TABLE(x)         (((x) & 0x01) == ACPI_TABLE_SINGLE ? 1 : 0)
-
 /*
  * Macros for the master AML opcode table
  */
-#if defined(ACPI_DISASSEMBLER) || defined (ACPI_DEBUG_OUTPUT)
-#define ACPI_OP(name,Pargs,Iargs,obj_type,class,type,flags)    {name,(u32)(Pargs),(u32)(Iargs),(u32)(flags),obj_type,class,type}
+#if defined (ACPI_DISASSEMBLER) || defined (ACPI_DEBUG_OUTPUT)
+#define ACPI_OP(name, Pargs, Iargs, obj_type, class, type, flags) \
+	{name, (u32)(Pargs), (u32)(Iargs), (u32)(flags), obj_type, class, type}
 #else
-#define ACPI_OP(name,Pargs,Iargs,obj_type,class,type,flags)    {(u32)(Pargs),(u32)(Iargs),(u32)(flags),obj_type,class,type}
+#define ACPI_OP(name, Pargs, Iargs, obj_type, class, type, flags) \
+	{(u32)(Pargs), (u32)(Iargs), (u32)(flags), obj_type, class, type}
 #endif
 
 #ifdef ACPI_DISASSEMBLER
@@ -392,18 +372,18 @@ struct acpi_integer_overlay {
 #define ARG_6(x)                        ((u32)(x) << (5 * ARG_TYPE_WIDTH))
 
 #define ARGI_LIST1(a)                   (ARG_1(a))
-#define ARGI_LIST2(a,b)                 (ARG_1(b)|ARG_2(a))
-#define ARGI_LIST3(a,b,c)               (ARG_1(c)|ARG_2(b)|ARG_3(a))
-#define ARGI_LIST4(a,b,c,d)             (ARG_1(d)|ARG_2(c)|ARG_3(b)|ARG_4(a))
-#define ARGI_LIST5(a,b,c,d,e)           (ARG_1(e)|ARG_2(d)|ARG_3(c)|ARG_4(b)|ARG_5(a))
-#define ARGI_LIST6(a,b,c,d,e,f)         (ARG_1(f)|ARG_2(e)|ARG_3(d)|ARG_4(c)|ARG_5(b)|ARG_6(a))
+#define ARGI_LIST2(a, b)                (ARG_1(b)|ARG_2(a))
+#define ARGI_LIST3(a, b, c)             (ARG_1(c)|ARG_2(b)|ARG_3(a))
+#define ARGI_LIST4(a, b, c, d)          (ARG_1(d)|ARG_2(c)|ARG_3(b)|ARG_4(a))
+#define ARGI_LIST5(a, b, c, d, e)       (ARG_1(e)|ARG_2(d)|ARG_3(c)|ARG_4(b)|ARG_5(a))
+#define ARGI_LIST6(a, b, c, d, e, f)    (ARG_1(f)|ARG_2(e)|ARG_3(d)|ARG_4(c)|ARG_5(b)|ARG_6(a))
 
 #define ARGP_LIST1(a)                   (ARG_1(a))
-#define ARGP_LIST2(a,b)                 (ARG_1(a)|ARG_2(b))
-#define ARGP_LIST3(a,b,c)               (ARG_1(a)|ARG_2(b)|ARG_3(c))
-#define ARGP_LIST4(a,b,c,d)             (ARG_1(a)|ARG_2(b)|ARG_3(c)|ARG_4(d))
-#define ARGP_LIST5(a,b,c,d,e)           (ARG_1(a)|ARG_2(b)|ARG_3(c)|ARG_4(d)|ARG_5(e))
-#define ARGP_LIST6(a,b,c,d,e,f)         (ARG_1(a)|ARG_2(b)|ARG_3(c)|ARG_4(d)|ARG_5(e)|ARG_6(f))
+#define ARGP_LIST2(a, b)                (ARG_1(a)|ARG_2(b))
+#define ARGP_LIST3(a, b, c)             (ARG_1(a)|ARG_2(b)|ARG_3(c))
+#define ARGP_LIST4(a, b, c, d)          (ARG_1(a)|ARG_2(b)|ARG_3(c)|ARG_4(d))
+#define ARGP_LIST5(a, b, c, d, e)       (ARG_1(a)|ARG_2(b)|ARG_3(c)|ARG_4(d)|ARG_5(e))
+#define ARGP_LIST6(a, b, c, d, e, f)    (ARG_1(a)|ARG_2(b)|ARG_3(c)|ARG_4(d)|ARG_5(e)|ARG_6(f))
 
 #define GET_CURRENT_ARG_TYPE(list)      (list & ((u32) 0x1F))
 #define INCREMENT_ARG_LIST(list)        (list >>= ((u32) ARG_TYPE_WIDTH))
@@ -434,8 +414,8 @@ struct acpi_integer_overlay {
 #define ACPI_WARNING(plist)             acpi_ut_warning plist
 #define ACPI_EXCEPTION(plist)           acpi_ut_exception plist
 #define ACPI_ERROR(plist)               acpi_ut_error plist
-#define ACPI_ERROR_NAMESPACE(s,e)       acpi_ns_report_error (AE_INFO, s, e);
-#define ACPI_ERROR_METHOD(s,n,p,e)      acpi_ns_report_method_error (AE_INFO, s, n, p, e);
+#define ACPI_ERROR_NAMESPACE(s, e)      acpi_ns_report_error (AE_INFO, s, e);
+#define ACPI_ERROR_METHOD(s, n, p, e)   acpi_ns_report_method_error (AE_INFO, s, n, p, e);
 
 #else
 
@@ -445,8 +425,8 @@ struct acpi_integer_overlay {
 #define ACPI_WARNING(plist)
 #define ACPI_EXCEPTION(plist)
 #define ACPI_ERROR(plist)
-#define ACPI_ERROR_NAMESPACE(s,e)
-#define ACPI_ERROR_METHOD(s,n,p,e)
+#define ACPI_ERROR_NAMESPACE(s, e)
+#define ACPI_ERROR_METHOD(s, n, p, e)
 #endif
 
 /*
@@ -467,7 +447,7 @@ struct acpi_integer_overlay {
 /*
  * If ACPI_GET_FUNCTION_NAME was not defined in the compiler-dependent header,
  * define it now. This is the case where there the compiler does not support
- * a __FUNCTION__ macro or equivalent.
+ * a __func__ macro or equivalent.
  */
 #ifndef ACPI_GET_FUNCTION_NAME
 #define ACPI_GET_FUNCTION_NAME          _acpi_function_name
@@ -475,12 +455,12 @@ struct acpi_integer_overlay {
  * The Name parameter should be the procedure name as a quoted string.
  * The function name is also used by the function exit macros below.
  * Note: (const char) is used to be compatible with the debug interfaces
- * and macros such as __FUNCTION__.
+ * and macros such as __func__.
  */
 #define ACPI_FUNCTION_NAME(name)	static const char _acpi_function_name[] = #name;
 
 #else
-/* Compiler supports __FUNCTION__ (or equivalent) -- Ignore this macro */
+/* Compiler supports __func__ (or equivalent) -- Ignore this macro */
 
 #define ACPI_FUNCTION_NAME(name)
 #endif
@@ -489,18 +469,18 @@ struct acpi_integer_overlay {
 
 #define ACPI_FUNCTION_TRACE(a)          ACPI_FUNCTION_NAME(a) \
 			  acpi_ut_trace(ACPI_DEBUG_PARAMETERS)
-#define ACPI_FUNCTION_TRACE_PTR(a,b)    ACPI_FUNCTION_NAME(a) \
-					   acpi_ut_trace_ptr(ACPI_DEBUG_PARAMETERS,(void *)b)
-#define ACPI_FUNCTION_TRACE_U32(a,b)    ACPI_FUNCTION_NAME(a) \
-							 acpi_ut_trace_u32(ACPI_DEBUG_PARAMETERS,(u32)b)
-#define ACPI_FUNCTION_TRACE_STR(a,b)    ACPI_FUNCTION_NAME(a) \
-									  acpi_ut_trace_str(ACPI_DEBUG_PARAMETERS,(char *)b)
+#define ACPI_FUNCTION_TRACE_PTR(a, b)   ACPI_FUNCTION_NAME(a) \
+					   acpi_ut_trace_ptr(ACPI_DEBUG_PARAMETERS, (void *)b)
+#define ACPI_FUNCTION_TRACE_U32(a, b)   ACPI_FUNCTION_NAME(a) \
+							 acpi_ut_trace_u32(ACPI_DEBUG_PARAMETERS, (u32)b)
+#define ACPI_FUNCTION_TRACE_STR(a, b)   ACPI_FUNCTION_NAME(a) \
+									  acpi_ut_trace_str(ACPI_DEBUG_PARAMETERS, (char *)b)
 
 #define ACPI_FUNCTION_ENTRY()           acpi_ut_track_stack_ptr()
 
 /*
  * Function exit tracing.
- * WARNING: These macros include a return statement.  This is usually considered
+ * WARNING: These macros include a return statement. This is usually considered
  * bad form, but having a separate exit macro is very ugly and difficult to maintain.
  * One of the FUNCTION_TRACE macros above must be used in conjunction with these macros
  * so that "_AcpiFunctionName" is defined.
@@ -596,13 +576,13 @@ struct acpi_integer_overlay {
 
 /* Stack and buffer dumping */
 
-#define ACPI_DUMP_STACK_ENTRY(a)        acpi_ex_dump_operand((a),0)
-#define ACPI_DUMP_OPERANDS(a,b,c)	acpi_ex_dump_operands(a,b,c)
+#define ACPI_DUMP_STACK_ENTRY(a)        acpi_ex_dump_operand((a), 0)
+#define ACPI_DUMP_OPERANDS(a, b, c)	acpi_ex_dump_operands(a, b, c)
 
-#define ACPI_DUMP_ENTRY(a,b)            acpi_ns_dump_entry (a,b)
-#define ACPI_DUMP_PATHNAME(a,b,c,d)     acpi_ns_dump_pathname(a,b,c,d)
+#define ACPI_DUMP_ENTRY(a, b)           acpi_ns_dump_entry (a, b)
+#define ACPI_DUMP_PATHNAME(a, b, c, d)  acpi_ns_dump_pathname(a, b, c, d)
 #define ACPI_DUMP_RESOURCE_LIST(a)      acpi_rs_dump_resource_list(a)
-#define ACPI_DUMP_BUFFER(a,b)           acpi_ut_dump_buffer((u8 *)a,b,DB_BYTE_DISPLAY,_COMPONENT)
+#define ACPI_DUMP_BUFFER(a, b)          acpi_ut_dump_buffer((u8 *) a, b, DB_BYTE_DISPLAY, _COMPONENT)
 
 /*
  * Master debug print macros
@@ -625,20 +605,20 @@ struct acpi_integer_overlay {
 #define ACPI_DEBUG_ONLY_MEMBERS(a)	do { } while(0)
 #define ACPI_FUNCTION_NAME(a)		do { } while(0)
 #define ACPI_FUNCTION_TRACE(a)		do { } while(0)
-#define ACPI_FUNCTION_TRACE_PTR(a,b)	do { } while(0)
-#define ACPI_FUNCTION_TRACE_U32(a,b)	do { } while(0)
-#define ACPI_FUNCTION_TRACE_STR(a,b)	do { } while(0)
+#define ACPI_FUNCTION_TRACE_PTR(a, b)	do { } while(0)
+#define ACPI_FUNCTION_TRACE_U32(a, b)	do { } while(0)
+#define ACPI_FUNCTION_TRACE_STR(a, b)	do { } while(0)
 #define ACPI_FUNCTION_EXIT		do { } while(0)
 #define ACPI_FUNCTION_STATUS_EXIT(s)	do { } while(0)
 #define ACPI_FUNCTION_VALUE_EXIT(s)	do { } while(0)
 #define ACPI_FUNCTION_ENTRY()		do { } while(0)
 #define ACPI_DUMP_STACK_ENTRY(a)	do { } while(0)
-#define ACPI_DUMP_OPERANDS(a,b,c)      do { } while(0)
-#define ACPI_DUMP_ENTRY(a,b)		do { } while(0)
-#define ACPI_DUMP_TABLES(a,b)		do { } while(0)
-#define ACPI_DUMP_PATHNAME(a,b,c,d)	do { } while(0)
+#define ACPI_DUMP_OPERANDS(a, b, c)     do { } while(0)
+#define ACPI_DUMP_ENTRY(a, b)		do { } while(0)
+#define ACPI_DUMP_TABLES(a, b)		do { } while(0)
+#define ACPI_DUMP_PATHNAME(a, b, c, d)	do { } while(0)
 #define ACPI_DUMP_RESOURCE_LIST(a)	do { } while(0)
-#define ACPI_DUMP_BUFFER(a,b)		do { } while(0)
+#define ACPI_DUMP_BUFFER(a, b)		do { } while(0)
 #define ACPI_DEBUG_PRINT(pl)		do { } while(0)
 #define ACPI_DEBUG_PRINT_RAW(pl)	do { } while(0)
 
@@ -677,15 +657,17 @@ struct acpi_integer_overlay {
 /*
  * Memory allocation tracking (DEBUG ONLY)
  */
+#define ACPI_MEM_PARAMETERS         _COMPONENT, _acpi_module_name, __LINE__
+
 #ifndef ACPI_DBG_TRACK_ALLOCATIONS
 
 /* Memory allocation */
 
 #ifndef ACPI_ALLOCATE
-#define ACPI_ALLOCATE(a)            acpi_ut_allocate((acpi_size)(a),_COMPONENT,_acpi_module_name,__LINE__)
+#define ACPI_ALLOCATE(a)            acpi_ut_allocate((acpi_size)(a), ACPI_MEM_PARAMETERS)
 #endif
 #ifndef ACPI_ALLOCATE_ZEROED
-#define ACPI_ALLOCATE_ZEROED(a)     acpi_ut_allocate_zeroed((acpi_size)(a), _COMPONENT,_acpi_module_name,__LINE__)
+#define ACPI_ALLOCATE_ZEROED(a)     acpi_ut_allocate_zeroed((acpi_size)(a), ACPI_MEM_PARAMETERS)
 #endif
 #ifndef ACPI_FREE
 #define ACPI_FREE(a)                acpio_os_free(a)
@@ -696,11 +678,16 @@ struct acpi_integer_overlay {
 
 /* Memory allocation */
 
-#define ACPI_ALLOCATE(a)            acpi_ut_allocate_and_track((acpi_size)(a),_COMPONENT,_acpi_module_name,__LINE__)
-#define ACPI_ALLOCATE_ZEROED(a)     acpi_ut_allocate_zeroed_and_track((acpi_size)(a), _COMPONENT,_acpi_module_name,__LINE__)
-#define ACPI_FREE(a)                acpi_ut_free_and_track(a,_COMPONENT,_acpi_module_name,__LINE__)
+#define ACPI_ALLOCATE(a)            acpi_ut_allocate_and_track((acpi_size)(a), ACPI_MEM_PARAMETERS)
+#define ACPI_ALLOCATE_ZEROED(a)     acpi_ut_allocate_zeroed_and_track((acpi_size)(a), ACPI_MEM_PARAMETERS)
+#define ACPI_FREE(a)                acpi_ut_free_and_track(a, ACPI_MEM_PARAMETERS)
 #define ACPI_MEM_TRACKING(a)        a
 
 #endif				/* ACPI_DBG_TRACK_ALLOCATIONS */
 
+/* Preemption point */
+#ifndef ACPI_PREEMPTION_POINT
+#define ACPI_PREEMPTION_POINT() /* no preemption */
+#endif
+
 #endif				/* ACMACROS_H */
diff --git a/include/acpi/acnamesp.h b/include/acpi/acnamesp.h
index c34008507b69..db4e6f677855 100644
--- a/include/acpi/acnamesp.h
+++ b/include/acpi/acnamesp.h
@@ -178,6 +178,22 @@ acpi_ns_dump_objects(acpi_object_type type,
 acpi_status acpi_ns_evaluate(struct acpi_evaluate_info *info);
 
 /*
+ * nspredef - Support for predefined/reserved names
+ */
+acpi_status
+acpi_ns_check_predefined_names(struct acpi_namespace_node *node,
+			       union acpi_operand_object *return_object);
+
+const union acpi_predefined_info *acpi_ns_check_for_predefined_name(struct
+								    acpi_namespace_node
+								    *node);
+
+void
+acpi_ns_check_parameter_count(char *pathname,
+			      struct acpi_namespace_node *node,
+			      const union acpi_predefined_info *info);
+
+/*
  * nsnames - Name and Scope manipulation
  */
 u32 acpi_ns_opens_scope(acpi_object_type type);
diff --git a/include/acpi/acobject.h b/include/acpi/acobject.h
index e9657dac69b7..eb6f038b03d9 100644
--- a/include/acpi/acobject.h
+++ b/include/acpi/acobject.h
@@ -308,18 +308,34 @@ struct acpi_object_addr_handler {
  *****************************************************************************/
 
 /*
- * The Reference object type is used for these opcodes:
- * Arg[0-6], Local[0-7], index_op, name_op, zero_op, one_op, ones_op, debug_op
+ * The Reference object is used for these opcodes:
+ * Arg[0-6], Local[0-7], index_op, name_op, ref_of_op, load_op, load_table_op, debug_op
+ * The Reference.Class differentiates these types.
  */
 struct acpi_object_reference {
-	ACPI_OBJECT_COMMON_HEADER u8 target_type;	/* Used for index_op */
-	u16 opcode;
+	ACPI_OBJECT_COMMON_HEADER u8 class;	/* Reference Class */
+	u8 target_type;		/* Used for Index Op */
+	u8 reserved;
 	void *object;		/* name_op=>HANDLE to obj, index_op=>union acpi_operand_object */
-	struct acpi_namespace_node *node;
-	union acpi_operand_object **where;
-	u32 offset;		/* Used for arg_op, local_op, and index_op */
+	struct acpi_namespace_node *node;	/* ref_of or Namepath */
+	union acpi_operand_object **where;	/* Target of Index */
+	u32 value;		/* Used for Local/Arg/Index/ddb_handle */
 };
 
+/* Values for Reference.Class above */
+
+typedef enum {
+	ACPI_REFCLASS_LOCAL = 0,	/* Method local */
+	ACPI_REFCLASS_ARG = 1,	/* Method argument */
+	ACPI_REFCLASS_REFOF = 2,	/* Result of ref_of() TBD: Split to Ref/Node and Ref/operand_obj? */
+	ACPI_REFCLASS_INDEX = 3,	/* Result of Index() */
+	ACPI_REFCLASS_TABLE = 4,	/* ddb_handle - Load(), load_table() */
+	ACPI_REFCLASS_NAME = 5,	/* Reference to a named object */
+	ACPI_REFCLASS_DEBUG = 6,	/* Debug object */
+
+	ACPI_REFCLASS_MAX = 6
+} ACPI_REFERENCE_CLASSES;
+
 /*
  * Extra object is used as additional storage for types that
  * have AML code in their declarations (term_args) that must be
@@ -379,6 +395,13 @@ union acpi_operand_object {
 	struct acpi_object_extra extra;
 	struct acpi_object_data data;
 	struct acpi_object_cache_list cache;
+
+	/*
+	 * Add namespace node to union in order to simplify code that accepts both
+	 * ACPI_OPERAND_OBJECTs and ACPI_NAMESPACE_NODEs. The structures share
+	 * a common descriptor_type field in order to differentiate them.
+	 */
+	struct acpi_namespace_node node;
 };
 
 /******************************************************************************
diff --git a/include/acpi/acoutput.h b/include/acpi/acoutput.h
index e17873defcec..db8852d8bcf7 100644
--- a/include/acpi/acoutput.h
+++ b/include/acpi/acoutput.h
@@ -80,12 +80,10 @@
 /*
  * Raw debug output levels, do not use these in the DEBUG_PRINT macros
  */
-#define ACPI_LV_ERROR               0x00000001
-#define ACPI_LV_WARN                0x00000002
-#define ACPI_LV_INIT                0x00000004
-#define ACPI_LV_DEBUG_OBJECT        0x00000008
-#define ACPI_LV_INFO                0x00000010
-#define ACPI_LV_ALL_EXCEPTIONS      0x0000001F
+#define ACPI_LV_INIT                0x00000001
+#define ACPI_LV_DEBUG_OBJECT        0x00000002
+#define ACPI_LV_INFO                0x00000004
+#define ACPI_LV_ALL_EXCEPTIONS      0x00000007
 
 /* Trace verbosity level 1 [Standard Trace Level] */
 
@@ -127,7 +125,6 @@
 #define ACPI_LV_VERBOSE_INFO        0x20000000
 #define ACPI_LV_FULL_TABLES         0x40000000
 #define ACPI_LV_EVENTS              0x80000000
-
 #define ACPI_LV_VERBOSE             0xF0000000
 
 /*
@@ -135,21 +132,17 @@
  */
 #define ACPI_DEBUG_LEVEL(dl)        (u32) dl,ACPI_DEBUG_PARAMETERS
 
-/* Exception level -- used in the global "DebugLevel" */
-
+/*
+ * Exception level -- used in the global "DebugLevel"
+ *
+ * Note: For errors, use the ACPI_ERROR or ACPI_EXCEPTION interfaces.
+ * For warnings, use ACPI_WARNING.
+ */
 #define ACPI_DB_INIT                ACPI_DEBUG_LEVEL (ACPI_LV_INIT)
 #define ACPI_DB_DEBUG_OBJECT        ACPI_DEBUG_LEVEL (ACPI_LV_DEBUG_OBJECT)
 #define ACPI_DB_INFO                ACPI_DEBUG_LEVEL (ACPI_LV_INFO)
 #define ACPI_DB_ALL_EXCEPTIONS      ACPI_DEBUG_LEVEL (ACPI_LV_ALL_EXCEPTIONS)
 
-/*
- * These two levels are essentially obsolete, all instances in the
- * ACPICA core code have been replaced by ACPI_ERROR and ACPI_WARNING
- * (Kept here because some drivers may still use them)
- */
-#define ACPI_DB_ERROR               ACPI_DEBUG_LEVEL (ACPI_LV_ERROR)
-#define ACPI_DB_WARN                ACPI_DEBUG_LEVEL (ACPI_LV_WARN)
-
 /* Trace level -- also used in the global "DebugLevel" */
 
 #define ACPI_DB_INIT_NAMES          ACPI_DEBUG_LEVEL (ACPI_LV_INIT_NAMES)
@@ -173,13 +166,14 @@
 #define ACPI_DB_USER_REQUESTS       ACPI_DEBUG_LEVEL (ACPI_LV_USER_REQUESTS)
 #define ACPI_DB_PACKAGE             ACPI_DEBUG_LEVEL (ACPI_LV_PACKAGE)
 #define ACPI_DB_MUTEX               ACPI_DEBUG_LEVEL (ACPI_LV_MUTEX)
+#define ACPI_DB_EVENTS              ACPI_DEBUG_LEVEL (ACPI_LV_EVENTS)
 
 #define ACPI_DB_ALL                 ACPI_DEBUG_LEVEL (ACPI_LV_ALL)
 
 /* Defaults for debug_level, debug and normal */
 
-#define ACPI_DEBUG_DEFAULT          (ACPI_LV_INIT | ACPI_LV_WARN | ACPI_LV_ERROR)
-#define ACPI_NORMAL_DEFAULT         (ACPI_LV_INIT | ACPI_LV_WARN | ACPI_LV_ERROR)
+#define ACPI_DEBUG_DEFAULT          (ACPI_LV_INFO)
+#define ACPI_NORMAL_DEFAULT         (ACPI_LV_INIT | ACPI_LV_DEBUG_OBJECT)
 #define ACPI_DEBUG_ALL              (ACPI_LV_AML_DISASSEMBLE | ACPI_LV_ALL_EXCEPTIONS | ACPI_LV_ALL)
 
 #endif				/* __ACOUTPUT_H__ */
diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h
index a5ac0bc7f52e..e9f6574930ef 100644
--- a/include/acpi/acpi_bus.h
+++ b/include/acpi/acpi_bus.h
@@ -46,7 +46,7 @@ acpi_extract_package(union acpi_object *package,
 acpi_status
 acpi_evaluate_integer(acpi_handle handle,
 		      acpi_string pathname,
-		      struct acpi_object_list *arguments, unsigned long *data);
+		      struct acpi_object_list *arguments, unsigned long long *data);
 acpi_status
 acpi_evaluate_reference(acpi_handle handle,
 			acpi_string pathname,
@@ -300,7 +300,11 @@ struct acpi_device {
 	enum acpi_bus_removal_type removal_type;	/* indicate for different removal type */
 };
 
-#define acpi_driver_data(d)	((d)->driver_data)
+static inline void *acpi_driver_data(struct acpi_device *d)
+{
+	return d->driver_data;
+}
+
 #define to_acpi_device(d)	container_of(d, struct acpi_device, dev)
 #define to_acpi_driver(d)	container_of(d, struct acpi_driver, drv)
 
@@ -327,6 +331,9 @@ int acpi_bus_get_private_data(acpi_handle, void **);
 extern int acpi_notifier_call_chain(struct acpi_device *, u32, u32);
 extern int register_acpi_notifier(struct notifier_block *);
 extern int unregister_acpi_notifier(struct notifier_block *);
+
+extern int register_acpi_bus_notifier(struct notifier_block *nb);
+extern void unregister_acpi_bus_notifier(struct notifier_block *nb);
 /*
  * External Functions
  */
@@ -373,6 +380,8 @@ struct acpi_bus_type {
 int register_acpi_bus_type(struct acpi_bus_type *);
 int unregister_acpi_bus_type(struct acpi_bus_type *);
 struct device *acpi_get_physical_device(acpi_handle);
+struct device *acpi_get_physical_pci_device(acpi_handle);
+
 /* helper */
 acpi_handle acpi_get_child(acpi_handle, acpi_integer);
 acpi_handle acpi_get_pci_rootbridge_handle(unsigned int, unsigned int);
diff --git a/include/acpi/acpi_drivers.h b/include/acpi/acpi_drivers.h
index e5f38e5ce86f..5fc1bb0f4a90 100644
--- a/include/acpi/acpi_drivers.h
+++ b/include/acpi/acpi_drivers.h
@@ -31,8 +31,24 @@
 
 #define ACPI_MAX_STRING			80
 
+/*
+ * Please update drivers/acpi/debug.c and Documentation/acpi/debug.txt
+ * if you add to this list.
+ */
 #define ACPI_BUS_COMPONENT		0x00010000
+#define ACPI_AC_COMPONENT		0x00020000
+#define ACPI_BATTERY_COMPONENT		0x00040000
+#define ACPI_BUTTON_COMPONENT		0x00080000
+#define ACPI_SBS_COMPONENT		0x00100000
+#define ACPI_FAN_COMPONENT		0x00200000
+#define ACPI_PCI_COMPONENT		0x00400000
+#define ACPI_POWER_COMPONENT		0x00800000
+#define ACPI_CONTAINER_COMPONENT	0x01000000
 #define ACPI_SYSTEM_COMPONENT		0x02000000
+#define ACPI_THERMAL_COMPONENT		0x04000000
+#define ACPI_MEMORY_DEVICE_COMPONENT	0x08000000
+#define ACPI_VIDEO_COMPONENT		0x10000000
+#define ACPI_PROCESSOR_COMPONENT	0x20000000
 
 /*
  * _HID definitions
@@ -41,6 +57,7 @@
  */
 
 #define ACPI_POWER_HID			"LNXPOWER"
+#define ACPI_PROCESSOR_OBJECT_HID	"ACPI_CPU"
 #define ACPI_PROCESSOR_HID		"ACPI0007"
 #define ACPI_SYSTEM_HID			"LNXSYSTM"
 #define ACPI_THERMAL_HID		"LNXTHERM"
@@ -54,7 +71,6 @@
                                        PCI
    -------------------------------------------------------------------------- */
 
-#define ACPI_PCI_COMPONENT		0x00400000
 
 /* ACPI PCI Interrupt Link (pci_link.c) */
 
@@ -86,21 +102,19 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_device *device, int domain,
                                   Power Resource
    -------------------------------------------------------------------------- */
 
-#ifdef CONFIG_ACPI_POWER
 int acpi_device_sleep_wake(struct acpi_device *dev,
                            int enable, int sleep_state, int dev_state);
 int acpi_enable_wakeup_device_power(struct acpi_device *dev, int sleep_state);
 int acpi_disable_wakeup_device_power(struct acpi_device *dev);
 int acpi_power_get_inferred_state(struct acpi_device *device);
 int acpi_power_transition(struct acpi_device *device, int state);
-#endif
+extern int acpi_power_nocheck;
 
 /* --------------------------------------------------------------------------
                                   Embedded Controller
    -------------------------------------------------------------------------- */
-#ifdef CONFIG_ACPI_EC
 int acpi_ec_ecdt_probe(void);
-#endif
+int acpi_boot_ec_enable(void);
 
 /* --------------------------------------------------------------------------
                                     Processor
@@ -115,12 +129,17 @@ int acpi_processor_set_thermal_limit(acpi_handle handle, int type);
 /*--------------------------------------------------------------------------
                                   Dock Station
   -------------------------------------------------------------------------- */
+struct acpi_dock_ops {
+	acpi_notify_handler handler;
+	acpi_notify_handler uevent;
+};
+
 #if defined(CONFIG_ACPI_DOCK) || defined(CONFIG_ACPI_DOCK_MODULE)
 extern int is_dock_device(acpi_handle handle);
 extern int register_dock_notifier(struct notifier_block *nb);
 extern void unregister_dock_notifier(struct notifier_block *nb);
 extern int register_hotplug_dock_device(acpi_handle handle,
-					acpi_notify_handler handler,
+					struct acpi_dock_ops *ops,
 					void *context);
 extern void unregister_hotplug_dock_device(acpi_handle handle);
 #else
@@ -136,7 +155,7 @@ static inline void unregister_dock_notifier(struct notifier_block *nb)
 {
 }
 static inline int register_hotplug_dock_device(acpi_handle handle,
-					       acpi_notify_handler handler,
+					       struct acpi_dock_ops *ops,
 					       void *context)
 {
 	return -ENODEV;
diff --git a/include/acpi/acpiosxf.h b/include/acpi/acpiosxf.h
index 3f93a6b4e17f..b91440ac0d16 100644
--- a/include/acpi/acpiosxf.h
+++ b/include/acpi/acpiosxf.h
@@ -193,6 +193,9 @@ acpi_status
 acpi_os_execute(acpi_execute_type type,
 		acpi_osd_exec_callback function, void *context);
 
+acpi_status
+acpi_os_hotplug_execute(acpi_osd_exec_callback function, void *context);
+
 void acpi_os_wait_events_complete(void *context);
 
 void acpi_os_sleep(acpi_integer milliseconds);
diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h
index 94d94e126e9f..33bc0e3b1954 100644
--- a/include/acpi/acpixf.h
+++ b/include/acpi/acpixf.h
@@ -252,9 +252,9 @@ acpi_status acpi_get_event_status(u32 event, acpi_event_status * event_status);
 
 acpi_status acpi_set_gpe_type(acpi_handle gpe_device, u32 gpe_number, u8 type);
 
-acpi_status acpi_enable_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags);
+acpi_status acpi_enable_gpe(acpi_handle gpe_device, u32 gpe_number);
 
-acpi_status acpi_disable_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags);
+acpi_status acpi_disable_gpe(acpi_handle gpe_device, u32 gpe_number);
 
 acpi_status acpi_clear_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags);
 
diff --git a/include/acpi/acpredef.h b/include/acpi/acpredef.h
new file mode 100644
index 000000000000..16a9ca9a66e4
--- /dev/null
+++ b/include/acpi/acpredef.h
@@ -0,0 +1,371 @@
+/******************************************************************************
+ *
+ * Name: acpredef - Information table for ACPI predefined methods and objects
+ *              $Revision: 1.1 $
+ *
+ *****************************************************************************/
+
+/*
+ * Copyright (C) 2000 - 2008, Intel Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    substantially similar to the "NO WARRANTY" disclaimer below
+ *    ("Disclaimer") and any redistribution must be conditioned upon
+ *    including a substantially similar Disclaimer requirement for further
+ *    binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ *    of any contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGES.
+ */
+
+#ifndef __ACPREDEF_H__
+#define __ACPREDEF_H__
+
+/******************************************************************************
+ *
+ * Return Package types
+ *
+ * 1) PTYPE1 packages do not contain sub-packages.
+ *
+ * ACPI_PTYPE1_FIXED: Fixed length, 1 or 2 object types:
+ *     object type
+ *     count
+ *     object type
+ *     count
+ *
+ * ACPI_PTYPE1_VAR: Variable length:
+ *    object type (Int/Buf/Ref)
+ *
+ * ACPI_PTYPE1_OPTION: Package has some required and some optional elements:
+ *      Used for _PRW
+ *
+ *
+ * 2) PTYPE2 packages contain a variable number of sub-packages. Each of the
+ *    different types describe the contents of each of the sub-packages.
+ *
+ * ACPI_PTYPE2: Each subpackage contains 1 or 2 object types:
+ *     object type
+ *     count
+ *     object type
+ *     count
+ *
+ * ACPI_PTYPE2_COUNT: Each subpackage has a count as first element:
+ *     object type
+ *
+ * ACPI_PTYPE2_PKG_COUNT: Count of subpackages at start, 1 or 2 object types:
+ *     object type
+ *     count
+ *     object type
+ *     count
+ *
+ * ACPI_PTYPE2_FIXED: Each subpackage is of fixed length:
+ *      Used for _PRT
+ *
+ * ACPI_PTYPE2_MIN: Each subpackage has a variable but minimum length
+ *      Used for _HPX
+ *
+ *****************************************************************************/
+
+enum acpi_return_package_types {
+	ACPI_PTYPE1_FIXED = 1,
+	ACPI_PTYPE1_VAR = 2,
+	ACPI_PTYPE1_OPTION = 3,
+	ACPI_PTYPE2 = 4,
+	ACPI_PTYPE2_COUNT = 5,
+	ACPI_PTYPE2_PKG_COUNT = 6,
+	ACPI_PTYPE2_FIXED = 7,
+	ACPI_PTYPE2_MIN = 8
+};
+
+/*
+ * Predefined method/object information table.
+ *
+ * These are the names that can actually be evaluated via acpi_evaluate_object.
+ * Not present in this table are the following:
+ *
+ *      1) Predefined/Reserved names that are never evaluated via acpi_evaluate_object:
+ *          _Lxx and _Exx GPE methods
+ *          _Qxx EC methods
+ *          _T_x compiler temporary variables
+ *
+ *      2) Predefined names that never actually exist within the AML code:
+ *          Predefined resource descriptor field names
+ *
+ *      3) Predefined names that are implemented within ACPICA:
+ *          _OSI
+ *
+ *      4) Some predefined names that are not documented within the ACPI spec.
+ *          _WDG, _WED
+ *
+ * The main entries in the table each contain the following items:
+ *
+ * Name                 - The ACPI reserved name
+ * param_count          - Number of arguments to the method
+ * expected_btypes      - Allowed type(s) for the return value.
+ *                        0 means that no return value is expected.
+ *
+ * For methods that return packages, the next entry in the table contains
+ * information about the expected structure of the package. This information
+ * is saved here (rather than in a separate table) in order to minimize the
+ * overall size of the stored data.
+ */
+static const union acpi_predefined_info predefined_names[] = {
+	{.info = {"_AC0", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_AC1", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_AC2", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_AC3", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_AC4", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_AC5", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_AC6", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_AC7", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_AC8", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_AC9", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_ADR", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_AL0", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}},	/* variable (Refs) */
+	{.info = {"_AL1", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}},	/* variable (Refs) */
+	{.info = {"_AL2", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}},	/* variable (Refs) */
+	{.info = {"_AL3", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}},	/* variable (Refs) */
+	{.info = {"_AL4", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}},	/* variable (Refs) */
+	{.info = {"_AL5", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}},	/* variable (Refs) */
+	{.info = {"_AL6", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}},	/* variable (Refs) */
+	{.info = {"_AL7", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}},	/* variable (Refs) */
+	{.info = {"_AL8", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}},	/* variable (Refs) */
+	{.info = {"_AL9", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}},	/* variable (Refs) */
+	{.info = {"_ALC", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_ALI", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_ALP", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_ALR", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2, ACPI_RTYPE_INTEGER, 2, 0, 0, 0}},	/* variable (Pkgs) each 2 (Ints) */
+	{.info = {"_ALT", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_BBN", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_BCL", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 0, 0, 0, 0}},	/* variable (Ints) */
+	{.info = {"_BCM", 1, 0}},
+	{.info = {"_BDN", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_BFS", 1, 0}},
+	{.info = {"_BIF", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER,
+					  9,
+					  ACPI_RTYPE_STRING | ACPI_RTYPE_BUFFER, 4, 0}},	/* fixed (9 Int),(4 Str) */
+	{.info = {"_BLT", 3, 0}},
+	{.info = {"_BMC", 1, 0}},
+	{.info = {"_BMD", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 5, 0, 0, 0}},	/* fixed (5 Int) */
+	{.info = {"_BQC", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_BST", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 4, 0, 0, 0}},	/* fixed (4 Int) */
+	{.info = {"_BTM", 1, ACPI_RTYPE_INTEGER}},
+	{.info = {"_BTP", 1, 0}},
+	{.info = {"_CBA", 0, ACPI_RTYPE_INTEGER}},	/* see PCI firmware spec 3.0 */
+	{.info = {"_CID", 0,
+	 ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING | ACPI_RTYPE_PACKAGE}},
+	{.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING, 0, 0, 0, 0}},	/* variable (Ints/Strs) */
+	{.info = {"_CRS", 0, ACPI_RTYPE_BUFFER}},
+	{.info = {"_CRT", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_CSD", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2_COUNT, ACPI_RTYPE_INTEGER, 0, 0, 0, 0}},	/* variable (1 Int(n), n-1 Int) */
+	{.info = {"_CST", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2_PKG_COUNT,
+					  ACPI_RTYPE_BUFFER, 1,
+					  ACPI_RTYPE_INTEGER, 3, 0}},	/* variable (1 Int(n), n Pkg (1 Buf/3 Int) */
+	{.info = {"_DCK", 1, ACPI_RTYPE_INTEGER}},
+	{.info = {"_DCS", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_DDC", 1, ACPI_RTYPE_INTEGER | ACPI_RTYPE_BUFFER}},
+	{.info = {"_DDN", 0, ACPI_RTYPE_STRING}},
+	{.info = {"_DGS", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_DIS", 0, 0}},
+	{.info = {"_DMA", 0, ACPI_RTYPE_BUFFER}},
+	{.info = {"_DOD", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 0, 0, 0, 0}},	/* variable (Ints) */
+	{.info = {"_DOS", 1, 0}},
+	{.info = {"_DSM", 4, ACPI_RTYPE_ALL}},	/* Must return a type, but it can be of any type */
+	{.info = {"_DSS", 1, 0}},
+	{.info = {"_DSW", 3, 0}},
+	{.info = {"_EC_", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_EDL", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}},	/* variable (Refs) */
+	{.info = {"_EJ0", 1, 0}},
+	{.info = {"_EJ1", 1, 0}},
+	{.info = {"_EJ2", 1, 0}},
+	{.info = {"_EJ3", 1, 0}},
+	{.info = {"_EJ4", 1, 0}},
+	{.info = {"_EJD", 0, ACPI_RTYPE_STRING}},
+	{.info = {"_FDE", 0, ACPI_RTYPE_BUFFER}},
+	{.info = {"_FDI", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 16, 0, 0, 0}},	/* fixed (16 Int) */
+	{.info = {"_FDM", 1, 0}},
+	{.info = {"_FIX", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 0, 0, 0, 0}},	/* variable (Ints) */
+	{.info = {"_GLK", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_GPD", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_GPE", 0, ACPI_RTYPE_INTEGER}},	/* _GPE method, not _GPE scope */
+	{.info = {"_GSB", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_GTF", 0, ACPI_RTYPE_BUFFER}},
+	{.info = {"_GTM", 0, ACPI_RTYPE_BUFFER}},
+	{.info = {"_GTS", 1, 0}},
+	{.info = {"_HID", 0, ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING}},
+	{.info = {"_HOT", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_HPP", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 4, 0, 0, 0}},	/* fixed (4 Int) */
+
+	/*
+	 * For _HPX, a single package is returned, containing a variable number of sub-packages.
+	 * Each sub-package contains a PCI record setting. There are several different type of
+	 * record settings, of different lengths, but all elements of all settings are Integers.
+	 */
+	{.info = {"_HPX", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2_MIN, ACPI_RTYPE_INTEGER, 5, 0, 0, 0}},	/* variable (Pkgs) each (var Ints) */
+	{.info = {"_IFT", 0, ACPI_RTYPE_INTEGER}},	/* see IPMI spec */
+	{.info = {"_INI", 0, 0}},
+	{.info = {"_IRC", 0, 0}},
+	{.info = {"_LCK", 1, 0}},
+	{.info = {"_LID", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_MAT", 0, ACPI_RTYPE_BUFFER}},
+	{.info = {"_MLS", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2, ACPI_RTYPE_STRING, 2, 0, 0, 0}},	/* variable (Pkgs) each (2 Str) */
+	{.info = {"_MSG", 1, 0}},
+	{.info = {"_OFF", 0, 0}},
+	{.info = {"_ON_", 0, 0}},
+	{.info = {"_OS_", 0, ACPI_RTYPE_STRING}},
+	{.info = {"_OSC", 4, ACPI_RTYPE_BUFFER}},
+	{.info = {"_OST", 3, 0}},
+	{.info = {"_PCL", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}},	/* variable (Refs) */
+	{.info = {"_PCT", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_BUFFER, 2, 0, 0, 0}},	/* fixed (2 Buf) */
+	{.info = {"_PDC", 1, 0}},
+	{.info = {"_PIC", 1, 0}},
+	{.info = {"_PLD", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_BUFFER, 0, 0, 0, 0}},	/* variable (Bufs) */
+	{.info = {"_PPC", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_PPE", 0, ACPI_RTYPE_INTEGER}},	/* see dig64 spec */
+	{.info = {"_PR0", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}},	/* variable (Refs) */
+	{.info = {"_PR1", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}},	/* variable (Refs) */
+	{.info = {"_PR2", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}},	/* variable (Refs) */
+	{.info = {"_PRS", 0, ACPI_RTYPE_BUFFER}},
+
+	/*
+	 * For _PRT, many BIOSs reverse the 2nd and 3rd Package elements. This bug is so prevalent that there
+	 * is code in the ACPICA Resource Manager to detect this and switch them back. For now, do not allow
+	 * and issue a warning. To allow this and eliminate the warning, add the ACPI_RTYPE_REFERENCE
+	 * type to the 2nd element (index 1) in the statement below.
+	 */
+	{.info = {"_PRT", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2_FIXED, 4,
+					  ACPI_RTYPE_INTEGER,
+					  ACPI_RTYPE_INTEGER,
+					  ACPI_RTYPE_INTEGER | ACPI_RTYPE_REFERENCE, ACPI_RTYPE_INTEGER}},	/* variable (Pkgs) each (4): Int,Int,Int/Ref,Int */
+
+	{.info = {"_PRW", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_OPTION, 2,
+					  ACPI_RTYPE_INTEGER |
+					  ACPI_RTYPE_PACKAGE,
+					  ACPI_RTYPE_INTEGER, ACPI_RTYPE_REFERENCE, 0}},	/* variable (Pkgs) each: Pkg/Int,Int,[variable Refs] (Pkg is Ref/Int) */
+
+	{.info = {"_PS0", 0, 0}},
+	{.info = {"_PS1", 0, 0}},
+	{.info = {"_PS2", 0, 0}},
+	{.info = {"_PS3", 0, 0}},
+	{.info = {"_PSC", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_PSD", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2_COUNT, ACPI_RTYPE_INTEGER, 0, 0, 0, 0}},	/* variable (Pkgs) each (5 Int) with count */
+	{.info = {"_PSL", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}},	/* variable (Refs) */
+	{.info = {"_PSR", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_PSS", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2, ACPI_RTYPE_INTEGER, 6, 0, 0, 0}},	/* variable (Pkgs) each (6 Int) */
+	{.info = {"_PSV", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_PSW", 1, 0}},
+	{.info = {"_PTC", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_BUFFER, 2, 0, 0, 0}},	/* fixed (2 Buf) */
+	{.info = {"_PTS", 1, 0}},
+	{.info = {"_PXM", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_REG", 2, 0}},
+	{.info = {"_REV", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_RMV", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_ROM", 2, ACPI_RTYPE_BUFFER}},
+	{.info = {"_RTV", 0, ACPI_RTYPE_INTEGER}},
+
+	/*
+	 * For _S0_ through _S5_, the ACPI spec defines a return Package containing 1 Integer,
+	 * but most DSDTs have it wrong - 2,3, or 4 integers. Allow this by making the objects "variable length",
+	 * but all elements must be Integers.
+	 */
+	{.info = {"_S0_", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1, 0, 0, 0}},	/* fixed (1 Int) */
+	{.info = {"_S1_", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1, 0, 0, 0}},	/* fixed (1 Int) */
+	{.info = {"_S2_", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1, 0, 0, 0}},	/* fixed (1 Int) */
+	{.info = {"_S3_", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1, 0, 0, 0}},	/* fixed (1 Int) */
+	{.info = {"_S4_", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1, 0, 0, 0}},	/* fixed (1 Int) */
+	{.info = {"_S5_", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1, 0, 0, 0}},	/* fixed (1 Int) */
+
+	{.info = {"_S1D", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_S2D", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_S3D", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_S4D", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_S0W", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_S1W", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_S2W", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_S3W", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_S4W", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_SBS", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_SCP", 0x13, 0}},	/* Acpi 1.0 allowed 1 arg. Acpi 3.0 expanded to 3 args. Allow both. */
+	/* Note: the 3-arg definition may be removed for ACPI 4.0 */
+	{.info = {"_SDD", 1, 0}},
+	{.info = {"_SEG", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_SLI", 0, ACPI_RTYPE_BUFFER}},
+	{.info = {"_SPD", 1, ACPI_RTYPE_INTEGER}},
+	{.info = {"_SRS", 1, 0}},
+	{.info = {"_SRV", 0, ACPI_RTYPE_INTEGER}},	/* see IPMI spec */
+	{.info = {"_SST", 1, 0}},
+	{.info = {"_STA", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_STM", 3, 0}},
+	{.info = {"_STR", 0, ACPI_RTYPE_BUFFER}},
+	{.info = {"_SUN", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_SWS", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_TC1", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_TC2", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_TMP", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_TPC", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_TPT", 1, 0}},
+	{.info = {"_TRT", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2, ACPI_RTYPE_REFERENCE, 2,
+					  ACPI_RTYPE_INTEGER, 6, 0}},	/* variable (Pkgs) each 2_ref/6_int */
+	{.info = {"_TSD", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2_COUNT, ACPI_RTYPE_INTEGER, 5, 0, 0, 0}},	/* variable (Pkgs) each 5_int with count */
+	{.info = {"_TSP", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_TSS", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2, ACPI_RTYPE_INTEGER, 5, 0, 0, 0}},	/* variable (Pkgs) each 5_int */
+	{.info = {"_TST", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_TTS", 1, 0}},
+	{.info = {"_TZD", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}},	/* variable (Refs) */
+	{.info = {"_TZM", 0, ACPI_RTYPE_REFERENCE}},
+	{.info = {"_TZP", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_UID", 0, ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING}},
+	{.info = {"_UPC", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 4, 0, 0, 0}},	/* fixed (4 Int) */
+	{.info = {"_UPD", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_UPP", 0, ACPI_RTYPE_INTEGER}},
+	{.info = {"_VPO", 0, ACPI_RTYPE_INTEGER}},
+
+	/* Acpi 1.0 defined _WAK with no return value. Later, it was changed to return a package */
+
+	{.info = {"_WAK", 1, ACPI_RTYPE_NONE | ACPI_RTYPE_INTEGER | ACPI_RTYPE_PACKAGE}},
+	{.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 2, 0, 0, 0}},	/* fixed (2 Int), but is optional */
+	{.ret_info = {0, 0, 0, 0, 0, 0}}	/* Table terminator */
+};
+
+#if 0
+	/* Not implemented */
+
+{
+"_WDG", 0, ACPI_RTYPE_BUFFER},	/* MS Extension */
+
+{
+"_WED", 1, ACPI_RTYPE_PACKAGE},	/* MS Extension */
+
+    /* This is an internally implemented control method, no need to check */
+{
+"_OSI", 1, ACPI_RTYPE_INTEGER},
+
+    /* TBD: */
+    _PRT - currently ignore reversed entries.attempt to fix here ?
+    think about code that attempts to fix package elements like _BIF, etc.
+#endif
+#endif
diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index d38f9be2f6ee..63f5b4cf4de1 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -908,7 +908,9 @@ enum acpi_madt_type {
 	ACPI_MADT_TYPE_IO_SAPIC = 6,
 	ACPI_MADT_TYPE_LOCAL_SAPIC = 7,
 	ACPI_MADT_TYPE_INTERRUPT_SOURCE = 8,
-	ACPI_MADT_TYPE_RESERVED = 9	/* 9 and greater are reserved */
+	ACPI_MADT_TYPE_LOCAL_X2APIC = 9,
+	ACPI_MADT_TYPE_LOCAL_X2APIC_NMI = 10,
+	ACPI_MADT_TYPE_RESERVED = 11	/* 11 and greater are reserved */
 };
 
 /*
@@ -1009,6 +1011,26 @@ struct acpi_madt_interrupt_source {
 
 #define ACPI_MADT_CPEI_OVERRIDE     (1)
 
+/* 9: Processor Local X2_APIC (07/2008) */
+
+struct acpi_madt_local_x2apic {
+	struct acpi_subtable_header header;
+	u16 reserved;		/* Reserved - must be zero */
+	u32 local_apic_id;	/* Processor X2_APIC ID  */
+	u32 lapic_flags;
+	u32 uid;		/* Extended X2_APIC processor ID */
+};
+
+/* 10: Local X2APIC NMI (07/2008) */
+
+struct acpi_madt_local_x2apic_nmi {
+	struct acpi_subtable_header header;
+	u16 inti_flags;
+	u32 uid;		/* Processor X2_APIC ID */
+	u8 lint;		/* LINTn to which NMI is connected */
+	u8 reserved[3];
+};
+
 /*
  * Common flags fields for MADT subtables
  */
@@ -1150,10 +1172,15 @@ struct acpi_table_srat {
 enum acpi_srat_type {
 	ACPI_SRAT_TYPE_CPU_AFFINITY = 0,
 	ACPI_SRAT_TYPE_MEMORY_AFFINITY = 1,
-	ACPI_SRAT_TYPE_RESERVED = 2
+	ACPI_SRAT_TYPE_X2APIC_CPU_AFFINITY = 2,
+	ACPI_SRAT_TYPE_RESERVED = 3	/* 3 and greater are reserved */
 };
 
-/* SRAT sub-tables */
+/*
+ * SRAT Sub-tables, correspond to Type in struct acpi_subtable_header
+ */
+
+/* 0: Processor Local APIC/SAPIC Affinity */
 
 struct acpi_srat_cpu_affinity {
 	struct acpi_subtable_header header;
@@ -1165,9 +1192,7 @@ struct acpi_srat_cpu_affinity {
 	u32 reserved;		/* Reserved, must be zero */
 };
 
-/* Flags */
-
-#define ACPI_SRAT_CPU_ENABLED       (1)	/* 00: Use affinity structure */
+/* 1: Memory Affinity */
 
 struct acpi_srat_mem_affinity {
 	struct acpi_subtable_header header;
@@ -1186,6 +1211,20 @@ struct acpi_srat_mem_affinity {
 #define ACPI_SRAT_MEM_HOT_PLUGGABLE (1<<1)	/* 01: Memory region is hot pluggable */
 #define ACPI_SRAT_MEM_NON_VOLATILE  (1<<2)	/* 02: Memory region is non-volatile */
 
+/* 2: Processor Local X2_APIC Affinity (07/2008) */
+
+struct acpi_srat_x2apic_cpu_affinity {
+	struct acpi_subtable_header header;
+	u16 reserved;		/* Reserved, must be zero */
+	u32 proximity_domain;
+	u32 apic_id;
+	u32 flags;
+};
+
+/* Flags for struct acpi_srat_cpu_affinity and struct acpi_srat_x2apic_cpu_affinity */
+
+#define ACPI_SRAT_CPU_ENABLED       (1)	/* 00: Use affinity structure */
+
 /*******************************************************************************
  *
  * TCPA - Trusted Computing Platform Alliance table
diff --git a/include/acpi/actypes.h b/include/acpi/actypes.h
index 4ea4f40bf894..7220361790b3 100644
--- a/include/acpi/actypes.h
+++ b/include/acpi/actypes.h
@@ -525,6 +525,7 @@ typedef u32 acpi_event_status;
 #define ACPI_EVENT_FLAG_ENABLED         (acpi_event_status) 0x01
 #define ACPI_EVENT_FLAG_WAKE_ENABLED    (acpi_event_status) 0x02
 #define ACPI_EVENT_FLAG_SET             (acpi_event_status) 0x04
+#define ACPI_EVENT_FLAG_HANDLE		(acpi_event_status) 0x08
 
 /*
  * General Purpose Events (GPE)
@@ -607,8 +608,15 @@ typedef u8 acpi_adr_space_type;
 
 /*
  * bit_register IDs
- * These are bitfields defined within the full ACPI registers
+ *
+ * These values are intended to be used by the hardware interfaces
+ * and are mapped to individual bitfields defined within the ACPI
+ * registers. See the acpi_gbl_bit_register_info global table in utglobal.c
+ * for this mapping.
  */
+
+/* PM1 Status register */
+
 #define ACPI_BITREG_TIMER_STATUS                0x00
 #define ACPI_BITREG_BUS_MASTER_STATUS           0x01
 #define ACPI_BITREG_GLOBAL_LOCK_STATUS          0x02
@@ -618,24 +626,29 @@ typedef u8 acpi_adr_space_type;
 #define ACPI_BITREG_WAKE_STATUS                 0x06
 #define ACPI_BITREG_PCIEXP_WAKE_STATUS          0x07
 
+/* PM1 Enable register */
+
 #define ACPI_BITREG_TIMER_ENABLE                0x08
 #define ACPI_BITREG_GLOBAL_LOCK_ENABLE          0x09
 #define ACPI_BITREG_POWER_BUTTON_ENABLE         0x0A
 #define ACPI_BITREG_SLEEP_BUTTON_ENABLE         0x0B
 #define ACPI_BITREG_RT_CLOCK_ENABLE             0x0C
-#define ACPI_BITREG_WAKE_ENABLE                 0x0D
-#define ACPI_BITREG_PCIEXP_WAKE_DISABLE         0x0E
+#define ACPI_BITREG_PCIEXP_WAKE_DISABLE         0x0D
+
+/* PM1 Control register */
+
+#define ACPI_BITREG_SCI_ENABLE                  0x0E
+#define ACPI_BITREG_BUS_MASTER_RLD              0x0F
+#define ACPI_BITREG_GLOBAL_LOCK_RELEASE         0x10
+#define ACPI_BITREG_SLEEP_TYPE_A                0x11
+#define ACPI_BITREG_SLEEP_TYPE_B                0x12
+#define ACPI_BITREG_SLEEP_ENABLE                0x13
 
-#define ACPI_BITREG_SCI_ENABLE                  0x0F
-#define ACPI_BITREG_BUS_MASTER_RLD              0x10
-#define ACPI_BITREG_GLOBAL_LOCK_RELEASE         0x11
-#define ACPI_BITREG_SLEEP_TYPE_A                0x12
-#define ACPI_BITREG_SLEEP_TYPE_B                0x13
-#define ACPI_BITREG_SLEEP_ENABLE                0x14
+/* PM2 Control register */
 
-#define ACPI_BITREG_ARB_DISABLE                 0x15
+#define ACPI_BITREG_ARB_DISABLE                 0x14
 
-#define ACPI_BITREG_MAX                         0x15
+#define ACPI_BITREG_MAX                         0x14
 #define ACPI_NUM_BITREG                         ACPI_BITREG_MAX + 1
 
 /*
@@ -859,6 +872,7 @@ struct acpi_obj_info_header {
 struct acpi_device_info {
 	ACPI_COMMON_OBJ_INFO;
 
+	u32 param_count;	/* If a method, required parameter count */
 	u32 valid;		/* Indicates which fields below are valid */
 	u32 current_status;	/* _STA value */
 	acpi_integer address;	/* _ADR value if any */
@@ -1225,8 +1239,8 @@ struct acpi_resource {
 
 #pragma pack()
 
-#define ACPI_RS_SIZE_MIN                    12
 #define ACPI_RS_SIZE_NO_DATA                8	/* Id + Length fields */
+#define ACPI_RS_SIZE_MIN                    (u32) ACPI_ROUND_UP_TO_NATIVE_WORD (12)
 #define ACPI_RS_SIZE(type)                  (u32) (ACPI_RS_SIZE_NO_DATA + sizeof (type))
 
 #define ACPI_NEXT_RESOURCE(res)             (struct acpi_resource *)((u8 *) res + res->length)
diff --git a/include/acpi/acutils.h b/include/acpi/acutils.h
index 69f8888771ff..d8307b2987e3 100644
--- a/include/acpi/acutils.h
+++ b/include/acpi/acutils.h
@@ -110,7 +110,7 @@ struct acpi_pkg_info {
 /*
  * utglobal - Global data structures and procedures
  */
-void acpi_ut_init_globals(void);
+acpi_status acpi_ut_init_globals(void);
 
 #if defined(ACPI_DEBUG_OUTPUT) || defined(ACPI_DEBUGGER)
 
@@ -126,6 +126,8 @@ char *acpi_ut_get_node_name(void *object);
 
 char *acpi_ut_get_descriptor_name(void *object);
 
+const char *acpi_ut_get_reference_name(union acpi_operand_object *object);
+
 char *acpi_ut_get_object_type_name(union acpi_operand_object *obj_desc);
 
 char *acpi_ut_get_region_name(u8 space_id);
diff --git a/include/acpi/platform/acgcc.h b/include/acpi/platform/acgcc.h
index 8996dba90cd9..8e2cdc57b197 100644
--- a/include/acpi/platform/acgcc.h
+++ b/include/acpi/platform/acgcc.h
@@ -46,7 +46,7 @@
 
 /* Function name is used for debug output. Non-ANSI, compiler-dependent */
 
-#define ACPI_GET_FUNCTION_NAME          __FUNCTION__
+#define ACPI_GET_FUNCTION_NAME          __func__
 
 /*
  * This macro is used to tag functions as "printf-like" because
diff --git a/include/acpi/platform/aclinux.h b/include/acpi/platform/aclinux.h
index 9af464598682..0515e754449d 100644
--- a/include/acpi/platform/aclinux.h
+++ b/include/acpi/platform/aclinux.h
@@ -53,6 +53,7 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/ctype.h>
+#include <linux/sched.h>
 #include <asm/system.h>
 #include <asm/atomic.h>
 #include <asm/div64.h>
@@ -137,4 +138,13 @@ static inline void *acpi_os_acquire_object(acpi_cache_t * cache)
 #define ACPI_ALLOCATE_ZEROED(a)	acpi_os_allocate_zeroed(a)
 #define ACPI_FREE(a)		kfree(a)
 
+/*
+ * We need to show where it is safe to preempt execution of ACPICA
+ */
+#define ACPI_PREEMPTION_POINT()		\
+	do {				\
+		if (!irqs_disabled())	\
+			cond_resched();	\
+	} while (0)
+
 #endif				/* __ACLINUX_H__ */
diff --git a/include/asm-arm/plat-s3c/debug-macro.S b/include/asm-arm/plat-s3c/debug-macro.S
deleted file mode 100644
index 84c40b847da8..000000000000
--- a/include/asm-arm/plat-s3c/debug-macro.S
+++ /dev/null
@@ -1,75 +0,0 @@
-/* linux/include/asm-arm/plat-s3c/debug-macro.S
- *
- * Copyright 2005, 2007 Simtec Electronics
- *	http://armlinux.simtec.co.uk/
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <asm/plat-s3c/regs-serial.h>
-
-/* The S3C2440 implementations are used by default as they are the
- * most widely re-used */
-
-	.macro fifo_level_s3c2440 rd, rx
-		ldr	\rd, [ \rx, # S3C2410_UFSTAT ]
-		and	\rd, \rd, #S3C2440_UFSTAT_TXMASK
-	.endm
-
-#ifndef fifo_level
-#define fifo_level fifo_level_s3c2410
-#endif
-
-	.macro  fifo_full_s3c2440 rd, rx
-		ldr	\rd, [ \rx, # S3C2410_UFSTAT ]
-		tst	\rd, #S3C2440_UFSTAT_TXFULL
-	.endm
-
-#ifndef fifo_full
-#define fifo_full fifo_full_s3c2440
-#endif
-
-	.macro	senduart,rd,rx
-		strb 	\rd, [\rx, # S3C2410_UTXH ]
-	.endm
-
-	.macro	busyuart, rd, rx
-		ldr	\rd, [ \rx, # S3C2410_UFCON ]
-		tst	\rd, #S3C2410_UFCON_FIFOMODE	@ fifo enabled?
-		beq	1001f				@
-		@ FIFO enabled...
-1003:
-		fifo_full \rd, \rx
-		bne	1003b
-		b	1002f
-
-1001:
-		@ busy waiting for non fifo
-		ldr	\rd, [ \rx, # S3C2410_UTRSTAT ]
-		tst	\rd, #S3C2410_UTRSTAT_TXFE
-		beq	1001b
-
-1002:		@ exit busyuart
-	.endm
-
-	.macro	waituart,rd,rx
-		ldr	\rd, [ \rx, # S3C2410_UFCON ]
-		tst	\rd, #S3C2410_UFCON_FIFOMODE	@ fifo enabled?
-		beq	1001f				@
-		@ FIFO enabled...
-1003:
-		fifo_level \rd, \rx
-		teq	\rd, #0
-		bne	1003b
-		b	1002f
-1001:
-		@ idle waiting for non fifo
-		ldr	\rd, [ \rx, # S3C2410_UTRSTAT ]
-		tst	\rd, #S3C2410_UTRSTAT_TXFE
-		beq	1001b
-
-1002:		@ exit busyuart
-	.endm
diff --git a/include/asm-arm/plat-s3c/iic.h b/include/asm-arm/plat-s3c/iic.h
deleted file mode 100644
index 5106acaa1d0e..000000000000
--- a/include/asm-arm/plat-s3c/iic.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/iic.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - I2C Controller platfrom_device info
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_IIC_H
-#define __ASM_ARCH_IIC_H __FILE__
-
-#define S3C_IICFLG_FILTER	(1<<0)	/* enable s3c2440 filter */
-
-/* Notes:
- *	1) All frequencies are expressed in Hz
- *	2) A value of zero is `do not care`
-*/
-
-struct s3c2410_platform_i2c {
-	int		bus_num;	/* bus number to use */
-	unsigned int	flags;
-	unsigned int	slave_addr;	/* slave address for controller */
-	unsigned long	bus_freq;	/* standard bus frequency */
-	unsigned long	max_freq;	/* max frequency for the bus */
-	unsigned long	min_freq;	/* min frequency for the bus */
-	unsigned int	sda_delay;	/* pclks (s3c2440 only) */
-};
-
-#endif /* __ASM_ARCH_IIC_H */
diff --git a/include/asm-arm/plat-s3c/map.h b/include/asm-arm/plat-s3c/map.h
deleted file mode 100644
index b84289d32a54..000000000000
--- a/include/asm-arm/plat-s3c/map.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/include/asm-arm/plat-s3c/map.h
- *
- * Copyright 2003, 2007 Simtec Electronics
- *	http://armlinux.simtec.co.uk/
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * S3C - Memory map definitions (virtual addresses)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_MAP_H
-#define __ASM_PLAT_MAP_H __FILE__
-
-/* Fit all our registers in at 0xF4000000 upwards, trying to use as
- * little of the VA space as possible so vmalloc and friends have a
- * better chance of getting memory.
- *
- * we try to ensure stuff like the IRQ registers are available for
- * an single MOVS instruction (ie, only 8 bits of set data)
- */
-
-#define S3C_ADDR_BASE	(0xF4000000)
-
-#ifndef __ASSEMBLY__
-#define S3C_ADDR(x)	((void __iomem __force *)S3C_ADDR_BASE + (x))
-#else
-#define S3C_ADDR(x)	(S3C_ADDR_BASE + (x))
-#endif
-
-#define S3C_VA_IRQ	S3C_ADDR(0x00000000)	/* irq controller(s) */
-#define S3C_VA_SYS	S3C_ADDR(0x00100000)	/* system control */
-#define S3C_VA_MEM	S3C_ADDR(0x00200000)	/* system control */
-#define S3C_VA_TIMER	S3C_ADDR(0x00300000)	/* timer block */
-#define S3C_VA_WATCHDOG	S3C_ADDR(0x00400000)	/* watchdog */
-#define S3C_VA_UART	S3C_ADDR(0x01000000)	/* UART */
-
-#endif /* __ASM_PLAT_MAP_H */
diff --git a/include/asm-arm/plat-s3c/nand.h b/include/asm-arm/plat-s3c/nand.h
deleted file mode 100644
index f4dcd14af059..000000000000
--- a/include/asm-arm/plat-s3c/nand.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/nand.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - NAND device controller platfrom_device info
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* struct s3c2410_nand_set
- *
- * define an set of one or more nand chips registered with an unique mtd
- *
- * nr_chips	 = number of chips in this set
- * nr_partitions = number of partitions pointed to be partitoons (or zero)
- * name		 = name of set (optional)
- * nr_map	 = map for low-layer logical to physical chip numbers (option)
- * partitions	 = mtd partition list
-*/
-
-struct s3c2410_nand_set {
-	unsigned int		disable_ecc : 1;
-
-	int			nr_chips;
-	int			nr_partitions;
-	char			*name;
-	int			*nr_map;
-	struct mtd_partition	*partitions;
-	struct nand_ecclayout	*ecc_layout;
-};
-
-struct s3c2410_platform_nand {
-	/* timing information for controller, all times in nanoseconds */
-
-	int	tacls;	/* time for active CLE/ALE to nWE/nOE */
-	int	twrph0;	/* active time for nWE/nOE */
-	int	twrph1;	/* time for release CLE/ALE from nWE/nOE inactive */
-
-	unsigned int	ignore_unset_ecc : 1;
-
-	int			nr_sets;
-	struct s3c2410_nand_set *sets;
-
-	void			(*select_chip)(struct s3c2410_nand_set *,
-					       int chip);
-};
-
diff --git a/include/asm-arm/plat-s3c/regs-ac97.h b/include/asm-arm/plat-s3c/regs-ac97.h
deleted file mode 100644
index c3878f7acb83..000000000000
--- a/include/asm-arm/plat-s3c/regs-ac97.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-ac97.h
- *
- * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
- *		http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2440 AC97 Controller
-*/
-
-#ifndef __ASM_ARCH_REGS_AC97_H
-#define __ASM_ARCH_REGS_AC97_H __FILE__
-
-#define S3C_AC97_GLBCTRL				(0x00)
-
-#define S3C_AC97_GLBCTRL_CODECREADYIE			(1<<22)
-#define S3C_AC97_GLBCTRL_PCMOUTURIE			(1<<21)
-#define S3C_AC97_GLBCTRL_PCMINORIE			(1<<20)
-#define S3C_AC97_GLBCTRL_MICINORIE			(1<<19)
-#define S3C_AC97_GLBCTRL_PCMOUTTIE			(1<<18)
-#define S3C_AC97_GLBCTRL_PCMINTIE			(1<<17)
-#define S3C_AC97_GLBCTRL_MICINTIE			(1<<16)
-#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF			(0<<12)
-#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO			(1<<12)
-#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA			(2<<12)
-#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK			(3<<12)
-#define S3C_AC97_GLBCTRL_PCMINTM_OFF			(0<<10)
-#define S3C_AC97_GLBCTRL_PCMINTM_PIO			(1<<10)
-#define S3C_AC97_GLBCTRL_PCMINTM_DMA			(2<<10)
-#define S3C_AC97_GLBCTRL_PCMINTM_MASK			(3<<10)
-#define S3C_AC97_GLBCTRL_MICINTM_OFF			(0<<8)
-#define S3C_AC97_GLBCTRL_MICINTM_PIO			(1<<8)
-#define S3C_AC97_GLBCTRL_MICINTM_DMA			(2<<8)
-#define S3C_AC97_GLBCTRL_MICINTM_MASK			(3<<8)
-#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE		(1<<3)
-#define S3C_AC97_GLBCTRL_ACLINKON			(1<<2)
-#define S3C_AC97_GLBCTRL_WARMRESET			(1<<1)
-#define S3C_AC97_GLBCTRL_COLDRESET			(1<<0)
-
-#define S3C_AC97_GLBSTAT				(0x04)
-
-#define S3C_AC97_GLBSTAT_CODECREADY			(1<<22)
-#define S3C_AC97_GLBSTAT_PCMOUTUR			(1<<21)
-#define S3C_AC97_GLBSTAT_PCMINORI			(1<<20)
-#define S3C_AC97_GLBSTAT_MICINORI			(1<<19)
-#define S3C_AC97_GLBSTAT_PCMOUTTI			(1<<18)
-#define S3C_AC97_GLBSTAT_PCMINTI			(1<<17)
-#define S3C_AC97_GLBSTAT_MICINTI			(1<<16)
-#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE			(0<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_INIT			(1<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_READY		(2<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE		(3<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_LP			(4<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_WARM			(5<<0)
-
-#define S3C_AC97_CODEC_CMD				(0x08)
-
-#define S3C_AC97_CODEC_CMD_READ				(1<<23)
-
-#define S3C_AC97_STAT					(0x0c)
-#define S3C_AC97_PCM_ADDR				(0x10)
-#define S3C_AC97_PCM_DATA				(0x18)
-#define S3C_AC97_MIC_DATA				(0x1C)
-
-#endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/include/asm-arm/plat-s3c/regs-adc.h b/include/asm-arm/plat-s3c/regs-adc.h
deleted file mode 100644
index 4323cccc86cd..000000000000
--- a/include/asm-arm/plat-s3c/regs-adc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-adc.h
- *
- * Copyright (c) 2004 Shannon Holland <holland@loser.net>
- *
- * This program is free software; yosu can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 ADC registers
-*/
-
-#ifndef __ASM_ARCH_REGS_ADC_H
-#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
-
-#define S3C2410_ADCREG(x) (x)
-
-#define S3C2410_ADCCON	   S3C2410_ADCREG(0x00)
-#define S3C2410_ADCTSC	   S3C2410_ADCREG(0x04)
-#define S3C2410_ADCDLY	   S3C2410_ADCREG(0x08)
-#define S3C2410_ADCDAT0	   S3C2410_ADCREG(0x0C)
-#define S3C2410_ADCDAT1	   S3C2410_ADCREG(0x10)
-
-
-/* ADCCON Register Bits */
-#define S3C2410_ADCCON_ECFLG		(1<<15)
-#define S3C2410_ADCCON_PRSCEN		(1<<14)
-#define S3C2410_ADCCON_PRSCVL(x)	(((x)&0xFF)<<6)
-#define S3C2410_ADCCON_PRSCVLMASK	(0xFF<<6)
-#define S3C2410_ADCCON_SELMUX(x)	(((x)&0x7)<<3)
-#define S3C2410_ADCCON_MUXMASK		(0x7<<3)
-#define S3C2410_ADCCON_STDBM		(1<<2)
-#define S3C2410_ADCCON_READ_START	(1<<1)
-#define S3C2410_ADCCON_ENABLE_START	(1<<0)
-#define S3C2410_ADCCON_STARTMASK	(0x3<<0)
-
-
-/* ADCTSC Register Bits */
-#define S3C2410_ADCTSC_YM_SEN		(1<<7)
-#define S3C2410_ADCTSC_YP_SEN		(1<<6)
-#define S3C2410_ADCTSC_XM_SEN		(1<<5)
-#define S3C2410_ADCTSC_XP_SEN		(1<<4)
-#define S3C2410_ADCTSC_PULL_UP_DISABLE	(1<<3)
-#define S3C2410_ADCTSC_AUTO_PST		(1<<2)
-#define S3C2410_ADCTSC_XY_PST(x)	(((x)&0x3)<<0)
-
-/* ADCDAT0 Bits */
-#define S3C2410_ADCDAT0_UPDOWN		(1<<15)
-#define S3C2410_ADCDAT0_AUTO_PST	(1<<14)
-#define S3C2410_ADCDAT0_XY_PST		(0x3<<12)
-#define S3C2410_ADCDAT0_XPDATA_MASK	(0x03FF)
-
-/* ADCDAT1 Bits */
-#define S3C2410_ADCDAT1_UPDOWN		(1<<15)
-#define S3C2410_ADCDAT1_AUTO_PST	(1<<14)
-#define S3C2410_ADCDAT1_XY_PST		(0x3<<12)
-#define S3C2410_ADCDAT1_YPDATA_MASK	(0x03FF)
-
-#endif /* __ASM_ARCH_REGS_ADC_H */
-
-
diff --git a/include/asm-arm/plat-s3c/regs-iic.h b/include/asm-arm/plat-s3c/regs-iic.h
deleted file mode 100644
index 2f7c17de8ac8..000000000000
--- a/include/asm-arm/plat-s3c/regs-iic.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-iic.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *		http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 I2C Controller
-*/
-
-#ifndef __ASM_ARCH_REGS_IIC_H
-#define __ASM_ARCH_REGS_IIC_H __FILE__
-
-/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
-
-#define S3C2410_IICREG(x) (x)
-
-#define S3C2410_IICCON    S3C2410_IICREG(0x00)
-#define S3C2410_IICSTAT   S3C2410_IICREG(0x04)
-#define S3C2410_IICADD    S3C2410_IICREG(0x08)
-#define S3C2410_IICDS     S3C2410_IICREG(0x0C)
-#define S3C2440_IICLC	  S3C2410_IICREG(0x10)
-
-#define S3C2410_IICCON_ACKEN		(1<<7)
-#define S3C2410_IICCON_TXDIV_16		(0<<6)
-#define S3C2410_IICCON_TXDIV_512	(1<<6)
-#define S3C2410_IICCON_IRQEN		(1<<5)
-#define S3C2410_IICCON_IRQPEND		(1<<4)
-#define S3C2410_IICCON_SCALE(x)		((x)&15)
-#define S3C2410_IICCON_SCALEMASK	(0xf)
-
-#define S3C2410_IICSTAT_MASTER_RX	(2<<6)
-#define S3C2410_IICSTAT_MASTER_TX	(3<<6)
-#define S3C2410_IICSTAT_SLAVE_RX	(0<<6)
-#define S3C2410_IICSTAT_SLAVE_TX	(1<<6)
-#define S3C2410_IICSTAT_MODEMASK	(3<<6)
-
-#define S3C2410_IICSTAT_START		(1<<5)
-#define S3C2410_IICSTAT_BUSBUSY		(1<<5)
-#define S3C2410_IICSTAT_TXRXEN		(1<<4)
-#define S3C2410_IICSTAT_ARBITR		(1<<3)
-#define S3C2410_IICSTAT_ASSLAVE		(1<<2)
-#define S3C2410_IICSTAT_ADDR0		(1<<1)
-#define S3C2410_IICSTAT_LASTBIT		(1<<0)
-
-#define S3C2410_IICLC_SDA_DELAY0	(0 << 0)
-#define S3C2410_IICLC_SDA_DELAY5	(1 << 0)
-#define S3C2410_IICLC_SDA_DELAY10	(2 << 0)
-#define S3C2410_IICLC_SDA_DELAY15	(3 << 0)
-#define S3C2410_IICLC_SDA_DELAY_MASK	(3 << 0)
-
-#define S3C2410_IICLC_FILTER_ON		(1<<2)
-
-#endif /* __ASM_ARCH_REGS_IIC_H */
diff --git a/include/asm-arm/plat-s3c/regs-nand.h b/include/asm-arm/plat-s3c/regs-nand.h
deleted file mode 100644
index b2caa4bca270..000000000000
--- a/include/asm-arm/plat-s3c/regs-nand.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-nand.h
- *
- * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
- *		      http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 NAND register definitions
-*/
-
-#ifndef __ASM_ARM_REGS_NAND
-#define __ASM_ARM_REGS_NAND
-
-
-#define S3C2410_NFREG(x) (x)
-
-#define S3C2410_NFCONF  S3C2410_NFREG(0x00)
-#define S3C2410_NFCMD   S3C2410_NFREG(0x04)
-#define S3C2410_NFADDR  S3C2410_NFREG(0x08)
-#define S3C2410_NFDATA  S3C2410_NFREG(0x0C)
-#define S3C2410_NFSTAT  S3C2410_NFREG(0x10)
-#define S3C2410_NFECC   S3C2410_NFREG(0x14)
-
-#define S3C2440_NFCONT   S3C2410_NFREG(0x04)
-#define S3C2440_NFCMD    S3C2410_NFREG(0x08)
-#define S3C2440_NFADDR   S3C2410_NFREG(0x0C)
-#define S3C2440_NFDATA   S3C2410_NFREG(0x10)
-#define S3C2440_NFECCD0  S3C2410_NFREG(0x14)
-#define S3C2440_NFECCD1  S3C2410_NFREG(0x18)
-#define S3C2440_NFECCD   S3C2410_NFREG(0x1C)
-#define S3C2440_NFSTAT   S3C2410_NFREG(0x20)
-#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
-#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
-#define S3C2440_NFMECC0  S3C2410_NFREG(0x2C)
-#define S3C2440_NFMECC1  S3C2410_NFREG(0x30)
-#define S3C2440_NFSECC   S3C2410_NFREG(0x34)
-#define S3C2440_NFSBLK   S3C2410_NFREG(0x38)
-#define S3C2440_NFEBLK   S3C2410_NFREG(0x3C)
-
-#define S3C2412_NFSBLK		S3C2410_NFREG(0x20)
-#define S3C2412_NFEBLK		S3C2410_NFREG(0x24)
-#define S3C2412_NFSTAT		S3C2410_NFREG(0x28)
-#define S3C2412_NFMECC_ERR0	S3C2410_NFREG(0x2C)
-#define S3C2412_NFMECC_ERR1	S3C2410_NFREG(0x30)
-#define S3C2412_NFMECC0		S3C2410_NFREG(0x34)
-#define S3C2412_NFMECC1		S3C2410_NFREG(0x38)
-#define S3C2412_NFSECC		S3C2410_NFREG(0x3C)
-
-#define S3C2410_NFCONF_EN          (1<<15)
-#define S3C2410_NFCONF_512BYTE     (1<<14)
-#define S3C2410_NFCONF_4STEP       (1<<13)
-#define S3C2410_NFCONF_INITECC     (1<<12)
-#define S3C2410_NFCONF_nFCE        (1<<11)
-#define S3C2410_NFCONF_TACLS(x)    ((x)<<8)
-#define S3C2410_NFCONF_TWRPH0(x)   ((x)<<4)
-#define S3C2410_NFCONF_TWRPH1(x)   ((x)<<0)
-
-#define S3C2410_NFSTAT_BUSY        (1<<0)
-
-#define S3C2440_NFCONF_BUSWIDTH_8	(0<<0)
-#define S3C2440_NFCONF_BUSWIDTH_16	(1<<0)
-#define S3C2440_NFCONF_ADVFLASH		(1<<3)
-#define S3C2440_NFCONF_TACLS(x)		((x)<<12)
-#define S3C2440_NFCONF_TWRPH0(x)	((x)<<8)
-#define S3C2440_NFCONF_TWRPH1(x)	((x)<<4)
-
-#define S3C2440_NFCONT_LOCKTIGHT	(1<<13)
-#define S3C2440_NFCONT_SOFTLOCK		(1<<12)
-#define S3C2440_NFCONT_ILLEGALACC_EN	(1<<10)
-#define S3C2440_NFCONT_RNBINT_EN	(1<<9)
-#define S3C2440_NFCONT_RN_FALLING	(1<<8)
-#define S3C2440_NFCONT_SPARE_ECCLOCK	(1<<6)
-#define S3C2440_NFCONT_MAIN_ECCLOCK	(1<<5)
-#define S3C2440_NFCONT_INITECC		(1<<4)
-#define S3C2440_NFCONT_nFCE		(1<<1)
-#define S3C2440_NFCONT_ENABLE		(1<<0)
-
-#define S3C2440_NFSTAT_READY		(1<<0)
-#define S3C2440_NFSTAT_nCE		(1<<1)
-#define S3C2440_NFSTAT_RnB_CHANGE	(1<<2)
-#define S3C2440_NFSTAT_ILLEGAL_ACCESS	(1<<3)
-
-#define S3C2412_NFCONF_NANDBOOT		(1<<31)
-#define S3C2412_NFCONF_ECCCLKCON	(1<<30)
-#define S3C2412_NFCONF_ECC_MLC		(1<<24)
-#define S3C2412_NFCONF_TACLS_MASK	(7<<12)	/* 1 extra bit of Tacls */
-
-#define S3C2412_NFCONT_ECC4_DIRWR	(1<<18)
-#define S3C2412_NFCONT_LOCKTIGHT	(1<<17)
-#define S3C2412_NFCONT_SOFTLOCK		(1<<16)
-#define S3C2412_NFCONT_ECC4_ENCINT	(1<<13)
-#define S3C2412_NFCONT_ECC4_DECINT	(1<<12)
-#define S3C2412_NFCONT_MAIN_ECC_LOCK	(1<<7)
-#define S3C2412_NFCONT_INIT_MAIN_ECC	(1<<5)
-#define S3C2412_NFCONT_nFCE1		(1<<2)
-#define S3C2412_NFCONT_nFCE0		(1<<1)
-
-#define S3C2412_NFSTAT_ECC_ENCDONE	(1<<7)
-#define S3C2412_NFSTAT_ECC_DECDONE	(1<<6)
-#define S3C2412_NFSTAT_ILLEGAL_ACCESS	(1<<5)
-#define S3C2412_NFSTAT_RnB_CHANGE	(1<<4)
-#define S3C2412_NFSTAT_nFCE1		(1<<3)
-#define S3C2412_NFSTAT_nFCE0		(1<<2)
-#define S3C2412_NFSTAT_Res1		(1<<1)
-#define S3C2412_NFSTAT_READY		(1<<0)
-
-#define S3C2412_NFECCERR_SERRDATA(x)	(((x) >> 21) & 0xf)
-#define S3C2412_NFECCERR_SERRBIT(x)	(((x) >> 18) & 0x7)
-#define S3C2412_NFECCERR_MERRDATA(x)	(((x) >> 7) & 0x3ff)
-#define S3C2412_NFECCERR_MERRBIT(x)	(((x) >> 4) & 0x7)
-#define S3C2412_NFECCERR_SPARE_ERR(x)	(((x) >> 2) & 0x3)
-#define S3C2412_NFECCERR_MAIN_ERR(x)	(((x) >> 2) & 0x3)
-#define S3C2412_NFECCERR_NONE		(0)
-#define S3C2412_NFECCERR_1BIT		(1)
-#define S3C2412_NFECCERR_MULTIBIT	(2)
-#define S3C2412_NFECCERR_ECCAREA	(3)
-
-
-
-#endif /* __ASM_ARM_REGS_NAND */
-
diff --git a/include/asm-arm/plat-s3c/regs-rtc.h b/include/asm-arm/plat-s3c/regs-rtc.h
deleted file mode 100644
index d5837cf8e402..000000000000
--- a/include/asm-arm/plat-s3c/regs-rtc.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *		      http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Internal RTC register definition
-*/
-
-#ifndef __ASM_ARCH_REGS_RTC_H
-#define __ASM_ARCH_REGS_RTC_H __FILE__
-
-#define S3C2410_RTCREG(x) (x)
-
-#define S3C2410_RTCCON	      S3C2410_RTCREG(0x40)
-#define S3C2410_RTCCON_RTCEN  (1<<0)
-#define S3C2410_RTCCON_CLKSEL (1<<1)
-#define S3C2410_RTCCON_CNTSEL (1<<2)
-#define S3C2410_RTCCON_CLKRST (1<<3)
-
-#define S3C2410_TICNT	      S3C2410_RTCREG(0x44)
-#define S3C2410_TICNT_ENABLE  (1<<7)
-
-#define S3C2410_RTCALM	      S3C2410_RTCREG(0x50)
-#define S3C2410_RTCALM_ALMEN  (1<<6)
-#define S3C2410_RTCALM_YEAREN (1<<5)
-#define S3C2410_RTCALM_MONEN  (1<<4)
-#define S3C2410_RTCALM_DAYEN  (1<<3)
-#define S3C2410_RTCALM_HOUREN (1<<2)
-#define S3C2410_RTCALM_MINEN  (1<<1)
-#define S3C2410_RTCALM_SECEN  (1<<0)
-
-#define S3C2410_RTCALM_ALL \
-  S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
-  S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
-  S3C2410_RTCALM_SECEN
-
-
-#define S3C2410_ALMSEC	      S3C2410_RTCREG(0x54)
-#define S3C2410_ALMMIN	      S3C2410_RTCREG(0x58)
-#define S3C2410_ALMHOUR	      S3C2410_RTCREG(0x5c)
-
-#define S3C2410_ALMDATE	      S3C2410_RTCREG(0x60)
-#define S3C2410_ALMMON	      S3C2410_RTCREG(0x64)
-#define S3C2410_ALMYEAR	      S3C2410_RTCREG(0x68)
-
-#define S3C2410_RTCRST	      S3C2410_RTCREG(0x6c)
-
-#define S3C2410_RTCSEC	      S3C2410_RTCREG(0x70)
-#define S3C2410_RTCMIN	      S3C2410_RTCREG(0x74)
-#define S3C2410_RTCHOUR	      S3C2410_RTCREG(0x78)
-#define S3C2410_RTCDATE	      S3C2410_RTCREG(0x7c)
-#define S3C2410_RTCDAY	      S3C2410_RTCREG(0x80)
-#define S3C2410_RTCMON	      S3C2410_RTCREG(0x84)
-#define S3C2410_RTCYEAR	      S3C2410_RTCREG(0x88)
-
-
-#endif /* __ASM_ARCH_REGS_RTC_H */
diff --git a/include/asm-arm/plat-s3c/regs-serial.h b/include/asm-arm/plat-s3c/regs-serial.h
deleted file mode 100644
index a0daa647b92c..000000000000
--- a/include/asm-arm/plat-s3c/regs-serial.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-serial.h
- *
- *  From linux/include/asm-arm/hardware/serial_s3c2410.h
- *
- *  Internal header file for Samsung S3C2410 serial ports (UART0-2)
- *
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *
- *  Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
- *
- *  Adapted from:
- *
- *  Internal header file for MX1ADS serial ports (UART1 & 2)
- *
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#ifndef __ASM_ARM_REGS_SERIAL_H
-#define __ASM_ARM_REGS_SERIAL_H
-
-#define S3C24XX_VA_UART0      (S3C_VA_UART)
-#define S3C24XX_VA_UART1      (S3C_VA_UART + 0x4000 )
-#define S3C24XX_VA_UART2      (S3C_VA_UART + 0x8000 )
-#define S3C24XX_VA_UART3      (S3C_VA_UART + 0xC000 )
-
-#define S3C2410_PA_UART0      (S3C24XX_PA_UART)
-#define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
-#define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
-#define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )
-
-#define S3C2410_URXH	  (0x24)
-#define S3C2410_UTXH	  (0x20)
-#define S3C2410_ULCON	  (0x00)
-#define S3C2410_UCON	  (0x04)
-#define S3C2410_UFCON	  (0x08)
-#define S3C2410_UMCON	  (0x0C)
-#define S3C2410_UBRDIV	  (0x28)
-#define S3C2410_UTRSTAT	  (0x10)
-#define S3C2410_UERSTAT	  (0x14)
-#define S3C2410_UFSTAT	  (0x18)
-#define S3C2410_UMSTAT	  (0x1C)
-
-#define S3C2410_LCON_CFGMASK	  ((0xF<<3)|(0x3))
-
-#define S3C2410_LCON_CS5	  (0x0)
-#define S3C2410_LCON_CS6	  (0x1)
-#define S3C2410_LCON_CS7	  (0x2)
-#define S3C2410_LCON_CS8	  (0x3)
-#define S3C2410_LCON_CSMASK	  (0x3)
-
-#define S3C2410_LCON_PNONE	  (0x0)
-#define S3C2410_LCON_PEVEN	  (0x5 << 3)
-#define S3C2410_LCON_PODD	  (0x4 << 3)
-#define S3C2410_LCON_PMASK	  (0x7 << 3)
-
-#define S3C2410_LCON_STOPB	  (1<<2)
-#define S3C2410_LCON_IRM          (1<<6)
-
-#define S3C2440_UCON_CLKMASK	  (3<<10)
-#define S3C2440_UCON_PCLK	  (0<<10)
-#define S3C2440_UCON_UCLK	  (1<<10)
-#define S3C2440_UCON_PCLK2	  (2<<10)
-#define S3C2440_UCON_FCLK	  (3<<10)
-#define S3C2443_UCON_EPLL	  (3<<10)
-
-#define S3C2440_UCON2_FCLK_EN	  (1<<15)
-#define S3C2440_UCON0_DIVMASK	  (15 << 12)
-#define S3C2440_UCON1_DIVMASK	  (15 << 12)
-#define S3C2440_UCON2_DIVMASK	  (7 << 12)
-#define S3C2440_UCON_DIVSHIFT	  (12)
-
-#define S3C2412_UCON_CLKMASK	(3<<10)
-#define S3C2412_UCON_UCLK	(1<<10)
-#define S3C2412_UCON_USYSCLK	(3<<10)
-#define S3C2412_UCON_PCLK	(0<<10)
-#define S3C2412_UCON_PCLK2	(2<<10)
-
-#define S3C2410_UCON_UCLK	  (1<<10)
-#define S3C2410_UCON_SBREAK	  (1<<4)
-
-#define S3C2410_UCON_TXILEVEL	  (1<<9)
-#define S3C2410_UCON_RXILEVEL	  (1<<8)
-#define S3C2410_UCON_TXIRQMODE	  (1<<2)
-#define S3C2410_UCON_RXIRQMODE	  (1<<0)
-#define S3C2410_UCON_RXFIFO_TOI	  (1<<7)
-#define S3C2443_UCON_RXERR_IRQEN  (1<<6)
-#define S3C2443_UCON_LOOPBACK	  (1<<5)
-
-#define S3C2410_UCON_DEFAULT	  (S3C2410_UCON_TXILEVEL  | \
-				   S3C2410_UCON_RXILEVEL  | \
-				   S3C2410_UCON_TXIRQMODE | \
-				   S3C2410_UCON_RXIRQMODE | \
-				   S3C2410_UCON_RXFIFO_TOI)
-
-#define S3C2410_UFCON_FIFOMODE	  (1<<0)
-#define S3C2410_UFCON_TXTRIG0	  (0<<6)
-#define S3C2410_UFCON_RXTRIG8	  (1<<4)
-#define S3C2410_UFCON_RXTRIG12	  (2<<4)
-
-/* S3C2440 FIFO trigger levels */
-#define S3C2440_UFCON_RXTRIG1	  (0<<4)
-#define S3C2440_UFCON_RXTRIG8	  (1<<4)
-#define S3C2440_UFCON_RXTRIG16	  (2<<4)
-#define S3C2440_UFCON_RXTRIG32	  (3<<4)
-
-#define S3C2440_UFCON_TXTRIG0	  (0<<6)
-#define S3C2440_UFCON_TXTRIG16	  (1<<6)
-#define S3C2440_UFCON_TXTRIG32	  (2<<6)
-#define S3C2440_UFCON_TXTRIG48	  (3<<6)
-
-#define S3C2410_UFCON_RESETBOTH	  (3<<1)
-#define S3C2410_UFCON_RESETTX	  (1<<2)
-#define S3C2410_UFCON_RESETRX	  (1<<1)
-
-#define S3C2410_UFCON_DEFAULT	  (S3C2410_UFCON_FIFOMODE | \
-				   S3C2410_UFCON_TXTRIG0  | \
-				   S3C2410_UFCON_RXTRIG8 )
-
-#define	S3C2410_UMCOM_AFC	  (1<<4)
-#define	S3C2410_UMCOM_RTS_LOW	  (1<<0)
-
-#define S3C2412_UMCON_AFC_63	(0<<5)		/* same as s3c2443 */
-#define S3C2412_UMCON_AFC_56	(1<<5)
-#define S3C2412_UMCON_AFC_48	(2<<5)
-#define S3C2412_UMCON_AFC_40	(3<<5)
-#define S3C2412_UMCON_AFC_32	(4<<5)
-#define S3C2412_UMCON_AFC_24	(5<<5)
-#define S3C2412_UMCON_AFC_16	(6<<5)
-#define S3C2412_UMCON_AFC_8	(7<<5)
-
-#define S3C2410_UFSTAT_TXFULL	  (1<<9)
-#define S3C2410_UFSTAT_RXFULL	  (1<<8)
-#define S3C2410_UFSTAT_TXMASK	  (15<<4)
-#define S3C2410_UFSTAT_TXSHIFT	  (4)
-#define S3C2410_UFSTAT_RXMASK	  (15<<0)
-#define S3C2410_UFSTAT_RXSHIFT	  (0)
-
-/* UFSTAT S3C2443 same as S3C2440 */
-#define S3C2440_UFSTAT_TXFULL	  (1<<14)
-#define S3C2440_UFSTAT_RXFULL	  (1<<6)
-#define S3C2440_UFSTAT_TXSHIFT	  (8)
-#define S3C2440_UFSTAT_RXSHIFT	  (0)
-#define S3C2440_UFSTAT_TXMASK	  (63<<8)
-#define S3C2440_UFSTAT_RXMASK	  (63)
-
-#define S3C2410_UTRSTAT_TXE	  (1<<2)
-#define S3C2410_UTRSTAT_TXFE	  (1<<1)
-#define S3C2410_UTRSTAT_RXDR	  (1<<0)
-
-#define S3C2410_UERSTAT_OVERRUN	  (1<<0)
-#define S3C2410_UERSTAT_FRAME	  (1<<2)
-#define S3C2410_UERSTAT_BREAK	  (1<<3)
-#define S3C2443_UERSTAT_PARITY	  (1<<1)
-
-#define S3C2410_UERSTAT_ANY	  (S3C2410_UERSTAT_OVERRUN | \
-				   S3C2410_UERSTAT_FRAME | \
-				   S3C2410_UERSTAT_BREAK)
-
-#define S3C2410_UMSTAT_CTS	  (1<<0)
-#define S3C2410_UMSTAT_DeltaCTS	  (1<<2)
-
-#define S3C2443_DIVSLOT		  (0x2C)
-
-#ifndef __ASSEMBLY__
-
-/* struct s3c24xx_uart_clksrc
- *
- * this structure defines a named clock source that can be used for the
- * uart, so that the best clock can be selected for the requested baud
- * rate.
- *
- * min_baud and max_baud define the range of baud-rates this clock is
- * acceptable for, if they are both zero, it is assumed any baud rate that
- * can be generated from this clock will be used.
- *
- * divisor gives the divisor from the clock to the one seen by the uart
-*/
-
-struct s3c24xx_uart_clksrc {
-	const char	*name;
-	unsigned int	 divisor;
-	unsigned int	 min_baud;
-	unsigned int	 max_baud;
-};
-
-/* configuration structure for per-machine configurations for the
- * serial port
- *
- * the pointer is setup by the machine specific initialisation from the
- * arch/arm/mach-s3c2410/ directory.
-*/
-
-struct s3c2410_uartcfg {
-	unsigned char	   hwport;	 /* hardware port number */
-	unsigned char	   unused;
-	unsigned short	   flags;
-	upf_t		   uart_flags;	 /* default uart flags */
-
-	unsigned long	   ucon;	 /* value of ucon for port */
-	unsigned long	   ulcon;	 /* value of ulcon for port */
-	unsigned long	   ufcon;	 /* value of ufcon for port */
-
-	struct s3c24xx_uart_clksrc *clocks;
-	unsigned int		    clocks_size;
-};
-
-/* s3c24xx_uart_devs
- *
- * this is exported from the core as we cannot use driver_register(),
- * or platform_add_device() before the console_initcall()
-*/
-
-extern struct platform_device *s3c24xx_uart_devs[3];
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ASM_ARM_REGS_SERIAL_H */
-
diff --git a/include/asm-arm/plat-s3c/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h
deleted file mode 100644
index cc0eedd53e38..000000000000
--- a/include/asm-arm/plat-s3c/regs-timer.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-timer.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *		      http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Timer configuration
-*/
-
-
-#ifndef __ASM_ARCH_REGS_TIMER_H
-#define __ASM_ARCH_REGS_TIMER_H
-
-#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
-#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
-
-#define S3C2410_TCFG0	      S3C_TIMERREG(0x00)
-#define S3C2410_TCFG1	      S3C_TIMERREG(0x04)
-#define S3C2410_TCON	      S3C_TIMERREG(0x08)
-
-#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
-#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
-#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
-#define S3C2410_TCFG_DEADZONE_MASK   (255<<16)
-#define S3C2410_TCFG_DEADZONE_SHIFT  (16)
-
-#define S3C2410_TCFG1_MUX4_DIV2	  (0<<16)
-#define S3C2410_TCFG1_MUX4_DIV4	  (1<<16)
-#define S3C2410_TCFG1_MUX4_DIV8	  (2<<16)
-#define S3C2410_TCFG1_MUX4_DIV16  (3<<16)
-#define S3C2410_TCFG1_MUX4_TCLK1  (4<<16)
-#define S3C2410_TCFG1_MUX4_MASK	  (15<<16)
-#define S3C2410_TCFG1_MUX4_SHIFT  (16)
-
-#define S3C2410_TCFG1_MUX3_DIV2	  (0<<12)
-#define S3C2410_TCFG1_MUX3_DIV4	  (1<<12)
-#define S3C2410_TCFG1_MUX3_DIV8	  (2<<12)
-#define S3C2410_TCFG1_MUX3_DIV16  (3<<12)
-#define S3C2410_TCFG1_MUX3_TCLK1  (4<<12)
-#define S3C2410_TCFG1_MUX3_MASK	  (15<<12)
-
-
-#define S3C2410_TCFG1_MUX2_DIV2	  (0<<8)
-#define S3C2410_TCFG1_MUX2_DIV4	  (1<<8)
-#define S3C2410_TCFG1_MUX2_DIV8	  (2<<8)
-#define S3C2410_TCFG1_MUX2_DIV16  (3<<8)
-#define S3C2410_TCFG1_MUX2_TCLK1  (4<<8)
-#define S3C2410_TCFG1_MUX2_MASK	  (15<<8)
-
-
-#define S3C2410_TCFG1_MUX1_DIV2	  (0<<4)
-#define S3C2410_TCFG1_MUX1_DIV4	  (1<<4)
-#define S3C2410_TCFG1_MUX1_DIV8	  (2<<4)
-#define S3C2410_TCFG1_MUX1_DIV16  (3<<4)
-#define S3C2410_TCFG1_MUX1_TCLK0  (4<<4)
-#define S3C2410_TCFG1_MUX1_MASK	  (15<<4)
-
-#define S3C2410_TCFG1_MUX0_DIV2	  (0<<0)
-#define S3C2410_TCFG1_MUX0_DIV4	  (1<<0)
-#define S3C2410_TCFG1_MUX0_DIV8	  (2<<0)
-#define S3C2410_TCFG1_MUX0_DIV16  (3<<0)
-#define S3C2410_TCFG1_MUX0_TCLK0  (4<<0)
-#define S3C2410_TCFG1_MUX0_MASK	  (15<<0)
-
-#define S3C2410_TCFG1_MUX_DIV2	  (0<<0)
-#define S3C2410_TCFG1_MUX_DIV4	  (1<<0)
-#define S3C2410_TCFG1_MUX_DIV8	  (2<<0)
-#define S3C2410_TCFG1_MUX_DIV16   (3<<0)
-#define S3C2410_TCFG1_MUX_TCLK    (4<<0)
-#define S3C2410_TCFG1_MUX_MASK	  (15<<0)
-
-#define S3C2410_TCFG1_SHIFT(x)	  ((x) * 4)
-
-/* for each timer, we have an count buffer, an compare buffer and
- * an observation buffer
-*/
-
-/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
-
-#define S3C2410_TCNTB(tmr)    S3C_TIMERREG2(tmr, 0x00)
-#define S3C2410_TCMPB(tmr)    S3C_TIMERREG2(tmr, 0x04)
-#define S3C2410_TCNTO(tmr)    S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
-
-#define S3C2410_TCON_T4RELOAD	  (1<<22)
-#define S3C2410_TCON_T4MANUALUPD  (1<<21)
-#define S3C2410_TCON_T4START	  (1<<20)
-
-#define S3C2410_TCON_T3RELOAD	  (1<<19)
-#define S3C2410_TCON_T3INVERT	  (1<<18)
-#define S3C2410_TCON_T3MANUALUPD  (1<<17)
-#define S3C2410_TCON_T3START	  (1<<16)
-
-#define S3C2410_TCON_T2RELOAD	  (1<<15)
-#define S3C2410_TCON_T2INVERT	  (1<<14)
-#define S3C2410_TCON_T2MANUALUPD  (1<<13)
-#define S3C2410_TCON_T2START	  (1<<12)
-
-#define S3C2410_TCON_T1RELOAD	  (1<<11)
-#define S3C2410_TCON_T1INVERT	  (1<<10)
-#define S3C2410_TCON_T1MANUALUPD  (1<<9)
-#define S3C2410_TCON_T1START	  (1<<8)
-
-#define S3C2410_TCON_T0DEADZONE	  (1<<4)
-#define S3C2410_TCON_T0RELOAD	  (1<<3)
-#define S3C2410_TCON_T0INVERT	  (1<<2)
-#define S3C2410_TCON_T0MANUALUPD  (1<<1)
-#define S3C2410_TCON_T0START	  (1<<0)
-
-#endif /*  __ASM_ARCH_REGS_TIMER_H */
-
-
-
diff --git a/include/asm-arm/plat-s3c/regs-watchdog.h b/include/asm-arm/plat-s3c/regs-watchdog.h
deleted file mode 100644
index 4938492470f7..000000000000
--- a/include/asm-arm/plat-s3c/regs-watchdog.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *		      http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Watchdog timer control
-*/
-
-
-#ifndef __ASM_ARCH_REGS_WATCHDOG_H
-#define __ASM_ARCH_REGS_WATCHDOG_H
-
-#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
-
-#define S3C2410_WTCON	   S3C_WDOGREG(0x00)
-#define S3C2410_WTDAT	   S3C_WDOGREG(0x04)
-#define S3C2410_WTCNT	   S3C_WDOGREG(0x08)
-
-/* the watchdog can either generate a reset pulse, or an
- * interrupt.
- */
-
-#define S3C2410_WTCON_RSTEN   (0x01)
-#define S3C2410_WTCON_INTEN   (1<<2)
-#define S3C2410_WTCON_ENABLE  (1<<5)
-
-#define S3C2410_WTCON_DIV16   (0<<3)
-#define S3C2410_WTCON_DIV32   (1<<3)
-#define S3C2410_WTCON_DIV64   (2<<3)
-#define S3C2410_WTCON_DIV128  (3<<3)
-
-#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
-#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
-
-#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
-
-
diff --git a/include/asm-arm/plat-s3c/uncompress.h b/include/asm-arm/plat-s3c/uncompress.h
deleted file mode 100644
index 19b9eda39485..000000000000
--- a/include/asm-arm/plat-s3c/uncompress.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* linux/include/asm-arm/plat-s3c/uncompress.h
- *
- * Copyright 2003, 2007 Simtec Electronics
- *	http://armlinux.simtec.co.uk/
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * S3C - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_UNCOMPRESS_H
-#define __ASM_PLAT_UNCOMPRESS_H
-
-typedef unsigned int upf_t;	/* cannot include linux/serial_core.h */
-
-/* uart setup */
-
-static unsigned int fifo_mask;
-static unsigned int fifo_max;
-
-/* forward declerations */
-
-static void arch_detect_cpu(void);
-
-/* defines for UART registers */
-
-#include <asm/plat-s3c/regs-serial.h>
-#include <asm/plat-s3c/regs-watchdog.h>
-
-/* working in physical space... */
-#undef S3C2410_WDOGREG
-#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
-
-/* how many bytes we allow into the FIFO at a time in FIFO mode */
-#define FIFO_MAX	 (14)
-
-#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
-
-static __inline__ void
-uart_wr(unsigned int reg, unsigned int val)
-{
-	volatile unsigned int *ptr;
-
-	ptr = (volatile unsigned int *)(reg + uart_base);
-	*ptr = val;
-}
-
-static __inline__ unsigned int
-uart_rd(unsigned int reg)
-{
-	volatile unsigned int *ptr;
-
-	ptr = (volatile unsigned int *)(reg + uart_base);
-	return *ptr;
-}
-
-/* we can deal with the case the UARTs are being run
- * in FIFO mode, so that we don't hold up our execution
- * waiting for tx to happen...
-*/
-
-static void putc(int ch)
-{
-	if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
-		int level;
-
-		while (1) {
-			level = uart_rd(S3C2410_UFSTAT);
-			level &= fifo_mask;
-
-			if (level < fifo_max)
-				break;
-		}
-
-	} else {
-		/* not using fifos */
-
-		while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
-			barrier();
-	}
-
-	/* write byte to transmission register */
-	uart_wr(S3C2410_UTXH, ch);
-}
-
-static inline void flush(void)
-{
-}
-
-#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
-
-/* CONFIG_S3C_BOOT_WATCHDOG
- *
- * Simple boot-time watchdog setup, to reboot the system if there is
- * any problem with the boot process
-*/
-
-#ifdef CONFIG_S3C_BOOT_WATCHDOG
-
-#define WDOG_COUNT (0xff00)
-
-static inline void arch_decomp_wdog(void)
-{
-	__raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-}
-
-static void arch_decomp_wdog_start(void)
-{
-	__raw_writel(WDOG_COUNT, S3C2410_WTDAT);
-	__raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-	__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
-}
-
-#else
-#define arch_decomp_wdog_start()
-#define arch_decomp_wdog()
-#endif
-
-#ifdef CONFIG_S3C_BOOT_ERROR_RESET
-
-static void arch_decomp_error(const char *x)
-{
-	putstr("\n\n");
-	putstr(x);
-	putstr("\n\n -- System resetting\n");
-
-	__raw_writel(0x4000, S3C2410_WTDAT);
-	__raw_writel(0x4000, S3C2410_WTCNT);
-	__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
-
-	while(1);
-}
-
-#define arch_error arch_decomp_error
-#endif
-
-static void error(char *err);
-
-static void
-arch_decomp_setup(void)
-{
-	/* we may need to setup the uart(s) here if we are not running
-	 * on an BAST... the BAST will have left the uarts configured
-	 * after calling linux.
-	 */
-
-	arch_detect_cpu();
-	arch_decomp_wdog_start();
-}
-
-
-#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/include/asm-arm/plat-s3c24xx/clock.h b/include/asm-arm/plat-s3c24xx/clock.h
deleted file mode 100644
index 235b753cd877..000000000000
--- a/include/asm-arm/plat-s3c24xx/clock.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/clock.h
- * linux/arch/arm/mach-s3c2410/clock.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *	http://www.simtec.co.uk/products/SWLINUX/
- *	Written by Ben Dooks, <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct clk {
-	struct list_head      list;
-	struct module        *owner;
-	struct clk           *parent;
-	const char           *name;
-	int		      id;
-	int		      usage;
-	unsigned long         rate;
-	unsigned long         ctrlbit;
-
-	int		    (*enable)(struct clk *, int enable);
-	int		    (*set_rate)(struct clk *c, unsigned long rate);
-	unsigned long	    (*get_rate)(struct clk *c);
-	unsigned long	    (*round_rate)(struct clk *c, unsigned long rate);
-	int		    (*set_parent)(struct clk *c, struct clk *parent);
-};
-
-/* other clocks which may be registered by board support */
-
-extern struct clk s3c24xx_dclk0;
-extern struct clk s3c24xx_dclk1;
-extern struct clk s3c24xx_clkout0;
-extern struct clk s3c24xx_clkout1;
-extern struct clk s3c24xx_uclk;
-
-extern struct clk clk_usb_bus;
-
-/* core clock support */
-
-extern struct clk clk_f;
-extern struct clk clk_h;
-extern struct clk clk_p;
-extern struct clk clk_mpll;
-extern struct clk clk_upll;
-extern struct clk clk_xtal;
-
-/* exports for arch/arm/mach-s3c2410
- *
- * Please DO NOT use these outside of arch/arm/mach-s3c2410
-*/
-
-extern struct mutex clocks_mutex;
-
-extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
-
-extern int s3c24xx_register_clock(struct clk *clk);
-extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
-
-extern int s3c24xx_setup_clocks(unsigned long xtal,
-				unsigned long fclk,
-				unsigned long hclk,
-				unsigned long pclk);
diff --git a/include/asm-arm/plat-s3c24xx/common-smdk.h b/include/asm-arm/plat-s3c24xx/common-smdk.h
deleted file mode 100644
index 58d9094c935c..000000000000
--- a/include/asm-arm/plat-s3c24xx/common-smdk.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/common-smdk.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * Common code for SMDK2410 and SMDK2440 boards
- *
- * http://www.fluff.org/ben/smdk2440/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-extern void smdk_machine_init(void);
diff --git a/include/asm-arm/plat-s3c24xx/cpu.h b/include/asm-arm/plat-s3c24xx/cpu.h
deleted file mode 100644
index 23e420e8bd5b..000000000000
--- a/include/asm-arm/plat-s3c24xx/cpu.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/cpu.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C24XX CPU support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* todo - fix when rmk changes iodescs to use `void __iomem *` */
-
-#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
-
-#ifndef MHZ
-#define MHZ (1000*1000)
-#endif
-
-#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000)
-
-/* forward declaration */
-struct s3c24xx_uart_resources;
-struct platform_device;
-struct s3c2410_uartcfg;
-struct map_desc;
-
-/* core initialisation functions */
-
-extern void s3c24xx_init_irq(void);
-
-extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
-
-extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c24xx_init_clocks(int xtal);
-
-extern void s3c24xx_init_uartdevs(char *name,
-				  struct s3c24xx_uart_resources *res,
-				  struct s3c2410_uartcfg *cfg, int no);
-
-/* timer for 2410/2440 */
-
-struct sys_timer;
-extern struct sys_timer s3c24xx_timer;
-
-/* system device classes */
-
-extern struct sysdev_class s3c2410_sysclass;
-extern struct sysdev_class s3c2412_sysclass;
-extern struct sysdev_class s3c2440_sysclass;
-extern struct sysdev_class s3c2442_sysclass;
-extern struct sysdev_class s3c2443_sysclass;
diff --git a/include/asm-arm/plat-s3c24xx/devs.h b/include/asm-arm/plat-s3c24xx/devs.h
deleted file mode 100644
index badaac9d64a8..000000000000
--- a/include/asm-arm/plat-s3c24xx/devs.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/devs.h
- *
- * Copyright (c) 2004 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2410 standard platform devices
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/platform_device.h>
-
-struct s3c24xx_uart_resources {
-	struct resource		*resources;
-	unsigned long		 nr_resources;
-};
-
-extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
-
-extern struct platform_device *s3c24xx_uart_devs[];
-extern struct platform_device *s3c24xx_uart_src[];
-
-extern struct platform_device s3c_device_timer[];
-
-extern struct platform_device s3c_device_usb;
-extern struct platform_device s3c_device_lcd;
-extern struct platform_device s3c_device_wdt;
-extern struct platform_device s3c_device_i2c;
-extern struct platform_device s3c_device_iis;
-extern struct platform_device s3c_device_rtc;
-extern struct platform_device s3c_device_adc;
-extern struct platform_device s3c_device_sdi;
-extern struct platform_device s3c_device_hsmmc;
-
-extern struct platform_device s3c_device_spi0;
-extern struct platform_device s3c_device_spi1;
-
-extern struct platform_device s3c_device_nand;
-
-extern struct platform_device s3c_device_usbgadget;
-
-/* s3c2440 specific devices */
-
-#ifdef CONFIG_CPU_S3C2440
-
-extern struct platform_device s3c_device_camif;
-
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/dma.h b/include/asm-arm/plat-s3c24xx/dma.h
deleted file mode 100644
index c78efe316fc8..000000000000
--- a/include/asm-arm/plat-s3c24xx/dma.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/dma.h
- *
- * Copyright (C) 2006 Simtec Electronics
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * Samsung S3C24XX DMA support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-extern struct sysdev_class dma_sysclass;
-extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
-
-#define DMA_CH_VALID		(1<<31)
-#define DMA_CH_NEVER		(1<<30)
-
-struct s3c24xx_dma_addr {
-	unsigned long		from;
-	unsigned long		to;
-};
-
-/* struct s3c24xx_dma_map
- *
- * this holds the mapping information for the channel selected
- * to be connected to the specified device
-*/
-
-struct s3c24xx_dma_map {
-	const char		*name;
-	struct s3c24xx_dma_addr  hw_addr;
-
-	unsigned long		 channels[S3C2410_DMA_CHANNELS];
-	unsigned long		 channels_rx[S3C2410_DMA_CHANNELS];
-};
-
-struct s3c24xx_dma_selection {
-	struct s3c24xx_dma_map	*map;
-	unsigned long		 map_size;
-	unsigned long		 dcon_mask;
-
-	void	(*select)(struct s3c2410_dma_chan *chan,
-			  struct s3c24xx_dma_map *map);
-
-	void	(*direction)(struct s3c2410_dma_chan *chan,
-			     struct s3c24xx_dma_map *map,
-			     enum s3c2410_dmasrc dir);
-};
-
-extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
-
-/* struct s3c24xx_dma_order_ch
- *
- * channel map for one of the `enum dma_ch` dma channels. the list
- * entry contains a set of low-level channel numbers, orred with
- * DMA_CH_VALID, which are checked in the order in the array.
-*/
-
-struct s3c24xx_dma_order_ch {
-	unsigned int	list[S3C2410_DMA_CHANNELS];	/* list of channels */
-	unsigned int	flags;				/* flags */
-};
-
-/* struct s3c24xx_dma_order
- *
- * information provided by either the core or the board to give the
- * dma system a hint on how to allocate channels
-*/
-
-struct s3c24xx_dma_order {
-	struct s3c24xx_dma_order_ch	channels[DMACH_MAX];
-};
-
-extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map);
-
-/* DMA init code, called from the cpu support code */
-
-extern int s3c2410_dma_init(void);
-
-extern int s3c24xx_dma_init(unsigned int channels, unsigned int irq,
-			    unsigned int stride);
diff --git a/include/asm-arm/plat-s3c24xx/irq.h b/include/asm-arm/plat-s3c24xx/irq.h
deleted file mode 100644
index 45746a995343..000000000000
--- a/include/asm-arm/plat-s3c24xx/irq.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/irq.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C24XX CPU IRQ support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define irqdbf(x...)
-#define irqdbf2(x...)
-
-#define EXTINT_OFF (IRQ_EINT4 - 4)
-
-/* these are exported for arch/arm/mach-* usage */
-extern struct irq_chip s3c_irq_level_chip;
-extern struct irq_chip s3c_irq_chip;
-
-static inline void
-s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
-		int subcheck)
-{
-	unsigned long mask;
-	unsigned long submask;
-
-	submask = __raw_readl(S3C2410_INTSUBMSK);
-	mask = __raw_readl(S3C2410_INTMSK);
-
-	submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
-
-	/* check to see if we need to mask the parent IRQ */
-
-	if ((submask  & subcheck) == subcheck) {
-		__raw_writel(mask | parentbit, S3C2410_INTMSK);
-	}
-
-	/* write back masks */
-	__raw_writel(submask, S3C2410_INTSUBMSK);
-
-}
-
-static inline void
-s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
-{
-	unsigned long mask;
-	unsigned long submask;
-
-	submask = __raw_readl(S3C2410_INTSUBMSK);
-	mask = __raw_readl(S3C2410_INTMSK);
-
-	submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
-	mask &= ~parentbit;
-
-	/* write back masks */
-	__raw_writel(submask, S3C2410_INTSUBMSK);
-	__raw_writel(mask, S3C2410_INTMSK);
-}
-
-
-static inline void
-s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
-{
-	unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
-
-	s3c_irqsub_mask(irqno, parentmask, group);
-
-	__raw_writel(bit, S3C2410_SUBSRCPND);
-
-	/* only ack parent if we've got all the irqs (seems we must
-	 * ack, all and hope that the irq system retriggers ok when
-	 * the interrupt goes off again)
-	 */
-
-	if (1) {
-		__raw_writel(parentmask, S3C2410_SRCPND);
-		__raw_writel(parentmask, S3C2410_INTPND);
-	}
-}
-
-static inline void
-s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
-{
-	unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
-
-	__raw_writel(bit, S3C2410_SUBSRCPND);
-
-	/* only ack parent if we've got all the irqs (seems we must
-	 * ack, all and hope that the irq system retriggers ok when
-	 * the interrupt goes off again)
-	 */
-
-	if (1) {
-		__raw_writel(parentmask, S3C2410_SRCPND);
-		__raw_writel(parentmask, S3C2410_INTPND);
-	}
-}
-
-/* exported for use in arch/arm/mach-s3c2410 */
-
-#ifdef CONFIG_PM
-extern int s3c_irq_wake(unsigned int irqno, unsigned int state);
-#else
-#define s3c_irq_wake NULL
-#endif
-
-extern int s3c_irqext_type(unsigned int irq, unsigned int type);
diff --git a/include/asm-arm/plat-s3c24xx/mci.h b/include/asm-arm/plat-s3c24xx/mci.h
deleted file mode 100644
index 2d0852ac3b27..000000000000
--- a/include/asm-arm/plat-s3c24xx/mci.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef _ARCH_MCI_H
-#define _ARCH_MCI_H
-
-struct s3c24xx_mci_pdata {
-	unsigned int	wprotect_invert : 1;
-	unsigned int	detect_invert : 1;   /* set => detect active high. */
-
-	unsigned int	gpio_detect;
-	unsigned int	gpio_wprotect;
-	unsigned long	ocr_avail;
-	void		(*set_power)(unsigned char power_mode,
-				     unsigned short vdd);
-};
-
-#endif /* _ARCH_NCI_H */
diff --git a/include/asm-arm/plat-s3c24xx/pm.h b/include/asm-arm/plat-s3c24xx/pm.h
deleted file mode 100644
index cc623667e48a..000000000000
--- a/include/asm-arm/plat-s3c24xx/pm.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/pm.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *	Written by Ben Dooks, <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* s3c2410_pm_init
- *
- * called from board at initialisation time to setup the power
- * management
-*/
-
-#ifdef CONFIG_PM
-
-extern __init int s3c2410_pm_init(void);
-
-#else
-
-static inline int s3c2410_pm_init(void)
-{
-	return 0;
-}
-#endif
-
-/* configuration for the IRQ mask over sleep */
-extern unsigned long s3c_irqwake_intmask;
-extern unsigned long s3c_irqwake_eintmask;
-
-/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
-extern unsigned long s3c_irqwake_intallow;
-extern unsigned long s3c_irqwake_eintallow;
-
-/* per-cpu sleep functions */
-
-extern void (*pm_cpu_prep)(void);
-extern void (*pm_cpu_sleep)(void);
-
-/* Flags for PM Control */
-
-extern unsigned long s3c_pm_flags;
-
-/* from sleep.S */
-
-extern int  s3c2410_cpu_save(unsigned long *saveblk);
-extern void s3c2410_cpu_suspend(void);
-extern void s3c2410_cpu_resume(void);
-
-extern unsigned long s3c2410_sleep_save_phys;
-
-/* sleep save info */
-
-struct sleep_save {
-	void __iomem	*reg;
-	unsigned long	val;
-};
-
-#define SAVE_ITEM(x) \
-	{ .reg = (x) }
-
-extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count);
-extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count);
-
-#ifdef CONFIG_PM
-extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
-extern int s3c24xx_irq_resume(struct sys_device *dev);
-#else
-#define s3c24xx_irq_suspend NULL
-#define s3c24xx_irq_resume  NULL
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/regs-spi.h b/include/asm-arm/plat-s3c24xx/regs-spi.h
deleted file mode 100644
index 2b35479ee35c..000000000000
--- a/include/asm-arm/plat-s3c24xx/regs-spi.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-spi.h
- *
- * Copyright (c) 2004 Fetron GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 SPI register definition
-*/
-
-#ifndef __ASM_ARCH_REGS_SPI_H
-#define __ASM_ARCH_REGS_SPI_H
-
-#define S3C2410_SPI1	(0x20)
-#define S3C2412_SPI1	(0x100)
-
-#define S3C2410_SPCON	(0x00)
-
-#define S3C2412_SPCON_RXFIFO_RB2	(0<<14)
-#define S3C2412_SPCON_RXFIFO_RB4	(1<<14)
-#define S3C2412_SPCON_RXFIFO_RB12	(2<<14)
-#define S3C2412_SPCON_RXFIFO_RB14	(3<<14)
-#define S3C2412_SPCON_TXFIFO_RB2	(0<<12)
-#define S3C2412_SPCON_TXFIFO_RB4	(1<<12)
-#define S3C2412_SPCON_TXFIFO_RB12	(2<<12)
-#define S3C2412_SPCON_TXFIFO_RB14	(3<<12)
-#define S3C2412_SPCON_RXFIFO_RESET	(1<<11) /* RxFIFO reset */
-#define S3C2412_SPCON_TXFIFO_RESET	(1<<10) /* TxFIFO reset */
-#define S3C2412_SPCON_RXFIFO_EN		(1<<9)  /* RxFIFO Enable */
-#define S3C2412_SPCON_TXFIFO_EN		(1<<8)  /* TxFIFO Enable */
-
-#define S3C2412_SPCON_DIRC_RX	  (1<<7)
-
-#define S3C2410_SPCON_SMOD_DMA	  (2<<5)	/* DMA mode */
-#define S3C2410_SPCON_SMOD_INT	  (1<<5)	/* interrupt mode */
-#define S3C2410_SPCON_SMOD_POLL   (0<<5)	/* polling mode */
-#define S3C2410_SPCON_ENSCK	  (1<<4)	/* Enable SCK */
-#define S3C2410_SPCON_MSTR	  (1<<3)	/* Master/Slave select
-						   0: slave, 1: master */
-#define S3C2410_SPCON_CPOL_HIGH	  (1<<2)	/* Clock polarity select */
-#define S3C2410_SPCON_CPOL_LOW	  (0<<2)	/* Clock polarity select */
-
-#define S3C2410_SPCON_CPHA_FMTB	  (1<<1)	/* Clock Phase Select */
-#define S3C2410_SPCON_CPHA_FMTA	  (0<<1)	/* Clock Phase Select */
-
-#define S3C2410_SPCON_TAGD	  (1<<0)	/* Tx auto garbage data mode */
-
-
-#define S3C2410_SPSTA	 (0x04)
-
-#define S3C2412_SPSTA_RXFIFO_AE		(1<<11)
-#define S3C2412_SPSTA_TXFIFO_AE		(1<<10)
-#define S3C2412_SPSTA_RXFIFO_ERROR	(1<<9)
-#define S3C2412_SPSTA_TXFIFO_ERROR	(1<<8)
-#define S3C2412_SPSTA_RXFIFO_FIFO	(1<<7)
-#define S3C2412_SPSTA_RXFIFO_EMPTY	(1<<6)
-#define S3C2412_SPSTA_TXFIFO_NFULL	(1<<5)
-#define S3C2412_SPSTA_TXFIFO_EMPTY	(1<<4)
-
-#define S3C2410_SPSTA_DCOL	  (1<<2)	/* Data Collision Error */
-#define S3C2410_SPSTA_MULD	  (1<<1)	/* Multi Master Error */
-#define S3C2410_SPSTA_READY	  (1<<0)	/* Data Tx/Rx ready */
-#define S3C2412_SPSTA_READY_ORG	  (1<<3)
-
-#define S3C2410_SPPIN	 (0x08)
-
-#define S3C2410_SPPIN_ENMUL	  (1<<2)	/* Multi Master Error detect */
-#define S3C2410_SPPIN_RESERVED	  (1<<1)
-#define S3C2400_SPPIN_nCS     	  (1<<1)	/* SPI Card Select */
-#define S3C2410_SPPIN_KEEP	  (1<<0)	/* Master Out keep */
-
-#define S3C2410_SPPRE	 (0x0C)
-#define S3C2410_SPTDAT	 (0x10)
-#define S3C2410_SPRDAT	 (0x14)
-
-#define S3C2412_TXFIFO	 (0x18)
-#define S3C2412_RXFIFO	 (0x18)
-#define S3C2412_SPFIC	 (0x24)
-
-
-#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/include/asm-arm/plat-s3c24xx/regs-udc.h b/include/asm-arm/plat-s3c24xx/regs-udc.h
deleted file mode 100644
index f0dd4a41b37b..000000000000
--- a/include/asm-arm/plat-s3c24xx/regs-udc.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-udc.h
- *
- * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
- *
- * This include file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
-*/
-
-#ifndef __ASM_ARCH_REGS_UDC_H
-#define __ASM_ARCH_REGS_UDC_H
-
-#define S3C2410_USBDREG(x) (x)
-
-#define S3C2410_UDC_FUNC_ADDR_REG	S3C2410_USBDREG(0x0140)
-#define S3C2410_UDC_PWR_REG		S3C2410_USBDREG(0x0144)
-#define S3C2410_UDC_EP_INT_REG		S3C2410_USBDREG(0x0148)
-
-#define S3C2410_UDC_USB_INT_REG		S3C2410_USBDREG(0x0158)
-#define S3C2410_UDC_EP_INT_EN_REG	S3C2410_USBDREG(0x015c)
-
-#define S3C2410_UDC_USB_INT_EN_REG	S3C2410_USBDREG(0x016c)
-
-#define S3C2410_UDC_FRAME_NUM1_REG	S3C2410_USBDREG(0x0170)
-#define S3C2410_UDC_FRAME_NUM2_REG	S3C2410_USBDREG(0x0174)
-
-#define S3C2410_UDC_EP0_FIFO_REG	S3C2410_USBDREG(0x01c0)
-#define S3C2410_UDC_EP1_FIFO_REG	S3C2410_USBDREG(0x01c4)
-#define S3C2410_UDC_EP2_FIFO_REG	S3C2410_USBDREG(0x01c8)
-#define S3C2410_UDC_EP3_FIFO_REG	S3C2410_USBDREG(0x01cc)
-#define S3C2410_UDC_EP4_FIFO_REG	S3C2410_USBDREG(0x01d0)
-
-#define S3C2410_UDC_EP1_DMA_CON		S3C2410_USBDREG(0x0200)
-#define S3C2410_UDC_EP1_DMA_UNIT	S3C2410_USBDREG(0x0204)
-#define S3C2410_UDC_EP1_DMA_FIFO	S3C2410_USBDREG(0x0208)
-#define S3C2410_UDC_EP1_DMA_TTC_L	S3C2410_USBDREG(0x020c)
-#define S3C2410_UDC_EP1_DMA_TTC_M	S3C2410_USBDREG(0x0210)
-#define S3C2410_UDC_EP1_DMA_TTC_H	S3C2410_USBDREG(0x0214)
-
-#define S3C2410_UDC_EP2_DMA_CON		S3C2410_USBDREG(0x0218)
-#define S3C2410_UDC_EP2_DMA_UNIT	S3C2410_USBDREG(0x021c)
-#define S3C2410_UDC_EP2_DMA_FIFO	S3C2410_USBDREG(0x0220)
-#define S3C2410_UDC_EP2_DMA_TTC_L	S3C2410_USBDREG(0x0224)
-#define S3C2410_UDC_EP2_DMA_TTC_M	S3C2410_USBDREG(0x0228)
-#define S3C2410_UDC_EP2_DMA_TTC_H	S3C2410_USBDREG(0x022c)
-
-#define S3C2410_UDC_EP3_DMA_CON		S3C2410_USBDREG(0x0240)
-#define S3C2410_UDC_EP3_DMA_UNIT	S3C2410_USBDREG(0x0244)
-#define S3C2410_UDC_EP3_DMA_FIFO	S3C2410_USBDREG(0x0248)
-#define S3C2410_UDC_EP3_DMA_TTC_L	S3C2410_USBDREG(0x024c)
-#define S3C2410_UDC_EP3_DMA_TTC_M	S3C2410_USBDREG(0x0250)
-#define S3C2410_UDC_EP3_DMA_TTC_H	S3C2410_USBDREG(0x0254)
-
-#define S3C2410_UDC_EP4_DMA_CON		S3C2410_USBDREG(0x0258)
-#define S3C2410_UDC_EP4_DMA_UNIT	S3C2410_USBDREG(0x025c)
-#define S3C2410_UDC_EP4_DMA_FIFO	S3C2410_USBDREG(0x0260)
-#define S3C2410_UDC_EP4_DMA_TTC_L	S3C2410_USBDREG(0x0264)
-#define S3C2410_UDC_EP4_DMA_TTC_M	S3C2410_USBDREG(0x0268)
-#define S3C2410_UDC_EP4_DMA_TTC_H	S3C2410_USBDREG(0x026c)
-
-#define S3C2410_UDC_INDEX_REG		S3C2410_USBDREG(0x0178)
-
-/* indexed registers */
-
-#define S3C2410_UDC_MAXP_REG		S3C2410_USBDREG(0x0180)
-
-#define S3C2410_UDC_EP0_CSR_REG		S3C2410_USBDREG(0x0184)
-
-#define S3C2410_UDC_IN_CSR1_REG		S3C2410_USBDREG(0x0184)
-#define S3C2410_UDC_IN_CSR2_REG		S3C2410_USBDREG(0x0188)
-
-#define S3C2410_UDC_OUT_CSR1_REG	S3C2410_USBDREG(0x0190)
-#define S3C2410_UDC_OUT_CSR2_REG	S3C2410_USBDREG(0x0194)
-#define S3C2410_UDC_OUT_FIFO_CNT1_REG	S3C2410_USBDREG(0x0198)
-#define S3C2410_UDC_OUT_FIFO_CNT2_REG	S3C2410_USBDREG(0x019c)
-
-#define S3C2410_UDC_FUNCADDR_UPDATE	(1<<7)
-
-#define S3C2410_UDC_PWR_ISOUP		(1<<7) // R/W
-#define S3C2410_UDC_PWR_RESET		(1<<3) // R
-#define S3C2410_UDC_PWR_RESUME		(1<<2) // R/W
-#define S3C2410_UDC_PWR_SUSPEND		(1<<1) // R
-#define S3C2410_UDC_PWR_ENSUSPEND	(1<<0) // R/W
-
-#define S3C2410_UDC_PWR_DEFAULT		0x00
-
-#define S3C2410_UDC_INT_EP4		(1<<4) // R/W (clear only)
-#define S3C2410_UDC_INT_EP3		(1<<3) // R/W (clear only)
-#define S3C2410_UDC_INT_EP2		(1<<2) // R/W (clear only)
-#define S3C2410_UDC_INT_EP1		(1<<1) // R/W (clear only)
-#define S3C2410_UDC_INT_EP0		(1<<0) // R/W (clear only)
-
-#define S3C2410_UDC_USBINT_RESET	(1<<2) // R/W (clear only)
-#define S3C2410_UDC_USBINT_RESUME	(1<<1) // R/W (clear only)
-#define S3C2410_UDC_USBINT_SUSPEND	(1<<0) // R/W (clear only)
-
-#define S3C2410_UDC_INTE_EP4		(1<<4) // R/W
-#define S3C2410_UDC_INTE_EP3		(1<<3) // R/W
-#define S3C2410_UDC_INTE_EP2		(1<<2) // R/W
-#define S3C2410_UDC_INTE_EP1		(1<<1) // R/W
-#define S3C2410_UDC_INTE_EP0		(1<<0) // R/W
-
-#define S3C2410_UDC_USBINTE_RESET	(1<<2) // R/W
-#define S3C2410_UDC_USBINTE_SUSPEND	(1<<0) // R/W
-
-
-#define S3C2410_UDC_INDEX_EP0		(0x00)
-#define S3C2410_UDC_INDEX_EP1		(0x01) // ??
-#define S3C2410_UDC_INDEX_EP2		(0x02) // ??
-#define S3C2410_UDC_INDEX_EP3		(0x03) // ??
-#define S3C2410_UDC_INDEX_EP4		(0x04) // ??
-
-#define S3C2410_UDC_ICSR1_CLRDT		(1<<6) // R/W
-#define S3C2410_UDC_ICSR1_SENTSTL	(1<<5) // R/W (clear only)
-#define S3C2410_UDC_ICSR1_SENDSTL	(1<<4) // R/W
-#define S3C2410_UDC_ICSR1_FFLUSH	(1<<3) // W   (set only)
-#define S3C2410_UDC_ICSR1_UNDRUN	(1<<2) // R/W (clear only)
-#define S3C2410_UDC_ICSR1_PKTRDY	(1<<0) // R/W (set only)
-
-#define S3C2410_UDC_ICSR2_AUTOSET	(1<<7) // R/W
-#define S3C2410_UDC_ICSR2_ISO		(1<<6) // R/W
-#define S3C2410_UDC_ICSR2_MODEIN	(1<<5) // R/W
-#define S3C2410_UDC_ICSR2_DMAIEN	(1<<4) // R/W
-
-#define S3C2410_UDC_OCSR1_CLRDT		(1<<7) // R/W
-#define S3C2410_UDC_OCSR1_SENTSTL	(1<<6) // R/W (clear only)
-#define S3C2410_UDC_OCSR1_SENDSTL	(1<<5) // R/W
-#define S3C2410_UDC_OCSR1_FFLUSH	(1<<4) // R/W
-#define S3C2410_UDC_OCSR1_DERROR	(1<<3) // R
-#define S3C2410_UDC_OCSR1_OVRRUN	(1<<2) // R/W (clear only)
-#define S3C2410_UDC_OCSR1_PKTRDY	(1<<0) // R/W (clear only)
-
-#define S3C2410_UDC_OCSR2_AUTOCLR	(1<<7) // R/W
-#define S3C2410_UDC_OCSR2_ISO		(1<<6) // R/W
-#define S3C2410_UDC_OCSR2_DMAIEN	(1<<5) // R/W
-
-#define S3C2410_UDC_EP0_CSR_OPKRDY	(1<<0)
-#define S3C2410_UDC_EP0_CSR_IPKRDY	(1<<1)
-#define S3C2410_UDC_EP0_CSR_SENTSTL	(1<<2)
-#define S3C2410_UDC_EP0_CSR_DE		(1<<3)
-#define S3C2410_UDC_EP0_CSR_SE		(1<<4)
-#define S3C2410_UDC_EP0_CSR_SENDSTL	(1<<5)
-#define S3C2410_UDC_EP0_CSR_SOPKTRDY	(1<<6)
-#define S3C2410_UDC_EP0_CSR_SSE	(1<<7)
-
-#define S3C2410_UDC_MAXP_8		(1<<0)
-#define S3C2410_UDC_MAXP_16		(1<<1)
-#define S3C2410_UDC_MAXP_32		(1<<2)
-#define S3C2410_UDC_MAXP_64		(1<<3)
-
-
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2400.h b/include/asm-arm/plat-s3c24xx/s3c2400.h
deleted file mode 100644
index 3a5a16821af8..000000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2400.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2400.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C2400 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Modifications:
- *     09-Fev-2006 LCVR  First version, based on s3c2410.h
-*/
-
-#ifdef CONFIG_CPU_S3C2400
-
-extern  int s3c2400_init(void);
-
-extern void s3c2400_map_io(struct map_desc *mach_desc, int size);
-
-extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2400_init_clocks(int xtal);
-
-#else
-#define s3c2400_init_clocks NULL
-#define s3c2400_init_uarts NULL
-#define s3c2400_map_io NULL
-#define s3c2400_init NULL
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2410.h b/include/asm-arm/plat-s3c24xx/s3c2410.h
deleted file mode 100644
index 3cd1ec677b3f..000000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2410.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2410.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2410 machine directory
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#ifdef CONFIG_CPU_S3C2410
-
-extern  int s3c2410_init(void);
-
-extern void s3c2410_map_io(struct map_desc *mach_desc, int size);
-
-extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2410_init_clocks(int xtal);
-
-#else
-#define s3c2410_init_clocks NULL
-#define s3c2410_init_uarts NULL
-#define s3c2410_map_io NULL
-#define s3c2410_init NULL
-#endif
-
-extern int s3c2410_baseclk_add(void);
diff --git a/include/asm-arm/plat-s3c24xx/s3c2412.h b/include/asm-arm/plat-s3c24xx/s3c2412.h
deleted file mode 100644
index 3ec97685e781..000000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2412.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2412.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2412 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2412
-
-extern  int s3c2412_init(void);
-
-extern void s3c2412_map_io(struct map_desc *mach_desc, int size);
-
-extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2412_init_clocks(int xtal);
-
-extern  int s3c2412_baseclk_add(void);
-#else
-#define s3c2412_init_clocks NULL
-#define s3c2412_init_uarts NULL
-#define s3c2412_map_io NULL
-#define s3c2412_init NULL
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2440.h b/include/asm-arm/plat-s3c24xx/s3c2440.h
deleted file mode 100644
index 107853bf9481..000000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2440.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2440.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2440 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2440
-extern  int s3c2440_init(void);
-#else
-#define s3c2440_init NULL
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2442.h b/include/asm-arm/plat-s3c24xx/s3c2442.h
deleted file mode 100644
index 451a23a2092a..000000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2442.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2442.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2442 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2442
-extern  int s3c2442_init(void);
-#else
-#define s3c2442_init NULL
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2443.h b/include/asm-arm/plat-s3c24xx/s3c2443.h
deleted file mode 100644
index 11d83b5c84e6..000000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2443.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2443.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2443 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2443
-
-struct s3c2410_uartcfg;
-
-extern  int s3c2443_init(void);
-
-extern void s3c2443_map_io(struct map_desc *mach_desc, int size);
-
-extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2443_init_clocks(int xtal);
-
-extern  int s3c2443_baseclk_add(void);
-
-#else
-#define s3c2443_init_clocks NULL
-#define s3c2443_init_uarts NULL
-#define s3c2443_map_io NULL
-#define s3c2443_init NULL
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/udc.h b/include/asm-arm/plat-s3c24xx/udc.h
deleted file mode 100644
index 546bb4008f49..000000000000
--- a/include/asm-arm/plat-s3c24xx/udc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/udc.h
- *
- * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *
- *  Changelog:
- *	14-Mar-2005	RTP	Created file
- *	02-Aug-2005	RTP	File rename
- *	07-Sep-2005	BJD	Minor cleanups, changed cmd to enum
- *	18-Jan-2007	HMW	Add per-platform vbus_draw function
-*/
-
-#ifndef __ASM_ARM_ARCH_UDC_H
-#define __ASM_ARM_ARCH_UDC_H
-
-enum s3c2410_udc_cmd_e {
-	S3C2410_UDC_P_ENABLE	= 1,	/* Pull-up enable        */
-	S3C2410_UDC_P_DISABLE	= 2,	/* Pull-up disable       */
-	S3C2410_UDC_P_RESET	= 3,	/* UDC reset, in case of */
-};
-
-struct s3c2410_udc_mach_info {
-	void	(*udc_command)(enum s3c2410_udc_cmd_e);
- 	void	(*vbus_draw)(unsigned int ma);
-	unsigned int vbus_pin;
-	unsigned char vbus_pin_inverted;
-};
-
-extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
-
-#endif /* __ASM_ARM_ARCH_UDC_H */
diff --git a/include/asm-cris/Kbuild b/include/asm-cris/Kbuild
deleted file mode 100644
index d5b631935ec8..000000000000
--- a/include/asm-cris/Kbuild
+++ /dev/null
@@ -1,11 +0,0 @@
-include include/asm-generic/Kbuild.asm
-
-header-y += arch-v10/
-header-y += arch-v32/
-
-header-y += ethernet.h
-header-y += rtc.h
-header-y += sync_serial.h
-
-unifdef-y += etraxgpio.h
-unifdef-y += rs485.h
diff --git a/include/asm-cris/arch-v10/Kbuild b/include/asm-cris/arch-v10/Kbuild
deleted file mode 100644
index 7a192e1290b1..000000000000
--- a/include/asm-cris/arch-v10/Kbuild
+++ /dev/null
@@ -1,4 +0,0 @@
-header-y += user.h
-header-y += svinto.h
-header-y += sv_addr_ag.h
-header-y += sv_addr.agh
diff --git a/include/asm-cris/arch-v10/atomic.h b/include/asm-cris/arch-v10/atomic.h
deleted file mode 100644
index 6ef5e7d09024..000000000000
--- a/include/asm-cris/arch-v10/atomic.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_CRIS_ARCH_ATOMIC__
-#define __ASM_CRIS_ARCH_ATOMIC__
-
-#define cris_atomic_save(addr, flags) local_irq_save(flags);
-#define cris_atomic_restore(addr, flags) local_irq_restore(flags);
-
-#endif
diff --git a/include/asm-cris/arch-v10/bitops.h b/include/asm-cris/arch-v10/bitops.h
deleted file mode 100644
index be85f6de25d3..000000000000
--- a/include/asm-cris/arch-v10/bitops.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* asm/arch/bitops.h for Linux/CRISv10 */
-
-#ifndef _CRIS_ARCH_BITOPS_H
-#define _CRIS_ARCH_BITOPS_H
-
-/*
- * Helper functions for the core of the ff[sz] functions, wrapping the
- * syntactically awkward asms.  The asms compute the number of leading
- * zeroes of a bits-in-byte and byte-in-word and word-in-dword-swapped
- * number.  They differ in that the first function also inverts all bits
- * in the input.
- */
-static inline unsigned long cris_swapnwbrlz(unsigned long w)
-{
-	/* Let's just say we return the result in the same register as the
-	   input.  Saying we clobber the input but can return the result
-	   in another register:
-	   !  __asm__ ("swapnwbr %2\n\tlz %2,%0"
-	   !	      : "=r,r" (res), "=r,X" (dummy) : "1,0" (w));
-	   confuses gcc (sched.c, gcc from cris-dist-1.14).  */
-
-	unsigned long res;
-	__asm__ ("swapnwbr %0 \n\t"
-		 "lz %0,%0"
-		 : "=r" (res) : "0" (w));
-	return res;
-}
-
-static inline unsigned long cris_swapwbrlz(unsigned long w)
-{
-	unsigned res;
-	__asm__ ("swapwbr %0 \n\t"
-		 "lz %0,%0"
-		 : "=r" (res)
-		 : "0" (w));
-	return res;
-}
-
-/*
- * ffz = Find First Zero in word. Undefined if no zero exists,
- * so code should check against ~0UL first..
- */
-static inline unsigned long ffz(unsigned long w)
-{
-	return cris_swapnwbrlz(w);
-}
-
-/**
- * __ffs - find first bit in word.
- * @word: The word to search
- *
- * Undefined if no bit exists, so code should check against 0 first.
- */
-static inline unsigned long __ffs(unsigned long word)
-{
-	return cris_swapnwbrlz(~word);
-}
-
-/**
- * ffs - find first bit set
- * @x: the word to search
- *
- * This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-
-static inline unsigned long kernel_ffs(unsigned long w)
-{
-	return w ? cris_swapwbrlz (w) + 1 : 0;
-}
-
-#endif
diff --git a/include/asm-cris/arch-v10/bug.h b/include/asm-cris/arch-v10/bug.h
deleted file mode 100644
index 3485d6b34bb0..000000000000
--- a/include/asm-cris/arch-v10/bug.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifndef __ASM_CRISv10_ARCH_BUG_H
-#define __ASM_CRISv10_ARCH_BUG_H
-
-#include <linux/stringify.h>
-
-#ifdef CONFIG_BUG
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-/* The BUG() macro is used for marking obviously incorrect code paths.
- * It will cause a message with the file name and line number to be printed,
- * and then cause an oops.  The message is actually printed by handle_BUG()
- * in arch/cris/kernel/traps.c, and the reason we use this method of storing
- * the file name and line number is that we do not want to affect the registers
- * by calling printk() before causing the oops.
- */
-
-#define BUG_PREFIX 0x0D7F
-#define BUG_MAGIC  0x00001234
-
-struct bug_frame {
-	unsigned short prefix;
-	unsigned int magic;
-	unsigned short clear;
-	unsigned short movu;
-	unsigned short line;
-	unsigned short jump;
-	unsigned char *filename;
-};
-
-#if 0
-/* Unfortunately this version of the macro does not work due to a problem
- * with the compiler (aka a bug) when compiling with -O2, which sometimes
- * erroneously causes the second input to be stored in a register...
- */
-#define BUG()								\
-	__asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\
-				"movu.w %0,$r0\n\t"			\
-				"jump %1\n\t"				\
-				: : "i" (__LINE__), "i" (__FILE__))
-#else
-/* This version will have to do for now, until the compiler is fixed.
- * The drawbacks of this version are that the file name will appear multiple
- * times in the .rodata section, and that __LINE__ and __FILE__ can probably
- * not be used like this with newer versions of gcc.
- */
-#define BUG()								\
-	__asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\
-			      "movu.w " __stringify(__LINE__) ",$r0\n\t"\
-			      "jump 0f\n\t"				\
-			      ".section .rodata\n"			\
-			      "0:\t.string \"" __FILE__ "\"\n\t"	\
-			      ".previous")
-#endif
-
-#else
-
-/* This just causes an oops. */
-#define BUG() (*(int *)0 = 0)
-
-#endif
-
-#define HAVE_ARCH_BUG
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
diff --git a/include/asm-cris/arch-v10/byteorder.h b/include/asm-cris/arch-v10/byteorder.h
deleted file mode 100644
index 255b646b7fa8..000000000000
--- a/include/asm-cris/arch-v10/byteorder.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef _CRIS_ARCH_BYTEORDER_H
-#define _CRIS_ARCH_BYTEORDER_H
-
-#include <asm/types.h>
-#include <linux/compiler.h>
-
-/* we just define these two (as we can do the swap in a single
- * asm instruction in CRIS) and the arch-independent files will put
- * them together into ntohl etc.
- */
-
-static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
-{
-	__asm__ ("swapwb %0" : "=r" (x) : "0" (x));
-  
-	return(x);
-}
-
-static inline __attribute_const__ __u16 ___arch__swab16(__u16 x)
-{
-	__asm__ ("swapb %0" : "=r" (x) : "0" (x));
-	
-	return(x);
-}
-
-#endif
diff --git a/include/asm-cris/arch-v10/cache.h b/include/asm-cris/arch-v10/cache.h
deleted file mode 100644
index aea27184d2d2..000000000000
--- a/include/asm-cris/arch-v10/cache.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _ASM_ARCH_CACHE_H
-#define _ASM_ARCH_CACHE_H
-
-/* Etrax 100LX have 32-byte cache-lines. */
-#define L1_CACHE_BYTES 32
-#define L1_CACHE_SHIFT 5
-
-#endif /* _ASM_ARCH_CACHE_H */
diff --git a/include/asm-cris/arch-v10/checksum.h b/include/asm-cris/arch-v10/checksum.h
deleted file mode 100644
index b8000c5d7fe1..000000000000
--- a/include/asm-cris/arch-v10/checksum.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef _CRIS_ARCH_CHECKSUM_H
-#define _CRIS_ARCH_CHECKSUM_H
-
-/* Checksum some values used in TCP/UDP headers.
- *
- * The gain by doing this in asm is that C will not generate carry-additions
- * for the 32-bit components of the checksum, so otherwise we would have had
- * to split all of those into 16-bit components, then add.
- */
-
-static inline __wsum
-csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
-		   unsigned short proto, __wsum sum)
-{
-	__wsum res;
-	__asm__ ("add.d %2, %0\n\t"
-		 "ax\n\t"
-		 "add.d %3, %0\n\t"
-		 "ax\n\t"
-		 "add.d %4, %0\n\t"
-		 "ax\n\t"
-		 "addq 0, %0\n"
-	: "=r" (res)
-	: "0" (sum), "r" (daddr), "r" (saddr), "r" ((len + proto) << 8));
-
-	return res;
-}	
-
-#endif
diff --git a/include/asm-cris/arch-v10/delay.h b/include/asm-cris/arch-v10/delay.h
deleted file mode 100644
index 39481f6e0c30..000000000000
--- a/include/asm-cris/arch-v10/delay.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _CRIS_ARCH_DELAY_H
-#define _CRIS_ARCH_DELAY_H
-
-static inline void __delay(int loops)
-{
-	__asm__ __volatile__ (
-			      "move.d %0,$r9\n\t"
-			      "beq 2f\n\t"
-			      "subq 1,$r9\n\t"
-			      "1:\n\t"
-			      "bne 1b\n\t"
-			      "subq 1,$r9\n"
-			      "2:"
-			      : : "g" (loops) : "r9");
-}
-
-#endif /* defined(_CRIS_ARCH_DELAY_H) */
-
-
-
diff --git a/include/asm-cris/arch-v10/dma.h b/include/asm-cris/arch-v10/dma.h
deleted file mode 100644
index ecb9dba6fa4f..000000000000
--- a/include/asm-cris/arch-v10/dma.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Defines for using and allocating dma channels. */
-
-#ifndef _ASM_ARCH_DMA_H
-#define _ASM_ARCH_DMA_H
-
-#define MAX_DMA_CHANNELS	10
-
-/* dma0 and dma1 used for network (ethernet) */
-#define NETWORK_TX_DMA_NBR 0
-#define NETWORK_RX_DMA_NBR 1
-
-/* dma2 and dma3 shared by par0, scsi0, ser2 and ata */
-#define PAR0_TX_DMA_NBR 2
-#define PAR0_RX_DMA_NBR 3
-#define SCSI0_TX_DMA_NBR 2
-#define SCSI0_RX_DMA_NBR 3
-#define SER2_TX_DMA_NBR 2
-#define SER2_RX_DMA_NBR 3
-#define ATA_TX_DMA_NBR 2
-#define ATA_RX_DMA_NBR 3
-
-/* dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */
-#define PAR1_TX_DMA_NBR 4
-#define PAR1_RX_DMA_NBR 5
-#define SCSI1_TX_DMA_NBR 4
-#define SCSI1_RX_DMA_NBR 5
-#define SER3_TX_DMA_NBR 4
-#define SER3_RX_DMA_NBR 5
-#define EXTDMA0_TX_DMA_NBR 4
-#define EXTDMA0_RX_DMA_NBR 5
-
-/* dma6 and dma7 shared by ser0, extdma1 and mem2mem */
-#define SER0_TX_DMA_NBR 6
-#define SER0_RX_DMA_NBR 7
-#define EXTDMA1_TX_DMA_NBR 6
-#define EXTDMA1_RX_DMA_NBR 7
-#define MEM2MEM_TX_DMA_NBR 6
-#define MEM2MEM_RX_DMA_NBR 7
-
-/* dma8 and dma9 shared by ser1 and usb */
-#define SER1_TX_DMA_NBR 8
-#define SER1_RX_DMA_NBR 9
-#define USB_TX_DMA_NBR 8
-#define USB_RX_DMA_NBR 9
-
-#endif
-
-enum dma_owner
-{
-  dma_eth,
-  dma_ser0,
-  dma_ser1, /* Async and sync */
-  dma_ser2,
-  dma_ser3, /* Async and sync */
-  dma_ata,
-  dma_par0,
-  dma_par1,
-  dma_ext0,
-  dma_ext1,
-  dma_int6,
-  dma_int7,
-  dma_usb,
-  dma_scsi0,
-  dma_scsi1
-};
-
-/* Masks used by cris_request_dma options: */
-#define DMA_VERBOSE_ON_ERROR    (1<<0)
-#define DMA_PANIC_ON_ERROR     ((1<<1)|DMA_VERBOSE_ON_ERROR)
-
-int cris_request_dma(unsigned int dmanr, const char * device_id,
-                     unsigned options, enum dma_owner owner);
-
-void cris_free_dma(unsigned int dmanr, const char * device_id);
diff --git a/include/asm-cris/arch-v10/elf.h b/include/asm-cris/arch-v10/elf.h
deleted file mode 100644
index 1c38ee728b17..000000000000
--- a/include/asm-cris/arch-v10/elf.h
+++ /dev/null
@@ -1,81 +0,0 @@
-#ifndef __ASMCRIS_ARCH_ELF_H
-#define __ASMCRIS_ARCH_ELF_H
-
-#define ELF_MACH EF_CRIS_VARIANT_ANY_V0_V10
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x)			\
- ((x)->e_machine == EM_CRIS			\
-  && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_ANY_V0_V10	\
-      || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32))))
-
-/*
- * ELF register definitions..
- */
-
-#include <asm/ptrace.h>
-
-/* SVR4/i386 ABI (pages 3-31, 3-32) says that when the program
-   starts (a register; assume first param register for CRIS)
-   contains a pointer to a function which might be
-   registered using `atexit'.  This provides a mean for the
-   dynamic linker to call DT_FINI functions for shared libraries
-   that have been loaded before the code runs.
-
-   A value of 0 tells we have no such handler.  */
-
-/* Explicitly set registers to 0 to increase determinism.  */
-#define ELF_PLAT_INIT(_r, load_addr)	do { \
-	(_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \
-	(_r)->r9 = 0;  (_r)->r8 = 0;  (_r)->r7 = 0;  (_r)->r6 = 0;  \
-	(_r)->r5 = 0;  (_r)->r4 = 0;  (_r)->r3 = 0;  (_r)->r2 = 0;  \
-	(_r)->r1 = 0;  (_r)->r0 = 0;  (_r)->mof = 0; (_r)->srp = 0; \
-} while (0)
-
-/* The additional layer below is because the stack pointer is missing in 
-   the pt_regs struct, but needed in a core dump. pr_reg is a elf_gregset_t,
-   and should be filled in according to the layout of the user_regs_struct
-   struct; regs is a pt_regs struct. We dump all registers, though several are
-   obviously unnecessary. That way there's less need for intelligence at 
-   the receiving end (i.e. gdb). */
-#define ELF_CORE_COPY_REGS(pr_reg, regs)                   \
-	pr_reg[0] = regs->r0;                              \
-	pr_reg[1] = regs->r1;                              \
-	pr_reg[2] = regs->r2;                              \
-	pr_reg[3] = regs->r3;                              \
-	pr_reg[4] = regs->r4;                              \
-	pr_reg[5] = regs->r5;                              \
-	pr_reg[6] = regs->r6;                              \
-	pr_reg[7] = regs->r7;                              \
-	pr_reg[8] = regs->r8;                              \
-	pr_reg[9] = regs->r9;                              \
-	pr_reg[10] = regs->r10;                            \
-	pr_reg[11] = regs->r11;                            \
-	pr_reg[12] = regs->r12;                            \
-	pr_reg[13] = regs->r13;                            \
-	pr_reg[14] = rdusp();               /* sp */       \
-	pr_reg[15] = regs->irp;             /* pc */       \
-	pr_reg[16] = 0;                     /* p0 */       \
-	pr_reg[17] = rdvr();                /* vr */       \
-	pr_reg[18] = 0;                     /* p2 */       \
-	pr_reg[19] = 0;                     /* p3 */       \
-	pr_reg[20] = 0;                     /* p4 */       \
-	pr_reg[21] = (regs->dccr & 0xffff); /* ccr */      \
-	pr_reg[22] = 0;                     /* p6 */       \
-	pr_reg[23] = regs->mof;             /* mof */      \
-	pr_reg[24] = 0;                     /* p8 */       \
-	pr_reg[25] = 0;                     /* ibr */      \
-	pr_reg[26] = 0;                     /* irp */      \
-	pr_reg[27] = regs->srp;             /* srp */      \
-	pr_reg[28] = 0;                     /* bar */      \
-	pr_reg[29] = regs->dccr;            /* dccr */     \
-	pr_reg[30] = 0;                     /* brp */      \
-	pr_reg[31] = rdusp();               /* usp */      \
-	pr_reg[32] = 0;                     /* csrinstr */ \
-	pr_reg[33] = 0;                     /* csraddr */  \
-	pr_reg[34] = 0;                     /* csrdata */
-
-
-#endif
diff --git a/include/asm-cris/arch-v10/io.h b/include/asm-cris/arch-v10/io.h
deleted file mode 100644
index c08c24265299..000000000000
--- a/include/asm-cris/arch-v10/io.h
+++ /dev/null
@@ -1,199 +0,0 @@
-#ifndef _ASM_ARCH_CRIS_IO_H
-#define _ASM_ARCH_CRIS_IO_H
-
-#include <asm/arch/svinto.h>
-
-/* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */
-
-extern unsigned long gen_config_ii_shadow;
-extern unsigned long port_g_data_shadow;
-extern unsigned char port_pa_dir_shadow;
-extern unsigned char port_pa_data_shadow;
-extern unsigned char port_pb_i2c_shadow;
-extern unsigned char port_pb_config_shadow;
-extern unsigned char port_pb_dir_shadow;
-extern unsigned char port_pb_data_shadow;
-extern unsigned long r_timer_ctrl_shadow;
-
-extern unsigned long port_cse1_shadow;
-extern unsigned long port_csp0_shadow;
-extern unsigned long port_csp4_shadow;
-
-extern volatile unsigned long *port_cse1_addr;
-extern volatile unsigned long *port_csp0_addr;
-extern volatile unsigned long *port_csp4_addr;
-
-/* macro for setting regs through a shadow -
- * r = register name (like R_PORT_PA_DATA)
- * s = shadow name (like port_pa_data_shadow)
- * b = bit number
- * v = value (0 or 1)
- */
-
-#define REG_SHADOW_SET(r,s,b,v) *r = s = (s & ~(1 << (b))) | ((v) << (b))
-
-/* The LED's on various Etrax-based products are set differently. */
-
-#if defined(CONFIG_ETRAX_NO_LEDS) || defined(CONFIG_SVINTO_SIM)
-#undef CONFIG_ETRAX_PA_LEDS
-#undef CONFIG_ETRAX_PB_LEDS
-#undef CONFIG_ETRAX_CSP0_LEDS
-#define CRIS_LED_NETWORK_SET_G(x)
-#define CRIS_LED_NETWORK_SET_R(x)
-#define CRIS_LED_ACTIVE_SET_G(x)
-#define CRIS_LED_ACTIVE_SET_R(x)
-#define CRIS_LED_DISK_WRITE(x)
-#define CRIS_LED_DISK_READ(x)
-#endif
-
-#if !defined(CONFIG_ETRAX_CSP0_LEDS)
-#define CRIS_LED_BIT_SET(x)
-#define CRIS_LED_BIT_CLR(x)
-#endif
-
-#define CRIS_LED_OFF    0x00
-#define CRIS_LED_GREEN  0x01
-#define CRIS_LED_RED    0x02
-#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED)
-
-#if defined(CONFIG_ETRAX_NO_LEDS)
-#define CRIS_LED_NETWORK_SET(x)
-#else
-#if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R
-#define CRIS_LED_NETWORK_SET(x)                          \
-	do {                                        \
-		CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \
-	} while (0)
-#else
-#define CRIS_LED_NETWORK_SET(x)                          \
-	do {                                        \
-		CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \
-		CRIS_LED_NETWORK_SET_R((x) & CRIS_LED_RED);   \
-	} while (0)
-#endif
-#if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R
-#define CRIS_LED_ACTIVE_SET(x)                           \
-	do {                                        \
-		CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN);  \
-	} while (0)
-#else
-#define CRIS_LED_ACTIVE_SET(x)                           \
-	do {                                        \
-		CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN);  \
-		CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED);    \
-	} while (0)
-#endif
-#endif
-
-#ifdef CONFIG_ETRAX_PA_LEDS
-#define CRIS_LED_NETWORK_SET_G(x) \
-         REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1G, !(x))
-#define CRIS_LED_NETWORK_SET_R(x) \
-         REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1R, !(x))
-#define CRIS_LED_ACTIVE_SET_G(x) \
-         REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2G, !(x))
-#define CRIS_LED_ACTIVE_SET_R(x) \
-         REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2R, !(x))
-#define CRIS_LED_DISK_WRITE(x) \
-         do{\
-                REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x));\
-                REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3R, !(x));\
-        }while(0)
-#define CRIS_LED_DISK_READ(x) \
-	REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, \
-		CONFIG_ETRAX_LED3G, !(x))
-#endif
-
-#ifdef CONFIG_ETRAX_PB_LEDS
-#define CRIS_LED_NETWORK_SET_G(x) \
-         REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1G, !(x))
-#define CRIS_LED_NETWORK_SET_R(x) \
-         REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1R, !(x))
-#define CRIS_LED_ACTIVE_SET_G(x) \
-         REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2G, !(x))
-#define CRIS_LED_ACTIVE_SET_R(x) \
-         REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2R, !(x))
-#define CRIS_LED_DISK_WRITE(x) \
-        do{\
-                REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x));\
-                REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3R, !(x));\
-        }while(0)
-#define CRIS_LED_DISK_READ(x) \
-	REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, \
-		CONFIG_ETRAX_LED3G, !(x))
-#endif
-
-#ifdef CONFIG_ETRAX_CSP0_LEDS
-#define CONFIGURABLE_LEDS\
-        ((1 << CONFIG_ETRAX_LED1G ) | (1 << CONFIG_ETRAX_LED1R ) |\
-         (1 << CONFIG_ETRAX_LED2G ) | (1 << CONFIG_ETRAX_LED2R ) |\
-         (1 << CONFIG_ETRAX_LED3G ) | (1 << CONFIG_ETRAX_LED3R ) |\
-         (1 << CONFIG_ETRAX_LED4G ) | (1 << CONFIG_ETRAX_LED4R ) |\
-         (1 << CONFIG_ETRAX_LED5G ) | (1 << CONFIG_ETRAX_LED5R ) |\
-         (1 << CONFIG_ETRAX_LED6G ) | (1 << CONFIG_ETRAX_LED6R ) |\
-         (1 << CONFIG_ETRAX_LED7G ) | (1 << CONFIG_ETRAX_LED7R ) |\
-         (1 << CONFIG_ETRAX_LED8Y ) | (1 << CONFIG_ETRAX_LED9Y ) |\
-         (1 << CONFIG_ETRAX_LED10Y ) |(1 << CONFIG_ETRAX_LED11Y )|\
-         (1 << CONFIG_ETRAX_LED12R ))
-
-#define CRIS_LED_NETWORK_SET_G(x) \
-         REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1G, !(x))
-#define CRIS_LED_NETWORK_SET_R(x) \
-         REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1R, !(x))
-#define CRIS_LED_ACTIVE_SET_G(x) \
-         REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2G, !(x))
-#define CRIS_LED_ACTIVE_SET_R(x) \
-         REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2R, !(x))
-#define CRIS_LED_DISK_WRITE(x) \
-        do{\
-                REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x));\
-                REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3R, !(x));\
-        }while(0)
-#define CRIS_LED_DISK_READ(x) \
-         REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x))
-#define CRIS_LED_BIT_SET(x)\
-        do{\
-                if((( 1 << x) & CONFIGURABLE_LEDS)  != 0)\
-                       REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 1);\
-        }while(0)
-#define CRIS_LED_BIT_CLR(x)\
-        do{\
-                if((( 1 << x) & CONFIGURABLE_LEDS)  != 0)\
-                       REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 0);\
-        }while(0)
-#endif
-
-#
-#ifdef CONFIG_ETRAX_SOFT_SHUTDOWN
-#define SOFT_SHUTDOWN() \
-          REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_SHUTDOWN_BIT, 1)
-#else
-#define SOFT_SHUTDOWN()
-#endif
-
-/* Console I/O for simulated etrax100.  Use #ifdef so erroneous
-   use will be evident. */
-#ifdef CONFIG_SVINTO_SIM
-  /* Let's use the ucsim interface since it lets us do write(2, ...) */
-#define SIMCOUT(s,len)							\
-  asm ("moveq 4,$r9	\n\t"						\
-       "moveq 2,$r10	\n\t"						\
-       "move.d %0,$r11	\n\t"						\
-       "move.d %1,$r12	\n\t"						\
-       "push $irp	\n\t"						\
-       "move 0f,$irp	\n\t"						\
-       "jump -6809	\n"						\
-       "0:		\n\t"						\
-       "pop $irp"							\
-       : : "rm" (s), "rm" (len) : "r9","r10","r11","r12","memory")
-#define TRACE_ON() __extension__ \
- ({ int _Foofoo; __asm__ volatile ("bmod [%0],%0" : "=r" (_Foofoo) : "0" \
-			       (255)); _Foofoo; })
-
-#define TRACE_OFF() do { __asm__ volatile ("bmod [%0],%0" :: "r" (254)); } while (0)
-#define SIM_END() do { __asm__ volatile ("bmod [%0],%0" :: "r" (28)); } while (0)
-#define CRIS_CYCLES() __extension__ \
- ({ unsigned long c; asm ("bmod [%1],%0" : "=r" (c) : "r" (27)); c;})
-#endif /* ! defined CONFIG_SVINTO_SIM */
-
-#endif
diff --git a/include/asm-cris/arch-v10/io_interface_mux.h b/include/asm-cris/arch-v10/io_interface_mux.h
deleted file mode 100644
index d92500080883..000000000000
--- a/include/asm-cris/arch-v10/io_interface_mux.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* IO interface mux allocator for ETRAX100LX.
- * Copyright 2004, Axis Communications AB
- * $Id: io_interface_mux.h,v 1.1 2004/12/13 12:21:53 starvik Exp $
- */
-
-
-#ifndef _IO_INTERFACE_MUX_H
-#define _IO_INTERFACE_MUX_H
-
-
-/* C.f. ETRAX100LX Designer's Reference 20.9 */
-
-/* The order in enum must match the order of interfaces[] in
- * io_interface_mux.c */
-enum cris_io_interface {
-	/* Begin Non-multiplexed interfaces */
-	if_eth = 0,
-	if_serial_0,
-	/* End Non-multiplexed interfaces */
-	if_serial_1,
-	if_serial_2,
-	if_serial_3,
-	if_sync_serial_1,
-	if_sync_serial_3,
-	if_shared_ram,
-	if_shared_ram_w,
-	if_par_0,
-	if_par_1,
-	if_par_w,
-	if_scsi8_0,
-	if_scsi8_1,
-	if_scsi_w,
-	if_ata,
-	if_csp,
-	if_i2c,
-	if_usb_1,
-	if_usb_2,
-	/* GPIO pins */
-	if_gpio_grp_a,
-	if_gpio_grp_b,
-	if_gpio_grp_c,
-	if_gpio_grp_d,
-	if_gpio_grp_e,
-	if_gpio_grp_f,
-	if_max_interfaces,
-	if_unclaimed
-};
-
-int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id);
-
-void cris_free_io_interface(enum cris_io_interface ioif);
-
-/* port can be 'a', 'b' or 'g' */
-int cris_io_interface_allocate_pins(const enum cris_io_interface ioif,
-				    const char port,
-				    const unsigned start_bit,
-				    const unsigned stop_bit);
-
-/* port can be 'a', 'b' or 'g' */
-int cris_io_interface_free_pins(const enum cris_io_interface ioif,
-                                const char port,
-                                const unsigned start_bit,
-                                const unsigned stop_bit);
-
-int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available,
-						      const unsigned int gpio_out_available,
-						      const unsigned char pa_available,
-						      const unsigned char pb_available));
-
-void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available,
-						     const unsigned int gpio_out_available,
-                                                     const unsigned char pa_available,
-						     const unsigned char pb_available));
-
-#endif /* _IO_INTERFACE_MUX_H */
diff --git a/include/asm-cris/arch-v10/irq.h b/include/asm-cris/arch-v10/irq.h
deleted file mode 100644
index b1128a9984ae..000000000000
--- a/include/asm-cris/arch-v10/irq.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Interrupt handling assembler and defines for Linux/CRISv10
- */
-
-#ifndef _ASM_ARCH_IRQ_H
-#define _ASM_ARCH_IRQ_H
-
-#include <asm/arch/sv_addr_ag.h>
-
-#define NR_IRQS 32
-
-/* The first vector number used for IRQs in v10 is really 0x20 */
-/* but all the code and constants are offseted to make 0 the first */
-#define FIRST_IRQ 0
-
-#define SOME_IRQ_NBR        IO_BITNR(R_VECT_MASK_RD, some)   /* 0 ? */
-#define NMI_IRQ_NBR         IO_BITNR(R_VECT_MASK_RD, nmi)    /* 1 */
-#define TIMER0_IRQ_NBR      IO_BITNR(R_VECT_MASK_RD, timer0) /* 2 */
-#define TIMER1_IRQ_NBR      IO_BITNR(R_VECT_MASK_RD, timer1) /* 3 */
-/* mio, ata, par0, scsi0 on 4 */
-/* par1, scsi1 on 5 */
-#define NETWORK_STATUS_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, network) /* 6 */
-
-#define SERIAL_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, serial) /* 8 */
-#define PA_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, pa) /* 11 */
-/* extdma0 and extdma1 is at irq 12 and 13 and/or same as dma5 and dma6 ? */
-#define EXTDMA0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma0)
-#define EXTDMA1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma1)
-
-/* dma0-9 is irq 16..25 */
-/* 16,17: network */
-#define DMA0_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma0)
-#define DMA1_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma1)
-#define NETWORK_DMA_TX_IRQ_NBR DMA0_TX_IRQ_NBR
-#define NETWORK_DMA_RX_IRQ_NBR DMA1_RX_IRQ_NBR
-
-/* 18,19: dma2 and dma3 shared by par0, scsi0, ser2 and ata */
-#define DMA2_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma2)
-#define DMA3_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma3)
-#define SER2_DMA_TX_IRQ_NBR DMA2_TX_IRQ_NBR
-#define SER2_DMA_RX_IRQ_NBR DMA3_RX_IRQ_NBR
-
-/* 20,21: dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */
-#define DMA4_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma4)
-#define DMA5_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma5)
-#define SER3_DMA_TX_IRQ_NBR DMA4_TX_IRQ_NBR
-#define SER3_DMA_RX_IRQ_NBR DMA5_RX_IRQ_NBR
-
-/* 22,23: dma6 and dma7 shared by ser0, extdma1 and mem2mem */
-#define DMA6_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma6)
-#define DMA7_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma7)
-#define SER0_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR
-#define SER0_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR
-#define MEM2MEM_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR
-#define MEM2MEM_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR
-
-/* 24,25: dma8 and dma9 shared by ser1 and usb */
-#define DMA8_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma8)
-#define DMA9_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma9)
-#define SER1_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR
-#define SER1_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR
-#define USB_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR
-#define USB_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR
-
-/* usb: controller at irq 31 + uses DMA8 and DMA9 */
-#define USB_HC_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, usb)
-
-/* our fine, global, etrax irq vector! the pointer lives in the head.S file. */
-
-typedef void (*irqvectptr)(void);
-
-struct etrax_interrupt_vector {
-	irqvectptr v[256];
-};
-
-extern struct etrax_interrupt_vector *etrax_irv;
-void set_int_vector(int n, irqvectptr addr);
-void set_break_vector(int n, irqvectptr addr);
-
-#define __STR(x) #x
-#define STR(x) __STR(x)
- 
-/* SAVE_ALL saves registers so they match pt_regs */
-
-#define SAVE_ALL \
-  "move $irp,[$sp=$sp-16]\n\t" /* push instruction pointer and fake SBFS struct */ \
-  "push $srp\n\t"       /* push subroutine return pointer */ \
-  "push $dccr\n\t"      /* push condition codes */ \
-  "push $mof\n\t"       /* push multiply overflow reg */ \
-  "di\n\t"             /* need to disable irq's at this point */\
-  "subq 14*4,$sp\n\t"   /* make room for r0-r13 */ \
-  "movem $r13,[$sp]\n\t" /* push the r0-r13 registers */ \
-  "push $r10\n\t"       /* push orig_r10 */ \
-  "clear.d [$sp=$sp-4]\n\t"  /* frametype - this is a normal stackframe */
-
-  /* BLOCK_IRQ and UNBLOCK_IRQ do the same as mask_irq and unmask_irq */
-
-#define BLOCK_IRQ(mask,nr) \
-  "move.d " #mask ",$r0\n\t" \
-  "move.d $r0,[0xb00000d8]\n\t" 
-  
-#define UNBLOCK_IRQ(mask) \
-  "move.d " #mask ",$r0\n\t" \
-  "move.d $r0,[0xb00000dc]\n\t" 
-
-#define IRQ_NAME2(nr) nr##_interrupt(void)
-#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
-#define sIRQ_NAME(nr) IRQ_NAME2(sIRQ##nr)
-#define BAD_IRQ_NAME(nr) IRQ_NAME2(bad_IRQ##nr)
-
-  /* the asm IRQ handler makes sure the causing IRQ is blocked, then it calls
-   * do_IRQ (with irq disabled still). after that it unblocks and jumps to
-   * ret_from_intr (entry.S)
-   *
-   * The reason the IRQ is blocked is to allow an sti() before the handler which
-   * will acknowledge the interrupt is run.
-   */
-
-#define BUILD_IRQ(nr,mask) \
-void IRQ_NAME(nr); \
-__asm__ ( \
-          ".text\n\t" \
-          "IRQ" #nr "_interrupt:\n\t" \
-	  SAVE_ALL \
-	  BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \
-	  "moveq "#nr",$r10\n\t" \
-	  "move.d $sp,$r11\n\t" \
-	  "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
-	  UNBLOCK_IRQ(mask) \
-	  "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
-	  "jump ret_from_intr\n\t");
-
-/* This is subtle. The timer interrupt is crucial and it should not be disabled for 
- * too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would
- * have been BLOCK'ed, and then softirq's are run before we return here to UNBLOCK.
- * If the softirq's take too much time to run, the timer irq won't run and the 
- * watchdog will kill us.
- *
- * Furthermore, if a lot of other irq's occur before we return here, the multiple_irq
- * handler is run and it prioritizes the timer interrupt. However if we had BLOCK'ed
- * it here, we would not get the multiple_irq at all.
- *
- * The non-blocking here is based on the knowledge that the timer interrupt is 
- * registred as a fast interrupt (IRQF_DISABLED) so that we _know_ there will not
- * be an sti() before the timer irq handler is run to acknowledge the interrupt.
- */
-
-#define BUILD_TIMER_IRQ(nr,mask) \
-void IRQ_NAME(nr); \
-__asm__ ( \
-          ".text\n\t" \
-          "IRQ" #nr "_interrupt:\n\t" \
-	  SAVE_ALL \
-	  "moveq "#nr",$r10\n\t" \
-	  "move.d $sp,$r11\n\t" \
-	  "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
-	  "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
-	  "jump ret_from_intr\n\t");
-
-#endif
diff --git a/include/asm-cris/arch-v10/memmap.h b/include/asm-cris/arch-v10/memmap.h
deleted file mode 100644
index 13f3b971407f..000000000000
--- a/include/asm-cris/arch-v10/memmap.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef _ASM_ARCH_MEMMAP_H
-#define _ASM_ARCH_MEMMAP_H
-
-#define MEM_CSE0_START (0x00000000)
-#define MEM_CSE0_SIZE (0x04000000)
-#define MEM_CSE1_START (0x04000000)
-#define MEM_CSE1_SIZE (0x04000000)
-#define MEM_CSR0_START (0x08000000)
-#define MEM_CSR1_START (0x0c000000)
-#define MEM_CSP0_START (0x10000000)
-#define MEM_CSP1_START (0x14000000)
-#define MEM_CSP2_START (0x18000000)
-#define MEM_CSP3_START (0x1c000000)
-#define MEM_CSP4_START (0x20000000)
-#define MEM_CSP5_START (0x24000000)
-#define MEM_CSP6_START (0x28000000)
-#define MEM_CSP7_START (0x2c000000)
-#define MEM_DRAM_START (0x40000000)
-
-#define MEM_NON_CACHEABLE (0x80000000)
-
-#endif
diff --git a/include/asm-cris/arch-v10/mmu.h b/include/asm-cris/arch-v10/mmu.h
deleted file mode 100644
index df84f1716e6b..000000000000
--- a/include/asm-cris/arch-v10/mmu.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * CRIS MMU constants and PTE layout
- */
-
-#ifndef _CRIS_ARCH_MMU_H
-#define _CRIS_ARCH_MMU_H
-
-/* type used in struct mm to couple an MMU context to an active mm */
-
-typedef struct
-{
-  unsigned int page_id;
-} mm_context_t;
-
-/* kernel memory segments */
-
-#define KSEG_F 0xf0000000UL
-#define KSEG_E 0xe0000000UL
-#define KSEG_D 0xd0000000UL
-#define KSEG_C 0xc0000000UL
-#define KSEG_B 0xb0000000UL
-#define KSEG_A 0xa0000000UL
-#define KSEG_9 0x90000000UL
-#define KSEG_8 0x80000000UL
-#define KSEG_7 0x70000000UL
-#define KSEG_6 0x60000000UL
-#define KSEG_5 0x50000000UL
-#define KSEG_4 0x40000000UL
-#define KSEG_3 0x30000000UL
-#define KSEG_2 0x20000000UL
-#define KSEG_1 0x10000000UL
-#define KSEG_0 0x00000000UL
-
-/* CRIS PTE bits (see R_TLB_LO in the register description)
- *
- *   Bit:  31-13 12-------4    3        2       1       0  
- *         ________________________________________________
- *        | pfn | reserved | global | valid | kernel | we  |
- *        |_____|__________|________|_______|________|_____|
- *
- * (pfn = physical frame number)
- */
-
-/* Real HW-based PTE bits. We use some synonym names so that
- * things become less confusing in combination with the SW-based
- * bits further below.
- *
- */
-
-#define _PAGE_WE	   (1<<0) /* page is write-enabled */
-#define _PAGE_SILENT_WRITE (1<<0) /* synonym */
-#define _PAGE_KERNEL	   (1<<1) /* page is kernel only */
-#define _PAGE_VALID	   (1<<2) /* page is valid */
-#define _PAGE_SILENT_READ  (1<<2) /* synonym */
-#define _PAGE_GLOBAL       (1<<3) /* global page - context is ignored */
-
-/* Bits the HW doesn't care about but the kernel uses them in SW */
-
-#define _PAGE_PRESENT   (1<<4)  /* page present in memory */
-#define _PAGE_FILE      (1<<5)  /* set: pagecache, unset: swap (when !PRESENT) */
-#define _PAGE_ACCESSED	(1<<5)  /* simulated in software using valid bit */
-#define _PAGE_MODIFIED	(1<<6)  /* simulated in software using we bit */
-#define _PAGE_READ      (1<<7)  /* read-enabled */
-#define _PAGE_WRITE     (1<<8)  /* write-enabled */
-
-/* Define some higher level generic page attributes. */
-
-#define __READABLE      (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
-#define __WRITEABLE     (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
-
-#define _PAGE_TABLE     (_PAGE_PRESENT | __READABLE | __WRITEABLE)
-#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED)
-
-#define PAGE_NONE       __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
-#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
-				 _PAGE_ACCESSED)
-#define PAGE_COPY       __pgprot(_PAGE_PRESENT | __READABLE)  // | _PAGE_COW
-#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | __READABLE)
-#define PAGE_KERNEL     __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \
-				 _PAGE_PRESENT | __READABLE | __WRITEABLE)
-#define _KERNPG_TABLE   (_PAGE_TABLE | _PAGE_KERNEL)
-
-/*
- * CRIS can't do page protection for execute, and considers read the same.
- * Also, write permissions imply read permissions. This is the closest we can
- * get..
- */
-
-#define __P000	PAGE_NONE
-#define __P001	PAGE_READONLY
-#define __P010	PAGE_COPY
-#define __P011	PAGE_COPY
-#define __P100	PAGE_READONLY
-#define __P101	PAGE_READONLY
-#define __P110	PAGE_COPY
-#define __P111	PAGE_COPY
-
-#define __S000	PAGE_NONE
-#define __S001	PAGE_READONLY
-#define __S010	PAGE_SHARED
-#define __S011	PAGE_SHARED
-#define __S100	PAGE_READONLY
-#define __S101	PAGE_READONLY
-#define __S110	PAGE_SHARED
-#define __S111	PAGE_SHARED
-
-#define PTE_FILE_MAX_BITS	26
-
-#endif
diff --git a/include/asm-cris/arch-v10/offset.h b/include/asm-cris/arch-v10/offset.h
deleted file mode 100644
index 675b51d85639..000000000000
--- a/include/asm-cris/arch-v10/offset.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef __ASM_OFFSETS_H__
-#define __ASM_OFFSETS_H__
-/*
- * DO NOT MODIFY.
- *
- * This file was generated by arch/cris/Makefile
- *
- */
-
-#define PT_orig_r10 4 /* offsetof(struct pt_regs, orig_r10) */
-#define PT_r13 8 /* offsetof(struct pt_regs, r13) */
-#define PT_r12 12 /* offsetof(struct pt_regs, r12) */
-#define PT_r11 16 /* offsetof(struct pt_regs, r11) */
-#define PT_r10 20 /* offsetof(struct pt_regs, r10) */
-#define PT_r9 24 /* offsetof(struct pt_regs, r9) */
-#define PT_mof 64 /* offsetof(struct pt_regs, mof) */
-#define PT_dccr 68 /* offsetof(struct pt_regs, dccr) */
-#define PT_srp 72 /* offsetof(struct pt_regs, srp) */
-
-#define TI_task 0 /* offsetof(struct thread_info, task) */
-#define TI_flags 8 /* offsetof(struct thread_info, flags) */
-#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */
-
-#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */
-#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */
-#define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */
-
-#define TASK_pid 141 /* offsetof(struct task_struct, pid) */
-
-#define LCLONE_VM 256 /* CLONE_VM */
-#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */
-
-#endif
diff --git a/include/asm-cris/arch-v10/page.h b/include/asm-cris/arch-v10/page.h
deleted file mode 100644
index ffafc99c3472..000000000000
--- a/include/asm-cris/arch-v10/page.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef _CRIS_ARCH_PAGE_H
-#define _CRIS_ARCH_PAGE_H
-
-
-#ifdef __KERNEL__
-
-/* This handles the memory map.. */
-#ifdef CONFIG_CRIS_LOW_MAP
-#define PAGE_OFFSET		KSEG_6   /* kseg_6 is mapped to physical ram */
-#else
-#define PAGE_OFFSET		KSEG_C   /* kseg_c is mapped to physical ram */
-#endif
-
-/* macros to convert between really physical and virtual addresses
- * by stripping a selected bit, we can convert between KSEG_x and
- * 0x40000000 where the DRAM really resides
- */
-
-#ifdef CONFIG_CRIS_LOW_MAP
-/* we have DRAM virtually at 0x6 */
-#define __pa(x)                 ((unsigned long)(x) & 0xdfffffff)
-#define __va(x)                 ((void *)((unsigned long)(x) | 0x20000000))
-#else
-/* we have DRAM virtually at 0xc */
-#define __pa(x)                 ((unsigned long)(x) & 0x7fffffff)
-#define __va(x)                 ((void *)((unsigned long)(x) | 0x80000000))
-#endif
-
-#endif
-#endif
diff --git a/include/asm-cris/arch-v10/pgtable.h b/include/asm-cris/arch-v10/pgtable.h
deleted file mode 100644
index 2a2576d1fc97..000000000000
--- a/include/asm-cris/arch-v10/pgtable.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef _CRIS_ARCH_PGTABLE_H
-#define _CRIS_ARCH_PGTABLE_H
-
-/*
- * Kernels own virtual memory area. 
- */
-
-#ifdef CONFIG_CRIS_LOW_MAP
-#define VMALLOC_START     KSEG_7
-#define VMALLOC_END       KSEG_8
-#else
-#define VMALLOC_START     KSEG_D
-#define VMALLOC_END       KSEG_E
-#endif
-
-#endif
-
diff --git a/include/asm-cris/arch-v10/processor.h b/include/asm-cris/arch-v10/processor.h
deleted file mode 100644
index cc692c7a0660..000000000000
--- a/include/asm-cris/arch-v10/processor.h
+++ /dev/null
@@ -1,70 +0,0 @@
-#ifndef __ASM_CRIS_ARCH_PROCESSOR_H
-#define __ASM_CRIS_ARCH_PROCESSOR_H
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({void *pc; __asm__ ("move.d $pc,%0" : "=rm" (pc)); pc; })
-
-/* CRIS has no problems with write protection */
-#define wp_works_ok 1
-
-/* CRIS thread_struct. this really has nothing to do with the processor itself, since
- * CRIS does not do any hardware task-switching, but it's here for legacy reasons.
- * The thread_struct here is used when task-switching using _resume defined in entry.S.
- * The offsets here are hardcoded into _resume - if you change this struct, you need to
- * change them as well!!!
-*/
-
-struct thread_struct {
-	unsigned long ksp;     /* kernel stack pointer */
-	unsigned long usp;     /* user stack pointer */
-	unsigned long dccr;    /* saved flag register */
-};
-
-/*
- * User space process size. This is hardcoded into a few places,
- * so don't change it unless you know what you are doing.
- */
-
-#ifdef CONFIG_CRIS_LOW_MAP
-#define TASK_SIZE       (0x50000000UL)   /* 1.25 GB */
-#else
-#define TASK_SIZE       (0xA0000000UL)   /* 2.56 GB */
-#endif
-
-#define INIT_THREAD  { \
-   0, 0, 0x20 }  /* ccr = int enable, nothing else */
-
-#define KSTK_EIP(tsk)	\
-({			\
-	unsigned long eip = 0;   \
-	unsigned long regs = (unsigned long)task_pt_regs(tsk); \
-	if (regs > PAGE_SIZE && \
-		virt_addr_valid(regs)) \
-	eip = ((struct pt_regs *)regs)->irp; \
-	eip; \
-})
-
-/* give the thread a program location
- * set user-mode (The 'U' flag (User mode flag) is CCR/DCCR bit 8) 
- * switch user-stackpointer
- */
-
-#define start_thread(regs, ip, usp) do { \
-	set_fs(USER_DS);      \
-	regs->irp = ip;       \
-	regs->dccr |= 1 << U_DCCR_BITNR; \
-	wrusp(usp);           \
-} while(0)
-
-/* Called when handling a kernel bus fault fixup.
- *
- * After a fixup we do not want to return by restoring the CPU-state
- * anymore, so switch frame-types (see ptrace.h)
- */
-#define arch_fixup(regs) \
-   regs->frametype = CRIS_FRAME_NORMAL;
-
-#endif
diff --git a/include/asm-cris/arch-v10/ptrace.h b/include/asm-cris/arch-v10/ptrace.h
deleted file mode 100644
index 2f464eab3a51..000000000000
--- a/include/asm-cris/arch-v10/ptrace.h
+++ /dev/null
@@ -1,119 +0,0 @@
-#ifndef _CRIS_ARCH_PTRACE_H
-#define _CRIS_ARCH_PTRACE_H
-
-/* Frame types */
-
-#define CRIS_FRAME_NORMAL   0 /* normal frame without SBFS stacking */
-#define CRIS_FRAME_BUSFAULT 1 /* frame stacked using SBFS, need RBF return
-				 path */
-
-/* Register numbers in the ptrace system call interface */
-
-#define PT_FRAMETYPE 0
-#define PT_ORIG_R10  1
-#define PT_R13       2
-#define PT_R12       3
-#define PT_R11       4
-#define PT_R10       5
-#define PT_R9        6
-#define PT_R8        7
-#define PT_R7        8
-#define PT_R6        9
-#define PT_R5        10
-#define PT_R4        11
-#define PT_R3        12
-#define PT_R2        13
-#define PT_R1        14
-#define PT_R0        15
-#define PT_MOF       16
-#define PT_DCCR      17
-#define PT_SRP       18
-#define PT_IRP       19    /* This is actually the debugged process' PC */
-#define PT_CSRINSTR  20    /* CPU Status record remnants -
-			      valid if frametype == busfault */
-#define PT_CSRADDR   21
-#define PT_CSRDATA   22
-#define PT_USP       23    /* special case - USP is not in the pt_regs */
-#define PT_MAX       23
-
-/* Condition code bit numbers.  The same numbers apply to CCR of course,
-   but we use DCCR everywhere else, so let's try and be consistent.  */
-#define C_DCCR_BITNR 0
-#define V_DCCR_BITNR 1
-#define Z_DCCR_BITNR 2
-#define N_DCCR_BITNR 3
-#define X_DCCR_BITNR 4
-#define I_DCCR_BITNR 5
-#define B_DCCR_BITNR 6
-#define M_DCCR_BITNR 7
-#define U_DCCR_BITNR 8
-#define P_DCCR_BITNR 9
-#define F_DCCR_BITNR 10
-
-/* pt_regs not only specifices the format in the user-struct during
- * ptrace but is also the frame format used in the kernel prologue/epilogues 
- * themselves
- */
-
-struct pt_regs {
-	unsigned long frametype;  /* type of stackframe */
-	unsigned long orig_r10;
-	/* pushed by movem r13, [sp] in SAVE_ALL, movem pushes backwards */
-	unsigned long r13;
-	unsigned long r12;
-	unsigned long r11;
-	unsigned long r10;
-	unsigned long r9;
-	unsigned long r8;
-	unsigned long r7;
-	unsigned long r6;
-	unsigned long r5;
-	unsigned long r4;
-	unsigned long r3;
-	unsigned long r2;
-	unsigned long r1;
-	unsigned long r0;
-	unsigned long mof;
-	unsigned long dccr;
-	unsigned long srp;
-	unsigned long irp; /* This is actually the debugged process' PC */
-	unsigned long csrinstr;
-	unsigned long csraddr;
-	unsigned long csrdata;
-};
-
-/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S)
- * when doing a context-switch. it is used (apart from in resume) when a new
- * thread is made and we need to make _resume (which is starting it for the
- * first time) realise what is going on.
- *
- * Actually, the use is very close to the thread struct (TSS) in that both the
- * switch_stack and the TSS are used to keep thread stuff when switching in
- * _resume.
- */
-
-struct switch_stack {
-	unsigned long r9;
-	unsigned long r8;
-	unsigned long r7;
-	unsigned long r6;
-	unsigned long r5;
-	unsigned long r4;
-	unsigned long r3;
-	unsigned long r2;
-	unsigned long r1;
-	unsigned long r0;
-	unsigned long return_ip; /* ip that _resume will return to */
-};
-
-#ifdef __KERNEL__
-
-/* bit 8 is user-mode flag */
-#define user_mode(regs) (((regs)->dccr & 0x100) != 0)
-#define instruction_pointer(regs) ((regs)->irp)
-#define profile_pc(regs) instruction_pointer(regs)
-extern void show_regs(struct pt_regs *);
-
-#endif  /*  __KERNEL__  */
-
-#endif
diff --git a/include/asm-cris/arch-v10/sv_addr.agh b/include/asm-cris/arch-v10/sv_addr.agh
deleted file mode 100644
index 6ac3a7bc9760..000000000000
--- a/include/asm-cris/arch-v10/sv_addr.agh
+++ /dev/null
@@ -1,7306 +0,0 @@
-/*
-!* This file was automatically generated by /n/asic/bin/reg_macro_gen
-!* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd'.
-!* Editing within this file is thus not recommended,
-!* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead.
-!*/
-
-
-/*
-!* Bus interface configuration registers
-!*/
-
-#define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000)
-#define R_WAITSTATES__pcs4_7_zw__BITNR 30
-#define R_WAITSTATES__pcs4_7_zw__WIDTH 2
-#define R_WAITSTATES__pcs4_7_ew__BITNR 28
-#define R_WAITSTATES__pcs4_7_ew__WIDTH 2
-#define R_WAITSTATES__pcs4_7_lw__BITNR 24
-#define R_WAITSTATES__pcs4_7_lw__WIDTH 4
-#define R_WAITSTATES__pcs0_3_zw__BITNR 22
-#define R_WAITSTATES__pcs0_3_zw__WIDTH 2
-#define R_WAITSTATES__pcs0_3_ew__BITNR 20
-#define R_WAITSTATES__pcs0_3_ew__WIDTH 2
-#define R_WAITSTATES__pcs0_3_lw__BITNR 16
-#define R_WAITSTATES__pcs0_3_lw__WIDTH 4
-#define R_WAITSTATES__sram_zw__BITNR 14
-#define R_WAITSTATES__sram_zw__WIDTH 2
-#define R_WAITSTATES__sram_ew__BITNR 12
-#define R_WAITSTATES__sram_ew__WIDTH 2
-#define R_WAITSTATES__sram_lw__BITNR 8
-#define R_WAITSTATES__sram_lw__WIDTH 4
-#define R_WAITSTATES__flash_zw__BITNR 6
-#define R_WAITSTATES__flash_zw__WIDTH 2
-#define R_WAITSTATES__flash_ew__BITNR 4
-#define R_WAITSTATES__flash_ew__WIDTH 2
-#define R_WAITSTATES__flash_lw__BITNR 0
-#define R_WAITSTATES__flash_lw__WIDTH 4
-
-#define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004)
-#define R_BUS_CONFIG__sram_type__BITNR 9
-#define R_BUS_CONFIG__sram_type__WIDTH 1
-#define R_BUS_CONFIG__sram_type__cwe 1
-#define R_BUS_CONFIG__sram_type__bwe 0
-#define R_BUS_CONFIG__dma_burst__BITNR 8
-#define R_BUS_CONFIG__dma_burst__WIDTH 1
-#define R_BUS_CONFIG__dma_burst__burst16 1
-#define R_BUS_CONFIG__dma_burst__burst32 0
-#define R_BUS_CONFIG__pcs4_7_wr__BITNR 7
-#define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1
-#define R_BUS_CONFIG__pcs4_7_wr__ext 1
-#define R_BUS_CONFIG__pcs4_7_wr__norm 0
-#define R_BUS_CONFIG__pcs0_3_wr__BITNR 6
-#define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1
-#define R_BUS_CONFIG__pcs0_3_wr__ext 1
-#define R_BUS_CONFIG__pcs0_3_wr__norm 0
-#define R_BUS_CONFIG__sram_wr__BITNR 5
-#define R_BUS_CONFIG__sram_wr__WIDTH 1
-#define R_BUS_CONFIG__sram_wr__ext 1
-#define R_BUS_CONFIG__sram_wr__norm 0
-#define R_BUS_CONFIG__flash_wr__BITNR 4
-#define R_BUS_CONFIG__flash_wr__WIDTH 1
-#define R_BUS_CONFIG__flash_wr__ext 1
-#define R_BUS_CONFIG__flash_wr__norm 0
-#define R_BUS_CONFIG__pcs4_7_bw__BITNR 3
-#define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1
-#define R_BUS_CONFIG__pcs4_7_bw__bw32 1
-#define R_BUS_CONFIG__pcs4_7_bw__bw16 0
-#define R_BUS_CONFIG__pcs0_3_bw__BITNR 2
-#define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1
-#define R_BUS_CONFIG__pcs0_3_bw__bw32 1
-#define R_BUS_CONFIG__pcs0_3_bw__bw16 0
-#define R_BUS_CONFIG__sram_bw__BITNR 1
-#define R_BUS_CONFIG__sram_bw__WIDTH 1
-#define R_BUS_CONFIG__sram_bw__bw32 1
-#define R_BUS_CONFIG__sram_bw__bw16 0
-#define R_BUS_CONFIG__flash_bw__BITNR 0
-#define R_BUS_CONFIG__flash_bw__WIDTH 1
-#define R_BUS_CONFIG__flash_bw__bw32 1
-#define R_BUS_CONFIG__flash_bw__bw16 0
-
-#define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004)
-#define R_BUS_STATUS__pll_lock_tm__BITNR 5
-#define R_BUS_STATUS__pll_lock_tm__WIDTH 1
-#define R_BUS_STATUS__pll_lock_tm__expired 0
-#define R_BUS_STATUS__pll_lock_tm__counting 1
-#define R_BUS_STATUS__both_faults__BITNR 4
-#define R_BUS_STATUS__both_faults__WIDTH 1
-#define R_BUS_STATUS__both_faults__no 0
-#define R_BUS_STATUS__both_faults__yes 1
-#define R_BUS_STATUS__bsen___BITNR 3
-#define R_BUS_STATUS__bsen___WIDTH 1
-#define R_BUS_STATUS__bsen___enable 0
-#define R_BUS_STATUS__bsen___disable 1
-#define R_BUS_STATUS__boot__BITNR 1
-#define R_BUS_STATUS__boot__WIDTH 2
-#define R_BUS_STATUS__boot__uncached 0
-#define R_BUS_STATUS__boot__serial 1
-#define R_BUS_STATUS__boot__network 2
-#define R_BUS_STATUS__boot__parallel 3
-#define R_BUS_STATUS__flashw__BITNR 0
-#define R_BUS_STATUS__flashw__WIDTH 1
-#define R_BUS_STATUS__flashw__bw32 1
-#define R_BUS_STATUS__flashw__bw16 0
-
-#define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008)
-#define R_DRAM_TIMING__sdram__BITNR 31
-#define R_DRAM_TIMING__sdram__WIDTH 1
-#define R_DRAM_TIMING__sdram__enable 1
-#define R_DRAM_TIMING__sdram__disable 0
-#define R_DRAM_TIMING__ref__BITNR 14
-#define R_DRAM_TIMING__ref__WIDTH 2
-#define R_DRAM_TIMING__ref__e52us 0
-#define R_DRAM_TIMING__ref__e13us 1
-#define R_DRAM_TIMING__ref__e8700ns 2
-#define R_DRAM_TIMING__ref__disable 3
-#define R_DRAM_TIMING__rp__BITNR 12
-#define R_DRAM_TIMING__rp__WIDTH 2
-#define R_DRAM_TIMING__rs__BITNR 10
-#define R_DRAM_TIMING__rs__WIDTH 2
-#define R_DRAM_TIMING__rh__BITNR 8
-#define R_DRAM_TIMING__rh__WIDTH 2
-#define R_DRAM_TIMING__w__BITNR 7
-#define R_DRAM_TIMING__w__WIDTH 1
-#define R_DRAM_TIMING__w__norm 0
-#define R_DRAM_TIMING__w__ext 1
-#define R_DRAM_TIMING__c__BITNR 6
-#define R_DRAM_TIMING__c__WIDTH 1
-#define R_DRAM_TIMING__c__norm 0
-#define R_DRAM_TIMING__c__ext 1
-#define R_DRAM_TIMING__cz__BITNR 4
-#define R_DRAM_TIMING__cz__WIDTH 2
-#define R_DRAM_TIMING__cp__BITNR 2
-#define R_DRAM_TIMING__cp__WIDTH 2
-#define R_DRAM_TIMING__cw__BITNR 0
-#define R_DRAM_TIMING__cw__WIDTH 2
-
-#define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008)
-#define R_SDRAM_TIMING__sdram__BITNR 31
-#define R_SDRAM_TIMING__sdram__WIDTH 1
-#define R_SDRAM_TIMING__sdram__enable 1
-#define R_SDRAM_TIMING__sdram__disable 0
-#define R_SDRAM_TIMING__mrs_data__BITNR 16
-#define R_SDRAM_TIMING__mrs_data__WIDTH 15
-#define R_SDRAM_TIMING__ref__BITNR 14
-#define R_SDRAM_TIMING__ref__WIDTH 2
-#define R_SDRAM_TIMING__ref__e52us 0
-#define R_SDRAM_TIMING__ref__e13us 1
-#define R_SDRAM_TIMING__ref__e6500ns 2
-#define R_SDRAM_TIMING__ref__disable 3
-#define R_SDRAM_TIMING__ddr__BITNR 13
-#define R_SDRAM_TIMING__ddr__WIDTH 1
-#define R_SDRAM_TIMING__ddr__on 1
-#define R_SDRAM_TIMING__ddr__off 0
-#define R_SDRAM_TIMING__clk100__BITNR 12
-#define R_SDRAM_TIMING__clk100__WIDTH 1
-#define R_SDRAM_TIMING__clk100__on 1
-#define R_SDRAM_TIMING__clk100__off 0
-#define R_SDRAM_TIMING__ps__BITNR 11
-#define R_SDRAM_TIMING__ps__WIDTH 1
-#define R_SDRAM_TIMING__ps__on 1
-#define R_SDRAM_TIMING__ps__off 0
-#define R_SDRAM_TIMING__cmd__BITNR 9
-#define R_SDRAM_TIMING__cmd__WIDTH 2
-#define R_SDRAM_TIMING__cmd__pre 3
-#define R_SDRAM_TIMING__cmd__ref 2
-#define R_SDRAM_TIMING__cmd__mrs 1
-#define R_SDRAM_TIMING__cmd__nop 0
-#define R_SDRAM_TIMING__pde__BITNR 8
-#define R_SDRAM_TIMING__pde__WIDTH 1
-#define R_SDRAM_TIMING__rc__BITNR 6
-#define R_SDRAM_TIMING__rc__WIDTH 2
-#define R_SDRAM_TIMING__rp__BITNR 4
-#define R_SDRAM_TIMING__rp__WIDTH 2
-#define R_SDRAM_TIMING__rcd__BITNR 2
-#define R_SDRAM_TIMING__rcd__WIDTH 2
-#define R_SDRAM_TIMING__cl__BITNR 0
-#define R_SDRAM_TIMING__cl__WIDTH 2
-
-#define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c)
-#define R_DRAM_CONFIG__wmm1__BITNR 31
-#define R_DRAM_CONFIG__wmm1__WIDTH 1
-#define R_DRAM_CONFIG__wmm1__wmm 1
-#define R_DRAM_CONFIG__wmm1__norm 0
-#define R_DRAM_CONFIG__wmm0__BITNR 30
-#define R_DRAM_CONFIG__wmm0__WIDTH 1
-#define R_DRAM_CONFIG__wmm0__wmm 1
-#define R_DRAM_CONFIG__wmm0__norm 0
-#define R_DRAM_CONFIG__sh1__BITNR 27
-#define R_DRAM_CONFIG__sh1__WIDTH 3
-#define R_DRAM_CONFIG__sh0__BITNR 24
-#define R_DRAM_CONFIG__sh0__WIDTH 3
-#define R_DRAM_CONFIG__w__BITNR 23
-#define R_DRAM_CONFIG__w__WIDTH 1
-#define R_DRAM_CONFIG__w__bw16 0
-#define R_DRAM_CONFIG__w__bw32 1
-#define R_DRAM_CONFIG__c__BITNR 22
-#define R_DRAM_CONFIG__c__WIDTH 1
-#define R_DRAM_CONFIG__c__byte 0
-#define R_DRAM_CONFIG__c__bank 1
-#define R_DRAM_CONFIG__e__BITNR 21
-#define R_DRAM_CONFIG__e__WIDTH 1
-#define R_DRAM_CONFIG__e__fast 0
-#define R_DRAM_CONFIG__e__edo 1
-#define R_DRAM_CONFIG__group_sel__BITNR 16
-#define R_DRAM_CONFIG__group_sel__WIDTH 5
-#define R_DRAM_CONFIG__group_sel__grp0 0
-#define R_DRAM_CONFIG__group_sel__grp1 1
-#define R_DRAM_CONFIG__group_sel__bit9 9
-#define R_DRAM_CONFIG__group_sel__bit10 10
-#define R_DRAM_CONFIG__group_sel__bit11 11
-#define R_DRAM_CONFIG__group_sel__bit12 12
-#define R_DRAM_CONFIG__group_sel__bit13 13
-#define R_DRAM_CONFIG__group_sel__bit14 14
-#define R_DRAM_CONFIG__group_sel__bit15 15
-#define R_DRAM_CONFIG__group_sel__bit16 16
-#define R_DRAM_CONFIG__group_sel__bit17 17
-#define R_DRAM_CONFIG__group_sel__bit18 18
-#define R_DRAM_CONFIG__group_sel__bit19 19
-#define R_DRAM_CONFIG__group_sel__bit20 20
-#define R_DRAM_CONFIG__group_sel__bit21 21
-#define R_DRAM_CONFIG__group_sel__bit22 22
-#define R_DRAM_CONFIG__group_sel__bit23 23
-#define R_DRAM_CONFIG__group_sel__bit24 24
-#define R_DRAM_CONFIG__group_sel__bit25 25
-#define R_DRAM_CONFIG__group_sel__bit26 26
-#define R_DRAM_CONFIG__group_sel__bit27 27
-#define R_DRAM_CONFIG__group_sel__bit28 28
-#define R_DRAM_CONFIG__group_sel__bit29 29
-#define R_DRAM_CONFIG__ca1__BITNR 13
-#define R_DRAM_CONFIG__ca1__WIDTH 3
-#define R_DRAM_CONFIG__bank23sel__BITNR 8
-#define R_DRAM_CONFIG__bank23sel__WIDTH 5
-#define R_DRAM_CONFIG__bank23sel__bank0 0
-#define R_DRAM_CONFIG__bank23sel__bank1 1
-#define R_DRAM_CONFIG__bank23sel__bit9 9
-#define R_DRAM_CONFIG__bank23sel__bit10 10
-#define R_DRAM_CONFIG__bank23sel__bit11 11
-#define R_DRAM_CONFIG__bank23sel__bit12 12
-#define R_DRAM_CONFIG__bank23sel__bit13 13
-#define R_DRAM_CONFIG__bank23sel__bit14 14
-#define R_DRAM_CONFIG__bank23sel__bit15 15
-#define R_DRAM_CONFIG__bank23sel__bit16 16
-#define R_DRAM_CONFIG__bank23sel__bit17 17
-#define R_DRAM_CONFIG__bank23sel__bit18 18
-#define R_DRAM_CONFIG__bank23sel__bit19 19
-#define R_DRAM_CONFIG__bank23sel__bit20 20
-#define R_DRAM_CONFIG__bank23sel__bit21 21
-#define R_DRAM_CONFIG__bank23sel__bit22 22
-#define R_DRAM_CONFIG__bank23sel__bit23 23
-#define R_DRAM_CONFIG__bank23sel__bit24 24
-#define R_DRAM_CONFIG__bank23sel__bit25 25
-#define R_DRAM_CONFIG__bank23sel__bit26 26
-#define R_DRAM_CONFIG__bank23sel__bit27 27
-#define R_DRAM_CONFIG__bank23sel__bit28 28
-#define R_DRAM_CONFIG__bank23sel__bit29 29
-#define R_DRAM_CONFIG__ca0__BITNR 5
-#define R_DRAM_CONFIG__ca0__WIDTH 3
-#define R_DRAM_CONFIG__bank01sel__BITNR 0
-#define R_DRAM_CONFIG__bank01sel__WIDTH 5
-#define R_DRAM_CONFIG__bank01sel__bank0 0
-#define R_DRAM_CONFIG__bank01sel__bank1 1
-#define R_DRAM_CONFIG__bank01sel__bit9 9
-#define R_DRAM_CONFIG__bank01sel__bit10 10
-#define R_DRAM_CONFIG__bank01sel__bit11 11
-#define R_DRAM_CONFIG__bank01sel__bit12 12
-#define R_DRAM_CONFIG__bank01sel__bit13 13
-#define R_DRAM_CONFIG__bank01sel__bit14 14
-#define R_DRAM_CONFIG__bank01sel__bit15 15
-#define R_DRAM_CONFIG__bank01sel__bit16 16
-#define R_DRAM_CONFIG__bank01sel__bit17 17
-#define R_DRAM_CONFIG__bank01sel__bit18 18
-#define R_DRAM_CONFIG__bank01sel__bit19 19
-#define R_DRAM_CONFIG__bank01sel__bit20 20
-#define R_DRAM_CONFIG__bank01sel__bit21 21
-#define R_DRAM_CONFIG__bank01sel__bit22 22
-#define R_DRAM_CONFIG__bank01sel__bit23 23
-#define R_DRAM_CONFIG__bank01sel__bit24 24
-#define R_DRAM_CONFIG__bank01sel__bit25 25
-#define R_DRAM_CONFIG__bank01sel__bit26 26
-#define R_DRAM_CONFIG__bank01sel__bit27 27
-#define R_DRAM_CONFIG__bank01sel__bit28 28
-#define R_DRAM_CONFIG__bank01sel__bit29 29
-
-#define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c)
-#define R_SDRAM_CONFIG__wmm1__BITNR 31
-#define R_SDRAM_CONFIG__wmm1__WIDTH 1
-#define R_SDRAM_CONFIG__wmm1__wmm 1
-#define R_SDRAM_CONFIG__wmm1__norm 0
-#define R_SDRAM_CONFIG__wmm0__BITNR 30
-#define R_SDRAM_CONFIG__wmm0__WIDTH 1
-#define R_SDRAM_CONFIG__wmm0__wmm 1
-#define R_SDRAM_CONFIG__wmm0__norm 0
-#define R_SDRAM_CONFIG__sh1__BITNR 27
-#define R_SDRAM_CONFIG__sh1__WIDTH 3
-#define R_SDRAM_CONFIG__sh0__BITNR 24
-#define R_SDRAM_CONFIG__sh0__WIDTH 3
-#define R_SDRAM_CONFIG__w__BITNR 23
-#define R_SDRAM_CONFIG__w__WIDTH 1
-#define R_SDRAM_CONFIG__w__bw16 0
-#define R_SDRAM_CONFIG__w__bw32 1
-#define R_SDRAM_CONFIG__type1__BITNR 22
-#define R_SDRAM_CONFIG__type1__WIDTH 1
-#define R_SDRAM_CONFIG__type1__bank2 0
-#define R_SDRAM_CONFIG__type1__bank4 1
-#define R_SDRAM_CONFIG__type0__BITNR 21
-#define R_SDRAM_CONFIG__type0__WIDTH 1
-#define R_SDRAM_CONFIG__type0__bank2 0
-#define R_SDRAM_CONFIG__type0__bank4 1
-#define R_SDRAM_CONFIG__group_sel__BITNR 16
-#define R_SDRAM_CONFIG__group_sel__WIDTH 5
-#define R_SDRAM_CONFIG__group_sel__grp0 0
-#define R_SDRAM_CONFIG__group_sel__grp1 1
-#define R_SDRAM_CONFIG__group_sel__bit9 9
-#define R_SDRAM_CONFIG__group_sel__bit10 10
-#define R_SDRAM_CONFIG__group_sel__bit11 11
-#define R_SDRAM_CONFIG__group_sel__bit12 12
-#define R_SDRAM_CONFIG__group_sel__bit13 13
-#define R_SDRAM_CONFIG__group_sel__bit14 14
-#define R_SDRAM_CONFIG__group_sel__bit15 15
-#define R_SDRAM_CONFIG__group_sel__bit16 16
-#define R_SDRAM_CONFIG__group_sel__bit17 17
-#define R_SDRAM_CONFIG__group_sel__bit18 18
-#define R_SDRAM_CONFIG__group_sel__bit19 19
-#define R_SDRAM_CONFIG__group_sel__bit20 20
-#define R_SDRAM_CONFIG__group_sel__bit21 21
-#define R_SDRAM_CONFIG__group_sel__bit22 22
-#define R_SDRAM_CONFIG__group_sel__bit23 23
-#define R_SDRAM_CONFIG__group_sel__bit24 24
-#define R_SDRAM_CONFIG__group_sel__bit25 25
-#define R_SDRAM_CONFIG__group_sel__bit26 26
-#define R_SDRAM_CONFIG__group_sel__bit27 27
-#define R_SDRAM_CONFIG__group_sel__bit28 28
-#define R_SDRAM_CONFIG__group_sel__bit29 29
-#define R_SDRAM_CONFIG__ca1__BITNR 13
-#define R_SDRAM_CONFIG__ca1__WIDTH 3
-#define R_SDRAM_CONFIG__bank_sel1__BITNR 8
-#define R_SDRAM_CONFIG__bank_sel1__WIDTH 5
-#define R_SDRAM_CONFIG__bank_sel1__bit9 9
-#define R_SDRAM_CONFIG__bank_sel1__bit10 10
-#define R_SDRAM_CONFIG__bank_sel1__bit11 11
-#define R_SDRAM_CONFIG__bank_sel1__bit12 12
-#define R_SDRAM_CONFIG__bank_sel1__bit13 13
-#define R_SDRAM_CONFIG__bank_sel1__bit14 14
-#define R_SDRAM_CONFIG__bank_sel1__bit15 15
-#define R_SDRAM_CONFIG__bank_sel1__bit16 16
-#define R_SDRAM_CONFIG__bank_sel1__bit17 17
-#define R_SDRAM_CONFIG__bank_sel1__bit18 18
-#define R_SDRAM_CONFIG__bank_sel1__bit19 19
-#define R_SDRAM_CONFIG__bank_sel1__bit20 20
-#define R_SDRAM_CONFIG__bank_sel1__bit21 21
-#define R_SDRAM_CONFIG__bank_sel1__bit22 22
-#define R_SDRAM_CONFIG__bank_sel1__bit23 23
-#define R_SDRAM_CONFIG__bank_sel1__bit24 24
-#define R_SDRAM_CONFIG__bank_sel1__bit25 25
-#define R_SDRAM_CONFIG__bank_sel1__bit26 26
-#define R_SDRAM_CONFIG__bank_sel1__bit27 27
-#define R_SDRAM_CONFIG__bank_sel1__bit28 28
-#define R_SDRAM_CONFIG__bank_sel1__bit29 29
-#define R_SDRAM_CONFIG__ca0__BITNR 5
-#define R_SDRAM_CONFIG__ca0__WIDTH 3
-#define R_SDRAM_CONFIG__bank_sel0__BITNR 0
-#define R_SDRAM_CONFIG__bank_sel0__WIDTH 5
-#define R_SDRAM_CONFIG__bank_sel0__bit9 9
-#define R_SDRAM_CONFIG__bank_sel0__bit10 10
-#define R_SDRAM_CONFIG__bank_sel0__bit11 11
-#define R_SDRAM_CONFIG__bank_sel0__bit12 12
-#define R_SDRAM_CONFIG__bank_sel0__bit13 13
-#define R_SDRAM_CONFIG__bank_sel0__bit14 14
-#define R_SDRAM_CONFIG__bank_sel0__bit15 15
-#define R_SDRAM_CONFIG__bank_sel0__bit16 16
-#define R_SDRAM_CONFIG__bank_sel0__bit17 17
-#define R_SDRAM_CONFIG__bank_sel0__bit18 18
-#define R_SDRAM_CONFIG__bank_sel0__bit19 19
-#define R_SDRAM_CONFIG__bank_sel0__bit20 20
-#define R_SDRAM_CONFIG__bank_sel0__bit21 21
-#define R_SDRAM_CONFIG__bank_sel0__bit22 22
-#define R_SDRAM_CONFIG__bank_sel0__bit23 23
-#define R_SDRAM_CONFIG__bank_sel0__bit24 24
-#define R_SDRAM_CONFIG__bank_sel0__bit25 25
-#define R_SDRAM_CONFIG__bank_sel0__bit26 26
-#define R_SDRAM_CONFIG__bank_sel0__bit27 27
-#define R_SDRAM_CONFIG__bank_sel0__bit28 28
-#define R_SDRAM_CONFIG__bank_sel0__bit29 29
-
-/*
-!* External DMA registers
-!*/
-
-#define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010)
-#define R_EXT_DMA_0_CMD__cnt__BITNR 23
-#define R_EXT_DMA_0_CMD__cnt__WIDTH 1
-#define R_EXT_DMA_0_CMD__cnt__enable 1
-#define R_EXT_DMA_0_CMD__cnt__disable 0
-#define R_EXT_DMA_0_CMD__rqpol__BITNR 22
-#define R_EXT_DMA_0_CMD__rqpol__WIDTH 1
-#define R_EXT_DMA_0_CMD__rqpol__ahigh 0
-#define R_EXT_DMA_0_CMD__rqpol__alow 1
-#define R_EXT_DMA_0_CMD__apol__BITNR 21
-#define R_EXT_DMA_0_CMD__apol__WIDTH 1
-#define R_EXT_DMA_0_CMD__apol__ahigh 0
-#define R_EXT_DMA_0_CMD__apol__alow 1
-#define R_EXT_DMA_0_CMD__rq_ack__BITNR 20
-#define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1
-#define R_EXT_DMA_0_CMD__rq_ack__burst 0
-#define R_EXT_DMA_0_CMD__rq_ack__handsh 1
-#define R_EXT_DMA_0_CMD__wid__BITNR 18
-#define R_EXT_DMA_0_CMD__wid__WIDTH 2
-#define R_EXT_DMA_0_CMD__wid__byte 0
-#define R_EXT_DMA_0_CMD__wid__word 1
-#define R_EXT_DMA_0_CMD__wid__dword 2
-#define R_EXT_DMA_0_CMD__dir__BITNR 17
-#define R_EXT_DMA_0_CMD__dir__WIDTH 1
-#define R_EXT_DMA_0_CMD__dir__input 0
-#define R_EXT_DMA_0_CMD__dir__output 1
-#define R_EXT_DMA_0_CMD__run__BITNR 16
-#define R_EXT_DMA_0_CMD__run__WIDTH 1
-#define R_EXT_DMA_0_CMD__run__start 1
-#define R_EXT_DMA_0_CMD__run__stop 0
-#define R_EXT_DMA_0_CMD__trf_count__BITNR 0
-#define R_EXT_DMA_0_CMD__trf_count__WIDTH 16
-
-#define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010)
-#define R_EXT_DMA_0_STAT__run__BITNR 16
-#define R_EXT_DMA_0_STAT__run__WIDTH 1
-#define R_EXT_DMA_0_STAT__run__start 1
-#define R_EXT_DMA_0_STAT__run__stop 0
-#define R_EXT_DMA_0_STAT__trf_count__BITNR 0
-#define R_EXT_DMA_0_STAT__trf_count__WIDTH 16
-
-#define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014)
-#define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2
-#define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28
-
-#define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018)
-#define R_EXT_DMA_1_CMD__cnt__BITNR 23
-#define R_EXT_DMA_1_CMD__cnt__WIDTH 1
-#define R_EXT_DMA_1_CMD__cnt__enable 1
-#define R_EXT_DMA_1_CMD__cnt__disable 0
-#define R_EXT_DMA_1_CMD__rqpol__BITNR 22
-#define R_EXT_DMA_1_CMD__rqpol__WIDTH 1
-#define R_EXT_DMA_1_CMD__rqpol__ahigh 0
-#define R_EXT_DMA_1_CMD__rqpol__alow 1
-#define R_EXT_DMA_1_CMD__apol__BITNR 21
-#define R_EXT_DMA_1_CMD__apol__WIDTH 1
-#define R_EXT_DMA_1_CMD__apol__ahigh 0
-#define R_EXT_DMA_1_CMD__apol__alow 1
-#define R_EXT_DMA_1_CMD__rq_ack__BITNR 20
-#define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1
-#define R_EXT_DMA_1_CMD__rq_ack__burst 0
-#define R_EXT_DMA_1_CMD__rq_ack__handsh 1
-#define R_EXT_DMA_1_CMD__wid__BITNR 18
-#define R_EXT_DMA_1_CMD__wid__WIDTH 2
-#define R_EXT_DMA_1_CMD__wid__byte 0
-#define R_EXT_DMA_1_CMD__wid__word 1
-#define R_EXT_DMA_1_CMD__wid__dword 2
-#define R_EXT_DMA_1_CMD__dir__BITNR 17
-#define R_EXT_DMA_1_CMD__dir__WIDTH 1
-#define R_EXT_DMA_1_CMD__dir__input 0
-#define R_EXT_DMA_1_CMD__dir__output 1
-#define R_EXT_DMA_1_CMD__run__BITNR 16
-#define R_EXT_DMA_1_CMD__run__WIDTH 1
-#define R_EXT_DMA_1_CMD__run__start 1
-#define R_EXT_DMA_1_CMD__run__stop 0
-#define R_EXT_DMA_1_CMD__trf_count__BITNR 0
-#define R_EXT_DMA_1_CMD__trf_count__WIDTH 16
-
-#define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018)
-#define R_EXT_DMA_1_STAT__run__BITNR 16
-#define R_EXT_DMA_1_STAT__run__WIDTH 1
-#define R_EXT_DMA_1_STAT__run__start 1
-#define R_EXT_DMA_1_STAT__run__stop 0
-#define R_EXT_DMA_1_STAT__trf_count__BITNR 0
-#define R_EXT_DMA_1_STAT__trf_count__WIDTH 16
-
-#define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c)
-#define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2
-#define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28
-
-/*
-!* Timer registers
-!*/
-
-#define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020)
-#define R_TIMER_CTRL__timerdiv1__BITNR 24
-#define R_TIMER_CTRL__timerdiv1__WIDTH 8
-#define R_TIMER_CTRL__timerdiv0__BITNR 16
-#define R_TIMER_CTRL__timerdiv0__WIDTH 8
-#define R_TIMER_CTRL__presc_timer1__BITNR 15
-#define R_TIMER_CTRL__presc_timer1__WIDTH 1
-#define R_TIMER_CTRL__presc_timer1__normal 0
-#define R_TIMER_CTRL__presc_timer1__prescale 1
-#define R_TIMER_CTRL__i1__BITNR 14
-#define R_TIMER_CTRL__i1__WIDTH 1
-#define R_TIMER_CTRL__i1__clr 1
-#define R_TIMER_CTRL__i1__nop 0
-#define R_TIMER_CTRL__tm1__BITNR 12
-#define R_TIMER_CTRL__tm1__WIDTH 2
-#define R_TIMER_CTRL__tm1__stop_ld 0
-#define R_TIMER_CTRL__tm1__freeze 1
-#define R_TIMER_CTRL__tm1__run 2
-#define R_TIMER_CTRL__tm1__reserved 3
-#define R_TIMER_CTRL__clksel1__BITNR 8
-#define R_TIMER_CTRL__clksel1__WIDTH 4
-#define R_TIMER_CTRL__clksel1__c300Hz 0
-#define R_TIMER_CTRL__clksel1__c600Hz 1
-#define R_TIMER_CTRL__clksel1__c1200Hz 2
-#define R_TIMER_CTRL__clksel1__c2400Hz 3
-#define R_TIMER_CTRL__clksel1__c4800Hz 4
-#define R_TIMER_CTRL__clksel1__c9600Hz 5
-#define R_TIMER_CTRL__clksel1__c19k2Hz 6
-#define R_TIMER_CTRL__clksel1__c38k4Hz 7
-#define R_TIMER_CTRL__clksel1__c57k6Hz 8
-#define R_TIMER_CTRL__clksel1__c115k2Hz 9
-#define R_TIMER_CTRL__clksel1__c230k4Hz 10
-#define R_TIMER_CTRL__clksel1__c460k8Hz 11
-#define R_TIMER_CTRL__clksel1__c921k6Hz 12
-#define R_TIMER_CTRL__clksel1__c1843k2Hz 13
-#define R_TIMER_CTRL__clksel1__c6250kHz 14
-#define R_TIMER_CTRL__clksel1__cascade0 15
-#define R_TIMER_CTRL__presc_ext__BITNR 7
-#define R_TIMER_CTRL__presc_ext__WIDTH 1
-#define R_TIMER_CTRL__presc_ext__prescale 0
-#define R_TIMER_CTRL__presc_ext__external 1
-#define R_TIMER_CTRL__i0__BITNR 6
-#define R_TIMER_CTRL__i0__WIDTH 1
-#define R_TIMER_CTRL__i0__clr 1
-#define R_TIMER_CTRL__i0__nop 0
-#define R_TIMER_CTRL__tm0__BITNR 4
-#define R_TIMER_CTRL__tm0__WIDTH 2
-#define R_TIMER_CTRL__tm0__stop_ld 0
-#define R_TIMER_CTRL__tm0__freeze 1
-#define R_TIMER_CTRL__tm0__run 2
-#define R_TIMER_CTRL__tm0__reserved 3
-#define R_TIMER_CTRL__clksel0__BITNR 0
-#define R_TIMER_CTRL__clksel0__WIDTH 4
-#define R_TIMER_CTRL__clksel0__c300Hz 0
-#define R_TIMER_CTRL__clksel0__c600Hz 1
-#define R_TIMER_CTRL__clksel0__c1200Hz 2
-#define R_TIMER_CTRL__clksel0__c2400Hz 3
-#define R_TIMER_CTRL__clksel0__c4800Hz 4
-#define R_TIMER_CTRL__clksel0__c9600Hz 5
-#define R_TIMER_CTRL__clksel0__c19k2Hz 6
-#define R_TIMER_CTRL__clksel0__c38k4Hz 7
-#define R_TIMER_CTRL__clksel0__c57k6Hz 8
-#define R_TIMER_CTRL__clksel0__c115k2Hz 9
-#define R_TIMER_CTRL__clksel0__c230k4Hz 10
-#define R_TIMER_CTRL__clksel0__c460k8Hz 11
-#define R_TIMER_CTRL__clksel0__c921k6Hz 12
-#define R_TIMER_CTRL__clksel0__c1843k2Hz 13
-#define R_TIMER_CTRL__clksel0__c6250kHz 14
-#define R_TIMER_CTRL__clksel0__flexible 15
-
-#define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020)
-#define R_TIMER_DATA__timer1__BITNR 24
-#define R_TIMER_DATA__timer1__WIDTH 8
-#define R_TIMER_DATA__timer0__BITNR 16
-#define R_TIMER_DATA__timer0__WIDTH 8
-#define R_TIMER_DATA__clkdiv_high__BITNR 8
-#define R_TIMER_DATA__clkdiv_high__WIDTH 8
-#define R_TIMER_DATA__clkdiv_low__BITNR 0
-#define R_TIMER_DATA__clkdiv_low__WIDTH 8
-
-#define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022)
-#define R_TIMER01_DATA__count__BITNR 0
-#define R_TIMER01_DATA__count__WIDTH 16
-
-#define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022)
-#define R_TIMER0_DATA__count__BITNR 0
-#define R_TIMER0_DATA__count__WIDTH 8
-
-#define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023)
-#define R_TIMER1_DATA__count__BITNR 0
-#define R_TIMER1_DATA__count__WIDTH 8
-
-#define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024)
-#define R_WATCHDOG__key__BITNR 1
-#define R_WATCHDOG__key__WIDTH 3
-#define R_WATCHDOG__enable__BITNR 0
-#define R_WATCHDOG__enable__WIDTH 1
-#define R_WATCHDOG__enable__stop 0
-#define R_WATCHDOG__enable__start 1
-
-#define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0)
-#define R_CLOCK_PRESCALE__ser_presc__BITNR 16
-#define R_CLOCK_PRESCALE__ser_presc__WIDTH 16
-#define R_CLOCK_PRESCALE__tim_presc__BITNR 0
-#define R_CLOCK_PRESCALE__tim_presc__WIDTH 16
-
-#define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2)
-#define R_SERIAL_PRESCALE__ser_presc__BITNR 0
-#define R_SERIAL_PRESCALE__ser_presc__WIDTH 16
-
-#define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0)
-#define R_TIMER_PRESCALE__tim_presc__BITNR 0
-#define R_TIMER_PRESCALE__tim_presc__WIDTH 16
-
-#define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0)
-#define R_PRESCALE_STATUS__ser_status__BITNR 16
-#define R_PRESCALE_STATUS__ser_status__WIDTH 16
-#define R_PRESCALE_STATUS__tim_status__BITNR 0
-#define R_PRESCALE_STATUS__tim_status__WIDTH 16
-
-#define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2)
-#define R_SER_PRESC_STATUS__ser_status__BITNR 0
-#define R_SER_PRESC_STATUS__ser_status__WIDTH 16
-
-#define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0)
-#define R_TIM_PRESC_STATUS__tim_status__BITNR 0
-#define R_TIM_PRESC_STATUS__tim_status__WIDTH 16
-
-#define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4)
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1
-#define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16
-#define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7
-#define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15
-#define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1
-#define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0
-#define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1
-#define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11
-#define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4
-#define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0
-#define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10
-
-/*
-!* Shared RAM interface registers
-!*/
-
-#define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040)
-#define R_SHARED_RAM_CONFIG__width__BITNR 3
-#define R_SHARED_RAM_CONFIG__width__WIDTH 1
-#define R_SHARED_RAM_CONFIG__width__byte 0
-#define R_SHARED_RAM_CONFIG__width__word 1
-#define R_SHARED_RAM_CONFIG__enable__BITNR 2
-#define R_SHARED_RAM_CONFIG__enable__WIDTH 1
-#define R_SHARED_RAM_CONFIG__enable__yes 1
-#define R_SHARED_RAM_CONFIG__enable__no 0
-#define R_SHARED_RAM_CONFIG__pint__BITNR 1
-#define R_SHARED_RAM_CONFIG__pint__WIDTH 1
-#define R_SHARED_RAM_CONFIG__pint__int 1
-#define R_SHARED_RAM_CONFIG__pint__nop 0
-#define R_SHARED_RAM_CONFIG__clri__BITNR 0
-#define R_SHARED_RAM_CONFIG__clri__WIDTH 1
-#define R_SHARED_RAM_CONFIG__clri__clr 1
-#define R_SHARED_RAM_CONFIG__clri__nop 0
-
-#define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044)
-#define R_SHARED_RAM_ADDR__base_addr__BITNR 8
-#define R_SHARED_RAM_ADDR__base_addr__WIDTH 22
-
-/*
-!* General config registers
-!*/
-
-#define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c)
-#define R_GEN_CONFIG__par_w__BITNR 31
-#define R_GEN_CONFIG__par_w__WIDTH 1
-#define R_GEN_CONFIG__par_w__select 1
-#define R_GEN_CONFIG__par_w__disable 0
-#define R_GEN_CONFIG__usb2__BITNR 30
-#define R_GEN_CONFIG__usb2__WIDTH 1
-#define R_GEN_CONFIG__usb2__select 1
-#define R_GEN_CONFIG__usb2__disable 0
-#define R_GEN_CONFIG__usb1__BITNR 29
-#define R_GEN_CONFIG__usb1__WIDTH 1
-#define R_GEN_CONFIG__usb1__select 1
-#define R_GEN_CONFIG__usb1__disable 0
-#define R_GEN_CONFIG__g24dir__BITNR 27
-#define R_GEN_CONFIG__g24dir__WIDTH 1
-#define R_GEN_CONFIG__g24dir__in 0
-#define R_GEN_CONFIG__g24dir__out 1
-#define R_GEN_CONFIG__g16_23dir__BITNR 26
-#define R_GEN_CONFIG__g16_23dir__WIDTH 1
-#define R_GEN_CONFIG__g16_23dir__in 0
-#define R_GEN_CONFIG__g16_23dir__out 1
-#define R_GEN_CONFIG__g8_15dir__BITNR 25
-#define R_GEN_CONFIG__g8_15dir__WIDTH 1
-#define R_GEN_CONFIG__g8_15dir__in 0
-#define R_GEN_CONFIG__g8_15dir__out 1
-#define R_GEN_CONFIG__g0dir__BITNR 24
-#define R_GEN_CONFIG__g0dir__WIDTH 1
-#define R_GEN_CONFIG__g0dir__in 0
-#define R_GEN_CONFIG__g0dir__out 1
-#define R_GEN_CONFIG__dma9__BITNR 23
-#define R_GEN_CONFIG__dma9__WIDTH 1
-#define R_GEN_CONFIG__dma9__usb 0
-#define R_GEN_CONFIG__dma9__serial1 1
-#define R_GEN_CONFIG__dma8__BITNR 22
-#define R_GEN_CONFIG__dma8__WIDTH 1
-#define R_GEN_CONFIG__dma8__usb 0
-#define R_GEN_CONFIG__dma8__serial1 1
-#define R_GEN_CONFIG__dma7__BITNR 20
-#define R_GEN_CONFIG__dma7__WIDTH 2
-#define R_GEN_CONFIG__dma7__unused 0
-#define R_GEN_CONFIG__dma7__serial0 1
-#define R_GEN_CONFIG__dma7__extdma1 2
-#define R_GEN_CONFIG__dma7__intdma6 3
-#define R_GEN_CONFIG__dma6__BITNR 18
-#define R_GEN_CONFIG__dma6__WIDTH 2
-#define R_GEN_CONFIG__dma6__unused 0
-#define R_GEN_CONFIG__dma6__serial0 1
-#define R_GEN_CONFIG__dma6__extdma1 2
-#define R_GEN_CONFIG__dma6__intdma7 3
-#define R_GEN_CONFIG__dma5__BITNR 16
-#define R_GEN_CONFIG__dma5__WIDTH 2
-#define R_GEN_CONFIG__dma5__par1 0
-#define R_GEN_CONFIG__dma5__scsi1 1
-#define R_GEN_CONFIG__dma5__serial3 2
-#define R_GEN_CONFIG__dma5__extdma0 3
-#define R_GEN_CONFIG__dma4__BITNR 14
-#define R_GEN_CONFIG__dma4__WIDTH 2
-#define R_GEN_CONFIG__dma4__par1 0
-#define R_GEN_CONFIG__dma4__scsi1 1
-#define R_GEN_CONFIG__dma4__serial3 2
-#define R_GEN_CONFIG__dma4__extdma0 3
-#define R_GEN_CONFIG__dma3__BITNR 12
-#define R_GEN_CONFIG__dma3__WIDTH 2
-#define R_GEN_CONFIG__dma3__par0 0
-#define R_GEN_CONFIG__dma3__scsi0 1
-#define R_GEN_CONFIG__dma3__serial2 2
-#define R_GEN_CONFIG__dma3__ata 3
-#define R_GEN_CONFIG__dma2__BITNR 10
-#define R_GEN_CONFIG__dma2__WIDTH 2
-#define R_GEN_CONFIG__dma2__par0 0
-#define R_GEN_CONFIG__dma2__scsi0 1
-#define R_GEN_CONFIG__dma2__serial2 2
-#define R_GEN_CONFIG__dma2__ata 3
-#define R_GEN_CONFIG__mio_w__BITNR 9
-#define R_GEN_CONFIG__mio_w__WIDTH 1
-#define R_GEN_CONFIG__mio_w__select 1
-#define R_GEN_CONFIG__mio_w__disable 0
-#define R_GEN_CONFIG__ser3__BITNR 8
-#define R_GEN_CONFIG__ser3__WIDTH 1
-#define R_GEN_CONFIG__ser3__select 1
-#define R_GEN_CONFIG__ser3__disable 0
-#define R_GEN_CONFIG__par1__BITNR 7
-#define R_GEN_CONFIG__par1__WIDTH 1
-#define R_GEN_CONFIG__par1__select 1
-#define R_GEN_CONFIG__par1__disable 0
-#define R_GEN_CONFIG__scsi0w__BITNR 6
-#define R_GEN_CONFIG__scsi0w__WIDTH 1
-#define R_GEN_CONFIG__scsi0w__select 1
-#define R_GEN_CONFIG__scsi0w__disable 0
-#define R_GEN_CONFIG__scsi1__BITNR 5
-#define R_GEN_CONFIG__scsi1__WIDTH 1
-#define R_GEN_CONFIG__scsi1__select 1
-#define R_GEN_CONFIG__scsi1__disable 0
-#define R_GEN_CONFIG__mio__BITNR 4
-#define R_GEN_CONFIG__mio__WIDTH 1
-#define R_GEN_CONFIG__mio__select 1
-#define R_GEN_CONFIG__mio__disable 0
-#define R_GEN_CONFIG__ser2__BITNR 3
-#define R_GEN_CONFIG__ser2__WIDTH 1
-#define R_GEN_CONFIG__ser2__select 1
-#define R_GEN_CONFIG__ser2__disable 0
-#define R_GEN_CONFIG__par0__BITNR 2
-#define R_GEN_CONFIG__par0__WIDTH 1
-#define R_GEN_CONFIG__par0__select 1
-#define R_GEN_CONFIG__par0__disable 0
-#define R_GEN_CONFIG__ata__BITNR 1
-#define R_GEN_CONFIG__ata__WIDTH 1
-#define R_GEN_CONFIG__ata__select 1
-#define R_GEN_CONFIG__ata__disable 0
-#define R_GEN_CONFIG__scsi0__BITNR 0
-#define R_GEN_CONFIG__scsi0__WIDTH 1
-#define R_GEN_CONFIG__scsi0__select 1
-#define R_GEN_CONFIG__scsi0__disable 0
-
-#define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034)
-#define R_GEN_CONFIG_II__sermode3__BITNR 6
-#define R_GEN_CONFIG_II__sermode3__WIDTH 1
-#define R_GEN_CONFIG_II__sermode3__async 0
-#define R_GEN_CONFIG_II__sermode3__sync 1
-#define R_GEN_CONFIG_II__sermode1__BITNR 4
-#define R_GEN_CONFIG_II__sermode1__WIDTH 1
-#define R_GEN_CONFIG_II__sermode1__async 0
-#define R_GEN_CONFIG_II__sermode1__sync 1
-#define R_GEN_CONFIG_II__ext_clk__BITNR 2
-#define R_GEN_CONFIG_II__ext_clk__WIDTH 1
-#define R_GEN_CONFIG_II__ext_clk__select 1
-#define R_GEN_CONFIG_II__ext_clk__disable 0
-#define R_GEN_CONFIG_II__ser2__BITNR 1
-#define R_GEN_CONFIG_II__ser2__WIDTH 1
-#define R_GEN_CONFIG_II__ser2__select 1
-#define R_GEN_CONFIG_II__ser2__disable 0
-#define R_GEN_CONFIG_II__ser3__BITNR 0
-#define R_GEN_CONFIG_II__ser3__WIDTH 1
-#define R_GEN_CONFIG_II__ser3__select 1
-#define R_GEN_CONFIG_II__ser3__disable 0
-
-#define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028)
-#define R_PORT_G_DATA__data__BITNR 0
-#define R_PORT_G_DATA__data__WIDTH 32
-
-/*
-!* General port configuration registers
-!*/
-
-#define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030)
-#define R_PORT_PA_SET__dir7__BITNR 15
-#define R_PORT_PA_SET__dir7__WIDTH 1
-#define R_PORT_PA_SET__dir7__input 0
-#define R_PORT_PA_SET__dir7__output 1
-#define R_PORT_PA_SET__dir6__BITNR 14
-#define R_PORT_PA_SET__dir6__WIDTH 1
-#define R_PORT_PA_SET__dir6__input 0
-#define R_PORT_PA_SET__dir6__output 1
-#define R_PORT_PA_SET__dir5__BITNR 13
-#define R_PORT_PA_SET__dir5__WIDTH 1
-#define R_PORT_PA_SET__dir5__input 0
-#define R_PORT_PA_SET__dir5__output 1
-#define R_PORT_PA_SET__dir4__BITNR 12
-#define R_PORT_PA_SET__dir4__WIDTH 1
-#define R_PORT_PA_SET__dir4__input 0
-#define R_PORT_PA_SET__dir4__output 1
-#define R_PORT_PA_SET__dir3__BITNR 11
-#define R_PORT_PA_SET__dir3__WIDTH 1
-#define R_PORT_PA_SET__dir3__input 0
-#define R_PORT_PA_SET__dir3__output 1
-#define R_PORT_PA_SET__dir2__BITNR 10
-#define R_PORT_PA_SET__dir2__WIDTH 1
-#define R_PORT_PA_SET__dir2__input 0
-#define R_PORT_PA_SET__dir2__output 1
-#define R_PORT_PA_SET__dir1__BITNR 9
-#define R_PORT_PA_SET__dir1__WIDTH 1
-#define R_PORT_PA_SET__dir1__input 0
-#define R_PORT_PA_SET__dir1__output 1
-#define R_PORT_PA_SET__dir0__BITNR 8
-#define R_PORT_PA_SET__dir0__WIDTH 1
-#define R_PORT_PA_SET__dir0__input 0
-#define R_PORT_PA_SET__dir0__output 1
-#define R_PORT_PA_SET__data_out__BITNR 0
-#define R_PORT_PA_SET__data_out__WIDTH 8
-
-#define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030)
-#define R_PORT_PA_DATA__data_out__BITNR 0
-#define R_PORT_PA_DATA__data_out__WIDTH 8
-
-#define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031)
-#define R_PORT_PA_DIR__dir7__BITNR 7
-#define R_PORT_PA_DIR__dir7__WIDTH 1
-#define R_PORT_PA_DIR__dir7__input 0
-#define R_PORT_PA_DIR__dir7__output 1
-#define R_PORT_PA_DIR__dir6__BITNR 6
-#define R_PORT_PA_DIR__dir6__WIDTH 1
-#define R_PORT_PA_DIR__dir6__input 0
-#define R_PORT_PA_DIR__dir6__output 1
-#define R_PORT_PA_DIR__dir5__BITNR 5
-#define R_PORT_PA_DIR__dir5__WIDTH 1
-#define R_PORT_PA_DIR__dir5__input 0
-#define R_PORT_PA_DIR__dir5__output 1
-#define R_PORT_PA_DIR__dir4__BITNR 4
-#define R_PORT_PA_DIR__dir4__WIDTH 1
-#define R_PORT_PA_DIR__dir4__input 0
-#define R_PORT_PA_DIR__dir4__output 1
-#define R_PORT_PA_DIR__dir3__BITNR 3
-#define R_PORT_PA_DIR__dir3__WIDTH 1
-#define R_PORT_PA_DIR__dir3__input 0
-#define R_PORT_PA_DIR__dir3__output 1
-#define R_PORT_PA_DIR__dir2__BITNR 2
-#define R_PORT_PA_DIR__dir2__WIDTH 1
-#define R_PORT_PA_DIR__dir2__input 0
-#define R_PORT_PA_DIR__dir2__output 1
-#define R_PORT_PA_DIR__dir1__BITNR 1
-#define R_PORT_PA_DIR__dir1__WIDTH 1
-#define R_PORT_PA_DIR__dir1__input 0
-#define R_PORT_PA_DIR__dir1__output 1
-#define R_PORT_PA_DIR__dir0__BITNR 0
-#define R_PORT_PA_DIR__dir0__WIDTH 1
-#define R_PORT_PA_DIR__dir0__input 0
-#define R_PORT_PA_DIR__dir0__output 1
-
-#define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030)
-#define R_PORT_PA_READ__data_in__BITNR 0
-#define R_PORT_PA_READ__data_in__WIDTH 8
-
-#define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038)
-#define R_PORT_PB_SET__syncser3__BITNR 29
-#define R_PORT_PB_SET__syncser3__WIDTH 1
-#define R_PORT_PB_SET__syncser3__port_cs 0
-#define R_PORT_PB_SET__syncser3__ss3extra 1
-#define R_PORT_PB_SET__syncser1__BITNR 28
-#define R_PORT_PB_SET__syncser1__WIDTH 1
-#define R_PORT_PB_SET__syncser1__port_cs 0
-#define R_PORT_PB_SET__syncser1__ss1extra 1
-#define R_PORT_PB_SET__i2c_en__BITNR 27
-#define R_PORT_PB_SET__i2c_en__WIDTH 1
-#define R_PORT_PB_SET__i2c_en__off 0
-#define R_PORT_PB_SET__i2c_en__on 1
-#define R_PORT_PB_SET__i2c_d__BITNR 26
-#define R_PORT_PB_SET__i2c_d__WIDTH 1
-#define R_PORT_PB_SET__i2c_clk__BITNR 25
-#define R_PORT_PB_SET__i2c_clk__WIDTH 1
-#define R_PORT_PB_SET__i2c_oe___BITNR 24
-#define R_PORT_PB_SET__i2c_oe___WIDTH 1
-#define R_PORT_PB_SET__i2c_oe___enable 0
-#define R_PORT_PB_SET__i2c_oe___disable 1
-#define R_PORT_PB_SET__cs7__BITNR 23
-#define R_PORT_PB_SET__cs7__WIDTH 1
-#define R_PORT_PB_SET__cs7__port 0
-#define R_PORT_PB_SET__cs7__cs 1
-#define R_PORT_PB_SET__cs6__BITNR 22
-#define R_PORT_PB_SET__cs6__WIDTH 1
-#define R_PORT_PB_SET__cs6__port 0
-#define R_PORT_PB_SET__cs6__cs 1
-#define R_PORT_PB_SET__cs5__BITNR 21
-#define R_PORT_PB_SET__cs5__WIDTH 1
-#define R_PORT_PB_SET__cs5__port 0
-#define R_PORT_PB_SET__cs5__cs 1
-#define R_PORT_PB_SET__cs4__BITNR 20
-#define R_PORT_PB_SET__cs4__WIDTH 1
-#define R_PORT_PB_SET__cs4__port 0
-#define R_PORT_PB_SET__cs4__cs 1
-#define R_PORT_PB_SET__cs3__BITNR 19
-#define R_PORT_PB_SET__cs3__WIDTH 1
-#define R_PORT_PB_SET__cs3__port 0
-#define R_PORT_PB_SET__cs3__cs 1
-#define R_PORT_PB_SET__cs2__BITNR 18
-#define R_PORT_PB_SET__cs2__WIDTH 1
-#define R_PORT_PB_SET__cs2__port 0
-#define R_PORT_PB_SET__cs2__cs 1
-#define R_PORT_PB_SET__scsi1__BITNR 17
-#define R_PORT_PB_SET__scsi1__WIDTH 1
-#define R_PORT_PB_SET__scsi1__port_cs 0
-#define R_PORT_PB_SET__scsi1__enph 1
-#define R_PORT_PB_SET__scsi0__BITNR 16
-#define R_PORT_PB_SET__scsi0__WIDTH 1
-#define R_PORT_PB_SET__scsi0__port_cs 0
-#define R_PORT_PB_SET__scsi0__enph 1
-#define R_PORT_PB_SET__dir7__BITNR 15
-#define R_PORT_PB_SET__dir7__WIDTH 1
-#define R_PORT_PB_SET__dir7__input 0
-#define R_PORT_PB_SET__dir7__output 1
-#define R_PORT_PB_SET__dir6__BITNR 14
-#define R_PORT_PB_SET__dir6__WIDTH 1
-#define R_PORT_PB_SET__dir6__input 0
-#define R_PORT_PB_SET__dir6__output 1
-#define R_PORT_PB_SET__dir5__BITNR 13
-#define R_PORT_PB_SET__dir5__WIDTH 1
-#define R_PORT_PB_SET__dir5__input 0
-#define R_PORT_PB_SET__dir5__output 1
-#define R_PORT_PB_SET__dir4__BITNR 12
-#define R_PORT_PB_SET__dir4__WIDTH 1
-#define R_PORT_PB_SET__dir4__input 0
-#define R_PORT_PB_SET__dir4__output 1
-#define R_PORT_PB_SET__dir3__BITNR 11
-#define R_PORT_PB_SET__dir3__WIDTH 1
-#define R_PORT_PB_SET__dir3__input 0
-#define R_PORT_PB_SET__dir3__output 1
-#define R_PORT_PB_SET__dir2__BITNR 10
-#define R_PORT_PB_SET__dir2__WIDTH 1
-#define R_PORT_PB_SET__dir2__input 0
-#define R_PORT_PB_SET__dir2__output 1
-#define R_PORT_PB_SET__dir1__BITNR 9
-#define R_PORT_PB_SET__dir1__WIDTH 1
-#define R_PORT_PB_SET__dir1__input 0
-#define R_PORT_PB_SET__dir1__output 1
-#define R_PORT_PB_SET__dir0__BITNR 8
-#define R_PORT_PB_SET__dir0__WIDTH 1
-#define R_PORT_PB_SET__dir0__input 0
-#define R_PORT_PB_SET__dir0__output 1
-#define R_PORT_PB_SET__data_out__BITNR 0
-#define R_PORT_PB_SET__data_out__WIDTH 8
-
-#define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038)
-#define R_PORT_PB_DATA__data_out__BITNR 0
-#define R_PORT_PB_DATA__data_out__WIDTH 8
-
-#define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039)
-#define R_PORT_PB_DIR__dir7__BITNR 7
-#define R_PORT_PB_DIR__dir7__WIDTH 1
-#define R_PORT_PB_DIR__dir7__input 0
-#define R_PORT_PB_DIR__dir7__output 1
-#define R_PORT_PB_DIR__dir6__BITNR 6
-#define R_PORT_PB_DIR__dir6__WIDTH 1
-#define R_PORT_PB_DIR__dir6__input 0
-#define R_PORT_PB_DIR__dir6__output 1
-#define R_PORT_PB_DIR__dir5__BITNR 5
-#define R_PORT_PB_DIR__dir5__WIDTH 1
-#define R_PORT_PB_DIR__dir5__input 0
-#define R_PORT_PB_DIR__dir5__output 1
-#define R_PORT_PB_DIR__dir4__BITNR 4
-#define R_PORT_PB_DIR__dir4__WIDTH 1
-#define R_PORT_PB_DIR__dir4__input 0
-#define R_PORT_PB_DIR__dir4__output 1
-#define R_PORT_PB_DIR__dir3__BITNR 3
-#define R_PORT_PB_DIR__dir3__WIDTH 1
-#define R_PORT_PB_DIR__dir3__input 0
-#define R_PORT_PB_DIR__dir3__output 1
-#define R_PORT_PB_DIR__dir2__BITNR 2
-#define R_PORT_PB_DIR__dir2__WIDTH 1
-#define R_PORT_PB_DIR__dir2__input 0
-#define R_PORT_PB_DIR__dir2__output 1
-#define R_PORT_PB_DIR__dir1__BITNR 1
-#define R_PORT_PB_DIR__dir1__WIDTH 1
-#define R_PORT_PB_DIR__dir1__input 0
-#define R_PORT_PB_DIR__dir1__output 1
-#define R_PORT_PB_DIR__dir0__BITNR 0
-#define R_PORT_PB_DIR__dir0__WIDTH 1
-#define R_PORT_PB_DIR__dir0__input 0
-#define R_PORT_PB_DIR__dir0__output 1
-
-#define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a)
-#define R_PORT_PB_CONFIG__cs7__BITNR 7
-#define R_PORT_PB_CONFIG__cs7__WIDTH 1
-#define R_PORT_PB_CONFIG__cs7__port 0
-#define R_PORT_PB_CONFIG__cs7__cs 1
-#define R_PORT_PB_CONFIG__cs6__BITNR 6
-#define R_PORT_PB_CONFIG__cs6__WIDTH 1
-#define R_PORT_PB_CONFIG__cs6__port 0
-#define R_PORT_PB_CONFIG__cs6__cs 1
-#define R_PORT_PB_CONFIG__cs5__BITNR 5
-#define R_PORT_PB_CONFIG__cs5__WIDTH 1
-#define R_PORT_PB_CONFIG__cs5__port 0
-#define R_PORT_PB_CONFIG__cs5__cs 1
-#define R_PORT_PB_CONFIG__cs4__BITNR 4
-#define R_PORT_PB_CONFIG__cs4__WIDTH 1
-#define R_PORT_PB_CONFIG__cs4__port 0
-#define R_PORT_PB_CONFIG__cs4__cs 1
-#define R_PORT_PB_CONFIG__cs3__BITNR 3
-#define R_PORT_PB_CONFIG__cs3__WIDTH 1
-#define R_PORT_PB_CONFIG__cs3__port 0
-#define R_PORT_PB_CONFIG__cs3__cs 1
-#define R_PORT_PB_CONFIG__cs2__BITNR 2
-#define R_PORT_PB_CONFIG__cs2__WIDTH 1
-#define R_PORT_PB_CONFIG__cs2__port 0
-#define R_PORT_PB_CONFIG__cs2__cs 1
-#define R_PORT_PB_CONFIG__scsi1__BITNR 1
-#define R_PORT_PB_CONFIG__scsi1__WIDTH 1
-#define R_PORT_PB_CONFIG__scsi1__port_cs 0
-#define R_PORT_PB_CONFIG__scsi1__enph 1
-#define R_PORT_PB_CONFIG__scsi0__BITNR 0
-#define R_PORT_PB_CONFIG__scsi0__WIDTH 1
-#define R_PORT_PB_CONFIG__scsi0__port_cs 0
-#define R_PORT_PB_CONFIG__scsi0__enph 1
-
-#define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b)
-#define R_PORT_PB_I2C__syncser3__BITNR 5
-#define R_PORT_PB_I2C__syncser3__WIDTH 1
-#define R_PORT_PB_I2C__syncser3__port_cs 0
-#define R_PORT_PB_I2C__syncser3__ss3extra 1
-#define R_PORT_PB_I2C__syncser1__BITNR 4
-#define R_PORT_PB_I2C__syncser1__WIDTH 1
-#define R_PORT_PB_I2C__syncser1__port_cs 0
-#define R_PORT_PB_I2C__syncser1__ss1extra 1
-#define R_PORT_PB_I2C__i2c_en__BITNR 3
-#define R_PORT_PB_I2C__i2c_en__WIDTH 1
-#define R_PORT_PB_I2C__i2c_en__off 0
-#define R_PORT_PB_I2C__i2c_en__on 1
-#define R_PORT_PB_I2C__i2c_d__BITNR 2
-#define R_PORT_PB_I2C__i2c_d__WIDTH 1
-#define R_PORT_PB_I2C__i2c_clk__BITNR 1
-#define R_PORT_PB_I2C__i2c_clk__WIDTH 1
-#define R_PORT_PB_I2C__i2c_oe___BITNR 0
-#define R_PORT_PB_I2C__i2c_oe___WIDTH 1
-#define R_PORT_PB_I2C__i2c_oe___enable 0
-#define R_PORT_PB_I2C__i2c_oe___disable 1
-
-#define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038)
-#define R_PORT_PB_READ__data_in__BITNR 0
-#define R_PORT_PB_READ__data_in__WIDTH 8
-
-/*
-!* Serial port registers
-!*/
-
-#define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060)
-#define R_SERIAL0_CTRL__tr_baud__BITNR 28
-#define R_SERIAL0_CTRL__tr_baud__WIDTH 4
-#define R_SERIAL0_CTRL__tr_baud__c300Hz 0
-#define R_SERIAL0_CTRL__tr_baud__c600Hz 1
-#define R_SERIAL0_CTRL__tr_baud__c1200Hz 2
-#define R_SERIAL0_CTRL__tr_baud__c2400Hz 3
-#define R_SERIAL0_CTRL__tr_baud__c4800Hz 4
-#define R_SERIAL0_CTRL__tr_baud__c9600Hz 5
-#define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6
-#define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7
-#define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8
-#define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9
-#define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10
-#define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11
-#define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12
-#define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13
-#define R_SERIAL0_CTRL__tr_baud__c6250kHz 14
-#define R_SERIAL0_CTRL__tr_baud__reserved 15
-#define R_SERIAL0_CTRL__rec_baud__BITNR 24
-#define R_SERIAL0_CTRL__rec_baud__WIDTH 4
-#define R_SERIAL0_CTRL__rec_baud__c300Hz 0
-#define R_SERIAL0_CTRL__rec_baud__c600Hz 1
-#define R_SERIAL0_CTRL__rec_baud__c1200Hz 2
-#define R_SERIAL0_CTRL__rec_baud__c2400Hz 3
-#define R_SERIAL0_CTRL__rec_baud__c4800Hz 4
-#define R_SERIAL0_CTRL__rec_baud__c9600Hz 5
-#define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6
-#define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7
-#define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8
-#define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9
-#define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10
-#define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11
-#define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12
-#define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13
-#define R_SERIAL0_CTRL__rec_baud__c6250kHz 14
-#define R_SERIAL0_CTRL__rec_baud__reserved 15
-#define R_SERIAL0_CTRL__dma_err__BITNR 23
-#define R_SERIAL0_CTRL__dma_err__WIDTH 1
-#define R_SERIAL0_CTRL__dma_err__stop 0
-#define R_SERIAL0_CTRL__dma_err__ignore 1
-#define R_SERIAL0_CTRL__rec_enable__BITNR 22
-#define R_SERIAL0_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL0_CTRL__rec_enable__disable 0
-#define R_SERIAL0_CTRL__rec_enable__enable 1
-#define R_SERIAL0_CTRL__rts___BITNR 21
-#define R_SERIAL0_CTRL__rts___WIDTH 1
-#define R_SERIAL0_CTRL__rts___active 0
-#define R_SERIAL0_CTRL__rts___inactive 1
-#define R_SERIAL0_CTRL__sampling__BITNR 20
-#define R_SERIAL0_CTRL__sampling__WIDTH 1
-#define R_SERIAL0_CTRL__sampling__middle 0
-#define R_SERIAL0_CTRL__sampling__majority 1
-#define R_SERIAL0_CTRL__rec_stick_par__BITNR 19
-#define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL0_CTRL__rec_stick_par__normal 0
-#define R_SERIAL0_CTRL__rec_stick_par__stick 1
-#define R_SERIAL0_CTRL__rec_par__BITNR 18
-#define R_SERIAL0_CTRL__rec_par__WIDTH 1
-#define R_SERIAL0_CTRL__rec_par__even 0
-#define R_SERIAL0_CTRL__rec_par__odd 1
-#define R_SERIAL0_CTRL__rec_par_en__BITNR 17
-#define R_SERIAL0_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL0_CTRL__rec_par_en__disable 0
-#define R_SERIAL0_CTRL__rec_par_en__enable 1
-#define R_SERIAL0_CTRL__rec_bitnr__BITNR 16
-#define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1
-#define R_SERIAL0_CTRL__txd__BITNR 15
-#define R_SERIAL0_CTRL__txd__WIDTH 1
-#define R_SERIAL0_CTRL__tr_enable__BITNR 14
-#define R_SERIAL0_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL0_CTRL__tr_enable__disable 0
-#define R_SERIAL0_CTRL__tr_enable__enable 1
-#define R_SERIAL0_CTRL__auto_cts__BITNR 13
-#define R_SERIAL0_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL0_CTRL__auto_cts__disabled 0
-#define R_SERIAL0_CTRL__auto_cts__active 1
-#define R_SERIAL0_CTRL__stop_bits__BITNR 12
-#define R_SERIAL0_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL0_CTRL__stop_bits__one_bit 0
-#define R_SERIAL0_CTRL__stop_bits__two_bits 1
-#define R_SERIAL0_CTRL__tr_stick_par__BITNR 11
-#define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL0_CTRL__tr_stick_par__normal 0
-#define R_SERIAL0_CTRL__tr_stick_par__stick 1
-#define R_SERIAL0_CTRL__tr_par__BITNR 10
-#define R_SERIAL0_CTRL__tr_par__WIDTH 1
-#define R_SERIAL0_CTRL__tr_par__even 0
-#define R_SERIAL0_CTRL__tr_par__odd 1
-#define R_SERIAL0_CTRL__tr_par_en__BITNR 9
-#define R_SERIAL0_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL0_CTRL__tr_par_en__disable 0
-#define R_SERIAL0_CTRL__tr_par_en__enable 1
-#define R_SERIAL0_CTRL__tr_bitnr__BITNR 8
-#define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1
-#define R_SERIAL0_CTRL__data_out__BITNR 0
-#define R_SERIAL0_CTRL__data_out__WIDTH 8
-
-#define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063)
-#define R_SERIAL0_BAUD__tr_baud__BITNR 4
-#define R_SERIAL0_BAUD__tr_baud__WIDTH 4
-#define R_SERIAL0_BAUD__tr_baud__c300Hz 0
-#define R_SERIAL0_BAUD__tr_baud__c600Hz 1
-#define R_SERIAL0_BAUD__tr_baud__c1200Hz 2
-#define R_SERIAL0_BAUD__tr_baud__c2400Hz 3
-#define R_SERIAL0_BAUD__tr_baud__c4800Hz 4
-#define R_SERIAL0_BAUD__tr_baud__c9600Hz 5
-#define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6
-#define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7
-#define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8
-#define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9
-#define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10
-#define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11
-#define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12
-#define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13
-#define R_SERIAL0_BAUD__tr_baud__c6250kHz 14
-#define R_SERIAL0_BAUD__tr_baud__reserved 15
-#define R_SERIAL0_BAUD__rec_baud__BITNR 0
-#define R_SERIAL0_BAUD__rec_baud__WIDTH 4
-#define R_SERIAL0_BAUD__rec_baud__c300Hz 0
-#define R_SERIAL0_BAUD__rec_baud__c600Hz 1
-#define R_SERIAL0_BAUD__rec_baud__c1200Hz 2
-#define R_SERIAL0_BAUD__rec_baud__c2400Hz 3
-#define R_SERIAL0_BAUD__rec_baud__c4800Hz 4
-#define R_SERIAL0_BAUD__rec_baud__c9600Hz 5
-#define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6
-#define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7
-#define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8
-#define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9
-#define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10
-#define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11
-#define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12
-#define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13
-#define R_SERIAL0_BAUD__rec_baud__c6250kHz 14
-#define R_SERIAL0_BAUD__rec_baud__reserved 15
-
-#define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062)
-#define R_SERIAL0_REC_CTRL__dma_err__BITNR 7
-#define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1
-#define R_SERIAL0_REC_CTRL__dma_err__stop 0
-#define R_SERIAL0_REC_CTRL__dma_err__ignore 1
-#define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6
-#define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL0_REC_CTRL__rec_enable__disable 0
-#define R_SERIAL0_REC_CTRL__rec_enable__enable 1
-#define R_SERIAL0_REC_CTRL__rts___BITNR 5
-#define R_SERIAL0_REC_CTRL__rts___WIDTH 1
-#define R_SERIAL0_REC_CTRL__rts___active 0
-#define R_SERIAL0_REC_CTRL__rts___inactive 1
-#define R_SERIAL0_REC_CTRL__sampling__BITNR 4
-#define R_SERIAL0_REC_CTRL__sampling__WIDTH 1
-#define R_SERIAL0_REC_CTRL__sampling__middle 0
-#define R_SERIAL0_REC_CTRL__sampling__majority 1
-#define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3
-#define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0
-#define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1
-#define R_SERIAL0_REC_CTRL__rec_par__BITNR 2
-#define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1
-#define R_SERIAL0_REC_CTRL__rec_par__even 0
-#define R_SERIAL0_REC_CTRL__rec_par__odd 1
-#define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1
-#define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL0_REC_CTRL__rec_par_en__disable 0
-#define R_SERIAL0_REC_CTRL__rec_par_en__enable 1
-#define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0
-#define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1
-
-#define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061)
-#define R_SERIAL0_TR_CTRL__txd__BITNR 7
-#define R_SERIAL0_TR_CTRL__txd__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6
-#define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_enable__disable 0
-#define R_SERIAL0_TR_CTRL__tr_enable__enable 1
-#define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5
-#define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL0_TR_CTRL__auto_cts__disabled 0
-#define R_SERIAL0_TR_CTRL__auto_cts__active 1
-#define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4
-#define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0
-#define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1
-#define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3
-#define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0
-#define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1
-#define R_SERIAL0_TR_CTRL__tr_par__BITNR 2
-#define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_par__even 0
-#define R_SERIAL0_TR_CTRL__tr_par__odd 1
-#define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1
-#define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_par_en__disable 0
-#define R_SERIAL0_TR_CTRL__tr_par_en__enable 1
-#define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0
-#define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1
-
-#define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060)
-#define R_SERIAL0_TR_DATA__data_out__BITNR 0
-#define R_SERIAL0_TR_DATA__data_out__WIDTH 8
-
-#define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060)
-#define R_SERIAL0_READ__xoff_detect__BITNR 15
-#define R_SERIAL0_READ__xoff_detect__WIDTH 1
-#define R_SERIAL0_READ__xoff_detect__no_xoff 0
-#define R_SERIAL0_READ__xoff_detect__xoff 1
-#define R_SERIAL0_READ__cts___BITNR 14
-#define R_SERIAL0_READ__cts___WIDTH 1
-#define R_SERIAL0_READ__cts___active 0
-#define R_SERIAL0_READ__cts___inactive 1
-#define R_SERIAL0_READ__tr_ready__BITNR 13
-#define R_SERIAL0_READ__tr_ready__WIDTH 1
-#define R_SERIAL0_READ__tr_ready__full 0
-#define R_SERIAL0_READ__tr_ready__ready 1
-#define R_SERIAL0_READ__rxd__BITNR 12
-#define R_SERIAL0_READ__rxd__WIDTH 1
-#define R_SERIAL0_READ__overrun__BITNR 11
-#define R_SERIAL0_READ__overrun__WIDTH 1
-#define R_SERIAL0_READ__overrun__no 0
-#define R_SERIAL0_READ__overrun__yes 1
-#define R_SERIAL0_READ__par_err__BITNR 10
-#define R_SERIAL0_READ__par_err__WIDTH 1
-#define R_SERIAL0_READ__par_err__no 0
-#define R_SERIAL0_READ__par_err__yes 1
-#define R_SERIAL0_READ__framing_err__BITNR 9
-#define R_SERIAL0_READ__framing_err__WIDTH 1
-#define R_SERIAL0_READ__framing_err__no 0
-#define R_SERIAL0_READ__framing_err__yes 1
-#define R_SERIAL0_READ__data_avail__BITNR 8
-#define R_SERIAL0_READ__data_avail__WIDTH 1
-#define R_SERIAL0_READ__data_avail__no 0
-#define R_SERIAL0_READ__data_avail__yes 1
-#define R_SERIAL0_READ__data_in__BITNR 0
-#define R_SERIAL0_READ__data_in__WIDTH 8
-
-#define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061)
-#define R_SERIAL0_STATUS__xoff_detect__BITNR 7
-#define R_SERIAL0_STATUS__xoff_detect__WIDTH 1
-#define R_SERIAL0_STATUS__xoff_detect__no_xoff 0
-#define R_SERIAL0_STATUS__xoff_detect__xoff 1
-#define R_SERIAL0_STATUS__cts___BITNR 6
-#define R_SERIAL0_STATUS__cts___WIDTH 1
-#define R_SERIAL0_STATUS__cts___active 0
-#define R_SERIAL0_STATUS__cts___inactive 1
-#define R_SERIAL0_STATUS__tr_ready__BITNR 5
-#define R_SERIAL0_STATUS__tr_ready__WIDTH 1
-#define R_SERIAL0_STATUS__tr_ready__full 0
-#define R_SERIAL0_STATUS__tr_ready__ready 1
-#define R_SERIAL0_STATUS__rxd__BITNR 4
-#define R_SERIAL0_STATUS__rxd__WIDTH 1
-#define R_SERIAL0_STATUS__overrun__BITNR 3
-#define R_SERIAL0_STATUS__overrun__WIDTH 1
-#define R_SERIAL0_STATUS__overrun__no 0
-#define R_SERIAL0_STATUS__overrun__yes 1
-#define R_SERIAL0_STATUS__par_err__BITNR 2
-#define R_SERIAL0_STATUS__par_err__WIDTH 1
-#define R_SERIAL0_STATUS__par_err__no 0
-#define R_SERIAL0_STATUS__par_err__yes 1
-#define R_SERIAL0_STATUS__framing_err__BITNR 1
-#define R_SERIAL0_STATUS__framing_err__WIDTH 1
-#define R_SERIAL0_STATUS__framing_err__no 0
-#define R_SERIAL0_STATUS__framing_err__yes 1
-#define R_SERIAL0_STATUS__data_avail__BITNR 0
-#define R_SERIAL0_STATUS__data_avail__WIDTH 1
-#define R_SERIAL0_STATUS__data_avail__no 0
-#define R_SERIAL0_STATUS__data_avail__yes 1
-
-#define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060)
-#define R_SERIAL0_REC_DATA__data_in__BITNR 0
-#define R_SERIAL0_REC_DATA__data_in__WIDTH 8
-
-#define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064)
-#define R_SERIAL0_XOFF__tx_stop__BITNR 9
-#define R_SERIAL0_XOFF__tx_stop__WIDTH 1
-#define R_SERIAL0_XOFF__tx_stop__enable 0
-#define R_SERIAL0_XOFF__tx_stop__stop 1
-#define R_SERIAL0_XOFF__auto_xoff__BITNR 8
-#define R_SERIAL0_XOFF__auto_xoff__WIDTH 1
-#define R_SERIAL0_XOFF__auto_xoff__disable 0
-#define R_SERIAL0_XOFF__auto_xoff__enable 1
-#define R_SERIAL0_XOFF__xoff_char__BITNR 0
-#define R_SERIAL0_XOFF__xoff_char__WIDTH 8
-
-#define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068)
-#define R_SERIAL1_CTRL__tr_baud__BITNR 28
-#define R_SERIAL1_CTRL__tr_baud__WIDTH 4
-#define R_SERIAL1_CTRL__tr_baud__c300Hz 0
-#define R_SERIAL1_CTRL__tr_baud__c600Hz 1
-#define R_SERIAL1_CTRL__tr_baud__c1200Hz 2
-#define R_SERIAL1_CTRL__tr_baud__c2400Hz 3
-#define R_SERIAL1_CTRL__tr_baud__c4800Hz 4
-#define R_SERIAL1_CTRL__tr_baud__c9600Hz 5
-#define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6
-#define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7
-#define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8
-#define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9
-#define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10
-#define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11
-#define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12
-#define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13
-#define R_SERIAL1_CTRL__tr_baud__c6250kHz 14
-#define R_SERIAL1_CTRL__tr_baud__reserved 15
-#define R_SERIAL1_CTRL__rec_baud__BITNR 24
-#define R_SERIAL1_CTRL__rec_baud__WIDTH 4
-#define R_SERIAL1_CTRL__rec_baud__c300Hz 0
-#define R_SERIAL1_CTRL__rec_baud__c600Hz 1
-#define R_SERIAL1_CTRL__rec_baud__c1200Hz 2
-#define R_SERIAL1_CTRL__rec_baud__c2400Hz 3
-#define R_SERIAL1_CTRL__rec_baud__c4800Hz 4
-#define R_SERIAL1_CTRL__rec_baud__c9600Hz 5
-#define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6
-#define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7
-#define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8
-#define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9
-#define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10
-#define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11
-#define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12
-#define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13
-#define R_SERIAL1_CTRL__rec_baud__c6250kHz 14
-#define R_SERIAL1_CTRL__rec_baud__reserved 15
-#define R_SERIAL1_CTRL__dma_err__BITNR 23
-#define R_SERIAL1_CTRL__dma_err__WIDTH 1
-#define R_SERIAL1_CTRL__dma_err__stop 0
-#define R_SERIAL1_CTRL__dma_err__ignore 1
-#define R_SERIAL1_CTRL__rec_enable__BITNR 22
-#define R_SERIAL1_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL1_CTRL__rec_enable__disable 0
-#define R_SERIAL1_CTRL__rec_enable__enable 1
-#define R_SERIAL1_CTRL__rts___BITNR 21
-#define R_SERIAL1_CTRL__rts___WIDTH 1
-#define R_SERIAL1_CTRL__rts___active 0
-#define R_SERIAL1_CTRL__rts___inactive 1
-#define R_SERIAL1_CTRL__sampling__BITNR 20
-#define R_SERIAL1_CTRL__sampling__WIDTH 1
-#define R_SERIAL1_CTRL__sampling__middle 0
-#define R_SERIAL1_CTRL__sampling__majority 1
-#define R_SERIAL1_CTRL__rec_stick_par__BITNR 19
-#define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL1_CTRL__rec_stick_par__normal 0
-#define R_SERIAL1_CTRL__rec_stick_par__stick 1
-#define R_SERIAL1_CTRL__rec_par__BITNR 18
-#define R_SERIAL1_CTRL__rec_par__WIDTH 1
-#define R_SERIAL1_CTRL__rec_par__even 0
-#define R_SERIAL1_CTRL__rec_par__odd 1
-#define R_SERIAL1_CTRL__rec_par_en__BITNR 17
-#define R_SERIAL1_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL1_CTRL__rec_par_en__disable 0
-#define R_SERIAL1_CTRL__rec_par_en__enable 1
-#define R_SERIAL1_CTRL__rec_bitnr__BITNR 16
-#define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1
-#define R_SERIAL1_CTRL__txd__BITNR 15
-#define R_SERIAL1_CTRL__txd__WIDTH 1
-#define R_SERIAL1_CTRL__tr_enable__BITNR 14
-#define R_SERIAL1_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL1_CTRL__tr_enable__disable 0
-#define R_SERIAL1_CTRL__tr_enable__enable 1
-#define R_SERIAL1_CTRL__auto_cts__BITNR 13
-#define R_SERIAL1_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL1_CTRL__auto_cts__disabled 0
-#define R_SERIAL1_CTRL__auto_cts__active 1
-#define R_SERIAL1_CTRL__stop_bits__BITNR 12
-#define R_SERIAL1_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL1_CTRL__stop_bits__one_bit 0
-#define R_SERIAL1_CTRL__stop_bits__two_bits 1
-#define R_SERIAL1_CTRL__tr_stick_par__BITNR 11
-#define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL1_CTRL__tr_stick_par__normal 0
-#define R_SERIAL1_CTRL__tr_stick_par__stick 1
-#define R_SERIAL1_CTRL__tr_par__BITNR 10
-#define R_SERIAL1_CTRL__tr_par__WIDTH 1
-#define R_SERIAL1_CTRL__tr_par__even 0
-#define R_SERIAL1_CTRL__tr_par__odd 1
-#define R_SERIAL1_CTRL__tr_par_en__BITNR 9
-#define R_SERIAL1_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL1_CTRL__tr_par_en__disable 0
-#define R_SERIAL1_CTRL__tr_par_en__enable 1
-#define R_SERIAL1_CTRL__tr_bitnr__BITNR 8
-#define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1
-#define R_SERIAL1_CTRL__data_out__BITNR 0
-#define R_SERIAL1_CTRL__data_out__WIDTH 8
-
-#define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b)
-#define R_SERIAL1_BAUD__tr_baud__BITNR 4
-#define R_SERIAL1_BAUD__tr_baud__WIDTH 4
-#define R_SERIAL1_BAUD__tr_baud__c300Hz 0
-#define R_SERIAL1_BAUD__tr_baud__c600Hz 1
-#define R_SERIAL1_BAUD__tr_baud__c1200Hz 2
-#define R_SERIAL1_BAUD__tr_baud__c2400Hz 3
-#define R_SERIAL1_BAUD__tr_baud__c4800Hz 4
-#define R_SERIAL1_BAUD__tr_baud__c9600Hz 5
-#define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6
-#define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7
-#define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8
-#define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9
-#define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10
-#define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11
-#define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12
-#define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13
-#define R_SERIAL1_BAUD__tr_baud__c6250kHz 14
-#define R_SERIAL1_BAUD__tr_baud__reserved 15
-#define R_SERIAL1_BAUD__rec_baud__BITNR 0
-#define R_SERIAL1_BAUD__rec_baud__WIDTH 4
-#define R_SERIAL1_BAUD__rec_baud__c300Hz 0
-#define R_SERIAL1_BAUD__rec_baud__c600Hz 1
-#define R_SERIAL1_BAUD__rec_baud__c1200Hz 2
-#define R_SERIAL1_BAUD__rec_baud__c2400Hz 3
-#define R_SERIAL1_BAUD__rec_baud__c4800Hz 4
-#define R_SERIAL1_BAUD__rec_baud__c9600Hz 5
-#define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6
-#define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7
-#define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8
-#define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9
-#define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10
-#define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11
-#define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12
-#define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13
-#define R_SERIAL1_BAUD__rec_baud__c6250kHz 14
-#define R_SERIAL1_BAUD__rec_baud__reserved 15
-
-#define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a)
-#define R_SERIAL1_REC_CTRL__dma_err__BITNR 7
-#define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1
-#define R_SERIAL1_REC_CTRL__dma_err__stop 0
-#define R_SERIAL1_REC_CTRL__dma_err__ignore 1
-#define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6
-#define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL1_REC_CTRL__rec_enable__disable 0
-#define R_SERIAL1_REC_CTRL__rec_enable__enable 1
-#define R_SERIAL1_REC_CTRL__rts___BITNR 5
-#define R_SERIAL1_REC_CTRL__rts___WIDTH 1
-#define R_SERIAL1_REC_CTRL__rts___active 0
-#define R_SERIAL1_REC_CTRL__rts___inactive 1
-#define R_SERIAL1_REC_CTRL__sampling__BITNR 4
-#define R_SERIAL1_REC_CTRL__sampling__WIDTH 1
-#define R_SERIAL1_REC_CTRL__sampling__middle 0
-#define R_SERIAL1_REC_CTRL__sampling__majority 1
-#define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3
-#define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0
-#define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1
-#define R_SERIAL1_REC_CTRL__rec_par__BITNR 2
-#define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1
-#define R_SERIAL1_REC_CTRL__rec_par__even 0
-#define R_SERIAL1_REC_CTRL__rec_par__odd 1
-#define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1
-#define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL1_REC_CTRL__rec_par_en__disable 0
-#define R_SERIAL1_REC_CTRL__rec_par_en__enable 1
-#define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0
-#define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1
-
-#define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069)
-#define R_SERIAL1_TR_CTRL__txd__BITNR 7
-#define R_SERIAL1_TR_CTRL__txd__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6
-#define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_enable__disable 0
-#define R_SERIAL1_TR_CTRL__tr_enable__enable 1
-#define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5
-#define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL1_TR_CTRL__auto_cts__disabled 0
-#define R_SERIAL1_TR_CTRL__auto_cts__active 1
-#define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4
-#define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0
-#define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1
-#define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3
-#define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0
-#define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1
-#define R_SERIAL1_TR_CTRL__tr_par__BITNR 2
-#define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_par__even 0
-#define R_SERIAL1_TR_CTRL__tr_par__odd 1
-#define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1
-#define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_par_en__disable 0
-#define R_SERIAL1_TR_CTRL__tr_par_en__enable 1
-#define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0
-#define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1
-
-#define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068)
-#define R_SERIAL1_TR_DATA__data_out__BITNR 0
-#define R_SERIAL1_TR_DATA__data_out__WIDTH 8
-
-#define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068)
-#define R_SERIAL1_READ__xoff_detect__BITNR 15
-#define R_SERIAL1_READ__xoff_detect__WIDTH 1
-#define R_SERIAL1_READ__xoff_detect__no_xoff 0
-#define R_SERIAL1_READ__xoff_detect__xoff 1
-#define R_SERIAL1_READ__cts___BITNR 14
-#define R_SERIAL1_READ__cts___WIDTH 1
-#define R_SERIAL1_READ__cts___active 0
-#define R_SERIAL1_READ__cts___inactive 1
-#define R_SERIAL1_READ__tr_ready__BITNR 13
-#define R_SERIAL1_READ__tr_ready__WIDTH 1
-#define R_SERIAL1_READ__tr_ready__full 0
-#define R_SERIAL1_READ__tr_ready__ready 1
-#define R_SERIAL1_READ__rxd__BITNR 12
-#define R_SERIAL1_READ__rxd__WIDTH 1
-#define R_SERIAL1_READ__overrun__BITNR 11
-#define R_SERIAL1_READ__overrun__WIDTH 1
-#define R_SERIAL1_READ__overrun__no 0
-#define R_SERIAL1_READ__overrun__yes 1
-#define R_SERIAL1_READ__par_err__BITNR 10
-#define R_SERIAL1_READ__par_err__WIDTH 1
-#define R_SERIAL1_READ__par_err__no 0
-#define R_SERIAL1_READ__par_err__yes 1
-#define R_SERIAL1_READ__framing_err__BITNR 9
-#define R_SERIAL1_READ__framing_err__WIDTH 1
-#define R_SERIAL1_READ__framing_err__no 0
-#define R_SERIAL1_READ__framing_err__yes 1
-#define R_SERIAL1_READ__data_avail__BITNR 8
-#define R_SERIAL1_READ__data_avail__WIDTH 1
-#define R_SERIAL1_READ__data_avail__no 0
-#define R_SERIAL1_READ__data_avail__yes 1
-#define R_SERIAL1_READ__data_in__BITNR 0
-#define R_SERIAL1_READ__data_in__WIDTH 8
-
-#define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069)
-#define R_SERIAL1_STATUS__xoff_detect__BITNR 7
-#define R_SERIAL1_STATUS__xoff_detect__WIDTH 1
-#define R_SERIAL1_STATUS__xoff_detect__no_xoff 0
-#define R_SERIAL1_STATUS__xoff_detect__xoff 1
-#define R_SERIAL1_STATUS__cts___BITNR 6
-#define R_SERIAL1_STATUS__cts___WIDTH 1
-#define R_SERIAL1_STATUS__cts___active 0
-#define R_SERIAL1_STATUS__cts___inactive 1
-#define R_SERIAL1_STATUS__tr_ready__BITNR 5
-#define R_SERIAL1_STATUS__tr_ready__WIDTH 1
-#define R_SERIAL1_STATUS__tr_ready__full 0
-#define R_SERIAL1_STATUS__tr_ready__ready 1
-#define R_SERIAL1_STATUS__rxd__BITNR 4
-#define R_SERIAL1_STATUS__rxd__WIDTH 1
-#define R_SERIAL1_STATUS__overrun__BITNR 3
-#define R_SERIAL1_STATUS__overrun__WIDTH 1
-#define R_SERIAL1_STATUS__overrun__no 0
-#define R_SERIAL1_STATUS__overrun__yes 1
-#define R_SERIAL1_STATUS__par_err__BITNR 2
-#define R_SERIAL1_STATUS__par_err__WIDTH 1
-#define R_SERIAL1_STATUS__par_err__no 0
-#define R_SERIAL1_STATUS__par_err__yes 1
-#define R_SERIAL1_STATUS__framing_err__BITNR 1
-#define R_SERIAL1_STATUS__framing_err__WIDTH 1
-#define R_SERIAL1_STATUS__framing_err__no 0
-#define R_SERIAL1_STATUS__framing_err__yes 1
-#define R_SERIAL1_STATUS__data_avail__BITNR 0
-#define R_SERIAL1_STATUS__data_avail__WIDTH 1
-#define R_SERIAL1_STATUS__data_avail__no 0
-#define R_SERIAL1_STATUS__data_avail__yes 1
-
-#define R_SERIAL1_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000068)
-#define R_SERIAL1_REC_DATA__data_in__BITNR 0
-#define R_SERIAL1_REC_DATA__data_in__WIDTH 8
-
-#define R_SERIAL1_XOFF (IO_TYPECAST_UDWORD 0xb000006c)
-#define R_SERIAL1_XOFF__tx_stop__BITNR 9
-#define R_SERIAL1_XOFF__tx_stop__WIDTH 1
-#define R_SERIAL1_XOFF__tx_stop__enable 0
-#define R_SERIAL1_XOFF__tx_stop__stop 1
-#define R_SERIAL1_XOFF__auto_xoff__BITNR 8
-#define R_SERIAL1_XOFF__auto_xoff__WIDTH 1
-#define R_SERIAL1_XOFF__auto_xoff__disable 0
-#define R_SERIAL1_XOFF__auto_xoff__enable 1
-#define R_SERIAL1_XOFF__xoff_char__BITNR 0
-#define R_SERIAL1_XOFF__xoff_char__WIDTH 8
-
-#define R_SERIAL2_CTRL (IO_TYPECAST_UDWORD 0xb0000070)
-#define R_SERIAL2_CTRL__tr_baud__BITNR 28
-#define R_SERIAL2_CTRL__tr_baud__WIDTH 4
-#define R_SERIAL2_CTRL__tr_baud__c300Hz 0
-#define R_SERIAL2_CTRL__tr_baud__c600Hz 1
-#define R_SERIAL2_CTRL__tr_baud__c1200Hz 2
-#define R_SERIAL2_CTRL__tr_baud__c2400Hz 3
-#define R_SERIAL2_CTRL__tr_baud__c4800Hz 4
-#define R_SERIAL2_CTRL__tr_baud__c9600Hz 5
-#define R_SERIAL2_CTRL__tr_baud__c19k2Hz 6
-#define R_SERIAL2_CTRL__tr_baud__c38k4Hz 7
-#define R_SERIAL2_CTRL__tr_baud__c57k6Hz 8
-#define R_SERIAL2_CTRL__tr_baud__c115k2Hz 9
-#define R_SERIAL2_CTRL__tr_baud__c230k4Hz 10
-#define R_SERIAL2_CTRL__tr_baud__c460k8Hz 11
-#define R_SERIAL2_CTRL__tr_baud__c921k6Hz 12
-#define R_SERIAL2_CTRL__tr_baud__c1843k2Hz 13
-#define R_SERIAL2_CTRL__tr_baud__c6250kHz 14
-#define R_SERIAL2_CTRL__tr_baud__reserved 15
-#define R_SERIAL2_CTRL__rec_baud__BITNR 24
-#define R_SERIAL2_CTRL__rec_baud__WIDTH 4
-#define R_SERIAL2_CTRL__rec_baud__c300Hz 0
-#define R_SERIAL2_CTRL__rec_baud__c600Hz 1
-#define R_SERIAL2_CTRL__rec_baud__c1200Hz 2
-#define R_SERIAL2_CTRL__rec_baud__c2400Hz 3
-#define R_SERIAL2_CTRL__rec_baud__c4800Hz 4
-#define R_SERIAL2_CTRL__rec_baud__c9600Hz 5
-#define R_SERIAL2_CTRL__rec_baud__c19k2Hz 6
-#define R_SERIAL2_CTRL__rec_baud__c38k4Hz 7
-#define R_SERIAL2_CTRL__rec_baud__c57k6Hz 8
-#define R_SERIAL2_CTRL__rec_baud__c115k2Hz 9
-#define R_SERIAL2_CTRL__rec_baud__c230k4Hz 10
-#define R_SERIAL2_CTRL__rec_baud__c460k8Hz 11
-#define R_SERIAL2_CTRL__rec_baud__c921k6Hz 12
-#define R_SERIAL2_CTRL__rec_baud__c1843k2Hz 13
-#define R_SERIAL2_CTRL__rec_baud__c6250kHz 14
-#define R_SERIAL2_CTRL__rec_baud__reserved 15
-#define R_SERIAL2_CTRL__dma_err__BITNR 23
-#define R_SERIAL2_CTRL__dma_err__WIDTH 1
-#define R_SERIAL2_CTRL__dma_err__stop 0
-#define R_SERIAL2_CTRL__dma_err__ignore 1
-#define R_SERIAL2_CTRL__rec_enable__BITNR 22
-#define R_SERIAL2_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL2_CTRL__rec_enable__disable 0
-#define R_SERIAL2_CTRL__rec_enable__enable 1
-#define R_SERIAL2_CTRL__rts___BITNR 21
-#define R_SERIAL2_CTRL__rts___WIDTH 1
-#define R_SERIAL2_CTRL__rts___active 0
-#define R_SERIAL2_CTRL__rts___inactive 1
-#define R_SERIAL2_CTRL__sampling__BITNR 20
-#define R_SERIAL2_CTRL__sampling__WIDTH 1
-#define R_SERIAL2_CTRL__sampling__middle 0
-#define R_SERIAL2_CTRL__sampling__majority 1
-#define R_SERIAL2_CTRL__rec_stick_par__BITNR 19
-#define R_SERIAL2_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL2_CTRL__rec_stick_par__normal 0
-#define R_SERIAL2_CTRL__rec_stick_par__stick 1
-#define R_SERIAL2_CTRL__rec_par__BITNR 18
-#define R_SERIAL2_CTRL__rec_par__WIDTH 1
-#define R_SERIAL2_CTRL__rec_par__even 0
-#define R_SERIAL2_CTRL__rec_par__odd 1
-#define R_SERIAL2_CTRL__rec_par_en__BITNR 17
-#define R_SERIAL2_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL2_CTRL__rec_par_en__disable 0
-#define R_SERIAL2_CTRL__rec_par_en__enable 1
-#define R_SERIAL2_CTRL__rec_bitnr__BITNR 16
-#define R_SERIAL2_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL2_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL2_CTRL__rec_bitnr__rec_7bit 1
-#define R_SERIAL2_CTRL__txd__BITNR 15
-#define R_SERIAL2_CTRL__txd__WIDTH 1
-#define R_SERIAL2_CTRL__tr_enable__BITNR 14
-#define R_SERIAL2_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL2_CTRL__tr_enable__disable 0
-#define R_SERIAL2_CTRL__tr_enable__enable 1
-#define R_SERIAL2_CTRL__auto_cts__BITNR 13
-#define R_SERIAL2_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL2_CTRL__auto_cts__disabled 0
-#define R_SERIAL2_CTRL__auto_cts__active 1
-#define R_SERIAL2_CTRL__stop_bits__BITNR 12
-#define R_SERIAL2_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL2_CTRL__stop_bits__one_bit 0
-#define R_SERIAL2_CTRL__stop_bits__two_bits 1
-#define R_SERIAL2_CTRL__tr_stick_par__BITNR 11
-#define R_SERIAL2_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL2_CTRL__tr_stick_par__normal 0
-#define R_SERIAL2_CTRL__tr_stick_par__stick 1
-#define R_SERIAL2_CTRL__tr_par__BITNR 10
-#define R_SERIAL2_CTRL__tr_par__WIDTH 1
-#define R_SERIAL2_CTRL__tr_par__even 0
-#define R_SERIAL2_CTRL__tr_par__odd 1
-#define R_SERIAL2_CTRL__tr_par_en__BITNR 9
-#define R_SERIAL2_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL2_CTRL__tr_par_en__disable 0
-#define R_SERIAL2_CTRL__tr_par_en__enable 1
-#define R_SERIAL2_CTRL__tr_bitnr__BITNR 8
-#define R_SERIAL2_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL2_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL2_CTRL__tr_bitnr__tr_7bit 1
-#define R_SERIAL2_CTRL__data_out__BITNR 0
-#define R_SERIAL2_CTRL__data_out__WIDTH 8
-
-#define R_SERIAL2_BAUD (IO_TYPECAST_BYTE 0xb0000073)
-#define R_SERIAL2_BAUD__tr_baud__BITNR 4
-#define R_SERIAL2_BAUD__tr_baud__WIDTH 4
-#define R_SERIAL2_BAUD__tr_baud__c300Hz 0
-#define R_SERIAL2_BAUD__tr_baud__c600Hz 1
-#define R_SERIAL2_BAUD__tr_baud__c1200Hz 2
-#define R_SERIAL2_BAUD__tr_baud__c2400Hz 3
-#define R_SERIAL2_BAUD__tr_baud__c4800Hz 4
-#define R_SERIAL2_BAUD__tr_baud__c9600Hz 5
-#define R_SERIAL2_BAUD__tr_baud__c19k2Hz 6
-#define R_SERIAL2_BAUD__tr_baud__c38k4Hz 7
-#define R_SERIAL2_BAUD__tr_baud__c57k6Hz 8
-#define R_SERIAL2_BAUD__tr_baud__c115k2Hz 9
-#define R_SERIAL2_BAUD__tr_baud__c230k4Hz 10
-#define R_SERIAL2_BAUD__tr_baud__c460k8Hz 11
-#define R_SERIAL2_BAUD__tr_baud__c921k6Hz 12
-#define R_SERIAL2_BAUD__tr_baud__c1843k2Hz 13
-#define R_SERIAL2_BAUD__tr_baud__c6250kHz 14
-#define R_SERIAL2_BAUD__tr_baud__reserved 15
-#define R_SERIAL2_BAUD__rec_baud__BITNR 0
-#define R_SERIAL2_BAUD__rec_baud__WIDTH 4
-#define R_SERIAL2_BAUD__rec_baud__c300Hz 0
-#define R_SERIAL2_BAUD__rec_baud__c600Hz 1
-#define R_SERIAL2_BAUD__rec_baud__c1200Hz 2
-#define R_SERIAL2_BAUD__rec_baud__c2400Hz 3
-#define R_SERIAL2_BAUD__rec_baud__c4800Hz 4
-#define R_SERIAL2_BAUD__rec_baud__c9600Hz 5
-#define R_SERIAL2_BAUD__rec_baud__c19k2Hz 6
-#define R_SERIAL2_BAUD__rec_baud__c38k4Hz 7
-#define R_SERIAL2_BAUD__rec_baud__c57k6Hz 8
-#define R_SERIAL2_BAUD__rec_baud__c115k2Hz 9
-#define R_SERIAL2_BAUD__rec_baud__c230k4Hz 10
-#define R_SERIAL2_BAUD__rec_baud__c460k8Hz 11
-#define R_SERIAL2_BAUD__rec_baud__c921k6Hz 12
-#define R_SERIAL2_BAUD__rec_baud__c1843k2Hz 13
-#define R_SERIAL2_BAUD__rec_baud__c6250kHz 14
-#define R_SERIAL2_BAUD__rec_baud__reserved 15
-
-#define R_SERIAL2_REC_CTRL (IO_TYPECAST_BYTE 0xb0000072)
-#define R_SERIAL2_REC_CTRL__dma_err__BITNR 7
-#define R_SERIAL2_REC_CTRL__dma_err__WIDTH 1
-#define R_SERIAL2_REC_CTRL__dma_err__stop 0
-#define R_SERIAL2_REC_CTRL__dma_err__ignore 1
-#define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6
-#define R_SERIAL2_REC_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL2_REC_CTRL__rec_enable__disable 0
-#define R_SERIAL2_REC_CTRL__rec_enable__enable 1
-#define R_SERIAL2_REC_CTRL__rts___BITNR 5
-#define R_SERIAL2_REC_CTRL__rts___WIDTH 1
-#define R_SERIAL2_REC_CTRL__rts___active 0
-#define R_SERIAL2_REC_CTRL__rts___inactive 1
-#define R_SERIAL2_REC_CTRL__sampling__BITNR 4
-#define R_SERIAL2_REC_CTRL__sampling__WIDTH 1
-#define R_SERIAL2_REC_CTRL__sampling__middle 0
-#define R_SERIAL2_REC_CTRL__sampling__majority 1
-#define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3
-#define R_SERIAL2_REC_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL2_REC_CTRL__rec_stick_par__normal 0
-#define R_SERIAL2_REC_CTRL__rec_stick_par__stick 1
-#define R_SERIAL2_REC_CTRL__rec_par__BITNR 2
-#define R_SERIAL2_REC_CTRL__rec_par__WIDTH 1
-#define R_SERIAL2_REC_CTRL__rec_par__even 0
-#define R_SERIAL2_REC_CTRL__rec_par__odd 1
-#define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1
-#define R_SERIAL2_REC_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL2_REC_CTRL__rec_par_en__disable 0
-#define R_SERIAL2_REC_CTRL__rec_par_en__enable 1
-#define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0
-#define R_SERIAL2_REC_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_7bit 1
-
-#define R_SERIAL2_TR_CTRL (IO_TYPECAST_BYTE 0xb0000071)
-#define R_SERIAL2_TR_CTRL__txd__BITNR 7
-#define R_SERIAL2_TR_CTRL__txd__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6
-#define R_SERIAL2_TR_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_enable__disable 0
-#define R_SERIAL2_TR_CTRL__tr_enable__enable 1
-#define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5
-#define R_SERIAL2_TR_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL2_TR_CTRL__auto_cts__disabled 0
-#define R_SERIAL2_TR_CTRL__auto_cts__active 1
-#define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4
-#define R_SERIAL2_TR_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL2_TR_CTRL__stop_bits__one_bit 0
-#define R_SERIAL2_TR_CTRL__stop_bits__two_bits 1
-#define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3
-#define R_SERIAL2_TR_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_stick_par__normal 0
-#define R_SERIAL2_TR_CTRL__tr_stick_par__stick 1
-#define R_SERIAL2_TR_CTRL__tr_par__BITNR 2
-#define R_SERIAL2_TR_CTRL__tr_par__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_par__even 0
-#define R_SERIAL2_TR_CTRL__tr_par__odd 1
-#define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1
-#define R_SERIAL2_TR_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_par_en__disable 0
-#define R_SERIAL2_TR_CTRL__tr_par_en__enable 1
-#define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0
-#define R_SERIAL2_TR_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_7bit 1
-
-#define R_SERIAL2_TR_DATA (IO_TYPECAST_BYTE 0xb0000070)
-#define R_SERIAL2_TR_DATA__data_out__BITNR 0
-#define R_SERIAL2_TR_DATA__data_out__WIDTH 8
-
-#define R_SERIAL2_READ (IO_TYPECAST_RO_UDWORD 0xb0000070)
-#define R_SERIAL2_READ__xoff_detect__BITNR 15
-#define R_SERIAL2_READ__xoff_detect__WIDTH 1
-#define R_SERIAL2_READ__xoff_detect__no_xoff 0
-#define R_SERIAL2_READ__xoff_detect__xoff 1
-#define R_SERIAL2_READ__cts___BITNR 14
-#define R_SERIAL2_READ__cts___WIDTH 1
-#define R_SERIAL2_READ__cts___active 0
-#define R_SERIAL2_READ__cts___inactive 1
-#define R_SERIAL2_READ__tr_ready__BITNR 13
-#define R_SERIAL2_READ__tr_ready__WIDTH 1
-#define R_SERIAL2_READ__tr_ready__full 0
-#define R_SERIAL2_READ__tr_ready__ready 1
-#define R_SERIAL2_READ__rxd__BITNR 12
-#define R_SERIAL2_READ__rxd__WIDTH 1
-#define R_SERIAL2_READ__overrun__BITNR 11
-#define R_SERIAL2_READ__overrun__WIDTH 1
-#define R_SERIAL2_READ__overrun__no 0
-#define R_SERIAL2_READ__overrun__yes 1
-#define R_SERIAL2_READ__par_err__BITNR 10
-#define R_SERIAL2_READ__par_err__WIDTH 1
-#define R_SERIAL2_READ__par_err__no 0
-#define R_SERIAL2_READ__par_err__yes 1
-#define R_SERIAL2_READ__framing_err__BITNR 9
-#define R_SERIAL2_READ__framing_err__WIDTH 1
-#define R_SERIAL2_READ__framing_err__no 0
-#define R_SERIAL2_READ__framing_err__yes 1
-#define R_SERIAL2_READ__data_avail__BITNR 8
-#define R_SERIAL2_READ__data_avail__WIDTH 1
-#define R_SERIAL2_READ__data_avail__no 0
-#define R_SERIAL2_READ__data_avail__yes 1
-#define R_SERIAL2_READ__data_in__BITNR 0
-#define R_SERIAL2_READ__data_in__WIDTH 8
-
-#define R_SERIAL2_STATUS (IO_TYPECAST_RO_BYTE 0xb0000071)
-#define R_SERIAL2_STATUS__xoff_detect__BITNR 7
-#define R_SERIAL2_STATUS__xoff_detect__WIDTH 1
-#define R_SERIAL2_STATUS__xoff_detect__no_xoff 0
-#define R_SERIAL2_STATUS__xoff_detect__xoff 1
-#define R_SERIAL2_STATUS__cts___BITNR 6
-#define R_SERIAL2_STATUS__cts___WIDTH 1
-#define R_SERIAL2_STATUS__cts___active 0
-#define R_SERIAL2_STATUS__cts___inactive 1
-#define R_SERIAL2_STATUS__tr_ready__BITNR 5
-#define R_SERIAL2_STATUS__tr_ready__WIDTH 1
-#define R_SERIAL2_STATUS__tr_ready__full 0
-#define R_SERIAL2_STATUS__tr_ready__ready 1
-#define R_SERIAL2_STATUS__rxd__BITNR 4
-#define R_SERIAL2_STATUS__rxd__WIDTH 1
-#define R_SERIAL2_STATUS__overrun__BITNR 3
-#define R_SERIAL2_STATUS__overrun__WIDTH 1
-#define R_SERIAL2_STATUS__overrun__no 0
-#define R_SERIAL2_STATUS__overrun__yes 1
-#define R_SERIAL2_STATUS__par_err__BITNR 2
-#define R_SERIAL2_STATUS__par_err__WIDTH 1
-#define R_SERIAL2_STATUS__par_err__no 0
-#define R_SERIAL2_STATUS__par_err__yes 1
-#define R_SERIAL2_STATUS__framing_err__BITNR 1
-#define R_SERIAL2_STATUS__framing_err__WIDTH 1
-#define R_SERIAL2_STATUS__framing_err__no 0
-#define R_SERIAL2_STATUS__framing_err__yes 1
-#define R_SERIAL2_STATUS__data_avail__BITNR 0
-#define R_SERIAL2_STATUS__data_avail__WIDTH 1
-#define R_SERIAL2_STATUS__data_avail__no 0
-#define R_SERIAL2_STATUS__data_avail__yes 1
-
-#define R_SERIAL2_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000070)
-#define R_SERIAL2_REC_DATA__data_in__BITNR 0
-#define R_SERIAL2_REC_DATA__data_in__WIDTH 8
-
-#define R_SERIAL2_XOFF (IO_TYPECAST_UDWORD 0xb0000074)
-#define R_SERIAL2_XOFF__tx_stop__BITNR 9
-#define R_SERIAL2_XOFF__tx_stop__WIDTH 1
-#define R_SERIAL2_XOFF__tx_stop__enable 0
-#define R_SERIAL2_XOFF__tx_stop__stop 1
-#define R_SERIAL2_XOFF__auto_xoff__BITNR 8
-#define R_SERIAL2_XOFF__auto_xoff__WIDTH 1
-#define R_SERIAL2_XOFF__auto_xoff__disable 0
-#define R_SERIAL2_XOFF__auto_xoff__enable 1
-#define R_SERIAL2_XOFF__xoff_char__BITNR 0
-#define R_SERIAL2_XOFF__xoff_char__WIDTH 8
-
-#define R_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078)
-#define R_SERIAL3_CTRL__tr_baud__BITNR 28
-#define R_SERIAL3_CTRL__tr_baud__WIDTH 4
-#define R_SERIAL3_CTRL__tr_baud__c300Hz 0
-#define R_SERIAL3_CTRL__tr_baud__c600Hz 1
-#define R_SERIAL3_CTRL__tr_baud__c1200Hz 2
-#define R_SERIAL3_CTRL__tr_baud__c2400Hz 3
-#define R_SERIAL3_CTRL__tr_baud__c4800Hz 4
-#define R_SERIAL3_CTRL__tr_baud__c9600Hz 5
-#define R_SERIAL3_CTRL__tr_baud__c19k2Hz 6
-#define R_SERIAL3_CTRL__tr_baud__c38k4Hz 7
-#define R_SERIAL3_CTRL__tr_baud__c57k6Hz 8
-#define R_SERIAL3_CTRL__tr_baud__c115k2Hz 9
-#define R_SERIAL3_CTRL__tr_baud__c230k4Hz 10
-#define R_SERIAL3_CTRL__tr_baud__c460k8Hz 11
-#define R_SERIAL3_CTRL__tr_baud__c921k6Hz 12
-#define R_SERIAL3_CTRL__tr_baud__c1843k2Hz 13
-#define R_SERIAL3_CTRL__tr_baud__c6250kHz 14
-#define R_SERIAL3_CTRL__tr_baud__reserved 15
-#define R_SERIAL3_CTRL__rec_baud__BITNR 24
-#define R_SERIAL3_CTRL__rec_baud__WIDTH 4
-#define R_SERIAL3_CTRL__rec_baud__c300Hz 0
-#define R_SERIAL3_CTRL__rec_baud__c600Hz 1
-#define R_SERIAL3_CTRL__rec_baud__c1200Hz 2
-#define R_SERIAL3_CTRL__rec_baud__c2400Hz 3
-#define R_SERIAL3_CTRL__rec_baud__c4800Hz 4
-#define R_SERIAL3_CTRL__rec_baud__c9600Hz 5
-#define R_SERIAL3_CTRL__rec_baud__c19k2Hz 6
-#define R_SERIAL3_CTRL__rec_baud__c38k4Hz 7
-#define R_SERIAL3_CTRL__rec_baud__c57k6Hz 8
-#define R_SERIAL3_CTRL__rec_baud__c115k2Hz 9
-#define R_SERIAL3_CTRL__rec_baud__c230k4Hz 10
-#define R_SERIAL3_CTRL__rec_baud__c460k8Hz 11
-#define R_SERIAL3_CTRL__rec_baud__c921k6Hz 12
-#define R_SERIAL3_CTRL__rec_baud__c1843k2Hz 13
-#define R_SERIAL3_CTRL__rec_baud__c6250kHz 14
-#define R_SERIAL3_CTRL__rec_baud__reserved 15
-#define R_SERIAL3_CTRL__dma_err__BITNR 23
-#define R_SERIAL3_CTRL__dma_err__WIDTH 1
-#define R_SERIAL3_CTRL__dma_err__stop 0
-#define R_SERIAL3_CTRL__dma_err__ignore 1
-#define R_SERIAL3_CTRL__rec_enable__BITNR 22
-#define R_SERIAL3_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL3_CTRL__rec_enable__disable 0
-#define R_SERIAL3_CTRL__rec_enable__enable 1
-#define R_SERIAL3_CTRL__rts___BITNR 21
-#define R_SERIAL3_CTRL__rts___WIDTH 1
-#define R_SERIAL3_CTRL__rts___active 0
-#define R_SERIAL3_CTRL__rts___inactive 1
-#define R_SERIAL3_CTRL__sampling__BITNR 20
-#define R_SERIAL3_CTRL__sampling__WIDTH 1
-#define R_SERIAL3_CTRL__sampling__middle 0
-#define R_SERIAL3_CTRL__sampling__majority 1
-#define R_SERIAL3_CTRL__rec_stick_par__BITNR 19
-#define R_SERIAL3_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL3_CTRL__rec_stick_par__normal 0
-#define R_SERIAL3_CTRL__rec_stick_par__stick 1
-#define R_SERIAL3_CTRL__rec_par__BITNR 18
-#define R_SERIAL3_CTRL__rec_par__WIDTH 1
-#define R_SERIAL3_CTRL__rec_par__even 0
-#define R_SERIAL3_CTRL__rec_par__odd 1
-#define R_SERIAL3_CTRL__rec_par_en__BITNR 17
-#define R_SERIAL3_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL3_CTRL__rec_par_en__disable 0
-#define R_SERIAL3_CTRL__rec_par_en__enable 1
-#define R_SERIAL3_CTRL__rec_bitnr__BITNR 16
-#define R_SERIAL3_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL3_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL3_CTRL__rec_bitnr__rec_7bit 1
-#define R_SERIAL3_CTRL__txd__BITNR 15
-#define R_SERIAL3_CTRL__txd__WIDTH 1
-#define R_SERIAL3_CTRL__tr_enable__BITNR 14
-#define R_SERIAL3_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL3_CTRL__tr_enable__disable 0
-#define R_SERIAL3_CTRL__tr_enable__enable 1
-#define R_SERIAL3_CTRL__auto_cts__BITNR 13
-#define R_SERIAL3_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL3_CTRL__auto_cts__disabled 0
-#define R_SERIAL3_CTRL__auto_cts__active 1
-#define R_SERIAL3_CTRL__stop_bits__BITNR 12
-#define R_SERIAL3_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL3_CTRL__stop_bits__one_bit 0
-#define R_SERIAL3_CTRL__stop_bits__two_bits 1
-#define R_SERIAL3_CTRL__tr_stick_par__BITNR 11
-#define R_SERIAL3_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL3_CTRL__tr_stick_par__normal 0
-#define R_SERIAL3_CTRL__tr_stick_par__stick 1
-#define R_SERIAL3_CTRL__tr_par__BITNR 10
-#define R_SERIAL3_CTRL__tr_par__WIDTH 1
-#define R_SERIAL3_CTRL__tr_par__even 0
-#define R_SERIAL3_CTRL__tr_par__odd 1
-#define R_SERIAL3_CTRL__tr_par_en__BITNR 9
-#define R_SERIAL3_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL3_CTRL__tr_par_en__disable 0
-#define R_SERIAL3_CTRL__tr_par_en__enable 1
-#define R_SERIAL3_CTRL__tr_bitnr__BITNR 8
-#define R_SERIAL3_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL3_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL3_CTRL__tr_bitnr__tr_7bit 1
-#define R_SERIAL3_CTRL__data_out__BITNR 0
-#define R_SERIAL3_CTRL__data_out__WIDTH 8
-
-#define R_SERIAL3_BAUD (IO_TYPECAST_BYTE 0xb000007b)
-#define R_SERIAL3_BAUD__tr_baud__BITNR 4
-#define R_SERIAL3_BAUD__tr_baud__WIDTH 4
-#define R_SERIAL3_BAUD__tr_baud__c300Hz 0
-#define R_SERIAL3_BAUD__tr_baud__c600Hz 1
-#define R_SERIAL3_BAUD__tr_baud__c1200Hz 2
-#define R_SERIAL3_BAUD__tr_baud__c2400Hz 3
-#define R_SERIAL3_BAUD__tr_baud__c4800Hz 4
-#define R_SERIAL3_BAUD__tr_baud__c9600Hz 5
-#define R_SERIAL3_BAUD__tr_baud__c19k2Hz 6
-#define R_SERIAL3_BAUD__tr_baud__c38k4Hz 7
-#define R_SERIAL3_BAUD__tr_baud__c57k6Hz 8
-#define R_SERIAL3_BAUD__tr_baud__c115k2Hz 9
-#define R_SERIAL3_BAUD__tr_baud__c230k4Hz 10
-#define R_SERIAL3_BAUD__tr_baud__c460k8Hz 11
-#define R_SERIAL3_BAUD__tr_baud__c921k6Hz 12
-#define R_SERIAL3_BAUD__tr_baud__c1843k2Hz 13
-#define R_SERIAL3_BAUD__tr_baud__c6250kHz 14
-#define R_SERIAL3_BAUD__tr_baud__reserved 15
-#define R_SERIAL3_BAUD__rec_baud__BITNR 0
-#define R_SERIAL3_BAUD__rec_baud__WIDTH 4
-#define R_SERIAL3_BAUD__rec_baud__c300Hz 0
-#define R_SERIAL3_BAUD__rec_baud__c600Hz 1
-#define R_SERIAL3_BAUD__rec_baud__c1200Hz 2
-#define R_SERIAL3_BAUD__rec_baud__c2400Hz 3
-#define R_SERIAL3_BAUD__rec_baud__c4800Hz 4
-#define R_SERIAL3_BAUD__rec_baud__c9600Hz 5
-#define R_SERIAL3_BAUD__rec_baud__c19k2Hz 6
-#define R_SERIAL3_BAUD__rec_baud__c38k4Hz 7
-#define R_SERIAL3_BAUD__rec_baud__c57k6Hz 8
-#define R_SERIAL3_BAUD__rec_baud__c115k2Hz 9
-#define R_SERIAL3_BAUD__rec_baud__c230k4Hz 10
-#define R_SERIAL3_BAUD__rec_baud__c460k8Hz 11
-#define R_SERIAL3_BAUD__rec_baud__c921k6Hz 12
-#define R_SERIAL3_BAUD__rec_baud__c1843k2Hz 13
-#define R_SERIAL3_BAUD__rec_baud__c6250kHz 14
-#define R_SERIAL3_BAUD__rec_baud__reserved 15
-
-#define R_SERIAL3_REC_CTRL (IO_TYPECAST_BYTE 0xb000007a)
-#define R_SERIAL3_REC_CTRL__dma_err__BITNR 7
-#define R_SERIAL3_REC_CTRL__dma_err__WIDTH 1
-#define R_SERIAL3_REC_CTRL__dma_err__stop 0
-#define R_SERIAL3_REC_CTRL__dma_err__ignore 1
-#define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6
-#define R_SERIAL3_REC_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL3_REC_CTRL__rec_enable__disable 0
-#define R_SERIAL3_REC_CTRL__rec_enable__enable 1
-#define R_SERIAL3_REC_CTRL__rts___BITNR 5
-#define R_SERIAL3_REC_CTRL__rts___WIDTH 1
-#define R_SERIAL3_REC_CTRL__rts___active 0
-#define R_SERIAL3_REC_CTRL__rts___inactive 1
-#define R_SERIAL3_REC_CTRL__sampling__BITNR 4
-#define R_SERIAL3_REC_CTRL__sampling__WIDTH 1
-#define R_SERIAL3_REC_CTRL__sampling__middle 0
-#define R_SERIAL3_REC_CTRL__sampling__majority 1
-#define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3
-#define R_SERIAL3_REC_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL3_REC_CTRL__rec_stick_par__normal 0
-#define R_SERIAL3_REC_CTRL__rec_stick_par__stick 1
-#define R_SERIAL3_REC_CTRL__rec_par__BITNR 2
-#define R_SERIAL3_REC_CTRL__rec_par__WIDTH 1
-#define R_SERIAL3_REC_CTRL__rec_par__even 0
-#define R_SERIAL3_REC_CTRL__rec_par__odd 1
-#define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1
-#define R_SERIAL3_REC_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL3_REC_CTRL__rec_par_en__disable 0
-#define R_SERIAL3_REC_CTRL__rec_par_en__enable 1
-#define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0
-#define R_SERIAL3_REC_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_7bit 1
-
-#define R_SERIAL3_TR_CTRL (IO_TYPECAST_BYTE 0xb0000079)
-#define R_SERIAL3_TR_CTRL__txd__BITNR 7
-#define R_SERIAL3_TR_CTRL__txd__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6
-#define R_SERIAL3_TR_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_enable__disable 0
-#define R_SERIAL3_TR_CTRL__tr_enable__enable 1
-#define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5
-#define R_SERIAL3_TR_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL3_TR_CTRL__auto_cts__disabled 0
-#define R_SERIAL3_TR_CTRL__auto_cts__active 1
-#define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4
-#define R_SERIAL3_TR_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL3_TR_CTRL__stop_bits__one_bit 0
-#define R_SERIAL3_TR_CTRL__stop_bits__two_bits 1
-#define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3
-#define R_SERIAL3_TR_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_stick_par__normal 0
-#define R_SERIAL3_TR_CTRL__tr_stick_par__stick 1
-#define R_SERIAL3_TR_CTRL__tr_par__BITNR 2
-#define R_SERIAL3_TR_CTRL__tr_par__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_par__even 0
-#define R_SERIAL3_TR_CTRL__tr_par__odd 1
-#define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1
-#define R_SERIAL3_TR_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_par_en__disable 0
-#define R_SERIAL3_TR_CTRL__tr_par_en__enable 1
-#define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0
-#define R_SERIAL3_TR_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_7bit 1
-
-#define R_SERIAL3_TR_DATA (IO_TYPECAST_BYTE 0xb0000078)
-#define R_SERIAL3_TR_DATA__data_out__BITNR 0
-#define R_SERIAL3_TR_DATA__data_out__WIDTH 8
-
-#define R_SERIAL3_READ (IO_TYPECAST_RO_UDWORD 0xb0000078)
-#define R_SERIAL3_READ__xoff_detect__BITNR 15
-#define R_SERIAL3_READ__xoff_detect__WIDTH 1
-#define R_SERIAL3_READ__xoff_detect__no_xoff 0
-#define R_SERIAL3_READ__xoff_detect__xoff 1
-#define R_SERIAL3_READ__cts___BITNR 14
-#define R_SERIAL3_READ__cts___WIDTH 1
-#define R_SERIAL3_READ__cts___active 0
-#define R_SERIAL3_READ__cts___inactive 1
-#define R_SERIAL3_READ__tr_ready__BITNR 13
-#define R_SERIAL3_READ__tr_ready__WIDTH 1
-#define R_SERIAL3_READ__tr_ready__full 0
-#define R_SERIAL3_READ__tr_ready__ready 1
-#define R_SERIAL3_READ__rxd__BITNR 12
-#define R_SERIAL3_READ__rxd__WIDTH 1
-#define R_SERIAL3_READ__overrun__BITNR 11
-#define R_SERIAL3_READ__overrun__WIDTH 1
-#define R_SERIAL3_READ__overrun__no 0
-#define R_SERIAL3_READ__overrun__yes 1
-#define R_SERIAL3_READ__par_err__BITNR 10
-#define R_SERIAL3_READ__par_err__WIDTH 1
-#define R_SERIAL3_READ__par_err__no 0
-#define R_SERIAL3_READ__par_err__yes 1
-#define R_SERIAL3_READ__framing_err__BITNR 9
-#define R_SERIAL3_READ__framing_err__WIDTH 1
-#define R_SERIAL3_READ__framing_err__no 0
-#define R_SERIAL3_READ__framing_err__yes 1
-#define R_SERIAL3_READ__data_avail__BITNR 8
-#define R_SERIAL3_READ__data_avail__WIDTH 1
-#define R_SERIAL3_READ__data_avail__no 0
-#define R_SERIAL3_READ__data_avail__yes 1
-#define R_SERIAL3_READ__data_in__BITNR 0
-#define R_SERIAL3_READ__data_in__WIDTH 8
-
-#define R_SERIAL3_STATUS (IO_TYPECAST_RO_BYTE 0xb0000079)
-#define R_SERIAL3_STATUS__xoff_detect__BITNR 7
-#define R_SERIAL3_STATUS__xoff_detect__WIDTH 1
-#define R_SERIAL3_STATUS__xoff_detect__no_xoff 0
-#define R_SERIAL3_STATUS__xoff_detect__xoff 1
-#define R_SERIAL3_STATUS__cts___BITNR 6
-#define R_SERIAL3_STATUS__cts___WIDTH 1
-#define R_SERIAL3_STATUS__cts___active 0
-#define R_SERIAL3_STATUS__cts___inactive 1
-#define R_SERIAL3_STATUS__tr_ready__BITNR 5
-#define R_SERIAL3_STATUS__tr_ready__WIDTH 1
-#define R_SERIAL3_STATUS__tr_ready__full 0
-#define R_SERIAL3_STATUS__tr_ready__ready 1
-#define R_SERIAL3_STATUS__rxd__BITNR 4
-#define R_SERIAL3_STATUS__rxd__WIDTH 1
-#define R_SERIAL3_STATUS__overrun__BITNR 3
-#define R_SERIAL3_STATUS__overrun__WIDTH 1
-#define R_SERIAL3_STATUS__overrun__no 0
-#define R_SERIAL3_STATUS__overrun__yes 1
-#define R_SERIAL3_STATUS__par_err__BITNR 2
-#define R_SERIAL3_STATUS__par_err__WIDTH 1
-#define R_SERIAL3_STATUS__par_err__no 0
-#define R_SERIAL3_STATUS__par_err__yes 1
-#define R_SERIAL3_STATUS__framing_err__BITNR 1
-#define R_SERIAL3_STATUS__framing_err__WIDTH 1
-#define R_SERIAL3_STATUS__framing_err__no 0
-#define R_SERIAL3_STATUS__framing_err__yes 1
-#define R_SERIAL3_STATUS__data_avail__BITNR 0
-#define R_SERIAL3_STATUS__data_avail__WIDTH 1
-#define R_SERIAL3_STATUS__data_avail__no 0
-#define R_SERIAL3_STATUS__data_avail__yes 1
-
-#define R_SERIAL3_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000078)
-#define R_SERIAL3_REC_DATA__data_in__BITNR 0
-#define R_SERIAL3_REC_DATA__data_in__WIDTH 8
-
-#define R_SERIAL3_XOFF (IO_TYPECAST_UDWORD 0xb000007c)
-#define R_SERIAL3_XOFF__tx_stop__BITNR 9
-#define R_SERIAL3_XOFF__tx_stop__WIDTH 1
-#define R_SERIAL3_XOFF__tx_stop__enable 0
-#define R_SERIAL3_XOFF__tx_stop__stop 1
-#define R_SERIAL3_XOFF__auto_xoff__BITNR 8
-#define R_SERIAL3_XOFF__auto_xoff__WIDTH 1
-#define R_SERIAL3_XOFF__auto_xoff__disable 0
-#define R_SERIAL3_XOFF__auto_xoff__enable 1
-#define R_SERIAL3_XOFF__xoff_char__BITNR 0
-#define R_SERIAL3_XOFF__xoff_char__WIDTH 8
-
-#define R_ALT_SER_BAUDRATE (IO_TYPECAST_UDWORD 0xb000005c)
-#define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28
-#define R_ALT_SER_BAUDRATE__ser3_tr__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser3_tr__normal 0
-#define R_ALT_SER_BAUDRATE__ser3_tr__prescale 1
-#define R_ALT_SER_BAUDRATE__ser3_tr__extern 2
-#define R_ALT_SER_BAUDRATE__ser3_tr__timer 3
-#define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24
-#define R_ALT_SER_BAUDRATE__ser3_rec__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser3_rec__normal 0
-#define R_ALT_SER_BAUDRATE__ser3_rec__prescale 1
-#define R_ALT_SER_BAUDRATE__ser3_rec__extern 2
-#define R_ALT_SER_BAUDRATE__ser3_rec__timer 3
-#define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20
-#define R_ALT_SER_BAUDRATE__ser2_tr__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser2_tr__normal 0
-#define R_ALT_SER_BAUDRATE__ser2_tr__prescale 1
-#define R_ALT_SER_BAUDRATE__ser2_tr__extern 2
-#define R_ALT_SER_BAUDRATE__ser2_tr__timer 3
-#define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16
-#define R_ALT_SER_BAUDRATE__ser2_rec__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser2_rec__normal 0
-#define R_ALT_SER_BAUDRATE__ser2_rec__prescale 1
-#define R_ALT_SER_BAUDRATE__ser2_rec__extern 2
-#define R_ALT_SER_BAUDRATE__ser2_rec__timer 3
-#define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12
-#define R_ALT_SER_BAUDRATE__ser1_tr__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser1_tr__normal 0
-#define R_ALT_SER_BAUDRATE__ser1_tr__prescale 1
-#define R_ALT_SER_BAUDRATE__ser1_tr__extern 2
-#define R_ALT_SER_BAUDRATE__ser1_tr__timer 3
-#define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8
-#define R_ALT_SER_BAUDRATE__ser1_rec__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser1_rec__normal 0
-#define R_ALT_SER_BAUDRATE__ser1_rec__prescale 1
-#define R_ALT_SER_BAUDRATE__ser1_rec__extern 2
-#define R_ALT_SER_BAUDRATE__ser1_rec__timer 3
-#define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4
-#define R_ALT_SER_BAUDRATE__ser0_tr__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser0_tr__normal 0
-#define R_ALT_SER_BAUDRATE__ser0_tr__prescale 1
-#define R_ALT_SER_BAUDRATE__ser0_tr__extern 2
-#define R_ALT_SER_BAUDRATE__ser0_tr__timer 3
-#define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0
-#define R_ALT_SER_BAUDRATE__ser0_rec__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser0_rec__normal 0
-#define R_ALT_SER_BAUDRATE__ser0_rec__prescale 1
-#define R_ALT_SER_BAUDRATE__ser0_rec__extern 2
-#define R_ALT_SER_BAUDRATE__ser0_rec__timer 3
-
-/*
-!* Network interface registers
-!*/
-
-#define R_NETWORK_SA_0 (IO_TYPECAST_UDWORD 0xb0000080)
-#define R_NETWORK_SA_0__ma0_low__BITNR 0
-#define R_NETWORK_SA_0__ma0_low__WIDTH 32
-
-#define R_NETWORK_SA_1 (IO_TYPECAST_UDWORD 0xb0000084)
-#define R_NETWORK_SA_1__ma1_low__BITNR 16
-#define R_NETWORK_SA_1__ma1_low__WIDTH 16
-#define R_NETWORK_SA_1__ma0_high__BITNR 0
-#define R_NETWORK_SA_1__ma0_high__WIDTH 16
-
-#define R_NETWORK_SA_2 (IO_TYPECAST_UDWORD 0xb0000088)
-#define R_NETWORK_SA_2__ma1_high__BITNR 0
-#define R_NETWORK_SA_2__ma1_high__WIDTH 32
-
-#define R_NETWORK_GA_0 (IO_TYPECAST_UDWORD 0xb000008c)
-#define R_NETWORK_GA_0__ga_low__BITNR 0
-#define R_NETWORK_GA_0__ga_low__WIDTH 32
-
-#define R_NETWORK_GA_1 (IO_TYPECAST_UDWORD 0xb0000090)
-#define R_NETWORK_GA_1__ga_high__BITNR 0
-#define R_NETWORK_GA_1__ga_high__WIDTH 32
-
-#define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094)
-#define R_NETWORK_REC_CONFIG__max_size__BITNR 10
-#define R_NETWORK_REC_CONFIG__max_size__WIDTH 1
-#define R_NETWORK_REC_CONFIG__max_size__size1518 0
-#define R_NETWORK_REC_CONFIG__max_size__size1522 1
-#define R_NETWORK_REC_CONFIG__duplex__BITNR 9
-#define R_NETWORK_REC_CONFIG__duplex__WIDTH 1
-#define R_NETWORK_REC_CONFIG__duplex__full 1
-#define R_NETWORK_REC_CONFIG__duplex__half 0
-#define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8
-#define R_NETWORK_REC_CONFIG__bad_crc__WIDTH 1
-#define R_NETWORK_REC_CONFIG__bad_crc__receive 1
-#define R_NETWORK_REC_CONFIG__bad_crc__discard 0
-#define R_NETWORK_REC_CONFIG__oversize__BITNR 7
-#define R_NETWORK_REC_CONFIG__oversize__WIDTH 1
-#define R_NETWORK_REC_CONFIG__oversize__receive 1
-#define R_NETWORK_REC_CONFIG__oversize__discard 0
-#define R_NETWORK_REC_CONFIG__undersize__BITNR 6
-#define R_NETWORK_REC_CONFIG__undersize__WIDTH 1
-#define R_NETWORK_REC_CONFIG__undersize__receive 1
-#define R_NETWORK_REC_CONFIG__undersize__discard 0
-#define R_NETWORK_REC_CONFIG__all_roots__BITNR 5
-#define R_NETWORK_REC_CONFIG__all_roots__WIDTH 1
-#define R_NETWORK_REC_CONFIG__all_roots__receive 1
-#define R_NETWORK_REC_CONFIG__all_roots__discard 0
-#define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4
-#define R_NETWORK_REC_CONFIG__tr_broadcast__WIDTH 1
-#define R_NETWORK_REC_CONFIG__tr_broadcast__receive 1
-#define R_NETWORK_REC_CONFIG__tr_broadcast__discard 0
-#define R_NETWORK_REC_CONFIG__broadcast__BITNR 3
-#define R_NETWORK_REC_CONFIG__broadcast__WIDTH 1
-#define R_NETWORK_REC_CONFIG__broadcast__receive 1
-#define R_NETWORK_REC_CONFIG__broadcast__discard 0
-#define R_NETWORK_REC_CONFIG__individual__BITNR 2
-#define R_NETWORK_REC_CONFIG__individual__WIDTH 1
-#define R_NETWORK_REC_CONFIG__individual__receive 1
-#define R_NETWORK_REC_CONFIG__individual__discard 0
-#define R_NETWORK_REC_CONFIG__ma1__BITNR 1
-#define R_NETWORK_REC_CONFIG__ma1__WIDTH 1
-#define R_NETWORK_REC_CONFIG__ma1__enable 1
-#define R_NETWORK_REC_CONFIG__ma1__disable 0
-#define R_NETWORK_REC_CONFIG__ma0__BITNR 0
-#define R_NETWORK_REC_CONFIG__ma0__WIDTH 1
-#define R_NETWORK_REC_CONFIG__ma0__enable 1
-#define R_NETWORK_REC_CONFIG__ma0__disable 0
-
-#define R_NETWORK_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb0000098)
-#define R_NETWORK_GEN_CONFIG__loopback__BITNR 5
-#define R_NETWORK_GEN_CONFIG__loopback__WIDTH 1
-#define R_NETWORK_GEN_CONFIG__loopback__on 1
-#define R_NETWORK_GEN_CONFIG__loopback__off 0
-#define R_NETWORK_GEN_CONFIG__frame__BITNR 4
-#define R_NETWORK_GEN_CONFIG__frame__WIDTH 1
-#define R_NETWORK_GEN_CONFIG__frame__tokenr 1
-#define R_NETWORK_GEN_CONFIG__frame__ether 0
-#define R_NETWORK_GEN_CONFIG__vg__BITNR 3
-#define R_NETWORK_GEN_CONFIG__vg__WIDTH 1
-#define R_NETWORK_GEN_CONFIG__vg__on 1
-#define R_NETWORK_GEN_CONFIG__vg__off 0
-#define R_NETWORK_GEN_CONFIG__phy__BITNR 1
-#define R_NETWORK_GEN_CONFIG__phy__WIDTH 2
-#define R_NETWORK_GEN_CONFIG__phy__sni 0
-#define R_NETWORK_GEN_CONFIG__phy__mii_clk 1
-#define R_NETWORK_GEN_CONFIG__phy__mii_err 2
-#define R_NETWORK_GEN_CONFIG__phy__mii_req 3
-#define R_NETWORK_GEN_CONFIG__enable__BITNR 0
-#define R_NETWORK_GEN_CONFIG__enable__WIDTH 1
-#define R_NETWORK_GEN_CONFIG__enable__on 1
-#define R_NETWORK_GEN_CONFIG__enable__off 0
-
-#define R_NETWORK_TR_CTRL (IO_TYPECAST_UDWORD 0xb000009c)
-#define R_NETWORK_TR_CTRL__clr_error__BITNR 8
-#define R_NETWORK_TR_CTRL__clr_error__WIDTH 1
-#define R_NETWORK_TR_CTRL__clr_error__clr 1
-#define R_NETWORK_TR_CTRL__clr_error__nop 0
-#define R_NETWORK_TR_CTRL__delay__BITNR 5
-#define R_NETWORK_TR_CTRL__delay__WIDTH 1
-#define R_NETWORK_TR_CTRL__delay__d2us 1
-#define R_NETWORK_TR_CTRL__delay__none 0
-#define R_NETWORK_TR_CTRL__cancel__BITNR 4
-#define R_NETWORK_TR_CTRL__cancel__WIDTH 1
-#define R_NETWORK_TR_CTRL__cancel__do 1
-#define R_NETWORK_TR_CTRL__cancel__dont 0
-#define R_NETWORK_TR_CTRL__cd__BITNR 3
-#define R_NETWORK_TR_CTRL__cd__WIDTH 1
-#define R_NETWORK_TR_CTRL__cd__enable 0
-#define R_NETWORK_TR_CTRL__cd__disable 1
-#define R_NETWORK_TR_CTRL__cd__ack_col 0
-#define R_NETWORK_TR_CTRL__cd__ack_crs 1
-#define R_NETWORK_TR_CTRL__retry__BITNR 2
-#define R_NETWORK_TR_CTRL__retry__WIDTH 1
-#define R_NETWORK_TR_CTRL__retry__enable 0
-#define R_NETWORK_TR_CTRL__retry__disable 1
-#define R_NETWORK_TR_CTRL__pad__BITNR 1
-#define R_NETWORK_TR_CTRL__pad__WIDTH 1
-#define R_NETWORK_TR_CTRL__pad__enable 1
-#define R_NETWORK_TR_CTRL__pad__disable 0
-#define R_NETWORK_TR_CTRL__crc__BITNR 0
-#define R_NETWORK_TR_CTRL__crc__WIDTH 1
-#define R_NETWORK_TR_CTRL__crc__enable 0
-#define R_NETWORK_TR_CTRL__crc__disable 1
-
-#define R_NETWORK_MGM_CTRL (IO_TYPECAST_UDWORD 0xb00000a0)
-#define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4
-#define R_NETWORK_MGM_CTRL__txd_pins__WIDTH 4
-#define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3
-#define R_NETWORK_MGM_CTRL__txer_pin__WIDTH 1
-#define R_NETWORK_MGM_CTRL__mdck__BITNR 2
-#define R_NETWORK_MGM_CTRL__mdck__WIDTH 1
-#define R_NETWORK_MGM_CTRL__mdoe__BITNR 1
-#define R_NETWORK_MGM_CTRL__mdoe__WIDTH 1
-#define R_NETWORK_MGM_CTRL__mdoe__enable 1
-#define R_NETWORK_MGM_CTRL__mdoe__disable 0
-#define R_NETWORK_MGM_CTRL__mdio__BITNR 0
-#define R_NETWORK_MGM_CTRL__mdio__WIDTH 1
-
-#define R_NETWORK_STAT (IO_TYPECAST_RO_UDWORD 0xb00000a0)
-#define R_NETWORK_STAT__rxd_pins__BITNR 4
-#define R_NETWORK_STAT__rxd_pins__WIDTH 4
-#define R_NETWORK_STAT__rxer__BITNR 3
-#define R_NETWORK_STAT__rxer__WIDTH 1
-#define R_NETWORK_STAT__underrun__BITNR 2
-#define R_NETWORK_STAT__underrun__WIDTH 1
-#define R_NETWORK_STAT__underrun__yes 1
-#define R_NETWORK_STAT__underrun__no 0
-#define R_NETWORK_STAT__exc_col__BITNR 1
-#define R_NETWORK_STAT__exc_col__WIDTH 1
-#define R_NETWORK_STAT__exc_col__yes 1
-#define R_NETWORK_STAT__exc_col__no 0
-#define R_NETWORK_STAT__mdio__BITNR 0
-#define R_NETWORK_STAT__mdio__WIDTH 1
-
-#define R_REC_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a4)
-#define R_REC_COUNTERS__congestion__BITNR 24
-#define R_REC_COUNTERS__congestion__WIDTH 8
-#define R_REC_COUNTERS__oversize__BITNR 16
-#define R_REC_COUNTERS__oversize__WIDTH 8
-#define R_REC_COUNTERS__alignment_error__BITNR 8
-#define R_REC_COUNTERS__alignment_error__WIDTH 8
-#define R_REC_COUNTERS__crc_error__BITNR 0
-#define R_REC_COUNTERS__crc_error__WIDTH 8
-
-#define R_TR_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a8)
-#define R_TR_COUNTERS__deferred__BITNR 24
-#define R_TR_COUNTERS__deferred__WIDTH 8
-#define R_TR_COUNTERS__late_col__BITNR 16
-#define R_TR_COUNTERS__late_col__WIDTH 8
-#define R_TR_COUNTERS__multiple_col__BITNR 8
-#define R_TR_COUNTERS__multiple_col__WIDTH 8
-#define R_TR_COUNTERS__single_col__BITNR 0
-#define R_TR_COUNTERS__single_col__WIDTH 8
-
-#define R_PHY_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000ac)
-#define R_PHY_COUNTERS__sqe_test_error__BITNR 8
-#define R_PHY_COUNTERS__sqe_test_error__WIDTH 8
-#define R_PHY_COUNTERS__carrier_loss__BITNR 0
-#define R_PHY_COUNTERS__carrier_loss__WIDTH 8
-
-/*
-!* Parallel printer port registers
-!*/
-
-#define R_PAR0_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040)
-#define R_PAR0_CTRL_DATA__peri_int__BITNR 24
-#define R_PAR0_CTRL_DATA__peri_int__WIDTH 1
-#define R_PAR0_CTRL_DATA__peri_int__ack 1
-#define R_PAR0_CTRL_DATA__peri_int__nop 0
-#define R_PAR0_CTRL_DATA__oe__BITNR 20
-#define R_PAR0_CTRL_DATA__oe__WIDTH 1
-#define R_PAR0_CTRL_DATA__oe__enable 1
-#define R_PAR0_CTRL_DATA__oe__disable 0
-#define R_PAR0_CTRL_DATA__seli__BITNR 19
-#define R_PAR0_CTRL_DATA__seli__WIDTH 1
-#define R_PAR0_CTRL_DATA__seli__active 1
-#define R_PAR0_CTRL_DATA__seli__inactive 0
-#define R_PAR0_CTRL_DATA__autofd__BITNR 18
-#define R_PAR0_CTRL_DATA__autofd__WIDTH 1
-#define R_PAR0_CTRL_DATA__autofd__active 1
-#define R_PAR0_CTRL_DATA__autofd__inactive 0
-#define R_PAR0_CTRL_DATA__strb__BITNR 17
-#define R_PAR0_CTRL_DATA__strb__WIDTH 1
-#define R_PAR0_CTRL_DATA__strb__active 1
-#define R_PAR0_CTRL_DATA__strb__inactive 0
-#define R_PAR0_CTRL_DATA__init__BITNR 16
-#define R_PAR0_CTRL_DATA__init__WIDTH 1
-#define R_PAR0_CTRL_DATA__init__active 1
-#define R_PAR0_CTRL_DATA__init__inactive 0
-#define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8
-#define R_PAR0_CTRL_DATA__ecp_cmd__WIDTH 1
-#define R_PAR0_CTRL_DATA__ecp_cmd__command 1
-#define R_PAR0_CTRL_DATA__ecp_cmd__data 0
-#define R_PAR0_CTRL_DATA__data__BITNR 0
-#define R_PAR0_CTRL_DATA__data__WIDTH 8
-
-#define R_PAR0_CTRL (IO_TYPECAST_BYTE 0xb0000042)
-#define R_PAR0_CTRL__ctrl__BITNR 0
-#define R_PAR0_CTRL__ctrl__WIDTH 5
-
-#define R_PAR0_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040)
-#define R_PAR0_STATUS_DATA__mode__BITNR 29
-#define R_PAR0_STATUS_DATA__mode__WIDTH 3
-#define R_PAR0_STATUS_DATA__mode__manual 0
-#define R_PAR0_STATUS_DATA__mode__centronics 1
-#define R_PAR0_STATUS_DATA__mode__fastbyte 2
-#define R_PAR0_STATUS_DATA__mode__nibble 3
-#define R_PAR0_STATUS_DATA__mode__byte 4
-#define R_PAR0_STATUS_DATA__mode__ecp_fwd 5
-#define R_PAR0_STATUS_DATA__mode__ecp_rev 6
-#define R_PAR0_STATUS_DATA__mode__off 7
-#define R_PAR0_STATUS_DATA__mode__epp_wr1 5
-#define R_PAR0_STATUS_DATA__mode__epp_wr2 6
-#define R_PAR0_STATUS_DATA__mode__epp_wr3 7
-#define R_PAR0_STATUS_DATA__mode__epp_rd 0
-#define R_PAR0_STATUS_DATA__perr__BITNR 28
-#define R_PAR0_STATUS_DATA__perr__WIDTH 1
-#define R_PAR0_STATUS_DATA__perr__active 1
-#define R_PAR0_STATUS_DATA__perr__inactive 0
-#define R_PAR0_STATUS_DATA__ack__BITNR 27
-#define R_PAR0_STATUS_DATA__ack__WIDTH 1
-#define R_PAR0_STATUS_DATA__ack__active 0
-#define R_PAR0_STATUS_DATA__ack__inactive 1
-#define R_PAR0_STATUS_DATA__busy__BITNR 26
-#define R_PAR0_STATUS_DATA__busy__WIDTH 1
-#define R_PAR0_STATUS_DATA__busy__active 1
-#define R_PAR0_STATUS_DATA__busy__inactive 0
-#define R_PAR0_STATUS_DATA__fault__BITNR 25
-#define R_PAR0_STATUS_DATA__fault__WIDTH 1
-#define R_PAR0_STATUS_DATA__fault__active 0
-#define R_PAR0_STATUS_DATA__fault__inactive 1
-#define R_PAR0_STATUS_DATA__sel__BITNR 24
-#define R_PAR0_STATUS_DATA__sel__WIDTH 1
-#define R_PAR0_STATUS_DATA__sel__active 1
-#define R_PAR0_STATUS_DATA__sel__inactive 0
-#define R_PAR0_STATUS_DATA__ext_mode__BITNR 23
-#define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1
-#define R_PAR0_STATUS_DATA__ext_mode__enable 1
-#define R_PAR0_STATUS_DATA__ext_mode__disable 0
-#define R_PAR0_STATUS_DATA__ecp_16__BITNR 22
-#define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1
-#define R_PAR0_STATUS_DATA__ecp_16__active 1
-#define R_PAR0_STATUS_DATA__ecp_16__inactive 0
-#define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17
-#define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1
-#define R_PAR0_STATUS_DATA__tr_rdy__ready 1
-#define R_PAR0_STATUS_DATA__tr_rdy__busy 0
-#define R_PAR0_STATUS_DATA__dav__BITNR 16
-#define R_PAR0_STATUS_DATA__dav__WIDTH 1
-#define R_PAR0_STATUS_DATA__dav__data 1
-#define R_PAR0_STATUS_DATA__dav__nodata 0
-#define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8
-#define R_PAR0_STATUS_DATA__ecp_cmd__WIDTH 1
-#define R_PAR0_STATUS_DATA__ecp_cmd__command 1
-#define R_PAR0_STATUS_DATA__ecp_cmd__data 0
-#define R_PAR0_STATUS_DATA__data__BITNR 0
-#define R_PAR0_STATUS_DATA__data__WIDTH 8
-
-#define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042)
-#define R_PAR0_STATUS__mode__BITNR 13
-#define R_PAR0_STATUS__mode__WIDTH 3
-#define R_PAR0_STATUS__mode__manual 0
-#define R_PAR0_STATUS__mode__centronics 1
-#define R_PAR0_STATUS__mode__fastbyte 2
-#define R_PAR0_STATUS__mode__nibble 3
-#define R_PAR0_STATUS__mode__byte 4
-#define R_PAR0_STATUS__mode__ecp_fwd 5
-#define R_PAR0_STATUS__mode__ecp_rev 6
-#define R_PAR0_STATUS__mode__off 7
-#define R_PAR0_STATUS__mode__epp_wr1 5
-#define R_PAR0_STATUS__mode__epp_wr2 6
-#define R_PAR0_STATUS__mode__epp_wr3 7
-#define R_PAR0_STATUS__mode__epp_rd 0
-#define R_PAR0_STATUS__perr__BITNR 12
-#define R_PAR0_STATUS__perr__WIDTH 1
-#define R_PAR0_STATUS__perr__active 1
-#define R_PAR0_STATUS__perr__inactive 0
-#define R_PAR0_STATUS__ack__BITNR 11
-#define R_PAR0_STATUS__ack__WIDTH 1
-#define R_PAR0_STATUS__ack__active 0
-#define R_PAR0_STATUS__ack__inactive 1
-#define R_PAR0_STATUS__busy__BITNR 10
-#define R_PAR0_STATUS__busy__WIDTH 1
-#define R_PAR0_STATUS__busy__active 1
-#define R_PAR0_STATUS__busy__inactive 0
-#define R_PAR0_STATUS__fault__BITNR 9
-#define R_PAR0_STATUS__fault__WIDTH 1
-#define R_PAR0_STATUS__fault__active 0
-#define R_PAR0_STATUS__fault__inactive 1
-#define R_PAR0_STATUS__sel__BITNR 8
-#define R_PAR0_STATUS__sel__WIDTH 1
-#define R_PAR0_STATUS__sel__active 1
-#define R_PAR0_STATUS__sel__inactive 0
-#define R_PAR0_STATUS__ext_mode__BITNR 7
-#define R_PAR0_STATUS__ext_mode__WIDTH 1
-#define R_PAR0_STATUS__ext_mode__enable 1
-#define R_PAR0_STATUS__ext_mode__disable 0
-#define R_PAR0_STATUS__ecp_16__BITNR 6
-#define R_PAR0_STATUS__ecp_16__WIDTH 1
-#define R_PAR0_STATUS__ecp_16__active 1
-#define R_PAR0_STATUS__ecp_16__inactive 0
-#define R_PAR0_STATUS__tr_rdy__BITNR 1
-#define R_PAR0_STATUS__tr_rdy__WIDTH 1
-#define R_PAR0_STATUS__tr_rdy__ready 1
-#define R_PAR0_STATUS__tr_rdy__busy 0
-#define R_PAR0_STATUS__dav__BITNR 0
-#define R_PAR0_STATUS__dav__WIDTH 1
-#define R_PAR0_STATUS__dav__data 1
-#define R_PAR0_STATUS__dav__nodata 0
-
-#define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040)
-#define R_PAR_ECP16_DATA__data__BITNR 0
-#define R_PAR_ECP16_DATA__data__WIDTH 16
-
-#define R_PAR0_CONFIG (IO_TYPECAST_UDWORD 0xb0000044)
-#define R_PAR0_CONFIG__ioe__BITNR 25
-#define R_PAR0_CONFIG__ioe__WIDTH 1
-#define R_PAR0_CONFIG__ioe__inv 1
-#define R_PAR0_CONFIG__ioe__noninv 0
-#define R_PAR0_CONFIG__iseli__BITNR 24
-#define R_PAR0_CONFIG__iseli__WIDTH 1
-#define R_PAR0_CONFIG__iseli__inv 1
-#define R_PAR0_CONFIG__iseli__noninv 0
-#define R_PAR0_CONFIG__iautofd__BITNR 23
-#define R_PAR0_CONFIG__iautofd__WIDTH 1
-#define R_PAR0_CONFIG__iautofd__inv 1
-#define R_PAR0_CONFIG__iautofd__noninv 0
-#define R_PAR0_CONFIG__istrb__BITNR 22
-#define R_PAR0_CONFIG__istrb__WIDTH 1
-#define R_PAR0_CONFIG__istrb__inv 1
-#define R_PAR0_CONFIG__istrb__noninv 0
-#define R_PAR0_CONFIG__iinit__BITNR 21
-#define R_PAR0_CONFIG__iinit__WIDTH 1
-#define R_PAR0_CONFIG__iinit__inv 1
-#define R_PAR0_CONFIG__iinit__noninv 0
-#define R_PAR0_CONFIG__iperr__BITNR 20
-#define R_PAR0_CONFIG__iperr__WIDTH 1
-#define R_PAR0_CONFIG__iperr__inv 1
-#define R_PAR0_CONFIG__iperr__noninv 0
-#define R_PAR0_CONFIG__iack__BITNR 19
-#define R_PAR0_CONFIG__iack__WIDTH 1
-#define R_PAR0_CONFIG__iack__inv 1
-#define R_PAR0_CONFIG__iack__noninv 0
-#define R_PAR0_CONFIG__ibusy__BITNR 18
-#define R_PAR0_CONFIG__ibusy__WIDTH 1
-#define R_PAR0_CONFIG__ibusy__inv 1
-#define R_PAR0_CONFIG__ibusy__noninv 0
-#define R_PAR0_CONFIG__ifault__BITNR 17
-#define R_PAR0_CONFIG__ifault__WIDTH 1
-#define R_PAR0_CONFIG__ifault__inv 1
-#define R_PAR0_CONFIG__ifault__noninv 0
-#define R_PAR0_CONFIG__isel__BITNR 16
-#define R_PAR0_CONFIG__isel__WIDTH 1
-#define R_PAR0_CONFIG__isel__inv 1
-#define R_PAR0_CONFIG__isel__noninv 0
-#define R_PAR0_CONFIG__ext_mode__BITNR 11
-#define R_PAR0_CONFIG__ext_mode__WIDTH 1
-#define R_PAR0_CONFIG__ext_mode__enable 1
-#define R_PAR0_CONFIG__ext_mode__disable 0
-#define R_PAR0_CONFIG__wide__BITNR 10
-#define R_PAR0_CONFIG__wide__WIDTH 1
-#define R_PAR0_CONFIG__wide__enable 1
-#define R_PAR0_CONFIG__wide__disable 0
-#define R_PAR0_CONFIG__dma__BITNR 9
-#define R_PAR0_CONFIG__dma__WIDTH 1
-#define R_PAR0_CONFIG__dma__enable 1
-#define R_PAR0_CONFIG__dma__disable 0
-#define R_PAR0_CONFIG__rle_in__BITNR 8
-#define R_PAR0_CONFIG__rle_in__WIDTH 1
-#define R_PAR0_CONFIG__rle_in__enable 1
-#define R_PAR0_CONFIG__rle_in__disable 0
-#define R_PAR0_CONFIG__rle_out__BITNR 7
-#define R_PAR0_CONFIG__rle_out__WIDTH 1
-#define R_PAR0_CONFIG__rle_out__enable 1
-#define R_PAR0_CONFIG__rle_out__disable 0
-#define R_PAR0_CONFIG__enable__BITNR 6
-#define R_PAR0_CONFIG__enable__WIDTH 1
-#define R_PAR0_CONFIG__enable__on 1
-#define R_PAR0_CONFIG__enable__reset 0
-#define R_PAR0_CONFIG__force__BITNR 5
-#define R_PAR0_CONFIG__force__WIDTH 1
-#define R_PAR0_CONFIG__force__on 1
-#define R_PAR0_CONFIG__force__off 0
-#define R_PAR0_CONFIG__ign_ack__BITNR 4
-#define R_PAR0_CONFIG__ign_ack__WIDTH 1
-#define R_PAR0_CONFIG__ign_ack__ignore 1
-#define R_PAR0_CONFIG__ign_ack__wait 0
-#define R_PAR0_CONFIG__oe_ack__BITNR 3
-#define R_PAR0_CONFIG__oe_ack__WIDTH 1
-#define R_PAR0_CONFIG__oe_ack__wait_oe 1
-#define R_PAR0_CONFIG__oe_ack__dont_wait 0
-#define R_PAR0_CONFIG__oe_ack__epp_addr 1
-#define R_PAR0_CONFIG__oe_ack__epp_data 0
-#define R_PAR0_CONFIG__epp_addr_data__BITNR 3
-#define R_PAR0_CONFIG__epp_addr_data__WIDTH 1
-#define R_PAR0_CONFIG__epp_addr_data__wait_oe 1
-#define R_PAR0_CONFIG__epp_addr_data__dont_wait 0
-#define R_PAR0_CONFIG__epp_addr_data__epp_addr 1
-#define R_PAR0_CONFIG__epp_addr_data__epp_data 0
-#define R_PAR0_CONFIG__mode__BITNR 0
-#define R_PAR0_CONFIG__mode__WIDTH 3
-#define R_PAR0_CONFIG__mode__manual 0
-#define R_PAR0_CONFIG__mode__centronics 1
-#define R_PAR0_CONFIG__mode__fastbyte 2
-#define R_PAR0_CONFIG__mode__nibble 3
-#define R_PAR0_CONFIG__mode__byte 4
-#define R_PAR0_CONFIG__mode__ecp_fwd 5
-#define R_PAR0_CONFIG__mode__ecp_rev 6
-#define R_PAR0_CONFIG__mode__off 7
-#define R_PAR0_CONFIG__mode__epp_wr1 5
-#define R_PAR0_CONFIG__mode__epp_wr2 6
-#define R_PAR0_CONFIG__mode__epp_wr3 7
-#define R_PAR0_CONFIG__mode__epp_rd 0
-
-#define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048)
-#define R_PAR0_DELAY__fine_hold__BITNR 21
-#define R_PAR0_DELAY__fine_hold__WIDTH 3
-#define R_PAR0_DELAY__hold__BITNR 16
-#define R_PAR0_DELAY__hold__WIDTH 5
-#define R_PAR0_DELAY__fine_strb__BITNR 13
-#define R_PAR0_DELAY__fine_strb__WIDTH 3
-#define R_PAR0_DELAY__strobe__BITNR 8
-#define R_PAR0_DELAY__strobe__WIDTH 5
-#define R_PAR0_DELAY__fine_setup__BITNR 5
-#define R_PAR0_DELAY__fine_setup__WIDTH 3
-#define R_PAR0_DELAY__setup__BITNR 0
-#define R_PAR0_DELAY__setup__WIDTH 5
-
-#define R_PAR1_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000050)
-#define R_PAR1_CTRL_DATA__peri_int__BITNR 24
-#define R_PAR1_CTRL_DATA__peri_int__WIDTH 1
-#define R_PAR1_CTRL_DATA__peri_int__ack 1
-#define R_PAR1_CTRL_DATA__peri_int__nop 0
-#define R_PAR1_CTRL_DATA__oe__BITNR 20
-#define R_PAR1_CTRL_DATA__oe__WIDTH 1
-#define R_PAR1_CTRL_DATA__oe__enable 1
-#define R_PAR1_CTRL_DATA__oe__disable 0
-#define R_PAR1_CTRL_DATA__seli__BITNR 19
-#define R_PAR1_CTRL_DATA__seli__WIDTH 1
-#define R_PAR1_CTRL_DATA__seli__active 1
-#define R_PAR1_CTRL_DATA__seli__inactive 0
-#define R_PAR1_CTRL_DATA__autofd__BITNR 18
-#define R_PAR1_CTRL_DATA__autofd__WIDTH 1
-#define R_PAR1_CTRL_DATA__autofd__active 1
-#define R_PAR1_CTRL_DATA__autofd__inactive 0
-#define R_PAR1_CTRL_DATA__strb__BITNR 17
-#define R_PAR1_CTRL_DATA__strb__WIDTH 1
-#define R_PAR1_CTRL_DATA__strb__active 1
-#define R_PAR1_CTRL_DATA__strb__inactive 0
-#define R_PAR1_CTRL_DATA__init__BITNR 16
-#define R_PAR1_CTRL_DATA__init__WIDTH 1
-#define R_PAR1_CTRL_DATA__init__active 1
-#define R_PAR1_CTRL_DATA__init__inactive 0
-#define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8
-#define R_PAR1_CTRL_DATA__ecp_cmd__WIDTH 1
-#define R_PAR1_CTRL_DATA__ecp_cmd__command 1
-#define R_PAR1_CTRL_DATA__ecp_cmd__data 0
-#define R_PAR1_CTRL_DATA__data__BITNR 0
-#define R_PAR1_CTRL_DATA__data__WIDTH 8
-
-#define R_PAR1_CTRL (IO_TYPECAST_BYTE 0xb0000052)
-#define R_PAR1_CTRL__ctrl__BITNR 0
-#define R_PAR1_CTRL__ctrl__WIDTH 5
-
-#define R_PAR1_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000050)
-#define R_PAR1_STATUS_DATA__mode__BITNR 29
-#define R_PAR1_STATUS_DATA__mode__WIDTH 3
-#define R_PAR1_STATUS_DATA__mode__manual 0
-#define R_PAR1_STATUS_DATA__mode__centronics 1
-#define R_PAR1_STATUS_DATA__mode__fastbyte 2
-#define R_PAR1_STATUS_DATA__mode__nibble 3
-#define R_PAR1_STATUS_DATA__mode__byte 4
-#define R_PAR1_STATUS_DATA__mode__ecp_fwd 5
-#define R_PAR1_STATUS_DATA__mode__ecp_rev 6
-#define R_PAR1_STATUS_DATA__mode__off 7
-#define R_PAR1_STATUS_DATA__mode__epp_wr1 5
-#define R_PAR1_STATUS_DATA__mode__epp_wr2 6
-#define R_PAR1_STATUS_DATA__mode__epp_wr3 7
-#define R_PAR1_STATUS_DATA__mode__epp_rd 0
-#define R_PAR1_STATUS_DATA__perr__BITNR 28
-#define R_PAR1_STATUS_DATA__perr__WIDTH 1
-#define R_PAR1_STATUS_DATA__perr__active 1
-#define R_PAR1_STATUS_DATA__perr__inactive 0
-#define R_PAR1_STATUS_DATA__ack__BITNR 27
-#define R_PAR1_STATUS_DATA__ack__WIDTH 1
-#define R_PAR1_STATUS_DATA__ack__active 0
-#define R_PAR1_STATUS_DATA__ack__inactive 1
-#define R_PAR1_STATUS_DATA__busy__BITNR 26
-#define R_PAR1_STATUS_DATA__busy__WIDTH 1
-#define R_PAR1_STATUS_DATA__busy__active 1
-#define R_PAR1_STATUS_DATA__busy__inactive 0
-#define R_PAR1_STATUS_DATA__fault__BITNR 25
-#define R_PAR1_STATUS_DATA__fault__WIDTH 1
-#define R_PAR1_STATUS_DATA__fault__active 0
-#define R_PAR1_STATUS_DATA__fault__inactive 1
-#define R_PAR1_STATUS_DATA__sel__BITNR 24
-#define R_PAR1_STATUS_DATA__sel__WIDTH 1
-#define R_PAR1_STATUS_DATA__sel__active 1
-#define R_PAR1_STATUS_DATA__sel__inactive 0
-#define R_PAR1_STATUS_DATA__ext_mode__BITNR 23
-#define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1
-#define R_PAR1_STATUS_DATA__ext_mode__enable 1
-#define R_PAR1_STATUS_DATA__ext_mode__disable 0
-#define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17
-#define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1
-#define R_PAR1_STATUS_DATA__tr_rdy__ready 1
-#define R_PAR1_STATUS_DATA__tr_rdy__busy 0
-#define R_PAR1_STATUS_DATA__dav__BITNR 16
-#define R_PAR1_STATUS_DATA__dav__WIDTH 1
-#define R_PAR1_STATUS_DATA__dav__data 1
-#define R_PAR1_STATUS_DATA__dav__nodata 0
-#define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8
-#define R_PAR1_STATUS_DATA__ecp_cmd__WIDTH 1
-#define R_PAR1_STATUS_DATA__ecp_cmd__command 1
-#define R_PAR1_STATUS_DATA__ecp_cmd__data 0
-#define R_PAR1_STATUS_DATA__data__BITNR 0
-#define R_PAR1_STATUS_DATA__data__WIDTH 8
-
-#define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052)
-#define R_PAR1_STATUS__mode__BITNR 13
-#define R_PAR1_STATUS__mode__WIDTH 3
-#define R_PAR1_STATUS__mode__manual 0
-#define R_PAR1_STATUS__mode__centronics 1
-#define R_PAR1_STATUS__mode__fastbyte 2
-#define R_PAR1_STATUS__mode__nibble 3
-#define R_PAR1_STATUS__mode__byte 4
-#define R_PAR1_STATUS__mode__ecp_fwd 5
-#define R_PAR1_STATUS__mode__ecp_rev 6
-#define R_PAR1_STATUS__mode__off 7
-#define R_PAR1_STATUS__mode__epp_wr1 5
-#define R_PAR1_STATUS__mode__epp_wr2 6
-#define R_PAR1_STATUS__mode__epp_wr3 7
-#define R_PAR1_STATUS__mode__epp_rd 0
-#define R_PAR1_STATUS__perr__BITNR 12
-#define R_PAR1_STATUS__perr__WIDTH 1
-#define R_PAR1_STATUS__perr__active 1
-#define R_PAR1_STATUS__perr__inactive 0
-#define R_PAR1_STATUS__ack__BITNR 11
-#define R_PAR1_STATUS__ack__WIDTH 1
-#define R_PAR1_STATUS__ack__active 0
-#define R_PAR1_STATUS__ack__inactive 1
-#define R_PAR1_STATUS__busy__BITNR 10
-#define R_PAR1_STATUS__busy__WIDTH 1
-#define R_PAR1_STATUS__busy__active 1
-#define R_PAR1_STATUS__busy__inactive 0
-#define R_PAR1_STATUS__fault__BITNR 9
-#define R_PAR1_STATUS__fault__WIDTH 1
-#define R_PAR1_STATUS__fault__active 0
-#define R_PAR1_STATUS__fault__inactive 1
-#define R_PAR1_STATUS__sel__BITNR 8
-#define R_PAR1_STATUS__sel__WIDTH 1
-#define R_PAR1_STATUS__sel__active 1
-#define R_PAR1_STATUS__sel__inactive 0
-#define R_PAR1_STATUS__ext_mode__BITNR 7
-#define R_PAR1_STATUS__ext_mode__WIDTH 1
-#define R_PAR1_STATUS__ext_mode__enable 1
-#define R_PAR1_STATUS__ext_mode__disable 0
-#define R_PAR1_STATUS__tr_rdy__BITNR 1
-#define R_PAR1_STATUS__tr_rdy__WIDTH 1
-#define R_PAR1_STATUS__tr_rdy__ready 1
-#define R_PAR1_STATUS__tr_rdy__busy 0
-#define R_PAR1_STATUS__dav__BITNR 0
-#define R_PAR1_STATUS__dav__WIDTH 1
-#define R_PAR1_STATUS__dav__data 1
-#define R_PAR1_STATUS__dav__nodata 0
-
-#define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054)
-#define R_PAR1_CONFIG__ioe__BITNR 25
-#define R_PAR1_CONFIG__ioe__WIDTH 1
-#define R_PAR1_CONFIG__ioe__inv 1
-#define R_PAR1_CONFIG__ioe__noninv 0
-#define R_PAR1_CONFIG__iseli__BITNR 24
-#define R_PAR1_CONFIG__iseli__WIDTH 1
-#define R_PAR1_CONFIG__iseli__inv 1
-#define R_PAR1_CONFIG__iseli__noninv 0
-#define R_PAR1_CONFIG__iautofd__BITNR 23
-#define R_PAR1_CONFIG__iautofd__WIDTH 1
-#define R_PAR1_CONFIG__iautofd__inv 1
-#define R_PAR1_CONFIG__iautofd__noninv 0
-#define R_PAR1_CONFIG__istrb__BITNR 22
-#define R_PAR1_CONFIG__istrb__WIDTH 1
-#define R_PAR1_CONFIG__istrb__inv 1
-#define R_PAR1_CONFIG__istrb__noninv 0
-#define R_PAR1_CONFIG__iinit__BITNR 21
-#define R_PAR1_CONFIG__iinit__WIDTH 1
-#define R_PAR1_CONFIG__iinit__inv 1
-#define R_PAR1_CONFIG__iinit__noninv 0
-#define R_PAR1_CONFIG__iperr__BITNR 20
-#define R_PAR1_CONFIG__iperr__WIDTH 1
-#define R_PAR1_CONFIG__iperr__inv 1
-#define R_PAR1_CONFIG__iperr__noninv 0
-#define R_PAR1_CONFIG__iack__BITNR 19
-#define R_PAR1_CONFIG__iack__WIDTH 1
-#define R_PAR1_CONFIG__iack__inv 1
-#define R_PAR1_CONFIG__iack__noninv 0
-#define R_PAR1_CONFIG__ibusy__BITNR 18
-#define R_PAR1_CONFIG__ibusy__WIDTH 1
-#define R_PAR1_CONFIG__ibusy__inv 1
-#define R_PAR1_CONFIG__ibusy__noninv 0
-#define R_PAR1_CONFIG__ifault__BITNR 17
-#define R_PAR1_CONFIG__ifault__WIDTH 1
-#define R_PAR1_CONFIG__ifault__inv 1
-#define R_PAR1_CONFIG__ifault__noninv 0
-#define R_PAR1_CONFIG__isel__BITNR 16
-#define R_PAR1_CONFIG__isel__WIDTH 1
-#define R_PAR1_CONFIG__isel__inv 1
-#define R_PAR1_CONFIG__isel__noninv 0
-#define R_PAR1_CONFIG__ext_mode__BITNR 11
-#define R_PAR1_CONFIG__ext_mode__WIDTH 1
-#define R_PAR1_CONFIG__ext_mode__enable 1
-#define R_PAR1_CONFIG__ext_mode__disable 0
-#define R_PAR1_CONFIG__dma__BITNR 9
-#define R_PAR1_CONFIG__dma__WIDTH 1
-#define R_PAR1_CONFIG__dma__enable 1
-#define R_PAR1_CONFIG__dma__disable 0
-#define R_PAR1_CONFIG__rle_in__BITNR 8
-#define R_PAR1_CONFIG__rle_in__WIDTH 1
-#define R_PAR1_CONFIG__rle_in__enable 1
-#define R_PAR1_CONFIG__rle_in__disable 0
-#define R_PAR1_CONFIG__rle_out__BITNR 7
-#define R_PAR1_CONFIG__rle_out__WIDTH 1
-#define R_PAR1_CONFIG__rle_out__enable 1
-#define R_PAR1_CONFIG__rle_out__disable 0
-#define R_PAR1_CONFIG__enable__BITNR 6
-#define R_PAR1_CONFIG__enable__WIDTH 1
-#define R_PAR1_CONFIG__enable__on 1
-#define R_PAR1_CONFIG__enable__reset 0
-#define R_PAR1_CONFIG__force__BITNR 5
-#define R_PAR1_CONFIG__force__WIDTH 1
-#define R_PAR1_CONFIG__force__on 1
-#define R_PAR1_CONFIG__force__off 0
-#define R_PAR1_CONFIG__ign_ack__BITNR 4
-#define R_PAR1_CONFIG__ign_ack__WIDTH 1
-#define R_PAR1_CONFIG__ign_ack__ignore 1
-#define R_PAR1_CONFIG__ign_ack__wait 0
-#define R_PAR1_CONFIG__oe_ack__BITNR 3
-#define R_PAR1_CONFIG__oe_ack__WIDTH 1
-#define R_PAR1_CONFIG__oe_ack__wait_oe 1
-#define R_PAR1_CONFIG__oe_ack__dont_wait 0
-#define R_PAR1_CONFIG__oe_ack__epp_addr 1
-#define R_PAR1_CONFIG__oe_ack__epp_data 0
-#define R_PAR1_CONFIG__epp_addr_data__BITNR 3
-#define R_PAR1_CONFIG__epp_addr_data__WIDTH 1
-#define R_PAR1_CONFIG__epp_addr_data__wait_oe 1
-#define R_PAR1_CONFIG__epp_addr_data__dont_wait 0
-#define R_PAR1_CONFIG__epp_addr_data__epp_addr 1
-#define R_PAR1_CONFIG__epp_addr_data__epp_data 0
-#define R_PAR1_CONFIG__mode__BITNR 0
-#define R_PAR1_CONFIG__mode__WIDTH 3
-#define R_PAR1_CONFIG__mode__manual 0
-#define R_PAR1_CONFIG__mode__centronics 1
-#define R_PAR1_CONFIG__mode__fastbyte 2
-#define R_PAR1_CONFIG__mode__nibble 3
-#define R_PAR1_CONFIG__mode__byte 4
-#define R_PAR1_CONFIG__mode__ecp_fwd 5
-#define R_PAR1_CONFIG__mode__ecp_rev 6
-#define R_PAR1_CONFIG__mode__off 7
-#define R_PAR1_CONFIG__mode__epp_wr1 5
-#define R_PAR1_CONFIG__mode__epp_wr2 6
-#define R_PAR1_CONFIG__mode__epp_wr3 7
-#define R_PAR1_CONFIG__mode__epp_rd 0
-
-#define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058)
-#define R_PAR1_DELAY__fine_hold__BITNR 21
-#define R_PAR1_DELAY__fine_hold__WIDTH 3
-#define R_PAR1_DELAY__hold__BITNR 16
-#define R_PAR1_DELAY__hold__WIDTH 5
-#define R_PAR1_DELAY__fine_strb__BITNR 13
-#define R_PAR1_DELAY__fine_strb__WIDTH 3
-#define R_PAR1_DELAY__strobe__BITNR 8
-#define R_PAR1_DELAY__strobe__WIDTH 5
-#define R_PAR1_DELAY__fine_setup__BITNR 5
-#define R_PAR1_DELAY__fine_setup__WIDTH 3
-#define R_PAR1_DELAY__setup__BITNR 0
-#define R_PAR1_DELAY__setup__WIDTH 5
-
-/*
-!* ATA interface registers
-!*/
-
-#define R_ATA_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040)
-#define R_ATA_CTRL_DATA__sel__BITNR 30
-#define R_ATA_CTRL_DATA__sel__WIDTH 2
-#define R_ATA_CTRL_DATA__cs1__BITNR 29
-#define R_ATA_CTRL_DATA__cs1__WIDTH 1
-#define R_ATA_CTRL_DATA__cs1__active 1
-#define R_ATA_CTRL_DATA__cs1__inactive 0
-#define R_ATA_CTRL_DATA__cs0__BITNR 28
-#define R_ATA_CTRL_DATA__cs0__WIDTH 1
-#define R_ATA_CTRL_DATA__cs0__active 1
-#define R_ATA_CTRL_DATA__cs0__inactive 0
-#define R_ATA_CTRL_DATA__addr__BITNR 25
-#define R_ATA_CTRL_DATA__addr__WIDTH 3
-#define R_ATA_CTRL_DATA__rw__BITNR 24
-#define R_ATA_CTRL_DATA__rw__WIDTH 1
-#define R_ATA_CTRL_DATA__rw__read 1
-#define R_ATA_CTRL_DATA__rw__write 0
-#define R_ATA_CTRL_DATA__src_dst__BITNR 23
-#define R_ATA_CTRL_DATA__src_dst__WIDTH 1
-#define R_ATA_CTRL_DATA__src_dst__dma 1
-#define R_ATA_CTRL_DATA__src_dst__register 0
-#define R_ATA_CTRL_DATA__handsh__BITNR 22
-#define R_ATA_CTRL_DATA__handsh__WIDTH 1
-#define R_ATA_CTRL_DATA__handsh__dma 1
-#define R_ATA_CTRL_DATA__handsh__pio 0
-#define R_ATA_CTRL_DATA__multi__BITNR 21
-#define R_ATA_CTRL_DATA__multi__WIDTH 1
-#define R_ATA_CTRL_DATA__multi__on 1
-#define R_ATA_CTRL_DATA__multi__off 0
-#define R_ATA_CTRL_DATA__dma_size__BITNR 20
-#define R_ATA_CTRL_DATA__dma_size__WIDTH 1
-#define R_ATA_CTRL_DATA__dma_size__byte 1
-#define R_ATA_CTRL_DATA__dma_size__word 0
-#define R_ATA_CTRL_DATA__data__BITNR 0
-#define R_ATA_CTRL_DATA__data__WIDTH 16
-
-#define R_ATA_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040)
-#define R_ATA_STATUS_DATA__busy__BITNR 18
-#define R_ATA_STATUS_DATA__busy__WIDTH 1
-#define R_ATA_STATUS_DATA__busy__yes 1
-#define R_ATA_STATUS_DATA__busy__no 0
-#define R_ATA_STATUS_DATA__tr_rdy__BITNR 17
-#define R_ATA_STATUS_DATA__tr_rdy__WIDTH 1
-#define R_ATA_STATUS_DATA__tr_rdy__ready 1
-#define R_ATA_STATUS_DATA__tr_rdy__busy 0
-#define R_ATA_STATUS_DATA__dav__BITNR 16
-#define R_ATA_STATUS_DATA__dav__WIDTH 1
-#define R_ATA_STATUS_DATA__dav__data 1
-#define R_ATA_STATUS_DATA__dav__nodata 0
-#define R_ATA_STATUS_DATA__data__BITNR 0
-#define R_ATA_STATUS_DATA__data__WIDTH 16
-
-#define R_ATA_CONFIG (IO_TYPECAST_UDWORD 0xb0000044)
-#define R_ATA_CONFIG__enable__BITNR 25
-#define R_ATA_CONFIG__enable__WIDTH 1
-#define R_ATA_CONFIG__enable__on 1
-#define R_ATA_CONFIG__enable__off 0
-#define R_ATA_CONFIG__dma_strobe__BITNR 20
-#define R_ATA_CONFIG__dma_strobe__WIDTH 5
-#define R_ATA_CONFIG__dma_hold__BITNR 15
-#define R_ATA_CONFIG__dma_hold__WIDTH 5
-#define R_ATA_CONFIG__pio_setup__BITNR 10
-#define R_ATA_CONFIG__pio_setup__WIDTH 5
-#define R_ATA_CONFIG__pio_strobe__BITNR 5
-#define R_ATA_CONFIG__pio_strobe__WIDTH 5
-#define R_ATA_CONFIG__pio_hold__BITNR 0
-#define R_ATA_CONFIG__pio_hold__WIDTH 5
-
-#define R_ATA_TRANSFER_CNT (IO_TYPECAST_UDWORD 0xb0000048)
-#define R_ATA_TRANSFER_CNT__count__BITNR 0
-#define R_ATA_TRANSFER_CNT__count__WIDTH 17
-
-/*
-!* SCSI registers
-!*/
-
-#define R_SCSI0_CTRL (IO_TYPECAST_UDWORD 0xb0000044)
-#define R_SCSI0_CTRL__id_type__BITNR 31
-#define R_SCSI0_CTRL__id_type__WIDTH 1
-#define R_SCSI0_CTRL__id_type__software 1
-#define R_SCSI0_CTRL__id_type__hardware 0
-#define R_SCSI0_CTRL__sel_timeout__BITNR 24
-#define R_SCSI0_CTRL__sel_timeout__WIDTH 7
-#define R_SCSI0_CTRL__synch_per__BITNR 16
-#define R_SCSI0_CTRL__synch_per__WIDTH 8
-#define R_SCSI0_CTRL__rst__BITNR 15
-#define R_SCSI0_CTRL__rst__WIDTH 1
-#define R_SCSI0_CTRL__rst__yes 1
-#define R_SCSI0_CTRL__rst__no 0
-#define R_SCSI0_CTRL__atn__BITNR 14
-#define R_SCSI0_CTRL__atn__WIDTH 1
-#define R_SCSI0_CTRL__atn__yes 1
-#define R_SCSI0_CTRL__atn__no 0
-#define R_SCSI0_CTRL__my_id__BITNR 9
-#define R_SCSI0_CTRL__my_id__WIDTH 4
-#define R_SCSI0_CTRL__target_id__BITNR 4
-#define R_SCSI0_CTRL__target_id__WIDTH 4
-#define R_SCSI0_CTRL__fast_20__BITNR 3
-#define R_SCSI0_CTRL__fast_20__WIDTH 1
-#define R_SCSI0_CTRL__fast_20__yes 1
-#define R_SCSI0_CTRL__fast_20__no 0
-#define R_SCSI0_CTRL__bus_width__BITNR 2
-#define R_SCSI0_CTRL__bus_width__WIDTH 1
-#define R_SCSI0_CTRL__bus_width__wide 1
-#define R_SCSI0_CTRL__bus_width__narrow 0
-#define R_SCSI0_CTRL__synch__BITNR 1
-#define R_SCSI0_CTRL__synch__WIDTH 1
-#define R_SCSI0_CTRL__synch__synch 1
-#define R_SCSI0_CTRL__synch__asynch 0
-#define R_SCSI0_CTRL__enable__BITNR 0
-#define R_SCSI0_CTRL__enable__WIDTH 1
-#define R_SCSI0_CTRL__enable__on 1
-#define R_SCSI0_CTRL__enable__off 0
-
-#define R_SCSI0_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000040)
-#define R_SCSI0_CMD_DATA__parity_in__BITNR 26
-#define R_SCSI0_CMD_DATA__parity_in__WIDTH 1
-#define R_SCSI0_CMD_DATA__parity_in__on 0
-#define R_SCSI0_CMD_DATA__parity_in__off 1
-#define R_SCSI0_CMD_DATA__skip__BITNR 25
-#define R_SCSI0_CMD_DATA__skip__WIDTH 1
-#define R_SCSI0_CMD_DATA__skip__on 1
-#define R_SCSI0_CMD_DATA__skip__off 0
-#define R_SCSI0_CMD_DATA__clr_status__BITNR 24
-#define R_SCSI0_CMD_DATA__clr_status__WIDTH 1
-#define R_SCSI0_CMD_DATA__clr_status__yes 1
-#define R_SCSI0_CMD_DATA__clr_status__nop 0
-#define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20
-#define R_SCSI0_CMD_DATA__asynch_setup__WIDTH 4
-#define R_SCSI0_CMD_DATA__command__BITNR 16
-#define R_SCSI0_CMD_DATA__command__WIDTH 4
-#define R_SCSI0_CMD_DATA__command__full_din_1 0
-#define R_SCSI0_CMD_DATA__command__full_dout_1 1
-#define R_SCSI0_CMD_DATA__command__full_stat_1 2
-#define R_SCSI0_CMD_DATA__command__resel_din 3
-#define R_SCSI0_CMD_DATA__command__resel_dout 4
-#define R_SCSI0_CMD_DATA__command__resel_stat 5
-#define R_SCSI0_CMD_DATA__command__arb_only 6
-#define R_SCSI0_CMD_DATA__command__full_din_3 8
-#define R_SCSI0_CMD_DATA__command__full_dout_3 9
-#define R_SCSI0_CMD_DATA__command__full_stat_3 10
-#define R_SCSI0_CMD_DATA__command__man_data_in 11
-#define R_SCSI0_CMD_DATA__command__man_data_out 12
-#define R_SCSI0_CMD_DATA__command__man_rat 13
-#define R_SCSI0_CMD_DATA__data_out__BITNR 0
-#define R_SCSI0_CMD_DATA__data_out__WIDTH 16
-
-#define R_SCSI0_DATA (IO_TYPECAST_UWORD 0xb0000040)
-#define R_SCSI0_DATA__data_out__BITNR 0
-#define R_SCSI0_DATA__data_out__WIDTH 16
-
-#define R_SCSI0_CMD (IO_TYPECAST_BYTE 0xb0000042)
-#define R_SCSI0_CMD__asynch_setup__BITNR 4
-#define R_SCSI0_CMD__asynch_setup__WIDTH 4
-#define R_SCSI0_CMD__command__BITNR 0
-#define R_SCSI0_CMD__command__WIDTH 4
-#define R_SCSI0_CMD__command__full_din_1 0
-#define R_SCSI0_CMD__command__full_dout_1 1
-#define R_SCSI0_CMD__command__full_stat_1 2
-#define R_SCSI0_CMD__command__resel_din 3
-#define R_SCSI0_CMD__command__resel_dout 4
-#define R_SCSI0_CMD__command__resel_stat 5
-#define R_SCSI0_CMD__command__arb_only 6
-#define R_SCSI0_CMD__command__full_din_3 8
-#define R_SCSI0_CMD__command__full_dout_3 9
-#define R_SCSI0_CMD__command__full_stat_3 10
-#define R_SCSI0_CMD__command__man_data_in 11
-#define R_SCSI0_CMD__command__man_data_out 12
-#define R_SCSI0_CMD__command__man_rat 13
-
-#define R_SCSI0_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000043)
-#define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2
-#define R_SCSI0_STATUS_CTRL__parity_in__WIDTH 1
-#define R_SCSI0_STATUS_CTRL__parity_in__on 0
-#define R_SCSI0_STATUS_CTRL__parity_in__off 1
-#define R_SCSI0_STATUS_CTRL__skip__BITNR 1
-#define R_SCSI0_STATUS_CTRL__skip__WIDTH 1
-#define R_SCSI0_STATUS_CTRL__skip__on 1
-#define R_SCSI0_STATUS_CTRL__skip__off 0
-#define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0
-#define R_SCSI0_STATUS_CTRL__clr_status__WIDTH 1
-#define R_SCSI0_STATUS_CTRL__clr_status__yes 1
-#define R_SCSI0_STATUS_CTRL__clr_status__nop 0
-
-#define R_SCSI0_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000048)
-#define R_SCSI0_STATUS__tst_arb_won__BITNR 23
-#define R_SCSI0_STATUS__tst_arb_won__WIDTH 1
-#define R_SCSI0_STATUS__tst_resel__BITNR 22
-#define R_SCSI0_STATUS__tst_resel__WIDTH 1
-#define R_SCSI0_STATUS__parity_error__BITNR 21
-#define R_SCSI0_STATUS__parity_error__WIDTH 1
-#define R_SCSI0_STATUS__bus_reset__BITNR 20
-#define R_SCSI0_STATUS__bus_reset__WIDTH 1
-#define R_SCSI0_STATUS__bus_reset__yes 1
-#define R_SCSI0_STATUS__bus_reset__no 0
-#define R_SCSI0_STATUS__resel_target__BITNR 15
-#define R_SCSI0_STATUS__resel_target__WIDTH 4
-#define R_SCSI0_STATUS__resel__BITNR 14
-#define R_SCSI0_STATUS__resel__WIDTH 1
-#define R_SCSI0_STATUS__resel__yes 1
-#define R_SCSI0_STATUS__resel__no 0
-#define R_SCSI0_STATUS__curr_phase__BITNR 11
-#define R_SCSI0_STATUS__curr_phase__WIDTH 3
-#define R_SCSI0_STATUS__curr_phase__ph_undef 0
-#define R_SCSI0_STATUS__curr_phase__ph_msg_in 7
-#define R_SCSI0_STATUS__curr_phase__ph_msg_out 6
-#define R_SCSI0_STATUS__curr_phase__ph_status 3
-#define R_SCSI0_STATUS__curr_phase__ph_command 2
-#define R_SCSI0_STATUS__curr_phase__ph_data_in 5
-#define R_SCSI0_STATUS__curr_phase__ph_data_out 4
-#define R_SCSI0_STATUS__curr_phase__ph_resel 1
-#define R_SCSI0_STATUS__last_seq_step__BITNR 6
-#define R_SCSI0_STATUS__last_seq_step__WIDTH 5
-#define R_SCSI0_STATUS__last_seq_step__st_bus_free 24
-#define R_SCSI0_STATUS__last_seq_step__st_arbitrate 8
-#define R_SCSI0_STATUS__last_seq_step__st_resel_req 29
-#define R_SCSI0_STATUS__last_seq_step__st_msg_1 2
-#define R_SCSI0_STATUS__last_seq_step__st_manual 28
-#define R_SCSI0_STATUS__last_seq_step__st_transf_cmd 30
-#define R_SCSI0_STATUS__last_seq_step__st_msg_2 6
-#define R_SCSI0_STATUS__last_seq_step__st_msg_3 22
-#define R_SCSI0_STATUS__last_seq_step__st_answer 3
-#define R_SCSI0_STATUS__last_seq_step__st_synch_din_perr 1
-#define R_SCSI0_STATUS__last_seq_step__st_transfer_done 15
-#define R_SCSI0_STATUS__last_seq_step__st_synch_dout 0
-#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout 25
-#define R_SCSI0_STATUS__last_seq_step__st_synch_din 13
-#define R_SCSI0_STATUS__last_seq_step__st_asynch_din 9
-#define R_SCSI0_STATUS__last_seq_step__st_synch_dout_ack 4
-#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack 12
-#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack_perr 5
-#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout_end 11
-#define R_SCSI0_STATUS__last_seq_step__st_iwr 27
-#define R_SCSI0_STATUS__last_seq_step__st_wait_free_disc 21
-#define R_SCSI0_STATUS__last_seq_step__st_sdp_disc 7
-#define R_SCSI0_STATUS__last_seq_step__st_cc 31
-#define R_SCSI0_STATUS__last_seq_step__st_iwr_good 14
-#define R_SCSI0_STATUS__last_seq_step__st_iwr_cc 23
-#define R_SCSI0_STATUS__last_seq_step__st_wait_free_iwr_cc 17
-#define R_SCSI0_STATUS__last_seq_step__st_wait_free_cc 20
-#define R_SCSI0_STATUS__last_seq_step__st_wait_free_sdp_disc 16
-#define R_SCSI0_STATUS__last_seq_step__st_manual_req 10
-#define R_SCSI0_STATUS__last_seq_step__st_manual_din_prot 18
-#define R_SCSI0_STATUS__valid_status__BITNR 5
-#define R_SCSI0_STATUS__valid_status__WIDTH 1
-#define R_SCSI0_STATUS__valid_status__yes 1
-#define R_SCSI0_STATUS__valid_status__no 0
-#define R_SCSI0_STATUS__seq_status__BITNR 0
-#define R_SCSI0_STATUS__seq_status__WIDTH 5
-#define R_SCSI0_STATUS__seq_status__info_seq_complete 0
-#define R_SCSI0_STATUS__seq_status__info_parity_error 1
-#define R_SCSI0_STATUS__seq_status__info_unhandled_msg_in 2
-#define R_SCSI0_STATUS__seq_status__info_unexp_ph_change 3
-#define R_SCSI0_STATUS__seq_status__info_arb_lost 4
-#define R_SCSI0_STATUS__seq_status__info_sel_timeout 5
-#define R_SCSI0_STATUS__seq_status__info_unexp_bf 6
-#define R_SCSI0_STATUS__seq_status__info_illegal_op 7
-#define R_SCSI0_STATUS__seq_status__info_rec_recvd 8
-#define R_SCSI0_STATUS__seq_status__info_reselected 9
-#define R_SCSI0_STATUS__seq_status__info_unhandled_status 10
-#define R_SCSI0_STATUS__seq_status__info_bus_reset 11
-#define R_SCSI0_STATUS__seq_status__info_illegal_bf 12
-#define R_SCSI0_STATUS__seq_status__info_bus_free 13
-
-#define R_SCSI0_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000040)
-#define R_SCSI0_DATA_IN__data_in__BITNR 0
-#define R_SCSI0_DATA_IN__data_in__WIDTH 16
-
-#define R_SCSI1_CTRL (IO_TYPECAST_UDWORD 0xb0000054)
-#define R_SCSI1_CTRL__id_type__BITNR 31
-#define R_SCSI1_CTRL__id_type__WIDTH 1
-#define R_SCSI1_CTRL__id_type__software 1
-#define R_SCSI1_CTRL__id_type__hardware 0
-#define R_SCSI1_CTRL__sel_timeout__BITNR 24
-#define R_SCSI1_CTRL__sel_timeout__WIDTH 7
-#define R_SCSI1_CTRL__synch_per__BITNR 16
-#define R_SCSI1_CTRL__synch_per__WIDTH 8
-#define R_SCSI1_CTRL__rst__BITNR 15
-#define R_SCSI1_CTRL__rst__WIDTH 1
-#define R_SCSI1_CTRL__rst__yes 1
-#define R_SCSI1_CTRL__rst__no 0
-#define R_SCSI1_CTRL__atn__BITNR 14
-#define R_SCSI1_CTRL__atn__WIDTH 1
-#define R_SCSI1_CTRL__atn__yes 1
-#define R_SCSI1_CTRL__atn__no 0
-#define R_SCSI1_CTRL__my_id__BITNR 9
-#define R_SCSI1_CTRL__my_id__WIDTH 4
-#define R_SCSI1_CTRL__target_id__BITNR 4
-#define R_SCSI1_CTRL__target_id__WIDTH 4
-#define R_SCSI1_CTRL__fast_20__BITNR 3
-#define R_SCSI1_CTRL__fast_20__WIDTH 1
-#define R_SCSI1_CTRL__fast_20__yes 1
-#define R_SCSI1_CTRL__fast_20__no 0
-#define R_SCSI1_CTRL__bus_width__BITNR 2
-#define R_SCSI1_CTRL__bus_width__WIDTH 1
-#define R_SCSI1_CTRL__bus_width__wide 1
-#define R_SCSI1_CTRL__bus_width__narrow 0
-#define R_SCSI1_CTRL__synch__BITNR 1
-#define R_SCSI1_CTRL__synch__WIDTH 1
-#define R_SCSI1_CTRL__synch__synch 1
-#define R_SCSI1_CTRL__synch__asynch 0
-#define R_SCSI1_CTRL__enable__BITNR 0
-#define R_SCSI1_CTRL__enable__WIDTH 1
-#define R_SCSI1_CTRL__enable__on 1
-#define R_SCSI1_CTRL__enable__off 0
-
-#define R_SCSI1_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000050)
-#define R_SCSI1_CMD_DATA__parity_in__BITNR 26
-#define R_SCSI1_CMD_DATA__parity_in__WIDTH 1
-#define R_SCSI1_CMD_DATA__parity_in__on 0
-#define R_SCSI1_CMD_DATA__parity_in__off 1
-#define R_SCSI1_CMD_DATA__skip__BITNR 25
-#define R_SCSI1_CMD_DATA__skip__WIDTH 1
-#define R_SCSI1_CMD_DATA__skip__on 1
-#define R_SCSI1_CMD_DATA__skip__off 0
-#define R_SCSI1_CMD_DATA__clr_status__BITNR 24
-#define R_SCSI1_CMD_DATA__clr_status__WIDTH 1
-#define R_SCSI1_CMD_DATA__clr_status__yes 1
-#define R_SCSI1_CMD_DATA__clr_status__nop 0
-#define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20
-#define R_SCSI1_CMD_DATA__asynch_setup__WIDTH 4
-#define R_SCSI1_CMD_DATA__command__BITNR 16
-#define R_SCSI1_CMD_DATA__command__WIDTH 4
-#define R_SCSI1_CMD_DATA__command__full_din_1 0
-#define R_SCSI1_CMD_DATA__command__full_dout_1 1
-#define R_SCSI1_CMD_DATA__command__full_stat_1 2
-#define R_SCSI1_CMD_DATA__command__resel_din 3
-#define R_SCSI1_CMD_DATA__command__resel_dout 4
-#define R_SCSI1_CMD_DATA__command__resel_stat 5
-#define R_SCSI1_CMD_DATA__command__arb_only 6
-#define R_SCSI1_CMD_DATA__command__full_din_3 8
-#define R_SCSI1_CMD_DATA__command__full_dout_3 9
-#define R_SCSI1_CMD_DATA__command__full_stat_3 10
-#define R_SCSI1_CMD_DATA__command__man_data_in 11
-#define R_SCSI1_CMD_DATA__command__man_data_out 12
-#define R_SCSI1_CMD_DATA__command__man_rat 13
-#define R_SCSI1_CMD_DATA__data_out__BITNR 0
-#define R_SCSI1_CMD_DATA__data_out__WIDTH 16
-
-#define R_SCSI1_DATA (IO_TYPECAST_UWORD 0xb0000050)
-#define R_SCSI1_DATA__data_out__BITNR 0
-#define R_SCSI1_DATA__data_out__WIDTH 16
-
-#define R_SCSI1_CMD (IO_TYPECAST_BYTE 0xb0000052)
-#define R_SCSI1_CMD__asynch_setup__BITNR 4
-#define R_SCSI1_CMD__asynch_setup__WIDTH 4
-#define R_SCSI1_CMD__command__BITNR 0
-#define R_SCSI1_CMD__command__WIDTH 4
-#define R_SCSI1_CMD__command__full_din_1 0
-#define R_SCSI1_CMD__command__full_dout_1 1
-#define R_SCSI1_CMD__command__full_stat_1 2
-#define R_SCSI1_CMD__command__resel_din 3
-#define R_SCSI1_CMD__command__resel_dout 4
-#define R_SCSI1_CMD__command__resel_stat 5
-#define R_SCSI1_CMD__command__arb_only 6
-#define R_SCSI1_CMD__command__full_din_3 8
-#define R_SCSI1_CMD__command__full_dout_3 9
-#define R_SCSI1_CMD__command__full_stat_3 10
-#define R_SCSI1_CMD__command__man_data_in 11
-#define R_SCSI1_CMD__command__man_data_out 12
-#define R_SCSI1_CMD__command__man_rat 13
-
-#define R_SCSI1_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000053)
-#define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2
-#define R_SCSI1_STATUS_CTRL__parity_in__WIDTH 1
-#define R_SCSI1_STATUS_CTRL__parity_in__on 0
-#define R_SCSI1_STATUS_CTRL__parity_in__off 1
-#define R_SCSI1_STATUS_CTRL__skip__BITNR 1
-#define R_SCSI1_STATUS_CTRL__skip__WIDTH 1
-#define R_SCSI1_STATUS_CTRL__skip__on 1
-#define R_SCSI1_STATUS_CTRL__skip__off 0
-#define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0
-#define R_SCSI1_STATUS_CTRL__clr_status__WIDTH 1
-#define R_SCSI1_STATUS_CTRL__clr_status__yes 1
-#define R_SCSI1_STATUS_CTRL__clr_status__nop 0
-
-#define R_SCSI1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000058)
-#define R_SCSI1_STATUS__tst_arb_won__BITNR 23
-#define R_SCSI1_STATUS__tst_arb_won__WIDTH 1
-#define R_SCSI1_STATUS__tst_resel__BITNR 22
-#define R_SCSI1_STATUS__tst_resel__WIDTH 1
-#define R_SCSI1_STATUS__parity_error__BITNR 21
-#define R_SCSI1_STATUS__parity_error__WIDTH 1
-#define R_SCSI1_STATUS__bus_reset__BITNR 20
-#define R_SCSI1_STATUS__bus_reset__WIDTH 1
-#define R_SCSI1_STATUS__bus_reset__yes 1
-#define R_SCSI1_STATUS__bus_reset__no 0
-#define R_SCSI1_STATUS__resel_target__BITNR 15
-#define R_SCSI1_STATUS__resel_target__WIDTH 4
-#define R_SCSI1_STATUS__resel__BITNR 14
-#define R_SCSI1_STATUS__resel__WIDTH 1
-#define R_SCSI1_STATUS__resel__yes 1
-#define R_SCSI1_STATUS__resel__no 0
-#define R_SCSI1_STATUS__curr_phase__BITNR 11
-#define R_SCSI1_STATUS__curr_phase__WIDTH 3
-#define R_SCSI1_STATUS__curr_phase__ph_undef 0
-#define R_SCSI1_STATUS__curr_phase__ph_msg_in 7
-#define R_SCSI1_STATUS__curr_phase__ph_msg_out 6
-#define R_SCSI1_STATUS__curr_phase__ph_status 3
-#define R_SCSI1_STATUS__curr_phase__ph_command 2
-#define R_SCSI1_STATUS__curr_phase__ph_data_in 5
-#define R_SCSI1_STATUS__curr_phase__ph_data_out 4
-#define R_SCSI1_STATUS__curr_phase__ph_resel 1
-#define R_SCSI1_STATUS__last_seq_step__BITNR 6
-#define R_SCSI1_STATUS__last_seq_step__WIDTH 5
-#define R_SCSI1_STATUS__last_seq_step__st_bus_free 24
-#define R_SCSI1_STATUS__last_seq_step__st_arbitrate 8
-#define R_SCSI1_STATUS__last_seq_step__st_resel_req 29
-#define R_SCSI1_STATUS__last_seq_step__st_msg_1 2
-#define R_SCSI1_STATUS__last_seq_step__st_manual 28
-#define R_SCSI1_STATUS__last_seq_step__st_transf_cmd 30
-#define R_SCSI1_STATUS__last_seq_step__st_msg_2 6
-#define R_SCSI1_STATUS__last_seq_step__st_msg_3 22
-#define R_SCSI1_STATUS__last_seq_step__st_answer 3
-#define R_SCSI1_STATUS__last_seq_step__st_synch_din_perr 1
-#define R_SCSI1_STATUS__last_seq_step__st_transfer_done 15
-#define R_SCSI1_STATUS__last_seq_step__st_synch_dout 0
-#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout 25
-#define R_SCSI1_STATUS__last_seq_step__st_synch_din 13
-#define R_SCSI1_STATUS__last_seq_step__st_asynch_din 9
-#define R_SCSI1_STATUS__last_seq_step__st_synch_dout_ack 4
-#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack 12
-#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack_perr 5
-#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout_end 11
-#define R_SCSI1_STATUS__last_seq_step__st_iwr 27
-#define R_SCSI1_STATUS__last_seq_step__st_wait_free_disc 21
-#define R_SCSI1_STATUS__last_seq_step__st_sdp_disc 7
-#define R_SCSI1_STATUS__last_seq_step__st_cc 31
-#define R_SCSI1_STATUS__last_seq_step__st_iwr_good 14
-#define R_SCSI1_STATUS__last_seq_step__st_iwr_cc 23
-#define R_SCSI1_STATUS__last_seq_step__st_wait_free_iwr_cc 17
-#define R_SCSI1_STATUS__last_seq_step__st_wait_free_cc 20
-#define R_SCSI1_STATUS__last_seq_step__st_wait_free_sdp_disc 16
-#define R_SCSI1_STATUS__last_seq_step__st_manual_req 10
-#define R_SCSI1_STATUS__last_seq_step__st_manual_din_prot 18
-#define R_SCSI1_STATUS__valid_status__BITNR 5
-#define R_SCSI1_STATUS__valid_status__WIDTH 1
-#define R_SCSI1_STATUS__valid_status__yes 1
-#define R_SCSI1_STATUS__valid_status__no 0
-#define R_SCSI1_STATUS__seq_status__BITNR 0
-#define R_SCSI1_STATUS__seq_status__WIDTH 5
-#define R_SCSI1_STATUS__seq_status__info_seq_complete 0
-#define R_SCSI1_STATUS__seq_status__info_parity_error 1
-#define R_SCSI1_STATUS__seq_status__info_unhandled_msg_in 2
-#define R_SCSI1_STATUS__seq_status__info_unexp_ph_change 3
-#define R_SCSI1_STATUS__seq_status__info_arb_lost 4
-#define R_SCSI1_STATUS__seq_status__info_sel_timeout 5
-#define R_SCSI1_STATUS__seq_status__info_unexp_bf 6
-#define R_SCSI1_STATUS__seq_status__info_illegal_op 7
-#define R_SCSI1_STATUS__seq_status__info_rec_recvd 8
-#define R_SCSI1_STATUS__seq_status__info_reselected 9
-#define R_SCSI1_STATUS__seq_status__info_unhandled_status 10
-#define R_SCSI1_STATUS__seq_status__info_bus_reset 11
-#define R_SCSI1_STATUS__seq_status__info_illegal_bf 12
-#define R_SCSI1_STATUS__seq_status__info_bus_free 13
-
-#define R_SCSI1_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000050)
-#define R_SCSI1_DATA_IN__data_in__BITNR 0
-#define R_SCSI1_DATA_IN__data_in__WIDTH 16
-
-/*
-!* Interrupt mask and status registers
-!*/
-
-#define R_IRQ_MASK0_RD (IO_TYPECAST_RO_UDWORD 0xb00000c0)
-#define R_IRQ_MASK0_RD__nmi_pin__BITNR 31
-#define R_IRQ_MASK0_RD__nmi_pin__WIDTH 1
-#define R_IRQ_MASK0_RD__nmi_pin__active 1
-#define R_IRQ_MASK0_RD__nmi_pin__inactive 0
-#define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30
-#define R_IRQ_MASK0_RD__watchdog_nmi__WIDTH 1
-#define R_IRQ_MASK0_RD__watchdog_nmi__active 1
-#define R_IRQ_MASK0_RD__watchdog_nmi__inactive 0
-#define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29
-#define R_IRQ_MASK0_RD__sqe_test_error__WIDTH 1
-#define R_IRQ_MASK0_RD__sqe_test_error__active 1
-#define R_IRQ_MASK0_RD__sqe_test_error__inactive 0
-#define R_IRQ_MASK0_RD__carrier_loss__BITNR 28
-#define R_IRQ_MASK0_RD__carrier_loss__WIDTH 1
-#define R_IRQ_MASK0_RD__carrier_loss__active 1
-#define R_IRQ_MASK0_RD__carrier_loss__inactive 0
-#define R_IRQ_MASK0_RD__deferred__BITNR 27
-#define R_IRQ_MASK0_RD__deferred__WIDTH 1
-#define R_IRQ_MASK0_RD__deferred__active 1
-#define R_IRQ_MASK0_RD__deferred__inactive 0
-#define R_IRQ_MASK0_RD__late_col__BITNR 26
-#define R_IRQ_MASK0_RD__late_col__WIDTH 1
-#define R_IRQ_MASK0_RD__late_col__active 1
-#define R_IRQ_MASK0_RD__late_col__inactive 0
-#define R_IRQ_MASK0_RD__multiple_col__BITNR 25
-#define R_IRQ_MASK0_RD__multiple_col__WIDTH 1
-#define R_IRQ_MASK0_RD__multiple_col__active 1
-#define R_IRQ_MASK0_RD__multiple_col__inactive 0
-#define R_IRQ_MASK0_RD__single_col__BITNR 24
-#define R_IRQ_MASK0_RD__single_col__WIDTH 1
-#define R_IRQ_MASK0_RD__single_col__active 1
-#define R_IRQ_MASK0_RD__single_col__inactive 0
-#define R_IRQ_MASK0_RD__congestion__BITNR 23
-#define R_IRQ_MASK0_RD__congestion__WIDTH 1
-#define R_IRQ_MASK0_RD__congestion__active 1
-#define R_IRQ_MASK0_RD__congestion__inactive 0
-#define R_IRQ_MASK0_RD__oversize__BITNR 22
-#define R_IRQ_MASK0_RD__oversize__WIDTH 1
-#define R_IRQ_MASK0_RD__oversize__active 1
-#define R_IRQ_MASK0_RD__oversize__inactive 0
-#define R_IRQ_MASK0_RD__alignment_error__BITNR 21
-#define R_IRQ_MASK0_RD__alignment_error__WIDTH 1
-#define R_IRQ_MASK0_RD__alignment_error__active 1
-#define R_IRQ_MASK0_RD__alignment_error__inactive 0
-#define R_IRQ_MASK0_RD__crc_error__BITNR 20
-#define R_IRQ_MASK0_RD__crc_error__WIDTH 1
-#define R_IRQ_MASK0_RD__crc_error__active 1
-#define R_IRQ_MASK0_RD__crc_error__inactive 0
-#define R_IRQ_MASK0_RD__overrun__BITNR 19
-#define R_IRQ_MASK0_RD__overrun__WIDTH 1
-#define R_IRQ_MASK0_RD__overrun__active 1
-#define R_IRQ_MASK0_RD__overrun__inactive 0
-#define R_IRQ_MASK0_RD__underrun__BITNR 18
-#define R_IRQ_MASK0_RD__underrun__WIDTH 1
-#define R_IRQ_MASK0_RD__underrun__active 1
-#define R_IRQ_MASK0_RD__underrun__inactive 0
-#define R_IRQ_MASK0_RD__excessive_col__BITNR 17
-#define R_IRQ_MASK0_RD__excessive_col__WIDTH 1
-#define R_IRQ_MASK0_RD__excessive_col__active 1
-#define R_IRQ_MASK0_RD__excessive_col__inactive 0
-#define R_IRQ_MASK0_RD__mdio__BITNR 16
-#define R_IRQ_MASK0_RD__mdio__WIDTH 1
-#define R_IRQ_MASK0_RD__mdio__active 1
-#define R_IRQ_MASK0_RD__mdio__inactive 0
-#define R_IRQ_MASK0_RD__ata_drq3__BITNR 15
-#define R_IRQ_MASK0_RD__ata_drq3__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_drq3__active 1
-#define R_IRQ_MASK0_RD__ata_drq3__inactive 0
-#define R_IRQ_MASK0_RD__ata_drq2__BITNR 14
-#define R_IRQ_MASK0_RD__ata_drq2__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_drq2__active 1
-#define R_IRQ_MASK0_RD__ata_drq2__inactive 0
-#define R_IRQ_MASK0_RD__ata_drq1__BITNR 13
-#define R_IRQ_MASK0_RD__ata_drq1__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_drq1__active 1
-#define R_IRQ_MASK0_RD__ata_drq1__inactive 0
-#define R_IRQ_MASK0_RD__ata_drq0__BITNR 12
-#define R_IRQ_MASK0_RD__ata_drq0__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_drq0__active 1
-#define R_IRQ_MASK0_RD__ata_drq0__inactive 0
-#define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11
-#define R_IRQ_MASK0_RD__par0_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK0_RD__par0_ecp_cmd__active 1
-#define R_IRQ_MASK0_RD__par0_ecp_cmd__inactive 0
-#define R_IRQ_MASK0_RD__ata_irq3__BITNR 11
-#define R_IRQ_MASK0_RD__ata_irq3__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_irq3__active 1
-#define R_IRQ_MASK0_RD__ata_irq3__inactive 0
-#define R_IRQ_MASK0_RD__par0_peri__BITNR 10
-#define R_IRQ_MASK0_RD__par0_peri__WIDTH 1
-#define R_IRQ_MASK0_RD__par0_peri__active 1
-#define R_IRQ_MASK0_RD__par0_peri__inactive 0
-#define R_IRQ_MASK0_RD__ata_irq2__BITNR 10
-#define R_IRQ_MASK0_RD__ata_irq2__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_irq2__active 1
-#define R_IRQ_MASK0_RD__ata_irq2__inactive 0
-#define R_IRQ_MASK0_RD__par0_data__BITNR 9
-#define R_IRQ_MASK0_RD__par0_data__WIDTH 1
-#define R_IRQ_MASK0_RD__par0_data__active 1
-#define R_IRQ_MASK0_RD__par0_data__inactive 0
-#define R_IRQ_MASK0_RD__ata_irq1__BITNR 9
-#define R_IRQ_MASK0_RD__ata_irq1__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_irq1__active 1
-#define R_IRQ_MASK0_RD__ata_irq1__inactive 0
-#define R_IRQ_MASK0_RD__par0_ready__BITNR 8
-#define R_IRQ_MASK0_RD__par0_ready__WIDTH 1
-#define R_IRQ_MASK0_RD__par0_ready__active 1
-#define R_IRQ_MASK0_RD__par0_ready__inactive 0
-#define R_IRQ_MASK0_RD__ata_irq0__BITNR 8
-#define R_IRQ_MASK0_RD__ata_irq0__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_irq0__active 1
-#define R_IRQ_MASK0_RD__ata_irq0__inactive 0
-#define R_IRQ_MASK0_RD__mio__BITNR 8
-#define R_IRQ_MASK0_RD__mio__WIDTH 1
-#define R_IRQ_MASK0_RD__mio__active 1
-#define R_IRQ_MASK0_RD__mio__inactive 0
-#define R_IRQ_MASK0_RD__scsi0__BITNR 8
-#define R_IRQ_MASK0_RD__scsi0__WIDTH 1
-#define R_IRQ_MASK0_RD__scsi0__active 1
-#define R_IRQ_MASK0_RD__scsi0__inactive 0
-#define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7
-#define R_IRQ_MASK0_RD__ata_dmaend__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_dmaend__active 1
-#define R_IRQ_MASK0_RD__ata_dmaend__inactive 0
-#define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5
-#define R_IRQ_MASK0_RD__irq_ext_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_RD__irq_ext_vector_nr__active 1
-#define R_IRQ_MASK0_RD__irq_ext_vector_nr__inactive 0
-#define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4
-#define R_IRQ_MASK0_RD__irq_int_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_RD__irq_int_vector_nr__active 1
-#define R_IRQ_MASK0_RD__irq_int_vector_nr__inactive 0
-#define R_IRQ_MASK0_RD__ext_dma1__BITNR 3
-#define R_IRQ_MASK0_RD__ext_dma1__WIDTH 1
-#define R_IRQ_MASK0_RD__ext_dma1__active 1
-#define R_IRQ_MASK0_RD__ext_dma1__inactive 0
-#define R_IRQ_MASK0_RD__ext_dma0__BITNR 2
-#define R_IRQ_MASK0_RD__ext_dma0__WIDTH 1
-#define R_IRQ_MASK0_RD__ext_dma0__active 1
-#define R_IRQ_MASK0_RD__ext_dma0__inactive 0
-#define R_IRQ_MASK0_RD__timer1__BITNR 1
-#define R_IRQ_MASK0_RD__timer1__WIDTH 1
-#define R_IRQ_MASK0_RD__timer1__active 1
-#define R_IRQ_MASK0_RD__timer1__inactive 0
-#define R_IRQ_MASK0_RD__timer0__BITNR 0
-#define R_IRQ_MASK0_RD__timer0__WIDTH 1
-#define R_IRQ_MASK0_RD__timer0__active 1
-#define R_IRQ_MASK0_RD__timer0__inactive 0
-
-#define R_IRQ_MASK0_CLR (IO_TYPECAST_UDWORD 0xb00000c0)
-#define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31
-#define R_IRQ_MASK0_CLR__nmi_pin__WIDTH 1
-#define R_IRQ_MASK0_CLR__nmi_pin__clr 1
-#define R_IRQ_MASK0_CLR__nmi_pin__nop 0
-#define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30
-#define R_IRQ_MASK0_CLR__watchdog_nmi__WIDTH 1
-#define R_IRQ_MASK0_CLR__watchdog_nmi__clr 1
-#define R_IRQ_MASK0_CLR__watchdog_nmi__nop 0
-#define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29
-#define R_IRQ_MASK0_CLR__sqe_test_error__WIDTH 1
-#define R_IRQ_MASK0_CLR__sqe_test_error__clr 1
-#define R_IRQ_MASK0_CLR__sqe_test_error__nop 0
-#define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28
-#define R_IRQ_MASK0_CLR__carrier_loss__WIDTH 1
-#define R_IRQ_MASK0_CLR__carrier_loss__clr 1
-#define R_IRQ_MASK0_CLR__carrier_loss__nop 0
-#define R_IRQ_MASK0_CLR__deferred__BITNR 27
-#define R_IRQ_MASK0_CLR__deferred__WIDTH 1
-#define R_IRQ_MASK0_CLR__deferred__clr 1
-#define R_IRQ_MASK0_CLR__deferred__nop 0
-#define R_IRQ_MASK0_CLR__late_col__BITNR 26
-#define R_IRQ_MASK0_CLR__late_col__WIDTH 1
-#define R_IRQ_MASK0_CLR__late_col__clr 1
-#define R_IRQ_MASK0_CLR__late_col__nop 0
-#define R_IRQ_MASK0_CLR__multiple_col__BITNR 25
-#define R_IRQ_MASK0_CLR__multiple_col__WIDTH 1
-#define R_IRQ_MASK0_CLR__multiple_col__clr 1
-#define R_IRQ_MASK0_CLR__multiple_col__nop 0
-#define R_IRQ_MASK0_CLR__single_col__BITNR 24
-#define R_IRQ_MASK0_CLR__single_col__WIDTH 1
-#define R_IRQ_MASK0_CLR__single_col__clr 1
-#define R_IRQ_MASK0_CLR__single_col__nop 0
-#define R_IRQ_MASK0_CLR__congestion__BITNR 23
-#define R_IRQ_MASK0_CLR__congestion__WIDTH 1
-#define R_IRQ_MASK0_CLR__congestion__clr 1
-#define R_IRQ_MASK0_CLR__congestion__nop 0
-#define R_IRQ_MASK0_CLR__oversize__BITNR 22
-#define R_IRQ_MASK0_CLR__oversize__WIDTH 1
-#define R_IRQ_MASK0_CLR__oversize__clr 1
-#define R_IRQ_MASK0_CLR__oversize__nop 0
-#define R_IRQ_MASK0_CLR__alignment_error__BITNR 21
-#define R_IRQ_MASK0_CLR__alignment_error__WIDTH 1
-#define R_IRQ_MASK0_CLR__alignment_error__clr 1
-#define R_IRQ_MASK0_CLR__alignment_error__nop 0
-#define R_IRQ_MASK0_CLR__crc_error__BITNR 20
-#define R_IRQ_MASK0_CLR__crc_error__WIDTH 1
-#define R_IRQ_MASK0_CLR__crc_error__clr 1
-#define R_IRQ_MASK0_CLR__crc_error__nop 0
-#define R_IRQ_MASK0_CLR__overrun__BITNR 19
-#define R_IRQ_MASK0_CLR__overrun__WIDTH 1
-#define R_IRQ_MASK0_CLR__overrun__clr 1
-#define R_IRQ_MASK0_CLR__overrun__nop 0
-#define R_IRQ_MASK0_CLR__underrun__BITNR 18
-#define R_IRQ_MASK0_CLR__underrun__WIDTH 1
-#define R_IRQ_MASK0_CLR__underrun__clr 1
-#define R_IRQ_MASK0_CLR__underrun__nop 0
-#define R_IRQ_MASK0_CLR__excessive_col__BITNR 17
-#define R_IRQ_MASK0_CLR__excessive_col__WIDTH 1
-#define R_IRQ_MASK0_CLR__excessive_col__clr 1
-#define R_IRQ_MASK0_CLR__excessive_col__nop 0
-#define R_IRQ_MASK0_CLR__mdio__BITNR 16
-#define R_IRQ_MASK0_CLR__mdio__WIDTH 1
-#define R_IRQ_MASK0_CLR__mdio__clr 1
-#define R_IRQ_MASK0_CLR__mdio__nop 0
-#define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15
-#define R_IRQ_MASK0_CLR__ata_drq3__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_drq3__clr 1
-#define R_IRQ_MASK0_CLR__ata_drq3__nop 0
-#define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14
-#define R_IRQ_MASK0_CLR__ata_drq2__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_drq2__clr 1
-#define R_IRQ_MASK0_CLR__ata_drq2__nop 0
-#define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13
-#define R_IRQ_MASK0_CLR__ata_drq1__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_drq1__clr 1
-#define R_IRQ_MASK0_CLR__ata_drq1__nop 0
-#define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12
-#define R_IRQ_MASK0_CLR__ata_drq0__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_drq0__clr 1
-#define R_IRQ_MASK0_CLR__ata_drq0__nop 0
-#define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11
-#define R_IRQ_MASK0_CLR__par0_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK0_CLR__par0_ecp_cmd__clr 1
-#define R_IRQ_MASK0_CLR__par0_ecp_cmd__nop 0
-#define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11
-#define R_IRQ_MASK0_CLR__ata_irq3__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_irq3__clr 1
-#define R_IRQ_MASK0_CLR__ata_irq3__nop 0
-#define R_IRQ_MASK0_CLR__par0_peri__BITNR 10
-#define R_IRQ_MASK0_CLR__par0_peri__WIDTH 1
-#define R_IRQ_MASK0_CLR__par0_peri__clr 1
-#define R_IRQ_MASK0_CLR__par0_peri__nop 0
-#define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10
-#define R_IRQ_MASK0_CLR__ata_irq2__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_irq2__clr 1
-#define R_IRQ_MASK0_CLR__ata_irq2__nop 0
-#define R_IRQ_MASK0_CLR__par0_data__BITNR 9
-#define R_IRQ_MASK0_CLR__par0_data__WIDTH 1
-#define R_IRQ_MASK0_CLR__par0_data__clr 1
-#define R_IRQ_MASK0_CLR__par0_data__nop 0
-#define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9
-#define R_IRQ_MASK0_CLR__ata_irq1__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_irq1__clr 1
-#define R_IRQ_MASK0_CLR__ata_irq1__nop 0
-#define R_IRQ_MASK0_CLR__par0_ready__BITNR 8
-#define R_IRQ_MASK0_CLR__par0_ready__WIDTH 1
-#define R_IRQ_MASK0_CLR__par0_ready__clr 1
-#define R_IRQ_MASK0_CLR__par0_ready__nop 0
-#define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8
-#define R_IRQ_MASK0_CLR__ata_irq0__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_irq0__clr 1
-#define R_IRQ_MASK0_CLR__ata_irq0__nop 0
-#define R_IRQ_MASK0_CLR__mio__BITNR 8
-#define R_IRQ_MASK0_CLR__mio__WIDTH 1
-#define R_IRQ_MASK0_CLR__mio__clr 1
-#define R_IRQ_MASK0_CLR__mio__nop 0
-#define R_IRQ_MASK0_CLR__scsi0__BITNR 8
-#define R_IRQ_MASK0_CLR__scsi0__WIDTH 1
-#define R_IRQ_MASK0_CLR__scsi0__clr 1
-#define R_IRQ_MASK0_CLR__scsi0__nop 0
-#define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7
-#define R_IRQ_MASK0_CLR__ata_dmaend__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_dmaend__clr 1
-#define R_IRQ_MASK0_CLR__ata_dmaend__nop 0
-#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5
-#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__clr 1
-#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__nop 0
-#define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4
-#define R_IRQ_MASK0_CLR__irq_int_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_CLR__irq_int_vector_nr__clr 1
-#define R_IRQ_MASK0_CLR__irq_int_vector_nr__nop 0
-#define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3
-#define R_IRQ_MASK0_CLR__ext_dma1__WIDTH 1
-#define R_IRQ_MASK0_CLR__ext_dma1__clr 1
-#define R_IRQ_MASK0_CLR__ext_dma1__nop 0
-#define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2
-#define R_IRQ_MASK0_CLR__ext_dma0__WIDTH 1
-#define R_IRQ_MASK0_CLR__ext_dma0__clr 1
-#define R_IRQ_MASK0_CLR__ext_dma0__nop 0
-#define R_IRQ_MASK0_CLR__timer1__BITNR 1
-#define R_IRQ_MASK0_CLR__timer1__WIDTH 1
-#define R_IRQ_MASK0_CLR__timer1__clr 1
-#define R_IRQ_MASK0_CLR__timer1__nop 0
-#define R_IRQ_MASK0_CLR__timer0__BITNR 0
-#define R_IRQ_MASK0_CLR__timer0__WIDTH 1
-#define R_IRQ_MASK0_CLR__timer0__clr 1
-#define R_IRQ_MASK0_CLR__timer0__nop 0
-
-#define R_IRQ_READ0 (IO_TYPECAST_RO_UDWORD 0xb00000c4)
-#define R_IRQ_READ0__nmi_pin__BITNR 31
-#define R_IRQ_READ0__nmi_pin__WIDTH 1
-#define R_IRQ_READ0__nmi_pin__active 1
-#define R_IRQ_READ0__nmi_pin__inactive 0
-#define R_IRQ_READ0__watchdog_nmi__BITNR 30
-#define R_IRQ_READ0__watchdog_nmi__WIDTH 1
-#define R_IRQ_READ0__watchdog_nmi__active 1
-#define R_IRQ_READ0__watchdog_nmi__inactive 0
-#define R_IRQ_READ0__sqe_test_error__BITNR 29
-#define R_IRQ_READ0__sqe_test_error__WIDTH 1
-#define R_IRQ_READ0__sqe_test_error__active 1
-#define R_IRQ_READ0__sqe_test_error__inactive 0
-#define R_IRQ_READ0__carrier_loss__BITNR 28
-#define R_IRQ_READ0__carrier_loss__WIDTH 1
-#define R_IRQ_READ0__carrier_loss__active 1
-#define R_IRQ_READ0__carrier_loss__inactive 0
-#define R_IRQ_READ0__deferred__BITNR 27
-#define R_IRQ_READ0__deferred__WIDTH 1
-#define R_IRQ_READ0__deferred__active 1
-#define R_IRQ_READ0__deferred__inactive 0
-#define R_IRQ_READ0__late_col__BITNR 26
-#define R_IRQ_READ0__late_col__WIDTH 1
-#define R_IRQ_READ0__late_col__active 1
-#define R_IRQ_READ0__late_col__inactive 0
-#define R_IRQ_READ0__multiple_col__BITNR 25
-#define R_IRQ_READ0__multiple_col__WIDTH 1
-#define R_IRQ_READ0__multiple_col__active 1
-#define R_IRQ_READ0__multiple_col__inactive 0
-#define R_IRQ_READ0__single_col__BITNR 24
-#define R_IRQ_READ0__single_col__WIDTH 1
-#define R_IRQ_READ0__single_col__active 1
-#define R_IRQ_READ0__single_col__inactive 0
-#define R_IRQ_READ0__congestion__BITNR 23
-#define R_IRQ_READ0__congestion__WIDTH 1
-#define R_IRQ_READ0__congestion__active 1
-#define R_IRQ_READ0__congestion__inactive 0
-#define R_IRQ_READ0__oversize__BITNR 22
-#define R_IRQ_READ0__oversize__WIDTH 1
-#define R_IRQ_READ0__oversize__active 1
-#define R_IRQ_READ0__oversize__inactive 0
-#define R_IRQ_READ0__alignment_error__BITNR 21
-#define R_IRQ_READ0__alignment_error__WIDTH 1
-#define R_IRQ_READ0__alignment_error__active 1
-#define R_IRQ_READ0__alignment_error__inactive 0
-#define R_IRQ_READ0__crc_error__BITNR 20
-#define R_IRQ_READ0__crc_error__WIDTH 1
-#define R_IRQ_READ0__crc_error__active 1
-#define R_IRQ_READ0__crc_error__inactive 0
-#define R_IRQ_READ0__overrun__BITNR 19
-#define R_IRQ_READ0__overrun__WIDTH 1
-#define R_IRQ_READ0__overrun__active 1
-#define R_IRQ_READ0__overrun__inactive 0
-#define R_IRQ_READ0__underrun__BITNR 18
-#define R_IRQ_READ0__underrun__WIDTH 1
-#define R_IRQ_READ0__underrun__active 1
-#define R_IRQ_READ0__underrun__inactive 0
-#define R_IRQ_READ0__excessive_col__BITNR 17
-#define R_IRQ_READ0__excessive_col__WIDTH 1
-#define R_IRQ_READ0__excessive_col__active 1
-#define R_IRQ_READ0__excessive_col__inactive 0
-#define R_IRQ_READ0__mdio__BITNR 16
-#define R_IRQ_READ0__mdio__WIDTH 1
-#define R_IRQ_READ0__mdio__active 1
-#define R_IRQ_READ0__mdio__inactive 0
-#define R_IRQ_READ0__ata_drq3__BITNR 15
-#define R_IRQ_READ0__ata_drq3__WIDTH 1
-#define R_IRQ_READ0__ata_drq3__active 1
-#define R_IRQ_READ0__ata_drq3__inactive 0
-#define R_IRQ_READ0__ata_drq2__BITNR 14
-#define R_IRQ_READ0__ata_drq2__WIDTH 1
-#define R_IRQ_READ0__ata_drq2__active 1
-#define R_IRQ_READ0__ata_drq2__inactive 0
-#define R_IRQ_READ0__ata_drq1__BITNR 13
-#define R_IRQ_READ0__ata_drq1__WIDTH 1
-#define R_IRQ_READ0__ata_drq1__active 1
-#define R_IRQ_READ0__ata_drq1__inactive 0
-#define R_IRQ_READ0__ata_drq0__BITNR 12
-#define R_IRQ_READ0__ata_drq0__WIDTH 1
-#define R_IRQ_READ0__ata_drq0__active 1
-#define R_IRQ_READ0__ata_drq0__inactive 0
-#define R_IRQ_READ0__par0_ecp_cmd__BITNR 11
-#define R_IRQ_READ0__par0_ecp_cmd__WIDTH 1
-#define R_IRQ_READ0__par0_ecp_cmd__active 1
-#define R_IRQ_READ0__par0_ecp_cmd__inactive 0
-#define R_IRQ_READ0__ata_irq3__BITNR 11
-#define R_IRQ_READ0__ata_irq3__WIDTH 1
-#define R_IRQ_READ0__ata_irq3__active 1
-#define R_IRQ_READ0__ata_irq3__inactive 0
-#define R_IRQ_READ0__par0_peri__BITNR 10
-#define R_IRQ_READ0__par0_peri__WIDTH 1
-#define R_IRQ_READ0__par0_peri__active 1
-#define R_IRQ_READ0__par0_peri__inactive 0
-#define R_IRQ_READ0__ata_irq2__BITNR 10
-#define R_IRQ_READ0__ata_irq2__WIDTH 1
-#define R_IRQ_READ0__ata_irq2__active 1
-#define R_IRQ_READ0__ata_irq2__inactive 0
-#define R_IRQ_READ0__par0_data__BITNR 9
-#define R_IRQ_READ0__par0_data__WIDTH 1
-#define R_IRQ_READ0__par0_data__active 1
-#define R_IRQ_READ0__par0_data__inactive 0
-#define R_IRQ_READ0__ata_irq1__BITNR 9
-#define R_IRQ_READ0__ata_irq1__WIDTH 1
-#define R_IRQ_READ0__ata_irq1__active 1
-#define R_IRQ_READ0__ata_irq1__inactive 0
-#define R_IRQ_READ0__par0_ready__BITNR 8
-#define R_IRQ_READ0__par0_ready__WIDTH 1
-#define R_IRQ_READ0__par0_ready__active 1
-#define R_IRQ_READ0__par0_ready__inactive 0
-#define R_IRQ_READ0__ata_irq0__BITNR 8
-#define R_IRQ_READ0__ata_irq0__WIDTH 1
-#define R_IRQ_READ0__ata_irq0__active 1
-#define R_IRQ_READ0__ata_irq0__inactive 0
-#define R_IRQ_READ0__mio__BITNR 8
-#define R_IRQ_READ0__mio__WIDTH 1
-#define R_IRQ_READ0__mio__active 1
-#define R_IRQ_READ0__mio__inactive 0
-#define R_IRQ_READ0__scsi0__BITNR 8
-#define R_IRQ_READ0__scsi0__WIDTH 1
-#define R_IRQ_READ0__scsi0__active 1
-#define R_IRQ_READ0__scsi0__inactive 0
-#define R_IRQ_READ0__ata_dmaend__BITNR 7
-#define R_IRQ_READ0__ata_dmaend__WIDTH 1
-#define R_IRQ_READ0__ata_dmaend__active 1
-#define R_IRQ_READ0__ata_dmaend__inactive 0
-#define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5
-#define R_IRQ_READ0__irq_ext_vector_nr__WIDTH 1
-#define R_IRQ_READ0__irq_ext_vector_nr__active 1
-#define R_IRQ_READ0__irq_ext_vector_nr__inactive 0
-#define R_IRQ_READ0__irq_int_vector_nr__BITNR 4
-#define R_IRQ_READ0__irq_int_vector_nr__WIDTH 1
-#define R_IRQ_READ0__irq_int_vector_nr__active 1
-#define R_IRQ_READ0__irq_int_vector_nr__inactive 0
-#define R_IRQ_READ0__ext_dma1__BITNR 3
-#define R_IRQ_READ0__ext_dma1__WIDTH 1
-#define R_IRQ_READ0__ext_dma1__active 1
-#define R_IRQ_READ0__ext_dma1__inactive 0
-#define R_IRQ_READ0__ext_dma0__BITNR 2
-#define R_IRQ_READ0__ext_dma0__WIDTH 1
-#define R_IRQ_READ0__ext_dma0__active 1
-#define R_IRQ_READ0__ext_dma0__inactive 0
-#define R_IRQ_READ0__timer1__BITNR 1
-#define R_IRQ_READ0__timer1__WIDTH 1
-#define R_IRQ_READ0__timer1__active 1
-#define R_IRQ_READ0__timer1__inactive 0
-#define R_IRQ_READ0__timer0__BITNR 0
-#define R_IRQ_READ0__timer0__WIDTH 1
-#define R_IRQ_READ0__timer0__active 1
-#define R_IRQ_READ0__timer0__inactive 0
-
-#define R_IRQ_MASK0_SET (IO_TYPECAST_UDWORD 0xb00000c4)
-#define R_IRQ_MASK0_SET__nmi_pin__BITNR 31
-#define R_IRQ_MASK0_SET__nmi_pin__WIDTH 1
-#define R_IRQ_MASK0_SET__nmi_pin__set 1
-#define R_IRQ_MASK0_SET__nmi_pin__nop 0
-#define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30
-#define R_IRQ_MASK0_SET__watchdog_nmi__WIDTH 1
-#define R_IRQ_MASK0_SET__watchdog_nmi__set 1
-#define R_IRQ_MASK0_SET__watchdog_nmi__nop 0
-#define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29
-#define R_IRQ_MASK0_SET__sqe_test_error__WIDTH 1
-#define R_IRQ_MASK0_SET__sqe_test_error__set 1
-#define R_IRQ_MASK0_SET__sqe_test_error__nop 0
-#define R_IRQ_MASK0_SET__carrier_loss__BITNR 28
-#define R_IRQ_MASK0_SET__carrier_loss__WIDTH 1
-#define R_IRQ_MASK0_SET__carrier_loss__set 1
-#define R_IRQ_MASK0_SET__carrier_loss__nop 0
-#define R_IRQ_MASK0_SET__deferred__BITNR 27
-#define R_IRQ_MASK0_SET__deferred__WIDTH 1
-#define R_IRQ_MASK0_SET__deferred__set 1
-#define R_IRQ_MASK0_SET__deferred__nop 0
-#define R_IRQ_MASK0_SET__late_col__BITNR 26
-#define R_IRQ_MASK0_SET__late_col__WIDTH 1
-#define R_IRQ_MASK0_SET__late_col__set 1
-#define R_IRQ_MASK0_SET__late_col__nop 0
-#define R_IRQ_MASK0_SET__multiple_col__BITNR 25
-#define R_IRQ_MASK0_SET__multiple_col__WIDTH 1
-#define R_IRQ_MASK0_SET__multiple_col__set 1
-#define R_IRQ_MASK0_SET__multiple_col__nop 0
-#define R_IRQ_MASK0_SET__single_col__BITNR 24
-#define R_IRQ_MASK0_SET__single_col__WIDTH 1
-#define R_IRQ_MASK0_SET__single_col__set 1
-#define R_IRQ_MASK0_SET__single_col__nop 0
-#define R_IRQ_MASK0_SET__congestion__BITNR 23
-#define R_IRQ_MASK0_SET__congestion__WIDTH 1
-#define R_IRQ_MASK0_SET__congestion__set 1
-#define R_IRQ_MASK0_SET__congestion__nop 0
-#define R_IRQ_MASK0_SET__oversize__BITNR 22
-#define R_IRQ_MASK0_SET__oversize__WIDTH 1
-#define R_IRQ_MASK0_SET__oversize__set 1
-#define R_IRQ_MASK0_SET__oversize__nop 0
-#define R_IRQ_MASK0_SET__alignment_error__BITNR 21
-#define R_IRQ_MASK0_SET__alignment_error__WIDTH 1
-#define R_IRQ_MASK0_SET__alignment_error__set 1
-#define R_IRQ_MASK0_SET__alignment_error__nop 0
-#define R_IRQ_MASK0_SET__crc_error__BITNR 20
-#define R_IRQ_MASK0_SET__crc_error__WIDTH 1
-#define R_IRQ_MASK0_SET__crc_error__set 1
-#define R_IRQ_MASK0_SET__crc_error__nop 0
-#define R_IRQ_MASK0_SET__overrun__BITNR 19
-#define R_IRQ_MASK0_SET__overrun__WIDTH 1
-#define R_IRQ_MASK0_SET__overrun__set 1
-#define R_IRQ_MASK0_SET__overrun__nop 0
-#define R_IRQ_MASK0_SET__underrun__BITNR 18
-#define R_IRQ_MASK0_SET__underrun__WIDTH 1
-#define R_IRQ_MASK0_SET__underrun__set 1
-#define R_IRQ_MASK0_SET__underrun__nop 0
-#define R_IRQ_MASK0_SET__excessive_col__BITNR 17
-#define R_IRQ_MASK0_SET__excessive_col__WIDTH 1
-#define R_IRQ_MASK0_SET__excessive_col__set 1
-#define R_IRQ_MASK0_SET__excessive_col__nop 0
-#define R_IRQ_MASK0_SET__mdio__BITNR 16
-#define R_IRQ_MASK0_SET__mdio__WIDTH 1
-#define R_IRQ_MASK0_SET__mdio__set 1
-#define R_IRQ_MASK0_SET__mdio__nop 0
-#define R_IRQ_MASK0_SET__ata_drq3__BITNR 15
-#define R_IRQ_MASK0_SET__ata_drq3__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_drq3__set 1
-#define R_IRQ_MASK0_SET__ata_drq3__nop 0
-#define R_IRQ_MASK0_SET__ata_drq2__BITNR 14
-#define R_IRQ_MASK0_SET__ata_drq2__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_drq2__set 1
-#define R_IRQ_MASK0_SET__ata_drq2__nop 0
-#define R_IRQ_MASK0_SET__ata_drq1__BITNR 13
-#define R_IRQ_MASK0_SET__ata_drq1__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_drq1__set 1
-#define R_IRQ_MASK0_SET__ata_drq1__nop 0
-#define R_IRQ_MASK0_SET__ata_drq0__BITNR 12
-#define R_IRQ_MASK0_SET__ata_drq0__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_drq0__set 1
-#define R_IRQ_MASK0_SET__ata_drq0__nop 0
-#define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11
-#define R_IRQ_MASK0_SET__par0_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK0_SET__par0_ecp_cmd__set 1
-#define R_IRQ_MASK0_SET__par0_ecp_cmd__nop 0
-#define R_IRQ_MASK0_SET__ata_irq3__BITNR 11
-#define R_IRQ_MASK0_SET__ata_irq3__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_irq3__set 1
-#define R_IRQ_MASK0_SET__ata_irq3__nop 0
-#define R_IRQ_MASK0_SET__par0_peri__BITNR 10
-#define R_IRQ_MASK0_SET__par0_peri__WIDTH 1
-#define R_IRQ_MASK0_SET__par0_peri__set 1
-#define R_IRQ_MASK0_SET__par0_peri__nop 0
-#define R_IRQ_MASK0_SET__ata_irq2__BITNR 10
-#define R_IRQ_MASK0_SET__ata_irq2__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_irq2__set 1
-#define R_IRQ_MASK0_SET__ata_irq2__nop 0
-#define R_IRQ_MASK0_SET__par0_data__BITNR 9
-#define R_IRQ_MASK0_SET__par0_data__WIDTH 1
-#define R_IRQ_MASK0_SET__par0_data__set 1
-#define R_IRQ_MASK0_SET__par0_data__nop 0
-#define R_IRQ_MASK0_SET__ata_irq1__BITNR 9
-#define R_IRQ_MASK0_SET__ata_irq1__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_irq1__set 1
-#define R_IRQ_MASK0_SET__ata_irq1__nop 0
-#define R_IRQ_MASK0_SET__par0_ready__BITNR 8
-#define R_IRQ_MASK0_SET__par0_ready__WIDTH 1
-#define R_IRQ_MASK0_SET__par0_ready__set 1
-#define R_IRQ_MASK0_SET__par0_ready__nop 0
-#define R_IRQ_MASK0_SET__ata_irq0__BITNR 8
-#define R_IRQ_MASK0_SET__ata_irq0__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_irq0__set 1
-#define R_IRQ_MASK0_SET__ata_irq0__nop 0
-#define R_IRQ_MASK0_SET__mio__BITNR 8
-#define R_IRQ_MASK0_SET__mio__WIDTH 1
-#define R_IRQ_MASK0_SET__mio__set 1
-#define R_IRQ_MASK0_SET__mio__nop 0
-#define R_IRQ_MASK0_SET__scsi0__BITNR 8
-#define R_IRQ_MASK0_SET__scsi0__WIDTH 1
-#define R_IRQ_MASK0_SET__scsi0__set 1
-#define R_IRQ_MASK0_SET__scsi0__nop 0
-#define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7
-#define R_IRQ_MASK0_SET__ata_dmaend__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_dmaend__set 1
-#define R_IRQ_MASK0_SET__ata_dmaend__nop 0
-#define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5
-#define R_IRQ_MASK0_SET__irq_ext_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_SET__irq_ext_vector_nr__set 1
-#define R_IRQ_MASK0_SET__irq_ext_vector_nr__nop 0
-#define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4
-#define R_IRQ_MASK0_SET__irq_int_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_SET__irq_int_vector_nr__set 1
-#define R_IRQ_MASK0_SET__irq_int_vector_nr__nop 0
-#define R_IRQ_MASK0_SET__ext_dma1__BITNR 3
-#define R_IRQ_MASK0_SET__ext_dma1__WIDTH 1
-#define R_IRQ_MASK0_SET__ext_dma1__set 1
-#define R_IRQ_MASK0_SET__ext_dma1__nop 0
-#define R_IRQ_MASK0_SET__ext_dma0__BITNR 2
-#define R_IRQ_MASK0_SET__ext_dma0__WIDTH 1
-#define R_IRQ_MASK0_SET__ext_dma0__set 1
-#define R_IRQ_MASK0_SET__ext_dma0__nop 0
-#define R_IRQ_MASK0_SET__timer1__BITNR 1
-#define R_IRQ_MASK0_SET__timer1__WIDTH 1
-#define R_IRQ_MASK0_SET__timer1__set 1
-#define R_IRQ_MASK0_SET__timer1__nop 0
-#define R_IRQ_MASK0_SET__timer0__BITNR 0
-#define R_IRQ_MASK0_SET__timer0__WIDTH 1
-#define R_IRQ_MASK0_SET__timer0__set 1
-#define R_IRQ_MASK0_SET__timer0__nop 0
-
-#define R_IRQ_MASK1_RD (IO_TYPECAST_RO_UDWORD 0xb00000c8)
-#define R_IRQ_MASK1_RD__sw_int7__BITNR 31
-#define R_IRQ_MASK1_RD__sw_int7__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int7__active 1
-#define R_IRQ_MASK1_RD__sw_int7__inactive 0
-#define R_IRQ_MASK1_RD__sw_int6__BITNR 30
-#define R_IRQ_MASK1_RD__sw_int6__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int6__active 1
-#define R_IRQ_MASK1_RD__sw_int6__inactive 0
-#define R_IRQ_MASK1_RD__sw_int5__BITNR 29
-#define R_IRQ_MASK1_RD__sw_int5__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int5__active 1
-#define R_IRQ_MASK1_RD__sw_int5__inactive 0
-#define R_IRQ_MASK1_RD__sw_int4__BITNR 28
-#define R_IRQ_MASK1_RD__sw_int4__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int4__active 1
-#define R_IRQ_MASK1_RD__sw_int4__inactive 0
-#define R_IRQ_MASK1_RD__sw_int3__BITNR 27
-#define R_IRQ_MASK1_RD__sw_int3__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int3__active 1
-#define R_IRQ_MASK1_RD__sw_int3__inactive 0
-#define R_IRQ_MASK1_RD__sw_int2__BITNR 26
-#define R_IRQ_MASK1_RD__sw_int2__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int2__active 1
-#define R_IRQ_MASK1_RD__sw_int2__inactive 0
-#define R_IRQ_MASK1_RD__sw_int1__BITNR 25
-#define R_IRQ_MASK1_RD__sw_int1__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int1__active 1
-#define R_IRQ_MASK1_RD__sw_int1__inactive 0
-#define R_IRQ_MASK1_RD__sw_int0__BITNR 24
-#define R_IRQ_MASK1_RD__sw_int0__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int0__active 1
-#define R_IRQ_MASK1_RD__sw_int0__inactive 0
-#define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19
-#define R_IRQ_MASK1_RD__par1_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK1_RD__par1_ecp_cmd__active 1
-#define R_IRQ_MASK1_RD__par1_ecp_cmd__inactive 0
-#define R_IRQ_MASK1_RD__par1_peri__BITNR 18
-#define R_IRQ_MASK1_RD__par1_peri__WIDTH 1
-#define R_IRQ_MASK1_RD__par1_peri__active 1
-#define R_IRQ_MASK1_RD__par1_peri__inactive 0
-#define R_IRQ_MASK1_RD__par1_data__BITNR 17
-#define R_IRQ_MASK1_RD__par1_data__WIDTH 1
-#define R_IRQ_MASK1_RD__par1_data__active 1
-#define R_IRQ_MASK1_RD__par1_data__inactive 0
-#define R_IRQ_MASK1_RD__par1_ready__BITNR 16
-#define R_IRQ_MASK1_RD__par1_ready__WIDTH 1
-#define R_IRQ_MASK1_RD__par1_ready__active 1
-#define R_IRQ_MASK1_RD__par1_ready__inactive 0
-#define R_IRQ_MASK1_RD__scsi1__BITNR 16
-#define R_IRQ_MASK1_RD__scsi1__WIDTH 1
-#define R_IRQ_MASK1_RD__scsi1__active 1
-#define R_IRQ_MASK1_RD__scsi1__inactive 0
-#define R_IRQ_MASK1_RD__ser3_ready__BITNR 15
-#define R_IRQ_MASK1_RD__ser3_ready__WIDTH 1
-#define R_IRQ_MASK1_RD__ser3_ready__active 1
-#define R_IRQ_MASK1_RD__ser3_ready__inactive 0
-#define R_IRQ_MASK1_RD__ser3_data__BITNR 14
-#define R_IRQ_MASK1_RD__ser3_data__WIDTH 1
-#define R_IRQ_MASK1_RD__ser3_data__active 1
-#define R_IRQ_MASK1_RD__ser3_data__inactive 0
-#define R_IRQ_MASK1_RD__ser2_ready__BITNR 13
-#define R_IRQ_MASK1_RD__ser2_ready__WIDTH 1
-#define R_IRQ_MASK1_RD__ser2_ready__active 1
-#define R_IRQ_MASK1_RD__ser2_ready__inactive 0
-#define R_IRQ_MASK1_RD__ser2_data__BITNR 12
-#define R_IRQ_MASK1_RD__ser2_data__WIDTH 1
-#define R_IRQ_MASK1_RD__ser2_data__active 1
-#define R_IRQ_MASK1_RD__ser2_data__inactive 0
-#define R_IRQ_MASK1_RD__ser1_ready__BITNR 11
-#define R_IRQ_MASK1_RD__ser1_ready__WIDTH 1
-#define R_IRQ_MASK1_RD__ser1_ready__active 1
-#define R_IRQ_MASK1_RD__ser1_ready__inactive 0
-#define R_IRQ_MASK1_RD__ser1_data__BITNR 10
-#define R_IRQ_MASK1_RD__ser1_data__WIDTH 1
-#define R_IRQ_MASK1_RD__ser1_data__active 1
-#define R_IRQ_MASK1_RD__ser1_data__inactive 0
-#define R_IRQ_MASK1_RD__ser0_ready__BITNR 9
-#define R_IRQ_MASK1_RD__ser0_ready__WIDTH 1
-#define R_IRQ_MASK1_RD__ser0_ready__active 1
-#define R_IRQ_MASK1_RD__ser0_ready__inactive 0
-#define R_IRQ_MASK1_RD__ser0_data__BITNR 8
-#define R_IRQ_MASK1_RD__ser0_data__WIDTH 1
-#define R_IRQ_MASK1_RD__ser0_data__active 1
-#define R_IRQ_MASK1_RD__ser0_data__inactive 0
-#define R_IRQ_MASK1_RD__pa7__BITNR 7
-#define R_IRQ_MASK1_RD__pa7__WIDTH 1
-#define R_IRQ_MASK1_RD__pa7__active 1
-#define R_IRQ_MASK1_RD__pa7__inactive 0
-#define R_IRQ_MASK1_RD__pa6__BITNR 6
-#define R_IRQ_MASK1_RD__pa6__WIDTH 1
-#define R_IRQ_MASK1_RD__pa6__active 1
-#define R_IRQ_MASK1_RD__pa6__inactive 0
-#define R_IRQ_MASK1_RD__pa5__BITNR 5
-#define R_IRQ_MASK1_RD__pa5__WIDTH 1
-#define R_IRQ_MASK1_RD__pa5__active 1
-#define R_IRQ_MASK1_RD__pa5__inactive 0
-#define R_IRQ_MASK1_RD__pa4__BITNR 4
-#define R_IRQ_MASK1_RD__pa4__WIDTH 1
-#define R_IRQ_MASK1_RD__pa4__active 1
-#define R_IRQ_MASK1_RD__pa4__inactive 0
-#define R_IRQ_MASK1_RD__pa3__BITNR 3
-#define R_IRQ_MASK1_RD__pa3__WIDTH 1
-#define R_IRQ_MASK1_RD__pa3__active 1
-#define R_IRQ_MASK1_RD__pa3__inactive 0
-#define R_IRQ_MASK1_RD__pa2__BITNR 2
-#define R_IRQ_MASK1_RD__pa2__WIDTH 1
-#define R_IRQ_MASK1_RD__pa2__active 1
-#define R_IRQ_MASK1_RD__pa2__inactive 0
-#define R_IRQ_MASK1_RD__pa1__BITNR 1
-#define R_IRQ_MASK1_RD__pa1__WIDTH 1
-#define R_IRQ_MASK1_RD__pa1__active 1
-#define R_IRQ_MASK1_RD__pa1__inactive 0
-#define R_IRQ_MASK1_RD__pa0__BITNR 0
-#define R_IRQ_MASK1_RD__pa0__WIDTH 1
-#define R_IRQ_MASK1_RD__pa0__active 1
-#define R_IRQ_MASK1_RD__pa0__inactive 0
-
-#define R_IRQ_MASK1_CLR (IO_TYPECAST_UDWORD 0xb00000c8)
-#define R_IRQ_MASK1_CLR__sw_int7__BITNR 31
-#define R_IRQ_MASK1_CLR__sw_int7__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int7__clr 1
-#define R_IRQ_MASK1_CLR__sw_int7__nop 0
-#define R_IRQ_MASK1_CLR__sw_int6__BITNR 30
-#define R_IRQ_MASK1_CLR__sw_int6__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int6__clr 1
-#define R_IRQ_MASK1_CLR__sw_int6__nop 0
-#define R_IRQ_MASK1_CLR__sw_int5__BITNR 29
-#define R_IRQ_MASK1_CLR__sw_int5__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int5__clr 1
-#define R_IRQ_MASK1_CLR__sw_int5__nop 0
-#define R_IRQ_MASK1_CLR__sw_int4__BITNR 28
-#define R_IRQ_MASK1_CLR__sw_int4__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int4__clr 1
-#define R_IRQ_MASK1_CLR__sw_int4__nop 0
-#define R_IRQ_MASK1_CLR__sw_int3__BITNR 27
-#define R_IRQ_MASK1_CLR__sw_int3__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int3__clr 1
-#define R_IRQ_MASK1_CLR__sw_int3__nop 0
-#define R_IRQ_MASK1_CLR__sw_int2__BITNR 26
-#define R_IRQ_MASK1_CLR__sw_int2__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int2__clr 1
-#define R_IRQ_MASK1_CLR__sw_int2__nop 0
-#define R_IRQ_MASK1_CLR__sw_int1__BITNR 25
-#define R_IRQ_MASK1_CLR__sw_int1__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int1__clr 1
-#define R_IRQ_MASK1_CLR__sw_int1__nop 0
-#define R_IRQ_MASK1_CLR__sw_int0__BITNR 24
-#define R_IRQ_MASK1_CLR__sw_int0__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int0__clr 1
-#define R_IRQ_MASK1_CLR__sw_int0__nop 0
-#define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19
-#define R_IRQ_MASK1_CLR__par1_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK1_CLR__par1_ecp_cmd__clr 1
-#define R_IRQ_MASK1_CLR__par1_ecp_cmd__nop 0
-#define R_IRQ_MASK1_CLR__par1_peri__BITNR 18
-#define R_IRQ_MASK1_CLR__par1_peri__WIDTH 1
-#define R_IRQ_MASK1_CLR__par1_peri__clr 1
-#define R_IRQ_MASK1_CLR__par1_peri__nop 0
-#define R_IRQ_MASK1_CLR__par1_data__BITNR 17
-#define R_IRQ_MASK1_CLR__par1_data__WIDTH 1
-#define R_IRQ_MASK1_CLR__par1_data__clr 1
-#define R_IRQ_MASK1_CLR__par1_data__nop 0
-#define R_IRQ_MASK1_CLR__par1_ready__BITNR 16
-#define R_IRQ_MASK1_CLR__par1_ready__WIDTH 1
-#define R_IRQ_MASK1_CLR__par1_ready__clr 1
-#define R_IRQ_MASK1_CLR__par1_ready__nop 0
-#define R_IRQ_MASK1_CLR__scsi1__BITNR 16
-#define R_IRQ_MASK1_CLR__scsi1__WIDTH 1
-#define R_IRQ_MASK1_CLR__scsi1__clr 1
-#define R_IRQ_MASK1_CLR__scsi1__nop 0
-#define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15
-#define R_IRQ_MASK1_CLR__ser3_ready__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser3_ready__clr 1
-#define R_IRQ_MASK1_CLR__ser3_ready__nop 0
-#define R_IRQ_MASK1_CLR__ser3_data__BITNR 14
-#define R_IRQ_MASK1_CLR__ser3_data__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser3_data__clr 1
-#define R_IRQ_MASK1_CLR__ser3_data__nop 0
-#define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13
-#define R_IRQ_MASK1_CLR__ser2_ready__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser2_ready__clr 1
-#define R_IRQ_MASK1_CLR__ser2_ready__nop 0
-#define R_IRQ_MASK1_CLR__ser2_data__BITNR 12
-#define R_IRQ_MASK1_CLR__ser2_data__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser2_data__clr 1
-#define R_IRQ_MASK1_CLR__ser2_data__nop 0
-#define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11
-#define R_IRQ_MASK1_CLR__ser1_ready__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser1_ready__clr 1
-#define R_IRQ_MASK1_CLR__ser1_ready__nop 0
-#define R_IRQ_MASK1_CLR__ser1_data__BITNR 10
-#define R_IRQ_MASK1_CLR__ser1_data__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser1_data__clr 1
-#define R_IRQ_MASK1_CLR__ser1_data__nop 0
-#define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9
-#define R_IRQ_MASK1_CLR__ser0_ready__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser0_ready__clr 1
-#define R_IRQ_MASK1_CLR__ser0_ready__nop 0
-#define R_IRQ_MASK1_CLR__ser0_data__BITNR 8
-#define R_IRQ_MASK1_CLR__ser0_data__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser0_data__clr 1
-#define R_IRQ_MASK1_CLR__ser0_data__nop 0
-#define R_IRQ_MASK1_CLR__pa7__BITNR 7
-#define R_IRQ_MASK1_CLR__pa7__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa7__clr 1
-#define R_IRQ_MASK1_CLR__pa7__nop 0
-#define R_IRQ_MASK1_CLR__pa6__BITNR 6
-#define R_IRQ_MASK1_CLR__pa6__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa6__clr 1
-#define R_IRQ_MASK1_CLR__pa6__nop 0
-#define R_IRQ_MASK1_CLR__pa5__BITNR 5
-#define R_IRQ_MASK1_CLR__pa5__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa5__clr 1
-#define R_IRQ_MASK1_CLR__pa5__nop 0
-#define R_IRQ_MASK1_CLR__pa4__BITNR 4
-#define R_IRQ_MASK1_CLR__pa4__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa4__clr 1
-#define R_IRQ_MASK1_CLR__pa4__nop 0
-#define R_IRQ_MASK1_CLR__pa3__BITNR 3
-#define R_IRQ_MASK1_CLR__pa3__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa3__clr 1
-#define R_IRQ_MASK1_CLR__pa3__nop 0
-#define R_IRQ_MASK1_CLR__pa2__BITNR 2
-#define R_IRQ_MASK1_CLR__pa2__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa2__clr 1
-#define R_IRQ_MASK1_CLR__pa2__nop 0
-#define R_IRQ_MASK1_CLR__pa1__BITNR 1
-#define R_IRQ_MASK1_CLR__pa1__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa1__clr 1
-#define R_IRQ_MASK1_CLR__pa1__nop 0
-#define R_IRQ_MASK1_CLR__pa0__BITNR 0
-#define R_IRQ_MASK1_CLR__pa0__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa0__clr 1
-#define R_IRQ_MASK1_CLR__pa0__nop 0
-
-#define R_IRQ_READ1 (IO_TYPECAST_RO_UDWORD 0xb00000cc)
-#define R_IRQ_READ1__sw_int7__BITNR 31
-#define R_IRQ_READ1__sw_int7__WIDTH 1
-#define R_IRQ_READ1__sw_int7__active 1
-#define R_IRQ_READ1__sw_int7__inactive 0
-#define R_IRQ_READ1__sw_int6__BITNR 30
-#define R_IRQ_READ1__sw_int6__WIDTH 1
-#define R_IRQ_READ1__sw_int6__active 1
-#define R_IRQ_READ1__sw_int6__inactive 0
-#define R_IRQ_READ1__sw_int5__BITNR 29
-#define R_IRQ_READ1__sw_int5__WIDTH 1
-#define R_IRQ_READ1__sw_int5__active 1
-#define R_IRQ_READ1__sw_int5__inactive 0
-#define R_IRQ_READ1__sw_int4__BITNR 28
-#define R_IRQ_READ1__sw_int4__WIDTH 1
-#define R_IRQ_READ1__sw_int4__active 1
-#define R_IRQ_READ1__sw_int4__inactive 0
-#define R_IRQ_READ1__sw_int3__BITNR 27
-#define R_IRQ_READ1__sw_int3__WIDTH 1
-#define R_IRQ_READ1__sw_int3__active 1
-#define R_IRQ_READ1__sw_int3__inactive 0
-#define R_IRQ_READ1__sw_int2__BITNR 26
-#define R_IRQ_READ1__sw_int2__WIDTH 1
-#define R_IRQ_READ1__sw_int2__active 1
-#define R_IRQ_READ1__sw_int2__inactive 0
-#define R_IRQ_READ1__sw_int1__BITNR 25
-#define R_IRQ_READ1__sw_int1__WIDTH 1
-#define R_IRQ_READ1__sw_int1__active 1
-#define R_IRQ_READ1__sw_int1__inactive 0
-#define R_IRQ_READ1__sw_int0__BITNR 24
-#define R_IRQ_READ1__sw_int0__WIDTH 1
-#define R_IRQ_READ1__sw_int0__active 1
-#define R_IRQ_READ1__sw_int0__inactive 0
-#define R_IRQ_READ1__par1_ecp_cmd__BITNR 19
-#define R_IRQ_READ1__par1_ecp_cmd__WIDTH 1
-#define R_IRQ_READ1__par1_ecp_cmd__active 1
-#define R_IRQ_READ1__par1_ecp_cmd__inactive 0
-#define R_IRQ_READ1__par1_peri__BITNR 18
-#define R_IRQ_READ1__par1_peri__WIDTH 1
-#define R_IRQ_READ1__par1_peri__active 1
-#define R_IRQ_READ1__par1_peri__inactive 0
-#define R_IRQ_READ1__par1_data__BITNR 17
-#define R_IRQ_READ1__par1_data__WIDTH 1
-#define R_IRQ_READ1__par1_data__active 1
-#define R_IRQ_READ1__par1_data__inactive 0
-#define R_IRQ_READ1__par1_ready__BITNR 16
-#define R_IRQ_READ1__par1_ready__WIDTH 1
-#define R_IRQ_READ1__par1_ready__active 1
-#define R_IRQ_READ1__par1_ready__inactive 0
-#define R_IRQ_READ1__scsi1__BITNR 16
-#define R_IRQ_READ1__scsi1__WIDTH 1
-#define R_IRQ_READ1__scsi1__active 1
-#define R_IRQ_READ1__scsi1__inactive 0
-#define R_IRQ_READ1__ser3_ready__BITNR 15
-#define R_IRQ_READ1__ser3_ready__WIDTH 1
-#define R_IRQ_READ1__ser3_ready__active 1
-#define R_IRQ_READ1__ser3_ready__inactive 0
-#define R_IRQ_READ1__ser3_data__BITNR 14
-#define R_IRQ_READ1__ser3_data__WIDTH 1
-#define R_IRQ_READ1__ser3_data__active 1
-#define R_IRQ_READ1__ser3_data__inactive 0
-#define R_IRQ_READ1__ser2_ready__BITNR 13
-#define R_IRQ_READ1__ser2_ready__WIDTH 1
-#define R_IRQ_READ1__ser2_ready__active 1
-#define R_IRQ_READ1__ser2_ready__inactive 0
-#define R_IRQ_READ1__ser2_data__BITNR 12
-#define R_IRQ_READ1__ser2_data__WIDTH 1
-#define R_IRQ_READ1__ser2_data__active 1
-#define R_IRQ_READ1__ser2_data__inactive 0
-#define R_IRQ_READ1__ser1_ready__BITNR 11
-#define R_IRQ_READ1__ser1_ready__WIDTH 1
-#define R_IRQ_READ1__ser1_ready__active 1
-#define R_IRQ_READ1__ser1_ready__inactive 0
-#define R_IRQ_READ1__ser1_data__BITNR 10
-#define R_IRQ_READ1__ser1_data__WIDTH 1
-#define R_IRQ_READ1__ser1_data__active 1
-#define R_IRQ_READ1__ser1_data__inactive 0
-#define R_IRQ_READ1__ser0_ready__BITNR 9
-#define R_IRQ_READ1__ser0_ready__WIDTH 1
-#define R_IRQ_READ1__ser0_ready__active 1
-#define R_IRQ_READ1__ser0_ready__inactive 0
-#define R_IRQ_READ1__ser0_data__BITNR 8
-#define R_IRQ_READ1__ser0_data__WIDTH 1
-#define R_IRQ_READ1__ser0_data__active 1
-#define R_IRQ_READ1__ser0_data__inactive 0
-#define R_IRQ_READ1__pa7__BITNR 7
-#define R_IRQ_READ1__pa7__WIDTH 1
-#define R_IRQ_READ1__pa7__active 1
-#define R_IRQ_READ1__pa7__inactive 0
-#define R_IRQ_READ1__pa6__BITNR 6
-#define R_IRQ_READ1__pa6__WIDTH 1
-#define R_IRQ_READ1__pa6__active 1
-#define R_IRQ_READ1__pa6__inactive 0
-#define R_IRQ_READ1__pa5__BITNR 5
-#define R_IRQ_READ1__pa5__WIDTH 1
-#define R_IRQ_READ1__pa5__active 1
-#define R_IRQ_READ1__pa5__inactive 0
-#define R_IRQ_READ1__pa4__BITNR 4
-#define R_IRQ_READ1__pa4__WIDTH 1
-#define R_IRQ_READ1__pa4__active 1
-#define R_IRQ_READ1__pa4__inactive 0
-#define R_IRQ_READ1__pa3__BITNR 3
-#define R_IRQ_READ1__pa3__WIDTH 1
-#define R_IRQ_READ1__pa3__active 1
-#define R_IRQ_READ1__pa3__inactive 0
-#define R_IRQ_READ1__pa2__BITNR 2
-#define R_IRQ_READ1__pa2__WIDTH 1
-#define R_IRQ_READ1__pa2__active 1
-#define R_IRQ_READ1__pa2__inactive 0
-#define R_IRQ_READ1__pa1__BITNR 1
-#define R_IRQ_READ1__pa1__WIDTH 1
-#define R_IRQ_READ1__pa1__active 1
-#define R_IRQ_READ1__pa1__inactive 0
-#define R_IRQ_READ1__pa0__BITNR 0
-#define R_IRQ_READ1__pa0__WIDTH 1
-#define R_IRQ_READ1__pa0__active 1
-#define R_IRQ_READ1__pa0__inactive 0
-
-#define R_IRQ_MASK1_SET (IO_TYPECAST_UDWORD 0xb00000cc)
-#define R_IRQ_MASK1_SET__sw_int7__BITNR 31
-#define R_IRQ_MASK1_SET__sw_int7__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int7__set 1
-#define R_IRQ_MASK1_SET__sw_int7__nop 0
-#define R_IRQ_MASK1_SET__sw_int6__BITNR 30
-#define R_IRQ_MASK1_SET__sw_int6__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int6__set 1
-#define R_IRQ_MASK1_SET__sw_int6__nop 0
-#define R_IRQ_MASK1_SET__sw_int5__BITNR 29
-#define R_IRQ_MASK1_SET__sw_int5__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int5__set 1
-#define R_IRQ_MASK1_SET__sw_int5__nop 0
-#define R_IRQ_MASK1_SET__sw_int4__BITNR 28
-#define R_IRQ_MASK1_SET__sw_int4__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int4__set 1
-#define R_IRQ_MASK1_SET__sw_int4__nop 0
-#define R_IRQ_MASK1_SET__sw_int3__BITNR 27
-#define R_IRQ_MASK1_SET__sw_int3__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int3__set 1
-#define R_IRQ_MASK1_SET__sw_int3__nop 0
-#define R_IRQ_MASK1_SET__sw_int2__BITNR 26
-#define R_IRQ_MASK1_SET__sw_int2__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int2__set 1
-#define R_IRQ_MASK1_SET__sw_int2__nop 0
-#define R_IRQ_MASK1_SET__sw_int1__BITNR 25
-#define R_IRQ_MASK1_SET__sw_int1__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int1__set 1
-#define R_IRQ_MASK1_SET__sw_int1__nop 0
-#define R_IRQ_MASK1_SET__sw_int0__BITNR 24
-#define R_IRQ_MASK1_SET__sw_int0__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int0__set 1
-#define R_IRQ_MASK1_SET__sw_int0__nop 0
-#define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19
-#define R_IRQ_MASK1_SET__par1_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK1_SET__par1_ecp_cmd__set 1
-#define R_IRQ_MASK1_SET__par1_ecp_cmd__nop 0
-#define R_IRQ_MASK1_SET__par1_peri__BITNR 18
-#define R_IRQ_MASK1_SET__par1_peri__WIDTH 1
-#define R_IRQ_MASK1_SET__par1_peri__set 1
-#define R_IRQ_MASK1_SET__par1_peri__nop 0
-#define R_IRQ_MASK1_SET__par1_data__BITNR 17
-#define R_IRQ_MASK1_SET__par1_data__WIDTH 1
-#define R_IRQ_MASK1_SET__par1_data__set 1
-#define R_IRQ_MASK1_SET__par1_data__nop 0
-#define R_IRQ_MASK1_SET__par1_ready__BITNR 16
-#define R_IRQ_MASK1_SET__par1_ready__WIDTH 1
-#define R_IRQ_MASK1_SET__par1_ready__set 1
-#define R_IRQ_MASK1_SET__par1_ready__nop 0
-#define R_IRQ_MASK1_SET__scsi1__BITNR 16
-#define R_IRQ_MASK1_SET__scsi1__WIDTH 1
-#define R_IRQ_MASK1_SET__scsi1__set 1
-#define R_IRQ_MASK1_SET__scsi1__nop 0
-#define R_IRQ_MASK1_SET__ser3_ready__BITNR 15
-#define R_IRQ_MASK1_SET__ser3_ready__WIDTH 1
-#define R_IRQ_MASK1_SET__ser3_ready__set 1
-#define R_IRQ_MASK1_SET__ser3_ready__nop 0
-#define R_IRQ_MASK1_SET__ser3_data__BITNR 14
-#define R_IRQ_MASK1_SET__ser3_data__WIDTH 1
-#define R_IRQ_MASK1_SET__ser3_data__set 1
-#define R_IRQ_MASK1_SET__ser3_data__nop 0
-#define R_IRQ_MASK1_SET__ser2_ready__BITNR 13
-#define R_IRQ_MASK1_SET__ser2_ready__WIDTH 1
-#define R_IRQ_MASK1_SET__ser2_ready__set 1
-#define R_IRQ_MASK1_SET__ser2_ready__nop 0
-#define R_IRQ_MASK1_SET__ser2_data__BITNR 12
-#define R_IRQ_MASK1_SET__ser2_data__WIDTH 1
-#define R_IRQ_MASK1_SET__ser2_data__set 1
-#define R_IRQ_MASK1_SET__ser2_data__nop 0
-#define R_IRQ_MASK1_SET__ser1_ready__BITNR 11
-#define R_IRQ_MASK1_SET__ser1_ready__WIDTH 1
-#define R_IRQ_MASK1_SET__ser1_ready__set 1
-#define R_IRQ_MASK1_SET__ser1_ready__nop 0
-#define R_IRQ_MASK1_SET__ser1_data__BITNR 10
-#define R_IRQ_MASK1_SET__ser1_data__WIDTH 1
-#define R_IRQ_MASK1_SET__ser1_data__set 1
-#define R_IRQ_MASK1_SET__ser1_data__nop 0
-#define R_IRQ_MASK1_SET__ser0_ready__BITNR 9
-#define R_IRQ_MASK1_SET__ser0_ready__WIDTH 1
-#define R_IRQ_MASK1_SET__ser0_ready__set 1
-#define R_IRQ_MASK1_SET__ser0_ready__nop 0
-#define R_IRQ_MASK1_SET__ser0_data__BITNR 8
-#define R_IRQ_MASK1_SET__ser0_data__WIDTH 1
-#define R_IRQ_MASK1_SET__ser0_data__set 1
-#define R_IRQ_MASK1_SET__ser0_data__nop 0
-#define R_IRQ_MASK1_SET__pa7__BITNR 7
-#define R_IRQ_MASK1_SET__pa7__WIDTH 1
-#define R_IRQ_MASK1_SET__pa7__set 1
-#define R_IRQ_MASK1_SET__pa7__nop 0
-#define R_IRQ_MASK1_SET__pa6__BITNR 6
-#define R_IRQ_MASK1_SET__pa6__WIDTH 1
-#define R_IRQ_MASK1_SET__pa6__set 1
-#define R_IRQ_MASK1_SET__pa6__nop 0
-#define R_IRQ_MASK1_SET__pa5__BITNR 5
-#define R_IRQ_MASK1_SET__pa5__WIDTH 1
-#define R_IRQ_MASK1_SET__pa5__set 1
-#define R_IRQ_MASK1_SET__pa5__nop 0
-#define R_IRQ_MASK1_SET__pa4__BITNR 4
-#define R_IRQ_MASK1_SET__pa4__WIDTH 1
-#define R_IRQ_MASK1_SET__pa4__set 1
-#define R_IRQ_MASK1_SET__pa4__nop 0
-#define R_IRQ_MASK1_SET__pa3__BITNR 3
-#define R_IRQ_MASK1_SET__pa3__WIDTH 1
-#define R_IRQ_MASK1_SET__pa3__set 1
-#define R_IRQ_MASK1_SET__pa3__nop 0
-#define R_IRQ_MASK1_SET__pa2__BITNR 2
-#define R_IRQ_MASK1_SET__pa2__WIDTH 1
-#define R_IRQ_MASK1_SET__pa2__set 1
-#define R_IRQ_MASK1_SET__pa2__nop 0
-#define R_IRQ_MASK1_SET__pa1__BITNR 1
-#define R_IRQ_MASK1_SET__pa1__WIDTH 1
-#define R_IRQ_MASK1_SET__pa1__set 1
-#define R_IRQ_MASK1_SET__pa1__nop 0
-#define R_IRQ_MASK1_SET__pa0__BITNR 0
-#define R_IRQ_MASK1_SET__pa0__WIDTH 1
-#define R_IRQ_MASK1_SET__pa0__set 1
-#define R_IRQ_MASK1_SET__pa0__nop 0
-
-#define R_IRQ_MASK2_RD (IO_TYPECAST_RO_UDWORD 0xb00000d0)
-#define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23
-#define R_IRQ_MASK2_RD__dma8_sub3_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_sub3_descr__active 1
-#define R_IRQ_MASK2_RD__dma8_sub3_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22
-#define R_IRQ_MASK2_RD__dma8_sub2_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_sub2_descr__active 1
-#define R_IRQ_MASK2_RD__dma8_sub2_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21
-#define R_IRQ_MASK2_RD__dma8_sub1_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_sub1_descr__active 1
-#define R_IRQ_MASK2_RD__dma8_sub1_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20
-#define R_IRQ_MASK2_RD__dma8_sub0_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_sub0_descr__active 1
-#define R_IRQ_MASK2_RD__dma8_sub0_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma9_eop__BITNR 19
-#define R_IRQ_MASK2_RD__dma9_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma9_eop__active 1
-#define R_IRQ_MASK2_RD__dma9_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma9_descr__BITNR 18
-#define R_IRQ_MASK2_RD__dma9_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma9_descr__active 1
-#define R_IRQ_MASK2_RD__dma9_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma8_eop__BITNR 17
-#define R_IRQ_MASK2_RD__dma8_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_eop__active 1
-#define R_IRQ_MASK2_RD__dma8_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma8_descr__BITNR 16
-#define R_IRQ_MASK2_RD__dma8_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_descr__active 1
-#define R_IRQ_MASK2_RD__dma8_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma7_eop__BITNR 15
-#define R_IRQ_MASK2_RD__dma7_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma7_eop__active 1
-#define R_IRQ_MASK2_RD__dma7_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma7_descr__BITNR 14
-#define R_IRQ_MASK2_RD__dma7_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma7_descr__active 1
-#define R_IRQ_MASK2_RD__dma7_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma6_eop__BITNR 13
-#define R_IRQ_MASK2_RD__dma6_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma6_eop__active 1
-#define R_IRQ_MASK2_RD__dma6_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma6_descr__BITNR 12
-#define R_IRQ_MASK2_RD__dma6_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma6_descr__active 1
-#define R_IRQ_MASK2_RD__dma6_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma5_eop__BITNR 11
-#define R_IRQ_MASK2_RD__dma5_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma5_eop__active 1
-#define R_IRQ_MASK2_RD__dma5_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma5_descr__BITNR 10
-#define R_IRQ_MASK2_RD__dma5_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma5_descr__active 1
-#define R_IRQ_MASK2_RD__dma5_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma4_eop__BITNR 9
-#define R_IRQ_MASK2_RD__dma4_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma4_eop__active 1
-#define R_IRQ_MASK2_RD__dma4_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma4_descr__BITNR 8
-#define R_IRQ_MASK2_RD__dma4_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma4_descr__active 1
-#define R_IRQ_MASK2_RD__dma4_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma3_eop__BITNR 7
-#define R_IRQ_MASK2_RD__dma3_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma3_eop__active 1
-#define R_IRQ_MASK2_RD__dma3_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma3_descr__BITNR 6
-#define R_IRQ_MASK2_RD__dma3_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma3_descr__active 1
-#define R_IRQ_MASK2_RD__dma3_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma2_eop__BITNR 5
-#define R_IRQ_MASK2_RD__dma2_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma2_eop__active 1
-#define R_IRQ_MASK2_RD__dma2_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma2_descr__BITNR 4
-#define R_IRQ_MASK2_RD__dma2_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma2_descr__active 1
-#define R_IRQ_MASK2_RD__dma2_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma1_eop__BITNR 3
-#define R_IRQ_MASK2_RD__dma1_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma1_eop__active 1
-#define R_IRQ_MASK2_RD__dma1_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma1_descr__BITNR 2
-#define R_IRQ_MASK2_RD__dma1_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma1_descr__active 1
-#define R_IRQ_MASK2_RD__dma1_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma0_eop__BITNR 1
-#define R_IRQ_MASK2_RD__dma0_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma0_eop__active 1
-#define R_IRQ_MASK2_RD__dma0_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma0_descr__BITNR 0
-#define R_IRQ_MASK2_RD__dma0_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma0_descr__active 1
-#define R_IRQ_MASK2_RD__dma0_descr__inactive 0
-
-#define R_IRQ_MASK2_CLR (IO_TYPECAST_UDWORD 0xb00000d0)
-#define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23
-#define R_IRQ_MASK2_CLR__dma8_sub3_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_sub3_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma8_sub3_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22
-#define R_IRQ_MASK2_CLR__dma8_sub2_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_sub2_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma8_sub2_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21
-#define R_IRQ_MASK2_CLR__dma8_sub1_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_sub1_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma8_sub1_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20
-#define R_IRQ_MASK2_CLR__dma8_sub0_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_sub0_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma8_sub0_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19
-#define R_IRQ_MASK2_CLR__dma9_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma9_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma9_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18
-#define R_IRQ_MASK2_CLR__dma9_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma9_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma9_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17
-#define R_IRQ_MASK2_CLR__dma8_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma8_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16
-#define R_IRQ_MASK2_CLR__dma8_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma8_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15
-#define R_IRQ_MASK2_CLR__dma7_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma7_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma7_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14
-#define R_IRQ_MASK2_CLR__dma7_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma7_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma7_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13
-#define R_IRQ_MASK2_CLR__dma6_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma6_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma6_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12
-#define R_IRQ_MASK2_CLR__dma6_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma6_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma6_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11
-#define R_IRQ_MASK2_CLR__dma5_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma5_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma5_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10
-#define R_IRQ_MASK2_CLR__dma5_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma5_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma5_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9
-#define R_IRQ_MASK2_CLR__dma4_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma4_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma4_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8
-#define R_IRQ_MASK2_CLR__dma4_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma4_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma4_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7
-#define R_IRQ_MASK2_CLR__dma3_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma3_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma3_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6
-#define R_IRQ_MASK2_CLR__dma3_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma3_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma3_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5
-#define R_IRQ_MASK2_CLR__dma2_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma2_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma2_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4
-#define R_IRQ_MASK2_CLR__dma2_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma2_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma2_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3
-#define R_IRQ_MASK2_CLR__dma1_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma1_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma1_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2
-#define R_IRQ_MASK2_CLR__dma1_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma1_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma1_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1
-#define R_IRQ_MASK2_CLR__dma0_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma0_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma0_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0
-#define R_IRQ_MASK2_CLR__dma0_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma0_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma0_descr__nop 0
-
-#define R_IRQ_READ2 (IO_TYPECAST_RO_UDWORD 0xb00000d4)
-#define R_IRQ_READ2__dma8_sub3_descr__BITNR 23
-#define R_IRQ_READ2__dma8_sub3_descr__WIDTH 1
-#define R_IRQ_READ2__dma8_sub3_descr__active 1
-#define R_IRQ_READ2__dma8_sub3_descr__inactive 0
-#define R_IRQ_READ2__dma8_sub2_descr__BITNR 22
-#define R_IRQ_READ2__dma8_sub2_descr__WIDTH 1
-#define R_IRQ_READ2__dma8_sub2_descr__active 1
-#define R_IRQ_READ2__dma8_sub2_descr__inactive 0
-#define R_IRQ_READ2__dma8_sub1_descr__BITNR 21
-#define R_IRQ_READ2__dma8_sub1_descr__WIDTH 1
-#define R_IRQ_READ2__dma8_sub1_descr__active 1
-#define R_IRQ_READ2__dma8_sub1_descr__inactive 0
-#define R_IRQ_READ2__dma8_sub0_descr__BITNR 20
-#define R_IRQ_READ2__dma8_sub0_descr__WIDTH 1
-#define R_IRQ_READ2__dma8_sub0_descr__active 1
-#define R_IRQ_READ2__dma8_sub0_descr__inactive 0
-#define R_IRQ_READ2__dma9_eop__BITNR 19
-#define R_IRQ_READ2__dma9_eop__WIDTH 1
-#define R_IRQ_READ2__dma9_eop__active 1
-#define R_IRQ_READ2__dma9_eop__inactive 0
-#define R_IRQ_READ2__dma9_descr__BITNR 18
-#define R_IRQ_READ2__dma9_descr__WIDTH 1
-#define R_IRQ_READ2__dma9_descr__active 1
-#define R_IRQ_READ2__dma9_descr__inactive 0
-#define R_IRQ_READ2__dma8_eop__BITNR 17
-#define R_IRQ_READ2__dma8_eop__WIDTH 1
-#define R_IRQ_READ2__dma8_eop__active 1
-#define R_IRQ_READ2__dma8_eop__inactive 0
-#define R_IRQ_READ2__dma8_descr__BITNR 16
-#define R_IRQ_READ2__dma8_descr__WIDTH 1
-#define R_IRQ_READ2__dma8_descr__active 1
-#define R_IRQ_READ2__dma8_descr__inactive 0
-#define R_IRQ_READ2__dma7_eop__BITNR 15
-#define R_IRQ_READ2__dma7_eop__WIDTH 1
-#define R_IRQ_READ2__dma7_eop__active 1
-#define R_IRQ_READ2__dma7_eop__inactive 0
-#define R_IRQ_READ2__dma7_descr__BITNR 14
-#define R_IRQ_READ2__dma7_descr__WIDTH 1
-#define R_IRQ_READ2__dma7_descr__active 1
-#define R_IRQ_READ2__dma7_descr__inactive 0
-#define R_IRQ_READ2__dma6_eop__BITNR 13
-#define R_IRQ_READ2__dma6_eop__WIDTH 1
-#define R_IRQ_READ2__dma6_eop__active 1
-#define R_IRQ_READ2__dma6_eop__inactive 0
-#define R_IRQ_READ2__dma6_descr__BITNR 12
-#define R_IRQ_READ2__dma6_descr__WIDTH 1
-#define R_IRQ_READ2__dma6_descr__active 1
-#define R_IRQ_READ2__dma6_descr__inactive 0
-#define R_IRQ_READ2__dma5_eop__BITNR 11
-#define R_IRQ_READ2__dma5_eop__WIDTH 1
-#define R_IRQ_READ2__dma5_eop__active 1
-#define R_IRQ_READ2__dma5_eop__inactive 0
-#define R_IRQ_READ2__dma5_descr__BITNR 10
-#define R_IRQ_READ2__dma5_descr__WIDTH 1
-#define R_IRQ_READ2__dma5_descr__active 1
-#define R_IRQ_READ2__dma5_descr__inactive 0
-#define R_IRQ_READ2__dma4_eop__BITNR 9
-#define R_IRQ_READ2__dma4_eop__WIDTH 1
-#define R_IRQ_READ2__dma4_eop__active 1
-#define R_IRQ_READ2__dma4_eop__inactive 0
-#define R_IRQ_READ2__dma4_descr__BITNR 8
-#define R_IRQ_READ2__dma4_descr__WIDTH 1
-#define R_IRQ_READ2__dma4_descr__active 1
-#define R_IRQ_READ2__dma4_descr__inactive 0
-#define R_IRQ_READ2__dma3_eop__BITNR 7
-#define R_IRQ_READ2__dma3_eop__WIDTH 1
-#define R_IRQ_READ2__dma3_eop__active 1
-#define R_IRQ_READ2__dma3_eop__inactive 0
-#define R_IRQ_READ2__dma3_descr__BITNR 6
-#define R_IRQ_READ2__dma3_descr__WIDTH 1
-#define R_IRQ_READ2__dma3_descr__active 1
-#define R_IRQ_READ2__dma3_descr__inactive 0
-#define R_IRQ_READ2__dma2_eop__BITNR 5
-#define R_IRQ_READ2__dma2_eop__WIDTH 1
-#define R_IRQ_READ2__dma2_eop__active 1
-#define R_IRQ_READ2__dma2_eop__inactive 0
-#define R_IRQ_READ2__dma2_descr__BITNR 4
-#define R_IRQ_READ2__dma2_descr__WIDTH 1
-#define R_IRQ_READ2__dma2_descr__active 1
-#define R_IRQ_READ2__dma2_descr__inactive 0
-#define R_IRQ_READ2__dma1_eop__BITNR 3
-#define R_IRQ_READ2__dma1_eop__WIDTH 1
-#define R_IRQ_READ2__dma1_eop__active 1
-#define R_IRQ_READ2__dma1_eop__inactive 0
-#define R_IRQ_READ2__dma1_descr__BITNR 2
-#define R_IRQ_READ2__dma1_descr__WIDTH 1
-#define R_IRQ_READ2__dma1_descr__active 1
-#define R_IRQ_READ2__dma1_descr__inactive 0
-#define R_IRQ_READ2__dma0_eop__BITNR 1
-#define R_IRQ_READ2__dma0_eop__WIDTH 1
-#define R_IRQ_READ2__dma0_eop__active 1
-#define R_IRQ_READ2__dma0_eop__inactive 0
-#define R_IRQ_READ2__dma0_descr__BITNR 0
-#define R_IRQ_READ2__dma0_descr__WIDTH 1
-#define R_IRQ_READ2__dma0_descr__active 1
-#define R_IRQ_READ2__dma0_descr__inactive 0
-
-#define R_IRQ_MASK2_SET (IO_TYPECAST_UDWORD 0xb00000d4)
-#define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23
-#define R_IRQ_MASK2_SET__dma8_sub3_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_sub3_descr__set 1
-#define R_IRQ_MASK2_SET__dma8_sub3_descr__nop 0
-#define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22
-#define R_IRQ_MASK2_SET__dma8_sub2_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_sub2_descr__set 1
-#define R_IRQ_MASK2_SET__dma8_sub2_descr__nop 0
-#define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21
-#define R_IRQ_MASK2_SET__dma8_sub1_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_sub1_descr__set 1
-#define R_IRQ_MASK2_SET__dma8_sub1_descr__nop 0
-#define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20
-#define R_IRQ_MASK2_SET__dma8_sub0_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_sub0_descr__set 1
-#define R_IRQ_MASK2_SET__dma8_sub0_descr__nop 0
-#define R_IRQ_MASK2_SET__dma9_eop__BITNR 19
-#define R_IRQ_MASK2_SET__dma9_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma9_eop__set 1
-#define R_IRQ_MASK2_SET__dma9_eop__nop 0
-#define R_IRQ_MASK2_SET__dma9_descr__BITNR 18
-#define R_IRQ_MASK2_SET__dma9_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma9_descr__set 1
-#define R_IRQ_MASK2_SET__dma9_descr__nop 0
-#define R_IRQ_MASK2_SET__dma8_eop__BITNR 17
-#define R_IRQ_MASK2_SET__dma8_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_eop__set 1
-#define R_IRQ_MASK2_SET__dma8_eop__nop 0
-#define R_IRQ_MASK2_SET__dma8_descr__BITNR 16
-#define R_IRQ_MASK2_SET__dma8_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_descr__set 1
-#define R_IRQ_MASK2_SET__dma8_descr__nop 0
-#define R_IRQ_MASK2_SET__dma7_eop__BITNR 15
-#define R_IRQ_MASK2_SET__dma7_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma7_eop__set 1
-#define R_IRQ_MASK2_SET__dma7_eop__nop 0
-#define R_IRQ_MASK2_SET__dma7_descr__BITNR 14
-#define R_IRQ_MASK2_SET__dma7_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma7_descr__set 1
-#define R_IRQ_MASK2_SET__dma7_descr__nop 0
-#define R_IRQ_MASK2_SET__dma6_eop__BITNR 13
-#define R_IRQ_MASK2_SET__dma6_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma6_eop__set 1
-#define R_IRQ_MASK2_SET__dma6_eop__nop 0
-#define R_IRQ_MASK2_SET__dma6_descr__BITNR 12
-#define R_IRQ_MASK2_SET__dma6_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma6_descr__set 1
-#define R_IRQ_MASK2_SET__dma6_descr__nop 0
-#define R_IRQ_MASK2_SET__dma5_eop__BITNR 11
-#define R_IRQ_MASK2_SET__dma5_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma5_eop__set 1
-#define R_IRQ_MASK2_SET__dma5_eop__nop 0
-#define R_IRQ_MASK2_SET__dma5_descr__BITNR 10
-#define R_IRQ_MASK2_SET__dma5_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma5_descr__set 1
-#define R_IRQ_MASK2_SET__dma5_descr__nop 0
-#define R_IRQ_MASK2_SET__dma4_eop__BITNR 9
-#define R_IRQ_MASK2_SET__dma4_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma4_eop__set 1
-#define R_IRQ_MASK2_SET__dma4_eop__nop 0
-#define R_IRQ_MASK2_SET__dma4_descr__BITNR 8
-#define R_IRQ_MASK2_SET__dma4_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma4_descr__set 1
-#define R_IRQ_MASK2_SET__dma4_descr__nop 0
-#define R_IRQ_MASK2_SET__dma3_eop__BITNR 7
-#define R_IRQ_MASK2_SET__dma3_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma3_eop__set 1
-#define R_IRQ_MASK2_SET__dma3_eop__nop 0
-#define R_IRQ_MASK2_SET__dma3_descr__BITNR 6
-#define R_IRQ_MASK2_SET__dma3_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma3_descr__set 1
-#define R_IRQ_MASK2_SET__dma3_descr__nop 0
-#define R_IRQ_MASK2_SET__dma2_eop__BITNR 5
-#define R_IRQ_MASK2_SET__dma2_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma2_eop__set 1
-#define R_IRQ_MASK2_SET__dma2_eop__nop 0
-#define R_IRQ_MASK2_SET__dma2_descr__BITNR 4
-#define R_IRQ_MASK2_SET__dma2_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma2_descr__set 1
-#define R_IRQ_MASK2_SET__dma2_descr__nop 0
-#define R_IRQ_MASK2_SET__dma1_eop__BITNR 3
-#define R_IRQ_MASK2_SET__dma1_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma1_eop__set 1
-#define R_IRQ_MASK2_SET__dma1_eop__nop 0
-#define R_IRQ_MASK2_SET__dma1_descr__BITNR 2
-#define R_IRQ_MASK2_SET__dma1_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma1_descr__set 1
-#define R_IRQ_MASK2_SET__dma1_descr__nop 0
-#define R_IRQ_MASK2_SET__dma0_eop__BITNR 1
-#define R_IRQ_MASK2_SET__dma0_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma0_eop__set 1
-#define R_IRQ_MASK2_SET__dma0_eop__nop 0
-#define R_IRQ_MASK2_SET__dma0_descr__BITNR 0
-#define R_IRQ_MASK2_SET__dma0_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma0_descr__set 1
-#define R_IRQ_MASK2_SET__dma0_descr__nop 0
-
-#define R_VECT_MASK_RD (IO_TYPECAST_RO_UDWORD 0xb00000d8)
-#define R_VECT_MASK_RD__usb__BITNR 31
-#define R_VECT_MASK_RD__usb__WIDTH 1
-#define R_VECT_MASK_RD__usb__active 1
-#define R_VECT_MASK_RD__usb__inactive 0
-#define R_VECT_MASK_RD__dma9__BITNR 25
-#define R_VECT_MASK_RD__dma9__WIDTH 1
-#define R_VECT_MASK_RD__dma9__active 1
-#define R_VECT_MASK_RD__dma9__inactive 0
-#define R_VECT_MASK_RD__dma8__BITNR 24
-#define R_VECT_MASK_RD__dma8__WIDTH 1
-#define R_VECT_MASK_RD__dma8__active 1
-#define R_VECT_MASK_RD__dma8__inactive 0
-#define R_VECT_MASK_RD__dma7__BITNR 23
-#define R_VECT_MASK_RD__dma7__WIDTH 1
-#define R_VECT_MASK_RD__dma7__active 1
-#define R_VECT_MASK_RD__dma7__inactive 0
-#define R_VECT_MASK_RD__dma6__BITNR 22
-#define R_VECT_MASK_RD__dma6__WIDTH 1
-#define R_VECT_MASK_RD__dma6__active 1
-#define R_VECT_MASK_RD__dma6__inactive 0
-#define R_VECT_MASK_RD__dma5__BITNR 21
-#define R_VECT_MASK_RD__dma5__WIDTH 1
-#define R_VECT_MASK_RD__dma5__active 1
-#define R_VECT_MASK_RD__dma5__inactive 0
-#define R_VECT_MASK_RD__dma4__BITNR 20
-#define R_VECT_MASK_RD__dma4__WIDTH 1
-#define R_VECT_MASK_RD__dma4__active 1
-#define R_VECT_MASK_RD__dma4__inactive 0
-#define R_VECT_MASK_RD__dma3__BITNR 19
-#define R_VECT_MASK_RD__dma3__WIDTH 1
-#define R_VECT_MASK_RD__dma3__active 1
-#define R_VECT_MASK_RD__dma3__inactive 0
-#define R_VECT_MASK_RD__dma2__BITNR 18
-#define R_VECT_MASK_RD__dma2__WIDTH 1
-#define R_VECT_MASK_RD__dma2__active 1
-#define R_VECT_MASK_RD__dma2__inactive 0
-#define R_VECT_MASK_RD__dma1__BITNR 17
-#define R_VECT_MASK_RD__dma1__WIDTH 1
-#define R_VECT_MASK_RD__dma1__active 1
-#define R_VECT_MASK_RD__dma1__inactive 0
-#define R_VECT_MASK_RD__dma0__BITNR 16
-#define R_VECT_MASK_RD__dma0__WIDTH 1
-#define R_VECT_MASK_RD__dma0__active 1
-#define R_VECT_MASK_RD__dma0__inactive 0
-#define R_VECT_MASK_RD__ext_dma1__BITNR 13
-#define R_VECT_MASK_RD__ext_dma1__WIDTH 1
-#define R_VECT_MASK_RD__ext_dma1__active 1
-#define R_VECT_MASK_RD__ext_dma1__inactive 0
-#define R_VECT_MASK_RD__ext_dma0__BITNR 12
-#define R_VECT_MASK_RD__ext_dma0__WIDTH 1
-#define R_VECT_MASK_RD__ext_dma0__active 1
-#define R_VECT_MASK_RD__ext_dma0__inactive 0
-#define R_VECT_MASK_RD__pa__BITNR 11
-#define R_VECT_MASK_RD__pa__WIDTH 1
-#define R_VECT_MASK_RD__pa__active 1
-#define R_VECT_MASK_RD__pa__inactive 0
-#define R_VECT_MASK_RD__irq_intnr__BITNR 10
-#define R_VECT_MASK_RD__irq_intnr__WIDTH 1
-#define R_VECT_MASK_RD__irq_intnr__active 1
-#define R_VECT_MASK_RD__irq_intnr__inactive 0
-#define R_VECT_MASK_RD__sw__BITNR 9
-#define R_VECT_MASK_RD__sw__WIDTH 1
-#define R_VECT_MASK_RD__sw__active 1
-#define R_VECT_MASK_RD__sw__inactive 0
-#define R_VECT_MASK_RD__serial__BITNR 8
-#define R_VECT_MASK_RD__serial__WIDTH 1
-#define R_VECT_MASK_RD__serial__active 1
-#define R_VECT_MASK_RD__serial__inactive 0
-#define R_VECT_MASK_RD__snmp__BITNR 7
-#define R_VECT_MASK_RD__snmp__WIDTH 1
-#define R_VECT_MASK_RD__snmp__active 1
-#define R_VECT_MASK_RD__snmp__inactive 0
-#define R_VECT_MASK_RD__network__BITNR 6
-#define R_VECT_MASK_RD__network__WIDTH 1
-#define R_VECT_MASK_RD__network__active 1
-#define R_VECT_MASK_RD__network__inactive 0
-#define R_VECT_MASK_RD__scsi1__BITNR 5
-#define R_VECT_MASK_RD__scsi1__WIDTH 1
-#define R_VECT_MASK_RD__scsi1__active 1
-#define R_VECT_MASK_RD__scsi1__inactive 0
-#define R_VECT_MASK_RD__par1__BITNR 5
-#define R_VECT_MASK_RD__par1__WIDTH 1
-#define R_VECT_MASK_RD__par1__active 1
-#define R_VECT_MASK_RD__par1__inactive 0
-#define R_VECT_MASK_RD__scsi0__BITNR 4
-#define R_VECT_MASK_RD__scsi0__WIDTH 1
-#define R_VECT_MASK_RD__scsi0__active 1
-#define R_VECT_MASK_RD__scsi0__inactive 0
-#define R_VECT_MASK_RD__par0__BITNR 4
-#define R_VECT_MASK_RD__par0__WIDTH 1
-#define R_VECT_MASK_RD__par0__active 1
-#define R_VECT_MASK_RD__par0__inactive 0
-#define R_VECT_MASK_RD__ata__BITNR 4
-#define R_VECT_MASK_RD__ata__WIDTH 1
-#define R_VECT_MASK_RD__ata__active 1
-#define R_VECT_MASK_RD__ata__inactive 0
-#define R_VECT_MASK_RD__mio__BITNR 4
-#define R_VECT_MASK_RD__mio__WIDTH 1
-#define R_VECT_MASK_RD__mio__active 1
-#define R_VECT_MASK_RD__mio__inactive 0
-#define R_VECT_MASK_RD__timer1__BITNR 3
-#define R_VECT_MASK_RD__timer1__WIDTH 1
-#define R_VECT_MASK_RD__timer1__active 1
-#define R_VECT_MASK_RD__timer1__inactive 0
-#define R_VECT_MASK_RD__timer0__BITNR 2
-#define R_VECT_MASK_RD__timer0__WIDTH 1
-#define R_VECT_MASK_RD__timer0__active 1
-#define R_VECT_MASK_RD__timer0__inactive 0
-#define R_VECT_MASK_RD__nmi__BITNR 1
-#define R_VECT_MASK_RD__nmi__WIDTH 1
-#define R_VECT_MASK_RD__nmi__active 1
-#define R_VECT_MASK_RD__nmi__inactive 0
-#define R_VECT_MASK_RD__some__BITNR 0
-#define R_VECT_MASK_RD__some__WIDTH 1
-#define R_VECT_MASK_RD__some__active 1
-#define R_VECT_MASK_RD__some__inactive 0
-
-#define R_VECT_MASK_CLR (IO_TYPECAST_UDWORD 0xb00000d8)
-#define R_VECT_MASK_CLR__usb__BITNR 31
-#define R_VECT_MASK_CLR__usb__WIDTH 1
-#define R_VECT_MASK_CLR__usb__clr 1
-#define R_VECT_MASK_CLR__usb__nop 0
-#define R_VECT_MASK_CLR__dma9__BITNR 25
-#define R_VECT_MASK_CLR__dma9__WIDTH 1
-#define R_VECT_MASK_CLR__dma9__clr 1
-#define R_VECT_MASK_CLR__dma9__nop 0
-#define R_VECT_MASK_CLR__dma8__BITNR 24
-#define R_VECT_MASK_CLR__dma8__WIDTH 1
-#define R_VECT_MASK_CLR__dma8__clr 1
-#define R_VECT_MASK_CLR__dma8__nop 0
-#define R_VECT_MASK_CLR__dma7__BITNR 23
-#define R_VECT_MASK_CLR__dma7__WIDTH 1
-#define R_VECT_MASK_CLR__dma7__clr 1
-#define R_VECT_MASK_CLR__dma7__nop 0
-#define R_VECT_MASK_CLR__dma6__BITNR 22
-#define R_VECT_MASK_CLR__dma6__WIDTH 1
-#define R_VECT_MASK_CLR__dma6__clr 1
-#define R_VECT_MASK_CLR__dma6__nop 0
-#define R_VECT_MASK_CLR__dma5__BITNR 21
-#define R_VECT_MASK_CLR__dma5__WIDTH 1
-#define R_VECT_MASK_CLR__dma5__clr 1
-#define R_VECT_MASK_CLR__dma5__nop 0
-#define R_VECT_MASK_CLR__dma4__BITNR 20
-#define R_VECT_MASK_CLR__dma4__WIDTH 1
-#define R_VECT_MASK_CLR__dma4__clr 1
-#define R_VECT_MASK_CLR__dma4__nop 0
-#define R_VECT_MASK_CLR__dma3__BITNR 19
-#define R_VECT_MASK_CLR__dma3__WIDTH 1
-#define R_VECT_MASK_CLR__dma3__clr 1
-#define R_VECT_MASK_CLR__dma3__nop 0
-#define R_VECT_MASK_CLR__dma2__BITNR 18
-#define R_VECT_MASK_CLR__dma2__WIDTH 1
-#define R_VECT_MASK_CLR__dma2__clr 1
-#define R_VECT_MASK_CLR__dma2__nop 0
-#define R_VECT_MASK_CLR__dma1__BITNR 17
-#define R_VECT_MASK_CLR__dma1__WIDTH 1
-#define R_VECT_MASK_CLR__dma1__clr 1
-#define R_VECT_MASK_CLR__dma1__nop 0
-#define R_VECT_MASK_CLR__dma0__BITNR 16
-#define R_VECT_MASK_CLR__dma0__WIDTH 1
-#define R_VECT_MASK_CLR__dma0__clr 1
-#define R_VECT_MASK_CLR__dma0__nop 0
-#define R_VECT_MASK_CLR__ext_dma1__BITNR 13
-#define R_VECT_MASK_CLR__ext_dma1__WIDTH 1
-#define R_VECT_MASK_CLR__ext_dma1__clr 1
-#define R_VECT_MASK_CLR__ext_dma1__nop 0
-#define R_VECT_MASK_CLR__ext_dma0__BITNR 12
-#define R_VECT_MASK_CLR__ext_dma0__WIDTH 1
-#define R_VECT_MASK_CLR__ext_dma0__clr 1
-#define R_VECT_MASK_CLR__ext_dma0__nop 0
-#define R_VECT_MASK_CLR__pa__BITNR 11
-#define R_VECT_MASK_CLR__pa__WIDTH 1
-#define R_VECT_MASK_CLR__pa__clr 1
-#define R_VECT_MASK_CLR__pa__nop 0
-#define R_VECT_MASK_CLR__irq_intnr__BITNR 10
-#define R_VECT_MASK_CLR__irq_intnr__WIDTH 1
-#define R_VECT_MASK_CLR__irq_intnr__clr 1
-#define R_VECT_MASK_CLR__irq_intnr__nop 0
-#define R_VECT_MASK_CLR__sw__BITNR 9
-#define R_VECT_MASK_CLR__sw__WIDTH 1
-#define R_VECT_MASK_CLR__sw__clr 1
-#define R_VECT_MASK_CLR__sw__nop 0
-#define R_VECT_MASK_CLR__serial__BITNR 8
-#define R_VECT_MASK_CLR__serial__WIDTH 1
-#define R_VECT_MASK_CLR__serial__clr 1
-#define R_VECT_MASK_CLR__serial__nop 0
-#define R_VECT_MASK_CLR__snmp__BITNR 7
-#define R_VECT_MASK_CLR__snmp__WIDTH 1
-#define R_VECT_MASK_CLR__snmp__clr 1
-#define R_VECT_MASK_CLR__snmp__nop 0
-#define R_VECT_MASK_CLR__network__BITNR 6
-#define R_VECT_MASK_CLR__network__WIDTH 1
-#define R_VECT_MASK_CLR__network__clr 1
-#define R_VECT_MASK_CLR__network__nop 0
-#define R_VECT_MASK_CLR__scsi1__BITNR 5
-#define R_VECT_MASK_CLR__scsi1__WIDTH 1
-#define R_VECT_MASK_CLR__scsi1__clr 1
-#define R_VECT_MASK_CLR__scsi1__nop 0
-#define R_VECT_MASK_CLR__par1__BITNR 5
-#define R_VECT_MASK_CLR__par1__WIDTH 1
-#define R_VECT_MASK_CLR__par1__clr 1
-#define R_VECT_MASK_CLR__par1__nop 0
-#define R_VECT_MASK_CLR__scsi0__BITNR 4
-#define R_VECT_MASK_CLR__scsi0__WIDTH 1
-#define R_VECT_MASK_CLR__scsi0__clr 1
-#define R_VECT_MASK_CLR__scsi0__nop 0
-#define R_VECT_MASK_CLR__par0__BITNR 4
-#define R_VECT_MASK_CLR__par0__WIDTH 1
-#define R_VECT_MASK_CLR__par0__clr 1
-#define R_VECT_MASK_CLR__par0__nop 0
-#define R_VECT_MASK_CLR__ata__BITNR 4
-#define R_VECT_MASK_CLR__ata__WIDTH 1
-#define R_VECT_MASK_CLR__ata__clr 1
-#define R_VECT_MASK_CLR__ata__nop 0
-#define R_VECT_MASK_CLR__mio__BITNR 4
-#define R_VECT_MASK_CLR__mio__WIDTH 1
-#define R_VECT_MASK_CLR__mio__clr 1
-#define R_VECT_MASK_CLR__mio__nop 0
-#define R_VECT_MASK_CLR__timer1__BITNR 3
-#define R_VECT_MASK_CLR__timer1__WIDTH 1
-#define R_VECT_MASK_CLR__timer1__clr 1
-#define R_VECT_MASK_CLR__timer1__nop 0
-#define R_VECT_MASK_CLR__timer0__BITNR 2
-#define R_VECT_MASK_CLR__timer0__WIDTH 1
-#define R_VECT_MASK_CLR__timer0__clr 1
-#define R_VECT_MASK_CLR__timer0__nop 0
-#define R_VECT_MASK_CLR__nmi__BITNR 1
-#define R_VECT_MASK_CLR__nmi__WIDTH 1
-#define R_VECT_MASK_CLR__nmi__clr 1
-#define R_VECT_MASK_CLR__nmi__nop 0
-#define R_VECT_MASK_CLR__some__BITNR 0
-#define R_VECT_MASK_CLR__some__WIDTH 1
-#define R_VECT_MASK_CLR__some__clr 1
-#define R_VECT_MASK_CLR__some__nop 0
-
-#define R_VECT_READ (IO_TYPECAST_RO_UDWORD 0xb00000dc)
-#define R_VECT_READ__usb__BITNR 31
-#define R_VECT_READ__usb__WIDTH 1
-#define R_VECT_READ__usb__active 1
-#define R_VECT_READ__usb__inactive 0
-#define R_VECT_READ__dma9__BITNR 25
-#define R_VECT_READ__dma9__WIDTH 1
-#define R_VECT_READ__dma9__active 1
-#define R_VECT_READ__dma9__inactive 0
-#define R_VECT_READ__dma8__BITNR 24
-#define R_VECT_READ__dma8__WIDTH 1
-#define R_VECT_READ__dma8__active 1
-#define R_VECT_READ__dma8__inactive 0
-#define R_VECT_READ__dma7__BITNR 23
-#define R_VECT_READ__dma7__WIDTH 1
-#define R_VECT_READ__dma7__active 1
-#define R_VECT_READ__dma7__inactive 0
-#define R_VECT_READ__dma6__BITNR 22
-#define R_VECT_READ__dma6__WIDTH 1
-#define R_VECT_READ__dma6__active 1
-#define R_VECT_READ__dma6__inactive 0
-#define R_VECT_READ__dma5__BITNR 21
-#define R_VECT_READ__dma5__WIDTH 1
-#define R_VECT_READ__dma5__active 1
-#define R_VECT_READ__dma5__inactive 0
-#define R_VECT_READ__dma4__BITNR 20
-#define R_VECT_READ__dma4__WIDTH 1
-#define R_VECT_READ__dma4__active 1
-#define R_VECT_READ__dma4__inactive 0
-#define R_VECT_READ__dma3__BITNR 19
-#define R_VECT_READ__dma3__WIDTH 1
-#define R_VECT_READ__dma3__active 1
-#define R_VECT_READ__dma3__inactive 0
-#define R_VECT_READ__dma2__BITNR 18
-#define R_VECT_READ__dma2__WIDTH 1
-#define R_VECT_READ__dma2__active 1
-#define R_VECT_READ__dma2__inactive 0
-#define R_VECT_READ__dma1__BITNR 17
-#define R_VECT_READ__dma1__WIDTH 1
-#define R_VECT_READ__dma1__active 1
-#define R_VECT_READ__dma1__inactive 0
-#define R_VECT_READ__dma0__BITNR 16
-#define R_VECT_READ__dma0__WIDTH 1
-#define R_VECT_READ__dma0__active 1
-#define R_VECT_READ__dma0__inactive 0
-#define R_VECT_READ__ext_dma1__BITNR 13
-#define R_VECT_READ__ext_dma1__WIDTH 1
-#define R_VECT_READ__ext_dma1__active 1
-#define R_VECT_READ__ext_dma1__inactive 0
-#define R_VECT_READ__ext_dma0__BITNR 12
-#define R_VECT_READ__ext_dma0__WIDTH 1
-#define R_VECT_READ__ext_dma0__active 1
-#define R_VECT_READ__ext_dma0__inactive 0
-#define R_VECT_READ__pa__BITNR 11
-#define R_VECT_READ__pa__WIDTH 1
-#define R_VECT_READ__pa__active 1
-#define R_VECT_READ__pa__inactive 0
-#define R_VECT_READ__irq_intnr__BITNR 10
-#define R_VECT_READ__irq_intnr__WIDTH 1
-#define R_VECT_READ__irq_intnr__active 1
-#define R_VECT_READ__irq_intnr__inactive 0
-#define R_VECT_READ__sw__BITNR 9
-#define R_VECT_READ__sw__WIDTH 1
-#define R_VECT_READ__sw__active 1
-#define R_VECT_READ__sw__inactive 0
-#define R_VECT_READ__serial__BITNR 8
-#define R_VECT_READ__serial__WIDTH 1
-#define R_VECT_READ__serial__active 1
-#define R_VECT_READ__serial__inactive 0
-#define R_VECT_READ__snmp__BITNR 7
-#define R_VECT_READ__snmp__WIDTH 1
-#define R_VECT_READ__snmp__active 1
-#define R_VECT_READ__snmp__inactive 0
-#define R_VECT_READ__network__BITNR 6
-#define R_VECT_READ__network__WIDTH 1
-#define R_VECT_READ__network__active 1
-#define R_VECT_READ__network__inactive 0
-#define R_VECT_READ__scsi1__BITNR 5
-#define R_VECT_READ__scsi1__WIDTH 1
-#define R_VECT_READ__scsi1__active 1
-#define R_VECT_READ__scsi1__inactive 0
-#define R_VECT_READ__par1__BITNR 5
-#define R_VECT_READ__par1__WIDTH 1
-#define R_VECT_READ__par1__active 1
-#define R_VECT_READ__par1__inactive 0
-#define R_VECT_READ__scsi0__BITNR 4
-#define R_VECT_READ__scsi0__WIDTH 1
-#define R_VECT_READ__scsi0__active 1
-#define R_VECT_READ__scsi0__inactive 0
-#define R_VECT_READ__par0__BITNR 4
-#define R_VECT_READ__par0__WIDTH 1
-#define R_VECT_READ__par0__active 1
-#define R_VECT_READ__par0__inactive 0
-#define R_VECT_READ__ata__BITNR 4
-#define R_VECT_READ__ata__WIDTH 1
-#define R_VECT_READ__ata__active 1
-#define R_VECT_READ__ata__inactive 0
-#define R_VECT_READ__mio__BITNR 4
-#define R_VECT_READ__mio__WIDTH 1
-#define R_VECT_READ__mio__active 1
-#define R_VECT_READ__mio__inactive 0
-#define R_VECT_READ__timer1__BITNR 3
-#define R_VECT_READ__timer1__WIDTH 1
-#define R_VECT_READ__timer1__active 1
-#define R_VECT_READ__timer1__inactive 0
-#define R_VECT_READ__timer0__BITNR 2
-#define R_VECT_READ__timer0__WIDTH 1
-#define R_VECT_READ__timer0__active 1
-#define R_VECT_READ__timer0__inactive 0
-#define R_VECT_READ__nmi__BITNR 1
-#define R_VECT_READ__nmi__WIDTH 1
-#define R_VECT_READ__nmi__active 1
-#define R_VECT_READ__nmi__inactive 0
-#define R_VECT_READ__some__BITNR 0
-#define R_VECT_READ__some__WIDTH 1
-#define R_VECT_READ__some__active 1
-#define R_VECT_READ__some__inactive 0
-
-#define R_VECT_MASK_SET (IO_TYPECAST_UDWORD 0xb00000dc)
-#define R_VECT_MASK_SET__usb__BITNR 31
-#define R_VECT_MASK_SET__usb__WIDTH 1
-#define R_VECT_MASK_SET__usb__set 1
-#define R_VECT_MASK_SET__usb__nop 0
-#define R_VECT_MASK_SET__dma9__BITNR 25
-#define R_VECT_MASK_SET__dma9__WIDTH 1
-#define R_VECT_MASK_SET__dma9__set 1
-#define R_VECT_MASK_SET__dma9__nop 0
-#define R_VECT_MASK_SET__dma8__BITNR 24
-#define R_VECT_MASK_SET__dma8__WIDTH 1
-#define R_VECT_MASK_SET__dma8__set 1
-#define R_VECT_MASK_SET__dma8__nop 0
-#define R_VECT_MASK_SET__dma7__BITNR 23
-#define R_VECT_MASK_SET__dma7__WIDTH 1
-#define R_VECT_MASK_SET__dma7__set 1
-#define R_VECT_MASK_SET__dma7__nop 0
-#define R_VECT_MASK_SET__dma6__BITNR 22
-#define R_VECT_MASK_SET__dma6__WIDTH 1
-#define R_VECT_MASK_SET__dma6__set 1
-#define R_VECT_MASK_SET__dma6__nop 0
-#define R_VECT_MASK_SET__dma5__BITNR 21
-#define R_VECT_MASK_SET__dma5__WIDTH 1
-#define R_VECT_MASK_SET__dma5__set 1
-#define R_VECT_MASK_SET__dma5__nop 0
-#define R_VECT_MASK_SET__dma4__BITNR 20
-#define R_VECT_MASK_SET__dma4__WIDTH 1
-#define R_VECT_MASK_SET__dma4__set 1
-#define R_VECT_MASK_SET__dma4__nop 0
-#define R_VECT_MASK_SET__dma3__BITNR 19
-#define R_VECT_MASK_SET__dma3__WIDTH 1
-#define R_VECT_MASK_SET__dma3__set 1
-#define R_VECT_MASK_SET__dma3__nop 0
-#define R_VECT_MASK_SET__dma2__BITNR 18
-#define R_VECT_MASK_SET__dma2__WIDTH 1
-#define R_VECT_MASK_SET__dma2__set 1
-#define R_VECT_MASK_SET__dma2__nop 0
-#define R_VECT_MASK_SET__dma1__BITNR 17
-#define R_VECT_MASK_SET__dma1__WIDTH 1
-#define R_VECT_MASK_SET__dma1__set 1
-#define R_VECT_MASK_SET__dma1__nop 0
-#define R_VECT_MASK_SET__dma0__BITNR 16
-#define R_VECT_MASK_SET__dma0__WIDTH 1
-#define R_VECT_MASK_SET__dma0__set 1
-#define R_VECT_MASK_SET__dma0__nop 0
-#define R_VECT_MASK_SET__ext_dma1__BITNR 13
-#define R_VECT_MASK_SET__ext_dma1__WIDTH 1
-#define R_VECT_MASK_SET__ext_dma1__set 1
-#define R_VECT_MASK_SET__ext_dma1__nop 0
-#define R_VECT_MASK_SET__ext_dma0__BITNR 12
-#define R_VECT_MASK_SET__ext_dma0__WIDTH 1
-#define R_VECT_MASK_SET__ext_dma0__set 1
-#define R_VECT_MASK_SET__ext_dma0__nop 0
-#define R_VECT_MASK_SET__pa__BITNR 11
-#define R_VECT_MASK_SET__pa__WIDTH 1
-#define R_VECT_MASK_SET__pa__set 1
-#define R_VECT_MASK_SET__pa__nop 0
-#define R_VECT_MASK_SET__irq_intnr__BITNR 10
-#define R_VECT_MASK_SET__irq_intnr__WIDTH 1
-#define R_VECT_MASK_SET__irq_intnr__set 1
-#define R_VECT_MASK_SET__irq_intnr__nop 0
-#define R_VECT_MASK_SET__sw__BITNR 9
-#define R_VECT_MASK_SET__sw__WIDTH 1
-#define R_VECT_MASK_SET__sw__set 1
-#define R_VECT_MASK_SET__sw__nop 0
-#define R_VECT_MASK_SET__serial__BITNR 8
-#define R_VECT_MASK_SET__serial__WIDTH 1
-#define R_VECT_MASK_SET__serial__set 1
-#define R_VECT_MASK_SET__serial__nop 0
-#define R_VECT_MASK_SET__snmp__BITNR 7
-#define R_VECT_MASK_SET__snmp__WIDTH 1
-#define R_VECT_MASK_SET__snmp__set 1
-#define R_VECT_MASK_SET__snmp__nop 0
-#define R_VECT_MASK_SET__network__BITNR 6
-#define R_VECT_MASK_SET__network__WIDTH 1
-#define R_VECT_MASK_SET__network__set 1
-#define R_VECT_MASK_SET__network__nop 0
-#define R_VECT_MASK_SET__scsi1__BITNR 5
-#define R_VECT_MASK_SET__scsi1__WIDTH 1
-#define R_VECT_MASK_SET__scsi1__set 1
-#define R_VECT_MASK_SET__scsi1__nop 0
-#define R_VECT_MASK_SET__par1__BITNR 5
-#define R_VECT_MASK_SET__par1__WIDTH 1
-#define R_VECT_MASK_SET__par1__set 1
-#define R_VECT_MASK_SET__par1__nop 0
-#define R_VECT_MASK_SET__scsi0__BITNR 4
-#define R_VECT_MASK_SET__scsi0__WIDTH 1
-#define R_VECT_MASK_SET__scsi0__set 1
-#define R_VECT_MASK_SET__scsi0__nop 0
-#define R_VECT_MASK_SET__par0__BITNR 4
-#define R_VECT_MASK_SET__par0__WIDTH 1
-#define R_VECT_MASK_SET__par0__set 1
-#define R_VECT_MASK_SET__par0__nop 0
-#define R_VECT_MASK_SET__ata__BITNR 4
-#define R_VECT_MASK_SET__ata__WIDTH 1
-#define R_VECT_MASK_SET__ata__set 1
-#define R_VECT_MASK_SET__ata__nop 0
-#define R_VECT_MASK_SET__mio__BITNR 4
-#define R_VECT_MASK_SET__mio__WIDTH 1
-#define R_VECT_MASK_SET__mio__set 1
-#define R_VECT_MASK_SET__mio__nop 0
-#define R_VECT_MASK_SET__timer1__BITNR 3
-#define R_VECT_MASK_SET__timer1__WIDTH 1
-#define R_VECT_MASK_SET__timer1__set 1
-#define R_VECT_MASK_SET__timer1__nop 0
-#define R_VECT_MASK_SET__timer0__BITNR 2
-#define R_VECT_MASK_SET__timer0__WIDTH 1
-#define R_VECT_MASK_SET__timer0__set 1
-#define R_VECT_MASK_SET__timer0__nop 0
-#define R_VECT_MASK_SET__nmi__BITNR 1
-#define R_VECT_MASK_SET__nmi__WIDTH 1
-#define R_VECT_MASK_SET__nmi__set 1
-#define R_VECT_MASK_SET__nmi__nop 0
-#define R_VECT_MASK_SET__some__BITNR 0
-#define R_VECT_MASK_SET__some__WIDTH 1
-#define R_VECT_MASK_SET__some__set 1
-#define R_VECT_MASK_SET__some__nop 0
-
-/*
-!* DMA registers
-!*/
-
-#define R_SET_EOP (IO_TYPECAST_UDWORD 0xb000003c)
-#define R_SET_EOP__ch9_eop__BITNR 3
-#define R_SET_EOP__ch9_eop__WIDTH 1
-#define R_SET_EOP__ch9_eop__set 1
-#define R_SET_EOP__ch9_eop__nop 0
-#define R_SET_EOP__ch7_eop__BITNR 2
-#define R_SET_EOP__ch7_eop__WIDTH 1
-#define R_SET_EOP__ch7_eop__set 1
-#define R_SET_EOP__ch7_eop__nop 0
-#define R_SET_EOP__ch5_eop__BITNR 1
-#define R_SET_EOP__ch5_eop__WIDTH 1
-#define R_SET_EOP__ch5_eop__set 1
-#define R_SET_EOP__ch5_eop__nop 0
-#define R_SET_EOP__ch3_eop__BITNR 0
-#define R_SET_EOP__ch3_eop__WIDTH 1
-#define R_SET_EOP__ch3_eop__set 1
-#define R_SET_EOP__ch3_eop__nop 0
-
-#define R_DMA_CH0_HWSW (IO_TYPECAST_UDWORD 0xb0000100)
-#define R_DMA_CH0_HWSW__hw__BITNR 16
-#define R_DMA_CH0_HWSW__hw__WIDTH 16
-#define R_DMA_CH0_HWSW__sw__BITNR 0
-#define R_DMA_CH0_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH0_DESCR (IO_TYPECAST_UDWORD 0xb000010c)
-#define R_DMA_CH0_DESCR__descr__BITNR 0
-#define R_DMA_CH0_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH0_NEXT (IO_TYPECAST_UDWORD 0xb0000104)
-#define R_DMA_CH0_NEXT__next__BITNR 0
-#define R_DMA_CH0_NEXT__next__WIDTH 32
-
-#define R_DMA_CH0_BUF (IO_TYPECAST_UDWORD 0xb0000108)
-#define R_DMA_CH0_BUF__buf__BITNR 0
-#define R_DMA_CH0_BUF__buf__WIDTH 32
-
-#define R_DMA_CH0_FIRST (IO_TYPECAST_UDWORD 0xb00001a0)
-#define R_DMA_CH0_FIRST__first__BITNR 0
-#define R_DMA_CH0_FIRST__first__WIDTH 32
-
-#define R_DMA_CH0_CMD (IO_TYPECAST_BYTE 0xb00001d0)
-#define R_DMA_CH0_CMD__cmd__BITNR 0
-#define R_DMA_CH0_CMD__cmd__WIDTH 3
-#define R_DMA_CH0_CMD__cmd__hold 0
-#define R_DMA_CH0_CMD__cmd__start 1
-#define R_DMA_CH0_CMD__cmd__restart 3
-#define R_DMA_CH0_CMD__cmd__continue 3
-#define R_DMA_CH0_CMD__cmd__reset 4
-
-#define R_DMA_CH0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d1)
-#define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH0_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH0_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH0_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH0_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH0_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH0_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH0_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d2)
-#define R_DMA_CH0_STATUS__avail__BITNR 0
-#define R_DMA_CH0_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH1_HWSW (IO_TYPECAST_UDWORD 0xb0000110)
-#define R_DMA_CH1_HWSW__hw__BITNR 16
-#define R_DMA_CH1_HWSW__hw__WIDTH 16
-#define R_DMA_CH1_HWSW__sw__BITNR 0
-#define R_DMA_CH1_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH1_DESCR (IO_TYPECAST_UDWORD 0xb000011c)
-#define R_DMA_CH1_DESCR__descr__BITNR 0
-#define R_DMA_CH1_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH1_NEXT (IO_TYPECAST_UDWORD 0xb0000114)
-#define R_DMA_CH1_NEXT__next__BITNR 0
-#define R_DMA_CH1_NEXT__next__WIDTH 32
-
-#define R_DMA_CH1_BUF (IO_TYPECAST_UDWORD 0xb0000118)
-#define R_DMA_CH1_BUF__buf__BITNR 0
-#define R_DMA_CH1_BUF__buf__WIDTH 32
-
-#define R_DMA_CH1_FIRST (IO_TYPECAST_UDWORD 0xb00001a4)
-#define R_DMA_CH1_FIRST__first__BITNR 0
-#define R_DMA_CH1_FIRST__first__WIDTH 32
-
-#define R_DMA_CH1_CMD (IO_TYPECAST_BYTE 0xb00001d4)
-#define R_DMA_CH1_CMD__cmd__BITNR 0
-#define R_DMA_CH1_CMD__cmd__WIDTH 3
-#define R_DMA_CH1_CMD__cmd__hold 0
-#define R_DMA_CH1_CMD__cmd__start 1
-#define R_DMA_CH1_CMD__cmd__restart 3
-#define R_DMA_CH1_CMD__cmd__continue 3
-#define R_DMA_CH1_CMD__cmd__reset 4
-
-#define R_DMA_CH1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d5)
-#define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH1_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH1_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH1_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH1_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH1_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH1_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH1_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d6)
-#define R_DMA_CH1_STATUS__avail__BITNR 0
-#define R_DMA_CH1_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH2_HWSW (IO_TYPECAST_UDWORD 0xb0000120)
-#define R_DMA_CH2_HWSW__hw__BITNR 16
-#define R_DMA_CH2_HWSW__hw__WIDTH 16
-#define R_DMA_CH2_HWSW__sw__BITNR 0
-#define R_DMA_CH2_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH2_DESCR (IO_TYPECAST_UDWORD 0xb000012c)
-#define R_DMA_CH2_DESCR__descr__BITNR 0
-#define R_DMA_CH2_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH2_NEXT (IO_TYPECAST_UDWORD 0xb0000124)
-#define R_DMA_CH2_NEXT__next__BITNR 0
-#define R_DMA_CH2_NEXT__next__WIDTH 32
-
-#define R_DMA_CH2_BUF (IO_TYPECAST_UDWORD 0xb0000128)
-#define R_DMA_CH2_BUF__buf__BITNR 0
-#define R_DMA_CH2_BUF__buf__WIDTH 32
-
-#define R_DMA_CH2_FIRST (IO_TYPECAST_UDWORD 0xb00001a8)
-#define R_DMA_CH2_FIRST__first__BITNR 0
-#define R_DMA_CH2_FIRST__first__WIDTH 32
-
-#define R_DMA_CH2_CMD (IO_TYPECAST_BYTE 0xb00001d8)
-#define R_DMA_CH2_CMD__cmd__BITNR 0
-#define R_DMA_CH2_CMD__cmd__WIDTH 3
-#define R_DMA_CH2_CMD__cmd__hold 0
-#define R_DMA_CH2_CMD__cmd__start 1
-#define R_DMA_CH2_CMD__cmd__restart 3
-#define R_DMA_CH2_CMD__cmd__continue 3
-#define R_DMA_CH2_CMD__cmd__reset 4
-
-#define R_DMA_CH2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d9)
-#define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH2_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH2_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH2_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH2_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH2_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH2_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH2_STATUS (IO_TYPECAST_RO_BYTE 0xb00001da)
-#define R_DMA_CH2_STATUS__avail__BITNR 0
-#define R_DMA_CH2_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH3_HWSW (IO_TYPECAST_UDWORD 0xb0000130)
-#define R_DMA_CH3_HWSW__hw__BITNR 16
-#define R_DMA_CH3_HWSW__hw__WIDTH 16
-#define R_DMA_CH3_HWSW__sw__BITNR 0
-#define R_DMA_CH3_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH3_DESCR (IO_TYPECAST_UDWORD 0xb000013c)
-#define R_DMA_CH3_DESCR__descr__BITNR 0
-#define R_DMA_CH3_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH3_NEXT (IO_TYPECAST_UDWORD 0xb0000134)
-#define R_DMA_CH3_NEXT__next__BITNR 0
-#define R_DMA_CH3_NEXT__next__WIDTH 32
-
-#define R_DMA_CH3_BUF (IO_TYPECAST_UDWORD 0xb0000138)
-#define R_DMA_CH3_BUF__buf__BITNR 0
-#define R_DMA_CH3_BUF__buf__WIDTH 32
-
-#define R_DMA_CH3_FIRST (IO_TYPECAST_UDWORD 0xb00001ac)
-#define R_DMA_CH3_FIRST__first__BITNR 0
-#define R_DMA_CH3_FIRST__first__WIDTH 32
-
-#define R_DMA_CH3_CMD (IO_TYPECAST_BYTE 0xb00001dc)
-#define R_DMA_CH3_CMD__cmd__BITNR 0
-#define R_DMA_CH3_CMD__cmd__WIDTH 3
-#define R_DMA_CH3_CMD__cmd__hold 0
-#define R_DMA_CH3_CMD__cmd__start 1
-#define R_DMA_CH3_CMD__cmd__restart 3
-#define R_DMA_CH3_CMD__cmd__continue 3
-#define R_DMA_CH3_CMD__cmd__reset 4
-
-#define R_DMA_CH3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001dd)
-#define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH3_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH3_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH3_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH3_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH3_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH3_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH3_STATUS (IO_TYPECAST_RO_BYTE 0xb00001de)
-#define R_DMA_CH3_STATUS__avail__BITNR 0
-#define R_DMA_CH3_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH4_HWSW (IO_TYPECAST_UDWORD 0xb0000140)
-#define R_DMA_CH4_HWSW__hw__BITNR 16
-#define R_DMA_CH4_HWSW__hw__WIDTH 16
-#define R_DMA_CH4_HWSW__sw__BITNR 0
-#define R_DMA_CH4_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH4_DESCR (IO_TYPECAST_UDWORD 0xb000014c)
-#define R_DMA_CH4_DESCR__descr__BITNR 0
-#define R_DMA_CH4_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH4_NEXT (IO_TYPECAST_UDWORD 0xb0000144)
-#define R_DMA_CH4_NEXT__next__BITNR 0
-#define R_DMA_CH4_NEXT__next__WIDTH 32
-
-#define R_DMA_CH4_BUF (IO_TYPECAST_UDWORD 0xb0000148)
-#define R_DMA_CH4_BUF__buf__BITNR 0
-#define R_DMA_CH4_BUF__buf__WIDTH 32
-
-#define R_DMA_CH4_FIRST (IO_TYPECAST_UDWORD 0xb00001b0)
-#define R_DMA_CH4_FIRST__first__BITNR 0
-#define R_DMA_CH4_FIRST__first__WIDTH 32
-
-#define R_DMA_CH4_CMD (IO_TYPECAST_BYTE 0xb00001e0)
-#define R_DMA_CH4_CMD__cmd__BITNR 0
-#define R_DMA_CH4_CMD__cmd__WIDTH 3
-#define R_DMA_CH4_CMD__cmd__hold 0
-#define R_DMA_CH4_CMD__cmd__start 1
-#define R_DMA_CH4_CMD__cmd__restart 3
-#define R_DMA_CH4_CMD__cmd__continue 3
-#define R_DMA_CH4_CMD__cmd__reset 4
-
-#define R_DMA_CH4_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e1)
-#define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH4_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH4_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH4_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH4_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH4_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH4_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH4_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e2)
-#define R_DMA_CH4_STATUS__avail__BITNR 0
-#define R_DMA_CH4_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH5_HWSW (IO_TYPECAST_UDWORD 0xb0000150)
-#define R_DMA_CH5_HWSW__hw__BITNR 16
-#define R_DMA_CH5_HWSW__hw__WIDTH 16
-#define R_DMA_CH5_HWSW__sw__BITNR 0
-#define R_DMA_CH5_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH5_DESCR (IO_TYPECAST_UDWORD 0xb000015c)
-#define R_DMA_CH5_DESCR__descr__BITNR 0
-#define R_DMA_CH5_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH5_NEXT (IO_TYPECAST_UDWORD 0xb0000154)
-#define R_DMA_CH5_NEXT__next__BITNR 0
-#define R_DMA_CH5_NEXT__next__WIDTH 32
-
-#define R_DMA_CH5_BUF (IO_TYPECAST_UDWORD 0xb0000158)
-#define R_DMA_CH5_BUF__buf__BITNR 0
-#define R_DMA_CH5_BUF__buf__WIDTH 32
-
-#define R_DMA_CH5_FIRST (IO_TYPECAST_UDWORD 0xb00001b4)
-#define R_DMA_CH5_FIRST__first__BITNR 0
-#define R_DMA_CH5_FIRST__first__WIDTH 32
-
-#define R_DMA_CH5_CMD (IO_TYPECAST_BYTE 0xb00001e4)
-#define R_DMA_CH5_CMD__cmd__BITNR 0
-#define R_DMA_CH5_CMD__cmd__WIDTH 3
-#define R_DMA_CH5_CMD__cmd__hold 0
-#define R_DMA_CH5_CMD__cmd__start 1
-#define R_DMA_CH5_CMD__cmd__restart 3
-#define R_DMA_CH5_CMD__cmd__continue 3
-#define R_DMA_CH5_CMD__cmd__reset 4
-
-#define R_DMA_CH5_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e5)
-#define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH5_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH5_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH5_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH5_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH5_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH5_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH5_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e6)
-#define R_DMA_CH5_STATUS__avail__BITNR 0
-#define R_DMA_CH5_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH6_HWSW (IO_TYPECAST_UDWORD 0xb0000160)
-#define R_DMA_CH6_HWSW__hw__BITNR 16
-#define R_DMA_CH6_HWSW__hw__WIDTH 16
-#define R_DMA_CH6_HWSW__sw__BITNR 0
-#define R_DMA_CH6_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH6_DESCR (IO_TYPECAST_UDWORD 0xb000016c)
-#define R_DMA_CH6_DESCR__descr__BITNR 0
-#define R_DMA_CH6_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH6_NEXT (IO_TYPECAST_UDWORD 0xb0000164)
-#define R_DMA_CH6_NEXT__next__BITNR 0
-#define R_DMA_CH6_NEXT__next__WIDTH 32
-
-#define R_DMA_CH6_BUF (IO_TYPECAST_UDWORD 0xb0000168)
-#define R_DMA_CH6_BUF__buf__BITNR 0
-#define R_DMA_CH6_BUF__buf__WIDTH 32
-
-#define R_DMA_CH6_FIRST (IO_TYPECAST_UDWORD 0xb00001b8)
-#define R_DMA_CH6_FIRST__first__BITNR 0
-#define R_DMA_CH6_FIRST__first__WIDTH 32
-
-#define R_DMA_CH6_CMD (IO_TYPECAST_BYTE 0xb00001e8)
-#define R_DMA_CH6_CMD__cmd__BITNR 0
-#define R_DMA_CH6_CMD__cmd__WIDTH 3
-#define R_DMA_CH6_CMD__cmd__hold 0
-#define R_DMA_CH6_CMD__cmd__start 1
-#define R_DMA_CH6_CMD__cmd__restart 3
-#define R_DMA_CH6_CMD__cmd__continue 3
-#define R_DMA_CH6_CMD__cmd__reset 4
-
-#define R_DMA_CH6_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e9)
-#define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH6_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH6_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH6_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH6_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH6_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH6_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH6_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ea)
-#define R_DMA_CH6_STATUS__avail__BITNR 0
-#define R_DMA_CH6_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH7_HWSW (IO_TYPECAST_UDWORD 0xb0000170)
-#define R_DMA_CH7_HWSW__hw__BITNR 16
-#define R_DMA_CH7_HWSW__hw__WIDTH 16
-#define R_DMA_CH7_HWSW__sw__BITNR 0
-#define R_DMA_CH7_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH7_DESCR (IO_TYPECAST_UDWORD 0xb000017c)
-#define R_DMA_CH7_DESCR__descr__BITNR 0
-#define R_DMA_CH7_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH7_NEXT (IO_TYPECAST_UDWORD 0xb0000174)
-#define R_DMA_CH7_NEXT__next__BITNR 0
-#define R_DMA_CH7_NEXT__next__WIDTH 32
-
-#define R_DMA_CH7_BUF (IO_TYPECAST_UDWORD 0xb0000178)
-#define R_DMA_CH7_BUF__buf__BITNR 0
-#define R_DMA_CH7_BUF__buf__WIDTH 32
-
-#define R_DMA_CH7_FIRST (IO_TYPECAST_UDWORD 0xb00001bc)
-#define R_DMA_CH7_FIRST__first__BITNR 0
-#define R_DMA_CH7_FIRST__first__WIDTH 32
-
-#define R_DMA_CH7_CMD (IO_TYPECAST_BYTE 0xb00001ec)
-#define R_DMA_CH7_CMD__cmd__BITNR 0
-#define R_DMA_CH7_CMD__cmd__WIDTH 3
-#define R_DMA_CH7_CMD__cmd__hold 0
-#define R_DMA_CH7_CMD__cmd__start 1
-#define R_DMA_CH7_CMD__cmd__restart 3
-#define R_DMA_CH7_CMD__cmd__continue 3
-#define R_DMA_CH7_CMD__cmd__reset 4
-
-#define R_DMA_CH7_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ed)
-#define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH7_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH7_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH7_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH7_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH7_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH7_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH7_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ee)
-#define R_DMA_CH7_STATUS__avail__BITNR 0
-#define R_DMA_CH7_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH8_HWSW (IO_TYPECAST_UDWORD 0xb0000180)
-#define R_DMA_CH8_HWSW__hw__BITNR 16
-#define R_DMA_CH8_HWSW__hw__WIDTH 16
-#define R_DMA_CH8_HWSW__sw__BITNR 0
-#define R_DMA_CH8_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH8_DESCR (IO_TYPECAST_UDWORD 0xb000018c)
-#define R_DMA_CH8_DESCR__descr__BITNR 0
-#define R_DMA_CH8_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH8_NEXT (IO_TYPECAST_UDWORD 0xb0000184)
-#define R_DMA_CH8_NEXT__next__BITNR 0
-#define R_DMA_CH8_NEXT__next__WIDTH 32
-
-#define R_DMA_CH8_BUF (IO_TYPECAST_UDWORD 0xb0000188)
-#define R_DMA_CH8_BUF__buf__BITNR 0
-#define R_DMA_CH8_BUF__buf__WIDTH 32
-
-#define R_DMA_CH8_FIRST (IO_TYPECAST_UDWORD 0xb00001c0)
-#define R_DMA_CH8_FIRST__first__BITNR 0
-#define R_DMA_CH8_FIRST__first__WIDTH 32
-
-#define R_DMA_CH8_CMD (IO_TYPECAST_BYTE 0xb00001f0)
-#define R_DMA_CH8_CMD__cmd__BITNR 0
-#define R_DMA_CH8_CMD__cmd__WIDTH 3
-#define R_DMA_CH8_CMD__cmd__hold 0
-#define R_DMA_CH8_CMD__cmd__start 1
-#define R_DMA_CH8_CMD__cmd__restart 3
-#define R_DMA_CH8_CMD__cmd__continue 3
-#define R_DMA_CH8_CMD__cmd__reset 4
-
-#define R_DMA_CH8_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f1)
-#define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH8_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH8_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH8_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH8_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH8_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH8_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH8_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f2)
-#define R_DMA_CH8_STATUS__avail__BITNR 0
-#define R_DMA_CH8_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH8_SUB (IO_TYPECAST_UDWORD 0xb000018c)
-#define R_DMA_CH8_SUB__sub__BITNR 0
-#define R_DMA_CH8_SUB__sub__WIDTH 32
-
-#define R_DMA_CH8_NEP (IO_TYPECAST_UDWORD 0xb00001c0)
-#define R_DMA_CH8_NEP__nep__BITNR 0
-#define R_DMA_CH8_NEP__nep__WIDTH 32
-
-#define R_DMA_CH8_SUB0_EP (IO_TYPECAST_UDWORD 0xb00001c8)
-#define R_DMA_CH8_SUB0_EP__ep__BITNR 0
-#define R_DMA_CH8_SUB0_EP__ep__WIDTH 32
-
-#define R_DMA_CH8_SUB0_CMD (IO_TYPECAST_BYTE 0xb00001d3)
-#define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0
-#define R_DMA_CH8_SUB0_CMD__cmd__WIDTH 1
-#define R_DMA_CH8_SUB0_CMD__cmd__stop 0
-#define R_DMA_CH8_SUB0_CMD__cmd__start 1
-
-#define R_DMA_CH8_SUB0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e3)
-#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__dont 0
-#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__do 1
-
-#define R_DMA_CH8_SUB1_EP (IO_TYPECAST_UDWORD 0xb00001cc)
-#define R_DMA_CH8_SUB1_EP__ep__BITNR 0
-#define R_DMA_CH8_SUB1_EP__ep__WIDTH 32
-
-#define R_DMA_CH8_SUB1_CMD (IO_TYPECAST_BYTE 0xb00001d7)
-#define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0
-#define R_DMA_CH8_SUB1_CMD__cmd__WIDTH 1
-#define R_DMA_CH8_SUB1_CMD__cmd__stop 0
-#define R_DMA_CH8_SUB1_CMD__cmd__start 1
-
-#define R_DMA_CH8_SUB1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e7)
-#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__dont 0
-#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__do 1
-
-#define R_DMA_CH8_SUB2_EP (IO_TYPECAST_UDWORD 0xb00001f8)
-#define R_DMA_CH8_SUB2_EP__ep__BITNR 0
-#define R_DMA_CH8_SUB2_EP__ep__WIDTH 32
-
-#define R_DMA_CH8_SUB2_CMD (IO_TYPECAST_BYTE 0xb00001db)
-#define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0
-#define R_DMA_CH8_SUB2_CMD__cmd__WIDTH 1
-#define R_DMA_CH8_SUB2_CMD__cmd__stop 0
-#define R_DMA_CH8_SUB2_CMD__cmd__start 1
-
-#define R_DMA_CH8_SUB2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001eb)
-#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__dont 0
-#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__do 1
-
-#define R_DMA_CH8_SUB3_EP (IO_TYPECAST_UDWORD 0xb00001fc)
-#define R_DMA_CH8_SUB3_EP__ep__BITNR 0
-#define R_DMA_CH8_SUB3_EP__ep__WIDTH 32
-
-#define R_DMA_CH8_SUB3_CMD (IO_TYPECAST_BYTE 0xb00001df)
-#define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0
-#define R_DMA_CH8_SUB3_CMD__cmd__WIDTH 1
-#define R_DMA_CH8_SUB3_CMD__cmd__stop 0
-#define R_DMA_CH8_SUB3_CMD__cmd__start 1
-
-#define R_DMA_CH8_SUB3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ef)
-#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__dont 0
-#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__do 1
-
-#define R_DMA_CH9_HWSW (IO_TYPECAST_UDWORD 0xb0000190)
-#define R_DMA_CH9_HWSW__hw__BITNR 16
-#define R_DMA_CH9_HWSW__hw__WIDTH 16
-#define R_DMA_CH9_HWSW__sw__BITNR 0
-#define R_DMA_CH9_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH9_DESCR (IO_TYPECAST_UDWORD 0xb000019c)
-#define R_DMA_CH9_DESCR__descr__BITNR 0
-#define R_DMA_CH9_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH9_NEXT (IO_TYPECAST_UDWORD 0xb0000194)
-#define R_DMA_CH9_NEXT__next__BITNR 0
-#define R_DMA_CH9_NEXT__next__WIDTH 32
-
-#define R_DMA_CH9_BUF (IO_TYPECAST_UDWORD 0xb0000198)
-#define R_DMA_CH9_BUF__buf__BITNR 0
-#define R_DMA_CH9_BUF__buf__WIDTH 32
-
-#define R_DMA_CH9_FIRST (IO_TYPECAST_UDWORD 0xb00001c4)
-#define R_DMA_CH9_FIRST__first__BITNR 0
-#define R_DMA_CH9_FIRST__first__WIDTH 32
-
-#define R_DMA_CH9_CMD (IO_TYPECAST_BYTE 0xb00001f4)
-#define R_DMA_CH9_CMD__cmd__BITNR 0
-#define R_DMA_CH9_CMD__cmd__WIDTH 3
-#define R_DMA_CH9_CMD__cmd__hold 0
-#define R_DMA_CH9_CMD__cmd__start 1
-#define R_DMA_CH9_CMD__cmd__restart 3
-#define R_DMA_CH9_CMD__cmd__continue 3
-#define R_DMA_CH9_CMD__cmd__reset 4
-
-#define R_DMA_CH9_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f5)
-#define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH9_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH9_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH9_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH9_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH9_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH9_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH9_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f6)
-#define R_DMA_CH9_STATUS__avail__BITNR 0
-#define R_DMA_CH9_STATUS__avail__WIDTH 7
-
-/*
-!* Test mode registers
-!*/
-
-#define R_TEST_MODE (IO_TYPECAST_UDWORD 0xb00000fc)
-#define R_TEST_MODE__single_step__BITNR 19
-#define R_TEST_MODE__single_step__WIDTH 1
-#define R_TEST_MODE__single_step__on 1
-#define R_TEST_MODE__single_step__off 0
-#define R_TEST_MODE__step_wr__BITNR 18
-#define R_TEST_MODE__step_wr__WIDTH 1
-#define R_TEST_MODE__step_wr__on 1
-#define R_TEST_MODE__step_wr__off 0
-#define R_TEST_MODE__step_rd__BITNR 17
-#define R_TEST_MODE__step_rd__WIDTH 1
-#define R_TEST_MODE__step_rd__on 1
-#define R_TEST_MODE__step_rd__off 0
-#define R_TEST_MODE__step_fetch__BITNR 16
-#define R_TEST_MODE__step_fetch__WIDTH 1
-#define R_TEST_MODE__step_fetch__on 1
-#define R_TEST_MODE__step_fetch__off 0
-#define R_TEST_MODE__mmu_test__BITNR 12
-#define R_TEST_MODE__mmu_test__WIDTH 1
-#define R_TEST_MODE__mmu_test__on 1
-#define R_TEST_MODE__mmu_test__off 0
-#define R_TEST_MODE__usb_test__BITNR 11
-#define R_TEST_MODE__usb_test__WIDTH 1
-#define R_TEST_MODE__usb_test__on 1
-#define R_TEST_MODE__usb_test__off 0
-#define R_TEST_MODE__scsi_timer_test__BITNR 10
-#define R_TEST_MODE__scsi_timer_test__WIDTH 1
-#define R_TEST_MODE__scsi_timer_test__on 1
-#define R_TEST_MODE__scsi_timer_test__off 0
-#define R_TEST_MODE__backoff__BITNR 9
-#define R_TEST_MODE__backoff__WIDTH 1
-#define R_TEST_MODE__backoff__on 1
-#define R_TEST_MODE__backoff__off 0
-#define R_TEST_MODE__snmp_test__BITNR 8
-#define R_TEST_MODE__snmp_test__WIDTH 1
-#define R_TEST_MODE__snmp_test__on 1
-#define R_TEST_MODE__snmp_test__off 0
-#define R_TEST_MODE__snmp_inc__BITNR 7
-#define R_TEST_MODE__snmp_inc__WIDTH 1
-#define R_TEST_MODE__snmp_inc__do 1
-#define R_TEST_MODE__snmp_inc__dont 0
-#define R_TEST_MODE__ser_loop__BITNR 6
-#define R_TEST_MODE__ser_loop__WIDTH 1
-#define R_TEST_MODE__ser_loop__on 1
-#define R_TEST_MODE__ser_loop__off 0
-#define R_TEST_MODE__baudrate__BITNR 5
-#define R_TEST_MODE__baudrate__WIDTH 1
-#define R_TEST_MODE__baudrate__on 1
-#define R_TEST_MODE__baudrate__off 0
-#define R_TEST_MODE__timer__BITNR 3
-#define R_TEST_MODE__timer__WIDTH 2
-#define R_TEST_MODE__timer__off 0
-#define R_TEST_MODE__timer__even 1
-#define R_TEST_MODE__timer__odd 2
-#define R_TEST_MODE__timer__all 3
-#define R_TEST_MODE__cache_test__BITNR 2
-#define R_TEST_MODE__cache_test__WIDTH 1
-#define R_TEST_MODE__cache_test__normal 0
-#define R_TEST_MODE__cache_test__test 1
-#define R_TEST_MODE__tag_test__BITNR 1
-#define R_TEST_MODE__tag_test__WIDTH 1
-#define R_TEST_MODE__tag_test__normal 0
-#define R_TEST_MODE__tag_test__test 1
-#define R_TEST_MODE__cache_enable__BITNR 0
-#define R_TEST_MODE__cache_enable__WIDTH 1
-#define R_TEST_MODE__cache_enable__enable 1
-#define R_TEST_MODE__cache_enable__disable 0
-
-#define R_SINGLE_STEP (IO_TYPECAST_BYTE 0xb00000fe)
-#define R_SINGLE_STEP__single_step__BITNR 3
-#define R_SINGLE_STEP__single_step__WIDTH 1
-#define R_SINGLE_STEP__single_step__on 1
-#define R_SINGLE_STEP__single_step__off 0
-#define R_SINGLE_STEP__step_wr__BITNR 2
-#define R_SINGLE_STEP__step_wr__WIDTH 1
-#define R_SINGLE_STEP__step_wr__on 1
-#define R_SINGLE_STEP__step_wr__off 0
-#define R_SINGLE_STEP__step_rd__BITNR 1
-#define R_SINGLE_STEP__step_rd__WIDTH 1
-#define R_SINGLE_STEP__step_rd__on 1
-#define R_SINGLE_STEP__step_rd__off 0
-#define R_SINGLE_STEP__step_fetch__BITNR 0
-#define R_SINGLE_STEP__step_fetch__WIDTH 1
-#define R_SINGLE_STEP__step_fetch__on 1
-#define R_SINGLE_STEP__step_fetch__off 0
-
-/*
-!* USB interface control registers
-!*/
-
-#define R_USB_REVISION (IO_TYPECAST_RO_BYTE 0xb0000200)
-#define R_USB_REVISION__major__BITNR 4
-#define R_USB_REVISION__major__WIDTH 4
-#define R_USB_REVISION__minor__BITNR 0
-#define R_USB_REVISION__minor__WIDTH 4
-
-#define R_USB_COMMAND (IO_TYPECAST_BYTE 0xb0000201)
-#define R_USB_COMMAND__port_sel__BITNR 6
-#define R_USB_COMMAND__port_sel__WIDTH 2
-#define R_USB_COMMAND__port_sel__nop 0
-#define R_USB_COMMAND__port_sel__port1 1
-#define R_USB_COMMAND__port_sel__port2 2
-#define R_USB_COMMAND__port_sel__both 3
-#define R_USB_COMMAND__port_cmd__BITNR 4
-#define R_USB_COMMAND__port_cmd__WIDTH 2
-#define R_USB_COMMAND__port_cmd__reset 0
-#define R_USB_COMMAND__port_cmd__disable 1
-#define R_USB_COMMAND__port_cmd__suspend 2
-#define R_USB_COMMAND__port_cmd__resume 3
-#define R_USB_COMMAND__busy__BITNR 3
-#define R_USB_COMMAND__busy__WIDTH 1
-#define R_USB_COMMAND__busy__no 0
-#define R_USB_COMMAND__busy__yes 1
-#define R_USB_COMMAND__ctrl_cmd__BITNR 0
-#define R_USB_COMMAND__ctrl_cmd__WIDTH 3
-#define R_USB_COMMAND__ctrl_cmd__nop 0
-#define R_USB_COMMAND__ctrl_cmd__reset 1
-#define R_USB_COMMAND__ctrl_cmd__deconfig 2
-#define R_USB_COMMAND__ctrl_cmd__host_config 3
-#define R_USB_COMMAND__ctrl_cmd__dev_config 4
-#define R_USB_COMMAND__ctrl_cmd__host_nop 5
-#define R_USB_COMMAND__ctrl_cmd__host_run 6
-#define R_USB_COMMAND__ctrl_cmd__host_stop 7
-
-#define R_USB_COMMAND_DEV (IO_TYPECAST_BYTE 0xb0000201)
-#define R_USB_COMMAND_DEV__port_sel__BITNR 6
-#define R_USB_COMMAND_DEV__port_sel__WIDTH 2
-#define R_USB_COMMAND_DEV__port_sel__nop 0
-#define R_USB_COMMAND_DEV__port_sel__dummy1 1
-#define R_USB_COMMAND_DEV__port_sel__dummy2 2
-#define R_USB_COMMAND_DEV__port_sel__any 3
-#define R_USB_COMMAND_DEV__port_cmd__BITNR 4
-#define R_USB_COMMAND_DEV__port_cmd__WIDTH 2
-#define R_USB_COMMAND_DEV__port_cmd__active 0
-#define R_USB_COMMAND_DEV__port_cmd__passive 1
-#define R_USB_COMMAND_DEV__port_cmd__nop 2
-#define R_USB_COMMAND_DEV__port_cmd__wakeup 3
-#define R_USB_COMMAND_DEV__busy__BITNR 3
-#define R_USB_COMMAND_DEV__busy__WIDTH 1
-#define R_USB_COMMAND_DEV__busy__no 0
-#define R_USB_COMMAND_DEV__busy__yes 1
-#define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0
-#define R_USB_COMMAND_DEV__ctrl_cmd__WIDTH 3
-#define R_USB_COMMAND_DEV__ctrl_cmd__nop 0
-#define R_USB_COMMAND_DEV__ctrl_cmd__reset 1
-#define R_USB_COMMAND_DEV__ctrl_cmd__deconfig 2
-#define R_USB_COMMAND_DEV__ctrl_cmd__host_config 3
-#define R_USB_COMMAND_DEV__ctrl_cmd__dev_config 4
-#define R_USB_COMMAND_DEV__ctrl_cmd__dev_active 5
-#define R_USB_COMMAND_DEV__ctrl_cmd__dev_passive 6
-#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop 7
-
-#define R_USB_STATUS (IO_TYPECAST_RO_BYTE 0xb0000202)
-#define R_USB_STATUS__ourun__BITNR 5
-#define R_USB_STATUS__ourun__WIDTH 1
-#define R_USB_STATUS__ourun__no 0
-#define R_USB_STATUS__ourun__yes 1
-#define R_USB_STATUS__perror__BITNR 4
-#define R_USB_STATUS__perror__WIDTH 1
-#define R_USB_STATUS__perror__no 0
-#define R_USB_STATUS__perror__yes 1
-#define R_USB_STATUS__device_mode__BITNR 3
-#define R_USB_STATUS__device_mode__WIDTH 1
-#define R_USB_STATUS__device_mode__no 0
-#define R_USB_STATUS__device_mode__yes 1
-#define R_USB_STATUS__host_mode__BITNR 2
-#define R_USB_STATUS__host_mode__WIDTH 1
-#define R_USB_STATUS__host_mode__no 0
-#define R_USB_STATUS__host_mode__yes 1
-#define R_USB_STATUS__started__BITNR 1
-#define R_USB_STATUS__started__WIDTH 1
-#define R_USB_STATUS__started__no 0
-#define R_USB_STATUS__started__yes 1
-#define R_USB_STATUS__running__BITNR 0
-#define R_USB_STATUS__running__WIDTH 1
-#define R_USB_STATUS__running__no 0
-#define R_USB_STATUS__running__yes 1
-
-#define R_USB_IRQ_MASK_SET (IO_TYPECAST_UWORD 0xb0000204)
-#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13
-#define R_USB_IRQ_MASK_SET__iso_eof__WIDTH 1
-#define R_USB_IRQ_MASK_SET__iso_eof__nop 0
-#define R_USB_IRQ_MASK_SET__iso_eof__set 1
-#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12
-#define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1
-#define R_USB_IRQ_MASK_SET__intr_eof__nop 0
-#define R_USB_IRQ_MASK_SET__intr_eof__set 1
-#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11
-#define R_USB_IRQ_MASK_SET__iso_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET__iso_eot__nop 0
-#define R_USB_IRQ_MASK_SET__iso_eot__set 1
-#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10
-#define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET__intr_eot__nop 0
-#define R_USB_IRQ_MASK_SET__intr_eot__set 1
-#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9
-#define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET__ctl_eot__nop 0
-#define R_USB_IRQ_MASK_SET__ctl_eot__set 1
-#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8
-#define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET__bulk_eot__nop 0
-#define R_USB_IRQ_MASK_SET__bulk_eot__set 1
-#define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_SET__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_SET__epid_attn__nop 0
-#define R_USB_IRQ_MASK_SET__epid_attn__set 1
-#define R_USB_IRQ_MASK_SET__sof__BITNR 2
-#define R_USB_IRQ_MASK_SET__sof__WIDTH 1
-#define R_USB_IRQ_MASK_SET__sof__nop 0
-#define R_USB_IRQ_MASK_SET__sof__set 1
-#define R_USB_IRQ_MASK_SET__port_status__BITNR 1
-#define R_USB_IRQ_MASK_SET__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_SET__port_status__nop 0
-#define R_USB_IRQ_MASK_SET__port_status__set 1
-#define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_SET__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_SET__ctl_status__nop 0
-#define R_USB_IRQ_MASK_SET__ctl_status__set 1
-
-#define R_USB_IRQ_MASK_READ (IO_TYPECAST_RO_UWORD 0xb0000204)
-#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13
-#define R_USB_IRQ_MASK_READ__iso_eof__WIDTH 1
-#define R_USB_IRQ_MASK_READ__iso_eof__no_pend 0
-#define R_USB_IRQ_MASK_READ__iso_eof__pend 1
-#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12
-#define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1
-#define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0
-#define R_USB_IRQ_MASK_READ__intr_eof__pend 1
-#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11
-#define R_USB_IRQ_MASK_READ__iso_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ__iso_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ__iso_eot__pend 1
-#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10
-#define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ__intr_eot__pend 1
-#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9
-#define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ__ctl_eot__pend 1
-#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8
-#define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ__bulk_eot__pend 1
-#define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_READ__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_READ__epid_attn__no_pend 0
-#define R_USB_IRQ_MASK_READ__epid_attn__pend 1
-#define R_USB_IRQ_MASK_READ__sof__BITNR 2
-#define R_USB_IRQ_MASK_READ__sof__WIDTH 1
-#define R_USB_IRQ_MASK_READ__sof__no_pend 0
-#define R_USB_IRQ_MASK_READ__sof__pend 1
-#define R_USB_IRQ_MASK_READ__port_status__BITNR 1
-#define R_USB_IRQ_MASK_READ__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_READ__port_status__no_pend 0
-#define R_USB_IRQ_MASK_READ__port_status__pend 1
-#define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_READ__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_READ__ctl_status__no_pend 0
-#define R_USB_IRQ_MASK_READ__ctl_status__pend 1
-
-#define R_USB_IRQ_MASK_CLR (IO_TYPECAST_UWORD 0xb0000206)
-#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13
-#define R_USB_IRQ_MASK_CLR__iso_eof__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__iso_eof__nop 0
-#define R_USB_IRQ_MASK_CLR__iso_eof__clr 1
-#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12
-#define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__intr_eof__nop 0
-#define R_USB_IRQ_MASK_CLR__intr_eof__clr 1
-#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11
-#define R_USB_IRQ_MASK_CLR__iso_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__iso_eot__nop 0
-#define R_USB_IRQ_MASK_CLR__iso_eot__clr 1
-#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10
-#define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__intr_eot__nop 0
-#define R_USB_IRQ_MASK_CLR__intr_eot__clr 1
-#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9
-#define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0
-#define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1
-#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8
-#define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0
-#define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1
-#define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_CLR__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__epid_attn__nop 0
-#define R_USB_IRQ_MASK_CLR__epid_attn__clr 1
-#define R_USB_IRQ_MASK_CLR__sof__BITNR 2
-#define R_USB_IRQ_MASK_CLR__sof__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__sof__nop 0
-#define R_USB_IRQ_MASK_CLR__sof__clr 1
-#define R_USB_IRQ_MASK_CLR__port_status__BITNR 1
-#define R_USB_IRQ_MASK_CLR__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__port_status__nop 0
-#define R_USB_IRQ_MASK_CLR__port_status__clr 1
-#define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_CLR__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__ctl_status__nop 0
-#define R_USB_IRQ_MASK_CLR__ctl_status__clr 1
-
-#define R_USB_IRQ_READ (IO_TYPECAST_RO_UWORD 0xb0000206)
-#define R_USB_IRQ_READ__iso_eof__BITNR 13
-#define R_USB_IRQ_READ__iso_eof__WIDTH 1
-#define R_USB_IRQ_READ__iso_eof__no_pend 0
-#define R_USB_IRQ_READ__iso_eof__pend 1
-#define R_USB_IRQ_READ__intr_eof__BITNR 12
-#define R_USB_IRQ_READ__intr_eof__WIDTH 1
-#define R_USB_IRQ_READ__intr_eof__no_pend 0
-#define R_USB_IRQ_READ__intr_eof__pend 1
-#define R_USB_IRQ_READ__iso_eot__BITNR 11
-#define R_USB_IRQ_READ__iso_eot__WIDTH 1
-#define R_USB_IRQ_READ__iso_eot__no_pend 0
-#define R_USB_IRQ_READ__iso_eot__pend 1
-#define R_USB_IRQ_READ__intr_eot__BITNR 10
-#define R_USB_IRQ_READ__intr_eot__WIDTH 1
-#define R_USB_IRQ_READ__intr_eot__no_pend 0
-#define R_USB_IRQ_READ__intr_eot__pend 1
-#define R_USB_IRQ_READ__ctl_eot__BITNR 9
-#define R_USB_IRQ_READ__ctl_eot__WIDTH 1
-#define R_USB_IRQ_READ__ctl_eot__no_pend 0
-#define R_USB_IRQ_READ__ctl_eot__pend 1
-#define R_USB_IRQ_READ__bulk_eot__BITNR 8
-#define R_USB_IRQ_READ__bulk_eot__WIDTH 1
-#define R_USB_IRQ_READ__bulk_eot__no_pend 0
-#define R_USB_IRQ_READ__bulk_eot__pend 1
-#define R_USB_IRQ_READ__epid_attn__BITNR 3
-#define R_USB_IRQ_READ__epid_attn__WIDTH 1
-#define R_USB_IRQ_READ__epid_attn__no_pend 0
-#define R_USB_IRQ_READ__epid_attn__pend 1
-#define R_USB_IRQ_READ__sof__BITNR 2
-#define R_USB_IRQ_READ__sof__WIDTH 1
-#define R_USB_IRQ_READ__sof__no_pend 0
-#define R_USB_IRQ_READ__sof__pend 1
-#define R_USB_IRQ_READ__port_status__BITNR 1
-#define R_USB_IRQ_READ__port_status__WIDTH 1
-#define R_USB_IRQ_READ__port_status__no_pend 0
-#define R_USB_IRQ_READ__port_status__pend 1
-#define R_USB_IRQ_READ__ctl_status__BITNR 0
-#define R_USB_IRQ_READ__ctl_status__WIDTH 1
-#define R_USB_IRQ_READ__ctl_status__no_pend 0
-#define R_USB_IRQ_READ__ctl_status__pend 1
-
-#define R_USB_IRQ_MASK_SET_DEV (IO_TYPECAST_UWORD 0xb0000204)
-#define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12
-#define R_USB_IRQ_MASK_SET_DEV__out_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__out_eot__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__out_eot__set 1
-#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11
-#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__set 1
-#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10
-#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__set 1
-#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9
-#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__set 1
-#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8
-#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__set 1
-#define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_SET_DEV__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__epid_attn__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__epid_attn__set 1
-#define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2
-#define R_USB_IRQ_MASK_SET_DEV__sof__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__sof__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__sof__set 1
-#define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1
-#define R_USB_IRQ_MASK_SET_DEV__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__port_status__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__port_status__set 1
-#define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_SET_DEV__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__ctl_status__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__ctl_status__set 1
-
-#define R_USB_IRQ_MASK_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000204)
-#define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12
-#define R_USB_IRQ_MASK_READ_DEV__out_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__out_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__out_eot__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11
-#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10
-#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9
-#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8
-#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_READ_DEV__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__epid_attn__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__epid_attn__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2
-#define R_USB_IRQ_MASK_READ_DEV__sof__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__sof__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__sof__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1
-#define R_USB_IRQ_MASK_READ_DEV__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__port_status__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__port_status__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_READ_DEV__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__ctl_status__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__ctl_status__pend 1
-
-#define R_USB_IRQ_MASK_CLR_DEV (IO_TYPECAST_UWORD 0xb0000206)
-#define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12
-#define R_USB_IRQ_MASK_CLR_DEV__out_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__out_eot__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__out_eot__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11
-#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10
-#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9
-#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8
-#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2
-#define R_USB_IRQ_MASK_CLR_DEV__sof__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__sof__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__sof__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1
-#define R_USB_IRQ_MASK_CLR_DEV__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__port_status__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__port_status__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__clr 1
-
-#define R_USB_IRQ_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000206)
-#define R_USB_IRQ_READ_DEV__out_eot__BITNR 12
-#define R_USB_IRQ_READ_DEV__out_eot__WIDTH 1
-#define R_USB_IRQ_READ_DEV__out_eot__no_pend 0
-#define R_USB_IRQ_READ_DEV__out_eot__pend 1
-#define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11
-#define R_USB_IRQ_READ_DEV__ep3_in_eot__WIDTH 1
-#define R_USB_IRQ_READ_DEV__ep3_in_eot__no_pend 0
-#define R_USB_IRQ_READ_DEV__ep3_in_eot__pend 1
-#define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10
-#define R_USB_IRQ_READ_DEV__ep2_in_eot__WIDTH 1
-#define R_USB_IRQ_READ_DEV__ep2_in_eot__no_pend 0
-#define R_USB_IRQ_READ_DEV__ep2_in_eot__pend 1
-#define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9
-#define R_USB_IRQ_READ_DEV__ep1_in_eot__WIDTH 1
-#define R_USB_IRQ_READ_DEV__ep1_in_eot__no_pend 0
-#define R_USB_IRQ_READ_DEV__ep1_in_eot__pend 1
-#define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8
-#define R_USB_IRQ_READ_DEV__ep0_in_eot__WIDTH 1
-#define R_USB_IRQ_READ_DEV__ep0_in_eot__no_pend 0
-#define R_USB_IRQ_READ_DEV__ep0_in_eot__pend 1
-#define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3
-#define R_USB_IRQ_READ_DEV__epid_attn__WIDTH 1
-#define R_USB_IRQ_READ_DEV__epid_attn__no_pend 0
-#define R_USB_IRQ_READ_DEV__epid_attn__pend 1
-#define R_USB_IRQ_READ_DEV__sof__BITNR 2
-#define R_USB_IRQ_READ_DEV__sof__WIDTH 1
-#define R_USB_IRQ_READ_DEV__sof__no_pend 0
-#define R_USB_IRQ_READ_DEV__sof__pend 1
-#define R_USB_IRQ_READ_DEV__port_status__BITNR 1
-#define R_USB_IRQ_READ_DEV__port_status__WIDTH 1
-#define R_USB_IRQ_READ_DEV__port_status__no_pend 0
-#define R_USB_IRQ_READ_DEV__port_status__pend 1
-#define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0
-#define R_USB_IRQ_READ_DEV__ctl_status__WIDTH 1
-#define R_USB_IRQ_READ_DEV__ctl_status__no_pend 0
-#define R_USB_IRQ_READ_DEV__ctl_status__pend 1
-
-#define R_USB_FM_NUMBER (IO_TYPECAST_UDWORD 0xb000020c)
-#define R_USB_FM_NUMBER__value__BITNR 0
-#define R_USB_FM_NUMBER__value__WIDTH 32
-
-#define R_USB_FM_INTERVAL (IO_TYPECAST_UWORD 0xb0000210)
-#define R_USB_FM_INTERVAL__fixed__BITNR 6
-#define R_USB_FM_INTERVAL__fixed__WIDTH 8
-#define R_USB_FM_INTERVAL__adj__BITNR 0
-#define R_USB_FM_INTERVAL__adj__WIDTH 6
-
-#define R_USB_FM_REMAINING (IO_TYPECAST_RO_UWORD 0xb0000212)
-#define R_USB_FM_REMAINING__value__BITNR 0
-#define R_USB_FM_REMAINING__value__WIDTH 14
-
-#define R_USB_FM_PSTART (IO_TYPECAST_UWORD 0xb0000214)
-#define R_USB_FM_PSTART__value__BITNR 0
-#define R_USB_FM_PSTART__value__WIDTH 14
-
-#define R_USB_RH_STATUS (IO_TYPECAST_RO_BYTE 0xb0000203)
-#define R_USB_RH_STATUS__babble2__BITNR 7
-#define R_USB_RH_STATUS__babble2__WIDTH 1
-#define R_USB_RH_STATUS__babble2__no 0
-#define R_USB_RH_STATUS__babble2__yes 1
-#define R_USB_RH_STATUS__babble1__BITNR 6
-#define R_USB_RH_STATUS__babble1__WIDTH 1
-#define R_USB_RH_STATUS__babble1__no 0
-#define R_USB_RH_STATUS__babble1__yes 1
-#define R_USB_RH_STATUS__bus1__BITNR 4
-#define R_USB_RH_STATUS__bus1__WIDTH 2
-#define R_USB_RH_STATUS__bus1__SE0 0
-#define R_USB_RH_STATUS__bus1__Diff0 1
-#define R_USB_RH_STATUS__bus1__Diff1 2
-#define R_USB_RH_STATUS__bus1__SE1 3
-#define R_USB_RH_STATUS__bus2__BITNR 2
-#define R_USB_RH_STATUS__bus2__WIDTH 2
-#define R_USB_RH_STATUS__bus2__SE0 0
-#define R_USB_RH_STATUS__bus2__Diff0 1
-#define R_USB_RH_STATUS__bus2__Diff1 2
-#define R_USB_RH_STATUS__bus2__SE1 3
-#define R_USB_RH_STATUS__nports__BITNR 0
-#define R_USB_RH_STATUS__nports__WIDTH 2
-
-#define R_USB_RH_PORT_STATUS_1 (IO_TYPECAST_RO_UWORD 0xb0000218)
-#define R_USB_RH_PORT_STATUS_1__speed__BITNR 9
-#define R_USB_RH_PORT_STATUS_1__speed__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__speed__full 0
-#define R_USB_RH_PORT_STATUS_1__speed__low 1
-#define R_USB_RH_PORT_STATUS_1__power__BITNR 8
-#define R_USB_RH_PORT_STATUS_1__power__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__reset__BITNR 4
-#define R_USB_RH_PORT_STATUS_1__reset__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__reset__no 0
-#define R_USB_RH_PORT_STATUS_1__reset__yes 1
-#define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3
-#define R_USB_RH_PORT_STATUS_1__overcurrent__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__overcurrent__no 0
-#define R_USB_RH_PORT_STATUS_1__overcurrent__yes 1
-#define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2
-#define R_USB_RH_PORT_STATUS_1__suspended__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__suspended__no 0
-#define R_USB_RH_PORT_STATUS_1__suspended__yes 1
-#define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1
-#define R_USB_RH_PORT_STATUS_1__enabled__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__enabled__no 0
-#define R_USB_RH_PORT_STATUS_1__enabled__yes 1
-#define R_USB_RH_PORT_STATUS_1__connected__BITNR 0
-#define R_USB_RH_PORT_STATUS_1__connected__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__connected__no 0
-#define R_USB_RH_PORT_STATUS_1__connected__yes 1
-
-#define R_USB_RH_PORT_STATUS_2 (IO_TYPECAST_RO_UWORD 0xb000021a)
-#define R_USB_RH_PORT_STATUS_2__speed__BITNR 9
-#define R_USB_RH_PORT_STATUS_2__speed__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__speed__full 0
-#define R_USB_RH_PORT_STATUS_2__speed__low 1
-#define R_USB_RH_PORT_STATUS_2__power__BITNR 8
-#define R_USB_RH_PORT_STATUS_2__power__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__reset__BITNR 4
-#define R_USB_RH_PORT_STATUS_2__reset__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__reset__no 0
-#define R_USB_RH_PORT_STATUS_2__reset__yes 1
-#define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3
-#define R_USB_RH_PORT_STATUS_2__overcurrent__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__overcurrent__no 0
-#define R_USB_RH_PORT_STATUS_2__overcurrent__yes 1
-#define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2
-#define R_USB_RH_PORT_STATUS_2__suspended__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__suspended__no 0
-#define R_USB_RH_PORT_STATUS_2__suspended__yes 1
-#define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1
-#define R_USB_RH_PORT_STATUS_2__enabled__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__enabled__no 0
-#define R_USB_RH_PORT_STATUS_2__enabled__yes 1
-#define R_USB_RH_PORT_STATUS_2__connected__BITNR 0
-#define R_USB_RH_PORT_STATUS_2__connected__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__connected__no 0
-#define R_USB_RH_PORT_STATUS_2__connected__yes 1
-
-#define R_USB_EPT_INDEX (IO_TYPECAST_BYTE 0xb0000208)
-#define R_USB_EPT_INDEX__value__BITNR 0
-#define R_USB_EPT_INDEX__value__WIDTH 5
-
-#define R_USB_EPT_DATA (IO_TYPECAST_UDWORD 0xb000021c)
-#define R_USB_EPT_DATA__valid__BITNR 31
-#define R_USB_EPT_DATA__valid__WIDTH 1
-#define R_USB_EPT_DATA__valid__no 0
-#define R_USB_EPT_DATA__valid__yes 1
-#define R_USB_EPT_DATA__hold__BITNR 30
-#define R_USB_EPT_DATA__hold__WIDTH 1
-#define R_USB_EPT_DATA__hold__no 0
-#define R_USB_EPT_DATA__hold__yes 1
-#define R_USB_EPT_DATA__error_count_in__BITNR 28
-#define R_USB_EPT_DATA__error_count_in__WIDTH 2
-#define R_USB_EPT_DATA__t_in__BITNR 27
-#define R_USB_EPT_DATA__t_in__WIDTH 1
-#define R_USB_EPT_DATA__low_speed__BITNR 26
-#define R_USB_EPT_DATA__low_speed__WIDTH 1
-#define R_USB_EPT_DATA__low_speed__no 0
-#define R_USB_EPT_DATA__low_speed__yes 1
-#define R_USB_EPT_DATA__port__BITNR 24
-#define R_USB_EPT_DATA__port__WIDTH 2
-#define R_USB_EPT_DATA__port__any 0
-#define R_USB_EPT_DATA__port__p1 1
-#define R_USB_EPT_DATA__port__p2 2
-#define R_USB_EPT_DATA__port__undef 3
-#define R_USB_EPT_DATA__error_code__BITNR 22
-#define R_USB_EPT_DATA__error_code__WIDTH 2
-#define R_USB_EPT_DATA__error_code__no_error 0
-#define R_USB_EPT_DATA__error_code__stall 1
-#define R_USB_EPT_DATA__error_code__bus_error 2
-#define R_USB_EPT_DATA__error_code__buffer_error 3
-#define R_USB_EPT_DATA__t_out__BITNR 21
-#define R_USB_EPT_DATA__t_out__WIDTH 1
-#define R_USB_EPT_DATA__error_count_out__BITNR 19
-#define R_USB_EPT_DATA__error_count_out__WIDTH 2
-#define R_USB_EPT_DATA__max_len__BITNR 11
-#define R_USB_EPT_DATA__max_len__WIDTH 7
-#define R_USB_EPT_DATA__ep__BITNR 7
-#define R_USB_EPT_DATA__ep__WIDTH 4
-#define R_USB_EPT_DATA__dev__BITNR 0
-#define R_USB_EPT_DATA__dev__WIDTH 7
-
-#define R_USB_EPT_DATA_ISO (IO_TYPECAST_UDWORD 0xb000021c)
-#define R_USB_EPT_DATA_ISO__valid__BITNR 31
-#define R_USB_EPT_DATA_ISO__valid__WIDTH 1
-#define R_USB_EPT_DATA_ISO__valid__no 0
-#define R_USB_EPT_DATA_ISO__valid__yes 1
-#define R_USB_EPT_DATA_ISO__port__BITNR 24
-#define R_USB_EPT_DATA_ISO__port__WIDTH 2
-#define R_USB_EPT_DATA_ISO__port__any 0
-#define R_USB_EPT_DATA_ISO__port__p1 1
-#define R_USB_EPT_DATA_ISO__port__p2 2
-#define R_USB_EPT_DATA_ISO__port__undef 3
-#define R_USB_EPT_DATA_ISO__error_code__BITNR 22
-#define R_USB_EPT_DATA_ISO__error_code__WIDTH 2
-#define R_USB_EPT_DATA_ISO__error_code__no_error 0
-#define R_USB_EPT_DATA_ISO__error_code__stall 1
-#define R_USB_EPT_DATA_ISO__error_code__bus_error 2
-#define R_USB_EPT_DATA_ISO__error_code__TBD3 3
-#define R_USB_EPT_DATA_ISO__max_len__BITNR 11
-#define R_USB_EPT_DATA_ISO__max_len__WIDTH 10
-#define R_USB_EPT_DATA_ISO__ep__BITNR 7
-#define R_USB_EPT_DATA_ISO__ep__WIDTH 4
-#define R_USB_EPT_DATA_ISO__dev__BITNR 0
-#define R_USB_EPT_DATA_ISO__dev__WIDTH 7
-
-#define R_USB_EPT_DATA_DEV (IO_TYPECAST_UDWORD 0xb000021c)
-#define R_USB_EPT_DATA_DEV__valid__BITNR 31
-#define R_USB_EPT_DATA_DEV__valid__WIDTH 1
-#define R_USB_EPT_DATA_DEV__valid__no 0
-#define R_USB_EPT_DATA_DEV__valid__yes 1
-#define R_USB_EPT_DATA_DEV__hold__BITNR 30
-#define R_USB_EPT_DATA_DEV__hold__WIDTH 1
-#define R_USB_EPT_DATA_DEV__hold__no 0
-#define R_USB_EPT_DATA_DEV__hold__yes 1
-#define R_USB_EPT_DATA_DEV__stall__BITNR 29
-#define R_USB_EPT_DATA_DEV__stall__WIDTH 1
-#define R_USB_EPT_DATA_DEV__stall__no 0
-#define R_USB_EPT_DATA_DEV__stall__yes 1
-#define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28
-#define R_USB_EPT_DATA_DEV__iso_resp__WIDTH 1
-#define R_USB_EPT_DATA_DEV__iso_resp__quiet 0
-#define R_USB_EPT_DATA_DEV__iso_resp__yes 1
-#define R_USB_EPT_DATA_DEV__ctrl__BITNR 27
-#define R_USB_EPT_DATA_DEV__ctrl__WIDTH 1
-#define R_USB_EPT_DATA_DEV__ctrl__no 0
-#define R_USB_EPT_DATA_DEV__ctrl__yes 1
-#define R_USB_EPT_DATA_DEV__iso__BITNR 26
-#define R_USB_EPT_DATA_DEV__iso__WIDTH 1
-#define R_USB_EPT_DATA_DEV__iso__no 0
-#define R_USB_EPT_DATA_DEV__iso__yes 1
-#define R_USB_EPT_DATA_DEV__port__BITNR 24
-#define R_USB_EPT_DATA_DEV__port__WIDTH 2
-#define R_USB_EPT_DATA_DEV__control_phase__BITNR 22
-#define R_USB_EPT_DATA_DEV__control_phase__WIDTH 1
-#define R_USB_EPT_DATA_DEV__t__BITNR 21
-#define R_USB_EPT_DATA_DEV__t__WIDTH 1
-#define R_USB_EPT_DATA_DEV__max_len__BITNR 11
-#define R_USB_EPT_DATA_DEV__max_len__WIDTH 10
-#define R_USB_EPT_DATA_DEV__ep__BITNR 7
-#define R_USB_EPT_DATA_DEV__ep__WIDTH 4
-#define R_USB_EPT_DATA_DEV__dev__BITNR 0
-#define R_USB_EPT_DATA_DEV__dev__WIDTH 7
-
-#define R_USB_SNMP_TERROR (IO_TYPECAST_UDWORD 0xb0000220)
-#define R_USB_SNMP_TERROR__value__BITNR 0
-#define R_USB_SNMP_TERROR__value__WIDTH 32
-
-#define R_USB_EPID_ATTN (IO_TYPECAST_RO_UDWORD 0xb0000224)
-#define R_USB_EPID_ATTN__value__BITNR 0
-#define R_USB_EPID_ATTN__value__WIDTH 32
-
-#define R_USB_PORT1_DISABLE (IO_TYPECAST_BYTE 0xb000006a)
-#define R_USB_PORT1_DISABLE__disable__BITNR 0
-#define R_USB_PORT1_DISABLE__disable__WIDTH 1
-#define R_USB_PORT1_DISABLE__disable__yes 0
-#define R_USB_PORT1_DISABLE__disable__no 1
-
-#define R_USB_PORT2_DISABLE (IO_TYPECAST_BYTE 0xb0000052)
-#define R_USB_PORT2_DISABLE__disable__BITNR 0
-#define R_USB_PORT2_DISABLE__disable__WIDTH 1
-#define R_USB_PORT2_DISABLE__disable__yes 0
-#define R_USB_PORT2_DISABLE__disable__no 1
-
-/*
-!* MMU registers
-!*/
-
-#define R_MMU_CONFIG (IO_TYPECAST_UDWORD 0xb0000240)
-#define R_MMU_CONFIG__mmu_enable__BITNR 31
-#define R_MMU_CONFIG__mmu_enable__WIDTH 1
-#define R_MMU_CONFIG__mmu_enable__enable 1
-#define R_MMU_CONFIG__mmu_enable__disable 0
-#define R_MMU_CONFIG__inv_excp__BITNR 18
-#define R_MMU_CONFIG__inv_excp__WIDTH 1
-#define R_MMU_CONFIG__inv_excp__enable 1
-#define R_MMU_CONFIG__inv_excp__disable 0
-#define R_MMU_CONFIG__acc_excp__BITNR 17
-#define R_MMU_CONFIG__acc_excp__WIDTH 1
-#define R_MMU_CONFIG__acc_excp__enable 1
-#define R_MMU_CONFIG__acc_excp__disable 0
-#define R_MMU_CONFIG__we_excp__BITNR 16
-#define R_MMU_CONFIG__we_excp__WIDTH 1
-#define R_MMU_CONFIG__we_excp__enable 1
-#define R_MMU_CONFIG__we_excp__disable 0
-#define R_MMU_CONFIG__seg_f__BITNR 15
-#define R_MMU_CONFIG__seg_f__WIDTH 1
-#define R_MMU_CONFIG__seg_f__seg 1
-#define R_MMU_CONFIG__seg_f__page 0
-#define R_MMU_CONFIG__seg_e__BITNR 14
-#define R_MMU_CONFIG__seg_e__WIDTH 1
-#define R_MMU_CONFIG__seg_e__seg 1
-#define R_MMU_CONFIG__seg_e__page 0
-#define R_MMU_CONFIG__seg_d__BITNR 13
-#define R_MMU_CONFIG__seg_d__WIDTH 1
-#define R_MMU_CONFIG__seg_d__seg 1
-#define R_MMU_CONFIG__seg_d__page 0
-#define R_MMU_CONFIG__seg_c__BITNR 12
-#define R_MMU_CONFIG__seg_c__WIDTH 1
-#define R_MMU_CONFIG__seg_c__seg 1
-#define R_MMU_CONFIG__seg_c__page 0
-#define R_MMU_CONFIG__seg_b__BITNR 11
-#define R_MMU_CONFIG__seg_b__WIDTH 1
-#define R_MMU_CONFIG__seg_b__seg 1
-#define R_MMU_CONFIG__seg_b__page 0
-#define R_MMU_CONFIG__seg_a__BITNR 10
-#define R_MMU_CONFIG__seg_a__WIDTH 1
-#define R_MMU_CONFIG__seg_a__seg 1
-#define R_MMU_CONFIG__seg_a__page 0
-#define R_MMU_CONFIG__seg_9__BITNR 9
-#define R_MMU_CONFIG__seg_9__WIDTH 1
-#define R_MMU_CONFIG__seg_9__seg 1
-#define R_MMU_CONFIG__seg_9__page 0
-#define R_MMU_CONFIG__seg_8__BITNR 8
-#define R_MMU_CONFIG__seg_8__WIDTH 1
-#define R_MMU_CONFIG__seg_8__seg 1
-#define R_MMU_CONFIG__seg_8__page 0
-#define R_MMU_CONFIG__seg_7__BITNR 7
-#define R_MMU_CONFIG__seg_7__WIDTH 1
-#define R_MMU_CONFIG__seg_7__seg 1
-#define R_MMU_CONFIG__seg_7__page 0
-#define R_MMU_CONFIG__seg_6__BITNR 6
-#define R_MMU_CONFIG__seg_6__WIDTH 1
-#define R_MMU_CONFIG__seg_6__seg 1
-#define R_MMU_CONFIG__seg_6__page 0
-#define R_MMU_CONFIG__seg_5__BITNR 5
-#define R_MMU_CONFIG__seg_5__WIDTH 1
-#define R_MMU_CONFIG__seg_5__seg 1
-#define R_MMU_CONFIG__seg_5__page 0
-#define R_MMU_CONFIG__seg_4__BITNR 4
-#define R_MMU_CONFIG__seg_4__WIDTH 1
-#define R_MMU_CONFIG__seg_4__seg 1
-#define R_MMU_CONFIG__seg_4__page 0
-#define R_MMU_CONFIG__seg_3__BITNR 3
-#define R_MMU_CONFIG__seg_3__WIDTH 1
-#define R_MMU_CONFIG__seg_3__seg 1
-#define R_MMU_CONFIG__seg_3__page 0
-#define R_MMU_CONFIG__seg_2__BITNR 2
-#define R_MMU_CONFIG__seg_2__WIDTH 1
-#define R_MMU_CONFIG__seg_2__seg 1
-#define R_MMU_CONFIG__seg_2__page 0
-#define R_MMU_CONFIG__seg_1__BITNR 1
-#define R_MMU_CONFIG__seg_1__WIDTH 1
-#define R_MMU_CONFIG__seg_1__seg 1
-#define R_MMU_CONFIG__seg_1__page 0
-#define R_MMU_CONFIG__seg_0__BITNR 0
-#define R_MMU_CONFIG__seg_0__WIDTH 1
-#define R_MMU_CONFIG__seg_0__seg 1
-#define R_MMU_CONFIG__seg_0__page 0
-
-#define R_MMU_KSEG (IO_TYPECAST_UWORD 0xb0000240)
-#define R_MMU_KSEG__seg_f__BITNR 15
-#define R_MMU_KSEG__seg_f__WIDTH 1
-#define R_MMU_KSEG__seg_f__seg 1
-#define R_MMU_KSEG__seg_f__page 0
-#define R_MMU_KSEG__seg_e__BITNR 14
-#define R_MMU_KSEG__seg_e__WIDTH 1
-#define R_MMU_KSEG__seg_e__seg 1
-#define R_MMU_KSEG__seg_e__page 0
-#define R_MMU_KSEG__seg_d__BITNR 13
-#define R_MMU_KSEG__seg_d__WIDTH 1
-#define R_MMU_KSEG__seg_d__seg 1
-#define R_MMU_KSEG__seg_d__page 0
-#define R_MMU_KSEG__seg_c__BITNR 12
-#define R_MMU_KSEG__seg_c__WIDTH 1
-#define R_MMU_KSEG__seg_c__seg 1
-#define R_MMU_KSEG__seg_c__page 0
-#define R_MMU_KSEG__seg_b__BITNR 11
-#define R_MMU_KSEG__seg_b__WIDTH 1
-#define R_MMU_KSEG__seg_b__seg 1
-#define R_MMU_KSEG__seg_b__page 0
-#define R_MMU_KSEG__seg_a__BITNR 10
-#define R_MMU_KSEG__seg_a__WIDTH 1
-#define R_MMU_KSEG__seg_a__seg 1
-#define R_MMU_KSEG__seg_a__page 0
-#define R_MMU_KSEG__seg_9__BITNR 9
-#define R_MMU_KSEG__seg_9__WIDTH 1
-#define R_MMU_KSEG__seg_9__seg 1
-#define R_MMU_KSEG__seg_9__page 0
-#define R_MMU_KSEG__seg_8__BITNR 8
-#define R_MMU_KSEG__seg_8__WIDTH 1
-#define R_MMU_KSEG__seg_8__seg 1
-#define R_MMU_KSEG__seg_8__page 0
-#define R_MMU_KSEG__seg_7__BITNR 7
-#define R_MMU_KSEG__seg_7__WIDTH 1
-#define R_MMU_KSEG__seg_7__seg 1
-#define R_MMU_KSEG__seg_7__page 0
-#define R_MMU_KSEG__seg_6__BITNR 6
-#define R_MMU_KSEG__seg_6__WIDTH 1
-#define R_MMU_KSEG__seg_6__seg 1
-#define R_MMU_KSEG__seg_6__page 0
-#define R_MMU_KSEG__seg_5__BITNR 5
-#define R_MMU_KSEG__seg_5__WIDTH 1
-#define R_MMU_KSEG__seg_5__seg 1
-#define R_MMU_KSEG__seg_5__page 0
-#define R_MMU_KSEG__seg_4__BITNR 4
-#define R_MMU_KSEG__seg_4__WIDTH 1
-#define R_MMU_KSEG__seg_4__seg 1
-#define R_MMU_KSEG__seg_4__page 0
-#define R_MMU_KSEG__seg_3__BITNR 3
-#define R_MMU_KSEG__seg_3__WIDTH 1
-#define R_MMU_KSEG__seg_3__seg 1
-#define R_MMU_KSEG__seg_3__page 0
-#define R_MMU_KSEG__seg_2__BITNR 2
-#define R_MMU_KSEG__seg_2__WIDTH 1
-#define R_MMU_KSEG__seg_2__seg 1
-#define R_MMU_KSEG__seg_2__page 0
-#define R_MMU_KSEG__seg_1__BITNR 1
-#define R_MMU_KSEG__seg_1__WIDTH 1
-#define R_MMU_KSEG__seg_1__seg 1
-#define R_MMU_KSEG__seg_1__page 0
-#define R_MMU_KSEG__seg_0__BITNR 0
-#define R_MMU_KSEG__seg_0__WIDTH 1
-#define R_MMU_KSEG__seg_0__seg 1
-#define R_MMU_KSEG__seg_0__page 0
-
-#define R_MMU_CTRL (IO_TYPECAST_BYTE 0xb0000242)
-#define R_MMU_CTRL__inv_excp__BITNR 2
-#define R_MMU_CTRL__inv_excp__WIDTH 1
-#define R_MMU_CTRL__inv_excp__enable 1
-#define R_MMU_CTRL__inv_excp__disable 0
-#define R_MMU_CTRL__acc_excp__BITNR 1
-#define R_MMU_CTRL__acc_excp__WIDTH 1
-#define R_MMU_CTRL__acc_excp__enable 1
-#define R_MMU_CTRL__acc_excp__disable 0
-#define R_MMU_CTRL__we_excp__BITNR 0
-#define R_MMU_CTRL__we_excp__WIDTH 1
-#define R_MMU_CTRL__we_excp__enable 1
-#define R_MMU_CTRL__we_excp__disable 0
-
-#define R_MMU_ENABLE (IO_TYPECAST_BYTE 0xb0000243)
-#define R_MMU_ENABLE__mmu_enable__BITNR 7
-#define R_MMU_ENABLE__mmu_enable__WIDTH 1
-#define R_MMU_ENABLE__mmu_enable__enable 1
-#define R_MMU_ENABLE__mmu_enable__disable 0
-
-#define R_MMU_KBASE_LO (IO_TYPECAST_UDWORD 0xb0000244)
-#define R_MMU_KBASE_LO__base_7__BITNR 28
-#define R_MMU_KBASE_LO__base_7__WIDTH 4
-#define R_MMU_KBASE_LO__base_6__BITNR 24
-#define R_MMU_KBASE_LO__base_6__WIDTH 4
-#define R_MMU_KBASE_LO__base_5__BITNR 20
-#define R_MMU_KBASE_LO__base_5__WIDTH 4
-#define R_MMU_KBASE_LO__base_4__BITNR 16
-#define R_MMU_KBASE_LO__base_4__WIDTH 4
-#define R_MMU_KBASE_LO__base_3__BITNR 12
-#define R_MMU_KBASE_LO__base_3__WIDTH 4
-#define R_MMU_KBASE_LO__base_2__BITNR 8
-#define R_MMU_KBASE_LO__base_2__WIDTH 4
-#define R_MMU_KBASE_LO__base_1__BITNR 4
-#define R_MMU_KBASE_LO__base_1__WIDTH 4
-#define R_MMU_KBASE_LO__base_0__BITNR 0
-#define R_MMU_KBASE_LO__base_0__WIDTH 4
-
-#define R_MMU_KBASE_HI (IO_TYPECAST_UDWORD 0xb0000248)
-#define R_MMU_KBASE_HI__base_f__BITNR 28
-#define R_MMU_KBASE_HI__base_f__WIDTH 4
-#define R_MMU_KBASE_HI__base_e__BITNR 24
-#define R_MMU_KBASE_HI__base_e__WIDTH 4
-#define R_MMU_KBASE_HI__base_d__BITNR 20
-#define R_MMU_KBASE_HI__base_d__WIDTH 4
-#define R_MMU_KBASE_HI__base_c__BITNR 16
-#define R_MMU_KBASE_HI__base_c__WIDTH 4
-#define R_MMU_KBASE_HI__base_b__BITNR 12
-#define R_MMU_KBASE_HI__base_b__WIDTH 4
-#define R_MMU_KBASE_HI__base_a__BITNR 8
-#define R_MMU_KBASE_HI__base_a__WIDTH 4
-#define R_MMU_KBASE_HI__base_9__BITNR 4
-#define R_MMU_KBASE_HI__base_9__WIDTH 4
-#define R_MMU_KBASE_HI__base_8__BITNR 0
-#define R_MMU_KBASE_HI__base_8__WIDTH 4
-
-#define R_MMU_CONTEXT (IO_TYPECAST_BYTE 0xb000024c)
-#define R_MMU_CONTEXT__page_id__BITNR 0
-#define R_MMU_CONTEXT__page_id__WIDTH 6
-
-#define R_MMU_CAUSE (IO_TYPECAST_RO_UDWORD 0xb0000250)
-#define R_MMU_CAUSE__vpn__BITNR 13
-#define R_MMU_CAUSE__vpn__WIDTH 19
-#define R_MMU_CAUSE__miss_excp__BITNR 12
-#define R_MMU_CAUSE__miss_excp__WIDTH 1
-#define R_MMU_CAUSE__miss_excp__yes 1
-#define R_MMU_CAUSE__miss_excp__no 0
-#define R_MMU_CAUSE__inv_excp__BITNR 11
-#define R_MMU_CAUSE__inv_excp__WIDTH 1
-#define R_MMU_CAUSE__inv_excp__yes 1
-#define R_MMU_CAUSE__inv_excp__no 0
-#define R_MMU_CAUSE__acc_excp__BITNR 10
-#define R_MMU_CAUSE__acc_excp__WIDTH 1
-#define R_MMU_CAUSE__acc_excp__yes 1
-#define R_MMU_CAUSE__acc_excp__no 0
-#define R_MMU_CAUSE__we_excp__BITNR 9
-#define R_MMU_CAUSE__we_excp__WIDTH 1
-#define R_MMU_CAUSE__we_excp__yes 1
-#define R_MMU_CAUSE__we_excp__no 0
-#define R_MMU_CAUSE__wr_rd__BITNR 8
-#define R_MMU_CAUSE__wr_rd__WIDTH 1
-#define R_MMU_CAUSE__wr_rd__write 1
-#define R_MMU_CAUSE__wr_rd__read 0
-#define R_MMU_CAUSE__page_id__BITNR 0
-#define R_MMU_CAUSE__page_id__WIDTH 6
-
-#define R_TLB_SELECT (IO_TYPECAST_BYTE 0xb0000254)
-#define R_TLB_SELECT__index__BITNR 0
-#define R_TLB_SELECT__index__WIDTH 6
-
-#define R_TLB_LO (IO_TYPECAST_UDWORD 0xb0000258)
-#define R_TLB_LO__pfn__BITNR 13
-#define R_TLB_LO__pfn__WIDTH 19
-#define R_TLB_LO__global__BITNR 3
-#define R_TLB_LO__global__WIDTH 1
-#define R_TLB_LO__global__yes 1
-#define R_TLB_LO__global__no 0
-#define R_TLB_LO__valid__BITNR 2
-#define R_TLB_LO__valid__WIDTH 1
-#define R_TLB_LO__valid__yes 1
-#define R_TLB_LO__valid__no 0
-#define R_TLB_LO__kernel__BITNR 1
-#define R_TLB_LO__kernel__WIDTH 1
-#define R_TLB_LO__kernel__yes 1
-#define R_TLB_LO__kernel__no 0
-#define R_TLB_LO__we__BITNR 0
-#define R_TLB_LO__we__WIDTH 1
-#define R_TLB_LO__we__yes 1
-#define R_TLB_LO__we__no 0
-
-#define R_TLB_HI (IO_TYPECAST_UDWORD 0xb000025c)
-#define R_TLB_HI__vpn__BITNR 13
-#define R_TLB_HI__vpn__WIDTH 19
-#define R_TLB_HI__page_id__BITNR 0
-#define R_TLB_HI__page_id__WIDTH 6
-
-/*
-!* Syncrounous serial port registers
-!*/
-
-#define R_SYNC_SERIAL1_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000006c)
-#define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0
-#define R_SYNC_SERIAL1_REC_DATA__data_in__WIDTH 32
-
-#define R_SYNC_SERIAL1_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000006c)
-#define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0
-#define R_SYNC_SERIAL1_REC_WORD__data_in__WIDTH 16
-
-#define R_SYNC_SERIAL1_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000006c)
-#define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0
-#define R_SYNC_SERIAL1_REC_BYTE__data_in__WIDTH 8
-
-#define R_SYNC_SERIAL1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000068)
-#define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15
-#define R_SYNC_SERIAL1_STATUS__rec_status__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__rec_status__running 0
-#define R_SYNC_SERIAL1_STATUS__rec_status__idle 1
-#define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14
-#define R_SYNC_SERIAL1_STATUS__tr_empty__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__tr_empty__empty 1
-#define R_SYNC_SERIAL1_STATUS__tr_empty__not_empty 0
-#define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13
-#define R_SYNC_SERIAL1_STATUS__tr_ready__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__tr_ready__full 0
-#define R_SYNC_SERIAL1_STATUS__tr_ready__ready 1
-#define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12
-#define R_SYNC_SERIAL1_STATUS__pin_1__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__pin_1__low 0
-#define R_SYNC_SERIAL1_STATUS__pin_1__high 1
-#define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11
-#define R_SYNC_SERIAL1_STATUS__pin_0__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__pin_0__low 0
-#define R_SYNC_SERIAL1_STATUS__pin_0__high 1
-#define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10
-#define R_SYNC_SERIAL1_STATUS__underflow__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__underflow__no 0
-#define R_SYNC_SERIAL1_STATUS__underflow__yes 1
-#define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9
-#define R_SYNC_SERIAL1_STATUS__overrun__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__overrun__no 0
-#define R_SYNC_SERIAL1_STATUS__overrun__yes 1
-#define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8
-#define R_SYNC_SERIAL1_STATUS__data_avail__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__data_avail__no 0
-#define R_SYNC_SERIAL1_STATUS__data_avail__yes 1
-#define R_SYNC_SERIAL1_STATUS__data__BITNR 0
-#define R_SYNC_SERIAL1_STATUS__data__WIDTH 8
-
-#define R_SYNC_SERIAL1_TR_DATA (IO_TYPECAST_UDWORD 0xb000006c)
-#define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0
-#define R_SYNC_SERIAL1_TR_DATA__data_out__WIDTH 32
-
-#define R_SYNC_SERIAL1_TR_WORD (IO_TYPECAST_UWORD 0xb000006c)
-#define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0
-#define R_SYNC_SERIAL1_TR_WORD__data_out__WIDTH 16
-
-#define R_SYNC_SERIAL1_TR_BYTE (IO_TYPECAST_BYTE 0xb000006c)
-#define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0
-#define R_SYNC_SERIAL1_TR_BYTE__data_out__WIDTH 8
-
-#define R_SYNC_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068)
-#define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28
-#define R_SYNC_SERIAL1_CTRL__tr_baud__WIDTH 4
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c150Hz 0
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c300Hz 1
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c600Hz 2
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c1200Hz 3
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c2400Hz 4
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c4800Hz 5
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c9600Hz 6
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c19k2Hz 7
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c28k8Hz 8
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c57k6Hz 9
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c115k2Hz 10
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c230k4Hz 11
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c460k8Hz 12
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c921k6Hz 13
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c3125kHz 14
-#define R_SYNC_SERIAL1_CTRL__tr_baud__reserved 15
-#define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27
-#define R_SYNC_SERIAL1_CTRL__dma_enable__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__dma_enable__on 1
-#define R_SYNC_SERIAL1_CTRL__dma_enable__off 0
-#define R_SYNC_SERIAL1_CTRL__mode__BITNR 24
-#define R_SYNC_SERIAL1_CTRL__mode__WIDTH 3
-#define R_SYNC_SERIAL1_CTRL__mode__master_output 0
-#define R_SYNC_SERIAL1_CTRL__mode__slave_output 1
-#define R_SYNC_SERIAL1_CTRL__mode__master_input 2
-#define R_SYNC_SERIAL1_CTRL__mode__slave_input 3
-#define R_SYNC_SERIAL1_CTRL__mode__master_bidir 4
-#define R_SYNC_SERIAL1_CTRL__mode__slave_bidir 5
-#define R_SYNC_SERIAL1_CTRL__error__BITNR 23
-#define R_SYNC_SERIAL1_CTRL__error__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__error__normal 0
-#define R_SYNC_SERIAL1_CTRL__error__ignore 1
-#define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22
-#define R_SYNC_SERIAL1_CTRL__rec_enable__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__rec_enable__disable 0
-#define R_SYNC_SERIAL1_CTRL__rec_enable__enable 1
-#define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21
-#define R_SYNC_SERIAL1_CTRL__f_synctype__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__f_synctype__normal 0
-#define R_SYNC_SERIAL1_CTRL__f_synctype__early 1
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__WIDTH 2
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__bit 0
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__word 1
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__extended 2
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__reserved 3
-#define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18
-#define R_SYNC_SERIAL1_CTRL__f_sync__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__f_sync__on 0
-#define R_SYNC_SERIAL1_CTRL__f_sync__off 1
-#define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17
-#define R_SYNC_SERIAL1_CTRL__clk_mode__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__clk_mode__normal 0
-#define R_SYNC_SERIAL1_CTRL__clk_mode__gated 1
-#define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16
-#define R_SYNC_SERIAL1_CTRL__clk_halt__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__clk_halt__running 0
-#define R_SYNC_SERIAL1_CTRL__clk_halt__stopped 1
-#define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15
-#define R_SYNC_SERIAL1_CTRL__bitorder__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__bitorder__lsb 0
-#define R_SYNC_SERIAL1_CTRL__bitorder__msb 1
-#define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14
-#define R_SYNC_SERIAL1_CTRL__tr_enable__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__tr_enable__disable 0
-#define R_SYNC_SERIAL1_CTRL__tr_enable__enable 1
-#define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11
-#define R_SYNC_SERIAL1_CTRL__wordsize__WIDTH 3
-#define R_SYNC_SERIAL1_CTRL__wordsize__size8bit 0
-#define R_SYNC_SERIAL1_CTRL__wordsize__size12bit 1
-#define R_SYNC_SERIAL1_CTRL__wordsize__size16bit 2
-#define R_SYNC_SERIAL1_CTRL__wordsize__size24bit 3
-#define R_SYNC_SERIAL1_CTRL__wordsize__size32bit 4
-#define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10
-#define R_SYNC_SERIAL1_CTRL__buf_empty__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_8 0
-#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_0 1
-#define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9
-#define R_SYNC_SERIAL1_CTRL__buf_full__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_32 0
-#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_8 1
-#define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8
-#define R_SYNC_SERIAL1_CTRL__flow_ctrl__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__flow_ctrl__disabled 0
-#define R_SYNC_SERIAL1_CTRL__flow_ctrl__enabled 1
-#define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6
-#define R_SYNC_SERIAL1_CTRL__clk_polarity__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__clk_polarity__pos 0
-#define R_SYNC_SERIAL1_CTRL__clk_polarity__neg 1
-#define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5
-#define R_SYNC_SERIAL1_CTRL__frame_polarity__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__frame_polarity__normal 0
-#define R_SYNC_SERIAL1_CTRL__frame_polarity__inverted 1
-#define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4
-#define R_SYNC_SERIAL1_CTRL__status_polarity__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__status_polarity__normal 0
-#define R_SYNC_SERIAL1_CTRL__status_polarity__inverted 1
-#define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3
-#define R_SYNC_SERIAL1_CTRL__clk_driver__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__clk_driver__normal 0
-#define R_SYNC_SERIAL1_CTRL__clk_driver__inverted 1
-#define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2
-#define R_SYNC_SERIAL1_CTRL__frame_driver__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__frame_driver__normal 0
-#define R_SYNC_SERIAL1_CTRL__frame_driver__inverted 1
-#define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1
-#define R_SYNC_SERIAL1_CTRL__status_driver__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__status_driver__normal 0
-#define R_SYNC_SERIAL1_CTRL__status_driver__inverted 1
-#define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0
-#define R_SYNC_SERIAL1_CTRL__def_out0__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__def_out0__high 1
-#define R_SYNC_SERIAL1_CTRL__def_out0__low 0
-
-#define R_SYNC_SERIAL3_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000007c)
-#define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0
-#define R_SYNC_SERIAL3_REC_DATA__data_in__WIDTH 32
-
-#define R_SYNC_SERIAL3_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000007c)
-#define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0
-#define R_SYNC_SERIAL3_REC_WORD__data_in__WIDTH 16
-
-#define R_SYNC_SERIAL3_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000007c)
-#define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0
-#define R_SYNC_SERIAL3_REC_BYTE__data_in__WIDTH 8
-
-#define R_SYNC_SERIAL3_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000078)
-#define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15
-#define R_SYNC_SERIAL3_STATUS__rec_status__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__rec_status__running 0
-#define R_SYNC_SERIAL3_STATUS__rec_status__idle 1
-#define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14
-#define R_SYNC_SERIAL3_STATUS__tr_empty__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__tr_empty__empty 1
-#define R_SYNC_SERIAL3_STATUS__tr_empty__not_empty 0
-#define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13
-#define R_SYNC_SERIAL3_STATUS__tr_ready__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__tr_ready__full 0
-#define R_SYNC_SERIAL3_STATUS__tr_ready__ready 1
-#define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12
-#define R_SYNC_SERIAL3_STATUS__pin_1__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__pin_1__low 0
-#define R_SYNC_SERIAL3_STATUS__pin_1__high 1
-#define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11
-#define R_SYNC_SERIAL3_STATUS__pin_0__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__pin_0__low 0
-#define R_SYNC_SERIAL3_STATUS__pin_0__high 1
-#define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10
-#define R_SYNC_SERIAL3_STATUS__underflow__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__underflow__no 0
-#define R_SYNC_SERIAL3_STATUS__underflow__yes 1
-#define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9
-#define R_SYNC_SERIAL3_STATUS__overrun__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__overrun__no 0
-#define R_SYNC_SERIAL3_STATUS__overrun__yes 1
-#define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8
-#define R_SYNC_SERIAL3_STATUS__data_avail__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__data_avail__no 0
-#define R_SYNC_SERIAL3_STATUS__data_avail__yes 1
-#define R_SYNC_SERIAL3_STATUS__data__BITNR 0
-#define R_SYNC_SERIAL3_STATUS__data__WIDTH 8
-
-#define R_SYNC_SERIAL3_TR_DATA (IO_TYPECAST_UDWORD 0xb000007c)
-#define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0
-#define R_SYNC_SERIAL3_TR_DATA__data_out__WIDTH 32
-
-#define R_SYNC_SERIAL3_TR_WORD (IO_TYPECAST_UWORD 0xb000007c)
-#define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0
-#define R_SYNC_SERIAL3_TR_WORD__data_out__WIDTH 16
-
-#define R_SYNC_SERIAL3_TR_BYTE (IO_TYPECAST_BYTE 0xb000007c)
-#define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0
-#define R_SYNC_SERIAL3_TR_BYTE__data_out__WIDTH 8
-
-#define R_SYNC_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078)
-#define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28
-#define R_SYNC_SERIAL3_CTRL__tr_baud__WIDTH 4
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c150Hz 0
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c300Hz 1
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c600Hz 2
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c1200Hz 3
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c2400Hz 4
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c4800Hz 5
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c9600Hz 6
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c19k2Hz 7
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c28k8Hz 8
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c57k6Hz 9
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c115k2Hz 10
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c230k4Hz 11
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c460k8Hz 12
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c921k6Hz 13
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c3125kHz 14
-#define R_SYNC_SERIAL3_CTRL__tr_baud__reserved 15
-#define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27
-#define R_SYNC_SERIAL3_CTRL__dma_enable__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__dma_enable__on 1
-#define R_SYNC_SERIAL3_CTRL__dma_enable__off 0
-#define R_SYNC_SERIAL3_CTRL__mode__BITNR 24
-#define R_SYNC_SERIAL3_CTRL__mode__WIDTH 3
-#define R_SYNC_SERIAL3_CTRL__mode__master_output 0
-#define R_SYNC_SERIAL3_CTRL__mode__slave_output 1
-#define R_SYNC_SERIAL3_CTRL__mode__master_input 2
-#define R_SYNC_SERIAL3_CTRL__mode__slave_input 3
-#define R_SYNC_SERIAL3_CTRL__mode__master_bidir 4
-#define R_SYNC_SERIAL3_CTRL__mode__slave_bidir 5
-#define R_SYNC_SERIAL3_CTRL__error__BITNR 23
-#define R_SYNC_SERIAL3_CTRL__error__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__error__normal 0
-#define R_SYNC_SERIAL3_CTRL__error__ignore 1
-#define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22
-#define R_SYNC_SERIAL3_CTRL__rec_enable__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__rec_enable__disable 0
-#define R_SYNC_SERIAL3_CTRL__rec_enable__enable 1
-#define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21
-#define R_SYNC_SERIAL3_CTRL__f_synctype__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__f_synctype__normal 0
-#define R_SYNC_SERIAL3_CTRL__f_synctype__early 1
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__WIDTH 2
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__bit 0
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__word 1
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__extended 2
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__reserved 3
-#define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18
-#define R_SYNC_SERIAL3_CTRL__f_sync__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__f_sync__on 0
-#define R_SYNC_SERIAL3_CTRL__f_sync__off 1
-#define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17
-#define R_SYNC_SERIAL3_CTRL__clk_mode__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__clk_mode__normal 0
-#define R_SYNC_SERIAL3_CTRL__clk_mode__gated 1
-#define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16
-#define R_SYNC_SERIAL3_CTRL__clk_halt__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__clk_halt__running 0
-#define R_SYNC_SERIAL3_CTRL__clk_halt__stopped 1
-#define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15
-#define R_SYNC_SERIAL3_CTRL__bitorder__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__bitorder__lsb 0
-#define R_SYNC_SERIAL3_CTRL__bitorder__msb 1
-#define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14
-#define R_SYNC_SERIAL3_CTRL__tr_enable__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__tr_enable__disable 0
-#define R_SYNC_SERIAL3_CTRL__tr_enable__enable 1
-#define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11
-#define R_SYNC_SERIAL3_CTRL__wordsize__WIDTH 3
-#define R_SYNC_SERIAL3_CTRL__wordsize__size8bit 0
-#define R_SYNC_SERIAL3_CTRL__wordsize__size12bit 1
-#define R_SYNC_SERIAL3_CTRL__wordsize__size16bit 2
-#define R_SYNC_SERIAL3_CTRL__wordsize__size24bit 3
-#define R_SYNC_SERIAL3_CTRL__wordsize__size32bit 4
-#define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10
-#define R_SYNC_SERIAL3_CTRL__buf_empty__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_8 0
-#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_0 1
-#define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9
-#define R_SYNC_SERIAL3_CTRL__buf_full__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_32 0
-#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_8 1
-#define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8
-#define R_SYNC_SERIAL3_CTRL__flow_ctrl__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__flow_ctrl__disabled 0
-#define R_SYNC_SERIAL3_CTRL__flow_ctrl__enabled 1
-#define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6
-#define R_SYNC_SERIAL3_CTRL__clk_polarity__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__clk_polarity__pos 0
-#define R_SYNC_SERIAL3_CTRL__clk_polarity__neg 1
-#define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5
-#define R_SYNC_SERIAL3_CTRL__frame_polarity__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__frame_polarity__normal 0
-#define R_SYNC_SERIAL3_CTRL__frame_polarity__inverted 1
-#define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4
-#define R_SYNC_SERIAL3_CTRL__status_polarity__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__status_polarity__normal 0
-#define R_SYNC_SERIAL3_CTRL__status_polarity__inverted 1
-#define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3
-#define R_SYNC_SERIAL3_CTRL__clk_driver__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__clk_driver__normal 0
-#define R_SYNC_SERIAL3_CTRL__clk_driver__inverted 1
-#define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2
-#define R_SYNC_SERIAL3_CTRL__frame_driver__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__frame_driver__normal 0
-#define R_SYNC_SERIAL3_CTRL__frame_driver__inverted 1
-#define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1
-#define R_SYNC_SERIAL3_CTRL__status_driver__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__status_driver__normal 0
-#define R_SYNC_SERIAL3_CTRL__status_driver__inverted 1
-#define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0
-#define R_SYNC_SERIAL3_CTRL__def_out0__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__def_out0__high 1
-#define R_SYNC_SERIAL3_CTRL__def_out0__low 0
-
diff --git a/include/asm-cris/arch-v10/sv_addr_ag.h b/include/asm-cris/arch-v10/sv_addr_ag.h
deleted file mode 100644
index e4a6b68b8982..000000000000
--- a/include/asm-cris/arch-v10/sv_addr_ag.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*!**************************************************************************
-*!                                                            
-*! MACROS:
-*!   IO_MASK(reg,field)
-*!   IO_STATE(reg,field,state)
-*!   IO_EXTRACT(reg,field,val)
-*!   IO_STATE_VALUE(reg,field,state)
-*!   IO_BITNR(reg,field)
-*!   IO_WIDTH(reg,field)
-*!   IO_FIELD(reg,field,val)
-*!   IO_RD(reg)
-*!   All moderegister addresses and fields of these.
-*!
-*!**************************************************************************/
-
-#ifndef __sv_addr_ag_h__
-#define __sv_addr_ag_h__
-
-
-#define __test_sv_addr__ 0
-
-/*------------------------------------------------------------
-!* General macros to manipulate moderegisters.
-!*-----------------------------------------------------------*/
-
-/* IO_MASK returns a mask for a specified bitfield in a register.
-   Note that this macro doesn't work when field width is 32 bits. */
-#define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_)
-#define IO_MASK_(reg_, field_) \
-    ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR )
-
-/* IO_STATE returns a constant corresponding to a one of the symbolic
-   states that the bitfield can have. (Shifted to correct position)  */
-#define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state)
-#define IO_STATE_(reg_, field_, _state) \
-    ( reg_##_##field_##_state << reg_##_##field_##_BITNR )
-
-/* IO_EXTRACT returns the masked and shifted value corresponding to the
-   bitfield can have. */
-#define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val)
-#define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \
-     - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR )
-
-/* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic
-   states that the bitfield can have. (Not shifted)  */
-#define IO_STATE_VALUE(reg, field, state) \
-    IO_STATE_VALUE_ (reg##_, field##_, _##state)
-#define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state )
-
-/* IO_FIELD shifts the val parameter to be aligned with the bitfield
-   specified. */
-#define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val)
-#define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR)
-
-/* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is
-   LSB and the returned bitnumber is LSB of the field. */
-#define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_)
-#define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR)
-
-/* IO_WIDTH returns the width, in bits, of a bitfield. */
-#define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_)
-#define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH)
-
-/*--- Obsolete. Kept for backw compatibility. ---*/
-/* Reads (or writes) a byte/uword/udword from the specified mode
-   register. */
-#define IO_RD(reg) (*(volatile u32*)(reg))
-#define IO_RD_B(reg) (*(volatile u8*)(reg))
-#define IO_RD_W(reg) (*(volatile u16*)(reg))
-#define IO_RD_D(reg) (*(volatile u32*)(reg))
-
-/*------------------------------------------------------------
-!* Start addresses of the different memory areas.
-!*-----------------------------------------------------------*/
-
-#define MEM_CSE0_START (0x00000000)
-#define MEM_CSE0_SIZE (0x04000000)
-#define MEM_CSE1_START (0x04000000)
-#define MEM_CSE1_SIZE (0x04000000)
-#define MEM_CSR0_START (0x08000000)
-#define MEM_CSR1_START (0x0c000000)
-#define MEM_CSP0_START (0x10000000)
-#define MEM_CSP1_START (0x14000000)
-#define MEM_CSP2_START (0x18000000)
-#define MEM_CSP3_START (0x1c000000)
-#define MEM_CSP4_START (0x20000000)
-#define MEM_CSP5_START (0x24000000)
-#define MEM_CSP6_START (0x28000000)
-#define MEM_CSP7_START (0x2c000000)
-#define MEM_DRAM_START (0x40000000)
-
-#define MEM_NON_CACHEABLE (0x80000000)
-
-/*------------------------------------------------------------
-!* Type casts used in mode register macros, making pointer
-!* dereferencing possible. Empty in assembler.
-!*-----------------------------------------------------------*/
-
-#ifndef __ASSEMBLER__
-# define  IO_TYPECAST_UDWORD  (volatile u32*)
-# define  IO_TYPECAST_RO_UDWORD  (const volatile u32*)
-# define  IO_TYPECAST_UWORD  (volatile u16*)
-# define  IO_TYPECAST_RO_UWORD  (const volatile u16*)
-# define  IO_TYPECAST_BYTE  (volatile u8*)
-# define  IO_TYPECAST_RO_BYTE  (const volatile u8*)
-#else
-# define  IO_TYPECAST_UDWORD
-# define  IO_TYPECAST_RO_UDWORD
-# define  IO_TYPECAST_UWORD
-# define  IO_TYPECAST_RO_UWORD
-# define  IO_TYPECAST_BYTE
-# define  IO_TYPECAST_RO_BYTE
-#endif
-
-/*------------------------------------------------------------*/
-
-#include "sv_addr.agh"
-
-#if __test_sv_addr__
-/* IO_MASK( R_BUS_CONFIG , CE ) */
-IO_MASK( R_WAITSTATES , SRAM_WS )
-IO_MASK( R_TEST , W32 )
-
-IO_STATE( R_BUS_CONFIG, CE, DISABLE )
-IO_STATE( R_BUS_CONFIG, CE, ENABLE )
-
-IO_STATE( R_DRAM_TIMING, REF, IVAL2 )
-
-IO_MASK( R_DRAM_TIMING, REF )
-
-IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT )
-
-IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S ) 
-   == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED )
-#endif
-
-
-#endif  /* ifndef __sv_addr_ag_h__ */
-
diff --git a/include/asm-cris/arch-v10/svinto.h b/include/asm-cris/arch-v10/svinto.h
deleted file mode 100644
index 0881a1af7cee..000000000000
--- a/include/asm-cris/arch-v10/svinto.h
+++ /dev/null
@@ -1,64 +0,0 @@
-#ifndef _ASM_CRIS_SVINTO_H
-#define _ASM_CRIS_SVINTO_H
-
-#include "sv_addr_ag.h"
-
-extern unsigned int genconfig_shadow; /* defined and set in head.S */
-
-/* dma stuff */
-
-enum {                          /* Available in:  */
-	d_eol      = (1 << 0),  /* flags          */
-	d_eop      = (1 << 1),  /* flags & status */
-	d_wait     = (1 << 2),  /* flags          */
-	d_int      = (1 << 3),  /* flags          */
-	d_txerr    = (1 << 4),  /* flags          */
-	d_stop     = (1 << 4),  /*         status */
-	d_ecp      = (1 << 4),  /* flags & status */
-	d_pri      = (1 << 5),  /* flags & status */
-	d_alignerr = (1 << 6),  /*         status */
-	d_crcerr   = (1 << 7)   /*         status */
-};
-
-/* Do remember that DMA does not go through the MMU and needs
- * a real physical address, not an address virtually mapped or
- * paged. Therefore the buf/next ptrs below are unsigned long instead
- * of void * to give a warning if you try to put a pointer directly
- * to them instead of going through virt_to_phys/phys_to_virt.
- */
-
-typedef struct etrax_dma_descr {
-	unsigned short sw_len;                /* 0-1 */
-	unsigned short ctrl;                  /* 2-3 */
-	unsigned long  next;                  /* 4-7 */
-	unsigned long  buf;                   /* 8-11 */
-	unsigned short hw_len;                /* 12-13 */
-	unsigned char  status;                /* 14 */
-	unsigned char  fifo_len;              /* 15 */
-} etrax_dma_descr;
-
-
-/* Use this for constant numbers only */
-#define RESET_DMA_NUM( n ) \
-  *R_DMA_CH##n##_CMD = IO_STATE( R_DMA_CH0_CMD, cmd, reset )
-
-/* Use this for constant numbers or symbols, 
- * having two macros makes it possible to use constant expressions. 
- */
-#define RESET_DMA( n ) RESET_DMA_NUM( n )
-
-
-/* Use this for constant numbers only */
-#define WAIT_DMA_NUM( n ) \
-  while( (*R_DMA_CH##n##_CMD & IO_MASK( R_DMA_CH0_CMD, cmd )) != \
-         IO_STATE( R_DMA_CH0_CMD, cmd, hold ) )
-
-/* Use this for constant numbers or symbols 
- * having two macros makes it possible to use constant expressions. 
- */
-#define WAIT_DMA( n ) WAIT_DMA_NUM( n )
-
-extern void prepare_rx_descriptor(struct etrax_dma_descr *desc);
-extern void flush_etrax_cache(void);
-
-#endif
diff --git a/include/asm-cris/arch-v10/system.h b/include/asm-cris/arch-v10/system.h
deleted file mode 100644
index 4a9cd36c9e16..000000000000
--- a/include/asm-cris/arch-v10/system.h
+++ /dev/null
@@ -1,63 +0,0 @@
-#ifndef __ASM_CRIS_ARCH_SYSTEM_H
-#define __ASM_CRIS_ARCH_SYSTEM_H
-
-
-/* read the CPU version register */
-
-static inline unsigned long rdvr(void) {
-	unsigned char vr;
-	__asm__ volatile ("move $vr,%0" : "=rm" (vr));
-	return vr;
-}
-
-#define cris_machine_name "cris"
-
-/* read/write the user-mode stackpointer */
-
-static inline unsigned long rdusp(void) {
-	unsigned long usp;
-	__asm__ __volatile__("move $usp,%0" : "=rm" (usp));
-	return usp;
-}
-
-#define wrusp(usp) \
-	__asm__ __volatile__("move %0,$usp" : /* no outputs */ : "rm" (usp))
-
-/* read the current stackpointer */
-
-static inline unsigned long rdsp(void) {
-	unsigned long sp;
-	__asm__ __volatile__("move.d $sp,%0" : "=rm" (sp));
-	return sp;
-}
-
-static inline unsigned long _get_base(char * addr)
-{
-  return 0;
-}
-
-#define nop() __asm__ __volatile__ ("nop");
-
-#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-#define tas(ptr) (xchg((ptr),1))
-
-struct __xchg_dummy { unsigned long a[100]; };
-#define __xg(x) ((struct __xchg_dummy *)(x))
-
-/* interrupt control.. */
-#define local_save_flags(x)	__asm__ __volatile__ ("move $ccr,%0" : "=rm" (x) : : "memory");
-#define local_irq_restore(x) 	__asm__ __volatile__ ("move %0,$ccr" : : "rm" (x) : "memory");
-#define local_irq_disable() 	__asm__ __volatile__ ( "di" : : :"memory");
-#define local_irq_enable()	__asm__ __volatile__ ( "ei" : : :"memory");
-
-#define irqs_disabled()			\
-({					\
-	unsigned long flags;		\
-	local_save_flags(flags);	\
-	!(flags & (1<<5));		\
-})
-
-/* For spinlocks etc */
-#define local_irq_save(x) __asm__ __volatile__ ("move $ccr,%0\n\tdi" : "=rm" (x) : : "memory");
-
-#endif
diff --git a/include/asm-cris/arch-v10/thread_info.h b/include/asm-cris/arch-v10/thread_info.h
deleted file mode 100644
index 218f4152d3e5..000000000000
--- a/include/asm-cris/arch-v10/thread_info.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _ASM_ARCH_THREAD_INFO_H
-#define _ASM_ARCH_THREAD_INFO_H
-
-/* how to get the thread information struct from C */
-static inline struct thread_info *current_thread_info(void)
-{
-	struct thread_info *ti;
-        __asm__("and.d $sp,%0; ":"=r" (ti) : "0" (~8191UL));
-        return ti;
-}
-
-#endif
diff --git a/include/asm-cris/arch-v10/timex.h b/include/asm-cris/arch-v10/timex.h
deleted file mode 100644
index e48447d94faf..000000000000
--- a/include/asm-cris/arch-v10/timex.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Use prescale timer at 25000 Hz instead of the baudrate timer at 
- * 19200 to get rid of the 64ppm to fast timer (and we get better 
- * resolution within a jiffie as well. 
- */
-#ifndef _ASM_CRIS_ARCH_TIMEX_H
-#define _ASM_CRIS_ARCH_TIMEX_H
-
-/* The prescaler clock runs at 25MHz, we divide it by 1000 in the prescaler */
-/* If you change anything here you must check time.c as well... */
-#define PRESCALE_FREQ 25000000
-#define PRESCALE_VALUE 1000
-#define CLOCK_TICK_RATE 25000 /* Underlying frequency of the HZ timer */
-/* The timer0 values gives 40us resolution (1/25000) but interrupts at HZ*/
-#define TIMER0_FREQ (CLOCK_TICK_RATE)
-#define TIMER0_CLKSEL flexible
-#define TIMER0_DIV (TIMER0_FREQ/(HZ))
-
-
-#define GET_JIFFIES_USEC() \
-  ( (TIMER0_DIV - *R_TIMER0_DATA) * (1000000/HZ)/TIMER0_DIV )
-
-unsigned long get_ns_in_jiffie(void);
-
-static inline unsigned long get_us_in_jiffie_highres(void)
-{
-	return get_ns_in_jiffie()/1000;
-}
-
-#endif
diff --git a/include/asm-cris/arch-v10/tlb.h b/include/asm-cris/arch-v10/tlb.h
deleted file mode 100644
index 31525bbe75c3..000000000000
--- a/include/asm-cris/arch-v10/tlb.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _CRIS_ARCH_TLB_H
-#define _CRIS_ARCH_TLB_H
-
-/* The TLB can host up to 64 different mm contexts at the same time.
- * The last page_id is never running - it is used as an invalid page_id
- * so we can make TLB entries that will never match. 
- */
-#define NUM_TLB_ENTRIES 64
-#define NUM_PAGEID 64
-#define INVALID_PAGEID 63
-#define NO_CONTEXT -1
-
-#endif
diff --git a/include/asm-cris/arch-v10/uaccess.h b/include/asm-cris/arch-v10/uaccess.h
deleted file mode 100644
index 65b02d9b605a..000000000000
--- a/include/asm-cris/arch-v10/uaccess.h
+++ /dev/null
@@ -1,660 +0,0 @@
-/* 
- * Authors:    Bjorn Wesen (bjornw@axis.com)
- *	       Hans-Peter Nilsson (hp@axis.com)
- *
- */
-#ifndef _CRIS_ARCH_UACCESS_H
-#define _CRIS_ARCH_UACCESS_H
-
-/*
- * We don't tell gcc that we are accessing memory, but this is OK
- * because we do not write to any memory gcc knows about, so there
- * are no aliasing issues.
- *
- * Note that PC at a fault is the address *after* the faulting
- * instruction.
- */
-#define __put_user_asm(x, addr, err, op)			\
-	__asm__ __volatile__(					\
-		"	"op" %1,[%2]\n"				\
-		"2:\n"						\
-		"	.section .fixup,\"ax\"\n"		\
-		"3:	move.d %3,%0\n"				\
-		"	jump 2b\n"				\
-		"	.previous\n"				\
-		"	.section __ex_table,\"a\"\n"		\
-		"	.dword 2b,3b\n"				\
-		"	.previous\n"				\
-		: "=r" (err)					\
-		: "r" (x), "r" (addr), "g" (-EFAULT), "0" (err))
-
-#define __put_user_asm_64(x, addr, err)				\
-	__asm__ __volatile__(					\
-		"	move.d %M1,[%2]\n"			\
-		"2:	move.d %H1,[%2+4]\n"			\
-		"4:\n"						\
-		"	.section .fixup,\"ax\"\n"		\
-		"3:	move.d %3,%0\n"				\
-		"	jump 4b\n"				\
-		"	.previous\n"				\
-		"	.section __ex_table,\"a\"\n"		\
-		"	.dword 2b,3b\n"				\
-		"	.dword 4b,3b\n"				\
-		"	.previous\n"				\
-		: "=r" (err)					\
-		: "r" (x), "r" (addr), "g" (-EFAULT), "0" (err))
-
-/* See comment before __put_user_asm.  */
-
-#define __get_user_asm(x, addr, err, op)		\
-	__asm__ __volatile__(				\
-		"	"op" [%2],%1\n"			\
-		"2:\n"					\
-		"	.section .fixup,\"ax\"\n"	\
-		"3:	move.d %3,%0\n"			\
-		"	moveq 0,%1\n"			\
-		"	jump 2b\n"			\
-		"	.previous\n"			\
-		"	.section __ex_table,\"a\"\n"	\
-		"	.dword 2b,3b\n"			\
-		"	.previous\n"			\
-		: "=r" (err), "=r" (x)			\
-		: "r" (addr), "g" (-EFAULT), "0" (err))
-
-#define __get_user_asm_64(x, addr, err)			\
-	__asm__ __volatile__(				\
-		"	move.d [%2],%M1\n"		\
-		"2:	move.d [%2+4],%H1\n"		\
-		"4:\n"					\
-		"	.section .fixup,\"ax\"\n"	\
-		"3:	move.d %3,%0\n"			\
-		"	moveq 0,%1\n"			\
-		"	jump 4b\n"			\
-		"	.previous\n"			\
-		"	.section __ex_table,\"a\"\n"	\
-		"	.dword 2b,3b\n"			\
-		"	.dword 4b,3b\n"			\
-		"	.previous\n"			\
-		: "=r" (err), "=r" (x)			\
-		: "r" (addr), "g" (-EFAULT), "0" (err))
-
-/*
- * Copy a null terminated string from userspace.
- *
- * Must return:
- * -EFAULT		for an exception
- * count		if we hit the buffer limit
- * bytes copied		if we hit a null byte
- * (without the null byte)
- */
-static inline long
-__do_strncpy_from_user(char *dst, const char *src, long count)
-{
-	long res;
-
-	if (count == 0)
-		return 0;
-
-	/*
-	 * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop.
-	 *  So do we.
-	 *
-	 *  This code is deduced from:
-	 *
-	 *	char tmp2;
-	 *	long tmp1, tmp3	
-	 *	tmp1 = count;
-	 *	while ((*dst++ = (tmp2 = *src++)) != 0
-	 *	       && --tmp1)
-	 *	  ;
-	 *
-	 *	res = count - tmp1;
-	 *
-	 *  with tweaks.
-	 */
-
-	__asm__ __volatile__ (
-		"	move.d %3,%0\n"
-		"	move.b [%2+],$r9\n"
-		"1:	beq 2f\n"
-		"	move.b $r9,[%1+]\n"
-
-		"	subq 1,%0\n"
-		"	bne 1b\n"
-		"	move.b [%2+],$r9\n"
-
-		"2:	sub.d %3,%0\n"
-		"	neg.d %0,%0\n"
-		"3:\n"
-		"	.section .fixup,\"ax\"\n"
-		"4:	move.d %7,%0\n"
-		"	jump 3b\n"
-
-		/* There's one address for a fault at the first move, and
-		   two possible PC values for a fault at the second move,
-		   being a delay-slot filler.  However, the branch-target
-		   for the second move is the same as the first address.
-		   Just so you don't get confused...  */
-		"	.previous\n"
-		"	.section __ex_table,\"a\"\n"
-		"	.dword 1b,4b\n"
-		"	.dword 2b,4b\n"
-		"	.previous"
-		: "=r" (res), "=r" (dst), "=r" (src), "=r" (count)
-		: "3" (count), "1" (dst), "2" (src), "g" (-EFAULT)
-		: "r9");
-
-	return res;
-}
-
-/* A few copy asms to build up the more complex ones from.
-
-   Note again, a post-increment is performed regardless of whether a bus
-   fault occurred in that instruction, and PC for a faulted insn is the
-   address *after* the insn.  */
-
-#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm__ __volatile__ (				\
-			COPY				\
-		"1:\n"					\
-		"	.section .fixup,\"ax\"\n"	\
-			FIXUP				\
-		"	jump 1b\n"			\
-		"	.previous\n"			\
-		"	.section __ex_table,\"a\"\n"	\
-			TENTRY				\
-		"	.previous\n"			\
-		: "=r" (to), "=r" (from), "=r" (ret)	\
-		: "0" (to), "1" (from), "2" (ret)	\
-		: "r9", "memory")
-
-#define __asm_copy_from_user_1(to, from, ret) \
-	__asm_copy_user_cont(to, from, ret,	\
-		"	move.b [%1+],$r9\n"	\
-		"2:	move.b $r9,[%0+]\n",	\
-		"3:	addq 1,%2\n"		\
-		"	clear.b [%0+]\n",	\
-		"	.dword 2b,3b\n")
-
-#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_user_cont(to, from, ret,		\
-		"	move.w [%1+],$r9\n"		\
-		"2:	move.w $r9,[%0+]\n" COPY,	\
-		"3:	addq 2,%2\n"			\
-		"	clear.w [%0+]\n" FIXUP,		\
-		"	.dword 2b,3b\n" TENTRY)
-
-#define __asm_copy_from_user_2(to, from, ret) \
-	__asm_copy_from_user_2x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_3(to, from, ret)		\
-	__asm_copy_from_user_2x_cont(to, from, ret,	\
-		"	move.b [%1+],$r9\n"		\
-		"4:	move.b $r9,[%0+]\n",		\
-		"5:	addq 1,%2\n"			\
-		"	clear.b [%0+]\n",		\
-		"	.dword 4b,5b\n")
-
-#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_user_cont(to, from, ret,		\
-		"	move.d [%1+],$r9\n"		\
-		"2:	move.d $r9,[%0+]\n" COPY,	\
-		"3:	addq 4,%2\n"			\
-		"	clear.d [%0+]\n" FIXUP,		\
-		"	.dword 2b,3b\n" TENTRY)
-
-#define __asm_copy_from_user_4(to, from, ret) \
-	__asm_copy_from_user_4x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_5(to, from, ret) \
-	__asm_copy_from_user_4x_cont(to, from, ret,	\
-		"	move.b [%1+],$r9\n"		\
-		"4:	move.b $r9,[%0+]\n",		\
-		"5:	addq 1,%2\n"			\
-		"	clear.b [%0+]\n",		\
-		"	.dword 4b,5b\n")
-
-#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_from_user_4x_cont(to, from, ret,	\
-		"	move.w [%1+],$r9\n"		\
-		"4:	move.w $r9,[%0+]\n" COPY,	\
-		"5:	addq 2,%2\n"			\
-		"	clear.w [%0+]\n" FIXUP,		\
-		"	.dword 4b,5b\n" TENTRY)
-
-#define __asm_copy_from_user_6(to, from, ret) \
-	__asm_copy_from_user_6x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_7(to, from, ret) \
-	__asm_copy_from_user_6x_cont(to, from, ret,	\
-		"	move.b [%1+],$r9\n"		\
-		"6:	move.b $r9,[%0+]\n",		\
-		"7:	addq 1,%2\n"			\
-		"	clear.b [%0+]\n",		\
-		"	.dword 6b,7b\n")
-
-#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_from_user_4x_cont(to, from, ret,	\
-		"	move.d [%1+],$r9\n"		\
-		"4:	move.d $r9,[%0+]\n" COPY,	\
-		"5:	addq 4,%2\n"			\
-		"	clear.d [%0+]\n" FIXUP,		\
-		"	.dword 4b,5b\n" TENTRY)
-
-#define __asm_copy_from_user_8(to, from, ret) \
-	__asm_copy_from_user_8x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_9(to, from, ret) \
-	__asm_copy_from_user_8x_cont(to, from, ret,	\
-		"	move.b [%1+],$r9\n"		\
-		"6:	move.b $r9,[%0+]\n",		\
-		"7:	addq 1,%2\n"			\
-		"	clear.b [%0+]\n",		\
-		"	.dword 6b,7b\n")
-
-#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_from_user_8x_cont(to, from, ret,	\
-		"	move.w [%1+],$r9\n"		\
-		"6:	move.w $r9,[%0+]\n" COPY,	\
-		"7:	addq 2,%2\n"			\
-		"	clear.w [%0+]\n" FIXUP,		\
-		"	.dword 6b,7b\n" TENTRY)
-
-#define __asm_copy_from_user_10(to, from, ret) \
-	__asm_copy_from_user_10x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_11(to, from, ret)		\
-	__asm_copy_from_user_10x_cont(to, from, ret,	\
-		"	move.b [%1+],$r9\n"		\
-		"8:	move.b $r9,[%0+]\n",		\
-		"9:	addq 1,%2\n"			\
-		"	clear.b [%0+]\n",		\
-		"	.dword 8b,9b\n")
-
-#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_from_user_8x_cont(to, from, ret,	\
-		"	move.d [%1+],$r9\n"		\
-		"6:	move.d $r9,[%0+]\n" COPY,	\
-		"7:	addq 4,%2\n"			\
-		"	clear.d [%0+]\n" FIXUP,		\
-		"	.dword 6b,7b\n" TENTRY)
-
-#define __asm_copy_from_user_12(to, from, ret) \
-	__asm_copy_from_user_12x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_13(to, from, ret) \
-	__asm_copy_from_user_12x_cont(to, from, ret,	\
-		"	move.b [%1+],$r9\n"		\
-		"8:	move.b $r9,[%0+]\n",		\
-		"9:	addq 1,%2\n"			\
-		"	clear.b [%0+]\n",		\
-		"	.dword 8b,9b\n")
-
-#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_from_user_12x_cont(to, from, ret,	\
-		"	move.w [%1+],$r9\n"		\
-		"8:	move.w $r9,[%0+]\n" COPY,	\
-		"9:	addq 2,%2\n"			\
-		"	clear.w [%0+]\n" FIXUP,		\
-		"	.dword 8b,9b\n" TENTRY)
-
-#define __asm_copy_from_user_14(to, from, ret) \
-	__asm_copy_from_user_14x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_15(to, from, ret) \
-	__asm_copy_from_user_14x_cont(to, from, ret,	\
-		"	move.b [%1+],$r9\n"		\
-		"10:	move.b $r9,[%0+]\n",		\
-		"11:	addq 1,%2\n"			\
-		"	clear.b [%0+]\n",		\
-		"	.dword 10b,11b\n")
-
-#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_from_user_12x_cont(to, from, ret,	\
-		"	move.d [%1+],$r9\n"		\
-		"8:	move.d $r9,[%0+]\n" COPY,	\
-		"9:	addq 4,%2\n"			\
-		"	clear.d [%0+]\n" FIXUP,		\
-		"	.dword 8b,9b\n" TENTRY)
-
-#define __asm_copy_from_user_16(to, from, ret) \
-	__asm_copy_from_user_16x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_from_user_16x_cont(to, from, ret,	\
-		"	move.d [%1+],$r9\n"		\
-		"10:	move.d $r9,[%0+]\n" COPY,	\
-		"11:	addq 4,%2\n"			\
-		"	clear.d [%0+]\n" FIXUP,		\
-		"	.dword 10b,11b\n" TENTRY)
-
-#define __asm_copy_from_user_20(to, from, ret) \
-	__asm_copy_from_user_20x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_from_user_20x_cont(to, from, ret,	\
-		"	move.d [%1+],$r9\n"		\
-		"12:	move.d $r9,[%0+]\n" COPY,	\
-		"13:	addq 4,%2\n"			\
-		"	clear.d [%0+]\n" FIXUP,		\
-		"	.dword 12b,13b\n" TENTRY)
-
-#define __asm_copy_from_user_24(to, from, ret) \
-	__asm_copy_from_user_24x_cont(to, from, ret, "", "", "")
-
-/* And now, the to-user ones.  */
-
-#define __asm_copy_to_user_1(to, from, ret)	\
-	__asm_copy_user_cont(to, from, ret,	\
-		"	move.b [%1+],$r9\n"	\
-		"	move.b $r9,[%0+]\n2:\n",	\
-		"3:	addq 1,%2\n",		\
-		"	.dword 2b,3b\n")
-
-#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_user_cont(to, from, ret,		\
-		"	move.w [%1+],$r9\n"		\
-		"	move.w $r9,[%0+]\n2:\n" COPY,	\
-		"3:	addq 2,%2\n" FIXUP,		\
-		"	.dword 2b,3b\n" TENTRY)
-
-#define __asm_copy_to_user_2(to, from, ret) \
-	__asm_copy_to_user_2x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_3(to, from, ret) \
-	__asm_copy_to_user_2x_cont(to, from, ret,	\
-		"	move.b [%1+],$r9\n"		\
-		"	move.b $r9,[%0+]\n4:\n",		\
-		"5:	addq 1,%2\n",			\
-		"	.dword 4b,5b\n")
-
-#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_user_cont(to, from, ret,		\
-		"	move.d [%1+],$r9\n"		\
-		"	move.d $r9,[%0+]\n2:\n" COPY,	\
-		"3:	addq 4,%2\n" FIXUP,		\
-		"	.dword 2b,3b\n" TENTRY)
-
-#define __asm_copy_to_user_4(to, from, ret) \
-	__asm_copy_to_user_4x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_5(to, from, ret) \
-	__asm_copy_to_user_4x_cont(to, from, ret,	\
-		"	move.b [%1+],$r9\n"		\
-		"	move.b $r9,[%0+]\n4:\n",		\
-		"5:	addq 1,%2\n",			\
-		"	.dword 4b,5b\n")
-
-#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_to_user_4x_cont(to, from, ret,	\
-		"	move.w [%1+],$r9\n"		\
-		"	move.w $r9,[%0+]\n4:\n" COPY,	\
-		"5:	addq 2,%2\n" FIXUP,		\
-		"	.dword 4b,5b\n" TENTRY)
-
-#define __asm_copy_to_user_6(to, from, ret) \
-	__asm_copy_to_user_6x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_7(to, from, ret) \
-	__asm_copy_to_user_6x_cont(to, from, ret,	\
-		"	move.b [%1+],$r9\n"		\
-		"	move.b $r9,[%0+]\n6:\n",		\
-		"7:	addq 1,%2\n",			\
-		"	.dword 6b,7b\n")
-
-#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_to_user_4x_cont(to, from, ret,	\
-		"	move.d [%1+],$r9\n"		\
-		"	move.d $r9,[%0+]\n4:\n" COPY,	\
-		"5:	addq 4,%2\n"  FIXUP,		\
-		"	.dword 4b,5b\n" TENTRY)
-
-#define __asm_copy_to_user_8(to, from, ret) \
-	__asm_copy_to_user_8x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_9(to, from, ret) \
-	__asm_copy_to_user_8x_cont(to, from, ret,	\
-		"	move.b [%1+],$r9\n"		\
-		"	move.b $r9,[%0+]\n6:\n",		\
-		"7:	addq 1,%2\n",			\
-		"	.dword 6b,7b\n")
-
-#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_to_user_8x_cont(to, from, ret,	\
-		"	move.w [%1+],$r9\n"		\
-		"	move.w $r9,[%0+]\n6:\n" COPY,	\
-		"7:	addq 2,%2\n" FIXUP,		\
-		"	.dword 6b,7b\n" TENTRY)
-
-#define __asm_copy_to_user_10(to, from, ret) \
-	__asm_copy_to_user_10x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_11(to, from, ret) \
-	__asm_copy_to_user_10x_cont(to, from, ret,	\
-		"	move.b [%1+],$r9\n"		\
-		"	move.b $r9,[%0+]\n8:\n",		\
-		"9:	addq 1,%2\n",			\
-		"	.dword 8b,9b\n")
-
-#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_to_user_8x_cont(to, from, ret,	\
-		"	move.d [%1+],$r9\n"		\
-		"	move.d $r9,[%0+]\n6:\n" COPY,	\
-		"7:	addq 4,%2\n" FIXUP,		\
-		"	.dword 6b,7b\n" TENTRY)
-
-#define __asm_copy_to_user_12(to, from, ret) \
-	__asm_copy_to_user_12x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_13(to, from, ret) \
-	__asm_copy_to_user_12x_cont(to, from, ret,	\
-		"	move.b [%1+],$r9\n"		\
-		"	move.b $r9,[%0+]\n8:\n",		\
-		"9:	addq 1,%2\n",			\
-		"	.dword 8b,9b\n")
-
-#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_to_user_12x_cont(to, from, ret,	\
-		"	move.w [%1+],$r9\n"		\
-		"	move.w $r9,[%0+]\n8:\n" COPY,	\
-		"9:	addq 2,%2\n" FIXUP,		\
-		"	.dword 8b,9b\n" TENTRY)
-
-#define __asm_copy_to_user_14(to, from, ret)	\
-	__asm_copy_to_user_14x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_15(to, from, ret) \
-	__asm_copy_to_user_14x_cont(to, from, ret,	\
-		"	move.b [%1+],$r9\n"		\
-		"	move.b $r9,[%0+]\n10:\n",		\
-		"11:	addq 1,%2\n",			\
-		"	.dword 10b,11b\n")
-
-#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_to_user_12x_cont(to, from, ret,	\
-		"	move.d [%1+],$r9\n"		\
-		"	move.d $r9,[%0+]\n8:\n" COPY,	\
-		"9:	addq 4,%2\n" FIXUP,		\
-		"	.dword 8b,9b\n" TENTRY)
-
-#define __asm_copy_to_user_16(to, from, ret) \
-	__asm_copy_to_user_16x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_to_user_16x_cont(to, from, ret,	\
-		"	move.d [%1+],$r9\n"		\
-		"	move.d $r9,[%0+]\n10:\n" COPY,	\
-		"11:	addq 4,%2\n" FIXUP,		\
-		"	.dword 10b,11b\n" TENTRY)
-
-#define __asm_copy_to_user_20(to, from, ret) \
-	__asm_copy_to_user_20x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY)	\
-	__asm_copy_to_user_20x_cont(to, from, ret,	\
-		"	move.d [%1+],$r9\n"		\
-		"	move.d $r9,[%0+]\n12:\n" COPY,	\
-		"13:	addq 4,%2\n" FIXUP,		\
-		"	.dword 12b,13b\n" TENTRY)
-
-#define __asm_copy_to_user_24(to, from, ret)	\
-	__asm_copy_to_user_24x_cont(to, from, ret, "", "", "")
-
-/* Define a few clearing asms with exception handlers.  */
-
-/* This frame-asm is like the __asm_copy_user_cont one, but has one less
-   input.  */
-
-#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \
-	__asm__ __volatile__ (				\
-			CLEAR				\
-		"1:\n"					\
-		"	.section .fixup,\"ax\"\n"	\
-			FIXUP				\
-		"	jump 1b\n"			\
-		"	.previous\n"			\
-		"	.section __ex_table,\"a\"\n"	\
-			TENTRY				\
-		"	.previous"			\
-		: "=r" (to), "=r" (ret)			\
-		: "0" (to), "1" (ret)			\
-		: "memory")
-
-#define __asm_clear_1(to, ret) \
-	__asm_clear(to, ret,			\
-		"	clear.b [%0+]\n2:\n",	\
-		"3:	addq 1,%1\n",		\
-		"	.dword 2b,3b\n")
-
-#define __asm_clear_2(to, ret) \
-	__asm_clear(to, ret,			\
-		"	clear.w [%0+]\n2:\n",	\
-		"3:	addq 2,%1\n",		\
-		"	.dword 2b,3b\n")
-
-#define __asm_clear_3(to, ret) \
-     __asm_clear(to, ret,			\
-		 "	clear.w [%0+]\n"	\
-		 "2:	clear.b [%0+]\n3:\n",	\
-		 "4:	addq 2,%1\n"		\
-		 "5:	addq 1,%1\n",		\
-		 "	.dword 2b,4b\n"		\
-		 "	.dword 3b,5b\n")
-
-#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
-	__asm_clear(to, ret,				\
-		"	clear.d [%0+]\n2:\n" CLEAR,	\
-		"3:	addq 4,%1\n" FIXUP,		\
-		"	.dword 2b,3b\n" TENTRY)
-
-#define __asm_clear_4(to, ret) \
-	__asm_clear_4x_cont(to, ret, "", "", "")
-
-#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
-	__asm_clear_4x_cont(to, ret,			\
-		"	clear.d [%0+]\n4:\n" CLEAR,	\
-		"5:	addq 4,%1\n" FIXUP,		\
-		"	.dword 4b,5b\n" TENTRY)
-
-#define __asm_clear_8(to, ret) \
-	__asm_clear_8x_cont(to, ret, "", "", "")
-
-#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
-	__asm_clear_8x_cont(to, ret,			\
-		"	clear.d [%0+]\n6:\n" CLEAR,	\
-		"7:	addq 4,%1\n" FIXUP,		\
-		"	.dword 6b,7b\n" TENTRY)
-
-#define __asm_clear_12(to, ret) \
-	__asm_clear_12x_cont(to, ret, "", "", "")
-
-#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
-	__asm_clear_12x_cont(to, ret,			\
-		"	clear.d [%0+]\n8:\n" CLEAR,	\
-		"9:	addq 4,%1\n" FIXUP,		\
-		"	.dword 8b,9b\n" TENTRY)
-
-#define __asm_clear_16(to, ret) \
-	__asm_clear_16x_cont(to, ret, "", "", "")
-
-#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
-	__asm_clear_16x_cont(to, ret,			\
-		"	clear.d [%0+]\n10:\n" CLEAR,	\
-		"11:	addq 4,%1\n" FIXUP,		\
-		"	.dword 10b,11b\n" TENTRY)
-
-#define __asm_clear_20(to, ret) \
-	__asm_clear_20x_cont(to, ret, "", "", "")
-
-#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
-	__asm_clear_20x_cont(to, ret,			\
-		"	clear.d [%0+]\n12:\n" CLEAR,	\
-		"13:	addq 4,%1\n" FIXUP,		\
-		"	.dword 12b,13b\n" TENTRY)
-
-#define __asm_clear_24(to, ret) \
-	__asm_clear_24x_cont(to, ret, "", "", "")
-
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return length of string in userspace including terminating 0
- * or 0 for error.  Return a value greater than N if too long.
- */
-
-static inline long
-strnlen_user(const char *s, long n)
-{
-	long res, tmp1;
-
-	if (!access_ok(VERIFY_READ, s, 0))
-		return 0;
-
-	/*
-	 * This code is deduced from:
-	 *
-	 *	tmp1 = n;
-	 *	while (tmp1-- > 0 && *s++)
-	 *	  ;
-	 *
-	 *	res = n - tmp1;
-	 *
-	 *  (with tweaks).
-	 */
-
-	__asm__ __volatile__ (
-		"	move.d %1,$r9\n"
-		"0:\n"
-		"	ble 1f\n"
-		"	subq 1,$r9\n"
-
-		"	test.b [%0+]\n"
-		"	bne 0b\n"
-		"	test.d $r9\n"
-		"1:\n"
-		"	move.d %1,%0\n"
-		"	sub.d $r9,%0\n"
-		"2:\n"
-		"	.section .fixup,\"ax\"\n"
-
-		"3:	clear.d %0\n"
-		"	jump 2b\n"
-
-		/* There's one address for a fault at the first move, and
-		   two possible PC values for a fault at the second move,
-		   being a delay-slot filler.  However, the branch-target
-		   for the second move is the same as the first address.
-		   Just so you don't get confused...  */
-		"	.previous\n"
-		"	.section __ex_table,\"a\"\n"
-		"	.dword 0b,3b\n"
-		"	.dword 1b,3b\n"
-		"	.previous\n"
-		: "=r" (res), "=r" (tmp1)
-		: "0" (s), "1" (n)
-		: "r9");
-
-	return res;
-}
-
-#endif
diff --git a/include/asm-cris/arch-v10/unistd.h b/include/asm-cris/arch-v10/unistd.h
deleted file mode 100644
index d1a38b9e6264..000000000000
--- a/include/asm-cris/arch-v10/unistd.h
+++ /dev/null
@@ -1,148 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_UNISTD_H_
-#define _ASM_CRIS_ARCH_UNISTD_H_
-
-/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
-/*
- * Don't remove the .ifnc tests; they are an insurance against
- * any hard-to-spot gcc register allocation bugs.
- */
-#define _syscall0(type,name) \
-type name(void) \
-{ \
-  register long __a __asm__ ("r10"); \
-  register long __n_ __asm__ ("r9") = (__NR_##name); \
-  __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
-			".err\n\t" \
-			".endif\n\t" \
-			"break 13" \
-			: "=r" (__a) \
-			: "r" (__n_)); \
-  if (__a >= 0) \
-     return (type) __a; \
-  errno = -__a; \
-  return (type) -1; \
-}
-
-#define _syscall1(type,name,type1,arg1) \
-type name(type1 arg1) \
-{ \
-  register long __a __asm__ ("r10") = (long) arg1; \
-  register long __n_ __asm__ ("r9") = (__NR_##name); \
-  __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
-			".err\n\t" \
-			".endif\n\t" \
-			"break 13" \
-			: "=r" (__a) \
-			: "r" (__n_), "0" (__a)); \
-  if (__a >= 0) \
-     return (type) __a; \
-  errno = -__a; \
-  return (type) -1; \
-}
-
-#define _syscall2(type,name,type1,arg1,type2,arg2) \
-type name(type1 arg1,type2 arg2) \
-{ \
-  register long __a __asm__ ("r10") = (long) arg1; \
-  register long __b __asm__ ("r11") = (long) arg2; \
-  register long __n_ __asm__ ("r9") = (__NR_##name); \
-  __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \
-			".err\n\t" \
-			".endif\n\t" \
-			"break 13" \
-			: "=r" (__a) \
-			: "r" (__n_), "0" (__a), "r" (__b)); \
-  if (__a >= 0) \
-     return (type) __a; \
-  errno = -__a; \
-  return (type) -1; \
-}
-
-#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
-type name(type1 arg1,type2 arg2,type3 arg3) \
-{ \
-  register long __a __asm__ ("r10") = (long) arg1; \
-  register long __b __asm__ ("r11") = (long) arg2; \
-  register long __c __asm__ ("r12") = (long) arg3; \
-  register long __n_ __asm__ ("r9") = (__NR_##name); \
-  __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \
-			".err\n\t" \
-			".endif\n\t" \
-			"break 13" \
-			: "=r" (__a) \
-			: "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \
-  if (__a >= 0) \
-     return (type) __a; \
-  errno = -__a; \
-  return (type) -1; \
-}
-
-#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
-type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
-{ \
-  register long __a __asm__ ("r10") = (long) arg1; \
-  register long __b __asm__ ("r11") = (long) arg2; \
-  register long __c __asm__ ("r12") = (long) arg3; \
-  register long __d __asm__ ("r13") = (long) arg4; \
-  register long __n_ __asm__ ("r9") = (__NR_##name); \
-  __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
-			".err\n\t" \
-			".endif\n\t" \
-			"break 13" \
-			: "=r" (__a) \
-			: "r" (__n_), "0" (__a), "r" (__b), \
-			  "r" (__c), "r" (__d)); \
-  if (__a >= 0) \
-     return (type) __a; \
-  errno = -__a; \
-  return (type) -1; \
-} 
-
-#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
-	  type5,arg5) \
-type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \
-{ \
-  register long __a __asm__ ("r10") = (long) arg1; \
-  register long __b __asm__ ("r11") = (long) arg2; \
-  register long __c __asm__ ("r12") = (long) arg3; \
-  register long __d __asm__ ("r13") = (long) arg4; \
-  register long __n_ __asm__ ("r9") = (__NR_##name); \
-  __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
-			".err\n\t" \
-			".endif\n\t" \
-			"move %6,$mof\n\t" \
-			"break 13" \
-			: "=r" (__a) \
-			: "r" (__n_), "0" (__a), "r" (__b), \
-			  "r" (__c), "r" (__d), "g" (arg5)); \
-  if (__a >= 0) \
-     return (type) __a; \
-  errno = -__a; \
-  return (type) -1; \
-}
-
-#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
-	  type5,arg5,type6,arg6) \
-type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \
-{ \
-  register long __a __asm__ ("r10") = (long) arg1; \
-  register long __b __asm__ ("r11") = (long) arg2; \
-  register long __c __asm__ ("r12") = (long) arg3; \
-  register long __d __asm__ ("r13") = (long) arg4; \
-  register long __n_ __asm__ ("r9") = (__NR_##name); \
-  __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
-			".err\n\t" \
-			".endif\n\t" \
-			"move %6,$mof\n\tmove %7,$srp\n\t" \
-			"break 13" \
-			: "=r" (__a) \
-			: "r" (__n_), "0" (__a), "r" (__b), \
-			  "r" (__c), "r" (__d), "g" (arg5), "g" (arg6)\
-			: "srp"); \
-  if (__a >= 0) \
-     return (type) __a; \
-  errno = -__a; \
-  return (type) -1; \
-}
-
-#endif
diff --git a/include/asm-cris/arch-v10/user.h b/include/asm-cris/arch-v10/user.h
deleted file mode 100644
index 9303ea77c915..000000000000
--- a/include/asm-cris/arch-v10/user.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef __ASM_CRIS_ARCH_USER_H
-#define __ASM_CRIS_ARCH_USER_H
-
-/* User mode registers, used for core dumps. In order to keep ELF_NGREG
-   sensible we let all registers be 32 bits. The csr registers are included
-   for future use. */
-struct user_regs_struct {
-        unsigned long r0;       /* General registers. */
-        unsigned long r1;
-        unsigned long r2;
-        unsigned long r3;
-        unsigned long r4;
-        unsigned long r5;
-        unsigned long r6;
-        unsigned long r7;
-        unsigned long r8;
-        unsigned long r9;
-        unsigned long r10;
-        unsigned long r11;
-        unsigned long r12;
-        unsigned long r13;
-        unsigned long sp;       /* Stack pointer. */
-        unsigned long pc;       /* Program counter. */
-        unsigned long p0;       /* Constant zero (only 8 bits). */
-        unsigned long vr;       /* Version register (only 8 bits). */
-        unsigned long p2;       /* Reserved. */
-        unsigned long p3;       /* Reserved. */
-        unsigned long p4;       /* Constant zero (only 16 bits). */
-        unsigned long ccr;      /* Condition code register (only 16 bits). */
-        unsigned long p6;       /* Reserved. */
-        unsigned long mof;      /* Multiply overflow register. */
-        unsigned long p8;       /* Constant zero. */
-        unsigned long ibr;      /* Not accessible. */
-        unsigned long irp;      /* Not accessible. */
-        unsigned long srp;      /* Subroutine return pointer. */
-        unsigned long bar;      /* Not accessible. */
-        unsigned long dccr;     /* Dword condition code register. */
-        unsigned long brp;      /* Not accessible. */
-        unsigned long usp;      /* User-mode stack pointer. Same as sp when 
-                                   in user mode. */
-        unsigned long csrinstr; /* Internal status registers. */
-        unsigned long csraddr;
-        unsigned long csrdata;
-};
-
-#endif
diff --git a/include/asm-cris/arch-v32/Kbuild b/include/asm-cris/arch-v32/Kbuild
deleted file mode 100644
index 35f2fc4f993e..000000000000
--- a/include/asm-cris/arch-v32/Kbuild
+++ /dev/null
@@ -1,2 +0,0 @@
-header-y += user.h
-header-y += cryptocop.h
diff --git a/include/asm-cris/arch-v32/arbiter.h b/include/asm-cris/arch-v32/arbiter.h
deleted file mode 100644
index 081a911d7af1..000000000000
--- a/include/asm-cris/arch-v32/arbiter.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_ARBITER_H
-#define _ASM_CRIS_ARCH_ARBITER_H
-
-#define EXT_REGION 0
-#define INT_REGION 1
-
-typedef void (watch_callback)(void);
-
-enum
-{
-  arbiter_all_dmas = 0x3ff,
-  arbiter_cpu = 0xc00,
-  arbiter_all_clients = 0x3fff
-};
-
-enum
-{
-  arbiter_all_read = 0x55,
-  arbiter_all_write = 0xaa,
-  arbiter_all_accesses = 0xff
-};
-
-int crisv32_arbiter_allocate_bandwidth(int client, int region,
-				       unsigned long bandwidth);
-int crisv32_arbiter_watch(unsigned long start, unsigned long size,
-                          unsigned long clients, unsigned long accesses,
-                          watch_callback* cb);
-int crisv32_arbiter_unwatch(int id);
-
-#endif
diff --git a/include/asm-cris/arch-v32/atomic.h b/include/asm-cris/arch-v32/atomic.h
deleted file mode 100644
index 852ceff8013f..000000000000
--- a/include/asm-cris/arch-v32/atomic.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef __ASM_CRIS_ARCH_ATOMIC__
-#define __ASM_CRIS_ARCH_ATOMIC__
-
-#include <linux/spinlock_types.h>
-
-extern void cris_spin_unlock(void *l, int val);
-extern void cris_spin_lock(void *l);
-extern int cris_spin_trylock(void* l);
-
-#ifndef CONFIG_SMP
-#define cris_atomic_save(addr, flags) local_irq_save(flags);
-#define cris_atomic_restore(addr, flags) local_irq_restore(flags);
-#else
-
-extern spinlock_t cris_atomic_locks[];
-#define LOCK_COUNT 128
-#define HASH_ADDR(a) (((int)a) & 127)
-
-#define cris_atomic_save(addr, flags) \
-  local_irq_save(flags); \
-  cris_spin_lock((void *)&cris_atomic_locks[HASH_ADDR(addr)].raw_lock.slock);
-
-#define cris_atomic_restore(addr, flags) \
-  { \
-    spinlock_t *lock = (void*)&cris_atomic_locks[HASH_ADDR(addr)]; \
-    __asm__ volatile ("move.d %1,%0" \
-			: "=m" (lock->raw_lock.slock) \
-			: "r" (1) \
-			: "memory"); \
-    local_irq_restore(flags); \
-  }
-
-#endif
-
-#endif
-
diff --git a/include/asm-cris/arch-v32/bitops.h b/include/asm-cris/arch-v32/bitops.h
deleted file mode 100644
index 147689d6b624..000000000000
--- a/include/asm-cris/arch-v32/bitops.h
+++ /dev/null
@@ -1,64 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_BITOPS_H
-#define _ASM_CRIS_ARCH_BITOPS_H
-
-/*
- * Helper functions for the core of the ff[sz] functions. They compute the
- * number of leading zeroes of a bits-in-byte, byte-in-word and
- * word-in-dword-swapped number. They differ in that the first function also
- * inverts all bits in the input.
- */
-
-static inline unsigned long
-cris_swapnwbrlz(unsigned long w)
-{
-	unsigned long res;
-
-	__asm__ __volatile__ ("swapnwbr %0\n\t"
-			      "lz %0,%0"
-			      : "=r" (res) : "0" (w));
-
-	return res;
-}
-
-static inline unsigned long
-cris_swapwbrlz(unsigned long w)
-{
-	unsigned long res;
-
-	__asm__ __volatile__ ("swapwbr %0\n\t"
-			      "lz %0,%0"
-			      : "=r" (res) : "0" (w));
-
-	return res;
-}
-
-/*
- * Find First Zero in word. Undefined if no zero exist, so the caller should
- * check against ~0 first.
- */
-static inline unsigned long
-ffz(unsigned long w)
-{
-	return cris_swapnwbrlz(w);
-}
-
-/*
- * Find First Set bit in word. Undefined if no 1 exist, so the caller
- * should check against 0 first.
- */
-static inline unsigned long
-__ffs(unsigned long w)
-{
-	return cris_swapnwbrlz(~w);
-}
-
-/*
- * Find First Bit that is set.
- */
-static inline unsigned long
-kernel_ffs(unsigned long w)
-{
-	return w ? cris_swapwbrlz (w) + 1 : 0;
-}
-
-#endif /* _ASM_CRIS_ARCH_BITOPS_H */
diff --git a/include/asm-cris/arch-v32/bug.h b/include/asm-cris/arch-v32/bug.h
deleted file mode 100644
index 0f211e135248..000000000000
--- a/include/asm-cris/arch-v32/bug.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef __ASM_CRISv32_ARCH_BUG_H
-#define __ASM_CRISv32_ARCH_BUG_H
-
-#include <linux/stringify.h>
-
-#ifdef CONFIG_BUG
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-/*
- * The penalty for the in-band code path will be the size of break 14.
- * All other stuff is done out-of-band with exception handlers.
- */
-#define BUG()								\
-	__asm__ __volatile__ ("0: break 14\n\t"				\
-			      ".section .fixup,\"ax\"\n"		\
-			      "1:\n\t"					\
-			      "move.d %0, $r10\n\t"			\
-			      "move.d %1, $r11\n\t"			\
-			      "jump do_BUG\n\t"				\
-			      "nop\n\t"					\
-			      ".previous\n\t"				\
-			      ".section __ex_table,\"a\"\n\t"		\
-			      ".dword 0b, 1b\n\t"			\
-			      ".previous\n\t"				\
-			      : : "ri" (__FILE__), "i" (__LINE__))
-#else
-#define BUG() __asm__ __volatile__ ("break 14\n\t")
-#endif
-
-#define HAVE_ARCH_BUG
-#endif
-
-#include <asm-generic/bug.h>
-#endif
diff --git a/include/asm-cris/arch-v32/byteorder.h b/include/asm-cris/arch-v32/byteorder.h
deleted file mode 100644
index 6ef8fb4a35f2..000000000000
--- a/include/asm-cris/arch-v32/byteorder.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_BYTEORDER_H
-#define _ASM_CRIS_ARCH_BYTEORDER_H
-
-#include <asm/types.h>
-
-static inline __const__ __u32
-___arch__swab32(__u32 x)
-{
-	__asm__ __volatile__ ("swapwb %0" : "=r" (x) : "0" (x));
-	return (x);
-}
-
-static inline __const__ __u16
-___arch__swab16(__u16 x)
-{
-	__asm__ __volatile__ ("swapb %0" : "=r" (x) : "0" (x));
-	return (x);
-}
-
-#endif /* _ASM_CRIS_ARCH_BYTEORDER_H */
diff --git a/include/asm-cris/arch-v32/cache.h b/include/asm-cris/arch-v32/cache.h
deleted file mode 100644
index b3d752dfe15b..000000000000
--- a/include/asm-cris/arch-v32/cache.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_CACHE_H
-#define _ASM_CRIS_ARCH_CACHE_H
-
-#include <asm/arch/hwregs/dma.h>
-
-/* A cache-line is 32 bytes. */
-#define L1_CACHE_BYTES 32
-#define L1_CACHE_SHIFT 5
-
-void flush_dma_list(dma_descr_data *descr);
-void flush_dma_descr(dma_descr_data *descr, int flush_buf);
-
-#define flush_dma_context(c) \
-  flush_dma_list(phys_to_virt((c)->saved_data));
-
-void cris_flush_cache_range(void *buf, unsigned long len);
-void cris_flush_cache(void);
-
-#endif /* _ASM_CRIS_ARCH_CACHE_H */
diff --git a/include/asm-cris/arch-v32/checksum.h b/include/asm-cris/arch-v32/checksum.h
deleted file mode 100644
index e5dcfce6e0dc..000000000000
--- a/include/asm-cris/arch-v32/checksum.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_CHECKSUM_H
-#define _ASM_CRIS_ARCH_CHECKSUM_H
-
-/*
- * Check values used in TCP/UDP headers.
- *
- * The gain of doing this in assembler instead of C, is that C doesn't
- * generate carry-additions for the 32-bit components of the
- * checksum. Which means it would be necessary to split all those into
- * 16-bit components and then add.
- */
-static inline __wsum
-csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
-		   unsigned short len, unsigned short proto, __wsum sum)
-{
-	__wsum res;
-
-	__asm__ __volatile__ ("add.d %2, %0\n\t"
-			      "addc %3, %0\n\t"
-			      "addc %4, %0\n\t"
-			      "addc 0, %0\n\t"
-			      : "=r" (res)
-			      : "0" (sum), "r" (daddr), "r" (saddr), \
-			      "r" ((len + proto) << 8));
-
-	return res;
-}
-
-#endif /* _ASM_CRIS_ARCH_CHECKSUM_H */
diff --git a/include/asm-cris/arch-v32/cryptocop.h b/include/asm-cris/arch-v32/cryptocop.h
deleted file mode 100644
index dfa1f66fb987..000000000000
--- a/include/asm-cris/arch-v32/cryptocop.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * The device /dev/cryptocop is accessible using this driver using
- * CRYPTOCOP_MAJOR (254) and minor number 0.
- */
-
-#ifndef CRYPTOCOP_H
-#define CRYPTOCOP_H
-
-#include <linux/uio.h>
-
-
-#define CRYPTOCOP_SESSION_ID_NONE (0)
-
-typedef unsigned long long int cryptocop_session_id;
-
-/* cryptocop ioctls */
-#define ETRAXCRYPTOCOP_IOCTYPE         (250)
-
-#define CRYPTOCOP_IO_CREATE_SESSION    _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 1, struct strcop_session_op)
-#define CRYPTOCOP_IO_CLOSE_SESSION     _IOW(ETRAXCRYPTOCOP_IOCTYPE, 2, struct strcop_session_op)
-#define CRYPTOCOP_IO_PROCESS_OP        _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 3, struct strcop_crypto_op)
-#define CRYPTOCOP_IO_MAXNR             (3)
-
-typedef enum {
-	cryptocop_cipher_des = 0,
-	cryptocop_cipher_3des = 1,
-	cryptocop_cipher_aes = 2,
-	cryptocop_cipher_m2m = 3, /* mem2mem is essentially a NULL cipher with blocklength=1 */
-	cryptocop_cipher_none
-} cryptocop_cipher_type;
-
-typedef enum {
-	cryptocop_digest_sha1 = 0,
-	cryptocop_digest_md5 = 1,
-	cryptocop_digest_none
-} cryptocop_digest_type;
-
-typedef enum {
-	cryptocop_csum_le = 0,
-	cryptocop_csum_be = 1,
-	cryptocop_csum_none
-} cryptocop_csum_type;
-
-typedef enum {
-	cryptocop_cipher_mode_ecb = 0,
-	cryptocop_cipher_mode_cbc,
-	cryptocop_cipher_mode_none
-} cryptocop_cipher_mode;
-
-typedef enum {
-	cryptocop_3des_eee = 0,
-	cryptocop_3des_eed = 1,
-	cryptocop_3des_ede = 2,
-	cryptocop_3des_edd = 3,
-	cryptocop_3des_dee = 4,
-	cryptocop_3des_ded = 5,
-	cryptocop_3des_dde = 6,
-	cryptocop_3des_ddd = 7
-} cryptocop_3des_mode;
-
-/* Usermode accessible (ioctl) operations. */
-struct strcop_session_op{
-	cryptocop_session_id    ses_id;
-
-	cryptocop_cipher_type   cipher; /* AES, DES, 3DES, m2m, none */
-
-	cryptocop_cipher_mode   cmode; /* ECB, CBC, none */
-	cryptocop_3des_mode     des3_mode;
-
-	cryptocop_digest_type   digest; /* MD5, SHA1, none */
-
-	cryptocop_csum_type     csum;   /* BE, LE, none */
-
-	unsigned char           *key;
-	size_t                  keylen;
-};
-
-#define CRYPTOCOP_CSUM_LENGTH         (2)
-#define CRYPTOCOP_MAX_DIGEST_LENGTH   (20)  /* SHA-1 20, MD5 16 */
-#define CRYPTOCOP_MAX_IV_LENGTH       (16)  /* (3)DES==8, AES == 16 */
-#define CRYPTOCOP_MAX_KEY_LENGTH      (32)
-
-struct strcop_crypto_op{
-	cryptocop_session_id ses_id;
-
-	/* Indata. */
-	unsigned char            *indata;
-	size_t                   inlen; /* Total indata length. */
-
-	/* Cipher configuration. */
-	unsigned char            do_cipher:1;
-	unsigned char            decrypt:1; /* 1 == decrypt, 0 == encrypt */
-	unsigned char            cipher_explicit:1;
-	size_t                   cipher_start;
-	size_t                   cipher_len;
-	/* cipher_iv is used if do_cipher and cipher_explicit and the cipher
-	   mode is CBC.  The length is controlled by the type of cipher,
-	   e.g. DES/3DES 8 octets and AES 16 octets. */
-	unsigned char            cipher_iv[CRYPTOCOP_MAX_IV_LENGTH];
-	/* Outdata. */
-	unsigned char            *cipher_outdata;
-	size_t                   cipher_outlen;
-
-	/* digest configuration. */
-	unsigned char            do_digest:1;
-	size_t                   digest_start;
-	size_t                   digest_len;
-	/* Outdata.  The actual length is determined by the type of the digest. */
-	unsigned char            digest[CRYPTOCOP_MAX_DIGEST_LENGTH];
-
-	/* Checksum configuration. */
-	unsigned char            do_csum:1;
-	size_t                   csum_start;
-	size_t                   csum_len;
-	/* Outdata. */
-	unsigned char            csum[CRYPTOCOP_CSUM_LENGTH];
-};
-
-
-
-#ifdef __KERNEL__
-
-/********** The API to use from inside the kernel. ************/
-
-#include <asm/arch/hwregs/dma.h>
-
-typedef enum {
-	cryptocop_alg_csum = 0,
-	cryptocop_alg_mem2mem,
-	cryptocop_alg_md5,
-	cryptocop_alg_sha1,
-	cryptocop_alg_des,
-	cryptocop_alg_3des,
-	cryptocop_alg_aes,
-	cryptocop_no_alg,
-} cryptocop_algorithm;
-
-typedef u8 cryptocop_tfrm_id;
-
-
-struct cryptocop_operation;
-
-typedef void (cryptocop_callback)(struct cryptocop_operation*, void*);
-
-struct cryptocop_transform_init {
-	cryptocop_algorithm    alg;
-	/* Keydata for ciphers. */
-	unsigned char          key[CRYPTOCOP_MAX_KEY_LENGTH];
-	unsigned int           keylen;
-	cryptocop_cipher_mode  cipher_mode;
-	cryptocop_3des_mode    tdes_mode;
-	cryptocop_csum_type    csum_mode; /* cryptocop_csum_none is not allowed when alg==cryptocop_alg_csum */
-
-	cryptocop_tfrm_id tid; /* Locally unique in session; assigned by user, checked by driver. */
-	struct cryptocop_transform_init *next;
-};
-
-
-typedef enum {
-	cryptocop_source_dma = 0,
-	cryptocop_source_des,
-	cryptocop_source_3des,
-	cryptocop_source_aes,
-	cryptocop_source_md5,
-	cryptocop_source_sha1,
-	cryptocop_source_csum,
-	cryptocop_source_none,
-} cryptocop_source;
-
-
-struct cryptocop_desc_cfg {
-	cryptocop_tfrm_id tid;
-	cryptocop_source src;
-	unsigned int last:1; /* Last use of this transform in the operation.  Will push outdata when encountered. */
-	struct cryptocop_desc_cfg *next;
-};
-
-struct cryptocop_desc {
-	size_t length;
-	struct cryptocop_desc_cfg *cfg;
-	struct cryptocop_desc *next;
-};
-
-
-/* Flags for cryptocop_tfrm_cfg */
-#define CRYPTOCOP_NO_FLAG     (0x00)
-#define CRYPTOCOP_ENCRYPT     (0x01)
-#define CRYPTOCOP_DECRYPT     (0x02)
-#define CRYPTOCOP_EXPLICIT_IV (0x04)
-
-struct cryptocop_tfrm_cfg {
-	cryptocop_tfrm_id tid;
-
-	unsigned int flags; /* DECRYPT, ENCRYPT, EXPLICIT_IV */
-
-	/* CBC initialisation vector for cihers. */
-	u8 iv[CRYPTOCOP_MAX_IV_LENGTH];
-
-	/* The position in output where to write the transform output.  The order
-	   in which the driver writes the output is unspecified, hence if several
-	   transforms write on the same positions in the output the result is
-	   unspecified. */
-	size_t inject_ix;
-
-	struct cryptocop_tfrm_cfg *next;
-};
-
-
-
-struct cryptocop_dma_list_operation{
-	/* The consumer can provide DMA lists to send to the co-processor.  'use_dmalists' in
-	   struct cryptocop_operation must be set for the driver to use them.  outlist,
-	   out_data_buf, inlist and in_data_buf must all be physical addresses since they will
-	   be loaded to DMA . */
-	dma_descr_data *outlist; /* Out from memory to the co-processor. */
-	char           *out_data_buf;
-	dma_descr_data *inlist; /* In from the co-processor to memory. */
-	char           *in_data_buf;
-
-	cryptocop_3des_mode tdes_mode;
-	cryptocop_csum_type csum_mode;
-};
-
-
-struct cryptocop_tfrm_operation{
-	/* Operation configuration, if not 'use_dmalists' is set. */
-	struct cryptocop_tfrm_cfg *tfrm_cfg;
-	struct cryptocop_desc *desc;
-
-	struct iovec *indata;
-	size_t incount;
-	size_t inlen; /* Total inlength. */
-
-	struct iovec *outdata;
-	size_t outcount;
-	size_t outlen; /* Total outlength. */
-};
-
-
-struct cryptocop_operation {
-	cryptocop_callback *cb;
-	void *cb_data;
-
-	cryptocop_session_id sid;
-
-	/* The status of the operation when returned to consumer. */
-	int operation_status; /* 0, -EAGAIN */
-
-	/* Flags */
-	unsigned int use_dmalists:1;  /* Use outlist and inlist instead of the desc/tfrm_cfg configuration. */
-	unsigned int in_interrupt:1;  /* Set if inserting job from interrupt context. */
-	unsigned int fast_callback:1; /* Set if fast callback wanted, i.e. from interrupt context. */
-
-	union{
-		struct cryptocop_dma_list_operation list_op;
-		struct cryptocop_tfrm_operation tfrm_op;
-	};
-};
-
-
-int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag);
-int cryptocop_free_session(cryptocop_session_id sid);
-
-int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation);
-
-int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation);
-
-int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation);
-
-#endif /* __KERNEL__ */
-
-#endif /* CRYPTOCOP_H */
diff --git a/include/asm-cris/arch-v32/delay.h b/include/asm-cris/arch-v32/delay.h
deleted file mode 100644
index e9fda03810a9..000000000000
--- a/include/asm-cris/arch-v32/delay.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_DELAY_H
-#define _ASM_CRIS_ARCH_DELAY_H
-
-extern void cris_delay10ns(u32 n10ns);
-#define udelay(u) cris_delay10ns((u)*100)
-#define ndelay(n) cris_delay10ns(((n)+9)/10)
-
-/*
- * Not used anymore for udelay or ndelay.  Referenced by
- * e.g. init/calibrate.c.  All other references are likely bugs;
- * should be replaced by mdelay, udelay or ndelay.
- */
-
-static inline void
-__delay(int loops)
-{
-	__asm__ __volatile__ (
-		"move.d %0, $r9\n\t"
-		"beq 2f\n\t"
-		"subq 1, $r9\n\t"
-		"1:\n\t"
-		"bne 1b\n\t"
-		"subq 1, $r9\n"
-		"2:"
-		: : "g" (loops) : "r9");
-}
-
-#endif /* _ASM_CRIS_ARCH_DELAY_H */
diff --git a/include/asm-cris/arch-v32/dma.h b/include/asm-cris/arch-v32/dma.h
deleted file mode 100644
index 3674081389fd..000000000000
--- a/include/asm-cris/arch-v32/dma.h
+++ /dev/null
@@ -1,79 +0,0 @@
-#ifndef _ASM_ARCH_CRIS_DMA_H
-#define _ASM_ARCH_CRIS_DMA_H
-
-/* Defines for using and allocating dma channels. */
-
-#define MAX_DMA_CHANNELS	10
-
-#define NETWORK_ETH0_TX_DMA_NBR 0	/* Ethernet 0 out. */
-#define NETWORK_ETH0 RX_DMA_NBR 1	/* Ethernet 0 in. */
-
-#define IO_PROC_DMA0_TX_DMA_NBR 2	/* IO processor DMA0 out. */
-#define IO_PROC_DMA0_RX_DMA_NBR 3	/* IO processor DMA0 in. */
-
-#define ATA_TX_DMA_NBR 2		/* ATA interface out. */
-#define ATA_RX_DMA_NBR 3		/* ATA interface in. */
-
-#define ASYNC_SER2_TX_DMA_NBR 2		/* Asynchronous serial port 2 out. */
-#define ASYNC_SER2_RX_DMA_NBR 3		/* Asynchronous serial port 2 in. */
-
-#define IO_PROC_DMA1_TX_DMA_NBR 4	/* IO processor DMA1 out. */
-#define IO_PROC_DMA1_RX_DMA_NBR 5	/* IO processor DMA1 in. */
-
-#define ASYNC_SER1_TX_DMA_NBR 4		/* Asynchronous serial port 1 out. */
-#define ASYNC_SER1_RX_DMA_NBR 5		/* Asynchronous serial port 1 in. */
-
-#define SYNC_SER0_TX_DMA_NBR 4		/* Synchronous serial port 0 out. */
-#define SYNC_SER0_RX_DMA_NBR 5		/* Synchronous serial port 0 in. */
-
-#define EXTDMA0_TX_DMA_NBR 6		/* External DMA 0 out. */
-#define EXTDMA1_RX_DMA_NBR 7		/* External DMA 1 in. */
-
-#define ASYNC_SER0_TX_DMA_NBR 6		/* Asynchronous serial port 0 out. */
-#define ASYNC_SER0_RX_DMA_NBR 7		/* Asynchronous serial port 0 in. */
-
-#define SYNC_SER1_TX_DMA_NBR 6		/* Synchronous serial port 1 out. */
-#define SYNC_SER1_RX_DMA_NBR 7		/* Synchronous serial port 1 in. */
-
-#define NETWORK_ETH1_TX_DMA_NBR 6	/* Ethernet 1 out. */
-#define NETWORK_ETH1_RX_DMA_NBR 7	/* Ethernet 1 in. */
-
-#define EXTDMA2_TX_DMA_NBR 8		/* External DMA 2 out. */
-#define EXTDMA3_RX_DMA_NBR 9		/* External DMA 3 in. */
-
-#define STRCOP_TX_DMA_NBR 8		/* Stream co-processor out. */
-#define STRCOP_RX_DMA_NBR 9		/* Stream co-processor in. */
-
-#define ASYNC_SER3_TX_DMA_NBR 8		/* Asynchronous serial port 3 out. */
-#define ASYNC_SER3_RX_DMA_NBR 9		/* Asynchronous serial port 3 in. */
-
-enum dma_owner
-{
-  dma_eth0,
-  dma_eth1,
-  dma_iop0,
-  dma_iop1,
-  dma_ser0,
-  dma_ser1,
-  dma_ser2,
-  dma_ser3,
-  dma_sser0,
-  dma_sser1,
-  dma_ata,
-  dma_strp,
-  dma_ext0,
-  dma_ext1,
-  dma_ext2,
-  dma_ext3
-};
-
-int crisv32_request_dma(unsigned int dmanr, const char * device_id,
-                        unsigned options, unsigned bandwidth, enum dma_owner owner);
-void crisv32_free_dma(unsigned int dmanr);
-
-/* Masks used by crisv32_request_dma options: */
-#define DMA_VERBOSE_ON_ERROR 1
-#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
-#define DMA_INT_MEM 4
-
-#endif /* _ASM_ARCH_CRIS_DMA_H */
diff --git a/include/asm-cris/arch-v32/elf.h b/include/asm-cris/arch-v32/elf.h
deleted file mode 100644
index 1324e505a4d8..000000000000
--- a/include/asm-cris/arch-v32/elf.h
+++ /dev/null
@@ -1,73 +0,0 @@
-#ifndef _ASM_CRIS_ELF_H
-#define _ASM_CRIS_ELF_H
-
-#define ELF_CORE_EFLAGS EF_CRIS_VARIANT_V32
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x)			\
- ((x)->e_machine == EM_CRIS			\
-  && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_V32	\
-      || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32))))
-
-/* CRISv32 ELF register definitions. */
-
-#include <asm/ptrace.h>
-
-/* Explicitly zero out registers to increase determinism. */
-#define ELF_PLAT_INIT(_r, load_addr)    do { \
-        (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \
-        (_r)->r9 = 0;  (_r)->r8 = 0;  (_r)->r7 = 0;  (_r)->r6 = 0;  \
-        (_r)->r5 = 0;  (_r)->r4 = 0;  (_r)->r3 = 0;  (_r)->r2 = 0;  \
-        (_r)->r1 = 0;  (_r)->r0 = 0;  (_r)->mof = 0; (_r)->srp = 0; \
-        (_r)->acr = 0; \
-} while (0)
-
-/*
- * An executable for which elf_read_implies_exec() returns TRUE will
- * have the READ_IMPLIES_EXEC personality flag set automatically.
- */
-#define elf_read_implies_exec_binary(ex, have_pt_gnu_stack)	(!(have_pt_gnu_stack))
-
-/*
- * This is basically a pt_regs with the additional definition
- * of the stack pointer since it's needed in a core dump.
- * pr_regs is a elf_gregset_t and should be filled according
- * to the layout of user_regs_struct.
- */
-#define ELF_CORE_COPY_REGS(pr_reg, regs)                   \
-        pr_reg[0] = regs->r0;                              \
-        pr_reg[1] = regs->r1;                              \
-        pr_reg[2] = regs->r2;                              \
-        pr_reg[3] = regs->r3;                              \
-        pr_reg[4] = regs->r4;                              \
-        pr_reg[5] = regs->r5;                              \
-        pr_reg[6] = regs->r6;                              \
-        pr_reg[7] = regs->r7;                              \
-        pr_reg[8] = regs->r8;                              \
-        pr_reg[9] = regs->r9;                              \
-        pr_reg[10] = regs->r10;                            \
-        pr_reg[11] = regs->r11;                            \
-        pr_reg[12] = regs->r12;                            \
-        pr_reg[13] = regs->r13;                            \
-        pr_reg[14] = rdusp();               /* SP */       \
-        pr_reg[15] = regs->acr;             /* ACR */      \
-        pr_reg[16] = 0;                     /* BZ */       \
-        pr_reg[17] = rdvr();                /* VR */       \
-        pr_reg[18] = 0;                     /* PID */      \
-        pr_reg[19] = regs->srs;             /* SRS */      \
-        pr_reg[20] = 0;                     /* WZ */       \
-        pr_reg[21] = regs->exs;             /* EXS */      \
-        pr_reg[22] = regs->eda;             /* EDA */      \
-        pr_reg[23] = regs->mof;             /* MOF */      \
-        pr_reg[24] = 0;                     /* DZ */       \
-        pr_reg[25] = 0;                     /* EBP */      \
-        pr_reg[26] = regs->erp;             /* ERP */      \
-        pr_reg[27] = regs->srp;             /* SRP */      \
-        pr_reg[28] = 0;                     /* NRP */      \
-        pr_reg[29] = regs->ccs;             /* CCS */      \
-        pr_reg[30] = rdusp();               /* USP */      \
-        pr_reg[31] = regs->spc;             /* SPC */      \
-
-#endif /* _ASM_CRIS_ELF_H */
diff --git a/include/asm-cris/arch-v32/hwregs/Makefile b/include/asm-cris/arch-v32/hwregs/Makefile
deleted file mode 100644
index f9a05d2aa061..000000000000
--- a/include/asm-cris/arch-v32/hwregs/Makefile
+++ /dev/null
@@ -1,186 +0,0 @@
-# Makefile to generate or copy the latest register definitions
-# and related datastructures and helpermacros.
-# The offical place for these files is at:
-RELEASE ?= r1_alfa5
-OFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/
-
-# which is updated on each new release.
-INCL_ASMFILES   =
-INCL_FILES      = ata_defs.h
-INCL_FILES     += bif_core_defs.h
-INCL_ASMFILES  += bif_core_defs_asm.h
-INCL_FILES     += bif_slave_defs.h
-#INCL_FILES     += bif_slave_ext_defs.h
-INCL_FILES     += config_defs.h
-INCL_ASMFILES  += config_defs_asm.h
-INCL_FILES     += cpu_vect.h
-#INCL_FILES     += cris_defs.h
-#INCL_FILES     += cris_supp_reg.h # In handcrafted supp_reg.h
-INCL_FILES     += dma.h
-INCL_FILES     += dma_defs.h
-INCL_FILES     += eth_defs.h
-INCL_FILES     += extmem_defs.h
-INCL_FILES     += gio_defs.h
-INCL_ASMFILES  += gio_defs_asm.h
-INCL_FILES     += intr_vect.h
-INCL_FILES     += intr_vect_defs.h
-INCL_ASMFILES  += intr_vect_defs_asm.h
-INCL_FILES     += marb_bp_defs.h
-INCL_FILES     += marb_defs.h
-INCL_ASMFILES  += mmu_defs_asm.h
-#INCL_FILES     += mmu_supp_reg.h # In handcrafted supp_reg.h
-#INCL_FILES     += par_defs.h # No useful content
-INCL_FILES     += pinmux_defs.h
-INCL_FILES     += reg_map.h
-INCL_ASMFILES  += reg_map_asm.h
-INCL_FILES     += reg_rdwr.h
-INCL_FILES     += ser_defs.h
-#INCL_FILES     += spec_reg.h # In handcrafted supp_reg.h
-INCL_FILES     += sser_defs.h
-INCL_FILES     += strcop_defs.h
-#INCL_FILES     += strcop.h # Where is this?
-INCL_FILES     += strmux_defs.h
-#INCL_FILES     += supp_reg.h # Handcrafted instead
-INCL_FILES     += timer_defs.h
-
-REGDESC =
-REGDESC += $(BASEDIR)/io/ata/rtl/ata_regs.r
-REGDESC += $(BASEDIR)/io/bif/rtl/bif_core_regs.r
-REGDESC += $(BASEDIR)/io/bif/rtl/bif_slave_regs.r
-#REGDESC += $(BASEDIR)/io/bif/sw/bif_slave_ext_regs.r
-REGDESC += $(DESIGNDIR)/top/rtl/config_regs.r
-REGDESC += $(BASEDIR)/mod/dma_common/rtl/dma_regdes.r
-REGDESC += $(BASEDIR)/io/eth/rtl/eth_regs.r
-REGDESC += $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r
-REGDESC += $(DESIGNDIR)/gio/rtl/gio_regs.r
-REGDESC += $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
-REGDESC += $(BASEDIR)/core/memarb/rtl/guinness/marb_top.r
-REGDESC += $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r
-#REGDESC += $(BASEDIR)/io/par_port/rtl/par_regs.r
-REGDESC += $(BASEDIR)/io/pinmux/rtl/guinness/pinmux_regs.r
-REGDESC += $(BASEDIR)/io/ser/rtl/ser_regs.r
-REGDESC += $(BASEDIR)/core/strcop/rtl/strcop_regs.r
-REGDESC += $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r
-REGDESC += $(BASEDIR)/io/timer/rtl/timer_regs.r
-#REGDESC += $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r
-
-
-BASEDIR = /n/asic/design
-DESIGNDIR = /n/asic/projects/guinness/design
-RDES2C = /n/asic/bin/rdes2c
-RDES2C = /n/asic/design/tools/rdesc/rdes2c
-RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr
-RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt
-
-## all    - Just print help - you probably want to do 'make gen'
-all: help
-
-# Disable implicit rule that may generate deleted files from RCS/ directory.
-%.r:
-
-%.h:
-
-## help   - This help
-help:
-	@grep '^## ' Makefile
-
-## gen    - Generate include files
-gen: $(INCL_FILES) $(INCL_ASMFILES)
-
-ata_defs.h: $(BASEDIR)/io/ata/rtl/ata_regs.r
-	$(RDES2C) $<
-config_defs.h: $(DESIGNDIR)/top/rtl/config_regs.r
-	$(RDES2C) $<
-config_defs_asm.h: $(DESIGNDIR)/top/rtl/config_regs.r
-	$(RDES2C) -asm $<
-# Can't generate cpu_vect.h yet
-#cpu_vect.h: $(DESIGNDIR)/top/rtl/cpu_vect.r # ????
-#	$(RDES2INTR) $<
-cpu_vect.h: $(OFFICIAL_INCDIR)cpu_vect.h
-	cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-dma_defs.h: $(BASEDIR)/core/dma/rtl/common/dma_regdes.r
-	$(RDES2C) $<
-$(BASEDIR)/core/dma/sw/dma.h:
-dma.h: $(BASEDIR)/core/dma/sw/dma.h
-	cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-eth_defs.h: $(BASEDIR)/io/eth/rtl/eth_regs.r
-	$(RDES2C) $<
-extmem_defs.h: $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r
-	$(RDES2C) $<
-gio_defs.h: $(DESIGNDIR)/gio/rtl/gio_regs.r
-	$(RDES2C) $<
-intr_vect_defs.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
-	$(RDES2C) $<
-intr_vect_defs_asm.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
-	$(RDES2C) -asm $<
-# Can't generate intr_vect.h yet
-#intr_vect.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
-#	$(RDES2INTR) $<
-intr_vect.h: $(OFFICIAL_INCDIR)intr_vect.h
-	cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-mmu_defs_asm.h: $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r
-	$(RDES2C) -asm $<
-par_defs.h: $(BASEDIR)/io/par_port/rtl/par_regs.r
-	$(RDES2C) $<
-
-# From /n/asic/projects/guinness/design/
-reg_map.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap
-	$(RDES2C) -base 0xb0000000 $^
-reg_map_asm.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap
-	$(RDES2C) -base 0xb0000000 -asm -outfile $@ $^
-
-reg_rdwr.h: $(DESIGNDIR)/top/sw/include/reg_rdwr.h
-	cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-
-ser_defs.h: $(BASEDIR)/io/ser/rtl/ser_regs.r
-	$(RDES2C) $<
-strcop_defs.h: $(BASEDIR)/core/strcop/rtl/strcop_regs.r
-	$(RDES2C) $<
-strcop.h: $(BASEDIR)/core/strcop/rtl/strcop.h
-	cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-strmux_defs.h: $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r
-	$(RDES2C) $<
-timer_defs.h: $(BASEDIR)/io/timer/rtl/timer_regs.r
-	$(RDES2C) $<
-usb_defs.h: $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r
-	$(RDES2C) $<
-
-## copy   - Copy files from official location
-copy:
-	@for HFILE in $(INCL_FILES); do \
-		echo "  $$HFILE"; \
-		cat $(OFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
-	done
-	@for HFILE in $(INCL_ASMFILES); do \
-		echo "  $$HFILE"; \
-		cat $(OFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
-	done
-## ls_official - List official location
-ls_official:
-	(cd $(OFFICIAL_INCDIR); ls -l *.h )
-
-## diff_official - Diff current directory with official location
-diff_official:
-	diff . $(OFFICIAL_INCDIR)
-
-## doc    - Generate .axw files from register description.
-doc: $(REGDESC)
-	for RDES in $^; do \
-		$(RDES2TXT) $$RDES; \
-	done
-
-.PHONY: axw
-## %.axw  - Generate the specified .axw file (doesn't work for all files
-##          due to inconsistent naming ir .r files.
-%.axw: axw
-	@for RDES in $(REGDESC); do \
-		if echo "$$RDES" | grep $* ; then \
-		  $(RDES2TXT) $$RDES; \
-		fi \
-	done
-
-.PHONY: clean
-## clean  - Remove .h files and .axw files.
-clean:
-	rm -rf $(INCL_FILES) *.axw
-
diff --git a/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h
deleted file mode 100644
index 866191418f9c..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h
+++ /dev/null
@@ -1,222 +0,0 @@
-#ifndef __ata_defs_asm_h
-#define __ata_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/ata/rtl/ata_regs.r
- *     id:           ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
- *     last modfied: Mon Apr 11 16:06:25 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r
- *      id: $Id: ata_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_ctrl0, scope ata, type rw */
-#define reg_ata_rw_ctrl0___pio_hold___lsb 0
-#define reg_ata_rw_ctrl0___pio_hold___width 6
-#define reg_ata_rw_ctrl0___pio_strb___lsb 6
-#define reg_ata_rw_ctrl0___pio_strb___width 6
-#define reg_ata_rw_ctrl0___pio_setup___lsb 12
-#define reg_ata_rw_ctrl0___pio_setup___width 6
-#define reg_ata_rw_ctrl0___dma_hold___lsb 18
-#define reg_ata_rw_ctrl0___dma_hold___width 6
-#define reg_ata_rw_ctrl0___dma_strb___lsb 24
-#define reg_ata_rw_ctrl0___dma_strb___width 6
-#define reg_ata_rw_ctrl0___rst___lsb 30
-#define reg_ata_rw_ctrl0___rst___width 1
-#define reg_ata_rw_ctrl0___rst___bit 30
-#define reg_ata_rw_ctrl0___en___lsb 31
-#define reg_ata_rw_ctrl0___en___width 1
-#define reg_ata_rw_ctrl0___en___bit 31
-#define reg_ata_rw_ctrl0_offset 12
-
-/* Register rw_ctrl1, scope ata, type rw */
-#define reg_ata_rw_ctrl1___udma_tcyc___lsb 0
-#define reg_ata_rw_ctrl1___udma_tcyc___width 4
-#define reg_ata_rw_ctrl1___udma_tdvs___lsb 4
-#define reg_ata_rw_ctrl1___udma_tdvs___width 4
-#define reg_ata_rw_ctrl1_offset 16
-
-/* Register rw_ctrl2, scope ata, type rw */
-#define reg_ata_rw_ctrl2___data___lsb 0
-#define reg_ata_rw_ctrl2___data___width 16
-#define reg_ata_rw_ctrl2___dma_size___lsb 19
-#define reg_ata_rw_ctrl2___dma_size___width 1
-#define reg_ata_rw_ctrl2___dma_size___bit 19
-#define reg_ata_rw_ctrl2___multi___lsb 20
-#define reg_ata_rw_ctrl2___multi___width 1
-#define reg_ata_rw_ctrl2___multi___bit 20
-#define reg_ata_rw_ctrl2___hsh___lsb 21
-#define reg_ata_rw_ctrl2___hsh___width 2
-#define reg_ata_rw_ctrl2___trf_mode___lsb 23
-#define reg_ata_rw_ctrl2___trf_mode___width 1
-#define reg_ata_rw_ctrl2___trf_mode___bit 23
-#define reg_ata_rw_ctrl2___rw___lsb 24
-#define reg_ata_rw_ctrl2___rw___width 1
-#define reg_ata_rw_ctrl2___rw___bit 24
-#define reg_ata_rw_ctrl2___addr___lsb 25
-#define reg_ata_rw_ctrl2___addr___width 3
-#define reg_ata_rw_ctrl2___cs0___lsb 28
-#define reg_ata_rw_ctrl2___cs0___width 1
-#define reg_ata_rw_ctrl2___cs0___bit 28
-#define reg_ata_rw_ctrl2___cs1___lsb 29
-#define reg_ata_rw_ctrl2___cs1___width 1
-#define reg_ata_rw_ctrl2___cs1___bit 29
-#define reg_ata_rw_ctrl2___sel___lsb 30
-#define reg_ata_rw_ctrl2___sel___width 2
-#define reg_ata_rw_ctrl2_offset 0
-
-/* Register rs_stat_data, scope ata, type rs */
-#define reg_ata_rs_stat_data___data___lsb 0
-#define reg_ata_rs_stat_data___data___width 16
-#define reg_ata_rs_stat_data___dav___lsb 16
-#define reg_ata_rs_stat_data___dav___width 1
-#define reg_ata_rs_stat_data___dav___bit 16
-#define reg_ata_rs_stat_data___busy___lsb 17
-#define reg_ata_rs_stat_data___busy___width 1
-#define reg_ata_rs_stat_data___busy___bit 17
-#define reg_ata_rs_stat_data_offset 4
-
-/* Register r_stat_data, scope ata, type r */
-#define reg_ata_r_stat_data___data___lsb 0
-#define reg_ata_r_stat_data___data___width 16
-#define reg_ata_r_stat_data___dav___lsb 16
-#define reg_ata_r_stat_data___dav___width 1
-#define reg_ata_r_stat_data___dav___bit 16
-#define reg_ata_r_stat_data___busy___lsb 17
-#define reg_ata_r_stat_data___busy___width 1
-#define reg_ata_r_stat_data___busy___bit 17
-#define reg_ata_r_stat_data_offset 8
-
-/* Register rw_trf_cnt, scope ata, type rw */
-#define reg_ata_rw_trf_cnt___cnt___lsb 0
-#define reg_ata_rw_trf_cnt___cnt___width 17
-#define reg_ata_rw_trf_cnt_offset 20
-
-/* Register r_stat_misc, scope ata, type r */
-#define reg_ata_r_stat_misc___crc___lsb 0
-#define reg_ata_r_stat_misc___crc___width 16
-#define reg_ata_r_stat_misc_offset 24
-
-/* Register rw_intr_mask, scope ata, type rw */
-#define reg_ata_rw_intr_mask___bus0___lsb 0
-#define reg_ata_rw_intr_mask___bus0___width 1
-#define reg_ata_rw_intr_mask___bus0___bit 0
-#define reg_ata_rw_intr_mask___bus1___lsb 1
-#define reg_ata_rw_intr_mask___bus1___width 1
-#define reg_ata_rw_intr_mask___bus1___bit 1
-#define reg_ata_rw_intr_mask___bus2___lsb 2
-#define reg_ata_rw_intr_mask___bus2___width 1
-#define reg_ata_rw_intr_mask___bus2___bit 2
-#define reg_ata_rw_intr_mask___bus3___lsb 3
-#define reg_ata_rw_intr_mask___bus3___width 1
-#define reg_ata_rw_intr_mask___bus3___bit 3
-#define reg_ata_rw_intr_mask_offset 28
-
-/* Register rw_ack_intr, scope ata, type rw */
-#define reg_ata_rw_ack_intr___bus0___lsb 0
-#define reg_ata_rw_ack_intr___bus0___width 1
-#define reg_ata_rw_ack_intr___bus0___bit 0
-#define reg_ata_rw_ack_intr___bus1___lsb 1
-#define reg_ata_rw_ack_intr___bus1___width 1
-#define reg_ata_rw_ack_intr___bus1___bit 1
-#define reg_ata_rw_ack_intr___bus2___lsb 2
-#define reg_ata_rw_ack_intr___bus2___width 1
-#define reg_ata_rw_ack_intr___bus2___bit 2
-#define reg_ata_rw_ack_intr___bus3___lsb 3
-#define reg_ata_rw_ack_intr___bus3___width 1
-#define reg_ata_rw_ack_intr___bus3___bit 3
-#define reg_ata_rw_ack_intr_offset 32
-
-/* Register r_intr, scope ata, type r */
-#define reg_ata_r_intr___bus0___lsb 0
-#define reg_ata_r_intr___bus0___width 1
-#define reg_ata_r_intr___bus0___bit 0
-#define reg_ata_r_intr___bus1___lsb 1
-#define reg_ata_r_intr___bus1___width 1
-#define reg_ata_r_intr___bus1___bit 1
-#define reg_ata_r_intr___bus2___lsb 2
-#define reg_ata_r_intr___bus2___width 1
-#define reg_ata_r_intr___bus2___bit 2
-#define reg_ata_r_intr___bus3___lsb 3
-#define reg_ata_r_intr___bus3___width 1
-#define reg_ata_r_intr___bus3___bit 3
-#define reg_ata_r_intr_offset 36
-
-/* Register r_masked_intr, scope ata, type r */
-#define reg_ata_r_masked_intr___bus0___lsb 0
-#define reg_ata_r_masked_intr___bus0___width 1
-#define reg_ata_r_masked_intr___bus0___bit 0
-#define reg_ata_r_masked_intr___bus1___lsb 1
-#define reg_ata_r_masked_intr___bus1___width 1
-#define reg_ata_r_masked_intr___bus1___bit 1
-#define reg_ata_r_masked_intr___bus2___lsb 2
-#define reg_ata_r_masked_intr___bus2___width 1
-#define reg_ata_r_masked_intr___bus2___bit 2
-#define reg_ata_r_masked_intr___bus3___lsb 3
-#define reg_ata_r_masked_intr___bus3___width 1
-#define reg_ata_r_masked_intr___bus3___bit 3
-#define reg_ata_r_masked_intr_offset 40
-
-
-/* Constants */
-#define regk_ata_active                           0x00000001
-#define regk_ata_byte                             0x00000001
-#define regk_ata_data                             0x00000001
-#define regk_ata_dma                              0x00000001
-#define regk_ata_inactive                         0x00000000
-#define regk_ata_no                               0x00000000
-#define regk_ata_nodata                           0x00000000
-#define regk_ata_pio                              0x00000000
-#define regk_ata_rd                               0x00000001
-#define regk_ata_reg                              0x00000000
-#define regk_ata_rw_ctrl0_default                 0x00000000
-#define regk_ata_rw_ctrl2_default                 0x00000000
-#define regk_ata_rw_intr_mask_default             0x00000000
-#define regk_ata_udma                             0x00000002
-#define regk_ata_word                             0x00000000
-#define regk_ata_wr                               0x00000000
-#define regk_ata_yes                              0x00000001
-#endif /* __ata_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h
deleted file mode 100644
index c686cb335621..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h
+++ /dev/null
@@ -1,319 +0,0 @@
-#ifndef __bif_core_defs_asm_h
-#define __bif_core_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/bif/rtl/bif_core_regs.r
- *     id:           bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
- *     last modfied: Mon Apr 11 16:06:33 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r
- *      id: $Id: bif_core_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_grp1_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp1_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp1_cfg___lw___width 6
-#define reg_bif_core_rw_grp1_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp1_cfg___ew___width 3
-#define reg_bif_core_rw_grp1_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp1_cfg___zw___width 3
-#define reg_bif_core_rw_grp1_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp1_cfg___aw___width 2
-#define reg_bif_core_rw_grp1_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp1_cfg___dw___width 2
-#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp1_cfg___ewb___width 2
-#define reg_bif_core_rw_grp1_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp1_cfg___bw___width 1
-#define reg_bif_core_rw_grp1_cfg___bw___bit 18
-#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp1_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp1_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp1_cfg___mode___width 1
-#define reg_bif_core_rw_grp1_cfg___mode___bit 21
-#define reg_bif_core_rw_grp1_cfg_offset 0
-
-/* Register rw_grp2_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp2_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp2_cfg___lw___width 6
-#define reg_bif_core_rw_grp2_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp2_cfg___ew___width 3
-#define reg_bif_core_rw_grp2_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp2_cfg___zw___width 3
-#define reg_bif_core_rw_grp2_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp2_cfg___aw___width 2
-#define reg_bif_core_rw_grp2_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp2_cfg___dw___width 2
-#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp2_cfg___ewb___width 2
-#define reg_bif_core_rw_grp2_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp2_cfg___bw___width 1
-#define reg_bif_core_rw_grp2_cfg___bw___bit 18
-#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp2_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp2_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp2_cfg___mode___width 1
-#define reg_bif_core_rw_grp2_cfg___mode___bit 21
-#define reg_bif_core_rw_grp2_cfg_offset 4
-
-/* Register rw_grp3_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp3_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp3_cfg___lw___width 6
-#define reg_bif_core_rw_grp3_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp3_cfg___ew___width 3
-#define reg_bif_core_rw_grp3_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp3_cfg___zw___width 3
-#define reg_bif_core_rw_grp3_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp3_cfg___aw___width 2
-#define reg_bif_core_rw_grp3_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp3_cfg___dw___width 2
-#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp3_cfg___ewb___width 2
-#define reg_bif_core_rw_grp3_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp3_cfg___bw___width 1
-#define reg_bif_core_rw_grp3_cfg___bw___bit 18
-#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp3_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp3_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp3_cfg___mode___width 1
-#define reg_bif_core_rw_grp3_cfg___mode___bit 21
-#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24
-#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26
-#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28
-#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30
-#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2
-#define reg_bif_core_rw_grp3_cfg_offset 8
-
-/* Register rw_grp4_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp4_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp4_cfg___lw___width 6
-#define reg_bif_core_rw_grp4_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp4_cfg___ew___width 3
-#define reg_bif_core_rw_grp4_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp4_cfg___zw___width 3
-#define reg_bif_core_rw_grp4_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp4_cfg___aw___width 2
-#define reg_bif_core_rw_grp4_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp4_cfg___dw___width 2
-#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp4_cfg___ewb___width 2
-#define reg_bif_core_rw_grp4_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp4_cfg___bw___width 1
-#define reg_bif_core_rw_grp4_cfg___bw___bit 18
-#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp4_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp4_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp4_cfg___mode___width 1
-#define reg_bif_core_rw_grp4_cfg___mode___bit 21
-#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26
-#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2
-#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28
-#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2
-#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30
-#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2
-#define reg_bif_core_rw_grp4_cfg_offset 12
-
-/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0
-#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5
-#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3
-#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8
-#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9
-#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10
-#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14
-#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15
-#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp0_offset 16
-
-/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0
-#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5
-#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3
-#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8
-#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9
-#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10
-#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14
-#define reg_bif_core_rw_sdram_cfg_grp1_offset 20
-
-/* Register rw_sdram_timing, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_timing___cl___lsb 0
-#define reg_bif_core_rw_sdram_timing___cl___width 3
-#define reg_bif_core_rw_sdram_timing___rcd___lsb 3
-#define reg_bif_core_rw_sdram_timing___rcd___width 3
-#define reg_bif_core_rw_sdram_timing___rp___lsb 6
-#define reg_bif_core_rw_sdram_timing___rp___width 3
-#define reg_bif_core_rw_sdram_timing___rc___lsb 9
-#define reg_bif_core_rw_sdram_timing___rc___width 2
-#define reg_bif_core_rw_sdram_timing___dpl___lsb 11
-#define reg_bif_core_rw_sdram_timing___dpl___width 2
-#define reg_bif_core_rw_sdram_timing___pde___lsb 13
-#define reg_bif_core_rw_sdram_timing___pde___width 1
-#define reg_bif_core_rw_sdram_timing___pde___bit 13
-#define reg_bif_core_rw_sdram_timing___ref___lsb 14
-#define reg_bif_core_rw_sdram_timing___ref___width 2
-#define reg_bif_core_rw_sdram_timing___cpd___lsb 16
-#define reg_bif_core_rw_sdram_timing___cpd___width 1
-#define reg_bif_core_rw_sdram_timing___cpd___bit 16
-#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17
-#define reg_bif_core_rw_sdram_timing___sdcke___width 1
-#define reg_bif_core_rw_sdram_timing___sdcke___bit 17
-#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18
-#define reg_bif_core_rw_sdram_timing___sdclk___width 1
-#define reg_bif_core_rw_sdram_timing___sdclk___bit 18
-#define reg_bif_core_rw_sdram_timing_offset 24
-
-/* Register rw_sdram_cmd, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0
-#define reg_bif_core_rw_sdram_cmd___cmd___width 3
-#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3
-#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15
-#define reg_bif_core_rw_sdram_cmd_offset 28
-
-/* Register rs_sdram_ref_stat, scope bif_core, type rs */
-#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0
-#define reg_bif_core_rs_sdram_ref_stat___ok___width 1
-#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0
-#define reg_bif_core_rs_sdram_ref_stat_offset 32
-
-/* Register r_sdram_ref_stat, scope bif_core, type r */
-#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0
-#define reg_bif_core_r_sdram_ref_stat___ok___width 1
-#define reg_bif_core_r_sdram_ref_stat___ok___bit 0
-#define reg_bif_core_r_sdram_ref_stat_offset 36
-
-
-/* Constants */
-#define regk_bif_core_bank2                       0x00000000
-#define regk_bif_core_bank4                       0x00000001
-#define regk_bif_core_bit10                       0x0000000a
-#define regk_bif_core_bit11                       0x0000000b
-#define regk_bif_core_bit12                       0x0000000c
-#define regk_bif_core_bit13                       0x0000000d
-#define regk_bif_core_bit14                       0x0000000e
-#define regk_bif_core_bit15                       0x0000000f
-#define regk_bif_core_bit16                       0x00000010
-#define regk_bif_core_bit17                       0x00000011
-#define regk_bif_core_bit18                       0x00000012
-#define regk_bif_core_bit19                       0x00000013
-#define regk_bif_core_bit20                       0x00000014
-#define regk_bif_core_bit21                       0x00000015
-#define regk_bif_core_bit22                       0x00000016
-#define regk_bif_core_bit23                       0x00000017
-#define regk_bif_core_bit24                       0x00000018
-#define regk_bif_core_bit25                       0x00000019
-#define regk_bif_core_bit26                       0x0000001a
-#define regk_bif_core_bit27                       0x0000001b
-#define regk_bif_core_bit28                       0x0000001c
-#define regk_bif_core_bit29                       0x0000001d
-#define regk_bif_core_bit9                        0x00000009
-#define regk_bif_core_bw16                        0x00000001
-#define regk_bif_core_bw32                        0x00000000
-#define regk_bif_core_bwe                         0x00000000
-#define regk_bif_core_cwe                         0x00000001
-#define regk_bif_core_e15us                       0x00000001
-#define regk_bif_core_e7800ns                     0x00000002
-#define regk_bif_core_grp0                        0x00000000
-#define regk_bif_core_grp1                        0x00000001
-#define regk_bif_core_mrs                         0x00000003
-#define regk_bif_core_no                          0x00000000
-#define regk_bif_core_none                        0x00000000
-#define regk_bif_core_nop                         0x00000000
-#define regk_bif_core_off                         0x00000000
-#define regk_bif_core_pre                         0x00000002
-#define regk_bif_core_r_sdram_ref_stat_default    0x00000001
-#define regk_bif_core_rd                          0x00000002
-#define regk_bif_core_ref                         0x00000001
-#define regk_bif_core_rs_sdram_ref_stat_default   0x00000001
-#define regk_bif_core_rw_grp1_cfg_default         0x000006cf
-#define regk_bif_core_rw_grp2_cfg_default         0x000006cf
-#define regk_bif_core_rw_grp3_cfg_default         0x000006cf
-#define regk_bif_core_rw_grp4_cfg_default         0x000006cf
-#define regk_bif_core_rw_sdram_cfg_grp1_default   0x00000000
-#define regk_bif_core_slf                         0x00000004
-#define regk_bif_core_wr                          0x00000001
-#define regk_bif_core_yes                         0x00000001
-#endif /* __bif_core_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h
deleted file mode 100644
index 71532aa18168..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h
+++ /dev/null
@@ -1,495 +0,0 @@
-#ifndef __bif_dma_defs_asm_h
-#define __bif_dma_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/bif/rtl/bif_dma_regs.r
- *     id:           bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
- *     last modfied: Mon Apr 11 16:06:33 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r
- *      id: $Id: bif_dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_ch0_ctrl, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch0_ctrl___bw___lsb 0
-#define reg_bif_dma_rw_ch0_ctrl___bw___width 2
-#define reg_bif_dma_rw_ch0_ctrl___burst_len___lsb 2
-#define reg_bif_dma_rw_ch0_ctrl___burst_len___width 1
-#define reg_bif_dma_rw_ch0_ctrl___burst_len___bit 2
-#define reg_bif_dma_rw_ch0_ctrl___cont___lsb 3
-#define reg_bif_dma_rw_ch0_ctrl___cont___width 1
-#define reg_bif_dma_rw_ch0_ctrl___cont___bit 3
-#define reg_bif_dma_rw_ch0_ctrl___end_pad___lsb 4
-#define reg_bif_dma_rw_ch0_ctrl___end_pad___width 1
-#define reg_bif_dma_rw_ch0_ctrl___end_pad___bit 4
-#define reg_bif_dma_rw_ch0_ctrl___cnt___lsb 5
-#define reg_bif_dma_rw_ch0_ctrl___cnt___width 1
-#define reg_bif_dma_rw_ch0_ctrl___cnt___bit 5
-#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___lsb 6
-#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___width 3
-#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___lsb 9
-#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___width 2
-#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___lsb 11
-#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___width 3
-#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___lsb 14
-#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___width 2
-#define reg_bif_dma_rw_ch0_ctrl___bus_mode___lsb 16
-#define reg_bif_dma_rw_ch0_ctrl___bus_mode___width 2
-#define reg_bif_dma_rw_ch0_ctrl___rate_en___lsb 18
-#define reg_bif_dma_rw_ch0_ctrl___rate_en___width 1
-#define reg_bif_dma_rw_ch0_ctrl___rate_en___bit 18
-#define reg_bif_dma_rw_ch0_ctrl___wr_all___lsb 19
-#define reg_bif_dma_rw_ch0_ctrl___wr_all___width 1
-#define reg_bif_dma_rw_ch0_ctrl___wr_all___bit 19
-#define reg_bif_dma_rw_ch0_ctrl_offset 0
-
-/* Register rw_ch0_addr, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch0_addr___addr___lsb 0
-#define reg_bif_dma_rw_ch0_addr___addr___width 32
-#define reg_bif_dma_rw_ch0_addr_offset 4
-
-/* Register rw_ch0_start, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch0_start___run___lsb 0
-#define reg_bif_dma_rw_ch0_start___run___width 1
-#define reg_bif_dma_rw_ch0_start___run___bit 0
-#define reg_bif_dma_rw_ch0_start_offset 8
-
-/* Register rw_ch0_cnt, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch0_cnt___start_cnt___lsb 0
-#define reg_bif_dma_rw_ch0_cnt___start_cnt___width 16
-#define reg_bif_dma_rw_ch0_cnt_offset 12
-
-/* Register r_ch0_stat, scope bif_dma, type r */
-#define reg_bif_dma_r_ch0_stat___cnt___lsb 0
-#define reg_bif_dma_r_ch0_stat___cnt___width 16
-#define reg_bif_dma_r_ch0_stat___run___lsb 31
-#define reg_bif_dma_r_ch0_stat___run___width 1
-#define reg_bif_dma_r_ch0_stat___run___bit 31
-#define reg_bif_dma_r_ch0_stat_offset 16
-
-/* Register rw_ch1_ctrl, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch1_ctrl___bw___lsb 0
-#define reg_bif_dma_rw_ch1_ctrl___bw___width 2
-#define reg_bif_dma_rw_ch1_ctrl___burst_len___lsb 2
-#define reg_bif_dma_rw_ch1_ctrl___burst_len___width 1
-#define reg_bif_dma_rw_ch1_ctrl___burst_len___bit 2
-#define reg_bif_dma_rw_ch1_ctrl___cont___lsb 3
-#define reg_bif_dma_rw_ch1_ctrl___cont___width 1
-#define reg_bif_dma_rw_ch1_ctrl___cont___bit 3
-#define reg_bif_dma_rw_ch1_ctrl___end_discard___lsb 4
-#define reg_bif_dma_rw_ch1_ctrl___end_discard___width 1
-#define reg_bif_dma_rw_ch1_ctrl___end_discard___bit 4
-#define reg_bif_dma_rw_ch1_ctrl___cnt___lsb 5
-#define reg_bif_dma_rw_ch1_ctrl___cnt___width 1
-#define reg_bif_dma_rw_ch1_ctrl___cnt___bit 5
-#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___lsb 6
-#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___width 3
-#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___lsb 9
-#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___width 2
-#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___lsb 11
-#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___width 3
-#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___lsb 14
-#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___width 2
-#define reg_bif_dma_rw_ch1_ctrl___bus_mode___lsb 16
-#define reg_bif_dma_rw_ch1_ctrl___bus_mode___width 2
-#define reg_bif_dma_rw_ch1_ctrl___rate_en___lsb 18
-#define reg_bif_dma_rw_ch1_ctrl___rate_en___width 1
-#define reg_bif_dma_rw_ch1_ctrl___rate_en___bit 18
-#define reg_bif_dma_rw_ch1_ctrl_offset 32
-
-/* Register rw_ch1_addr, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch1_addr___addr___lsb 0
-#define reg_bif_dma_rw_ch1_addr___addr___width 32
-#define reg_bif_dma_rw_ch1_addr_offset 36
-
-/* Register rw_ch1_start, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch1_start___run___lsb 0
-#define reg_bif_dma_rw_ch1_start___run___width 1
-#define reg_bif_dma_rw_ch1_start___run___bit 0
-#define reg_bif_dma_rw_ch1_start_offset 40
-
-/* Register rw_ch1_cnt, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch1_cnt___start_cnt___lsb 0
-#define reg_bif_dma_rw_ch1_cnt___start_cnt___width 16
-#define reg_bif_dma_rw_ch1_cnt_offset 44
-
-/* Register r_ch1_stat, scope bif_dma, type r */
-#define reg_bif_dma_r_ch1_stat___cnt___lsb 0
-#define reg_bif_dma_r_ch1_stat___cnt___width 16
-#define reg_bif_dma_r_ch1_stat___run___lsb 31
-#define reg_bif_dma_r_ch1_stat___run___width 1
-#define reg_bif_dma_r_ch1_stat___run___bit 31
-#define reg_bif_dma_r_ch1_stat_offset 48
-
-/* Register rw_ch2_ctrl, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch2_ctrl___bw___lsb 0
-#define reg_bif_dma_rw_ch2_ctrl___bw___width 2
-#define reg_bif_dma_rw_ch2_ctrl___burst_len___lsb 2
-#define reg_bif_dma_rw_ch2_ctrl___burst_len___width 1
-#define reg_bif_dma_rw_ch2_ctrl___burst_len___bit 2
-#define reg_bif_dma_rw_ch2_ctrl___cont___lsb 3
-#define reg_bif_dma_rw_ch2_ctrl___cont___width 1
-#define reg_bif_dma_rw_ch2_ctrl___cont___bit 3
-#define reg_bif_dma_rw_ch2_ctrl___end_pad___lsb 4
-#define reg_bif_dma_rw_ch2_ctrl___end_pad___width 1
-#define reg_bif_dma_rw_ch2_ctrl___end_pad___bit 4
-#define reg_bif_dma_rw_ch2_ctrl___cnt___lsb 5
-#define reg_bif_dma_rw_ch2_ctrl___cnt___width 1
-#define reg_bif_dma_rw_ch2_ctrl___cnt___bit 5
-#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___lsb 6
-#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___width 3
-#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___lsb 9
-#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___width 2
-#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___lsb 11
-#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___width 3
-#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___lsb 14
-#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___width 2
-#define reg_bif_dma_rw_ch2_ctrl___bus_mode___lsb 16
-#define reg_bif_dma_rw_ch2_ctrl___bus_mode___width 2
-#define reg_bif_dma_rw_ch2_ctrl___rate_en___lsb 18
-#define reg_bif_dma_rw_ch2_ctrl___rate_en___width 1
-#define reg_bif_dma_rw_ch2_ctrl___rate_en___bit 18
-#define reg_bif_dma_rw_ch2_ctrl___wr_all___lsb 19
-#define reg_bif_dma_rw_ch2_ctrl___wr_all___width 1
-#define reg_bif_dma_rw_ch2_ctrl___wr_all___bit 19
-#define reg_bif_dma_rw_ch2_ctrl_offset 64
-
-/* Register rw_ch2_addr, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch2_addr___addr___lsb 0
-#define reg_bif_dma_rw_ch2_addr___addr___width 32
-#define reg_bif_dma_rw_ch2_addr_offset 68
-
-/* Register rw_ch2_start, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch2_start___run___lsb 0
-#define reg_bif_dma_rw_ch2_start___run___width 1
-#define reg_bif_dma_rw_ch2_start___run___bit 0
-#define reg_bif_dma_rw_ch2_start_offset 72
-
-/* Register rw_ch2_cnt, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch2_cnt___start_cnt___lsb 0
-#define reg_bif_dma_rw_ch2_cnt___start_cnt___width 16
-#define reg_bif_dma_rw_ch2_cnt_offset 76
-
-/* Register r_ch2_stat, scope bif_dma, type r */
-#define reg_bif_dma_r_ch2_stat___cnt___lsb 0
-#define reg_bif_dma_r_ch2_stat___cnt___width 16
-#define reg_bif_dma_r_ch2_stat___run___lsb 31
-#define reg_bif_dma_r_ch2_stat___run___width 1
-#define reg_bif_dma_r_ch2_stat___run___bit 31
-#define reg_bif_dma_r_ch2_stat_offset 80
-
-/* Register rw_ch3_ctrl, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch3_ctrl___bw___lsb 0
-#define reg_bif_dma_rw_ch3_ctrl___bw___width 2
-#define reg_bif_dma_rw_ch3_ctrl___burst_len___lsb 2
-#define reg_bif_dma_rw_ch3_ctrl___burst_len___width 1
-#define reg_bif_dma_rw_ch3_ctrl___burst_len___bit 2
-#define reg_bif_dma_rw_ch3_ctrl___cont___lsb 3
-#define reg_bif_dma_rw_ch3_ctrl___cont___width 1
-#define reg_bif_dma_rw_ch3_ctrl___cont___bit 3
-#define reg_bif_dma_rw_ch3_ctrl___end_discard___lsb 4
-#define reg_bif_dma_rw_ch3_ctrl___end_discard___width 1
-#define reg_bif_dma_rw_ch3_ctrl___end_discard___bit 4
-#define reg_bif_dma_rw_ch3_ctrl___cnt___lsb 5
-#define reg_bif_dma_rw_ch3_ctrl___cnt___width 1
-#define reg_bif_dma_rw_ch3_ctrl___cnt___bit 5
-#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___lsb 6
-#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___width 3
-#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___lsb 9
-#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___width 2
-#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___lsb 11
-#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___width 3
-#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___lsb 14
-#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___width 2
-#define reg_bif_dma_rw_ch3_ctrl___bus_mode___lsb 16
-#define reg_bif_dma_rw_ch3_ctrl___bus_mode___width 2
-#define reg_bif_dma_rw_ch3_ctrl___rate_en___lsb 18
-#define reg_bif_dma_rw_ch3_ctrl___rate_en___width 1
-#define reg_bif_dma_rw_ch3_ctrl___rate_en___bit 18
-#define reg_bif_dma_rw_ch3_ctrl_offset 96
-
-/* Register rw_ch3_addr, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch3_addr___addr___lsb 0
-#define reg_bif_dma_rw_ch3_addr___addr___width 32
-#define reg_bif_dma_rw_ch3_addr_offset 100
-
-/* Register rw_ch3_start, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch3_start___run___lsb 0
-#define reg_bif_dma_rw_ch3_start___run___width 1
-#define reg_bif_dma_rw_ch3_start___run___bit 0
-#define reg_bif_dma_rw_ch3_start_offset 104
-
-/* Register rw_ch3_cnt, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch3_cnt___start_cnt___lsb 0
-#define reg_bif_dma_rw_ch3_cnt___start_cnt___width 16
-#define reg_bif_dma_rw_ch3_cnt_offset 108
-
-/* Register r_ch3_stat, scope bif_dma, type r */
-#define reg_bif_dma_r_ch3_stat___cnt___lsb 0
-#define reg_bif_dma_r_ch3_stat___cnt___width 16
-#define reg_bif_dma_r_ch3_stat___run___lsb 31
-#define reg_bif_dma_r_ch3_stat___run___width 1
-#define reg_bif_dma_r_ch3_stat___run___bit 31
-#define reg_bif_dma_r_ch3_stat_offset 112
-
-/* Register rw_intr_mask, scope bif_dma, type rw */
-#define reg_bif_dma_rw_intr_mask___ext_dma0___lsb 0
-#define reg_bif_dma_rw_intr_mask___ext_dma0___width 1
-#define reg_bif_dma_rw_intr_mask___ext_dma0___bit 0
-#define reg_bif_dma_rw_intr_mask___ext_dma1___lsb 1
-#define reg_bif_dma_rw_intr_mask___ext_dma1___width 1
-#define reg_bif_dma_rw_intr_mask___ext_dma1___bit 1
-#define reg_bif_dma_rw_intr_mask___ext_dma2___lsb 2
-#define reg_bif_dma_rw_intr_mask___ext_dma2___width 1
-#define reg_bif_dma_rw_intr_mask___ext_dma2___bit 2
-#define reg_bif_dma_rw_intr_mask___ext_dma3___lsb 3
-#define reg_bif_dma_rw_intr_mask___ext_dma3___width 1
-#define reg_bif_dma_rw_intr_mask___ext_dma3___bit 3
-#define reg_bif_dma_rw_intr_mask_offset 128
-
-/* Register rw_ack_intr, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ack_intr___ext_dma0___lsb 0
-#define reg_bif_dma_rw_ack_intr___ext_dma0___width 1
-#define reg_bif_dma_rw_ack_intr___ext_dma0___bit 0
-#define reg_bif_dma_rw_ack_intr___ext_dma1___lsb 1
-#define reg_bif_dma_rw_ack_intr___ext_dma1___width 1
-#define reg_bif_dma_rw_ack_intr___ext_dma1___bit 1
-#define reg_bif_dma_rw_ack_intr___ext_dma2___lsb 2
-#define reg_bif_dma_rw_ack_intr___ext_dma2___width 1
-#define reg_bif_dma_rw_ack_intr___ext_dma2___bit 2
-#define reg_bif_dma_rw_ack_intr___ext_dma3___lsb 3
-#define reg_bif_dma_rw_ack_intr___ext_dma3___width 1
-#define reg_bif_dma_rw_ack_intr___ext_dma3___bit 3
-#define reg_bif_dma_rw_ack_intr_offset 132
-
-/* Register r_intr, scope bif_dma, type r */
-#define reg_bif_dma_r_intr___ext_dma0___lsb 0
-#define reg_bif_dma_r_intr___ext_dma0___width 1
-#define reg_bif_dma_r_intr___ext_dma0___bit 0
-#define reg_bif_dma_r_intr___ext_dma1___lsb 1
-#define reg_bif_dma_r_intr___ext_dma1___width 1
-#define reg_bif_dma_r_intr___ext_dma1___bit 1
-#define reg_bif_dma_r_intr___ext_dma2___lsb 2
-#define reg_bif_dma_r_intr___ext_dma2___width 1
-#define reg_bif_dma_r_intr___ext_dma2___bit 2
-#define reg_bif_dma_r_intr___ext_dma3___lsb 3
-#define reg_bif_dma_r_intr___ext_dma3___width 1
-#define reg_bif_dma_r_intr___ext_dma3___bit 3
-#define reg_bif_dma_r_intr_offset 136
-
-/* Register r_masked_intr, scope bif_dma, type r */
-#define reg_bif_dma_r_masked_intr___ext_dma0___lsb 0
-#define reg_bif_dma_r_masked_intr___ext_dma0___width 1
-#define reg_bif_dma_r_masked_intr___ext_dma0___bit 0
-#define reg_bif_dma_r_masked_intr___ext_dma1___lsb 1
-#define reg_bif_dma_r_masked_intr___ext_dma1___width 1
-#define reg_bif_dma_r_masked_intr___ext_dma1___bit 1
-#define reg_bif_dma_r_masked_intr___ext_dma2___lsb 2
-#define reg_bif_dma_r_masked_intr___ext_dma2___width 1
-#define reg_bif_dma_r_masked_intr___ext_dma2___bit 2
-#define reg_bif_dma_r_masked_intr___ext_dma3___lsb 3
-#define reg_bif_dma_r_masked_intr___ext_dma3___width 1
-#define reg_bif_dma_r_masked_intr___ext_dma3___bit 3
-#define reg_bif_dma_r_masked_intr_offset 140
-
-/* Register rw_pin0_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin0_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin0_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin0_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin0_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin0_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin0_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin0_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin0_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin0_cfg_offset 160
-
-/* Register rw_pin1_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin1_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin1_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin1_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin1_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin1_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin1_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin1_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin1_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin1_cfg_offset 164
-
-/* Register rw_pin2_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin2_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin2_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin2_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin2_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin2_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin2_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin2_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin2_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin2_cfg_offset 168
-
-/* Register rw_pin3_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin3_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin3_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin3_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin3_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin3_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin3_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin3_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin3_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin3_cfg_offset 172
-
-/* Register rw_pin4_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin4_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin4_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin4_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin4_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin4_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin4_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin4_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin4_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin4_cfg_offset 176
-
-/* Register rw_pin5_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin5_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin5_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin5_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin5_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin5_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin5_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin5_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin5_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin5_cfg_offset 180
-
-/* Register rw_pin6_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin6_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin6_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin6_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin6_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin6_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin6_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin6_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin6_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin6_cfg_offset 184
-
-/* Register rw_pin7_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin7_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin7_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin7_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin7_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin7_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin7_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin7_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin7_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin7_cfg_offset 188
-
-/* Register r_pin_stat, scope bif_dma, type r */
-#define reg_bif_dma_r_pin_stat___pin0___lsb 0
-#define reg_bif_dma_r_pin_stat___pin0___width 1
-#define reg_bif_dma_r_pin_stat___pin0___bit 0
-#define reg_bif_dma_r_pin_stat___pin1___lsb 1
-#define reg_bif_dma_r_pin_stat___pin1___width 1
-#define reg_bif_dma_r_pin_stat___pin1___bit 1
-#define reg_bif_dma_r_pin_stat___pin2___lsb 2
-#define reg_bif_dma_r_pin_stat___pin2___width 1
-#define reg_bif_dma_r_pin_stat___pin2___bit 2
-#define reg_bif_dma_r_pin_stat___pin3___lsb 3
-#define reg_bif_dma_r_pin_stat___pin3___width 1
-#define reg_bif_dma_r_pin_stat___pin3___bit 3
-#define reg_bif_dma_r_pin_stat___pin4___lsb 4
-#define reg_bif_dma_r_pin_stat___pin4___width 1
-#define reg_bif_dma_r_pin_stat___pin4___bit 4
-#define reg_bif_dma_r_pin_stat___pin5___lsb 5
-#define reg_bif_dma_r_pin_stat___pin5___width 1
-#define reg_bif_dma_r_pin_stat___pin5___bit 5
-#define reg_bif_dma_r_pin_stat___pin6___lsb 6
-#define reg_bif_dma_r_pin_stat___pin6___width 1
-#define reg_bif_dma_r_pin_stat___pin6___bit 6
-#define reg_bif_dma_r_pin_stat___pin7___lsb 7
-#define reg_bif_dma_r_pin_stat___pin7___width 1
-#define reg_bif_dma_r_pin_stat___pin7___bit 7
-#define reg_bif_dma_r_pin_stat_offset 192
-
-
-/* Constants */
-#define regk_bif_dma_as_master                    0x00000001
-#define regk_bif_dma_as_slave                     0x00000001
-#define regk_bif_dma_burst1                       0x00000000
-#define regk_bif_dma_burst8                       0x00000001
-#define regk_bif_dma_bw16                         0x00000001
-#define regk_bif_dma_bw32                         0x00000002
-#define regk_bif_dma_bw8                          0x00000000
-#define regk_bif_dma_dack                         0x00000006
-#define regk_bif_dma_dack_inv                     0x00000007
-#define regk_bif_dma_force                        0x00000001
-#define regk_bif_dma_hi                           0x00000003
-#define regk_bif_dma_inv                          0x00000003
-#define regk_bif_dma_lo                           0x00000002
-#define regk_bif_dma_master                       0x00000001
-#define regk_bif_dma_no                           0x00000000
-#define regk_bif_dma_norm                         0x00000002
-#define regk_bif_dma_off                          0x00000000
-#define regk_bif_dma_rw_ch0_ctrl_default          0x00000000
-#define regk_bif_dma_rw_ch0_start_default         0x00000000
-#define regk_bif_dma_rw_ch1_ctrl_default          0x00000000
-#define regk_bif_dma_rw_ch1_start_default         0x00000000
-#define regk_bif_dma_rw_ch2_ctrl_default          0x00000000
-#define regk_bif_dma_rw_ch2_start_default         0x00000000
-#define regk_bif_dma_rw_ch3_ctrl_default          0x00000000
-#define regk_bif_dma_rw_ch3_start_default         0x00000000
-#define regk_bif_dma_rw_intr_mask_default         0x00000000
-#define regk_bif_dma_rw_pin0_cfg_default          0x00000000
-#define regk_bif_dma_rw_pin1_cfg_default          0x00000000
-#define regk_bif_dma_rw_pin2_cfg_default          0x00000000
-#define regk_bif_dma_rw_pin3_cfg_default          0x00000000
-#define regk_bif_dma_rw_pin4_cfg_default          0x00000000
-#define regk_bif_dma_rw_pin5_cfg_default          0x00000000
-#define regk_bif_dma_rw_pin6_cfg_default          0x00000000
-#define regk_bif_dma_rw_pin7_cfg_default          0x00000000
-#define regk_bif_dma_slave                        0x00000002
-#define regk_bif_dma_sreq                         0x00000006
-#define regk_bif_dma_sreq_inv                     0x00000007
-#define regk_bif_dma_tc                           0x00000004
-#define regk_bif_dma_tc_inv                       0x00000005
-#define regk_bif_dma_yes                          0x00000001
-#endif /* __bif_dma_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h
deleted file mode 100644
index 031f33a365bb..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h
+++ /dev/null
@@ -1,249 +0,0 @@
-#ifndef __bif_slave_defs_asm_h
-#define __bif_slave_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/bif/rtl/bif_slave_regs.r
- *     id:           bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
- *     last modfied: Mon Apr 11 16:06:34 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_slave_defs_asm.h ../../inst/bif/rtl/bif_slave_regs.r
- *      id: $Id: bif_slave_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_slave_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_slave_cfg___slave_id___lsb 0
-#define reg_bif_slave_rw_slave_cfg___slave_id___width 3
-#define reg_bif_slave_rw_slave_cfg___use_slave_id___lsb 3
-#define reg_bif_slave_rw_slave_cfg___use_slave_id___width 1
-#define reg_bif_slave_rw_slave_cfg___use_slave_id___bit 3
-#define reg_bif_slave_rw_slave_cfg___boot_rdy___lsb 4
-#define reg_bif_slave_rw_slave_cfg___boot_rdy___width 1
-#define reg_bif_slave_rw_slave_cfg___boot_rdy___bit 4
-#define reg_bif_slave_rw_slave_cfg___loopback___lsb 5
-#define reg_bif_slave_rw_slave_cfg___loopback___width 1
-#define reg_bif_slave_rw_slave_cfg___loopback___bit 5
-#define reg_bif_slave_rw_slave_cfg___dis___lsb 6
-#define reg_bif_slave_rw_slave_cfg___dis___width 1
-#define reg_bif_slave_rw_slave_cfg___dis___bit 6
-#define reg_bif_slave_rw_slave_cfg_offset 0
-
-/* Register r_slave_mode, scope bif_slave, type r */
-#define reg_bif_slave_r_slave_mode___ch0_mode___lsb 0
-#define reg_bif_slave_r_slave_mode___ch0_mode___width 1
-#define reg_bif_slave_r_slave_mode___ch0_mode___bit 0
-#define reg_bif_slave_r_slave_mode___ch1_mode___lsb 1
-#define reg_bif_slave_r_slave_mode___ch1_mode___width 1
-#define reg_bif_slave_r_slave_mode___ch1_mode___bit 1
-#define reg_bif_slave_r_slave_mode___ch2_mode___lsb 2
-#define reg_bif_slave_r_slave_mode___ch2_mode___width 1
-#define reg_bif_slave_r_slave_mode___ch2_mode___bit 2
-#define reg_bif_slave_r_slave_mode___ch3_mode___lsb 3
-#define reg_bif_slave_r_slave_mode___ch3_mode___width 1
-#define reg_bif_slave_r_slave_mode___ch3_mode___bit 3
-#define reg_bif_slave_r_slave_mode_offset 4
-
-/* Register rw_ch0_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_ch0_cfg___rd_hold___lsb 0
-#define reg_bif_slave_rw_ch0_cfg___rd_hold___width 2
-#define reg_bif_slave_rw_ch0_cfg___access_mode___lsb 2
-#define reg_bif_slave_rw_ch0_cfg___access_mode___width 1
-#define reg_bif_slave_rw_ch0_cfg___access_mode___bit 2
-#define reg_bif_slave_rw_ch0_cfg___access_ctrl___lsb 3
-#define reg_bif_slave_rw_ch0_cfg___access_ctrl___width 1
-#define reg_bif_slave_rw_ch0_cfg___access_ctrl___bit 3
-#define reg_bif_slave_rw_ch0_cfg___data_cs___lsb 4
-#define reg_bif_slave_rw_ch0_cfg___data_cs___width 2
-#define reg_bif_slave_rw_ch0_cfg_offset 16
-
-/* Register rw_ch1_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_ch1_cfg___rd_hold___lsb 0
-#define reg_bif_slave_rw_ch1_cfg___rd_hold___width 2
-#define reg_bif_slave_rw_ch1_cfg___access_mode___lsb 2
-#define reg_bif_slave_rw_ch1_cfg___access_mode___width 1
-#define reg_bif_slave_rw_ch1_cfg___access_mode___bit 2
-#define reg_bif_slave_rw_ch1_cfg___access_ctrl___lsb 3
-#define reg_bif_slave_rw_ch1_cfg___access_ctrl___width 1
-#define reg_bif_slave_rw_ch1_cfg___access_ctrl___bit 3
-#define reg_bif_slave_rw_ch1_cfg___data_cs___lsb 4
-#define reg_bif_slave_rw_ch1_cfg___data_cs___width 2
-#define reg_bif_slave_rw_ch1_cfg_offset 20
-
-/* Register rw_ch2_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_ch2_cfg___rd_hold___lsb 0
-#define reg_bif_slave_rw_ch2_cfg___rd_hold___width 2
-#define reg_bif_slave_rw_ch2_cfg___access_mode___lsb 2
-#define reg_bif_slave_rw_ch2_cfg___access_mode___width 1
-#define reg_bif_slave_rw_ch2_cfg___access_mode___bit 2
-#define reg_bif_slave_rw_ch2_cfg___access_ctrl___lsb 3
-#define reg_bif_slave_rw_ch2_cfg___access_ctrl___width 1
-#define reg_bif_slave_rw_ch2_cfg___access_ctrl___bit 3
-#define reg_bif_slave_rw_ch2_cfg___data_cs___lsb 4
-#define reg_bif_slave_rw_ch2_cfg___data_cs___width 2
-#define reg_bif_slave_rw_ch2_cfg_offset 24
-
-/* Register rw_ch3_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_ch3_cfg___rd_hold___lsb 0
-#define reg_bif_slave_rw_ch3_cfg___rd_hold___width 2
-#define reg_bif_slave_rw_ch3_cfg___access_mode___lsb 2
-#define reg_bif_slave_rw_ch3_cfg___access_mode___width 1
-#define reg_bif_slave_rw_ch3_cfg___access_mode___bit 2
-#define reg_bif_slave_rw_ch3_cfg___access_ctrl___lsb 3
-#define reg_bif_slave_rw_ch3_cfg___access_ctrl___width 1
-#define reg_bif_slave_rw_ch3_cfg___access_ctrl___bit 3
-#define reg_bif_slave_rw_ch3_cfg___data_cs___lsb 4
-#define reg_bif_slave_rw_ch3_cfg___data_cs___width 2
-#define reg_bif_slave_rw_ch3_cfg_offset 28
-
-/* Register rw_arb_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_arb_cfg___brin_mode___lsb 0
-#define reg_bif_slave_rw_arb_cfg___brin_mode___width 1
-#define reg_bif_slave_rw_arb_cfg___brin_mode___bit 0
-#define reg_bif_slave_rw_arb_cfg___brout_mode___lsb 1
-#define reg_bif_slave_rw_arb_cfg___brout_mode___width 3
-#define reg_bif_slave_rw_arb_cfg___bg_mode___lsb 4
-#define reg_bif_slave_rw_arb_cfg___bg_mode___width 3
-#define reg_bif_slave_rw_arb_cfg___release___lsb 7
-#define reg_bif_slave_rw_arb_cfg___release___width 2
-#define reg_bif_slave_rw_arb_cfg___acquire___lsb 9
-#define reg_bif_slave_rw_arb_cfg___acquire___width 1
-#define reg_bif_slave_rw_arb_cfg___acquire___bit 9
-#define reg_bif_slave_rw_arb_cfg___settle_time___lsb 10
-#define reg_bif_slave_rw_arb_cfg___settle_time___width 2
-#define reg_bif_slave_rw_arb_cfg___dram_ctrl___lsb 12
-#define reg_bif_slave_rw_arb_cfg___dram_ctrl___width 1
-#define reg_bif_slave_rw_arb_cfg___dram_ctrl___bit 12
-#define reg_bif_slave_rw_arb_cfg_offset 32
-
-/* Register r_arb_stat, scope bif_slave, type r */
-#define reg_bif_slave_r_arb_stat___init_mode___lsb 0
-#define reg_bif_slave_r_arb_stat___init_mode___width 1
-#define reg_bif_slave_r_arb_stat___init_mode___bit 0
-#define reg_bif_slave_r_arb_stat___mode___lsb 1
-#define reg_bif_slave_r_arb_stat___mode___width 1
-#define reg_bif_slave_r_arb_stat___mode___bit 1
-#define reg_bif_slave_r_arb_stat___brin___lsb 2
-#define reg_bif_slave_r_arb_stat___brin___width 1
-#define reg_bif_slave_r_arb_stat___brin___bit 2
-#define reg_bif_slave_r_arb_stat___brout___lsb 3
-#define reg_bif_slave_r_arb_stat___brout___width 1
-#define reg_bif_slave_r_arb_stat___brout___bit 3
-#define reg_bif_slave_r_arb_stat___bg___lsb 4
-#define reg_bif_slave_r_arb_stat___bg___width 1
-#define reg_bif_slave_r_arb_stat___bg___bit 4
-#define reg_bif_slave_r_arb_stat_offset 36
-
-/* Register rw_intr_mask, scope bif_slave, type rw */
-#define reg_bif_slave_rw_intr_mask___bus_release___lsb 0
-#define reg_bif_slave_rw_intr_mask___bus_release___width 1
-#define reg_bif_slave_rw_intr_mask___bus_release___bit 0
-#define reg_bif_slave_rw_intr_mask___bus_acquire___lsb 1
-#define reg_bif_slave_rw_intr_mask___bus_acquire___width 1
-#define reg_bif_slave_rw_intr_mask___bus_acquire___bit 1
-#define reg_bif_slave_rw_intr_mask_offset 64
-
-/* Register rw_ack_intr, scope bif_slave, type rw */
-#define reg_bif_slave_rw_ack_intr___bus_release___lsb 0
-#define reg_bif_slave_rw_ack_intr___bus_release___width 1
-#define reg_bif_slave_rw_ack_intr___bus_release___bit 0
-#define reg_bif_slave_rw_ack_intr___bus_acquire___lsb 1
-#define reg_bif_slave_rw_ack_intr___bus_acquire___width 1
-#define reg_bif_slave_rw_ack_intr___bus_acquire___bit 1
-#define reg_bif_slave_rw_ack_intr_offset 68
-
-/* Register r_intr, scope bif_slave, type r */
-#define reg_bif_slave_r_intr___bus_release___lsb 0
-#define reg_bif_slave_r_intr___bus_release___width 1
-#define reg_bif_slave_r_intr___bus_release___bit 0
-#define reg_bif_slave_r_intr___bus_acquire___lsb 1
-#define reg_bif_slave_r_intr___bus_acquire___width 1
-#define reg_bif_slave_r_intr___bus_acquire___bit 1
-#define reg_bif_slave_r_intr_offset 72
-
-/* Register r_masked_intr, scope bif_slave, type r */
-#define reg_bif_slave_r_masked_intr___bus_release___lsb 0
-#define reg_bif_slave_r_masked_intr___bus_release___width 1
-#define reg_bif_slave_r_masked_intr___bus_release___bit 0
-#define reg_bif_slave_r_masked_intr___bus_acquire___lsb 1
-#define reg_bif_slave_r_masked_intr___bus_acquire___width 1
-#define reg_bif_slave_r_masked_intr___bus_acquire___bit 1
-#define reg_bif_slave_r_masked_intr_offset 76
-
-
-/* Constants */
-#define regk_bif_slave_active_hi                  0x00000003
-#define regk_bif_slave_active_lo                  0x00000002
-#define regk_bif_slave_addr                       0x00000000
-#define regk_bif_slave_always                     0x00000001
-#define regk_bif_slave_at_idle                    0x00000002
-#define regk_bif_slave_burst_end                  0x00000003
-#define regk_bif_slave_dma                        0x00000001
-#define regk_bif_slave_hi                         0x00000003
-#define regk_bif_slave_inv                        0x00000001
-#define regk_bif_slave_lo                         0x00000002
-#define regk_bif_slave_local                      0x00000001
-#define regk_bif_slave_master                     0x00000000
-#define regk_bif_slave_mode_reg                   0x00000001
-#define regk_bif_slave_no                         0x00000000
-#define regk_bif_slave_norm                       0x00000000
-#define regk_bif_slave_on_access                  0x00000000
-#define regk_bif_slave_rw_arb_cfg_default         0x00000000
-#define regk_bif_slave_rw_ch0_cfg_default         0x00000000
-#define regk_bif_slave_rw_ch1_cfg_default         0x00000000
-#define regk_bif_slave_rw_ch2_cfg_default         0x00000000
-#define regk_bif_slave_rw_ch3_cfg_default         0x00000000
-#define regk_bif_slave_rw_intr_mask_default       0x00000000
-#define regk_bif_slave_rw_slave_cfg_default       0x00000000
-#define regk_bif_slave_shared                     0x00000000
-#define regk_bif_slave_slave                      0x00000001
-#define regk_bif_slave_t0ns                       0x00000003
-#define regk_bif_slave_t10ns                      0x00000002
-#define regk_bif_slave_t20ns                      0x00000003
-#define regk_bif_slave_t30ns                      0x00000002
-#define regk_bif_slave_t40ns                      0x00000001
-#define regk_bif_slave_t50ns                      0x00000000
-#define regk_bif_slave_yes                        0x00000001
-#define regk_bif_slave_z                          0x00000004
-#endif /* __bif_slave_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h
deleted file mode 100644
index e98476332e1f..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h
+++ /dev/null
@@ -1,131 +0,0 @@
-#ifndef __config_defs_asm_h
-#define __config_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../rtl/config_regs.r
- *     id:           config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
- *     last modfied: Thu Mar  4 12:34:39 2004
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r
- *      id: $Id: config_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_bootsel, scope config, type r */
-#define reg_config_r_bootsel___boot_mode___lsb 0
-#define reg_config_r_bootsel___boot_mode___width 3
-#define reg_config_r_bootsel___full_duplex___lsb 3
-#define reg_config_r_bootsel___full_duplex___width 1
-#define reg_config_r_bootsel___full_duplex___bit 3
-#define reg_config_r_bootsel___user___lsb 4
-#define reg_config_r_bootsel___user___width 1
-#define reg_config_r_bootsel___user___bit 4
-#define reg_config_r_bootsel___pll___lsb 5
-#define reg_config_r_bootsel___pll___width 1
-#define reg_config_r_bootsel___pll___bit 5
-#define reg_config_r_bootsel___flash_bw___lsb 6
-#define reg_config_r_bootsel___flash_bw___width 1
-#define reg_config_r_bootsel___flash_bw___bit 6
-#define reg_config_r_bootsel_offset 0
-
-/* Register rw_clk_ctrl, scope config, type rw */
-#define reg_config_rw_clk_ctrl___pll___lsb 0
-#define reg_config_rw_clk_ctrl___pll___width 1
-#define reg_config_rw_clk_ctrl___pll___bit 0
-#define reg_config_rw_clk_ctrl___cpu___lsb 1
-#define reg_config_rw_clk_ctrl___cpu___width 1
-#define reg_config_rw_clk_ctrl___cpu___bit 1
-#define reg_config_rw_clk_ctrl___iop___lsb 2
-#define reg_config_rw_clk_ctrl___iop___width 1
-#define reg_config_rw_clk_ctrl___iop___bit 2
-#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3
-#define reg_config_rw_clk_ctrl___dma01_eth0___width 1
-#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3
-#define reg_config_rw_clk_ctrl___dma23___lsb 4
-#define reg_config_rw_clk_ctrl___dma23___width 1
-#define reg_config_rw_clk_ctrl___dma23___bit 4
-#define reg_config_rw_clk_ctrl___dma45___lsb 5
-#define reg_config_rw_clk_ctrl___dma45___width 1
-#define reg_config_rw_clk_ctrl___dma45___bit 5
-#define reg_config_rw_clk_ctrl___dma67___lsb 6
-#define reg_config_rw_clk_ctrl___dma67___width 1
-#define reg_config_rw_clk_ctrl___dma67___bit 6
-#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7
-#define reg_config_rw_clk_ctrl___dma89_strcop___width 1
-#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7
-#define reg_config_rw_clk_ctrl___bif___lsb 8
-#define reg_config_rw_clk_ctrl___bif___width 1
-#define reg_config_rw_clk_ctrl___bif___bit 8
-#define reg_config_rw_clk_ctrl___fix_io___lsb 9
-#define reg_config_rw_clk_ctrl___fix_io___width 1
-#define reg_config_rw_clk_ctrl___fix_io___bit 9
-#define reg_config_rw_clk_ctrl_offset 4
-
-/* Register rw_pad_ctrl, scope config, type rw */
-#define reg_config_rw_pad_ctrl___usb_susp___lsb 0
-#define reg_config_rw_pad_ctrl___usb_susp___width 1
-#define reg_config_rw_pad_ctrl___usb_susp___bit 0
-#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1
-#define reg_config_rw_pad_ctrl___phyrst_n___width 1
-#define reg_config_rw_pad_ctrl___phyrst_n___bit 1
-#define reg_config_rw_pad_ctrl_offset 8
-
-
-/* Constants */
-#define regk_config_bw16                          0x00000000
-#define regk_config_bw32                          0x00000001
-#define regk_config_master                        0x00000005
-#define regk_config_nand                          0x00000003
-#define regk_config_net_rx                        0x00000001
-#define regk_config_net_tx_rx                     0x00000002
-#define regk_config_no                            0x00000000
-#define regk_config_none                          0x00000007
-#define regk_config_nor                           0x00000000
-#define regk_config_rw_clk_ctrl_default           0x00000002
-#define regk_config_rw_pad_ctrl_default           0x00000000
-#define regk_config_ser                           0x00000004
-#define regk_config_slave                         0x00000006
-#define regk_config_yes                           0x00000001
-#endif /* __config_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h b/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h
deleted file mode 100644
index 8370aee8a14a..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
- from ../../inst/crisp/doc/cpu_vect.r
-version . */
-
-#ifndef _______INST_CRISP_DOC_CPU_VECT_R
-#define _______INST_CRISP_DOC_CPU_VECT_R
-#define NMI_INTR_VECT	0x00
-#define RESERVED_1_INTR_VECT	0x01
-#define RESERVED_2_INTR_VECT	0x02
-#define SINGLE_STEP_INTR_VECT	0x03
-#define INSTR_TLB_REFILL_INTR_VECT	0x04
-#define INSTR_TLB_INV_INTR_VECT	0x05
-#define INSTR_TLB_ACC_INTR_VECT	0x06
-#define TLB_EX_INTR_VECT	0x07
-#define DATA_TLB_REFILL_INTR_VECT	0x08
-#define DATA_TLB_INV_INTR_VECT	0x09
-#define DATA_TLB_ACC_INTR_VECT	0x0a
-#define DATA_TLB_WE_INTR_VECT	0x0b
-#define HW_BP_INTR_VECT	0x0c
-#define RESERVED_D_INTR_VECT	0x0d
-#define RESERVED_E_INTR_VECT	0x0e
-#define RESERVED_F_INTR_VECT	0x0f
-#define BREAK_0_INTR_VECT	0x10
-#define BREAK_1_INTR_VECT	0x11
-#define BREAK_2_INTR_VECT	0x12
-#define BREAK_3_INTR_VECT	0x13
-#define BREAK_4_INTR_VECT	0x14
-#define BREAK_5_INTR_VECT	0x15
-#define BREAK_6_INTR_VECT	0x16
-#define BREAK_7_INTR_VECT	0x17
-#define BREAK_8_INTR_VECT	0x18
-#define BREAK_9_INTR_VECT	0x19
-#define BREAK_10_INTR_VECT	0x1a
-#define BREAK_11_INTR_VECT	0x1b
-#define BREAK_12_INTR_VECT	0x1c
-#define BREAK_13_INTR_VECT	0x1d
-#define BREAK_14_INTR_VECT	0x1e
-#define BREAK_15_INTR_VECT	0x1f
-#define MULTIPLE_INTR_VECT	0x30
-
-#endif
diff --git a/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h
deleted file mode 100644
index 7f768db272e2..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h
+++ /dev/null
@@ -1,114 +0,0 @@
-#ifndef __cris_defs_asm_h
-#define __cris_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/crisp/doc/cris.r
- *     id:           cris.r,v 1.6 2004/05/05 07:41:12 perz Exp
- *     last modfied: Mon Apr 11 16:06:39 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r
- *      id: $Id: cris_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_gc_cfg, scope cris, type rw */
-#define reg_cris_rw_gc_cfg___ic___lsb 0
-#define reg_cris_rw_gc_cfg___ic___width 1
-#define reg_cris_rw_gc_cfg___ic___bit 0
-#define reg_cris_rw_gc_cfg___dc___lsb 1
-#define reg_cris_rw_gc_cfg___dc___width 1
-#define reg_cris_rw_gc_cfg___dc___bit 1
-#define reg_cris_rw_gc_cfg___im___lsb 2
-#define reg_cris_rw_gc_cfg___im___width 1
-#define reg_cris_rw_gc_cfg___im___bit 2
-#define reg_cris_rw_gc_cfg___dm___lsb 3
-#define reg_cris_rw_gc_cfg___dm___width 1
-#define reg_cris_rw_gc_cfg___dm___bit 3
-#define reg_cris_rw_gc_cfg___gb___lsb 4
-#define reg_cris_rw_gc_cfg___gb___width 1
-#define reg_cris_rw_gc_cfg___gb___bit 4
-#define reg_cris_rw_gc_cfg___gk___lsb 5
-#define reg_cris_rw_gc_cfg___gk___width 1
-#define reg_cris_rw_gc_cfg___gk___bit 5
-#define reg_cris_rw_gc_cfg___gp___lsb 6
-#define reg_cris_rw_gc_cfg___gp___width 1
-#define reg_cris_rw_gc_cfg___gp___bit 6
-#define reg_cris_rw_gc_cfg_offset 0
-
-/* Register rw_gc_ccs, scope cris, type rw */
-#define reg_cris_rw_gc_ccs_offset 4
-
-/* Register rw_gc_srs, scope cris, type rw */
-#define reg_cris_rw_gc_srs___srs___lsb 0
-#define reg_cris_rw_gc_srs___srs___width 8
-#define reg_cris_rw_gc_srs_offset 8
-
-/* Register rw_gc_nrp, scope cris, type rw */
-#define reg_cris_rw_gc_nrp_offset 12
-
-/* Register rw_gc_exs, scope cris, type rw */
-#define reg_cris_rw_gc_exs_offset 16
-
-/* Register rw_gc_eda, scope cris, type rw */
-#define reg_cris_rw_gc_eda_offset 20
-
-/* Register rw_gc_r0, scope cris, type rw */
-#define reg_cris_rw_gc_r0_offset 32
-
-/* Register rw_gc_r1, scope cris, type rw */
-#define reg_cris_rw_gc_r1_offset 36
-
-/* Register rw_gc_r2, scope cris, type rw */
-#define reg_cris_rw_gc_r2_offset 40
-
-/* Register rw_gc_r3, scope cris, type rw */
-#define reg_cris_rw_gc_r3_offset 44
-
-
-/* Constants */
-#define regk_cris_no                              0x00000000
-#define regk_cris_rw_gc_cfg_default               0x00000000
-#define regk_cris_yes                             0x00000001
-#endif /* __cris_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h b/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h
deleted file mode 100644
index 7d3689a6f80d..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#define RW_GC_CFG	0
-#define RW_GC_CCS	1
-#define RW_GC_SRS	2
-#define RW_GC_NRP	3
-#define RW_GC_EXS	4
-#define RW_GC_EDA	5
-#define RW_GC_R0	8
-#define RW_GC_R1	9
-#define RW_GC_R2	10
-#define RW_GC_R3	11
diff --git a/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h
deleted file mode 100644
index 0cb71bc127ae..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h
+++ /dev/null
@@ -1,368 +0,0 @@
-#ifndef __dma_defs_asm_h
-#define __dma_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
- *     id:           dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
- *     last modfied: Mon Apr 11 16:06:51 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/dma_defs_asm.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
- *      id: $Id: dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_data, scope dma, type rw */
-#define reg_dma_rw_data_offset 0
-
-/* Register rw_data_next, scope dma, type rw */
-#define reg_dma_rw_data_next_offset 4
-
-/* Register rw_data_buf, scope dma, type rw */
-#define reg_dma_rw_data_buf_offset 8
-
-/* Register rw_data_ctrl, scope dma, type rw */
-#define reg_dma_rw_data_ctrl___eol___lsb 0
-#define reg_dma_rw_data_ctrl___eol___width 1
-#define reg_dma_rw_data_ctrl___eol___bit 0
-#define reg_dma_rw_data_ctrl___out_eop___lsb 3
-#define reg_dma_rw_data_ctrl___out_eop___width 1
-#define reg_dma_rw_data_ctrl___out_eop___bit 3
-#define reg_dma_rw_data_ctrl___intr___lsb 4
-#define reg_dma_rw_data_ctrl___intr___width 1
-#define reg_dma_rw_data_ctrl___intr___bit 4
-#define reg_dma_rw_data_ctrl___wait___lsb 5
-#define reg_dma_rw_data_ctrl___wait___width 1
-#define reg_dma_rw_data_ctrl___wait___bit 5
-#define reg_dma_rw_data_ctrl_offset 12
-
-/* Register rw_data_stat, scope dma, type rw */
-#define reg_dma_rw_data_stat___in_eop___lsb 3
-#define reg_dma_rw_data_stat___in_eop___width 1
-#define reg_dma_rw_data_stat___in_eop___bit 3
-#define reg_dma_rw_data_stat_offset 16
-
-/* Register rw_data_md, scope dma, type rw */
-#define reg_dma_rw_data_md___md___lsb 0
-#define reg_dma_rw_data_md___md___width 16
-#define reg_dma_rw_data_md_offset 20
-
-/* Register rw_data_md_s, scope dma, type rw */
-#define reg_dma_rw_data_md_s___md_s___lsb 0
-#define reg_dma_rw_data_md_s___md_s___width 16
-#define reg_dma_rw_data_md_s_offset 24
-
-/* Register rw_data_after, scope dma, type rw */
-#define reg_dma_rw_data_after_offset 28
-
-/* Register rw_ctxt, scope dma, type rw */
-#define reg_dma_rw_ctxt_offset 32
-
-/* Register rw_ctxt_next, scope dma, type rw */
-#define reg_dma_rw_ctxt_next_offset 36
-
-/* Register rw_ctxt_ctrl, scope dma, type rw */
-#define reg_dma_rw_ctxt_ctrl___eol___lsb 0
-#define reg_dma_rw_ctxt_ctrl___eol___width 1
-#define reg_dma_rw_ctxt_ctrl___eol___bit 0
-#define reg_dma_rw_ctxt_ctrl___intr___lsb 4
-#define reg_dma_rw_ctxt_ctrl___intr___width 1
-#define reg_dma_rw_ctxt_ctrl___intr___bit 4
-#define reg_dma_rw_ctxt_ctrl___store_mode___lsb 6
-#define reg_dma_rw_ctxt_ctrl___store_mode___width 1
-#define reg_dma_rw_ctxt_ctrl___store_mode___bit 6
-#define reg_dma_rw_ctxt_ctrl___en___lsb 7
-#define reg_dma_rw_ctxt_ctrl___en___width 1
-#define reg_dma_rw_ctxt_ctrl___en___bit 7
-#define reg_dma_rw_ctxt_ctrl_offset 40
-
-/* Register rw_ctxt_stat, scope dma, type rw */
-#define reg_dma_rw_ctxt_stat___dis___lsb 7
-#define reg_dma_rw_ctxt_stat___dis___width 1
-#define reg_dma_rw_ctxt_stat___dis___bit 7
-#define reg_dma_rw_ctxt_stat_offset 44
-
-/* Register rw_ctxt_md0, scope dma, type rw */
-#define reg_dma_rw_ctxt_md0___md0___lsb 0
-#define reg_dma_rw_ctxt_md0___md0___width 16
-#define reg_dma_rw_ctxt_md0_offset 48
-
-/* Register rw_ctxt_md0_s, scope dma, type rw */
-#define reg_dma_rw_ctxt_md0_s___md0_s___lsb 0
-#define reg_dma_rw_ctxt_md0_s___md0_s___width 16
-#define reg_dma_rw_ctxt_md0_s_offset 52
-
-/* Register rw_ctxt_md1, scope dma, type rw */
-#define reg_dma_rw_ctxt_md1_offset 56
-
-/* Register rw_ctxt_md1_s, scope dma, type rw */
-#define reg_dma_rw_ctxt_md1_s_offset 60
-
-/* Register rw_ctxt_md2, scope dma, type rw */
-#define reg_dma_rw_ctxt_md2_offset 64
-
-/* Register rw_ctxt_md2_s, scope dma, type rw */
-#define reg_dma_rw_ctxt_md2_s_offset 68
-
-/* Register rw_ctxt_md3, scope dma, type rw */
-#define reg_dma_rw_ctxt_md3_offset 72
-
-/* Register rw_ctxt_md3_s, scope dma, type rw */
-#define reg_dma_rw_ctxt_md3_s_offset 76
-
-/* Register rw_ctxt_md4, scope dma, type rw */
-#define reg_dma_rw_ctxt_md4_offset 80
-
-/* Register rw_ctxt_md4_s, scope dma, type rw */
-#define reg_dma_rw_ctxt_md4_s_offset 84
-
-/* Register rw_saved_data, scope dma, type rw */
-#define reg_dma_rw_saved_data_offset 88
-
-/* Register rw_saved_data_buf, scope dma, type rw */
-#define reg_dma_rw_saved_data_buf_offset 92
-
-/* Register rw_group, scope dma, type rw */
-#define reg_dma_rw_group_offset 96
-
-/* Register rw_group_next, scope dma, type rw */
-#define reg_dma_rw_group_next_offset 100
-
-/* Register rw_group_ctrl, scope dma, type rw */
-#define reg_dma_rw_group_ctrl___eol___lsb 0
-#define reg_dma_rw_group_ctrl___eol___width 1
-#define reg_dma_rw_group_ctrl___eol___bit 0
-#define reg_dma_rw_group_ctrl___tol___lsb 1
-#define reg_dma_rw_group_ctrl___tol___width 1
-#define reg_dma_rw_group_ctrl___tol___bit 1
-#define reg_dma_rw_group_ctrl___bol___lsb 2
-#define reg_dma_rw_group_ctrl___bol___width 1
-#define reg_dma_rw_group_ctrl___bol___bit 2
-#define reg_dma_rw_group_ctrl___intr___lsb 4
-#define reg_dma_rw_group_ctrl___intr___width 1
-#define reg_dma_rw_group_ctrl___intr___bit 4
-#define reg_dma_rw_group_ctrl___en___lsb 7
-#define reg_dma_rw_group_ctrl___en___width 1
-#define reg_dma_rw_group_ctrl___en___bit 7
-#define reg_dma_rw_group_ctrl_offset 104
-
-/* Register rw_group_stat, scope dma, type rw */
-#define reg_dma_rw_group_stat___dis___lsb 7
-#define reg_dma_rw_group_stat___dis___width 1
-#define reg_dma_rw_group_stat___dis___bit 7
-#define reg_dma_rw_group_stat_offset 108
-
-/* Register rw_group_md, scope dma, type rw */
-#define reg_dma_rw_group_md___md___lsb 0
-#define reg_dma_rw_group_md___md___width 16
-#define reg_dma_rw_group_md_offset 112
-
-/* Register rw_group_md_s, scope dma, type rw */
-#define reg_dma_rw_group_md_s___md_s___lsb 0
-#define reg_dma_rw_group_md_s___md_s___width 16
-#define reg_dma_rw_group_md_s_offset 116
-
-/* Register rw_group_up, scope dma, type rw */
-#define reg_dma_rw_group_up_offset 120
-
-/* Register rw_group_down, scope dma, type rw */
-#define reg_dma_rw_group_down_offset 124
-
-/* Register rw_cmd, scope dma, type rw */
-#define reg_dma_rw_cmd___cont_data___lsb 0
-#define reg_dma_rw_cmd___cont_data___width 1
-#define reg_dma_rw_cmd___cont_data___bit 0
-#define reg_dma_rw_cmd_offset 128
-
-/* Register rw_cfg, scope dma, type rw */
-#define reg_dma_rw_cfg___en___lsb 0
-#define reg_dma_rw_cfg___en___width 1
-#define reg_dma_rw_cfg___en___bit 0
-#define reg_dma_rw_cfg___stop___lsb 1
-#define reg_dma_rw_cfg___stop___width 1
-#define reg_dma_rw_cfg___stop___bit 1
-#define reg_dma_rw_cfg_offset 132
-
-/* Register rw_stat, scope dma, type rw */
-#define reg_dma_rw_stat___mode___lsb 0
-#define reg_dma_rw_stat___mode___width 5
-#define reg_dma_rw_stat___list_state___lsb 5
-#define reg_dma_rw_stat___list_state___width 3
-#define reg_dma_rw_stat___stream_cmd_src___lsb 8
-#define reg_dma_rw_stat___stream_cmd_src___width 8
-#define reg_dma_rw_stat___buf___lsb 24
-#define reg_dma_rw_stat___buf___width 8
-#define reg_dma_rw_stat_offset 136
-
-/* Register rw_intr_mask, scope dma, type rw */
-#define reg_dma_rw_intr_mask___group___lsb 0
-#define reg_dma_rw_intr_mask___group___width 1
-#define reg_dma_rw_intr_mask___group___bit 0
-#define reg_dma_rw_intr_mask___ctxt___lsb 1
-#define reg_dma_rw_intr_mask___ctxt___width 1
-#define reg_dma_rw_intr_mask___ctxt___bit 1
-#define reg_dma_rw_intr_mask___data___lsb 2
-#define reg_dma_rw_intr_mask___data___width 1
-#define reg_dma_rw_intr_mask___data___bit 2
-#define reg_dma_rw_intr_mask___in_eop___lsb 3
-#define reg_dma_rw_intr_mask___in_eop___width 1
-#define reg_dma_rw_intr_mask___in_eop___bit 3
-#define reg_dma_rw_intr_mask___stream_cmd___lsb 4
-#define reg_dma_rw_intr_mask___stream_cmd___width 1
-#define reg_dma_rw_intr_mask___stream_cmd___bit 4
-#define reg_dma_rw_intr_mask_offset 140
-
-/* Register rw_ack_intr, scope dma, type rw */
-#define reg_dma_rw_ack_intr___group___lsb 0
-#define reg_dma_rw_ack_intr___group___width 1
-#define reg_dma_rw_ack_intr___group___bit 0
-#define reg_dma_rw_ack_intr___ctxt___lsb 1
-#define reg_dma_rw_ack_intr___ctxt___width 1
-#define reg_dma_rw_ack_intr___ctxt___bit 1
-#define reg_dma_rw_ack_intr___data___lsb 2
-#define reg_dma_rw_ack_intr___data___width 1
-#define reg_dma_rw_ack_intr___data___bit 2
-#define reg_dma_rw_ack_intr___in_eop___lsb 3
-#define reg_dma_rw_ack_intr___in_eop___width 1
-#define reg_dma_rw_ack_intr___in_eop___bit 3
-#define reg_dma_rw_ack_intr___stream_cmd___lsb 4
-#define reg_dma_rw_ack_intr___stream_cmd___width 1
-#define reg_dma_rw_ack_intr___stream_cmd___bit 4
-#define reg_dma_rw_ack_intr_offset 144
-
-/* Register r_intr, scope dma, type r */
-#define reg_dma_r_intr___group___lsb 0
-#define reg_dma_r_intr___group___width 1
-#define reg_dma_r_intr___group___bit 0
-#define reg_dma_r_intr___ctxt___lsb 1
-#define reg_dma_r_intr___ctxt___width 1
-#define reg_dma_r_intr___ctxt___bit 1
-#define reg_dma_r_intr___data___lsb 2
-#define reg_dma_r_intr___data___width 1
-#define reg_dma_r_intr___data___bit 2
-#define reg_dma_r_intr___in_eop___lsb 3
-#define reg_dma_r_intr___in_eop___width 1
-#define reg_dma_r_intr___in_eop___bit 3
-#define reg_dma_r_intr___stream_cmd___lsb 4
-#define reg_dma_r_intr___stream_cmd___width 1
-#define reg_dma_r_intr___stream_cmd___bit 4
-#define reg_dma_r_intr_offset 148
-
-/* Register r_masked_intr, scope dma, type r */
-#define reg_dma_r_masked_intr___group___lsb 0
-#define reg_dma_r_masked_intr___group___width 1
-#define reg_dma_r_masked_intr___group___bit 0
-#define reg_dma_r_masked_intr___ctxt___lsb 1
-#define reg_dma_r_masked_intr___ctxt___width 1
-#define reg_dma_r_masked_intr___ctxt___bit 1
-#define reg_dma_r_masked_intr___data___lsb 2
-#define reg_dma_r_masked_intr___data___width 1
-#define reg_dma_r_masked_intr___data___bit 2
-#define reg_dma_r_masked_intr___in_eop___lsb 3
-#define reg_dma_r_masked_intr___in_eop___width 1
-#define reg_dma_r_masked_intr___in_eop___bit 3
-#define reg_dma_r_masked_intr___stream_cmd___lsb 4
-#define reg_dma_r_masked_intr___stream_cmd___width 1
-#define reg_dma_r_masked_intr___stream_cmd___bit 4
-#define reg_dma_r_masked_intr_offset 152
-
-/* Register rw_stream_cmd, scope dma, type rw */
-#define reg_dma_rw_stream_cmd___cmd___lsb 0
-#define reg_dma_rw_stream_cmd___cmd___width 10
-#define reg_dma_rw_stream_cmd___n___lsb 16
-#define reg_dma_rw_stream_cmd___n___width 8
-#define reg_dma_rw_stream_cmd___busy___lsb 31
-#define reg_dma_rw_stream_cmd___busy___width 1
-#define reg_dma_rw_stream_cmd___busy___bit 31
-#define reg_dma_rw_stream_cmd_offset 156
-
-
-/* Constants */
-#define regk_dma_ack_pkt                          0x00000100
-#define regk_dma_anytime                          0x00000001
-#define regk_dma_array                            0x00000008
-#define regk_dma_burst                            0x00000020
-#define regk_dma_client                           0x00000002
-#define regk_dma_copy_next                        0x00000010
-#define regk_dma_copy_up                          0x00000020
-#define regk_dma_data_at_eol                      0x00000001
-#define regk_dma_dis_c                            0x00000010
-#define regk_dma_dis_g                            0x00000020
-#define regk_dma_idle                             0x00000001
-#define regk_dma_intern                           0x00000004
-#define regk_dma_load_c                           0x00000200
-#define regk_dma_load_c_n                         0x00000280
-#define regk_dma_load_c_next                      0x00000240
-#define regk_dma_load_d                           0x00000140
-#define regk_dma_load_g                           0x00000300
-#define regk_dma_load_g_down                      0x000003c0
-#define regk_dma_load_g_next                      0x00000340
-#define regk_dma_load_g_up                        0x00000380
-#define regk_dma_next_en                          0x00000010
-#define regk_dma_next_pkt                         0x00000010
-#define regk_dma_no                               0x00000000
-#define regk_dma_only_at_wait                     0x00000000
-#define regk_dma_restore                          0x00000020
-#define regk_dma_rst                              0x00000001
-#define regk_dma_running                          0x00000004
-#define regk_dma_rw_cfg_default                   0x00000000
-#define regk_dma_rw_cmd_default                   0x00000000
-#define regk_dma_rw_intr_mask_default             0x00000000
-#define regk_dma_rw_stat_default                  0x00000101
-#define regk_dma_rw_stream_cmd_default            0x00000000
-#define regk_dma_save_down                        0x00000020
-#define regk_dma_save_up                          0x00000020
-#define regk_dma_set_reg                          0x00000050
-#define regk_dma_set_w_size1                      0x00000190
-#define regk_dma_set_w_size2                      0x000001a0
-#define regk_dma_set_w_size4                      0x000001c0
-#define regk_dma_stopped                          0x00000002
-#define regk_dma_store_c                          0x00000002
-#define regk_dma_store_descr                      0x00000000
-#define regk_dma_store_g                          0x00000004
-#define regk_dma_store_md                         0x00000001
-#define regk_dma_sw                               0x00000008
-#define regk_dma_update_down                      0x00000020
-#define regk_dma_yes                              0x00000001
-#endif /* __dma_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h
deleted file mode 100644
index c9f49864831b..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h
+++ /dev/null
@@ -1,498 +0,0 @@
-#ifndef __eth_defs_asm_h
-#define __eth_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/eth/rtl/eth_regs.r
- *     id:           eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp
- *     last modfied: Mon Apr 11 16:07:03 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r
- *      id: $Id: eth_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_ma0_lo, scope eth, type rw */
-#define reg_eth_rw_ma0_lo___addr___lsb 0
-#define reg_eth_rw_ma0_lo___addr___width 32
-#define reg_eth_rw_ma0_lo_offset 0
-
-/* Register rw_ma0_hi, scope eth, type rw */
-#define reg_eth_rw_ma0_hi___addr___lsb 0
-#define reg_eth_rw_ma0_hi___addr___width 16
-#define reg_eth_rw_ma0_hi_offset 4
-
-/* Register rw_ma1_lo, scope eth, type rw */
-#define reg_eth_rw_ma1_lo___addr___lsb 0
-#define reg_eth_rw_ma1_lo___addr___width 32
-#define reg_eth_rw_ma1_lo_offset 8
-
-/* Register rw_ma1_hi, scope eth, type rw */
-#define reg_eth_rw_ma1_hi___addr___lsb 0
-#define reg_eth_rw_ma1_hi___addr___width 16
-#define reg_eth_rw_ma1_hi_offset 12
-
-/* Register rw_ga_lo, scope eth, type rw */
-#define reg_eth_rw_ga_lo___table___lsb 0
-#define reg_eth_rw_ga_lo___table___width 32
-#define reg_eth_rw_ga_lo_offset 16
-
-/* Register rw_ga_hi, scope eth, type rw */
-#define reg_eth_rw_ga_hi___table___lsb 0
-#define reg_eth_rw_ga_hi___table___width 32
-#define reg_eth_rw_ga_hi_offset 20
-
-/* Register rw_gen_ctrl, scope eth, type rw */
-#define reg_eth_rw_gen_ctrl___en___lsb 0
-#define reg_eth_rw_gen_ctrl___en___width 1
-#define reg_eth_rw_gen_ctrl___en___bit 0
-#define reg_eth_rw_gen_ctrl___phy___lsb 1
-#define reg_eth_rw_gen_ctrl___phy___width 2
-#define reg_eth_rw_gen_ctrl___protocol___lsb 3
-#define reg_eth_rw_gen_ctrl___protocol___width 1
-#define reg_eth_rw_gen_ctrl___protocol___bit 3
-#define reg_eth_rw_gen_ctrl___loopback___lsb 4
-#define reg_eth_rw_gen_ctrl___loopback___width 1
-#define reg_eth_rw_gen_ctrl___loopback___bit 4
-#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___lsb 5
-#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___width 1
-#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___bit 5
-#define reg_eth_rw_gen_ctrl_offset 24
-
-/* Register rw_rec_ctrl, scope eth, type rw */
-#define reg_eth_rw_rec_ctrl___ma0___lsb 0
-#define reg_eth_rw_rec_ctrl___ma0___width 1
-#define reg_eth_rw_rec_ctrl___ma0___bit 0
-#define reg_eth_rw_rec_ctrl___ma1___lsb 1
-#define reg_eth_rw_rec_ctrl___ma1___width 1
-#define reg_eth_rw_rec_ctrl___ma1___bit 1
-#define reg_eth_rw_rec_ctrl___individual___lsb 2
-#define reg_eth_rw_rec_ctrl___individual___width 1
-#define reg_eth_rw_rec_ctrl___individual___bit 2
-#define reg_eth_rw_rec_ctrl___broadcast___lsb 3
-#define reg_eth_rw_rec_ctrl___broadcast___width 1
-#define reg_eth_rw_rec_ctrl___broadcast___bit 3
-#define reg_eth_rw_rec_ctrl___undersize___lsb 4
-#define reg_eth_rw_rec_ctrl___undersize___width 1
-#define reg_eth_rw_rec_ctrl___undersize___bit 4
-#define reg_eth_rw_rec_ctrl___oversize___lsb 5
-#define reg_eth_rw_rec_ctrl___oversize___width 1
-#define reg_eth_rw_rec_ctrl___oversize___bit 5
-#define reg_eth_rw_rec_ctrl___bad_crc___lsb 6
-#define reg_eth_rw_rec_ctrl___bad_crc___width 1
-#define reg_eth_rw_rec_ctrl___bad_crc___bit 6
-#define reg_eth_rw_rec_ctrl___duplex___lsb 7
-#define reg_eth_rw_rec_ctrl___duplex___width 1
-#define reg_eth_rw_rec_ctrl___duplex___bit 7
-#define reg_eth_rw_rec_ctrl___max_size___lsb 8
-#define reg_eth_rw_rec_ctrl___max_size___width 1
-#define reg_eth_rw_rec_ctrl___max_size___bit 8
-#define reg_eth_rw_rec_ctrl_offset 28
-
-/* Register rw_tr_ctrl, scope eth, type rw */
-#define reg_eth_rw_tr_ctrl___crc___lsb 0
-#define reg_eth_rw_tr_ctrl___crc___width 1
-#define reg_eth_rw_tr_ctrl___crc___bit 0
-#define reg_eth_rw_tr_ctrl___pad___lsb 1
-#define reg_eth_rw_tr_ctrl___pad___width 1
-#define reg_eth_rw_tr_ctrl___pad___bit 1
-#define reg_eth_rw_tr_ctrl___retry___lsb 2
-#define reg_eth_rw_tr_ctrl___retry___width 1
-#define reg_eth_rw_tr_ctrl___retry___bit 2
-#define reg_eth_rw_tr_ctrl___ignore_col___lsb 3
-#define reg_eth_rw_tr_ctrl___ignore_col___width 1
-#define reg_eth_rw_tr_ctrl___ignore_col___bit 3
-#define reg_eth_rw_tr_ctrl___cancel___lsb 4
-#define reg_eth_rw_tr_ctrl___cancel___width 1
-#define reg_eth_rw_tr_ctrl___cancel___bit 4
-#define reg_eth_rw_tr_ctrl___hsh_delay___lsb 5
-#define reg_eth_rw_tr_ctrl___hsh_delay___width 1
-#define reg_eth_rw_tr_ctrl___hsh_delay___bit 5
-#define reg_eth_rw_tr_ctrl___ignore_crs___lsb 6
-#define reg_eth_rw_tr_ctrl___ignore_crs___width 1
-#define reg_eth_rw_tr_ctrl___ignore_crs___bit 6
-#define reg_eth_rw_tr_ctrl_offset 32
-
-/* Register rw_clr_err, scope eth, type rw */
-#define reg_eth_rw_clr_err___clr___lsb 0
-#define reg_eth_rw_clr_err___clr___width 1
-#define reg_eth_rw_clr_err___clr___bit 0
-#define reg_eth_rw_clr_err_offset 36
-
-/* Register rw_mgm_ctrl, scope eth, type rw */
-#define reg_eth_rw_mgm_ctrl___mdio___lsb 0
-#define reg_eth_rw_mgm_ctrl___mdio___width 1
-#define reg_eth_rw_mgm_ctrl___mdio___bit 0
-#define reg_eth_rw_mgm_ctrl___mdoe___lsb 1
-#define reg_eth_rw_mgm_ctrl___mdoe___width 1
-#define reg_eth_rw_mgm_ctrl___mdoe___bit 1
-#define reg_eth_rw_mgm_ctrl___mdc___lsb 2
-#define reg_eth_rw_mgm_ctrl___mdc___width 1
-#define reg_eth_rw_mgm_ctrl___mdc___bit 2
-#define reg_eth_rw_mgm_ctrl___phyclk___lsb 3
-#define reg_eth_rw_mgm_ctrl___phyclk___width 1
-#define reg_eth_rw_mgm_ctrl___phyclk___bit 3
-#define reg_eth_rw_mgm_ctrl___txdata___lsb 4
-#define reg_eth_rw_mgm_ctrl___txdata___width 4
-#define reg_eth_rw_mgm_ctrl___txen___lsb 8
-#define reg_eth_rw_mgm_ctrl___txen___width 1
-#define reg_eth_rw_mgm_ctrl___txen___bit 8
-#define reg_eth_rw_mgm_ctrl_offset 40
-
-/* Register r_stat, scope eth, type r */
-#define reg_eth_r_stat___mdio___lsb 0
-#define reg_eth_r_stat___mdio___width 1
-#define reg_eth_r_stat___mdio___bit 0
-#define reg_eth_r_stat___exc_col___lsb 1
-#define reg_eth_r_stat___exc_col___width 1
-#define reg_eth_r_stat___exc_col___bit 1
-#define reg_eth_r_stat___urun___lsb 2
-#define reg_eth_r_stat___urun___width 1
-#define reg_eth_r_stat___urun___bit 2
-#define reg_eth_r_stat___phyclk___lsb 3
-#define reg_eth_r_stat___phyclk___width 1
-#define reg_eth_r_stat___phyclk___bit 3
-#define reg_eth_r_stat___txdata___lsb 4
-#define reg_eth_r_stat___txdata___width 4
-#define reg_eth_r_stat___txen___lsb 8
-#define reg_eth_r_stat___txen___width 1
-#define reg_eth_r_stat___txen___bit 8
-#define reg_eth_r_stat___col___lsb 9
-#define reg_eth_r_stat___col___width 1
-#define reg_eth_r_stat___col___bit 9
-#define reg_eth_r_stat___crs___lsb 10
-#define reg_eth_r_stat___crs___width 1
-#define reg_eth_r_stat___crs___bit 10
-#define reg_eth_r_stat___txclk___lsb 11
-#define reg_eth_r_stat___txclk___width 1
-#define reg_eth_r_stat___txclk___bit 11
-#define reg_eth_r_stat___rxdata___lsb 12
-#define reg_eth_r_stat___rxdata___width 4
-#define reg_eth_r_stat___rxer___lsb 16
-#define reg_eth_r_stat___rxer___width 1
-#define reg_eth_r_stat___rxer___bit 16
-#define reg_eth_r_stat___rxdv___lsb 17
-#define reg_eth_r_stat___rxdv___width 1
-#define reg_eth_r_stat___rxdv___bit 17
-#define reg_eth_r_stat___rxclk___lsb 18
-#define reg_eth_r_stat___rxclk___width 1
-#define reg_eth_r_stat___rxclk___bit 18
-#define reg_eth_r_stat_offset 44
-
-/* Register rs_rec_cnt, scope eth, type rs */
-#define reg_eth_rs_rec_cnt___crc_err___lsb 0
-#define reg_eth_rs_rec_cnt___crc_err___width 8
-#define reg_eth_rs_rec_cnt___align_err___lsb 8
-#define reg_eth_rs_rec_cnt___align_err___width 8
-#define reg_eth_rs_rec_cnt___oversize___lsb 16
-#define reg_eth_rs_rec_cnt___oversize___width 8
-#define reg_eth_rs_rec_cnt___congestion___lsb 24
-#define reg_eth_rs_rec_cnt___congestion___width 8
-#define reg_eth_rs_rec_cnt_offset 48
-
-/* Register r_rec_cnt, scope eth, type r */
-#define reg_eth_r_rec_cnt___crc_err___lsb 0
-#define reg_eth_r_rec_cnt___crc_err___width 8
-#define reg_eth_r_rec_cnt___align_err___lsb 8
-#define reg_eth_r_rec_cnt___align_err___width 8
-#define reg_eth_r_rec_cnt___oversize___lsb 16
-#define reg_eth_r_rec_cnt___oversize___width 8
-#define reg_eth_r_rec_cnt___congestion___lsb 24
-#define reg_eth_r_rec_cnt___congestion___width 8
-#define reg_eth_r_rec_cnt_offset 52
-
-/* Register rs_tr_cnt, scope eth, type rs */
-#define reg_eth_rs_tr_cnt___single_col___lsb 0
-#define reg_eth_rs_tr_cnt___single_col___width 8
-#define reg_eth_rs_tr_cnt___mult_col___lsb 8
-#define reg_eth_rs_tr_cnt___mult_col___width 8
-#define reg_eth_rs_tr_cnt___late_col___lsb 16
-#define reg_eth_rs_tr_cnt___late_col___width 8
-#define reg_eth_rs_tr_cnt___deferred___lsb 24
-#define reg_eth_rs_tr_cnt___deferred___width 8
-#define reg_eth_rs_tr_cnt_offset 56
-
-/* Register r_tr_cnt, scope eth, type r */
-#define reg_eth_r_tr_cnt___single_col___lsb 0
-#define reg_eth_r_tr_cnt___single_col___width 8
-#define reg_eth_r_tr_cnt___mult_col___lsb 8
-#define reg_eth_r_tr_cnt___mult_col___width 8
-#define reg_eth_r_tr_cnt___late_col___lsb 16
-#define reg_eth_r_tr_cnt___late_col___width 8
-#define reg_eth_r_tr_cnt___deferred___lsb 24
-#define reg_eth_r_tr_cnt___deferred___width 8
-#define reg_eth_r_tr_cnt_offset 60
-
-/* Register rs_phy_cnt, scope eth, type rs */
-#define reg_eth_rs_phy_cnt___carrier_loss___lsb 0
-#define reg_eth_rs_phy_cnt___carrier_loss___width 8
-#define reg_eth_rs_phy_cnt___sqe_err___lsb 8
-#define reg_eth_rs_phy_cnt___sqe_err___width 8
-#define reg_eth_rs_phy_cnt_offset 64
-
-/* Register r_phy_cnt, scope eth, type r */
-#define reg_eth_r_phy_cnt___carrier_loss___lsb 0
-#define reg_eth_r_phy_cnt___carrier_loss___width 8
-#define reg_eth_r_phy_cnt___sqe_err___lsb 8
-#define reg_eth_r_phy_cnt___sqe_err___width 8
-#define reg_eth_r_phy_cnt_offset 68
-
-/* Register rw_test_ctrl, scope eth, type rw */
-#define reg_eth_rw_test_ctrl___snmp_inc___lsb 0
-#define reg_eth_rw_test_ctrl___snmp_inc___width 1
-#define reg_eth_rw_test_ctrl___snmp_inc___bit 0
-#define reg_eth_rw_test_ctrl___snmp___lsb 1
-#define reg_eth_rw_test_ctrl___snmp___width 1
-#define reg_eth_rw_test_ctrl___snmp___bit 1
-#define reg_eth_rw_test_ctrl___backoff___lsb 2
-#define reg_eth_rw_test_ctrl___backoff___width 1
-#define reg_eth_rw_test_ctrl___backoff___bit 2
-#define reg_eth_rw_test_ctrl_offset 72
-
-/* Register rw_intr_mask, scope eth, type rw */
-#define reg_eth_rw_intr_mask___crc___lsb 0
-#define reg_eth_rw_intr_mask___crc___width 1
-#define reg_eth_rw_intr_mask___crc___bit 0
-#define reg_eth_rw_intr_mask___align___lsb 1
-#define reg_eth_rw_intr_mask___align___width 1
-#define reg_eth_rw_intr_mask___align___bit 1
-#define reg_eth_rw_intr_mask___oversize___lsb 2
-#define reg_eth_rw_intr_mask___oversize___width 1
-#define reg_eth_rw_intr_mask___oversize___bit 2
-#define reg_eth_rw_intr_mask___congestion___lsb 3
-#define reg_eth_rw_intr_mask___congestion___width 1
-#define reg_eth_rw_intr_mask___congestion___bit 3
-#define reg_eth_rw_intr_mask___single_col___lsb 4
-#define reg_eth_rw_intr_mask___single_col___width 1
-#define reg_eth_rw_intr_mask___single_col___bit 4
-#define reg_eth_rw_intr_mask___mult_col___lsb 5
-#define reg_eth_rw_intr_mask___mult_col___width 1
-#define reg_eth_rw_intr_mask___mult_col___bit 5
-#define reg_eth_rw_intr_mask___late_col___lsb 6
-#define reg_eth_rw_intr_mask___late_col___width 1
-#define reg_eth_rw_intr_mask___late_col___bit 6
-#define reg_eth_rw_intr_mask___deferred___lsb 7
-#define reg_eth_rw_intr_mask___deferred___width 1
-#define reg_eth_rw_intr_mask___deferred___bit 7
-#define reg_eth_rw_intr_mask___carrier_loss___lsb 8
-#define reg_eth_rw_intr_mask___carrier_loss___width 1
-#define reg_eth_rw_intr_mask___carrier_loss___bit 8
-#define reg_eth_rw_intr_mask___sqe_test_err___lsb 9
-#define reg_eth_rw_intr_mask___sqe_test_err___width 1
-#define reg_eth_rw_intr_mask___sqe_test_err___bit 9
-#define reg_eth_rw_intr_mask___orun___lsb 10
-#define reg_eth_rw_intr_mask___orun___width 1
-#define reg_eth_rw_intr_mask___orun___bit 10
-#define reg_eth_rw_intr_mask___urun___lsb 11
-#define reg_eth_rw_intr_mask___urun___width 1
-#define reg_eth_rw_intr_mask___urun___bit 11
-#define reg_eth_rw_intr_mask___excessive_col___lsb 12
-#define reg_eth_rw_intr_mask___excessive_col___width 1
-#define reg_eth_rw_intr_mask___excessive_col___bit 12
-#define reg_eth_rw_intr_mask___mdio___lsb 13
-#define reg_eth_rw_intr_mask___mdio___width 1
-#define reg_eth_rw_intr_mask___mdio___bit 13
-#define reg_eth_rw_intr_mask_offset 76
-
-/* Register rw_ack_intr, scope eth, type rw */
-#define reg_eth_rw_ack_intr___crc___lsb 0
-#define reg_eth_rw_ack_intr___crc___width 1
-#define reg_eth_rw_ack_intr___crc___bit 0
-#define reg_eth_rw_ack_intr___align___lsb 1
-#define reg_eth_rw_ack_intr___align___width 1
-#define reg_eth_rw_ack_intr___align___bit 1
-#define reg_eth_rw_ack_intr___oversize___lsb 2
-#define reg_eth_rw_ack_intr___oversize___width 1
-#define reg_eth_rw_ack_intr___oversize___bit 2
-#define reg_eth_rw_ack_intr___congestion___lsb 3
-#define reg_eth_rw_ack_intr___congestion___width 1
-#define reg_eth_rw_ack_intr___congestion___bit 3
-#define reg_eth_rw_ack_intr___single_col___lsb 4
-#define reg_eth_rw_ack_intr___single_col___width 1
-#define reg_eth_rw_ack_intr___single_col___bit 4
-#define reg_eth_rw_ack_intr___mult_col___lsb 5
-#define reg_eth_rw_ack_intr___mult_col___width 1
-#define reg_eth_rw_ack_intr___mult_col___bit 5
-#define reg_eth_rw_ack_intr___late_col___lsb 6
-#define reg_eth_rw_ack_intr___late_col___width 1
-#define reg_eth_rw_ack_intr___late_col___bit 6
-#define reg_eth_rw_ack_intr___deferred___lsb 7
-#define reg_eth_rw_ack_intr___deferred___width 1
-#define reg_eth_rw_ack_intr___deferred___bit 7
-#define reg_eth_rw_ack_intr___carrier_loss___lsb 8
-#define reg_eth_rw_ack_intr___carrier_loss___width 1
-#define reg_eth_rw_ack_intr___carrier_loss___bit 8
-#define reg_eth_rw_ack_intr___sqe_test_err___lsb 9
-#define reg_eth_rw_ack_intr___sqe_test_err___width 1
-#define reg_eth_rw_ack_intr___sqe_test_err___bit 9
-#define reg_eth_rw_ack_intr___orun___lsb 10
-#define reg_eth_rw_ack_intr___orun___width 1
-#define reg_eth_rw_ack_intr___orun___bit 10
-#define reg_eth_rw_ack_intr___urun___lsb 11
-#define reg_eth_rw_ack_intr___urun___width 1
-#define reg_eth_rw_ack_intr___urun___bit 11
-#define reg_eth_rw_ack_intr___excessive_col___lsb 12
-#define reg_eth_rw_ack_intr___excessive_col___width 1
-#define reg_eth_rw_ack_intr___excessive_col___bit 12
-#define reg_eth_rw_ack_intr___mdio___lsb 13
-#define reg_eth_rw_ack_intr___mdio___width 1
-#define reg_eth_rw_ack_intr___mdio___bit 13
-#define reg_eth_rw_ack_intr_offset 80
-
-/* Register r_intr, scope eth, type r */
-#define reg_eth_r_intr___crc___lsb 0
-#define reg_eth_r_intr___crc___width 1
-#define reg_eth_r_intr___crc___bit 0
-#define reg_eth_r_intr___align___lsb 1
-#define reg_eth_r_intr___align___width 1
-#define reg_eth_r_intr___align___bit 1
-#define reg_eth_r_intr___oversize___lsb 2
-#define reg_eth_r_intr___oversize___width 1
-#define reg_eth_r_intr___oversize___bit 2
-#define reg_eth_r_intr___congestion___lsb 3
-#define reg_eth_r_intr___congestion___width 1
-#define reg_eth_r_intr___congestion___bit 3
-#define reg_eth_r_intr___single_col___lsb 4
-#define reg_eth_r_intr___single_col___width 1
-#define reg_eth_r_intr___single_col___bit 4
-#define reg_eth_r_intr___mult_col___lsb 5
-#define reg_eth_r_intr___mult_col___width 1
-#define reg_eth_r_intr___mult_col___bit 5
-#define reg_eth_r_intr___late_col___lsb 6
-#define reg_eth_r_intr___late_col___width 1
-#define reg_eth_r_intr___late_col___bit 6
-#define reg_eth_r_intr___deferred___lsb 7
-#define reg_eth_r_intr___deferred___width 1
-#define reg_eth_r_intr___deferred___bit 7
-#define reg_eth_r_intr___carrier_loss___lsb 8
-#define reg_eth_r_intr___carrier_loss___width 1
-#define reg_eth_r_intr___carrier_loss___bit 8
-#define reg_eth_r_intr___sqe_test_err___lsb 9
-#define reg_eth_r_intr___sqe_test_err___width 1
-#define reg_eth_r_intr___sqe_test_err___bit 9
-#define reg_eth_r_intr___orun___lsb 10
-#define reg_eth_r_intr___orun___width 1
-#define reg_eth_r_intr___orun___bit 10
-#define reg_eth_r_intr___urun___lsb 11
-#define reg_eth_r_intr___urun___width 1
-#define reg_eth_r_intr___urun___bit 11
-#define reg_eth_r_intr___excessive_col___lsb 12
-#define reg_eth_r_intr___excessive_col___width 1
-#define reg_eth_r_intr___excessive_col___bit 12
-#define reg_eth_r_intr___mdio___lsb 13
-#define reg_eth_r_intr___mdio___width 1
-#define reg_eth_r_intr___mdio___bit 13
-#define reg_eth_r_intr_offset 84
-
-/* Register r_masked_intr, scope eth, type r */
-#define reg_eth_r_masked_intr___crc___lsb 0
-#define reg_eth_r_masked_intr___crc___width 1
-#define reg_eth_r_masked_intr___crc___bit 0
-#define reg_eth_r_masked_intr___align___lsb 1
-#define reg_eth_r_masked_intr___align___width 1
-#define reg_eth_r_masked_intr___align___bit 1
-#define reg_eth_r_masked_intr___oversize___lsb 2
-#define reg_eth_r_masked_intr___oversize___width 1
-#define reg_eth_r_masked_intr___oversize___bit 2
-#define reg_eth_r_masked_intr___congestion___lsb 3
-#define reg_eth_r_masked_intr___congestion___width 1
-#define reg_eth_r_masked_intr___congestion___bit 3
-#define reg_eth_r_masked_intr___single_col___lsb 4
-#define reg_eth_r_masked_intr___single_col___width 1
-#define reg_eth_r_masked_intr___single_col___bit 4
-#define reg_eth_r_masked_intr___mult_col___lsb 5
-#define reg_eth_r_masked_intr___mult_col___width 1
-#define reg_eth_r_masked_intr___mult_col___bit 5
-#define reg_eth_r_masked_intr___late_col___lsb 6
-#define reg_eth_r_masked_intr___late_col___width 1
-#define reg_eth_r_masked_intr___late_col___bit 6
-#define reg_eth_r_masked_intr___deferred___lsb 7
-#define reg_eth_r_masked_intr___deferred___width 1
-#define reg_eth_r_masked_intr___deferred___bit 7
-#define reg_eth_r_masked_intr___carrier_loss___lsb 8
-#define reg_eth_r_masked_intr___carrier_loss___width 1
-#define reg_eth_r_masked_intr___carrier_loss___bit 8
-#define reg_eth_r_masked_intr___sqe_test_err___lsb 9
-#define reg_eth_r_masked_intr___sqe_test_err___width 1
-#define reg_eth_r_masked_intr___sqe_test_err___bit 9
-#define reg_eth_r_masked_intr___orun___lsb 10
-#define reg_eth_r_masked_intr___orun___width 1
-#define reg_eth_r_masked_intr___orun___bit 10
-#define reg_eth_r_masked_intr___urun___lsb 11
-#define reg_eth_r_masked_intr___urun___width 1
-#define reg_eth_r_masked_intr___urun___bit 11
-#define reg_eth_r_masked_intr___excessive_col___lsb 12
-#define reg_eth_r_masked_intr___excessive_col___width 1
-#define reg_eth_r_masked_intr___excessive_col___bit 12
-#define reg_eth_r_masked_intr___mdio___lsb 13
-#define reg_eth_r_masked_intr___mdio___width 1
-#define reg_eth_r_masked_intr___mdio___bit 13
-#define reg_eth_r_masked_intr_offset 88
-
-
-/* Constants */
-#define regk_eth_discard                          0x00000000
-#define regk_eth_ether                            0x00000000
-#define regk_eth_full                             0x00000001
-#define regk_eth_half                             0x00000000
-#define regk_eth_hsh                              0x00000001
-#define regk_eth_mii                              0x00000001
-#define regk_eth_mii_clk                          0x00000000
-#define regk_eth_mii_rec                          0x00000002
-#define regk_eth_no                               0x00000000
-#define regk_eth_rec                              0x00000001
-#define regk_eth_rw_ga_hi_default                 0x00000000
-#define regk_eth_rw_ga_lo_default                 0x00000000
-#define regk_eth_rw_gen_ctrl_default              0x00000000
-#define regk_eth_rw_intr_mask_default             0x00000000
-#define regk_eth_rw_ma0_hi_default                0x00000000
-#define regk_eth_rw_ma0_lo_default                0x00000000
-#define regk_eth_rw_ma1_hi_default                0x00000000
-#define regk_eth_rw_ma1_lo_default                0x00000000
-#define regk_eth_rw_mgm_ctrl_default              0x00000000
-#define regk_eth_rw_test_ctrl_default             0x00000000
-#define regk_eth_size1518                         0x00000000
-#define regk_eth_size1522                         0x00000001
-#define regk_eth_yes                              0x00000001
-#endif /* __eth_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h
deleted file mode 100644
index 35356bc08629..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h
+++ /dev/null
@@ -1,276 +0,0 @@
-#ifndef __gio_defs_asm_h
-#define __gio_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/gio/rtl/gio_regs.r
- *     id:           gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
- *     last modfied: Mon Apr 11 16:07:47 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r
- *      id: $Id: gio_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_pa_dout, scope gio, type rw */
-#define reg_gio_rw_pa_dout___data___lsb 0
-#define reg_gio_rw_pa_dout___data___width 8
-#define reg_gio_rw_pa_dout_offset 0
-
-/* Register r_pa_din, scope gio, type r */
-#define reg_gio_r_pa_din___data___lsb 0
-#define reg_gio_r_pa_din___data___width 8
-#define reg_gio_r_pa_din_offset 4
-
-/* Register rw_pa_oe, scope gio, type rw */
-#define reg_gio_rw_pa_oe___oe___lsb 0
-#define reg_gio_rw_pa_oe___oe___width 8
-#define reg_gio_rw_pa_oe_offset 8
-
-/* Register rw_intr_cfg, scope gio, type rw */
-#define reg_gio_rw_intr_cfg___pa0___lsb 0
-#define reg_gio_rw_intr_cfg___pa0___width 3
-#define reg_gio_rw_intr_cfg___pa1___lsb 3
-#define reg_gio_rw_intr_cfg___pa1___width 3
-#define reg_gio_rw_intr_cfg___pa2___lsb 6
-#define reg_gio_rw_intr_cfg___pa2___width 3
-#define reg_gio_rw_intr_cfg___pa3___lsb 9
-#define reg_gio_rw_intr_cfg___pa3___width 3
-#define reg_gio_rw_intr_cfg___pa4___lsb 12
-#define reg_gio_rw_intr_cfg___pa4___width 3
-#define reg_gio_rw_intr_cfg___pa5___lsb 15
-#define reg_gio_rw_intr_cfg___pa5___width 3
-#define reg_gio_rw_intr_cfg___pa6___lsb 18
-#define reg_gio_rw_intr_cfg___pa6___width 3
-#define reg_gio_rw_intr_cfg___pa7___lsb 21
-#define reg_gio_rw_intr_cfg___pa7___width 3
-#define reg_gio_rw_intr_cfg_offset 12
-
-/* Register rw_intr_mask, scope gio, type rw */
-#define reg_gio_rw_intr_mask___pa0___lsb 0
-#define reg_gio_rw_intr_mask___pa0___width 1
-#define reg_gio_rw_intr_mask___pa0___bit 0
-#define reg_gio_rw_intr_mask___pa1___lsb 1
-#define reg_gio_rw_intr_mask___pa1___width 1
-#define reg_gio_rw_intr_mask___pa1___bit 1
-#define reg_gio_rw_intr_mask___pa2___lsb 2
-#define reg_gio_rw_intr_mask___pa2___width 1
-#define reg_gio_rw_intr_mask___pa2___bit 2
-#define reg_gio_rw_intr_mask___pa3___lsb 3
-#define reg_gio_rw_intr_mask___pa3___width 1
-#define reg_gio_rw_intr_mask___pa3___bit 3
-#define reg_gio_rw_intr_mask___pa4___lsb 4
-#define reg_gio_rw_intr_mask___pa4___width 1
-#define reg_gio_rw_intr_mask___pa4___bit 4
-#define reg_gio_rw_intr_mask___pa5___lsb 5
-#define reg_gio_rw_intr_mask___pa5___width 1
-#define reg_gio_rw_intr_mask___pa5___bit 5
-#define reg_gio_rw_intr_mask___pa6___lsb 6
-#define reg_gio_rw_intr_mask___pa6___width 1
-#define reg_gio_rw_intr_mask___pa6___bit 6
-#define reg_gio_rw_intr_mask___pa7___lsb 7
-#define reg_gio_rw_intr_mask___pa7___width 1
-#define reg_gio_rw_intr_mask___pa7___bit 7
-#define reg_gio_rw_intr_mask_offset 16
-
-/* Register rw_ack_intr, scope gio, type rw */
-#define reg_gio_rw_ack_intr___pa0___lsb 0
-#define reg_gio_rw_ack_intr___pa0___width 1
-#define reg_gio_rw_ack_intr___pa0___bit 0
-#define reg_gio_rw_ack_intr___pa1___lsb 1
-#define reg_gio_rw_ack_intr___pa1___width 1
-#define reg_gio_rw_ack_intr___pa1___bit 1
-#define reg_gio_rw_ack_intr___pa2___lsb 2
-#define reg_gio_rw_ack_intr___pa2___width 1
-#define reg_gio_rw_ack_intr___pa2___bit 2
-#define reg_gio_rw_ack_intr___pa3___lsb 3
-#define reg_gio_rw_ack_intr___pa3___width 1
-#define reg_gio_rw_ack_intr___pa3___bit 3
-#define reg_gio_rw_ack_intr___pa4___lsb 4
-#define reg_gio_rw_ack_intr___pa4___width 1
-#define reg_gio_rw_ack_intr___pa4___bit 4
-#define reg_gio_rw_ack_intr___pa5___lsb 5
-#define reg_gio_rw_ack_intr___pa5___width 1
-#define reg_gio_rw_ack_intr___pa5___bit 5
-#define reg_gio_rw_ack_intr___pa6___lsb 6
-#define reg_gio_rw_ack_intr___pa6___width 1
-#define reg_gio_rw_ack_intr___pa6___bit 6
-#define reg_gio_rw_ack_intr___pa7___lsb 7
-#define reg_gio_rw_ack_intr___pa7___width 1
-#define reg_gio_rw_ack_intr___pa7___bit 7
-#define reg_gio_rw_ack_intr_offset 20
-
-/* Register r_intr, scope gio, type r */
-#define reg_gio_r_intr___pa0___lsb 0
-#define reg_gio_r_intr___pa0___width 1
-#define reg_gio_r_intr___pa0___bit 0
-#define reg_gio_r_intr___pa1___lsb 1
-#define reg_gio_r_intr___pa1___width 1
-#define reg_gio_r_intr___pa1___bit 1
-#define reg_gio_r_intr___pa2___lsb 2
-#define reg_gio_r_intr___pa2___width 1
-#define reg_gio_r_intr___pa2___bit 2
-#define reg_gio_r_intr___pa3___lsb 3
-#define reg_gio_r_intr___pa3___width 1
-#define reg_gio_r_intr___pa3___bit 3
-#define reg_gio_r_intr___pa4___lsb 4
-#define reg_gio_r_intr___pa4___width 1
-#define reg_gio_r_intr___pa4___bit 4
-#define reg_gio_r_intr___pa5___lsb 5
-#define reg_gio_r_intr___pa5___width 1
-#define reg_gio_r_intr___pa5___bit 5
-#define reg_gio_r_intr___pa6___lsb 6
-#define reg_gio_r_intr___pa6___width 1
-#define reg_gio_r_intr___pa6___bit 6
-#define reg_gio_r_intr___pa7___lsb 7
-#define reg_gio_r_intr___pa7___width 1
-#define reg_gio_r_intr___pa7___bit 7
-#define reg_gio_r_intr_offset 24
-
-/* Register r_masked_intr, scope gio, type r */
-#define reg_gio_r_masked_intr___pa0___lsb 0
-#define reg_gio_r_masked_intr___pa0___width 1
-#define reg_gio_r_masked_intr___pa0___bit 0
-#define reg_gio_r_masked_intr___pa1___lsb 1
-#define reg_gio_r_masked_intr___pa1___width 1
-#define reg_gio_r_masked_intr___pa1___bit 1
-#define reg_gio_r_masked_intr___pa2___lsb 2
-#define reg_gio_r_masked_intr___pa2___width 1
-#define reg_gio_r_masked_intr___pa2___bit 2
-#define reg_gio_r_masked_intr___pa3___lsb 3
-#define reg_gio_r_masked_intr___pa3___width 1
-#define reg_gio_r_masked_intr___pa3___bit 3
-#define reg_gio_r_masked_intr___pa4___lsb 4
-#define reg_gio_r_masked_intr___pa4___width 1
-#define reg_gio_r_masked_intr___pa4___bit 4
-#define reg_gio_r_masked_intr___pa5___lsb 5
-#define reg_gio_r_masked_intr___pa5___width 1
-#define reg_gio_r_masked_intr___pa5___bit 5
-#define reg_gio_r_masked_intr___pa6___lsb 6
-#define reg_gio_r_masked_intr___pa6___width 1
-#define reg_gio_r_masked_intr___pa6___bit 6
-#define reg_gio_r_masked_intr___pa7___lsb 7
-#define reg_gio_r_masked_intr___pa7___width 1
-#define reg_gio_r_masked_intr___pa7___bit 7
-#define reg_gio_r_masked_intr_offset 28
-
-/* Register rw_pb_dout, scope gio, type rw */
-#define reg_gio_rw_pb_dout___data___lsb 0
-#define reg_gio_rw_pb_dout___data___width 18
-#define reg_gio_rw_pb_dout_offset 32
-
-/* Register r_pb_din, scope gio, type r */
-#define reg_gio_r_pb_din___data___lsb 0
-#define reg_gio_r_pb_din___data___width 18
-#define reg_gio_r_pb_din_offset 36
-
-/* Register rw_pb_oe, scope gio, type rw */
-#define reg_gio_rw_pb_oe___oe___lsb 0
-#define reg_gio_rw_pb_oe___oe___width 18
-#define reg_gio_rw_pb_oe_offset 40
-
-/* Register rw_pc_dout, scope gio, type rw */
-#define reg_gio_rw_pc_dout___data___lsb 0
-#define reg_gio_rw_pc_dout___data___width 18
-#define reg_gio_rw_pc_dout_offset 48
-
-/* Register r_pc_din, scope gio, type r */
-#define reg_gio_r_pc_din___data___lsb 0
-#define reg_gio_r_pc_din___data___width 18
-#define reg_gio_r_pc_din_offset 52
-
-/* Register rw_pc_oe, scope gio, type rw */
-#define reg_gio_rw_pc_oe___oe___lsb 0
-#define reg_gio_rw_pc_oe___oe___width 18
-#define reg_gio_rw_pc_oe_offset 56
-
-/* Register rw_pd_dout, scope gio, type rw */
-#define reg_gio_rw_pd_dout___data___lsb 0
-#define reg_gio_rw_pd_dout___data___width 18
-#define reg_gio_rw_pd_dout_offset 64
-
-/* Register r_pd_din, scope gio, type r */
-#define reg_gio_r_pd_din___data___lsb 0
-#define reg_gio_r_pd_din___data___width 18
-#define reg_gio_r_pd_din_offset 68
-
-/* Register rw_pd_oe, scope gio, type rw */
-#define reg_gio_rw_pd_oe___oe___lsb 0
-#define reg_gio_rw_pd_oe___oe___width 18
-#define reg_gio_rw_pd_oe_offset 72
-
-/* Register rw_pe_dout, scope gio, type rw */
-#define reg_gio_rw_pe_dout___data___lsb 0
-#define reg_gio_rw_pe_dout___data___width 18
-#define reg_gio_rw_pe_dout_offset 80
-
-/* Register r_pe_din, scope gio, type r */
-#define reg_gio_r_pe_din___data___lsb 0
-#define reg_gio_r_pe_din___data___width 18
-#define reg_gio_r_pe_din_offset 84
-
-/* Register rw_pe_oe, scope gio, type rw */
-#define reg_gio_rw_pe_oe___oe___lsb 0
-#define reg_gio_rw_pe_oe___oe___width 18
-#define reg_gio_rw_pe_oe_offset 88
-
-
-/* Constants */
-#define regk_gio_anyedge                          0x00000007
-#define regk_gio_hi                               0x00000001
-#define regk_gio_lo                               0x00000002
-#define regk_gio_negedge                          0x00000006
-#define regk_gio_no                               0x00000000
-#define regk_gio_off                              0x00000000
-#define regk_gio_posedge                          0x00000005
-#define regk_gio_rw_intr_cfg_default              0x00000000
-#define regk_gio_rw_intr_mask_default             0x00000000
-#define regk_gio_rw_pa_oe_default                 0x00000000
-#define regk_gio_rw_pb_oe_default                 0x00000000
-#define regk_gio_rw_pc_oe_default                 0x00000000
-#define regk_gio_rw_pd_oe_default                 0x00000000
-#define regk_gio_rw_pe_oe_default                 0x00000000
-#define regk_gio_set                              0x00000003
-#define regk_gio_yes                              0x00000001
-#endif /* __gio_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h b/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h
deleted file mode 100644
index c8315905c571..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
- from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
-version . */
-
-#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
-#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
-#define MEMARB_INTR_VECT	0x31
-#define GEN_IO_INTR_VECT	0x32
-#define IOP0_INTR_VECT	0x33
-#define IOP1_INTR_VECT	0x34
-#define IOP2_INTR_VECT	0x35
-#define IOP3_INTR_VECT	0x36
-#define DMA0_INTR_VECT	0x37
-#define DMA1_INTR_VECT	0x38
-#define DMA2_INTR_VECT	0x39
-#define DMA3_INTR_VECT	0x3a
-#define DMA4_INTR_VECT	0x3b
-#define DMA5_INTR_VECT	0x3c
-#define DMA6_INTR_VECT	0x3d
-#define DMA7_INTR_VECT	0x3e
-#define DMA8_INTR_VECT	0x3f
-#define DMA9_INTR_VECT	0x40
-#define ATA_INTR_VECT	0x41
-#define SSER0_INTR_VECT	0x42
-#define SSER1_INTR_VECT	0x43
-#define SER0_INTR_VECT	0x44
-#define SER1_INTR_VECT	0x45
-#define SER2_INTR_VECT	0x46
-#define SER3_INTR_VECT	0x47
-#define P21_INTR_VECT	0x48
-#define ETH0_INTR_VECT	0x49
-#define ETH1_INTR_VECT	0x4a
-#define TIMER_INTR_VECT	0x4b
-#define BIF_ARB_INTR_VECT	0x4c
-#define BIF_DMA_INTR_VECT	0x4d
-#define EXT_INTR_VECT	0x4e
-
-#endif
diff --git a/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h
deleted file mode 100644
index 6df2a433b02d..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h
+++ /dev/null
@@ -1,355 +0,0 @@
-#ifndef __intr_vect_defs_asm_h
-#define __intr_vect_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/intr_vect/rtl/guinness/ivmask.config.r
- *     id:           ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
- *     last modfied: Mon Apr 11 16:08:03 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
- *      id: $Id: intr_vect_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_mask, scope intr_vect, type rw */
-#define reg_intr_vect_rw_mask___memarb___lsb 0
-#define reg_intr_vect_rw_mask___memarb___width 1
-#define reg_intr_vect_rw_mask___memarb___bit 0
-#define reg_intr_vect_rw_mask___gen_io___lsb 1
-#define reg_intr_vect_rw_mask___gen_io___width 1
-#define reg_intr_vect_rw_mask___gen_io___bit 1
-#define reg_intr_vect_rw_mask___iop0___lsb 2
-#define reg_intr_vect_rw_mask___iop0___width 1
-#define reg_intr_vect_rw_mask___iop0___bit 2
-#define reg_intr_vect_rw_mask___iop1___lsb 3
-#define reg_intr_vect_rw_mask___iop1___width 1
-#define reg_intr_vect_rw_mask___iop1___bit 3
-#define reg_intr_vect_rw_mask___iop2___lsb 4
-#define reg_intr_vect_rw_mask___iop2___width 1
-#define reg_intr_vect_rw_mask___iop2___bit 4
-#define reg_intr_vect_rw_mask___iop3___lsb 5
-#define reg_intr_vect_rw_mask___iop3___width 1
-#define reg_intr_vect_rw_mask___iop3___bit 5
-#define reg_intr_vect_rw_mask___dma0___lsb 6
-#define reg_intr_vect_rw_mask___dma0___width 1
-#define reg_intr_vect_rw_mask___dma0___bit 6
-#define reg_intr_vect_rw_mask___dma1___lsb 7
-#define reg_intr_vect_rw_mask___dma1___width 1
-#define reg_intr_vect_rw_mask___dma1___bit 7
-#define reg_intr_vect_rw_mask___dma2___lsb 8
-#define reg_intr_vect_rw_mask___dma2___width 1
-#define reg_intr_vect_rw_mask___dma2___bit 8
-#define reg_intr_vect_rw_mask___dma3___lsb 9
-#define reg_intr_vect_rw_mask___dma3___width 1
-#define reg_intr_vect_rw_mask___dma3___bit 9
-#define reg_intr_vect_rw_mask___dma4___lsb 10
-#define reg_intr_vect_rw_mask___dma4___width 1
-#define reg_intr_vect_rw_mask___dma4___bit 10
-#define reg_intr_vect_rw_mask___dma5___lsb 11
-#define reg_intr_vect_rw_mask___dma5___width 1
-#define reg_intr_vect_rw_mask___dma5___bit 11
-#define reg_intr_vect_rw_mask___dma6___lsb 12
-#define reg_intr_vect_rw_mask___dma6___width 1
-#define reg_intr_vect_rw_mask___dma6___bit 12
-#define reg_intr_vect_rw_mask___dma7___lsb 13
-#define reg_intr_vect_rw_mask___dma7___width 1
-#define reg_intr_vect_rw_mask___dma7___bit 13
-#define reg_intr_vect_rw_mask___dma8___lsb 14
-#define reg_intr_vect_rw_mask___dma8___width 1
-#define reg_intr_vect_rw_mask___dma8___bit 14
-#define reg_intr_vect_rw_mask___dma9___lsb 15
-#define reg_intr_vect_rw_mask___dma9___width 1
-#define reg_intr_vect_rw_mask___dma9___bit 15
-#define reg_intr_vect_rw_mask___ata___lsb 16
-#define reg_intr_vect_rw_mask___ata___width 1
-#define reg_intr_vect_rw_mask___ata___bit 16
-#define reg_intr_vect_rw_mask___sser0___lsb 17
-#define reg_intr_vect_rw_mask___sser0___width 1
-#define reg_intr_vect_rw_mask___sser0___bit 17
-#define reg_intr_vect_rw_mask___sser1___lsb 18
-#define reg_intr_vect_rw_mask___sser1___width 1
-#define reg_intr_vect_rw_mask___sser1___bit 18
-#define reg_intr_vect_rw_mask___ser0___lsb 19
-#define reg_intr_vect_rw_mask___ser0___width 1
-#define reg_intr_vect_rw_mask___ser0___bit 19
-#define reg_intr_vect_rw_mask___ser1___lsb 20
-#define reg_intr_vect_rw_mask___ser1___width 1
-#define reg_intr_vect_rw_mask___ser1___bit 20
-#define reg_intr_vect_rw_mask___ser2___lsb 21
-#define reg_intr_vect_rw_mask___ser2___width 1
-#define reg_intr_vect_rw_mask___ser2___bit 21
-#define reg_intr_vect_rw_mask___ser3___lsb 22
-#define reg_intr_vect_rw_mask___ser3___width 1
-#define reg_intr_vect_rw_mask___ser3___bit 22
-#define reg_intr_vect_rw_mask___p21___lsb 23
-#define reg_intr_vect_rw_mask___p21___width 1
-#define reg_intr_vect_rw_mask___p21___bit 23
-#define reg_intr_vect_rw_mask___eth0___lsb 24
-#define reg_intr_vect_rw_mask___eth0___width 1
-#define reg_intr_vect_rw_mask___eth0___bit 24
-#define reg_intr_vect_rw_mask___eth1___lsb 25
-#define reg_intr_vect_rw_mask___eth1___width 1
-#define reg_intr_vect_rw_mask___eth1___bit 25
-#define reg_intr_vect_rw_mask___timer___lsb 26
-#define reg_intr_vect_rw_mask___timer___width 1
-#define reg_intr_vect_rw_mask___timer___bit 26
-#define reg_intr_vect_rw_mask___bif_arb___lsb 27
-#define reg_intr_vect_rw_mask___bif_arb___width 1
-#define reg_intr_vect_rw_mask___bif_arb___bit 27
-#define reg_intr_vect_rw_mask___bif_dma___lsb 28
-#define reg_intr_vect_rw_mask___bif_dma___width 1
-#define reg_intr_vect_rw_mask___bif_dma___bit 28
-#define reg_intr_vect_rw_mask___ext___lsb 29
-#define reg_intr_vect_rw_mask___ext___width 1
-#define reg_intr_vect_rw_mask___ext___bit 29
-#define reg_intr_vect_rw_mask_offset 0
-
-/* Register r_vect, scope intr_vect, type r */
-#define reg_intr_vect_r_vect___memarb___lsb 0
-#define reg_intr_vect_r_vect___memarb___width 1
-#define reg_intr_vect_r_vect___memarb___bit 0
-#define reg_intr_vect_r_vect___gen_io___lsb 1
-#define reg_intr_vect_r_vect___gen_io___width 1
-#define reg_intr_vect_r_vect___gen_io___bit 1
-#define reg_intr_vect_r_vect___iop0___lsb 2
-#define reg_intr_vect_r_vect___iop0___width 1
-#define reg_intr_vect_r_vect___iop0___bit 2
-#define reg_intr_vect_r_vect___iop1___lsb 3
-#define reg_intr_vect_r_vect___iop1___width 1
-#define reg_intr_vect_r_vect___iop1___bit 3
-#define reg_intr_vect_r_vect___iop2___lsb 4
-#define reg_intr_vect_r_vect___iop2___width 1
-#define reg_intr_vect_r_vect___iop2___bit 4
-#define reg_intr_vect_r_vect___iop3___lsb 5
-#define reg_intr_vect_r_vect___iop3___width 1
-#define reg_intr_vect_r_vect___iop3___bit 5
-#define reg_intr_vect_r_vect___dma0___lsb 6
-#define reg_intr_vect_r_vect___dma0___width 1
-#define reg_intr_vect_r_vect___dma0___bit 6
-#define reg_intr_vect_r_vect___dma1___lsb 7
-#define reg_intr_vect_r_vect___dma1___width 1
-#define reg_intr_vect_r_vect___dma1___bit 7
-#define reg_intr_vect_r_vect___dma2___lsb 8
-#define reg_intr_vect_r_vect___dma2___width 1
-#define reg_intr_vect_r_vect___dma2___bit 8
-#define reg_intr_vect_r_vect___dma3___lsb 9
-#define reg_intr_vect_r_vect___dma3___width 1
-#define reg_intr_vect_r_vect___dma3___bit 9
-#define reg_intr_vect_r_vect___dma4___lsb 10
-#define reg_intr_vect_r_vect___dma4___width 1
-#define reg_intr_vect_r_vect___dma4___bit 10
-#define reg_intr_vect_r_vect___dma5___lsb 11
-#define reg_intr_vect_r_vect___dma5___width 1
-#define reg_intr_vect_r_vect___dma5___bit 11
-#define reg_intr_vect_r_vect___dma6___lsb 12
-#define reg_intr_vect_r_vect___dma6___width 1
-#define reg_intr_vect_r_vect___dma6___bit 12
-#define reg_intr_vect_r_vect___dma7___lsb 13
-#define reg_intr_vect_r_vect___dma7___width 1
-#define reg_intr_vect_r_vect___dma7___bit 13
-#define reg_intr_vect_r_vect___dma8___lsb 14
-#define reg_intr_vect_r_vect___dma8___width 1
-#define reg_intr_vect_r_vect___dma8___bit 14
-#define reg_intr_vect_r_vect___dma9___lsb 15
-#define reg_intr_vect_r_vect___dma9___width 1
-#define reg_intr_vect_r_vect___dma9___bit 15
-#define reg_intr_vect_r_vect___ata___lsb 16
-#define reg_intr_vect_r_vect___ata___width 1
-#define reg_intr_vect_r_vect___ata___bit 16
-#define reg_intr_vect_r_vect___sser0___lsb 17
-#define reg_intr_vect_r_vect___sser0___width 1
-#define reg_intr_vect_r_vect___sser0___bit 17
-#define reg_intr_vect_r_vect___sser1___lsb 18
-#define reg_intr_vect_r_vect___sser1___width 1
-#define reg_intr_vect_r_vect___sser1___bit 18
-#define reg_intr_vect_r_vect___ser0___lsb 19
-#define reg_intr_vect_r_vect___ser0___width 1
-#define reg_intr_vect_r_vect___ser0___bit 19
-#define reg_intr_vect_r_vect___ser1___lsb 20
-#define reg_intr_vect_r_vect___ser1___width 1
-#define reg_intr_vect_r_vect___ser1___bit 20
-#define reg_intr_vect_r_vect___ser2___lsb 21
-#define reg_intr_vect_r_vect___ser2___width 1
-#define reg_intr_vect_r_vect___ser2___bit 21
-#define reg_intr_vect_r_vect___ser3___lsb 22
-#define reg_intr_vect_r_vect___ser3___width 1
-#define reg_intr_vect_r_vect___ser3___bit 22
-#define reg_intr_vect_r_vect___p21___lsb 23
-#define reg_intr_vect_r_vect___p21___width 1
-#define reg_intr_vect_r_vect___p21___bit 23
-#define reg_intr_vect_r_vect___eth0___lsb 24
-#define reg_intr_vect_r_vect___eth0___width 1
-#define reg_intr_vect_r_vect___eth0___bit 24
-#define reg_intr_vect_r_vect___eth1___lsb 25
-#define reg_intr_vect_r_vect___eth1___width 1
-#define reg_intr_vect_r_vect___eth1___bit 25
-#define reg_intr_vect_r_vect___timer___lsb 26
-#define reg_intr_vect_r_vect___timer___width 1
-#define reg_intr_vect_r_vect___timer___bit 26
-#define reg_intr_vect_r_vect___bif_arb___lsb 27
-#define reg_intr_vect_r_vect___bif_arb___width 1
-#define reg_intr_vect_r_vect___bif_arb___bit 27
-#define reg_intr_vect_r_vect___bif_dma___lsb 28
-#define reg_intr_vect_r_vect___bif_dma___width 1
-#define reg_intr_vect_r_vect___bif_dma___bit 28
-#define reg_intr_vect_r_vect___ext___lsb 29
-#define reg_intr_vect_r_vect___ext___width 1
-#define reg_intr_vect_r_vect___ext___bit 29
-#define reg_intr_vect_r_vect_offset 4
-
-/* Register r_masked_vect, scope intr_vect, type r */
-#define reg_intr_vect_r_masked_vect___memarb___lsb 0
-#define reg_intr_vect_r_masked_vect___memarb___width 1
-#define reg_intr_vect_r_masked_vect___memarb___bit 0
-#define reg_intr_vect_r_masked_vect___gen_io___lsb 1
-#define reg_intr_vect_r_masked_vect___gen_io___width 1
-#define reg_intr_vect_r_masked_vect___gen_io___bit 1
-#define reg_intr_vect_r_masked_vect___iop0___lsb 2
-#define reg_intr_vect_r_masked_vect___iop0___width 1
-#define reg_intr_vect_r_masked_vect___iop0___bit 2
-#define reg_intr_vect_r_masked_vect___iop1___lsb 3
-#define reg_intr_vect_r_masked_vect___iop1___width 1
-#define reg_intr_vect_r_masked_vect___iop1___bit 3
-#define reg_intr_vect_r_masked_vect___iop2___lsb 4
-#define reg_intr_vect_r_masked_vect___iop2___width 1
-#define reg_intr_vect_r_masked_vect___iop2___bit 4
-#define reg_intr_vect_r_masked_vect___iop3___lsb 5
-#define reg_intr_vect_r_masked_vect___iop3___width 1
-#define reg_intr_vect_r_masked_vect___iop3___bit 5
-#define reg_intr_vect_r_masked_vect___dma0___lsb 6
-#define reg_intr_vect_r_masked_vect___dma0___width 1
-#define reg_intr_vect_r_masked_vect___dma0___bit 6
-#define reg_intr_vect_r_masked_vect___dma1___lsb 7
-#define reg_intr_vect_r_masked_vect___dma1___width 1
-#define reg_intr_vect_r_masked_vect___dma1___bit 7
-#define reg_intr_vect_r_masked_vect___dma2___lsb 8
-#define reg_intr_vect_r_masked_vect___dma2___width 1
-#define reg_intr_vect_r_masked_vect___dma2___bit 8
-#define reg_intr_vect_r_masked_vect___dma3___lsb 9
-#define reg_intr_vect_r_masked_vect___dma3___width 1
-#define reg_intr_vect_r_masked_vect___dma3___bit 9
-#define reg_intr_vect_r_masked_vect___dma4___lsb 10
-#define reg_intr_vect_r_masked_vect___dma4___width 1
-#define reg_intr_vect_r_masked_vect___dma4___bit 10
-#define reg_intr_vect_r_masked_vect___dma5___lsb 11
-#define reg_intr_vect_r_masked_vect___dma5___width 1
-#define reg_intr_vect_r_masked_vect___dma5___bit 11
-#define reg_intr_vect_r_masked_vect___dma6___lsb 12
-#define reg_intr_vect_r_masked_vect___dma6___width 1
-#define reg_intr_vect_r_masked_vect___dma6___bit 12
-#define reg_intr_vect_r_masked_vect___dma7___lsb 13
-#define reg_intr_vect_r_masked_vect___dma7___width 1
-#define reg_intr_vect_r_masked_vect___dma7___bit 13
-#define reg_intr_vect_r_masked_vect___dma8___lsb 14
-#define reg_intr_vect_r_masked_vect___dma8___width 1
-#define reg_intr_vect_r_masked_vect___dma8___bit 14
-#define reg_intr_vect_r_masked_vect___dma9___lsb 15
-#define reg_intr_vect_r_masked_vect___dma9___width 1
-#define reg_intr_vect_r_masked_vect___dma9___bit 15
-#define reg_intr_vect_r_masked_vect___ata___lsb 16
-#define reg_intr_vect_r_masked_vect___ata___width 1
-#define reg_intr_vect_r_masked_vect___ata___bit 16
-#define reg_intr_vect_r_masked_vect___sser0___lsb 17
-#define reg_intr_vect_r_masked_vect___sser0___width 1
-#define reg_intr_vect_r_masked_vect___sser0___bit 17
-#define reg_intr_vect_r_masked_vect___sser1___lsb 18
-#define reg_intr_vect_r_masked_vect___sser1___width 1
-#define reg_intr_vect_r_masked_vect___sser1___bit 18
-#define reg_intr_vect_r_masked_vect___ser0___lsb 19
-#define reg_intr_vect_r_masked_vect___ser0___width 1
-#define reg_intr_vect_r_masked_vect___ser0___bit 19
-#define reg_intr_vect_r_masked_vect___ser1___lsb 20
-#define reg_intr_vect_r_masked_vect___ser1___width 1
-#define reg_intr_vect_r_masked_vect___ser1___bit 20
-#define reg_intr_vect_r_masked_vect___ser2___lsb 21
-#define reg_intr_vect_r_masked_vect___ser2___width 1
-#define reg_intr_vect_r_masked_vect___ser2___bit 21
-#define reg_intr_vect_r_masked_vect___ser3___lsb 22
-#define reg_intr_vect_r_masked_vect___ser3___width 1
-#define reg_intr_vect_r_masked_vect___ser3___bit 22
-#define reg_intr_vect_r_masked_vect___p21___lsb 23
-#define reg_intr_vect_r_masked_vect___p21___width 1
-#define reg_intr_vect_r_masked_vect___p21___bit 23
-#define reg_intr_vect_r_masked_vect___eth0___lsb 24
-#define reg_intr_vect_r_masked_vect___eth0___width 1
-#define reg_intr_vect_r_masked_vect___eth0___bit 24
-#define reg_intr_vect_r_masked_vect___eth1___lsb 25
-#define reg_intr_vect_r_masked_vect___eth1___width 1
-#define reg_intr_vect_r_masked_vect___eth1___bit 25
-#define reg_intr_vect_r_masked_vect___timer___lsb 26
-#define reg_intr_vect_r_masked_vect___timer___width 1
-#define reg_intr_vect_r_masked_vect___timer___bit 26
-#define reg_intr_vect_r_masked_vect___bif_arb___lsb 27
-#define reg_intr_vect_r_masked_vect___bif_arb___width 1
-#define reg_intr_vect_r_masked_vect___bif_arb___bit 27
-#define reg_intr_vect_r_masked_vect___bif_dma___lsb 28
-#define reg_intr_vect_r_masked_vect___bif_dma___width 1
-#define reg_intr_vect_r_masked_vect___bif_dma___bit 28
-#define reg_intr_vect_r_masked_vect___ext___lsb 29
-#define reg_intr_vect_r_masked_vect___ext___width 1
-#define reg_intr_vect_r_masked_vect___ext___bit 29
-#define reg_intr_vect_r_masked_vect_offset 8
-
-/* Register r_nmi, scope intr_vect, type r */
-#define reg_intr_vect_r_nmi___ext___lsb 0
-#define reg_intr_vect_r_nmi___ext___width 1
-#define reg_intr_vect_r_nmi___ext___bit 0
-#define reg_intr_vect_r_nmi___watchdog___lsb 1
-#define reg_intr_vect_r_nmi___watchdog___width 1
-#define reg_intr_vect_r_nmi___watchdog___bit 1
-#define reg_intr_vect_r_nmi_offset 12
-
-/* Register r_guru, scope intr_vect, type r */
-#define reg_intr_vect_r_guru___jtag___lsb 0
-#define reg_intr_vect_r_guru___jtag___width 1
-#define reg_intr_vect_r_guru___jtag___bit 0
-#define reg_intr_vect_r_guru_offset 16
-
-
-/* Constants */
-#define regk_intr_vect_off                        0x00000000
-#define regk_intr_vect_on                         0x00000001
-#define regk_intr_vect_rw_mask_default            0x00000000
-#endif /* __intr_vect_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h
deleted file mode 100644
index 0c8084054840..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h
+++ /dev/null
@@ -1,69 +0,0 @@
-#ifndef __irq_nmi_defs_asm_h
-#define __irq_nmi_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../mod/irq_nmi.r
- *     id:           <not found>
- *     last modfied: Thu Jan 22 09:22:43 2004
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/irq_nmi_defs_asm.h ../../mod/irq_nmi.r
- *      id: $Id: irq_nmi_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cmd, scope irq_nmi, type rw */
-#define reg_irq_nmi_rw_cmd___delay___lsb 0
-#define reg_irq_nmi_rw_cmd___delay___width 16
-#define reg_irq_nmi_rw_cmd___op___lsb 16
-#define reg_irq_nmi_rw_cmd___op___width 2
-#define reg_irq_nmi_rw_cmd_offset 0
-
-
-/* Constants */
-#define regk_irq_nmi_ack_irq                      0x00000002
-#define regk_irq_nmi_ack_nmi                      0x00000003
-#define regk_irq_nmi_irq                          0x00000000
-#define regk_irq_nmi_nmi                          0x00000001
-#endif /* __irq_nmi_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h
deleted file mode 100644
index 45400eb8d389..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h
+++ /dev/null
@@ -1,579 +0,0 @@
-#ifndef __marb_defs_asm_h
-#define __marb_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:12:16 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
- *      id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_marb_rw_int_slots 4
-/* Register rw_int_slots, scope marb, type rw */
-#define reg_marb_rw_int_slots___owner___lsb 0
-#define reg_marb_rw_int_slots___owner___width 4
-#define reg_marb_rw_int_slots_offset 0
-
-#define STRIDE_marb_rw_ext_slots 4
-/* Register rw_ext_slots, scope marb, type rw */
-#define reg_marb_rw_ext_slots___owner___lsb 0
-#define reg_marb_rw_ext_slots___owner___width 4
-#define reg_marb_rw_ext_slots_offset 256
-
-#define STRIDE_marb_rw_regs_slots 4
-/* Register rw_regs_slots, scope marb, type rw */
-#define reg_marb_rw_regs_slots___owner___lsb 0
-#define reg_marb_rw_regs_slots___owner___width 4
-#define reg_marb_rw_regs_slots_offset 512
-
-/* Register rw_intr_mask, scope marb, type rw */
-#define reg_marb_rw_intr_mask___bp0___lsb 0
-#define reg_marb_rw_intr_mask___bp0___width 1
-#define reg_marb_rw_intr_mask___bp0___bit 0
-#define reg_marb_rw_intr_mask___bp1___lsb 1
-#define reg_marb_rw_intr_mask___bp1___width 1
-#define reg_marb_rw_intr_mask___bp1___bit 1
-#define reg_marb_rw_intr_mask___bp2___lsb 2
-#define reg_marb_rw_intr_mask___bp2___width 1
-#define reg_marb_rw_intr_mask___bp2___bit 2
-#define reg_marb_rw_intr_mask___bp3___lsb 3
-#define reg_marb_rw_intr_mask___bp3___width 1
-#define reg_marb_rw_intr_mask___bp3___bit 3
-#define reg_marb_rw_intr_mask_offset 528
-
-/* Register rw_ack_intr, scope marb, type rw */
-#define reg_marb_rw_ack_intr___bp0___lsb 0
-#define reg_marb_rw_ack_intr___bp0___width 1
-#define reg_marb_rw_ack_intr___bp0___bit 0
-#define reg_marb_rw_ack_intr___bp1___lsb 1
-#define reg_marb_rw_ack_intr___bp1___width 1
-#define reg_marb_rw_ack_intr___bp1___bit 1
-#define reg_marb_rw_ack_intr___bp2___lsb 2
-#define reg_marb_rw_ack_intr___bp2___width 1
-#define reg_marb_rw_ack_intr___bp2___bit 2
-#define reg_marb_rw_ack_intr___bp3___lsb 3
-#define reg_marb_rw_ack_intr___bp3___width 1
-#define reg_marb_rw_ack_intr___bp3___bit 3
-#define reg_marb_rw_ack_intr_offset 532
-
-/* Register r_intr, scope marb, type r */
-#define reg_marb_r_intr___bp0___lsb 0
-#define reg_marb_r_intr___bp0___width 1
-#define reg_marb_r_intr___bp0___bit 0
-#define reg_marb_r_intr___bp1___lsb 1
-#define reg_marb_r_intr___bp1___width 1
-#define reg_marb_r_intr___bp1___bit 1
-#define reg_marb_r_intr___bp2___lsb 2
-#define reg_marb_r_intr___bp2___width 1
-#define reg_marb_r_intr___bp2___bit 2
-#define reg_marb_r_intr___bp3___lsb 3
-#define reg_marb_r_intr___bp3___width 1
-#define reg_marb_r_intr___bp3___bit 3
-#define reg_marb_r_intr_offset 536
-
-/* Register r_masked_intr, scope marb, type r */
-#define reg_marb_r_masked_intr___bp0___lsb 0
-#define reg_marb_r_masked_intr___bp0___width 1
-#define reg_marb_r_masked_intr___bp0___bit 0
-#define reg_marb_r_masked_intr___bp1___lsb 1
-#define reg_marb_r_masked_intr___bp1___width 1
-#define reg_marb_r_masked_intr___bp1___bit 1
-#define reg_marb_r_masked_intr___bp2___lsb 2
-#define reg_marb_r_masked_intr___bp2___width 1
-#define reg_marb_r_masked_intr___bp2___bit 2
-#define reg_marb_r_masked_intr___bp3___lsb 3
-#define reg_marb_r_masked_intr___bp3___width 1
-#define reg_marb_r_masked_intr___bp3___bit 3
-#define reg_marb_r_masked_intr_offset 540
-
-/* Register rw_stop_mask, scope marb, type rw */
-#define reg_marb_rw_stop_mask___dma0___lsb 0
-#define reg_marb_rw_stop_mask___dma0___width 1
-#define reg_marb_rw_stop_mask___dma0___bit 0
-#define reg_marb_rw_stop_mask___dma1___lsb 1
-#define reg_marb_rw_stop_mask___dma1___width 1
-#define reg_marb_rw_stop_mask___dma1___bit 1
-#define reg_marb_rw_stop_mask___dma2___lsb 2
-#define reg_marb_rw_stop_mask___dma2___width 1
-#define reg_marb_rw_stop_mask___dma2___bit 2
-#define reg_marb_rw_stop_mask___dma3___lsb 3
-#define reg_marb_rw_stop_mask___dma3___width 1
-#define reg_marb_rw_stop_mask___dma3___bit 3
-#define reg_marb_rw_stop_mask___dma4___lsb 4
-#define reg_marb_rw_stop_mask___dma4___width 1
-#define reg_marb_rw_stop_mask___dma4___bit 4
-#define reg_marb_rw_stop_mask___dma5___lsb 5
-#define reg_marb_rw_stop_mask___dma5___width 1
-#define reg_marb_rw_stop_mask___dma5___bit 5
-#define reg_marb_rw_stop_mask___dma6___lsb 6
-#define reg_marb_rw_stop_mask___dma6___width 1
-#define reg_marb_rw_stop_mask___dma6___bit 6
-#define reg_marb_rw_stop_mask___dma7___lsb 7
-#define reg_marb_rw_stop_mask___dma7___width 1
-#define reg_marb_rw_stop_mask___dma7___bit 7
-#define reg_marb_rw_stop_mask___dma8___lsb 8
-#define reg_marb_rw_stop_mask___dma8___width 1
-#define reg_marb_rw_stop_mask___dma8___bit 8
-#define reg_marb_rw_stop_mask___dma9___lsb 9
-#define reg_marb_rw_stop_mask___dma9___width 1
-#define reg_marb_rw_stop_mask___dma9___bit 9
-#define reg_marb_rw_stop_mask___cpui___lsb 10
-#define reg_marb_rw_stop_mask___cpui___width 1
-#define reg_marb_rw_stop_mask___cpui___bit 10
-#define reg_marb_rw_stop_mask___cpud___lsb 11
-#define reg_marb_rw_stop_mask___cpud___width 1
-#define reg_marb_rw_stop_mask___cpud___bit 11
-#define reg_marb_rw_stop_mask___iop___lsb 12
-#define reg_marb_rw_stop_mask___iop___width 1
-#define reg_marb_rw_stop_mask___iop___bit 12
-#define reg_marb_rw_stop_mask___slave___lsb 13
-#define reg_marb_rw_stop_mask___slave___width 1
-#define reg_marb_rw_stop_mask___slave___bit 13
-#define reg_marb_rw_stop_mask_offset 544
-
-/* Register r_stopped, scope marb, type r */
-#define reg_marb_r_stopped___dma0___lsb 0
-#define reg_marb_r_stopped___dma0___width 1
-#define reg_marb_r_stopped___dma0___bit 0
-#define reg_marb_r_stopped___dma1___lsb 1
-#define reg_marb_r_stopped___dma1___width 1
-#define reg_marb_r_stopped___dma1___bit 1
-#define reg_marb_r_stopped___dma2___lsb 2
-#define reg_marb_r_stopped___dma2___width 1
-#define reg_marb_r_stopped___dma2___bit 2
-#define reg_marb_r_stopped___dma3___lsb 3
-#define reg_marb_r_stopped___dma3___width 1
-#define reg_marb_r_stopped___dma3___bit 3
-#define reg_marb_r_stopped___dma4___lsb 4
-#define reg_marb_r_stopped___dma4___width 1
-#define reg_marb_r_stopped___dma4___bit 4
-#define reg_marb_r_stopped___dma5___lsb 5
-#define reg_marb_r_stopped___dma5___width 1
-#define reg_marb_r_stopped___dma5___bit 5
-#define reg_marb_r_stopped___dma6___lsb 6
-#define reg_marb_r_stopped___dma6___width 1
-#define reg_marb_r_stopped___dma6___bit 6
-#define reg_marb_r_stopped___dma7___lsb 7
-#define reg_marb_r_stopped___dma7___width 1
-#define reg_marb_r_stopped___dma7___bit 7
-#define reg_marb_r_stopped___dma8___lsb 8
-#define reg_marb_r_stopped___dma8___width 1
-#define reg_marb_r_stopped___dma8___bit 8
-#define reg_marb_r_stopped___dma9___lsb 9
-#define reg_marb_r_stopped___dma9___width 1
-#define reg_marb_r_stopped___dma9___bit 9
-#define reg_marb_r_stopped___cpui___lsb 10
-#define reg_marb_r_stopped___cpui___width 1
-#define reg_marb_r_stopped___cpui___bit 10
-#define reg_marb_r_stopped___cpud___lsb 11
-#define reg_marb_r_stopped___cpud___width 1
-#define reg_marb_r_stopped___cpud___bit 11
-#define reg_marb_r_stopped___iop___lsb 12
-#define reg_marb_r_stopped___iop___width 1
-#define reg_marb_r_stopped___iop___bit 12
-#define reg_marb_r_stopped___slave___lsb 13
-#define reg_marb_r_stopped___slave___width 1
-#define reg_marb_r_stopped___slave___bit 13
-#define reg_marb_r_stopped_offset 548
-
-/* Register rw_no_snoop, scope marb, type rw */
-#define reg_marb_rw_no_snoop___dma0___lsb 0
-#define reg_marb_rw_no_snoop___dma0___width 1
-#define reg_marb_rw_no_snoop___dma0___bit 0
-#define reg_marb_rw_no_snoop___dma1___lsb 1
-#define reg_marb_rw_no_snoop___dma1___width 1
-#define reg_marb_rw_no_snoop___dma1___bit 1
-#define reg_marb_rw_no_snoop___dma2___lsb 2
-#define reg_marb_rw_no_snoop___dma2___width 1
-#define reg_marb_rw_no_snoop___dma2___bit 2
-#define reg_marb_rw_no_snoop___dma3___lsb 3
-#define reg_marb_rw_no_snoop___dma3___width 1
-#define reg_marb_rw_no_snoop___dma3___bit 3
-#define reg_marb_rw_no_snoop___dma4___lsb 4
-#define reg_marb_rw_no_snoop___dma4___width 1
-#define reg_marb_rw_no_snoop___dma4___bit 4
-#define reg_marb_rw_no_snoop___dma5___lsb 5
-#define reg_marb_rw_no_snoop___dma5___width 1
-#define reg_marb_rw_no_snoop___dma5___bit 5
-#define reg_marb_rw_no_snoop___dma6___lsb 6
-#define reg_marb_rw_no_snoop___dma6___width 1
-#define reg_marb_rw_no_snoop___dma6___bit 6
-#define reg_marb_rw_no_snoop___dma7___lsb 7
-#define reg_marb_rw_no_snoop___dma7___width 1
-#define reg_marb_rw_no_snoop___dma7___bit 7
-#define reg_marb_rw_no_snoop___dma8___lsb 8
-#define reg_marb_rw_no_snoop___dma8___width 1
-#define reg_marb_rw_no_snoop___dma8___bit 8
-#define reg_marb_rw_no_snoop___dma9___lsb 9
-#define reg_marb_rw_no_snoop___dma9___width 1
-#define reg_marb_rw_no_snoop___dma9___bit 9
-#define reg_marb_rw_no_snoop___cpui___lsb 10
-#define reg_marb_rw_no_snoop___cpui___width 1
-#define reg_marb_rw_no_snoop___cpui___bit 10
-#define reg_marb_rw_no_snoop___cpud___lsb 11
-#define reg_marb_rw_no_snoop___cpud___width 1
-#define reg_marb_rw_no_snoop___cpud___bit 11
-#define reg_marb_rw_no_snoop___iop___lsb 12
-#define reg_marb_rw_no_snoop___iop___width 1
-#define reg_marb_rw_no_snoop___iop___bit 12
-#define reg_marb_rw_no_snoop___slave___lsb 13
-#define reg_marb_rw_no_snoop___slave___width 1
-#define reg_marb_rw_no_snoop___slave___bit 13
-#define reg_marb_rw_no_snoop_offset 832
-
-/* Register rw_no_snoop_rq, scope marb, type rw */
-#define reg_marb_rw_no_snoop_rq___cpui___lsb 10
-#define reg_marb_rw_no_snoop_rq___cpui___width 1
-#define reg_marb_rw_no_snoop_rq___cpui___bit 10
-#define reg_marb_rw_no_snoop_rq___cpud___lsb 11
-#define reg_marb_rw_no_snoop_rq___cpud___width 1
-#define reg_marb_rw_no_snoop_rq___cpud___bit 11
-#define reg_marb_rw_no_snoop_rq_offset 836
-
-
-/* Constants */
-#define regk_marb_cpud                            0x0000000b
-#define regk_marb_cpui                            0x0000000a
-#define regk_marb_dma0                            0x00000000
-#define regk_marb_dma1                            0x00000001
-#define regk_marb_dma2                            0x00000002
-#define regk_marb_dma3                            0x00000003
-#define regk_marb_dma4                            0x00000004
-#define regk_marb_dma5                            0x00000005
-#define regk_marb_dma6                            0x00000006
-#define regk_marb_dma7                            0x00000007
-#define regk_marb_dma8                            0x00000008
-#define regk_marb_dma9                            0x00000009
-#define regk_marb_iop                             0x0000000c
-#define regk_marb_no                              0x00000000
-#define regk_marb_r_stopped_default               0x00000000
-#define regk_marb_rw_ext_slots_default            0x00000000
-#define regk_marb_rw_ext_slots_size               0x00000040
-#define regk_marb_rw_int_slots_default            0x00000000
-#define regk_marb_rw_int_slots_size               0x00000040
-#define regk_marb_rw_intr_mask_default            0x00000000
-#define regk_marb_rw_no_snoop_default             0x00000000
-#define regk_marb_rw_no_snoop_rq_default          0x00000000
-#define regk_marb_rw_regs_slots_default           0x00000000
-#define regk_marb_rw_regs_slots_size              0x00000004
-#define regk_marb_rw_stop_mask_default            0x00000000
-#define regk_marb_slave                           0x0000000d
-#define regk_marb_yes                             0x00000001
-#endif /* __marb_defs_asm_h */
-#ifndef __marb_bp_defs_asm_h
-#define __marb_bp_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:12:16 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
- *      id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_first_addr, scope marb_bp, type rw */
-#define reg_marb_bp_rw_first_addr_offset 0
-
-/* Register rw_last_addr, scope marb_bp, type rw */
-#define reg_marb_bp_rw_last_addr_offset 4
-
-/* Register rw_op, scope marb_bp, type rw */
-#define reg_marb_bp_rw_op___rd___lsb 0
-#define reg_marb_bp_rw_op___rd___width 1
-#define reg_marb_bp_rw_op___rd___bit 0
-#define reg_marb_bp_rw_op___wr___lsb 1
-#define reg_marb_bp_rw_op___wr___width 1
-#define reg_marb_bp_rw_op___wr___bit 1
-#define reg_marb_bp_rw_op___rd_excl___lsb 2
-#define reg_marb_bp_rw_op___rd_excl___width 1
-#define reg_marb_bp_rw_op___rd_excl___bit 2
-#define reg_marb_bp_rw_op___pri_wr___lsb 3
-#define reg_marb_bp_rw_op___pri_wr___width 1
-#define reg_marb_bp_rw_op___pri_wr___bit 3
-#define reg_marb_bp_rw_op___us_rd___lsb 4
-#define reg_marb_bp_rw_op___us_rd___width 1
-#define reg_marb_bp_rw_op___us_rd___bit 4
-#define reg_marb_bp_rw_op___us_wr___lsb 5
-#define reg_marb_bp_rw_op___us_wr___width 1
-#define reg_marb_bp_rw_op___us_wr___bit 5
-#define reg_marb_bp_rw_op___us_rd_excl___lsb 6
-#define reg_marb_bp_rw_op___us_rd_excl___width 1
-#define reg_marb_bp_rw_op___us_rd_excl___bit 6
-#define reg_marb_bp_rw_op___us_pri_wr___lsb 7
-#define reg_marb_bp_rw_op___us_pri_wr___width 1
-#define reg_marb_bp_rw_op___us_pri_wr___bit 7
-#define reg_marb_bp_rw_op_offset 8
-
-/* Register rw_clients, scope marb_bp, type rw */
-#define reg_marb_bp_rw_clients___dma0___lsb 0
-#define reg_marb_bp_rw_clients___dma0___width 1
-#define reg_marb_bp_rw_clients___dma0___bit 0
-#define reg_marb_bp_rw_clients___dma1___lsb 1
-#define reg_marb_bp_rw_clients___dma1___width 1
-#define reg_marb_bp_rw_clients___dma1___bit 1
-#define reg_marb_bp_rw_clients___dma2___lsb 2
-#define reg_marb_bp_rw_clients___dma2___width 1
-#define reg_marb_bp_rw_clients___dma2___bit 2
-#define reg_marb_bp_rw_clients___dma3___lsb 3
-#define reg_marb_bp_rw_clients___dma3___width 1
-#define reg_marb_bp_rw_clients___dma3___bit 3
-#define reg_marb_bp_rw_clients___dma4___lsb 4
-#define reg_marb_bp_rw_clients___dma4___width 1
-#define reg_marb_bp_rw_clients___dma4___bit 4
-#define reg_marb_bp_rw_clients___dma5___lsb 5
-#define reg_marb_bp_rw_clients___dma5___width 1
-#define reg_marb_bp_rw_clients___dma5___bit 5
-#define reg_marb_bp_rw_clients___dma6___lsb 6
-#define reg_marb_bp_rw_clients___dma6___width 1
-#define reg_marb_bp_rw_clients___dma6___bit 6
-#define reg_marb_bp_rw_clients___dma7___lsb 7
-#define reg_marb_bp_rw_clients___dma7___width 1
-#define reg_marb_bp_rw_clients___dma7___bit 7
-#define reg_marb_bp_rw_clients___dma8___lsb 8
-#define reg_marb_bp_rw_clients___dma8___width 1
-#define reg_marb_bp_rw_clients___dma8___bit 8
-#define reg_marb_bp_rw_clients___dma9___lsb 9
-#define reg_marb_bp_rw_clients___dma9___width 1
-#define reg_marb_bp_rw_clients___dma9___bit 9
-#define reg_marb_bp_rw_clients___cpui___lsb 10
-#define reg_marb_bp_rw_clients___cpui___width 1
-#define reg_marb_bp_rw_clients___cpui___bit 10
-#define reg_marb_bp_rw_clients___cpud___lsb 11
-#define reg_marb_bp_rw_clients___cpud___width 1
-#define reg_marb_bp_rw_clients___cpud___bit 11
-#define reg_marb_bp_rw_clients___iop___lsb 12
-#define reg_marb_bp_rw_clients___iop___width 1
-#define reg_marb_bp_rw_clients___iop___bit 12
-#define reg_marb_bp_rw_clients___slave___lsb 13
-#define reg_marb_bp_rw_clients___slave___width 1
-#define reg_marb_bp_rw_clients___slave___bit 13
-#define reg_marb_bp_rw_clients_offset 12
-
-/* Register rw_options, scope marb_bp, type rw */
-#define reg_marb_bp_rw_options___wrap___lsb 0
-#define reg_marb_bp_rw_options___wrap___width 1
-#define reg_marb_bp_rw_options___wrap___bit 0
-#define reg_marb_bp_rw_options_offset 16
-
-/* Register r_brk_addr, scope marb_bp, type r */
-#define reg_marb_bp_r_brk_addr_offset 20
-
-/* Register r_brk_op, scope marb_bp, type r */
-#define reg_marb_bp_r_brk_op___rd___lsb 0
-#define reg_marb_bp_r_brk_op___rd___width 1
-#define reg_marb_bp_r_brk_op___rd___bit 0
-#define reg_marb_bp_r_brk_op___wr___lsb 1
-#define reg_marb_bp_r_brk_op___wr___width 1
-#define reg_marb_bp_r_brk_op___wr___bit 1
-#define reg_marb_bp_r_brk_op___rd_excl___lsb 2
-#define reg_marb_bp_r_brk_op___rd_excl___width 1
-#define reg_marb_bp_r_brk_op___rd_excl___bit 2
-#define reg_marb_bp_r_brk_op___pri_wr___lsb 3
-#define reg_marb_bp_r_brk_op___pri_wr___width 1
-#define reg_marb_bp_r_brk_op___pri_wr___bit 3
-#define reg_marb_bp_r_brk_op___us_rd___lsb 4
-#define reg_marb_bp_r_brk_op___us_rd___width 1
-#define reg_marb_bp_r_brk_op___us_rd___bit 4
-#define reg_marb_bp_r_brk_op___us_wr___lsb 5
-#define reg_marb_bp_r_brk_op___us_wr___width 1
-#define reg_marb_bp_r_brk_op___us_wr___bit 5
-#define reg_marb_bp_r_brk_op___us_rd_excl___lsb 6
-#define reg_marb_bp_r_brk_op___us_rd_excl___width 1
-#define reg_marb_bp_r_brk_op___us_rd_excl___bit 6
-#define reg_marb_bp_r_brk_op___us_pri_wr___lsb 7
-#define reg_marb_bp_r_brk_op___us_pri_wr___width 1
-#define reg_marb_bp_r_brk_op___us_pri_wr___bit 7
-#define reg_marb_bp_r_brk_op_offset 24
-
-/* Register r_brk_clients, scope marb_bp, type r */
-#define reg_marb_bp_r_brk_clients___dma0___lsb 0
-#define reg_marb_bp_r_brk_clients___dma0___width 1
-#define reg_marb_bp_r_brk_clients___dma0___bit 0
-#define reg_marb_bp_r_brk_clients___dma1___lsb 1
-#define reg_marb_bp_r_brk_clients___dma1___width 1
-#define reg_marb_bp_r_brk_clients___dma1___bit 1
-#define reg_marb_bp_r_brk_clients___dma2___lsb 2
-#define reg_marb_bp_r_brk_clients___dma2___width 1
-#define reg_marb_bp_r_brk_clients___dma2___bit 2
-#define reg_marb_bp_r_brk_clients___dma3___lsb 3
-#define reg_marb_bp_r_brk_clients___dma3___width 1
-#define reg_marb_bp_r_brk_clients___dma3___bit 3
-#define reg_marb_bp_r_brk_clients___dma4___lsb 4
-#define reg_marb_bp_r_brk_clients___dma4___width 1
-#define reg_marb_bp_r_brk_clients___dma4___bit 4
-#define reg_marb_bp_r_brk_clients___dma5___lsb 5
-#define reg_marb_bp_r_brk_clients___dma5___width 1
-#define reg_marb_bp_r_brk_clients___dma5___bit 5
-#define reg_marb_bp_r_brk_clients___dma6___lsb 6
-#define reg_marb_bp_r_brk_clients___dma6___width 1
-#define reg_marb_bp_r_brk_clients___dma6___bit 6
-#define reg_marb_bp_r_brk_clients___dma7___lsb 7
-#define reg_marb_bp_r_brk_clients___dma7___width 1
-#define reg_marb_bp_r_brk_clients___dma7___bit 7
-#define reg_marb_bp_r_brk_clients___dma8___lsb 8
-#define reg_marb_bp_r_brk_clients___dma8___width 1
-#define reg_marb_bp_r_brk_clients___dma8___bit 8
-#define reg_marb_bp_r_brk_clients___dma9___lsb 9
-#define reg_marb_bp_r_brk_clients___dma9___width 1
-#define reg_marb_bp_r_brk_clients___dma9___bit 9
-#define reg_marb_bp_r_brk_clients___cpui___lsb 10
-#define reg_marb_bp_r_brk_clients___cpui___width 1
-#define reg_marb_bp_r_brk_clients___cpui___bit 10
-#define reg_marb_bp_r_brk_clients___cpud___lsb 11
-#define reg_marb_bp_r_brk_clients___cpud___width 1
-#define reg_marb_bp_r_brk_clients___cpud___bit 11
-#define reg_marb_bp_r_brk_clients___iop___lsb 12
-#define reg_marb_bp_r_brk_clients___iop___width 1
-#define reg_marb_bp_r_brk_clients___iop___bit 12
-#define reg_marb_bp_r_brk_clients___slave___lsb 13
-#define reg_marb_bp_r_brk_clients___slave___width 1
-#define reg_marb_bp_r_brk_clients___slave___bit 13
-#define reg_marb_bp_r_brk_clients_offset 28
-
-/* Register r_brk_first_client, scope marb_bp, type r */
-#define reg_marb_bp_r_brk_first_client___dma0___lsb 0
-#define reg_marb_bp_r_brk_first_client___dma0___width 1
-#define reg_marb_bp_r_brk_first_client___dma0___bit 0
-#define reg_marb_bp_r_brk_first_client___dma1___lsb 1
-#define reg_marb_bp_r_brk_first_client___dma1___width 1
-#define reg_marb_bp_r_brk_first_client___dma1___bit 1
-#define reg_marb_bp_r_brk_first_client___dma2___lsb 2
-#define reg_marb_bp_r_brk_first_client___dma2___width 1
-#define reg_marb_bp_r_brk_first_client___dma2___bit 2
-#define reg_marb_bp_r_brk_first_client___dma3___lsb 3
-#define reg_marb_bp_r_brk_first_client___dma3___width 1
-#define reg_marb_bp_r_brk_first_client___dma3___bit 3
-#define reg_marb_bp_r_brk_first_client___dma4___lsb 4
-#define reg_marb_bp_r_brk_first_client___dma4___width 1
-#define reg_marb_bp_r_brk_first_client___dma4___bit 4
-#define reg_marb_bp_r_brk_first_client___dma5___lsb 5
-#define reg_marb_bp_r_brk_first_client___dma5___width 1
-#define reg_marb_bp_r_brk_first_client___dma5___bit 5
-#define reg_marb_bp_r_brk_first_client___dma6___lsb 6
-#define reg_marb_bp_r_brk_first_client___dma6___width 1
-#define reg_marb_bp_r_brk_first_client___dma6___bit 6
-#define reg_marb_bp_r_brk_first_client___dma7___lsb 7
-#define reg_marb_bp_r_brk_first_client___dma7___width 1
-#define reg_marb_bp_r_brk_first_client___dma7___bit 7
-#define reg_marb_bp_r_brk_first_client___dma8___lsb 8
-#define reg_marb_bp_r_brk_first_client___dma8___width 1
-#define reg_marb_bp_r_brk_first_client___dma8___bit 8
-#define reg_marb_bp_r_brk_first_client___dma9___lsb 9
-#define reg_marb_bp_r_brk_first_client___dma9___width 1
-#define reg_marb_bp_r_brk_first_client___dma9___bit 9
-#define reg_marb_bp_r_brk_first_client___cpui___lsb 10
-#define reg_marb_bp_r_brk_first_client___cpui___width 1
-#define reg_marb_bp_r_brk_first_client___cpui___bit 10
-#define reg_marb_bp_r_brk_first_client___cpud___lsb 11
-#define reg_marb_bp_r_brk_first_client___cpud___width 1
-#define reg_marb_bp_r_brk_first_client___cpud___bit 11
-#define reg_marb_bp_r_brk_first_client___iop___lsb 12
-#define reg_marb_bp_r_brk_first_client___iop___width 1
-#define reg_marb_bp_r_brk_first_client___iop___bit 12
-#define reg_marb_bp_r_brk_first_client___slave___lsb 13
-#define reg_marb_bp_r_brk_first_client___slave___width 1
-#define reg_marb_bp_r_brk_first_client___slave___bit 13
-#define reg_marb_bp_r_brk_first_client_offset 32
-
-/* Register r_brk_size, scope marb_bp, type r */
-#define reg_marb_bp_r_brk_size_offset 36
-
-/* Register rw_ack, scope marb_bp, type rw */
-#define reg_marb_bp_rw_ack_offset 40
-
-
-/* Constants */
-#define regk_marb_bp_no                           0x00000000
-#define regk_marb_bp_rw_op_default                0x00000000
-#define regk_marb_bp_rw_options_default           0x00000000
-#define regk_marb_bp_yes                          0x00000001
-#endif /* __marb_bp_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h
deleted file mode 100644
index 505b7a16d878..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h
+++ /dev/null
@@ -1,212 +0,0 @@
-#ifndef __mmu_defs_asm_h
-#define __mmu_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/mmu/doc/mmu_regs.r
- *     id:           mmu_regs.r,v 1.12 2004/05/06 13:48:45 mikaeln Exp
- *     last modfied: Mon Apr 11 17:03:20 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r
- *      id: $Id: mmu_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_mm_cfg, scope mmu, type rw */
-#define reg_mmu_rw_mm_cfg___seg_0___lsb 0
-#define reg_mmu_rw_mm_cfg___seg_0___width 1
-#define reg_mmu_rw_mm_cfg___seg_0___bit 0
-#define reg_mmu_rw_mm_cfg___seg_1___lsb 1
-#define reg_mmu_rw_mm_cfg___seg_1___width 1
-#define reg_mmu_rw_mm_cfg___seg_1___bit 1
-#define reg_mmu_rw_mm_cfg___seg_2___lsb 2
-#define reg_mmu_rw_mm_cfg___seg_2___width 1
-#define reg_mmu_rw_mm_cfg___seg_2___bit 2
-#define reg_mmu_rw_mm_cfg___seg_3___lsb 3
-#define reg_mmu_rw_mm_cfg___seg_3___width 1
-#define reg_mmu_rw_mm_cfg___seg_3___bit 3
-#define reg_mmu_rw_mm_cfg___seg_4___lsb 4
-#define reg_mmu_rw_mm_cfg___seg_4___width 1
-#define reg_mmu_rw_mm_cfg___seg_4___bit 4
-#define reg_mmu_rw_mm_cfg___seg_5___lsb 5
-#define reg_mmu_rw_mm_cfg___seg_5___width 1
-#define reg_mmu_rw_mm_cfg___seg_5___bit 5
-#define reg_mmu_rw_mm_cfg___seg_6___lsb 6
-#define reg_mmu_rw_mm_cfg___seg_6___width 1
-#define reg_mmu_rw_mm_cfg___seg_6___bit 6
-#define reg_mmu_rw_mm_cfg___seg_7___lsb 7
-#define reg_mmu_rw_mm_cfg___seg_7___width 1
-#define reg_mmu_rw_mm_cfg___seg_7___bit 7
-#define reg_mmu_rw_mm_cfg___seg_8___lsb 8
-#define reg_mmu_rw_mm_cfg___seg_8___width 1
-#define reg_mmu_rw_mm_cfg___seg_8___bit 8
-#define reg_mmu_rw_mm_cfg___seg_9___lsb 9
-#define reg_mmu_rw_mm_cfg___seg_9___width 1
-#define reg_mmu_rw_mm_cfg___seg_9___bit 9
-#define reg_mmu_rw_mm_cfg___seg_a___lsb 10
-#define reg_mmu_rw_mm_cfg___seg_a___width 1
-#define reg_mmu_rw_mm_cfg___seg_a___bit 10
-#define reg_mmu_rw_mm_cfg___seg_b___lsb 11
-#define reg_mmu_rw_mm_cfg___seg_b___width 1
-#define reg_mmu_rw_mm_cfg___seg_b___bit 11
-#define reg_mmu_rw_mm_cfg___seg_c___lsb 12
-#define reg_mmu_rw_mm_cfg___seg_c___width 1
-#define reg_mmu_rw_mm_cfg___seg_c___bit 12
-#define reg_mmu_rw_mm_cfg___seg_d___lsb 13
-#define reg_mmu_rw_mm_cfg___seg_d___width 1
-#define reg_mmu_rw_mm_cfg___seg_d___bit 13
-#define reg_mmu_rw_mm_cfg___seg_e___lsb 14
-#define reg_mmu_rw_mm_cfg___seg_e___width 1
-#define reg_mmu_rw_mm_cfg___seg_e___bit 14
-#define reg_mmu_rw_mm_cfg___seg_f___lsb 15
-#define reg_mmu_rw_mm_cfg___seg_f___width 1
-#define reg_mmu_rw_mm_cfg___seg_f___bit 15
-#define reg_mmu_rw_mm_cfg___inv___lsb 16
-#define reg_mmu_rw_mm_cfg___inv___width 1
-#define reg_mmu_rw_mm_cfg___inv___bit 16
-#define reg_mmu_rw_mm_cfg___ex___lsb 17
-#define reg_mmu_rw_mm_cfg___ex___width 1
-#define reg_mmu_rw_mm_cfg___ex___bit 17
-#define reg_mmu_rw_mm_cfg___acc___lsb 18
-#define reg_mmu_rw_mm_cfg___acc___width 1
-#define reg_mmu_rw_mm_cfg___acc___bit 18
-#define reg_mmu_rw_mm_cfg___we___lsb 19
-#define reg_mmu_rw_mm_cfg___we___width 1
-#define reg_mmu_rw_mm_cfg___we___bit 19
-#define reg_mmu_rw_mm_cfg_offset 0
-
-/* Register rw_mm_kbase_lo, scope mmu, type rw */
-#define reg_mmu_rw_mm_kbase_lo___base_0___lsb 0
-#define reg_mmu_rw_mm_kbase_lo___base_0___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_1___lsb 4
-#define reg_mmu_rw_mm_kbase_lo___base_1___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_2___lsb 8
-#define reg_mmu_rw_mm_kbase_lo___base_2___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_3___lsb 12
-#define reg_mmu_rw_mm_kbase_lo___base_3___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_4___lsb 16
-#define reg_mmu_rw_mm_kbase_lo___base_4___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_5___lsb 20
-#define reg_mmu_rw_mm_kbase_lo___base_5___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_6___lsb 24
-#define reg_mmu_rw_mm_kbase_lo___base_6___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_7___lsb 28
-#define reg_mmu_rw_mm_kbase_lo___base_7___width 4
-#define reg_mmu_rw_mm_kbase_lo_offset 4
-
-/* Register rw_mm_kbase_hi, scope mmu, type rw */
-#define reg_mmu_rw_mm_kbase_hi___base_8___lsb 0
-#define reg_mmu_rw_mm_kbase_hi___base_8___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_9___lsb 4
-#define reg_mmu_rw_mm_kbase_hi___base_9___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_a___lsb 8
-#define reg_mmu_rw_mm_kbase_hi___base_a___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_b___lsb 12
-#define reg_mmu_rw_mm_kbase_hi___base_b___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_c___lsb 16
-#define reg_mmu_rw_mm_kbase_hi___base_c___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_d___lsb 20
-#define reg_mmu_rw_mm_kbase_hi___base_d___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_e___lsb 24
-#define reg_mmu_rw_mm_kbase_hi___base_e___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_f___lsb 28
-#define reg_mmu_rw_mm_kbase_hi___base_f___width 4
-#define reg_mmu_rw_mm_kbase_hi_offset 8
-
-/* Register r_mm_cause, scope mmu, type r */
-#define reg_mmu_r_mm_cause___pid___lsb 0
-#define reg_mmu_r_mm_cause___pid___width 8
-#define reg_mmu_r_mm_cause___op___lsb 8
-#define reg_mmu_r_mm_cause___op___width 2
-#define reg_mmu_r_mm_cause___vpn___lsb 13
-#define reg_mmu_r_mm_cause___vpn___width 19
-#define reg_mmu_r_mm_cause_offset 12
-
-/* Register rw_mm_tlb_sel, scope mmu, type rw */
-#define reg_mmu_rw_mm_tlb_sel___idx___lsb 0
-#define reg_mmu_rw_mm_tlb_sel___idx___width 4
-#define reg_mmu_rw_mm_tlb_sel___set___lsb 4
-#define reg_mmu_rw_mm_tlb_sel___set___width 2
-#define reg_mmu_rw_mm_tlb_sel_offset 16
-
-/* Register rw_mm_tlb_lo, scope mmu, type rw */
-#define reg_mmu_rw_mm_tlb_lo___x___lsb 0
-#define reg_mmu_rw_mm_tlb_lo___x___width 1
-#define reg_mmu_rw_mm_tlb_lo___x___bit 0
-#define reg_mmu_rw_mm_tlb_lo___w___lsb 1
-#define reg_mmu_rw_mm_tlb_lo___w___width 1
-#define reg_mmu_rw_mm_tlb_lo___w___bit 1
-#define reg_mmu_rw_mm_tlb_lo___k___lsb 2
-#define reg_mmu_rw_mm_tlb_lo___k___width 1
-#define reg_mmu_rw_mm_tlb_lo___k___bit 2
-#define reg_mmu_rw_mm_tlb_lo___v___lsb 3
-#define reg_mmu_rw_mm_tlb_lo___v___width 1
-#define reg_mmu_rw_mm_tlb_lo___v___bit 3
-#define reg_mmu_rw_mm_tlb_lo___g___lsb 4
-#define reg_mmu_rw_mm_tlb_lo___g___width 1
-#define reg_mmu_rw_mm_tlb_lo___g___bit 4
-#define reg_mmu_rw_mm_tlb_lo___pfn___lsb 13
-#define reg_mmu_rw_mm_tlb_lo___pfn___width 19
-#define reg_mmu_rw_mm_tlb_lo_offset 20
-
-/* Register rw_mm_tlb_hi, scope mmu, type rw */
-#define reg_mmu_rw_mm_tlb_hi___pid___lsb 0
-#define reg_mmu_rw_mm_tlb_hi___pid___width 8
-#define reg_mmu_rw_mm_tlb_hi___vpn___lsb 13
-#define reg_mmu_rw_mm_tlb_hi___vpn___width 19
-#define reg_mmu_rw_mm_tlb_hi_offset 24
-
-
-/* Constants */
-#define regk_mmu_execute                          0x00000000
-#define regk_mmu_flush                            0x00000003
-#define regk_mmu_linear                           0x00000001
-#define regk_mmu_no                               0x00000000
-#define regk_mmu_off                              0x00000000
-#define regk_mmu_on                               0x00000001
-#define regk_mmu_page                             0x00000000
-#define regk_mmu_read                             0x00000001
-#define regk_mmu_write                            0x00000002
-#define regk_mmu_yes                              0x00000001
-#endif /* __mmu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h b/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h
deleted file mode 100644
index 339500bf3bc0..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#define RW_MM_CFG	0
-#define RW_MM_KBASE_LO	1
-#define RW_MM_KBASE_HI	2
-#define R_MM_CAUSE	3
-#define RW_MM_TLB_SEL	4
-#define RW_MM_TLB_LO	5
-#define RW_MM_TLB_HI	6
diff --git a/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h
deleted file mode 100644
index 13c725e4c774..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h
+++ /dev/null
@@ -1,632 +0,0 @@
-#ifndef __pinmux_defs_asm_h
-#define __pinmux_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/pinmux/rtl/guinness/pinmux_regs.r
- *     id:           pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
- *     last modfied: Mon Apr 11 16:09:11 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
- *      id: $Id: pinmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_pa, scope pinmux, type rw */
-#define reg_pinmux_rw_pa___pa0___lsb 0
-#define reg_pinmux_rw_pa___pa0___width 1
-#define reg_pinmux_rw_pa___pa0___bit 0
-#define reg_pinmux_rw_pa___pa1___lsb 1
-#define reg_pinmux_rw_pa___pa1___width 1
-#define reg_pinmux_rw_pa___pa1___bit 1
-#define reg_pinmux_rw_pa___pa2___lsb 2
-#define reg_pinmux_rw_pa___pa2___width 1
-#define reg_pinmux_rw_pa___pa2___bit 2
-#define reg_pinmux_rw_pa___pa3___lsb 3
-#define reg_pinmux_rw_pa___pa3___width 1
-#define reg_pinmux_rw_pa___pa3___bit 3
-#define reg_pinmux_rw_pa___pa4___lsb 4
-#define reg_pinmux_rw_pa___pa4___width 1
-#define reg_pinmux_rw_pa___pa4___bit 4
-#define reg_pinmux_rw_pa___pa5___lsb 5
-#define reg_pinmux_rw_pa___pa5___width 1
-#define reg_pinmux_rw_pa___pa5___bit 5
-#define reg_pinmux_rw_pa___pa6___lsb 6
-#define reg_pinmux_rw_pa___pa6___width 1
-#define reg_pinmux_rw_pa___pa6___bit 6
-#define reg_pinmux_rw_pa___pa7___lsb 7
-#define reg_pinmux_rw_pa___pa7___width 1
-#define reg_pinmux_rw_pa___pa7___bit 7
-#define reg_pinmux_rw_pa___csp2_n___lsb 8
-#define reg_pinmux_rw_pa___csp2_n___width 1
-#define reg_pinmux_rw_pa___csp2_n___bit 8
-#define reg_pinmux_rw_pa___csp3_n___lsb 9
-#define reg_pinmux_rw_pa___csp3_n___width 1
-#define reg_pinmux_rw_pa___csp3_n___bit 9
-#define reg_pinmux_rw_pa___csp5_n___lsb 10
-#define reg_pinmux_rw_pa___csp5_n___width 1
-#define reg_pinmux_rw_pa___csp5_n___bit 10
-#define reg_pinmux_rw_pa___csp6_n___lsb 11
-#define reg_pinmux_rw_pa___csp6_n___width 1
-#define reg_pinmux_rw_pa___csp6_n___bit 11
-#define reg_pinmux_rw_pa___hsh4___lsb 12
-#define reg_pinmux_rw_pa___hsh4___width 1
-#define reg_pinmux_rw_pa___hsh4___bit 12
-#define reg_pinmux_rw_pa___hsh5___lsb 13
-#define reg_pinmux_rw_pa___hsh5___width 1
-#define reg_pinmux_rw_pa___hsh5___bit 13
-#define reg_pinmux_rw_pa___hsh6___lsb 14
-#define reg_pinmux_rw_pa___hsh6___width 1
-#define reg_pinmux_rw_pa___hsh6___bit 14
-#define reg_pinmux_rw_pa___hsh7___lsb 15
-#define reg_pinmux_rw_pa___hsh7___width 1
-#define reg_pinmux_rw_pa___hsh7___bit 15
-#define reg_pinmux_rw_pa_offset 0
-
-/* Register rw_hwprot, scope pinmux, type rw */
-#define reg_pinmux_rw_hwprot___ser1___lsb 0
-#define reg_pinmux_rw_hwprot___ser1___width 1
-#define reg_pinmux_rw_hwprot___ser1___bit 0
-#define reg_pinmux_rw_hwprot___ser2___lsb 1
-#define reg_pinmux_rw_hwprot___ser2___width 1
-#define reg_pinmux_rw_hwprot___ser2___bit 1
-#define reg_pinmux_rw_hwprot___ser3___lsb 2
-#define reg_pinmux_rw_hwprot___ser3___width 1
-#define reg_pinmux_rw_hwprot___ser3___bit 2
-#define reg_pinmux_rw_hwprot___sser0___lsb 3
-#define reg_pinmux_rw_hwprot___sser0___width 1
-#define reg_pinmux_rw_hwprot___sser0___bit 3
-#define reg_pinmux_rw_hwprot___sser1___lsb 4
-#define reg_pinmux_rw_hwprot___sser1___width 1
-#define reg_pinmux_rw_hwprot___sser1___bit 4
-#define reg_pinmux_rw_hwprot___ata0___lsb 5
-#define reg_pinmux_rw_hwprot___ata0___width 1
-#define reg_pinmux_rw_hwprot___ata0___bit 5
-#define reg_pinmux_rw_hwprot___ata1___lsb 6
-#define reg_pinmux_rw_hwprot___ata1___width 1
-#define reg_pinmux_rw_hwprot___ata1___bit 6
-#define reg_pinmux_rw_hwprot___ata2___lsb 7
-#define reg_pinmux_rw_hwprot___ata2___width 1
-#define reg_pinmux_rw_hwprot___ata2___bit 7
-#define reg_pinmux_rw_hwprot___ata3___lsb 8
-#define reg_pinmux_rw_hwprot___ata3___width 1
-#define reg_pinmux_rw_hwprot___ata3___bit 8
-#define reg_pinmux_rw_hwprot___ata___lsb 9
-#define reg_pinmux_rw_hwprot___ata___width 1
-#define reg_pinmux_rw_hwprot___ata___bit 9
-#define reg_pinmux_rw_hwprot___eth1___lsb 10
-#define reg_pinmux_rw_hwprot___eth1___width 1
-#define reg_pinmux_rw_hwprot___eth1___bit 10
-#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11
-#define reg_pinmux_rw_hwprot___eth1_mgm___width 1
-#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11
-#define reg_pinmux_rw_hwprot___timer___lsb 12
-#define reg_pinmux_rw_hwprot___timer___width 1
-#define reg_pinmux_rw_hwprot___timer___bit 12
-#define reg_pinmux_rw_hwprot___p21___lsb 13
-#define reg_pinmux_rw_hwprot___p21___width 1
-#define reg_pinmux_rw_hwprot___p21___bit 13
-#define reg_pinmux_rw_hwprot_offset 4
-
-/* Register rw_pb_gio, scope pinmux, type rw */
-#define reg_pinmux_rw_pb_gio___pb0___lsb 0
-#define reg_pinmux_rw_pb_gio___pb0___width 1
-#define reg_pinmux_rw_pb_gio___pb0___bit 0
-#define reg_pinmux_rw_pb_gio___pb1___lsb 1
-#define reg_pinmux_rw_pb_gio___pb1___width 1
-#define reg_pinmux_rw_pb_gio___pb1___bit 1
-#define reg_pinmux_rw_pb_gio___pb2___lsb 2
-#define reg_pinmux_rw_pb_gio___pb2___width 1
-#define reg_pinmux_rw_pb_gio___pb2___bit 2
-#define reg_pinmux_rw_pb_gio___pb3___lsb 3
-#define reg_pinmux_rw_pb_gio___pb3___width 1
-#define reg_pinmux_rw_pb_gio___pb3___bit 3
-#define reg_pinmux_rw_pb_gio___pb4___lsb 4
-#define reg_pinmux_rw_pb_gio___pb4___width 1
-#define reg_pinmux_rw_pb_gio___pb4___bit 4
-#define reg_pinmux_rw_pb_gio___pb5___lsb 5
-#define reg_pinmux_rw_pb_gio___pb5___width 1
-#define reg_pinmux_rw_pb_gio___pb5___bit 5
-#define reg_pinmux_rw_pb_gio___pb6___lsb 6
-#define reg_pinmux_rw_pb_gio___pb6___width 1
-#define reg_pinmux_rw_pb_gio___pb6___bit 6
-#define reg_pinmux_rw_pb_gio___pb7___lsb 7
-#define reg_pinmux_rw_pb_gio___pb7___width 1
-#define reg_pinmux_rw_pb_gio___pb7___bit 7
-#define reg_pinmux_rw_pb_gio___pb8___lsb 8
-#define reg_pinmux_rw_pb_gio___pb8___width 1
-#define reg_pinmux_rw_pb_gio___pb8___bit 8
-#define reg_pinmux_rw_pb_gio___pb9___lsb 9
-#define reg_pinmux_rw_pb_gio___pb9___width 1
-#define reg_pinmux_rw_pb_gio___pb9___bit 9
-#define reg_pinmux_rw_pb_gio___pb10___lsb 10
-#define reg_pinmux_rw_pb_gio___pb10___width 1
-#define reg_pinmux_rw_pb_gio___pb10___bit 10
-#define reg_pinmux_rw_pb_gio___pb11___lsb 11
-#define reg_pinmux_rw_pb_gio___pb11___width 1
-#define reg_pinmux_rw_pb_gio___pb11___bit 11
-#define reg_pinmux_rw_pb_gio___pb12___lsb 12
-#define reg_pinmux_rw_pb_gio___pb12___width 1
-#define reg_pinmux_rw_pb_gio___pb12___bit 12
-#define reg_pinmux_rw_pb_gio___pb13___lsb 13
-#define reg_pinmux_rw_pb_gio___pb13___width 1
-#define reg_pinmux_rw_pb_gio___pb13___bit 13
-#define reg_pinmux_rw_pb_gio___pb14___lsb 14
-#define reg_pinmux_rw_pb_gio___pb14___width 1
-#define reg_pinmux_rw_pb_gio___pb14___bit 14
-#define reg_pinmux_rw_pb_gio___pb15___lsb 15
-#define reg_pinmux_rw_pb_gio___pb15___width 1
-#define reg_pinmux_rw_pb_gio___pb15___bit 15
-#define reg_pinmux_rw_pb_gio___pb16___lsb 16
-#define reg_pinmux_rw_pb_gio___pb16___width 1
-#define reg_pinmux_rw_pb_gio___pb16___bit 16
-#define reg_pinmux_rw_pb_gio___pb17___lsb 17
-#define reg_pinmux_rw_pb_gio___pb17___width 1
-#define reg_pinmux_rw_pb_gio___pb17___bit 17
-#define reg_pinmux_rw_pb_gio_offset 8
-
-/* Register rw_pb_iop, scope pinmux, type rw */
-#define reg_pinmux_rw_pb_iop___pb0___lsb 0
-#define reg_pinmux_rw_pb_iop___pb0___width 1
-#define reg_pinmux_rw_pb_iop___pb0___bit 0
-#define reg_pinmux_rw_pb_iop___pb1___lsb 1
-#define reg_pinmux_rw_pb_iop___pb1___width 1
-#define reg_pinmux_rw_pb_iop___pb1___bit 1
-#define reg_pinmux_rw_pb_iop___pb2___lsb 2
-#define reg_pinmux_rw_pb_iop___pb2___width 1
-#define reg_pinmux_rw_pb_iop___pb2___bit 2
-#define reg_pinmux_rw_pb_iop___pb3___lsb 3
-#define reg_pinmux_rw_pb_iop___pb3___width 1
-#define reg_pinmux_rw_pb_iop___pb3___bit 3
-#define reg_pinmux_rw_pb_iop___pb4___lsb 4
-#define reg_pinmux_rw_pb_iop___pb4___width 1
-#define reg_pinmux_rw_pb_iop___pb4___bit 4
-#define reg_pinmux_rw_pb_iop___pb5___lsb 5
-#define reg_pinmux_rw_pb_iop___pb5___width 1
-#define reg_pinmux_rw_pb_iop___pb5___bit 5
-#define reg_pinmux_rw_pb_iop___pb6___lsb 6
-#define reg_pinmux_rw_pb_iop___pb6___width 1
-#define reg_pinmux_rw_pb_iop___pb6___bit 6
-#define reg_pinmux_rw_pb_iop___pb7___lsb 7
-#define reg_pinmux_rw_pb_iop___pb7___width 1
-#define reg_pinmux_rw_pb_iop___pb7___bit 7
-#define reg_pinmux_rw_pb_iop___pb8___lsb 8
-#define reg_pinmux_rw_pb_iop___pb8___width 1
-#define reg_pinmux_rw_pb_iop___pb8___bit 8
-#define reg_pinmux_rw_pb_iop___pb9___lsb 9
-#define reg_pinmux_rw_pb_iop___pb9___width 1
-#define reg_pinmux_rw_pb_iop___pb9___bit 9
-#define reg_pinmux_rw_pb_iop___pb10___lsb 10
-#define reg_pinmux_rw_pb_iop___pb10___width 1
-#define reg_pinmux_rw_pb_iop___pb10___bit 10
-#define reg_pinmux_rw_pb_iop___pb11___lsb 11
-#define reg_pinmux_rw_pb_iop___pb11___width 1
-#define reg_pinmux_rw_pb_iop___pb11___bit 11
-#define reg_pinmux_rw_pb_iop___pb12___lsb 12
-#define reg_pinmux_rw_pb_iop___pb12___width 1
-#define reg_pinmux_rw_pb_iop___pb12___bit 12
-#define reg_pinmux_rw_pb_iop___pb13___lsb 13
-#define reg_pinmux_rw_pb_iop___pb13___width 1
-#define reg_pinmux_rw_pb_iop___pb13___bit 13
-#define reg_pinmux_rw_pb_iop___pb14___lsb 14
-#define reg_pinmux_rw_pb_iop___pb14___width 1
-#define reg_pinmux_rw_pb_iop___pb14___bit 14
-#define reg_pinmux_rw_pb_iop___pb15___lsb 15
-#define reg_pinmux_rw_pb_iop___pb15___width 1
-#define reg_pinmux_rw_pb_iop___pb15___bit 15
-#define reg_pinmux_rw_pb_iop___pb16___lsb 16
-#define reg_pinmux_rw_pb_iop___pb16___width 1
-#define reg_pinmux_rw_pb_iop___pb16___bit 16
-#define reg_pinmux_rw_pb_iop___pb17___lsb 17
-#define reg_pinmux_rw_pb_iop___pb17___width 1
-#define reg_pinmux_rw_pb_iop___pb17___bit 17
-#define reg_pinmux_rw_pb_iop_offset 12
-
-/* Register rw_pc_gio, scope pinmux, type rw */
-#define reg_pinmux_rw_pc_gio___pc0___lsb 0
-#define reg_pinmux_rw_pc_gio___pc0___width 1
-#define reg_pinmux_rw_pc_gio___pc0___bit 0
-#define reg_pinmux_rw_pc_gio___pc1___lsb 1
-#define reg_pinmux_rw_pc_gio___pc1___width 1
-#define reg_pinmux_rw_pc_gio___pc1___bit 1
-#define reg_pinmux_rw_pc_gio___pc2___lsb 2
-#define reg_pinmux_rw_pc_gio___pc2___width 1
-#define reg_pinmux_rw_pc_gio___pc2___bit 2
-#define reg_pinmux_rw_pc_gio___pc3___lsb 3
-#define reg_pinmux_rw_pc_gio___pc3___width 1
-#define reg_pinmux_rw_pc_gio___pc3___bit 3
-#define reg_pinmux_rw_pc_gio___pc4___lsb 4
-#define reg_pinmux_rw_pc_gio___pc4___width 1
-#define reg_pinmux_rw_pc_gio___pc4___bit 4
-#define reg_pinmux_rw_pc_gio___pc5___lsb 5
-#define reg_pinmux_rw_pc_gio___pc5___width 1
-#define reg_pinmux_rw_pc_gio___pc5___bit 5
-#define reg_pinmux_rw_pc_gio___pc6___lsb 6
-#define reg_pinmux_rw_pc_gio___pc6___width 1
-#define reg_pinmux_rw_pc_gio___pc6___bit 6
-#define reg_pinmux_rw_pc_gio___pc7___lsb 7
-#define reg_pinmux_rw_pc_gio___pc7___width 1
-#define reg_pinmux_rw_pc_gio___pc7___bit 7
-#define reg_pinmux_rw_pc_gio___pc8___lsb 8
-#define reg_pinmux_rw_pc_gio___pc8___width 1
-#define reg_pinmux_rw_pc_gio___pc8___bit 8
-#define reg_pinmux_rw_pc_gio___pc9___lsb 9
-#define reg_pinmux_rw_pc_gio___pc9___width 1
-#define reg_pinmux_rw_pc_gio___pc9___bit 9
-#define reg_pinmux_rw_pc_gio___pc10___lsb 10
-#define reg_pinmux_rw_pc_gio___pc10___width 1
-#define reg_pinmux_rw_pc_gio___pc10___bit 10
-#define reg_pinmux_rw_pc_gio___pc11___lsb 11
-#define reg_pinmux_rw_pc_gio___pc11___width 1
-#define reg_pinmux_rw_pc_gio___pc11___bit 11
-#define reg_pinmux_rw_pc_gio___pc12___lsb 12
-#define reg_pinmux_rw_pc_gio___pc12___width 1
-#define reg_pinmux_rw_pc_gio___pc12___bit 12
-#define reg_pinmux_rw_pc_gio___pc13___lsb 13
-#define reg_pinmux_rw_pc_gio___pc13___width 1
-#define reg_pinmux_rw_pc_gio___pc13___bit 13
-#define reg_pinmux_rw_pc_gio___pc14___lsb 14
-#define reg_pinmux_rw_pc_gio___pc14___width 1
-#define reg_pinmux_rw_pc_gio___pc14___bit 14
-#define reg_pinmux_rw_pc_gio___pc15___lsb 15
-#define reg_pinmux_rw_pc_gio___pc15___width 1
-#define reg_pinmux_rw_pc_gio___pc15___bit 15
-#define reg_pinmux_rw_pc_gio___pc16___lsb 16
-#define reg_pinmux_rw_pc_gio___pc16___width 1
-#define reg_pinmux_rw_pc_gio___pc16___bit 16
-#define reg_pinmux_rw_pc_gio___pc17___lsb 17
-#define reg_pinmux_rw_pc_gio___pc17___width 1
-#define reg_pinmux_rw_pc_gio___pc17___bit 17
-#define reg_pinmux_rw_pc_gio_offset 16
-
-/* Register rw_pc_iop, scope pinmux, type rw */
-#define reg_pinmux_rw_pc_iop___pc0___lsb 0
-#define reg_pinmux_rw_pc_iop___pc0___width 1
-#define reg_pinmux_rw_pc_iop___pc0___bit 0
-#define reg_pinmux_rw_pc_iop___pc1___lsb 1
-#define reg_pinmux_rw_pc_iop___pc1___width 1
-#define reg_pinmux_rw_pc_iop___pc1___bit 1
-#define reg_pinmux_rw_pc_iop___pc2___lsb 2
-#define reg_pinmux_rw_pc_iop___pc2___width 1
-#define reg_pinmux_rw_pc_iop___pc2___bit 2
-#define reg_pinmux_rw_pc_iop___pc3___lsb 3
-#define reg_pinmux_rw_pc_iop___pc3___width 1
-#define reg_pinmux_rw_pc_iop___pc3___bit 3
-#define reg_pinmux_rw_pc_iop___pc4___lsb 4
-#define reg_pinmux_rw_pc_iop___pc4___width 1
-#define reg_pinmux_rw_pc_iop___pc4___bit 4
-#define reg_pinmux_rw_pc_iop___pc5___lsb 5
-#define reg_pinmux_rw_pc_iop___pc5___width 1
-#define reg_pinmux_rw_pc_iop___pc5___bit 5
-#define reg_pinmux_rw_pc_iop___pc6___lsb 6
-#define reg_pinmux_rw_pc_iop___pc6___width 1
-#define reg_pinmux_rw_pc_iop___pc6___bit 6
-#define reg_pinmux_rw_pc_iop___pc7___lsb 7
-#define reg_pinmux_rw_pc_iop___pc7___width 1
-#define reg_pinmux_rw_pc_iop___pc7___bit 7
-#define reg_pinmux_rw_pc_iop___pc8___lsb 8
-#define reg_pinmux_rw_pc_iop___pc8___width 1
-#define reg_pinmux_rw_pc_iop___pc8___bit 8
-#define reg_pinmux_rw_pc_iop___pc9___lsb 9
-#define reg_pinmux_rw_pc_iop___pc9___width 1
-#define reg_pinmux_rw_pc_iop___pc9___bit 9
-#define reg_pinmux_rw_pc_iop___pc10___lsb 10
-#define reg_pinmux_rw_pc_iop___pc10___width 1
-#define reg_pinmux_rw_pc_iop___pc10___bit 10
-#define reg_pinmux_rw_pc_iop___pc11___lsb 11
-#define reg_pinmux_rw_pc_iop___pc11___width 1
-#define reg_pinmux_rw_pc_iop___pc11___bit 11
-#define reg_pinmux_rw_pc_iop___pc12___lsb 12
-#define reg_pinmux_rw_pc_iop___pc12___width 1
-#define reg_pinmux_rw_pc_iop___pc12___bit 12
-#define reg_pinmux_rw_pc_iop___pc13___lsb 13
-#define reg_pinmux_rw_pc_iop___pc13___width 1
-#define reg_pinmux_rw_pc_iop___pc13___bit 13
-#define reg_pinmux_rw_pc_iop___pc14___lsb 14
-#define reg_pinmux_rw_pc_iop___pc14___width 1
-#define reg_pinmux_rw_pc_iop___pc14___bit 14
-#define reg_pinmux_rw_pc_iop___pc15___lsb 15
-#define reg_pinmux_rw_pc_iop___pc15___width 1
-#define reg_pinmux_rw_pc_iop___pc15___bit 15
-#define reg_pinmux_rw_pc_iop___pc16___lsb 16
-#define reg_pinmux_rw_pc_iop___pc16___width 1
-#define reg_pinmux_rw_pc_iop___pc16___bit 16
-#define reg_pinmux_rw_pc_iop___pc17___lsb 17
-#define reg_pinmux_rw_pc_iop___pc17___width 1
-#define reg_pinmux_rw_pc_iop___pc17___bit 17
-#define reg_pinmux_rw_pc_iop_offset 20
-
-/* Register rw_pd_gio, scope pinmux, type rw */
-#define reg_pinmux_rw_pd_gio___pd0___lsb 0
-#define reg_pinmux_rw_pd_gio___pd0___width 1
-#define reg_pinmux_rw_pd_gio___pd0___bit 0
-#define reg_pinmux_rw_pd_gio___pd1___lsb 1
-#define reg_pinmux_rw_pd_gio___pd1___width 1
-#define reg_pinmux_rw_pd_gio___pd1___bit 1
-#define reg_pinmux_rw_pd_gio___pd2___lsb 2
-#define reg_pinmux_rw_pd_gio___pd2___width 1
-#define reg_pinmux_rw_pd_gio___pd2___bit 2
-#define reg_pinmux_rw_pd_gio___pd3___lsb 3
-#define reg_pinmux_rw_pd_gio___pd3___width 1
-#define reg_pinmux_rw_pd_gio___pd3___bit 3
-#define reg_pinmux_rw_pd_gio___pd4___lsb 4
-#define reg_pinmux_rw_pd_gio___pd4___width 1
-#define reg_pinmux_rw_pd_gio___pd4___bit 4
-#define reg_pinmux_rw_pd_gio___pd5___lsb 5
-#define reg_pinmux_rw_pd_gio___pd5___width 1
-#define reg_pinmux_rw_pd_gio___pd5___bit 5
-#define reg_pinmux_rw_pd_gio___pd6___lsb 6
-#define reg_pinmux_rw_pd_gio___pd6___width 1
-#define reg_pinmux_rw_pd_gio___pd6___bit 6
-#define reg_pinmux_rw_pd_gio___pd7___lsb 7
-#define reg_pinmux_rw_pd_gio___pd7___width 1
-#define reg_pinmux_rw_pd_gio___pd7___bit 7
-#define reg_pinmux_rw_pd_gio___pd8___lsb 8
-#define reg_pinmux_rw_pd_gio___pd8___width 1
-#define reg_pinmux_rw_pd_gio___pd8___bit 8
-#define reg_pinmux_rw_pd_gio___pd9___lsb 9
-#define reg_pinmux_rw_pd_gio___pd9___width 1
-#define reg_pinmux_rw_pd_gio___pd9___bit 9
-#define reg_pinmux_rw_pd_gio___pd10___lsb 10
-#define reg_pinmux_rw_pd_gio___pd10___width 1
-#define reg_pinmux_rw_pd_gio___pd10___bit 10
-#define reg_pinmux_rw_pd_gio___pd11___lsb 11
-#define reg_pinmux_rw_pd_gio___pd11___width 1
-#define reg_pinmux_rw_pd_gio___pd11___bit 11
-#define reg_pinmux_rw_pd_gio___pd12___lsb 12
-#define reg_pinmux_rw_pd_gio___pd12___width 1
-#define reg_pinmux_rw_pd_gio___pd12___bit 12
-#define reg_pinmux_rw_pd_gio___pd13___lsb 13
-#define reg_pinmux_rw_pd_gio___pd13___width 1
-#define reg_pinmux_rw_pd_gio___pd13___bit 13
-#define reg_pinmux_rw_pd_gio___pd14___lsb 14
-#define reg_pinmux_rw_pd_gio___pd14___width 1
-#define reg_pinmux_rw_pd_gio___pd14___bit 14
-#define reg_pinmux_rw_pd_gio___pd15___lsb 15
-#define reg_pinmux_rw_pd_gio___pd15___width 1
-#define reg_pinmux_rw_pd_gio___pd15___bit 15
-#define reg_pinmux_rw_pd_gio___pd16___lsb 16
-#define reg_pinmux_rw_pd_gio___pd16___width 1
-#define reg_pinmux_rw_pd_gio___pd16___bit 16
-#define reg_pinmux_rw_pd_gio___pd17___lsb 17
-#define reg_pinmux_rw_pd_gio___pd17___width 1
-#define reg_pinmux_rw_pd_gio___pd17___bit 17
-#define reg_pinmux_rw_pd_gio_offset 24
-
-/* Register rw_pd_iop, scope pinmux, type rw */
-#define reg_pinmux_rw_pd_iop___pd0___lsb 0
-#define reg_pinmux_rw_pd_iop___pd0___width 1
-#define reg_pinmux_rw_pd_iop___pd0___bit 0
-#define reg_pinmux_rw_pd_iop___pd1___lsb 1
-#define reg_pinmux_rw_pd_iop___pd1___width 1
-#define reg_pinmux_rw_pd_iop___pd1___bit 1
-#define reg_pinmux_rw_pd_iop___pd2___lsb 2
-#define reg_pinmux_rw_pd_iop___pd2___width 1
-#define reg_pinmux_rw_pd_iop___pd2___bit 2
-#define reg_pinmux_rw_pd_iop___pd3___lsb 3
-#define reg_pinmux_rw_pd_iop___pd3___width 1
-#define reg_pinmux_rw_pd_iop___pd3___bit 3
-#define reg_pinmux_rw_pd_iop___pd4___lsb 4
-#define reg_pinmux_rw_pd_iop___pd4___width 1
-#define reg_pinmux_rw_pd_iop___pd4___bit 4
-#define reg_pinmux_rw_pd_iop___pd5___lsb 5
-#define reg_pinmux_rw_pd_iop___pd5___width 1
-#define reg_pinmux_rw_pd_iop___pd5___bit 5
-#define reg_pinmux_rw_pd_iop___pd6___lsb 6
-#define reg_pinmux_rw_pd_iop___pd6___width 1
-#define reg_pinmux_rw_pd_iop___pd6___bit 6
-#define reg_pinmux_rw_pd_iop___pd7___lsb 7
-#define reg_pinmux_rw_pd_iop___pd7___width 1
-#define reg_pinmux_rw_pd_iop___pd7___bit 7
-#define reg_pinmux_rw_pd_iop___pd8___lsb 8
-#define reg_pinmux_rw_pd_iop___pd8___width 1
-#define reg_pinmux_rw_pd_iop___pd8___bit 8
-#define reg_pinmux_rw_pd_iop___pd9___lsb 9
-#define reg_pinmux_rw_pd_iop___pd9___width 1
-#define reg_pinmux_rw_pd_iop___pd9___bit 9
-#define reg_pinmux_rw_pd_iop___pd10___lsb 10
-#define reg_pinmux_rw_pd_iop___pd10___width 1
-#define reg_pinmux_rw_pd_iop___pd10___bit 10
-#define reg_pinmux_rw_pd_iop___pd11___lsb 11
-#define reg_pinmux_rw_pd_iop___pd11___width 1
-#define reg_pinmux_rw_pd_iop___pd11___bit 11
-#define reg_pinmux_rw_pd_iop___pd12___lsb 12
-#define reg_pinmux_rw_pd_iop___pd12___width 1
-#define reg_pinmux_rw_pd_iop___pd12___bit 12
-#define reg_pinmux_rw_pd_iop___pd13___lsb 13
-#define reg_pinmux_rw_pd_iop___pd13___width 1
-#define reg_pinmux_rw_pd_iop___pd13___bit 13
-#define reg_pinmux_rw_pd_iop___pd14___lsb 14
-#define reg_pinmux_rw_pd_iop___pd14___width 1
-#define reg_pinmux_rw_pd_iop___pd14___bit 14
-#define reg_pinmux_rw_pd_iop___pd15___lsb 15
-#define reg_pinmux_rw_pd_iop___pd15___width 1
-#define reg_pinmux_rw_pd_iop___pd15___bit 15
-#define reg_pinmux_rw_pd_iop___pd16___lsb 16
-#define reg_pinmux_rw_pd_iop___pd16___width 1
-#define reg_pinmux_rw_pd_iop___pd16___bit 16
-#define reg_pinmux_rw_pd_iop___pd17___lsb 17
-#define reg_pinmux_rw_pd_iop___pd17___width 1
-#define reg_pinmux_rw_pd_iop___pd17___bit 17
-#define reg_pinmux_rw_pd_iop_offset 28
-
-/* Register rw_pe_gio, scope pinmux, type rw */
-#define reg_pinmux_rw_pe_gio___pe0___lsb 0
-#define reg_pinmux_rw_pe_gio___pe0___width 1
-#define reg_pinmux_rw_pe_gio___pe0___bit 0
-#define reg_pinmux_rw_pe_gio___pe1___lsb 1
-#define reg_pinmux_rw_pe_gio___pe1___width 1
-#define reg_pinmux_rw_pe_gio___pe1___bit 1
-#define reg_pinmux_rw_pe_gio___pe2___lsb 2
-#define reg_pinmux_rw_pe_gio___pe2___width 1
-#define reg_pinmux_rw_pe_gio___pe2___bit 2
-#define reg_pinmux_rw_pe_gio___pe3___lsb 3
-#define reg_pinmux_rw_pe_gio___pe3___width 1
-#define reg_pinmux_rw_pe_gio___pe3___bit 3
-#define reg_pinmux_rw_pe_gio___pe4___lsb 4
-#define reg_pinmux_rw_pe_gio___pe4___width 1
-#define reg_pinmux_rw_pe_gio___pe4___bit 4
-#define reg_pinmux_rw_pe_gio___pe5___lsb 5
-#define reg_pinmux_rw_pe_gio___pe5___width 1
-#define reg_pinmux_rw_pe_gio___pe5___bit 5
-#define reg_pinmux_rw_pe_gio___pe6___lsb 6
-#define reg_pinmux_rw_pe_gio___pe6___width 1
-#define reg_pinmux_rw_pe_gio___pe6___bit 6
-#define reg_pinmux_rw_pe_gio___pe7___lsb 7
-#define reg_pinmux_rw_pe_gio___pe7___width 1
-#define reg_pinmux_rw_pe_gio___pe7___bit 7
-#define reg_pinmux_rw_pe_gio___pe8___lsb 8
-#define reg_pinmux_rw_pe_gio___pe8___width 1
-#define reg_pinmux_rw_pe_gio___pe8___bit 8
-#define reg_pinmux_rw_pe_gio___pe9___lsb 9
-#define reg_pinmux_rw_pe_gio___pe9___width 1
-#define reg_pinmux_rw_pe_gio___pe9___bit 9
-#define reg_pinmux_rw_pe_gio___pe10___lsb 10
-#define reg_pinmux_rw_pe_gio___pe10___width 1
-#define reg_pinmux_rw_pe_gio___pe10___bit 10
-#define reg_pinmux_rw_pe_gio___pe11___lsb 11
-#define reg_pinmux_rw_pe_gio___pe11___width 1
-#define reg_pinmux_rw_pe_gio___pe11___bit 11
-#define reg_pinmux_rw_pe_gio___pe12___lsb 12
-#define reg_pinmux_rw_pe_gio___pe12___width 1
-#define reg_pinmux_rw_pe_gio___pe12___bit 12
-#define reg_pinmux_rw_pe_gio___pe13___lsb 13
-#define reg_pinmux_rw_pe_gio___pe13___width 1
-#define reg_pinmux_rw_pe_gio___pe13___bit 13
-#define reg_pinmux_rw_pe_gio___pe14___lsb 14
-#define reg_pinmux_rw_pe_gio___pe14___width 1
-#define reg_pinmux_rw_pe_gio___pe14___bit 14
-#define reg_pinmux_rw_pe_gio___pe15___lsb 15
-#define reg_pinmux_rw_pe_gio___pe15___width 1
-#define reg_pinmux_rw_pe_gio___pe15___bit 15
-#define reg_pinmux_rw_pe_gio___pe16___lsb 16
-#define reg_pinmux_rw_pe_gio___pe16___width 1
-#define reg_pinmux_rw_pe_gio___pe16___bit 16
-#define reg_pinmux_rw_pe_gio___pe17___lsb 17
-#define reg_pinmux_rw_pe_gio___pe17___width 1
-#define reg_pinmux_rw_pe_gio___pe17___bit 17
-#define reg_pinmux_rw_pe_gio_offset 32
-
-/* Register rw_pe_iop, scope pinmux, type rw */
-#define reg_pinmux_rw_pe_iop___pe0___lsb 0
-#define reg_pinmux_rw_pe_iop___pe0___width 1
-#define reg_pinmux_rw_pe_iop___pe0___bit 0
-#define reg_pinmux_rw_pe_iop___pe1___lsb 1
-#define reg_pinmux_rw_pe_iop___pe1___width 1
-#define reg_pinmux_rw_pe_iop___pe1___bit 1
-#define reg_pinmux_rw_pe_iop___pe2___lsb 2
-#define reg_pinmux_rw_pe_iop___pe2___width 1
-#define reg_pinmux_rw_pe_iop___pe2___bit 2
-#define reg_pinmux_rw_pe_iop___pe3___lsb 3
-#define reg_pinmux_rw_pe_iop___pe3___width 1
-#define reg_pinmux_rw_pe_iop___pe3___bit 3
-#define reg_pinmux_rw_pe_iop___pe4___lsb 4
-#define reg_pinmux_rw_pe_iop___pe4___width 1
-#define reg_pinmux_rw_pe_iop___pe4___bit 4
-#define reg_pinmux_rw_pe_iop___pe5___lsb 5
-#define reg_pinmux_rw_pe_iop___pe5___width 1
-#define reg_pinmux_rw_pe_iop___pe5___bit 5
-#define reg_pinmux_rw_pe_iop___pe6___lsb 6
-#define reg_pinmux_rw_pe_iop___pe6___width 1
-#define reg_pinmux_rw_pe_iop___pe6___bit 6
-#define reg_pinmux_rw_pe_iop___pe7___lsb 7
-#define reg_pinmux_rw_pe_iop___pe7___width 1
-#define reg_pinmux_rw_pe_iop___pe7___bit 7
-#define reg_pinmux_rw_pe_iop___pe8___lsb 8
-#define reg_pinmux_rw_pe_iop___pe8___width 1
-#define reg_pinmux_rw_pe_iop___pe8___bit 8
-#define reg_pinmux_rw_pe_iop___pe9___lsb 9
-#define reg_pinmux_rw_pe_iop___pe9___width 1
-#define reg_pinmux_rw_pe_iop___pe9___bit 9
-#define reg_pinmux_rw_pe_iop___pe10___lsb 10
-#define reg_pinmux_rw_pe_iop___pe10___width 1
-#define reg_pinmux_rw_pe_iop___pe10___bit 10
-#define reg_pinmux_rw_pe_iop___pe11___lsb 11
-#define reg_pinmux_rw_pe_iop___pe11___width 1
-#define reg_pinmux_rw_pe_iop___pe11___bit 11
-#define reg_pinmux_rw_pe_iop___pe12___lsb 12
-#define reg_pinmux_rw_pe_iop___pe12___width 1
-#define reg_pinmux_rw_pe_iop___pe12___bit 12
-#define reg_pinmux_rw_pe_iop___pe13___lsb 13
-#define reg_pinmux_rw_pe_iop___pe13___width 1
-#define reg_pinmux_rw_pe_iop___pe13___bit 13
-#define reg_pinmux_rw_pe_iop___pe14___lsb 14
-#define reg_pinmux_rw_pe_iop___pe14___width 1
-#define reg_pinmux_rw_pe_iop___pe14___bit 14
-#define reg_pinmux_rw_pe_iop___pe15___lsb 15
-#define reg_pinmux_rw_pe_iop___pe15___width 1
-#define reg_pinmux_rw_pe_iop___pe15___bit 15
-#define reg_pinmux_rw_pe_iop___pe16___lsb 16
-#define reg_pinmux_rw_pe_iop___pe16___width 1
-#define reg_pinmux_rw_pe_iop___pe16___bit 16
-#define reg_pinmux_rw_pe_iop___pe17___lsb 17
-#define reg_pinmux_rw_pe_iop___pe17___width 1
-#define reg_pinmux_rw_pe_iop___pe17___bit 17
-#define reg_pinmux_rw_pe_iop_offset 36
-
-/* Register rw_usb_phy, scope pinmux, type rw */
-#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0
-#define reg_pinmux_rw_usb_phy___en_usb0___width 1
-#define reg_pinmux_rw_usb_phy___en_usb0___bit 0
-#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1
-#define reg_pinmux_rw_usb_phy___en_usb1___width 1
-#define reg_pinmux_rw_usb_phy___en_usb1___bit 1
-#define reg_pinmux_rw_usb_phy_offset 40
-
-
-/* Constants */
-#define regk_pinmux_no                            0x00000000
-#define regk_pinmux_rw_hwprot_default             0x00000000
-#define regk_pinmux_rw_pa_default                 0x00000000
-#define regk_pinmux_rw_pb_gio_default             0x00000000
-#define regk_pinmux_rw_pb_iop_default             0x00000000
-#define regk_pinmux_rw_pc_gio_default             0x00000000
-#define regk_pinmux_rw_pc_iop_default             0x00000000
-#define regk_pinmux_rw_pd_gio_default             0x00000000
-#define regk_pinmux_rw_pd_iop_default             0x00000000
-#define regk_pinmux_rw_pe_gio_default             0x00000000
-#define regk_pinmux_rw_pe_iop_default             0x00000000
-#define regk_pinmux_rw_usb_phy_default            0x00000000
-#define regk_pinmux_yes                           0x00000001
-#endif /* __pinmux_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h
deleted file mode 100644
index 76959b70cd2c..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h
+++ /dev/null
@@ -1,96 +0,0 @@
-#ifndef __reg_map_h
-#define __reg_map_h
-
-/*
- * This file is autogenerated from
- *   file:            ../../mod/fakereg.rmap
- *     id:            fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
- *     last modified: Wed Feb 11 20:53:25 2004
- *   file:            ../../rtl/global.rmap
- *     id:            global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
- *     last modified: Mon Aug 18 17:08:23 2003
- *   file:            ../../mod/modreg.rmap
- *     id:            modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
- *     last modified: Fri Feb 20 16:40:04 2004
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
- *      id: $Id: reg_map_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-#define regi_artpec_mod                           0xb7044000
-#define regi_ata                                  0xb0032000
-#define regi_ata_mod                              0xb7006000
-#define regi_barber                               0xb701a000
-#define regi_bif_core                             0xb0014000
-#define regi_bif_dma                              0xb0016000
-#define regi_bif_slave                            0xb0018000
-#define regi_bif_slave_ext                        0xac000000
-#define regi_bus_master                           0xb703c000
-#define regi_config                               0xb003c000
-#define regi_dma0                                 0xb0000000
-#define regi_dma1                                 0xb0002000
-#define regi_dma2                                 0xb0004000
-#define regi_dma3                                 0xb0006000
-#define regi_dma4                                 0xb0008000
-#define regi_dma5                                 0xb000a000
-#define regi_dma6                                 0xb000c000
-#define regi_dma7                                 0xb000e000
-#define regi_dma8                                 0xb0010000
-#define regi_dma9                                 0xb0012000
-#define regi_eth0                                 0xb0034000
-#define regi_eth1                                 0xb0036000
-#define regi_eth_mod                              0xb7004000
-#define regi_eth_mod1                             0xb701c000
-#define regi_eth_strmod                           0xb7008000
-#define regi_eth_strmod1                          0xb7032000
-#define regi_ext_dma                              0xb703a000
-#define regi_ext_mem                              0xb7046000
-#define regi_gen_io                               0xb7016000
-#define regi_gio                                  0xb001a000
-#define regi_hook                                 0xb7000000
-#define regi_iop                                  0xb0020000
-#define regi_irq                                  0xb001c000
-#define regi_irq_nmi                              0xb701e000
-#define regi_marb                                 0xb003e000
-#define regi_marb_bp0                             0xb003e240
-#define regi_marb_bp1                             0xb003e280
-#define regi_marb_bp2                             0xb003e2c0
-#define regi_marb_bp3                             0xb003e300
-#define regi_nand_mod                             0xb7014000
-#define regi_p21                                  0xb002e000
-#define regi_p21_mod                              0xb7042000
-#define regi_pci_mod                              0xb7010000
-#define regi_pin_test                             0xb7018000
-#define regi_pinmux                               0xb0038000
-#define regi_sdram_chk                            0xb703e000
-#define regi_sdram_mod                            0xb7012000
-#define regi_ser0                                 0xb0026000
-#define regi_ser1                                 0xb0028000
-#define regi_ser2                                 0xb002a000
-#define regi_ser3                                 0xb002c000
-#define regi_ser_mod0                             0xb7020000
-#define regi_ser_mod1                             0xb7022000
-#define regi_ser_mod2                             0xb7024000
-#define regi_ser_mod3                             0xb7026000
-#define regi_smif_stat                            0xb700e000
-#define regi_sser0                                0xb0022000
-#define regi_sser1                                0xb0024000
-#define regi_sser_mod0                            0xb700a000
-#define regi_sser_mod1                            0xb700c000
-#define regi_strcop                               0xb0030000
-#define regi_strmux                               0xb003a000
-#define regi_strmux_tst                           0xb7040000
-#define regi_tap                                  0xb7002000
-#define regi_timer                                0xb001e000
-#define regi_timer_mod                            0xb7034000
-#define regi_trace                                0xb0040000
-#define regi_usb0                                 0xb7028000
-#define regi_usb1                                 0xb702a000
-#define regi_usb2                                 0xb702c000
-#define regi_usb3                                 0xb702e000
-#define regi_usb_dev                              0xb7030000
-#define regi_utmi_mod0                            0xb7036000
-#define regi_utmi_mod1                            0xb7038000
-#endif /* __reg_map_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h
deleted file mode 100644
index 10246f49fb28..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h
+++ /dev/null
@@ -1,142 +0,0 @@
-#ifndef __rt_trace_defs_asm_h
-#define __rt_trace_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/rt_trace/rtl/rt_regs.r
- *     id:           rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp
- *     last modfied: Mon Apr 11 16:09:14 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/rt_trace_defs_asm.h ../../inst/rt_trace/rtl/rt_regs.r
- *      id: $Id: rt_trace_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope rt_trace, type rw */
-#define reg_rt_trace_rw_cfg___en___lsb 0
-#define reg_rt_trace_rw_cfg___en___width 1
-#define reg_rt_trace_rw_cfg___en___bit 0
-#define reg_rt_trace_rw_cfg___mode___lsb 1
-#define reg_rt_trace_rw_cfg___mode___width 1
-#define reg_rt_trace_rw_cfg___mode___bit 1
-#define reg_rt_trace_rw_cfg___owner___lsb 2
-#define reg_rt_trace_rw_cfg___owner___width 1
-#define reg_rt_trace_rw_cfg___owner___bit 2
-#define reg_rt_trace_rw_cfg___wp___lsb 3
-#define reg_rt_trace_rw_cfg___wp___width 1
-#define reg_rt_trace_rw_cfg___wp___bit 3
-#define reg_rt_trace_rw_cfg___stall___lsb 4
-#define reg_rt_trace_rw_cfg___stall___width 1
-#define reg_rt_trace_rw_cfg___stall___bit 4
-#define reg_rt_trace_rw_cfg___wp_start___lsb 8
-#define reg_rt_trace_rw_cfg___wp_start___width 7
-#define reg_rt_trace_rw_cfg___wp_stop___lsb 16
-#define reg_rt_trace_rw_cfg___wp_stop___width 7
-#define reg_rt_trace_rw_cfg_offset 0
-
-/* Register rw_tap_ctrl, scope rt_trace, type rw */
-#define reg_rt_trace_rw_tap_ctrl___ack_data___lsb 0
-#define reg_rt_trace_rw_tap_ctrl___ack_data___width 1
-#define reg_rt_trace_rw_tap_ctrl___ack_data___bit 0
-#define reg_rt_trace_rw_tap_ctrl___ack_guru___lsb 1
-#define reg_rt_trace_rw_tap_ctrl___ack_guru___width 1
-#define reg_rt_trace_rw_tap_ctrl___ack_guru___bit 1
-#define reg_rt_trace_rw_tap_ctrl_offset 4
-
-/* Register r_tap_stat, scope rt_trace, type r */
-#define reg_rt_trace_r_tap_stat___dav___lsb 0
-#define reg_rt_trace_r_tap_stat___dav___width 1
-#define reg_rt_trace_r_tap_stat___dav___bit 0
-#define reg_rt_trace_r_tap_stat___empty___lsb 1
-#define reg_rt_trace_r_tap_stat___empty___width 1
-#define reg_rt_trace_r_tap_stat___empty___bit 1
-#define reg_rt_trace_r_tap_stat_offset 8
-
-/* Register rw_tap_data, scope rt_trace, type rw */
-#define reg_rt_trace_rw_tap_data_offset 12
-
-/* Register rw_tap_hdata, scope rt_trace, type rw */
-#define reg_rt_trace_rw_tap_hdata___op___lsb 0
-#define reg_rt_trace_rw_tap_hdata___op___width 4
-#define reg_rt_trace_rw_tap_hdata___sub_op___lsb 4
-#define reg_rt_trace_rw_tap_hdata___sub_op___width 4
-#define reg_rt_trace_rw_tap_hdata_offset 16
-
-/* Register r_redir, scope rt_trace, type r */
-#define reg_rt_trace_r_redir_offset 20
-
-
-/* Constants */
-#define regk_rt_trace_brk                         0x0000000c
-#define regk_rt_trace_dbg                         0x00000003
-#define regk_rt_trace_dbgdi                       0x00000004
-#define regk_rt_trace_dbgdo                       0x00000005
-#define regk_rt_trace_gmode                       0x00000000
-#define regk_rt_trace_no                          0x00000000
-#define regk_rt_trace_nop                         0x00000000
-#define regk_rt_trace_normal                      0x00000000
-#define regk_rt_trace_rdmem                       0x00000007
-#define regk_rt_trace_rdmemb                      0x00000009
-#define regk_rt_trace_rdpreg                      0x00000002
-#define regk_rt_trace_rdreg                       0x00000001
-#define regk_rt_trace_rdsreg                      0x00000003
-#define regk_rt_trace_redir                       0x00000006
-#define regk_rt_trace_ret                         0x0000000b
-#define regk_rt_trace_rw_cfg_default              0x00000000
-#define regk_rt_trace_trcfg                       0x00000001
-#define regk_rt_trace_wp                          0x00000001
-#define regk_rt_trace_wp0                         0x00000001
-#define regk_rt_trace_wp1                         0x00000002
-#define regk_rt_trace_wp2                         0x00000004
-#define regk_rt_trace_wp3                         0x00000008
-#define regk_rt_trace_wp4                         0x00000010
-#define regk_rt_trace_wp5                         0x00000020
-#define regk_rt_trace_wp6                         0x00000040
-#define regk_rt_trace_wrmem                       0x00000008
-#define regk_rt_trace_wrmemb                      0x0000000a
-#define regk_rt_trace_wrpreg                      0x00000005
-#define regk_rt_trace_wrreg                       0x00000004
-#define regk_rt_trace_wrsreg                      0x00000006
-#define regk_rt_trace_yes                         0x00000001
-#endif /* __rt_trace_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h
deleted file mode 100644
index 4a2808bdf390..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h
+++ /dev/null
@@ -1,359 +0,0 @@
-#ifndef __ser_defs_asm_h
-#define __ser_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/ser/rtl/ser_regs.r
- *     id:           ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp
- *     last modfied: Mon Apr 11 16:09:21 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ser_defs_asm.h ../../inst/ser/rtl/ser_regs.r
- *      id: $Id: ser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_tr_ctrl, scope ser, type rw */
-#define reg_ser_rw_tr_ctrl___base_freq___lsb 0
-#define reg_ser_rw_tr_ctrl___base_freq___width 3
-#define reg_ser_rw_tr_ctrl___en___lsb 3
-#define reg_ser_rw_tr_ctrl___en___width 1
-#define reg_ser_rw_tr_ctrl___en___bit 3
-#define reg_ser_rw_tr_ctrl___par___lsb 4
-#define reg_ser_rw_tr_ctrl___par___width 2
-#define reg_ser_rw_tr_ctrl___par_en___lsb 6
-#define reg_ser_rw_tr_ctrl___par_en___width 1
-#define reg_ser_rw_tr_ctrl___par_en___bit 6
-#define reg_ser_rw_tr_ctrl___data_bits___lsb 7
-#define reg_ser_rw_tr_ctrl___data_bits___width 1
-#define reg_ser_rw_tr_ctrl___data_bits___bit 7
-#define reg_ser_rw_tr_ctrl___stop_bits___lsb 8
-#define reg_ser_rw_tr_ctrl___stop_bits___width 1
-#define reg_ser_rw_tr_ctrl___stop_bits___bit 8
-#define reg_ser_rw_tr_ctrl___stop___lsb 9
-#define reg_ser_rw_tr_ctrl___stop___width 1
-#define reg_ser_rw_tr_ctrl___stop___bit 9
-#define reg_ser_rw_tr_ctrl___rts_delay___lsb 10
-#define reg_ser_rw_tr_ctrl___rts_delay___width 3
-#define reg_ser_rw_tr_ctrl___rts_setup___lsb 13
-#define reg_ser_rw_tr_ctrl___rts_setup___width 1
-#define reg_ser_rw_tr_ctrl___rts_setup___bit 13
-#define reg_ser_rw_tr_ctrl___auto_rts___lsb 14
-#define reg_ser_rw_tr_ctrl___auto_rts___width 1
-#define reg_ser_rw_tr_ctrl___auto_rts___bit 14
-#define reg_ser_rw_tr_ctrl___txd___lsb 15
-#define reg_ser_rw_tr_ctrl___txd___width 1
-#define reg_ser_rw_tr_ctrl___txd___bit 15
-#define reg_ser_rw_tr_ctrl___auto_cts___lsb 16
-#define reg_ser_rw_tr_ctrl___auto_cts___width 1
-#define reg_ser_rw_tr_ctrl___auto_cts___bit 16
-#define reg_ser_rw_tr_ctrl_offset 0
-
-/* Register rw_tr_dma_en, scope ser, type rw */
-#define reg_ser_rw_tr_dma_en___en___lsb 0
-#define reg_ser_rw_tr_dma_en___en___width 1
-#define reg_ser_rw_tr_dma_en___en___bit 0
-#define reg_ser_rw_tr_dma_en_offset 4
-
-/* Register rw_rec_ctrl, scope ser, type rw */
-#define reg_ser_rw_rec_ctrl___base_freq___lsb 0
-#define reg_ser_rw_rec_ctrl___base_freq___width 3
-#define reg_ser_rw_rec_ctrl___en___lsb 3
-#define reg_ser_rw_rec_ctrl___en___width 1
-#define reg_ser_rw_rec_ctrl___en___bit 3
-#define reg_ser_rw_rec_ctrl___par___lsb 4
-#define reg_ser_rw_rec_ctrl___par___width 2
-#define reg_ser_rw_rec_ctrl___par_en___lsb 6
-#define reg_ser_rw_rec_ctrl___par_en___width 1
-#define reg_ser_rw_rec_ctrl___par_en___bit 6
-#define reg_ser_rw_rec_ctrl___data_bits___lsb 7
-#define reg_ser_rw_rec_ctrl___data_bits___width 1
-#define reg_ser_rw_rec_ctrl___data_bits___bit 7
-#define reg_ser_rw_rec_ctrl___dma_mode___lsb 8
-#define reg_ser_rw_rec_ctrl___dma_mode___width 1
-#define reg_ser_rw_rec_ctrl___dma_mode___bit 8
-#define reg_ser_rw_rec_ctrl___dma_err___lsb 9
-#define reg_ser_rw_rec_ctrl___dma_err___width 1
-#define reg_ser_rw_rec_ctrl___dma_err___bit 9
-#define reg_ser_rw_rec_ctrl___sampling___lsb 10
-#define reg_ser_rw_rec_ctrl___sampling___width 1
-#define reg_ser_rw_rec_ctrl___sampling___bit 10
-#define reg_ser_rw_rec_ctrl___timeout___lsb 11
-#define reg_ser_rw_rec_ctrl___timeout___width 3
-#define reg_ser_rw_rec_ctrl___auto_eop___lsb 14
-#define reg_ser_rw_rec_ctrl___auto_eop___width 1
-#define reg_ser_rw_rec_ctrl___auto_eop___bit 14
-#define reg_ser_rw_rec_ctrl___half_duplex___lsb 15
-#define reg_ser_rw_rec_ctrl___half_duplex___width 1
-#define reg_ser_rw_rec_ctrl___half_duplex___bit 15
-#define reg_ser_rw_rec_ctrl___rts_n___lsb 16
-#define reg_ser_rw_rec_ctrl___rts_n___width 1
-#define reg_ser_rw_rec_ctrl___rts_n___bit 16
-#define reg_ser_rw_rec_ctrl___loopback___lsb 17
-#define reg_ser_rw_rec_ctrl___loopback___width 1
-#define reg_ser_rw_rec_ctrl___loopback___bit 17
-#define reg_ser_rw_rec_ctrl_offset 8
-
-/* Register rw_tr_baud_div, scope ser, type rw */
-#define reg_ser_rw_tr_baud_div___div___lsb 0
-#define reg_ser_rw_tr_baud_div___div___width 16
-#define reg_ser_rw_tr_baud_div_offset 12
-
-/* Register rw_rec_baud_div, scope ser, type rw */
-#define reg_ser_rw_rec_baud_div___div___lsb 0
-#define reg_ser_rw_rec_baud_div___div___width 16
-#define reg_ser_rw_rec_baud_div_offset 16
-
-/* Register rw_xoff, scope ser, type rw */
-#define reg_ser_rw_xoff___chr___lsb 0
-#define reg_ser_rw_xoff___chr___width 8
-#define reg_ser_rw_xoff___automatic___lsb 8
-#define reg_ser_rw_xoff___automatic___width 1
-#define reg_ser_rw_xoff___automatic___bit 8
-#define reg_ser_rw_xoff_offset 20
-
-/* Register rw_xoff_clr, scope ser, type rw */
-#define reg_ser_rw_xoff_clr___clr___lsb 0
-#define reg_ser_rw_xoff_clr___clr___width 1
-#define reg_ser_rw_xoff_clr___clr___bit 0
-#define reg_ser_rw_xoff_clr_offset 24
-
-/* Register rw_dout, scope ser, type rw */
-#define reg_ser_rw_dout___data___lsb 0
-#define reg_ser_rw_dout___data___width 8
-#define reg_ser_rw_dout_offset 28
-
-/* Register rs_stat_din, scope ser, type rs */
-#define reg_ser_rs_stat_din___data___lsb 0
-#define reg_ser_rs_stat_din___data___width 8
-#define reg_ser_rs_stat_din___dav___lsb 16
-#define reg_ser_rs_stat_din___dav___width 1
-#define reg_ser_rs_stat_din___dav___bit 16
-#define reg_ser_rs_stat_din___framing_err___lsb 17
-#define reg_ser_rs_stat_din___framing_err___width 1
-#define reg_ser_rs_stat_din___framing_err___bit 17
-#define reg_ser_rs_stat_din___par_err___lsb 18
-#define reg_ser_rs_stat_din___par_err___width 1
-#define reg_ser_rs_stat_din___par_err___bit 18
-#define reg_ser_rs_stat_din___orun___lsb 19
-#define reg_ser_rs_stat_din___orun___width 1
-#define reg_ser_rs_stat_din___orun___bit 19
-#define reg_ser_rs_stat_din___rec_err___lsb 20
-#define reg_ser_rs_stat_din___rec_err___width 1
-#define reg_ser_rs_stat_din___rec_err___bit 20
-#define reg_ser_rs_stat_din___rxd___lsb 21
-#define reg_ser_rs_stat_din___rxd___width 1
-#define reg_ser_rs_stat_din___rxd___bit 21
-#define reg_ser_rs_stat_din___tr_idle___lsb 22
-#define reg_ser_rs_stat_din___tr_idle___width 1
-#define reg_ser_rs_stat_din___tr_idle___bit 22
-#define reg_ser_rs_stat_din___tr_empty___lsb 23
-#define reg_ser_rs_stat_din___tr_empty___width 1
-#define reg_ser_rs_stat_din___tr_empty___bit 23
-#define reg_ser_rs_stat_din___tr_rdy___lsb 24
-#define reg_ser_rs_stat_din___tr_rdy___width 1
-#define reg_ser_rs_stat_din___tr_rdy___bit 24
-#define reg_ser_rs_stat_din___cts_n___lsb 25
-#define reg_ser_rs_stat_din___cts_n___width 1
-#define reg_ser_rs_stat_din___cts_n___bit 25
-#define reg_ser_rs_stat_din___xoff_detect___lsb 26
-#define reg_ser_rs_stat_din___xoff_detect___width 1
-#define reg_ser_rs_stat_din___xoff_detect___bit 26
-#define reg_ser_rs_stat_din___rts_n___lsb 27
-#define reg_ser_rs_stat_din___rts_n___width 1
-#define reg_ser_rs_stat_din___rts_n___bit 27
-#define reg_ser_rs_stat_din___txd___lsb 28
-#define reg_ser_rs_stat_din___txd___width 1
-#define reg_ser_rs_stat_din___txd___bit 28
-#define reg_ser_rs_stat_din_offset 32
-
-/* Register r_stat_din, scope ser, type r */
-#define reg_ser_r_stat_din___data___lsb 0
-#define reg_ser_r_stat_din___data___width 8
-#define reg_ser_r_stat_din___dav___lsb 16
-#define reg_ser_r_stat_din___dav___width 1
-#define reg_ser_r_stat_din___dav___bit 16
-#define reg_ser_r_stat_din___framing_err___lsb 17
-#define reg_ser_r_stat_din___framing_err___width 1
-#define reg_ser_r_stat_din___framing_err___bit 17
-#define reg_ser_r_stat_din___par_err___lsb 18
-#define reg_ser_r_stat_din___par_err___width 1
-#define reg_ser_r_stat_din___par_err___bit 18
-#define reg_ser_r_stat_din___orun___lsb 19
-#define reg_ser_r_stat_din___orun___width 1
-#define reg_ser_r_stat_din___orun___bit 19
-#define reg_ser_r_stat_din___rec_err___lsb 20
-#define reg_ser_r_stat_din___rec_err___width 1
-#define reg_ser_r_stat_din___rec_err___bit 20
-#define reg_ser_r_stat_din___rxd___lsb 21
-#define reg_ser_r_stat_din___rxd___width 1
-#define reg_ser_r_stat_din___rxd___bit 21
-#define reg_ser_r_stat_din___tr_idle___lsb 22
-#define reg_ser_r_stat_din___tr_idle___width 1
-#define reg_ser_r_stat_din___tr_idle___bit 22
-#define reg_ser_r_stat_din___tr_empty___lsb 23
-#define reg_ser_r_stat_din___tr_empty___width 1
-#define reg_ser_r_stat_din___tr_empty___bit 23
-#define reg_ser_r_stat_din___tr_rdy___lsb 24
-#define reg_ser_r_stat_din___tr_rdy___width 1
-#define reg_ser_r_stat_din___tr_rdy___bit 24
-#define reg_ser_r_stat_din___cts_n___lsb 25
-#define reg_ser_r_stat_din___cts_n___width 1
-#define reg_ser_r_stat_din___cts_n___bit 25
-#define reg_ser_r_stat_din___xoff_detect___lsb 26
-#define reg_ser_r_stat_din___xoff_detect___width 1
-#define reg_ser_r_stat_din___xoff_detect___bit 26
-#define reg_ser_r_stat_din___rts_n___lsb 27
-#define reg_ser_r_stat_din___rts_n___width 1
-#define reg_ser_r_stat_din___rts_n___bit 27
-#define reg_ser_r_stat_din___txd___lsb 28
-#define reg_ser_r_stat_din___txd___width 1
-#define reg_ser_r_stat_din___txd___bit 28
-#define reg_ser_r_stat_din_offset 36
-
-/* Register rw_rec_eop, scope ser, type rw */
-#define reg_ser_rw_rec_eop___set___lsb 0
-#define reg_ser_rw_rec_eop___set___width 1
-#define reg_ser_rw_rec_eop___set___bit 0
-#define reg_ser_rw_rec_eop_offset 40
-
-/* Register rw_intr_mask, scope ser, type rw */
-#define reg_ser_rw_intr_mask___tr_rdy___lsb 0
-#define reg_ser_rw_intr_mask___tr_rdy___width 1
-#define reg_ser_rw_intr_mask___tr_rdy___bit 0
-#define reg_ser_rw_intr_mask___tr_empty___lsb 1
-#define reg_ser_rw_intr_mask___tr_empty___width 1
-#define reg_ser_rw_intr_mask___tr_empty___bit 1
-#define reg_ser_rw_intr_mask___tr_idle___lsb 2
-#define reg_ser_rw_intr_mask___tr_idle___width 1
-#define reg_ser_rw_intr_mask___tr_idle___bit 2
-#define reg_ser_rw_intr_mask___dav___lsb 3
-#define reg_ser_rw_intr_mask___dav___width 1
-#define reg_ser_rw_intr_mask___dav___bit 3
-#define reg_ser_rw_intr_mask_offset 44
-
-/* Register rw_ack_intr, scope ser, type rw */
-#define reg_ser_rw_ack_intr___tr_rdy___lsb 0
-#define reg_ser_rw_ack_intr___tr_rdy___width 1
-#define reg_ser_rw_ack_intr___tr_rdy___bit 0
-#define reg_ser_rw_ack_intr___tr_empty___lsb 1
-#define reg_ser_rw_ack_intr___tr_empty___width 1
-#define reg_ser_rw_ack_intr___tr_empty___bit 1
-#define reg_ser_rw_ack_intr___tr_idle___lsb 2
-#define reg_ser_rw_ack_intr___tr_idle___width 1
-#define reg_ser_rw_ack_intr___tr_idle___bit 2
-#define reg_ser_rw_ack_intr___dav___lsb 3
-#define reg_ser_rw_ack_intr___dav___width 1
-#define reg_ser_rw_ack_intr___dav___bit 3
-#define reg_ser_rw_ack_intr_offset 48
-
-/* Register r_intr, scope ser, type r */
-#define reg_ser_r_intr___tr_rdy___lsb 0
-#define reg_ser_r_intr___tr_rdy___width 1
-#define reg_ser_r_intr___tr_rdy___bit 0
-#define reg_ser_r_intr___tr_empty___lsb 1
-#define reg_ser_r_intr___tr_empty___width 1
-#define reg_ser_r_intr___tr_empty___bit 1
-#define reg_ser_r_intr___tr_idle___lsb 2
-#define reg_ser_r_intr___tr_idle___width 1
-#define reg_ser_r_intr___tr_idle___bit 2
-#define reg_ser_r_intr___dav___lsb 3
-#define reg_ser_r_intr___dav___width 1
-#define reg_ser_r_intr___dav___bit 3
-#define reg_ser_r_intr_offset 52
-
-/* Register r_masked_intr, scope ser, type r */
-#define reg_ser_r_masked_intr___tr_rdy___lsb 0
-#define reg_ser_r_masked_intr___tr_rdy___width 1
-#define reg_ser_r_masked_intr___tr_rdy___bit 0
-#define reg_ser_r_masked_intr___tr_empty___lsb 1
-#define reg_ser_r_masked_intr___tr_empty___width 1
-#define reg_ser_r_masked_intr___tr_empty___bit 1
-#define reg_ser_r_masked_intr___tr_idle___lsb 2
-#define reg_ser_r_masked_intr___tr_idle___width 1
-#define reg_ser_r_masked_intr___tr_idle___bit 2
-#define reg_ser_r_masked_intr___dav___lsb 3
-#define reg_ser_r_masked_intr___dav___width 1
-#define reg_ser_r_masked_intr___dav___bit 3
-#define reg_ser_r_masked_intr_offset 56
-
-
-/* Constants */
-#define regk_ser_active                           0x00000000
-#define regk_ser_bits1                            0x00000000
-#define regk_ser_bits2                            0x00000001
-#define regk_ser_bits7                            0x00000001
-#define regk_ser_bits8                            0x00000000
-#define regk_ser_del0_5                           0x00000000
-#define regk_ser_del1                             0x00000001
-#define regk_ser_del1_5                           0x00000002
-#define regk_ser_del2                             0x00000003
-#define regk_ser_del2_5                           0x00000004
-#define regk_ser_del3                             0x00000005
-#define regk_ser_del3_5                           0x00000006
-#define regk_ser_del4                             0x00000007
-#define regk_ser_even                             0x00000000
-#define regk_ser_ext                              0x00000001
-#define regk_ser_f100                             0x00000007
-#define regk_ser_f29_493                          0x00000004
-#define regk_ser_f32                              0x00000005
-#define regk_ser_f32_768                          0x00000006
-#define regk_ser_ignore                           0x00000001
-#define regk_ser_inactive                         0x00000001
-#define regk_ser_majority                         0x00000001
-#define regk_ser_mark                             0x00000002
-#define regk_ser_middle                           0x00000000
-#define regk_ser_no                               0x00000000
-#define regk_ser_odd                              0x00000001
-#define regk_ser_off                              0x00000000
-#define regk_ser_rw_intr_mask_default             0x00000000
-#define regk_ser_rw_rec_baud_div_default          0x00000000
-#define regk_ser_rw_rec_ctrl_default              0x00010000
-#define regk_ser_rw_tr_baud_div_default           0x00000000
-#define regk_ser_rw_tr_ctrl_default               0x00008000
-#define regk_ser_rw_tr_dma_en_default             0x00000000
-#define regk_ser_rw_xoff_default                  0x00000000
-#define regk_ser_space                            0x00000003
-#define regk_ser_stop                             0x00000000
-#define regk_ser_yes                              0x00000001
-#endif /* __ser_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h
deleted file mode 100644
index 27d4d91b3abd..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h
+++ /dev/null
@@ -1,462 +0,0 @@
-#ifndef __sser_defs_asm_h
-#define __sser_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/syncser/rtl/sser_regs.r
- *     id:           sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp
- *     last modfied: Mon Apr 11 16:09:48 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r
- *      id: $Id: sser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope sser, type rw */
-#define reg_sser_rw_cfg___clk_div___lsb 0
-#define reg_sser_rw_cfg___clk_div___width 16
-#define reg_sser_rw_cfg___base_freq___lsb 16
-#define reg_sser_rw_cfg___base_freq___width 3
-#define reg_sser_rw_cfg___gate_clk___lsb 19
-#define reg_sser_rw_cfg___gate_clk___width 1
-#define reg_sser_rw_cfg___gate_clk___bit 19
-#define reg_sser_rw_cfg___clkgate_ctrl___lsb 20
-#define reg_sser_rw_cfg___clkgate_ctrl___width 1
-#define reg_sser_rw_cfg___clkgate_ctrl___bit 20
-#define reg_sser_rw_cfg___clkgate_in___lsb 21
-#define reg_sser_rw_cfg___clkgate_in___width 1
-#define reg_sser_rw_cfg___clkgate_in___bit 21
-#define reg_sser_rw_cfg___clk_dir___lsb 22
-#define reg_sser_rw_cfg___clk_dir___width 1
-#define reg_sser_rw_cfg___clk_dir___bit 22
-#define reg_sser_rw_cfg___clk_od_mode___lsb 23
-#define reg_sser_rw_cfg___clk_od_mode___width 1
-#define reg_sser_rw_cfg___clk_od_mode___bit 23
-#define reg_sser_rw_cfg___out_clk_pol___lsb 24
-#define reg_sser_rw_cfg___out_clk_pol___width 1
-#define reg_sser_rw_cfg___out_clk_pol___bit 24
-#define reg_sser_rw_cfg___out_clk_src___lsb 25
-#define reg_sser_rw_cfg___out_clk_src___width 2
-#define reg_sser_rw_cfg___clk_in_sel___lsb 27
-#define reg_sser_rw_cfg___clk_in_sel___width 1
-#define reg_sser_rw_cfg___clk_in_sel___bit 27
-#define reg_sser_rw_cfg___hold_pol___lsb 28
-#define reg_sser_rw_cfg___hold_pol___width 1
-#define reg_sser_rw_cfg___hold_pol___bit 28
-#define reg_sser_rw_cfg___prepare___lsb 29
-#define reg_sser_rw_cfg___prepare___width 1
-#define reg_sser_rw_cfg___prepare___bit 29
-#define reg_sser_rw_cfg___en___lsb 30
-#define reg_sser_rw_cfg___en___width 1
-#define reg_sser_rw_cfg___en___bit 30
-#define reg_sser_rw_cfg_offset 0
-
-/* Register rw_frm_cfg, scope sser, type rw */
-#define reg_sser_rw_frm_cfg___wordrate___lsb 0
-#define reg_sser_rw_frm_cfg___wordrate___width 10
-#define reg_sser_rw_frm_cfg___rec_delay___lsb 10
-#define reg_sser_rw_frm_cfg___rec_delay___width 3
-#define reg_sser_rw_frm_cfg___tr_delay___lsb 13
-#define reg_sser_rw_frm_cfg___tr_delay___width 3
-#define reg_sser_rw_frm_cfg___early_wend___lsb 16
-#define reg_sser_rw_frm_cfg___early_wend___width 1
-#define reg_sser_rw_frm_cfg___early_wend___bit 16
-#define reg_sser_rw_frm_cfg___level___lsb 17
-#define reg_sser_rw_frm_cfg___level___width 2
-#define reg_sser_rw_frm_cfg___type___lsb 19
-#define reg_sser_rw_frm_cfg___type___width 1
-#define reg_sser_rw_frm_cfg___type___bit 19
-#define reg_sser_rw_frm_cfg___clk_pol___lsb 20
-#define reg_sser_rw_frm_cfg___clk_pol___width 1
-#define reg_sser_rw_frm_cfg___clk_pol___bit 20
-#define reg_sser_rw_frm_cfg___fr_in_rxclk___lsb 21
-#define reg_sser_rw_frm_cfg___fr_in_rxclk___width 1
-#define reg_sser_rw_frm_cfg___fr_in_rxclk___bit 21
-#define reg_sser_rw_frm_cfg___clk_src___lsb 22
-#define reg_sser_rw_frm_cfg___clk_src___width 1
-#define reg_sser_rw_frm_cfg___clk_src___bit 22
-#define reg_sser_rw_frm_cfg___out_off___lsb 23
-#define reg_sser_rw_frm_cfg___out_off___width 1
-#define reg_sser_rw_frm_cfg___out_off___bit 23
-#define reg_sser_rw_frm_cfg___out_on___lsb 24
-#define reg_sser_rw_frm_cfg___out_on___width 1
-#define reg_sser_rw_frm_cfg___out_on___bit 24
-#define reg_sser_rw_frm_cfg___frame_pin_dir___lsb 25
-#define reg_sser_rw_frm_cfg___frame_pin_dir___width 1
-#define reg_sser_rw_frm_cfg___frame_pin_dir___bit 25
-#define reg_sser_rw_frm_cfg___frame_pin_use___lsb 26
-#define reg_sser_rw_frm_cfg___frame_pin_use___width 2
-#define reg_sser_rw_frm_cfg___status_pin_dir___lsb 28
-#define reg_sser_rw_frm_cfg___status_pin_dir___width 1
-#define reg_sser_rw_frm_cfg___status_pin_dir___bit 28
-#define reg_sser_rw_frm_cfg___status_pin_use___lsb 29
-#define reg_sser_rw_frm_cfg___status_pin_use___width 2
-#define reg_sser_rw_frm_cfg_offset 4
-
-/* Register rw_tr_cfg, scope sser, type rw */
-#define reg_sser_rw_tr_cfg___tr_en___lsb 0
-#define reg_sser_rw_tr_cfg___tr_en___width 1
-#define reg_sser_rw_tr_cfg___tr_en___bit 0
-#define reg_sser_rw_tr_cfg___stop___lsb 1
-#define reg_sser_rw_tr_cfg___stop___width 1
-#define reg_sser_rw_tr_cfg___stop___bit 1
-#define reg_sser_rw_tr_cfg___urun_stop___lsb 2
-#define reg_sser_rw_tr_cfg___urun_stop___width 1
-#define reg_sser_rw_tr_cfg___urun_stop___bit 2
-#define reg_sser_rw_tr_cfg___eop_stop___lsb 3
-#define reg_sser_rw_tr_cfg___eop_stop___width 1
-#define reg_sser_rw_tr_cfg___eop_stop___bit 3
-#define reg_sser_rw_tr_cfg___sample_size___lsb 4
-#define reg_sser_rw_tr_cfg___sample_size___width 6
-#define reg_sser_rw_tr_cfg___sh_dir___lsb 10
-#define reg_sser_rw_tr_cfg___sh_dir___width 1
-#define reg_sser_rw_tr_cfg___sh_dir___bit 10
-#define reg_sser_rw_tr_cfg___clk_pol___lsb 11
-#define reg_sser_rw_tr_cfg___clk_pol___width 1
-#define reg_sser_rw_tr_cfg___clk_pol___bit 11
-#define reg_sser_rw_tr_cfg___clk_src___lsb 12
-#define reg_sser_rw_tr_cfg___clk_src___width 1
-#define reg_sser_rw_tr_cfg___clk_src___bit 12
-#define reg_sser_rw_tr_cfg___use_dma___lsb 13
-#define reg_sser_rw_tr_cfg___use_dma___width 1
-#define reg_sser_rw_tr_cfg___use_dma___bit 13
-#define reg_sser_rw_tr_cfg___mode___lsb 14
-#define reg_sser_rw_tr_cfg___mode___width 2
-#define reg_sser_rw_tr_cfg___frm_src___lsb 16
-#define reg_sser_rw_tr_cfg___frm_src___width 1
-#define reg_sser_rw_tr_cfg___frm_src___bit 16
-#define reg_sser_rw_tr_cfg___use60958___lsb 17
-#define reg_sser_rw_tr_cfg___use60958___width 1
-#define reg_sser_rw_tr_cfg___use60958___bit 17
-#define reg_sser_rw_tr_cfg___iec60958_ckdiv___lsb 18
-#define reg_sser_rw_tr_cfg___iec60958_ckdiv___width 2
-#define reg_sser_rw_tr_cfg___rate_ctrl___lsb 20
-#define reg_sser_rw_tr_cfg___rate_ctrl___width 1
-#define reg_sser_rw_tr_cfg___rate_ctrl___bit 20
-#define reg_sser_rw_tr_cfg___use_md___lsb 21
-#define reg_sser_rw_tr_cfg___use_md___width 1
-#define reg_sser_rw_tr_cfg___use_md___bit 21
-#define reg_sser_rw_tr_cfg___dual_i2s___lsb 22
-#define reg_sser_rw_tr_cfg___dual_i2s___width 1
-#define reg_sser_rw_tr_cfg___dual_i2s___bit 22
-#define reg_sser_rw_tr_cfg___data_pin_use___lsb 23
-#define reg_sser_rw_tr_cfg___data_pin_use___width 2
-#define reg_sser_rw_tr_cfg___od_mode___lsb 25
-#define reg_sser_rw_tr_cfg___od_mode___width 1
-#define reg_sser_rw_tr_cfg___od_mode___bit 25
-#define reg_sser_rw_tr_cfg___bulk_wspace___lsb 26
-#define reg_sser_rw_tr_cfg___bulk_wspace___width 2
-#define reg_sser_rw_tr_cfg_offset 8
-
-/* Register rw_rec_cfg, scope sser, type rw */
-#define reg_sser_rw_rec_cfg___rec_en___lsb 0
-#define reg_sser_rw_rec_cfg___rec_en___width 1
-#define reg_sser_rw_rec_cfg___rec_en___bit 0
-#define reg_sser_rw_rec_cfg___force_eop___lsb 1
-#define reg_sser_rw_rec_cfg___force_eop___width 1
-#define reg_sser_rw_rec_cfg___force_eop___bit 1
-#define reg_sser_rw_rec_cfg___stop___lsb 2
-#define reg_sser_rw_rec_cfg___stop___width 1
-#define reg_sser_rw_rec_cfg___stop___bit 2
-#define reg_sser_rw_rec_cfg___orun_stop___lsb 3
-#define reg_sser_rw_rec_cfg___orun_stop___width 1
-#define reg_sser_rw_rec_cfg___orun_stop___bit 3
-#define reg_sser_rw_rec_cfg___eop_stop___lsb 4
-#define reg_sser_rw_rec_cfg___eop_stop___width 1
-#define reg_sser_rw_rec_cfg___eop_stop___bit 4
-#define reg_sser_rw_rec_cfg___sample_size___lsb 5
-#define reg_sser_rw_rec_cfg___sample_size___width 6
-#define reg_sser_rw_rec_cfg___sh_dir___lsb 11
-#define reg_sser_rw_rec_cfg___sh_dir___width 1
-#define reg_sser_rw_rec_cfg___sh_dir___bit 11
-#define reg_sser_rw_rec_cfg___clk_pol___lsb 12
-#define reg_sser_rw_rec_cfg___clk_pol___width 1
-#define reg_sser_rw_rec_cfg___clk_pol___bit 12
-#define reg_sser_rw_rec_cfg___clk_src___lsb 13
-#define reg_sser_rw_rec_cfg___clk_src___width 1
-#define reg_sser_rw_rec_cfg___clk_src___bit 13
-#define reg_sser_rw_rec_cfg___use_dma___lsb 14
-#define reg_sser_rw_rec_cfg___use_dma___width 1
-#define reg_sser_rw_rec_cfg___use_dma___bit 14
-#define reg_sser_rw_rec_cfg___mode___lsb 15
-#define reg_sser_rw_rec_cfg___mode___width 2
-#define reg_sser_rw_rec_cfg___frm_src___lsb 17
-#define reg_sser_rw_rec_cfg___frm_src___width 2
-#define reg_sser_rw_rec_cfg___use60958___lsb 19
-#define reg_sser_rw_rec_cfg___use60958___width 1
-#define reg_sser_rw_rec_cfg___use60958___bit 19
-#define reg_sser_rw_rec_cfg___iec60958_ui_len___lsb 20
-#define reg_sser_rw_rec_cfg___iec60958_ui_len___width 5
-#define reg_sser_rw_rec_cfg___slave2_en___lsb 25
-#define reg_sser_rw_rec_cfg___slave2_en___width 1
-#define reg_sser_rw_rec_cfg___slave2_en___bit 25
-#define reg_sser_rw_rec_cfg___slave3_en___lsb 26
-#define reg_sser_rw_rec_cfg___slave3_en___width 1
-#define reg_sser_rw_rec_cfg___slave3_en___bit 26
-#define reg_sser_rw_rec_cfg___fifo_thr___lsb 27
-#define reg_sser_rw_rec_cfg___fifo_thr___width 2
-#define reg_sser_rw_rec_cfg_offset 12
-
-/* Register rw_tr_data, scope sser, type rw */
-#define reg_sser_rw_tr_data___data___lsb 0
-#define reg_sser_rw_tr_data___data___width 16
-#define reg_sser_rw_tr_data___md___lsb 16
-#define reg_sser_rw_tr_data___md___width 1
-#define reg_sser_rw_tr_data___md___bit 16
-#define reg_sser_rw_tr_data_offset 16
-
-/* Register r_rec_data, scope sser, type r */
-#define reg_sser_r_rec_data___data___lsb 0
-#define reg_sser_r_rec_data___data___width 16
-#define reg_sser_r_rec_data___md___lsb 16
-#define reg_sser_r_rec_data___md___width 1
-#define reg_sser_r_rec_data___md___bit 16
-#define reg_sser_r_rec_data___ext_clk___lsb 17
-#define reg_sser_r_rec_data___ext_clk___width 1
-#define reg_sser_r_rec_data___ext_clk___bit 17
-#define reg_sser_r_rec_data___status_in___lsb 18
-#define reg_sser_r_rec_data___status_in___width 1
-#define reg_sser_r_rec_data___status_in___bit 18
-#define reg_sser_r_rec_data___frame_in___lsb 19
-#define reg_sser_r_rec_data___frame_in___width 1
-#define reg_sser_r_rec_data___frame_in___bit 19
-#define reg_sser_r_rec_data___din___lsb 20
-#define reg_sser_r_rec_data___din___width 1
-#define reg_sser_r_rec_data___din___bit 20
-#define reg_sser_r_rec_data___data_in___lsb 21
-#define reg_sser_r_rec_data___data_in___width 1
-#define reg_sser_r_rec_data___data_in___bit 21
-#define reg_sser_r_rec_data___clk_in___lsb 22
-#define reg_sser_r_rec_data___clk_in___width 1
-#define reg_sser_r_rec_data___clk_in___bit 22
-#define reg_sser_r_rec_data_offset 20
-
-/* Register rw_extra, scope sser, type rw */
-#define reg_sser_rw_extra___clkoff_cycles___lsb 0
-#define reg_sser_rw_extra___clkoff_cycles___width 20
-#define reg_sser_rw_extra___clkoff_en___lsb 20
-#define reg_sser_rw_extra___clkoff_en___width 1
-#define reg_sser_rw_extra___clkoff_en___bit 20
-#define reg_sser_rw_extra___clkon_en___lsb 21
-#define reg_sser_rw_extra___clkon_en___width 1
-#define reg_sser_rw_extra___clkon_en___bit 21
-#define reg_sser_rw_extra___dout_delay___lsb 22
-#define reg_sser_rw_extra___dout_delay___width 5
-#define reg_sser_rw_extra_offset 24
-
-/* Register rw_intr_mask, scope sser, type rw */
-#define reg_sser_rw_intr_mask___trdy___lsb 0
-#define reg_sser_rw_intr_mask___trdy___width 1
-#define reg_sser_rw_intr_mask___trdy___bit 0
-#define reg_sser_rw_intr_mask___rdav___lsb 1
-#define reg_sser_rw_intr_mask___rdav___width 1
-#define reg_sser_rw_intr_mask___rdav___bit 1
-#define reg_sser_rw_intr_mask___tidle___lsb 2
-#define reg_sser_rw_intr_mask___tidle___width 1
-#define reg_sser_rw_intr_mask___tidle___bit 2
-#define reg_sser_rw_intr_mask___rstop___lsb 3
-#define reg_sser_rw_intr_mask___rstop___width 1
-#define reg_sser_rw_intr_mask___rstop___bit 3
-#define reg_sser_rw_intr_mask___urun___lsb 4
-#define reg_sser_rw_intr_mask___urun___width 1
-#define reg_sser_rw_intr_mask___urun___bit 4
-#define reg_sser_rw_intr_mask___orun___lsb 5
-#define reg_sser_rw_intr_mask___orun___width 1
-#define reg_sser_rw_intr_mask___orun___bit 5
-#define reg_sser_rw_intr_mask___md_rec___lsb 6
-#define reg_sser_rw_intr_mask___md_rec___width 1
-#define reg_sser_rw_intr_mask___md_rec___bit 6
-#define reg_sser_rw_intr_mask___md_sent___lsb 7
-#define reg_sser_rw_intr_mask___md_sent___width 1
-#define reg_sser_rw_intr_mask___md_sent___bit 7
-#define reg_sser_rw_intr_mask___r958err___lsb 8
-#define reg_sser_rw_intr_mask___r958err___width 1
-#define reg_sser_rw_intr_mask___r958err___bit 8
-#define reg_sser_rw_intr_mask_offset 28
-
-/* Register rw_ack_intr, scope sser, type rw */
-#define reg_sser_rw_ack_intr___trdy___lsb 0
-#define reg_sser_rw_ack_intr___trdy___width 1
-#define reg_sser_rw_ack_intr___trdy___bit 0
-#define reg_sser_rw_ack_intr___rdav___lsb 1
-#define reg_sser_rw_ack_intr___rdav___width 1
-#define reg_sser_rw_ack_intr___rdav___bit 1
-#define reg_sser_rw_ack_intr___tidle___lsb 2
-#define reg_sser_rw_ack_intr___tidle___width 1
-#define reg_sser_rw_ack_intr___tidle___bit 2
-#define reg_sser_rw_ack_intr___rstop___lsb 3
-#define reg_sser_rw_ack_intr___rstop___width 1
-#define reg_sser_rw_ack_intr___rstop___bit 3
-#define reg_sser_rw_ack_intr___urun___lsb 4
-#define reg_sser_rw_ack_intr___urun___width 1
-#define reg_sser_rw_ack_intr___urun___bit 4
-#define reg_sser_rw_ack_intr___orun___lsb 5
-#define reg_sser_rw_ack_intr___orun___width 1
-#define reg_sser_rw_ack_intr___orun___bit 5
-#define reg_sser_rw_ack_intr___md_rec___lsb 6
-#define reg_sser_rw_ack_intr___md_rec___width 1
-#define reg_sser_rw_ack_intr___md_rec___bit 6
-#define reg_sser_rw_ack_intr___md_sent___lsb 7
-#define reg_sser_rw_ack_intr___md_sent___width 1
-#define reg_sser_rw_ack_intr___md_sent___bit 7
-#define reg_sser_rw_ack_intr___r958err___lsb 8
-#define reg_sser_rw_ack_intr___r958err___width 1
-#define reg_sser_rw_ack_intr___r958err___bit 8
-#define reg_sser_rw_ack_intr_offset 32
-
-/* Register r_intr, scope sser, type r */
-#define reg_sser_r_intr___trdy___lsb 0
-#define reg_sser_r_intr___trdy___width 1
-#define reg_sser_r_intr___trdy___bit 0
-#define reg_sser_r_intr___rdav___lsb 1
-#define reg_sser_r_intr___rdav___width 1
-#define reg_sser_r_intr___rdav___bit 1
-#define reg_sser_r_intr___tidle___lsb 2
-#define reg_sser_r_intr___tidle___width 1
-#define reg_sser_r_intr___tidle___bit 2
-#define reg_sser_r_intr___rstop___lsb 3
-#define reg_sser_r_intr___rstop___width 1
-#define reg_sser_r_intr___rstop___bit 3
-#define reg_sser_r_intr___urun___lsb 4
-#define reg_sser_r_intr___urun___width 1
-#define reg_sser_r_intr___urun___bit 4
-#define reg_sser_r_intr___orun___lsb 5
-#define reg_sser_r_intr___orun___width 1
-#define reg_sser_r_intr___orun___bit 5
-#define reg_sser_r_intr___md_rec___lsb 6
-#define reg_sser_r_intr___md_rec___width 1
-#define reg_sser_r_intr___md_rec___bit 6
-#define reg_sser_r_intr___md_sent___lsb 7
-#define reg_sser_r_intr___md_sent___width 1
-#define reg_sser_r_intr___md_sent___bit 7
-#define reg_sser_r_intr___r958err___lsb 8
-#define reg_sser_r_intr___r958err___width 1
-#define reg_sser_r_intr___r958err___bit 8
-#define reg_sser_r_intr_offset 36
-
-/* Register r_masked_intr, scope sser, type r */
-#define reg_sser_r_masked_intr___trdy___lsb 0
-#define reg_sser_r_masked_intr___trdy___width 1
-#define reg_sser_r_masked_intr___trdy___bit 0
-#define reg_sser_r_masked_intr___rdav___lsb 1
-#define reg_sser_r_masked_intr___rdav___width 1
-#define reg_sser_r_masked_intr___rdav___bit 1
-#define reg_sser_r_masked_intr___tidle___lsb 2
-#define reg_sser_r_masked_intr___tidle___width 1
-#define reg_sser_r_masked_intr___tidle___bit 2
-#define reg_sser_r_masked_intr___rstop___lsb 3
-#define reg_sser_r_masked_intr___rstop___width 1
-#define reg_sser_r_masked_intr___rstop___bit 3
-#define reg_sser_r_masked_intr___urun___lsb 4
-#define reg_sser_r_masked_intr___urun___width 1
-#define reg_sser_r_masked_intr___urun___bit 4
-#define reg_sser_r_masked_intr___orun___lsb 5
-#define reg_sser_r_masked_intr___orun___width 1
-#define reg_sser_r_masked_intr___orun___bit 5
-#define reg_sser_r_masked_intr___md_rec___lsb 6
-#define reg_sser_r_masked_intr___md_rec___width 1
-#define reg_sser_r_masked_intr___md_rec___bit 6
-#define reg_sser_r_masked_intr___md_sent___lsb 7
-#define reg_sser_r_masked_intr___md_sent___width 1
-#define reg_sser_r_masked_intr___md_sent___bit 7
-#define reg_sser_r_masked_intr___r958err___lsb 8
-#define reg_sser_r_masked_intr___r958err___width 1
-#define reg_sser_r_masked_intr___r958err___bit 8
-#define reg_sser_r_masked_intr_offset 40
-
-
-/* Constants */
-#define regk_sser_both                            0x00000002
-#define regk_sser_bulk                            0x00000001
-#define regk_sser_clk100                          0x00000000
-#define regk_sser_clk_in                          0x00000000
-#define regk_sser_const0                          0x00000003
-#define regk_sser_dout                            0x00000002
-#define regk_sser_edge                            0x00000000
-#define regk_sser_ext                             0x00000001
-#define regk_sser_ext_clk                         0x00000001
-#define regk_sser_f100                            0x00000000
-#define regk_sser_f29_493                         0x00000004
-#define regk_sser_f32                             0x00000005
-#define regk_sser_f32_768                         0x00000006
-#define regk_sser_frm                             0x00000003
-#define regk_sser_gio0                            0x00000000
-#define regk_sser_gio1                            0x00000001
-#define regk_sser_hispeed                         0x00000001
-#define regk_sser_hold                            0x00000002
-#define regk_sser_in                              0x00000000
-#define regk_sser_inf                             0x00000003
-#define regk_sser_intern                          0x00000000
-#define regk_sser_intern_clk                      0x00000001
-#define regk_sser_intern_tb                       0x00000000
-#define regk_sser_iso                             0x00000000
-#define regk_sser_level                           0x00000001
-#define regk_sser_lospeed                         0x00000000
-#define regk_sser_lsbfirst                        0x00000000
-#define regk_sser_msbfirst                        0x00000001
-#define regk_sser_neg                             0x00000001
-#define regk_sser_neg_lo                          0x00000000
-#define regk_sser_no                              0x00000000
-#define regk_sser_no_clk                          0x00000007
-#define regk_sser_nojitter                        0x00000002
-#define regk_sser_out                             0x00000001
-#define regk_sser_pos                             0x00000000
-#define regk_sser_pos_hi                          0x00000001
-#define regk_sser_rec                             0x00000000
-#define regk_sser_rw_cfg_default                  0x00000000
-#define regk_sser_rw_extra_default                0x00000000
-#define regk_sser_rw_frm_cfg_default              0x00000000
-#define regk_sser_rw_intr_mask_default            0x00000000
-#define regk_sser_rw_rec_cfg_default              0x00000000
-#define regk_sser_rw_tr_cfg_default               0x01800000
-#define regk_sser_rw_tr_data_default              0x00000000
-#define regk_sser_thr16                           0x00000001
-#define regk_sser_thr32                           0x00000002
-#define regk_sser_thr8                            0x00000000
-#define regk_sser_tr                              0x00000001
-#define regk_sser_ts_out                          0x00000003
-#define regk_sser_tx_bulk                         0x00000002
-#define regk_sser_wiresave                        0x00000002
-#define regk_sser_yes                             0x00000001
-#endif /* __sser_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h
deleted file mode 100644
index 55083e6aec93..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h
+++ /dev/null
@@ -1,84 +0,0 @@
-#ifndef __strcop_defs_asm_h
-#define __strcop_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/strcop/rtl/strcop_regs.r
- *     id:           strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp
- *     last modfied: Mon Apr 11 16:09:38 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strcop_defs_asm.h ../../inst/strcop/rtl/strcop_regs.r
- *      id: $Id: strcop_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope strcop, type rw */
-#define reg_strcop_rw_cfg___td3___lsb 0
-#define reg_strcop_rw_cfg___td3___width 1
-#define reg_strcop_rw_cfg___td3___bit 0
-#define reg_strcop_rw_cfg___td2___lsb 1
-#define reg_strcop_rw_cfg___td2___width 1
-#define reg_strcop_rw_cfg___td2___bit 1
-#define reg_strcop_rw_cfg___td1___lsb 2
-#define reg_strcop_rw_cfg___td1___width 1
-#define reg_strcop_rw_cfg___td1___bit 2
-#define reg_strcop_rw_cfg___ipend___lsb 3
-#define reg_strcop_rw_cfg___ipend___width 1
-#define reg_strcop_rw_cfg___ipend___bit 3
-#define reg_strcop_rw_cfg___ignore_sync___lsb 4
-#define reg_strcop_rw_cfg___ignore_sync___width 1
-#define reg_strcop_rw_cfg___ignore_sync___bit 4
-#define reg_strcop_rw_cfg___en___lsb 5
-#define reg_strcop_rw_cfg___en___width 1
-#define reg_strcop_rw_cfg___en___bit 5
-#define reg_strcop_rw_cfg_offset 0
-
-
-/* Constants */
-#define regk_strcop_big                           0x00000001
-#define regk_strcop_d                             0x00000001
-#define regk_strcop_e                             0x00000000
-#define regk_strcop_little                        0x00000000
-#define regk_strcop_rw_cfg_default                0x00000002
-#endif /* __strcop_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h
deleted file mode 100644
index 69b299920f71..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h
+++ /dev/null
@@ -1,100 +0,0 @@
-#ifndef __strmux_defs_asm_h
-#define __strmux_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/strmux/rtl/guinness/strmux_regs.r
- *     id:           strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp
- *     last modfied: Mon Apr 11 16:09:43 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strmux_defs_asm.h ../../inst/strmux/rtl/guinness/strmux_regs.r
- *      id: $Id: strmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope strmux, type rw */
-#define reg_strmux_rw_cfg___dma0___lsb 0
-#define reg_strmux_rw_cfg___dma0___width 3
-#define reg_strmux_rw_cfg___dma1___lsb 3
-#define reg_strmux_rw_cfg___dma1___width 3
-#define reg_strmux_rw_cfg___dma2___lsb 6
-#define reg_strmux_rw_cfg___dma2___width 3
-#define reg_strmux_rw_cfg___dma3___lsb 9
-#define reg_strmux_rw_cfg___dma3___width 3
-#define reg_strmux_rw_cfg___dma4___lsb 12
-#define reg_strmux_rw_cfg___dma4___width 3
-#define reg_strmux_rw_cfg___dma5___lsb 15
-#define reg_strmux_rw_cfg___dma5___width 3
-#define reg_strmux_rw_cfg___dma6___lsb 18
-#define reg_strmux_rw_cfg___dma6___width 3
-#define reg_strmux_rw_cfg___dma7___lsb 21
-#define reg_strmux_rw_cfg___dma7___width 3
-#define reg_strmux_rw_cfg___dma8___lsb 24
-#define reg_strmux_rw_cfg___dma8___width 3
-#define reg_strmux_rw_cfg___dma9___lsb 27
-#define reg_strmux_rw_cfg___dma9___width 3
-#define reg_strmux_rw_cfg_offset 0
-
-
-/* Constants */
-#define regk_strmux_ata                           0x00000003
-#define regk_strmux_eth0                          0x00000001
-#define regk_strmux_eth1                          0x00000004
-#define regk_strmux_ext0                          0x00000001
-#define regk_strmux_ext1                          0x00000001
-#define regk_strmux_ext2                          0x00000001
-#define regk_strmux_ext3                          0x00000001
-#define regk_strmux_iop0                          0x00000002
-#define regk_strmux_iop1                          0x00000001
-#define regk_strmux_off                           0x00000000
-#define regk_strmux_p21                           0x00000004
-#define regk_strmux_rw_cfg_default                0x00000000
-#define regk_strmux_ser0                          0x00000002
-#define regk_strmux_ser1                          0x00000002
-#define regk_strmux_ser2                          0x00000004
-#define regk_strmux_ser3                          0x00000003
-#define regk_strmux_sser0                         0x00000003
-#define regk_strmux_sser1                         0x00000003
-#define regk_strmux_strcop                        0x00000002
-#endif /* __strmux_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h
deleted file mode 100644
index 43146021fc16..000000000000
--- a/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h
+++ /dev/null
@@ -1,229 +0,0 @@
-#ifndef __timer_defs_asm_h
-#define __timer_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/timer/rtl/timer_regs.r
- *     id:           timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
- *     last modfied: Mon Apr 11 16:09:53 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r
- *      id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_tmr0_div, scope timer, type rw */
-#define reg_timer_rw_tmr0_div_offset 0
-
-/* Register r_tmr0_data, scope timer, type r */
-#define reg_timer_r_tmr0_data_offset 4
-
-/* Register rw_tmr0_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr0_ctrl___op___lsb 0
-#define reg_timer_rw_tmr0_ctrl___op___width 2
-#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr0_ctrl___freq___width 3
-#define reg_timer_rw_tmr0_ctrl_offset 8
-
-/* Register rw_tmr1_div, scope timer, type rw */
-#define reg_timer_rw_tmr1_div_offset 16
-
-/* Register r_tmr1_data, scope timer, type r */
-#define reg_timer_r_tmr1_data_offset 20
-
-/* Register rw_tmr1_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr1_ctrl___op___lsb 0
-#define reg_timer_rw_tmr1_ctrl___op___width 2
-#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr1_ctrl___freq___width 3
-#define reg_timer_rw_tmr1_ctrl_offset 24
-
-/* Register rs_cnt_data, scope timer, type rs */
-#define reg_timer_rs_cnt_data___tmr___lsb 0
-#define reg_timer_rs_cnt_data___tmr___width 24
-#define reg_timer_rs_cnt_data___cnt___lsb 24
-#define reg_timer_rs_cnt_data___cnt___width 8
-#define reg_timer_rs_cnt_data_offset 32
-
-/* Register r_cnt_data, scope timer, type r */
-#define reg_timer_r_cnt_data___tmr___lsb 0
-#define reg_timer_r_cnt_data___tmr___width 24
-#define reg_timer_r_cnt_data___cnt___lsb 24
-#define reg_timer_r_cnt_data___cnt___width 8
-#define reg_timer_r_cnt_data_offset 36
-
-/* Register rw_cnt_cfg, scope timer, type rw */
-#define reg_timer_rw_cnt_cfg___clk___lsb 0
-#define reg_timer_rw_cnt_cfg___clk___width 2
-#define reg_timer_rw_cnt_cfg_offset 40
-
-/* Register rw_trig, scope timer, type rw */
-#define reg_timer_rw_trig_offset 48
-
-/* Register rw_trig_cfg, scope timer, type rw */
-#define reg_timer_rw_trig_cfg___tmr___lsb 0
-#define reg_timer_rw_trig_cfg___tmr___width 2
-#define reg_timer_rw_trig_cfg_offset 52
-
-/* Register r_time, scope timer, type r */
-#define reg_timer_r_time_offset 56
-
-/* Register rw_out, scope timer, type rw */
-#define reg_timer_rw_out___tmr___lsb 0
-#define reg_timer_rw_out___tmr___width 2
-#define reg_timer_rw_out_offset 60
-
-/* Register rw_wd_ctrl, scope timer, type rw */
-#define reg_timer_rw_wd_ctrl___cnt___lsb 0
-#define reg_timer_rw_wd_ctrl___cnt___width 8
-#define reg_timer_rw_wd_ctrl___cmd___lsb 8
-#define reg_timer_rw_wd_ctrl___cmd___width 1
-#define reg_timer_rw_wd_ctrl___cmd___bit 8
-#define reg_timer_rw_wd_ctrl___key___lsb 9
-#define reg_timer_rw_wd_ctrl___key___width 7
-#define reg_timer_rw_wd_ctrl_offset 64
-
-/* Register r_wd_stat, scope timer, type r */
-#define reg_timer_r_wd_stat___cnt___lsb 0
-#define reg_timer_r_wd_stat___cnt___width 8
-#define reg_timer_r_wd_stat___cmd___lsb 8
-#define reg_timer_r_wd_stat___cmd___width 1
-#define reg_timer_r_wd_stat___cmd___bit 8
-#define reg_timer_r_wd_stat_offset 68
-
-/* Register rw_intr_mask, scope timer, type rw */
-#define reg_timer_rw_intr_mask___tmr0___lsb 0
-#define reg_timer_rw_intr_mask___tmr0___width 1
-#define reg_timer_rw_intr_mask___tmr0___bit 0
-#define reg_timer_rw_intr_mask___tmr1___lsb 1
-#define reg_timer_rw_intr_mask___tmr1___width 1
-#define reg_timer_rw_intr_mask___tmr1___bit 1
-#define reg_timer_rw_intr_mask___cnt___lsb 2
-#define reg_timer_rw_intr_mask___cnt___width 1
-#define reg_timer_rw_intr_mask___cnt___bit 2
-#define reg_timer_rw_intr_mask___trig___lsb 3
-#define reg_timer_rw_intr_mask___trig___width 1
-#define reg_timer_rw_intr_mask___trig___bit 3
-#define reg_timer_rw_intr_mask_offset 72
-
-/* Register rw_ack_intr, scope timer, type rw */
-#define reg_timer_rw_ack_intr___tmr0___lsb 0
-#define reg_timer_rw_ack_intr___tmr0___width 1
-#define reg_timer_rw_ack_intr___tmr0___bit 0
-#define reg_timer_rw_ack_intr___tmr1___lsb 1
-#define reg_timer_rw_ack_intr___tmr1___width 1
-#define reg_timer_rw_ack_intr___tmr1___bit 1
-#define reg_timer_rw_ack_intr___cnt___lsb 2
-#define reg_timer_rw_ack_intr___cnt___width 1
-#define reg_timer_rw_ack_intr___cnt___bit 2
-#define reg_timer_rw_ack_intr___trig___lsb 3
-#define reg_timer_rw_ack_intr___trig___width 1
-#define reg_timer_rw_ack_intr___trig___bit 3
-#define reg_timer_rw_ack_intr_offset 76
-
-/* Register r_intr, scope timer, type r */
-#define reg_timer_r_intr___tmr0___lsb 0
-#define reg_timer_r_intr___tmr0___width 1
-#define reg_timer_r_intr___tmr0___bit 0
-#define reg_timer_r_intr___tmr1___lsb 1
-#define reg_timer_r_intr___tmr1___width 1
-#define reg_timer_r_intr___tmr1___bit 1
-#define reg_timer_r_intr___cnt___lsb 2
-#define reg_timer_r_intr___cnt___width 1
-#define reg_timer_r_intr___cnt___bit 2
-#define reg_timer_r_intr___trig___lsb 3
-#define reg_timer_r_intr___trig___width 1
-#define reg_timer_r_intr___trig___bit 3
-#define reg_timer_r_intr_offset 80
-
-/* Register r_masked_intr, scope timer, type r */
-#define reg_timer_r_masked_intr___tmr0___lsb 0
-#define reg_timer_r_masked_intr___tmr0___width 1
-#define reg_timer_r_masked_intr___tmr0___bit 0
-#define reg_timer_r_masked_intr___tmr1___lsb 1
-#define reg_timer_r_masked_intr___tmr1___width 1
-#define reg_timer_r_masked_intr___tmr1___bit 1
-#define reg_timer_r_masked_intr___cnt___lsb 2
-#define reg_timer_r_masked_intr___cnt___width 1
-#define reg_timer_r_masked_intr___cnt___bit 2
-#define reg_timer_r_masked_intr___trig___lsb 3
-#define reg_timer_r_masked_intr___trig___width 1
-#define reg_timer_r_masked_intr___trig___bit 3
-#define reg_timer_r_masked_intr_offset 84
-
-/* Register rw_test, scope timer, type rw */
-#define reg_timer_rw_test___dis___lsb 0
-#define reg_timer_rw_test___dis___width 1
-#define reg_timer_rw_test___dis___bit 0
-#define reg_timer_rw_test___en___lsb 1
-#define reg_timer_rw_test___en___width 1
-#define reg_timer_rw_test___en___bit 1
-#define reg_timer_rw_test_offset 88
-
-
-/* Constants */
-#define regk_timer_ext                            0x00000001
-#define regk_timer_f100                           0x00000007
-#define regk_timer_f29_493                        0x00000004
-#define regk_timer_f32                            0x00000005
-#define regk_timer_f32_768                        0x00000006
-#define regk_timer_hold                           0x00000001
-#define regk_timer_ld                             0x00000000
-#define regk_timer_no                             0x00000000
-#define regk_timer_off                            0x00000000
-#define regk_timer_run                            0x00000002
-#define regk_timer_rw_cnt_cfg_default             0x00000000
-#define regk_timer_rw_intr_mask_default           0x00000000
-#define regk_timer_rw_out_default                 0x00000000
-#define regk_timer_rw_test_default                0x00000000
-#define regk_timer_rw_tmr0_ctrl_default           0x00000000
-#define regk_timer_rw_tmr1_ctrl_default           0x00000000
-#define regk_timer_rw_trig_cfg_default            0x00000000
-#define regk_timer_start                          0x00000001
-#define regk_timer_stop                           0x00000000
-#define regk_timer_time                           0x00000001
-#define regk_timer_tmr0                           0x00000002
-#define regk_timer_tmr1                           0x00000003
-#define regk_timer_yes                            0x00000001
-#endif /* __timer_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/ata_defs.h b/include/asm-cris/arch-v32/hwregs/ata_defs.h
deleted file mode 100644
index 43b6643ff0d3..000000000000
--- a/include/asm-cris/arch-v32/hwregs/ata_defs.h
+++ /dev/null
@@ -1,222 +0,0 @@
-#ifndef __ata_defs_h
-#define __ata_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/ata/rtl/ata_regs.r
- *     id:           ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
- *     last modfied: Mon Apr 11 16:06:25 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r
- *      id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope ata */
-
-/* Register rw_ctrl0, scope ata, type rw */
-typedef struct {
-  unsigned int pio_hold  : 6;
-  unsigned int pio_strb  : 6;
-  unsigned int pio_setup : 6;
-  unsigned int dma_hold  : 6;
-  unsigned int dma_strb  : 6;
-  unsigned int rst       : 1;
-  unsigned int en        : 1;
-} reg_ata_rw_ctrl0;
-#define REG_RD_ADDR_ata_rw_ctrl0 12
-#define REG_WR_ADDR_ata_rw_ctrl0 12
-
-/* Register rw_ctrl1, scope ata, type rw */
-typedef struct {
-  unsigned int udma_tcyc : 4;
-  unsigned int udma_tdvs : 4;
-  unsigned int dummy1    : 24;
-} reg_ata_rw_ctrl1;
-#define REG_RD_ADDR_ata_rw_ctrl1 16
-#define REG_WR_ADDR_ata_rw_ctrl1 16
-
-/* Register rw_ctrl2, scope ata, type rw */
-typedef struct {
-  unsigned int data     : 16;
-  unsigned int dummy1   : 3;
-  unsigned int dma_size : 1;
-  unsigned int multi    : 1;
-  unsigned int hsh      : 2;
-  unsigned int trf_mode : 1;
-  unsigned int rw       : 1;
-  unsigned int addr     : 3;
-  unsigned int cs0      : 1;
-  unsigned int cs1      : 1;
-  unsigned int sel      : 2;
-} reg_ata_rw_ctrl2;
-#define REG_RD_ADDR_ata_rw_ctrl2 0
-#define REG_WR_ADDR_ata_rw_ctrl2 0
-
-/* Register rs_stat_data, scope ata, type rs */
-typedef struct {
-  unsigned int data : 16;
-  unsigned int dav  : 1;
-  unsigned int busy : 1;
-  unsigned int dummy1 : 14;
-} reg_ata_rs_stat_data;
-#define REG_RD_ADDR_ata_rs_stat_data 4
-
-/* Register r_stat_data, scope ata, type r */
-typedef struct {
-  unsigned int data : 16;
-  unsigned int dav  : 1;
-  unsigned int busy : 1;
-  unsigned int dummy1 : 14;
-} reg_ata_r_stat_data;
-#define REG_RD_ADDR_ata_r_stat_data 8
-
-/* Register rw_trf_cnt, scope ata, type rw */
-typedef struct {
-  unsigned int cnt : 17;
-  unsigned int dummy1 : 15;
-} reg_ata_rw_trf_cnt;
-#define REG_RD_ADDR_ata_rw_trf_cnt 20
-#define REG_WR_ADDR_ata_rw_trf_cnt 20
-
-/* Register r_stat_misc, scope ata, type r */
-typedef struct {
-  unsigned int crc : 16;
-  unsigned int dummy1 : 16;
-} reg_ata_r_stat_misc;
-#define REG_RD_ADDR_ata_r_stat_misc 24
-
-/* Register rw_intr_mask, scope ata, type rw */
-typedef struct {
-  unsigned int bus0 : 1;
-  unsigned int bus1 : 1;
-  unsigned int bus2 : 1;
-  unsigned int bus3 : 1;
-  unsigned int dummy1 : 28;
-} reg_ata_rw_intr_mask;
-#define REG_RD_ADDR_ata_rw_intr_mask 28
-#define REG_WR_ADDR_ata_rw_intr_mask 28
-
-/* Register rw_ack_intr, scope ata, type rw */
-typedef struct {
-  unsigned int bus0 : 1;
-  unsigned int bus1 : 1;
-  unsigned int bus2 : 1;
-  unsigned int bus3 : 1;
-  unsigned int dummy1 : 28;
-} reg_ata_rw_ack_intr;
-#define REG_RD_ADDR_ata_rw_ack_intr 32
-#define REG_WR_ADDR_ata_rw_ack_intr 32
-
-/* Register r_intr, scope ata, type r */
-typedef struct {
-  unsigned int bus0 : 1;
-  unsigned int bus1 : 1;
-  unsigned int bus2 : 1;
-  unsigned int bus3 : 1;
-  unsigned int dummy1 : 28;
-} reg_ata_r_intr;
-#define REG_RD_ADDR_ata_r_intr 36
-
-/* Register r_masked_intr, scope ata, type r */
-typedef struct {
-  unsigned int bus0 : 1;
-  unsigned int bus1 : 1;
-  unsigned int bus2 : 1;
-  unsigned int bus3 : 1;
-  unsigned int dummy1 : 28;
-} reg_ata_r_masked_intr;
-#define REG_RD_ADDR_ata_r_masked_intr 40
-
-
-/* Constants */
-enum {
-  regk_ata_active                          = 0x00000001,
-  regk_ata_byte                            = 0x00000001,
-  regk_ata_data                            = 0x00000001,
-  regk_ata_dma                             = 0x00000001,
-  regk_ata_inactive                        = 0x00000000,
-  regk_ata_no                              = 0x00000000,
-  regk_ata_nodata                          = 0x00000000,
-  regk_ata_pio                             = 0x00000000,
-  regk_ata_rd                              = 0x00000001,
-  regk_ata_reg                             = 0x00000000,
-  regk_ata_rw_ctrl0_default                = 0x00000000,
-  regk_ata_rw_ctrl2_default                = 0x00000000,
-  regk_ata_rw_intr_mask_default            = 0x00000000,
-  regk_ata_udma                            = 0x00000002,
-  regk_ata_word                            = 0x00000000,
-  regk_ata_wr                              = 0x00000000,
-  regk_ata_yes                             = 0x00000001
-};
-#endif /* __ata_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/bif_core_defs.h b/include/asm-cris/arch-v32/hwregs/bif_core_defs.h
deleted file mode 100644
index a56608b50359..000000000000
--- a/include/asm-cris/arch-v32/hwregs/bif_core_defs.h
+++ /dev/null
@@ -1,284 +0,0 @@
-#ifndef __bif_core_defs_h
-#define __bif_core_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/bif/rtl/bif_core_regs.r
- *     id:           bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
- *     last modfied: Mon Apr 11 16:06:33 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
- *      id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_core */
-
-/* Register rw_grp1_cfg, scope bif_core, type rw */
-typedef struct {
-  unsigned int lw        : 6;
-  unsigned int ew        : 3;
-  unsigned int zw        : 3;
-  unsigned int aw        : 2;
-  unsigned int dw        : 2;
-  unsigned int ewb       : 2;
-  unsigned int bw        : 1;
-  unsigned int wr_extend : 1;
-  unsigned int erc_en    : 1;
-  unsigned int mode      : 1;
-  unsigned int dummy1    : 10;
-} reg_bif_core_rw_grp1_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0
-#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0
-
-/* Register rw_grp2_cfg, scope bif_core, type rw */
-typedef struct {
-  unsigned int lw        : 6;
-  unsigned int ew        : 3;
-  unsigned int zw        : 3;
-  unsigned int aw        : 2;
-  unsigned int dw        : 2;
-  unsigned int ewb       : 2;
-  unsigned int bw        : 1;
-  unsigned int wr_extend : 1;
-  unsigned int erc_en    : 1;
-  unsigned int mode      : 1;
-  unsigned int dummy1    : 10;
-} reg_bif_core_rw_grp2_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4
-#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4
-
-/* Register rw_grp3_cfg, scope bif_core, type rw */
-typedef struct {
-  unsigned int lw         : 6;
-  unsigned int ew         : 3;
-  unsigned int zw         : 3;
-  unsigned int aw         : 2;
-  unsigned int dw         : 2;
-  unsigned int ewb        : 2;
-  unsigned int bw         : 1;
-  unsigned int wr_extend  : 1;
-  unsigned int erc_en     : 1;
-  unsigned int mode       : 1;
-  unsigned int dummy1     : 2;
-  unsigned int gated_csp0 : 2;
-  unsigned int gated_csp1 : 2;
-  unsigned int gated_csp2 : 2;
-  unsigned int gated_csp3 : 2;
-} reg_bif_core_rw_grp3_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8
-#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8
-
-/* Register rw_grp4_cfg, scope bif_core, type rw */
-typedef struct {
-  unsigned int lw         : 6;
-  unsigned int ew         : 3;
-  unsigned int zw         : 3;
-  unsigned int aw         : 2;
-  unsigned int dw         : 2;
-  unsigned int ewb        : 2;
-  unsigned int bw         : 1;
-  unsigned int wr_extend  : 1;
-  unsigned int erc_en     : 1;
-  unsigned int mode       : 1;
-  unsigned int dummy1     : 4;
-  unsigned int gated_csp4 : 2;
-  unsigned int gated_csp5 : 2;
-  unsigned int gated_csp6 : 2;
-} reg_bif_core_rw_grp4_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12
-#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12
-
-/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
-typedef struct {
-  unsigned int bank_sel : 5;
-  unsigned int ca       : 3;
-  unsigned int type     : 1;
-  unsigned int bw       : 1;
-  unsigned int sh       : 3;
-  unsigned int wmm      : 1;
-  unsigned int sh16     : 1;
-  unsigned int grp_sel  : 5;
-  unsigned int dummy1   : 12;
-} reg_bif_core_rw_sdram_cfg_grp0;
-#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16
-#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16
-
-/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
-typedef struct {
-  unsigned int bank_sel : 5;
-  unsigned int ca       : 3;
-  unsigned int type     : 1;
-  unsigned int bw       : 1;
-  unsigned int sh       : 3;
-  unsigned int wmm      : 1;
-  unsigned int sh16     : 1;
-  unsigned int dummy1   : 17;
-} reg_bif_core_rw_sdram_cfg_grp1;
-#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20
-#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20
-
-/* Register rw_sdram_timing, scope bif_core, type rw */
-typedef struct {
-  unsigned int cl    : 3;
-  unsigned int rcd   : 3;
-  unsigned int rp    : 3;
-  unsigned int rc    : 2;
-  unsigned int dpl   : 2;
-  unsigned int pde   : 1;
-  unsigned int ref   : 2;
-  unsigned int cpd   : 1;
-  unsigned int sdcke : 1;
-  unsigned int sdclk : 1;
-  unsigned int dummy1 : 13;
-} reg_bif_core_rw_sdram_timing;
-#define REG_RD_ADDR_bif_core_rw_sdram_timing 24
-#define REG_WR_ADDR_bif_core_rw_sdram_timing 24
-
-/* Register rw_sdram_cmd, scope bif_core, type rw */
-typedef struct {
-  unsigned int cmd      : 3;
-  unsigned int mrs_data : 15;
-  unsigned int dummy1   : 14;
-} reg_bif_core_rw_sdram_cmd;
-#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28
-#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28
-
-/* Register rs_sdram_ref_stat, scope bif_core, type rs */
-typedef struct {
-  unsigned int ok : 1;
-  unsigned int dummy1 : 31;
-} reg_bif_core_rs_sdram_ref_stat;
-#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32
-
-/* Register r_sdram_ref_stat, scope bif_core, type r */
-typedef struct {
-  unsigned int ok : 1;
-  unsigned int dummy1 : 31;
-} reg_bif_core_r_sdram_ref_stat;
-#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36
-
-
-/* Constants */
-enum {
-  regk_bif_core_bank2                      = 0x00000000,
-  regk_bif_core_bank4                      = 0x00000001,
-  regk_bif_core_bit10                      = 0x0000000a,
-  regk_bif_core_bit11                      = 0x0000000b,
-  regk_bif_core_bit12                      = 0x0000000c,
-  regk_bif_core_bit13                      = 0x0000000d,
-  regk_bif_core_bit14                      = 0x0000000e,
-  regk_bif_core_bit15                      = 0x0000000f,
-  regk_bif_core_bit16                      = 0x00000010,
-  regk_bif_core_bit17                      = 0x00000011,
-  regk_bif_core_bit18                      = 0x00000012,
-  regk_bif_core_bit19                      = 0x00000013,
-  regk_bif_core_bit20                      = 0x00000014,
-  regk_bif_core_bit21                      = 0x00000015,
-  regk_bif_core_bit22                      = 0x00000016,
-  regk_bif_core_bit23                      = 0x00000017,
-  regk_bif_core_bit24                      = 0x00000018,
-  regk_bif_core_bit25                      = 0x00000019,
-  regk_bif_core_bit26                      = 0x0000001a,
-  regk_bif_core_bit27                      = 0x0000001b,
-  regk_bif_core_bit28                      = 0x0000001c,
-  regk_bif_core_bit29                      = 0x0000001d,
-  regk_bif_core_bit9                       = 0x00000009,
-  regk_bif_core_bw16                       = 0x00000001,
-  regk_bif_core_bw32                       = 0x00000000,
-  regk_bif_core_bwe                        = 0x00000000,
-  regk_bif_core_cwe                        = 0x00000001,
-  regk_bif_core_e15us                      = 0x00000001,
-  regk_bif_core_e7800ns                    = 0x00000002,
-  regk_bif_core_grp0                       = 0x00000000,
-  regk_bif_core_grp1                       = 0x00000001,
-  regk_bif_core_mrs                        = 0x00000003,
-  regk_bif_core_no                         = 0x00000000,
-  regk_bif_core_none                       = 0x00000000,
-  regk_bif_core_nop                        = 0x00000000,
-  regk_bif_core_off                        = 0x00000000,
-  regk_bif_core_pre                        = 0x00000002,
-  regk_bif_core_r_sdram_ref_stat_default   = 0x00000001,
-  regk_bif_core_rd                         = 0x00000002,
-  regk_bif_core_ref                        = 0x00000001,
-  regk_bif_core_rs_sdram_ref_stat_default  = 0x00000001,
-  regk_bif_core_rw_grp1_cfg_default        = 0x000006cf,
-  regk_bif_core_rw_grp2_cfg_default        = 0x000006cf,
-  regk_bif_core_rw_grp3_cfg_default        = 0x000006cf,
-  regk_bif_core_rw_grp4_cfg_default        = 0x000006cf,
-  regk_bif_core_rw_sdram_cfg_grp1_default  = 0x00000000,
-  regk_bif_core_slf                        = 0x00000004,
-  regk_bif_core_wr                         = 0x00000001,
-  regk_bif_core_yes                        = 0x00000001
-};
-#endif /* __bif_core_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h b/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h
deleted file mode 100644
index b931c1aab679..000000000000
--- a/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h
+++ /dev/null
@@ -1,473 +0,0 @@
-#ifndef __bif_dma_defs_h
-#define __bif_dma_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/bif/rtl/bif_dma_regs.r
- *     id:           bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
- *     last modfied: Mon Apr 11 16:06:33 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r
- *      id: $Id: bif_dma_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_dma */
-
-/* Register rw_ch0_ctrl, scope bif_dma, type rw */
-typedef struct {
-  unsigned int bw         : 2;
-  unsigned int burst_len  : 1;
-  unsigned int cont       : 1;
-  unsigned int end_pad    : 1;
-  unsigned int cnt        : 1;
-  unsigned int dreq_pin   : 3;
-  unsigned int dreq_mode  : 2;
-  unsigned int tc_in_pin  : 3;
-  unsigned int tc_in_mode : 2;
-  unsigned int bus_mode   : 2;
-  unsigned int rate_en    : 1;
-  unsigned int wr_all     : 1;
-  unsigned int dummy1     : 12;
-} reg_bif_dma_rw_ch0_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0
-#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0
-
-/* Register rw_ch0_addr, scope bif_dma, type rw */
-typedef struct {
-  unsigned int addr : 32;
-} reg_bif_dma_rw_ch0_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4
-#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4
-
-/* Register rw_ch0_start, scope bif_dma, type rw */
-typedef struct {
-  unsigned int run : 1;
-  unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch0_start;
-#define REG_RD_ADDR_bif_dma_rw_ch0_start 8
-#define REG_WR_ADDR_bif_dma_rw_ch0_start 8
-
-/* Register rw_ch0_cnt, scope bif_dma, type rw */
-typedef struct {
-  unsigned int start_cnt : 16;
-  unsigned int dummy1    : 16;
-} reg_bif_dma_rw_ch0_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12
-#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12
-
-/* Register r_ch0_stat, scope bif_dma, type r */
-typedef struct {
-  unsigned int cnt : 16;
-  unsigned int dummy1 : 15;
-  unsigned int run : 1;
-} reg_bif_dma_r_ch0_stat;
-#define REG_RD_ADDR_bif_dma_r_ch0_stat 16
-
-/* Register rw_ch1_ctrl, scope bif_dma, type rw */
-typedef struct {
-  unsigned int bw          : 2;
-  unsigned int burst_len   : 1;
-  unsigned int cont        : 1;
-  unsigned int end_discard : 1;
-  unsigned int cnt         : 1;
-  unsigned int dreq_pin    : 3;
-  unsigned int dreq_mode   : 2;
-  unsigned int tc_in_pin   : 3;
-  unsigned int tc_in_mode  : 2;
-  unsigned int bus_mode    : 2;
-  unsigned int rate_en     : 1;
-  unsigned int dummy1      : 13;
-} reg_bif_dma_rw_ch1_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32
-#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32
-
-/* Register rw_ch1_addr, scope bif_dma, type rw */
-typedef struct {
-  unsigned int addr : 32;
-} reg_bif_dma_rw_ch1_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36
-#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36
-
-/* Register rw_ch1_start, scope bif_dma, type rw */
-typedef struct {
-  unsigned int run : 1;
-  unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch1_start;
-#define REG_RD_ADDR_bif_dma_rw_ch1_start 40
-#define REG_WR_ADDR_bif_dma_rw_ch1_start 40
-
-/* Register rw_ch1_cnt, scope bif_dma, type rw */
-typedef struct {
-  unsigned int start_cnt : 16;
-  unsigned int dummy1    : 16;
-} reg_bif_dma_rw_ch1_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44
-#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44
-
-/* Register r_ch1_stat, scope bif_dma, type r */
-typedef struct {
-  unsigned int cnt : 16;
-  unsigned int dummy1 : 15;
-  unsigned int run : 1;
-} reg_bif_dma_r_ch1_stat;
-#define REG_RD_ADDR_bif_dma_r_ch1_stat 48
-
-/* Register rw_ch2_ctrl, scope bif_dma, type rw */
-typedef struct {
-  unsigned int bw         : 2;
-  unsigned int burst_len  : 1;
-  unsigned int cont       : 1;
-  unsigned int end_pad    : 1;
-  unsigned int cnt        : 1;
-  unsigned int dreq_pin   : 3;
-  unsigned int dreq_mode  : 2;
-  unsigned int tc_in_pin  : 3;
-  unsigned int tc_in_mode : 2;
-  unsigned int bus_mode   : 2;
-  unsigned int rate_en    : 1;
-  unsigned int wr_all     : 1;
-  unsigned int dummy1     : 12;
-} reg_bif_dma_rw_ch2_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64
-#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64
-
-/* Register rw_ch2_addr, scope bif_dma, type rw */
-typedef struct {
-  unsigned int addr : 32;
-} reg_bif_dma_rw_ch2_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68
-#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68
-
-/* Register rw_ch2_start, scope bif_dma, type rw */
-typedef struct {
-  unsigned int run : 1;
-  unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch2_start;
-#define REG_RD_ADDR_bif_dma_rw_ch2_start 72
-#define REG_WR_ADDR_bif_dma_rw_ch2_start 72
-
-/* Register rw_ch2_cnt, scope bif_dma, type rw */
-typedef struct {
-  unsigned int start_cnt : 16;
-  unsigned int dummy1    : 16;
-} reg_bif_dma_rw_ch2_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76
-#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76
-
-/* Register r_ch2_stat, scope bif_dma, type r */
-typedef struct {
-  unsigned int cnt : 16;
-  unsigned int dummy1 : 15;
-  unsigned int run : 1;
-} reg_bif_dma_r_ch2_stat;
-#define REG_RD_ADDR_bif_dma_r_ch2_stat 80
-
-/* Register rw_ch3_ctrl, scope bif_dma, type rw */
-typedef struct {
-  unsigned int bw          : 2;
-  unsigned int burst_len   : 1;
-  unsigned int cont        : 1;
-  unsigned int end_discard : 1;
-  unsigned int cnt         : 1;
-  unsigned int dreq_pin    : 3;
-  unsigned int dreq_mode   : 2;
-  unsigned int tc_in_pin   : 3;
-  unsigned int tc_in_mode  : 2;
-  unsigned int bus_mode    : 2;
-  unsigned int rate_en     : 1;
-  unsigned int dummy1      : 13;
-} reg_bif_dma_rw_ch3_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96
-#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96
-
-/* Register rw_ch3_addr, scope bif_dma, type rw */
-typedef struct {
-  unsigned int addr : 32;
-} reg_bif_dma_rw_ch3_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100
-#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100
-
-/* Register rw_ch3_start, scope bif_dma, type rw */
-typedef struct {
-  unsigned int run : 1;
-  unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch3_start;
-#define REG_RD_ADDR_bif_dma_rw_ch3_start 104
-#define REG_WR_ADDR_bif_dma_rw_ch3_start 104
-
-/* Register rw_ch3_cnt, scope bif_dma, type rw */
-typedef struct {
-  unsigned int start_cnt : 16;
-  unsigned int dummy1    : 16;
-} reg_bif_dma_rw_ch3_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108
-#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108
-
-/* Register r_ch3_stat, scope bif_dma, type r */
-typedef struct {
-  unsigned int cnt : 16;
-  unsigned int dummy1 : 15;
-  unsigned int run : 1;
-} reg_bif_dma_r_ch3_stat;
-#define REG_RD_ADDR_bif_dma_r_ch3_stat 112
-
-/* Register rw_intr_mask, scope bif_dma, type rw */
-typedef struct {
-  unsigned int ext_dma0 : 1;
-  unsigned int ext_dma1 : 1;
-  unsigned int ext_dma2 : 1;
-  unsigned int ext_dma3 : 1;
-  unsigned int dummy1   : 28;
-} reg_bif_dma_rw_intr_mask;
-#define REG_RD_ADDR_bif_dma_rw_intr_mask 128
-#define REG_WR_ADDR_bif_dma_rw_intr_mask 128
-
-/* Register rw_ack_intr, scope bif_dma, type rw */
-typedef struct {
-  unsigned int ext_dma0 : 1;
-  unsigned int ext_dma1 : 1;
-  unsigned int ext_dma2 : 1;
-  unsigned int ext_dma3 : 1;
-  unsigned int dummy1   : 28;
-} reg_bif_dma_rw_ack_intr;
-#define REG_RD_ADDR_bif_dma_rw_ack_intr 132
-#define REG_WR_ADDR_bif_dma_rw_ack_intr 132
-
-/* Register r_intr, scope bif_dma, type r */
-typedef struct {
-  unsigned int ext_dma0 : 1;
-  unsigned int ext_dma1 : 1;
-  unsigned int ext_dma2 : 1;
-  unsigned int ext_dma3 : 1;
-  unsigned int dummy1   : 28;
-} reg_bif_dma_r_intr;
-#define REG_RD_ADDR_bif_dma_r_intr 136
-
-/* Register r_masked_intr, scope bif_dma, type r */
-typedef struct {
-  unsigned int ext_dma0 : 1;
-  unsigned int ext_dma1 : 1;
-  unsigned int ext_dma2 : 1;
-  unsigned int ext_dma3 : 1;
-  unsigned int dummy1   : 28;
-} reg_bif_dma_r_masked_intr;
-#define REG_RD_ADDR_bif_dma_r_masked_intr 140
-
-/* Register rw_pin0_cfg, scope bif_dma, type rw */
-typedef struct {
-  unsigned int master_ch   : 2;
-  unsigned int master_mode : 3;
-  unsigned int slave_ch    : 2;
-  unsigned int slave_mode  : 3;
-  unsigned int dummy1      : 22;
-} reg_bif_dma_rw_pin0_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160
-#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160
-
-/* Register rw_pin1_cfg, scope bif_dma, type rw */
-typedef struct {
-  unsigned int master_ch   : 2;
-  unsigned int master_mode : 3;
-  unsigned int slave_ch    : 2;
-  unsigned int slave_mode  : 3;
-  unsigned int dummy1      : 22;
-} reg_bif_dma_rw_pin1_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164
-#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164
-
-/* Register rw_pin2_cfg, scope bif_dma, type rw */
-typedef struct {
-  unsigned int master_ch   : 2;
-  unsigned int master_mode : 3;
-  unsigned int slave_ch    : 2;
-  unsigned int slave_mode  : 3;
-  unsigned int dummy1      : 22;
-} reg_bif_dma_rw_pin2_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168
-#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168
-
-/* Register rw_pin3_cfg, scope bif_dma, type rw */
-typedef struct {
-  unsigned int master_ch   : 2;
-  unsigned int master_mode : 3;
-  unsigned int slave_ch    : 2;
-  unsigned int slave_mode  : 3;
-  unsigned int dummy1      : 22;
-} reg_bif_dma_rw_pin3_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172
-#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172
-
-/* Register rw_pin4_cfg, scope bif_dma, type rw */
-typedef struct {
-  unsigned int master_ch   : 2;
-  unsigned int master_mode : 3;
-  unsigned int slave_ch    : 2;
-  unsigned int slave_mode  : 3;
-  unsigned int dummy1      : 22;
-} reg_bif_dma_rw_pin4_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176
-#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176
-
-/* Register rw_pin5_cfg, scope bif_dma, type rw */
-typedef struct {
-  unsigned int master_ch   : 2;
-  unsigned int master_mode : 3;
-  unsigned int slave_ch    : 2;
-  unsigned int slave_mode  : 3;
-  unsigned int dummy1      : 22;
-} reg_bif_dma_rw_pin5_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180
-#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180
-
-/* Register rw_pin6_cfg, scope bif_dma, type rw */
-typedef struct {
-  unsigned int master_ch   : 2;
-  unsigned int master_mode : 3;
-  unsigned int slave_ch    : 2;
-  unsigned int slave_mode  : 3;
-  unsigned int dummy1      : 22;
-} reg_bif_dma_rw_pin6_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184
-#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184
-
-/* Register rw_pin7_cfg, scope bif_dma, type rw */
-typedef struct {
-  unsigned int master_ch   : 2;
-  unsigned int master_mode : 3;
-  unsigned int slave_ch    : 2;
-  unsigned int slave_mode  : 3;
-  unsigned int dummy1      : 22;
-} reg_bif_dma_rw_pin7_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188
-#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188
-
-/* Register r_pin_stat, scope bif_dma, type r */
-typedef struct {
-  unsigned int pin0 : 1;
-  unsigned int pin1 : 1;
-  unsigned int pin2 : 1;
-  unsigned int pin3 : 1;
-  unsigned int pin4 : 1;
-  unsigned int pin5 : 1;
-  unsigned int pin6 : 1;
-  unsigned int pin7 : 1;
-  unsigned int dummy1 : 24;
-} reg_bif_dma_r_pin_stat;
-#define REG_RD_ADDR_bif_dma_r_pin_stat 192
-
-
-/* Constants */
-enum {
-  regk_bif_dma_as_master                   = 0x00000001,
-  regk_bif_dma_as_slave                    = 0x00000001,
-  regk_bif_dma_burst1                      = 0x00000000,
-  regk_bif_dma_burst8                      = 0x00000001,
-  regk_bif_dma_bw16                        = 0x00000001,
-  regk_bif_dma_bw32                        = 0x00000002,
-  regk_bif_dma_bw8                         = 0x00000000,
-  regk_bif_dma_dack                        = 0x00000006,
-  regk_bif_dma_dack_inv                    = 0x00000007,
-  regk_bif_dma_force                       = 0x00000001,
-  regk_bif_dma_hi                          = 0x00000003,
-  regk_bif_dma_inv                         = 0x00000003,
-  regk_bif_dma_lo                          = 0x00000002,
-  regk_bif_dma_master                      = 0x00000001,
-  regk_bif_dma_no                          = 0x00000000,
-  regk_bif_dma_norm                        = 0x00000002,
-  regk_bif_dma_off                         = 0x00000000,
-  regk_bif_dma_rw_ch0_ctrl_default         = 0x00000000,
-  regk_bif_dma_rw_ch0_start_default        = 0x00000000,
-  regk_bif_dma_rw_ch1_ctrl_default         = 0x00000000,
-  regk_bif_dma_rw_ch1_start_default        = 0x00000000,
-  regk_bif_dma_rw_ch2_ctrl_default         = 0x00000000,
-  regk_bif_dma_rw_ch2_start_default        = 0x00000000,
-  regk_bif_dma_rw_ch3_ctrl_default         = 0x00000000,
-  regk_bif_dma_rw_ch3_start_default        = 0x00000000,
-  regk_bif_dma_rw_intr_mask_default        = 0x00000000,
-  regk_bif_dma_rw_pin0_cfg_default         = 0x00000000,
-  regk_bif_dma_rw_pin1_cfg_default         = 0x00000000,
-  regk_bif_dma_rw_pin2_cfg_default         = 0x00000000,
-  regk_bif_dma_rw_pin3_cfg_default         = 0x00000000,
-  regk_bif_dma_rw_pin4_cfg_default         = 0x00000000,
-  regk_bif_dma_rw_pin5_cfg_default         = 0x00000000,
-  regk_bif_dma_rw_pin6_cfg_default         = 0x00000000,
-  regk_bif_dma_rw_pin7_cfg_default         = 0x00000000,
-  regk_bif_dma_slave                       = 0x00000002,
-  regk_bif_dma_sreq                        = 0x00000006,
-  regk_bif_dma_sreq_inv                    = 0x00000007,
-  regk_bif_dma_tc                          = 0x00000004,
-  regk_bif_dma_tc_inv                      = 0x00000005,
-  regk_bif_dma_yes                         = 0x00000001
-};
-#endif /* __bif_dma_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h b/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h
deleted file mode 100644
index d18fc3c9f569..000000000000
--- a/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h
+++ /dev/null
@@ -1,249 +0,0 @@
-#ifndef __bif_slave_defs_h
-#define __bif_slave_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/bif/rtl/bif_slave_regs.r
- *     id:           bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
- *     last modfied: Mon Apr 11 16:06:34 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r
- *      id: $Id: bif_slave_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_slave */
-
-/* Register rw_slave_cfg, scope bif_slave, type rw */
-typedef struct {
-  unsigned int slave_id     : 3;
-  unsigned int use_slave_id : 1;
-  unsigned int boot_rdy     : 1;
-  unsigned int loopback     : 1;
-  unsigned int dis          : 1;
-  unsigned int dummy1       : 25;
-} reg_bif_slave_rw_slave_cfg;
-#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0
-#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0
-
-/* Register r_slave_mode, scope bif_slave, type r */
-typedef struct {
-  unsigned int ch0_mode : 1;
-  unsigned int ch1_mode : 1;
-  unsigned int ch2_mode : 1;
-  unsigned int ch3_mode : 1;
-  unsigned int dummy1   : 28;
-} reg_bif_slave_r_slave_mode;
-#define REG_RD_ADDR_bif_slave_r_slave_mode 4
-
-/* Register rw_ch0_cfg, scope bif_slave, type rw */
-typedef struct {
-  unsigned int rd_hold     : 2;
-  unsigned int access_mode : 1;
-  unsigned int access_ctrl : 1;
-  unsigned int data_cs     : 2;
-  unsigned int dummy1      : 26;
-} reg_bif_slave_rw_ch0_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16
-#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16
-
-/* Register rw_ch1_cfg, scope bif_slave, type rw */
-typedef struct {
-  unsigned int rd_hold     : 2;
-  unsigned int access_mode : 1;
-  unsigned int access_ctrl : 1;
-  unsigned int data_cs     : 2;
-  unsigned int dummy1      : 26;
-} reg_bif_slave_rw_ch1_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20
-#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20
-
-/* Register rw_ch2_cfg, scope bif_slave, type rw */
-typedef struct {
-  unsigned int rd_hold     : 2;
-  unsigned int access_mode : 1;
-  unsigned int access_ctrl : 1;
-  unsigned int data_cs     : 2;
-  unsigned int dummy1      : 26;
-} reg_bif_slave_rw_ch2_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24
-#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24
-
-/* Register rw_ch3_cfg, scope bif_slave, type rw */
-typedef struct {
-  unsigned int rd_hold     : 2;
-  unsigned int access_mode : 1;
-  unsigned int access_ctrl : 1;
-  unsigned int data_cs     : 2;
-  unsigned int dummy1      : 26;
-} reg_bif_slave_rw_ch3_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28
-#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28
-
-/* Register rw_arb_cfg, scope bif_slave, type rw */
-typedef struct {
-  unsigned int brin_mode   : 1;
-  unsigned int brout_mode  : 3;
-  unsigned int bg_mode     : 3;
-  unsigned int release     : 2;
-  unsigned int acquire     : 1;
-  unsigned int settle_time : 2;
-  unsigned int dram_ctrl   : 1;
-  unsigned int dummy1      : 19;
-} reg_bif_slave_rw_arb_cfg;
-#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32
-#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32
-
-/* Register r_arb_stat, scope bif_slave, type r */
-typedef struct {
-  unsigned int init_mode : 1;
-  unsigned int mode      : 1;
-  unsigned int brin      : 1;
-  unsigned int brout     : 1;
-  unsigned int bg        : 1;
-  unsigned int dummy1    : 27;
-} reg_bif_slave_r_arb_stat;
-#define REG_RD_ADDR_bif_slave_r_arb_stat 36
-
-/* Register rw_intr_mask, scope bif_slave, type rw */
-typedef struct {
-  unsigned int bus_release : 1;
-  unsigned int bus_acquire : 1;
-  unsigned int dummy1      : 30;
-} reg_bif_slave_rw_intr_mask;
-#define REG_RD_ADDR_bif_slave_rw_intr_mask 64
-#define REG_WR_ADDR_bif_slave_rw_intr_mask 64
-
-/* Register rw_ack_intr, scope bif_slave, type rw */
-typedef struct {
-  unsigned int bus_release : 1;
-  unsigned int bus_acquire : 1;
-  unsigned int dummy1      : 30;
-} reg_bif_slave_rw_ack_intr;
-#define REG_RD_ADDR_bif_slave_rw_ack_intr 68
-#define REG_WR_ADDR_bif_slave_rw_ack_intr 68
-
-/* Register r_intr, scope bif_slave, type r */
-typedef struct {
-  unsigned int bus_release : 1;
-  unsigned int bus_acquire : 1;
-  unsigned int dummy1      : 30;
-} reg_bif_slave_r_intr;
-#define REG_RD_ADDR_bif_slave_r_intr 72
-
-/* Register r_masked_intr, scope bif_slave, type r */
-typedef struct {
-  unsigned int bus_release : 1;
-  unsigned int bus_acquire : 1;
-  unsigned int dummy1      : 30;
-} reg_bif_slave_r_masked_intr;
-#define REG_RD_ADDR_bif_slave_r_masked_intr 76
-
-
-/* Constants */
-enum {
-  regk_bif_slave_active_hi                 = 0x00000003,
-  regk_bif_slave_active_lo                 = 0x00000002,
-  regk_bif_slave_addr                      = 0x00000000,
-  regk_bif_slave_always                    = 0x00000001,
-  regk_bif_slave_at_idle                   = 0x00000002,
-  regk_bif_slave_burst_end                 = 0x00000003,
-  regk_bif_slave_dma                       = 0x00000001,
-  regk_bif_slave_hi                        = 0x00000003,
-  regk_bif_slave_inv                       = 0x00000001,
-  regk_bif_slave_lo                        = 0x00000002,
-  regk_bif_slave_local                     = 0x00000001,
-  regk_bif_slave_master                    = 0x00000000,
-  regk_bif_slave_mode_reg                  = 0x00000001,
-  regk_bif_slave_no                        = 0x00000000,
-  regk_bif_slave_norm                      = 0x00000000,
-  regk_bif_slave_on_access                 = 0x00000000,
-  regk_bif_slave_rw_arb_cfg_default        = 0x00000000,
-  regk_bif_slave_rw_ch0_cfg_default        = 0x00000000,
-  regk_bif_slave_rw_ch1_cfg_default        = 0x00000000,
-  regk_bif_slave_rw_ch2_cfg_default        = 0x00000000,
-  regk_bif_slave_rw_ch3_cfg_default        = 0x00000000,
-  regk_bif_slave_rw_intr_mask_default      = 0x00000000,
-  regk_bif_slave_rw_slave_cfg_default      = 0x00000000,
-  regk_bif_slave_shared                    = 0x00000000,
-  regk_bif_slave_slave                     = 0x00000001,
-  regk_bif_slave_t0ns                      = 0x00000003,
-  regk_bif_slave_t10ns                     = 0x00000002,
-  regk_bif_slave_t20ns                     = 0x00000003,
-  regk_bif_slave_t30ns                     = 0x00000002,
-  regk_bif_slave_t40ns                     = 0x00000001,
-  regk_bif_slave_t50ns                     = 0x00000000,
-  regk_bif_slave_yes                       = 0x00000001,
-  regk_bif_slave_z                         = 0x00000004
-};
-#endif /* __bif_slave_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/config_defs.h b/include/asm-cris/arch-v32/hwregs/config_defs.h
deleted file mode 100644
index 45457a4e3817..000000000000
--- a/include/asm-cris/arch-v32/hwregs/config_defs.h
+++ /dev/null
@@ -1,142 +0,0 @@
-#ifndef __config_defs_h
-#define __config_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../rtl/config_regs.r
- *     id:           config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
- *     last modfied: Thu Mar  4 12:34:39 2004
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r
- *      id: $Id: config_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope config */
-
-/* Register r_bootsel, scope config, type r */
-typedef struct {
-  unsigned int boot_mode   : 3;
-  unsigned int full_duplex : 1;
-  unsigned int user        : 1;
-  unsigned int pll         : 1;
-  unsigned int flash_bw    : 1;
-  unsigned int dummy1      : 25;
-} reg_config_r_bootsel;
-#define REG_RD_ADDR_config_r_bootsel 0
-
-/* Register rw_clk_ctrl, scope config, type rw */
-typedef struct {
-  unsigned int pll          : 1;
-  unsigned int cpu          : 1;
-  unsigned int iop          : 1;
-  unsigned int dma01_eth0   : 1;
-  unsigned int dma23        : 1;
-  unsigned int dma45        : 1;
-  unsigned int dma67        : 1;
-  unsigned int dma89_strcop : 1;
-  unsigned int bif          : 1;
-  unsigned int fix_io       : 1;
-  unsigned int dummy1       : 22;
-} reg_config_rw_clk_ctrl;
-#define REG_RD_ADDR_config_rw_clk_ctrl 4
-#define REG_WR_ADDR_config_rw_clk_ctrl 4
-
-/* Register rw_pad_ctrl, scope config, type rw */
-typedef struct {
-  unsigned int usb_susp : 1;
-  unsigned int phyrst_n : 1;
-  unsigned int dummy1   : 30;
-} reg_config_rw_pad_ctrl;
-#define REG_RD_ADDR_config_rw_pad_ctrl 8
-#define REG_WR_ADDR_config_rw_pad_ctrl 8
-
-
-/* Constants */
-enum {
-  regk_config_bw16                         = 0x00000000,
-  regk_config_bw32                         = 0x00000001,
-  regk_config_master                       = 0x00000005,
-  regk_config_nand                         = 0x00000003,
-  regk_config_net_rx                       = 0x00000001,
-  regk_config_net_tx_rx                    = 0x00000002,
-  regk_config_no                           = 0x00000000,
-  regk_config_none                         = 0x00000007,
-  regk_config_nor                          = 0x00000000,
-  regk_config_rw_clk_ctrl_default          = 0x00000002,
-  regk_config_rw_pad_ctrl_default          = 0x00000000,
-  regk_config_ser                          = 0x00000004,
-  regk_config_slave                        = 0x00000006,
-  regk_config_yes                          = 0x00000001
-};
-#endif /* __config_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/cpu_vect.h b/include/asm-cris/arch-v32/hwregs/cpu_vect.h
deleted file mode 100644
index 8370aee8a14a..000000000000
--- a/include/asm-cris/arch-v32/hwregs/cpu_vect.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
- from ../../inst/crisp/doc/cpu_vect.r
-version . */
-
-#ifndef _______INST_CRISP_DOC_CPU_VECT_R
-#define _______INST_CRISP_DOC_CPU_VECT_R
-#define NMI_INTR_VECT	0x00
-#define RESERVED_1_INTR_VECT	0x01
-#define RESERVED_2_INTR_VECT	0x02
-#define SINGLE_STEP_INTR_VECT	0x03
-#define INSTR_TLB_REFILL_INTR_VECT	0x04
-#define INSTR_TLB_INV_INTR_VECT	0x05
-#define INSTR_TLB_ACC_INTR_VECT	0x06
-#define TLB_EX_INTR_VECT	0x07
-#define DATA_TLB_REFILL_INTR_VECT	0x08
-#define DATA_TLB_INV_INTR_VECT	0x09
-#define DATA_TLB_ACC_INTR_VECT	0x0a
-#define DATA_TLB_WE_INTR_VECT	0x0b
-#define HW_BP_INTR_VECT	0x0c
-#define RESERVED_D_INTR_VECT	0x0d
-#define RESERVED_E_INTR_VECT	0x0e
-#define RESERVED_F_INTR_VECT	0x0f
-#define BREAK_0_INTR_VECT	0x10
-#define BREAK_1_INTR_VECT	0x11
-#define BREAK_2_INTR_VECT	0x12
-#define BREAK_3_INTR_VECT	0x13
-#define BREAK_4_INTR_VECT	0x14
-#define BREAK_5_INTR_VECT	0x15
-#define BREAK_6_INTR_VECT	0x16
-#define BREAK_7_INTR_VECT	0x17
-#define BREAK_8_INTR_VECT	0x18
-#define BREAK_9_INTR_VECT	0x19
-#define BREAK_10_INTR_VECT	0x1a
-#define BREAK_11_INTR_VECT	0x1b
-#define BREAK_12_INTR_VECT	0x1c
-#define BREAK_13_INTR_VECT	0x1d
-#define BREAK_14_INTR_VECT	0x1e
-#define BREAK_15_INTR_VECT	0x1f
-#define MULTIPLE_INTR_VECT	0x30
-
-#endif
diff --git a/include/asm-cris/arch-v32/hwregs/dma.h b/include/asm-cris/arch-v32/hwregs/dma.h
deleted file mode 100644
index 3ce322b5c731..000000000000
--- a/include/asm-cris/arch-v32/hwregs/dma.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * DMA C definitions and help macros
- *
- */
-
-#ifndef dma_h
-#define dma_h
-
-/* registers */ /* Really needed, since both are listed in sw.list? */
-#include "dma_defs.h"
-
-
-/* descriptors */
-
-// ------------------------------------------------------------ dma_descr_group
-typedef struct dma_descr_group {
-  struct dma_descr_group       *next;
-  unsigned                      eol        : 1;
-  unsigned                      tol        : 1;
-  unsigned                      bol        : 1;
-  unsigned                                 : 1;
-  unsigned                      intr       : 1;
-  unsigned                                 : 2;
-  unsigned                      en         : 1;
-  unsigned                                 : 7;
-  unsigned                      dis        : 1;
-  unsigned                      md         : 16;
-  struct dma_descr_group       *up;
-  union {
-    struct dma_descr_context   *context;
-    struct dma_descr_group     *group;
-  }                             down;
-} dma_descr_group;
-
-// ---------------------------------------------------------- dma_descr_context
-typedef struct dma_descr_context {
-  struct dma_descr_context     *next;
-  unsigned                      eol        : 1;
-  unsigned                                 : 3;
-  unsigned                      intr       : 1;
-  unsigned                                 : 1;
-  unsigned                      store_mode : 1;
-  unsigned                      en         : 1;
-  unsigned                                 : 7;
-  unsigned                      dis        : 1;
-  unsigned                      md0        : 16;
-  unsigned                      md1;
-  unsigned                      md2;
-  unsigned                      md3;
-  unsigned                      md4;
-  struct dma_descr_data        *saved_data;
-  char                         *saved_data_buf;
-} dma_descr_context;
-
-// ------------------------------------------------------------- dma_descr_data
-typedef struct dma_descr_data {
-  struct dma_descr_data        *next;
-  char                         *buf;
-  unsigned                      eol        : 1;
-  unsigned                                 : 2;
-  unsigned                      out_eop    : 1;
-  unsigned                      intr       : 1;
-  unsigned                      wait       : 1;
-  unsigned                                 : 2;
-  unsigned                                 : 3;
-  unsigned                      in_eop     : 1;
-  unsigned                                 : 4;
-  unsigned                      md         : 16;
-  char                         *after;
-} dma_descr_data;
-
-// --------------------------------------------------------------------- macros
-
-// enable DMA channel
-#define DMA_ENABLE( inst ) \
-   do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\
-        e.en = regk_dma_yes; \
-        REG_WR( dma, inst, rw_cfg, e); } while( 0 )
-
-// reset DMA channel
-#define DMA_RESET( inst ) \
-   do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\
-        r.en = regk_dma_no; \
-        REG_WR( dma, inst, rw_cfg, r); } while( 0 )
-
-// stop DMA channel
-#define DMA_STOP( inst ) \
-   do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\
-        s.stop = regk_dma_yes; \
-        REG_WR( dma, inst, rw_cfg, s); } while( 0 )
-
-// continue DMA channel operation
-#define DMA_CONTINUE( inst ) \
-   do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\
-        c.stop = regk_dma_no; \
-        REG_WR( dma, inst, rw_cfg, c); } while( 0 )
-
-// give stream command
-#define DMA_WR_CMD( inst, cmd_par ) \
-   do { reg_dma_rw_stream_cmd __x = {0}; \
-	do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \
-	__x.cmd = (cmd_par); \
-	REG_WR(dma, inst, rw_stream_cmd, __x); \
-   } while (0)
-
-// load: g,c,d:burst
-#define DMA_START_GROUP( inst, group_descr ) \
-   do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \
-        DMA_WR_CMD( inst, regk_dma_load_g ); \
-        DMA_WR_CMD( inst, regk_dma_load_c ); \
-        DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
-      } while( 0 )
-
-// load: c,d:burst
-#define DMA_START_CONTEXT( inst, ctx_descr ) \
-   do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \
-        DMA_WR_CMD( inst, regk_dma_load_c ); \
-        DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
-      } while( 0 )
-
-// if the DMA is at the end of the data list, the last data descr is reloaded
-#define DMA_CONTINUE_DATA( inst ) \
-do { reg_dma_rw_cmd c = {0}; \
-     c.cont_data = regk_dma_yes;\
-     REG_WR( dma, inst, rw_cmd, c ); } while( 0 )
-
-#endif
diff --git a/include/asm-cris/arch-v32/hwregs/dma_defs.h b/include/asm-cris/arch-v32/hwregs/dma_defs.h
deleted file mode 100644
index 48ac8cef7ebe..000000000000
--- a/include/asm-cris/arch-v32/hwregs/dma_defs.h
+++ /dev/null
@@ -1,436 +0,0 @@
-#ifndef __dma_defs_h
-#define __dma_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
- *     id:           dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
- *     last modfied: Mon Apr 11 16:06:51 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
- *      id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope dma */
-
-/* Register rw_data, scope dma, type rw */
-typedef unsigned int reg_dma_rw_data;
-#define REG_RD_ADDR_dma_rw_data 0
-#define REG_WR_ADDR_dma_rw_data 0
-
-/* Register rw_data_next, scope dma, type rw */
-typedef unsigned int reg_dma_rw_data_next;
-#define REG_RD_ADDR_dma_rw_data_next 4
-#define REG_WR_ADDR_dma_rw_data_next 4
-
-/* Register rw_data_buf, scope dma, type rw */
-typedef unsigned int reg_dma_rw_data_buf;
-#define REG_RD_ADDR_dma_rw_data_buf 8
-#define REG_WR_ADDR_dma_rw_data_buf 8
-
-/* Register rw_data_ctrl, scope dma, type rw */
-typedef struct {
-  unsigned int eol     : 1;
-  unsigned int dummy1  : 2;
-  unsigned int out_eop : 1;
-  unsigned int intr    : 1;
-  unsigned int wait    : 1;
-  unsigned int dummy2  : 26;
-} reg_dma_rw_data_ctrl;
-#define REG_RD_ADDR_dma_rw_data_ctrl 12
-#define REG_WR_ADDR_dma_rw_data_ctrl 12
-
-/* Register rw_data_stat, scope dma, type rw */
-typedef struct {
-  unsigned int dummy1 : 3;
-  unsigned int in_eop : 1;
-  unsigned int dummy2 : 28;
-} reg_dma_rw_data_stat;
-#define REG_RD_ADDR_dma_rw_data_stat 16
-#define REG_WR_ADDR_dma_rw_data_stat 16
-
-/* Register rw_data_md, scope dma, type rw */
-typedef struct {
-  unsigned int md : 16;
-  unsigned int dummy1 : 16;
-} reg_dma_rw_data_md;
-#define REG_RD_ADDR_dma_rw_data_md 20
-#define REG_WR_ADDR_dma_rw_data_md 20
-
-/* Register rw_data_md_s, scope dma, type rw */
-typedef struct {
-  unsigned int md_s : 16;
-  unsigned int dummy1 : 16;
-} reg_dma_rw_data_md_s;
-#define REG_RD_ADDR_dma_rw_data_md_s 24
-#define REG_WR_ADDR_dma_rw_data_md_s 24
-
-/* Register rw_data_after, scope dma, type rw */
-typedef unsigned int reg_dma_rw_data_after;
-#define REG_RD_ADDR_dma_rw_data_after 28
-#define REG_WR_ADDR_dma_rw_data_after 28
-
-/* Register rw_ctxt, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt;
-#define REG_RD_ADDR_dma_rw_ctxt 32
-#define REG_WR_ADDR_dma_rw_ctxt 32
-
-/* Register rw_ctxt_next, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_next;
-#define REG_RD_ADDR_dma_rw_ctxt_next 36
-#define REG_WR_ADDR_dma_rw_ctxt_next 36
-
-/* Register rw_ctxt_ctrl, scope dma, type rw */
-typedef struct {
-  unsigned int eol        : 1;
-  unsigned int dummy1     : 3;
-  unsigned int intr       : 1;
-  unsigned int dummy2     : 1;
-  unsigned int store_mode : 1;
-  unsigned int en         : 1;
-  unsigned int dummy3     : 24;
-} reg_dma_rw_ctxt_ctrl;
-#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40
-#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40
-
-/* Register rw_ctxt_stat, scope dma, type rw */
-typedef struct {
-  unsigned int dummy1 : 7;
-  unsigned int dis : 1;
-  unsigned int dummy2 : 24;
-} reg_dma_rw_ctxt_stat;
-#define REG_RD_ADDR_dma_rw_ctxt_stat 44
-#define REG_WR_ADDR_dma_rw_ctxt_stat 44
-
-/* Register rw_ctxt_md0, scope dma, type rw */
-typedef struct {
-  unsigned int md0 : 16;
-  unsigned int dummy1 : 16;
-} reg_dma_rw_ctxt_md0;
-#define REG_RD_ADDR_dma_rw_ctxt_md0 48
-#define REG_WR_ADDR_dma_rw_ctxt_md0 48
-
-/* Register rw_ctxt_md0_s, scope dma, type rw */
-typedef struct {
-  unsigned int md0_s : 16;
-  unsigned int dummy1 : 16;
-} reg_dma_rw_ctxt_md0_s;
-#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52
-#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52
-
-/* Register rw_ctxt_md1, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md1;
-#define REG_RD_ADDR_dma_rw_ctxt_md1 56
-#define REG_WR_ADDR_dma_rw_ctxt_md1 56
-
-/* Register rw_ctxt_md1_s, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md1_s;
-#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60
-#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60
-
-/* Register rw_ctxt_md2, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md2;
-#define REG_RD_ADDR_dma_rw_ctxt_md2 64
-#define REG_WR_ADDR_dma_rw_ctxt_md2 64
-
-/* Register rw_ctxt_md2_s, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md2_s;
-#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68
-#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68
-
-/* Register rw_ctxt_md3, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md3;
-#define REG_RD_ADDR_dma_rw_ctxt_md3 72
-#define REG_WR_ADDR_dma_rw_ctxt_md3 72
-
-/* Register rw_ctxt_md3_s, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md3_s;
-#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76
-#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76
-
-/* Register rw_ctxt_md4, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md4;
-#define REG_RD_ADDR_dma_rw_ctxt_md4 80
-#define REG_WR_ADDR_dma_rw_ctxt_md4 80
-
-/* Register rw_ctxt_md4_s, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md4_s;
-#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84
-#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84
-
-/* Register rw_saved_data, scope dma, type rw */
-typedef unsigned int reg_dma_rw_saved_data;
-#define REG_RD_ADDR_dma_rw_saved_data 88
-#define REG_WR_ADDR_dma_rw_saved_data 88
-
-/* Register rw_saved_data_buf, scope dma, type rw */
-typedef unsigned int reg_dma_rw_saved_data_buf;
-#define REG_RD_ADDR_dma_rw_saved_data_buf 92
-#define REG_WR_ADDR_dma_rw_saved_data_buf 92
-
-/* Register rw_group, scope dma, type rw */
-typedef unsigned int reg_dma_rw_group;
-#define REG_RD_ADDR_dma_rw_group 96
-#define REG_WR_ADDR_dma_rw_group 96
-
-/* Register rw_group_next, scope dma, type rw */
-typedef unsigned int reg_dma_rw_group_next;
-#define REG_RD_ADDR_dma_rw_group_next 100
-#define REG_WR_ADDR_dma_rw_group_next 100
-
-/* Register rw_group_ctrl, scope dma, type rw */
-typedef struct {
-  unsigned int eol  : 1;
-  unsigned int tol  : 1;
-  unsigned int bol  : 1;
-  unsigned int dummy1 : 1;
-  unsigned int intr : 1;
-  unsigned int dummy2 : 2;
-  unsigned int en   : 1;
-  unsigned int dummy3 : 24;
-} reg_dma_rw_group_ctrl;
-#define REG_RD_ADDR_dma_rw_group_ctrl 104
-#define REG_WR_ADDR_dma_rw_group_ctrl 104
-
-/* Register rw_group_stat, scope dma, type rw */
-typedef struct {
-  unsigned int dummy1 : 7;
-  unsigned int dis : 1;
-  unsigned int dummy2 : 24;
-} reg_dma_rw_group_stat;
-#define REG_RD_ADDR_dma_rw_group_stat 108
-#define REG_WR_ADDR_dma_rw_group_stat 108
-
-/* Register rw_group_md, scope dma, type rw */
-typedef struct {
-  unsigned int md : 16;
-  unsigned int dummy1 : 16;
-} reg_dma_rw_group_md;
-#define REG_RD_ADDR_dma_rw_group_md 112
-#define REG_WR_ADDR_dma_rw_group_md 112
-
-/* Register rw_group_md_s, scope dma, type rw */
-typedef struct {
-  unsigned int md_s : 16;
-  unsigned int dummy1 : 16;
-} reg_dma_rw_group_md_s;
-#define REG_RD_ADDR_dma_rw_group_md_s 116
-#define REG_WR_ADDR_dma_rw_group_md_s 116
-
-/* Register rw_group_up, scope dma, type rw */
-typedef unsigned int reg_dma_rw_group_up;
-#define REG_RD_ADDR_dma_rw_group_up 120
-#define REG_WR_ADDR_dma_rw_group_up 120
-
-/* Register rw_group_down, scope dma, type rw */
-typedef unsigned int reg_dma_rw_group_down;
-#define REG_RD_ADDR_dma_rw_group_down 124
-#define REG_WR_ADDR_dma_rw_group_down 124
-
-/* Register rw_cmd, scope dma, type rw */
-typedef struct {
-  unsigned int cont_data : 1;
-  unsigned int dummy1    : 31;
-} reg_dma_rw_cmd;
-#define REG_RD_ADDR_dma_rw_cmd 128
-#define REG_WR_ADDR_dma_rw_cmd 128
-
-/* Register rw_cfg, scope dma, type rw */
-typedef struct {
-  unsigned int en   : 1;
-  unsigned int stop : 1;
-  unsigned int dummy1 : 30;
-} reg_dma_rw_cfg;
-#define REG_RD_ADDR_dma_rw_cfg 132
-#define REG_WR_ADDR_dma_rw_cfg 132
-
-/* Register rw_stat, scope dma, type rw */
-typedef struct {
-  unsigned int mode           : 5;
-  unsigned int list_state     : 3;
-  unsigned int stream_cmd_src : 8;
-  unsigned int dummy1         : 8;
-  unsigned int buf            : 8;
-} reg_dma_rw_stat;
-#define REG_RD_ADDR_dma_rw_stat 136
-#define REG_WR_ADDR_dma_rw_stat 136
-
-/* Register rw_intr_mask, scope dma, type rw */
-typedef struct {
-  unsigned int group      : 1;
-  unsigned int ctxt       : 1;
-  unsigned int data       : 1;
-  unsigned int in_eop     : 1;
-  unsigned int stream_cmd : 1;
-  unsigned int dummy1     : 27;
-} reg_dma_rw_intr_mask;
-#define REG_RD_ADDR_dma_rw_intr_mask 140
-#define REG_WR_ADDR_dma_rw_intr_mask 140
-
-/* Register rw_ack_intr, scope dma, type rw */
-typedef struct {
-  unsigned int group      : 1;
-  unsigned int ctxt       : 1;
-  unsigned int data       : 1;
-  unsigned int in_eop     : 1;
-  unsigned int stream_cmd : 1;
-  unsigned int dummy1     : 27;
-} reg_dma_rw_ack_intr;
-#define REG_RD_ADDR_dma_rw_ack_intr 144
-#define REG_WR_ADDR_dma_rw_ack_intr 144
-
-/* Register r_intr, scope dma, type r */
-typedef struct {
-  unsigned int group      : 1;
-  unsigned int ctxt       : 1;
-  unsigned int data       : 1;
-  unsigned int in_eop     : 1;
-  unsigned int stream_cmd : 1;
-  unsigned int dummy1     : 27;
-} reg_dma_r_intr;
-#define REG_RD_ADDR_dma_r_intr 148
-
-/* Register r_masked_intr, scope dma, type r */
-typedef struct {
-  unsigned int group      : 1;
-  unsigned int ctxt       : 1;
-  unsigned int data       : 1;
-  unsigned int in_eop     : 1;
-  unsigned int stream_cmd : 1;
-  unsigned int dummy1     : 27;
-} reg_dma_r_masked_intr;
-#define REG_RD_ADDR_dma_r_masked_intr 152
-
-/* Register rw_stream_cmd, scope dma, type rw */
-typedef struct {
-  unsigned int cmd  : 10;
-  unsigned int dummy1 : 6;
-  unsigned int n    : 8;
-  unsigned int dummy2 : 7;
-  unsigned int busy : 1;
-} reg_dma_rw_stream_cmd;
-#define REG_RD_ADDR_dma_rw_stream_cmd 156
-#define REG_WR_ADDR_dma_rw_stream_cmd 156
-
-
-/* Constants */
-enum {
-  regk_dma_ack_pkt                         = 0x00000100,
-  regk_dma_anytime                         = 0x00000001,
-  regk_dma_array                           = 0x00000008,
-  regk_dma_burst                           = 0x00000020,
-  regk_dma_client                          = 0x00000002,
-  regk_dma_copy_next                       = 0x00000010,
-  regk_dma_copy_up                         = 0x00000020,
-  regk_dma_data_at_eol                     = 0x00000001,
-  regk_dma_dis_c                           = 0x00000010,
-  regk_dma_dis_g                           = 0x00000020,
-  regk_dma_idle                            = 0x00000001,
-  regk_dma_intern                          = 0x00000004,
-  regk_dma_load_c                          = 0x00000200,
-  regk_dma_load_c_n                        = 0x00000280,
-  regk_dma_load_c_next                     = 0x00000240,
-  regk_dma_load_d                          = 0x00000140,
-  regk_dma_load_g                          = 0x00000300,
-  regk_dma_load_g_down                     = 0x000003c0,
-  regk_dma_load_g_next                     = 0x00000340,
-  regk_dma_load_g_up                       = 0x00000380,
-  regk_dma_next_en                         = 0x00000010,
-  regk_dma_next_pkt                        = 0x00000010,
-  regk_dma_no                              = 0x00000000,
-  regk_dma_only_at_wait                    = 0x00000000,
-  regk_dma_restore                         = 0x00000020,
-  regk_dma_rst                             = 0x00000001,
-  regk_dma_running                         = 0x00000004,
-  regk_dma_rw_cfg_default                  = 0x00000000,
-  regk_dma_rw_cmd_default                  = 0x00000000,
-  regk_dma_rw_intr_mask_default            = 0x00000000,
-  regk_dma_rw_stat_default                 = 0x00000101,
-  regk_dma_rw_stream_cmd_default           = 0x00000000,
-  regk_dma_save_down                       = 0x00000020,
-  regk_dma_save_up                         = 0x00000020,
-  regk_dma_set_reg                         = 0x00000050,
-  regk_dma_set_w_size1                     = 0x00000190,
-  regk_dma_set_w_size2                     = 0x000001a0,
-  regk_dma_set_w_size4                     = 0x000001c0,
-  regk_dma_stopped                         = 0x00000002,
-  regk_dma_store_c                         = 0x00000002,
-  regk_dma_store_descr                     = 0x00000000,
-  regk_dma_store_g                         = 0x00000004,
-  regk_dma_store_md                        = 0x00000001,
-  regk_dma_sw                              = 0x00000008,
-  regk_dma_update_down                     = 0x00000020,
-  regk_dma_yes                             = 0x00000001
-};
-#endif /* __dma_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/eth_defs.h b/include/asm-cris/arch-v32/hwregs/eth_defs.h
deleted file mode 100644
index 90fe8a28894f..000000000000
--- a/include/asm-cris/arch-v32/hwregs/eth_defs.h
+++ /dev/null
@@ -1,378 +0,0 @@
-#ifndef __eth_defs_h
-#define __eth_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           eth.r
- *     id:           eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp
- *     last modfied: Mon Jan  9 06:06:41 2006
- *
- *   by /n/asic/design/tools/rdesc/rdes2c eth.r
- *      id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope eth */
-
-/* Register rw_ma0_lo, scope eth, type rw */
-typedef struct {
-  unsigned int addr : 32;
-} reg_eth_rw_ma0_lo;
-#define REG_RD_ADDR_eth_rw_ma0_lo 0
-#define REG_WR_ADDR_eth_rw_ma0_lo 0
-
-/* Register rw_ma0_hi, scope eth, type rw */
-typedef struct {
-  unsigned int addr : 16;
-  unsigned int dummy1 : 16;
-} reg_eth_rw_ma0_hi;
-#define REG_RD_ADDR_eth_rw_ma0_hi 4
-#define REG_WR_ADDR_eth_rw_ma0_hi 4
-
-/* Register rw_ma1_lo, scope eth, type rw */
-typedef struct {
-  unsigned int addr : 32;
-} reg_eth_rw_ma1_lo;
-#define REG_RD_ADDR_eth_rw_ma1_lo 8
-#define REG_WR_ADDR_eth_rw_ma1_lo 8
-
-/* Register rw_ma1_hi, scope eth, type rw */
-typedef struct {
-  unsigned int addr : 16;
-  unsigned int dummy1 : 16;
-} reg_eth_rw_ma1_hi;
-#define REG_RD_ADDR_eth_rw_ma1_hi 12
-#define REG_WR_ADDR_eth_rw_ma1_hi 12
-
-/* Register rw_ga_lo, scope eth, type rw */
-typedef struct {
-  unsigned int tbl : 32;
-} reg_eth_rw_ga_lo;
-#define REG_RD_ADDR_eth_rw_ga_lo 16
-#define REG_WR_ADDR_eth_rw_ga_lo 16
-
-/* Register rw_ga_hi, scope eth, type rw */
-typedef struct {
-  unsigned int tbl : 32;
-} reg_eth_rw_ga_hi;
-#define REG_RD_ADDR_eth_rw_ga_hi 20
-#define REG_WR_ADDR_eth_rw_ga_hi 20
-
-/* Register rw_gen_ctrl, scope eth, type rw */
-typedef struct {
-  unsigned int en         : 1;
-  unsigned int phy        : 2;
-  unsigned int protocol   : 1;
-  unsigned int loopback   : 1;
-  unsigned int flow_ctrl  : 1;
-  unsigned int gtxclk_out : 1;
-  unsigned int phyrst_n   : 1;
-  unsigned int dummy1     : 24;
-} reg_eth_rw_gen_ctrl;
-#define REG_RD_ADDR_eth_rw_gen_ctrl 24
-#define REG_WR_ADDR_eth_rw_gen_ctrl 24
-
-/* Register rw_rec_ctrl, scope eth, type rw */
-typedef struct {
-  unsigned int ma0        : 1;
-  unsigned int ma1        : 1;
-  unsigned int individual : 1;
-  unsigned int broadcast  : 1;
-  unsigned int undersize  : 1;
-  unsigned int oversize   : 1;
-  unsigned int bad_crc    : 1;
-  unsigned int duplex     : 1;
-  unsigned int max_size   : 16;
-  unsigned int dummy1     : 8;
-} reg_eth_rw_rec_ctrl;
-#define REG_RD_ADDR_eth_rw_rec_ctrl 28
-#define REG_WR_ADDR_eth_rw_rec_ctrl 28
-
-/* Register rw_tr_ctrl, scope eth, type rw */
-typedef struct {
-  unsigned int crc         : 1;
-  unsigned int pad         : 1;
-  unsigned int retry       : 1;
-  unsigned int ignore_col  : 1;
-  unsigned int cancel      : 1;
-  unsigned int hsh_delay   : 1;
-  unsigned int ignore_crs  : 1;
-  unsigned int carrier_ext : 1;
-  unsigned int dummy1      : 24;
-} reg_eth_rw_tr_ctrl;
-#define REG_RD_ADDR_eth_rw_tr_ctrl 32
-#define REG_WR_ADDR_eth_rw_tr_ctrl 32
-
-/* Register rw_clr_err, scope eth, type rw */
-typedef struct {
-  unsigned int clr : 1;
-  unsigned int dummy1 : 31;
-} reg_eth_rw_clr_err;
-#define REG_RD_ADDR_eth_rw_clr_err 36
-#define REG_WR_ADDR_eth_rw_clr_err 36
-
-/* Register rw_mgm_ctrl, scope eth, type rw */
-typedef struct {
-  unsigned int mdio : 1;
-  unsigned int mdoe : 1;
-  unsigned int mdc  : 1;
-  unsigned int dummy1 : 29;
-} reg_eth_rw_mgm_ctrl;
-#define REG_RD_ADDR_eth_rw_mgm_ctrl 40
-#define REG_WR_ADDR_eth_rw_mgm_ctrl 40
-
-/* Register r_stat, scope eth, type r */
-typedef struct {
-  unsigned int mdio    : 1;
-  unsigned int exc_col : 1;
-  unsigned int urun    : 1;
-  unsigned int clk_125 : 1;
-  unsigned int dummy1  : 28;
-} reg_eth_r_stat;
-#define REG_RD_ADDR_eth_r_stat 44
-
-/* Register rs_rec_cnt, scope eth, type rs */
-typedef struct {
-  unsigned int crc_err    : 8;
-  unsigned int align_err  : 8;
-  unsigned int oversize   : 8;
-  unsigned int congestion : 8;
-} reg_eth_rs_rec_cnt;
-#define REG_RD_ADDR_eth_rs_rec_cnt 48
-
-/* Register r_rec_cnt, scope eth, type r */
-typedef struct {
-  unsigned int crc_err    : 8;
-  unsigned int align_err  : 8;
-  unsigned int oversize   : 8;
-  unsigned int congestion : 8;
-} reg_eth_r_rec_cnt;
-#define REG_RD_ADDR_eth_r_rec_cnt 52
-
-/* Register rs_tr_cnt, scope eth, type rs */
-typedef struct {
-  unsigned int single_col : 8;
-  unsigned int mult_col   : 8;
-  unsigned int late_col   : 8;
-  unsigned int deferred   : 8;
-} reg_eth_rs_tr_cnt;
-#define REG_RD_ADDR_eth_rs_tr_cnt 56
-
-/* Register r_tr_cnt, scope eth, type r */
-typedef struct {
-  unsigned int single_col : 8;
-  unsigned int mult_col   : 8;
-  unsigned int late_col   : 8;
-  unsigned int deferred   : 8;
-} reg_eth_r_tr_cnt;
-#define REG_RD_ADDR_eth_r_tr_cnt 60
-
-/* Register rs_phy_cnt, scope eth, type rs */
-typedef struct {
-  unsigned int carrier_loss : 8;
-  unsigned int sqe_err      : 8;
-  unsigned int dummy1       : 16;
-} reg_eth_rs_phy_cnt;
-#define REG_RD_ADDR_eth_rs_phy_cnt 64
-
-/* Register r_phy_cnt, scope eth, type r */
-typedef struct {
-  unsigned int carrier_loss : 8;
-  unsigned int sqe_err      : 8;
-  unsigned int dummy1       : 16;
-} reg_eth_r_phy_cnt;
-#define REG_RD_ADDR_eth_r_phy_cnt 68
-
-/* Register rw_test_ctrl, scope eth, type rw */
-typedef struct {
-  unsigned int snmp_inc : 1;
-  unsigned int snmp     : 1;
-  unsigned int backoff  : 1;
-  unsigned int dummy1   : 29;
-} reg_eth_rw_test_ctrl;
-#define REG_RD_ADDR_eth_rw_test_ctrl 72
-#define REG_WR_ADDR_eth_rw_test_ctrl 72
-
-/* Register rw_intr_mask, scope eth, type rw */
-typedef struct {
-  unsigned int crc          : 1;
-  unsigned int align        : 1;
-  unsigned int oversize     : 1;
-  unsigned int congestion   : 1;
-  unsigned int single_col   : 1;
-  unsigned int mult_col     : 1;
-  unsigned int late_col     : 1;
-  unsigned int deferred     : 1;
-  unsigned int carrier_loss : 1;
-  unsigned int sqe_test_err : 1;
-  unsigned int orun         : 1;
-  unsigned int urun         : 1;
-  unsigned int exc_col      : 1;
-  unsigned int mdio         : 1;
-  unsigned int dummy1       : 18;
-} reg_eth_rw_intr_mask;
-#define REG_RD_ADDR_eth_rw_intr_mask 76
-#define REG_WR_ADDR_eth_rw_intr_mask 76
-
-/* Register rw_ack_intr, scope eth, type rw */
-typedef struct {
-  unsigned int crc          : 1;
-  unsigned int align        : 1;
-  unsigned int oversize     : 1;
-  unsigned int congestion   : 1;
-  unsigned int single_col   : 1;
-  unsigned int mult_col     : 1;
-  unsigned int late_col     : 1;
-  unsigned int deferred     : 1;
-  unsigned int carrier_loss : 1;
-  unsigned int sqe_test_err : 1;
-  unsigned int orun         : 1;
-  unsigned int urun         : 1;
-  unsigned int exc_col      : 1;
-  unsigned int mdio         : 1;
-  unsigned int dummy1       : 18;
-} reg_eth_rw_ack_intr;
-#define REG_RD_ADDR_eth_rw_ack_intr 80
-#define REG_WR_ADDR_eth_rw_ack_intr 80
-
-/* Register r_intr, scope eth, type r */
-typedef struct {
-  unsigned int crc          : 1;
-  unsigned int align        : 1;
-  unsigned int oversize     : 1;
-  unsigned int congestion   : 1;
-  unsigned int single_col   : 1;
-  unsigned int mult_col     : 1;
-  unsigned int late_col     : 1;
-  unsigned int deferred     : 1;
-  unsigned int carrier_loss : 1;
-  unsigned int sqe_test_err : 1;
-  unsigned int orun         : 1;
-  unsigned int urun         : 1;
-  unsigned int exc_col      : 1;
-  unsigned int mdio         : 1;
-  unsigned int dummy1       : 18;
-} reg_eth_r_intr;
-#define REG_RD_ADDR_eth_r_intr 84
-
-/* Register r_masked_intr, scope eth, type r */
-typedef struct {
-  unsigned int crc          : 1;
-  unsigned int align        : 1;
-  unsigned int oversize     : 1;
-  unsigned int congestion   : 1;
-  unsigned int single_col   : 1;
-  unsigned int mult_col     : 1;
-  unsigned int late_col     : 1;
-  unsigned int deferred     : 1;
-  unsigned int carrier_loss : 1;
-  unsigned int sqe_test_err : 1;
-  unsigned int orun         : 1;
-  unsigned int urun         : 1;
-  unsigned int exc_col      : 1;
-  unsigned int mdio         : 1;
-  unsigned int dummy1       : 18;
-} reg_eth_r_masked_intr;
-#define REG_RD_ADDR_eth_r_masked_intr 88
-
-
-/* Constants */
-enum {
-  regk_eth_discard                         = 0x00000000,
-  regk_eth_ether                           = 0x00000000,
-  regk_eth_full                            = 0x00000001,
-  regk_eth_gmii                            = 0x00000003,
-  regk_eth_gtxclk                          = 0x00000001,
-  regk_eth_half                            = 0x00000000,
-  regk_eth_hsh                             = 0x00000001,
-  regk_eth_mii                             = 0x00000001,
-  regk_eth_mii_arec                        = 0x00000002,
-  regk_eth_mii_clk                         = 0x00000000,
-  regk_eth_no                              = 0x00000000,
-  regk_eth_phyrst                          = 0x00000000,
-  regk_eth_rec                             = 0x00000001,
-  regk_eth_rw_ga_hi_default                = 0x00000000,
-  regk_eth_rw_ga_lo_default                = 0x00000000,
-  regk_eth_rw_gen_ctrl_default             = 0x00000000,
-  regk_eth_rw_intr_mask_default            = 0x00000000,
-  regk_eth_rw_ma0_hi_default               = 0x00000000,
-  regk_eth_rw_ma0_lo_default               = 0x00000000,
-  regk_eth_rw_ma1_hi_default               = 0x00000000,
-  regk_eth_rw_ma1_lo_default               = 0x00000000,
-  regk_eth_rw_mgm_ctrl_default             = 0x00000000,
-  regk_eth_rw_test_ctrl_default            = 0x00000000,
-  regk_eth_size1518                        = 0x000005ee,
-  regk_eth_size1522                        = 0x000005f2,
-  regk_eth_yes                             = 0x00000001
-};
-#endif /* __eth_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/extmem_defs.h b/include/asm-cris/arch-v32/hwregs/extmem_defs.h
deleted file mode 100644
index c47b5ca48ece..000000000000
--- a/include/asm-cris/arch-v32/hwregs/extmem_defs.h
+++ /dev/null
@@ -1,369 +0,0 @@
-#ifndef __extmem_defs_h
-#define __extmem_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/ext_mem/mod/extmem_regs.r
- *     id:           extmem_regs.r,v 1.1 2004/02/16 13:29:30 np Exp
- *     last modfied: Tue Mar 30 22:26:21 2004
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r
- *      id: $Id: extmem_defs.h,v 1.5 2004/06/04 07:15:33 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope extmem */
-
-/* Register rw_cse0_cfg, scope extmem, type rw */
-typedef struct {
-  unsigned int lw     : 6;
-  unsigned int ew     : 3;
-  unsigned int zw     : 3;
-  unsigned int aw     : 2;
-  unsigned int dw     : 2;
-  unsigned int ewb    : 2;
-  unsigned int bw     : 1;
-  unsigned int mode   : 1;
-  unsigned int erc_en : 1;
-  unsigned int dummy1 : 6;
-  unsigned int size   : 3;
-  unsigned int log    : 1;
-  unsigned int en     : 1;
-} reg_extmem_rw_cse0_cfg;
-#define REG_RD_ADDR_extmem_rw_cse0_cfg 0
-#define REG_WR_ADDR_extmem_rw_cse0_cfg 0
-
-/* Register rw_cse1_cfg, scope extmem, type rw */
-typedef struct {
-  unsigned int lw     : 6;
-  unsigned int ew     : 3;
-  unsigned int zw     : 3;
-  unsigned int aw     : 2;
-  unsigned int dw     : 2;
-  unsigned int ewb    : 2;
-  unsigned int bw     : 1;
-  unsigned int mode   : 1;
-  unsigned int erc_en : 1;
-  unsigned int dummy1 : 6;
-  unsigned int size   : 3;
-  unsigned int log    : 1;
-  unsigned int en     : 1;
-} reg_extmem_rw_cse1_cfg;
-#define REG_RD_ADDR_extmem_rw_cse1_cfg 4
-#define REG_WR_ADDR_extmem_rw_cse1_cfg 4
-
-/* Register rw_csr0_cfg, scope extmem, type rw */
-typedef struct {
-  unsigned int lw     : 6;
-  unsigned int ew     : 3;
-  unsigned int zw     : 3;
-  unsigned int aw     : 2;
-  unsigned int dw     : 2;
-  unsigned int ewb    : 2;
-  unsigned int bw     : 1;
-  unsigned int mode   : 1;
-  unsigned int erc_en : 1;
-  unsigned int dummy1 : 6;
-  unsigned int size   : 3;
-  unsigned int log    : 1;
-  unsigned int en     : 1;
-} reg_extmem_rw_csr0_cfg;
-#define REG_RD_ADDR_extmem_rw_csr0_cfg 8
-#define REG_WR_ADDR_extmem_rw_csr0_cfg 8
-
-/* Register rw_csr1_cfg, scope extmem, type rw */
-typedef struct {
-  unsigned int lw     : 6;
-  unsigned int ew     : 3;
-  unsigned int zw     : 3;
-  unsigned int aw     : 2;
-  unsigned int dw     : 2;
-  unsigned int ewb    : 2;
-  unsigned int bw     : 1;
-  unsigned int mode   : 1;
-  unsigned int erc_en : 1;
-  unsigned int dummy1 : 6;
-  unsigned int size   : 3;
-  unsigned int log    : 1;
-  unsigned int en     : 1;
-} reg_extmem_rw_csr1_cfg;
-#define REG_RD_ADDR_extmem_rw_csr1_cfg 12
-#define REG_WR_ADDR_extmem_rw_csr1_cfg 12
-
-/* Register rw_csp0_cfg, scope extmem, type rw */
-typedef struct {
-  unsigned int lw     : 6;
-  unsigned int ew     : 3;
-  unsigned int zw     : 3;
-  unsigned int aw     : 2;
-  unsigned int dw     : 2;
-  unsigned int ewb    : 2;
-  unsigned int bw     : 1;
-  unsigned int mode   : 1;
-  unsigned int erc_en : 1;
-  unsigned int dummy1 : 6;
-  unsigned int size   : 3;
-  unsigned int log    : 1;
-  unsigned int en     : 1;
-} reg_extmem_rw_csp0_cfg;
-#define REG_RD_ADDR_extmem_rw_csp0_cfg 16
-#define REG_WR_ADDR_extmem_rw_csp0_cfg 16
-
-/* Register rw_csp1_cfg, scope extmem, type rw */
-typedef struct {
-  unsigned int lw     : 6;
-  unsigned int ew     : 3;
-  unsigned int zw     : 3;
-  unsigned int aw     : 2;
-  unsigned int dw     : 2;
-  unsigned int ewb    : 2;
-  unsigned int bw     : 1;
-  unsigned int mode   : 1;
-  unsigned int erc_en : 1;
-  unsigned int dummy1 : 6;
-  unsigned int size   : 3;
-  unsigned int log    : 1;
-  unsigned int en     : 1;
-} reg_extmem_rw_csp1_cfg;
-#define REG_RD_ADDR_extmem_rw_csp1_cfg 20
-#define REG_WR_ADDR_extmem_rw_csp1_cfg 20
-
-/* Register rw_csp2_cfg, scope extmem, type rw */
-typedef struct {
-  unsigned int lw     : 6;
-  unsigned int ew     : 3;
-  unsigned int zw     : 3;
-  unsigned int aw     : 2;
-  unsigned int dw     : 2;
-  unsigned int ewb    : 2;
-  unsigned int bw     : 1;
-  unsigned int mode   : 1;
-  unsigned int erc_en : 1;
-  unsigned int dummy1 : 6;
-  unsigned int size   : 3;
-  unsigned int log    : 1;
-  unsigned int en     : 1;
-} reg_extmem_rw_csp2_cfg;
-#define REG_RD_ADDR_extmem_rw_csp2_cfg 24
-#define REG_WR_ADDR_extmem_rw_csp2_cfg 24
-
-/* Register rw_csp3_cfg, scope extmem, type rw */
-typedef struct {
-  unsigned int lw     : 6;
-  unsigned int ew     : 3;
-  unsigned int zw     : 3;
-  unsigned int aw     : 2;
-  unsigned int dw     : 2;
-  unsigned int ewb    : 2;
-  unsigned int bw     : 1;
-  unsigned int mode   : 1;
-  unsigned int erc_en : 1;
-  unsigned int dummy1 : 6;
-  unsigned int size   : 3;
-  unsigned int log    : 1;
-  unsigned int en     : 1;
-} reg_extmem_rw_csp3_cfg;
-#define REG_RD_ADDR_extmem_rw_csp3_cfg 28
-#define REG_WR_ADDR_extmem_rw_csp3_cfg 28
-
-/* Register rw_csp4_cfg, scope extmem, type rw */
-typedef struct {
-  unsigned int lw     : 6;
-  unsigned int ew     : 3;
-  unsigned int zw     : 3;
-  unsigned int aw     : 2;
-  unsigned int dw     : 2;
-  unsigned int ewb    : 2;
-  unsigned int bw     : 1;
-  unsigned int mode   : 1;
-  unsigned int erc_en : 1;
-  unsigned int dummy1 : 6;
-  unsigned int size   : 3;
-  unsigned int log    : 1;
-  unsigned int en     : 1;
-} reg_extmem_rw_csp4_cfg;
-#define REG_RD_ADDR_extmem_rw_csp4_cfg 32
-#define REG_WR_ADDR_extmem_rw_csp4_cfg 32
-
-/* Register rw_csp5_cfg, scope extmem, type rw */
-typedef struct {
-  unsigned int lw     : 6;
-  unsigned int ew     : 3;
-  unsigned int zw     : 3;
-  unsigned int aw     : 2;
-  unsigned int dw     : 2;
-  unsigned int ewb    : 2;
-  unsigned int bw     : 1;
-  unsigned int mode   : 1;
-  unsigned int erc_en : 1;
-  unsigned int dummy1 : 6;
-  unsigned int size   : 3;
-  unsigned int log    : 1;
-  unsigned int en     : 1;
-} reg_extmem_rw_csp5_cfg;
-#define REG_RD_ADDR_extmem_rw_csp5_cfg 36
-#define REG_WR_ADDR_extmem_rw_csp5_cfg 36
-
-/* Register rw_csp6_cfg, scope extmem, type rw */
-typedef struct {
-  unsigned int lw     : 6;
-  unsigned int ew     : 3;
-  unsigned int zw     : 3;
-  unsigned int aw     : 2;
-  unsigned int dw     : 2;
-  unsigned int ewb    : 2;
-  unsigned int bw     : 1;
-  unsigned int mode   : 1;
-  unsigned int erc_en : 1;
-  unsigned int dummy1 : 6;
-  unsigned int size   : 3;
-  unsigned int log    : 1;
-  unsigned int en     : 1;
-} reg_extmem_rw_csp6_cfg;
-#define REG_RD_ADDR_extmem_rw_csp6_cfg 40
-#define REG_WR_ADDR_extmem_rw_csp6_cfg 40
-
-/* Register rw_css_cfg, scope extmem, type rw */
-typedef struct {
-  unsigned int lw     : 6;
-  unsigned int ew     : 3;
-  unsigned int zw     : 3;
-  unsigned int aw     : 2;
-  unsigned int dw     : 2;
-  unsigned int ewb    : 2;
-  unsigned int bw     : 1;
-  unsigned int mode   : 1;
-  unsigned int erc_en : 1;
-  unsigned int dummy1 : 6;
-  unsigned int size   : 3;
-  unsigned int log    : 1;
-  unsigned int en     : 1;
-} reg_extmem_rw_css_cfg;
-#define REG_RD_ADDR_extmem_rw_css_cfg 44
-#define REG_WR_ADDR_extmem_rw_css_cfg 44
-
-/* Register rw_status_handle, scope extmem, type rw */
-typedef struct {
-  unsigned int h : 32;
-} reg_extmem_rw_status_handle;
-#define REG_RD_ADDR_extmem_rw_status_handle 48
-#define REG_WR_ADDR_extmem_rw_status_handle 48
-
-/* Register rw_wait_pin, scope extmem, type rw */
-typedef struct {
-  unsigned int val   : 16;
-  unsigned int dummy1 : 15;
-  unsigned int start : 1;
-} reg_extmem_rw_wait_pin;
-#define REG_RD_ADDR_extmem_rw_wait_pin 52
-#define REG_WR_ADDR_extmem_rw_wait_pin 52
-
-/* Register rw_gated_csp, scope extmem, type rw */
-typedef struct {
-  unsigned int dummy1 : 31;
-  unsigned int en : 1;
-} reg_extmem_rw_gated_csp;
-#define REG_RD_ADDR_extmem_rw_gated_csp 56
-#define REG_WR_ADDR_extmem_rw_gated_csp 56
-
-
-/* Constants */
-enum {
-  regk_extmem_b16                          = 0x00000001,
-  regk_extmem_b32                          = 0x00000000,
-  regk_extmem_bwe                          = 0x00000000,
-  regk_extmem_cwe                          = 0x00000001,
-  regk_extmem_no                           = 0x00000000,
-  regk_extmem_rw_cse0_cfg_default          = 0x000006cf,
-  regk_extmem_rw_cse1_cfg_default          = 0x000006cf,
-  regk_extmem_rw_csp0_cfg_default          = 0x000006cf,
-  regk_extmem_rw_csp1_cfg_default          = 0x000006cf,
-  regk_extmem_rw_csp2_cfg_default          = 0x000006cf,
-  regk_extmem_rw_csp3_cfg_default          = 0x000006cf,
-  regk_extmem_rw_csp4_cfg_default          = 0x000006cf,
-  regk_extmem_rw_csp5_cfg_default          = 0x000006cf,
-  regk_extmem_rw_csp6_cfg_default          = 0x000006cf,
-  regk_extmem_rw_csr0_cfg_default          = 0x000006cf,
-  regk_extmem_rw_csr1_cfg_default          = 0x000006cf,
-  regk_extmem_rw_css_cfg_default           = 0x000006cf,
-  regk_extmem_s128KB                       = 0x00000000,
-  regk_extmem_s16MB                        = 0x00000005,
-  regk_extmem_s1MB                         = 0x00000001,
-  regk_extmem_s2MB                         = 0x00000002,
-  regk_extmem_s32MB                        = 0x00000006,
-  regk_extmem_s4MB                         = 0x00000003,
-  regk_extmem_s64MB                        = 0x00000007,
-  regk_extmem_s8MB                         = 0x00000004,
-  regk_extmem_yes                          = 0x00000001
-};
-#endif /* __extmem_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/gio_defs.h b/include/asm-cris/arch-v32/hwregs/gio_defs.h
deleted file mode 100644
index 3e9a0b25366f..000000000000
--- a/include/asm-cris/arch-v32/hwregs/gio_defs.h
+++ /dev/null
@@ -1,295 +0,0 @@
-#ifndef __gio_defs_h
-#define __gio_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/gio/rtl/gio_regs.r
- *     id:           gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
- *     last modfied: Mon Apr 11 16:07:47 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r
- *      id: $Id: gio_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope gio */
-
-/* Register rw_pa_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pa_dout;
-#define REG_RD_ADDR_gio_rw_pa_dout 0
-#define REG_WR_ADDR_gio_rw_pa_dout 0
-
-/* Register r_pa_din, scope gio, type r */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_r_pa_din;
-#define REG_RD_ADDR_gio_r_pa_din 4
-
-/* Register rw_pa_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pa_oe;
-#define REG_RD_ADDR_gio_rw_pa_oe 8
-#define REG_WR_ADDR_gio_rw_pa_oe 8
-
-/* Register rw_intr_cfg, scope gio, type rw */
-typedef struct {
-  unsigned int pa0 : 3;
-  unsigned int pa1 : 3;
-  unsigned int pa2 : 3;
-  unsigned int pa3 : 3;
-  unsigned int pa4 : 3;
-  unsigned int pa5 : 3;
-  unsigned int pa6 : 3;
-  unsigned int pa7 : 3;
-  unsigned int dummy1 : 8;
-} reg_gio_rw_intr_cfg;
-#define REG_RD_ADDR_gio_rw_intr_cfg 12
-#define REG_WR_ADDR_gio_rw_intr_cfg 12
-
-/* Register rw_intr_mask, scope gio, type rw */
-typedef struct {
-  unsigned int pa0 : 1;
-  unsigned int pa1 : 1;
-  unsigned int pa2 : 1;
-  unsigned int pa3 : 1;
-  unsigned int pa4 : 1;
-  unsigned int pa5 : 1;
-  unsigned int pa6 : 1;
-  unsigned int pa7 : 1;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_intr_mask;
-#define REG_RD_ADDR_gio_rw_intr_mask 16
-#define REG_WR_ADDR_gio_rw_intr_mask 16
-
-/* Register rw_ack_intr, scope gio, type rw */
-typedef struct {
-  unsigned int pa0 : 1;
-  unsigned int pa1 : 1;
-  unsigned int pa2 : 1;
-  unsigned int pa3 : 1;
-  unsigned int pa4 : 1;
-  unsigned int pa5 : 1;
-  unsigned int pa6 : 1;
-  unsigned int pa7 : 1;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_ack_intr;
-#define REG_RD_ADDR_gio_rw_ack_intr 20
-#define REG_WR_ADDR_gio_rw_ack_intr 20
-
-/* Register r_intr, scope gio, type r */
-typedef struct {
-  unsigned int pa0 : 1;
-  unsigned int pa1 : 1;
-  unsigned int pa2 : 1;
-  unsigned int pa3 : 1;
-  unsigned int pa4 : 1;
-  unsigned int pa5 : 1;
-  unsigned int pa6 : 1;
-  unsigned int pa7 : 1;
-  unsigned int dummy1 : 24;
-} reg_gio_r_intr;
-#define REG_RD_ADDR_gio_r_intr 24
-
-/* Register r_masked_intr, scope gio, type r */
-typedef struct {
-  unsigned int pa0 : 1;
-  unsigned int pa1 : 1;
-  unsigned int pa2 : 1;
-  unsigned int pa3 : 1;
-  unsigned int pa4 : 1;
-  unsigned int pa5 : 1;
-  unsigned int pa6 : 1;
-  unsigned int pa7 : 1;
-  unsigned int dummy1 : 24;
-} reg_gio_r_masked_intr;
-#define REG_RD_ADDR_gio_r_masked_intr 28
-
-/* Register rw_pb_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_rw_pb_dout;
-#define REG_RD_ADDR_gio_rw_pb_dout 32
-#define REG_WR_ADDR_gio_rw_pb_dout 32
-
-/* Register r_pb_din, scope gio, type r */
-typedef struct {
-  unsigned int data : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_r_pb_din;
-#define REG_RD_ADDR_gio_r_pb_din 36
-
-/* Register rw_pb_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_rw_pb_oe;
-#define REG_RD_ADDR_gio_rw_pb_oe 40
-#define REG_WR_ADDR_gio_rw_pb_oe 40
-
-/* Register rw_pc_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_rw_pc_dout;
-#define REG_RD_ADDR_gio_rw_pc_dout 48
-#define REG_WR_ADDR_gio_rw_pc_dout 48
-
-/* Register r_pc_din, scope gio, type r */
-typedef struct {
-  unsigned int data : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_r_pc_din;
-#define REG_RD_ADDR_gio_r_pc_din 52
-
-/* Register rw_pc_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_rw_pc_oe;
-#define REG_RD_ADDR_gio_rw_pc_oe 56
-#define REG_WR_ADDR_gio_rw_pc_oe 56
-
-/* Register rw_pd_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_rw_pd_dout;
-#define REG_RD_ADDR_gio_rw_pd_dout 64
-#define REG_WR_ADDR_gio_rw_pd_dout 64
-
-/* Register r_pd_din, scope gio, type r */
-typedef struct {
-  unsigned int data : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_r_pd_din;
-#define REG_RD_ADDR_gio_r_pd_din 68
-
-/* Register rw_pd_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_rw_pd_oe;
-#define REG_RD_ADDR_gio_rw_pd_oe 72
-#define REG_WR_ADDR_gio_rw_pd_oe 72
-
-/* Register rw_pe_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_rw_pe_dout;
-#define REG_RD_ADDR_gio_rw_pe_dout 80
-#define REG_WR_ADDR_gio_rw_pe_dout 80
-
-/* Register r_pe_din, scope gio, type r */
-typedef struct {
-  unsigned int data : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_r_pe_din;
-#define REG_RD_ADDR_gio_r_pe_din 84
-
-/* Register rw_pe_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_rw_pe_oe;
-#define REG_RD_ADDR_gio_rw_pe_oe 88
-#define REG_WR_ADDR_gio_rw_pe_oe 88
-
-
-/* Constants */
-enum {
-  regk_gio_anyedge                         = 0x00000007,
-  regk_gio_hi                              = 0x00000001,
-  regk_gio_lo                              = 0x00000002,
-  regk_gio_negedge                         = 0x00000006,
-  regk_gio_no                              = 0x00000000,
-  regk_gio_off                             = 0x00000000,
-  regk_gio_posedge                         = 0x00000005,
-  regk_gio_rw_intr_cfg_default             = 0x00000000,
-  regk_gio_rw_intr_mask_default            = 0x00000000,
-  regk_gio_rw_pa_oe_default                = 0x00000000,
-  regk_gio_rw_pb_oe_default                = 0x00000000,
-  regk_gio_rw_pc_oe_default                = 0x00000000,
-  regk_gio_rw_pd_oe_default                = 0x00000000,
-  regk_gio_rw_pe_oe_default                = 0x00000000,
-  regk_gio_set                             = 0x00000003,
-  regk_gio_yes                             = 0x00000001
-};
-#endif /* __gio_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/intr_vect.h b/include/asm-cris/arch-v32/hwregs/intr_vect.h
deleted file mode 100644
index 5c1b28fb205d..000000000000
--- a/include/asm-cris/arch-v32/hwregs/intr_vect.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
- from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
-version . */
-
-#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
-#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
-#define MEMARB_INTR_VECT	0x31
-#define GEN_IO_INTR_VECT	0x32
-#define IOP0_INTR_VECT	0x33
-#define IOP1_INTR_VECT	0x34
-#define IOP2_INTR_VECT	0x35
-#define IOP3_INTR_VECT	0x36
-#define DMA0_INTR_VECT	0x37
-#define DMA1_INTR_VECT	0x38
-#define DMA2_INTR_VECT	0x39
-#define DMA3_INTR_VECT	0x3a
-#define DMA4_INTR_VECT	0x3b
-#define DMA5_INTR_VECT	0x3c
-#define DMA6_INTR_VECT	0x3d
-#define DMA7_INTR_VECT	0x3e
-#define DMA8_INTR_VECT	0x3f
-#define DMA9_INTR_VECT	0x40
-#define ATA_INTR_VECT	0x41
-#define SSER0_INTR_VECT	0x42
-#define SSER1_INTR_VECT	0x43
-#define SER0_INTR_VECT	0x44
-#define SER1_INTR_VECT	0x45
-#define SER2_INTR_VECT	0x46
-#define SER3_INTR_VECT	0x47
-#define P21_INTR_VECT	0x48
-#define ETH0_INTR_VECT	0x49
-#define ETH1_INTR_VECT	0x4a
-#define TIMER_INTR_VECT	0x4b
-#define BIF_ARB_INTR_VECT	0x4c
-#define BIF_DMA_INTR_VECT	0x4d
-#define EXT_INTR_VECT	0x4e
-#define IPI_INTR_VECT	0x4f
-
-#endif
diff --git a/include/asm-cris/arch-v32/hwregs/iop/Makefile b/include/asm-cris/arch-v32/hwregs/iop/Makefile
deleted file mode 100644
index a90056a095e3..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/Makefile
+++ /dev/null
@@ -1,146 +0,0 @@
-# $Id: Makefile,v 1.3 2004/01/07 20:34:55 johana Exp $
-# Makefile to generate or copy the latest register definitions
-# and related datastructures and helpermacros.
-# The offical place for these files is probably at:
-RELEASE ?= r1_alfa5
-IOPOFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/
-
-IOPROCDIR = /n/asic/design/io/io_proc/rtl
-
-IOPROCINCL_FILES =
-IOPROCINCL_FILES2=
-IOPROCINCL_FILES += iop_crc_par_defs.h
-IOPROCINCL_FILES += iop_dmc_in_defs.h
-IOPROCINCL_FILES += iop_dmc_out_defs.h
-IOPROCINCL_FILES += iop_fifo_in_defs.h
-IOPROCINCL_FILES += iop_fifo_in_xtra_defs.h
-IOPROCINCL_FILES += iop_fifo_out_defs.h
-IOPROCINCL_FILES += iop_fifo_out_xtra_defs.h
-IOPROCINCL_FILES += iop_mpu_defs.h
-IOPROCINCL_FILES2+= iop_mpu_macros.h
-IOPROCINCL_FILES2+= iop_reg_space.h
-IOPROCINCL_FILES += iop_sap_in_defs.h
-IOPROCINCL_FILES += iop_sap_out_defs.h
-IOPROCINCL_FILES += iop_scrc_in_defs.h
-IOPROCINCL_FILES += iop_scrc_out_defs.h
-IOPROCINCL_FILES += iop_spu_defs.h
-# in guiness/
-IOPROCINCL_FILES += iop_sw_cfg_defs.h
-IOPROCINCL_FILES += iop_sw_cpu_defs.h
-IOPROCINCL_FILES += iop_sw_mpu_defs.h
-IOPROCINCL_FILES += iop_sw_spu_defs.h
-#
-IOPROCINCL_FILES += iop_timer_grp_defs.h
-IOPROCINCL_FILES += iop_trigger_grp_defs.h
-# in guiness/
-IOPROCINCL_FILES += iop_version_defs.h
-
-IOPROCASMINCL_FILES = $(patsubst %_defs.h,%_defs_asm.h,$(IOPROCINCL_FILES))
-IOPROCASMINCL_FILES+= iop_reg_space_asm.h
-
-
-IOPROCREGDESC =
-IOPROCREGDESC += $(IOPROCDIR)/iop_crc_par.r
-#IOPROCREGDESC += $(IOPROCDIR)/iop_crc_ser.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_in.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_out.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in_xtra.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out_xtra.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_mpu.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_sap_in.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_sap_out.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_in.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_out.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_spu.r
-IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cfg.r
-IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cpu.r
-IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_mpu.r
-IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_spu.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_timer_grp.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_trigger_grp.r
-IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_version.r
-
-
-RDES2C = /n/asic/bin/rdes2c
-RDES2C = /n/asic/design/tools/rdesc/rdes2c
-RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr
-RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt
-
-## all    - Just print help - you probably want to do 'make gen'
-all: help
-
-## help   - This help
-help:
-	@grep '^## ' Makefile
-
-## gen    - Generate include files
-gen: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES)
-	echo "INCL: $(IOPROCINCL_FILES)"
-	echo "INCL2: $(IOPROCINCL_FILES2)"
-	echo "ASMINCL: $(IOPROCASMINCL_FILES)"
-
-# From the official location...
-iop_reg_space.h: $(IOPOFFICIAL_INCDIR)/iop_reg_space.h
-	cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-iop_mpu_macros.h: $(IOPOFFICIAL_INCDIR)/iop_mpu_macros.h
-	cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-
-## copy   - Copy files from official location
-copy:
-	@echo "## Copying and fixing iop files ##"
-	@for HFILE in $(IOPROCINCL_FILES); do \
-		echo "  $$HFILE"; \
-		cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
-	done
-	@for HFILE in $(IOPROCINCL_FILES2); do \
-		echo "  $$HFILE"; \
-		cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
-	done
-	@echo "## Copying and fixing iop asm files ##"
-	@for HFILE in $(IOPROCASMINCL_FILES); do \
-		echo "  $$HFILE"; \
-		cat $(IOPOFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > asm/$$HFILE; \
-	done
-
-# I/O processor files:
-## iop    - Generate I/O processor include files
-iop: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES)
-iop_sw_%_defs.h: $(IOPROCDIR)/guinness/iop_sw_%.r
-	$(RDES2C) $<
-iop_version_defs.h: $(IOPROCDIR)/guinness/iop_version.r
-	$(RDES2C) $<
-%_defs.h: $(IOPROCDIR)/%.r
-	$(RDES2C) $<
-%_defs_asm.h: $(IOPROCDIR)/%.r
-	$(RDES2C) -asm $<
-iop_version_defs_asm.h: $(IOPROCDIR)/guinness/iop_version.r
-	$(RDES2C) -asm $<
-
-## doc    - Generate .axw files from register description.
-doc: $(IOPROCREGDESC)
-	for RDES in $^; do \
-		$(RDES2TXT) $$RDES; \
-	done
-
-.PHONY: axw
-## %.axw  - Generate the specified .axw file (doesn't work for all files
-##          due to inconsistent naming of .r files.
-%.axw: axw
-	@for RDES in $(IOPROCREGDESC); do \
-		if echo "$$RDES" | grep $* ; then \
-		  $(RDES2TXT) $$RDES; \
-		fi \
-	done
-
-.PHONY: clean
-## clean  - Remove .h files and .axw files.
-clean:
-	rm -rf $(IOPROCINCL_FILES) *.axw
-
-.PHONY: cleandoc
-## cleandoc  - Remove .axw files.
-cleandoc:
-	rm -rf *.axw
-
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h
deleted file mode 100644
index a4b58000c164..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h
+++ /dev/null
@@ -1,171 +0,0 @@
-#ifndef __iop_crc_par_defs_asm_h
-#define __iop_crc_par_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_crc_par.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:08:45 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r
- *      id: $Id: iop_crc_par_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_cfg___mode___lsb 0
-#define reg_iop_crc_par_rw_cfg___mode___width 1
-#define reg_iop_crc_par_rw_cfg___mode___bit 0
-#define reg_iop_crc_par_rw_cfg___crc_out___lsb 1
-#define reg_iop_crc_par_rw_cfg___crc_out___width 1
-#define reg_iop_crc_par_rw_cfg___crc_out___bit 1
-#define reg_iop_crc_par_rw_cfg___rev_out___lsb 2
-#define reg_iop_crc_par_rw_cfg___rev_out___width 1
-#define reg_iop_crc_par_rw_cfg___rev_out___bit 2
-#define reg_iop_crc_par_rw_cfg___inv_out___lsb 3
-#define reg_iop_crc_par_rw_cfg___inv_out___width 1
-#define reg_iop_crc_par_rw_cfg___inv_out___bit 3
-#define reg_iop_crc_par_rw_cfg___trig___lsb 4
-#define reg_iop_crc_par_rw_cfg___trig___width 2
-#define reg_iop_crc_par_rw_cfg___poly___lsb 6
-#define reg_iop_crc_par_rw_cfg___poly___width 3
-#define reg_iop_crc_par_rw_cfg_offset 0
-
-/* Register rw_init_crc, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_init_crc_offset 4
-
-/* Register rw_correct_crc, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_correct_crc_offset 8
-
-/* Register rw_ctrl, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_ctrl___en___lsb 0
-#define reg_iop_crc_par_rw_ctrl___en___width 1
-#define reg_iop_crc_par_rw_ctrl___en___bit 0
-#define reg_iop_crc_par_rw_ctrl_offset 12
-
-/* Register rw_set_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_set_last___tr_dif___lsb 0
-#define reg_iop_crc_par_rw_set_last___tr_dif___width 1
-#define reg_iop_crc_par_rw_set_last___tr_dif___bit 0
-#define reg_iop_crc_par_rw_set_last_offset 16
-
-/* Register rw_wr1byte, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr1byte___data___lsb 0
-#define reg_iop_crc_par_rw_wr1byte___data___width 8
-#define reg_iop_crc_par_rw_wr1byte_offset 20
-
-/* Register rw_wr2byte, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr2byte___data___lsb 0
-#define reg_iop_crc_par_rw_wr2byte___data___width 16
-#define reg_iop_crc_par_rw_wr2byte_offset 24
-
-/* Register rw_wr3byte, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr3byte___data___lsb 0
-#define reg_iop_crc_par_rw_wr3byte___data___width 24
-#define reg_iop_crc_par_rw_wr3byte_offset 28
-
-/* Register rw_wr4byte, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr4byte___data___lsb 0
-#define reg_iop_crc_par_rw_wr4byte___data___width 32
-#define reg_iop_crc_par_rw_wr4byte_offset 32
-
-/* Register rw_wr1byte_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr1byte_last___data___lsb 0
-#define reg_iop_crc_par_rw_wr1byte_last___data___width 8
-#define reg_iop_crc_par_rw_wr1byte_last_offset 36
-
-/* Register rw_wr2byte_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr2byte_last___data___lsb 0
-#define reg_iop_crc_par_rw_wr2byte_last___data___width 16
-#define reg_iop_crc_par_rw_wr2byte_last_offset 40
-
-/* Register rw_wr3byte_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr3byte_last___data___lsb 0
-#define reg_iop_crc_par_rw_wr3byte_last___data___width 24
-#define reg_iop_crc_par_rw_wr3byte_last_offset 44
-
-/* Register rw_wr4byte_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr4byte_last___data___lsb 0
-#define reg_iop_crc_par_rw_wr4byte_last___data___width 32
-#define reg_iop_crc_par_rw_wr4byte_last_offset 48
-
-/* Register r_stat, scope iop_crc_par, type r */
-#define reg_iop_crc_par_r_stat___err___lsb 0
-#define reg_iop_crc_par_r_stat___err___width 1
-#define reg_iop_crc_par_r_stat___err___bit 0
-#define reg_iop_crc_par_r_stat___busy___lsb 1
-#define reg_iop_crc_par_r_stat___busy___width 1
-#define reg_iop_crc_par_r_stat___busy___bit 1
-#define reg_iop_crc_par_r_stat_offset 52
-
-/* Register r_sh_reg, scope iop_crc_par, type r */
-#define reg_iop_crc_par_r_sh_reg_offset 56
-
-/* Register r_crc, scope iop_crc_par, type r */
-#define reg_iop_crc_par_r_crc_offset 60
-
-/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_strb_rec_dif_in___last___lsb 0
-#define reg_iop_crc_par_rw_strb_rec_dif_in___last___width 2
-#define reg_iop_crc_par_rw_strb_rec_dif_in_offset 64
-
-
-/* Constants */
-#define regk_iop_crc_par_calc                     0x00000001
-#define regk_iop_crc_par_ccitt                    0x00000002
-#define regk_iop_crc_par_check                    0x00000000
-#define regk_iop_crc_par_crc16                    0x00000001
-#define regk_iop_crc_par_crc32                    0x00000000
-#define regk_iop_crc_par_crc5                     0x00000003
-#define regk_iop_crc_par_crc5_11                  0x00000004
-#define regk_iop_crc_par_dif_in                   0x00000002
-#define regk_iop_crc_par_hi                       0x00000000
-#define regk_iop_crc_par_neg                      0x00000002
-#define regk_iop_crc_par_no                       0x00000000
-#define regk_iop_crc_par_pos                      0x00000001
-#define regk_iop_crc_par_pos_neg                  0x00000003
-#define regk_iop_crc_par_rw_cfg_default           0x00000000
-#define regk_iop_crc_par_rw_ctrl_default          0x00000000
-#define regk_iop_crc_par_yes                      0x00000001
-#endif /* __iop_crc_par_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h
deleted file mode 100644
index e7d539feccb1..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h
+++ /dev/null
@@ -1,321 +0,0 @@
-#ifndef __iop_dmc_in_defs_asm_h
-#define __iop_dmc_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_dmc_in.r
- *     id:           iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:45 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_in_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_in.r
- *      id: $Id: iop_dmc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_cfg___sth_intr___lsb 0
-#define reg_iop_dmc_in_rw_cfg___sth_intr___width 3
-#define reg_iop_dmc_in_rw_cfg___last_dis_dif___lsb 3
-#define reg_iop_dmc_in_rw_cfg___last_dis_dif___width 1
-#define reg_iop_dmc_in_rw_cfg___last_dis_dif___bit 3
-#define reg_iop_dmc_in_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ctrl___dif_en___lsb 0
-#define reg_iop_dmc_in_rw_ctrl___dif_en___width 1
-#define reg_iop_dmc_in_rw_ctrl___dif_en___bit 0
-#define reg_iop_dmc_in_rw_ctrl___dif_dis___lsb 1
-#define reg_iop_dmc_in_rw_ctrl___dif_dis___width 1
-#define reg_iop_dmc_in_rw_ctrl___dif_dis___bit 1
-#define reg_iop_dmc_in_rw_ctrl___stream_clr___lsb 2
-#define reg_iop_dmc_in_rw_ctrl___stream_clr___width 1
-#define reg_iop_dmc_in_rw_ctrl___stream_clr___bit 2
-#define reg_iop_dmc_in_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_stat___dif_en___lsb 0
-#define reg_iop_dmc_in_r_stat___dif_en___width 1
-#define reg_iop_dmc_in_r_stat___dif_en___bit 0
-#define reg_iop_dmc_in_r_stat_offset 8
-
-/* Register rw_stream_cmd, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_stream_cmd___cmd___lsb 0
-#define reg_iop_dmc_in_rw_stream_cmd___cmd___width 10
-#define reg_iop_dmc_in_rw_stream_cmd___n___lsb 16
-#define reg_iop_dmc_in_rw_stream_cmd___n___width 8
-#define reg_iop_dmc_in_rw_stream_cmd_offset 12
-
-/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_stream_wr_data_offset 16
-
-/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_stream_wr_data_last_offset 20
-
-/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_stream_ctrl___eop___lsb 0
-#define reg_iop_dmc_in_rw_stream_ctrl___eop___width 1
-#define reg_iop_dmc_in_rw_stream_ctrl___eop___bit 0
-#define reg_iop_dmc_in_rw_stream_ctrl___wait___lsb 1
-#define reg_iop_dmc_in_rw_stream_ctrl___wait___width 1
-#define reg_iop_dmc_in_rw_stream_ctrl___wait___bit 1
-#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___lsb 2
-#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___width 1
-#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___bit 2
-#define reg_iop_dmc_in_rw_stream_ctrl___size___lsb 3
-#define reg_iop_dmc_in_rw_stream_ctrl___size___width 3
-#define reg_iop_dmc_in_rw_stream_ctrl_offset 24
-
-/* Register r_stream_stat, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_stream_stat___sth___lsb 0
-#define reg_iop_dmc_in_r_stream_stat___sth___width 7
-#define reg_iop_dmc_in_r_stream_stat___full___lsb 16
-#define reg_iop_dmc_in_r_stream_stat___full___width 1
-#define reg_iop_dmc_in_r_stream_stat___full___bit 16
-#define reg_iop_dmc_in_r_stream_stat___last_pkt___lsb 17
-#define reg_iop_dmc_in_r_stream_stat___last_pkt___width 1
-#define reg_iop_dmc_in_r_stream_stat___last_pkt___bit 17
-#define reg_iop_dmc_in_r_stream_stat___data_md_valid___lsb 18
-#define reg_iop_dmc_in_r_stream_stat___data_md_valid___width 1
-#define reg_iop_dmc_in_r_stream_stat___data_md_valid___bit 18
-#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___lsb 19
-#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___width 1
-#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___bit 19
-#define reg_iop_dmc_in_r_stream_stat___group_md_valid___lsb 20
-#define reg_iop_dmc_in_r_stream_stat___group_md_valid___width 1
-#define reg_iop_dmc_in_r_stream_stat___group_md_valid___bit 20
-#define reg_iop_dmc_in_r_stream_stat___stream_busy___lsb 21
-#define reg_iop_dmc_in_r_stream_stat___stream_busy___width 1
-#define reg_iop_dmc_in_r_stream_stat___stream_busy___bit 21
-#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___lsb 22
-#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___width 1
-#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___bit 22
-#define reg_iop_dmc_in_r_stream_stat_offset 28
-
-/* Register r_data_descr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_data_descr___ctrl___lsb 0
-#define reg_iop_dmc_in_r_data_descr___ctrl___width 8
-#define reg_iop_dmc_in_r_data_descr___stat___lsb 8
-#define reg_iop_dmc_in_r_data_descr___stat___width 8
-#define reg_iop_dmc_in_r_data_descr___md___lsb 16
-#define reg_iop_dmc_in_r_data_descr___md___width 16
-#define reg_iop_dmc_in_r_data_descr_offset 32
-
-/* Register r_ctxt_descr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_ctxt_descr___ctrl___lsb 0
-#define reg_iop_dmc_in_r_ctxt_descr___ctrl___width 8
-#define reg_iop_dmc_in_r_ctxt_descr___stat___lsb 8
-#define reg_iop_dmc_in_r_ctxt_descr___stat___width 8
-#define reg_iop_dmc_in_r_ctxt_descr___md0___lsb 16
-#define reg_iop_dmc_in_r_ctxt_descr___md0___width 16
-#define reg_iop_dmc_in_r_ctxt_descr_offset 36
-
-/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_ctxt_descr_md1_offset 40
-
-/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_ctxt_descr_md2_offset 44
-
-/* Register r_group_descr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_group_descr___ctrl___lsb 0
-#define reg_iop_dmc_in_r_group_descr___ctrl___width 8
-#define reg_iop_dmc_in_r_group_descr___stat___lsb 8
-#define reg_iop_dmc_in_r_group_descr___stat___width 8
-#define reg_iop_dmc_in_r_group_descr___md___lsb 16
-#define reg_iop_dmc_in_r_group_descr___md___width 16
-#define reg_iop_dmc_in_r_group_descr_offset 56
-
-/* Register rw_data_descr, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_data_descr___md___lsb 16
-#define reg_iop_dmc_in_rw_data_descr___md___width 16
-#define reg_iop_dmc_in_rw_data_descr_offset 60
-
-/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ctxt_descr___md0___lsb 16
-#define reg_iop_dmc_in_rw_ctxt_descr___md0___width 16
-#define reg_iop_dmc_in_rw_ctxt_descr_offset 64
-
-/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ctxt_descr_md1_offset 68
-
-/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ctxt_descr_md2_offset 72
-
-/* Register rw_group_descr, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_group_descr___md___lsb 16
-#define reg_iop_dmc_in_rw_group_descr___md___width 16
-#define reg_iop_dmc_in_rw_group_descr_offset 84
-
-/* Register rw_intr_mask, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_intr_mask___data_md___lsb 0
-#define reg_iop_dmc_in_rw_intr_mask___data_md___width 1
-#define reg_iop_dmc_in_rw_intr_mask___data_md___bit 0
-#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___lsb 1
-#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___width 1
-#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___bit 1
-#define reg_iop_dmc_in_rw_intr_mask___group_md___lsb 2
-#define reg_iop_dmc_in_rw_intr_mask___group_md___width 1
-#define reg_iop_dmc_in_rw_intr_mask___group_md___bit 2
-#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___lsb 3
-#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___width 1
-#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___bit 3
-#define reg_iop_dmc_in_rw_intr_mask___sth___lsb 4
-#define reg_iop_dmc_in_rw_intr_mask___sth___width 1
-#define reg_iop_dmc_in_rw_intr_mask___sth___bit 4
-#define reg_iop_dmc_in_rw_intr_mask___full___lsb 5
-#define reg_iop_dmc_in_rw_intr_mask___full___width 1
-#define reg_iop_dmc_in_rw_intr_mask___full___bit 5
-#define reg_iop_dmc_in_rw_intr_mask_offset 88
-
-/* Register rw_ack_intr, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ack_intr___data_md___lsb 0
-#define reg_iop_dmc_in_rw_ack_intr___data_md___width 1
-#define reg_iop_dmc_in_rw_ack_intr___data_md___bit 0
-#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___width 1
-#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___bit 1
-#define reg_iop_dmc_in_rw_ack_intr___group_md___lsb 2
-#define reg_iop_dmc_in_rw_ack_intr___group_md___width 1
-#define reg_iop_dmc_in_rw_ack_intr___group_md___bit 2
-#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___width 1
-#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_in_rw_ack_intr___sth___lsb 4
-#define reg_iop_dmc_in_rw_ack_intr___sth___width 1
-#define reg_iop_dmc_in_rw_ack_intr___sth___bit 4
-#define reg_iop_dmc_in_rw_ack_intr___full___lsb 5
-#define reg_iop_dmc_in_rw_ack_intr___full___width 1
-#define reg_iop_dmc_in_rw_ack_intr___full___bit 5
-#define reg_iop_dmc_in_rw_ack_intr_offset 92
-
-/* Register r_intr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_intr___data_md___lsb 0
-#define reg_iop_dmc_in_r_intr___data_md___width 1
-#define reg_iop_dmc_in_r_intr___data_md___bit 0
-#define reg_iop_dmc_in_r_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_in_r_intr___ctxt_md___width 1
-#define reg_iop_dmc_in_r_intr___ctxt_md___bit 1
-#define reg_iop_dmc_in_r_intr___group_md___lsb 2
-#define reg_iop_dmc_in_r_intr___group_md___width 1
-#define reg_iop_dmc_in_r_intr___group_md___bit 2
-#define reg_iop_dmc_in_r_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_in_r_intr___cmd_rdy___width 1
-#define reg_iop_dmc_in_r_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_in_r_intr___sth___lsb 4
-#define reg_iop_dmc_in_r_intr___sth___width 1
-#define reg_iop_dmc_in_r_intr___sth___bit 4
-#define reg_iop_dmc_in_r_intr___full___lsb 5
-#define reg_iop_dmc_in_r_intr___full___width 1
-#define reg_iop_dmc_in_r_intr___full___bit 5
-#define reg_iop_dmc_in_r_intr_offset 96
-
-/* Register r_masked_intr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_masked_intr___data_md___lsb 0
-#define reg_iop_dmc_in_r_masked_intr___data_md___width 1
-#define reg_iop_dmc_in_r_masked_intr___data_md___bit 0
-#define reg_iop_dmc_in_r_masked_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_in_r_masked_intr___ctxt_md___width 1
-#define reg_iop_dmc_in_r_masked_intr___ctxt_md___bit 1
-#define reg_iop_dmc_in_r_masked_intr___group_md___lsb 2
-#define reg_iop_dmc_in_r_masked_intr___group_md___width 1
-#define reg_iop_dmc_in_r_masked_intr___group_md___bit 2
-#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___width 1
-#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_in_r_masked_intr___sth___lsb 4
-#define reg_iop_dmc_in_r_masked_intr___sth___width 1
-#define reg_iop_dmc_in_r_masked_intr___sth___bit 4
-#define reg_iop_dmc_in_r_masked_intr___full___lsb 5
-#define reg_iop_dmc_in_r_masked_intr___full___width 1
-#define reg_iop_dmc_in_r_masked_intr___full___bit 5
-#define reg_iop_dmc_in_r_masked_intr_offset 100
-
-
-/* Constants */
-#define regk_iop_dmc_in_ack_pkt                   0x00000100
-#define regk_iop_dmc_in_array                     0x00000008
-#define regk_iop_dmc_in_burst                     0x00000020
-#define regk_iop_dmc_in_copy_next                 0x00000010
-#define regk_iop_dmc_in_copy_up                   0x00000020
-#define regk_iop_dmc_in_dis_c                     0x00000010
-#define regk_iop_dmc_in_dis_g                     0x00000020
-#define regk_iop_dmc_in_lim1                      0x00000000
-#define regk_iop_dmc_in_lim16                     0x00000004
-#define regk_iop_dmc_in_lim2                      0x00000001
-#define regk_iop_dmc_in_lim32                     0x00000005
-#define regk_iop_dmc_in_lim4                      0x00000002
-#define regk_iop_dmc_in_lim64                     0x00000006
-#define regk_iop_dmc_in_lim8                      0x00000003
-#define regk_iop_dmc_in_load_c                    0x00000200
-#define regk_iop_dmc_in_load_c_n                  0x00000280
-#define regk_iop_dmc_in_load_c_next               0x00000240
-#define regk_iop_dmc_in_load_d                    0x00000140
-#define regk_iop_dmc_in_load_g                    0x00000300
-#define regk_iop_dmc_in_load_g_down               0x000003c0
-#define regk_iop_dmc_in_load_g_next               0x00000340
-#define regk_iop_dmc_in_load_g_up                 0x00000380
-#define regk_iop_dmc_in_next_en                   0x00000010
-#define regk_iop_dmc_in_next_pkt                  0x00000010
-#define regk_iop_dmc_in_no                        0x00000000
-#define regk_iop_dmc_in_restore                   0x00000020
-#define regk_iop_dmc_in_rw_cfg_default            0x00000000
-#define regk_iop_dmc_in_rw_ctxt_descr_default     0x00000000
-#define regk_iop_dmc_in_rw_ctxt_descr_md1_default  0x00000000
-#define regk_iop_dmc_in_rw_ctxt_descr_md2_default  0x00000000
-#define regk_iop_dmc_in_rw_data_descr_default     0x00000000
-#define regk_iop_dmc_in_rw_group_descr_default    0x00000000
-#define regk_iop_dmc_in_rw_intr_mask_default      0x00000000
-#define regk_iop_dmc_in_rw_stream_ctrl_default    0x00000000
-#define regk_iop_dmc_in_save_down                 0x00000020
-#define regk_iop_dmc_in_save_up                   0x00000020
-#define regk_iop_dmc_in_set_reg                   0x00000050
-#define regk_iop_dmc_in_set_w_size1               0x00000190
-#define regk_iop_dmc_in_set_w_size2               0x000001a0
-#define regk_iop_dmc_in_set_w_size4               0x000001c0
-#define regk_iop_dmc_in_store_c                   0x00000002
-#define regk_iop_dmc_in_store_descr               0x00000000
-#define regk_iop_dmc_in_store_g                   0x00000004
-#define regk_iop_dmc_in_store_md                  0x00000001
-#define regk_iop_dmc_in_update_down               0x00000020
-#define regk_iop_dmc_in_yes                       0x00000001
-#endif /* __iop_dmc_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h
deleted file mode 100644
index 9fe1a8054371..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h
+++ /dev/null
@@ -1,349 +0,0 @@
-#ifndef __iop_dmc_out_defs_asm_h
-#define __iop_dmc_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_dmc_out.r
- *     id:           iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:45 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r
- *      id: $Id: iop_dmc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_cfg___trf_lim___lsb 0
-#define reg_iop_dmc_out_rw_cfg___trf_lim___width 16
-#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___lsb 16
-#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___width 1
-#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___bit 16
-#define reg_iop_dmc_out_rw_cfg___dth_intr___lsb 17
-#define reg_iop_dmc_out_rw_cfg___dth_intr___width 3
-#define reg_iop_dmc_out_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ctrl___dif_en___lsb 0
-#define reg_iop_dmc_out_rw_ctrl___dif_en___width 1
-#define reg_iop_dmc_out_rw_ctrl___dif_en___bit 0
-#define reg_iop_dmc_out_rw_ctrl___dif_dis___lsb 1
-#define reg_iop_dmc_out_rw_ctrl___dif_dis___width 1
-#define reg_iop_dmc_out_rw_ctrl___dif_dis___bit 1
-#define reg_iop_dmc_out_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_stat___dif_en___lsb 0
-#define reg_iop_dmc_out_r_stat___dif_en___width 1
-#define reg_iop_dmc_out_r_stat___dif_en___bit 0
-#define reg_iop_dmc_out_r_stat_offset 8
-
-/* Register rw_stream_cmd, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_stream_cmd___cmd___lsb 0
-#define reg_iop_dmc_out_rw_stream_cmd___cmd___width 10
-#define reg_iop_dmc_out_rw_stream_cmd___n___lsb 16
-#define reg_iop_dmc_out_rw_stream_cmd___n___width 8
-#define reg_iop_dmc_out_rw_stream_cmd_offset 12
-
-/* Register rs_stream_data, scope iop_dmc_out, type rs */
-#define reg_iop_dmc_out_rs_stream_data_offset 16
-
-/* Register r_stream_data, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_stream_data_offset 20
-
-/* Register r_stream_stat, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_stream_stat___dth___lsb 0
-#define reg_iop_dmc_out_r_stream_stat___dth___width 7
-#define reg_iop_dmc_out_r_stream_stat___dv___lsb 16
-#define reg_iop_dmc_out_r_stream_stat___dv___width 1
-#define reg_iop_dmc_out_r_stream_stat___dv___bit 16
-#define reg_iop_dmc_out_r_stream_stat___all_avail___lsb 17
-#define reg_iop_dmc_out_r_stream_stat___all_avail___width 1
-#define reg_iop_dmc_out_r_stream_stat___all_avail___bit 17
-#define reg_iop_dmc_out_r_stream_stat___last___lsb 18
-#define reg_iop_dmc_out_r_stream_stat___last___width 1
-#define reg_iop_dmc_out_r_stream_stat___last___bit 18
-#define reg_iop_dmc_out_r_stream_stat___size___lsb 19
-#define reg_iop_dmc_out_r_stream_stat___size___width 3
-#define reg_iop_dmc_out_r_stream_stat___data_md_valid___lsb 22
-#define reg_iop_dmc_out_r_stream_stat___data_md_valid___width 1
-#define reg_iop_dmc_out_r_stream_stat___data_md_valid___bit 22
-#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___lsb 23
-#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___width 1
-#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___bit 23
-#define reg_iop_dmc_out_r_stream_stat___group_md_valid___lsb 24
-#define reg_iop_dmc_out_r_stream_stat___group_md_valid___width 1
-#define reg_iop_dmc_out_r_stream_stat___group_md_valid___bit 24
-#define reg_iop_dmc_out_r_stream_stat___stream_busy___lsb 25
-#define reg_iop_dmc_out_r_stream_stat___stream_busy___width 1
-#define reg_iop_dmc_out_r_stream_stat___stream_busy___bit 25
-#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___lsb 26
-#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___width 1
-#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___bit 26
-#define reg_iop_dmc_out_r_stream_stat___cmd_rq___lsb 27
-#define reg_iop_dmc_out_r_stream_stat___cmd_rq___width 1
-#define reg_iop_dmc_out_r_stream_stat___cmd_rq___bit 27
-#define reg_iop_dmc_out_r_stream_stat_offset 24
-
-/* Register r_data_descr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_data_descr___ctrl___lsb 0
-#define reg_iop_dmc_out_r_data_descr___ctrl___width 8
-#define reg_iop_dmc_out_r_data_descr___stat___lsb 8
-#define reg_iop_dmc_out_r_data_descr___stat___width 8
-#define reg_iop_dmc_out_r_data_descr___md___lsb 16
-#define reg_iop_dmc_out_r_data_descr___md___width 16
-#define reg_iop_dmc_out_r_data_descr_offset 28
-
-/* Register r_ctxt_descr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_ctxt_descr___ctrl___lsb 0
-#define reg_iop_dmc_out_r_ctxt_descr___ctrl___width 8
-#define reg_iop_dmc_out_r_ctxt_descr___stat___lsb 8
-#define reg_iop_dmc_out_r_ctxt_descr___stat___width 8
-#define reg_iop_dmc_out_r_ctxt_descr___md0___lsb 16
-#define reg_iop_dmc_out_r_ctxt_descr___md0___width 16
-#define reg_iop_dmc_out_r_ctxt_descr_offset 32
-
-/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_ctxt_descr_md1_offset 36
-
-/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_ctxt_descr_md2_offset 40
-
-/* Register r_group_descr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_group_descr___ctrl___lsb 0
-#define reg_iop_dmc_out_r_group_descr___ctrl___width 8
-#define reg_iop_dmc_out_r_group_descr___stat___lsb 8
-#define reg_iop_dmc_out_r_group_descr___stat___width 8
-#define reg_iop_dmc_out_r_group_descr___md___lsb 16
-#define reg_iop_dmc_out_r_group_descr___md___width 16
-#define reg_iop_dmc_out_r_group_descr_offset 52
-
-/* Register rw_data_descr, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_data_descr___md___lsb 16
-#define reg_iop_dmc_out_rw_data_descr___md___width 16
-#define reg_iop_dmc_out_rw_data_descr_offset 56
-
-/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ctxt_descr___md0___lsb 16
-#define reg_iop_dmc_out_rw_ctxt_descr___md0___width 16
-#define reg_iop_dmc_out_rw_ctxt_descr_offset 60
-
-/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ctxt_descr_md1_offset 64
-
-/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ctxt_descr_md2_offset 68
-
-/* Register rw_group_descr, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_group_descr___md___lsb 16
-#define reg_iop_dmc_out_rw_group_descr___md___width 16
-#define reg_iop_dmc_out_rw_group_descr_offset 80
-
-/* Register rw_intr_mask, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_intr_mask___data_md___lsb 0
-#define reg_iop_dmc_out_rw_intr_mask___data_md___width 1
-#define reg_iop_dmc_out_rw_intr_mask___data_md___bit 0
-#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___lsb 1
-#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___width 1
-#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___bit 1
-#define reg_iop_dmc_out_rw_intr_mask___group_md___lsb 2
-#define reg_iop_dmc_out_rw_intr_mask___group_md___width 1
-#define reg_iop_dmc_out_rw_intr_mask___group_md___bit 2
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___lsb 3
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___width 1
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___bit 3
-#define reg_iop_dmc_out_rw_intr_mask___dth___lsb 4
-#define reg_iop_dmc_out_rw_intr_mask___dth___width 1
-#define reg_iop_dmc_out_rw_intr_mask___dth___bit 4
-#define reg_iop_dmc_out_rw_intr_mask___dv___lsb 5
-#define reg_iop_dmc_out_rw_intr_mask___dv___width 1
-#define reg_iop_dmc_out_rw_intr_mask___dv___bit 5
-#define reg_iop_dmc_out_rw_intr_mask___last_data___lsb 6
-#define reg_iop_dmc_out_rw_intr_mask___last_data___width 1
-#define reg_iop_dmc_out_rw_intr_mask___last_data___bit 6
-#define reg_iop_dmc_out_rw_intr_mask___trf_lim___lsb 7
-#define reg_iop_dmc_out_rw_intr_mask___trf_lim___width 1
-#define reg_iop_dmc_out_rw_intr_mask___trf_lim___bit 7
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___lsb 8
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___width 1
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___bit 8
-#define reg_iop_dmc_out_rw_intr_mask_offset 84
-
-/* Register rw_ack_intr, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ack_intr___data_md___lsb 0
-#define reg_iop_dmc_out_rw_ack_intr___data_md___width 1
-#define reg_iop_dmc_out_rw_ack_intr___data_md___bit 0
-#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___width 1
-#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___bit 1
-#define reg_iop_dmc_out_rw_ack_intr___group_md___lsb 2
-#define reg_iop_dmc_out_rw_ack_intr___group_md___width 1
-#define reg_iop_dmc_out_rw_ack_intr___group_md___bit 2
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___width 1
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_out_rw_ack_intr___dth___lsb 4
-#define reg_iop_dmc_out_rw_ack_intr___dth___width 1
-#define reg_iop_dmc_out_rw_ack_intr___dth___bit 4
-#define reg_iop_dmc_out_rw_ack_intr___dv___lsb 5
-#define reg_iop_dmc_out_rw_ack_intr___dv___width 1
-#define reg_iop_dmc_out_rw_ack_intr___dv___bit 5
-#define reg_iop_dmc_out_rw_ack_intr___last_data___lsb 6
-#define reg_iop_dmc_out_rw_ack_intr___last_data___width 1
-#define reg_iop_dmc_out_rw_ack_intr___last_data___bit 6
-#define reg_iop_dmc_out_rw_ack_intr___trf_lim___lsb 7
-#define reg_iop_dmc_out_rw_ack_intr___trf_lim___width 1
-#define reg_iop_dmc_out_rw_ack_intr___trf_lim___bit 7
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___lsb 8
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___width 1
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___bit 8
-#define reg_iop_dmc_out_rw_ack_intr_offset 88
-
-/* Register r_intr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_intr___data_md___lsb 0
-#define reg_iop_dmc_out_r_intr___data_md___width 1
-#define reg_iop_dmc_out_r_intr___data_md___bit 0
-#define reg_iop_dmc_out_r_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_out_r_intr___ctxt_md___width 1
-#define reg_iop_dmc_out_r_intr___ctxt_md___bit 1
-#define reg_iop_dmc_out_r_intr___group_md___lsb 2
-#define reg_iop_dmc_out_r_intr___group_md___width 1
-#define reg_iop_dmc_out_r_intr___group_md___bit 2
-#define reg_iop_dmc_out_r_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_out_r_intr___cmd_rdy___width 1
-#define reg_iop_dmc_out_r_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_out_r_intr___dth___lsb 4
-#define reg_iop_dmc_out_r_intr___dth___width 1
-#define reg_iop_dmc_out_r_intr___dth___bit 4
-#define reg_iop_dmc_out_r_intr___dv___lsb 5
-#define reg_iop_dmc_out_r_intr___dv___width 1
-#define reg_iop_dmc_out_r_intr___dv___bit 5
-#define reg_iop_dmc_out_r_intr___last_data___lsb 6
-#define reg_iop_dmc_out_r_intr___last_data___width 1
-#define reg_iop_dmc_out_r_intr___last_data___bit 6
-#define reg_iop_dmc_out_r_intr___trf_lim___lsb 7
-#define reg_iop_dmc_out_r_intr___trf_lim___width 1
-#define reg_iop_dmc_out_r_intr___trf_lim___bit 7
-#define reg_iop_dmc_out_r_intr___cmd_rq___lsb 8
-#define reg_iop_dmc_out_r_intr___cmd_rq___width 1
-#define reg_iop_dmc_out_r_intr___cmd_rq___bit 8
-#define reg_iop_dmc_out_r_intr_offset 92
-
-/* Register r_masked_intr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_masked_intr___data_md___lsb 0
-#define reg_iop_dmc_out_r_masked_intr___data_md___width 1
-#define reg_iop_dmc_out_r_masked_intr___data_md___bit 0
-#define reg_iop_dmc_out_r_masked_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_out_r_masked_intr___ctxt_md___width 1
-#define reg_iop_dmc_out_r_masked_intr___ctxt_md___bit 1
-#define reg_iop_dmc_out_r_masked_intr___group_md___lsb 2
-#define reg_iop_dmc_out_r_masked_intr___group_md___width 1
-#define reg_iop_dmc_out_r_masked_intr___group_md___bit 2
-#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___width 1
-#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_out_r_masked_intr___dth___lsb 4
-#define reg_iop_dmc_out_r_masked_intr___dth___width 1
-#define reg_iop_dmc_out_r_masked_intr___dth___bit 4
-#define reg_iop_dmc_out_r_masked_intr___dv___lsb 5
-#define reg_iop_dmc_out_r_masked_intr___dv___width 1
-#define reg_iop_dmc_out_r_masked_intr___dv___bit 5
-#define reg_iop_dmc_out_r_masked_intr___last_data___lsb 6
-#define reg_iop_dmc_out_r_masked_intr___last_data___width 1
-#define reg_iop_dmc_out_r_masked_intr___last_data___bit 6
-#define reg_iop_dmc_out_r_masked_intr___trf_lim___lsb 7
-#define reg_iop_dmc_out_r_masked_intr___trf_lim___width 1
-#define reg_iop_dmc_out_r_masked_intr___trf_lim___bit 7
-#define reg_iop_dmc_out_r_masked_intr___cmd_rq___lsb 8
-#define reg_iop_dmc_out_r_masked_intr___cmd_rq___width 1
-#define reg_iop_dmc_out_r_masked_intr___cmd_rq___bit 8
-#define reg_iop_dmc_out_r_masked_intr_offset 96
-
-
-/* Constants */
-#define regk_iop_dmc_out_ack_pkt                  0x00000100
-#define regk_iop_dmc_out_array                    0x00000008
-#define regk_iop_dmc_out_burst                    0x00000020
-#define regk_iop_dmc_out_copy_next                0x00000010
-#define regk_iop_dmc_out_copy_up                  0x00000020
-#define regk_iop_dmc_out_dis_c                    0x00000010
-#define regk_iop_dmc_out_dis_g                    0x00000020
-#define regk_iop_dmc_out_lim1                     0x00000000
-#define regk_iop_dmc_out_lim16                    0x00000004
-#define regk_iop_dmc_out_lim2                     0x00000001
-#define regk_iop_dmc_out_lim32                    0x00000005
-#define regk_iop_dmc_out_lim4                     0x00000002
-#define regk_iop_dmc_out_lim64                    0x00000006
-#define regk_iop_dmc_out_lim8                     0x00000003
-#define regk_iop_dmc_out_load_c                   0x00000200
-#define regk_iop_dmc_out_load_c_n                 0x00000280
-#define regk_iop_dmc_out_load_c_next              0x00000240
-#define regk_iop_dmc_out_load_d                   0x00000140
-#define regk_iop_dmc_out_load_g                   0x00000300
-#define regk_iop_dmc_out_load_g_down              0x000003c0
-#define regk_iop_dmc_out_load_g_next              0x00000340
-#define regk_iop_dmc_out_load_g_up                0x00000380
-#define regk_iop_dmc_out_next_en                  0x00000010
-#define regk_iop_dmc_out_next_pkt                 0x00000010
-#define regk_iop_dmc_out_no                       0x00000000
-#define regk_iop_dmc_out_restore                  0x00000020
-#define regk_iop_dmc_out_rw_cfg_default           0x00000000
-#define regk_iop_dmc_out_rw_ctxt_descr_default    0x00000000
-#define regk_iop_dmc_out_rw_ctxt_descr_md1_default  0x00000000
-#define regk_iop_dmc_out_rw_ctxt_descr_md2_default  0x00000000
-#define regk_iop_dmc_out_rw_data_descr_default    0x00000000
-#define regk_iop_dmc_out_rw_group_descr_default   0x00000000
-#define regk_iop_dmc_out_rw_intr_mask_default     0x00000000
-#define regk_iop_dmc_out_save_down                0x00000020
-#define regk_iop_dmc_out_save_up                  0x00000020
-#define regk_iop_dmc_out_set_reg                  0x00000050
-#define regk_iop_dmc_out_set_w_size1              0x00000190
-#define regk_iop_dmc_out_set_w_size2              0x000001a0
-#define regk_iop_dmc_out_set_w_size4              0x000001c0
-#define regk_iop_dmc_out_store_c                  0x00000002
-#define regk_iop_dmc_out_store_descr              0x00000000
-#define regk_iop_dmc_out_store_g                  0x00000004
-#define regk_iop_dmc_out_store_md                 0x00000001
-#define regk_iop_dmc_out_update_down              0x00000020
-#define regk_iop_dmc_out_yes                      0x00000001
-#endif /* __iop_dmc_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h
deleted file mode 100644
index 974dee082f9f..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h
+++ /dev/null
@@ -1,234 +0,0 @@
-#ifndef __iop_fifo_in_defs_asm_h
-#define __iop_fifo_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_fifo_in.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:07 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in.r
- *      id: $Id: iop_fifo_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_cfg___avail_lim___lsb 0
-#define reg_iop_fifo_in_rw_cfg___avail_lim___width 3
-#define reg_iop_fifo_in_rw_cfg___byte_order___lsb 3
-#define reg_iop_fifo_in_rw_cfg___byte_order___width 2
-#define reg_iop_fifo_in_rw_cfg___trig___lsb 5
-#define reg_iop_fifo_in_rw_cfg___trig___width 2
-#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___lsb 7
-#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___width 1
-#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___bit 7
-#define reg_iop_fifo_in_rw_cfg___mode___lsb 8
-#define reg_iop_fifo_in_rw_cfg___mode___width 2
-#define reg_iop_fifo_in_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_ctrl___dif_in_en___lsb 0
-#define reg_iop_fifo_in_rw_ctrl___dif_in_en___width 1
-#define reg_iop_fifo_in_rw_ctrl___dif_in_en___bit 0
-#define reg_iop_fifo_in_rw_ctrl___dif_out_en___lsb 1
-#define reg_iop_fifo_in_rw_ctrl___dif_out_en___width 1
-#define reg_iop_fifo_in_rw_ctrl___dif_out_en___bit 1
-#define reg_iop_fifo_in_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_stat___avail_bytes___lsb 0
-#define reg_iop_fifo_in_r_stat___avail_bytes___width 4
-#define reg_iop_fifo_in_r_stat___last___lsb 4
-#define reg_iop_fifo_in_r_stat___last___width 8
-#define reg_iop_fifo_in_r_stat___dif_in_en___lsb 12
-#define reg_iop_fifo_in_r_stat___dif_in_en___width 1
-#define reg_iop_fifo_in_r_stat___dif_in_en___bit 12
-#define reg_iop_fifo_in_r_stat___dif_out_en___lsb 13
-#define reg_iop_fifo_in_r_stat___dif_out_en___width 1
-#define reg_iop_fifo_in_r_stat___dif_out_en___bit 13
-#define reg_iop_fifo_in_r_stat_offset 8
-
-/* Register rs_rd1byte, scope iop_fifo_in, type rs */
-#define reg_iop_fifo_in_rs_rd1byte___data___lsb 0
-#define reg_iop_fifo_in_rs_rd1byte___data___width 8
-#define reg_iop_fifo_in_rs_rd1byte_offset 12
-
-/* Register r_rd1byte, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_rd1byte___data___lsb 0
-#define reg_iop_fifo_in_r_rd1byte___data___width 8
-#define reg_iop_fifo_in_r_rd1byte_offset 16
-
-/* Register rs_rd2byte, scope iop_fifo_in, type rs */
-#define reg_iop_fifo_in_rs_rd2byte___data___lsb 0
-#define reg_iop_fifo_in_rs_rd2byte___data___width 16
-#define reg_iop_fifo_in_rs_rd2byte_offset 20
-
-/* Register r_rd2byte, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_rd2byte___data___lsb 0
-#define reg_iop_fifo_in_r_rd2byte___data___width 16
-#define reg_iop_fifo_in_r_rd2byte_offset 24
-
-/* Register rs_rd3byte, scope iop_fifo_in, type rs */
-#define reg_iop_fifo_in_rs_rd3byte___data___lsb 0
-#define reg_iop_fifo_in_rs_rd3byte___data___width 24
-#define reg_iop_fifo_in_rs_rd3byte_offset 28
-
-/* Register r_rd3byte, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_rd3byte___data___lsb 0
-#define reg_iop_fifo_in_r_rd3byte___data___width 24
-#define reg_iop_fifo_in_r_rd3byte_offset 32
-
-/* Register rs_rd4byte, scope iop_fifo_in, type rs */
-#define reg_iop_fifo_in_rs_rd4byte___data___lsb 0
-#define reg_iop_fifo_in_rs_rd4byte___data___width 32
-#define reg_iop_fifo_in_rs_rd4byte_offset 36
-
-/* Register r_rd4byte, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_rd4byte___data___lsb 0
-#define reg_iop_fifo_in_r_rd4byte___data___width 32
-#define reg_iop_fifo_in_r_rd4byte_offset 40
-
-/* Register rw_set_last, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_set_last_offset 44
-
-/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_strb_dif_in___last___lsb 0
-#define reg_iop_fifo_in_rw_strb_dif_in___last___width 2
-#define reg_iop_fifo_in_rw_strb_dif_in_offset 48
-
-/* Register rw_intr_mask, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_intr_mask___urun___lsb 0
-#define reg_iop_fifo_in_rw_intr_mask___urun___width 1
-#define reg_iop_fifo_in_rw_intr_mask___urun___bit 0
-#define reg_iop_fifo_in_rw_intr_mask___last_data___lsb 1
-#define reg_iop_fifo_in_rw_intr_mask___last_data___width 1
-#define reg_iop_fifo_in_rw_intr_mask___last_data___bit 1
-#define reg_iop_fifo_in_rw_intr_mask___dav___lsb 2
-#define reg_iop_fifo_in_rw_intr_mask___dav___width 1
-#define reg_iop_fifo_in_rw_intr_mask___dav___bit 2
-#define reg_iop_fifo_in_rw_intr_mask___avail___lsb 3
-#define reg_iop_fifo_in_rw_intr_mask___avail___width 1
-#define reg_iop_fifo_in_rw_intr_mask___avail___bit 3
-#define reg_iop_fifo_in_rw_intr_mask___orun___lsb 4
-#define reg_iop_fifo_in_rw_intr_mask___orun___width 1
-#define reg_iop_fifo_in_rw_intr_mask___orun___bit 4
-#define reg_iop_fifo_in_rw_intr_mask_offset 52
-
-/* Register rw_ack_intr, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_ack_intr___urun___lsb 0
-#define reg_iop_fifo_in_rw_ack_intr___urun___width 1
-#define reg_iop_fifo_in_rw_ack_intr___urun___bit 0
-#define reg_iop_fifo_in_rw_ack_intr___last_data___lsb 1
-#define reg_iop_fifo_in_rw_ack_intr___last_data___width 1
-#define reg_iop_fifo_in_rw_ack_intr___last_data___bit 1
-#define reg_iop_fifo_in_rw_ack_intr___dav___lsb 2
-#define reg_iop_fifo_in_rw_ack_intr___dav___width 1
-#define reg_iop_fifo_in_rw_ack_intr___dav___bit 2
-#define reg_iop_fifo_in_rw_ack_intr___avail___lsb 3
-#define reg_iop_fifo_in_rw_ack_intr___avail___width 1
-#define reg_iop_fifo_in_rw_ack_intr___avail___bit 3
-#define reg_iop_fifo_in_rw_ack_intr___orun___lsb 4
-#define reg_iop_fifo_in_rw_ack_intr___orun___width 1
-#define reg_iop_fifo_in_rw_ack_intr___orun___bit 4
-#define reg_iop_fifo_in_rw_ack_intr_offset 56
-
-/* Register r_intr, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_intr___urun___lsb 0
-#define reg_iop_fifo_in_r_intr___urun___width 1
-#define reg_iop_fifo_in_r_intr___urun___bit 0
-#define reg_iop_fifo_in_r_intr___last_data___lsb 1
-#define reg_iop_fifo_in_r_intr___last_data___width 1
-#define reg_iop_fifo_in_r_intr___last_data___bit 1
-#define reg_iop_fifo_in_r_intr___dav___lsb 2
-#define reg_iop_fifo_in_r_intr___dav___width 1
-#define reg_iop_fifo_in_r_intr___dav___bit 2
-#define reg_iop_fifo_in_r_intr___avail___lsb 3
-#define reg_iop_fifo_in_r_intr___avail___width 1
-#define reg_iop_fifo_in_r_intr___avail___bit 3
-#define reg_iop_fifo_in_r_intr___orun___lsb 4
-#define reg_iop_fifo_in_r_intr___orun___width 1
-#define reg_iop_fifo_in_r_intr___orun___bit 4
-#define reg_iop_fifo_in_r_intr_offset 60
-
-/* Register r_masked_intr, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_masked_intr___urun___lsb 0
-#define reg_iop_fifo_in_r_masked_intr___urun___width 1
-#define reg_iop_fifo_in_r_masked_intr___urun___bit 0
-#define reg_iop_fifo_in_r_masked_intr___last_data___lsb 1
-#define reg_iop_fifo_in_r_masked_intr___last_data___width 1
-#define reg_iop_fifo_in_r_masked_intr___last_data___bit 1
-#define reg_iop_fifo_in_r_masked_intr___dav___lsb 2
-#define reg_iop_fifo_in_r_masked_intr___dav___width 1
-#define reg_iop_fifo_in_r_masked_intr___dav___bit 2
-#define reg_iop_fifo_in_r_masked_intr___avail___lsb 3
-#define reg_iop_fifo_in_r_masked_intr___avail___width 1
-#define reg_iop_fifo_in_r_masked_intr___avail___bit 3
-#define reg_iop_fifo_in_r_masked_intr___orun___lsb 4
-#define reg_iop_fifo_in_r_masked_intr___orun___width 1
-#define reg_iop_fifo_in_r_masked_intr___orun___bit 4
-#define reg_iop_fifo_in_r_masked_intr_offset 64
-
-
-/* Constants */
-#define regk_iop_fifo_in_dif_in                   0x00000002
-#define regk_iop_fifo_in_hi                       0x00000000
-#define regk_iop_fifo_in_neg                      0x00000002
-#define regk_iop_fifo_in_no                       0x00000000
-#define regk_iop_fifo_in_order16                  0x00000001
-#define regk_iop_fifo_in_order24                  0x00000002
-#define regk_iop_fifo_in_order32                  0x00000003
-#define regk_iop_fifo_in_order8                   0x00000000
-#define regk_iop_fifo_in_pos                      0x00000001
-#define regk_iop_fifo_in_pos_neg                  0x00000003
-#define regk_iop_fifo_in_rw_cfg_default           0x00000024
-#define regk_iop_fifo_in_rw_ctrl_default          0x00000000
-#define regk_iop_fifo_in_rw_intr_mask_default     0x00000000
-#define regk_iop_fifo_in_rw_set_last_default      0x00000000
-#define regk_iop_fifo_in_rw_strb_dif_in_default   0x00000000
-#define regk_iop_fifo_in_size16                   0x00000002
-#define regk_iop_fifo_in_size24                   0x00000001
-#define regk_iop_fifo_in_size32                   0x00000000
-#define regk_iop_fifo_in_size8                    0x00000003
-#define regk_iop_fifo_in_yes                      0x00000001
-#endif /* __iop_fifo_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h
deleted file mode 100644
index e00fab0c9335..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h
+++ /dev/null
@@ -1,155 +0,0 @@
-#ifndef __iop_fifo_in_extra_defs_asm_h
-#define __iop_fifo_in_extra_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_fifo_in_extra.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:08 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r
- *      id: $Id: iop_fifo_in_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */
-#define reg_iop_fifo_in_extra_rw_wr_data_offset 0
-
-/* Register r_stat, scope iop_fifo_in_extra, type r */
-#define reg_iop_fifo_in_extra_r_stat___avail_bytes___lsb 0
-#define reg_iop_fifo_in_extra_r_stat___avail_bytes___width 4
-#define reg_iop_fifo_in_extra_r_stat___last___lsb 4
-#define reg_iop_fifo_in_extra_r_stat___last___width 8
-#define reg_iop_fifo_in_extra_r_stat___dif_in_en___lsb 12
-#define reg_iop_fifo_in_extra_r_stat___dif_in_en___width 1
-#define reg_iop_fifo_in_extra_r_stat___dif_in_en___bit 12
-#define reg_iop_fifo_in_extra_r_stat___dif_out_en___lsb 13
-#define reg_iop_fifo_in_extra_r_stat___dif_out_en___width 1
-#define reg_iop_fifo_in_extra_r_stat___dif_out_en___bit 13
-#define reg_iop_fifo_in_extra_r_stat_offset 4
-
-/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */
-#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___lsb 0
-#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___width 2
-#define reg_iop_fifo_in_extra_rw_strb_dif_in_offset 8
-
-/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */
-#define reg_iop_fifo_in_extra_rw_intr_mask___urun___lsb 0
-#define reg_iop_fifo_in_extra_rw_intr_mask___urun___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___urun___bit 0
-#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___lsb 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___bit 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___dav___lsb 2
-#define reg_iop_fifo_in_extra_rw_intr_mask___dav___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___dav___bit 2
-#define reg_iop_fifo_in_extra_rw_intr_mask___avail___lsb 3
-#define reg_iop_fifo_in_extra_rw_intr_mask___avail___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___avail___bit 3
-#define reg_iop_fifo_in_extra_rw_intr_mask___orun___lsb 4
-#define reg_iop_fifo_in_extra_rw_intr_mask___orun___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___orun___bit 4
-#define reg_iop_fifo_in_extra_rw_intr_mask_offset 12
-
-/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */
-#define reg_iop_fifo_in_extra_rw_ack_intr___urun___lsb 0
-#define reg_iop_fifo_in_extra_rw_ack_intr___urun___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___urun___bit 0
-#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___lsb 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___bit 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___dav___lsb 2
-#define reg_iop_fifo_in_extra_rw_ack_intr___dav___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___dav___bit 2
-#define reg_iop_fifo_in_extra_rw_ack_intr___avail___lsb 3
-#define reg_iop_fifo_in_extra_rw_ack_intr___avail___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___avail___bit 3
-#define reg_iop_fifo_in_extra_rw_ack_intr___orun___lsb 4
-#define reg_iop_fifo_in_extra_rw_ack_intr___orun___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___orun___bit 4
-#define reg_iop_fifo_in_extra_rw_ack_intr_offset 16
-
-/* Register r_intr, scope iop_fifo_in_extra, type r */
-#define reg_iop_fifo_in_extra_r_intr___urun___lsb 0
-#define reg_iop_fifo_in_extra_r_intr___urun___width 1
-#define reg_iop_fifo_in_extra_r_intr___urun___bit 0
-#define reg_iop_fifo_in_extra_r_intr___last_data___lsb 1
-#define reg_iop_fifo_in_extra_r_intr___last_data___width 1
-#define reg_iop_fifo_in_extra_r_intr___last_data___bit 1
-#define reg_iop_fifo_in_extra_r_intr___dav___lsb 2
-#define reg_iop_fifo_in_extra_r_intr___dav___width 1
-#define reg_iop_fifo_in_extra_r_intr___dav___bit 2
-#define reg_iop_fifo_in_extra_r_intr___avail___lsb 3
-#define reg_iop_fifo_in_extra_r_intr___avail___width 1
-#define reg_iop_fifo_in_extra_r_intr___avail___bit 3
-#define reg_iop_fifo_in_extra_r_intr___orun___lsb 4
-#define reg_iop_fifo_in_extra_r_intr___orun___width 1
-#define reg_iop_fifo_in_extra_r_intr___orun___bit 4
-#define reg_iop_fifo_in_extra_r_intr_offset 20
-
-/* Register r_masked_intr, scope iop_fifo_in_extra, type r */
-#define reg_iop_fifo_in_extra_r_masked_intr___urun___lsb 0
-#define reg_iop_fifo_in_extra_r_masked_intr___urun___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___urun___bit 0
-#define reg_iop_fifo_in_extra_r_masked_intr___last_data___lsb 1
-#define reg_iop_fifo_in_extra_r_masked_intr___last_data___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___last_data___bit 1
-#define reg_iop_fifo_in_extra_r_masked_intr___dav___lsb 2
-#define reg_iop_fifo_in_extra_r_masked_intr___dav___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___dav___bit 2
-#define reg_iop_fifo_in_extra_r_masked_intr___avail___lsb 3
-#define reg_iop_fifo_in_extra_r_masked_intr___avail___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___avail___bit 3
-#define reg_iop_fifo_in_extra_r_masked_intr___orun___lsb 4
-#define reg_iop_fifo_in_extra_r_masked_intr___orun___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___orun___bit 4
-#define reg_iop_fifo_in_extra_r_masked_intr_offset 24
-
-
-/* Constants */
-#define regk_iop_fifo_in_extra_fifo_in            0x00000002
-#define regk_iop_fifo_in_extra_no                 0x00000000
-#define regk_iop_fifo_in_extra_rw_intr_mask_default  0x00000000
-#define regk_iop_fifo_in_extra_yes                0x00000001
-#endif /* __iop_fifo_in_extra_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h
deleted file mode 100644
index 9ec5f4a826df..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h
+++ /dev/null
@@ -1,254 +0,0 @@
-#ifndef __iop_fifo_out_defs_asm_h
-#define __iop_fifo_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_fifo_out.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:09 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r
- *      id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0
-#define reg_iop_fifo_out_rw_cfg___free_lim___width 3
-#define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3
-#define reg_iop_fifo_out_rw_cfg___byte_order___width 2
-#define reg_iop_fifo_out_rw_cfg___trig___lsb 5
-#define reg_iop_fifo_out_rw_cfg___trig___width 2
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7
-#define reg_iop_fifo_out_rw_cfg___mode___lsb 8
-#define reg_iop_fifo_out_rw_cfg___mode___width 2
-#define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10
-#define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1
-#define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11
-#define reg_iop_fifo_out_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0
-#define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1
-#define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0
-#define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1
-#define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1
-#define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1
-#define reg_iop_fifo_out_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_fifo_out, type r */
-#define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0
-#define reg_iop_fifo_out_r_stat___avail_bytes___width 4
-#define reg_iop_fifo_out_r_stat___last___lsb 4
-#define reg_iop_fifo_out_r_stat___last___width 8
-#define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12
-#define reg_iop_fifo_out_r_stat___dif_in_en___width 1
-#define reg_iop_fifo_out_r_stat___dif_in_en___bit 12
-#define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13
-#define reg_iop_fifo_out_r_stat___dif_out_en___width 1
-#define reg_iop_fifo_out_r_stat___dif_out_en___bit 13
-#define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14
-#define reg_iop_fifo_out_r_stat___zero_data_last___width 1
-#define reg_iop_fifo_out_r_stat___zero_data_last___bit 14
-#define reg_iop_fifo_out_r_stat_offset 8
-
-/* Register rw_wr1byte, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr1byte___data___lsb 0
-#define reg_iop_fifo_out_rw_wr1byte___data___width 8
-#define reg_iop_fifo_out_rw_wr1byte_offset 12
-
-/* Register rw_wr2byte, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr2byte___data___lsb 0
-#define reg_iop_fifo_out_rw_wr2byte___data___width 16
-#define reg_iop_fifo_out_rw_wr2byte_offset 16
-
-/* Register rw_wr3byte, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr3byte___data___lsb 0
-#define reg_iop_fifo_out_rw_wr3byte___data___width 24
-#define reg_iop_fifo_out_rw_wr3byte_offset 20
-
-/* Register rw_wr4byte, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr4byte___data___lsb 0
-#define reg_iop_fifo_out_rw_wr4byte___data___width 32
-#define reg_iop_fifo_out_rw_wr4byte_offset 24
-
-/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0
-#define reg_iop_fifo_out_rw_wr1byte_last___data___width 8
-#define reg_iop_fifo_out_rw_wr1byte_last_offset 28
-
-/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0
-#define reg_iop_fifo_out_rw_wr2byte_last___data___width 16
-#define reg_iop_fifo_out_rw_wr2byte_last_offset 32
-
-/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0
-#define reg_iop_fifo_out_rw_wr3byte_last___data___width 24
-#define reg_iop_fifo_out_rw_wr3byte_last_offset 36
-
-/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0
-#define reg_iop_fifo_out_rw_wr4byte_last___data___width 32
-#define reg_iop_fifo_out_rw_wr4byte_last_offset 40
-
-/* Register rw_set_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_set_last_offset 44
-
-/* Register rs_rd_data, scope iop_fifo_out, type rs */
-#define reg_iop_fifo_out_rs_rd_data_offset 48
-
-/* Register r_rd_data, scope iop_fifo_out, type r */
-#define reg_iop_fifo_out_r_rd_data_offset 52
-
-/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_strb_dif_out_offset 56
-
-/* Register rw_intr_mask, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0
-#define reg_iop_fifo_out_rw_intr_mask___urun___width 1
-#define reg_iop_fifo_out_rw_intr_mask___urun___bit 0
-#define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1
-#define reg_iop_fifo_out_rw_intr_mask___last_data___width 1
-#define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1
-#define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2
-#define reg_iop_fifo_out_rw_intr_mask___dav___width 1
-#define reg_iop_fifo_out_rw_intr_mask___dav___bit 2
-#define reg_iop_fifo_out_rw_intr_mask___free___lsb 3
-#define reg_iop_fifo_out_rw_intr_mask___free___width 1
-#define reg_iop_fifo_out_rw_intr_mask___free___bit 3
-#define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4
-#define reg_iop_fifo_out_rw_intr_mask___orun___width 1
-#define reg_iop_fifo_out_rw_intr_mask___orun___bit 4
-#define reg_iop_fifo_out_rw_intr_mask_offset 60
-
-/* Register rw_ack_intr, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0
-#define reg_iop_fifo_out_rw_ack_intr___urun___width 1
-#define reg_iop_fifo_out_rw_ack_intr___urun___bit 0
-#define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1
-#define reg_iop_fifo_out_rw_ack_intr___last_data___width 1
-#define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1
-#define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2
-#define reg_iop_fifo_out_rw_ack_intr___dav___width 1
-#define reg_iop_fifo_out_rw_ack_intr___dav___bit 2
-#define reg_iop_fifo_out_rw_ack_intr___free___lsb 3
-#define reg_iop_fifo_out_rw_ack_intr___free___width 1
-#define reg_iop_fifo_out_rw_ack_intr___free___bit 3
-#define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4
-#define reg_iop_fifo_out_rw_ack_intr___orun___width 1
-#define reg_iop_fifo_out_rw_ack_intr___orun___bit 4
-#define reg_iop_fifo_out_rw_ack_intr_offset 64
-
-/* Register r_intr, scope iop_fifo_out, type r */
-#define reg_iop_fifo_out_r_intr___urun___lsb 0
-#define reg_iop_fifo_out_r_intr___urun___width 1
-#define reg_iop_fifo_out_r_intr___urun___bit 0
-#define reg_iop_fifo_out_r_intr___last_data___lsb 1
-#define reg_iop_fifo_out_r_intr___last_data___width 1
-#define reg_iop_fifo_out_r_intr___last_data___bit 1
-#define reg_iop_fifo_out_r_intr___dav___lsb 2
-#define reg_iop_fifo_out_r_intr___dav___width 1
-#define reg_iop_fifo_out_r_intr___dav___bit 2
-#define reg_iop_fifo_out_r_intr___free___lsb 3
-#define reg_iop_fifo_out_r_intr___free___width 1
-#define reg_iop_fifo_out_r_intr___free___bit 3
-#define reg_iop_fifo_out_r_intr___orun___lsb 4
-#define reg_iop_fifo_out_r_intr___orun___width 1
-#define reg_iop_fifo_out_r_intr___orun___bit 4
-#define reg_iop_fifo_out_r_intr_offset 68
-
-/* Register r_masked_intr, scope iop_fifo_out, type r */
-#define reg_iop_fifo_out_r_masked_intr___urun___lsb 0
-#define reg_iop_fifo_out_r_masked_intr___urun___width 1
-#define reg_iop_fifo_out_r_masked_intr___urun___bit 0
-#define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1
-#define reg_iop_fifo_out_r_masked_intr___last_data___width 1
-#define reg_iop_fifo_out_r_masked_intr___last_data___bit 1
-#define reg_iop_fifo_out_r_masked_intr___dav___lsb 2
-#define reg_iop_fifo_out_r_masked_intr___dav___width 1
-#define reg_iop_fifo_out_r_masked_intr___dav___bit 2
-#define reg_iop_fifo_out_r_masked_intr___free___lsb 3
-#define reg_iop_fifo_out_r_masked_intr___free___width 1
-#define reg_iop_fifo_out_r_masked_intr___free___bit 3
-#define reg_iop_fifo_out_r_masked_intr___orun___lsb 4
-#define reg_iop_fifo_out_r_masked_intr___orun___width 1
-#define reg_iop_fifo_out_r_masked_intr___orun___bit 4
-#define reg_iop_fifo_out_r_masked_intr_offset 72
-
-
-/* Constants */
-#define regk_iop_fifo_out_hi                      0x00000000
-#define regk_iop_fifo_out_neg                     0x00000002
-#define regk_iop_fifo_out_no                      0x00000000
-#define regk_iop_fifo_out_order16                 0x00000001
-#define regk_iop_fifo_out_order24                 0x00000002
-#define regk_iop_fifo_out_order32                 0x00000003
-#define regk_iop_fifo_out_order8                  0x00000000
-#define regk_iop_fifo_out_pos                     0x00000001
-#define regk_iop_fifo_out_pos_neg                 0x00000003
-#define regk_iop_fifo_out_rw_cfg_default          0x00000024
-#define regk_iop_fifo_out_rw_ctrl_default         0x00000000
-#define regk_iop_fifo_out_rw_intr_mask_default    0x00000000
-#define regk_iop_fifo_out_rw_set_last_default     0x00000000
-#define regk_iop_fifo_out_rw_strb_dif_out_default  0x00000000
-#define regk_iop_fifo_out_rw_wr1byte_default      0x00000000
-#define regk_iop_fifo_out_rw_wr1byte_last_default  0x00000000
-#define regk_iop_fifo_out_rw_wr2byte_default      0x00000000
-#define regk_iop_fifo_out_rw_wr2byte_last_default  0x00000000
-#define regk_iop_fifo_out_rw_wr3byte_default      0x00000000
-#define regk_iop_fifo_out_rw_wr3byte_last_default  0x00000000
-#define regk_iop_fifo_out_rw_wr4byte_default      0x00000000
-#define regk_iop_fifo_out_rw_wr4byte_last_default  0x00000000
-#define regk_iop_fifo_out_size16                  0x00000002
-#define regk_iop_fifo_out_size24                  0x00000001
-#define regk_iop_fifo_out_size32                  0x00000000
-#define regk_iop_fifo_out_size8                   0x00000003
-#define regk_iop_fifo_out_yes                     0x00000001
-#endif /* __iop_fifo_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h
deleted file mode 100644
index 0f84a50cf77c..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h
+++ /dev/null
@@ -1,158 +0,0 @@
-#ifndef __iop_fifo_out_extra_defs_asm_h
-#define __iop_fifo_out_extra_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_fifo_out_extra.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:10 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
- *      id: $Id: iop_fifo_out_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */
-#define reg_iop_fifo_out_extra_rs_rd_data_offset 0
-
-/* Register r_rd_data, scope iop_fifo_out_extra, type r */
-#define reg_iop_fifo_out_extra_r_rd_data_offset 4
-
-/* Register r_stat, scope iop_fifo_out_extra, type r */
-#define reg_iop_fifo_out_extra_r_stat___avail_bytes___lsb 0
-#define reg_iop_fifo_out_extra_r_stat___avail_bytes___width 4
-#define reg_iop_fifo_out_extra_r_stat___last___lsb 4
-#define reg_iop_fifo_out_extra_r_stat___last___width 8
-#define reg_iop_fifo_out_extra_r_stat___dif_in_en___lsb 12
-#define reg_iop_fifo_out_extra_r_stat___dif_in_en___width 1
-#define reg_iop_fifo_out_extra_r_stat___dif_in_en___bit 12
-#define reg_iop_fifo_out_extra_r_stat___dif_out_en___lsb 13
-#define reg_iop_fifo_out_extra_r_stat___dif_out_en___width 1
-#define reg_iop_fifo_out_extra_r_stat___dif_out_en___bit 13
-#define reg_iop_fifo_out_extra_r_stat___zero_data_last___lsb 14
-#define reg_iop_fifo_out_extra_r_stat___zero_data_last___width 1
-#define reg_iop_fifo_out_extra_r_stat___zero_data_last___bit 14
-#define reg_iop_fifo_out_extra_r_stat_offset 8
-
-/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
-#define reg_iop_fifo_out_extra_rw_strb_dif_out_offset 12
-
-/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
-#define reg_iop_fifo_out_extra_rw_intr_mask___urun___lsb 0
-#define reg_iop_fifo_out_extra_rw_intr_mask___urun___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___urun___bit 0
-#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___lsb 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___bit 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___dav___lsb 2
-#define reg_iop_fifo_out_extra_rw_intr_mask___dav___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___dav___bit 2
-#define reg_iop_fifo_out_extra_rw_intr_mask___free___lsb 3
-#define reg_iop_fifo_out_extra_rw_intr_mask___free___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___free___bit 3
-#define reg_iop_fifo_out_extra_rw_intr_mask___orun___lsb 4
-#define reg_iop_fifo_out_extra_rw_intr_mask___orun___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___orun___bit 4
-#define reg_iop_fifo_out_extra_rw_intr_mask_offset 16
-
-/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
-#define reg_iop_fifo_out_extra_rw_ack_intr___urun___lsb 0
-#define reg_iop_fifo_out_extra_rw_ack_intr___urun___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___urun___bit 0
-#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___lsb 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___bit 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___dav___lsb 2
-#define reg_iop_fifo_out_extra_rw_ack_intr___dav___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___dav___bit 2
-#define reg_iop_fifo_out_extra_rw_ack_intr___free___lsb 3
-#define reg_iop_fifo_out_extra_rw_ack_intr___free___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___free___bit 3
-#define reg_iop_fifo_out_extra_rw_ack_intr___orun___lsb 4
-#define reg_iop_fifo_out_extra_rw_ack_intr___orun___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___orun___bit 4
-#define reg_iop_fifo_out_extra_rw_ack_intr_offset 20
-
-/* Register r_intr, scope iop_fifo_out_extra, type r */
-#define reg_iop_fifo_out_extra_r_intr___urun___lsb 0
-#define reg_iop_fifo_out_extra_r_intr___urun___width 1
-#define reg_iop_fifo_out_extra_r_intr___urun___bit 0
-#define reg_iop_fifo_out_extra_r_intr___last_data___lsb 1
-#define reg_iop_fifo_out_extra_r_intr___last_data___width 1
-#define reg_iop_fifo_out_extra_r_intr___last_data___bit 1
-#define reg_iop_fifo_out_extra_r_intr___dav___lsb 2
-#define reg_iop_fifo_out_extra_r_intr___dav___width 1
-#define reg_iop_fifo_out_extra_r_intr___dav___bit 2
-#define reg_iop_fifo_out_extra_r_intr___free___lsb 3
-#define reg_iop_fifo_out_extra_r_intr___free___width 1
-#define reg_iop_fifo_out_extra_r_intr___free___bit 3
-#define reg_iop_fifo_out_extra_r_intr___orun___lsb 4
-#define reg_iop_fifo_out_extra_r_intr___orun___width 1
-#define reg_iop_fifo_out_extra_r_intr___orun___bit 4
-#define reg_iop_fifo_out_extra_r_intr_offset 24
-
-/* Register r_masked_intr, scope iop_fifo_out_extra, type r */
-#define reg_iop_fifo_out_extra_r_masked_intr___urun___lsb 0
-#define reg_iop_fifo_out_extra_r_masked_intr___urun___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___urun___bit 0
-#define reg_iop_fifo_out_extra_r_masked_intr___last_data___lsb 1
-#define reg_iop_fifo_out_extra_r_masked_intr___last_data___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___last_data___bit 1
-#define reg_iop_fifo_out_extra_r_masked_intr___dav___lsb 2
-#define reg_iop_fifo_out_extra_r_masked_intr___dav___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___dav___bit 2
-#define reg_iop_fifo_out_extra_r_masked_intr___free___lsb 3
-#define reg_iop_fifo_out_extra_r_masked_intr___free___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___free___bit 3
-#define reg_iop_fifo_out_extra_r_masked_intr___orun___lsb 4
-#define reg_iop_fifo_out_extra_r_masked_intr___orun___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___orun___bit 4
-#define reg_iop_fifo_out_extra_r_masked_intr_offset 28
-
-
-/* Constants */
-#define regk_iop_fifo_out_extra_no                0x00000000
-#define regk_iop_fifo_out_extra_rw_intr_mask_default  0x00000000
-#define regk_iop_fifo_out_extra_yes               0x00000001
-#endif /* __iop_fifo_out_extra_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h
deleted file mode 100644
index 80490c82cc29..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h
+++ /dev/null
@@ -1,177 +0,0 @@
-#ifndef __iop_mpu_defs_asm_h
-#define __iop_mpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_mpu.r
- *     id:           iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:45 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r
- *      id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_iop_mpu_rw_r 4
-/* Register rw_r, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_r_offset 0
-
-/* Register rw_ctrl, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_ctrl___en___lsb 0
-#define reg_iop_mpu_rw_ctrl___en___width 1
-#define reg_iop_mpu_rw_ctrl___en___bit 0
-#define reg_iop_mpu_rw_ctrl_offset 128
-
-/* Register r_pc, scope iop_mpu, type r */
-#define reg_iop_mpu_r_pc___addr___lsb 0
-#define reg_iop_mpu_r_pc___addr___width 12
-#define reg_iop_mpu_r_pc_offset 132
-
-/* Register r_stat, scope iop_mpu, type r */
-#define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0
-#define reg_iop_mpu_r_stat___instr_reg_busy___width 1
-#define reg_iop_mpu_r_stat___instr_reg_busy___bit 0
-#define reg_iop_mpu_r_stat___intr_busy___lsb 1
-#define reg_iop_mpu_r_stat___intr_busy___width 1
-#define reg_iop_mpu_r_stat___intr_busy___bit 1
-#define reg_iop_mpu_r_stat___intr_vect___lsb 2
-#define reg_iop_mpu_r_stat___intr_vect___width 16
-#define reg_iop_mpu_r_stat_offset 136
-
-/* Register rw_instr, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_instr_offset 140
-
-/* Register rw_immediate, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_immediate_offset 144
-
-/* Register r_trace, scope iop_mpu, type r */
-#define reg_iop_mpu_r_trace___intr_vect___lsb 0
-#define reg_iop_mpu_r_trace___intr_vect___width 16
-#define reg_iop_mpu_r_trace___pc___lsb 16
-#define reg_iop_mpu_r_trace___pc___width 12
-#define reg_iop_mpu_r_trace___en___lsb 28
-#define reg_iop_mpu_r_trace___en___width 1
-#define reg_iop_mpu_r_trace___en___bit 28
-#define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29
-#define reg_iop_mpu_r_trace___instr_reg_busy___width 1
-#define reg_iop_mpu_r_trace___instr_reg_busy___bit 29
-#define reg_iop_mpu_r_trace___intr_busy___lsb 30
-#define reg_iop_mpu_r_trace___intr_busy___width 1
-#define reg_iop_mpu_r_trace___intr_busy___bit 30
-#define reg_iop_mpu_r_trace_offset 148
-
-/* Register r_wr_stat, scope iop_mpu, type r */
-#define reg_iop_mpu_r_wr_stat___r0___lsb 0
-#define reg_iop_mpu_r_wr_stat___r0___width 1
-#define reg_iop_mpu_r_wr_stat___r0___bit 0
-#define reg_iop_mpu_r_wr_stat___r1___lsb 1
-#define reg_iop_mpu_r_wr_stat___r1___width 1
-#define reg_iop_mpu_r_wr_stat___r1___bit 1
-#define reg_iop_mpu_r_wr_stat___r2___lsb 2
-#define reg_iop_mpu_r_wr_stat___r2___width 1
-#define reg_iop_mpu_r_wr_stat___r2___bit 2
-#define reg_iop_mpu_r_wr_stat___r3___lsb 3
-#define reg_iop_mpu_r_wr_stat___r3___width 1
-#define reg_iop_mpu_r_wr_stat___r3___bit 3
-#define reg_iop_mpu_r_wr_stat___r4___lsb 4
-#define reg_iop_mpu_r_wr_stat___r4___width 1
-#define reg_iop_mpu_r_wr_stat___r4___bit 4
-#define reg_iop_mpu_r_wr_stat___r5___lsb 5
-#define reg_iop_mpu_r_wr_stat___r5___width 1
-#define reg_iop_mpu_r_wr_stat___r5___bit 5
-#define reg_iop_mpu_r_wr_stat___r6___lsb 6
-#define reg_iop_mpu_r_wr_stat___r6___width 1
-#define reg_iop_mpu_r_wr_stat___r6___bit 6
-#define reg_iop_mpu_r_wr_stat___r7___lsb 7
-#define reg_iop_mpu_r_wr_stat___r7___width 1
-#define reg_iop_mpu_r_wr_stat___r7___bit 7
-#define reg_iop_mpu_r_wr_stat___r8___lsb 8
-#define reg_iop_mpu_r_wr_stat___r8___width 1
-#define reg_iop_mpu_r_wr_stat___r8___bit 8
-#define reg_iop_mpu_r_wr_stat___r9___lsb 9
-#define reg_iop_mpu_r_wr_stat___r9___width 1
-#define reg_iop_mpu_r_wr_stat___r9___bit 9
-#define reg_iop_mpu_r_wr_stat___r10___lsb 10
-#define reg_iop_mpu_r_wr_stat___r10___width 1
-#define reg_iop_mpu_r_wr_stat___r10___bit 10
-#define reg_iop_mpu_r_wr_stat___r11___lsb 11
-#define reg_iop_mpu_r_wr_stat___r11___width 1
-#define reg_iop_mpu_r_wr_stat___r11___bit 11
-#define reg_iop_mpu_r_wr_stat___r12___lsb 12
-#define reg_iop_mpu_r_wr_stat___r12___width 1
-#define reg_iop_mpu_r_wr_stat___r12___bit 12
-#define reg_iop_mpu_r_wr_stat___r13___lsb 13
-#define reg_iop_mpu_r_wr_stat___r13___width 1
-#define reg_iop_mpu_r_wr_stat___r13___bit 13
-#define reg_iop_mpu_r_wr_stat___r14___lsb 14
-#define reg_iop_mpu_r_wr_stat___r14___width 1
-#define reg_iop_mpu_r_wr_stat___r14___bit 14
-#define reg_iop_mpu_r_wr_stat___r15___lsb 15
-#define reg_iop_mpu_r_wr_stat___r15___width 1
-#define reg_iop_mpu_r_wr_stat___r15___bit 15
-#define reg_iop_mpu_r_wr_stat_offset 152
-
-#define STRIDE_iop_mpu_rw_thread 4
-/* Register rw_thread, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_thread___addr___lsb 0
-#define reg_iop_mpu_rw_thread___addr___width 12
-#define reg_iop_mpu_rw_thread_offset 156
-
-#define STRIDE_iop_mpu_rw_intr 4
-/* Register rw_intr, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_intr___addr___lsb 0
-#define reg_iop_mpu_rw_intr___addr___width 12
-#define reg_iop_mpu_rw_intr_offset 196
-
-
-/* Constants */
-#define regk_iop_mpu_no                           0x00000000
-#define regk_iop_mpu_r_pc_default                 0x00000000
-#define regk_iop_mpu_rw_ctrl_default              0x00000000
-#define regk_iop_mpu_rw_intr_size                 0x00000010
-#define regk_iop_mpu_rw_r_size                    0x00000010
-#define regk_iop_mpu_rw_thread_default            0x00000000
-#define regk_iop_mpu_rw_thread_size               0x00000004
-#define regk_iop_mpu_yes                          0x00000001
-#endif /* __iop_mpu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h
deleted file mode 100644
index a20b8857b4d0..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Autogenerated Changes here will be lost!
- * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg
- */
-#define iop_version 0
-#define iop_fifo_in0_extra 64
-#define iop_fifo_in1_extra 128
-#define iop_fifo_out0_extra 192
-#define iop_fifo_out1_extra 256
-#define iop_trigger_grp0 320
-#define iop_trigger_grp1 384
-#define iop_trigger_grp2 448
-#define iop_trigger_grp3 512
-#define iop_trigger_grp4 576
-#define iop_trigger_grp5 640
-#define iop_trigger_grp6 704
-#define iop_trigger_grp7 768
-#define iop_crc_par0 896
-#define iop_crc_par1 1024
-#define iop_dmc_in0 1152
-#define iop_dmc_in1 1280
-#define iop_dmc_out0 1408
-#define iop_dmc_out1 1536
-#define iop_fifo_in0 1664
-#define iop_fifo_in1 1792
-#define iop_fifo_out0 1920
-#define iop_fifo_out1 2048
-#define iop_scrc_in0 2176
-#define iop_scrc_in1 2304
-#define iop_scrc_out0 2432
-#define iop_scrc_out1 2560
-#define iop_timer_grp0 2688
-#define iop_timer_grp1 2816
-#define iop_timer_grp2 2944
-#define iop_timer_grp3 3072
-#define iop_sap_in 3328
-#define iop_sap_out 3584
-#define iop_spu0 3840
-#define iop_spu1 4096
-#define iop_sw_cfg 4352
-#define iop_sw_cpu 4608
-#define iop_sw_mpu 4864
-#define iop_sw_spu0 5120
-#define iop_sw_spu1 5376
-#define iop_mpu 5632
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h
deleted file mode 100644
index a4a10ff300b3..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h
+++ /dev/null
@@ -1,182 +0,0 @@
-#ifndef __iop_sap_in_defs_asm_h
-#define __iop_sap_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_sap_in.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:08:45 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r
- *      id: $Id: iop_sap_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_bus0_sync, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0
-#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2
-#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3
-#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5
-#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7
-#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1
-#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7
-#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8
-#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10
-#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3
-#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13
-#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15
-#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1
-#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15
-#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16
-#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18
-#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3
-#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21
-#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23
-#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1
-#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23
-#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24
-#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26
-#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3
-#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29
-#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31
-#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1
-#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31
-#define reg_iop_sap_in_rw_bus0_sync_offset 0
-
-/* Register rw_bus1_sync, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0
-#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2
-#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3
-#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5
-#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7
-#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1
-#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7
-#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8
-#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10
-#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3
-#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13
-#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15
-#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1
-#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15
-#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16
-#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18
-#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3
-#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21
-#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23
-#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1
-#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23
-#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24
-#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26
-#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3
-#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29
-#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31
-#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1
-#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31
-#define reg_iop_sap_in_rw_bus1_sync_offset 4
-
-#define STRIDE_iop_sap_in_rw_gio 4
-/* Register rw_gio, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
-#define reg_iop_sap_in_rw_gio___sync_sel___width 2
-#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
-#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
-#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
-#define reg_iop_sap_in_rw_gio___sync_edge___width 2
-#define reg_iop_sap_in_rw_gio___delay___lsb 7
-#define reg_iop_sap_in_rw_gio___delay___width 1
-#define reg_iop_sap_in_rw_gio___delay___bit 7
-#define reg_iop_sap_in_rw_gio___logic___lsb 8
-#define reg_iop_sap_in_rw_gio___logic___width 2
-#define reg_iop_sap_in_rw_gio_offset 8
-
-
-/* Constants */
-#define regk_iop_sap_in_and                       0x00000002
-#define regk_iop_sap_in_ext_clk200                0x00000003
-#define regk_iop_sap_in_gio1                      0x00000000
-#define regk_iop_sap_in_gio13                     0x00000005
-#define regk_iop_sap_in_gio18                     0x00000003
-#define regk_iop_sap_in_gio19                     0x00000004
-#define regk_iop_sap_in_gio21                     0x00000006
-#define regk_iop_sap_in_gio23                     0x00000005
-#define regk_iop_sap_in_gio29                     0x00000007
-#define regk_iop_sap_in_gio5                      0x00000004
-#define regk_iop_sap_in_gio6                      0x00000001
-#define regk_iop_sap_in_gio7                      0x00000002
-#define regk_iop_sap_in_inv                       0x00000001
-#define regk_iop_sap_in_neg                       0x00000002
-#define regk_iop_sap_in_no                        0x00000000
-#define regk_iop_sap_in_no_del_ext_clk200         0x00000001
-#define regk_iop_sap_in_none                      0x00000000
-#define regk_iop_sap_in_or                        0x00000003
-#define regk_iop_sap_in_pos                       0x00000001
-#define regk_iop_sap_in_pos_neg                   0x00000003
-#define regk_iop_sap_in_rw_bus0_sync_default      0x02020202
-#define regk_iop_sap_in_rw_bus1_sync_default      0x02020202
-#define regk_iop_sap_in_rw_gio_default            0x00000002
-#define regk_iop_sap_in_rw_gio_size               0x00000020
-#define regk_iop_sap_in_timer_grp0_tmr3           0x00000006
-#define regk_iop_sap_in_timer_grp1_tmr3           0x00000004
-#define regk_iop_sap_in_timer_grp2_tmr3           0x00000005
-#define regk_iop_sap_in_timer_grp3_tmr3           0x00000007
-#define regk_iop_sap_in_tmr_clk200                0x00000000
-#define regk_iop_sap_in_two_clk200                0x00000002
-#define regk_iop_sap_in_yes                       0x00000001
-#endif /* __iop_sap_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h
deleted file mode 100644
index 0ec727f92a25..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h
+++ /dev/null
@@ -1,346 +0,0 @@
-#ifndef __iop_sap_out_defs_asm_h
-#define __iop_sap_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_sap_out.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r
- *      id: $Id: iop_sap_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_gen_gated, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0
-#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4
-#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7
-#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9
-#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11
-#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated___clk2_src___lsb 14
-#define reg_iop_sap_out_rw_gen_gated___clk2_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___lsb 16
-#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___lsb 18
-#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated___clk3_src___lsb 21
-#define reg_iop_sap_out_rw_gen_gated___clk3_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___lsb 23
-#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___lsb 25
-#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated_offset 0
-
-/* Register rw_bus0, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___lsb 3
-#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___lsb 5
-#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___bit 5
-#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___lsb 6
-#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___lsb 9
-#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___lsb 11
-#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___bit 11
-#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___lsb 12
-#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___lsb 15
-#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___lsb 17
-#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___bit 17
-#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___lsb 18
-#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___lsb 21
-#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___lsb 23
-#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___bit 23
-#define reg_iop_sap_out_rw_bus0_offset 4
-
-/* Register rw_bus1, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___lsb 3
-#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___lsb 5
-#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___bit 5
-#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___lsb 6
-#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___lsb 9
-#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___lsb 11
-#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___bit 11
-#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___lsb 12
-#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___lsb 15
-#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___lsb 17
-#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___bit 17
-#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___lsb 18
-#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___lsb 21
-#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___lsb 23
-#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___bit 23
-#define reg_iop_sap_out_rw_bus1_offset 8
-
-/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___lsb 6
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___lsb 8
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___bit 8
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___lsb 9
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___width 2
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___lsb 20
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___width 2
-#define reg_iop_sap_out_rw_bus0_lo_oe_offset 12
-
-/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___lsb 6
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___lsb 8
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___bit 8
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___lsb 9
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___width 2
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___lsb 20
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___width 2
-#define reg_iop_sap_out_rw_bus0_hi_oe_offset 16
-
-/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___lsb 6
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___lsb 8
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___bit 8
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___lsb 9
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___width 2
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___lsb 20
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___width 2
-#define reg_iop_sap_out_rw_bus1_lo_oe_offset 20
-
-/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___lsb 6
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___lsb 8
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___bit 8
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___lsb 9
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___width 2
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___lsb 20
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___width 2
-#define reg_iop_sap_out_rw_bus1_hi_oe_offset 24
-
-#define STRIDE_iop_sap_out_rw_gio 4
-/* Register rw_gio, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3
-#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_gio___out_clk_ext___width 4
-#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 7
-#define reg_iop_sap_out_rw_gio___out_gated_clk___width 2
-#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 9
-#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1
-#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 9
-#define reg_iop_sap_out_rw_gio___out_logic___lsb 10
-#define reg_iop_sap_out_rw_gio___out_logic___width 1
-#define reg_iop_sap_out_rw_gio___out_logic___bit 10
-#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3
-#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 3
-#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 2
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 19
-#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20
-#define reg_iop_sap_out_rw_gio___oe_logic___width 2
-#define reg_iop_sap_out_rw_gio_offset 28
-
-
-/* Constants */
-#define regk_iop_sap_out_and                      0x00000002
-#define regk_iop_sap_out_clk0                     0x00000000
-#define regk_iop_sap_out_clk1                     0x00000001
-#define regk_iop_sap_out_clk12                    0x00000002
-#define regk_iop_sap_out_clk2                     0x00000002
-#define regk_iop_sap_out_clk200                   0x00000001
-#define regk_iop_sap_out_clk3                     0x00000003
-#define regk_iop_sap_out_ext                      0x00000003
-#define regk_iop_sap_out_gated                    0x00000004
-#define regk_iop_sap_out_gio1                     0x00000000
-#define regk_iop_sap_out_gio13                    0x00000002
-#define regk_iop_sap_out_gio13_clk                0x0000000c
-#define regk_iop_sap_out_gio15                    0x00000001
-#define regk_iop_sap_out_gio18                    0x00000003
-#define regk_iop_sap_out_gio18_clk                0x0000000d
-#define regk_iop_sap_out_gio1_clk                 0x00000008
-#define regk_iop_sap_out_gio21_clk                0x0000000e
-#define regk_iop_sap_out_gio23                    0x00000002
-#define regk_iop_sap_out_gio29_clk                0x0000000f
-#define regk_iop_sap_out_gio31                    0x00000003
-#define regk_iop_sap_out_gio5                     0x00000001
-#define regk_iop_sap_out_gio5_clk                 0x00000009
-#define regk_iop_sap_out_gio6_clk                 0x0000000a
-#define regk_iop_sap_out_gio7                     0x00000000
-#define regk_iop_sap_out_gio7_clk                 0x0000000b
-#define regk_iop_sap_out_gio_in13                 0x00000001
-#define regk_iop_sap_out_gio_in21                 0x00000002
-#define regk_iop_sap_out_gio_in29                 0x00000003
-#define regk_iop_sap_out_gio_in5                  0x00000000
-#define regk_iop_sap_out_inv                      0x00000001
-#define regk_iop_sap_out_nand                     0x00000003
-#define regk_iop_sap_out_no                       0x00000000
-#define regk_iop_sap_out_none                     0x00000000
-#define regk_iop_sap_out_rw_bus0_default          0x00000000
-#define regk_iop_sap_out_rw_bus0_hi_oe_default    0x00000000
-#define regk_iop_sap_out_rw_bus0_lo_oe_default    0x00000000
-#define regk_iop_sap_out_rw_bus1_default          0x00000000
-#define regk_iop_sap_out_rw_bus1_hi_oe_default    0x00000000
-#define regk_iop_sap_out_rw_bus1_lo_oe_default    0x00000000
-#define regk_iop_sap_out_rw_gen_gated_default     0x00000000
-#define regk_iop_sap_out_rw_gio_default           0x00000000
-#define regk_iop_sap_out_rw_gio_size              0x00000020
-#define regk_iop_sap_out_spu0_gio0                0x00000002
-#define regk_iop_sap_out_spu0_gio1                0x00000003
-#define regk_iop_sap_out_spu0_gio12               0x00000004
-#define regk_iop_sap_out_spu0_gio13               0x00000004
-#define regk_iop_sap_out_spu0_gio14               0x00000004
-#define regk_iop_sap_out_spu0_gio15               0x00000004
-#define regk_iop_sap_out_spu0_gio2                0x00000002
-#define regk_iop_sap_out_spu0_gio3                0x00000003
-#define regk_iop_sap_out_spu0_gio4                0x00000002
-#define regk_iop_sap_out_spu0_gio5                0x00000003
-#define regk_iop_sap_out_spu0_gio6                0x00000002
-#define regk_iop_sap_out_spu0_gio7                0x00000003
-#define regk_iop_sap_out_spu1_gio0                0x00000005
-#define regk_iop_sap_out_spu1_gio1                0x00000006
-#define regk_iop_sap_out_spu1_gio12               0x00000007
-#define regk_iop_sap_out_spu1_gio13               0x00000007
-#define regk_iop_sap_out_spu1_gio14               0x00000007
-#define regk_iop_sap_out_spu1_gio15               0x00000007
-#define regk_iop_sap_out_spu1_gio2                0x00000005
-#define regk_iop_sap_out_spu1_gio3                0x00000006
-#define regk_iop_sap_out_spu1_gio4                0x00000005
-#define regk_iop_sap_out_spu1_gio5                0x00000006
-#define regk_iop_sap_out_spu1_gio6                0x00000005
-#define regk_iop_sap_out_spu1_gio7                0x00000006
-#define regk_iop_sap_out_timer_grp0_tmr2          0x00000004
-#define regk_iop_sap_out_timer_grp1_tmr2          0x00000005
-#define regk_iop_sap_out_timer_grp2_tmr2          0x00000006
-#define regk_iop_sap_out_timer_grp3_tmr2          0x00000007
-#define regk_iop_sap_out_tmr                      0x00000005
-#define regk_iop_sap_out_yes                      0x00000001
-#endif /* __iop_sap_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h
deleted file mode 100644
index 2cf5721597fc..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h
+++ /dev/null
@@ -1,111 +0,0 @@
-#ifndef __iop_scrc_in_defs_asm_h
-#define __iop_scrc_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_scrc_in.r
- *     id:           iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r
- *      id: $Id: iop_scrc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_cfg___trig___lsb 0
-#define reg_iop_scrc_in_rw_cfg___trig___width 2
-#define reg_iop_scrc_in_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_ctrl___dif_in_en___lsb 0
-#define reg_iop_scrc_in_rw_ctrl___dif_in_en___width 1
-#define reg_iop_scrc_in_rw_ctrl___dif_in_en___bit 0
-#define reg_iop_scrc_in_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_scrc_in, type r */
-#define reg_iop_scrc_in_r_stat___err___lsb 0
-#define reg_iop_scrc_in_r_stat___err___width 1
-#define reg_iop_scrc_in_r_stat___err___bit 0
-#define reg_iop_scrc_in_r_stat_offset 8
-
-/* Register rw_init_crc, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_init_crc_offset 12
-
-/* Register rs_computed_crc, scope iop_scrc_in, type rs */
-#define reg_iop_scrc_in_rs_computed_crc_offset 16
-
-/* Register r_computed_crc, scope iop_scrc_in, type r */
-#define reg_iop_scrc_in_r_computed_crc_offset 20
-
-/* Register rw_crc, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_crc_offset 24
-
-/* Register rw_correct_crc, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_correct_crc_offset 28
-
-/* Register rw_wr1bit, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_wr1bit___data___lsb 0
-#define reg_iop_scrc_in_rw_wr1bit___data___width 2
-#define reg_iop_scrc_in_rw_wr1bit___last___lsb 2
-#define reg_iop_scrc_in_rw_wr1bit___last___width 2
-#define reg_iop_scrc_in_rw_wr1bit_offset 32
-
-
-/* Constants */
-#define regk_iop_scrc_in_dif_in                   0x00000002
-#define regk_iop_scrc_in_hi                       0x00000000
-#define regk_iop_scrc_in_neg                      0x00000002
-#define regk_iop_scrc_in_no                       0x00000000
-#define regk_iop_scrc_in_pos                      0x00000001
-#define regk_iop_scrc_in_pos_neg                  0x00000003
-#define regk_iop_scrc_in_r_computed_crc_default   0x00000000
-#define regk_iop_scrc_in_rs_computed_crc_default  0x00000000
-#define regk_iop_scrc_in_rw_cfg_default           0x00000000
-#define regk_iop_scrc_in_rw_ctrl_default          0x00000000
-#define regk_iop_scrc_in_rw_init_crc_default      0x00000000
-#define regk_iop_scrc_in_set0                     0x00000000
-#define regk_iop_scrc_in_set1                     0x00000001
-#define regk_iop_scrc_in_yes                      0x00000001
-#endif /* __iop_scrc_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h
deleted file mode 100644
index 640a25725f20..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h
+++ /dev/null
@@ -1,105 +0,0 @@
-#ifndef __iop_scrc_out_defs_asm_h
-#define __iop_scrc_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_scrc_out.r
- *     id:           iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_out_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_out.r
- *      id: $Id: iop_scrc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_cfg___trig___lsb 0
-#define reg_iop_scrc_out_rw_cfg___trig___width 2
-#define reg_iop_scrc_out_rw_cfg___inv_crc___lsb 2
-#define reg_iop_scrc_out_rw_cfg___inv_crc___width 1
-#define reg_iop_scrc_out_rw_cfg___inv_crc___bit 2
-#define reg_iop_scrc_out_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_ctrl___strb_src___lsb 0
-#define reg_iop_scrc_out_rw_ctrl___strb_src___width 1
-#define reg_iop_scrc_out_rw_ctrl___strb_src___bit 0
-#define reg_iop_scrc_out_rw_ctrl___out_src___lsb 1
-#define reg_iop_scrc_out_rw_ctrl___out_src___width 1
-#define reg_iop_scrc_out_rw_ctrl___out_src___bit 1
-#define reg_iop_scrc_out_rw_ctrl_offset 4
-
-/* Register rw_init_crc, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_init_crc_offset 8
-
-/* Register rw_crc, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_crc_offset 12
-
-/* Register rw_data, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_data___val___lsb 0
-#define reg_iop_scrc_out_rw_data___val___width 1
-#define reg_iop_scrc_out_rw_data___val___bit 0
-#define reg_iop_scrc_out_rw_data_offset 16
-
-/* Register r_computed_crc, scope iop_scrc_out, type r */
-#define reg_iop_scrc_out_r_computed_crc_offset 20
-
-
-/* Constants */
-#define regk_iop_scrc_out_crc                     0x00000001
-#define regk_iop_scrc_out_data                    0x00000000
-#define regk_iop_scrc_out_dif                     0x00000001
-#define regk_iop_scrc_out_hi                      0x00000000
-#define regk_iop_scrc_out_neg                     0x00000002
-#define regk_iop_scrc_out_no                      0x00000000
-#define regk_iop_scrc_out_pos                     0x00000001
-#define regk_iop_scrc_out_pos_neg                 0x00000003
-#define regk_iop_scrc_out_reg                     0x00000000
-#define regk_iop_scrc_out_rw_cfg_default          0x00000000
-#define regk_iop_scrc_out_rw_crc_default          0x00000000
-#define regk_iop_scrc_out_rw_ctrl_default         0x00000000
-#define regk_iop_scrc_out_rw_data_default         0x00000000
-#define regk_iop_scrc_out_rw_init_crc_default     0x00000000
-#define regk_iop_scrc_out_yes                     0x00000001
-#endif /* __iop_scrc_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h
deleted file mode 100644
index bb402c1aa761..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h
+++ /dev/null
@@ -1,573 +0,0 @@
-#ifndef __iop_spu_defs_asm_h
-#define __iop_spu_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_spu.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r
- *      id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_iop_spu_rw_r 4
-/* Register rw_r, scope iop_spu, type rw */
-#define reg_iop_spu_rw_r_offset 0
-
-/* Register rw_seq_pc, scope iop_spu, type rw */
-#define reg_iop_spu_rw_seq_pc___addr___lsb 0
-#define reg_iop_spu_rw_seq_pc___addr___width 12
-#define reg_iop_spu_rw_seq_pc_offset 64
-
-/* Register rw_fsm_pc, scope iop_spu, type rw */
-#define reg_iop_spu_rw_fsm_pc___addr___lsb 0
-#define reg_iop_spu_rw_fsm_pc___addr___width 12
-#define reg_iop_spu_rw_fsm_pc_offset 68
-
-/* Register rw_ctrl, scope iop_spu, type rw */
-#define reg_iop_spu_rw_ctrl___fsm___lsb 0
-#define reg_iop_spu_rw_ctrl___fsm___width 1
-#define reg_iop_spu_rw_ctrl___fsm___bit 0
-#define reg_iop_spu_rw_ctrl___en___lsb 1
-#define reg_iop_spu_rw_ctrl___en___width 1
-#define reg_iop_spu_rw_ctrl___en___bit 1
-#define reg_iop_spu_rw_ctrl_offset 72
-
-/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
-#define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0
-#define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3
-#define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8
-#define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13
-#define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3
-#define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16
-#define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21
-#define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3
-#define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24
-#define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29
-#define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3
-#define reg_iop_spu_rw_fsm_inputs3_0_offset 76
-
-/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
-#define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0
-#define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3
-#define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8
-#define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13
-#define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3
-#define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16
-#define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21
-#define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3
-#define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24
-#define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29
-#define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3
-#define reg_iop_spu_rw_fsm_inputs7_4_offset 80
-
-/* Register rw_gio_out, scope iop_spu, type rw */
-#define reg_iop_spu_rw_gio_out_offset 84
-
-/* Register rw_bus0_out, scope iop_spu, type rw */
-#define reg_iop_spu_rw_bus0_out_offset 88
-
-/* Register rw_bus1_out, scope iop_spu, type rw */
-#define reg_iop_spu_rw_bus1_out_offset 92
-
-/* Register r_gio_in, scope iop_spu, type r */
-#define reg_iop_spu_r_gio_in_offset 96
-
-/* Register r_bus0_in, scope iop_spu, type r */
-#define reg_iop_spu_r_bus0_in_offset 100
-
-/* Register r_bus1_in, scope iop_spu, type r */
-#define reg_iop_spu_r_bus1_in_offset 104
-
-/* Register rw_gio_out_set, scope iop_spu, type rw */
-#define reg_iop_spu_rw_gio_out_set_offset 108
-
-/* Register rw_gio_out_clr, scope iop_spu, type rw */
-#define reg_iop_spu_rw_gio_out_clr_offset 112
-
-/* Register rs_wr_stat, scope iop_spu, type rs */
-#define reg_iop_spu_rs_wr_stat___r0___lsb 0
-#define reg_iop_spu_rs_wr_stat___r0___width 1
-#define reg_iop_spu_rs_wr_stat___r0___bit 0
-#define reg_iop_spu_rs_wr_stat___r1___lsb 1
-#define reg_iop_spu_rs_wr_stat___r1___width 1
-#define reg_iop_spu_rs_wr_stat___r1___bit 1
-#define reg_iop_spu_rs_wr_stat___r2___lsb 2
-#define reg_iop_spu_rs_wr_stat___r2___width 1
-#define reg_iop_spu_rs_wr_stat___r2___bit 2
-#define reg_iop_spu_rs_wr_stat___r3___lsb 3
-#define reg_iop_spu_rs_wr_stat___r3___width 1
-#define reg_iop_spu_rs_wr_stat___r3___bit 3
-#define reg_iop_spu_rs_wr_stat___r4___lsb 4
-#define reg_iop_spu_rs_wr_stat___r4___width 1
-#define reg_iop_spu_rs_wr_stat___r4___bit 4
-#define reg_iop_spu_rs_wr_stat___r5___lsb 5
-#define reg_iop_spu_rs_wr_stat___r5___width 1
-#define reg_iop_spu_rs_wr_stat___r5___bit 5
-#define reg_iop_spu_rs_wr_stat___r6___lsb 6
-#define reg_iop_spu_rs_wr_stat___r6___width 1
-#define reg_iop_spu_rs_wr_stat___r6___bit 6
-#define reg_iop_spu_rs_wr_stat___r7___lsb 7
-#define reg_iop_spu_rs_wr_stat___r7___width 1
-#define reg_iop_spu_rs_wr_stat___r7___bit 7
-#define reg_iop_spu_rs_wr_stat___r8___lsb 8
-#define reg_iop_spu_rs_wr_stat___r8___width 1
-#define reg_iop_spu_rs_wr_stat___r8___bit 8
-#define reg_iop_spu_rs_wr_stat___r9___lsb 9
-#define reg_iop_spu_rs_wr_stat___r9___width 1
-#define reg_iop_spu_rs_wr_stat___r9___bit 9
-#define reg_iop_spu_rs_wr_stat___r10___lsb 10
-#define reg_iop_spu_rs_wr_stat___r10___width 1
-#define reg_iop_spu_rs_wr_stat___r10___bit 10
-#define reg_iop_spu_rs_wr_stat___r11___lsb 11
-#define reg_iop_spu_rs_wr_stat___r11___width 1
-#define reg_iop_spu_rs_wr_stat___r11___bit 11
-#define reg_iop_spu_rs_wr_stat___r12___lsb 12
-#define reg_iop_spu_rs_wr_stat___r12___width 1
-#define reg_iop_spu_rs_wr_stat___r12___bit 12
-#define reg_iop_spu_rs_wr_stat___r13___lsb 13
-#define reg_iop_spu_rs_wr_stat___r13___width 1
-#define reg_iop_spu_rs_wr_stat___r13___bit 13
-#define reg_iop_spu_rs_wr_stat___r14___lsb 14
-#define reg_iop_spu_rs_wr_stat___r14___width 1
-#define reg_iop_spu_rs_wr_stat___r14___bit 14
-#define reg_iop_spu_rs_wr_stat___r15___lsb 15
-#define reg_iop_spu_rs_wr_stat___r15___width 1
-#define reg_iop_spu_rs_wr_stat___r15___bit 15
-#define reg_iop_spu_rs_wr_stat_offset 116
-
-/* Register r_wr_stat, scope iop_spu, type r */
-#define reg_iop_spu_r_wr_stat___r0___lsb 0
-#define reg_iop_spu_r_wr_stat___r0___width 1
-#define reg_iop_spu_r_wr_stat___r0___bit 0
-#define reg_iop_spu_r_wr_stat___r1___lsb 1
-#define reg_iop_spu_r_wr_stat___r1___width 1
-#define reg_iop_spu_r_wr_stat___r1___bit 1
-#define reg_iop_spu_r_wr_stat___r2___lsb 2
-#define reg_iop_spu_r_wr_stat___r2___width 1
-#define reg_iop_spu_r_wr_stat___r2___bit 2
-#define reg_iop_spu_r_wr_stat___r3___lsb 3
-#define reg_iop_spu_r_wr_stat___r3___width 1
-#define reg_iop_spu_r_wr_stat___r3___bit 3
-#define reg_iop_spu_r_wr_stat___r4___lsb 4
-#define reg_iop_spu_r_wr_stat___r4___width 1
-#define reg_iop_spu_r_wr_stat___r4___bit 4
-#define reg_iop_spu_r_wr_stat___r5___lsb 5
-#define reg_iop_spu_r_wr_stat___r5___width 1
-#define reg_iop_spu_r_wr_stat___r5___bit 5
-#define reg_iop_spu_r_wr_stat___r6___lsb 6
-#define reg_iop_spu_r_wr_stat___r6___width 1
-#define reg_iop_spu_r_wr_stat___r6___bit 6
-#define reg_iop_spu_r_wr_stat___r7___lsb 7
-#define reg_iop_spu_r_wr_stat___r7___width 1
-#define reg_iop_spu_r_wr_stat___r7___bit 7
-#define reg_iop_spu_r_wr_stat___r8___lsb 8
-#define reg_iop_spu_r_wr_stat___r8___width 1
-#define reg_iop_spu_r_wr_stat___r8___bit 8
-#define reg_iop_spu_r_wr_stat___r9___lsb 9
-#define reg_iop_spu_r_wr_stat___r9___width 1
-#define reg_iop_spu_r_wr_stat___r9___bit 9
-#define reg_iop_spu_r_wr_stat___r10___lsb 10
-#define reg_iop_spu_r_wr_stat___r10___width 1
-#define reg_iop_spu_r_wr_stat___r10___bit 10
-#define reg_iop_spu_r_wr_stat___r11___lsb 11
-#define reg_iop_spu_r_wr_stat___r11___width 1
-#define reg_iop_spu_r_wr_stat___r11___bit 11
-#define reg_iop_spu_r_wr_stat___r12___lsb 12
-#define reg_iop_spu_r_wr_stat___r12___width 1
-#define reg_iop_spu_r_wr_stat___r12___bit 12
-#define reg_iop_spu_r_wr_stat___r13___lsb 13
-#define reg_iop_spu_r_wr_stat___r13___width 1
-#define reg_iop_spu_r_wr_stat___r13___bit 13
-#define reg_iop_spu_r_wr_stat___r14___lsb 14
-#define reg_iop_spu_r_wr_stat___r14___width 1
-#define reg_iop_spu_r_wr_stat___r14___bit 14
-#define reg_iop_spu_r_wr_stat___r15___lsb 15
-#define reg_iop_spu_r_wr_stat___r15___width 1
-#define reg_iop_spu_r_wr_stat___r15___bit 15
-#define reg_iop_spu_r_wr_stat_offset 120
-
-/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */
-#define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124
-
-/* Register r_stat_in, scope iop_spu, type r */
-#define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0
-#define reg_iop_spu_r_stat_in___timer_grp_lo___width 4
-#define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4
-#define reg_iop_spu_r_stat_in___fifo_out_last___width 1
-#define reg_iop_spu_r_stat_in___fifo_out_last___bit 4
-#define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5
-#define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1
-#define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5
-#define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6
-#define reg_iop_spu_r_stat_in___fifo_out_all___width 1
-#define reg_iop_spu_r_stat_in___fifo_out_all___bit 6
-#define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7
-#define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1
-#define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7
-#define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8
-#define reg_iop_spu_r_stat_in___dmc_out_all___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_all___bit 8
-#define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9
-#define reg_iop_spu_r_stat_in___dmc_out_dth___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9
-#define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10
-#define reg_iop_spu_r_stat_in___dmc_out_eop___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10
-#define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11
-#define reg_iop_spu_r_stat_in___dmc_out_dv___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11
-#define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12
-#define reg_iop_spu_r_stat_in___dmc_out_last___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_last___bit 12
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14
-#define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15
-#define reg_iop_spu_r_stat_in___pcrc_correct___width 1
-#define reg_iop_spu_r_stat_in___pcrc_correct___bit 15
-#define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16
-#define reg_iop_spu_r_stat_in___timer_grp_hi___width 4
-#define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20
-#define reg_iop_spu_r_stat_in___dmc_in_sth___width 1
-#define reg_iop_spu_r_stat_in___dmc_in_sth___bit 20
-#define reg_iop_spu_r_stat_in___dmc_in_full___lsb 21
-#define reg_iop_spu_r_stat_in___dmc_in_full___width 1
-#define reg_iop_spu_r_stat_in___dmc_in_full___bit 21
-#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___lsb 22
-#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___width 1
-#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___bit 22
-#define reg_iop_spu_r_stat_in___spu_gio_out___lsb 23
-#define reg_iop_spu_r_stat_in___spu_gio_out___width 4
-#define reg_iop_spu_r_stat_in___sync_clk12___lsb 27
-#define reg_iop_spu_r_stat_in___sync_clk12___width 1
-#define reg_iop_spu_r_stat_in___sync_clk12___bit 27
-#define reg_iop_spu_r_stat_in___scrc_out_data___lsb 28
-#define reg_iop_spu_r_stat_in___scrc_out_data___width 1
-#define reg_iop_spu_r_stat_in___scrc_out_data___bit 28
-#define reg_iop_spu_r_stat_in___scrc_in_err___lsb 29
-#define reg_iop_spu_r_stat_in___scrc_in_err___width 1
-#define reg_iop_spu_r_stat_in___scrc_in_err___bit 29
-#define reg_iop_spu_r_stat_in___mc_busy___lsb 30
-#define reg_iop_spu_r_stat_in___mc_busy___width 1
-#define reg_iop_spu_r_stat_in___mc_busy___bit 30
-#define reg_iop_spu_r_stat_in___mc_owned___lsb 31
-#define reg_iop_spu_r_stat_in___mc_owned___width 1
-#define reg_iop_spu_r_stat_in___mc_owned___bit 31
-#define reg_iop_spu_r_stat_in_offset 128
-
-/* Register r_trigger_in, scope iop_spu, type r */
-#define reg_iop_spu_r_trigger_in_offset 132
-
-/* Register r_special_stat, scope iop_spu, type r */
-#define reg_iop_spu_r_special_stat___c_flag___lsb 0
-#define reg_iop_spu_r_special_stat___c_flag___width 1
-#define reg_iop_spu_r_special_stat___c_flag___bit 0
-#define reg_iop_spu_r_special_stat___v_flag___lsb 1
-#define reg_iop_spu_r_special_stat___v_flag___width 1
-#define reg_iop_spu_r_special_stat___v_flag___bit 1
-#define reg_iop_spu_r_special_stat___z_flag___lsb 2
-#define reg_iop_spu_r_special_stat___z_flag___width 1
-#define reg_iop_spu_r_special_stat___z_flag___bit 2
-#define reg_iop_spu_r_special_stat___n_flag___lsb 3
-#define reg_iop_spu_r_special_stat___n_flag___width 1
-#define reg_iop_spu_r_special_stat___n_flag___bit 3
-#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___lsb 4
-#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___width 1
-#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___bit 4
-#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___lsb 5
-#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___width 1
-#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___bit 5
-#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___lsb 6
-#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___width 1
-#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___bit 6
-#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___lsb 7
-#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___width 1
-#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___bit 7
-#define reg_iop_spu_r_special_stat___fsm_in0___lsb 8
-#define reg_iop_spu_r_special_stat___fsm_in0___width 1
-#define reg_iop_spu_r_special_stat___fsm_in0___bit 8
-#define reg_iop_spu_r_special_stat___fsm_in1___lsb 9
-#define reg_iop_spu_r_special_stat___fsm_in1___width 1
-#define reg_iop_spu_r_special_stat___fsm_in1___bit 9
-#define reg_iop_spu_r_special_stat___fsm_in2___lsb 10
-#define reg_iop_spu_r_special_stat___fsm_in2___width 1
-#define reg_iop_spu_r_special_stat___fsm_in2___bit 10
-#define reg_iop_spu_r_special_stat___fsm_in3___lsb 11
-#define reg_iop_spu_r_special_stat___fsm_in3___width 1
-#define reg_iop_spu_r_special_stat___fsm_in3___bit 11
-#define reg_iop_spu_r_special_stat___fsm_in4___lsb 12
-#define reg_iop_spu_r_special_stat___fsm_in4___width 1
-#define reg_iop_spu_r_special_stat___fsm_in4___bit 12
-#define reg_iop_spu_r_special_stat___fsm_in5___lsb 13
-#define reg_iop_spu_r_special_stat___fsm_in5___width 1
-#define reg_iop_spu_r_special_stat___fsm_in5___bit 13
-#define reg_iop_spu_r_special_stat___fsm_in6___lsb 14
-#define reg_iop_spu_r_special_stat___fsm_in6___width 1
-#define reg_iop_spu_r_special_stat___fsm_in6___bit 14
-#define reg_iop_spu_r_special_stat___fsm_in7___lsb 15
-#define reg_iop_spu_r_special_stat___fsm_in7___width 1
-#define reg_iop_spu_r_special_stat___fsm_in7___bit 15
-#define reg_iop_spu_r_special_stat___event0___lsb 16
-#define reg_iop_spu_r_special_stat___event0___width 1
-#define reg_iop_spu_r_special_stat___event0___bit 16
-#define reg_iop_spu_r_special_stat___event1___lsb 17
-#define reg_iop_spu_r_special_stat___event1___width 1
-#define reg_iop_spu_r_special_stat___event1___bit 17
-#define reg_iop_spu_r_special_stat___event2___lsb 18
-#define reg_iop_spu_r_special_stat___event2___width 1
-#define reg_iop_spu_r_special_stat___event2___bit 18
-#define reg_iop_spu_r_special_stat___event3___lsb 19
-#define reg_iop_spu_r_special_stat___event3___width 1
-#define reg_iop_spu_r_special_stat___event3___bit 19
-#define reg_iop_spu_r_special_stat_offset 136
-
-/* Register rw_reg_access, scope iop_spu, type rw */
-#define reg_iop_spu_rw_reg_access___addr___lsb 0
-#define reg_iop_spu_rw_reg_access___addr___width 13
-#define reg_iop_spu_rw_reg_access___imm_hi___lsb 16
-#define reg_iop_spu_rw_reg_access___imm_hi___width 16
-#define reg_iop_spu_rw_reg_access_offset 140
-
-#define STRIDE_iop_spu_rw_event_cfg 4
-/* Register rw_event_cfg, scope iop_spu, type rw */
-#define reg_iop_spu_rw_event_cfg___addr___lsb 0
-#define reg_iop_spu_rw_event_cfg___addr___width 12
-#define reg_iop_spu_rw_event_cfg___src___lsb 12
-#define reg_iop_spu_rw_event_cfg___src___width 2
-#define reg_iop_spu_rw_event_cfg___eq_en___lsb 14
-#define reg_iop_spu_rw_event_cfg___eq_en___width 1
-#define reg_iop_spu_rw_event_cfg___eq_en___bit 14
-#define reg_iop_spu_rw_event_cfg___eq_inv___lsb 15
-#define reg_iop_spu_rw_event_cfg___eq_inv___width 1
-#define reg_iop_spu_rw_event_cfg___eq_inv___bit 15
-#define reg_iop_spu_rw_event_cfg___gt_en___lsb 16
-#define reg_iop_spu_rw_event_cfg___gt_en___width 1
-#define reg_iop_spu_rw_event_cfg___gt_en___bit 16
-#define reg_iop_spu_rw_event_cfg___gt_inv___lsb 17
-#define reg_iop_spu_rw_event_cfg___gt_inv___width 1
-#define reg_iop_spu_rw_event_cfg___gt_inv___bit 17
-#define reg_iop_spu_rw_event_cfg_offset 144
-
-#define STRIDE_iop_spu_rw_event_mask 4
-/* Register rw_event_mask, scope iop_spu, type rw */
-#define reg_iop_spu_rw_event_mask_offset 160
-
-#define STRIDE_iop_spu_rw_event_val 4
-/* Register rw_event_val, scope iop_spu, type rw */
-#define reg_iop_spu_rw_event_val_offset 176
-
-/* Register rw_event_ret, scope iop_spu, type rw */
-#define reg_iop_spu_rw_event_ret___addr___lsb 0
-#define reg_iop_spu_rw_event_ret___addr___width 12
-#define reg_iop_spu_rw_event_ret_offset 192
-
-/* Register r_trace, scope iop_spu, type r */
-#define reg_iop_spu_r_trace___fsm___lsb 0
-#define reg_iop_spu_r_trace___fsm___width 1
-#define reg_iop_spu_r_trace___fsm___bit 0
-#define reg_iop_spu_r_trace___en___lsb 1
-#define reg_iop_spu_r_trace___en___width 1
-#define reg_iop_spu_r_trace___en___bit 1
-#define reg_iop_spu_r_trace___c_flag___lsb 2
-#define reg_iop_spu_r_trace___c_flag___width 1
-#define reg_iop_spu_r_trace___c_flag___bit 2
-#define reg_iop_spu_r_trace___v_flag___lsb 3
-#define reg_iop_spu_r_trace___v_flag___width 1
-#define reg_iop_spu_r_trace___v_flag___bit 3
-#define reg_iop_spu_r_trace___z_flag___lsb 4
-#define reg_iop_spu_r_trace___z_flag___width 1
-#define reg_iop_spu_r_trace___z_flag___bit 4
-#define reg_iop_spu_r_trace___n_flag___lsb 5
-#define reg_iop_spu_r_trace___n_flag___width 1
-#define reg_iop_spu_r_trace___n_flag___bit 5
-#define reg_iop_spu_r_trace___seq_addr___lsb 6
-#define reg_iop_spu_r_trace___seq_addr___width 12
-#define reg_iop_spu_r_trace___fsm_addr___lsb 20
-#define reg_iop_spu_r_trace___fsm_addr___width 12
-#define reg_iop_spu_r_trace_offset 196
-
-/* Register r_fsm_trace, scope iop_spu, type r */
-#define reg_iop_spu_r_fsm_trace___fsm___lsb 0
-#define reg_iop_spu_r_fsm_trace___fsm___width 1
-#define reg_iop_spu_r_fsm_trace___fsm___bit 0
-#define reg_iop_spu_r_fsm_trace___en___lsb 1
-#define reg_iop_spu_r_fsm_trace___en___width 1
-#define reg_iop_spu_r_fsm_trace___en___bit 1
-#define reg_iop_spu_r_fsm_trace___tmr_done___lsb 2
-#define reg_iop_spu_r_fsm_trace___tmr_done___width 1
-#define reg_iop_spu_r_fsm_trace___tmr_done___bit 2
-#define reg_iop_spu_r_fsm_trace___inp0___lsb 3
-#define reg_iop_spu_r_fsm_trace___inp0___width 1
-#define reg_iop_spu_r_fsm_trace___inp0___bit 3
-#define reg_iop_spu_r_fsm_trace___inp1___lsb 4
-#define reg_iop_spu_r_fsm_trace___inp1___width 1
-#define reg_iop_spu_r_fsm_trace___inp1___bit 4
-#define reg_iop_spu_r_fsm_trace___inp2___lsb 5
-#define reg_iop_spu_r_fsm_trace___inp2___width 1
-#define reg_iop_spu_r_fsm_trace___inp2___bit 5
-#define reg_iop_spu_r_fsm_trace___inp3___lsb 6
-#define reg_iop_spu_r_fsm_trace___inp3___width 1
-#define reg_iop_spu_r_fsm_trace___inp3___bit 6
-#define reg_iop_spu_r_fsm_trace___event0___lsb 7
-#define reg_iop_spu_r_fsm_trace___event0___width 1
-#define reg_iop_spu_r_fsm_trace___event0___bit 7
-#define reg_iop_spu_r_fsm_trace___event1___lsb 8
-#define reg_iop_spu_r_fsm_trace___event1___width 1
-#define reg_iop_spu_r_fsm_trace___event1___bit 8
-#define reg_iop_spu_r_fsm_trace___event2___lsb 9
-#define reg_iop_spu_r_fsm_trace___event2___width 1
-#define reg_iop_spu_r_fsm_trace___event2___bit 9
-#define reg_iop_spu_r_fsm_trace___event3___lsb 10
-#define reg_iop_spu_r_fsm_trace___event3___width 1
-#define reg_iop_spu_r_fsm_trace___event3___bit 10
-#define reg_iop_spu_r_fsm_trace___gio_out___lsb 11
-#define reg_iop_spu_r_fsm_trace___gio_out___width 8
-#define reg_iop_spu_r_fsm_trace___fsm_addr___lsb 20
-#define reg_iop_spu_r_fsm_trace___fsm_addr___width 12
-#define reg_iop_spu_r_fsm_trace_offset 200
-
-#define STRIDE_iop_spu_rw_brp 4
-/* Register rw_brp, scope iop_spu, type rw */
-#define reg_iop_spu_rw_brp___addr___lsb 0
-#define reg_iop_spu_rw_brp___addr___width 12
-#define reg_iop_spu_rw_brp___fsm___lsb 12
-#define reg_iop_spu_rw_brp___fsm___width 1
-#define reg_iop_spu_rw_brp___fsm___bit 12
-#define reg_iop_spu_rw_brp___en___lsb 13
-#define reg_iop_spu_rw_brp___en___width 1
-#define reg_iop_spu_rw_brp___en___bit 13
-#define reg_iop_spu_rw_brp_offset 204
-
-
-/* Constants */
-#define regk_iop_spu_attn_hi                      0x00000005
-#define regk_iop_spu_attn_lo                      0x00000005
-#define regk_iop_spu_attn_r0                      0x00000000
-#define regk_iop_spu_attn_r1                      0x00000001
-#define regk_iop_spu_attn_r10                     0x00000002
-#define regk_iop_spu_attn_r11                     0x00000003
-#define regk_iop_spu_attn_r12                     0x00000004
-#define regk_iop_spu_attn_r13                     0x00000005
-#define regk_iop_spu_attn_r14                     0x00000006
-#define regk_iop_spu_attn_r15                     0x00000007
-#define regk_iop_spu_attn_r2                      0x00000002
-#define regk_iop_spu_attn_r3                      0x00000003
-#define regk_iop_spu_attn_r4                      0x00000004
-#define regk_iop_spu_attn_r5                      0x00000005
-#define regk_iop_spu_attn_r6                      0x00000006
-#define regk_iop_spu_attn_r7                      0x00000007
-#define regk_iop_spu_attn_r8                      0x00000000
-#define regk_iop_spu_attn_r9                      0x00000001
-#define regk_iop_spu_c                            0x00000000
-#define regk_iop_spu_flag                         0x00000002
-#define regk_iop_spu_gio_in                       0x00000000
-#define regk_iop_spu_gio_out                      0x00000005
-#define regk_iop_spu_gio_out0                     0x00000008
-#define regk_iop_spu_gio_out1                     0x00000009
-#define regk_iop_spu_gio_out2                     0x0000000a
-#define regk_iop_spu_gio_out3                     0x0000000b
-#define regk_iop_spu_gio_out4                     0x0000000c
-#define regk_iop_spu_gio_out5                     0x0000000d
-#define regk_iop_spu_gio_out6                     0x0000000e
-#define regk_iop_spu_gio_out7                     0x0000000f
-#define regk_iop_spu_n                            0x00000003
-#define regk_iop_spu_no                           0x00000000
-#define regk_iop_spu_r0                           0x00000008
-#define regk_iop_spu_r1                           0x00000009
-#define regk_iop_spu_r10                          0x0000000a
-#define regk_iop_spu_r11                          0x0000000b
-#define regk_iop_spu_r12                          0x0000000c
-#define regk_iop_spu_r13                          0x0000000d
-#define regk_iop_spu_r14                          0x0000000e
-#define regk_iop_spu_r15                          0x0000000f
-#define regk_iop_spu_r2                           0x0000000a
-#define regk_iop_spu_r3                           0x0000000b
-#define regk_iop_spu_r4                           0x0000000c
-#define regk_iop_spu_r5                           0x0000000d
-#define regk_iop_spu_r6                           0x0000000e
-#define regk_iop_spu_r7                           0x0000000f
-#define regk_iop_spu_r8                           0x00000008
-#define regk_iop_spu_r9                           0x00000009
-#define regk_iop_spu_reg_hi                       0x00000002
-#define regk_iop_spu_reg_lo                       0x00000002
-#define regk_iop_spu_rw_brp_default               0x00000000
-#define regk_iop_spu_rw_brp_size                  0x00000004
-#define regk_iop_spu_rw_ctrl_default              0x00000000
-#define regk_iop_spu_rw_event_cfg_size            0x00000004
-#define regk_iop_spu_rw_event_mask_size           0x00000004
-#define regk_iop_spu_rw_event_val_size            0x00000004
-#define regk_iop_spu_rw_gio_out_default           0x00000000
-#define regk_iop_spu_rw_r_size                    0x00000010
-#define regk_iop_spu_rw_reg_access_default        0x00000000
-#define regk_iop_spu_stat_in                      0x00000002
-#define regk_iop_spu_statin_hi                    0x00000004
-#define regk_iop_spu_statin_lo                    0x00000004
-#define regk_iop_spu_trig                         0x00000003
-#define regk_iop_spu_trigger                      0x00000006
-#define regk_iop_spu_v                            0x00000001
-#define regk_iop_spu_wsts_gioout_spec             0x00000001
-#define regk_iop_spu_xor                          0x00000003
-#define regk_iop_spu_xor_bus0_r2_0                0x00000000
-#define regk_iop_spu_xor_bus0m_r2_0               0x00000002
-#define regk_iop_spu_xor_bus1_r3_0                0x00000001
-#define regk_iop_spu_xor_bus1m_r3_0               0x00000003
-#define regk_iop_spu_yes                          0x00000001
-#define regk_iop_spu_z                            0x00000002
-#endif /* __iop_spu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
deleted file mode 100644
index 3be60f9b024c..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
+++ /dev/null
@@ -1,1052 +0,0 @@
-#ifndef __iop_sw_cfg_defs_asm_h
-#define __iop_sw_cfg_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:19 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
- *      id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0
-
-/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4
-
-/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8
-
-/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12
-
-/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16
-
-/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20
-
-/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24
-
-/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28
-
-/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32
-
-/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36
-
-/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40
-
-/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44
-
-/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48
-
-/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52
-
-/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_sap_in_owner_offset 56
-
-/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_sap_out_owner_offset 60
-
-/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64
-
-/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68
-
-/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72
-
-/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76
-
-/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_spu0_owner_offset 80
-
-/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_spu1_owner_offset 84
-
-/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88
-
-/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92
-
-/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96
-
-/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100
-
-/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104
-
-/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108
-
-/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112
-
-/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116
-
-/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120
-
-/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124
-
-/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128
-
-/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132
-
-/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8
-#define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8
-#define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8
-#define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16
-#define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8
-#define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24
-#define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8
-#define reg_iop_sw_cfg_rw_bus0_mask_offset 136
-
-/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3
-#define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140
-
-/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8
-#define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8
-#define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8
-#define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16
-#define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8
-#define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24
-#define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8
-#define reg_iop_sw_cfg_rw_bus1_mask_offset 144
-
-/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3
-#define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148
-
-/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0
-#define reg_iop_sw_cfg_rw_gio_mask___val___width 32
-#define reg_iop_sw_cfg_rw_gio_mask_offset 152
-
-/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0
-#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32
-#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156
-
-/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16
-#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18
-#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20
-#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22
-#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24
-#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26
-#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28
-#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30
-#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2
-#define reg_iop_sw_cfg_rw_pinmapping_offset 160
-
-/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164
-
-/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168
-
-/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172
-
-/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176
-
-/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180
-
-/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184
-
-/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188
-
-/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192
-
-/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196
-
-/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0
-#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2
-#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2
-#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2
-#define reg_iop_sw_cfg_rw_spu0_cfg_offset 200
-
-/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0
-#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2
-#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2
-#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2
-#define reg_iop_sw_cfg_rw_spu1_cfg_offset 204
-
-/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208
-
-/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212
-
-/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216
-
-/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220
-
-/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224
-
-/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0
-#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1
-#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18
-#define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228
-
-/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0
-#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1
-#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18
-#define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232
-
-/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg_offset 236
-
-
-/* Constants */
-#define regk_iop_sw_cfg_a                         0x00000001
-#define regk_iop_sw_cfg_b                         0x00000002
-#define regk_iop_sw_cfg_bus0                      0x00000000
-#define regk_iop_sw_cfg_bus0_rot16                0x00000004
-#define regk_iop_sw_cfg_bus0_rot24                0x00000006
-#define regk_iop_sw_cfg_bus0_rot8                 0x00000002
-#define regk_iop_sw_cfg_bus1                      0x00000001
-#define regk_iop_sw_cfg_bus1_rot16                0x00000005
-#define regk_iop_sw_cfg_bus1_rot24                0x00000007
-#define regk_iop_sw_cfg_bus1_rot8                 0x00000003
-#define regk_iop_sw_cfg_clk12                     0x00000000
-#define regk_iop_sw_cfg_cpu                       0x00000000
-#define regk_iop_sw_cfg_dmc0                      0x00000000
-#define regk_iop_sw_cfg_dmc1                      0x00000001
-#define regk_iop_sw_cfg_gated_clk0                0x00000010
-#define regk_iop_sw_cfg_gated_clk1                0x00000011
-#define regk_iop_sw_cfg_gated_clk2                0x00000012
-#define regk_iop_sw_cfg_gated_clk3                0x00000013
-#define regk_iop_sw_cfg_gio0                      0x00000004
-#define regk_iop_sw_cfg_gio1                      0x00000001
-#define regk_iop_sw_cfg_gio2                      0x00000005
-#define regk_iop_sw_cfg_gio3                      0x00000002
-#define regk_iop_sw_cfg_gio4                      0x00000006
-#define regk_iop_sw_cfg_gio5                      0x00000003
-#define regk_iop_sw_cfg_gio6                      0x00000007
-#define regk_iop_sw_cfg_gio7                      0x00000004
-#define regk_iop_sw_cfg_gio_in0                   0x00000000
-#define regk_iop_sw_cfg_gio_in1                   0x00000001
-#define regk_iop_sw_cfg_gio_in10                  0x00000002
-#define regk_iop_sw_cfg_gio_in11                  0x00000003
-#define regk_iop_sw_cfg_gio_in14                  0x00000004
-#define regk_iop_sw_cfg_gio_in15                  0x00000005
-#define regk_iop_sw_cfg_gio_in18                  0x00000002
-#define regk_iop_sw_cfg_gio_in19                  0x00000003
-#define regk_iop_sw_cfg_gio_in20                  0x00000004
-#define regk_iop_sw_cfg_gio_in21                  0x00000005
-#define regk_iop_sw_cfg_gio_in26                  0x00000006
-#define regk_iop_sw_cfg_gio_in27                  0x00000007
-#define regk_iop_sw_cfg_gio_in28                  0x00000006
-#define regk_iop_sw_cfg_gio_in29                  0x00000007
-#define regk_iop_sw_cfg_gio_in4                   0x00000000
-#define regk_iop_sw_cfg_gio_in5                   0x00000001
-#define regk_iop_sw_cfg_last_timer_grp0_tmr2      0x00000001
-#define regk_iop_sw_cfg_last_timer_grp1_tmr2      0x00000001
-#define regk_iop_sw_cfg_last_timer_grp2_tmr2      0x00000002
-#define regk_iop_sw_cfg_last_timer_grp2_tmr3      0x00000003
-#define regk_iop_sw_cfg_last_timer_grp3_tmr2      0x00000002
-#define regk_iop_sw_cfg_last_timer_grp3_tmr3      0x00000003
-#define regk_iop_sw_cfg_mpu                       0x00000001
-#define regk_iop_sw_cfg_none                      0x00000000
-#define regk_iop_sw_cfg_par0                      0x00000000
-#define regk_iop_sw_cfg_par1                      0x00000001
-#define regk_iop_sw_cfg_pdp_out0                  0x00000002
-#define regk_iop_sw_cfg_pdp_out0_hi               0x00000001
-#define regk_iop_sw_cfg_pdp_out0_hi_rot8          0x00000005
-#define regk_iop_sw_cfg_pdp_out0_lo               0x00000000
-#define regk_iop_sw_cfg_pdp_out0_lo_rot8          0x00000004
-#define regk_iop_sw_cfg_pdp_out1                  0x00000003
-#define regk_iop_sw_cfg_pdp_out1_hi               0x00000003
-#define regk_iop_sw_cfg_pdp_out1_hi_rot8          0x00000005
-#define regk_iop_sw_cfg_pdp_out1_lo               0x00000002
-#define regk_iop_sw_cfg_pdp_out1_lo_rot8          0x00000004
-#define regk_iop_sw_cfg_rw_bus0_mask_default      0x00000000
-#define regk_iop_sw_cfg_rw_bus0_oe_mask_default   0x00000000
-#define regk_iop_sw_cfg_rw_bus1_mask_default      0x00000000
-#define regk_iop_sw_cfg_rw_bus1_oe_mask_default   0x00000000
-#define regk_iop_sw_cfg_rw_bus_out_cfg_default    0x00000000
-#define regk_iop_sw_cfg_rw_crc_par0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_crc_par1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_dmc_in0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_dmc_in1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_dmc_out0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_dmc_out1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_mask_default       0x00000000
-#define regk_iop_sw_cfg_rw_gio_oe_mask_default    0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_pdp0_cfg_default       0x00000000
-#define regk_iop_sw_cfg_rw_pdp1_cfg_default       0x00000000
-#define regk_iop_sw_cfg_rw_pinmapping_default     0x55555555
-#define regk_iop_sw_cfg_rw_sap_in_owner_default   0x00000000
-#define regk_iop_sw_cfg_rw_sap_out_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_scrc_in0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_scrc_in1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_scrc_out0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_scrc_out1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_sdp_cfg_default        0x00000000
-#define regk_iop_sw_cfg_rw_spu0_cfg_default       0x00000000
-#define regk_iop_sw_cfg_rw_spu0_owner_default     0x00000000
-#define regk_iop_sw_cfg_rw_spu1_cfg_default       0x00000000
-#define regk_iop_sw_cfg_rw_spu1_owner_default     0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp2_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp2_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp3_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp3_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default  0x00000000
-#define regk_iop_sw_cfg_sdp_out0                  0x00000008
-#define regk_iop_sw_cfg_sdp_out1                  0x00000009
-#define regk_iop_sw_cfg_size16                    0x00000002
-#define regk_iop_sw_cfg_size24                    0x00000003
-#define regk_iop_sw_cfg_size32                    0x00000004
-#define regk_iop_sw_cfg_size8                     0x00000001
-#define regk_iop_sw_cfg_spu0                      0x00000002
-#define regk_iop_sw_cfg_spu0_bus_out0_hi          0x00000006
-#define regk_iop_sw_cfg_spu0_bus_out0_lo          0x00000006
-#define regk_iop_sw_cfg_spu0_bus_out1_hi          0x00000007
-#define regk_iop_sw_cfg_spu0_bus_out1_lo          0x00000007
-#define regk_iop_sw_cfg_spu0_g0                   0x0000000e
-#define regk_iop_sw_cfg_spu0_g1                   0x0000000e
-#define regk_iop_sw_cfg_spu0_g2                   0x0000000e
-#define regk_iop_sw_cfg_spu0_g3                   0x0000000e
-#define regk_iop_sw_cfg_spu0_g4                   0x0000000e
-#define regk_iop_sw_cfg_spu0_g5                   0x0000000e
-#define regk_iop_sw_cfg_spu0_g6                   0x0000000e
-#define regk_iop_sw_cfg_spu0_g7                   0x0000000e
-#define regk_iop_sw_cfg_spu0_gio0                 0x00000000
-#define regk_iop_sw_cfg_spu0_gio1                 0x00000001
-#define regk_iop_sw_cfg_spu0_gio2                 0x00000000
-#define regk_iop_sw_cfg_spu0_gio5                 0x00000005
-#define regk_iop_sw_cfg_spu0_gio6                 0x00000006
-#define regk_iop_sw_cfg_spu0_gio7                 0x00000007
-#define regk_iop_sw_cfg_spu0_gio_out0             0x00000008
-#define regk_iop_sw_cfg_spu0_gio_out1             0x00000009
-#define regk_iop_sw_cfg_spu0_gio_out2             0x0000000a
-#define regk_iop_sw_cfg_spu0_gio_out3             0x0000000b
-#define regk_iop_sw_cfg_spu0_gio_out4             0x0000000c
-#define regk_iop_sw_cfg_spu0_gio_out5             0x0000000d
-#define regk_iop_sw_cfg_spu0_gio_out6             0x0000000e
-#define regk_iop_sw_cfg_spu0_gio_out7             0x0000000f
-#define regk_iop_sw_cfg_spu0_gioout0              0x00000000
-#define regk_iop_sw_cfg_spu0_gioout1              0x00000000
-#define regk_iop_sw_cfg_spu0_gioout10             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout11             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout12             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout13             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout14             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout15             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout16             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout17             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout18             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout19             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout2              0x00000002
-#define regk_iop_sw_cfg_spu0_gioout20             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout21             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout22             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout23             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout24             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout25             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout26             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout27             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout28             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout29             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout3              0x00000002
-#define regk_iop_sw_cfg_spu0_gioout30             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout31             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout4              0x00000004
-#define regk_iop_sw_cfg_spu0_gioout5              0x00000004
-#define regk_iop_sw_cfg_spu0_gioout6              0x00000006
-#define regk_iop_sw_cfg_spu0_gioout7              0x00000006
-#define regk_iop_sw_cfg_spu0_gioout8              0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout9              0x0000000e
-#define regk_iop_sw_cfg_spu1                      0x00000003
-#define regk_iop_sw_cfg_spu1_bus_out0_hi          0x00000006
-#define regk_iop_sw_cfg_spu1_bus_out0_lo          0x00000006
-#define regk_iop_sw_cfg_spu1_bus_out1_hi          0x00000007
-#define regk_iop_sw_cfg_spu1_bus_out1_lo          0x00000007
-#define regk_iop_sw_cfg_spu1_g0                   0x0000000f
-#define regk_iop_sw_cfg_spu1_g1                   0x0000000f
-#define regk_iop_sw_cfg_spu1_g2                   0x0000000f
-#define regk_iop_sw_cfg_spu1_g3                   0x0000000f
-#define regk_iop_sw_cfg_spu1_g4                   0x0000000f
-#define regk_iop_sw_cfg_spu1_g5                   0x0000000f
-#define regk_iop_sw_cfg_spu1_g6                   0x0000000f
-#define regk_iop_sw_cfg_spu1_g7                   0x0000000f
-#define regk_iop_sw_cfg_spu1_gio0                 0x00000002
-#define regk_iop_sw_cfg_spu1_gio1                 0x00000003
-#define regk_iop_sw_cfg_spu1_gio2                 0x00000002
-#define regk_iop_sw_cfg_spu1_gio5                 0x00000005
-#define regk_iop_sw_cfg_spu1_gio6                 0x00000006
-#define regk_iop_sw_cfg_spu1_gio7                 0x00000007
-#define regk_iop_sw_cfg_spu1_gio_out0             0x00000008
-#define regk_iop_sw_cfg_spu1_gio_out1             0x00000009
-#define regk_iop_sw_cfg_spu1_gio_out2             0x0000000a
-#define regk_iop_sw_cfg_spu1_gio_out3             0x0000000b
-#define regk_iop_sw_cfg_spu1_gio_out4             0x0000000c
-#define regk_iop_sw_cfg_spu1_gio_out5             0x0000000d
-#define regk_iop_sw_cfg_spu1_gio_out6             0x0000000e
-#define regk_iop_sw_cfg_spu1_gio_out7             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout0              0x00000001
-#define regk_iop_sw_cfg_spu1_gioout1              0x00000001
-#define regk_iop_sw_cfg_spu1_gioout10             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout11             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout12             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout13             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout14             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout15             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout16             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout17             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout18             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout19             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout2              0x00000003
-#define regk_iop_sw_cfg_spu1_gioout20             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout21             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout22             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout23             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout24             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout25             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout26             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout27             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout28             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout29             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout3              0x00000003
-#define regk_iop_sw_cfg_spu1_gioout30             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout31             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout4              0x00000005
-#define regk_iop_sw_cfg_spu1_gioout5              0x00000005
-#define regk_iop_sw_cfg_spu1_gioout6              0x00000007
-#define regk_iop_sw_cfg_spu1_gioout7              0x00000007
-#define regk_iop_sw_cfg_spu1_gioout8              0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout9              0x0000000f
-#define regk_iop_sw_cfg_strb_timer_grp0_tmr0      0x00000001
-#define regk_iop_sw_cfg_strb_timer_grp0_tmr1      0x00000002
-#define regk_iop_sw_cfg_strb_timer_grp1_tmr0      0x00000001
-#define regk_iop_sw_cfg_strb_timer_grp1_tmr1      0x00000002
-#define regk_iop_sw_cfg_strb_timer_grp2_tmr0      0x00000003
-#define regk_iop_sw_cfg_strb_timer_grp2_tmr1      0x00000002
-#define regk_iop_sw_cfg_strb_timer_grp3_tmr0      0x00000003
-#define regk_iop_sw_cfg_strb_timer_grp3_tmr1      0x00000002
-#define regk_iop_sw_cfg_timer_grp0                0x00000000
-#define regk_iop_sw_cfg_timer_grp0_rot            0x00000001
-#define regk_iop_sw_cfg_timer_grp0_strb0          0x0000000a
-#define regk_iop_sw_cfg_timer_grp0_strb1          0x0000000a
-#define regk_iop_sw_cfg_timer_grp0_strb2          0x0000000a
-#define regk_iop_sw_cfg_timer_grp0_strb3          0x0000000a
-#define regk_iop_sw_cfg_timer_grp0_tmr0           0x00000004
-#define regk_iop_sw_cfg_timer_grp0_tmr1           0x00000004
-#define regk_iop_sw_cfg_timer_grp1                0x00000000
-#define regk_iop_sw_cfg_timer_grp1_rot            0x00000001
-#define regk_iop_sw_cfg_timer_grp1_strb0          0x0000000b
-#define regk_iop_sw_cfg_timer_grp1_strb1          0x0000000b
-#define regk_iop_sw_cfg_timer_grp1_strb2          0x0000000b
-#define regk_iop_sw_cfg_timer_grp1_strb3          0x0000000b
-#define regk_iop_sw_cfg_timer_grp1_tmr0           0x00000005
-#define regk_iop_sw_cfg_timer_grp1_tmr1           0x00000005
-#define regk_iop_sw_cfg_timer_grp2                0x00000000
-#define regk_iop_sw_cfg_timer_grp2_rot            0x00000001
-#define regk_iop_sw_cfg_timer_grp2_strb0          0x0000000c
-#define regk_iop_sw_cfg_timer_grp2_strb1          0x0000000c
-#define regk_iop_sw_cfg_timer_grp2_strb2          0x0000000c
-#define regk_iop_sw_cfg_timer_grp2_strb3          0x0000000c
-#define regk_iop_sw_cfg_timer_grp2_tmr0           0x00000006
-#define regk_iop_sw_cfg_timer_grp2_tmr1           0x00000006
-#define regk_iop_sw_cfg_timer_grp3                0x00000000
-#define regk_iop_sw_cfg_timer_grp3_rot            0x00000001
-#define regk_iop_sw_cfg_timer_grp3_strb0          0x0000000d
-#define regk_iop_sw_cfg_timer_grp3_strb1          0x0000000d
-#define regk_iop_sw_cfg_timer_grp3_strb2          0x0000000d
-#define regk_iop_sw_cfg_timer_grp3_strb3          0x0000000d
-#define regk_iop_sw_cfg_timer_grp3_tmr0           0x00000007
-#define regk_iop_sw_cfg_timer_grp3_tmr1           0x00000007
-#define regk_iop_sw_cfg_trig0_0                   0x00000000
-#define regk_iop_sw_cfg_trig0_1                   0x00000000
-#define regk_iop_sw_cfg_trig0_2                   0x00000000
-#define regk_iop_sw_cfg_trig0_3                   0x00000000
-#define regk_iop_sw_cfg_trig1_0                   0x00000000
-#define regk_iop_sw_cfg_trig1_1                   0x00000000
-#define regk_iop_sw_cfg_trig1_2                   0x00000000
-#define regk_iop_sw_cfg_trig1_3                   0x00000000
-#define regk_iop_sw_cfg_trig2_0                   0x00000000
-#define regk_iop_sw_cfg_trig2_1                   0x00000000
-#define regk_iop_sw_cfg_trig2_2                   0x00000000
-#define regk_iop_sw_cfg_trig2_3                   0x00000000
-#define regk_iop_sw_cfg_trig3_0                   0x00000000
-#define regk_iop_sw_cfg_trig3_1                   0x00000000
-#define regk_iop_sw_cfg_trig3_2                   0x00000000
-#define regk_iop_sw_cfg_trig3_3                   0x00000000
-#define regk_iop_sw_cfg_trig4_0                   0x00000001
-#define regk_iop_sw_cfg_trig4_1                   0x00000001
-#define regk_iop_sw_cfg_trig4_2                   0x00000001
-#define regk_iop_sw_cfg_trig4_3                   0x00000001
-#define regk_iop_sw_cfg_trig5_0                   0x00000001
-#define regk_iop_sw_cfg_trig5_1                   0x00000001
-#define regk_iop_sw_cfg_trig5_2                   0x00000001
-#define regk_iop_sw_cfg_trig5_3                   0x00000001
-#define regk_iop_sw_cfg_trig6_0                   0x00000001
-#define regk_iop_sw_cfg_trig6_1                   0x00000001
-#define regk_iop_sw_cfg_trig6_2                   0x00000001
-#define regk_iop_sw_cfg_trig6_3                   0x00000001
-#define regk_iop_sw_cfg_trig7_0                   0x00000001
-#define regk_iop_sw_cfg_trig7_1                   0x00000001
-#define regk_iop_sw_cfg_trig7_2                   0x00000001
-#define regk_iop_sw_cfg_trig7_3                   0x00000001
-#endif /* __iop_sw_cfg_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
deleted file mode 100644
index db347bcba025..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
+++ /dev/null
@@ -1,1758 +0,0 @@
-#ifndef __iop_sw_cpu_defs_asm_h
-#define __iop_sw_cpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:19 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
- *      id: $Id: iop_sw_cpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___lsb 6
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___bit 6
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___lsb 7
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___bit 7
-#define reg_iop_sw_cpu_rw_mc_ctrl_offset 0
-
-/* Register rw_mc_data, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_cpu_rw_mc_data___val___width 32
-#define reg_iop_sw_cpu_rw_mc_data_offset 4
-
-/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_addr_offset 8
-
-/* Register rs_mc_data, scope iop_sw_cpu, type rs */
-#define reg_iop_sw_cpu_rs_mc_data_offset 12
-
-/* Register r_mc_data, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_mc_data_offset 16
-
-/* Register r_mc_stat, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___lsb 2
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___bit 2
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___lsb 3
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___bit 3
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 4
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 4
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 5
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 5
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___lsb 6
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___bit 6
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___lsb 7
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___bit 7
-#define reg_iop_sw_cpu_r_mc_stat_offset 20
-
-/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask_offset 24
-
-/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask_offset 28
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask_offset 32
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask_offset 36
-
-/* Register r_bus0_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_bus0_in_offset 40
-
-/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask_offset 44
-
-/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask_offset 48
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask_offset 52
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask_offset 56
-
-/* Register r_bus1_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_bus1_in_offset 60
-
-/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 64
-
-/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_set_mask_offset 68
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 72
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 76
-
-/* Register r_gio_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_gio_in_offset 80
-
-/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___lsb 16
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___bit 16
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___lsb 17
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___bit 17
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___lsb 18
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___bit 18
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___lsb 19
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___bit 19
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___lsb 20
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___bit 20
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___lsb 21
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___bit 21
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___lsb 22
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___bit 22
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___lsb 23
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___bit 23
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___lsb 24
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___bit 24
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___lsb 25
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___bit 25
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___lsb 26
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___bit 26
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___lsb 27
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___bit 27
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___lsb 28
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___bit 28
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___lsb 29
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___bit 29
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___lsb 30
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___bit 30
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___lsb 31
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___bit 31
-#define reg_iop_sw_cpu_rw_intr0_mask_offset 84
-
-/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___lsb 16
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___bit 16
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___lsb 17
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___bit 17
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___lsb 18
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___bit 18
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___lsb 19
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___bit 19
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___lsb 20
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___bit 20
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___lsb 21
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___bit 21
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___lsb 22
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___bit 22
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___lsb 23
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___bit 23
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___lsb 24
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___bit 24
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___lsb 25
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___bit 25
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___lsb 26
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___bit 26
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___lsb 27
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___bit 27
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___lsb 28
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___bit 28
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___lsb 29
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___bit 29
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___lsb 30
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___bit 30
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___lsb 31
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___bit 31
-#define reg_iop_sw_cpu_rw_ack_intr0_offset 88
-
-/* Register r_intr0, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_r_intr0___spu0_0___lsb 16
-#define reg_iop_sw_cpu_r_intr0___spu0_0___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_0___bit 16
-#define reg_iop_sw_cpu_r_intr0___spu0_1___lsb 17
-#define reg_iop_sw_cpu_r_intr0___spu0_1___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_1___bit 17
-#define reg_iop_sw_cpu_r_intr0___spu0_2___lsb 18
-#define reg_iop_sw_cpu_r_intr0___spu0_2___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_2___bit 18
-#define reg_iop_sw_cpu_r_intr0___spu0_3___lsb 19
-#define reg_iop_sw_cpu_r_intr0___spu0_3___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_3___bit 19
-#define reg_iop_sw_cpu_r_intr0___spu0_4___lsb 20
-#define reg_iop_sw_cpu_r_intr0___spu0_4___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_4___bit 20
-#define reg_iop_sw_cpu_r_intr0___spu0_5___lsb 21
-#define reg_iop_sw_cpu_r_intr0___spu0_5___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_5___bit 21
-#define reg_iop_sw_cpu_r_intr0___spu0_6___lsb 22
-#define reg_iop_sw_cpu_r_intr0___spu0_6___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_6___bit 22
-#define reg_iop_sw_cpu_r_intr0___spu0_7___lsb 23
-#define reg_iop_sw_cpu_r_intr0___spu0_7___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_7___bit 23
-#define reg_iop_sw_cpu_r_intr0___spu1_8___lsb 24
-#define reg_iop_sw_cpu_r_intr0___spu1_8___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_8___bit 24
-#define reg_iop_sw_cpu_r_intr0___spu1_9___lsb 25
-#define reg_iop_sw_cpu_r_intr0___spu1_9___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_9___bit 25
-#define reg_iop_sw_cpu_r_intr0___spu1_10___lsb 26
-#define reg_iop_sw_cpu_r_intr0___spu1_10___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_10___bit 26
-#define reg_iop_sw_cpu_r_intr0___spu1_11___lsb 27
-#define reg_iop_sw_cpu_r_intr0___spu1_11___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_11___bit 27
-#define reg_iop_sw_cpu_r_intr0___spu1_12___lsb 28
-#define reg_iop_sw_cpu_r_intr0___spu1_12___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_12___bit 28
-#define reg_iop_sw_cpu_r_intr0___spu1_13___lsb 29
-#define reg_iop_sw_cpu_r_intr0___spu1_13___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_13___bit 29
-#define reg_iop_sw_cpu_r_intr0___spu1_14___lsb 30
-#define reg_iop_sw_cpu_r_intr0___spu1_14___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_14___bit 30
-#define reg_iop_sw_cpu_r_intr0___spu1_15___lsb 31
-#define reg_iop_sw_cpu_r_intr0___spu1_15___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_15___bit 31
-#define reg_iop_sw_cpu_r_intr0_offset 92
-
-/* Register r_masked_intr0, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___bit 16
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___bit 17
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___bit 18
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___bit 19
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___bit 20
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___bit 21
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___bit 22
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___bit 23
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___bit 24
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___bit 25
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___bit 26
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___bit 27
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___bit 28
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___bit 29
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___bit 30
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___bit 31
-#define reg_iop_sw_cpu_r_masked_intr0_offset 96
-
-/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___lsb 16
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___bit 16
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___lsb 17
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___bit 17
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___lsb 18
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___bit 18
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___lsb 19
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___bit 19
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___lsb 20
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___bit 20
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___lsb 21
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___bit 21
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___lsb 22
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___bit 22
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___lsb 23
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___bit 23
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___lsb 24
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___bit 24
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___lsb 25
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___bit 25
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___lsb 26
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___bit 26
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___lsb 27
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___bit 27
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___lsb 28
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___bit 28
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___lsb 29
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___bit 29
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___lsb 30
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___bit 30
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___lsb 31
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___bit 31
-#define reg_iop_sw_cpu_rw_intr1_mask_offset 100
-
-/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___lsb 16
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___bit 16
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___lsb 17
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___bit 17
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___lsb 18
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___bit 18
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___lsb 19
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___bit 19
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___lsb 20
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___bit 20
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___lsb 21
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___bit 21
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___lsb 22
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___bit 22
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___lsb 23
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___bit 23
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___lsb 24
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___bit 24
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___lsb 25
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___bit 25
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___lsb 26
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___bit 26
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___lsb 27
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___bit 27
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___lsb 28
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___bit 28
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___lsb 29
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___bit 29
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___lsb 30
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___bit 30
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___lsb 31
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___bit 31
-#define reg_iop_sw_cpu_rw_ack_intr1_offset 104
-
-/* Register r_intr1, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_r_intr1___spu0_8___lsb 16
-#define reg_iop_sw_cpu_r_intr1___spu0_8___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_8___bit 16
-#define reg_iop_sw_cpu_r_intr1___spu0_9___lsb 17
-#define reg_iop_sw_cpu_r_intr1___spu0_9___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_9___bit 17
-#define reg_iop_sw_cpu_r_intr1___spu0_10___lsb 18
-#define reg_iop_sw_cpu_r_intr1___spu0_10___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_10___bit 18
-#define reg_iop_sw_cpu_r_intr1___spu0_11___lsb 19
-#define reg_iop_sw_cpu_r_intr1___spu0_11___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_11___bit 19
-#define reg_iop_sw_cpu_r_intr1___spu0_12___lsb 20
-#define reg_iop_sw_cpu_r_intr1___spu0_12___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_12___bit 20
-#define reg_iop_sw_cpu_r_intr1___spu0_13___lsb 21
-#define reg_iop_sw_cpu_r_intr1___spu0_13___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_13___bit 21
-#define reg_iop_sw_cpu_r_intr1___spu0_14___lsb 22
-#define reg_iop_sw_cpu_r_intr1___spu0_14___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_14___bit 22
-#define reg_iop_sw_cpu_r_intr1___spu0_15___lsb 23
-#define reg_iop_sw_cpu_r_intr1___spu0_15___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_15___bit 23
-#define reg_iop_sw_cpu_r_intr1___spu1_0___lsb 24
-#define reg_iop_sw_cpu_r_intr1___spu1_0___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_0___bit 24
-#define reg_iop_sw_cpu_r_intr1___spu1_1___lsb 25
-#define reg_iop_sw_cpu_r_intr1___spu1_1___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_1___bit 25
-#define reg_iop_sw_cpu_r_intr1___spu1_2___lsb 26
-#define reg_iop_sw_cpu_r_intr1___spu1_2___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_2___bit 26
-#define reg_iop_sw_cpu_r_intr1___spu1_3___lsb 27
-#define reg_iop_sw_cpu_r_intr1___spu1_3___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_3___bit 27
-#define reg_iop_sw_cpu_r_intr1___spu1_4___lsb 28
-#define reg_iop_sw_cpu_r_intr1___spu1_4___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_4___bit 28
-#define reg_iop_sw_cpu_r_intr1___spu1_5___lsb 29
-#define reg_iop_sw_cpu_r_intr1___spu1_5___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_5___bit 29
-#define reg_iop_sw_cpu_r_intr1___spu1_6___lsb 30
-#define reg_iop_sw_cpu_r_intr1___spu1_6___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_6___bit 30
-#define reg_iop_sw_cpu_r_intr1___spu1_7___lsb 31
-#define reg_iop_sw_cpu_r_intr1___spu1_7___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_7___bit 31
-#define reg_iop_sw_cpu_r_intr1_offset 108
-
-/* Register r_masked_intr1, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___bit 16
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___bit 17
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___bit 18
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___bit 19
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___bit 20
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___bit 21
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___bit 22
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___bit 23
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___bit 24
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___bit 25
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___bit 26
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___bit 27
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___bit 28
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___bit 29
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___bit 30
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___bit 31
-#define reg_iop_sw_cpu_r_masked_intr1_offset 112
-
-/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___lsb 8
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___bit 8
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___lsb 9
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___bit 9
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___lsb 10
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___bit 10
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___lsb 11
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___bit 11
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___lsb 12
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___bit 12
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___lsb 13
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___bit 13
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___lsb 14
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___bit 14
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___lsb 15
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___bit 15
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___lsb 16
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___bit 16
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___lsb 17
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___bit 17
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___lsb 18
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___bit 18
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___lsb 19
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___bit 19
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___lsb 20
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___bit 20
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___lsb 21
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___bit 21
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___bit 30
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___bit 31
-#define reg_iop_sw_cpu_rw_intr2_mask_offset 116
-
-/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr2_offset 120
-
-/* Register r_intr2, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr2___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_intr2___mpu_0___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_intr2___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_intr2___mpu_1___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_intr2___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_intr2___mpu_2___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_intr2___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_intr2___mpu_3___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_intr2___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_intr2___mpu_4___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_intr2___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_intr2___mpu_5___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_intr2___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_intr2___mpu_6___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_intr2___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_intr2___mpu_7___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_intr2___spu0_0___lsb 8
-#define reg_iop_sw_cpu_r_intr2___spu0_0___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_0___bit 8
-#define reg_iop_sw_cpu_r_intr2___spu0_1___lsb 9
-#define reg_iop_sw_cpu_r_intr2___spu0_1___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_1___bit 9
-#define reg_iop_sw_cpu_r_intr2___spu0_2___lsb 10
-#define reg_iop_sw_cpu_r_intr2___spu0_2___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_2___bit 10
-#define reg_iop_sw_cpu_r_intr2___spu0_3___lsb 11
-#define reg_iop_sw_cpu_r_intr2___spu0_3___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_3___bit 11
-#define reg_iop_sw_cpu_r_intr2___spu0_4___lsb 12
-#define reg_iop_sw_cpu_r_intr2___spu0_4___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_4___bit 12
-#define reg_iop_sw_cpu_r_intr2___spu0_5___lsb 13
-#define reg_iop_sw_cpu_r_intr2___spu0_5___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_5___bit 13
-#define reg_iop_sw_cpu_r_intr2___spu0_6___lsb 14
-#define reg_iop_sw_cpu_r_intr2___spu0_6___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_6___bit 14
-#define reg_iop_sw_cpu_r_intr2___spu0_7___lsb 15
-#define reg_iop_sw_cpu_r_intr2___spu0_7___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_7___bit 15
-#define reg_iop_sw_cpu_r_intr2___dmc_in0___lsb 16
-#define reg_iop_sw_cpu_r_intr2___dmc_in0___width 1
-#define reg_iop_sw_cpu_r_intr2___dmc_in0___bit 16
-#define reg_iop_sw_cpu_r_intr2___dmc_out0___lsb 17
-#define reg_iop_sw_cpu_r_intr2___dmc_out0___width 1
-#define reg_iop_sw_cpu_r_intr2___dmc_out0___bit 17
-#define reg_iop_sw_cpu_r_intr2___fifo_in0___lsb 18
-#define reg_iop_sw_cpu_r_intr2___fifo_in0___width 1
-#define reg_iop_sw_cpu_r_intr2___fifo_in0___bit 18
-#define reg_iop_sw_cpu_r_intr2___fifo_out0___lsb 19
-#define reg_iop_sw_cpu_r_intr2___fifo_out0___width 1
-#define reg_iop_sw_cpu_r_intr2___fifo_out0___bit 19
-#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___lsb 20
-#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___width 1
-#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___bit 20
-#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___lsb 21
-#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___width 1
-#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___bit 21
-#define reg_iop_sw_cpu_r_intr2___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_intr2___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_intr2___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_intr2___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_intr2___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_intr2___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_intr2___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_intr2___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_intr2___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_intr2___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_intr2___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_intr2___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_intr2___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_intr2___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_intr2___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_intr2___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_intr2___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_r_intr2___timer_grp0___width 1
-#define reg_iop_sw_cpu_r_intr2___timer_grp0___bit 30
-#define reg_iop_sw_cpu_r_intr2___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_r_intr2___timer_grp1___width 1
-#define reg_iop_sw_cpu_r_intr2___timer_grp1___bit 31
-#define reg_iop_sw_cpu_r_intr2_offset 124
-
-/* Register r_masked_intr2, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___bit 8
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___bit 9
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___bit 10
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___bit 11
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___bit 12
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___bit 13
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___bit 14
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___bit 15
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___bit 16
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___bit 17
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___bit 18
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___bit 19
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___bit 20
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___bit 21
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___bit 30
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___bit 31
-#define reg_iop_sw_cpu_r_masked_intr2_offset 128
-
-/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___lsb 8
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___bit 8
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___lsb 9
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___bit 9
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___lsb 10
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___bit 10
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___lsb 11
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___bit 11
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___lsb 12
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___bit 12
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___lsb 13
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___bit 13
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___lsb 14
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___bit 14
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___lsb 15
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___bit 15
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___lsb 16
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___bit 16
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___lsb 17
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___bit 17
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___lsb 18
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___bit 18
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___lsb 19
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___bit 19
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___lsb 20
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___bit 20
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___lsb 21
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___bit 21
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___lsb 30
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___bit 30
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___lsb 31
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___bit 31
-#define reg_iop_sw_cpu_rw_intr3_mask_offset 132
-
-/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr3_offset 136
-
-/* Register r_intr3, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr3___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_intr3___mpu_16___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_intr3___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_intr3___mpu_17___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_intr3___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_intr3___mpu_18___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_intr3___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_intr3___mpu_19___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_intr3___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_intr3___mpu_20___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_intr3___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_intr3___mpu_21___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_intr3___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_intr3___mpu_22___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_intr3___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_intr3___mpu_23___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_intr3___spu1_0___lsb 8
-#define reg_iop_sw_cpu_r_intr3___spu1_0___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_0___bit 8
-#define reg_iop_sw_cpu_r_intr3___spu1_1___lsb 9
-#define reg_iop_sw_cpu_r_intr3___spu1_1___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_1___bit 9
-#define reg_iop_sw_cpu_r_intr3___spu1_2___lsb 10
-#define reg_iop_sw_cpu_r_intr3___spu1_2___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_2___bit 10
-#define reg_iop_sw_cpu_r_intr3___spu1_3___lsb 11
-#define reg_iop_sw_cpu_r_intr3___spu1_3___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_3___bit 11
-#define reg_iop_sw_cpu_r_intr3___spu1_4___lsb 12
-#define reg_iop_sw_cpu_r_intr3___spu1_4___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_4___bit 12
-#define reg_iop_sw_cpu_r_intr3___spu1_5___lsb 13
-#define reg_iop_sw_cpu_r_intr3___spu1_5___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_5___bit 13
-#define reg_iop_sw_cpu_r_intr3___spu1_6___lsb 14
-#define reg_iop_sw_cpu_r_intr3___spu1_6___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_6___bit 14
-#define reg_iop_sw_cpu_r_intr3___spu1_7___lsb 15
-#define reg_iop_sw_cpu_r_intr3___spu1_7___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_7___bit 15
-#define reg_iop_sw_cpu_r_intr3___dmc_in1___lsb 16
-#define reg_iop_sw_cpu_r_intr3___dmc_in1___width 1
-#define reg_iop_sw_cpu_r_intr3___dmc_in1___bit 16
-#define reg_iop_sw_cpu_r_intr3___dmc_out1___lsb 17
-#define reg_iop_sw_cpu_r_intr3___dmc_out1___width 1
-#define reg_iop_sw_cpu_r_intr3___dmc_out1___bit 17
-#define reg_iop_sw_cpu_r_intr3___fifo_in1___lsb 18
-#define reg_iop_sw_cpu_r_intr3___fifo_in1___width 1
-#define reg_iop_sw_cpu_r_intr3___fifo_in1___bit 18
-#define reg_iop_sw_cpu_r_intr3___fifo_out1___lsb 19
-#define reg_iop_sw_cpu_r_intr3___fifo_out1___width 1
-#define reg_iop_sw_cpu_r_intr3___fifo_out1___bit 19
-#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___lsb 20
-#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___width 1
-#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___bit 20
-#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___lsb 21
-#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___width 1
-#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___bit 21
-#define reg_iop_sw_cpu_r_intr3___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_intr3___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_intr3___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_intr3___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_intr3___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_intr3___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_intr3___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_intr3___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_intr3___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_intr3___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_intr3___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_intr3___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_intr3___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_intr3___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_intr3___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_intr3___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_intr3___timer_grp2___lsb 30
-#define reg_iop_sw_cpu_r_intr3___timer_grp2___width 1
-#define reg_iop_sw_cpu_r_intr3___timer_grp2___bit 30
-#define reg_iop_sw_cpu_r_intr3___timer_grp3___lsb 31
-#define reg_iop_sw_cpu_r_intr3___timer_grp3___width 1
-#define reg_iop_sw_cpu_r_intr3___timer_grp3___bit 31
-#define reg_iop_sw_cpu_r_intr3_offset 140
-
-/* Register r_masked_intr3, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___bit 8
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___bit 9
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___bit 10
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___bit 11
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___bit 12
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___bit 13
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___bit 14
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___bit 15
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___bit 16
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___bit 17
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___bit 18
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___bit 19
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___bit 20
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___bit 21
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___bit 30
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___bit 31
-#define reg_iop_sw_cpu_r_masked_intr3_offset 144
-
-
-/* Constants */
-#define regk_iop_sw_cpu_copy                      0x00000000
-#define regk_iop_sw_cpu_no                        0x00000000
-#define regk_iop_sw_cpu_rd                        0x00000002
-#define regk_iop_sw_cpu_reg_copy                  0x00000001
-#define regk_iop_sw_cpu_rw_bus0_clr_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_bus0_oe_set_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_bus0_set_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_bus1_clr_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_bus1_oe_set_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_bus1_set_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_gio_clr_mask_default   0x00000000
-#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_gio_set_mask_default   0x00000000
-#define regk_iop_sw_cpu_rw_intr0_mask_default     0x00000000
-#define regk_iop_sw_cpu_rw_intr1_mask_default     0x00000000
-#define regk_iop_sw_cpu_rw_intr2_mask_default     0x00000000
-#define regk_iop_sw_cpu_rw_intr3_mask_default     0x00000000
-#define regk_iop_sw_cpu_wr                        0x00000003
-#define regk_iop_sw_cpu_yes                       0x00000001
-#endif /* __iop_sw_cpu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
deleted file mode 100644
index ee7dc0435b59..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
+++ /dev/null
@@ -1,1776 +0,0 @@
-#ifndef __iop_sw_mpu_defs_asm_h
-#define __iop_sw_mpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:19 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_mpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
- *      id: $Id: iop_sw_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0
-#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2
-#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0
-
-/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___lsb 6
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___bit 6
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___lsb 7
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___bit 7
-#define reg_iop_sw_mpu_rw_mc_ctrl_offset 4
-
-/* Register rw_mc_data, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_mpu_rw_mc_data___val___width 32
-#define reg_iop_sw_mpu_rw_mc_data_offset 8
-
-/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_addr_offset 12
-
-/* Register rs_mc_data, scope iop_sw_mpu, type rs */
-#define reg_iop_sw_mpu_rs_mc_data_offset 16
-
-/* Register r_mc_data, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_mc_data_offset 20
-
-/* Register r_mc_stat, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___lsb 2
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___bit 2
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___lsb 3
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___bit 3
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 4
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 4
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 5
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 5
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___lsb 6
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___bit 6
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___lsb 7
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___bit 7
-#define reg_iop_sw_mpu_r_mc_stat_offset 24
-
-/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask_offset 28
-
-/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask_offset 32
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask_offset 36
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask_offset 40
-
-/* Register r_bus0_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_bus0_in_offset 44
-
-/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask_offset 48
-
-/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask_offset 52
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask_offset 56
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask_offset 60
-
-/* Register r_bus1_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_bus1_in_offset 64
-
-/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 68
-
-/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_set_mask_offset 72
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 76
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 80
-
-/* Register r_gio_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_gio_in_offset 84
-
-/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31
-#define reg_iop_sw_mpu_rw_cpu_intr_offset 88
-
-/* Register r_cpu_intr, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31
-#define reg_iop_sw_mpu_r_cpu_intr_offset 92
-
-/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___lsb 16
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___bit 16
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___lsb 17
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___bit 17
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___lsb 19
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___bit 19
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___bit 20
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___lsb 21
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___bit 21
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___lsb 22
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___bit 22
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___bit 23
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___lsb 24
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___bit 24
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___lsb 25
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___bit 25
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___lsb 27
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___bit 27
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___bit 28
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___lsb 29
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___bit 29
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___lsb 30
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___bit 30
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___bit 31
-#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 96
-
-/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___lsb 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___bit 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___lsb 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___bit 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___lsb 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___bit 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___lsb 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___bit 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___lsb 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___bit 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___lsb 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___bit 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 100
-
-/* Register r_intr_grp0, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___bit 0
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___bit 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___bit 3
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___bit 5
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___bit 8
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___bit 9
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___bit 11
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___bit 13
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___lsb 16
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___bit 16
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___lsb 17
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___bit 17
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___lsb 19
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___bit 19
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___lsb 21
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___bit 21
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___lsb 22
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___bit 22
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___lsb 24
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___bit 24
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___lsb 25
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___bit 25
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___lsb 27
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___bit 27
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___lsb 29
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___bit 29
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___lsb 30
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___bit 30
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_intr_grp0_offset 104
-
-/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___lsb 16
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___bit 16
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___lsb 17
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___bit 17
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___lsb 19
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___bit 19
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___lsb 21
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___bit 21
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___lsb 22
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___bit 22
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___lsb 24
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___bit 24
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___lsb 25
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___bit 25
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___lsb 27
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___bit 27
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___lsb 29
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___bit 29
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___lsb 30
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___bit 30
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 108
-
-/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___lsb 16
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___bit 16
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___lsb 17
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___bit 17
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 19
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 19
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___bit 20
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___lsb 21
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___bit 21
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___lsb 22
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___bit 22
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___bit 23
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___lsb 24
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___bit 24
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___lsb 25
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___bit 25
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 27
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 27
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___bit 28
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___lsb 29
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___bit 29
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___bit 31
-#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 112
-
-/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___lsb 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___bit 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___lsb 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___bit 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___lsb 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___bit 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___lsb 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___bit 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___lsb 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___bit 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___lsb 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___bit 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 116
-
-/* Register r_intr_grp1, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___bit 0
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___bit 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 3
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___bit 5
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___bit 8
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___bit 9
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 11
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___bit 13
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___lsb 16
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___bit 16
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___lsb 17
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___bit 17
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 19
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 19
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___lsb 21
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___bit 21
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___lsb 22
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___bit 22
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___lsb 24
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___bit 24
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___lsb 25
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___bit 25
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 27
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 27
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___lsb 29
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___bit 29
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_intr_grp1_offset 120
-
-/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___lsb 16
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___bit 16
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___lsb 17
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___bit 17
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 19
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 19
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___lsb 21
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___bit 21
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___lsb 22
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___bit 22
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___lsb 24
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___bit 24
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___lsb 25
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___bit 25
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 27
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 27
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___lsb 29
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___bit 29
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 124
-
-/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___lsb 16
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___bit 16
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___lsb 17
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___bit 17
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___lsb 19
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___bit 19
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___bit 20
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___lsb 21
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___bit 21
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___lsb 22
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___bit 22
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___bit 23
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___lsb 24
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___bit 24
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___lsb 25
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___bit 25
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___lsb 27
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___bit 27
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___bit 28
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___lsb 29
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___bit 29
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___lsb 30
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___bit 30
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___bit 31
-#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 128
-
-/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___lsb 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___bit 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___lsb 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___bit 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___lsb 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___bit 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___lsb 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___bit 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___lsb 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___bit 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___lsb 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___bit 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 132
-
-/* Register r_intr_grp2, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___bit 0
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___bit 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___bit 3
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___bit 5
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___bit 8
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___bit 9
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___bit 11
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___bit 13
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___lsb 16
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___bit 16
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___lsb 17
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___bit 17
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___lsb 19
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___bit 19
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___lsb 21
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___bit 21
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___lsb 22
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___bit 22
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___lsb 24
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___bit 24
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___lsb 25
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___bit 25
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___lsb 27
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___bit 27
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___lsb 29
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___bit 29
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___lsb 30
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___bit 30
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_intr_grp2_offset 136
-
-/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___lsb 16
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___bit 16
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___lsb 17
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___bit 17
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___lsb 19
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___bit 19
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___lsb 21
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___bit 21
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___lsb 22
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___bit 22
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___lsb 24
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___bit 24
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___lsb 25
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___bit 25
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___lsb 27
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___bit 27
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___lsb 29
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___bit 29
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___lsb 30
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___bit 30
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 140
-
-/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___lsb 16
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___bit 16
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___lsb 17
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___bit 17
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 19
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 19
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___bit 20
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___lsb 21
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___bit 21
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___lsb 22
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___bit 22
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___bit 23
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___lsb 24
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___bit 24
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___lsb 25
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___bit 25
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 27
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 27
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___bit 28
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___lsb 29
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___bit 29
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___bit 31
-#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 144
-
-/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___lsb 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___bit 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___lsb 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___bit 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___lsb 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___bit 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___lsb 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___bit 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___lsb 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___bit 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___lsb 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___bit 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 148
-
-/* Register r_intr_grp3, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___bit 0
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___bit 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 3
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___bit 5
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___bit 8
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___bit 9
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 11
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___bit 13
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___lsb 16
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___bit 16
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___lsb 17
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___bit 17
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 19
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 19
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___lsb 21
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___bit 21
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___lsb 22
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___bit 22
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___lsb 24
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___bit 24
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___lsb 25
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___bit 25
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 27
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 27
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___lsb 29
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___bit 29
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_intr_grp3_offset 152
-
-/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___lsb 16
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___bit 16
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___lsb 17
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___bit 17
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 19
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 19
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___lsb 21
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___bit 21
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___lsb 22
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___bit 22
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___lsb 24
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___bit 24
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___lsb 25
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___bit 25
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 27
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 27
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___lsb 29
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___bit 29
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 156
-
-
-/* Constants */
-#define regk_iop_sw_mpu_copy                      0x00000000
-#define regk_iop_sw_mpu_cpu                       0x00000000
-#define regk_iop_sw_mpu_mpu                       0x00000001
-#define regk_iop_sw_mpu_no                        0x00000000
-#define regk_iop_sw_mpu_nop                       0x00000000
-#define regk_iop_sw_mpu_rd                        0x00000002
-#define regk_iop_sw_mpu_reg_copy                  0x00000001
-#define regk_iop_sw_mpu_rw_bus0_clr_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_bus0_oe_set_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_bus0_set_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_bus1_clr_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_bus1_oe_set_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_bus1_set_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_gio_clr_mask_default   0x00000000
-#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_gio_set_mask_default   0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp0_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp1_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp2_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp3_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_sw_cfg_owner_default   0x00000000
-#define regk_iop_sw_mpu_set                       0x00000001
-#define regk_iop_sw_mpu_spu0                      0x00000002
-#define regk_iop_sw_mpu_spu1                      0x00000003
-#define regk_iop_sw_mpu_wr                        0x00000003
-#define regk_iop_sw_mpu_yes                       0x00000001
-#endif /* __iop_sw_mpu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h
deleted file mode 100644
index 0929f144cfa1..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h
+++ /dev/null
@@ -1,691 +0,0 @@
-#ifndef __iop_sw_spu_defs_asm_h
-#define __iop_sw_spu_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:19 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_spu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
- *      id: $Id: iop_sw_spu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___lsb 6
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___bit 6
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___lsb 7
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___bit 7
-#define reg_iop_sw_spu_rw_mc_ctrl_offset 0
-
-/* Register rw_mc_data, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_spu_rw_mc_data___val___width 32
-#define reg_iop_sw_spu_rw_mc_data_offset 4
-
-/* Register rw_mc_addr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_addr_offset 8
-
-/* Register rs_mc_data, scope iop_sw_spu, type rs */
-#define reg_iop_sw_spu_rs_mc_data_offset 12
-
-/* Register r_mc_data, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mc_data_offset 16
-
-/* Register r_mc_stat, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu0___lsb 2
-#define reg_iop_sw_spu_r_mc_stat___busy_spu0___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu0___bit 2
-#define reg_iop_sw_spu_r_mc_stat___busy_spu1___lsb 3
-#define reg_iop_sw_spu_r_mc_stat___busy_spu1___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu1___bit 3
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 4
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 4
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 5
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 5
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___lsb 6
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___bit 6
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___lsb 7
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___bit 7
-#define reg_iop_sw_spu_r_mc_stat_offset 20
-
-/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_offset 24
-
-/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_offset 28
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask_offset 32
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask_offset 36
-
-/* Register r_bus0_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_bus0_in_offset 40
-
-/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_offset 44
-
-/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_offset 48
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask_offset 52
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask_offset 56
-
-/* Register r_bus1_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_bus1_in_offset 60
-
-/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_clr_mask_offset 64
-
-/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_set_mask_offset 68
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 72
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 76
-
-/* Register r_gio_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_gio_in_offset 80
-
-/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo_offset 84
-
-/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi_offset 88
-
-/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo_offset 92
-
-/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi_offset 96
-
-/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo_offset 100
-
-/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi_offset 104
-
-/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo_offset 108
-
-/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi_offset 112
-
-/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 116
-
-/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120
-
-/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 124
-
-/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 128
-
-/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 132
-
-/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 136
-
-/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 140
-
-/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 144
-
-/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_rw_cpu_intr_offset 148
-
-/* Register r_cpu_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_r_cpu_intr_offset 152
-
-/* Register r_hw_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9
-#define reg_iop_sw_spu_r_hw_intr___timer_grp2___lsb 10
-#define reg_iop_sw_spu_r_hw_intr___timer_grp2___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp2___bit 10
-#define reg_iop_sw_spu_r_hw_intr___timer_grp3___lsb 11
-#define reg_iop_sw_spu_r_hw_intr___timer_grp3___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp3___bit 11
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0___lsb 12
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0___bit 12
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___lsb 13
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___bit 13
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0___lsb 14
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0___bit 14
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___lsb 15
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___bit 15
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1___lsb 16
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1___bit 16
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___lsb 17
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___bit 17
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1___lsb 18
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1___bit 18
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___lsb 19
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___bit 19
-#define reg_iop_sw_spu_r_hw_intr___dmc_out0___lsb 20
-#define reg_iop_sw_spu_r_hw_intr___dmc_out0___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_out0___bit 20
-#define reg_iop_sw_spu_r_hw_intr___dmc_in0___lsb 21
-#define reg_iop_sw_spu_r_hw_intr___dmc_in0___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_in0___bit 21
-#define reg_iop_sw_spu_r_hw_intr___dmc_out1___lsb 22
-#define reg_iop_sw_spu_r_hw_intr___dmc_out1___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_out1___bit 22
-#define reg_iop_sw_spu_r_hw_intr___dmc_in1___lsb 23
-#define reg_iop_sw_spu_r_hw_intr___dmc_in1___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_in1___bit 23
-#define reg_iop_sw_spu_r_hw_intr_offset 156
-
-/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_rw_mpu_intr_offset 160
-
-/* Register r_mpu_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___lsb 16
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___bit 16
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___lsb 17
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___bit 17
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___lsb 18
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___bit 18
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___lsb 19
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___bit 19
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___lsb 20
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___bit 20
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___lsb 21
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___bit 21
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___lsb 22
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___bit 22
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___lsb 23
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___bit 23
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___lsb 24
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___bit 24
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___lsb 25
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___bit 25
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___lsb 26
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___bit 26
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___lsb 27
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___bit 27
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___lsb 28
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___bit 28
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___lsb 29
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___bit 29
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___lsb 30
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___bit 30
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___lsb 31
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___bit 31
-#define reg_iop_sw_spu_r_mpu_intr_offset 164
-
-
-/* Constants */
-#define regk_iop_sw_spu_copy                      0x00000000
-#define regk_iop_sw_spu_no                        0x00000000
-#define regk_iop_sw_spu_nop                       0x00000000
-#define regk_iop_sw_spu_rd                        0x00000002
-#define regk_iop_sw_spu_reg_copy                  0x00000001
-#define regk_iop_sw_spu_rw_bus0_clr_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_bus0_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_bus0_oe_set_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_bus0_set_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_bus1_clr_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_bus1_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_bus1_oe_set_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_bus1_set_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_gio_clr_mask_default   0x00000000
-#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_gio_oe_set_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_gio_set_mask_default   0x00000000
-#define regk_iop_sw_spu_set                       0x00000001
-#define regk_iop_sw_spu_wr                        0x00000003
-#define regk_iop_sw_spu_yes                       0x00000001
-#endif /* __iop_sw_spu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h
deleted file mode 100644
index 7129a9a4bedc..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h
+++ /dev/null
@@ -1,237 +0,0 @@
-#ifndef __iop_timer_grp_defs_asm_h
-#define __iop_timer_grp_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_timer_grp.r
- *     id:           iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r
- *      id: $Id: iop_timer_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_cfg___clk_src___lsb 0
-#define reg_iop_timer_grp_rw_cfg___clk_src___width 1
-#define reg_iop_timer_grp_rw_cfg___clk_src___bit 0
-#define reg_iop_timer_grp_rw_cfg___trig___lsb 1
-#define reg_iop_timer_grp_rw_cfg___trig___width 2
-#define reg_iop_timer_grp_rw_cfg___clk_gen_div___lsb 3
-#define reg_iop_timer_grp_rw_cfg___clk_gen_div___width 8
-#define reg_iop_timer_grp_rw_cfg___clk_div___lsb 11
-#define reg_iop_timer_grp_rw_cfg___clk_div___width 8
-#define reg_iop_timer_grp_rw_cfg_offset 0
-
-/* Register rw_half_period, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_half_period___quota_lo___lsb 0
-#define reg_iop_timer_grp_rw_half_period___quota_lo___width 15
-#define reg_iop_timer_grp_rw_half_period___quota_hi___lsb 15
-#define reg_iop_timer_grp_rw_half_period___quota_hi___width 15
-#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___lsb 30
-#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___width 1
-#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___bit 30
-#define reg_iop_timer_grp_rw_half_period_offset 4
-
-/* Register rw_half_period_len, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_half_period_len_offset 8
-
-#define STRIDE_iop_timer_grp_rw_tmr_cfg 4
-/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___lsb 0
-#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___width 3
-#define reg_iop_timer_grp_rw_tmr_cfg___strb___lsb 3
-#define reg_iop_timer_grp_rw_tmr_cfg___strb___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___lsb 5
-#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___lsb 7
-#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___bit 7
-#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___lsb 8
-#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___inv___lsb 10
-#define reg_iop_timer_grp_rw_tmr_cfg___inv___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___inv___bit 10
-#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___lsb 11
-#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___lsb 13
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___lsb 15
-#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___bit 15
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___lsb 16
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___bit 16
-#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___lsb 17
-#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___bit 17
-#define reg_iop_timer_grp_rw_tmr_cfg_offset 12
-
-#define STRIDE_iop_timer_grp_rw_tmr_len 4
-/* Register rw_tmr_len, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_tmr_len___val___lsb 0
-#define reg_iop_timer_grp_rw_tmr_len___val___width 16
-#define reg_iop_timer_grp_rw_tmr_len_offset 44
-
-/* Register rw_cmd, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_cmd___rst___lsb 0
-#define reg_iop_timer_grp_rw_cmd___rst___width 4
-#define reg_iop_timer_grp_rw_cmd___en___lsb 4
-#define reg_iop_timer_grp_rw_cmd___en___width 4
-#define reg_iop_timer_grp_rw_cmd___dis___lsb 8
-#define reg_iop_timer_grp_rw_cmd___dis___width 4
-#define reg_iop_timer_grp_rw_cmd___strb___lsb 12
-#define reg_iop_timer_grp_rw_cmd___strb___width 4
-#define reg_iop_timer_grp_rw_cmd_offset 60
-
-/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
-#define reg_iop_timer_grp_r_clk_gen_cnt_offset 64
-
-#define STRIDE_iop_timer_grp_rs_tmr_cnt 8
-/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
-#define reg_iop_timer_grp_rs_tmr_cnt___val___lsb 0
-#define reg_iop_timer_grp_rs_tmr_cnt___val___width 16
-#define reg_iop_timer_grp_rs_tmr_cnt_offset 68
-
-#define STRIDE_iop_timer_grp_r_tmr_cnt 8
-/* Register r_tmr_cnt, scope iop_timer_grp, type r */
-#define reg_iop_timer_grp_r_tmr_cnt___val___lsb 0
-#define reg_iop_timer_grp_r_tmr_cnt___val___width 16
-#define reg_iop_timer_grp_r_tmr_cnt_offset 72
-
-/* Register rw_intr_mask, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_intr_mask___tmr0___lsb 0
-#define reg_iop_timer_grp_rw_intr_mask___tmr0___width 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr0___bit 0
-#define reg_iop_timer_grp_rw_intr_mask___tmr1___lsb 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr1___width 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr1___bit 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr2___lsb 2
-#define reg_iop_timer_grp_rw_intr_mask___tmr2___width 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr2___bit 2
-#define reg_iop_timer_grp_rw_intr_mask___tmr3___lsb 3
-#define reg_iop_timer_grp_rw_intr_mask___tmr3___width 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr3___bit 3
-#define reg_iop_timer_grp_rw_intr_mask_offset 100
-
-/* Register rw_ack_intr, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_ack_intr___tmr0___lsb 0
-#define reg_iop_timer_grp_rw_ack_intr___tmr0___width 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr0___bit 0
-#define reg_iop_timer_grp_rw_ack_intr___tmr1___lsb 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr1___width 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr1___bit 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr2___lsb 2
-#define reg_iop_timer_grp_rw_ack_intr___tmr2___width 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr2___bit 2
-#define reg_iop_timer_grp_rw_ack_intr___tmr3___lsb 3
-#define reg_iop_timer_grp_rw_ack_intr___tmr3___width 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr3___bit 3
-#define reg_iop_timer_grp_rw_ack_intr_offset 104
-
-/* Register r_intr, scope iop_timer_grp, type r */
-#define reg_iop_timer_grp_r_intr___tmr0___lsb 0
-#define reg_iop_timer_grp_r_intr___tmr0___width 1
-#define reg_iop_timer_grp_r_intr___tmr0___bit 0
-#define reg_iop_timer_grp_r_intr___tmr1___lsb 1
-#define reg_iop_timer_grp_r_intr___tmr1___width 1
-#define reg_iop_timer_grp_r_intr___tmr1___bit 1
-#define reg_iop_timer_grp_r_intr___tmr2___lsb 2
-#define reg_iop_timer_grp_r_intr___tmr2___width 1
-#define reg_iop_timer_grp_r_intr___tmr2___bit 2
-#define reg_iop_timer_grp_r_intr___tmr3___lsb 3
-#define reg_iop_timer_grp_r_intr___tmr3___width 1
-#define reg_iop_timer_grp_r_intr___tmr3___bit 3
-#define reg_iop_timer_grp_r_intr_offset 108
-
-/* Register r_masked_intr, scope iop_timer_grp, type r */
-#define reg_iop_timer_grp_r_masked_intr___tmr0___lsb 0
-#define reg_iop_timer_grp_r_masked_intr___tmr0___width 1
-#define reg_iop_timer_grp_r_masked_intr___tmr0___bit 0
-#define reg_iop_timer_grp_r_masked_intr___tmr1___lsb 1
-#define reg_iop_timer_grp_r_masked_intr___tmr1___width 1
-#define reg_iop_timer_grp_r_masked_intr___tmr1___bit 1
-#define reg_iop_timer_grp_r_masked_intr___tmr2___lsb 2
-#define reg_iop_timer_grp_r_masked_intr___tmr2___width 1
-#define reg_iop_timer_grp_r_masked_intr___tmr2___bit 2
-#define reg_iop_timer_grp_r_masked_intr___tmr3___lsb 3
-#define reg_iop_timer_grp_r_masked_intr___tmr3___width 1
-#define reg_iop_timer_grp_r_masked_intr___tmr3___bit 3
-#define reg_iop_timer_grp_r_masked_intr_offset 112
-
-
-/* Constants */
-#define regk_iop_timer_grp_clk200                 0x00000000
-#define regk_iop_timer_grp_clk_gen                0x00000002
-#define regk_iop_timer_grp_complete               0x00000002
-#define regk_iop_timer_grp_div_clk200             0x00000001
-#define regk_iop_timer_grp_div_clk_gen            0x00000003
-#define regk_iop_timer_grp_ext                    0x00000001
-#define regk_iop_timer_grp_hi                     0x00000000
-#define regk_iop_timer_grp_long_period            0x00000001
-#define regk_iop_timer_grp_neg                    0x00000002
-#define regk_iop_timer_grp_no                     0x00000000
-#define regk_iop_timer_grp_once                   0x00000003
-#define regk_iop_timer_grp_pause                  0x00000001
-#define regk_iop_timer_grp_pos                    0x00000001
-#define regk_iop_timer_grp_pos_neg                0x00000003
-#define regk_iop_timer_grp_pulse                  0x00000000
-#define regk_iop_timer_grp_r_tmr_cnt_size         0x00000004
-#define regk_iop_timer_grp_rs_tmr_cnt_size        0x00000004
-#define regk_iop_timer_grp_rw_cfg_default         0x00000002
-#define regk_iop_timer_grp_rw_intr_mask_default   0x00000000
-#define regk_iop_timer_grp_rw_tmr_cfg_default0    0x00018000
-#define regk_iop_timer_grp_rw_tmr_cfg_default1    0x0001a900
-#define regk_iop_timer_grp_rw_tmr_cfg_default2    0x0001d200
-#define regk_iop_timer_grp_rw_tmr_cfg_default3    0x0001fb00
-#define regk_iop_timer_grp_rw_tmr_cfg_size        0x00000004
-#define regk_iop_timer_grp_rw_tmr_len_default     0x00000000
-#define regk_iop_timer_grp_rw_tmr_len_size        0x00000004
-#define regk_iop_timer_grp_short_period           0x00000000
-#define regk_iop_timer_grp_stop                   0x00000000
-#define regk_iop_timer_grp_tmr                    0x00000004
-#define regk_iop_timer_grp_toggle                 0x00000001
-#define regk_iop_timer_grp_yes                    0x00000001
-#endif /* __iop_timer_grp_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h
deleted file mode 100644
index 1005d9db80dc..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h
+++ /dev/null
@@ -1,157 +0,0 @@
-#ifndef __iop_trigger_grp_defs_asm_h
-#define __iop_trigger_grp_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_trigger_grp.r
- *     id:           iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r
- *      id: $Id: iop_trigger_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_iop_trigger_grp_rw_cfg 4
-/* Register rw_cfg, scope iop_trigger_grp, type rw */
-#define reg_iop_trigger_grp_rw_cfg___action___lsb 0
-#define reg_iop_trigger_grp_rw_cfg___action___width 2
-#define reg_iop_trigger_grp_rw_cfg___once___lsb 2
-#define reg_iop_trigger_grp_rw_cfg___once___width 1
-#define reg_iop_trigger_grp_rw_cfg___once___bit 2
-#define reg_iop_trigger_grp_rw_cfg___trig___lsb 3
-#define reg_iop_trigger_grp_rw_cfg___trig___width 3
-#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6
-#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1
-#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6
-#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7
-#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1
-#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7
-#define reg_iop_trigger_grp_rw_cfg_offset 0
-
-/* Register rw_cmd, scope iop_trigger_grp, type rw */
-#define reg_iop_trigger_grp_rw_cmd___dis___lsb 0
-#define reg_iop_trigger_grp_rw_cmd___dis___width 4
-#define reg_iop_trigger_grp_rw_cmd___en___lsb 4
-#define reg_iop_trigger_grp_rw_cmd___en___width 4
-#define reg_iop_trigger_grp_rw_cmd_offset 16
-
-/* Register rw_intr_mask, scope iop_trigger_grp, type rw */
-#define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0
-#define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0
-#define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2
-#define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2
-#define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3
-#define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3
-#define reg_iop_trigger_grp_rw_intr_mask_offset 20
-
-/* Register rw_ack_intr, scope iop_trigger_grp, type rw */
-#define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0
-#define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0
-#define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2
-#define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2
-#define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3
-#define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3
-#define reg_iop_trigger_grp_rw_ack_intr_offset 24
-
-/* Register r_intr, scope iop_trigger_grp, type r */
-#define reg_iop_trigger_grp_r_intr___trig0___lsb 0
-#define reg_iop_trigger_grp_r_intr___trig0___width 1
-#define reg_iop_trigger_grp_r_intr___trig0___bit 0
-#define reg_iop_trigger_grp_r_intr___trig1___lsb 1
-#define reg_iop_trigger_grp_r_intr___trig1___width 1
-#define reg_iop_trigger_grp_r_intr___trig1___bit 1
-#define reg_iop_trigger_grp_r_intr___trig2___lsb 2
-#define reg_iop_trigger_grp_r_intr___trig2___width 1
-#define reg_iop_trigger_grp_r_intr___trig2___bit 2
-#define reg_iop_trigger_grp_r_intr___trig3___lsb 3
-#define reg_iop_trigger_grp_r_intr___trig3___width 1
-#define reg_iop_trigger_grp_r_intr___trig3___bit 3
-#define reg_iop_trigger_grp_r_intr_offset 28
-
-/* Register r_masked_intr, scope iop_trigger_grp, type r */
-#define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0
-#define reg_iop_trigger_grp_r_masked_intr___trig0___width 1
-#define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0
-#define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1
-#define reg_iop_trigger_grp_r_masked_intr___trig1___width 1
-#define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1
-#define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2
-#define reg_iop_trigger_grp_r_masked_intr___trig2___width 1
-#define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2
-#define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3
-#define reg_iop_trigger_grp_r_masked_intr___trig3___width 1
-#define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3
-#define reg_iop_trigger_grp_r_masked_intr_offset 32
-
-
-/* Constants */
-#define regk_iop_trigger_grp_fall                 0x00000002
-#define regk_iop_trigger_grp_fall_lo              0x00000006
-#define regk_iop_trigger_grp_no                   0x00000000
-#define regk_iop_trigger_grp_off                  0x00000000
-#define regk_iop_trigger_grp_pulse                0x00000000
-#define regk_iop_trigger_grp_rise                 0x00000001
-#define regk_iop_trigger_grp_rise_fall            0x00000003
-#define regk_iop_trigger_grp_rise_fall_hi         0x00000007
-#define regk_iop_trigger_grp_rise_fall_lo         0x00000004
-#define regk_iop_trigger_grp_rise_hi              0x00000005
-#define regk_iop_trigger_grp_rw_cfg_default       0x000000c0
-#define regk_iop_trigger_grp_rw_cfg_size          0x00000004
-#define regk_iop_trigger_grp_rw_intr_mask_default  0x00000000
-#define regk_iop_trigger_grp_toggle               0x00000003
-#define regk_iop_trigger_grp_yes                  0x00000001
-#endif /* __iop_trigger_grp_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h
deleted file mode 100644
index e13feb20a7e3..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h
+++ /dev/null
@@ -1,64 +0,0 @@
-#ifndef __iop_version_defs_asm_h
-#define __iop_version_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/guinness/iop_version.r
- *     id:           iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp
- *     last modfied: Mon Apr 11 16:08:44 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_version_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_version.r
- *      id: $Id: iop_version_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_version, scope iop_version, type r */
-#define reg_iop_version_r_version___nr___lsb 0
-#define reg_iop_version_r_version___nr___width 8
-#define reg_iop_version_r_version_offset 0
-
-
-/* Constants */
-#define regk_iop_version_v1_0                     0x00000001
-#endif /* __iop_version_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h
deleted file mode 100644
index 90e4785b6474..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h
+++ /dev/null
@@ -1,232 +0,0 @@
-#ifndef __iop_crc_par_defs_h
-#define __iop_crc_par_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_crc_par.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:08:45 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r
- *      id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_crc_par */
-
-/* Register rw_cfg, scope iop_crc_par, type rw */
-typedef struct {
-  unsigned int mode    : 1;
-  unsigned int crc_out : 1;
-  unsigned int rev_out : 1;
-  unsigned int inv_out : 1;
-  unsigned int trig    : 2;
-  unsigned int poly    : 3;
-  unsigned int dummy1  : 23;
-} reg_iop_crc_par_rw_cfg;
-#define REG_RD_ADDR_iop_crc_par_rw_cfg 0
-#define REG_WR_ADDR_iop_crc_par_rw_cfg 0
-
-/* Register rw_init_crc, scope iop_crc_par, type rw */
-typedef unsigned int reg_iop_crc_par_rw_init_crc;
-#define REG_RD_ADDR_iop_crc_par_rw_init_crc 4
-#define REG_WR_ADDR_iop_crc_par_rw_init_crc 4
-
-/* Register rw_correct_crc, scope iop_crc_par, type rw */
-typedef unsigned int reg_iop_crc_par_rw_correct_crc;
-#define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8
-#define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8
-
-/* Register rw_ctrl, scope iop_crc_par, type rw */
-typedef struct {
-  unsigned int en : 1;
-  unsigned int dummy1 : 31;
-} reg_iop_crc_par_rw_ctrl;
-#define REG_RD_ADDR_iop_crc_par_rw_ctrl 12
-#define REG_WR_ADDR_iop_crc_par_rw_ctrl 12
-
-/* Register rw_set_last, scope iop_crc_par, type rw */
-typedef struct {
-  unsigned int tr_dif : 1;
-  unsigned int dummy1 : 31;
-} reg_iop_crc_par_rw_set_last;
-#define REG_RD_ADDR_iop_crc_par_rw_set_last 16
-#define REG_WR_ADDR_iop_crc_par_rw_set_last 16
-
-/* Register rw_wr1byte, scope iop_crc_par, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_iop_crc_par_rw_wr1byte;
-#define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20
-#define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20
-
-/* Register rw_wr2byte, scope iop_crc_par, type rw */
-typedef struct {
-  unsigned int data : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_crc_par_rw_wr2byte;
-#define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24
-#define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24
-
-/* Register rw_wr3byte, scope iop_crc_par, type rw */
-typedef struct {
-  unsigned int data : 24;
-  unsigned int dummy1 : 8;
-} reg_iop_crc_par_rw_wr3byte;
-#define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28
-#define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28
-
-/* Register rw_wr4byte, scope iop_crc_par, type rw */
-typedef struct {
-  unsigned int data : 32;
-} reg_iop_crc_par_rw_wr4byte;
-#define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32
-#define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32
-
-/* Register rw_wr1byte_last, scope iop_crc_par, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_iop_crc_par_rw_wr1byte_last;
-#define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36
-#define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36
-
-/* Register rw_wr2byte_last, scope iop_crc_par, type rw */
-typedef struct {
-  unsigned int data : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_crc_par_rw_wr2byte_last;
-#define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40
-#define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40
-
-/* Register rw_wr3byte_last, scope iop_crc_par, type rw */
-typedef struct {
-  unsigned int data : 24;
-  unsigned int dummy1 : 8;
-} reg_iop_crc_par_rw_wr3byte_last;
-#define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44
-#define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44
-
-/* Register rw_wr4byte_last, scope iop_crc_par, type rw */
-typedef struct {
-  unsigned int data : 32;
-} reg_iop_crc_par_rw_wr4byte_last;
-#define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48
-#define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48
-
-/* Register r_stat, scope iop_crc_par, type r */
-typedef struct {
-  unsigned int err  : 1;
-  unsigned int busy : 1;
-  unsigned int dummy1 : 30;
-} reg_iop_crc_par_r_stat;
-#define REG_RD_ADDR_iop_crc_par_r_stat 52
-
-/* Register r_sh_reg, scope iop_crc_par, type r */
-typedef unsigned int reg_iop_crc_par_r_sh_reg;
-#define REG_RD_ADDR_iop_crc_par_r_sh_reg 56
-
-/* Register r_crc, scope iop_crc_par, type r */
-typedef unsigned int reg_iop_crc_par_r_crc;
-#define REG_RD_ADDR_iop_crc_par_r_crc 60
-
-/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
-typedef struct {
-  unsigned int last : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_crc_par_rw_strb_rec_dif_in;
-#define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
-#define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
-
-
-/* Constants */
-enum {
-  regk_iop_crc_par_calc                    = 0x00000001,
-  regk_iop_crc_par_ccitt                   = 0x00000002,
-  regk_iop_crc_par_check                   = 0x00000000,
-  regk_iop_crc_par_crc16                   = 0x00000001,
-  regk_iop_crc_par_crc32                   = 0x00000000,
-  regk_iop_crc_par_crc5                    = 0x00000003,
-  regk_iop_crc_par_crc5_11                 = 0x00000004,
-  regk_iop_crc_par_dif_in                  = 0x00000002,
-  regk_iop_crc_par_hi                      = 0x00000000,
-  regk_iop_crc_par_neg                     = 0x00000002,
-  regk_iop_crc_par_no                      = 0x00000000,
-  regk_iop_crc_par_pos                     = 0x00000001,
-  regk_iop_crc_par_pos_neg                 = 0x00000003,
-  regk_iop_crc_par_rw_cfg_default          = 0x00000000,
-  regk_iop_crc_par_rw_ctrl_default         = 0x00000000,
-  regk_iop_crc_par_yes                     = 0x00000001
-};
-#endif /* __iop_crc_par_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h
deleted file mode 100644
index 76aec6e37f3e..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h
+++ /dev/null
@@ -1,325 +0,0 @@
-#ifndef __iop_dmc_in_defs_h
-#define __iop_dmc_in_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_dmc_in.r
- *     id:           iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:45 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_in_defs.h ../../inst/io_proc/rtl/iop_dmc_in.r
- *      id: $Id: iop_dmc_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_dmc_in */
-
-/* Register rw_cfg, scope iop_dmc_in, type rw */
-typedef struct {
-  unsigned int sth_intr     : 3;
-  unsigned int last_dis_dif : 1;
-  unsigned int dummy1       : 28;
-} reg_iop_dmc_in_rw_cfg;
-#define REG_RD_ADDR_iop_dmc_in_rw_cfg 0
-#define REG_WR_ADDR_iop_dmc_in_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_dmc_in, type rw */
-typedef struct {
-  unsigned int dif_en     : 1;
-  unsigned int dif_dis    : 1;
-  unsigned int stream_clr : 1;
-  unsigned int dummy1     : 29;
-} reg_iop_dmc_in_rw_ctrl;
-#define REG_RD_ADDR_iop_dmc_in_rw_ctrl 4
-#define REG_WR_ADDR_iop_dmc_in_rw_ctrl 4
-
-/* Register r_stat, scope iop_dmc_in, type r */
-typedef struct {
-  unsigned int dif_en : 1;
-  unsigned int dummy1 : 31;
-} reg_iop_dmc_in_r_stat;
-#define REG_RD_ADDR_iop_dmc_in_r_stat 8
-
-/* Register rw_stream_cmd, scope iop_dmc_in, type rw */
-typedef struct {
-  unsigned int cmd : 10;
-  unsigned int dummy1 : 6;
-  unsigned int n   : 8;
-  unsigned int dummy2 : 8;
-} reg_iop_dmc_in_rw_stream_cmd;
-#define REG_RD_ADDR_iop_dmc_in_rw_stream_cmd 12
-#define REG_WR_ADDR_iop_dmc_in_rw_stream_cmd 12
-
-/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */
-typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data;
-#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data 16
-#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data 16
-
-/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */
-typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data_last;
-#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data_last 20
-#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data_last 20
-
-/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */
-typedef struct {
-  unsigned int eop     : 1;
-  unsigned int wait    : 1;
-  unsigned int keep_md : 1;
-  unsigned int size    : 3;
-  unsigned int dummy1  : 26;
-} reg_iop_dmc_in_rw_stream_ctrl;
-#define REG_RD_ADDR_iop_dmc_in_rw_stream_ctrl 24
-#define REG_WR_ADDR_iop_dmc_in_rw_stream_ctrl 24
-
-/* Register r_stream_stat, scope iop_dmc_in, type r */
-typedef struct {
-  unsigned int sth            : 7;
-  unsigned int dummy1         : 9;
-  unsigned int full           : 1;
-  unsigned int last_pkt       : 1;
-  unsigned int data_md_valid  : 1;
-  unsigned int ctxt_md_valid  : 1;
-  unsigned int group_md_valid : 1;
-  unsigned int stream_busy    : 1;
-  unsigned int cmd_rdy        : 1;
-  unsigned int dummy2         : 9;
-} reg_iop_dmc_in_r_stream_stat;
-#define REG_RD_ADDR_iop_dmc_in_r_stream_stat 28
-
-/* Register r_data_descr, scope iop_dmc_in, type r */
-typedef struct {
-  unsigned int ctrl : 8;
-  unsigned int stat : 8;
-  unsigned int md   : 16;
-} reg_iop_dmc_in_r_data_descr;
-#define REG_RD_ADDR_iop_dmc_in_r_data_descr 32
-
-/* Register r_ctxt_descr, scope iop_dmc_in, type r */
-typedef struct {
-  unsigned int ctrl : 8;
-  unsigned int stat : 8;
-  unsigned int md0  : 16;
-} reg_iop_dmc_in_r_ctxt_descr;
-#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr 36
-
-/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */
-typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md1;
-#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md1 40
-
-/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */
-typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md2;
-#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md2 44
-
-/* Register r_group_descr, scope iop_dmc_in, type r */
-typedef struct {
-  unsigned int ctrl : 8;
-  unsigned int stat : 8;
-  unsigned int md   : 16;
-} reg_iop_dmc_in_r_group_descr;
-#define REG_RD_ADDR_iop_dmc_in_r_group_descr 56
-
-/* Register rw_data_descr, scope iop_dmc_in, type rw */
-typedef struct {
-  unsigned int dummy1 : 16;
-  unsigned int md : 16;
-} reg_iop_dmc_in_rw_data_descr;
-#define REG_RD_ADDR_iop_dmc_in_rw_data_descr 60
-#define REG_WR_ADDR_iop_dmc_in_rw_data_descr 60
-
-/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */
-typedef struct {
-  unsigned int dummy1 : 16;
-  unsigned int md0 : 16;
-} reg_iop_dmc_in_rw_ctxt_descr;
-#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr 64
-#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr 64
-
-/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */
-typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md1;
-#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68
-#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68
-
-/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */
-typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md2;
-#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72
-#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72
-
-/* Register rw_group_descr, scope iop_dmc_in, type rw */
-typedef struct {
-  unsigned int dummy1 : 16;
-  unsigned int md : 16;
-} reg_iop_dmc_in_rw_group_descr;
-#define REG_RD_ADDR_iop_dmc_in_rw_group_descr 84
-#define REG_WR_ADDR_iop_dmc_in_rw_group_descr 84
-
-/* Register rw_intr_mask, scope iop_dmc_in, type rw */
-typedef struct {
-  unsigned int data_md  : 1;
-  unsigned int ctxt_md  : 1;
-  unsigned int group_md : 1;
-  unsigned int cmd_rdy  : 1;
-  unsigned int sth      : 1;
-  unsigned int full     : 1;
-  unsigned int dummy1   : 26;
-} reg_iop_dmc_in_rw_intr_mask;
-#define REG_RD_ADDR_iop_dmc_in_rw_intr_mask 88
-#define REG_WR_ADDR_iop_dmc_in_rw_intr_mask 88
-
-/* Register rw_ack_intr, scope iop_dmc_in, type rw */
-typedef struct {
-  unsigned int data_md  : 1;
-  unsigned int ctxt_md  : 1;
-  unsigned int group_md : 1;
-  unsigned int cmd_rdy  : 1;
-  unsigned int sth      : 1;
-  unsigned int full     : 1;
-  unsigned int dummy1   : 26;
-} reg_iop_dmc_in_rw_ack_intr;
-#define REG_RD_ADDR_iop_dmc_in_rw_ack_intr 92
-#define REG_WR_ADDR_iop_dmc_in_rw_ack_intr 92
-
-/* Register r_intr, scope iop_dmc_in, type r */
-typedef struct {
-  unsigned int data_md  : 1;
-  unsigned int ctxt_md  : 1;
-  unsigned int group_md : 1;
-  unsigned int cmd_rdy  : 1;
-  unsigned int sth      : 1;
-  unsigned int full     : 1;
-  unsigned int dummy1   : 26;
-} reg_iop_dmc_in_r_intr;
-#define REG_RD_ADDR_iop_dmc_in_r_intr 96
-
-/* Register r_masked_intr, scope iop_dmc_in, type r */
-typedef struct {
-  unsigned int data_md  : 1;
-  unsigned int ctxt_md  : 1;
-  unsigned int group_md : 1;
-  unsigned int cmd_rdy  : 1;
-  unsigned int sth      : 1;
-  unsigned int full     : 1;
-  unsigned int dummy1   : 26;
-} reg_iop_dmc_in_r_masked_intr;
-#define REG_RD_ADDR_iop_dmc_in_r_masked_intr 100
-
-
-/* Constants */
-enum {
-  regk_iop_dmc_in_ack_pkt                  = 0x00000100,
-  regk_iop_dmc_in_array                    = 0x00000008,
-  regk_iop_dmc_in_burst                    = 0x00000020,
-  regk_iop_dmc_in_copy_next                = 0x00000010,
-  regk_iop_dmc_in_copy_up                  = 0x00000020,
-  regk_iop_dmc_in_dis_c                    = 0x00000010,
-  regk_iop_dmc_in_dis_g                    = 0x00000020,
-  regk_iop_dmc_in_lim1                     = 0x00000000,
-  regk_iop_dmc_in_lim16                    = 0x00000004,
-  regk_iop_dmc_in_lim2                     = 0x00000001,
-  regk_iop_dmc_in_lim32                    = 0x00000005,
-  regk_iop_dmc_in_lim4                     = 0x00000002,
-  regk_iop_dmc_in_lim64                    = 0x00000006,
-  regk_iop_dmc_in_lim8                     = 0x00000003,
-  regk_iop_dmc_in_load_c                   = 0x00000200,
-  regk_iop_dmc_in_load_c_n                 = 0x00000280,
-  regk_iop_dmc_in_load_c_next              = 0x00000240,
-  regk_iop_dmc_in_load_d                   = 0x00000140,
-  regk_iop_dmc_in_load_g                   = 0x00000300,
-  regk_iop_dmc_in_load_g_down              = 0x000003c0,
-  regk_iop_dmc_in_load_g_next              = 0x00000340,
-  regk_iop_dmc_in_load_g_up                = 0x00000380,
-  regk_iop_dmc_in_next_en                  = 0x00000010,
-  regk_iop_dmc_in_next_pkt                 = 0x00000010,
-  regk_iop_dmc_in_no                       = 0x00000000,
-  regk_iop_dmc_in_restore                  = 0x00000020,
-  regk_iop_dmc_in_rw_cfg_default           = 0x00000000,
-  regk_iop_dmc_in_rw_ctxt_descr_default    = 0x00000000,
-  regk_iop_dmc_in_rw_ctxt_descr_md1_default = 0x00000000,
-  regk_iop_dmc_in_rw_ctxt_descr_md2_default = 0x00000000,
-  regk_iop_dmc_in_rw_data_descr_default    = 0x00000000,
-  regk_iop_dmc_in_rw_group_descr_default   = 0x00000000,
-  regk_iop_dmc_in_rw_intr_mask_default     = 0x00000000,
-  regk_iop_dmc_in_rw_stream_ctrl_default   = 0x00000000,
-  regk_iop_dmc_in_save_down                = 0x00000020,
-  regk_iop_dmc_in_save_up                  = 0x00000020,
-  regk_iop_dmc_in_set_reg                  = 0x00000050,
-  regk_iop_dmc_in_set_w_size1              = 0x00000190,
-  regk_iop_dmc_in_set_w_size2              = 0x000001a0,
-  regk_iop_dmc_in_set_w_size4              = 0x000001c0,
-  regk_iop_dmc_in_store_c                  = 0x00000002,
-  regk_iop_dmc_in_store_descr              = 0x00000000,
-  regk_iop_dmc_in_store_g                  = 0x00000004,
-  regk_iop_dmc_in_store_md                 = 0x00000001,
-  regk_iop_dmc_in_update_down              = 0x00000020,
-  regk_iop_dmc_in_yes                      = 0x00000001
-};
-#endif /* __iop_dmc_in_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h
deleted file mode 100644
index 938a0d4c4604..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h
+++ /dev/null
@@ -1,326 +0,0 @@
-#ifndef __iop_dmc_out_defs_h
-#define __iop_dmc_out_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_dmc_out.r
- *     id:           iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:45 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r
- *      id: $Id: iop_dmc_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_dmc_out */
-
-/* Register rw_cfg, scope iop_dmc_out, type rw */
-typedef struct {
-  unsigned int trf_lim         : 16;
-  unsigned int last_at_trf_lim : 1;
-  unsigned int dth_intr        : 3;
-  unsigned int dummy1          : 12;
-} reg_iop_dmc_out_rw_cfg;
-#define REG_RD_ADDR_iop_dmc_out_rw_cfg 0
-#define REG_WR_ADDR_iop_dmc_out_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_dmc_out, type rw */
-typedef struct {
-  unsigned int dif_en  : 1;
-  unsigned int dif_dis : 1;
-  unsigned int dummy1  : 30;
-} reg_iop_dmc_out_rw_ctrl;
-#define REG_RD_ADDR_iop_dmc_out_rw_ctrl 4
-#define REG_WR_ADDR_iop_dmc_out_rw_ctrl 4
-
-/* Register r_stat, scope iop_dmc_out, type r */
-typedef struct {
-  unsigned int dif_en : 1;
-  unsigned int dummy1 : 31;
-} reg_iop_dmc_out_r_stat;
-#define REG_RD_ADDR_iop_dmc_out_r_stat 8
-
-/* Register rw_stream_cmd, scope iop_dmc_out, type rw */
-typedef struct {
-  unsigned int cmd : 10;
-  unsigned int dummy1 : 6;
-  unsigned int n   : 8;
-  unsigned int dummy2 : 8;
-} reg_iop_dmc_out_rw_stream_cmd;
-#define REG_RD_ADDR_iop_dmc_out_rw_stream_cmd 12
-#define REG_WR_ADDR_iop_dmc_out_rw_stream_cmd 12
-
-/* Register rs_stream_data, scope iop_dmc_out, type rs */
-typedef unsigned int reg_iop_dmc_out_rs_stream_data;
-#define REG_RD_ADDR_iop_dmc_out_rs_stream_data 16
-
-/* Register r_stream_data, scope iop_dmc_out, type r */
-typedef unsigned int reg_iop_dmc_out_r_stream_data;
-#define REG_RD_ADDR_iop_dmc_out_r_stream_data 20
-
-/* Register r_stream_stat, scope iop_dmc_out, type r */
-typedef struct {
-  unsigned int dth            : 7;
-  unsigned int dummy1         : 9;
-  unsigned int dv             : 1;
-  unsigned int all_avail      : 1;
-  unsigned int last           : 1;
-  unsigned int size           : 3;
-  unsigned int data_md_valid  : 1;
-  unsigned int ctxt_md_valid  : 1;
-  unsigned int group_md_valid : 1;
-  unsigned int stream_busy    : 1;
-  unsigned int cmd_rdy        : 1;
-  unsigned int cmd_rq         : 1;
-  unsigned int dummy2         : 4;
-} reg_iop_dmc_out_r_stream_stat;
-#define REG_RD_ADDR_iop_dmc_out_r_stream_stat 24
-
-/* Register r_data_descr, scope iop_dmc_out, type r */
-typedef struct {
-  unsigned int ctrl : 8;
-  unsigned int stat : 8;
-  unsigned int md   : 16;
-} reg_iop_dmc_out_r_data_descr;
-#define REG_RD_ADDR_iop_dmc_out_r_data_descr 28
-
-/* Register r_ctxt_descr, scope iop_dmc_out, type r */
-typedef struct {
-  unsigned int ctrl : 8;
-  unsigned int stat : 8;
-  unsigned int md0  : 16;
-} reg_iop_dmc_out_r_ctxt_descr;
-#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr 32
-
-/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */
-typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md1;
-#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md1 36
-
-/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */
-typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md2;
-#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md2 40
-
-/* Register r_group_descr, scope iop_dmc_out, type r */
-typedef struct {
-  unsigned int ctrl : 8;
-  unsigned int stat : 8;
-  unsigned int md   : 16;
-} reg_iop_dmc_out_r_group_descr;
-#define REG_RD_ADDR_iop_dmc_out_r_group_descr 52
-
-/* Register rw_data_descr, scope iop_dmc_out, type rw */
-typedef struct {
-  unsigned int dummy1 : 16;
-  unsigned int md : 16;
-} reg_iop_dmc_out_rw_data_descr;
-#define REG_RD_ADDR_iop_dmc_out_rw_data_descr 56
-#define REG_WR_ADDR_iop_dmc_out_rw_data_descr 56
-
-/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
-typedef struct {
-  unsigned int dummy1 : 16;
-  unsigned int md0 : 16;
-} reg_iop_dmc_out_rw_ctxt_descr;
-#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr 60
-#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr 60
-
-/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
-typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md1;
-#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
-#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
-
-/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
-typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md2;
-#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
-#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
-
-/* Register rw_group_descr, scope iop_dmc_out, type rw */
-typedef struct {
-  unsigned int dummy1 : 16;
-  unsigned int md : 16;
-} reg_iop_dmc_out_rw_group_descr;
-#define REG_RD_ADDR_iop_dmc_out_rw_group_descr 80
-#define REG_WR_ADDR_iop_dmc_out_rw_group_descr 80
-
-/* Register rw_intr_mask, scope iop_dmc_out, type rw */
-typedef struct {
-  unsigned int data_md   : 1;
-  unsigned int ctxt_md   : 1;
-  unsigned int group_md  : 1;
-  unsigned int cmd_rdy   : 1;
-  unsigned int dth       : 1;
-  unsigned int dv        : 1;
-  unsigned int last_data : 1;
-  unsigned int trf_lim   : 1;
-  unsigned int cmd_rq    : 1;
-  unsigned int dummy1    : 23;
-} reg_iop_dmc_out_rw_intr_mask;
-#define REG_RD_ADDR_iop_dmc_out_rw_intr_mask 84
-#define REG_WR_ADDR_iop_dmc_out_rw_intr_mask 84
-
-/* Register rw_ack_intr, scope iop_dmc_out, type rw */
-typedef struct {
-  unsigned int data_md   : 1;
-  unsigned int ctxt_md   : 1;
-  unsigned int group_md  : 1;
-  unsigned int cmd_rdy   : 1;
-  unsigned int dth       : 1;
-  unsigned int dv        : 1;
-  unsigned int last_data : 1;
-  unsigned int trf_lim   : 1;
-  unsigned int cmd_rq    : 1;
-  unsigned int dummy1    : 23;
-} reg_iop_dmc_out_rw_ack_intr;
-#define REG_RD_ADDR_iop_dmc_out_rw_ack_intr 88
-#define REG_WR_ADDR_iop_dmc_out_rw_ack_intr 88
-
-/* Register r_intr, scope iop_dmc_out, type r */
-typedef struct {
-  unsigned int data_md   : 1;
-  unsigned int ctxt_md   : 1;
-  unsigned int group_md  : 1;
-  unsigned int cmd_rdy   : 1;
-  unsigned int dth       : 1;
-  unsigned int dv        : 1;
-  unsigned int last_data : 1;
-  unsigned int trf_lim   : 1;
-  unsigned int cmd_rq    : 1;
-  unsigned int dummy1    : 23;
-} reg_iop_dmc_out_r_intr;
-#define REG_RD_ADDR_iop_dmc_out_r_intr 92
-
-/* Register r_masked_intr, scope iop_dmc_out, type r */
-typedef struct {
-  unsigned int data_md   : 1;
-  unsigned int ctxt_md   : 1;
-  unsigned int group_md  : 1;
-  unsigned int cmd_rdy   : 1;
-  unsigned int dth       : 1;
-  unsigned int dv        : 1;
-  unsigned int last_data : 1;
-  unsigned int trf_lim   : 1;
-  unsigned int cmd_rq    : 1;
-  unsigned int dummy1    : 23;
-} reg_iop_dmc_out_r_masked_intr;
-#define REG_RD_ADDR_iop_dmc_out_r_masked_intr 96
-
-
-/* Constants */
-enum {
-  regk_iop_dmc_out_ack_pkt                 = 0x00000100,
-  regk_iop_dmc_out_array                   = 0x00000008,
-  regk_iop_dmc_out_burst                   = 0x00000020,
-  regk_iop_dmc_out_copy_next               = 0x00000010,
-  regk_iop_dmc_out_copy_up                 = 0x00000020,
-  regk_iop_dmc_out_dis_c                   = 0x00000010,
-  regk_iop_dmc_out_dis_g                   = 0x00000020,
-  regk_iop_dmc_out_lim1                    = 0x00000000,
-  regk_iop_dmc_out_lim16                   = 0x00000004,
-  regk_iop_dmc_out_lim2                    = 0x00000001,
-  regk_iop_dmc_out_lim32                   = 0x00000005,
-  regk_iop_dmc_out_lim4                    = 0x00000002,
-  regk_iop_dmc_out_lim64                   = 0x00000006,
-  regk_iop_dmc_out_lim8                    = 0x00000003,
-  regk_iop_dmc_out_load_c                  = 0x00000200,
-  regk_iop_dmc_out_load_c_n                = 0x00000280,
-  regk_iop_dmc_out_load_c_next             = 0x00000240,
-  regk_iop_dmc_out_load_d                  = 0x00000140,
-  regk_iop_dmc_out_load_g                  = 0x00000300,
-  regk_iop_dmc_out_load_g_down             = 0x000003c0,
-  regk_iop_dmc_out_load_g_next             = 0x00000340,
-  regk_iop_dmc_out_load_g_up               = 0x00000380,
-  regk_iop_dmc_out_next_en                 = 0x00000010,
-  regk_iop_dmc_out_next_pkt                = 0x00000010,
-  regk_iop_dmc_out_no                      = 0x00000000,
-  regk_iop_dmc_out_restore                 = 0x00000020,
-  regk_iop_dmc_out_rw_cfg_default          = 0x00000000,
-  regk_iop_dmc_out_rw_ctxt_descr_default   = 0x00000000,
-  regk_iop_dmc_out_rw_ctxt_descr_md1_default = 0x00000000,
-  regk_iop_dmc_out_rw_ctxt_descr_md2_default = 0x00000000,
-  regk_iop_dmc_out_rw_data_descr_default   = 0x00000000,
-  regk_iop_dmc_out_rw_group_descr_default  = 0x00000000,
-  regk_iop_dmc_out_rw_intr_mask_default    = 0x00000000,
-  regk_iop_dmc_out_save_down               = 0x00000020,
-  regk_iop_dmc_out_save_up                 = 0x00000020,
-  regk_iop_dmc_out_set_reg                 = 0x00000050,
-  regk_iop_dmc_out_set_w_size1             = 0x00000190,
-  regk_iop_dmc_out_set_w_size2             = 0x000001a0,
-  regk_iop_dmc_out_set_w_size4             = 0x000001c0,
-  regk_iop_dmc_out_store_c                 = 0x00000002,
-  regk_iop_dmc_out_store_descr             = 0x00000000,
-  regk_iop_dmc_out_store_g                 = 0x00000004,
-  regk_iop_dmc_out_store_md                = 0x00000001,
-  regk_iop_dmc_out_update_down             = 0x00000020,
-  regk_iop_dmc_out_yes                     = 0x00000001
-};
-#endif /* __iop_dmc_out_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h
deleted file mode 100644
index e0c982b263fa..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h
+++ /dev/null
@@ -1,255 +0,0 @@
-#ifndef __iop_fifo_in_defs_h
-#define __iop_fifo_in_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_fifo_in.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:07 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r
- *      id: $Id: iop_fifo_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_fifo_in */
-
-/* Register rw_cfg, scope iop_fifo_in, type rw */
-typedef struct {
-  unsigned int avail_lim       : 3;
-  unsigned int byte_order      : 2;
-  unsigned int trig            : 2;
-  unsigned int last_dis_dif_in : 1;
-  unsigned int mode            : 2;
-  unsigned int dummy1          : 22;
-} reg_iop_fifo_in_rw_cfg;
-#define REG_RD_ADDR_iop_fifo_in_rw_cfg 0
-#define REG_WR_ADDR_iop_fifo_in_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_fifo_in, type rw */
-typedef struct {
-  unsigned int dif_in_en  : 1;
-  unsigned int dif_out_en : 1;
-  unsigned int dummy1     : 30;
-} reg_iop_fifo_in_rw_ctrl;
-#define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4
-#define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4
-
-/* Register r_stat, scope iop_fifo_in, type r */
-typedef struct {
-  unsigned int avail_bytes : 4;
-  unsigned int last        : 8;
-  unsigned int dif_in_en   : 1;
-  unsigned int dif_out_en  : 1;
-  unsigned int dummy1      : 18;
-} reg_iop_fifo_in_r_stat;
-#define REG_RD_ADDR_iop_fifo_in_r_stat 8
-
-/* Register rs_rd1byte, scope iop_fifo_in, type rs */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_iop_fifo_in_rs_rd1byte;
-#define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12
-
-/* Register r_rd1byte, scope iop_fifo_in, type r */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_iop_fifo_in_r_rd1byte;
-#define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16
-
-/* Register rs_rd2byte, scope iop_fifo_in, type rs */
-typedef struct {
-  unsigned int data : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_fifo_in_rs_rd2byte;
-#define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20
-
-/* Register r_rd2byte, scope iop_fifo_in, type r */
-typedef struct {
-  unsigned int data : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_fifo_in_r_rd2byte;
-#define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24
-
-/* Register rs_rd3byte, scope iop_fifo_in, type rs */
-typedef struct {
-  unsigned int data : 24;
-  unsigned int dummy1 : 8;
-} reg_iop_fifo_in_rs_rd3byte;
-#define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28
-
-/* Register r_rd3byte, scope iop_fifo_in, type r */
-typedef struct {
-  unsigned int data : 24;
-  unsigned int dummy1 : 8;
-} reg_iop_fifo_in_r_rd3byte;
-#define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32
-
-/* Register rs_rd4byte, scope iop_fifo_in, type rs */
-typedef struct {
-  unsigned int data : 32;
-} reg_iop_fifo_in_rs_rd4byte;
-#define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36
-
-/* Register r_rd4byte, scope iop_fifo_in, type r */
-typedef struct {
-  unsigned int data : 32;
-} reg_iop_fifo_in_r_rd4byte;
-#define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40
-
-/* Register rw_set_last, scope iop_fifo_in, type rw */
-typedef unsigned int reg_iop_fifo_in_rw_set_last;
-#define REG_RD_ADDR_iop_fifo_in_rw_set_last 44
-#define REG_WR_ADDR_iop_fifo_in_rw_set_last 44
-
-/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
-typedef struct {
-  unsigned int last : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_fifo_in_rw_strb_dif_in;
-#define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48
-#define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48
-
-/* Register rw_intr_mask, scope iop_fifo_in, type rw */
-typedef struct {
-  unsigned int urun      : 1;
-  unsigned int last_data : 1;
-  unsigned int dav       : 1;
-  unsigned int avail     : 1;
-  unsigned int orun      : 1;
-  unsigned int dummy1    : 27;
-} reg_iop_fifo_in_rw_intr_mask;
-#define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52
-#define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52
-
-/* Register rw_ack_intr, scope iop_fifo_in, type rw */
-typedef struct {
-  unsigned int urun      : 1;
-  unsigned int last_data : 1;
-  unsigned int dav       : 1;
-  unsigned int avail     : 1;
-  unsigned int orun      : 1;
-  unsigned int dummy1    : 27;
-} reg_iop_fifo_in_rw_ack_intr;
-#define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56
-#define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56
-
-/* Register r_intr, scope iop_fifo_in, type r */
-typedef struct {
-  unsigned int urun      : 1;
-  unsigned int last_data : 1;
-  unsigned int dav       : 1;
-  unsigned int avail     : 1;
-  unsigned int orun      : 1;
-  unsigned int dummy1    : 27;
-} reg_iop_fifo_in_r_intr;
-#define REG_RD_ADDR_iop_fifo_in_r_intr 60
-
-/* Register r_masked_intr, scope iop_fifo_in, type r */
-typedef struct {
-  unsigned int urun      : 1;
-  unsigned int last_data : 1;
-  unsigned int dav       : 1;
-  unsigned int avail     : 1;
-  unsigned int orun      : 1;
-  unsigned int dummy1    : 27;
-} reg_iop_fifo_in_r_masked_intr;
-#define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64
-
-
-/* Constants */
-enum {
-  regk_iop_fifo_in_dif_in                  = 0x00000002,
-  regk_iop_fifo_in_hi                      = 0x00000000,
-  regk_iop_fifo_in_neg                     = 0x00000002,
-  regk_iop_fifo_in_no                      = 0x00000000,
-  regk_iop_fifo_in_order16                 = 0x00000001,
-  regk_iop_fifo_in_order24                 = 0x00000002,
-  regk_iop_fifo_in_order32                 = 0x00000003,
-  regk_iop_fifo_in_order8                  = 0x00000000,
-  regk_iop_fifo_in_pos                     = 0x00000001,
-  regk_iop_fifo_in_pos_neg                 = 0x00000003,
-  regk_iop_fifo_in_rw_cfg_default          = 0x00000024,
-  regk_iop_fifo_in_rw_ctrl_default         = 0x00000000,
-  regk_iop_fifo_in_rw_intr_mask_default    = 0x00000000,
-  regk_iop_fifo_in_rw_set_last_default     = 0x00000000,
-  regk_iop_fifo_in_rw_strb_dif_in_default  = 0x00000000,
-  regk_iop_fifo_in_size16                  = 0x00000002,
-  regk_iop_fifo_in_size24                  = 0x00000001,
-  regk_iop_fifo_in_size32                  = 0x00000000,
-  regk_iop_fifo_in_size8                   = 0x00000003,
-  regk_iop_fifo_in_yes                     = 0x00000001
-};
-#endif /* __iop_fifo_in_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h
deleted file mode 100644
index 798ac95870e9..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h
+++ /dev/null
@@ -1,164 +0,0 @@
-#ifndef __iop_fifo_in_extra_defs_h
-#define __iop_fifo_in_extra_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_fifo_in_extra.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:08 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r
- *      id: $Id: iop_fifo_in_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_fifo_in_extra */
-
-/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */
-typedef unsigned int reg_iop_fifo_in_extra_rw_wr_data;
-#define REG_RD_ADDR_iop_fifo_in_extra_rw_wr_data 0
-#define REG_WR_ADDR_iop_fifo_in_extra_rw_wr_data 0
-
-/* Register r_stat, scope iop_fifo_in_extra, type r */
-typedef struct {
-  unsigned int avail_bytes : 4;
-  unsigned int last        : 8;
-  unsigned int dif_in_en   : 1;
-  unsigned int dif_out_en  : 1;
-  unsigned int dummy1      : 18;
-} reg_iop_fifo_in_extra_r_stat;
-#define REG_RD_ADDR_iop_fifo_in_extra_r_stat 4
-
-/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */
-typedef struct {
-  unsigned int last : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_fifo_in_extra_rw_strb_dif_in;
-#define REG_RD_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8
-#define REG_WR_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8
-
-/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */
-typedef struct {
-  unsigned int urun      : 1;
-  unsigned int last_data : 1;
-  unsigned int dav       : 1;
-  unsigned int avail     : 1;
-  unsigned int orun      : 1;
-  unsigned int dummy1    : 27;
-} reg_iop_fifo_in_extra_rw_intr_mask;
-#define REG_RD_ADDR_iop_fifo_in_extra_rw_intr_mask 12
-#define REG_WR_ADDR_iop_fifo_in_extra_rw_intr_mask 12
-
-/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */
-typedef struct {
-  unsigned int urun      : 1;
-  unsigned int last_data : 1;
-  unsigned int dav       : 1;
-  unsigned int avail     : 1;
-  unsigned int orun      : 1;
-  unsigned int dummy1    : 27;
-} reg_iop_fifo_in_extra_rw_ack_intr;
-#define REG_RD_ADDR_iop_fifo_in_extra_rw_ack_intr 16
-#define REG_WR_ADDR_iop_fifo_in_extra_rw_ack_intr 16
-
-/* Register r_intr, scope iop_fifo_in_extra, type r */
-typedef struct {
-  unsigned int urun      : 1;
-  unsigned int last_data : 1;
-  unsigned int dav       : 1;
-  unsigned int avail     : 1;
-  unsigned int orun      : 1;
-  unsigned int dummy1    : 27;
-} reg_iop_fifo_in_extra_r_intr;
-#define REG_RD_ADDR_iop_fifo_in_extra_r_intr 20
-
-/* Register r_masked_intr, scope iop_fifo_in_extra, type r */
-typedef struct {
-  unsigned int urun      : 1;
-  unsigned int last_data : 1;
-  unsigned int dav       : 1;
-  unsigned int avail     : 1;
-  unsigned int orun      : 1;
-  unsigned int dummy1    : 27;
-} reg_iop_fifo_in_extra_r_masked_intr;
-#define REG_RD_ADDR_iop_fifo_in_extra_r_masked_intr 24
-
-
-/* Constants */
-enum {
-  regk_iop_fifo_in_extra_fifo_in           = 0x00000002,
-  regk_iop_fifo_in_extra_no                = 0x00000000,
-  regk_iop_fifo_in_extra_rw_intr_mask_default = 0x00000000,
-  regk_iop_fifo_in_extra_yes               = 0x00000001
-};
-#endif /* __iop_fifo_in_extra_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h
deleted file mode 100644
index 833e10f02526..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h
+++ /dev/null
@@ -1,278 +0,0 @@
-#ifndef __iop_fifo_out_defs_h
-#define __iop_fifo_out_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_fifo_out.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:09 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r
- *      id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_fifo_out */
-
-/* Register rw_cfg, scope iop_fifo_out, type rw */
-typedef struct {
-  unsigned int free_lim         : 3;
-  unsigned int byte_order       : 2;
-  unsigned int trig             : 2;
-  unsigned int last_dis_dif_in  : 1;
-  unsigned int mode             : 2;
-  unsigned int delay_out_last   : 1;
-  unsigned int last_dis_dif_out : 1;
-  unsigned int dummy1           : 20;
-} reg_iop_fifo_out_rw_cfg;
-#define REG_RD_ADDR_iop_fifo_out_rw_cfg 0
-#define REG_WR_ADDR_iop_fifo_out_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_fifo_out, type rw */
-typedef struct {
-  unsigned int dif_in_en  : 1;
-  unsigned int dif_out_en : 1;
-  unsigned int dummy1     : 30;
-} reg_iop_fifo_out_rw_ctrl;
-#define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4
-#define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4
-
-/* Register r_stat, scope iop_fifo_out, type r */
-typedef struct {
-  unsigned int avail_bytes    : 4;
-  unsigned int last           : 8;
-  unsigned int dif_in_en      : 1;
-  unsigned int dif_out_en     : 1;
-  unsigned int zero_data_last : 1;
-  unsigned int dummy1         : 17;
-} reg_iop_fifo_out_r_stat;
-#define REG_RD_ADDR_iop_fifo_out_r_stat 8
-
-/* Register rw_wr1byte, scope iop_fifo_out, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_iop_fifo_out_rw_wr1byte;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12
-#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12
-
-/* Register rw_wr2byte, scope iop_fifo_out, type rw */
-typedef struct {
-  unsigned int data : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_fifo_out_rw_wr2byte;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16
-#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16
-
-/* Register rw_wr3byte, scope iop_fifo_out, type rw */
-typedef struct {
-  unsigned int data : 24;
-  unsigned int dummy1 : 8;
-} reg_iop_fifo_out_rw_wr3byte;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20
-#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20
-
-/* Register rw_wr4byte, scope iop_fifo_out, type rw */
-typedef struct {
-  unsigned int data : 32;
-} reg_iop_fifo_out_rw_wr4byte;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24
-#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24
-
-/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_iop_fifo_out_rw_wr1byte_last;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28
-#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28
-
-/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
-typedef struct {
-  unsigned int data : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_fifo_out_rw_wr2byte_last;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32
-#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32
-
-/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
-typedef struct {
-  unsigned int data : 24;
-  unsigned int dummy1 : 8;
-} reg_iop_fifo_out_rw_wr3byte_last;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36
-#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36
-
-/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
-typedef struct {
-  unsigned int data : 32;
-} reg_iop_fifo_out_rw_wr4byte_last;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40
-#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40
-
-/* Register rw_set_last, scope iop_fifo_out, type rw */
-typedef unsigned int reg_iop_fifo_out_rw_set_last;
-#define REG_RD_ADDR_iop_fifo_out_rw_set_last 44
-#define REG_WR_ADDR_iop_fifo_out_rw_set_last 44
-
-/* Register rs_rd_data, scope iop_fifo_out, type rs */
-typedef unsigned int reg_iop_fifo_out_rs_rd_data;
-#define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48
-
-/* Register r_rd_data, scope iop_fifo_out, type r */
-typedef unsigned int reg_iop_fifo_out_r_rd_data;
-#define REG_RD_ADDR_iop_fifo_out_r_rd_data 52
-
-/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
-typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out;
-#define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56
-#define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56
-
-/* Register rw_intr_mask, scope iop_fifo_out, type rw */
-typedef struct {
-  unsigned int urun      : 1;
-  unsigned int last_data : 1;
-  unsigned int dav       : 1;
-  unsigned int free      : 1;
-  unsigned int orun      : 1;
-  unsigned int dummy1    : 27;
-} reg_iop_fifo_out_rw_intr_mask;
-#define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60
-#define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60
-
-/* Register rw_ack_intr, scope iop_fifo_out, type rw */
-typedef struct {
-  unsigned int urun      : 1;
-  unsigned int last_data : 1;
-  unsigned int dav       : 1;
-  unsigned int free      : 1;
-  unsigned int orun      : 1;
-  unsigned int dummy1    : 27;
-} reg_iop_fifo_out_rw_ack_intr;
-#define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64
-#define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64
-
-/* Register r_intr, scope iop_fifo_out, type r */
-typedef struct {
-  unsigned int urun      : 1;
-  unsigned int last_data : 1;
-  unsigned int dav       : 1;
-  unsigned int free      : 1;
-  unsigned int orun      : 1;
-  unsigned int dummy1    : 27;
-} reg_iop_fifo_out_r_intr;
-#define REG_RD_ADDR_iop_fifo_out_r_intr 68
-
-/* Register r_masked_intr, scope iop_fifo_out, type r */
-typedef struct {
-  unsigned int urun      : 1;
-  unsigned int last_data : 1;
-  unsigned int dav       : 1;
-  unsigned int free      : 1;
-  unsigned int orun      : 1;
-  unsigned int dummy1    : 27;
-} reg_iop_fifo_out_r_masked_intr;
-#define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72
-
-
-/* Constants */
-enum {
-  regk_iop_fifo_out_hi                     = 0x00000000,
-  regk_iop_fifo_out_neg                    = 0x00000002,
-  regk_iop_fifo_out_no                     = 0x00000000,
-  regk_iop_fifo_out_order16                = 0x00000001,
-  regk_iop_fifo_out_order24                = 0x00000002,
-  regk_iop_fifo_out_order32                = 0x00000003,
-  regk_iop_fifo_out_order8                 = 0x00000000,
-  regk_iop_fifo_out_pos                    = 0x00000001,
-  regk_iop_fifo_out_pos_neg                = 0x00000003,
-  regk_iop_fifo_out_rw_cfg_default         = 0x00000024,
-  regk_iop_fifo_out_rw_ctrl_default        = 0x00000000,
-  regk_iop_fifo_out_rw_intr_mask_default   = 0x00000000,
-  regk_iop_fifo_out_rw_set_last_default    = 0x00000000,
-  regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000,
-  regk_iop_fifo_out_rw_wr1byte_default     = 0x00000000,
-  regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000,
-  regk_iop_fifo_out_rw_wr2byte_default     = 0x00000000,
-  regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000,
-  regk_iop_fifo_out_rw_wr3byte_default     = 0x00000000,
-  regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000,
-  regk_iop_fifo_out_rw_wr4byte_default     = 0x00000000,
-  regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000,
-  regk_iop_fifo_out_size16                 = 0x00000002,
-  regk_iop_fifo_out_size24                 = 0x00000001,
-  regk_iop_fifo_out_size32                 = 0x00000000,
-  regk_iop_fifo_out_size8                  = 0x00000003,
-  regk_iop_fifo_out_yes                    = 0x00000001
-};
-#endif /* __iop_fifo_out_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h
deleted file mode 100644
index 4a840aae84ee..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h
+++ /dev/null
@@ -1,164 +0,0 @@
-#ifndef __iop_fifo_out_extra_defs_h
-#define __iop_fifo_out_extra_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_fifo_out_extra.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:10 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
- *      id: $Id: iop_fifo_out_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_fifo_out_extra */
-
-/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */
-typedef unsigned int reg_iop_fifo_out_extra_rs_rd_data;
-#define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0
-
-/* Register r_rd_data, scope iop_fifo_out_extra, type r */
-typedef unsigned int reg_iop_fifo_out_extra_r_rd_data;
-#define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4
-
-/* Register r_stat, scope iop_fifo_out_extra, type r */
-typedef struct {
-  unsigned int avail_bytes    : 4;
-  unsigned int last           : 8;
-  unsigned int dif_in_en      : 1;
-  unsigned int dif_out_en     : 1;
-  unsigned int zero_data_last : 1;
-  unsigned int dummy1         : 17;
-} reg_iop_fifo_out_extra_r_stat;
-#define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8
-
-/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
-typedef unsigned int reg_iop_fifo_out_extra_rw_strb_dif_out;
-#define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
-#define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
-
-/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
-typedef struct {
-  unsigned int urun      : 1;
-  unsigned int last_data : 1;
-  unsigned int dav       : 1;
-  unsigned int free      : 1;
-  unsigned int orun      : 1;
-  unsigned int dummy1    : 27;
-} reg_iop_fifo_out_extra_rw_intr_mask;
-#define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16
-#define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16
-
-/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
-typedef struct {
-  unsigned int urun      : 1;
-  unsigned int last_data : 1;
-  unsigned int dav       : 1;
-  unsigned int free      : 1;
-  unsigned int orun      : 1;
-  unsigned int dummy1    : 27;
-} reg_iop_fifo_out_extra_rw_ack_intr;
-#define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20
-#define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20
-
-/* Register r_intr, scope iop_fifo_out_extra, type r */
-typedef struct {
-  unsigned int urun      : 1;
-  unsigned int last_data : 1;
-  unsigned int dav       : 1;
-  unsigned int free      : 1;
-  unsigned int orun      : 1;
-  unsigned int dummy1    : 27;
-} reg_iop_fifo_out_extra_r_intr;
-#define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24
-
-/* Register r_masked_intr, scope iop_fifo_out_extra, type r */
-typedef struct {
-  unsigned int urun      : 1;
-  unsigned int last_data : 1;
-  unsigned int dav       : 1;
-  unsigned int free      : 1;
-  unsigned int orun      : 1;
-  unsigned int dummy1    : 27;
-} reg_iop_fifo_out_extra_r_masked_intr;
-#define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28
-
-
-/* Constants */
-enum {
-  regk_iop_fifo_out_extra_no               = 0x00000000,
-  regk_iop_fifo_out_extra_rw_intr_mask_default = 0x00000000,
-  regk_iop_fifo_out_extra_yes              = 0x00000001
-};
-#endif /* __iop_fifo_out_extra_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h
deleted file mode 100644
index c2b0ba1be60f..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h
+++ /dev/null
@@ -1,190 +0,0 @@
-#ifndef __iop_mpu_defs_h
-#define __iop_mpu_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_mpu.r
- *     id:           iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:45 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_mpu_defs.h ../../inst/io_proc/rtl/iop_mpu.r
- *      id: $Id: iop_mpu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_mpu */
-
-#define STRIDE_iop_mpu_rw_r 4
-/* Register rw_r, scope iop_mpu, type rw */
-typedef unsigned int reg_iop_mpu_rw_r;
-#define REG_RD_ADDR_iop_mpu_rw_r 0
-#define REG_WR_ADDR_iop_mpu_rw_r 0
-
-/* Register rw_ctrl, scope iop_mpu, type rw */
-typedef struct {
-  unsigned int en : 1;
-  unsigned int dummy1 : 31;
-} reg_iop_mpu_rw_ctrl;
-#define REG_RD_ADDR_iop_mpu_rw_ctrl 128
-#define REG_WR_ADDR_iop_mpu_rw_ctrl 128
-
-/* Register r_pc, scope iop_mpu, type r */
-typedef struct {
-  unsigned int addr : 12;
-  unsigned int dummy1 : 20;
-} reg_iop_mpu_r_pc;
-#define REG_RD_ADDR_iop_mpu_r_pc 132
-
-/* Register r_stat, scope iop_mpu, type r */
-typedef struct {
-  unsigned int instr_reg_busy : 1;
-  unsigned int intr_busy      : 1;
-  unsigned int intr_vect      : 16;
-  unsigned int dummy1         : 14;
-} reg_iop_mpu_r_stat;
-#define REG_RD_ADDR_iop_mpu_r_stat 136
-
-/* Register rw_instr, scope iop_mpu, type rw */
-typedef unsigned int reg_iop_mpu_rw_instr;
-#define REG_RD_ADDR_iop_mpu_rw_instr 140
-#define REG_WR_ADDR_iop_mpu_rw_instr 140
-
-/* Register rw_immediate, scope iop_mpu, type rw */
-typedef unsigned int reg_iop_mpu_rw_immediate;
-#define REG_RD_ADDR_iop_mpu_rw_immediate 144
-#define REG_WR_ADDR_iop_mpu_rw_immediate 144
-
-/* Register r_trace, scope iop_mpu, type r */
-typedef struct {
-  unsigned int intr_vect      : 16;
-  unsigned int pc             : 12;
-  unsigned int en             : 1;
-  unsigned int instr_reg_busy : 1;
-  unsigned int intr_busy      : 1;
-  unsigned int dummy1         : 1;
-} reg_iop_mpu_r_trace;
-#define REG_RD_ADDR_iop_mpu_r_trace 148
-
-/* Register r_wr_stat, scope iop_mpu, type r */
-typedef struct {
-  unsigned int r0  : 1;
-  unsigned int r1  : 1;
-  unsigned int r2  : 1;
-  unsigned int r3  : 1;
-  unsigned int r4  : 1;
-  unsigned int r5  : 1;
-  unsigned int r6  : 1;
-  unsigned int r7  : 1;
-  unsigned int r8  : 1;
-  unsigned int r9  : 1;
-  unsigned int r10 : 1;
-  unsigned int r11 : 1;
-  unsigned int r12 : 1;
-  unsigned int r13 : 1;
-  unsigned int r14 : 1;
-  unsigned int r15 : 1;
-  unsigned int dummy1 : 16;
-} reg_iop_mpu_r_wr_stat;
-#define REG_RD_ADDR_iop_mpu_r_wr_stat 152
-
-#define STRIDE_iop_mpu_rw_thread 4
-/* Register rw_thread, scope iop_mpu, type rw */
-typedef struct {
-  unsigned int addr : 12;
-  unsigned int dummy1 : 20;
-} reg_iop_mpu_rw_thread;
-#define REG_RD_ADDR_iop_mpu_rw_thread 156
-#define REG_WR_ADDR_iop_mpu_rw_thread 156
-
-#define STRIDE_iop_mpu_rw_intr 4
-/* Register rw_intr, scope iop_mpu, type rw */
-typedef struct {
-  unsigned int addr : 12;
-  unsigned int dummy1 : 20;
-} reg_iop_mpu_rw_intr;
-#define REG_RD_ADDR_iop_mpu_rw_intr 196
-#define REG_WR_ADDR_iop_mpu_rw_intr 196
-
-
-/* Constants */
-enum {
-  regk_iop_mpu_no                          = 0x00000000,
-  regk_iop_mpu_r_pc_default                = 0x00000000,
-  regk_iop_mpu_rw_ctrl_default             = 0x00000000,
-  regk_iop_mpu_rw_intr_size                = 0x00000010,
-  regk_iop_mpu_rw_r_size                   = 0x00000010,
-  regk_iop_mpu_rw_thread_default           = 0x00000000,
-  regk_iop_mpu_rw_thread_size              = 0x00000004,
-  regk_iop_mpu_yes                         = 0x00000001
-};
-#endif /* __iop_mpu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h
deleted file mode 100644
index 2ec897ced166..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h
+++ /dev/null
@@ -1,764 +0,0 @@
-/* ************************************************************************* */
-/* This file is autogenerated by IOPASM Version 1.2                          */
-/* DO NOT EDIT THIS FILE - All changes will be lost!                         */
-/* ************************************************************************* */
-
-
-
-#ifndef __IOP_MPU_MACROS_H__
-#define __IOP_MPU_MACROS_H__
-
-
-/* ************************************************************************* */
-/*                           REGISTER DEFINITIONS                            */
-/* ************************************************************************* */
-#define MPU_R0 (0x0)
-#define MPU_R1 (0x1)
-#define MPU_R2 (0x2)
-#define MPU_R3 (0x3)
-#define MPU_R4 (0x4)
-#define MPU_R5 (0x5)
-#define MPU_R6 (0x6)
-#define MPU_R7 (0x7)
-#define MPU_R8 (0x8)
-#define MPU_R9 (0x9)
-#define MPU_R10 (0xa)
-#define MPU_R11 (0xb)
-#define MPU_R12 (0xc)
-#define MPU_R13 (0xd)
-#define MPU_R14 (0xe)
-#define MPU_R15 (0xf)
-#define MPU_PC (0x2)
-#define MPU_WSTS (0x3)
-#define MPU_JADDR (0x4)
-#define MPU_IRP (0x5)
-#define MPU_SRP (0x6)
-#define MPU_T0 (0x8)
-#define MPU_T1 (0x9)
-#define MPU_T2 (0xa)
-#define MPU_T3 (0xb)
-#define MPU_I0 (0x10)
-#define MPU_I1 (0x11)
-#define MPU_I2 (0x12)
-#define MPU_I3 (0x13)
-#define MPU_I4 (0x14)
-#define MPU_I5 (0x15)
-#define MPU_I6 (0x16)
-#define MPU_I7 (0x17)
-#define MPU_I8 (0x18)
-#define MPU_I9 (0x19)
-#define MPU_I10 (0x1a)
-#define MPU_I11 (0x1b)
-#define MPU_I12 (0x1c)
-#define MPU_I13 (0x1d)
-#define MPU_I14 (0x1e)
-#define MPU_I15 (0x1f)
-#define MPU_P2 (0x2)
-#define MPU_P3 (0x3)
-#define MPU_P5 (0x5)
-#define MPU_P6 (0x6)
-#define MPU_P8 (0x8)
-#define MPU_P9 (0x9)
-#define MPU_P10 (0xa)
-#define MPU_P11 (0xb)
-#define MPU_P16 (0x10)
-#define MPU_P17 (0x12)
-#define MPU_P18 (0x12)
-#define MPU_P19 (0x13)
-#define MPU_P20 (0x14)
-#define MPU_P21 (0x15)
-#define MPU_P22 (0x16)
-#define MPU_P23 (0x17)
-#define MPU_P24 (0x18)
-#define MPU_P25 (0x19)
-#define MPU_P26 (0x1a)
-#define MPU_P27 (0x1b)
-#define MPU_P28 (0x1c)
-#define MPU_P29 (0x1d)
-#define MPU_P30 (0x1e)
-#define MPU_P31 (0x1f)
-#define MPU_P1 (0x1)
-#define MPU_REGA (0x1)
-
-
-
-/* ************************************************************************* */
-/*                              ADDRESS MACROS                               */
-/* ************************************************************************* */
-#define MK_DWORD_ADDR(ADDR) (ADDR >> 2)
-#define MK_BYTE_ADDR(ADDR) (ADDR)
-
-
-
-/* ************************************************************************* */
-/*                            INSTRUCTION MACROS                             */
-/* ************************************************************************* */
-#define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\
-                                 | ((N & ((1 << 16) - 1)) << 0)\
-                                 | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\
-                                 | ((N & ((1 << 5) - 1)) << 16)\
-                                 | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_IRR_INSTR(S,N,D) (0xC000008C | ((N & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ADDX_RIR_INSTR(S,N,D) (0xC000008C | ((S & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ADDX_ISR_INSTR(S,N,D) (0xC000028C | ((N & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ADDX_SIR_INSTR(S,N,D) (0xC000028C | ((S & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ADDX_IRS_INSTR(S,N,D) (0xC000048C | ((N & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ADDX_RIS_INSTR(S,N,D) (0xC000048C | ((S & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ADDX_ISS_INSTR(S,N,D) (0xC000068C | ((N & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ADDX_SIS_INSTR(S,N,D) (0xC000068C | ((S & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_AND_RRR(S,N,D) (0x4000008A | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_RRS(S,N,D) (0x4000048A | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_RSR(S,N,D) (0x4000018A | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_RSS(S,N,D) (0x4000058A | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_SRR(S,N,D) (0x4000028A | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_SRS(S,N,D) (0x4000068A | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_SSR(S,N,D) (0x4000038A | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_SSS(S,N,D) (0x4000078A | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDQ_RIR(S,N,D) (0x08000000 | ((S & ((1 << 5) - 1)) << 16)\
-                                 | ((N & ((1 << 16) - 1)) << 0)\
-                                 | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDQ_IRR(S,N,D) (0x08000000 | ((S & ((1 << 16) - 1)) << 0)\
-                                 | ((N & ((1 << 5) - 1)) << 16)\
-                                 | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_RIR_INSTR(S,N,D) (0xC000008A | ((S & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ANDX_IRR_INSTR(S,N,D) (0xC000008A | ((N & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ANDX_ISR_INSTR(S,N,D) (0xC000028A | ((N & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ANDX_SIR_INSTR(S,N,D) (0xC000028A | ((S & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ANDX_IRS_INSTR(S,N,D) (0xC000048A | ((N & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ANDX_ISS_INSTR(S,N,D) (0xC000068A | ((N & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ANDX_RIS_INSTR(S,N,D) (0xC000048A | ((S & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ANDX_SIS_INSTR(S,N,D) (0xC000068A | ((S & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_BA_I(S) (0x60000000 | ((S & ((1 << 16) - 1)) << 0))
-
-#define MPU_BAR_R(S) (0x62000000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_BAR_S(S) (0x63000000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_BBC_RII(S,N,D) (0x78000000 | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 21)\
-                                | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_BBS_RII(S,N,D) (0x7C000000 | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 21)\
-                                | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_BNZ_RI(S,D) (0x74400000 | ((S & ((1 << 5) - 1)) << 16)\
-                             | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_BMI_RI(S,D) (0x7FE00000 | ((S & ((1 << 5) - 1)) << 16)\
-                             | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_BPL_RI(S,D) (0x7BE00000 | ((S & ((1 << 5) - 1)) << 16)\
-                             | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_BZ_RI(S,D) (0x74000000 | ((S & ((1 << 5) - 1)) << 16)\
-                            | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_DI() (0x40000001)
-
-#define MPU_EI() (0x40000003)
-
-#define MPU_HALT() (0x40000002)
-
-#define MPU_JIR_I(S) (0x60200000 | ((S & ((1 << 16) - 1)) << 0))
-
-#define MPU_JIR_R(S) (0x62200000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_JIR_S(S) (0x63200000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_JNT() (0x61000000)
-
-#define MPU_JSR_I(S) (0x60400000 | ((S & ((1 << 16) - 1)) << 0))
-
-#define MPU_JSR_R(S) (0x62400000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_JSR_S(S) (0x63400000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_LSL_RRR(S,N,D) (0x4000008E | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_RRS(S,N,D) (0x4000048E | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_RSR(S,N,D) (0x4000018E | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_RSS(S,N,D) (0x4000058E | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_SRR(S,N,D) (0x4000028E | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_SRS(S,N,D) (0x4000068E | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_SSR(S,N,D) (0x4000038E | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_SSS(S,N,D) (0x4000078E | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSLQ_RIR(S,N,D) (0x18000000 | ((S & ((1 << 5) - 1)) << 16)\
-                                 | ((N & ((1 << 16) - 1)) << 0)\
-                                 | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_RRR(S,N,D) (0x4000008F | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_RRS(S,N,D) (0x4000048F | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_RSR(S,N,D) (0x4000018F | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_RSS(S,N,D) (0x4000058F | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_SRR(S,N,D) (0x4000028F | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_SRS(S,N,D) (0x4000068F | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_SSR(S,N,D) (0x4000038F | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_SSS(S,N,D) (0x4000078F | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSRQ_RIR(S,N,D) (0x1C000000 | ((S & ((1 << 5) - 1)) << 16)\
-                                 | ((N & ((1 << 16) - 1)) << 0)\
-                                 | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LW_IR(S,D) (0x64400000 | ((S & ((1 << 16) - 1)) << 0)\
-                            | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_IS(S,D) (0x64600000 | ((S & ((1 << 16) - 1)) << 0)\
-                            | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_RR(S,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
-                            | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_RS(S,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
-                            | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_SR(S,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
-                            | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_SS(S,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
-                            | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_RIR(S,N,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
-                               | ((N & ((1 << 8) - 1)) << 0)\
-                               | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_RIS(S,N,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
-                               | ((N & ((1 << 8) - 1)) << 0)\
-                               | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_SIR(S,N,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
-                               | ((N & ((1 << 8) - 1)) << 0)\
-                               | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_SIS(S,N,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
-                               | ((N & ((1 << 8) - 1)) << 0)\
-                               | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_MOVE_RR(S,D) (0x40000081 | ((S & ((1 << 5) - 1)) << 11)\
-                              | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVE_RS(S,D) (0x40000481 | ((S & ((1 << 5) - 1)) << 11)\
-                              | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVE_SR(S,D) (0x40000181 | ((S & ((1 << 5) - 1)) << 11)\
-                              | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVE_SS(S,D) (0x40000581 | ((S & ((1 << 5) - 1)) << 11)\
-                              | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVEQ_IR(S,D) (0x24000000 | ((S & ((1 << 16) - 1)) << 0)\
-                               | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVEQ_IS(S,D) (0x2C000000 | ((S & ((1 << 16) - 1)) << 0)\
-                               | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVEX_IR_INSTR(S,D) (0xC0000081 | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVEX_IR_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_MOVEX_IS_INSTR(S,D) (0xC0000481 | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVEX_IS_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_NOP() (0x40000000)
-
-#define MPU_NOT_RR(S,D) (0x40100081 | ((S & ((1 << 5) - 1)) << 11)\
-                             | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_NOT_RS(S,D) (0x40100481 | ((S & ((1 << 5) - 1)) << 11)\
-                             | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_NOT_SR(S,D) (0x40100181 | ((S & ((1 << 5) - 1)) << 11)\
-                             | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_NOT_SS(S,D) (0x40100581 | ((S & ((1 << 5) - 1)) << 11)\
-                             | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_RRR(S,N,D) (0x4000008B | ((S & ((1 << 5) - 1)) << 16)\
-                               | ((N & ((1 << 5) - 1)) << 11)\
-                               | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_RRS(S,N,D) (0x4000048B | ((S & ((1 << 5) - 1)) << 16)\
-                               | ((N & ((1 << 5) - 1)) << 11)\
-                               | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_RSR(S,N,D) (0x4000018B | ((S & ((1 << 5) - 1)) << 16)\
-                               | ((N & ((1 << 5) - 1)) << 11)\
-                               | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_RSS(S,N,D) (0x4000058B | ((S & ((1 << 5) - 1)) << 16)\
-                               | ((N & ((1 << 5) - 1)) << 11)\
-                               | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_SRR(S,N,D) (0x4000028B | ((S & ((1 << 5) - 1)) << 16)\
-                               | ((N & ((1 << 5) - 1)) << 11)\
-                               | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_SRS(S,N,D) (0x4000068B | ((S & ((1 << 5) - 1)) << 16)\
-                               | ((N & ((1 << 5) - 1)) << 11)\
-                               | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_SSR(S,N,D) (0x4000038B | ((S & ((1 << 5) - 1)) << 16)\
-                               | ((N & ((1 << 5) - 1)) << 11)\
-                               | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_SSS(S,N,D) (0x4000078B | ((S & ((1 << 5) - 1)) << 16)\
-                               | ((N & ((1 << 5) - 1)) << 11)\
-                               | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORQ_RIR(S,N,D) (0x0C000000 | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 16) - 1)) << 0)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORQ_IRR(S,N,D) (0x0C000000 | ((S & ((1 << 16) - 1)) << 0)\
-                                | ((N & ((1 << 5) - 1)) << 16)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_RIR_INSTR(S,N,D) (0xC000008B | ((S & ((1 << 5) - 1)) << 16)\
-                                      | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ORX_IRR_INSTR(S,N,D) (0xC000008B | ((N & ((1 << 5) - 1)) << 16)\
-                                      | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ORX_SIR_INSTR(S,N,D) (0xC000028B | ((S & ((1 << 5) - 1)) << 16)\
-                                      | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ORX_ISR_INSTR(S,N,D) (0xC000028B | ((N & ((1 << 5) - 1)) << 16)\
-                                      | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ORX_RIS_INSTR(S,N,D) (0xC000048B | ((S & ((1 << 5) - 1)) << 16)\
-                                      | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ORX_IRS_INSTR(S,N,D) (0xC000048B | ((N & ((1 << 5) - 1)) << 16)\
-                                      | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ORX_SIS_INSTR(S,N,D) (0xC000068B | ((S & ((1 << 5) - 1)) << 16)\
-                                      | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ORX_ISS_INSTR(S,N,D) (0xC000068B | ((N & ((1 << 5) - 1)) << 16)\
-                                      | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_RET() (0x63003000)
-
-#define MPU_RETI() (0x63602800)
-
-#define MPU_RR_IR(S,D) (0x50000000 | ((S & ((1 << 11) - 1)) << 0)\
-                            | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_RR_SR(S,D) (0x50008000 | ((S & ((1 << 5) - 1)) << 16)\
-                            | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_RW_RI(S,D) (0x56000000 | ((S & ((1 << 5) - 1)) << 11)\
-                            | ((D & ((1 << 11) - 1)) << 0))
-
-#define MPU_RW_RS(S,D) (0x57000000 | ((S & ((1 << 5) - 1)) << 11)\
-                            | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_RWQ_II(S,D) (0x58000000 | ((S & ((1 << 16) - 1)) << 11)\
-                             | ((D & ((1 << 11) - 1)) << 0))
-
-#define MPU_RWQ_IS(S,D) (0x55000000 | ((S & ((1 << 16) - 1)) << 0)\
-                             | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_RWX_II_INSTR(S,D) (0xD4000000 | ((D & ((1 << 11) - 1)) << 0))
-
-#define MPU_RWX_II_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_RWX_IS_INSTR(S,D) (0xD5000000 | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_RWX_IS_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_SUB_RRR(S,N,D) (0x4000008D | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_RRS(S,N,D) (0x4000048D | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_RSR(S,N,D) (0x4000018D | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_RSS(S,N,D) (0x4000058D | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_SRR(S,N,D) (0x4000028D | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_SRS(S,N,D) (0x4000068D | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_SSR(S,N,D) (0x4000038D | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_SSS(S,N,D) (0x4000078D | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBQ_RIR(S,N,D) (0x14000000 | ((S & ((1 << 5) - 1)) << 16)\
-                                 | ((N & ((1 << 16) - 1)) << 0)\
-                                 | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBX_RIR_INSTR(S,N,D) (0xC000008D | ((S & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_SUBX_SIR_INSTR(S,N,D) (0xC000028D | ((S & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_SUBX_RIS_INSTR(S,N,D) (0xC000048D | ((S & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_SUBX_SIS_INSTR(S,N,D) (0xC000068D | ((S & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_SW_RI(S,D) (0x64000000 | ((S & ((1 << 5) - 1)) << 16)\
-                            | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_SW_SI(S,D) (0x64200000 | ((S & ((1 << 5) - 1)) << 16)\
-                            | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_SW_RR(S,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
-                            | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_SR(S,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
-                            | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_RS(S,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
-                            | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_SS(S,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
-                            | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_RIR(S,N,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
-                               | ((N & ((1 << 8) - 1)) << 0)\
-                               | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_SIR(S,N,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
-                               | ((N & ((1 << 8) - 1)) << 0)\
-                               | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_RIS(S,N,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
-                               | ((N & ((1 << 8) - 1)) << 0)\
-                               | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_SIS(S,N,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
-                               | ((N & ((1 << 8) - 1)) << 0)\
-                               | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SWX_II_INSTR(S,D) (0xE4000000 | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_SWX_II_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_SWX_IR_INSTR(S,D) (0xE6000000 | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SWX_IR_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_SWX_IS_INSTR(S,D) (0xE7000000 | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SWX_IS_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_SWX_IIR_INSTR(S,N,D) (0xE6000000 | ((N & ((1 << 8) - 1)) << 0)\
-                                      | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SWX_IIR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_SWX_IIS_INSTR(S,N,D) (0xE7000000 | ((N & ((1 << 8) - 1)) << 0)\
-                                      | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SWX_IIS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_XOR_RRR(S,N,D) (0x40000089 | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_RRS(S,N,D) (0x40000489 | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_RSR(S,N,D) (0x40000189 | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_RSS(S,N,D) (0x40000589 | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SRR(S,N,D) (0x40000289 | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SRS(S,N,D) (0x40000689 | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SSR(S,N,D) (0x40000389 | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SSS(S,N,D) (0x40000789 | ((S & ((1 << 5) - 1)) << 16)\
-                                | ((N & ((1 << 5) - 1)) << 11)\
-                                | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_RR(S,D) (0x40000088 | ((S & ((1 << 5) - 1)) << 11)\
-                             | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_RS(S,D) (0x40000488 | ((S & ((1 << 5) - 1)) << 11)\
-                             | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SR(S,D) (0x40000188 | ((S & ((1 << 5) - 1)) << 11)\
-                             | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SS(S,D) (0x40000588 | ((S & ((1 << 5) - 1)) << 11)\
-                             | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORQ_RIR(S,N,D) (0x04000000 | ((S & ((1 << 5) - 1)) << 16)\
-                                 | ((N & ((1 << 16) - 1)) << 0)\
-                                 | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORQ_IRR(S,N,D) (0x04000000 | ((S & ((1 << 16) - 1)) << 0)\
-                                 | ((N & ((1 << 5) - 1)) << 16)\
-                                 | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_RIR_INSTR(S,N,D) (0xC0000089 | ((S & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_XORX_IRR_INSTR(S,N,D) (0xC0000089 | ((N & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_XORX_SIR_INSTR(S,N,D) (0xC0000289 | ((S & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_XORX_ISR_INSTR(S,N,D) (0xC0000289 | ((N & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_XORX_RIS_INSTR(S,N,D) (0xC0000489 | ((S & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_XORX_IRS_INSTR(S,N,D) (0xC0000489 | ((N & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_XORX_SIS_INSTR(S,N,D) (0xC0000689 | ((S & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_XORX_ISS_INSTR(S,N,D) (0xC0000689 | ((N & ((1 << 5) - 1)) << 16)\
-                                       | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-
-#endif /* end of __IOP_MPU_MACROS_H__ */
-/* End of iop_mpu_macros.h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h b/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h
deleted file mode 100644
index 756550f5d6cb..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Autogenerated Changes here will be lost!
- * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg
- */
-#define regi_iop_version (regi_iop + 0)
-#define regi_iop_fifo_in0_extra (regi_iop + 64)
-#define regi_iop_fifo_in1_extra (regi_iop + 128)
-#define regi_iop_fifo_out0_extra (regi_iop + 192)
-#define regi_iop_fifo_out1_extra (regi_iop + 256)
-#define regi_iop_trigger_grp0 (regi_iop + 320)
-#define regi_iop_trigger_grp1 (regi_iop + 384)
-#define regi_iop_trigger_grp2 (regi_iop + 448)
-#define regi_iop_trigger_grp3 (regi_iop + 512)
-#define regi_iop_trigger_grp4 (regi_iop + 576)
-#define regi_iop_trigger_grp5 (regi_iop + 640)
-#define regi_iop_trigger_grp6 (regi_iop + 704)
-#define regi_iop_trigger_grp7 (regi_iop + 768)
-#define regi_iop_crc_par0 (regi_iop + 896)
-#define regi_iop_crc_par1 (regi_iop + 1024)
-#define regi_iop_dmc_in0 (regi_iop + 1152)
-#define regi_iop_dmc_in1 (regi_iop + 1280)
-#define regi_iop_dmc_out0 (regi_iop + 1408)
-#define regi_iop_dmc_out1 (regi_iop + 1536)
-#define regi_iop_fifo_in0 (regi_iop + 1664)
-#define regi_iop_fifo_in1 (regi_iop + 1792)
-#define regi_iop_fifo_out0 (regi_iop + 1920)
-#define regi_iop_fifo_out1 (regi_iop + 2048)
-#define regi_iop_scrc_in0 (regi_iop + 2176)
-#define regi_iop_scrc_in1 (regi_iop + 2304)
-#define regi_iop_scrc_out0 (regi_iop + 2432)
-#define regi_iop_scrc_out1 (regi_iop + 2560)
-#define regi_iop_timer_grp0 (regi_iop + 2688)
-#define regi_iop_timer_grp1 (regi_iop + 2816)
-#define regi_iop_timer_grp2 (regi_iop + 2944)
-#define regi_iop_timer_grp3 (regi_iop + 3072)
-#define regi_iop_sap_in (regi_iop + 3328)
-#define regi_iop_sap_out (regi_iop + 3584)
-#define regi_iop_spu0 (regi_iop + 3840)
-#define regi_iop_spu1 (regi_iop + 4096)
-#define regi_iop_sw_cfg (regi_iop + 4352)
-#define regi_iop_sw_cpu (regi_iop + 4608)
-#define regi_iop_sw_mpu (regi_iop + 4864)
-#define regi_iop_sw_spu0 (regi_iop + 5120)
-#define regi_iop_sw_spu1 (regi_iop + 5376)
-#define regi_iop_mpu (regi_iop + 5632)
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h
deleted file mode 100644
index 5548ac10074f..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h
+++ /dev/null
@@ -1,179 +0,0 @@
-#ifndef __iop_sap_in_defs_h
-#define __iop_sap_in_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_sap_in.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:08:45 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_in_defs.h ../../inst/io_proc/rtl/iop_sap_in.r
- *      id: $Id: iop_sap_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sap_in */
-
-/* Register rw_bus0_sync, scope iop_sap_in, type rw */
-typedef struct {
-  unsigned int byte0_sel     : 2;
-  unsigned int byte0_ext_src : 3;
-  unsigned int byte0_edge    : 2;
-  unsigned int byte0_delay   : 1;
-  unsigned int byte1_sel     : 2;
-  unsigned int byte1_ext_src : 3;
-  unsigned int byte1_edge    : 2;
-  unsigned int byte1_delay   : 1;
-  unsigned int byte2_sel     : 2;
-  unsigned int byte2_ext_src : 3;
-  unsigned int byte2_edge    : 2;
-  unsigned int byte2_delay   : 1;
-  unsigned int byte3_sel     : 2;
-  unsigned int byte3_ext_src : 3;
-  unsigned int byte3_edge    : 2;
-  unsigned int byte3_delay   : 1;
-} reg_iop_sap_in_rw_bus0_sync;
-#define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0
-#define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0
-
-/* Register rw_bus1_sync, scope iop_sap_in, type rw */
-typedef struct {
-  unsigned int byte0_sel     : 2;
-  unsigned int byte0_ext_src : 3;
-  unsigned int byte0_edge    : 2;
-  unsigned int byte0_delay   : 1;
-  unsigned int byte1_sel     : 2;
-  unsigned int byte1_ext_src : 3;
-  unsigned int byte1_edge    : 2;
-  unsigned int byte1_delay   : 1;
-  unsigned int byte2_sel     : 2;
-  unsigned int byte2_ext_src : 3;
-  unsigned int byte2_edge    : 2;
-  unsigned int byte2_delay   : 1;
-  unsigned int byte3_sel     : 2;
-  unsigned int byte3_ext_src : 3;
-  unsigned int byte3_edge    : 2;
-  unsigned int byte3_delay   : 1;
-} reg_iop_sap_in_rw_bus1_sync;
-#define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4
-#define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4
-
-#define STRIDE_iop_sap_in_rw_gio 4
-/* Register rw_gio, scope iop_sap_in, type rw */
-typedef struct {
-  unsigned int sync_sel     : 2;
-  unsigned int sync_ext_src : 3;
-  unsigned int sync_edge    : 2;
-  unsigned int delay        : 1;
-  unsigned int logic        : 2;
-  unsigned int dummy1       : 22;
-} reg_iop_sap_in_rw_gio;
-#define REG_RD_ADDR_iop_sap_in_rw_gio 8
-#define REG_WR_ADDR_iop_sap_in_rw_gio 8
-
-
-/* Constants */
-enum {
-  regk_iop_sap_in_and                      = 0x00000002,
-  regk_iop_sap_in_ext_clk200               = 0x00000003,
-  regk_iop_sap_in_gio1                     = 0x00000000,
-  regk_iop_sap_in_gio13                    = 0x00000005,
-  regk_iop_sap_in_gio18                    = 0x00000003,
-  regk_iop_sap_in_gio19                    = 0x00000004,
-  regk_iop_sap_in_gio21                    = 0x00000006,
-  regk_iop_sap_in_gio23                    = 0x00000005,
-  regk_iop_sap_in_gio29                    = 0x00000007,
-  regk_iop_sap_in_gio5                     = 0x00000004,
-  regk_iop_sap_in_gio6                     = 0x00000001,
-  regk_iop_sap_in_gio7                     = 0x00000002,
-  regk_iop_sap_in_inv                      = 0x00000001,
-  regk_iop_sap_in_neg                      = 0x00000002,
-  regk_iop_sap_in_no                       = 0x00000000,
-  regk_iop_sap_in_no_del_ext_clk200        = 0x00000001,
-  regk_iop_sap_in_none                     = 0x00000000,
-  regk_iop_sap_in_or                       = 0x00000003,
-  regk_iop_sap_in_pos                      = 0x00000001,
-  regk_iop_sap_in_pos_neg                  = 0x00000003,
-  regk_iop_sap_in_rw_bus0_sync_default     = 0x02020202,
-  regk_iop_sap_in_rw_bus1_sync_default     = 0x02020202,
-  regk_iop_sap_in_rw_gio_default           = 0x00000002,
-  regk_iop_sap_in_rw_gio_size              = 0x00000020,
-  regk_iop_sap_in_timer_grp0_tmr3          = 0x00000006,
-  regk_iop_sap_in_timer_grp1_tmr3          = 0x00000004,
-  regk_iop_sap_in_timer_grp2_tmr3          = 0x00000005,
-  regk_iop_sap_in_timer_grp3_tmr3          = 0x00000007,
-  regk_iop_sap_in_tmr_clk200               = 0x00000000,
-  regk_iop_sap_in_two_clk200               = 0x00000002,
-  regk_iop_sap_in_yes                      = 0x00000001
-};
-#endif /* __iop_sap_in_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h
deleted file mode 100644
index 273936996183..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h
+++ /dev/null
@@ -1,306 +0,0 @@
-#ifndef __iop_sap_out_defs_h
-#define __iop_sap_out_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_sap_out.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_out_defs.h ../../inst/io_proc/rtl/iop_sap_out.r
- *      id: $Id: iop_sap_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sap_out */
-
-/* Register rw_gen_gated, scope iop_sap_out, type rw */
-typedef struct {
-  unsigned int clk0_src       : 2;
-  unsigned int clk0_gate_src  : 2;
-  unsigned int clk0_force_src : 3;
-  unsigned int clk1_src       : 2;
-  unsigned int clk1_gate_src  : 2;
-  unsigned int clk1_force_src : 3;
-  unsigned int clk2_src       : 2;
-  unsigned int clk2_gate_src  : 2;
-  unsigned int clk2_force_src : 3;
-  unsigned int clk3_src       : 2;
-  unsigned int clk3_gate_src  : 2;
-  unsigned int clk3_force_src : 3;
-  unsigned int dummy1         : 4;
-} reg_iop_sap_out_rw_gen_gated;
-#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0
-#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0
-
-/* Register rw_bus0, scope iop_sap_out, type rw */
-typedef struct {
-  unsigned int byte0_clk_sel   : 3;
-  unsigned int byte0_gated_clk : 2;
-  unsigned int byte0_clk_inv   : 1;
-  unsigned int byte1_clk_sel   : 3;
-  unsigned int byte1_gated_clk : 2;
-  unsigned int byte1_clk_inv   : 1;
-  unsigned int byte2_clk_sel   : 3;
-  unsigned int byte2_gated_clk : 2;
-  unsigned int byte2_clk_inv   : 1;
-  unsigned int byte3_clk_sel   : 3;
-  unsigned int byte3_gated_clk : 2;
-  unsigned int byte3_clk_inv   : 1;
-  unsigned int dummy1          : 8;
-} reg_iop_sap_out_rw_bus0;
-#define REG_RD_ADDR_iop_sap_out_rw_bus0 4
-#define REG_WR_ADDR_iop_sap_out_rw_bus0 4
-
-/* Register rw_bus1, scope iop_sap_out, type rw */
-typedef struct {
-  unsigned int byte0_clk_sel   : 3;
-  unsigned int byte0_gated_clk : 2;
-  unsigned int byte0_clk_inv   : 1;
-  unsigned int byte1_clk_sel   : 3;
-  unsigned int byte1_gated_clk : 2;
-  unsigned int byte1_clk_inv   : 1;
-  unsigned int byte2_clk_sel   : 3;
-  unsigned int byte2_gated_clk : 2;
-  unsigned int byte2_clk_inv   : 1;
-  unsigned int byte3_clk_sel   : 3;
-  unsigned int byte3_gated_clk : 2;
-  unsigned int byte3_clk_inv   : 1;
-  unsigned int dummy1          : 8;
-} reg_iop_sap_out_rw_bus1;
-#define REG_RD_ADDR_iop_sap_out_rw_bus1 8
-#define REG_WR_ADDR_iop_sap_out_rw_bus1 8
-
-/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */
-typedef struct {
-  unsigned int byte0_clk_sel   : 3;
-  unsigned int byte0_clk_ext   : 3;
-  unsigned int byte0_gated_clk : 2;
-  unsigned int byte0_clk_inv   : 1;
-  unsigned int byte0_logic     : 2;
-  unsigned int byte1_clk_sel   : 3;
-  unsigned int byte1_clk_ext   : 3;
-  unsigned int byte1_gated_clk : 2;
-  unsigned int byte1_clk_inv   : 1;
-  unsigned int byte1_logic     : 2;
-  unsigned int dummy1          : 10;
-} reg_iop_sap_out_rw_bus0_lo_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus0_lo_oe 12
-#define REG_WR_ADDR_iop_sap_out_rw_bus0_lo_oe 12
-
-/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */
-typedef struct {
-  unsigned int byte2_clk_sel   : 3;
-  unsigned int byte2_clk_ext   : 3;
-  unsigned int byte2_gated_clk : 2;
-  unsigned int byte2_clk_inv   : 1;
-  unsigned int byte2_logic     : 2;
-  unsigned int byte3_clk_sel   : 3;
-  unsigned int byte3_clk_ext   : 3;
-  unsigned int byte3_gated_clk : 2;
-  unsigned int byte3_clk_inv   : 1;
-  unsigned int byte3_logic     : 2;
-  unsigned int dummy1          : 10;
-} reg_iop_sap_out_rw_bus0_hi_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus0_hi_oe 16
-#define REG_WR_ADDR_iop_sap_out_rw_bus0_hi_oe 16
-
-/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */
-typedef struct {
-  unsigned int byte0_clk_sel   : 3;
-  unsigned int byte0_clk_ext   : 3;
-  unsigned int byte0_gated_clk : 2;
-  unsigned int byte0_clk_inv   : 1;
-  unsigned int byte0_logic     : 2;
-  unsigned int byte1_clk_sel   : 3;
-  unsigned int byte1_clk_ext   : 3;
-  unsigned int byte1_gated_clk : 2;
-  unsigned int byte1_clk_inv   : 1;
-  unsigned int byte1_logic     : 2;
-  unsigned int dummy1          : 10;
-} reg_iop_sap_out_rw_bus1_lo_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus1_lo_oe 20
-#define REG_WR_ADDR_iop_sap_out_rw_bus1_lo_oe 20
-
-/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */
-typedef struct {
-  unsigned int byte2_clk_sel   : 3;
-  unsigned int byte2_clk_ext   : 3;
-  unsigned int byte2_gated_clk : 2;
-  unsigned int byte2_clk_inv   : 1;
-  unsigned int byte2_logic     : 2;
-  unsigned int byte3_clk_sel   : 3;
-  unsigned int byte3_clk_ext   : 3;
-  unsigned int byte3_gated_clk : 2;
-  unsigned int byte3_clk_inv   : 1;
-  unsigned int byte3_logic     : 2;
-  unsigned int dummy1          : 10;
-} reg_iop_sap_out_rw_bus1_hi_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus1_hi_oe 24
-#define REG_WR_ADDR_iop_sap_out_rw_bus1_hi_oe 24
-
-#define STRIDE_iop_sap_out_rw_gio 4
-/* Register rw_gio, scope iop_sap_out, type rw */
-typedef struct {
-  unsigned int out_clk_sel   : 3;
-  unsigned int out_clk_ext   : 4;
-  unsigned int out_gated_clk : 2;
-  unsigned int out_clk_inv   : 1;
-  unsigned int out_logic     : 1;
-  unsigned int oe_clk_sel    : 3;
-  unsigned int oe_clk_ext    : 3;
-  unsigned int oe_gated_clk  : 2;
-  unsigned int oe_clk_inv    : 1;
-  unsigned int oe_logic      : 2;
-  unsigned int dummy1        : 10;
-} reg_iop_sap_out_rw_gio;
-#define REG_RD_ADDR_iop_sap_out_rw_gio 28
-#define REG_WR_ADDR_iop_sap_out_rw_gio 28
-
-
-/* Constants */
-enum {
-  regk_iop_sap_out_and                     = 0x00000002,
-  regk_iop_sap_out_clk0                    = 0x00000000,
-  regk_iop_sap_out_clk1                    = 0x00000001,
-  regk_iop_sap_out_clk12                   = 0x00000002,
-  regk_iop_sap_out_clk2                    = 0x00000002,
-  regk_iop_sap_out_clk200                  = 0x00000001,
-  regk_iop_sap_out_clk3                    = 0x00000003,
-  regk_iop_sap_out_ext                     = 0x00000003,
-  regk_iop_sap_out_gated                   = 0x00000004,
-  regk_iop_sap_out_gio1                    = 0x00000000,
-  regk_iop_sap_out_gio13                   = 0x00000002,
-  regk_iop_sap_out_gio13_clk               = 0x0000000c,
-  regk_iop_sap_out_gio15                   = 0x00000001,
-  regk_iop_sap_out_gio18                   = 0x00000003,
-  regk_iop_sap_out_gio18_clk               = 0x0000000d,
-  regk_iop_sap_out_gio1_clk                = 0x00000008,
-  regk_iop_sap_out_gio21_clk               = 0x0000000e,
-  regk_iop_sap_out_gio23                   = 0x00000002,
-  regk_iop_sap_out_gio29_clk               = 0x0000000f,
-  regk_iop_sap_out_gio31                   = 0x00000003,
-  regk_iop_sap_out_gio5                    = 0x00000001,
-  regk_iop_sap_out_gio5_clk                = 0x00000009,
-  regk_iop_sap_out_gio6_clk                = 0x0000000a,
-  regk_iop_sap_out_gio7                    = 0x00000000,
-  regk_iop_sap_out_gio7_clk                = 0x0000000b,
-  regk_iop_sap_out_gio_in13                = 0x00000001,
-  regk_iop_sap_out_gio_in21                = 0x00000002,
-  regk_iop_sap_out_gio_in29                = 0x00000003,
-  regk_iop_sap_out_gio_in5                 = 0x00000000,
-  regk_iop_sap_out_inv                     = 0x00000001,
-  regk_iop_sap_out_nand                    = 0x00000003,
-  regk_iop_sap_out_no                      = 0x00000000,
-  regk_iop_sap_out_none                    = 0x00000000,
-  regk_iop_sap_out_rw_bus0_default         = 0x00000000,
-  regk_iop_sap_out_rw_bus0_hi_oe_default   = 0x00000000,
-  regk_iop_sap_out_rw_bus0_lo_oe_default   = 0x00000000,
-  regk_iop_sap_out_rw_bus1_default         = 0x00000000,
-  regk_iop_sap_out_rw_bus1_hi_oe_default   = 0x00000000,
-  regk_iop_sap_out_rw_bus1_lo_oe_default   = 0x00000000,
-  regk_iop_sap_out_rw_gen_gated_default    = 0x00000000,
-  regk_iop_sap_out_rw_gio_default          = 0x00000000,
-  regk_iop_sap_out_rw_gio_size             = 0x00000020,
-  regk_iop_sap_out_spu0_gio0               = 0x00000002,
-  regk_iop_sap_out_spu0_gio1               = 0x00000003,
-  regk_iop_sap_out_spu0_gio12              = 0x00000004,
-  regk_iop_sap_out_spu0_gio13              = 0x00000004,
-  regk_iop_sap_out_spu0_gio14              = 0x00000004,
-  regk_iop_sap_out_spu0_gio15              = 0x00000004,
-  regk_iop_sap_out_spu0_gio2               = 0x00000002,
-  regk_iop_sap_out_spu0_gio3               = 0x00000003,
-  regk_iop_sap_out_spu0_gio4               = 0x00000002,
-  regk_iop_sap_out_spu0_gio5               = 0x00000003,
-  regk_iop_sap_out_spu0_gio6               = 0x00000002,
-  regk_iop_sap_out_spu0_gio7               = 0x00000003,
-  regk_iop_sap_out_spu1_gio0               = 0x00000005,
-  regk_iop_sap_out_spu1_gio1               = 0x00000006,
-  regk_iop_sap_out_spu1_gio12              = 0x00000007,
-  regk_iop_sap_out_spu1_gio13              = 0x00000007,
-  regk_iop_sap_out_spu1_gio14              = 0x00000007,
-  regk_iop_sap_out_spu1_gio15              = 0x00000007,
-  regk_iop_sap_out_spu1_gio2               = 0x00000005,
-  regk_iop_sap_out_spu1_gio3               = 0x00000006,
-  regk_iop_sap_out_spu1_gio4               = 0x00000005,
-  regk_iop_sap_out_spu1_gio5               = 0x00000006,
-  regk_iop_sap_out_spu1_gio6               = 0x00000005,
-  regk_iop_sap_out_spu1_gio7               = 0x00000006,
-  regk_iop_sap_out_timer_grp0_tmr2         = 0x00000004,
-  regk_iop_sap_out_timer_grp1_tmr2         = 0x00000005,
-  regk_iop_sap_out_timer_grp2_tmr2         = 0x00000006,
-  regk_iop_sap_out_timer_grp3_tmr2         = 0x00000007,
-  regk_iop_sap_out_tmr                     = 0x00000005,
-  regk_iop_sap_out_yes                     = 0x00000001
-};
-#endif /* __iop_sap_out_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h
deleted file mode 100644
index 4f0a9a81e737..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h
+++ /dev/null
@@ -1,160 +0,0 @@
-#ifndef __iop_scrc_in_defs_h
-#define __iop_scrc_in_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_scrc_in.r
- *     id:           iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_in_defs.h ../../inst/io_proc/rtl/iop_scrc_in.r
- *      id: $Id: iop_scrc_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_scrc_in */
-
-/* Register rw_cfg, scope iop_scrc_in, type rw */
-typedef struct {
-  unsigned int trig : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_scrc_in_rw_cfg;
-#define REG_RD_ADDR_iop_scrc_in_rw_cfg 0
-#define REG_WR_ADDR_iop_scrc_in_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_scrc_in, type rw */
-typedef struct {
-  unsigned int dif_in_en : 1;
-  unsigned int dummy1    : 31;
-} reg_iop_scrc_in_rw_ctrl;
-#define REG_RD_ADDR_iop_scrc_in_rw_ctrl 4
-#define REG_WR_ADDR_iop_scrc_in_rw_ctrl 4
-
-/* Register r_stat, scope iop_scrc_in, type r */
-typedef struct {
-  unsigned int err : 1;
-  unsigned int dummy1 : 31;
-} reg_iop_scrc_in_r_stat;
-#define REG_RD_ADDR_iop_scrc_in_r_stat 8
-
-/* Register rw_init_crc, scope iop_scrc_in, type rw */
-typedef unsigned int reg_iop_scrc_in_rw_init_crc;
-#define REG_RD_ADDR_iop_scrc_in_rw_init_crc 12
-#define REG_WR_ADDR_iop_scrc_in_rw_init_crc 12
-
-/* Register rs_computed_crc, scope iop_scrc_in, type rs */
-typedef unsigned int reg_iop_scrc_in_rs_computed_crc;
-#define REG_RD_ADDR_iop_scrc_in_rs_computed_crc 16
-
-/* Register r_computed_crc, scope iop_scrc_in, type r */
-typedef unsigned int reg_iop_scrc_in_r_computed_crc;
-#define REG_RD_ADDR_iop_scrc_in_r_computed_crc 20
-
-/* Register rw_crc, scope iop_scrc_in, type rw */
-typedef unsigned int reg_iop_scrc_in_rw_crc;
-#define REG_RD_ADDR_iop_scrc_in_rw_crc 24
-#define REG_WR_ADDR_iop_scrc_in_rw_crc 24
-
-/* Register rw_correct_crc, scope iop_scrc_in, type rw */
-typedef unsigned int reg_iop_scrc_in_rw_correct_crc;
-#define REG_RD_ADDR_iop_scrc_in_rw_correct_crc 28
-#define REG_WR_ADDR_iop_scrc_in_rw_correct_crc 28
-
-/* Register rw_wr1bit, scope iop_scrc_in, type rw */
-typedef struct {
-  unsigned int data : 2;
-  unsigned int last : 2;
-  unsigned int dummy1 : 28;
-} reg_iop_scrc_in_rw_wr1bit;
-#define REG_RD_ADDR_iop_scrc_in_rw_wr1bit 32
-#define REG_WR_ADDR_iop_scrc_in_rw_wr1bit 32
-
-
-/* Constants */
-enum {
-  regk_iop_scrc_in_dif_in                  = 0x00000002,
-  regk_iop_scrc_in_hi                      = 0x00000000,
-  regk_iop_scrc_in_neg                     = 0x00000002,
-  regk_iop_scrc_in_no                      = 0x00000000,
-  regk_iop_scrc_in_pos                     = 0x00000001,
-  regk_iop_scrc_in_pos_neg                 = 0x00000003,
-  regk_iop_scrc_in_r_computed_crc_default  = 0x00000000,
-  regk_iop_scrc_in_rs_computed_crc_default = 0x00000000,
-  regk_iop_scrc_in_rw_cfg_default          = 0x00000000,
-  regk_iop_scrc_in_rw_ctrl_default         = 0x00000000,
-  regk_iop_scrc_in_rw_init_crc_default     = 0x00000000,
-  regk_iop_scrc_in_set0                    = 0x00000000,
-  regk_iop_scrc_in_set1                    = 0x00000001,
-  regk_iop_scrc_in_yes                     = 0x00000001
-};
-#endif /* __iop_scrc_in_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h
deleted file mode 100644
index fd1d6ea1d484..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h
+++ /dev/null
@@ -1,146 +0,0 @@
-#ifndef __iop_scrc_out_defs_h
-#define __iop_scrc_out_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_scrc_out.r
- *     id:           iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_out_defs.h ../../inst/io_proc/rtl/iop_scrc_out.r
- *      id: $Id: iop_scrc_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_scrc_out */
-
-/* Register rw_cfg, scope iop_scrc_out, type rw */
-typedef struct {
-  unsigned int trig    : 2;
-  unsigned int inv_crc : 1;
-  unsigned int dummy1  : 29;
-} reg_iop_scrc_out_rw_cfg;
-#define REG_RD_ADDR_iop_scrc_out_rw_cfg 0
-#define REG_WR_ADDR_iop_scrc_out_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_scrc_out, type rw */
-typedef struct {
-  unsigned int strb_src : 1;
-  unsigned int out_src  : 1;
-  unsigned int dummy1   : 30;
-} reg_iop_scrc_out_rw_ctrl;
-#define REG_RD_ADDR_iop_scrc_out_rw_ctrl 4
-#define REG_WR_ADDR_iop_scrc_out_rw_ctrl 4
-
-/* Register rw_init_crc, scope iop_scrc_out, type rw */
-typedef unsigned int reg_iop_scrc_out_rw_init_crc;
-#define REG_RD_ADDR_iop_scrc_out_rw_init_crc 8
-#define REG_WR_ADDR_iop_scrc_out_rw_init_crc 8
-
-/* Register rw_crc, scope iop_scrc_out, type rw */
-typedef unsigned int reg_iop_scrc_out_rw_crc;
-#define REG_RD_ADDR_iop_scrc_out_rw_crc 12
-#define REG_WR_ADDR_iop_scrc_out_rw_crc 12
-
-/* Register rw_data, scope iop_scrc_out, type rw */
-typedef struct {
-  unsigned int val : 1;
-  unsigned int dummy1 : 31;
-} reg_iop_scrc_out_rw_data;
-#define REG_RD_ADDR_iop_scrc_out_rw_data 16
-#define REG_WR_ADDR_iop_scrc_out_rw_data 16
-
-/* Register r_computed_crc, scope iop_scrc_out, type r */
-typedef unsigned int reg_iop_scrc_out_r_computed_crc;
-#define REG_RD_ADDR_iop_scrc_out_r_computed_crc 20
-
-
-/* Constants */
-enum {
-  regk_iop_scrc_out_crc                    = 0x00000001,
-  regk_iop_scrc_out_data                   = 0x00000000,
-  regk_iop_scrc_out_dif                    = 0x00000001,
-  regk_iop_scrc_out_hi                     = 0x00000000,
-  regk_iop_scrc_out_neg                    = 0x00000002,
-  regk_iop_scrc_out_no                     = 0x00000000,
-  regk_iop_scrc_out_pos                    = 0x00000001,
-  regk_iop_scrc_out_pos_neg                = 0x00000003,
-  regk_iop_scrc_out_reg                    = 0x00000000,
-  regk_iop_scrc_out_rw_cfg_default         = 0x00000000,
-  regk_iop_scrc_out_rw_crc_default         = 0x00000000,
-  regk_iop_scrc_out_rw_ctrl_default        = 0x00000000,
-  regk_iop_scrc_out_rw_data_default        = 0x00000000,
-  regk_iop_scrc_out_rw_init_crc_default    = 0x00000000,
-  regk_iop_scrc_out_yes                    = 0x00000001
-};
-#endif /* __iop_scrc_out_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h
deleted file mode 100644
index 0fda26e2f06f..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h
+++ /dev/null
@@ -1,453 +0,0 @@
-#ifndef __iop_spu_defs_h
-#define __iop_spu_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_spu.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r
- *      id: $Id: iop_spu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_spu */
-
-#define STRIDE_iop_spu_rw_r 4
-/* Register rw_r, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_r;
-#define REG_RD_ADDR_iop_spu_rw_r 0
-#define REG_WR_ADDR_iop_spu_rw_r 0
-
-/* Register rw_seq_pc, scope iop_spu, type rw */
-typedef struct {
-  unsigned int addr : 12;
-  unsigned int dummy1 : 20;
-} reg_iop_spu_rw_seq_pc;
-#define REG_RD_ADDR_iop_spu_rw_seq_pc 64
-#define REG_WR_ADDR_iop_spu_rw_seq_pc 64
-
-/* Register rw_fsm_pc, scope iop_spu, type rw */
-typedef struct {
-  unsigned int addr : 12;
-  unsigned int dummy1 : 20;
-} reg_iop_spu_rw_fsm_pc;
-#define REG_RD_ADDR_iop_spu_rw_fsm_pc 68
-#define REG_WR_ADDR_iop_spu_rw_fsm_pc 68
-
-/* Register rw_ctrl, scope iop_spu, type rw */
-typedef struct {
-  unsigned int fsm : 1;
-  unsigned int en  : 1;
-  unsigned int dummy1 : 30;
-} reg_iop_spu_rw_ctrl;
-#define REG_RD_ADDR_iop_spu_rw_ctrl 72
-#define REG_WR_ADDR_iop_spu_rw_ctrl 72
-
-/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
-typedef struct {
-  unsigned int val0 : 5;
-  unsigned int src0 : 3;
-  unsigned int val1 : 5;
-  unsigned int src1 : 3;
-  unsigned int val2 : 5;
-  unsigned int src2 : 3;
-  unsigned int val3 : 5;
-  unsigned int src3 : 3;
-} reg_iop_spu_rw_fsm_inputs3_0;
-#define REG_RD_ADDR_iop_spu_rw_fsm_inputs3_0 76
-#define REG_WR_ADDR_iop_spu_rw_fsm_inputs3_0 76
-
-/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
-typedef struct {
-  unsigned int val4 : 5;
-  unsigned int src4 : 3;
-  unsigned int val5 : 5;
-  unsigned int src5 : 3;
-  unsigned int val6 : 5;
-  unsigned int src6 : 3;
-  unsigned int val7 : 5;
-  unsigned int src7 : 3;
-} reg_iop_spu_rw_fsm_inputs7_4;
-#define REG_RD_ADDR_iop_spu_rw_fsm_inputs7_4 80
-#define REG_WR_ADDR_iop_spu_rw_fsm_inputs7_4 80
-
-/* Register rw_gio_out, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_gio_out;
-#define REG_RD_ADDR_iop_spu_rw_gio_out 84
-#define REG_WR_ADDR_iop_spu_rw_gio_out 84
-
-/* Register rw_bus0_out, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_bus0_out;
-#define REG_RD_ADDR_iop_spu_rw_bus0_out 88
-#define REG_WR_ADDR_iop_spu_rw_bus0_out 88
-
-/* Register rw_bus1_out, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_bus1_out;
-#define REG_RD_ADDR_iop_spu_rw_bus1_out 92
-#define REG_WR_ADDR_iop_spu_rw_bus1_out 92
-
-/* Register r_gio_in, scope iop_spu, type r */
-typedef unsigned int reg_iop_spu_r_gio_in;
-#define REG_RD_ADDR_iop_spu_r_gio_in 96
-
-/* Register r_bus0_in, scope iop_spu, type r */
-typedef unsigned int reg_iop_spu_r_bus0_in;
-#define REG_RD_ADDR_iop_spu_r_bus0_in 100
-
-/* Register r_bus1_in, scope iop_spu, type r */
-typedef unsigned int reg_iop_spu_r_bus1_in;
-#define REG_RD_ADDR_iop_spu_r_bus1_in 104
-
-/* Register rw_gio_out_set, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_gio_out_set;
-#define REG_RD_ADDR_iop_spu_rw_gio_out_set 108
-#define REG_WR_ADDR_iop_spu_rw_gio_out_set 108
-
-/* Register rw_gio_out_clr, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_gio_out_clr;
-#define REG_RD_ADDR_iop_spu_rw_gio_out_clr 112
-#define REG_WR_ADDR_iop_spu_rw_gio_out_clr 112
-
-/* Register rs_wr_stat, scope iop_spu, type rs */
-typedef struct {
-  unsigned int r0  : 1;
-  unsigned int r1  : 1;
-  unsigned int r2  : 1;
-  unsigned int r3  : 1;
-  unsigned int r4  : 1;
-  unsigned int r5  : 1;
-  unsigned int r6  : 1;
-  unsigned int r7  : 1;
-  unsigned int r8  : 1;
-  unsigned int r9  : 1;
-  unsigned int r10 : 1;
-  unsigned int r11 : 1;
-  unsigned int r12 : 1;
-  unsigned int r13 : 1;
-  unsigned int r14 : 1;
-  unsigned int r15 : 1;
-  unsigned int dummy1 : 16;
-} reg_iop_spu_rs_wr_stat;
-#define REG_RD_ADDR_iop_spu_rs_wr_stat 116
-
-/* Register r_wr_stat, scope iop_spu, type r */
-typedef struct {
-  unsigned int r0  : 1;
-  unsigned int r1  : 1;
-  unsigned int r2  : 1;
-  unsigned int r3  : 1;
-  unsigned int r4  : 1;
-  unsigned int r5  : 1;
-  unsigned int r6  : 1;
-  unsigned int r7  : 1;
-  unsigned int r8  : 1;
-  unsigned int r9  : 1;
-  unsigned int r10 : 1;
-  unsigned int r11 : 1;
-  unsigned int r12 : 1;
-  unsigned int r13 : 1;
-  unsigned int r14 : 1;
-  unsigned int r15 : 1;
-  unsigned int dummy1 : 16;
-} reg_iop_spu_r_wr_stat;
-#define REG_RD_ADDR_iop_spu_r_wr_stat 120
-
-/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */
-typedef unsigned int reg_iop_spu_r_reg_indexed_by_bus0_in;
-#define REG_RD_ADDR_iop_spu_r_reg_indexed_by_bus0_in 124
-
-/* Register r_stat_in, scope iop_spu, type r */
-typedef struct {
-  unsigned int timer_grp_lo    : 4;
-  unsigned int fifo_out_last   : 1;
-  unsigned int fifo_out_rdy    : 1;
-  unsigned int fifo_out_all    : 1;
-  unsigned int fifo_in_rdy     : 1;
-  unsigned int dmc_out_all     : 1;
-  unsigned int dmc_out_dth     : 1;
-  unsigned int dmc_out_eop     : 1;
-  unsigned int dmc_out_dv      : 1;
-  unsigned int dmc_out_last    : 1;
-  unsigned int dmc_out_cmd_rq  : 1;
-  unsigned int dmc_out_cmd_rdy : 1;
-  unsigned int pcrc_correct    : 1;
-  unsigned int timer_grp_hi    : 4;
-  unsigned int dmc_in_sth      : 1;
-  unsigned int dmc_in_full     : 1;
-  unsigned int dmc_in_cmd_rdy  : 1;
-  unsigned int spu_gio_out     : 4;
-  unsigned int sync_clk12      : 1;
-  unsigned int scrc_out_data   : 1;
-  unsigned int scrc_in_err     : 1;
-  unsigned int mc_busy         : 1;
-  unsigned int mc_owned        : 1;
-} reg_iop_spu_r_stat_in;
-#define REG_RD_ADDR_iop_spu_r_stat_in 128
-
-/* Register r_trigger_in, scope iop_spu, type r */
-typedef unsigned int reg_iop_spu_r_trigger_in;
-#define REG_RD_ADDR_iop_spu_r_trigger_in 132
-
-/* Register r_special_stat, scope iop_spu, type r */
-typedef struct {
-  unsigned int c_flag         : 1;
-  unsigned int v_flag         : 1;
-  unsigned int z_flag         : 1;
-  unsigned int n_flag         : 1;
-  unsigned int xor_bus0_r2_0  : 1;
-  unsigned int xor_bus1_r3_0  : 1;
-  unsigned int xor_bus0m_r2_0 : 1;
-  unsigned int xor_bus1m_r3_0 : 1;
-  unsigned int fsm_in0        : 1;
-  unsigned int fsm_in1        : 1;
-  unsigned int fsm_in2        : 1;
-  unsigned int fsm_in3        : 1;
-  unsigned int fsm_in4        : 1;
-  unsigned int fsm_in5        : 1;
-  unsigned int fsm_in6        : 1;
-  unsigned int fsm_in7        : 1;
-  unsigned int event0         : 1;
-  unsigned int event1         : 1;
-  unsigned int event2         : 1;
-  unsigned int event3         : 1;
-  unsigned int dummy1         : 12;
-} reg_iop_spu_r_special_stat;
-#define REG_RD_ADDR_iop_spu_r_special_stat 136
-
-/* Register rw_reg_access, scope iop_spu, type rw */
-typedef struct {
-  unsigned int addr   : 13;
-  unsigned int dummy1 : 3;
-  unsigned int imm_hi : 16;
-} reg_iop_spu_rw_reg_access;
-#define REG_RD_ADDR_iop_spu_rw_reg_access 140
-#define REG_WR_ADDR_iop_spu_rw_reg_access 140
-
-#define STRIDE_iop_spu_rw_event_cfg 4
-/* Register rw_event_cfg, scope iop_spu, type rw */
-typedef struct {
-  unsigned int addr   : 12;
-  unsigned int src    : 2;
-  unsigned int eq_en  : 1;
-  unsigned int eq_inv : 1;
-  unsigned int gt_en  : 1;
-  unsigned int gt_inv : 1;
-  unsigned int dummy1 : 14;
-} reg_iop_spu_rw_event_cfg;
-#define REG_RD_ADDR_iop_spu_rw_event_cfg 144
-#define REG_WR_ADDR_iop_spu_rw_event_cfg 144
-
-#define STRIDE_iop_spu_rw_event_mask 4
-/* Register rw_event_mask, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_event_mask;
-#define REG_RD_ADDR_iop_spu_rw_event_mask 160
-#define REG_WR_ADDR_iop_spu_rw_event_mask 160
-
-#define STRIDE_iop_spu_rw_event_val 4
-/* Register rw_event_val, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_event_val;
-#define REG_RD_ADDR_iop_spu_rw_event_val 176
-#define REG_WR_ADDR_iop_spu_rw_event_val 176
-
-/* Register rw_event_ret, scope iop_spu, type rw */
-typedef struct {
-  unsigned int addr : 12;
-  unsigned int dummy1 : 20;
-} reg_iop_spu_rw_event_ret;
-#define REG_RD_ADDR_iop_spu_rw_event_ret 192
-#define REG_WR_ADDR_iop_spu_rw_event_ret 192
-
-/* Register r_trace, scope iop_spu, type r */
-typedef struct {
-  unsigned int fsm      : 1;
-  unsigned int en       : 1;
-  unsigned int c_flag   : 1;
-  unsigned int v_flag   : 1;
-  unsigned int z_flag   : 1;
-  unsigned int n_flag   : 1;
-  unsigned int seq_addr : 12;
-  unsigned int dummy1   : 2;
-  unsigned int fsm_addr : 12;
-} reg_iop_spu_r_trace;
-#define REG_RD_ADDR_iop_spu_r_trace 196
-
-/* Register r_fsm_trace, scope iop_spu, type r */
-typedef struct {
-  unsigned int fsm      : 1;
-  unsigned int en       : 1;
-  unsigned int tmr_done : 1;
-  unsigned int inp0     : 1;
-  unsigned int inp1     : 1;
-  unsigned int inp2     : 1;
-  unsigned int inp3     : 1;
-  unsigned int event0   : 1;
-  unsigned int event1   : 1;
-  unsigned int event2   : 1;
-  unsigned int event3   : 1;
-  unsigned int gio_out  : 8;
-  unsigned int dummy1   : 1;
-  unsigned int fsm_addr : 12;
-} reg_iop_spu_r_fsm_trace;
-#define REG_RD_ADDR_iop_spu_r_fsm_trace 200
-
-#define STRIDE_iop_spu_rw_brp 4
-/* Register rw_brp, scope iop_spu, type rw */
-typedef struct {
-  unsigned int addr : 12;
-  unsigned int fsm  : 1;
-  unsigned int en   : 1;
-  unsigned int dummy1 : 18;
-} reg_iop_spu_rw_brp;
-#define REG_RD_ADDR_iop_spu_rw_brp 204
-#define REG_WR_ADDR_iop_spu_rw_brp 204
-
-
-/* Constants */
-enum {
-  regk_iop_spu_attn_hi                     = 0x00000005,
-  regk_iop_spu_attn_lo                     = 0x00000005,
-  regk_iop_spu_attn_r0                     = 0x00000000,
-  regk_iop_spu_attn_r1                     = 0x00000001,
-  regk_iop_spu_attn_r10                    = 0x00000002,
-  regk_iop_spu_attn_r11                    = 0x00000003,
-  regk_iop_spu_attn_r12                    = 0x00000004,
-  regk_iop_spu_attn_r13                    = 0x00000005,
-  regk_iop_spu_attn_r14                    = 0x00000006,
-  regk_iop_spu_attn_r15                    = 0x00000007,
-  regk_iop_spu_attn_r2                     = 0x00000002,
-  regk_iop_spu_attn_r3                     = 0x00000003,
-  regk_iop_spu_attn_r4                     = 0x00000004,
-  regk_iop_spu_attn_r5                     = 0x00000005,
-  regk_iop_spu_attn_r6                     = 0x00000006,
-  regk_iop_spu_attn_r7                     = 0x00000007,
-  regk_iop_spu_attn_r8                     = 0x00000000,
-  regk_iop_spu_attn_r9                     = 0x00000001,
-  regk_iop_spu_c                           = 0x00000000,
-  regk_iop_spu_flag                        = 0x00000002,
-  regk_iop_spu_gio_in                      = 0x00000000,
-  regk_iop_spu_gio_out                     = 0x00000005,
-  regk_iop_spu_gio_out0                    = 0x00000008,
-  regk_iop_spu_gio_out1                    = 0x00000009,
-  regk_iop_spu_gio_out2                    = 0x0000000a,
-  regk_iop_spu_gio_out3                    = 0x0000000b,
-  regk_iop_spu_gio_out4                    = 0x0000000c,
-  regk_iop_spu_gio_out5                    = 0x0000000d,
-  regk_iop_spu_gio_out6                    = 0x0000000e,
-  regk_iop_spu_gio_out7                    = 0x0000000f,
-  regk_iop_spu_n                           = 0x00000003,
-  regk_iop_spu_no                          = 0x00000000,
-  regk_iop_spu_r0                          = 0x00000008,
-  regk_iop_spu_r1                          = 0x00000009,
-  regk_iop_spu_r10                         = 0x0000000a,
-  regk_iop_spu_r11                         = 0x0000000b,
-  regk_iop_spu_r12                         = 0x0000000c,
-  regk_iop_spu_r13                         = 0x0000000d,
-  regk_iop_spu_r14                         = 0x0000000e,
-  regk_iop_spu_r15                         = 0x0000000f,
-  regk_iop_spu_r2                          = 0x0000000a,
-  regk_iop_spu_r3                          = 0x0000000b,
-  regk_iop_spu_r4                          = 0x0000000c,
-  regk_iop_spu_r5                          = 0x0000000d,
-  regk_iop_spu_r6                          = 0x0000000e,
-  regk_iop_spu_r7                          = 0x0000000f,
-  regk_iop_spu_r8                          = 0x00000008,
-  regk_iop_spu_r9                          = 0x00000009,
-  regk_iop_spu_reg_hi                      = 0x00000002,
-  regk_iop_spu_reg_lo                      = 0x00000002,
-  regk_iop_spu_rw_brp_default              = 0x00000000,
-  regk_iop_spu_rw_brp_size                 = 0x00000004,
-  regk_iop_spu_rw_ctrl_default             = 0x00000000,
-  regk_iop_spu_rw_event_cfg_size           = 0x00000004,
-  regk_iop_spu_rw_event_mask_size          = 0x00000004,
-  regk_iop_spu_rw_event_val_size           = 0x00000004,
-  regk_iop_spu_rw_gio_out_default          = 0x00000000,
-  regk_iop_spu_rw_r_size                   = 0x00000010,
-  regk_iop_spu_rw_reg_access_default       = 0x00000000,
-  regk_iop_spu_stat_in                     = 0x00000002,
-  regk_iop_spu_statin_hi                   = 0x00000004,
-  regk_iop_spu_statin_lo                   = 0x00000004,
-  regk_iop_spu_trig                        = 0x00000003,
-  regk_iop_spu_trigger                     = 0x00000006,
-  regk_iop_spu_v                           = 0x00000001,
-  regk_iop_spu_wsts_gioout_spec            = 0x00000001,
-  regk_iop_spu_xor                         = 0x00000003,
-  regk_iop_spu_xor_bus0_r2_0               = 0x00000000,
-  regk_iop_spu_xor_bus0m_r2_0              = 0x00000002,
-  regk_iop_spu_xor_bus1_r3_0               = 0x00000001,
-  regk_iop_spu_xor_bus1m_r3_0              = 0x00000003,
-  regk_iop_spu_yes                         = 0x00000001,
-  regk_iop_spu_z                           = 0x00000002
-};
-#endif /* __iop_spu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h
deleted file mode 100644
index d7b6d75884d2..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h
+++ /dev/null
@@ -1,1042 +0,0 @@
-#ifndef __iop_sw_cfg_defs_h
-#define __iop_sw_cfg_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:19 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
- *      id: $Id: iop_sw_cfg_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_cfg */
-
-/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_crc_par0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0
-#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0
-
-/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_crc_par1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4
-#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4
-
-/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_in0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8
-
-/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_in1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12
-
-/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_out0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16
-
-/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_out1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20
-
-/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24
-
-/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in0_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28
-
-/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32
-
-/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in1_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36
-
-/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40
-
-/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out0_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44
-
-/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48
-
-/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out1_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52
-
-/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_sap_in_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56
-#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56
-
-/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_sap_out_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60
-#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60
-
-/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_in0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64
-
-/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_in1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68
-
-/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_out0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72
-
-/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_out1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76
-
-/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_spu0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80
-
-/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_spu1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84
-
-/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88
-
-/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92
-
-/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp2_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96
-
-/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp3_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100
-
-/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104
-
-/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108
-
-/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp2_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112
-
-/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp3_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116
-
-/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp4_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120
-
-/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp5_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124
-
-/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp6_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128
-
-/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp7_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132
-
-/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_cfg_rw_bus0_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136
-
-/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_cfg_rw_bus0_oe_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140
-
-/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_cfg_rw_bus1_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144
-
-/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_cfg_rw_bus1_oe_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148
-
-/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_cfg_rw_gio_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152
-
-/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_cfg_rw_gio_oe_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156
-
-/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int bus0_byte0 : 2;
-  unsigned int bus0_byte1 : 2;
-  unsigned int bus0_byte2 : 2;
-  unsigned int bus0_byte3 : 2;
-  unsigned int bus1_byte0 : 2;
-  unsigned int bus1_byte1 : 2;
-  unsigned int bus1_byte2 : 2;
-  unsigned int bus1_byte3 : 2;
-  unsigned int gio3_0     : 2;
-  unsigned int gio7_4     : 2;
-  unsigned int gio11_8    : 2;
-  unsigned int gio15_12   : 2;
-  unsigned int gio19_16   : 2;
-  unsigned int gio23_20   : 2;
-  unsigned int gio27_24   : 2;
-  unsigned int gio31_28   : 2;
-} reg_iop_sw_cfg_rw_pinmapping;
-#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160
-#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160
-
-/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int bus0_lo    : 3;
-  unsigned int bus0_hi    : 3;
-  unsigned int bus0_lo_oe : 3;
-  unsigned int bus0_hi_oe : 3;
-  unsigned int bus1_lo    : 3;
-  unsigned int bus1_hi    : 3;
-  unsigned int bus1_lo_oe : 3;
-  unsigned int bus1_hi_oe : 3;
-  unsigned int dummy1     : 8;
-} reg_iop_sw_cfg_rw_bus_out_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164
-
-/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int gio0    : 4;
-  unsigned int gio0_oe : 2;
-  unsigned int gio1    : 4;
-  unsigned int gio1_oe : 2;
-  unsigned int gio2    : 4;
-  unsigned int gio2_oe : 2;
-  unsigned int gio3    : 4;
-  unsigned int gio3_oe : 2;
-  unsigned int dummy1  : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168
-
-/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int gio4    : 4;
-  unsigned int gio4_oe : 2;
-  unsigned int gio5    : 4;
-  unsigned int gio5_oe : 2;
-  unsigned int gio6    : 4;
-  unsigned int gio6_oe : 2;
-  unsigned int gio7    : 4;
-  unsigned int gio7_oe : 2;
-  unsigned int dummy1  : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172
-
-/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int gio8     : 4;
-  unsigned int gio8_oe  : 2;
-  unsigned int gio9     : 4;
-  unsigned int gio9_oe  : 2;
-  unsigned int gio10    : 4;
-  unsigned int gio10_oe : 2;
-  unsigned int gio11    : 4;
-  unsigned int gio11_oe : 2;
-  unsigned int dummy1   : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp2_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176
-
-/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int gio12    : 4;
-  unsigned int gio12_oe : 2;
-  unsigned int gio13    : 4;
-  unsigned int gio13_oe : 2;
-  unsigned int gio14    : 4;
-  unsigned int gio14_oe : 2;
-  unsigned int gio15    : 4;
-  unsigned int gio15_oe : 2;
-  unsigned int dummy1   : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp3_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180
-
-/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int gio16    : 4;
-  unsigned int gio16_oe : 2;
-  unsigned int gio17    : 4;
-  unsigned int gio17_oe : 2;
-  unsigned int gio18    : 4;
-  unsigned int gio18_oe : 2;
-  unsigned int gio19    : 4;
-  unsigned int gio19_oe : 2;
-  unsigned int dummy1   : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp4_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184
-
-/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int gio20    : 4;
-  unsigned int gio20_oe : 2;
-  unsigned int gio21    : 4;
-  unsigned int gio21_oe : 2;
-  unsigned int gio22    : 4;
-  unsigned int gio22_oe : 2;
-  unsigned int gio23    : 4;
-  unsigned int gio23_oe : 2;
-  unsigned int dummy1   : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp5_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188
-
-/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int gio24    : 4;
-  unsigned int gio24_oe : 2;
-  unsigned int gio25    : 4;
-  unsigned int gio25_oe : 2;
-  unsigned int gio26    : 4;
-  unsigned int gio26_oe : 2;
-  unsigned int gio27    : 4;
-  unsigned int gio27_oe : 2;
-  unsigned int dummy1   : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp6_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192
-
-/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int gio28    : 4;
-  unsigned int gio28_oe : 2;
-  unsigned int gio29    : 4;
-  unsigned int gio29_oe : 2;
-  unsigned int gio30    : 4;
-  unsigned int gio30_oe : 2;
-  unsigned int gio31    : 4;
-  unsigned int gio31_oe : 2;
-  unsigned int dummy1   : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp7_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196
-
-/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int bus0_in : 2;
-  unsigned int bus1_in : 2;
-  unsigned int dummy1  : 28;
-} reg_iop_sw_cfg_rw_spu0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200
-
-/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int bus0_in : 2;
-  unsigned int bus1_in : 2;
-  unsigned int dummy1  : 28;
-} reg_iop_sw_cfg_rw_spu1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204
-
-/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int ext_clk  : 3;
-  unsigned int tmr0_en  : 1;
-  unsigned int tmr1_en  : 1;
-  unsigned int tmr2_en  : 1;
-  unsigned int tmr3_en  : 1;
-  unsigned int tmr0_dis : 1;
-  unsigned int tmr1_dis : 1;
-  unsigned int tmr2_dis : 1;
-  unsigned int tmr3_dis : 1;
-  unsigned int dummy1   : 21;
-} reg_iop_sw_cfg_rw_timer_grp0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208
-
-/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int ext_clk  : 3;
-  unsigned int tmr0_en  : 1;
-  unsigned int tmr1_en  : 1;
-  unsigned int tmr2_en  : 1;
-  unsigned int tmr3_en  : 1;
-  unsigned int tmr0_dis : 1;
-  unsigned int tmr1_dis : 1;
-  unsigned int tmr2_dis : 1;
-  unsigned int tmr3_dis : 1;
-  unsigned int dummy1   : 21;
-} reg_iop_sw_cfg_rw_timer_grp1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212
-
-/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int ext_clk  : 3;
-  unsigned int tmr0_en  : 1;
-  unsigned int tmr1_en  : 1;
-  unsigned int tmr2_en  : 1;
-  unsigned int tmr3_en  : 1;
-  unsigned int tmr0_dis : 1;
-  unsigned int tmr1_dis : 1;
-  unsigned int tmr2_dis : 1;
-  unsigned int tmr3_dis : 1;
-  unsigned int dummy1   : 21;
-} reg_iop_sw_cfg_rw_timer_grp2_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216
-
-/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int ext_clk  : 3;
-  unsigned int tmr0_en  : 1;
-  unsigned int tmr1_en  : 1;
-  unsigned int tmr2_en  : 1;
-  unsigned int tmr3_en  : 1;
-  unsigned int tmr0_dis : 1;
-  unsigned int tmr1_dis : 1;
-  unsigned int tmr2_dis : 1;
-  unsigned int tmr3_dis : 1;
-  unsigned int dummy1   : 21;
-} reg_iop_sw_cfg_rw_timer_grp3_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220
-
-/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int grp0_dis : 1;
-  unsigned int grp0_en  : 1;
-  unsigned int grp1_dis : 1;
-  unsigned int grp1_en  : 1;
-  unsigned int grp2_dis : 1;
-  unsigned int grp2_en  : 1;
-  unsigned int grp3_dis : 1;
-  unsigned int grp3_en  : 1;
-  unsigned int grp4_dis : 1;
-  unsigned int grp4_en  : 1;
-  unsigned int grp5_dis : 1;
-  unsigned int grp5_en  : 1;
-  unsigned int grp6_dis : 1;
-  unsigned int grp6_en  : 1;
-  unsigned int grp7_dis : 1;
-  unsigned int grp7_en  : 1;
-  unsigned int dummy1   : 16;
-} reg_iop_sw_cfg_rw_trigger_grps_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224
-
-/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int dmc0_usr : 1;
-  unsigned int out_strb : 5;
-  unsigned int in_src   : 3;
-  unsigned int in_size  : 3;
-  unsigned int in_last  : 2;
-  unsigned int in_strb  : 4;
-  unsigned int out_src  : 1;
-  unsigned int dummy1   : 13;
-} reg_iop_sw_cfg_rw_pdp0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228
-#define REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228
-
-/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int dmc1_usr : 1;
-  unsigned int out_strb : 5;
-  unsigned int in_src   : 3;
-  unsigned int in_size  : 3;
-  unsigned int in_last  : 2;
-  unsigned int in_strb  : 4;
-  unsigned int out_src  : 1;
-  unsigned int dummy1   : 13;
-} reg_iop_sw_cfg_rw_pdp1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232
-#define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232
-
-/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int sdp_out0_strb : 3;
-  unsigned int sdp_out1_strb : 3;
-  unsigned int sdp_in0_data  : 3;
-  unsigned int sdp_in0_last  : 2;
-  unsigned int sdp_in0_strb  : 3;
-  unsigned int sdp_in1_data  : 3;
-  unsigned int sdp_in1_last  : 2;
-  unsigned int sdp_in1_strb  : 3;
-  unsigned int dummy1        : 10;
-} reg_iop_sw_cfg_rw_sdp_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236
-#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236
-
-
-/* Constants */
-enum {
-  regk_iop_sw_cfg_a                        = 0x00000001,
-  regk_iop_sw_cfg_b                        = 0x00000002,
-  regk_iop_sw_cfg_bus0                     = 0x00000000,
-  regk_iop_sw_cfg_bus0_rot16               = 0x00000004,
-  regk_iop_sw_cfg_bus0_rot24               = 0x00000006,
-  regk_iop_sw_cfg_bus0_rot8                = 0x00000002,
-  regk_iop_sw_cfg_bus1                     = 0x00000001,
-  regk_iop_sw_cfg_bus1_rot16               = 0x00000005,
-  regk_iop_sw_cfg_bus1_rot24               = 0x00000007,
-  regk_iop_sw_cfg_bus1_rot8                = 0x00000003,
-  regk_iop_sw_cfg_clk12                    = 0x00000000,
-  regk_iop_sw_cfg_cpu                      = 0x00000000,
-  regk_iop_sw_cfg_dmc0                     = 0x00000000,
-  regk_iop_sw_cfg_dmc1                     = 0x00000001,
-  regk_iop_sw_cfg_gated_clk0               = 0x00000010,
-  regk_iop_sw_cfg_gated_clk1               = 0x00000011,
-  regk_iop_sw_cfg_gated_clk2               = 0x00000012,
-  regk_iop_sw_cfg_gated_clk3               = 0x00000013,
-  regk_iop_sw_cfg_gio0                     = 0x00000004,
-  regk_iop_sw_cfg_gio1                     = 0x00000001,
-  regk_iop_sw_cfg_gio2                     = 0x00000005,
-  regk_iop_sw_cfg_gio3                     = 0x00000002,
-  regk_iop_sw_cfg_gio4                     = 0x00000006,
-  regk_iop_sw_cfg_gio5                     = 0x00000003,
-  regk_iop_sw_cfg_gio6                     = 0x00000007,
-  regk_iop_sw_cfg_gio7                     = 0x00000004,
-  regk_iop_sw_cfg_gio_in0                  = 0x00000000,
-  regk_iop_sw_cfg_gio_in1                  = 0x00000001,
-  regk_iop_sw_cfg_gio_in10                 = 0x00000002,
-  regk_iop_sw_cfg_gio_in11                 = 0x00000003,
-  regk_iop_sw_cfg_gio_in14                 = 0x00000004,
-  regk_iop_sw_cfg_gio_in15                 = 0x00000005,
-  regk_iop_sw_cfg_gio_in18                 = 0x00000002,
-  regk_iop_sw_cfg_gio_in19                 = 0x00000003,
-  regk_iop_sw_cfg_gio_in20                 = 0x00000004,
-  regk_iop_sw_cfg_gio_in21                 = 0x00000005,
-  regk_iop_sw_cfg_gio_in26                 = 0x00000006,
-  regk_iop_sw_cfg_gio_in27                 = 0x00000007,
-  regk_iop_sw_cfg_gio_in28                 = 0x00000006,
-  regk_iop_sw_cfg_gio_in29                 = 0x00000007,
-  regk_iop_sw_cfg_gio_in4                  = 0x00000000,
-  regk_iop_sw_cfg_gio_in5                  = 0x00000001,
-  regk_iop_sw_cfg_last_timer_grp0_tmr2     = 0x00000001,
-  regk_iop_sw_cfg_last_timer_grp1_tmr2     = 0x00000001,
-  regk_iop_sw_cfg_last_timer_grp2_tmr2     = 0x00000002,
-  regk_iop_sw_cfg_last_timer_grp2_tmr3     = 0x00000003,
-  regk_iop_sw_cfg_last_timer_grp3_tmr2     = 0x00000002,
-  regk_iop_sw_cfg_last_timer_grp3_tmr3     = 0x00000003,
-  regk_iop_sw_cfg_mpu                      = 0x00000001,
-  regk_iop_sw_cfg_none                     = 0x00000000,
-  regk_iop_sw_cfg_par0                     = 0x00000000,
-  regk_iop_sw_cfg_par1                     = 0x00000001,
-  regk_iop_sw_cfg_pdp_out0                 = 0x00000002,
-  regk_iop_sw_cfg_pdp_out0_hi              = 0x00000001,
-  regk_iop_sw_cfg_pdp_out0_hi_rot8         = 0x00000005,
-  regk_iop_sw_cfg_pdp_out0_lo              = 0x00000000,
-  regk_iop_sw_cfg_pdp_out0_lo_rot8         = 0x00000004,
-  regk_iop_sw_cfg_pdp_out1                 = 0x00000003,
-  regk_iop_sw_cfg_pdp_out1_hi              = 0x00000003,
-  regk_iop_sw_cfg_pdp_out1_hi_rot8         = 0x00000005,
-  regk_iop_sw_cfg_pdp_out1_lo              = 0x00000002,
-  regk_iop_sw_cfg_pdp_out1_lo_rot8         = 0x00000004,
-  regk_iop_sw_cfg_rw_bus0_mask_default     = 0x00000000,
-  regk_iop_sw_cfg_rw_bus0_oe_mask_default  = 0x00000000,
-  regk_iop_sw_cfg_rw_bus1_mask_default     = 0x00000000,
-  regk_iop_sw_cfg_rw_bus1_oe_mask_default  = 0x00000000,
-  regk_iop_sw_cfg_rw_bus_out_cfg_default   = 0x00000000,
-  regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_mask_default      = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_oe_mask_default   = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_pdp0_cfg_default      = 0x00000000,
-  regk_iop_sw_cfg_rw_pdp1_cfg_default      = 0x00000000,
-  regk_iop_sw_cfg_rw_pinmapping_default    = 0x55555555,
-  regk_iop_sw_cfg_rw_sap_in_owner_default  = 0x00000000,
-  regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_sdp_cfg_default       = 0x00000000,
-  regk_iop_sw_cfg_rw_spu0_cfg_default      = 0x00000000,
-  regk_iop_sw_cfg_rw_spu0_owner_default    = 0x00000000,
-  regk_iop_sw_cfg_rw_spu1_cfg_default      = 0x00000000,
-  regk_iop_sw_cfg_rw_spu1_owner_default    = 0x00000000,
-  regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_sdp_out0                 = 0x00000008,
-  regk_iop_sw_cfg_sdp_out1                 = 0x00000009,
-  regk_iop_sw_cfg_size16                   = 0x00000002,
-  regk_iop_sw_cfg_size24                   = 0x00000003,
-  regk_iop_sw_cfg_size32                   = 0x00000004,
-  regk_iop_sw_cfg_size8                    = 0x00000001,
-  regk_iop_sw_cfg_spu0                     = 0x00000002,
-  regk_iop_sw_cfg_spu0_bus_out0_hi         = 0x00000006,
-  regk_iop_sw_cfg_spu0_bus_out0_lo         = 0x00000006,
-  regk_iop_sw_cfg_spu0_bus_out1_hi         = 0x00000007,
-  regk_iop_sw_cfg_spu0_bus_out1_lo         = 0x00000007,
-  regk_iop_sw_cfg_spu0_g0                  = 0x0000000e,
-  regk_iop_sw_cfg_spu0_g1                  = 0x0000000e,
-  regk_iop_sw_cfg_spu0_g2                  = 0x0000000e,
-  regk_iop_sw_cfg_spu0_g3                  = 0x0000000e,
-  regk_iop_sw_cfg_spu0_g4                  = 0x0000000e,
-  regk_iop_sw_cfg_spu0_g5                  = 0x0000000e,
-  regk_iop_sw_cfg_spu0_g6                  = 0x0000000e,
-  regk_iop_sw_cfg_spu0_g7                  = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gio0                = 0x00000000,
-  regk_iop_sw_cfg_spu0_gio1                = 0x00000001,
-  regk_iop_sw_cfg_spu0_gio2                = 0x00000000,
-  regk_iop_sw_cfg_spu0_gio5                = 0x00000005,
-  regk_iop_sw_cfg_spu0_gio6                = 0x00000006,
-  regk_iop_sw_cfg_spu0_gio7                = 0x00000007,
-  regk_iop_sw_cfg_spu0_gio_out0            = 0x00000008,
-  regk_iop_sw_cfg_spu0_gio_out1            = 0x00000009,
-  regk_iop_sw_cfg_spu0_gio_out2            = 0x0000000a,
-  regk_iop_sw_cfg_spu0_gio_out3            = 0x0000000b,
-  regk_iop_sw_cfg_spu0_gio_out4            = 0x0000000c,
-  regk_iop_sw_cfg_spu0_gio_out5            = 0x0000000d,
-  regk_iop_sw_cfg_spu0_gio_out6            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gio_out7            = 0x0000000f,
-  regk_iop_sw_cfg_spu0_gioout0             = 0x00000000,
-  regk_iop_sw_cfg_spu0_gioout1             = 0x00000000,
-  regk_iop_sw_cfg_spu0_gioout10            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout11            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout12            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout13            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout14            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout15            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout16            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout17            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout18            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout19            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout2             = 0x00000002,
-  regk_iop_sw_cfg_spu0_gioout20            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout21            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout22            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout23            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout24            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout25            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout26            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout27            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout28            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout29            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout3             = 0x00000002,
-  regk_iop_sw_cfg_spu0_gioout30            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout31            = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout4             = 0x00000004,
-  regk_iop_sw_cfg_spu0_gioout5             = 0x00000004,
-  regk_iop_sw_cfg_spu0_gioout6             = 0x00000006,
-  regk_iop_sw_cfg_spu0_gioout7             = 0x00000006,
-  regk_iop_sw_cfg_spu0_gioout8             = 0x0000000e,
-  regk_iop_sw_cfg_spu0_gioout9             = 0x0000000e,
-  regk_iop_sw_cfg_spu1                     = 0x00000003,
-  regk_iop_sw_cfg_spu1_bus_out0_hi         = 0x00000006,
-  regk_iop_sw_cfg_spu1_bus_out0_lo         = 0x00000006,
-  regk_iop_sw_cfg_spu1_bus_out1_hi         = 0x00000007,
-  regk_iop_sw_cfg_spu1_bus_out1_lo         = 0x00000007,
-  regk_iop_sw_cfg_spu1_g0                  = 0x0000000f,
-  regk_iop_sw_cfg_spu1_g1                  = 0x0000000f,
-  regk_iop_sw_cfg_spu1_g2                  = 0x0000000f,
-  regk_iop_sw_cfg_spu1_g3                  = 0x0000000f,
-  regk_iop_sw_cfg_spu1_g4                  = 0x0000000f,
-  regk_iop_sw_cfg_spu1_g5                  = 0x0000000f,
-  regk_iop_sw_cfg_spu1_g6                  = 0x0000000f,
-  regk_iop_sw_cfg_spu1_g7                  = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gio0                = 0x00000002,
-  regk_iop_sw_cfg_spu1_gio1                = 0x00000003,
-  regk_iop_sw_cfg_spu1_gio2                = 0x00000002,
-  regk_iop_sw_cfg_spu1_gio5                = 0x00000005,
-  regk_iop_sw_cfg_spu1_gio6                = 0x00000006,
-  regk_iop_sw_cfg_spu1_gio7                = 0x00000007,
-  regk_iop_sw_cfg_spu1_gio_out0            = 0x00000008,
-  regk_iop_sw_cfg_spu1_gio_out1            = 0x00000009,
-  regk_iop_sw_cfg_spu1_gio_out2            = 0x0000000a,
-  regk_iop_sw_cfg_spu1_gio_out3            = 0x0000000b,
-  regk_iop_sw_cfg_spu1_gio_out4            = 0x0000000c,
-  regk_iop_sw_cfg_spu1_gio_out5            = 0x0000000d,
-  regk_iop_sw_cfg_spu1_gio_out6            = 0x0000000e,
-  regk_iop_sw_cfg_spu1_gio_out7            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout0             = 0x00000001,
-  regk_iop_sw_cfg_spu1_gioout1             = 0x00000001,
-  regk_iop_sw_cfg_spu1_gioout10            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout11            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout12            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout13            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout14            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout15            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout16            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout17            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout18            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout19            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout2             = 0x00000003,
-  regk_iop_sw_cfg_spu1_gioout20            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout21            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout22            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout23            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout24            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout25            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout26            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout27            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout28            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout29            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout3             = 0x00000003,
-  regk_iop_sw_cfg_spu1_gioout30            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout31            = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout4             = 0x00000005,
-  regk_iop_sw_cfg_spu1_gioout5             = 0x00000005,
-  regk_iop_sw_cfg_spu1_gioout6             = 0x00000007,
-  regk_iop_sw_cfg_spu1_gioout7             = 0x00000007,
-  regk_iop_sw_cfg_spu1_gioout8             = 0x0000000f,
-  regk_iop_sw_cfg_spu1_gioout9             = 0x0000000f,
-  regk_iop_sw_cfg_strb_timer_grp0_tmr0     = 0x00000001,
-  regk_iop_sw_cfg_strb_timer_grp0_tmr1     = 0x00000002,
-  regk_iop_sw_cfg_strb_timer_grp1_tmr0     = 0x00000001,
-  regk_iop_sw_cfg_strb_timer_grp1_tmr1     = 0x00000002,
-  regk_iop_sw_cfg_strb_timer_grp2_tmr0     = 0x00000003,
-  regk_iop_sw_cfg_strb_timer_grp2_tmr1     = 0x00000002,
-  regk_iop_sw_cfg_strb_timer_grp3_tmr0     = 0x00000003,
-  regk_iop_sw_cfg_strb_timer_grp3_tmr1     = 0x00000002,
-  regk_iop_sw_cfg_timer_grp0               = 0x00000000,
-  regk_iop_sw_cfg_timer_grp0_rot           = 0x00000001,
-  regk_iop_sw_cfg_timer_grp0_strb0         = 0x0000000a,
-  regk_iop_sw_cfg_timer_grp0_strb1         = 0x0000000a,
-  regk_iop_sw_cfg_timer_grp0_strb2         = 0x0000000a,
-  regk_iop_sw_cfg_timer_grp0_strb3         = 0x0000000a,
-  regk_iop_sw_cfg_timer_grp0_tmr0          = 0x00000004,
-  regk_iop_sw_cfg_timer_grp0_tmr1          = 0x00000004,
-  regk_iop_sw_cfg_timer_grp1               = 0x00000000,
-  regk_iop_sw_cfg_timer_grp1_rot           = 0x00000001,
-  regk_iop_sw_cfg_timer_grp1_strb0         = 0x0000000b,
-  regk_iop_sw_cfg_timer_grp1_strb1         = 0x0000000b,
-  regk_iop_sw_cfg_timer_grp1_strb2         = 0x0000000b,
-  regk_iop_sw_cfg_timer_grp1_strb3         = 0x0000000b,
-  regk_iop_sw_cfg_timer_grp1_tmr0          = 0x00000005,
-  regk_iop_sw_cfg_timer_grp1_tmr1          = 0x00000005,
-  regk_iop_sw_cfg_timer_grp2               = 0x00000000,
-  regk_iop_sw_cfg_timer_grp2_rot           = 0x00000001,
-  regk_iop_sw_cfg_timer_grp2_strb0         = 0x0000000c,
-  regk_iop_sw_cfg_timer_grp2_strb1         = 0x0000000c,
-  regk_iop_sw_cfg_timer_grp2_strb2         = 0x0000000c,
-  regk_iop_sw_cfg_timer_grp2_strb3         = 0x0000000c,
-  regk_iop_sw_cfg_timer_grp2_tmr0          = 0x00000006,
-  regk_iop_sw_cfg_timer_grp2_tmr1          = 0x00000006,
-  regk_iop_sw_cfg_timer_grp3               = 0x00000000,
-  regk_iop_sw_cfg_timer_grp3_rot           = 0x00000001,
-  regk_iop_sw_cfg_timer_grp3_strb0         = 0x0000000d,
-  regk_iop_sw_cfg_timer_grp3_strb1         = 0x0000000d,
-  regk_iop_sw_cfg_timer_grp3_strb2         = 0x0000000d,
-  regk_iop_sw_cfg_timer_grp3_strb3         = 0x0000000d,
-  regk_iop_sw_cfg_timer_grp3_tmr0          = 0x00000007,
-  regk_iop_sw_cfg_timer_grp3_tmr1          = 0x00000007,
-  regk_iop_sw_cfg_trig0_0                  = 0x00000000,
-  regk_iop_sw_cfg_trig0_1                  = 0x00000000,
-  regk_iop_sw_cfg_trig0_2                  = 0x00000000,
-  regk_iop_sw_cfg_trig0_3                  = 0x00000000,
-  regk_iop_sw_cfg_trig1_0                  = 0x00000000,
-  regk_iop_sw_cfg_trig1_1                  = 0x00000000,
-  regk_iop_sw_cfg_trig1_2                  = 0x00000000,
-  regk_iop_sw_cfg_trig1_3                  = 0x00000000,
-  regk_iop_sw_cfg_trig2_0                  = 0x00000000,
-  regk_iop_sw_cfg_trig2_1                  = 0x00000000,
-  regk_iop_sw_cfg_trig2_2                  = 0x00000000,
-  regk_iop_sw_cfg_trig2_3                  = 0x00000000,
-  regk_iop_sw_cfg_trig3_0                  = 0x00000000,
-  regk_iop_sw_cfg_trig3_1                  = 0x00000000,
-  regk_iop_sw_cfg_trig3_2                  = 0x00000000,
-  regk_iop_sw_cfg_trig3_3                  = 0x00000000,
-  regk_iop_sw_cfg_trig4_0                  = 0x00000001,
-  regk_iop_sw_cfg_trig4_1                  = 0x00000001,
-  regk_iop_sw_cfg_trig4_2                  = 0x00000001,
-  regk_iop_sw_cfg_trig4_3                  = 0x00000001,
-  regk_iop_sw_cfg_trig5_0                  = 0x00000001,
-  regk_iop_sw_cfg_trig5_1                  = 0x00000001,
-  regk_iop_sw_cfg_trig5_2                  = 0x00000001,
-  regk_iop_sw_cfg_trig5_3                  = 0x00000001,
-  regk_iop_sw_cfg_trig6_0                  = 0x00000001,
-  regk_iop_sw_cfg_trig6_1                  = 0x00000001,
-  regk_iop_sw_cfg_trig6_2                  = 0x00000001,
-  regk_iop_sw_cfg_trig6_3                  = 0x00000001,
-  regk_iop_sw_cfg_trig7_0                  = 0x00000001,
-  regk_iop_sw_cfg_trig7_1                  = 0x00000001,
-  regk_iop_sw_cfg_trig7_2                  = 0x00000001,
-  regk_iop_sw_cfg_trig7_3                  = 0x00000001
-};
-#endif /* __iop_sw_cfg_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h
deleted file mode 100644
index 5fed844b19e2..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h
+++ /dev/null
@@ -1,853 +0,0 @@
-#ifndef __iop_sw_cpu_defs_h
-#define __iop_sw_cpu_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:19 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
- *      id: $Id: iop_sw_cpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_cpu */
-
-/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int keep_owner  : 1;
-  unsigned int cmd         : 2;
-  unsigned int size        : 3;
-  unsigned int wr_spu0_mem : 1;
-  unsigned int wr_spu1_mem : 1;
-  unsigned int dummy1      : 24;
-} reg_iop_sw_cpu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 0
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 0
-
-/* Register rw_mc_data, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_cpu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 4
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 4
-
-/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
-typedef unsigned int reg_iop_sw_cpu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 8
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 8
-
-/* Register rs_mc_data, scope iop_sw_cpu, type rs */
-typedef unsigned int reg_iop_sw_cpu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 12
-
-/* Register r_mc_data, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 16
-
-/* Register r_mc_stat, scope iop_sw_cpu, type r */
-typedef struct {
-  unsigned int busy_cpu      : 1;
-  unsigned int busy_mpu      : 1;
-  unsigned int busy_spu0     : 1;
-  unsigned int busy_spu1     : 1;
-  unsigned int owned_by_cpu  : 1;
-  unsigned int owned_by_mpu  : 1;
-  unsigned int owned_by_spu0 : 1;
-  unsigned int owned_by_spu1 : 1;
-  unsigned int dummy1        : 24;
-} reg_iop_sw_cpu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 20
-
-/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus0_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24
-
-/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus0_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask 28
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask 28
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus0_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus0_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36
-
-/* Register r_bus0_in, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_bus0_in;
-#define REG_RD_ADDR_iop_sw_cpu_r_bus0_in 40
-
-/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus1_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44
-
-/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus1_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask 48
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask 48
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus1_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus1_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56
-
-/* Register r_bus1_in, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_bus1_in;
-#define REG_RD_ADDR_iop_sw_cpu_r_bus1_in 60
-
-/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 64
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 64
-
-/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 68
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 68
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76
-
-/* Register r_gio_in, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 80
-
-/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int mpu_0   : 1;
-  unsigned int mpu_1   : 1;
-  unsigned int mpu_2   : 1;
-  unsigned int mpu_3   : 1;
-  unsigned int mpu_4   : 1;
-  unsigned int mpu_5   : 1;
-  unsigned int mpu_6   : 1;
-  unsigned int mpu_7   : 1;
-  unsigned int mpu_8   : 1;
-  unsigned int mpu_9   : 1;
-  unsigned int mpu_10  : 1;
-  unsigned int mpu_11  : 1;
-  unsigned int mpu_12  : 1;
-  unsigned int mpu_13  : 1;
-  unsigned int mpu_14  : 1;
-  unsigned int mpu_15  : 1;
-  unsigned int spu0_0  : 1;
-  unsigned int spu0_1  : 1;
-  unsigned int spu0_2  : 1;
-  unsigned int spu0_3  : 1;
-  unsigned int spu0_4  : 1;
-  unsigned int spu0_5  : 1;
-  unsigned int spu0_6  : 1;
-  unsigned int spu0_7  : 1;
-  unsigned int spu1_8  : 1;
-  unsigned int spu1_9  : 1;
-  unsigned int spu1_10 : 1;
-  unsigned int spu1_11 : 1;
-  unsigned int spu1_12 : 1;
-  unsigned int spu1_13 : 1;
-  unsigned int spu1_14 : 1;
-  unsigned int spu1_15 : 1;
-} reg_iop_sw_cpu_rw_intr0_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 84
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 84
-
-/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int mpu_0   : 1;
-  unsigned int mpu_1   : 1;
-  unsigned int mpu_2   : 1;
-  unsigned int mpu_3   : 1;
-  unsigned int mpu_4   : 1;
-  unsigned int mpu_5   : 1;
-  unsigned int mpu_6   : 1;
-  unsigned int mpu_7   : 1;
-  unsigned int mpu_8   : 1;
-  unsigned int mpu_9   : 1;
-  unsigned int mpu_10  : 1;
-  unsigned int mpu_11  : 1;
-  unsigned int mpu_12  : 1;
-  unsigned int mpu_13  : 1;
-  unsigned int mpu_14  : 1;
-  unsigned int mpu_15  : 1;
-  unsigned int spu0_0  : 1;
-  unsigned int spu0_1  : 1;
-  unsigned int spu0_2  : 1;
-  unsigned int spu0_3  : 1;
-  unsigned int spu0_4  : 1;
-  unsigned int spu0_5  : 1;
-  unsigned int spu0_6  : 1;
-  unsigned int spu0_7  : 1;
-  unsigned int spu1_8  : 1;
-  unsigned int spu1_9  : 1;
-  unsigned int spu1_10 : 1;
-  unsigned int spu1_11 : 1;
-  unsigned int spu1_12 : 1;
-  unsigned int spu1_13 : 1;
-  unsigned int spu1_14 : 1;
-  unsigned int spu1_15 : 1;
-} reg_iop_sw_cpu_rw_ack_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 88
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 88
-
-/* Register r_intr0, scope iop_sw_cpu, type r */
-typedef struct {
-  unsigned int mpu_0   : 1;
-  unsigned int mpu_1   : 1;
-  unsigned int mpu_2   : 1;
-  unsigned int mpu_3   : 1;
-  unsigned int mpu_4   : 1;
-  unsigned int mpu_5   : 1;
-  unsigned int mpu_6   : 1;
-  unsigned int mpu_7   : 1;
-  unsigned int mpu_8   : 1;
-  unsigned int mpu_9   : 1;
-  unsigned int mpu_10  : 1;
-  unsigned int mpu_11  : 1;
-  unsigned int mpu_12  : 1;
-  unsigned int mpu_13  : 1;
-  unsigned int mpu_14  : 1;
-  unsigned int mpu_15  : 1;
-  unsigned int spu0_0  : 1;
-  unsigned int spu0_1  : 1;
-  unsigned int spu0_2  : 1;
-  unsigned int spu0_3  : 1;
-  unsigned int spu0_4  : 1;
-  unsigned int spu0_5  : 1;
-  unsigned int spu0_6  : 1;
-  unsigned int spu0_7  : 1;
-  unsigned int spu1_8  : 1;
-  unsigned int spu1_9  : 1;
-  unsigned int spu1_10 : 1;
-  unsigned int spu1_11 : 1;
-  unsigned int spu1_12 : 1;
-  unsigned int spu1_13 : 1;
-  unsigned int spu1_14 : 1;
-  unsigned int spu1_15 : 1;
-} reg_iop_sw_cpu_r_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr0 92
-
-/* Register r_masked_intr0, scope iop_sw_cpu, type r */
-typedef struct {
-  unsigned int mpu_0   : 1;
-  unsigned int mpu_1   : 1;
-  unsigned int mpu_2   : 1;
-  unsigned int mpu_3   : 1;
-  unsigned int mpu_4   : 1;
-  unsigned int mpu_5   : 1;
-  unsigned int mpu_6   : 1;
-  unsigned int mpu_7   : 1;
-  unsigned int mpu_8   : 1;
-  unsigned int mpu_9   : 1;
-  unsigned int mpu_10  : 1;
-  unsigned int mpu_11  : 1;
-  unsigned int mpu_12  : 1;
-  unsigned int mpu_13  : 1;
-  unsigned int mpu_14  : 1;
-  unsigned int mpu_15  : 1;
-  unsigned int spu0_0  : 1;
-  unsigned int spu0_1  : 1;
-  unsigned int spu0_2  : 1;
-  unsigned int spu0_3  : 1;
-  unsigned int spu0_4  : 1;
-  unsigned int spu0_5  : 1;
-  unsigned int spu0_6  : 1;
-  unsigned int spu0_7  : 1;
-  unsigned int spu1_8  : 1;
-  unsigned int spu1_9  : 1;
-  unsigned int spu1_10 : 1;
-  unsigned int spu1_11 : 1;
-  unsigned int spu1_12 : 1;
-  unsigned int spu1_13 : 1;
-  unsigned int spu1_14 : 1;
-  unsigned int spu1_15 : 1;
-} reg_iop_sw_cpu_r_masked_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 96
-
-/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int mpu_16  : 1;
-  unsigned int mpu_17  : 1;
-  unsigned int mpu_18  : 1;
-  unsigned int mpu_19  : 1;
-  unsigned int mpu_20  : 1;
-  unsigned int mpu_21  : 1;
-  unsigned int mpu_22  : 1;
-  unsigned int mpu_23  : 1;
-  unsigned int mpu_24  : 1;
-  unsigned int mpu_25  : 1;
-  unsigned int mpu_26  : 1;
-  unsigned int mpu_27  : 1;
-  unsigned int mpu_28  : 1;
-  unsigned int mpu_29  : 1;
-  unsigned int mpu_30  : 1;
-  unsigned int mpu_31  : 1;
-  unsigned int spu0_8  : 1;
-  unsigned int spu0_9  : 1;
-  unsigned int spu0_10 : 1;
-  unsigned int spu0_11 : 1;
-  unsigned int spu0_12 : 1;
-  unsigned int spu0_13 : 1;
-  unsigned int spu0_14 : 1;
-  unsigned int spu0_15 : 1;
-  unsigned int spu1_0  : 1;
-  unsigned int spu1_1  : 1;
-  unsigned int spu1_2  : 1;
-  unsigned int spu1_3  : 1;
-  unsigned int spu1_4  : 1;
-  unsigned int spu1_5  : 1;
-  unsigned int spu1_6  : 1;
-  unsigned int spu1_7  : 1;
-} reg_iop_sw_cpu_rw_intr1_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 100
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 100
-
-/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int mpu_16  : 1;
-  unsigned int mpu_17  : 1;
-  unsigned int mpu_18  : 1;
-  unsigned int mpu_19  : 1;
-  unsigned int mpu_20  : 1;
-  unsigned int mpu_21  : 1;
-  unsigned int mpu_22  : 1;
-  unsigned int mpu_23  : 1;
-  unsigned int mpu_24  : 1;
-  unsigned int mpu_25  : 1;
-  unsigned int mpu_26  : 1;
-  unsigned int mpu_27  : 1;
-  unsigned int mpu_28  : 1;
-  unsigned int mpu_29  : 1;
-  unsigned int mpu_30  : 1;
-  unsigned int mpu_31  : 1;
-  unsigned int spu0_8  : 1;
-  unsigned int spu0_9  : 1;
-  unsigned int spu0_10 : 1;
-  unsigned int spu0_11 : 1;
-  unsigned int spu0_12 : 1;
-  unsigned int spu0_13 : 1;
-  unsigned int spu0_14 : 1;
-  unsigned int spu0_15 : 1;
-  unsigned int spu1_0  : 1;
-  unsigned int spu1_1  : 1;
-  unsigned int spu1_2  : 1;
-  unsigned int spu1_3  : 1;
-  unsigned int spu1_4  : 1;
-  unsigned int spu1_5  : 1;
-  unsigned int spu1_6  : 1;
-  unsigned int spu1_7  : 1;
-} reg_iop_sw_cpu_rw_ack_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 104
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 104
-
-/* Register r_intr1, scope iop_sw_cpu, type r */
-typedef struct {
-  unsigned int mpu_16  : 1;
-  unsigned int mpu_17  : 1;
-  unsigned int mpu_18  : 1;
-  unsigned int mpu_19  : 1;
-  unsigned int mpu_20  : 1;
-  unsigned int mpu_21  : 1;
-  unsigned int mpu_22  : 1;
-  unsigned int mpu_23  : 1;
-  unsigned int mpu_24  : 1;
-  unsigned int mpu_25  : 1;
-  unsigned int mpu_26  : 1;
-  unsigned int mpu_27  : 1;
-  unsigned int mpu_28  : 1;
-  unsigned int mpu_29  : 1;
-  unsigned int mpu_30  : 1;
-  unsigned int mpu_31  : 1;
-  unsigned int spu0_8  : 1;
-  unsigned int spu0_9  : 1;
-  unsigned int spu0_10 : 1;
-  unsigned int spu0_11 : 1;
-  unsigned int spu0_12 : 1;
-  unsigned int spu0_13 : 1;
-  unsigned int spu0_14 : 1;
-  unsigned int spu0_15 : 1;
-  unsigned int spu1_0  : 1;
-  unsigned int spu1_1  : 1;
-  unsigned int spu1_2  : 1;
-  unsigned int spu1_3  : 1;
-  unsigned int spu1_4  : 1;
-  unsigned int spu1_5  : 1;
-  unsigned int spu1_6  : 1;
-  unsigned int spu1_7  : 1;
-} reg_iop_sw_cpu_r_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr1 108
-
-/* Register r_masked_intr1, scope iop_sw_cpu, type r */
-typedef struct {
-  unsigned int mpu_16  : 1;
-  unsigned int mpu_17  : 1;
-  unsigned int mpu_18  : 1;
-  unsigned int mpu_19  : 1;
-  unsigned int mpu_20  : 1;
-  unsigned int mpu_21  : 1;
-  unsigned int mpu_22  : 1;
-  unsigned int mpu_23  : 1;
-  unsigned int mpu_24  : 1;
-  unsigned int mpu_25  : 1;
-  unsigned int mpu_26  : 1;
-  unsigned int mpu_27  : 1;
-  unsigned int mpu_28  : 1;
-  unsigned int mpu_29  : 1;
-  unsigned int mpu_30  : 1;
-  unsigned int mpu_31  : 1;
-  unsigned int spu0_8  : 1;
-  unsigned int spu0_9  : 1;
-  unsigned int spu0_10 : 1;
-  unsigned int spu0_11 : 1;
-  unsigned int spu0_12 : 1;
-  unsigned int spu0_13 : 1;
-  unsigned int spu0_14 : 1;
-  unsigned int spu0_15 : 1;
-  unsigned int spu1_0  : 1;
-  unsigned int spu1_1  : 1;
-  unsigned int spu1_2  : 1;
-  unsigned int spu1_3  : 1;
-  unsigned int spu1_4  : 1;
-  unsigned int spu1_5  : 1;
-  unsigned int spu1_6  : 1;
-  unsigned int spu1_7  : 1;
-} reg_iop_sw_cpu_r_masked_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 112
-
-/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int mpu_0           : 1;
-  unsigned int mpu_1           : 1;
-  unsigned int mpu_2           : 1;
-  unsigned int mpu_3           : 1;
-  unsigned int mpu_4           : 1;
-  unsigned int mpu_5           : 1;
-  unsigned int mpu_6           : 1;
-  unsigned int mpu_7           : 1;
-  unsigned int spu0_0          : 1;
-  unsigned int spu0_1          : 1;
-  unsigned int spu0_2          : 1;
-  unsigned int spu0_3          : 1;
-  unsigned int spu0_4          : 1;
-  unsigned int spu0_5          : 1;
-  unsigned int spu0_6          : 1;
-  unsigned int spu0_7          : 1;
-  unsigned int dmc_in0         : 1;
-  unsigned int dmc_out0        : 1;
-  unsigned int fifo_in0        : 1;
-  unsigned int fifo_out0       : 1;
-  unsigned int fifo_in0_extra  : 1;
-  unsigned int fifo_out0_extra : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp0      : 1;
-  unsigned int timer_grp1      : 1;
-} reg_iop_sw_cpu_rw_intr2_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask 116
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask 116
-
-/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int mpu_0  : 1;
-  unsigned int mpu_1  : 1;
-  unsigned int mpu_2  : 1;
-  unsigned int mpu_3  : 1;
-  unsigned int mpu_4  : 1;
-  unsigned int mpu_5  : 1;
-  unsigned int mpu_6  : 1;
-  unsigned int mpu_7  : 1;
-  unsigned int spu0_0 : 1;
-  unsigned int spu0_1 : 1;
-  unsigned int spu0_2 : 1;
-  unsigned int spu0_3 : 1;
-  unsigned int spu0_4 : 1;
-  unsigned int spu0_5 : 1;
-  unsigned int spu0_6 : 1;
-  unsigned int spu0_7 : 1;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_cpu_rw_ack_intr2;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2 120
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2 120
-
-/* Register r_intr2, scope iop_sw_cpu, type r */
-typedef struct {
-  unsigned int mpu_0           : 1;
-  unsigned int mpu_1           : 1;
-  unsigned int mpu_2           : 1;
-  unsigned int mpu_3           : 1;
-  unsigned int mpu_4           : 1;
-  unsigned int mpu_5           : 1;
-  unsigned int mpu_6           : 1;
-  unsigned int mpu_7           : 1;
-  unsigned int spu0_0          : 1;
-  unsigned int spu0_1          : 1;
-  unsigned int spu0_2          : 1;
-  unsigned int spu0_3          : 1;
-  unsigned int spu0_4          : 1;
-  unsigned int spu0_5          : 1;
-  unsigned int spu0_6          : 1;
-  unsigned int spu0_7          : 1;
-  unsigned int dmc_in0         : 1;
-  unsigned int dmc_out0        : 1;
-  unsigned int fifo_in0        : 1;
-  unsigned int fifo_out0       : 1;
-  unsigned int fifo_in0_extra  : 1;
-  unsigned int fifo_out0_extra : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp0      : 1;
-  unsigned int timer_grp1      : 1;
-} reg_iop_sw_cpu_r_intr2;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr2 124
-
-/* Register r_masked_intr2, scope iop_sw_cpu, type r */
-typedef struct {
-  unsigned int mpu_0           : 1;
-  unsigned int mpu_1           : 1;
-  unsigned int mpu_2           : 1;
-  unsigned int mpu_3           : 1;
-  unsigned int mpu_4           : 1;
-  unsigned int mpu_5           : 1;
-  unsigned int mpu_6           : 1;
-  unsigned int mpu_7           : 1;
-  unsigned int spu0_0          : 1;
-  unsigned int spu0_1          : 1;
-  unsigned int spu0_2          : 1;
-  unsigned int spu0_3          : 1;
-  unsigned int spu0_4          : 1;
-  unsigned int spu0_5          : 1;
-  unsigned int spu0_6          : 1;
-  unsigned int spu0_7          : 1;
-  unsigned int dmc_in0         : 1;
-  unsigned int dmc_out0        : 1;
-  unsigned int fifo_in0        : 1;
-  unsigned int fifo_out0       : 1;
-  unsigned int fifo_in0_extra  : 1;
-  unsigned int fifo_out0_extra : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp0      : 1;
-  unsigned int timer_grp1      : 1;
-} reg_iop_sw_cpu_r_masked_intr2;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2 128
-
-/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int mpu_16          : 1;
-  unsigned int mpu_17          : 1;
-  unsigned int mpu_18          : 1;
-  unsigned int mpu_19          : 1;
-  unsigned int mpu_20          : 1;
-  unsigned int mpu_21          : 1;
-  unsigned int mpu_22          : 1;
-  unsigned int mpu_23          : 1;
-  unsigned int spu1_0          : 1;
-  unsigned int spu1_1          : 1;
-  unsigned int spu1_2          : 1;
-  unsigned int spu1_3          : 1;
-  unsigned int spu1_4          : 1;
-  unsigned int spu1_5          : 1;
-  unsigned int spu1_6          : 1;
-  unsigned int spu1_7          : 1;
-  unsigned int dmc_in1         : 1;
-  unsigned int dmc_out1        : 1;
-  unsigned int fifo_in1        : 1;
-  unsigned int fifo_out1       : 1;
-  unsigned int fifo_in1_extra  : 1;
-  unsigned int fifo_out1_extra : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp2      : 1;
-  unsigned int timer_grp3      : 1;
-} reg_iop_sw_cpu_rw_intr3_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask 132
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask 132
-
-/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int mpu_16 : 1;
-  unsigned int mpu_17 : 1;
-  unsigned int mpu_18 : 1;
-  unsigned int mpu_19 : 1;
-  unsigned int mpu_20 : 1;
-  unsigned int mpu_21 : 1;
-  unsigned int mpu_22 : 1;
-  unsigned int mpu_23 : 1;
-  unsigned int spu1_0 : 1;
-  unsigned int spu1_1 : 1;
-  unsigned int spu1_2 : 1;
-  unsigned int spu1_3 : 1;
-  unsigned int spu1_4 : 1;
-  unsigned int spu1_5 : 1;
-  unsigned int spu1_6 : 1;
-  unsigned int spu1_7 : 1;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_cpu_rw_ack_intr3;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3 136
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3 136
-
-/* Register r_intr3, scope iop_sw_cpu, type r */
-typedef struct {
-  unsigned int mpu_16          : 1;
-  unsigned int mpu_17          : 1;
-  unsigned int mpu_18          : 1;
-  unsigned int mpu_19          : 1;
-  unsigned int mpu_20          : 1;
-  unsigned int mpu_21          : 1;
-  unsigned int mpu_22          : 1;
-  unsigned int mpu_23          : 1;
-  unsigned int spu1_0          : 1;
-  unsigned int spu1_1          : 1;
-  unsigned int spu1_2          : 1;
-  unsigned int spu1_3          : 1;
-  unsigned int spu1_4          : 1;
-  unsigned int spu1_5          : 1;
-  unsigned int spu1_6          : 1;
-  unsigned int spu1_7          : 1;
-  unsigned int dmc_in1         : 1;
-  unsigned int dmc_out1        : 1;
-  unsigned int fifo_in1        : 1;
-  unsigned int fifo_out1       : 1;
-  unsigned int fifo_in1_extra  : 1;
-  unsigned int fifo_out1_extra : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp2      : 1;
-  unsigned int timer_grp3      : 1;
-} reg_iop_sw_cpu_r_intr3;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr3 140
-
-/* Register r_masked_intr3, scope iop_sw_cpu, type r */
-typedef struct {
-  unsigned int mpu_16          : 1;
-  unsigned int mpu_17          : 1;
-  unsigned int mpu_18          : 1;
-  unsigned int mpu_19          : 1;
-  unsigned int mpu_20          : 1;
-  unsigned int mpu_21          : 1;
-  unsigned int mpu_22          : 1;
-  unsigned int mpu_23          : 1;
-  unsigned int spu1_0          : 1;
-  unsigned int spu1_1          : 1;
-  unsigned int spu1_2          : 1;
-  unsigned int spu1_3          : 1;
-  unsigned int spu1_4          : 1;
-  unsigned int spu1_5          : 1;
-  unsigned int spu1_6          : 1;
-  unsigned int spu1_7          : 1;
-  unsigned int dmc_in1         : 1;
-  unsigned int dmc_out1        : 1;
-  unsigned int fifo_in1        : 1;
-  unsigned int fifo_out1       : 1;
-  unsigned int fifo_in1_extra  : 1;
-  unsigned int fifo_out1_extra : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp2      : 1;
-  unsigned int timer_grp3      : 1;
-} reg_iop_sw_cpu_r_masked_intr3;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3 144
-
-
-/* Constants */
-enum {
-  regk_iop_sw_cpu_copy                     = 0x00000000,
-  regk_iop_sw_cpu_no                       = 0x00000000,
-  regk_iop_sw_cpu_rd                       = 0x00000002,
-  regk_iop_sw_cpu_reg_copy                 = 0x00000001,
-  regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000,
-  regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000,
-  regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000,
-  regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000,
-  regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000,
-  regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000,
-  regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000,
-  regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000,
-  regk_iop_sw_cpu_rw_gio_clr_mask_default  = 0x00000000,
-  regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000,
-  regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000,
-  regk_iop_sw_cpu_rw_gio_set_mask_default  = 0x00000000,
-  regk_iop_sw_cpu_rw_intr0_mask_default    = 0x00000000,
-  regk_iop_sw_cpu_rw_intr1_mask_default    = 0x00000000,
-  regk_iop_sw_cpu_rw_intr2_mask_default    = 0x00000000,
-  regk_iop_sw_cpu_rw_intr3_mask_default    = 0x00000000,
-  regk_iop_sw_cpu_wr                       = 0x00000003,
-  regk_iop_sw_cpu_yes                      = 0x00000001
-};
-#endif /* __iop_sw_cpu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h
deleted file mode 100644
index da718f2a8cad..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h
+++ /dev/null
@@ -1,893 +0,0 @@
-#ifndef __iop_sw_mpu_defs_h
-#define __iop_sw_mpu_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:19 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_mpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
- *      id: $Id: iop_sw_mpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_mpu */
-
-/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_mpu_rw_sw_cfg_owner;
-#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
-#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
-
-/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int keep_owner  : 1;
-  unsigned int cmd         : 2;
-  unsigned int size        : 3;
-  unsigned int wr_spu0_mem : 1;
-  unsigned int wr_spu1_mem : 1;
-  unsigned int dummy1      : 24;
-} reg_iop_sw_mpu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 4
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 4
-
-/* Register rw_mc_data, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_mpu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 8
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 8
-
-/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
-typedef unsigned int reg_iop_sw_mpu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 12
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 12
-
-/* Register rs_mc_data, scope iop_sw_mpu, type rs */
-typedef unsigned int reg_iop_sw_mpu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 16
-
-/* Register r_mc_data, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 20
-
-/* Register r_mc_stat, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int busy_cpu      : 1;
-  unsigned int busy_mpu      : 1;
-  unsigned int busy_spu0     : 1;
-  unsigned int busy_spu1     : 1;
-  unsigned int owned_by_cpu  : 1;
-  unsigned int owned_by_mpu  : 1;
-  unsigned int owned_by_spu0 : 1;
-  unsigned int owned_by_spu1 : 1;
-  unsigned int dummy1        : 24;
-} reg_iop_sw_mpu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 24
-
-/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus0_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
-
-/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus0_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus0_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus0_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
-
-/* Register r_bus0_in, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_bus0_in;
-#define REG_RD_ADDR_iop_sw_mpu_r_bus0_in 44
-
-/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus1_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
-
-/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus1_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus1_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus1_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
-
-/* Register r_bus1_in, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_bus1_in;
-#define REG_RD_ADDR_iop_sw_mpu_r_bus1_in 64
-
-/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
-
-/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 72
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 72
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
-
-/* Register r_gio_in, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 84
-
-/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int intr0  : 1;
-  unsigned int intr1  : 1;
-  unsigned int intr2  : 1;
-  unsigned int intr3  : 1;
-  unsigned int intr4  : 1;
-  unsigned int intr5  : 1;
-  unsigned int intr6  : 1;
-  unsigned int intr7  : 1;
-  unsigned int intr8  : 1;
-  unsigned int intr9  : 1;
-  unsigned int intr10 : 1;
-  unsigned int intr11 : 1;
-  unsigned int intr12 : 1;
-  unsigned int intr13 : 1;
-  unsigned int intr14 : 1;
-  unsigned int intr15 : 1;
-  unsigned int intr16 : 1;
-  unsigned int intr17 : 1;
-  unsigned int intr18 : 1;
-  unsigned int intr19 : 1;
-  unsigned int intr20 : 1;
-  unsigned int intr21 : 1;
-  unsigned int intr22 : 1;
-  unsigned int intr23 : 1;
-  unsigned int intr24 : 1;
-  unsigned int intr25 : 1;
-  unsigned int intr26 : 1;
-  unsigned int intr27 : 1;
-  unsigned int intr28 : 1;
-  unsigned int intr29 : 1;
-  unsigned int intr30 : 1;
-  unsigned int intr31 : 1;
-} reg_iop_sw_mpu_rw_cpu_intr;
-#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 88
-#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 88
-
-/* Register r_cpu_intr, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int intr0  : 1;
-  unsigned int intr1  : 1;
-  unsigned int intr2  : 1;
-  unsigned int intr3  : 1;
-  unsigned int intr4  : 1;
-  unsigned int intr5  : 1;
-  unsigned int intr6  : 1;
-  unsigned int intr7  : 1;
-  unsigned int intr8  : 1;
-  unsigned int intr9  : 1;
-  unsigned int intr10 : 1;
-  unsigned int intr11 : 1;
-  unsigned int intr12 : 1;
-  unsigned int intr13 : 1;
-  unsigned int intr14 : 1;
-  unsigned int intr15 : 1;
-  unsigned int intr16 : 1;
-  unsigned int intr17 : 1;
-  unsigned int intr18 : 1;
-  unsigned int intr19 : 1;
-  unsigned int intr20 : 1;
-  unsigned int intr21 : 1;
-  unsigned int intr22 : 1;
-  unsigned int intr23 : 1;
-  unsigned int intr24 : 1;
-  unsigned int intr25 : 1;
-  unsigned int intr26 : 1;
-  unsigned int intr27 : 1;
-  unsigned int intr28 : 1;
-  unsigned int intr29 : 1;
-  unsigned int intr30 : 1;
-  unsigned int intr31 : 1;
-} reg_iop_sw_mpu_r_cpu_intr;
-#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 92
-
-/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int spu0_intr0      : 1;
-  unsigned int spu1_intr0      : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int timer_grp0      : 1;
-  unsigned int fifo_out0       : 1;
-  unsigned int fifo_out0_extra : 1;
-  unsigned int dmc_out0        : 1;
-  unsigned int spu0_intr1      : 1;
-  unsigned int spu1_intr1      : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int timer_grp1      : 1;
-  unsigned int fifo_in0        : 1;
-  unsigned int fifo_in0_extra  : 1;
-  unsigned int dmc_in0         : 1;
-  unsigned int spu0_intr2      : 1;
-  unsigned int spu1_intr2      : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int timer_grp2      : 1;
-  unsigned int fifo_out1       : 1;
-  unsigned int fifo_out1_extra : 1;
-  unsigned int dmc_out1        : 1;
-  unsigned int spu0_intr3      : 1;
-  unsigned int spu1_intr3      : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp3      : 1;
-  unsigned int fifo_in1        : 1;
-  unsigned int fifo_in1_extra  : 1;
-  unsigned int dmc_in1         : 1;
-} reg_iop_sw_mpu_rw_intr_grp0_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
-
-/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int spu0_intr0 : 1;
-  unsigned int spu1_intr0 : 1;
-  unsigned int dummy1     : 6;
-  unsigned int spu0_intr1 : 1;
-  unsigned int spu1_intr1 : 1;
-  unsigned int dummy2     : 6;
-  unsigned int spu0_intr2 : 1;
-  unsigned int spu1_intr2 : 1;
-  unsigned int dummy3     : 6;
-  unsigned int spu0_intr3 : 1;
-  unsigned int spu1_intr3 : 1;
-  unsigned int dummy4     : 6;
-} reg_iop_sw_mpu_rw_ack_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
-
-/* Register r_intr_grp0, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int spu0_intr0      : 1;
-  unsigned int spu1_intr0      : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int timer_grp0      : 1;
-  unsigned int fifo_out0       : 1;
-  unsigned int fifo_out0_extra : 1;
-  unsigned int dmc_out0        : 1;
-  unsigned int spu0_intr1      : 1;
-  unsigned int spu1_intr1      : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int timer_grp1      : 1;
-  unsigned int fifo_in0        : 1;
-  unsigned int fifo_in0_extra  : 1;
-  unsigned int dmc_in0         : 1;
-  unsigned int spu0_intr2      : 1;
-  unsigned int spu1_intr2      : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int timer_grp2      : 1;
-  unsigned int fifo_out1       : 1;
-  unsigned int fifo_out1_extra : 1;
-  unsigned int dmc_out1        : 1;
-  unsigned int spu0_intr3      : 1;
-  unsigned int spu1_intr3      : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp3      : 1;
-  unsigned int fifo_in1        : 1;
-  unsigned int fifo_in1_extra  : 1;
-  unsigned int dmc_in1         : 1;
-} reg_iop_sw_mpu_r_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 104
-
-/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int spu0_intr0      : 1;
-  unsigned int spu1_intr0      : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int timer_grp0      : 1;
-  unsigned int fifo_out0       : 1;
-  unsigned int fifo_out0_extra : 1;
-  unsigned int dmc_out0        : 1;
-  unsigned int spu0_intr1      : 1;
-  unsigned int spu1_intr1      : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int timer_grp1      : 1;
-  unsigned int fifo_in0        : 1;
-  unsigned int fifo_in0_extra  : 1;
-  unsigned int dmc_in0         : 1;
-  unsigned int spu0_intr2      : 1;
-  unsigned int spu1_intr2      : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int timer_grp2      : 1;
-  unsigned int fifo_out1       : 1;
-  unsigned int fifo_out1_extra : 1;
-  unsigned int dmc_out1        : 1;
-  unsigned int spu0_intr3      : 1;
-  unsigned int spu1_intr3      : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp3      : 1;
-  unsigned int fifo_in1        : 1;
-  unsigned int fifo_in1_extra  : 1;
-  unsigned int dmc_in1         : 1;
-} reg_iop_sw_mpu_r_masked_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108
-
-/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int spu0_intr4      : 1;
-  unsigned int spu1_intr4      : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int timer_grp0      : 1;
-  unsigned int fifo_in0        : 1;
-  unsigned int fifo_in0_extra  : 1;
-  unsigned int dmc_out0        : 1;
-  unsigned int spu0_intr5      : 1;
-  unsigned int spu1_intr5      : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int timer_grp1      : 1;
-  unsigned int fifo_out1       : 1;
-  unsigned int fifo_out0_extra : 1;
-  unsigned int dmc_in0         : 1;
-  unsigned int spu0_intr6      : 1;
-  unsigned int spu1_intr6      : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp2      : 1;
-  unsigned int fifo_in1        : 1;
-  unsigned int fifo_in1_extra  : 1;
-  unsigned int dmc_out1        : 1;
-  unsigned int spu0_intr7      : 1;
-  unsigned int spu1_intr7      : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int timer_grp3      : 1;
-  unsigned int fifo_out0       : 1;
-  unsigned int fifo_out1_extra : 1;
-  unsigned int dmc_in1         : 1;
-} reg_iop_sw_mpu_rw_intr_grp1_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
-
-/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int spu0_intr4 : 1;
-  unsigned int spu1_intr4 : 1;
-  unsigned int dummy1     : 6;
-  unsigned int spu0_intr5 : 1;
-  unsigned int spu1_intr5 : 1;
-  unsigned int dummy2     : 6;
-  unsigned int spu0_intr6 : 1;
-  unsigned int spu1_intr6 : 1;
-  unsigned int dummy3     : 6;
-  unsigned int spu0_intr7 : 1;
-  unsigned int spu1_intr7 : 1;
-  unsigned int dummy4     : 6;
-} reg_iop_sw_mpu_rw_ack_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
-
-/* Register r_intr_grp1, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int spu0_intr4      : 1;
-  unsigned int spu1_intr4      : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int timer_grp0      : 1;
-  unsigned int fifo_in0        : 1;
-  unsigned int fifo_in0_extra  : 1;
-  unsigned int dmc_out0        : 1;
-  unsigned int spu0_intr5      : 1;
-  unsigned int spu1_intr5      : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int timer_grp1      : 1;
-  unsigned int fifo_out1       : 1;
-  unsigned int fifo_out0_extra : 1;
-  unsigned int dmc_in0         : 1;
-  unsigned int spu0_intr6      : 1;
-  unsigned int spu1_intr6      : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp2      : 1;
-  unsigned int fifo_in1        : 1;
-  unsigned int fifo_in1_extra  : 1;
-  unsigned int dmc_out1        : 1;
-  unsigned int spu0_intr7      : 1;
-  unsigned int spu1_intr7      : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int timer_grp3      : 1;
-  unsigned int fifo_out0       : 1;
-  unsigned int fifo_out1_extra : 1;
-  unsigned int dmc_in1         : 1;
-} reg_iop_sw_mpu_r_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120
-
-/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int spu0_intr4      : 1;
-  unsigned int spu1_intr4      : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int timer_grp0      : 1;
-  unsigned int fifo_in0        : 1;
-  unsigned int fifo_in0_extra  : 1;
-  unsigned int dmc_out0        : 1;
-  unsigned int spu0_intr5      : 1;
-  unsigned int spu1_intr5      : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int timer_grp1      : 1;
-  unsigned int fifo_out1       : 1;
-  unsigned int fifo_out0_extra : 1;
-  unsigned int dmc_in0         : 1;
-  unsigned int spu0_intr6      : 1;
-  unsigned int spu1_intr6      : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp2      : 1;
-  unsigned int fifo_in1        : 1;
-  unsigned int fifo_in1_extra  : 1;
-  unsigned int dmc_out1        : 1;
-  unsigned int spu0_intr7      : 1;
-  unsigned int spu1_intr7      : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int timer_grp3      : 1;
-  unsigned int fifo_out0       : 1;
-  unsigned int fifo_out1_extra : 1;
-  unsigned int dmc_in1         : 1;
-} reg_iop_sw_mpu_r_masked_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124
-
-/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int spu0_intr8      : 1;
-  unsigned int spu1_intr8      : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int timer_grp0      : 1;
-  unsigned int fifo_out1       : 1;
-  unsigned int fifo_out1_extra : 1;
-  unsigned int dmc_out0        : 1;
-  unsigned int spu0_intr9      : 1;
-  unsigned int spu1_intr9      : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp1      : 1;
-  unsigned int fifo_in1        : 1;
-  unsigned int fifo_in1_extra  : 1;
-  unsigned int dmc_in0         : 1;
-  unsigned int spu0_intr10     : 1;
-  unsigned int spu1_intr10     : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int timer_grp2      : 1;
-  unsigned int fifo_out0       : 1;
-  unsigned int fifo_out0_extra : 1;
-  unsigned int dmc_out1        : 1;
-  unsigned int spu0_intr11     : 1;
-  unsigned int spu1_intr11     : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int timer_grp3      : 1;
-  unsigned int fifo_in0        : 1;
-  unsigned int fifo_in0_extra  : 1;
-  unsigned int dmc_in1         : 1;
-} reg_iop_sw_mpu_rw_intr_grp2_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
-
-/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int spu0_intr8  : 1;
-  unsigned int spu1_intr8  : 1;
-  unsigned int dummy1      : 6;
-  unsigned int spu0_intr9  : 1;
-  unsigned int spu1_intr9  : 1;
-  unsigned int dummy2      : 6;
-  unsigned int spu0_intr10 : 1;
-  unsigned int spu1_intr10 : 1;
-  unsigned int dummy3      : 6;
-  unsigned int spu0_intr11 : 1;
-  unsigned int spu1_intr11 : 1;
-  unsigned int dummy4      : 6;
-} reg_iop_sw_mpu_rw_ack_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
-
-/* Register r_intr_grp2, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int spu0_intr8      : 1;
-  unsigned int spu1_intr8      : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int timer_grp0      : 1;
-  unsigned int fifo_out1       : 1;
-  unsigned int fifo_out1_extra : 1;
-  unsigned int dmc_out0        : 1;
-  unsigned int spu0_intr9      : 1;
-  unsigned int spu1_intr9      : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp1      : 1;
-  unsigned int fifo_in1        : 1;
-  unsigned int fifo_in1_extra  : 1;
-  unsigned int dmc_in0         : 1;
-  unsigned int spu0_intr10     : 1;
-  unsigned int spu1_intr10     : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int timer_grp2      : 1;
-  unsigned int fifo_out0       : 1;
-  unsigned int fifo_out0_extra : 1;
-  unsigned int dmc_out1        : 1;
-  unsigned int spu0_intr11     : 1;
-  unsigned int spu1_intr11     : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int timer_grp3      : 1;
-  unsigned int fifo_in0        : 1;
-  unsigned int fifo_in0_extra  : 1;
-  unsigned int dmc_in1         : 1;
-} reg_iop_sw_mpu_r_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136
-
-/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int spu0_intr8      : 1;
-  unsigned int spu1_intr8      : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int timer_grp0      : 1;
-  unsigned int fifo_out1       : 1;
-  unsigned int fifo_out1_extra : 1;
-  unsigned int dmc_out0        : 1;
-  unsigned int spu0_intr9      : 1;
-  unsigned int spu1_intr9      : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp1      : 1;
-  unsigned int fifo_in1        : 1;
-  unsigned int fifo_in1_extra  : 1;
-  unsigned int dmc_in0         : 1;
-  unsigned int spu0_intr10     : 1;
-  unsigned int spu1_intr10     : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int timer_grp2      : 1;
-  unsigned int fifo_out0       : 1;
-  unsigned int fifo_out0_extra : 1;
-  unsigned int dmc_out1        : 1;
-  unsigned int spu0_intr11     : 1;
-  unsigned int spu1_intr11     : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int timer_grp3      : 1;
-  unsigned int fifo_in0        : 1;
-  unsigned int fifo_in0_extra  : 1;
-  unsigned int dmc_in1         : 1;
-} reg_iop_sw_mpu_r_masked_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140
-
-/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int spu0_intr12     : 1;
-  unsigned int spu1_intr12     : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp0      : 1;
-  unsigned int fifo_in1        : 1;
-  unsigned int fifo_in1_extra  : 1;
-  unsigned int dmc_out0        : 1;
-  unsigned int spu0_intr13     : 1;
-  unsigned int spu1_intr13     : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int timer_grp1      : 1;
-  unsigned int fifo_out0       : 1;
-  unsigned int fifo_out0_extra : 1;
-  unsigned int dmc_in0         : 1;
-  unsigned int spu0_intr14     : 1;
-  unsigned int spu1_intr14     : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int timer_grp2      : 1;
-  unsigned int fifo_in0        : 1;
-  unsigned int fifo_in0_extra  : 1;
-  unsigned int dmc_out1        : 1;
-  unsigned int spu0_intr15     : 1;
-  unsigned int spu1_intr15     : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int timer_grp3      : 1;
-  unsigned int fifo_out1       : 1;
-  unsigned int fifo_out1_extra : 1;
-  unsigned int dmc_in1         : 1;
-} reg_iop_sw_mpu_rw_intr_grp3_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
-
-/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int spu0_intr12 : 1;
-  unsigned int spu1_intr12 : 1;
-  unsigned int dummy1      : 6;
-  unsigned int spu0_intr13 : 1;
-  unsigned int spu1_intr13 : 1;
-  unsigned int dummy2      : 6;
-  unsigned int spu0_intr14 : 1;
-  unsigned int spu1_intr14 : 1;
-  unsigned int dummy3      : 6;
-  unsigned int spu0_intr15 : 1;
-  unsigned int spu1_intr15 : 1;
-  unsigned int dummy4      : 6;
-} reg_iop_sw_mpu_rw_ack_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
-
-/* Register r_intr_grp3, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int spu0_intr12     : 1;
-  unsigned int spu1_intr12     : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp0      : 1;
-  unsigned int fifo_in1        : 1;
-  unsigned int fifo_in1_extra  : 1;
-  unsigned int dmc_out0        : 1;
-  unsigned int spu0_intr13     : 1;
-  unsigned int spu1_intr13     : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int timer_grp1      : 1;
-  unsigned int fifo_out0       : 1;
-  unsigned int fifo_out0_extra : 1;
-  unsigned int dmc_in0         : 1;
-  unsigned int spu0_intr14     : 1;
-  unsigned int spu1_intr14     : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int timer_grp2      : 1;
-  unsigned int fifo_in0        : 1;
-  unsigned int fifo_in0_extra  : 1;
-  unsigned int dmc_out1        : 1;
-  unsigned int spu0_intr15     : 1;
-  unsigned int spu1_intr15     : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int timer_grp3      : 1;
-  unsigned int fifo_out1       : 1;
-  unsigned int fifo_out1_extra : 1;
-  unsigned int dmc_in1         : 1;
-} reg_iop_sw_mpu_r_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152
-
-/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int spu0_intr12     : 1;
-  unsigned int spu1_intr12     : 1;
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp0      : 1;
-  unsigned int fifo_in1        : 1;
-  unsigned int fifo_in1_extra  : 1;
-  unsigned int dmc_out0        : 1;
-  unsigned int spu0_intr13     : 1;
-  unsigned int spu1_intr13     : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int timer_grp1      : 1;
-  unsigned int fifo_out0       : 1;
-  unsigned int fifo_out0_extra : 1;
-  unsigned int dmc_in0         : 1;
-  unsigned int spu0_intr14     : 1;
-  unsigned int spu1_intr14     : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int timer_grp2      : 1;
-  unsigned int fifo_in0        : 1;
-  unsigned int fifo_in0_extra  : 1;
-  unsigned int dmc_out1        : 1;
-  unsigned int spu0_intr15     : 1;
-  unsigned int spu1_intr15     : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int timer_grp3      : 1;
-  unsigned int fifo_out1       : 1;
-  unsigned int fifo_out1_extra : 1;
-  unsigned int dmc_in1         : 1;
-} reg_iop_sw_mpu_r_masked_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156
-
-
-/* Constants */
-enum {
-  regk_iop_sw_mpu_copy                     = 0x00000000,
-  regk_iop_sw_mpu_cpu                      = 0x00000000,
-  regk_iop_sw_mpu_mpu                      = 0x00000001,
-  regk_iop_sw_mpu_no                       = 0x00000000,
-  regk_iop_sw_mpu_nop                      = 0x00000000,
-  regk_iop_sw_mpu_rd                       = 0x00000002,
-  regk_iop_sw_mpu_reg_copy                 = 0x00000001,
-  regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_gio_clr_mask_default  = 0x00000000,
-  regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_gio_set_mask_default  = 0x00000000,
-  regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_sw_cfg_owner_default  = 0x00000000,
-  regk_iop_sw_mpu_set                      = 0x00000001,
-  regk_iop_sw_mpu_spu0                     = 0x00000002,
-  regk_iop_sw_mpu_spu1                     = 0x00000003,
-  regk_iop_sw_mpu_wr                       = 0x00000003,
-  regk_iop_sw_mpu_yes                      = 0x00000001
-};
-#endif /* __iop_sw_mpu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h
deleted file mode 100644
index b59dde4bd0d1..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h
+++ /dev/null
@@ -1,552 +0,0 @@
-#ifndef __iop_sw_spu_defs_h
-#define __iop_sw_spu_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:19 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
- *      id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_spu */
-
-/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int keep_owner  : 1;
-  unsigned int cmd         : 2;
-  unsigned int size        : 3;
-  unsigned int wr_spu0_mem : 1;
-  unsigned int wr_spu1_mem : 1;
-  unsigned int dummy1      : 24;
-} reg_iop_sw_spu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0
-
-/* Register rw_mc_data, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_spu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4
-
-/* Register rw_mc_addr, scope iop_sw_spu, type rw */
-typedef unsigned int reg_iop_sw_spu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8
-
-/* Register rs_mc_data, scope iop_sw_spu, type rs */
-typedef unsigned int reg_iop_sw_spu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12
-
-/* Register r_mc_data, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_r_mc_data 16
-
-/* Register r_mc_stat, scope iop_sw_spu, type r */
-typedef struct {
-  unsigned int busy_cpu      : 1;
-  unsigned int busy_mpu      : 1;
-  unsigned int busy_spu0     : 1;
-  unsigned int busy_spu1     : 1;
-  unsigned int owned_by_cpu  : 1;
-  unsigned int owned_by_mpu  : 1;
-  unsigned int owned_by_spu0 : 1;
-  unsigned int owned_by_spu1 : 1;
-  unsigned int dummy1        : 24;
-} reg_iop_sw_spu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20
-
-/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus0_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24
-
-/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus0_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus0_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus0_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36
-
-/* Register r_bus0_in, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_bus0_in;
-#define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40
-
-/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus1_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44
-
-/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus1_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus1_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus1_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56
-
-/* Register r_bus1_in, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_bus1_in;
-#define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60
-
-/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64
-
-/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76
-
-/* Register r_gio_in, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_spu_r_gio_in 80
-
-/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus0_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84
-
-/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus0_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88
-
-/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus0_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92
-
-/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus0_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96
-
-/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus1_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100
-
-/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus1_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104
-
-/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus1_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108
-
-/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus1_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112
-
-/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116
-
-/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120
-
-/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124
-
-/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128
-
-/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132
-
-/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136
-
-/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140
-
-/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
-
-/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int intr0  : 1;
-  unsigned int intr1  : 1;
-  unsigned int intr2  : 1;
-  unsigned int intr3  : 1;
-  unsigned int intr4  : 1;
-  unsigned int intr5  : 1;
-  unsigned int intr6  : 1;
-  unsigned int intr7  : 1;
-  unsigned int intr8  : 1;
-  unsigned int intr9  : 1;
-  unsigned int intr10 : 1;
-  unsigned int intr11 : 1;
-  unsigned int intr12 : 1;
-  unsigned int intr13 : 1;
-  unsigned int intr14 : 1;
-  unsigned int intr15 : 1;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_cpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148
-#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148
-
-/* Register r_cpu_intr, scope iop_sw_spu, type r */
-typedef struct {
-  unsigned int intr0  : 1;
-  unsigned int intr1  : 1;
-  unsigned int intr2  : 1;
-  unsigned int intr3  : 1;
-  unsigned int intr4  : 1;
-  unsigned int intr5  : 1;
-  unsigned int intr6  : 1;
-  unsigned int intr7  : 1;
-  unsigned int intr8  : 1;
-  unsigned int intr9  : 1;
-  unsigned int intr10 : 1;
-  unsigned int intr11 : 1;
-  unsigned int intr12 : 1;
-  unsigned int intr13 : 1;
-  unsigned int intr14 : 1;
-  unsigned int intr15 : 1;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_r_cpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152
-
-/* Register r_hw_intr, scope iop_sw_spu, type r */
-typedef struct {
-  unsigned int trigger_grp0    : 1;
-  unsigned int trigger_grp1    : 1;
-  unsigned int trigger_grp2    : 1;
-  unsigned int trigger_grp3    : 1;
-  unsigned int trigger_grp4    : 1;
-  unsigned int trigger_grp5    : 1;
-  unsigned int trigger_grp6    : 1;
-  unsigned int trigger_grp7    : 1;
-  unsigned int timer_grp0      : 1;
-  unsigned int timer_grp1      : 1;
-  unsigned int timer_grp2      : 1;
-  unsigned int timer_grp3      : 1;
-  unsigned int fifo_out0       : 1;
-  unsigned int fifo_out0_extra : 1;
-  unsigned int fifo_in0        : 1;
-  unsigned int fifo_in0_extra  : 1;
-  unsigned int fifo_out1       : 1;
-  unsigned int fifo_out1_extra : 1;
-  unsigned int fifo_in1        : 1;
-  unsigned int fifo_in1_extra  : 1;
-  unsigned int dmc_out0        : 1;
-  unsigned int dmc_in0         : 1;
-  unsigned int dmc_out1        : 1;
-  unsigned int dmc_in1         : 1;
-  unsigned int dummy1          : 8;
-} reg_iop_sw_spu_r_hw_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156
-
-/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int intr0  : 1;
-  unsigned int intr1  : 1;
-  unsigned int intr2  : 1;
-  unsigned int intr3  : 1;
-  unsigned int intr4  : 1;
-  unsigned int intr5  : 1;
-  unsigned int intr6  : 1;
-  unsigned int intr7  : 1;
-  unsigned int intr8  : 1;
-  unsigned int intr9  : 1;
-  unsigned int intr10 : 1;
-  unsigned int intr11 : 1;
-  unsigned int intr12 : 1;
-  unsigned int intr13 : 1;
-  unsigned int intr14 : 1;
-  unsigned int intr15 : 1;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_mpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160
-#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160
-
-/* Register r_mpu_intr, scope iop_sw_spu, type r */
-typedef struct {
-  unsigned int intr0            : 1;
-  unsigned int intr1            : 1;
-  unsigned int intr2            : 1;
-  unsigned int intr3            : 1;
-  unsigned int intr4            : 1;
-  unsigned int intr5            : 1;
-  unsigned int intr6            : 1;
-  unsigned int intr7            : 1;
-  unsigned int intr8            : 1;
-  unsigned int intr9            : 1;
-  unsigned int intr10           : 1;
-  unsigned int intr11           : 1;
-  unsigned int intr12           : 1;
-  unsigned int intr13           : 1;
-  unsigned int intr14           : 1;
-  unsigned int intr15           : 1;
-  unsigned int other_spu_intr0  : 1;
-  unsigned int other_spu_intr1  : 1;
-  unsigned int other_spu_intr2  : 1;
-  unsigned int other_spu_intr3  : 1;
-  unsigned int other_spu_intr4  : 1;
-  unsigned int other_spu_intr5  : 1;
-  unsigned int other_spu_intr6  : 1;
-  unsigned int other_spu_intr7  : 1;
-  unsigned int other_spu_intr8  : 1;
-  unsigned int other_spu_intr9  : 1;
-  unsigned int other_spu_intr10 : 1;
-  unsigned int other_spu_intr11 : 1;
-  unsigned int other_spu_intr12 : 1;
-  unsigned int other_spu_intr13 : 1;
-  unsigned int other_spu_intr14 : 1;
-  unsigned int other_spu_intr15 : 1;
-} reg_iop_sw_spu_r_mpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164
-
-
-/* Constants */
-enum {
-  regk_iop_sw_spu_copy                     = 0x00000000,
-  regk_iop_sw_spu_no                       = 0x00000000,
-  regk_iop_sw_spu_nop                      = 0x00000000,
-  regk_iop_sw_spu_rd                       = 0x00000002,
-  regk_iop_sw_spu_reg_copy                 = 0x00000001,
-  regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000,
-  regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000,
-  regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000,
-  regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000,
-  regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000,
-  regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000,
-  regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000,
-  regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000,
-  regk_iop_sw_spu_rw_gio_clr_mask_default  = 0x00000000,
-  regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000,
-  regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,
-  regk_iop_sw_spu_rw_gio_set_mask_default  = 0x00000000,
-  regk_iop_sw_spu_set                      = 0x00000001,
-  regk_iop_sw_spu_wr                       = 0x00000003,
-  regk_iop_sw_spu_yes                      = 0x00000001
-};
-#endif /* __iop_sw_spu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h
deleted file mode 100644
index c994114f3b51..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h
+++ /dev/null
@@ -1,249 +0,0 @@
-#ifndef __iop_timer_grp_defs_h
-#define __iop_timer_grp_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_timer_grp.r
- *     id:           iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r
- *      id: $Id: iop_timer_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_timer_grp */
-
-/* Register rw_cfg, scope iop_timer_grp, type rw */
-typedef struct {
-  unsigned int clk_src     : 1;
-  unsigned int trig        : 2;
-  unsigned int clk_gen_div : 8;
-  unsigned int clk_div     : 8;
-  unsigned int dummy1      : 13;
-} reg_iop_timer_grp_rw_cfg;
-#define REG_RD_ADDR_iop_timer_grp_rw_cfg 0
-#define REG_WR_ADDR_iop_timer_grp_rw_cfg 0
-
-/* Register rw_half_period, scope iop_timer_grp, type rw */
-typedef struct {
-  unsigned int quota_lo     : 15;
-  unsigned int quota_hi     : 15;
-  unsigned int quota_hi_sel : 1;
-  unsigned int dummy1       : 1;
-} reg_iop_timer_grp_rw_half_period;
-#define REG_RD_ADDR_iop_timer_grp_rw_half_period 4
-#define REG_WR_ADDR_iop_timer_grp_rw_half_period 4
-
-/* Register rw_half_period_len, scope iop_timer_grp, type rw */
-typedef unsigned int reg_iop_timer_grp_rw_half_period_len;
-#define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8
-#define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8
-
-#define STRIDE_iop_timer_grp_rw_tmr_cfg 4
-/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
-typedef struct {
-  unsigned int clk_src         : 3;
-  unsigned int strb            : 2;
-  unsigned int run_mode        : 2;
-  unsigned int out_mode        : 1;
-  unsigned int active_on_tmr   : 2;
-  unsigned int inv             : 1;
-  unsigned int en_by_tmr       : 2;
-  unsigned int dis_by_tmr      : 2;
-  unsigned int en_only_by_reg  : 1;
-  unsigned int dis_only_by_reg : 1;
-  unsigned int rst_at_en_strb  : 1;
-  unsigned int dummy1          : 14;
-} reg_iop_timer_grp_rw_tmr_cfg;
-#define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12
-#define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12
-
-#define STRIDE_iop_timer_grp_rw_tmr_len 4
-/* Register rw_tmr_len, scope iop_timer_grp, type rw */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_timer_grp_rw_tmr_len;
-#define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44
-#define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44
-
-/* Register rw_cmd, scope iop_timer_grp, type rw */
-typedef struct {
-  unsigned int rst  : 4;
-  unsigned int en   : 4;
-  unsigned int dis  : 4;
-  unsigned int strb : 4;
-  unsigned int dummy1 : 16;
-} reg_iop_timer_grp_rw_cmd;
-#define REG_RD_ADDR_iop_timer_grp_rw_cmd 60
-#define REG_WR_ADDR_iop_timer_grp_rw_cmd 60
-
-/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
-typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt;
-#define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64
-
-#define STRIDE_iop_timer_grp_rs_tmr_cnt 8
-/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_timer_grp_rs_tmr_cnt;
-#define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68
-
-#define STRIDE_iop_timer_grp_r_tmr_cnt 8
-/* Register r_tmr_cnt, scope iop_timer_grp, type r */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_timer_grp_r_tmr_cnt;
-#define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72
-
-/* Register rw_intr_mask, scope iop_timer_grp, type rw */
-typedef struct {
-  unsigned int tmr0 : 1;
-  unsigned int tmr1 : 1;
-  unsigned int tmr2 : 1;
-  unsigned int tmr3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_timer_grp_rw_intr_mask;
-#define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100
-#define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100
-
-/* Register rw_ack_intr, scope iop_timer_grp, type rw */
-typedef struct {
-  unsigned int tmr0 : 1;
-  unsigned int tmr1 : 1;
-  unsigned int tmr2 : 1;
-  unsigned int tmr3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_timer_grp_rw_ack_intr;
-#define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104
-#define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104
-
-/* Register r_intr, scope iop_timer_grp, type r */
-typedef struct {
-  unsigned int tmr0 : 1;
-  unsigned int tmr1 : 1;
-  unsigned int tmr2 : 1;
-  unsigned int tmr3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_timer_grp_r_intr;
-#define REG_RD_ADDR_iop_timer_grp_r_intr 108
-
-/* Register r_masked_intr, scope iop_timer_grp, type r */
-typedef struct {
-  unsigned int tmr0 : 1;
-  unsigned int tmr1 : 1;
-  unsigned int tmr2 : 1;
-  unsigned int tmr3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_timer_grp_r_masked_intr;
-#define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112
-
-
-/* Constants */
-enum {
-  regk_iop_timer_grp_clk200                = 0x00000000,
-  regk_iop_timer_grp_clk_gen               = 0x00000002,
-  regk_iop_timer_grp_complete              = 0x00000002,
-  regk_iop_timer_grp_div_clk200            = 0x00000001,
-  regk_iop_timer_grp_div_clk_gen           = 0x00000003,
-  regk_iop_timer_grp_ext                   = 0x00000001,
-  regk_iop_timer_grp_hi                    = 0x00000000,
-  regk_iop_timer_grp_long_period           = 0x00000001,
-  regk_iop_timer_grp_neg                   = 0x00000002,
-  regk_iop_timer_grp_no                    = 0x00000000,
-  regk_iop_timer_grp_once                  = 0x00000003,
-  regk_iop_timer_grp_pause                 = 0x00000001,
-  regk_iop_timer_grp_pos                   = 0x00000001,
-  regk_iop_timer_grp_pos_neg               = 0x00000003,
-  regk_iop_timer_grp_pulse                 = 0x00000000,
-  regk_iop_timer_grp_r_tmr_cnt_size        = 0x00000004,
-  regk_iop_timer_grp_rs_tmr_cnt_size       = 0x00000004,
-  regk_iop_timer_grp_rw_cfg_default        = 0x00000002,
-  regk_iop_timer_grp_rw_intr_mask_default  = 0x00000000,
-  regk_iop_timer_grp_rw_tmr_cfg_default0   = 0x00018000,
-  regk_iop_timer_grp_rw_tmr_cfg_default1   = 0x0001a900,
-  regk_iop_timer_grp_rw_tmr_cfg_default2   = 0x0001d200,
-  regk_iop_timer_grp_rw_tmr_cfg_default3   = 0x0001fb00,
-  regk_iop_timer_grp_rw_tmr_cfg_size       = 0x00000004,
-  regk_iop_timer_grp_rw_tmr_len_default    = 0x00000000,
-  regk_iop_timer_grp_rw_tmr_len_size       = 0x00000004,
-  regk_iop_timer_grp_short_period          = 0x00000000,
-  regk_iop_timer_grp_stop                  = 0x00000000,
-  regk_iop_timer_grp_tmr                   = 0x00000004,
-  regk_iop_timer_grp_toggle                = 0x00000001,
-  regk_iop_timer_grp_yes                   = 0x00000001
-};
-#endif /* __iop_timer_grp_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h
deleted file mode 100644
index 36e44282399d..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h
+++ /dev/null
@@ -1,170 +0,0 @@
-#ifndef __iop_trigger_grp_defs_h
-#define __iop_trigger_grp_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_trigger_grp.r
- *     id:           iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_trigger_grp_defs.h ../../inst/io_proc/rtl/iop_trigger_grp.r
- *      id: $Id: iop_trigger_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_trigger_grp */
-
-#define STRIDE_iop_trigger_grp_rw_cfg 4
-/* Register rw_cfg, scope iop_trigger_grp, type rw */
-typedef struct {
-  unsigned int action          : 2;
-  unsigned int once            : 1;
-  unsigned int trig            : 3;
-  unsigned int en_only_by_reg  : 1;
-  unsigned int dis_only_by_reg : 1;
-  unsigned int dummy1          : 24;
-} reg_iop_trigger_grp_rw_cfg;
-#define REG_RD_ADDR_iop_trigger_grp_rw_cfg 0
-#define REG_WR_ADDR_iop_trigger_grp_rw_cfg 0
-
-/* Register rw_cmd, scope iop_trigger_grp, type rw */
-typedef struct {
-  unsigned int dis : 4;
-  unsigned int en  : 4;
-  unsigned int dummy1 : 24;
-} reg_iop_trigger_grp_rw_cmd;
-#define REG_RD_ADDR_iop_trigger_grp_rw_cmd 16
-#define REG_WR_ADDR_iop_trigger_grp_rw_cmd 16
-
-/* Register rw_intr_mask, scope iop_trigger_grp, type rw */
-typedef struct {
-  unsigned int trig0 : 1;
-  unsigned int trig1 : 1;
-  unsigned int trig2 : 1;
-  unsigned int trig3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_trigger_grp_rw_intr_mask;
-#define REG_RD_ADDR_iop_trigger_grp_rw_intr_mask 20
-#define REG_WR_ADDR_iop_trigger_grp_rw_intr_mask 20
-
-/* Register rw_ack_intr, scope iop_trigger_grp, type rw */
-typedef struct {
-  unsigned int trig0 : 1;
-  unsigned int trig1 : 1;
-  unsigned int trig2 : 1;
-  unsigned int trig3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_trigger_grp_rw_ack_intr;
-#define REG_RD_ADDR_iop_trigger_grp_rw_ack_intr 24
-#define REG_WR_ADDR_iop_trigger_grp_rw_ack_intr 24
-
-/* Register r_intr, scope iop_trigger_grp, type r */
-typedef struct {
-  unsigned int trig0 : 1;
-  unsigned int trig1 : 1;
-  unsigned int trig2 : 1;
-  unsigned int trig3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_trigger_grp_r_intr;
-#define REG_RD_ADDR_iop_trigger_grp_r_intr 28
-
-/* Register r_masked_intr, scope iop_trigger_grp, type r */
-typedef struct {
-  unsigned int trig0 : 1;
-  unsigned int trig1 : 1;
-  unsigned int trig2 : 1;
-  unsigned int trig3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_trigger_grp_r_masked_intr;
-#define REG_RD_ADDR_iop_trigger_grp_r_masked_intr 32
-
-
-/* Constants */
-enum {
-  regk_iop_trigger_grp_fall                = 0x00000002,
-  regk_iop_trigger_grp_fall_lo             = 0x00000006,
-  regk_iop_trigger_grp_no                  = 0x00000000,
-  regk_iop_trigger_grp_off                 = 0x00000000,
-  regk_iop_trigger_grp_pulse               = 0x00000000,
-  regk_iop_trigger_grp_rise                = 0x00000001,
-  regk_iop_trigger_grp_rise_fall           = 0x00000003,
-  regk_iop_trigger_grp_rise_fall_hi        = 0x00000007,
-  regk_iop_trigger_grp_rise_fall_lo        = 0x00000004,
-  regk_iop_trigger_grp_rise_hi             = 0x00000005,
-  regk_iop_trigger_grp_rw_cfg_default      = 0x000000c0,
-  regk_iop_trigger_grp_rw_cfg_size         = 0x00000004,
-  regk_iop_trigger_grp_rw_intr_mask_default = 0x00000000,
-  regk_iop_trigger_grp_toggle              = 0x00000003,
-  regk_iop_trigger_grp_yes                 = 0x00000001
-};
-#endif /* __iop_trigger_grp_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h
deleted file mode 100644
index b8d6a910c71c..000000000000
--- a/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h
+++ /dev/null
@@ -1,99 +0,0 @@
-#ifndef __iop_version_defs_h
-#define __iop_version_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/guinness/iop_version.r
- *     id:           iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp
- *     last modfied: Mon Apr 11 16:08:44 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_version_defs.h ../../inst/io_proc/rtl/guinness/iop_version.r
- *      id: $Id: iop_version_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_version */
-
-/* Register r_version, scope iop_version, type r */
-typedef struct {
-  unsigned int nr : 8;
-  unsigned int dummy1 : 24;
-} reg_iop_version_r_version;
-#define REG_RD_ADDR_iop_version_r_version 0
-
-
-/* Constants */
-enum {
-  regk_iop_version_v1_0                    = 0x00000001
-};
-#endif /* __iop_version_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h b/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h
deleted file mode 100644
index 7b167e3c0572..000000000000
--- a/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h
+++ /dev/null
@@ -1,104 +0,0 @@
-#ifndef __irq_nmi_defs_h
-#define __irq_nmi_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../mod/irq_nmi.r
- *     id:           <not found>
- *     last modfied: Thu Jan 22 09:22:43 2004
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile irq_nmi_defs.h ../../mod/irq_nmi.r
- *      id: $Id: irq_nmi_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope irq_nmi */
-
-/* Register rw_cmd, scope irq_nmi, type rw */
-typedef struct {
-  unsigned int delay : 16;
-  unsigned int op    : 2;
-  unsigned int dummy1 : 14;
-} reg_irq_nmi_rw_cmd;
-#define REG_RD_ADDR_irq_nmi_rw_cmd 0
-#define REG_WR_ADDR_irq_nmi_rw_cmd 0
-
-
-/* Constants */
-enum {
-  regk_irq_nmi_ack_irq                     = 0x00000002,
-  regk_irq_nmi_ack_nmi                     = 0x00000003,
-  regk_irq_nmi_irq                         = 0x00000000,
-  regk_irq_nmi_nmi                         = 0x00000001
-};
-#endif /* __irq_nmi_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h b/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h
deleted file mode 100644
index a11fdd3cd907..000000000000
--- a/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h
+++ /dev/null
@@ -1,205 +0,0 @@
-#ifndef __marb_bp_defs_h
-#define __marb_bp_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
- *     id:           <not found>
- *     last modfied: Fri Nov  7 15:36:04 2003
- *
- *   by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r
- *      id: $Id: marb_bp_defs.h,v 1.2 2004/06/04 07:15:33 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-/* C-code for register scope marb_bp */
-
-/* Register rw_first_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_bp, type rw */
-typedef struct {
-  unsigned int read         : 1;
-  unsigned int write        : 1;
-  unsigned int read_excl    : 1;
-  unsigned int pri_write    : 1;
-  unsigned int us_read      : 1;
-  unsigned int us_write     : 1;
-  unsigned int us_read_excl : 1;
-  unsigned int us_pri_write : 1;
-  unsigned int dummy1       : 24;
-} reg_marb_bp_rw_op;
-#define REG_RD_ADDR_marb_bp_rw_op 8
-#define REG_WR_ADDR_marb_bp_rw_op 8
-
-/* Register rw_clients, scope marb_bp, type rw */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_bp_rw_clients;
-#define REG_RD_ADDR_marb_bp_rw_clients 12
-#define REG_WR_ADDR_marb_bp_rw_clients 12
-
-/* Register rw_options, scope marb_bp, type rw */
-typedef struct {
-  unsigned int wrap : 1;
-  unsigned int dummy1 : 31;
-} reg_marb_bp_rw_options;
-#define REG_RD_ADDR_marb_bp_rw_options 16
-#define REG_WR_ADDR_marb_bp_rw_options 16
-
-/* Register r_break_addr, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_break_addr;
-#define REG_RD_ADDR_marb_bp_r_break_addr 20
-
-/* Register r_break_op, scope marb_bp, type r */
-typedef struct {
-  unsigned int read         : 1;
-  unsigned int write        : 1;
-  unsigned int read_excl    : 1;
-  unsigned int pri_write    : 1;
-  unsigned int us_read      : 1;
-  unsigned int us_write     : 1;
-  unsigned int us_read_excl : 1;
-  unsigned int us_pri_write : 1;
-  unsigned int dummy1       : 24;
-} reg_marb_bp_r_break_op;
-#define REG_RD_ADDR_marb_bp_r_break_op 24
-
-/* Register r_break_clients, scope marb_bp, type r */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_bp_r_break_clients;
-#define REG_RD_ADDR_marb_bp_r_break_clients 28
-
-/* Register r_break_first_client, scope marb_bp, type r */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_bp_r_break_first_client;
-#define REG_RD_ADDR_marb_bp_r_break_first_client 32
-
-/* Register r_break_size, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_break_size;
-#define REG_RD_ADDR_marb_bp_r_break_size 36
-
-/* Register rw_ack, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_ack;
-#define REG_RD_ADDR_marb_bp_rw_ack 40
-#define REG_WR_ADDR_marb_bp_rw_ack 40
-
-
-/* Constants */
-enum {
-  regk_marb_bp_no                          = 0x00000000,
-  regk_marb_bp_rw_op_default               = 0x00000000,
-  regk_marb_bp_rw_options_default          = 0x00000000,
-  regk_marb_bp_yes                         = 0x00000001
-};
-#endif /* __marb_bp_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/marb_defs.h b/include/asm-cris/arch-v32/hwregs/marb_defs.h
deleted file mode 100644
index 71e8af0bb3a4..000000000000
--- a/include/asm-cris/arch-v32/hwregs/marb_defs.h
+++ /dev/null
@@ -1,475 +0,0 @@
-#ifndef __marb_defs_h
-#define __marb_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:12:16 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
- *      id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb */
-
-#define STRIDE_marb_rw_int_slots 4
-/* Register rw_int_slots, scope marb, type rw */
-typedef struct {
-  unsigned int owner : 4;
-  unsigned int dummy1 : 28;
-} reg_marb_rw_int_slots;
-#define REG_RD_ADDR_marb_rw_int_slots 0
-#define REG_WR_ADDR_marb_rw_int_slots 0
-
-#define STRIDE_marb_rw_ext_slots 4
-/* Register rw_ext_slots, scope marb, type rw */
-typedef struct {
-  unsigned int owner : 4;
-  unsigned int dummy1 : 28;
-} reg_marb_rw_ext_slots;
-#define REG_RD_ADDR_marb_rw_ext_slots 256
-#define REG_WR_ADDR_marb_rw_ext_slots 256
-
-#define STRIDE_marb_rw_regs_slots 4
-/* Register rw_regs_slots, scope marb, type rw */
-typedef struct {
-  unsigned int owner : 4;
-  unsigned int dummy1 : 28;
-} reg_marb_rw_regs_slots;
-#define REG_RD_ADDR_marb_rw_regs_slots 512
-#define REG_WR_ADDR_marb_rw_regs_slots 512
-
-/* Register rw_intr_mask, scope marb, type rw */
-typedef struct {
-  unsigned int bp0 : 1;
-  unsigned int bp1 : 1;
-  unsigned int bp2 : 1;
-  unsigned int bp3 : 1;
-  unsigned int dummy1 : 28;
-} reg_marb_rw_intr_mask;
-#define REG_RD_ADDR_marb_rw_intr_mask 528
-#define REG_WR_ADDR_marb_rw_intr_mask 528
-
-/* Register rw_ack_intr, scope marb, type rw */
-typedef struct {
-  unsigned int bp0 : 1;
-  unsigned int bp1 : 1;
-  unsigned int bp2 : 1;
-  unsigned int bp3 : 1;
-  unsigned int dummy1 : 28;
-} reg_marb_rw_ack_intr;
-#define REG_RD_ADDR_marb_rw_ack_intr 532
-#define REG_WR_ADDR_marb_rw_ack_intr 532
-
-/* Register r_intr, scope marb, type r */
-typedef struct {
-  unsigned int bp0 : 1;
-  unsigned int bp1 : 1;
-  unsigned int bp2 : 1;
-  unsigned int bp3 : 1;
-  unsigned int dummy1 : 28;
-} reg_marb_r_intr;
-#define REG_RD_ADDR_marb_r_intr 536
-
-/* Register r_masked_intr, scope marb, type r */
-typedef struct {
-  unsigned int bp0 : 1;
-  unsigned int bp1 : 1;
-  unsigned int bp2 : 1;
-  unsigned int bp3 : 1;
-  unsigned int dummy1 : 28;
-} reg_marb_r_masked_intr;
-#define REG_RD_ADDR_marb_r_masked_intr 540
-
-/* Register rw_stop_mask, scope marb, type rw */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_rw_stop_mask;
-#define REG_RD_ADDR_marb_rw_stop_mask 544
-#define REG_WR_ADDR_marb_rw_stop_mask 544
-
-/* Register r_stopped, scope marb, type r */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_r_stopped;
-#define REG_RD_ADDR_marb_r_stopped 548
-
-/* Register rw_no_snoop, scope marb, type rw */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_rw_no_snoop;
-#define REG_RD_ADDR_marb_rw_no_snoop 832
-#define REG_WR_ADDR_marb_rw_no_snoop 832
-
-/* Register rw_no_snoop_rq, scope marb, type rw */
-typedef struct {
-  unsigned int dummy1 : 10;
-  unsigned int cpui : 1;
-  unsigned int cpud : 1;
-  unsigned int dummy2 : 20;
-} reg_marb_rw_no_snoop_rq;
-#define REG_RD_ADDR_marb_rw_no_snoop_rq 836
-#define REG_WR_ADDR_marb_rw_no_snoop_rq 836
-
-
-/* Constants */
-enum {
-  regk_marb_cpud                           = 0x0000000b,
-  regk_marb_cpui                           = 0x0000000a,
-  regk_marb_dma0                           = 0x00000000,
-  regk_marb_dma1                           = 0x00000001,
-  regk_marb_dma2                           = 0x00000002,
-  regk_marb_dma3                           = 0x00000003,
-  regk_marb_dma4                           = 0x00000004,
-  regk_marb_dma5                           = 0x00000005,
-  regk_marb_dma6                           = 0x00000006,
-  regk_marb_dma7                           = 0x00000007,
-  regk_marb_dma8                           = 0x00000008,
-  regk_marb_dma9                           = 0x00000009,
-  regk_marb_iop                            = 0x0000000c,
-  regk_marb_no                             = 0x00000000,
-  regk_marb_r_stopped_default              = 0x00000000,
-  regk_marb_rw_ext_slots_default           = 0x00000000,
-  regk_marb_rw_ext_slots_size              = 0x00000040,
-  regk_marb_rw_int_slots_default           = 0x00000000,
-  regk_marb_rw_int_slots_size              = 0x00000040,
-  regk_marb_rw_intr_mask_default           = 0x00000000,
-  regk_marb_rw_no_snoop_default            = 0x00000000,
-  regk_marb_rw_no_snoop_rq_default         = 0x00000000,
-  regk_marb_rw_regs_slots_default          = 0x00000000,
-  regk_marb_rw_regs_slots_size             = 0x00000004,
-  regk_marb_rw_stop_mask_default           = 0x00000000,
-  regk_marb_slave                          = 0x0000000d,
-  regk_marb_yes                            = 0x00000001
-};
-#endif /* __marb_defs_h */
-#ifndef __marb_bp_defs_h
-#define __marb_bp_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:12:16 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
- *      id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_bp */
-
-/* Register rw_first_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_bp, type rw */
-typedef struct {
-  unsigned int rd         : 1;
-  unsigned int wr         : 1;
-  unsigned int rd_excl    : 1;
-  unsigned int pri_wr     : 1;
-  unsigned int us_rd      : 1;
-  unsigned int us_wr      : 1;
-  unsigned int us_rd_excl : 1;
-  unsigned int us_pri_wr  : 1;
-  unsigned int dummy1     : 24;
-} reg_marb_bp_rw_op;
-#define REG_RD_ADDR_marb_bp_rw_op 8
-#define REG_WR_ADDR_marb_bp_rw_op 8
-
-/* Register rw_clients, scope marb_bp, type rw */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_bp_rw_clients;
-#define REG_RD_ADDR_marb_bp_rw_clients 12
-#define REG_WR_ADDR_marb_bp_rw_clients 12
-
-/* Register rw_options, scope marb_bp, type rw */
-typedef struct {
-  unsigned int wrap : 1;
-  unsigned int dummy1 : 31;
-} reg_marb_bp_rw_options;
-#define REG_RD_ADDR_marb_bp_rw_options 16
-#define REG_WR_ADDR_marb_bp_rw_options 16
-
-/* Register r_brk_addr, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_brk_addr;
-#define REG_RD_ADDR_marb_bp_r_brk_addr 20
-
-/* Register r_brk_op, scope marb_bp, type r */
-typedef struct {
-  unsigned int rd         : 1;
-  unsigned int wr         : 1;
-  unsigned int rd_excl    : 1;
-  unsigned int pri_wr     : 1;
-  unsigned int us_rd      : 1;
-  unsigned int us_wr      : 1;
-  unsigned int us_rd_excl : 1;
-  unsigned int us_pri_wr  : 1;
-  unsigned int dummy1     : 24;
-} reg_marb_bp_r_brk_op;
-#define REG_RD_ADDR_marb_bp_r_brk_op 24
-
-/* Register r_brk_clients, scope marb_bp, type r */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_bp_r_brk_clients;
-#define REG_RD_ADDR_marb_bp_r_brk_clients 28
-
-/* Register r_brk_first_client, scope marb_bp, type r */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_bp_r_brk_first_client;
-#define REG_RD_ADDR_marb_bp_r_brk_first_client 32
-
-/* Register r_brk_size, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_brk_size;
-#define REG_RD_ADDR_marb_bp_r_brk_size 36
-
-/* Register rw_ack, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_ack;
-#define REG_RD_ADDR_marb_bp_rw_ack 40
-#define REG_WR_ADDR_marb_bp_rw_ack 40
-
-
-/* Constants */
-enum {
-  regk_marb_bp_no                          = 0x00000000,
-  regk_marb_bp_rw_op_default               = 0x00000000,
-  regk_marb_bp_rw_options_default          = 0x00000000,
-  regk_marb_bp_yes                         = 0x00000001
-};
-#endif /* __marb_bp_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/hwregs/pinmux_defs.h
deleted file mode 100644
index 9d91c2de1b07..000000000000
--- a/include/asm-cris/arch-v32/hwregs/pinmux_defs.h
+++ /dev/null
@@ -1,357 +0,0 @@
-#ifndef __pinmux_defs_h
-#define __pinmux_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/pinmux/rtl/guinness/pinmux_regs.r
- *     id:           pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
- *     last modfied: Mon Apr 11 16:09:11 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
- *      id: $Id: pinmux_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope pinmux */
-
-/* Register rw_pa, scope pinmux, type rw */
-typedef struct {
-  unsigned int pa0    : 1;
-  unsigned int pa1    : 1;
-  unsigned int pa2    : 1;
-  unsigned int pa3    : 1;
-  unsigned int pa4    : 1;
-  unsigned int pa5    : 1;
-  unsigned int pa6    : 1;
-  unsigned int pa7    : 1;
-  unsigned int csp2_n : 1;
-  unsigned int csp3_n : 1;
-  unsigned int csp5_n : 1;
-  unsigned int csp6_n : 1;
-  unsigned int hsh4   : 1;
-  unsigned int hsh5   : 1;
-  unsigned int hsh6   : 1;
-  unsigned int hsh7   : 1;
-  unsigned int dummy1 : 16;
-} reg_pinmux_rw_pa;
-#define REG_RD_ADDR_pinmux_rw_pa 0
-#define REG_WR_ADDR_pinmux_rw_pa 0
-
-/* Register rw_hwprot, scope pinmux, type rw */
-typedef struct {
-  unsigned int ser1     : 1;
-  unsigned int ser2     : 1;
-  unsigned int ser3     : 1;
-  unsigned int sser0    : 1;
-  unsigned int sser1    : 1;
-  unsigned int ata0     : 1;
-  unsigned int ata1     : 1;
-  unsigned int ata2     : 1;
-  unsigned int ata3     : 1;
-  unsigned int ata      : 1;
-  unsigned int eth1     : 1;
-  unsigned int eth1_mgm : 1;
-  unsigned int timer    : 1;
-  unsigned int p21      : 1;
-  unsigned int dummy1   : 18;
-} reg_pinmux_rw_hwprot;
-#define REG_RD_ADDR_pinmux_rw_hwprot 4
-#define REG_WR_ADDR_pinmux_rw_hwprot 4
-
-/* Register rw_pb_gio, scope pinmux, type rw */
-typedef struct {
-  unsigned int pb0  : 1;
-  unsigned int pb1  : 1;
-  unsigned int pb2  : 1;
-  unsigned int pb3  : 1;
-  unsigned int pb4  : 1;
-  unsigned int pb5  : 1;
-  unsigned int pb6  : 1;
-  unsigned int pb7  : 1;
-  unsigned int pb8  : 1;
-  unsigned int pb9  : 1;
-  unsigned int pb10 : 1;
-  unsigned int pb11 : 1;
-  unsigned int pb12 : 1;
-  unsigned int pb13 : 1;
-  unsigned int pb14 : 1;
-  unsigned int pb15 : 1;
-  unsigned int pb16 : 1;
-  unsigned int pb17 : 1;
-  unsigned int dummy1 : 14;
-} reg_pinmux_rw_pb_gio;
-#define REG_RD_ADDR_pinmux_rw_pb_gio 8
-#define REG_WR_ADDR_pinmux_rw_pb_gio 8
-
-/* Register rw_pb_iop, scope pinmux, type rw */
-typedef struct {
-  unsigned int pb0  : 1;
-  unsigned int pb1  : 1;
-  unsigned int pb2  : 1;
-  unsigned int pb3  : 1;
-  unsigned int pb4  : 1;
-  unsigned int pb5  : 1;
-  unsigned int pb6  : 1;
-  unsigned int pb7  : 1;
-  unsigned int pb8  : 1;
-  unsigned int pb9  : 1;
-  unsigned int pb10 : 1;
-  unsigned int pb11 : 1;
-  unsigned int pb12 : 1;
-  unsigned int pb13 : 1;
-  unsigned int pb14 : 1;
-  unsigned int pb15 : 1;
-  unsigned int pb16 : 1;
-  unsigned int pb17 : 1;
-  unsigned int dummy1 : 14;
-} reg_pinmux_rw_pb_iop;
-#define REG_RD_ADDR_pinmux_rw_pb_iop 12
-#define REG_WR_ADDR_pinmux_rw_pb_iop 12
-
-/* Register rw_pc_gio, scope pinmux, type rw */
-typedef struct {
-  unsigned int pc0  : 1;
-  unsigned int pc1  : 1;
-  unsigned int pc2  : 1;
-  unsigned int pc3  : 1;
-  unsigned int pc4  : 1;
-  unsigned int pc5  : 1;
-  unsigned int pc6  : 1;
-  unsigned int pc7  : 1;
-  unsigned int pc8  : 1;
-  unsigned int pc9  : 1;
-  unsigned int pc10 : 1;
-  unsigned int pc11 : 1;
-  unsigned int pc12 : 1;
-  unsigned int pc13 : 1;
-  unsigned int pc14 : 1;
-  unsigned int pc15 : 1;
-  unsigned int pc16 : 1;
-  unsigned int pc17 : 1;
-  unsigned int dummy1 : 14;
-} reg_pinmux_rw_pc_gio;
-#define REG_RD_ADDR_pinmux_rw_pc_gio 16
-#define REG_WR_ADDR_pinmux_rw_pc_gio 16
-
-/* Register rw_pc_iop, scope pinmux, type rw */
-typedef struct {
-  unsigned int pc0  : 1;
-  unsigned int pc1  : 1;
-  unsigned int pc2  : 1;
-  unsigned int pc3  : 1;
-  unsigned int pc4  : 1;
-  unsigned int pc5  : 1;
-  unsigned int pc6  : 1;
-  unsigned int pc7  : 1;
-  unsigned int pc8  : 1;
-  unsigned int pc9  : 1;
-  unsigned int pc10 : 1;
-  unsigned int pc11 : 1;
-  unsigned int pc12 : 1;
-  unsigned int pc13 : 1;
-  unsigned int pc14 : 1;
-  unsigned int pc15 : 1;
-  unsigned int pc16 : 1;
-  unsigned int pc17 : 1;
-  unsigned int dummy1 : 14;
-} reg_pinmux_rw_pc_iop;
-#define REG_RD_ADDR_pinmux_rw_pc_iop 20
-#define REG_WR_ADDR_pinmux_rw_pc_iop 20
-
-/* Register rw_pd_gio, scope pinmux, type rw */
-typedef struct {
-  unsigned int pd0  : 1;
-  unsigned int pd1  : 1;
-  unsigned int pd2  : 1;
-  unsigned int pd3  : 1;
-  unsigned int pd4  : 1;
-  unsigned int pd5  : 1;
-  unsigned int pd6  : 1;
-  unsigned int pd7  : 1;
-  unsigned int pd8  : 1;
-  unsigned int pd9  : 1;
-  unsigned int pd10 : 1;
-  unsigned int pd11 : 1;
-  unsigned int pd12 : 1;
-  unsigned int pd13 : 1;
-  unsigned int pd14 : 1;
-  unsigned int pd15 : 1;
-  unsigned int pd16 : 1;
-  unsigned int pd17 : 1;
-  unsigned int dummy1 : 14;
-} reg_pinmux_rw_pd_gio;
-#define REG_RD_ADDR_pinmux_rw_pd_gio 24
-#define REG_WR_ADDR_pinmux_rw_pd_gio 24
-
-/* Register rw_pd_iop, scope pinmux, type rw */
-typedef struct {
-  unsigned int pd0  : 1;
-  unsigned int pd1  : 1;
-  unsigned int pd2  : 1;
-  unsigned int pd3  : 1;
-  unsigned int pd4  : 1;
-  unsigned int pd5  : 1;
-  unsigned int pd6  : 1;
-  unsigned int pd7  : 1;
-  unsigned int pd8  : 1;
-  unsigned int pd9  : 1;
-  unsigned int pd10 : 1;
-  unsigned int pd11 : 1;
-  unsigned int pd12 : 1;
-  unsigned int pd13 : 1;
-  unsigned int pd14 : 1;
-  unsigned int pd15 : 1;
-  unsigned int pd16 : 1;
-  unsigned int pd17 : 1;
-  unsigned int dummy1 : 14;
-} reg_pinmux_rw_pd_iop;
-#define REG_RD_ADDR_pinmux_rw_pd_iop 28
-#define REG_WR_ADDR_pinmux_rw_pd_iop 28
-
-/* Register rw_pe_gio, scope pinmux, type rw */
-typedef struct {
-  unsigned int pe0  : 1;
-  unsigned int pe1  : 1;
-  unsigned int pe2  : 1;
-  unsigned int pe3  : 1;
-  unsigned int pe4  : 1;
-  unsigned int pe5  : 1;
-  unsigned int pe6  : 1;
-  unsigned int pe7  : 1;
-  unsigned int pe8  : 1;
-  unsigned int pe9  : 1;
-  unsigned int pe10 : 1;
-  unsigned int pe11 : 1;
-  unsigned int pe12 : 1;
-  unsigned int pe13 : 1;
-  unsigned int pe14 : 1;
-  unsigned int pe15 : 1;
-  unsigned int pe16 : 1;
-  unsigned int pe17 : 1;
-  unsigned int dummy1 : 14;
-} reg_pinmux_rw_pe_gio;
-#define REG_RD_ADDR_pinmux_rw_pe_gio 32
-#define REG_WR_ADDR_pinmux_rw_pe_gio 32
-
-/* Register rw_pe_iop, scope pinmux, type rw */
-typedef struct {
-  unsigned int pe0  : 1;
-  unsigned int pe1  : 1;
-  unsigned int pe2  : 1;
-  unsigned int pe3  : 1;
-  unsigned int pe4  : 1;
-  unsigned int pe5  : 1;
-  unsigned int pe6  : 1;
-  unsigned int pe7  : 1;
-  unsigned int pe8  : 1;
-  unsigned int pe9  : 1;
-  unsigned int pe10 : 1;
-  unsigned int pe11 : 1;
-  unsigned int pe12 : 1;
-  unsigned int pe13 : 1;
-  unsigned int pe14 : 1;
-  unsigned int pe15 : 1;
-  unsigned int pe16 : 1;
-  unsigned int pe17 : 1;
-  unsigned int dummy1 : 14;
-} reg_pinmux_rw_pe_iop;
-#define REG_RD_ADDR_pinmux_rw_pe_iop 36
-#define REG_WR_ADDR_pinmux_rw_pe_iop 36
-
-/* Register rw_usb_phy, scope pinmux, type rw */
-typedef struct {
-  unsigned int en_usb0 : 1;
-  unsigned int en_usb1 : 1;
-  unsigned int dummy1  : 30;
-} reg_pinmux_rw_usb_phy;
-#define REG_RD_ADDR_pinmux_rw_usb_phy 40
-#define REG_WR_ADDR_pinmux_rw_usb_phy 40
-
-
-/* Constants */
-enum {
-  regk_pinmux_no                           = 0x00000000,
-  regk_pinmux_rw_hwprot_default            = 0x00000000,
-  regk_pinmux_rw_pa_default                = 0x00000000,
-  regk_pinmux_rw_pb_gio_default            = 0x00000000,
-  regk_pinmux_rw_pb_iop_default            = 0x00000000,
-  regk_pinmux_rw_pc_gio_default            = 0x00000000,
-  regk_pinmux_rw_pc_iop_default            = 0x00000000,
-  regk_pinmux_rw_pd_gio_default            = 0x00000000,
-  regk_pinmux_rw_pd_iop_default            = 0x00000000,
-  regk_pinmux_rw_pe_gio_default            = 0x00000000,
-  regk_pinmux_rw_pe_iop_default            = 0x00000000,
-  regk_pinmux_rw_usb_phy_default           = 0x00000000,
-  regk_pinmux_yes                          = 0x00000001
-};
-#endif /* __pinmux_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/reg_rdwr.h b/include/asm-cris/arch-v32/hwregs/reg_rdwr.h
deleted file mode 100644
index 236f91efe7e8..000000000000
--- a/include/asm-cris/arch-v32/hwregs/reg_rdwr.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Read/write register macros used by *_defs.h
- */
-
-#ifndef reg_rdwr_h
-#define reg_rdwr_h
-
-#ifndef REG_READ
-#define REG_READ(type, addr) (*((volatile type *) (addr)))
-#endif
-
-#ifndef REG_WRITE
-#define REG_WRITE(type, addr, val) \
-   do { *((volatile type *) (addr)) = (val); } while(0)
-#endif
-
-#endif
diff --git a/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h b/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h
deleted file mode 100644
index d9f0e924fb23..000000000000
--- a/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h
+++ /dev/null
@@ -1,173 +0,0 @@
-#ifndef __rt_trace_defs_h
-#define __rt_trace_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/rt_trace/rtl/rt_regs.r
- *     id:           rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp
- *     last modfied: Mon Apr 11 16:09:14 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile rt_trace_defs.h ../../inst/rt_trace/rtl/rt_regs.r
- *      id: $Id: rt_trace_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope rt_trace */
-
-/* Register rw_cfg, scope rt_trace, type rw */
-typedef struct {
-  unsigned int en       : 1;
-  unsigned int mode     : 1;
-  unsigned int owner    : 1;
-  unsigned int wp       : 1;
-  unsigned int stall    : 1;
-  unsigned int dummy1   : 3;
-  unsigned int wp_start : 7;
-  unsigned int dummy2   : 1;
-  unsigned int wp_stop  : 7;
-  unsigned int dummy3   : 9;
-} reg_rt_trace_rw_cfg;
-#define REG_RD_ADDR_rt_trace_rw_cfg 0
-#define REG_WR_ADDR_rt_trace_rw_cfg 0
-
-/* Register rw_tap_ctrl, scope rt_trace, type rw */
-typedef struct {
-  unsigned int ack_data : 1;
-  unsigned int ack_guru : 1;
-  unsigned int dummy1   : 30;
-} reg_rt_trace_rw_tap_ctrl;
-#define REG_RD_ADDR_rt_trace_rw_tap_ctrl 4
-#define REG_WR_ADDR_rt_trace_rw_tap_ctrl 4
-
-/* Register r_tap_stat, scope rt_trace, type r */
-typedef struct {
-  unsigned int dav   : 1;
-  unsigned int empty : 1;
-  unsigned int dummy1 : 30;
-} reg_rt_trace_r_tap_stat;
-#define REG_RD_ADDR_rt_trace_r_tap_stat 8
-
-/* Register rw_tap_data, scope rt_trace, type rw */
-typedef unsigned int reg_rt_trace_rw_tap_data;
-#define REG_RD_ADDR_rt_trace_rw_tap_data 12
-#define REG_WR_ADDR_rt_trace_rw_tap_data 12
-
-/* Register rw_tap_hdata, scope rt_trace, type rw */
-typedef struct {
-  unsigned int op     : 4;
-  unsigned int sub_op : 4;
-  unsigned int dummy1 : 24;
-} reg_rt_trace_rw_tap_hdata;
-#define REG_RD_ADDR_rt_trace_rw_tap_hdata 16
-#define REG_WR_ADDR_rt_trace_rw_tap_hdata 16
-
-/* Register r_redir, scope rt_trace, type r */
-typedef unsigned int reg_rt_trace_r_redir;
-#define REG_RD_ADDR_rt_trace_r_redir 20
-
-
-/* Constants */
-enum {
-  regk_rt_trace_brk                        = 0x0000000c,
-  regk_rt_trace_dbg                        = 0x00000003,
-  regk_rt_trace_dbgdi                      = 0x00000004,
-  regk_rt_trace_dbgdo                      = 0x00000005,
-  regk_rt_trace_gmode                      = 0x00000000,
-  regk_rt_trace_no                         = 0x00000000,
-  regk_rt_trace_nop                        = 0x00000000,
-  regk_rt_trace_normal                     = 0x00000000,
-  regk_rt_trace_rdmem                      = 0x00000007,
-  regk_rt_trace_rdmemb                     = 0x00000009,
-  regk_rt_trace_rdpreg                     = 0x00000002,
-  regk_rt_trace_rdreg                      = 0x00000001,
-  regk_rt_trace_rdsreg                     = 0x00000003,
-  regk_rt_trace_redir                      = 0x00000006,
-  regk_rt_trace_ret                        = 0x0000000b,
-  regk_rt_trace_rw_cfg_default             = 0x00000000,
-  regk_rt_trace_trcfg                      = 0x00000001,
-  regk_rt_trace_wp                         = 0x00000001,
-  regk_rt_trace_wp0                        = 0x00000001,
-  regk_rt_trace_wp1                        = 0x00000002,
-  regk_rt_trace_wp2                        = 0x00000004,
-  regk_rt_trace_wp3                        = 0x00000008,
-  regk_rt_trace_wp4                        = 0x00000010,
-  regk_rt_trace_wp5                        = 0x00000020,
-  regk_rt_trace_wp6                        = 0x00000040,
-  regk_rt_trace_wrmem                      = 0x00000008,
-  regk_rt_trace_wrmemb                     = 0x0000000a,
-  regk_rt_trace_wrpreg                     = 0x00000005,
-  regk_rt_trace_wrreg                      = 0x00000004,
-  regk_rt_trace_wrsreg                     = 0x00000006,
-  regk_rt_trace_yes                        = 0x00000001
-};
-#endif /* __rt_trace_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/ser_defs.h b/include/asm-cris/arch-v32/hwregs/ser_defs.h
deleted file mode 100644
index 01c2fab97d43..000000000000
--- a/include/asm-cris/arch-v32/hwregs/ser_defs.h
+++ /dev/null
@@ -1,308 +0,0 @@
-#ifndef __ser_defs_h
-#define __ser_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/ser/rtl/ser_regs.r
- *     id:           ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp
- *     last modfied: Mon Apr 11 16:09:21 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r
- *      id: $Id: ser_defs.h,v 1.10 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope ser */
-
-/* Register rw_tr_ctrl, scope ser, type rw */
-typedef struct {
-  unsigned int base_freq : 3;
-  unsigned int en        : 1;
-  unsigned int par       : 2;
-  unsigned int par_en    : 1;
-  unsigned int data_bits : 1;
-  unsigned int stop_bits : 1;
-  unsigned int stop      : 1;
-  unsigned int rts_delay : 3;
-  unsigned int rts_setup : 1;
-  unsigned int auto_rts  : 1;
-  unsigned int txd       : 1;
-  unsigned int auto_cts  : 1;
-  unsigned int dummy1    : 15;
-} reg_ser_rw_tr_ctrl;
-#define REG_RD_ADDR_ser_rw_tr_ctrl 0
-#define REG_WR_ADDR_ser_rw_tr_ctrl 0
-
-/* Register rw_tr_dma_en, scope ser, type rw */
-typedef struct {
-  unsigned int en : 1;
-  unsigned int dummy1 : 31;
-} reg_ser_rw_tr_dma_en;
-#define REG_RD_ADDR_ser_rw_tr_dma_en 4
-#define REG_WR_ADDR_ser_rw_tr_dma_en 4
-
-/* Register rw_rec_ctrl, scope ser, type rw */
-typedef struct {
-  unsigned int base_freq   : 3;
-  unsigned int en          : 1;
-  unsigned int par         : 2;
-  unsigned int par_en      : 1;
-  unsigned int data_bits   : 1;
-  unsigned int dma_mode    : 1;
-  unsigned int dma_err     : 1;
-  unsigned int sampling    : 1;
-  unsigned int timeout     : 3;
-  unsigned int auto_eop    : 1;
-  unsigned int half_duplex : 1;
-  unsigned int rts_n       : 1;
-  unsigned int loopback    : 1;
-  unsigned int dummy1      : 14;
-} reg_ser_rw_rec_ctrl;
-#define REG_RD_ADDR_ser_rw_rec_ctrl 8
-#define REG_WR_ADDR_ser_rw_rec_ctrl 8
-
-/* Register rw_tr_baud_div, scope ser, type rw */
-typedef struct {
-  unsigned int div : 16;
-  unsigned int dummy1 : 16;
-} reg_ser_rw_tr_baud_div;
-#define REG_RD_ADDR_ser_rw_tr_baud_div 12
-#define REG_WR_ADDR_ser_rw_tr_baud_div 12
-
-/* Register rw_rec_baud_div, scope ser, type rw */
-typedef struct {
-  unsigned int div : 16;
-  unsigned int dummy1 : 16;
-} reg_ser_rw_rec_baud_div;
-#define REG_RD_ADDR_ser_rw_rec_baud_div 16
-#define REG_WR_ADDR_ser_rw_rec_baud_div 16
-
-/* Register rw_xoff, scope ser, type rw */
-typedef struct {
-  unsigned int chr       : 8;
-  unsigned int automatic : 1;
-  unsigned int dummy1    : 23;
-} reg_ser_rw_xoff;
-#define REG_RD_ADDR_ser_rw_xoff 20
-#define REG_WR_ADDR_ser_rw_xoff 20
-
-/* Register rw_xoff_clr, scope ser, type rw */
-typedef struct {
-  unsigned int clr : 1;
-  unsigned int dummy1 : 31;
-} reg_ser_rw_xoff_clr;
-#define REG_RD_ADDR_ser_rw_xoff_clr 24
-#define REG_WR_ADDR_ser_rw_xoff_clr 24
-
-/* Register rw_dout, scope ser, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_ser_rw_dout;
-#define REG_RD_ADDR_ser_rw_dout 28
-#define REG_WR_ADDR_ser_rw_dout 28
-
-/* Register rs_stat_din, scope ser, type rs */
-typedef struct {
-  unsigned int data        : 8;
-  unsigned int dummy1      : 8;
-  unsigned int dav         : 1;
-  unsigned int framing_err : 1;
-  unsigned int par_err     : 1;
-  unsigned int orun        : 1;
-  unsigned int rec_err     : 1;
-  unsigned int rxd         : 1;
-  unsigned int tr_idle     : 1;
-  unsigned int tr_empty    : 1;
-  unsigned int tr_rdy      : 1;
-  unsigned int cts_n       : 1;
-  unsigned int xoff_detect : 1;
-  unsigned int rts_n       : 1;
-  unsigned int txd         : 1;
-  unsigned int dummy2      : 3;
-} reg_ser_rs_stat_din;
-#define REG_RD_ADDR_ser_rs_stat_din 32
-
-/* Register r_stat_din, scope ser, type r */
-typedef struct {
-  unsigned int data        : 8;
-  unsigned int dummy1      : 8;
-  unsigned int dav         : 1;
-  unsigned int framing_err : 1;
-  unsigned int par_err     : 1;
-  unsigned int orun        : 1;
-  unsigned int rec_err     : 1;
-  unsigned int rxd         : 1;
-  unsigned int tr_idle     : 1;
-  unsigned int tr_empty    : 1;
-  unsigned int tr_rdy      : 1;
-  unsigned int cts_n       : 1;
-  unsigned int xoff_detect : 1;
-  unsigned int rts_n       : 1;
-  unsigned int txd         : 1;
-  unsigned int dummy2      : 3;
-} reg_ser_r_stat_din;
-#define REG_RD_ADDR_ser_r_stat_din 36
-
-/* Register rw_rec_eop, scope ser, type rw */
-typedef struct {
-  unsigned int set : 1;
-  unsigned int dummy1 : 31;
-} reg_ser_rw_rec_eop;
-#define REG_RD_ADDR_ser_rw_rec_eop 40
-#define REG_WR_ADDR_ser_rw_rec_eop 40
-
-/* Register rw_intr_mask, scope ser, type rw */
-typedef struct {
-  unsigned int tr_rdy   : 1;
-  unsigned int tr_empty : 1;
-  unsigned int tr_idle  : 1;
-  unsigned int dav      : 1;
-  unsigned int dummy1   : 28;
-} reg_ser_rw_intr_mask;
-#define REG_RD_ADDR_ser_rw_intr_mask 44
-#define REG_WR_ADDR_ser_rw_intr_mask 44
-
-/* Register rw_ack_intr, scope ser, type rw */
-typedef struct {
-  unsigned int tr_rdy   : 1;
-  unsigned int tr_empty : 1;
-  unsigned int tr_idle  : 1;
-  unsigned int dav      : 1;
-  unsigned int dummy1   : 28;
-} reg_ser_rw_ack_intr;
-#define REG_RD_ADDR_ser_rw_ack_intr 48
-#define REG_WR_ADDR_ser_rw_ack_intr 48
-
-/* Register r_intr, scope ser, type r */
-typedef struct {
-  unsigned int tr_rdy   : 1;
-  unsigned int tr_empty : 1;
-  unsigned int tr_idle  : 1;
-  unsigned int dav      : 1;
-  unsigned int dummy1   : 28;
-} reg_ser_r_intr;
-#define REG_RD_ADDR_ser_r_intr 52
-
-/* Register r_masked_intr, scope ser, type r */
-typedef struct {
-  unsigned int tr_rdy   : 1;
-  unsigned int tr_empty : 1;
-  unsigned int tr_idle  : 1;
-  unsigned int dav      : 1;
-  unsigned int dummy1   : 28;
-} reg_ser_r_masked_intr;
-#define REG_RD_ADDR_ser_r_masked_intr 56
-
-
-/* Constants */
-enum {
-  regk_ser_active                          = 0x00000000,
-  regk_ser_bits1                           = 0x00000000,
-  regk_ser_bits2                           = 0x00000001,
-  regk_ser_bits7                           = 0x00000001,
-  regk_ser_bits8                           = 0x00000000,
-  regk_ser_del0_5                          = 0x00000000,
-  regk_ser_del1                            = 0x00000001,
-  regk_ser_del1_5                          = 0x00000002,
-  regk_ser_del2                            = 0x00000003,
-  regk_ser_del2_5                          = 0x00000004,
-  regk_ser_del3                            = 0x00000005,
-  regk_ser_del3_5                          = 0x00000006,
-  regk_ser_del4                            = 0x00000007,
-  regk_ser_even                            = 0x00000000,
-  regk_ser_ext                             = 0x00000001,
-  regk_ser_f100                            = 0x00000007,
-  regk_ser_f29_493                         = 0x00000004,
-  regk_ser_f32                             = 0x00000005,
-  regk_ser_f32_768                         = 0x00000006,
-  regk_ser_ignore                          = 0x00000001,
-  regk_ser_inactive                        = 0x00000001,
-  regk_ser_majority                        = 0x00000001,
-  regk_ser_mark                            = 0x00000002,
-  regk_ser_middle                          = 0x00000000,
-  regk_ser_no                              = 0x00000000,
-  regk_ser_odd                             = 0x00000001,
-  regk_ser_off                             = 0x00000000,
-  regk_ser_rw_intr_mask_default            = 0x00000000,
-  regk_ser_rw_rec_baud_div_default         = 0x00000000,
-  regk_ser_rw_rec_ctrl_default             = 0x00010000,
-  regk_ser_rw_tr_baud_div_default          = 0x00000000,
-  regk_ser_rw_tr_ctrl_default              = 0x00008000,
-  regk_ser_rw_tr_dma_en_default            = 0x00000000,
-  regk_ser_rw_xoff_default                 = 0x00000000,
-  regk_ser_space                           = 0x00000003,
-  regk_ser_stop                            = 0x00000000,
-  regk_ser_yes                             = 0x00000001
-};
-#endif /* __ser_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/sser_defs.h b/include/asm-cris/arch-v32/hwregs/sser_defs.h
deleted file mode 100644
index 8d1dab218b91..000000000000
--- a/include/asm-cris/arch-v32/hwregs/sser_defs.h
+++ /dev/null
@@ -1,331 +0,0 @@
-#ifndef __sser_defs_h
-#define __sser_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/syncser/rtl/sser_regs.r
- *     id:           sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp
- *     last modfied: Mon Apr 11 16:09:48 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile sser_defs.h ../../inst/syncser/rtl/sser_regs.r
- *      id: $Id: sser_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope sser */
-
-/* Register rw_cfg, scope sser, type rw */
-typedef struct {
-  unsigned int clk_div      : 16;
-  unsigned int base_freq    : 3;
-  unsigned int gate_clk     : 1;
-  unsigned int clkgate_ctrl : 1;
-  unsigned int clkgate_in   : 1;
-  unsigned int clk_dir      : 1;
-  unsigned int clk_od_mode  : 1;
-  unsigned int out_clk_pol  : 1;
-  unsigned int out_clk_src  : 2;
-  unsigned int clk_in_sel   : 1;
-  unsigned int hold_pol     : 1;
-  unsigned int prepare      : 1;
-  unsigned int en           : 1;
-  unsigned int dummy1       : 1;
-} reg_sser_rw_cfg;
-#define REG_RD_ADDR_sser_rw_cfg 0
-#define REG_WR_ADDR_sser_rw_cfg 0
-
-/* Register rw_frm_cfg, scope sser, type rw */
-typedef struct {
-  unsigned int wordrate       : 10;
-  unsigned int rec_delay      : 3;
-  unsigned int tr_delay       : 3;
-  unsigned int early_wend     : 1;
-  unsigned int level          : 2;
-  unsigned int type           : 1;
-  unsigned int clk_pol        : 1;
-  unsigned int fr_in_rxclk    : 1;
-  unsigned int clk_src        : 1;
-  unsigned int out_off        : 1;
-  unsigned int out_on         : 1;
-  unsigned int frame_pin_dir  : 1;
-  unsigned int frame_pin_use  : 2;
-  unsigned int status_pin_dir : 1;
-  unsigned int status_pin_use : 2;
-  unsigned int dummy1         : 1;
-} reg_sser_rw_frm_cfg;
-#define REG_RD_ADDR_sser_rw_frm_cfg 4
-#define REG_WR_ADDR_sser_rw_frm_cfg 4
-
-/* Register rw_tr_cfg, scope sser, type rw */
-typedef struct {
-  unsigned int tr_en          : 1;
-  unsigned int stop           : 1;
-  unsigned int urun_stop      : 1;
-  unsigned int eop_stop       : 1;
-  unsigned int sample_size    : 6;
-  unsigned int sh_dir         : 1;
-  unsigned int clk_pol        : 1;
-  unsigned int clk_src        : 1;
-  unsigned int use_dma        : 1;
-  unsigned int mode           : 2;
-  unsigned int frm_src        : 1;
-  unsigned int use60958       : 1;
-  unsigned int iec60958_ckdiv : 2;
-  unsigned int rate_ctrl      : 1;
-  unsigned int use_md         : 1;
-  unsigned int dual_i2s       : 1;
-  unsigned int data_pin_use   : 2;
-  unsigned int od_mode        : 1;
-  unsigned int bulk_wspace    : 2;
-  unsigned int dummy1         : 4;
-} reg_sser_rw_tr_cfg;
-#define REG_RD_ADDR_sser_rw_tr_cfg 8
-#define REG_WR_ADDR_sser_rw_tr_cfg 8
-
-/* Register rw_rec_cfg, scope sser, type rw */
-typedef struct {
-  unsigned int rec_en          : 1;
-  unsigned int force_eop       : 1;
-  unsigned int stop            : 1;
-  unsigned int orun_stop       : 1;
-  unsigned int eop_stop        : 1;
-  unsigned int sample_size     : 6;
-  unsigned int sh_dir          : 1;
-  unsigned int clk_pol         : 1;
-  unsigned int clk_src         : 1;
-  unsigned int use_dma         : 1;
-  unsigned int mode            : 2;
-  unsigned int frm_src         : 2;
-  unsigned int use60958        : 1;
-  unsigned int iec60958_ui_len : 5;
-  unsigned int slave2_en       : 1;
-  unsigned int slave3_en       : 1;
-  unsigned int fifo_thr        : 2;
-  unsigned int dummy1          : 3;
-} reg_sser_rw_rec_cfg;
-#define REG_RD_ADDR_sser_rw_rec_cfg 12
-#define REG_WR_ADDR_sser_rw_rec_cfg 12
-
-/* Register rw_tr_data, scope sser, type rw */
-typedef struct {
-  unsigned int data : 16;
-  unsigned int md   : 1;
-  unsigned int dummy1 : 15;
-} reg_sser_rw_tr_data;
-#define REG_RD_ADDR_sser_rw_tr_data 16
-#define REG_WR_ADDR_sser_rw_tr_data 16
-
-/* Register r_rec_data, scope sser, type r */
-typedef struct {
-  unsigned int data      : 16;
-  unsigned int md        : 1;
-  unsigned int ext_clk   : 1;
-  unsigned int status_in : 1;
-  unsigned int frame_in  : 1;
-  unsigned int din       : 1;
-  unsigned int data_in   : 1;
-  unsigned int clk_in    : 1;
-  unsigned int dummy1    : 9;
-} reg_sser_r_rec_data;
-#define REG_RD_ADDR_sser_r_rec_data 20
-
-/* Register rw_extra, scope sser, type rw */
-typedef struct {
-  unsigned int clkoff_cycles : 20;
-  unsigned int clkoff_en     : 1;
-  unsigned int clkon_en      : 1;
-  unsigned int dout_delay    : 5;
-  unsigned int dummy1        : 5;
-} reg_sser_rw_extra;
-#define REG_RD_ADDR_sser_rw_extra 24
-#define REG_WR_ADDR_sser_rw_extra 24
-
-/* Register rw_intr_mask, scope sser, type rw */
-typedef struct {
-  unsigned int trdy    : 1;
-  unsigned int rdav    : 1;
-  unsigned int tidle   : 1;
-  unsigned int rstop   : 1;
-  unsigned int urun    : 1;
-  unsigned int orun    : 1;
-  unsigned int md_rec  : 1;
-  unsigned int md_sent : 1;
-  unsigned int r958err : 1;
-  unsigned int dummy1  : 23;
-} reg_sser_rw_intr_mask;
-#define REG_RD_ADDR_sser_rw_intr_mask 28
-#define REG_WR_ADDR_sser_rw_intr_mask 28
-
-/* Register rw_ack_intr, scope sser, type rw */
-typedef struct {
-  unsigned int trdy    : 1;
-  unsigned int rdav    : 1;
-  unsigned int tidle   : 1;
-  unsigned int rstop   : 1;
-  unsigned int urun    : 1;
-  unsigned int orun    : 1;
-  unsigned int md_rec  : 1;
-  unsigned int md_sent : 1;
-  unsigned int r958err : 1;
-  unsigned int dummy1  : 23;
-} reg_sser_rw_ack_intr;
-#define REG_RD_ADDR_sser_rw_ack_intr 32
-#define REG_WR_ADDR_sser_rw_ack_intr 32
-
-/* Register r_intr, scope sser, type r */
-typedef struct {
-  unsigned int trdy    : 1;
-  unsigned int rdav    : 1;
-  unsigned int tidle   : 1;
-  unsigned int rstop   : 1;
-  unsigned int urun    : 1;
-  unsigned int orun    : 1;
-  unsigned int md_rec  : 1;
-  unsigned int md_sent : 1;
-  unsigned int r958err : 1;
-  unsigned int dummy1  : 23;
-} reg_sser_r_intr;
-#define REG_RD_ADDR_sser_r_intr 36
-
-/* Register r_masked_intr, scope sser, type r */
-typedef struct {
-  unsigned int trdy    : 1;
-  unsigned int rdav    : 1;
-  unsigned int tidle   : 1;
-  unsigned int rstop   : 1;
-  unsigned int urun    : 1;
-  unsigned int orun    : 1;
-  unsigned int md_rec  : 1;
-  unsigned int md_sent : 1;
-  unsigned int r958err : 1;
-  unsigned int dummy1  : 23;
-} reg_sser_r_masked_intr;
-#define REG_RD_ADDR_sser_r_masked_intr 40
-
-
-/* Constants */
-enum {
-  regk_sser_both                           = 0x00000002,
-  regk_sser_bulk                           = 0x00000001,
-  regk_sser_clk100                         = 0x00000000,
-  regk_sser_clk_in                         = 0x00000000,
-  regk_sser_const0                         = 0x00000003,
-  regk_sser_dout                           = 0x00000002,
-  regk_sser_edge                           = 0x00000000,
-  regk_sser_ext                            = 0x00000001,
-  regk_sser_ext_clk                        = 0x00000001,
-  regk_sser_f100                           = 0x00000000,
-  regk_sser_f29_493                        = 0x00000004,
-  regk_sser_f32                            = 0x00000005,
-  regk_sser_f32_768                        = 0x00000006,
-  regk_sser_frm                            = 0x00000003,
-  regk_sser_gio0                           = 0x00000000,
-  regk_sser_gio1                           = 0x00000001,
-  regk_sser_hispeed                        = 0x00000001,
-  regk_sser_hold                           = 0x00000002,
-  regk_sser_in                             = 0x00000000,
-  regk_sser_inf                            = 0x00000003,
-  regk_sser_intern                         = 0x00000000,
-  regk_sser_intern_clk                     = 0x00000001,
-  regk_sser_intern_tb                      = 0x00000000,
-  regk_sser_iso                            = 0x00000000,
-  regk_sser_level                          = 0x00000001,
-  regk_sser_lospeed                        = 0x00000000,
-  regk_sser_lsbfirst                       = 0x00000000,
-  regk_sser_msbfirst                       = 0x00000001,
-  regk_sser_neg                            = 0x00000001,
-  regk_sser_neg_lo                         = 0x00000000,
-  regk_sser_no                             = 0x00000000,
-  regk_sser_no_clk                         = 0x00000007,
-  regk_sser_nojitter                       = 0x00000002,
-  regk_sser_out                            = 0x00000001,
-  regk_sser_pos                            = 0x00000000,
-  regk_sser_pos_hi                         = 0x00000001,
-  regk_sser_rec                            = 0x00000000,
-  regk_sser_rw_cfg_default                 = 0x00000000,
-  regk_sser_rw_extra_default               = 0x00000000,
-  regk_sser_rw_frm_cfg_default             = 0x00000000,
-  regk_sser_rw_intr_mask_default           = 0x00000000,
-  regk_sser_rw_rec_cfg_default             = 0x00000000,
-  regk_sser_rw_tr_cfg_default              = 0x01800000,
-  regk_sser_rw_tr_data_default             = 0x00000000,
-  regk_sser_thr16                          = 0x00000001,
-  regk_sser_thr32                          = 0x00000002,
-  regk_sser_thr8                           = 0x00000000,
-  regk_sser_tr                             = 0x00000001,
-  regk_sser_ts_out                         = 0x00000003,
-  regk_sser_tx_bulk                        = 0x00000002,
-  regk_sser_wiresave                       = 0x00000002,
-  regk_sser_yes                            = 0x00000001
-};
-#endif /* __sser_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/strcop.h b/include/asm-cris/arch-v32/hwregs/strcop.h
deleted file mode 100644
index 35131ba466f3..000000000000
--- a/include/asm-cris/arch-v32/hwregs/strcop.h
+++ /dev/null
@@ -1,57 +0,0 @@
-// $Id: strcop.h,v 1.3 2003/10/22 13:27:12 henriken Exp $
-
-// Streamcop meta-data configuration structs
-
-struct strcop_meta_out {
-	unsigned char  csumsel  : 3;
-	unsigned char  ciphsel  : 3;
-	unsigned char  ciphconf : 2;
-	unsigned char  hashsel  : 3;
-	unsigned char  hashconf : 1;
-	unsigned char  hashmode : 1;
-	unsigned char  decrypt  : 1;
-	unsigned char  dlkey    : 1;
-	unsigned char  cbcmode  : 1;
-};
-
-struct strcop_meta_in {
-	unsigned char  dmasel     : 3;
-	unsigned char  sync       : 1;
-	unsigned char  res1       : 5;
-	unsigned char  res2;
-};
-
-// Source definitions
-
-enum {
-	src_none = 0,
-	src_dma  = 1,
-	src_des  = 2,
-	src_sha1 = 3,
-	src_csum = 4,
-	src_aes  = 5,
-	src_md5  = 6,
-	src_res  = 7
-};
-
-// Cipher definitions
-
-enum {
-	ciph_des = 0,
-	ciph_3des = 1,
-	ciph_aes = 2
-};
-
-// Hash definitions
-
-enum {
-	hash_sha1 = 0,
-	hash_md5 = 1
-};
-
-enum {
-	hash_noiv = 0,
-	hash_iv = 1
-};
-
-
diff --git a/include/asm-cris/arch-v32/hwregs/strcop_defs.h b/include/asm-cris/arch-v32/hwregs/strcop_defs.h
deleted file mode 100644
index bd145a49b2c4..000000000000
--- a/include/asm-cris/arch-v32/hwregs/strcop_defs.h
+++ /dev/null
@@ -1,109 +0,0 @@
-#ifndef __strcop_defs_h
-#define __strcop_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/strcop/rtl/strcop_regs.r
- *     id:           strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp
- *     last modfied: Mon Apr 11 16:09:38 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile strcop_defs.h ../../inst/strcop/rtl/strcop_regs.r
- *      id: $Id: strcop_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope strcop */
-
-/* Register rw_cfg, scope strcop, type rw */
-typedef struct {
-  unsigned int td3         : 1;
-  unsigned int td2         : 1;
-  unsigned int td1         : 1;
-  unsigned int ipend       : 1;
-  unsigned int ignore_sync : 1;
-  unsigned int en          : 1;
-  unsigned int dummy1      : 26;
-} reg_strcop_rw_cfg;
-#define REG_RD_ADDR_strcop_rw_cfg 0
-#define REG_WR_ADDR_strcop_rw_cfg 0
-
-
-/* Constants */
-enum {
-  regk_strcop_big                          = 0x00000001,
-  regk_strcop_d                            = 0x00000001,
-  regk_strcop_e                            = 0x00000000,
-  regk_strcop_little                       = 0x00000000,
-  regk_strcop_rw_cfg_default               = 0x00000002
-};
-#endif /* __strcop_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/hwregs/strmux_defs.h
deleted file mode 100644
index 67474855c499..000000000000
--- a/include/asm-cris/arch-v32/hwregs/strmux_defs.h
+++ /dev/null
@@ -1,127 +0,0 @@
-#ifndef __strmux_defs_h
-#define __strmux_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/strmux/rtl/guinness/strmux_regs.r
- *     id:           strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp
- *     last modfied: Mon Apr 11 16:09:43 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r
- *      id: $Id: strmux_defs.h,v 1.5 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope strmux */
-
-/* Register rw_cfg, scope strmux, type rw */
-typedef struct {
-  unsigned int dma0 : 3;
-  unsigned int dma1 : 3;
-  unsigned int dma2 : 3;
-  unsigned int dma3 : 3;
-  unsigned int dma4 : 3;
-  unsigned int dma5 : 3;
-  unsigned int dma6 : 3;
-  unsigned int dma7 : 3;
-  unsigned int dma8 : 3;
-  unsigned int dma9 : 3;
-  unsigned int dummy1 : 2;
-} reg_strmux_rw_cfg;
-#define REG_RD_ADDR_strmux_rw_cfg 0
-#define REG_WR_ADDR_strmux_rw_cfg 0
-
-
-/* Constants */
-enum {
-  regk_strmux_ata                          = 0x00000003,
-  regk_strmux_eth0                         = 0x00000001,
-  regk_strmux_eth1                         = 0x00000004,
-  regk_strmux_ext0                         = 0x00000001,
-  regk_strmux_ext1                         = 0x00000001,
-  regk_strmux_ext2                         = 0x00000001,
-  regk_strmux_ext3                         = 0x00000001,
-  regk_strmux_iop0                         = 0x00000002,
-  regk_strmux_iop1                         = 0x00000001,
-  regk_strmux_off                          = 0x00000000,
-  regk_strmux_p21                          = 0x00000004,
-  regk_strmux_rw_cfg_default               = 0x00000000,
-  regk_strmux_ser0                         = 0x00000002,
-  regk_strmux_ser1                         = 0x00000002,
-  regk_strmux_ser2                         = 0x00000004,
-  regk_strmux_ser3                         = 0x00000003,
-  regk_strmux_sser0                        = 0x00000003,
-  regk_strmux_sser1                        = 0x00000003,
-  regk_strmux_strcop                       = 0x00000002
-};
-#endif /* __strmux_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/supp_reg.h b/include/asm-cris/arch-v32/hwregs/supp_reg.h
deleted file mode 100644
index ffe49625ae36..000000000000
--- a/include/asm-cris/arch-v32/hwregs/supp_reg.h
+++ /dev/null
@@ -1,78 +0,0 @@
-#ifndef __SUPP_REG_H__
-#define __SUPP_REG_H__
-
-/* Macros for reading and writing support/special registers. */
-
-#ifndef STRINGIFYFY
-#define STRINGIFYFY(i) #i
-#endif
-
-#ifndef STRINGIFY
-#define STRINGIFY(i) STRINGIFYFY(i)
-#endif
-
-#define SPEC_REG_BZ     "BZ"
-#define SPEC_REG_VR     "VR"
-#define SPEC_REG_PID    "PID"
-#define SPEC_REG_SRS    "SRS"
-#define SPEC_REG_WZ     "WZ"
-#define SPEC_REG_EXS    "EXS"
-#define SPEC_REG_EDA    "EDA"
-#define SPEC_REG_MOF    "MOF"
-#define SPEC_REG_DZ     "DZ"
-#define SPEC_REG_EBP    "EBP"
-#define SPEC_REG_ERP    "ERP"
-#define SPEC_REG_SRP    "SRP"
-#define SPEC_REG_NRP    "NRP"
-#define SPEC_REG_CCS    "CCS"
-#define SPEC_REG_USP    "USP"
-#define SPEC_REG_SPC    "SPC"
-
-#define RW_MM_CFG       0
-#define RW_MM_KBASE_LO  1
-#define RW_MM_KBASE_HI  2
-#define RW_MM_CAUSE     3
-#define RW_MM_TLB_SEL   4
-#define RW_MM_TLB_LO    5
-#define RW_MM_TLB_HI    6
-#define RW_MM_TLB_PGD   7
-
-#define BANK_GC		0
-#define BANK_IM		1
-#define BANK_DM		2
-#define BANK_BP		3
-
-#define RW_GC_CFG       0
-#define RW_GC_CCS       1
-#define RW_GC_SRS       2
-#define RW_GC_NRP       3
-#define RW_GC_EXS       4
-#define RW_GC_R0        8
-#define RW_GC_R1        9
-
-#define SPEC_REG_WR(r,v) \
-__asm__ __volatile__ ("move %0, $" r : : "r" (v));
-
-#define SPEC_REG_RD(r,v) \
-__asm__ __volatile__ ("move $" r ",%0" : "=r" (v));
-
-#define NOP() \
-	__asm__ __volatile__ ("nop");
-
-#define SUPP_BANK_SEL(b) 		\
-	SPEC_REG_WR(SPEC_REG_SRS,b);	\
-	NOP();				\
-	NOP();				\
-	NOP();
-
-#define SUPP_REG_WR(r,v) \
-__asm__ __volatile__ ("move %0, $S" STRINGIFYFY(r) "\n\t"	\
-		      "nop\n\t"					\
-		      "nop\n\t"					\
-		      "nop\n\t"					\
-		      : : "r" (v));
-
-#define SUPP_REG_RD(r,v) \
-__asm__ __volatile__ ("move $S" STRINGIFYFY(r) ",%0" : "=r" (v));
-
-#endif /* __SUPP_REG_H__ */
diff --git a/include/asm-cris/arch-v32/intmem.h b/include/asm-cris/arch-v32/intmem.h
deleted file mode 100644
index c0ada33bf90f..000000000000
--- a/include/asm-cris/arch-v32/intmem.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef _ASM_CRIS_INTMEM_H
-#define _ASM_CRIS_INTMEM_H
-
-void* crisv32_intmem_alloc(unsigned size, unsigned align);
-void crisv32_intmem_free(void* addr);
-void* crisv32_intmem_phys_to_virt(unsigned long addr);
-unsigned long crisv32_intmem_virt_to_phys(void *addr);
-
-#endif /* _ASM_CRIS_ARCH_INTMEM_H */
diff --git a/include/asm-cris/arch-v32/io.h b/include/asm-cris/arch-v32/io.h
deleted file mode 100644
index 6b38912f29ba..000000000000
--- a/include/asm-cris/arch-v32/io.h
+++ /dev/null
@@ -1,136 +0,0 @@
-#ifndef _ASM_ARCH_CRIS_IO_H
-#define _ASM_ARCH_CRIS_IO_H
-
-#include <linux/spinlock.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/gio_defs.h>
-
-enum crisv32_io_dir
-{
-  crisv32_io_dir_in = 0,
-  crisv32_io_dir_out = 1
-};
-
-struct crisv32_ioport
-{
-  volatile unsigned long *oe;
-  volatile unsigned long *data;
-  volatile unsigned long *data_in;
-  unsigned int pin_count;
-  spinlock_t lock;
-};
-
-struct crisv32_iopin
-{
-  struct crisv32_ioport* port;
-  int bit;
-};
-
-extern struct crisv32_ioport crisv32_ioports[];
-
-extern struct crisv32_iopin crisv32_led1_green;
-extern struct crisv32_iopin crisv32_led1_red;
-extern struct crisv32_iopin crisv32_led2_green;
-extern struct crisv32_iopin crisv32_led2_red;
-extern struct crisv32_iopin crisv32_led3_green;
-extern struct crisv32_iopin crisv32_led3_red;
-
-extern struct crisv32_iopin crisv32_led_net0_green;
-extern struct crisv32_iopin crisv32_led_net0_red;
-extern struct crisv32_iopin crisv32_led_net1_green;
-extern struct crisv32_iopin crisv32_led_net1_red;
-
-static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val)
-{
-	long flags;
-	spin_lock_irqsave(&iopin->port->lock, flags);
-
-	if (val)
-		*iopin->port->data |= iopin->bit;
-	else
-		*iopin->port->data &= ~iopin->bit;
-
-	spin_unlock_irqrestore(&iopin->port->lock, flags);
-}
-
-static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin,
-			       enum crisv32_io_dir dir)
-{
-	long flags;
-	spin_lock_irqsave(&iopin->port->lock, flags);
-
-	if (dir == crisv32_io_dir_in)
-		*iopin->port->oe &= ~iopin->bit;
-	else
-		*iopin->port->oe |= iopin->bit;
-
-	spin_unlock_irqrestore(&iopin->port->lock, flags);
-}
-
-static inline int crisv32_io_rd(struct crisv32_iopin* iopin)
-{
-	return ((*iopin->port->data_in & iopin->bit) ? 1 : 0);
-}
-
-int crisv32_io_get(struct crisv32_iopin* iopin,
-                   unsigned int port, unsigned int pin);
-int crisv32_io_get_name(struct crisv32_iopin* iopin,
-			const char *name);
-
-#define CRIS_LED_OFF    0x00
-#define CRIS_LED_GREEN  0x01
-#define CRIS_LED_RED    0x02
-#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED)
-
-#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
-#define CRIS_LED_NETWORK_GRP0_SET(x)                          \
-	do {                                             \
-		CRIS_LED_NETWORK_GRP0_SET_G((x) & CRIS_LED_GREEN); \
-		CRIS_LED_NETWORK_GRP0_SET_R((x) & CRIS_LED_RED);   \
-	} while (0)
-#else
-#define CRIS_LED_NETWORK_GRP0_SET(x) while (0) {}
-#endif
-
-#define CRIS_LED_NETWORK_GRP0_SET_G(x) \
-	crisv32_io_set(&crisv32_led_net0_green, !(x));
-
-#define CRIS_LED_NETWORK_GRP0_SET_R(x) \
-	crisv32_io_set(&crisv32_led_net0_red, !(x));
-
-#if defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)
-#define CRIS_LED_NETWORK_GRP1_SET(x)                          \
-	do {                                             \
-		CRIS_LED_NETWORK_GRP1_SET_G((x) & CRIS_LED_GREEN); \
-		CRIS_LED_NETWORK_GRP1_SET_R((x) & CRIS_LED_RED);   \
-	} while (0)
-#else
-#define CRIS_LED_NETWORK_GRP1_SET(x) while (0) {}
-#endif
-
-#define CRIS_LED_NETWORK_GRP1_SET_G(x) \
-	crisv32_io_set(&crisv32_led_net1_green, !(x));
-
-#define CRIS_LED_NETWORK_GRP1_SET_R(x) \
-	crisv32_io_set(&crisv32_led_net1_red, !(x));
-
-#define CRIS_LED_ACTIVE_SET(x)                           \
-	do {                                        \
-		CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN);  \
-		CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED);    \
-	} while (0)
-
-#define CRIS_LED_ACTIVE_SET_G(x) \
-	crisv32_io_set(&crisv32_led2_green, !(x));
-#define CRIS_LED_ACTIVE_SET_R(x) \
-	crisv32_io_set(&crisv32_led2_red, !(x));
-#define CRIS_LED_DISK_WRITE(x) \
-         do{\
-		crisv32_io_set(&crisv32_led3_green, !(x)); \
-		crisv32_io_set(&crisv32_led3_red, !(x));   \
-        }while(0)
-#define CRIS_LED_DISK_READ(x) \
-	crisv32_io_set(&crisv32_led3_green, !(x));
-
-#endif
diff --git a/include/asm-cris/arch-v32/irq.h b/include/asm-cris/arch-v32/irq.h
deleted file mode 100644
index 9e4c9fbdfddf..000000000000
--- a/include/asm-cris/arch-v32/irq.h
+++ /dev/null
@@ -1,124 +0,0 @@
-#ifndef _ASM_ARCH_IRQ_H
-#define _ASM_ARCH_IRQ_H
-
-#include <hwregs/intr_vect.h>
-
-/* Number of non-cpu interrupts. */
-#define NR_IRQS NBR_INTR_VECT /* Exceptions + IRQs */
-#define FIRST_IRQ 0x31 /* Exception number for first IRQ */
-#define NR_REAL_IRQS (NBR_INTR_VECT - FIRST_IRQ) /* IRQs */
-#if NR_REAL_IRQS > 32
-#define MACH_IRQS 64
-#else
-#define MACH_IRQS 32
-#endif
-
-#ifndef __ASSEMBLY__
-/* Global IRQ vector. */
-typedef void (*irqvectptr)(void);
-
-struct etrax_interrupt_vector {
-	irqvectptr v[256];
-};
-
-extern struct etrax_interrupt_vector *etrax_irv;	/* head.S */
-
-void mask_irq(int irq);
-void unmask_irq(int irq);
-
-void set_exception_vector(int n, irqvectptr addr);
-
-/* Save registers so that they match pt_regs. */
-#define SAVE_ALL \
-	"subq 12,$sp\n\t"	\
-	"move $erp,[$sp]\n\t"	\
-	"subq 4,$sp\n\t"	\
-	"move $srp,[$sp]\n\t"	\
-	"subq 4,$sp\n\t"	\
-	"move $ccs,[$sp]\n\t"	\
-	"subq 4,$sp\n\t"	\
-	"move $spc,[$sp]\n\t"	\
-	"subq 4,$sp\n\t"	\
-	"move $mof,[$sp]\n\t"	\
-	"subq 4,$sp\n\t"	\
-	"move $srs,[$sp]\n\t"	\
-	"subq 4,$sp\n\t"	\
-	"move.d $acr,[$sp]\n\t"	\
-	"subq 14*4,$sp\n\t"	\
-	"movem $r13,[$sp]\n\t"	\
-	"subq 4,$sp\n\t"	\
-	"move.d $r10,[$sp]\n"
-
-#define STR2(x) #x
-#define STR(x) STR2(x)
-
-#define IRQ_NAME2(nr) nr##_interrupt(void)
-#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
-
-/*
- * The reason for setting the S-bit when debugging the kernel is that we want
- * hardware breakpoints to remain active while we are in an exception handler.
- * Note that we cannot simply copy S1, since we may come here from user-space,
- * or any context where the S-bit wasn't set.
- */
-#ifdef CONFIG_ETRAX_KGDB
-#define KGDB_FIXUP \
-	"move $ccs, $r10\n\t"		\
-	"or.d (1<<9), $r10\n\t"		\
-	"move $r10, $ccs\n\t"
-#else
-#define KGDB_FIXUP ""
-#endif
-
-/*
- * Make sure the causing IRQ is blocked, then call do_IRQ. After that, unblock
- * and jump to ret_from_intr which is found in entry.S.
- *
- * The reason for blocking the IRQ is to allow an sti() before the handler,
- * which will acknowledge the interrupt, is run. The actual blocking is made
- * by crisv32_do_IRQ.
- */
-#define BUILD_IRQ(nr)		        \
-void IRQ_NAME(nr);			\
-__asm__ (				\
-	".text\n\t"			\
-	"IRQ" #nr "_interrupt:\n\t" 	\
-	SAVE_ALL			\
-	KGDB_FIXUP                      \
-	"move.d "#nr",$r10\n\t"		\
-	"move.d $sp, $r12\n\t"          \
-	"jsr crisv32_do_IRQ\n\t"       	\
-	"moveq 1, $r11\n\t"		\
-	"jump ret_from_intr\n\t"	\
-	"nop\n\t");
-/*
- * This is subtle. The timer interrupt is crucial and it should not be disabled
- * for too long. However, if it had been a normal interrupt as per BUILD_IRQ, it
- * would have been BLOCK'ed, and then softirq's are run before we return here to
- * UNBLOCK. If the softirq's take too much time to run, the timer irq won't run
- * and the watchdog will kill us.
- *
- * Furthermore, if a lot of other irq's occur before we return here, the
- * multiple_irq handler is run and it prioritizes the timer interrupt. However
- * if we had BLOCK'edit here, we would not get the multiple_irq at all.
- *
- * The non-blocking here is based on the knowledge that the timer interrupt is
- * registred as a fast interrupt (IRQF_DISABLED) so that we _know_ there will not
- * be an sti() before the timer irq handler is run to acknowledge the interrupt.
- */
-#define BUILD_TIMER_IRQ(nr, mask) 	\
-void IRQ_NAME(nr);			\
-__asm__ (				\
-	".text\n\t"			\
-	"IRQ" #nr "_interrupt:\n\t"	\
-	SAVE_ALL			\
-        KGDB_FIXUP                      \
-	"move.d "#nr",$r10\n\t"		\
-	"move.d $sp,$r12\n\t"		\
-	"jsr crisv32_do_IRQ\n\t"	\
-	"moveq 0,$r11\n\t"		\
-	"jump ret_from_intr\n\t"	\
-	"nop\n\t");
-
-#endif /* __ASSEMBLY__ */
-#endif /* _ASM_ARCH_IRQ_H */
diff --git a/include/asm-cris/arch-v32/mach-a3/arbiter.h b/include/asm-cris/arch-v32/mach-a3/arbiter.h
deleted file mode 100644
index 65e9d6ff0520..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/arbiter.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_ARBITER_H
-#define _ASM_CRIS_ARCH_ARBITER_H
-
-#define EXT_REGION 0
-#define INT_REGION 1
-
-typedef void (watch_callback)(void);
-
-enum {
-	arbiter_all_dmas = 0x7fe,
-	arbiter_cpu = 0x1800,
-	arbiter_all_clients = 0x7fff
-};
-
-enum {
-	arbiter_bar_all_clients = 0x1ff
-};
-
-enum {
-	arbiter_all_read = 0x55,
-	arbiter_all_write = 0xaa,
-	arbiter_all_accesses = 0xff
-};
-
-#define MARB_CLIENTS(foo_cli, bar_cli) (((bar_cli) << 16) | (foo_cli))
-
-int crisv32_arbiter_allocate_bandwidth(int client, int region,
-		unsigned long bandwidth);
-int crisv32_arbiter_watch(unsigned long start, unsigned long size,
-		unsigned long clients, unsigned long accesses,
-		watch_callback * cb);
-int crisv32_arbiter_unwatch(int id);
-
-#endif
diff --git a/include/asm-cris/arch-v32/mach-a3/dma.h b/include/asm-cris/arch-v32/mach-a3/dma.h
deleted file mode 100644
index 9e8eb13b601d..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/dma.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef _ASM_ARCH_CRIS_DMA_H
-#define _ASM_ARCH_CRIS_DMA_H
-
-/* Defines for using and allocating dma channels. */
-
-#define MAX_DMA_CHANNELS	12 /* 8 and 10 not used. */
-
-enum dma_owner {
-	dma_eth,
-	dma_ser0,
-	dma_ser1,
-	dma_ser2,
-	dma_ser3,
-	dma_ser4,
-	dma_iop,
-	dma_sser,
-	dma_strp,
-	dma_h264,
-	dma_jpeg
-};
-
-int crisv32_request_dma(unsigned int dmanr, const char *device_id,
-	unsigned options, unsigned bandwidth, enum dma_owner owner);
-void crisv32_free_dma(unsigned int dmanr);
-
-/* Masks used by crisv32_request_dma options: */
-#define DMA_VERBOSE_ON_ERROR 1
-#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
-#define DMA_INT_MEM 4
-
-#endif /* _ASM_ARCH_CRIS_DMA_H */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h
deleted file mode 100644
index 02855adf63e8..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h
+++ /dev/null
@@ -1,164 +0,0 @@
-#ifndef __clkgen_defs_asm_h
-#define __clkgen_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           clkgen.r
- *
- *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-	REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-	REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-	REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-	REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-	((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_bootsel, scope clkgen, type r */
-#define reg_clkgen_r_bootsel___boot_mode___lsb 0
-#define reg_clkgen_r_bootsel___boot_mode___width 5
-#define reg_clkgen_r_bootsel___intern_main_clk___lsb 5
-#define reg_clkgen_r_bootsel___intern_main_clk___width 1
-#define reg_clkgen_r_bootsel___intern_main_clk___bit 5
-#define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6
-#define reg_clkgen_r_bootsel___extern_usb2_clk___width 1
-#define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6
-#define reg_clkgen_r_bootsel_offset 0
-
-/* Register rw_clk_ctrl, scope clkgen, type rw */
-#define reg_clkgen_rw_clk_ctrl___pll___lsb 0
-#define reg_clkgen_rw_clk_ctrl___pll___width 1
-#define reg_clkgen_rw_clk_ctrl___pll___bit 0
-#define reg_clkgen_rw_clk_ctrl___cpu___lsb 1
-#define reg_clkgen_rw_clk_ctrl___cpu___width 1
-#define reg_clkgen_rw_clk_ctrl___cpu___bit 1
-#define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2
-#define reg_clkgen_rw_clk_ctrl___iop_usb___width 1
-#define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2
-#define reg_clkgen_rw_clk_ctrl___vin___lsb 3
-#define reg_clkgen_rw_clk_ctrl___vin___width 1
-#define reg_clkgen_rw_clk_ctrl___vin___bit 3
-#define reg_clkgen_rw_clk_ctrl___sclr___lsb 4
-#define reg_clkgen_rw_clk_ctrl___sclr___width 1
-#define reg_clkgen_rw_clk_ctrl___sclr___bit 4
-#define reg_clkgen_rw_clk_ctrl___h264___lsb 5
-#define reg_clkgen_rw_clk_ctrl___h264___width 1
-#define reg_clkgen_rw_clk_ctrl___h264___bit 5
-#define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6
-#define reg_clkgen_rw_clk_ctrl___ddr2___width 1
-#define reg_clkgen_rw_clk_ctrl___ddr2___bit 6
-#define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7
-#define reg_clkgen_rw_clk_ctrl___vout_hist___width 1
-#define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7
-#define reg_clkgen_rw_clk_ctrl___eth___lsb 8
-#define reg_clkgen_rw_clk_ctrl___eth___width 1
-#define reg_clkgen_rw_clk_ctrl___eth___bit 8
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9
-#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10
-#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1
-#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11
-#define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12
-#define reg_clkgen_rw_clk_ctrl___jpeg___width 1
-#define reg_clkgen_rw_clk_ctrl___jpeg___bit 12
-#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13
-#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1
-#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13
-#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14
-#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1
-#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14
-#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15
-#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1
-#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15
-#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16
-#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1
-#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16
-#define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17
-#define reg_clkgen_rw_clk_ctrl___dma9_11___width 1
-#define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17
-#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18
-#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1
-#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18
-#define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19
-#define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1
-#define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19
-#define reg_clkgen_rw_clk_ctrl_offset 4
-
-
-/* Constants */
-#define regk_clkgen_eth1000_rx                    0x0000000c
-#define regk_clkgen_eth1000_tx                    0x0000000e
-#define regk_clkgen_eth100_rx                     0x0000001d
-#define regk_clkgen_eth100_rx_half                0x0000001c
-#define regk_clkgen_eth100_tx                     0x0000001f
-#define regk_clkgen_eth100_tx_half                0x0000001e
-#define regk_clkgen_nand_3_2                      0x00000000
-#define regk_clkgen_nand_3_2_0x30                 0x00000002
-#define regk_clkgen_nand_3_2_0x30_pll             0x00000012
-#define regk_clkgen_nand_3_2_pll                  0x00000010
-#define regk_clkgen_nand_3_3                      0x00000001
-#define regk_clkgen_nand_3_3_0x30                 0x00000003
-#define regk_clkgen_nand_3_3_0x30_pll             0x00000013
-#define regk_clkgen_nand_3_3_pll                  0x00000011
-#define regk_clkgen_nand_4_2                      0x00000004
-#define regk_clkgen_nand_4_2_0x30                 0x00000006
-#define regk_clkgen_nand_4_2_0x30_pll             0x00000016
-#define regk_clkgen_nand_4_2_pll                  0x00000014
-#define regk_clkgen_nand_4_3                      0x00000005
-#define regk_clkgen_nand_4_3_0x30                 0x00000007
-#define regk_clkgen_nand_4_3_0x30_pll             0x00000017
-#define regk_clkgen_nand_4_3_pll                  0x00000015
-#define regk_clkgen_nand_5_2                      0x00000008
-#define regk_clkgen_nand_5_2_0x30                 0x0000000a
-#define regk_clkgen_nand_5_2_0x30_pll             0x0000001a
-#define regk_clkgen_nand_5_2_pll                  0x00000018
-#define regk_clkgen_nand_5_3                      0x00000009
-#define regk_clkgen_nand_5_3_0x30                 0x0000000b
-#define regk_clkgen_nand_5_3_0x30_pll             0x0000001b
-#define regk_clkgen_nand_5_3_pll                  0x00000019
-#define regk_clkgen_no                            0x00000000
-#define regk_clkgen_rw_clk_ctrl_default           0x00000002
-#define regk_clkgen_ser                           0x0000000d
-#define regk_clkgen_ser_pll                       0x0000000f
-#define regk_clkgen_yes                           0x00000001
-#endif /* __clkgen_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h
deleted file mode 100644
index b12be03edacb..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h
+++ /dev/null
@@ -1,266 +0,0 @@
-#ifndef __ddr2_defs_asm_h
-#define __ddr2_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ddr2.r
- *
- *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-	REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-	REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-	REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-	REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-	((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope ddr2, type rw */
-#define reg_ddr2_rw_cfg___col_width___lsb 0
-#define reg_ddr2_rw_cfg___col_width___width 4
-#define reg_ddr2_rw_cfg___nr_banks___lsb 4
-#define reg_ddr2_rw_cfg___nr_banks___width 1
-#define reg_ddr2_rw_cfg___nr_banks___bit 4
-#define reg_ddr2_rw_cfg___bw___lsb 5
-#define reg_ddr2_rw_cfg___bw___width 1
-#define reg_ddr2_rw_cfg___bw___bit 5
-#define reg_ddr2_rw_cfg___nr_ref___lsb 6
-#define reg_ddr2_rw_cfg___nr_ref___width 4
-#define reg_ddr2_rw_cfg___ref_interval___lsb 10
-#define reg_ddr2_rw_cfg___ref_interval___width 11
-#define reg_ddr2_rw_cfg___odt_ctrl___lsb 21
-#define reg_ddr2_rw_cfg___odt_ctrl___width 2
-#define reg_ddr2_rw_cfg___odt_mem___lsb 23
-#define reg_ddr2_rw_cfg___odt_mem___width 1
-#define reg_ddr2_rw_cfg___odt_mem___bit 23
-#define reg_ddr2_rw_cfg___imp_strength___lsb 24
-#define reg_ddr2_rw_cfg___imp_strength___width 1
-#define reg_ddr2_rw_cfg___imp_strength___bit 24
-#define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25
-#define reg_ddr2_rw_cfg___auto_imp_cal___width 1
-#define reg_ddr2_rw_cfg___auto_imp_cal___bit 25
-#define reg_ddr2_rw_cfg___imp_cal_override___lsb 26
-#define reg_ddr2_rw_cfg___imp_cal_override___width 1
-#define reg_ddr2_rw_cfg___imp_cal_override___bit 26
-#define reg_ddr2_rw_cfg___dll_override___lsb 27
-#define reg_ddr2_rw_cfg___dll_override___width 1
-#define reg_ddr2_rw_cfg___dll_override___bit 27
-#define reg_ddr2_rw_cfg_offset 0
-
-/* Register rw_timing, scope ddr2, type rw */
-#define reg_ddr2_rw_timing___wr___lsb 0
-#define reg_ddr2_rw_timing___wr___width 3
-#define reg_ddr2_rw_timing___rcd___lsb 3
-#define reg_ddr2_rw_timing___rcd___width 3
-#define reg_ddr2_rw_timing___rp___lsb 6
-#define reg_ddr2_rw_timing___rp___width 3
-#define reg_ddr2_rw_timing___ras___lsb 9
-#define reg_ddr2_rw_timing___ras___width 4
-#define reg_ddr2_rw_timing___rfc___lsb 13
-#define reg_ddr2_rw_timing___rfc___width 7
-#define reg_ddr2_rw_timing___rc___lsb 20
-#define reg_ddr2_rw_timing___rc___width 5
-#define reg_ddr2_rw_timing___rtp___lsb 25
-#define reg_ddr2_rw_timing___rtp___width 2
-#define reg_ddr2_rw_timing___rtw___lsb 27
-#define reg_ddr2_rw_timing___rtw___width 3
-#define reg_ddr2_rw_timing___wtr___lsb 30
-#define reg_ddr2_rw_timing___wtr___width 2
-#define reg_ddr2_rw_timing_offset 4
-
-/* Register rw_latency, scope ddr2, type rw */
-#define reg_ddr2_rw_latency___cas___lsb 0
-#define reg_ddr2_rw_latency___cas___width 3
-#define reg_ddr2_rw_latency___additive___lsb 3
-#define reg_ddr2_rw_latency___additive___width 3
-#define reg_ddr2_rw_latency_offset 8
-
-/* Register rw_phy_cfg, scope ddr2, type rw */
-#define reg_ddr2_rw_phy_cfg___en___lsb 0
-#define reg_ddr2_rw_phy_cfg___en___width 1
-#define reg_ddr2_rw_phy_cfg___en___bit 0
-#define reg_ddr2_rw_phy_cfg_offset 12
-
-/* Register rw_phy_ctrl, scope ddr2, type rw */
-#define reg_ddr2_rw_phy_ctrl___rst___lsb 0
-#define reg_ddr2_rw_phy_ctrl___rst___width 1
-#define reg_ddr2_rw_phy_ctrl___rst___bit 0
-#define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1
-#define reg_ddr2_rw_phy_ctrl___cal_rst___width 1
-#define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1
-#define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2
-#define reg_ddr2_rw_phy_ctrl___cal_start___width 1
-#define reg_ddr2_rw_phy_ctrl___cal_start___bit 2
-#define reg_ddr2_rw_phy_ctrl_offset 16
-
-/* Register rw_ctrl, scope ddr2, type rw */
-#define reg_ddr2_rw_ctrl___mrs_data___lsb 0
-#define reg_ddr2_rw_ctrl___mrs_data___width 16
-#define reg_ddr2_rw_ctrl___cmd___lsb 16
-#define reg_ddr2_rw_ctrl___cmd___width 8
-#define reg_ddr2_rw_ctrl_offset 20
-
-/* Register rw_pwr_down, scope ddr2, type rw */
-#define reg_ddr2_rw_pwr_down___self_ref___lsb 0
-#define reg_ddr2_rw_pwr_down___self_ref___width 2
-#define reg_ddr2_rw_pwr_down___phy_en___lsb 2
-#define reg_ddr2_rw_pwr_down___phy_en___width 1
-#define reg_ddr2_rw_pwr_down___phy_en___bit 2
-#define reg_ddr2_rw_pwr_down_offset 24
-
-/* Register r_stat, scope ddr2, type r */
-#define reg_ddr2_r_stat___dll_lock___lsb 0
-#define reg_ddr2_r_stat___dll_lock___width 1
-#define reg_ddr2_r_stat___dll_lock___bit 0
-#define reg_ddr2_r_stat___dll_delay_code___lsb 1
-#define reg_ddr2_r_stat___dll_delay_code___width 7
-#define reg_ddr2_r_stat___imp_cal_done___lsb 8
-#define reg_ddr2_r_stat___imp_cal_done___width 1
-#define reg_ddr2_r_stat___imp_cal_done___bit 8
-#define reg_ddr2_r_stat___imp_cal_fault___lsb 9
-#define reg_ddr2_r_stat___imp_cal_fault___width 1
-#define reg_ddr2_r_stat___imp_cal_fault___bit 9
-#define reg_ddr2_r_stat___cal_imp_pu___lsb 10
-#define reg_ddr2_r_stat___cal_imp_pu___width 4
-#define reg_ddr2_r_stat___cal_imp_pd___lsb 14
-#define reg_ddr2_r_stat___cal_imp_pd___width 4
-#define reg_ddr2_r_stat_offset 28
-
-/* Register rw_imp_ctrl, scope ddr2, type rw */
-#define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0
-#define reg_ddr2_rw_imp_ctrl___imp_pu___width 4
-#define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4
-#define reg_ddr2_rw_imp_ctrl___imp_pd___width 4
-#define reg_ddr2_rw_imp_ctrl_offset 32
-
-#define STRIDE_ddr2_rw_dll_ctrl 4
-/* Register rw_dll_ctrl, scope ddr2, type rw */
-#define reg_ddr2_rw_dll_ctrl___mode___lsb 0
-#define reg_ddr2_rw_dll_ctrl___mode___width 1
-#define reg_ddr2_rw_dll_ctrl___mode___bit 0
-#define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1
-#define reg_ddr2_rw_dll_ctrl___clk_delay___width 7
-#define reg_ddr2_rw_dll_ctrl_offset 36
-
-#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
-/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7
-#define reg_ddr2_rw_dqs_dll_ctrl_offset 52
-
-
-/* Constants */
-#define regk_ddr2_al0                             0x00000000
-#define regk_ddr2_al1                             0x00000008
-#define regk_ddr2_al2                             0x00000010
-#define regk_ddr2_al3                             0x00000018
-#define regk_ddr2_al4                             0x00000020
-#define regk_ddr2_auto                            0x00000003
-#define regk_ddr2_bank4                           0x00000000
-#define regk_ddr2_bank8                           0x00000001
-#define regk_ddr2_bl4                             0x00000002
-#define regk_ddr2_bl8                             0x00000003
-#define regk_ddr2_bt_il                           0x00000008
-#define regk_ddr2_bt_seq                          0x00000000
-#define regk_ddr2_bw16                            0x00000001
-#define regk_ddr2_bw32                            0x00000000
-#define regk_ddr2_cas2                            0x00000020
-#define regk_ddr2_cas3                            0x00000030
-#define regk_ddr2_cas4                            0x00000040
-#define regk_ddr2_cas5                            0x00000050
-#define regk_ddr2_deselect                        0x000000c0
-#define regk_ddr2_dic_weak                        0x00000002
-#define regk_ddr2_direct                          0x00000001
-#define regk_ddr2_dis                             0x00000000
-#define regk_ddr2_dll_dis                         0x00000001
-#define regk_ddr2_dll_en                          0x00000000
-#define regk_ddr2_dll_rst                         0x00000100
-#define regk_ddr2_emrs                            0x00000081
-#define regk_ddr2_emrs2                           0x00000082
-#define regk_ddr2_emrs3                           0x00000083
-#define regk_ddr2_full                            0x00000001
-#define regk_ddr2_hi_ref_rate                     0x00000080
-#define regk_ddr2_mrs                             0x00000080
-#define regk_ddr2_no                              0x00000000
-#define regk_ddr2_nop                             0x000000b8
-#define regk_ddr2_ocd_adj                         0x00000200
-#define regk_ddr2_ocd_default                     0x00000380
-#define regk_ddr2_ocd_drive0                      0x00000100
-#define regk_ddr2_ocd_drive1                      0x00000080
-#define regk_ddr2_ocd_exit                        0x00000000
-#define regk_ddr2_odt_dis                         0x00000000
-#define regk_ddr2_offs                            0x00000000
-#define regk_ddr2_pre                             0x00000090
-#define regk_ddr2_pre_all                         0x00000400
-#define regk_ddr2_pwr_down_fast                   0x00000000
-#define regk_ddr2_pwr_down_slow                   0x00001000
-#define regk_ddr2_ref                             0x00000088
-#define regk_ddr2_rtt150                          0x00000040
-#define regk_ddr2_rtt50                           0x00000044
-#define regk_ddr2_rtt75                           0x00000004
-#define regk_ddr2_rw_cfg_default                  0x00186000
-#define regk_ddr2_rw_dll_ctrl_default             0x00000000
-#define regk_ddr2_rw_dll_ctrl_size                0x00000004
-#define regk_ddr2_rw_dqs_dll_ctrl_default         0x00000000
-#define regk_ddr2_rw_dqs_dll_ctrl_size            0x00000004
-#define regk_ddr2_rw_latency_default              0x00000000
-#define regk_ddr2_rw_phy_cfg_default              0x00000000
-#define regk_ddr2_rw_pwr_down_default             0x00000000
-#define regk_ddr2_rw_timing_default               0x00000000
-#define regk_ddr2_s1Gb                            0x0000001a
-#define regk_ddr2_s256Mb                          0x0000000f
-#define regk_ddr2_s2Gb                            0x00000027
-#define regk_ddr2_s4Gb                            0x00000042
-#define regk_ddr2_s512Mb                          0x00000015
-#define regk_ddr2_temp0_85                        0x00000618
-#define regk_ddr2_temp85_95                       0x0000030c
-#define regk_ddr2_term150                         0x00000002
-#define regk_ddr2_term50                          0x00000003
-#define regk_ddr2_term75                          0x00000001
-#define regk_ddr2_test                            0x00000080
-#define regk_ddr2_weak                            0x00000000
-#define regk_ddr2_wr2                             0x00000200
-#define regk_ddr2_wr3                             0x00000400
-#define regk_ddr2_yes                             0x00000001
-#endif /* __ddr2_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h
deleted file mode 100644
index df6714fda179..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h
+++ /dev/null
@@ -1,849 +0,0 @@
-#ifndef __gio_defs_asm_h
-#define __gio_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           gio.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_pa_din, scope gio, type r */
-#define reg_gio_r_pa_din___data___lsb 0
-#define reg_gio_r_pa_din___data___width 32
-#define reg_gio_r_pa_din_offset 0
-
-/* Register rw_pa_dout, scope gio, type rw */
-#define reg_gio_rw_pa_dout___data___lsb 0
-#define reg_gio_rw_pa_dout___data___width 32
-#define reg_gio_rw_pa_dout_offset 4
-
-/* Register rw_pa_oe, scope gio, type rw */
-#define reg_gio_rw_pa_oe___oe___lsb 0
-#define reg_gio_rw_pa_oe___oe___width 32
-#define reg_gio_rw_pa_oe_offset 8
-
-/* Register rw_pa_byte0_dout, scope gio, type rw */
-#define reg_gio_rw_pa_byte0_dout___data___lsb 0
-#define reg_gio_rw_pa_byte0_dout___data___width 8
-#define reg_gio_rw_pa_byte0_dout_offset 12
-
-/* Register rw_pa_byte0_oe, scope gio, type rw */
-#define reg_gio_rw_pa_byte0_oe___oe___lsb 0
-#define reg_gio_rw_pa_byte0_oe___oe___width 8
-#define reg_gio_rw_pa_byte0_oe_offset 16
-
-/* Register rw_pa_byte1_dout, scope gio, type rw */
-#define reg_gio_rw_pa_byte1_dout___data___lsb 0
-#define reg_gio_rw_pa_byte1_dout___data___width 8
-#define reg_gio_rw_pa_byte1_dout_offset 20
-
-/* Register rw_pa_byte1_oe, scope gio, type rw */
-#define reg_gio_rw_pa_byte1_oe___oe___lsb 0
-#define reg_gio_rw_pa_byte1_oe___oe___width 8
-#define reg_gio_rw_pa_byte1_oe_offset 24
-
-/* Register rw_pa_byte2_dout, scope gio, type rw */
-#define reg_gio_rw_pa_byte2_dout___data___lsb 0
-#define reg_gio_rw_pa_byte2_dout___data___width 8
-#define reg_gio_rw_pa_byte2_dout_offset 28
-
-/* Register rw_pa_byte2_oe, scope gio, type rw */
-#define reg_gio_rw_pa_byte2_oe___oe___lsb 0
-#define reg_gio_rw_pa_byte2_oe___oe___width 8
-#define reg_gio_rw_pa_byte2_oe_offset 32
-
-/* Register rw_pa_byte3_dout, scope gio, type rw */
-#define reg_gio_rw_pa_byte3_dout___data___lsb 0
-#define reg_gio_rw_pa_byte3_dout___data___width 8
-#define reg_gio_rw_pa_byte3_dout_offset 36
-
-/* Register rw_pa_byte3_oe, scope gio, type rw */
-#define reg_gio_rw_pa_byte3_oe___oe___lsb 0
-#define reg_gio_rw_pa_byte3_oe___oe___width 8
-#define reg_gio_rw_pa_byte3_oe_offset 40
-
-/* Register r_pb_din, scope gio, type r */
-#define reg_gio_r_pb_din___data___lsb 0
-#define reg_gio_r_pb_din___data___width 32
-#define reg_gio_r_pb_din_offset 44
-
-/* Register rw_pb_dout, scope gio, type rw */
-#define reg_gio_rw_pb_dout___data___lsb 0
-#define reg_gio_rw_pb_dout___data___width 32
-#define reg_gio_rw_pb_dout_offset 48
-
-/* Register rw_pb_oe, scope gio, type rw */
-#define reg_gio_rw_pb_oe___oe___lsb 0
-#define reg_gio_rw_pb_oe___oe___width 32
-#define reg_gio_rw_pb_oe_offset 52
-
-/* Register rw_pb_byte0_dout, scope gio, type rw */
-#define reg_gio_rw_pb_byte0_dout___data___lsb 0
-#define reg_gio_rw_pb_byte0_dout___data___width 8
-#define reg_gio_rw_pb_byte0_dout_offset 56
-
-/* Register rw_pb_byte0_oe, scope gio, type rw */
-#define reg_gio_rw_pb_byte0_oe___oe___lsb 0
-#define reg_gio_rw_pb_byte0_oe___oe___width 8
-#define reg_gio_rw_pb_byte0_oe_offset 60
-
-/* Register rw_pb_byte1_dout, scope gio, type rw */
-#define reg_gio_rw_pb_byte1_dout___data___lsb 0
-#define reg_gio_rw_pb_byte1_dout___data___width 8
-#define reg_gio_rw_pb_byte1_dout_offset 64
-
-/* Register rw_pb_byte1_oe, scope gio, type rw */
-#define reg_gio_rw_pb_byte1_oe___oe___lsb 0
-#define reg_gio_rw_pb_byte1_oe___oe___width 8
-#define reg_gio_rw_pb_byte1_oe_offset 68
-
-/* Register rw_pb_byte2_dout, scope gio, type rw */
-#define reg_gio_rw_pb_byte2_dout___data___lsb 0
-#define reg_gio_rw_pb_byte2_dout___data___width 8
-#define reg_gio_rw_pb_byte2_dout_offset 72
-
-/* Register rw_pb_byte2_oe, scope gio, type rw */
-#define reg_gio_rw_pb_byte2_oe___oe___lsb 0
-#define reg_gio_rw_pb_byte2_oe___oe___width 8
-#define reg_gio_rw_pb_byte2_oe_offset 76
-
-/* Register rw_pb_byte3_dout, scope gio, type rw */
-#define reg_gio_rw_pb_byte3_dout___data___lsb 0
-#define reg_gio_rw_pb_byte3_dout___data___width 8
-#define reg_gio_rw_pb_byte3_dout_offset 80
-
-/* Register rw_pb_byte3_oe, scope gio, type rw */
-#define reg_gio_rw_pb_byte3_oe___oe___lsb 0
-#define reg_gio_rw_pb_byte3_oe___oe___width 8
-#define reg_gio_rw_pb_byte3_oe_offset 84
-
-/* Register r_pc_din, scope gio, type r */
-#define reg_gio_r_pc_din___data___lsb 0
-#define reg_gio_r_pc_din___data___width 16
-#define reg_gio_r_pc_din_offset 88
-
-/* Register rw_pc_dout, scope gio, type rw */
-#define reg_gio_rw_pc_dout___data___lsb 0
-#define reg_gio_rw_pc_dout___data___width 16
-#define reg_gio_rw_pc_dout_offset 92
-
-/* Register rw_pc_oe, scope gio, type rw */
-#define reg_gio_rw_pc_oe___oe___lsb 0
-#define reg_gio_rw_pc_oe___oe___width 16
-#define reg_gio_rw_pc_oe_offset 96
-
-/* Register rw_pc_byte0_dout, scope gio, type rw */
-#define reg_gio_rw_pc_byte0_dout___data___lsb 0
-#define reg_gio_rw_pc_byte0_dout___data___width 8
-#define reg_gio_rw_pc_byte0_dout_offset 100
-
-/* Register rw_pc_byte0_oe, scope gio, type rw */
-#define reg_gio_rw_pc_byte0_oe___oe___lsb 0
-#define reg_gio_rw_pc_byte0_oe___oe___width 8
-#define reg_gio_rw_pc_byte0_oe_offset 104
-
-/* Register rw_pc_byte1_dout, scope gio, type rw */
-#define reg_gio_rw_pc_byte1_dout___data___lsb 0
-#define reg_gio_rw_pc_byte1_dout___data___width 8
-#define reg_gio_rw_pc_byte1_dout_offset 108
-
-/* Register rw_pc_byte1_oe, scope gio, type rw */
-#define reg_gio_rw_pc_byte1_oe___oe___lsb 0
-#define reg_gio_rw_pc_byte1_oe___oe___width 8
-#define reg_gio_rw_pc_byte1_oe_offset 112
-
-/* Register r_pd_din, scope gio, type r */
-#define reg_gio_r_pd_din___data___lsb 0
-#define reg_gio_r_pd_din___data___width 32
-#define reg_gio_r_pd_din_offset 116
-
-/* Register rw_intr_cfg, scope gio, type rw */
-#define reg_gio_rw_intr_cfg___intr0___lsb 0
-#define reg_gio_rw_intr_cfg___intr0___width 3
-#define reg_gio_rw_intr_cfg___intr1___lsb 3
-#define reg_gio_rw_intr_cfg___intr1___width 3
-#define reg_gio_rw_intr_cfg___intr2___lsb 6
-#define reg_gio_rw_intr_cfg___intr2___width 3
-#define reg_gio_rw_intr_cfg___intr3___lsb 9
-#define reg_gio_rw_intr_cfg___intr3___width 3
-#define reg_gio_rw_intr_cfg___intr4___lsb 12
-#define reg_gio_rw_intr_cfg___intr4___width 3
-#define reg_gio_rw_intr_cfg___intr5___lsb 15
-#define reg_gio_rw_intr_cfg___intr5___width 3
-#define reg_gio_rw_intr_cfg___intr6___lsb 18
-#define reg_gio_rw_intr_cfg___intr6___width 3
-#define reg_gio_rw_intr_cfg___intr7___lsb 21
-#define reg_gio_rw_intr_cfg___intr7___width 3
-#define reg_gio_rw_intr_cfg_offset 120
-
-/* Register rw_intr_pins, scope gio, type rw */
-#define reg_gio_rw_intr_pins___intr0___lsb 0
-#define reg_gio_rw_intr_pins___intr0___width 4
-#define reg_gio_rw_intr_pins___intr1___lsb 4
-#define reg_gio_rw_intr_pins___intr1___width 4
-#define reg_gio_rw_intr_pins___intr2___lsb 8
-#define reg_gio_rw_intr_pins___intr2___width 4
-#define reg_gio_rw_intr_pins___intr3___lsb 12
-#define reg_gio_rw_intr_pins___intr3___width 4
-#define reg_gio_rw_intr_pins___intr4___lsb 16
-#define reg_gio_rw_intr_pins___intr4___width 4
-#define reg_gio_rw_intr_pins___intr5___lsb 20
-#define reg_gio_rw_intr_pins___intr5___width 4
-#define reg_gio_rw_intr_pins___intr6___lsb 24
-#define reg_gio_rw_intr_pins___intr6___width 4
-#define reg_gio_rw_intr_pins___intr7___lsb 28
-#define reg_gio_rw_intr_pins___intr7___width 4
-#define reg_gio_rw_intr_pins_offset 124
-
-/* Register rw_intr_mask, scope gio, type rw */
-#define reg_gio_rw_intr_mask___intr0___lsb 0
-#define reg_gio_rw_intr_mask___intr0___width 1
-#define reg_gio_rw_intr_mask___intr0___bit 0
-#define reg_gio_rw_intr_mask___intr1___lsb 1
-#define reg_gio_rw_intr_mask___intr1___width 1
-#define reg_gio_rw_intr_mask___intr1___bit 1
-#define reg_gio_rw_intr_mask___intr2___lsb 2
-#define reg_gio_rw_intr_mask___intr2___width 1
-#define reg_gio_rw_intr_mask___intr2___bit 2
-#define reg_gio_rw_intr_mask___intr3___lsb 3
-#define reg_gio_rw_intr_mask___intr3___width 1
-#define reg_gio_rw_intr_mask___intr3___bit 3
-#define reg_gio_rw_intr_mask___intr4___lsb 4
-#define reg_gio_rw_intr_mask___intr4___width 1
-#define reg_gio_rw_intr_mask___intr4___bit 4
-#define reg_gio_rw_intr_mask___intr5___lsb 5
-#define reg_gio_rw_intr_mask___intr5___width 1
-#define reg_gio_rw_intr_mask___intr5___bit 5
-#define reg_gio_rw_intr_mask___intr6___lsb 6
-#define reg_gio_rw_intr_mask___intr6___width 1
-#define reg_gio_rw_intr_mask___intr6___bit 6
-#define reg_gio_rw_intr_mask___intr7___lsb 7
-#define reg_gio_rw_intr_mask___intr7___width 1
-#define reg_gio_rw_intr_mask___intr7___bit 7
-#define reg_gio_rw_intr_mask___i2c0_done___lsb 8
-#define reg_gio_rw_intr_mask___i2c0_done___width 1
-#define reg_gio_rw_intr_mask___i2c0_done___bit 8
-#define reg_gio_rw_intr_mask___i2c1_done___lsb 9
-#define reg_gio_rw_intr_mask___i2c1_done___width 1
-#define reg_gio_rw_intr_mask___i2c1_done___bit 9
-#define reg_gio_rw_intr_mask_offset 128
-
-/* Register rw_ack_intr, scope gio, type rw */
-#define reg_gio_rw_ack_intr___intr0___lsb 0
-#define reg_gio_rw_ack_intr___intr0___width 1
-#define reg_gio_rw_ack_intr___intr0___bit 0
-#define reg_gio_rw_ack_intr___intr1___lsb 1
-#define reg_gio_rw_ack_intr___intr1___width 1
-#define reg_gio_rw_ack_intr___intr1___bit 1
-#define reg_gio_rw_ack_intr___intr2___lsb 2
-#define reg_gio_rw_ack_intr___intr2___width 1
-#define reg_gio_rw_ack_intr___intr2___bit 2
-#define reg_gio_rw_ack_intr___intr3___lsb 3
-#define reg_gio_rw_ack_intr___intr3___width 1
-#define reg_gio_rw_ack_intr___intr3___bit 3
-#define reg_gio_rw_ack_intr___intr4___lsb 4
-#define reg_gio_rw_ack_intr___intr4___width 1
-#define reg_gio_rw_ack_intr___intr4___bit 4
-#define reg_gio_rw_ack_intr___intr5___lsb 5
-#define reg_gio_rw_ack_intr___intr5___width 1
-#define reg_gio_rw_ack_intr___intr5___bit 5
-#define reg_gio_rw_ack_intr___intr6___lsb 6
-#define reg_gio_rw_ack_intr___intr6___width 1
-#define reg_gio_rw_ack_intr___intr6___bit 6
-#define reg_gio_rw_ack_intr___intr7___lsb 7
-#define reg_gio_rw_ack_intr___intr7___width 1
-#define reg_gio_rw_ack_intr___intr7___bit 7
-#define reg_gio_rw_ack_intr___i2c0_done___lsb 8
-#define reg_gio_rw_ack_intr___i2c0_done___width 1
-#define reg_gio_rw_ack_intr___i2c0_done___bit 8
-#define reg_gio_rw_ack_intr___i2c1_done___lsb 9
-#define reg_gio_rw_ack_intr___i2c1_done___width 1
-#define reg_gio_rw_ack_intr___i2c1_done___bit 9
-#define reg_gio_rw_ack_intr_offset 132
-
-/* Register r_intr, scope gio, type r */
-#define reg_gio_r_intr___intr0___lsb 0
-#define reg_gio_r_intr___intr0___width 1
-#define reg_gio_r_intr___intr0___bit 0
-#define reg_gio_r_intr___intr1___lsb 1
-#define reg_gio_r_intr___intr1___width 1
-#define reg_gio_r_intr___intr1___bit 1
-#define reg_gio_r_intr___intr2___lsb 2
-#define reg_gio_r_intr___intr2___width 1
-#define reg_gio_r_intr___intr2___bit 2
-#define reg_gio_r_intr___intr3___lsb 3
-#define reg_gio_r_intr___intr3___width 1
-#define reg_gio_r_intr___intr3___bit 3
-#define reg_gio_r_intr___intr4___lsb 4
-#define reg_gio_r_intr___intr4___width 1
-#define reg_gio_r_intr___intr4___bit 4
-#define reg_gio_r_intr___intr5___lsb 5
-#define reg_gio_r_intr___intr5___width 1
-#define reg_gio_r_intr___intr5___bit 5
-#define reg_gio_r_intr___intr6___lsb 6
-#define reg_gio_r_intr___intr6___width 1
-#define reg_gio_r_intr___intr6___bit 6
-#define reg_gio_r_intr___intr7___lsb 7
-#define reg_gio_r_intr___intr7___width 1
-#define reg_gio_r_intr___intr7___bit 7
-#define reg_gio_r_intr___i2c0_done___lsb 8
-#define reg_gio_r_intr___i2c0_done___width 1
-#define reg_gio_r_intr___i2c0_done___bit 8
-#define reg_gio_r_intr___i2c1_done___lsb 9
-#define reg_gio_r_intr___i2c1_done___width 1
-#define reg_gio_r_intr___i2c1_done___bit 9
-#define reg_gio_r_intr_offset 136
-
-/* Register r_masked_intr, scope gio, type r */
-#define reg_gio_r_masked_intr___intr0___lsb 0
-#define reg_gio_r_masked_intr___intr0___width 1
-#define reg_gio_r_masked_intr___intr0___bit 0
-#define reg_gio_r_masked_intr___intr1___lsb 1
-#define reg_gio_r_masked_intr___intr1___width 1
-#define reg_gio_r_masked_intr___intr1___bit 1
-#define reg_gio_r_masked_intr___intr2___lsb 2
-#define reg_gio_r_masked_intr___intr2___width 1
-#define reg_gio_r_masked_intr___intr2___bit 2
-#define reg_gio_r_masked_intr___intr3___lsb 3
-#define reg_gio_r_masked_intr___intr3___width 1
-#define reg_gio_r_masked_intr___intr3___bit 3
-#define reg_gio_r_masked_intr___intr4___lsb 4
-#define reg_gio_r_masked_intr___intr4___width 1
-#define reg_gio_r_masked_intr___intr4___bit 4
-#define reg_gio_r_masked_intr___intr5___lsb 5
-#define reg_gio_r_masked_intr___intr5___width 1
-#define reg_gio_r_masked_intr___intr5___bit 5
-#define reg_gio_r_masked_intr___intr6___lsb 6
-#define reg_gio_r_masked_intr___intr6___width 1
-#define reg_gio_r_masked_intr___intr6___bit 6
-#define reg_gio_r_masked_intr___intr7___lsb 7
-#define reg_gio_r_masked_intr___intr7___width 1
-#define reg_gio_r_masked_intr___intr7___bit 7
-#define reg_gio_r_masked_intr___i2c0_done___lsb 8
-#define reg_gio_r_masked_intr___i2c0_done___width 1
-#define reg_gio_r_masked_intr___i2c0_done___bit 8
-#define reg_gio_r_masked_intr___i2c1_done___lsb 9
-#define reg_gio_r_masked_intr___i2c1_done___width 1
-#define reg_gio_r_masked_intr___i2c1_done___bit 9
-#define reg_gio_r_masked_intr_offset 140
-
-/* Register rw_i2c0_start, scope gio, type rw */
-#define reg_gio_rw_i2c0_start___run___lsb 0
-#define reg_gio_rw_i2c0_start___run___width 1
-#define reg_gio_rw_i2c0_start___run___bit 0
-#define reg_gio_rw_i2c0_start_offset 144
-
-/* Register rw_i2c0_cfg, scope gio, type rw */
-#define reg_gio_rw_i2c0_cfg___en___lsb 0
-#define reg_gio_rw_i2c0_cfg___en___width 1
-#define reg_gio_rw_i2c0_cfg___en___bit 0
-#define reg_gio_rw_i2c0_cfg___bit_order___lsb 1
-#define reg_gio_rw_i2c0_cfg___bit_order___width 1
-#define reg_gio_rw_i2c0_cfg___bit_order___bit 1
-#define reg_gio_rw_i2c0_cfg___scl_io___lsb 2
-#define reg_gio_rw_i2c0_cfg___scl_io___width 1
-#define reg_gio_rw_i2c0_cfg___scl_io___bit 2
-#define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3
-#define reg_gio_rw_i2c0_cfg___scl_inv___width 1
-#define reg_gio_rw_i2c0_cfg___scl_inv___bit 3
-#define reg_gio_rw_i2c0_cfg___sda_io___lsb 4
-#define reg_gio_rw_i2c0_cfg___sda_io___width 1
-#define reg_gio_rw_i2c0_cfg___sda_io___bit 4
-#define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5
-#define reg_gio_rw_i2c0_cfg___sda_idle___width 1
-#define reg_gio_rw_i2c0_cfg___sda_idle___bit 5
-#define reg_gio_rw_i2c0_cfg_offset 148
-
-/* Register rw_i2c0_ctrl, scope gio, type rw */
-#define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0
-#define reg_gio_rw_i2c0_ctrl___trf_bits___width 6
-#define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6
-#define reg_gio_rw_i2c0_ctrl___switch_dir___width 6
-#define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12
-#define reg_gio_rw_i2c0_ctrl___extra_start___width 3
-#define reg_gio_rw_i2c0_ctrl___early_end___lsb 15
-#define reg_gio_rw_i2c0_ctrl___early_end___width 1
-#define reg_gio_rw_i2c0_ctrl___early_end___bit 15
-#define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16
-#define reg_gio_rw_i2c0_ctrl___start_stop___width 1
-#define reg_gio_rw_i2c0_ctrl___start_stop___bit 16
-#define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17
-#define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17
-#define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18
-#define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18
-#define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19
-#define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19
-#define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20
-#define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20
-#define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21
-#define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21
-#define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22
-#define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22
-#define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23
-#define reg_gio_rw_i2c0_ctrl___ack_bit___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23
-#define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24
-#define reg_gio_rw_i2c0_ctrl___start_bit___width 1
-#define reg_gio_rw_i2c0_ctrl___start_bit___bit 24
-#define reg_gio_rw_i2c0_ctrl___freq___lsb 25
-#define reg_gio_rw_i2c0_ctrl___freq___width 2
-#define reg_gio_rw_i2c0_ctrl_offset 152
-
-/* Register rw_i2c0_data, scope gio, type rw */
-#define reg_gio_rw_i2c0_data___data0___lsb 0
-#define reg_gio_rw_i2c0_data___data0___width 8
-#define reg_gio_rw_i2c0_data___data1___lsb 8
-#define reg_gio_rw_i2c0_data___data1___width 8
-#define reg_gio_rw_i2c0_data___data2___lsb 16
-#define reg_gio_rw_i2c0_data___data2___width 8
-#define reg_gio_rw_i2c0_data___data3___lsb 24
-#define reg_gio_rw_i2c0_data___data3___width 8
-#define reg_gio_rw_i2c0_data_offset 156
-
-/* Register rw_i2c0_data2, scope gio, type rw */
-#define reg_gio_rw_i2c0_data2___data4___lsb 0
-#define reg_gio_rw_i2c0_data2___data4___width 8
-#define reg_gio_rw_i2c0_data2___data5___lsb 8
-#define reg_gio_rw_i2c0_data2___data5___width 8
-#define reg_gio_rw_i2c0_data2___start_val___lsb 16
-#define reg_gio_rw_i2c0_data2___start_val___width 6
-#define reg_gio_rw_i2c0_data2___ack_val___lsb 22
-#define reg_gio_rw_i2c0_data2___ack_val___width 6
-#define reg_gio_rw_i2c0_data2_offset 160
-
-/* Register rw_i2c1_start, scope gio, type rw */
-#define reg_gio_rw_i2c1_start___run___lsb 0
-#define reg_gio_rw_i2c1_start___run___width 1
-#define reg_gio_rw_i2c1_start___run___bit 0
-#define reg_gio_rw_i2c1_start_offset 164
-
-/* Register rw_i2c1_cfg, scope gio, type rw */
-#define reg_gio_rw_i2c1_cfg___en___lsb 0
-#define reg_gio_rw_i2c1_cfg___en___width 1
-#define reg_gio_rw_i2c1_cfg___en___bit 0
-#define reg_gio_rw_i2c1_cfg___bit_order___lsb 1
-#define reg_gio_rw_i2c1_cfg___bit_order___width 1
-#define reg_gio_rw_i2c1_cfg___bit_order___bit 1
-#define reg_gio_rw_i2c1_cfg___scl_io___lsb 2
-#define reg_gio_rw_i2c1_cfg___scl_io___width 1
-#define reg_gio_rw_i2c1_cfg___scl_io___bit 2
-#define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3
-#define reg_gio_rw_i2c1_cfg___scl_inv___width 1
-#define reg_gio_rw_i2c1_cfg___scl_inv___bit 3
-#define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4
-#define reg_gio_rw_i2c1_cfg___sda0_io___width 1
-#define reg_gio_rw_i2c1_cfg___sda0_io___bit 4
-#define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5
-#define reg_gio_rw_i2c1_cfg___sda0_idle___width 1
-#define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5
-#define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6
-#define reg_gio_rw_i2c1_cfg___sda1_io___width 1
-#define reg_gio_rw_i2c1_cfg___sda1_io___bit 6
-#define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7
-#define reg_gio_rw_i2c1_cfg___sda1_idle___width 1
-#define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7
-#define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8
-#define reg_gio_rw_i2c1_cfg___sda2_io___width 1
-#define reg_gio_rw_i2c1_cfg___sda2_io___bit 8
-#define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9
-#define reg_gio_rw_i2c1_cfg___sda2_idle___width 1
-#define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9
-#define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10
-#define reg_gio_rw_i2c1_cfg___sda3_io___width 1
-#define reg_gio_rw_i2c1_cfg___sda3_io___bit 10
-#define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11
-#define reg_gio_rw_i2c1_cfg___sda3_idle___width 1
-#define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11
-#define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12
-#define reg_gio_rw_i2c1_cfg___sda_sel___width 2
-#define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14
-#define reg_gio_rw_i2c1_cfg___sen_idle___width 1
-#define reg_gio_rw_i2c1_cfg___sen_idle___bit 14
-#define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15
-#define reg_gio_rw_i2c1_cfg___sen_inv___width 1
-#define reg_gio_rw_i2c1_cfg___sen_inv___bit 15
-#define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16
-#define reg_gio_rw_i2c1_cfg___sen_sel___width 2
-#define reg_gio_rw_i2c1_cfg_offset 168
-
-/* Register rw_i2c1_ctrl, scope gio, type rw */
-#define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0
-#define reg_gio_rw_i2c1_ctrl___trf_bits___width 6
-#define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6
-#define reg_gio_rw_i2c1_ctrl___switch_dir___width 6
-#define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12
-#define reg_gio_rw_i2c1_ctrl___extra_start___width 3
-#define reg_gio_rw_i2c1_ctrl___early_end___lsb 15
-#define reg_gio_rw_i2c1_ctrl___early_end___width 1
-#define reg_gio_rw_i2c1_ctrl___early_end___bit 15
-#define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16
-#define reg_gio_rw_i2c1_ctrl___start_stop___width 1
-#define reg_gio_rw_i2c1_ctrl___start_stop___bit 16
-#define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17
-#define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17
-#define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18
-#define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18
-#define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19
-#define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19
-#define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20
-#define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20
-#define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21
-#define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21
-#define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22
-#define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22
-#define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23
-#define reg_gio_rw_i2c1_ctrl___ack_bit___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23
-#define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24
-#define reg_gio_rw_i2c1_ctrl___start_bit___width 1
-#define reg_gio_rw_i2c1_ctrl___start_bit___bit 24
-#define reg_gio_rw_i2c1_ctrl___freq___lsb 25
-#define reg_gio_rw_i2c1_ctrl___freq___width 2
-#define reg_gio_rw_i2c1_ctrl_offset 172
-
-/* Register rw_i2c1_data, scope gio, type rw */
-#define reg_gio_rw_i2c1_data___data0___lsb 0
-#define reg_gio_rw_i2c1_data___data0___width 8
-#define reg_gio_rw_i2c1_data___data1___lsb 8
-#define reg_gio_rw_i2c1_data___data1___width 8
-#define reg_gio_rw_i2c1_data___data2___lsb 16
-#define reg_gio_rw_i2c1_data___data2___width 8
-#define reg_gio_rw_i2c1_data___data3___lsb 24
-#define reg_gio_rw_i2c1_data___data3___width 8
-#define reg_gio_rw_i2c1_data_offset 176
-
-/* Register rw_i2c1_data2, scope gio, type rw */
-#define reg_gio_rw_i2c1_data2___data4___lsb 0
-#define reg_gio_rw_i2c1_data2___data4___width 8
-#define reg_gio_rw_i2c1_data2___data5___lsb 8
-#define reg_gio_rw_i2c1_data2___data5___width 8
-#define reg_gio_rw_i2c1_data2___start_val___lsb 16
-#define reg_gio_rw_i2c1_data2___start_val___width 6
-#define reg_gio_rw_i2c1_data2___ack_val___lsb 22
-#define reg_gio_rw_i2c1_data2___ack_val___width 6
-#define reg_gio_rw_i2c1_data2_offset 180
-
-/* Register r_ppwm_stat, scope gio, type r */
-#define reg_gio_r_ppwm_stat___freq___lsb 0
-#define reg_gio_r_ppwm_stat___freq___width 2
-#define reg_gio_r_ppwm_stat_offset 184
-
-/* Register rw_ppwm_data, scope gio, type rw */
-#define reg_gio_rw_ppwm_data___data___lsb 0
-#define reg_gio_rw_ppwm_data___data___width 8
-#define reg_gio_rw_ppwm_data_offset 188
-
-/* Register rw_pwm0_ctrl, scope gio, type rw */
-#define reg_gio_rw_pwm0_ctrl___mode___lsb 0
-#define reg_gio_rw_pwm0_ctrl___mode___width 2
-#define reg_gio_rw_pwm0_ctrl___ccd_override___lsb 2
-#define reg_gio_rw_pwm0_ctrl___ccd_override___width 1
-#define reg_gio_rw_pwm0_ctrl___ccd_override___bit 2
-#define reg_gio_rw_pwm0_ctrl___ccd_val___lsb 3
-#define reg_gio_rw_pwm0_ctrl___ccd_val___width 1
-#define reg_gio_rw_pwm0_ctrl___ccd_val___bit 3
-#define reg_gio_rw_pwm0_ctrl_offset 192
-
-/* Register rw_pwm0_var, scope gio, type rw */
-#define reg_gio_rw_pwm0_var___lo___lsb 0
-#define reg_gio_rw_pwm0_var___lo___width 13
-#define reg_gio_rw_pwm0_var___hi___lsb 13
-#define reg_gio_rw_pwm0_var___hi___width 13
-#define reg_gio_rw_pwm0_var_offset 196
-
-/* Register rw_pwm0_data, scope gio, type rw */
-#define reg_gio_rw_pwm0_data___data___lsb 0
-#define reg_gio_rw_pwm0_data___data___width 8
-#define reg_gio_rw_pwm0_data_offset 200
-
-/* Register rw_pwm1_ctrl, scope gio, type rw */
-#define reg_gio_rw_pwm1_ctrl___mode___lsb 0
-#define reg_gio_rw_pwm1_ctrl___mode___width 2
-#define reg_gio_rw_pwm1_ctrl___ccd_override___lsb 2
-#define reg_gio_rw_pwm1_ctrl___ccd_override___width 1
-#define reg_gio_rw_pwm1_ctrl___ccd_override___bit 2
-#define reg_gio_rw_pwm1_ctrl___ccd_val___lsb 3
-#define reg_gio_rw_pwm1_ctrl___ccd_val___width 1
-#define reg_gio_rw_pwm1_ctrl___ccd_val___bit 3
-#define reg_gio_rw_pwm1_ctrl_offset 204
-
-/* Register rw_pwm1_var, scope gio, type rw */
-#define reg_gio_rw_pwm1_var___lo___lsb 0
-#define reg_gio_rw_pwm1_var___lo___width 13
-#define reg_gio_rw_pwm1_var___hi___lsb 13
-#define reg_gio_rw_pwm1_var___hi___width 13
-#define reg_gio_rw_pwm1_var_offset 208
-
-/* Register rw_pwm1_data, scope gio, type rw */
-#define reg_gio_rw_pwm1_data___data___lsb 0
-#define reg_gio_rw_pwm1_data___data___width 8
-#define reg_gio_rw_pwm1_data_offset 212
-
-/* Register rw_pwm2_ctrl, scope gio, type rw */
-#define reg_gio_rw_pwm2_ctrl___mode___lsb 0
-#define reg_gio_rw_pwm2_ctrl___mode___width 2
-#define reg_gio_rw_pwm2_ctrl___ccd_override___lsb 2
-#define reg_gio_rw_pwm2_ctrl___ccd_override___width 1
-#define reg_gio_rw_pwm2_ctrl___ccd_override___bit 2
-#define reg_gio_rw_pwm2_ctrl___ccd_val___lsb 3
-#define reg_gio_rw_pwm2_ctrl___ccd_val___width 1
-#define reg_gio_rw_pwm2_ctrl___ccd_val___bit 3
-#define reg_gio_rw_pwm2_ctrl_offset 216
-
-/* Register rw_pwm2_var, scope gio, type rw */
-#define reg_gio_rw_pwm2_var___lo___lsb 0
-#define reg_gio_rw_pwm2_var___lo___width 13
-#define reg_gio_rw_pwm2_var___hi___lsb 13
-#define reg_gio_rw_pwm2_var___hi___width 13
-#define reg_gio_rw_pwm2_var_offset 220
-
-/* Register rw_pwm2_data, scope gio, type rw */
-#define reg_gio_rw_pwm2_data___data___lsb 0
-#define reg_gio_rw_pwm2_data___data___width 8
-#define reg_gio_rw_pwm2_data_offset 224
-
-/* Register rw_pwm_in_cfg, scope gio, type rw */
-#define reg_gio_rw_pwm_in_cfg___pin___lsb 0
-#define reg_gio_rw_pwm_in_cfg___pin___width 3
-#define reg_gio_rw_pwm_in_cfg_offset 228
-
-/* Register r_pwm_in_lo, scope gio, type r */
-#define reg_gio_r_pwm_in_lo___data___lsb 0
-#define reg_gio_r_pwm_in_lo___data___width 32
-#define reg_gio_r_pwm_in_lo_offset 232
-
-/* Register r_pwm_in_hi, scope gio, type r */
-#define reg_gio_r_pwm_in_hi___data___lsb 0
-#define reg_gio_r_pwm_in_hi___data___width 32
-#define reg_gio_r_pwm_in_hi_offset 236
-
-/* Register r_pwm_in_cnt, scope gio, type r */
-#define reg_gio_r_pwm_in_cnt___data___lsb 0
-#define reg_gio_r_pwm_in_cnt___data___width 32
-#define reg_gio_r_pwm_in_cnt_offset 240
-
-
-/* Constants */
-#define regk_gio_anyedge                          0x00000007
-#define regk_gio_f100k                            0x00000000
-#define regk_gio_f1562                            0x00000000
-#define regk_gio_f195                             0x00000003
-#define regk_gio_f1m                              0x00000002
-#define regk_gio_f390                             0x00000002
-#define regk_gio_f400k                            0x00000001
-#define regk_gio_f5m                              0x00000003
-#define regk_gio_f781                             0x00000001
-#define regk_gio_hi                               0x00000001
-#define regk_gio_in                               0x00000000
-#define regk_gio_intr_pa0                         0x00000000
-#define regk_gio_intr_pa1                         0x00000000
-#define regk_gio_intr_pa10                        0x00000001
-#define regk_gio_intr_pa11                        0x00000001
-#define regk_gio_intr_pa12                        0x00000001
-#define regk_gio_intr_pa13                        0x00000001
-#define regk_gio_intr_pa14                        0x00000001
-#define regk_gio_intr_pa15                        0x00000001
-#define regk_gio_intr_pa16                        0x00000002
-#define regk_gio_intr_pa17                        0x00000002
-#define regk_gio_intr_pa18                        0x00000002
-#define regk_gio_intr_pa19                        0x00000002
-#define regk_gio_intr_pa2                         0x00000000
-#define regk_gio_intr_pa20                        0x00000002
-#define regk_gio_intr_pa21                        0x00000002
-#define regk_gio_intr_pa22                        0x00000002
-#define regk_gio_intr_pa23                        0x00000002
-#define regk_gio_intr_pa24                        0x00000003
-#define regk_gio_intr_pa25                        0x00000003
-#define regk_gio_intr_pa26                        0x00000003
-#define regk_gio_intr_pa27                        0x00000003
-#define regk_gio_intr_pa28                        0x00000003
-#define regk_gio_intr_pa29                        0x00000003
-#define regk_gio_intr_pa3                         0x00000000
-#define regk_gio_intr_pa30                        0x00000003
-#define regk_gio_intr_pa31                        0x00000003
-#define regk_gio_intr_pa4                         0x00000000
-#define regk_gio_intr_pa5                         0x00000000
-#define regk_gio_intr_pa6                         0x00000000
-#define regk_gio_intr_pa7                         0x00000000
-#define regk_gio_intr_pa8                         0x00000001
-#define regk_gio_intr_pa9                         0x00000001
-#define regk_gio_intr_pb0                         0x00000004
-#define regk_gio_intr_pb1                         0x00000004
-#define regk_gio_intr_pb10                        0x00000005
-#define regk_gio_intr_pb11                        0x00000005
-#define regk_gio_intr_pb12                        0x00000005
-#define regk_gio_intr_pb13                        0x00000005
-#define regk_gio_intr_pb14                        0x00000005
-#define regk_gio_intr_pb15                        0x00000005
-#define regk_gio_intr_pb16                        0x00000006
-#define regk_gio_intr_pb17                        0x00000006
-#define regk_gio_intr_pb18                        0x00000006
-#define regk_gio_intr_pb19                        0x00000006
-#define regk_gio_intr_pb2                         0x00000004
-#define regk_gio_intr_pb20                        0x00000006
-#define regk_gio_intr_pb21                        0x00000006
-#define regk_gio_intr_pb22                        0x00000006
-#define regk_gio_intr_pb23                        0x00000006
-#define regk_gio_intr_pb24                        0x00000007
-#define regk_gio_intr_pb25                        0x00000007
-#define regk_gio_intr_pb26                        0x00000007
-#define regk_gio_intr_pb27                        0x00000007
-#define regk_gio_intr_pb28                        0x00000007
-#define regk_gio_intr_pb29                        0x00000007
-#define regk_gio_intr_pb3                         0x00000004
-#define regk_gio_intr_pb30                        0x00000007
-#define regk_gio_intr_pb31                        0x00000007
-#define regk_gio_intr_pb4                         0x00000004
-#define regk_gio_intr_pb5                         0x00000004
-#define regk_gio_intr_pb6                         0x00000004
-#define regk_gio_intr_pb7                         0x00000004
-#define regk_gio_intr_pb8                         0x00000005
-#define regk_gio_intr_pb9                         0x00000005
-#define regk_gio_intr_pc0                         0x00000008
-#define regk_gio_intr_pc1                         0x00000008
-#define regk_gio_intr_pc10                        0x00000009
-#define regk_gio_intr_pc11                        0x00000009
-#define regk_gio_intr_pc12                        0x00000009
-#define regk_gio_intr_pc13                        0x00000009
-#define regk_gio_intr_pc14                        0x00000009
-#define regk_gio_intr_pc15                        0x00000009
-#define regk_gio_intr_pc2                         0x00000008
-#define regk_gio_intr_pc3                         0x00000008
-#define regk_gio_intr_pc4                         0x00000008
-#define regk_gio_intr_pc5                         0x00000008
-#define regk_gio_intr_pc6                         0x00000008
-#define regk_gio_intr_pc7                         0x00000008
-#define regk_gio_intr_pc8                         0x00000009
-#define regk_gio_intr_pc9                         0x00000009
-#define regk_gio_intr_pd0                         0x0000000c
-#define regk_gio_intr_pd1                         0x0000000c
-#define regk_gio_intr_pd10                        0x0000000d
-#define regk_gio_intr_pd11                        0x0000000d
-#define regk_gio_intr_pd12                        0x0000000d
-#define regk_gio_intr_pd13                        0x0000000d
-#define regk_gio_intr_pd14                        0x0000000d
-#define regk_gio_intr_pd15                        0x0000000d
-#define regk_gio_intr_pd16                        0x0000000e
-#define regk_gio_intr_pd17                        0x0000000e
-#define regk_gio_intr_pd18                        0x0000000e
-#define regk_gio_intr_pd19                        0x0000000e
-#define regk_gio_intr_pd2                         0x0000000c
-#define regk_gio_intr_pd20                        0x0000000e
-#define regk_gio_intr_pd21                        0x0000000e
-#define regk_gio_intr_pd22                        0x0000000e
-#define regk_gio_intr_pd23                        0x0000000e
-#define regk_gio_intr_pd24                        0x0000000f
-#define regk_gio_intr_pd25                        0x0000000f
-#define regk_gio_intr_pd26                        0x0000000f
-#define regk_gio_intr_pd27                        0x0000000f
-#define regk_gio_intr_pd28                        0x0000000f
-#define regk_gio_intr_pd29                        0x0000000f
-#define regk_gio_intr_pd3                         0x0000000c
-#define regk_gio_intr_pd30                        0x0000000f
-#define regk_gio_intr_pd31                        0x0000000f
-#define regk_gio_intr_pd4                         0x0000000c
-#define regk_gio_intr_pd5                         0x0000000c
-#define regk_gio_intr_pd6                         0x0000000c
-#define regk_gio_intr_pd7                         0x0000000c
-#define regk_gio_intr_pd8                         0x0000000d
-#define regk_gio_intr_pd9                         0x0000000d
-#define regk_gio_lo                               0x00000002
-#define regk_gio_lsb                              0x00000000
-#define regk_gio_msb                              0x00000001
-#define regk_gio_negedge                          0x00000006
-#define regk_gio_no                               0x00000000
-#define regk_gio_no_switch                        0x0000003f
-#define regk_gio_none                             0x00000007
-#define regk_gio_off                              0x00000000
-#define regk_gio_opendrain                        0x00000000
-#define regk_gio_out                              0x00000001
-#define regk_gio_posedge                          0x00000005
-#define regk_gio_pwm_hfp                          0x00000002
-#define regk_gio_pwm_pa0                          0x00000001
-#define regk_gio_pwm_pa19                         0x00000004
-#define regk_gio_pwm_pa6                          0x00000002
-#define regk_gio_pwm_pa7                          0x00000003
-#define regk_gio_pwm_pb26                         0x00000005
-#define regk_gio_pwm_pd23                         0x00000006
-#define regk_gio_pwm_pd31                         0x00000007
-#define regk_gio_pwm_std                          0x00000001
-#define regk_gio_pwm_var                          0x00000003
-#define regk_gio_rw_i2c0_cfg_default              0x00000020
-#define regk_gio_rw_i2c0_ctrl_default             0x00010000
-#define regk_gio_rw_i2c0_start_default            0x00000000
-#define regk_gio_rw_i2c1_cfg_default              0x00000aa0
-#define regk_gio_rw_i2c1_ctrl_default             0x00010000
-#define regk_gio_rw_i2c1_start_default            0x00000000
-#define regk_gio_rw_intr_cfg_default              0x00000000
-#define regk_gio_rw_intr_mask_default             0x00000000
-#define regk_gio_rw_pa_oe_default                 0x00000000
-#define regk_gio_rw_pb_oe_default                 0x00000000
-#define regk_gio_rw_pc_oe_default                 0x00000000
-#define regk_gio_rw_ppwm_data_default             0x00000000
-#define regk_gio_rw_pwm0_ctrl_default             0x00000000
-#define regk_gio_rw_pwm1_ctrl_default             0x00000000
-#define regk_gio_rw_pwm2_ctrl_default             0x00000000
-#define regk_gio_rw_pwm_in_cfg_default            0x00000000
-#define regk_gio_sda0                             0x00000000
-#define regk_gio_sda1                             0x00000001
-#define regk_gio_sda2                             0x00000002
-#define regk_gio_sda3                             0x00000003
-#define regk_gio_sen                              0x00000000
-#define regk_gio_set                              0x00000003
-#define regk_gio_yes                              0x00000001
-#endif /* __gio_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h
deleted file mode 100644
index c3dc9c666c46..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h
+++ /dev/null
@@ -1,572 +0,0 @@
-#ifndef __pinmux_defs_asm_h
-#define __pinmux_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           pinmux.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile pinmux_defs_asm.h pinmux.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_hwprot, scope pinmux, type rw */
-#define reg_pinmux_rw_hwprot___eth___lsb 0
-#define reg_pinmux_rw_hwprot___eth___width 1
-#define reg_pinmux_rw_hwprot___eth___bit 0
-#define reg_pinmux_rw_hwprot___eth_mdio___lsb 1
-#define reg_pinmux_rw_hwprot___eth_mdio___width 1
-#define reg_pinmux_rw_hwprot___eth_mdio___bit 1
-#define reg_pinmux_rw_hwprot___geth___lsb 2
-#define reg_pinmux_rw_hwprot___geth___width 1
-#define reg_pinmux_rw_hwprot___geth___bit 2
-#define reg_pinmux_rw_hwprot___tg___lsb 3
-#define reg_pinmux_rw_hwprot___tg___width 1
-#define reg_pinmux_rw_hwprot___tg___bit 3
-#define reg_pinmux_rw_hwprot___tg_clk___lsb 4
-#define reg_pinmux_rw_hwprot___tg_clk___width 1
-#define reg_pinmux_rw_hwprot___tg_clk___bit 4
-#define reg_pinmux_rw_hwprot___vout___lsb 5
-#define reg_pinmux_rw_hwprot___vout___width 1
-#define reg_pinmux_rw_hwprot___vout___bit 5
-#define reg_pinmux_rw_hwprot___vout_sync___lsb 6
-#define reg_pinmux_rw_hwprot___vout_sync___width 1
-#define reg_pinmux_rw_hwprot___vout_sync___bit 6
-#define reg_pinmux_rw_hwprot___ser1___lsb 7
-#define reg_pinmux_rw_hwprot___ser1___width 1
-#define reg_pinmux_rw_hwprot___ser1___bit 7
-#define reg_pinmux_rw_hwprot___ser2___lsb 8
-#define reg_pinmux_rw_hwprot___ser2___width 1
-#define reg_pinmux_rw_hwprot___ser2___bit 8
-#define reg_pinmux_rw_hwprot___ser3___lsb 9
-#define reg_pinmux_rw_hwprot___ser3___width 1
-#define reg_pinmux_rw_hwprot___ser3___bit 9
-#define reg_pinmux_rw_hwprot___ser4___lsb 10
-#define reg_pinmux_rw_hwprot___ser4___width 1
-#define reg_pinmux_rw_hwprot___ser4___bit 10
-#define reg_pinmux_rw_hwprot___sser___lsb 11
-#define reg_pinmux_rw_hwprot___sser___width 1
-#define reg_pinmux_rw_hwprot___sser___bit 11
-#define reg_pinmux_rw_hwprot___pwm0___lsb 12
-#define reg_pinmux_rw_hwprot___pwm0___width 1
-#define reg_pinmux_rw_hwprot___pwm0___bit 12
-#define reg_pinmux_rw_hwprot___pwm1___lsb 13
-#define reg_pinmux_rw_hwprot___pwm1___width 1
-#define reg_pinmux_rw_hwprot___pwm1___bit 13
-#define reg_pinmux_rw_hwprot___pwm2___lsb 14
-#define reg_pinmux_rw_hwprot___pwm2___width 1
-#define reg_pinmux_rw_hwprot___pwm2___bit 14
-#define reg_pinmux_rw_hwprot___timer0___lsb 15
-#define reg_pinmux_rw_hwprot___timer0___width 1
-#define reg_pinmux_rw_hwprot___timer0___bit 15
-#define reg_pinmux_rw_hwprot___timer1___lsb 16
-#define reg_pinmux_rw_hwprot___timer1___width 1
-#define reg_pinmux_rw_hwprot___timer1___bit 16
-#define reg_pinmux_rw_hwprot___pio___lsb 17
-#define reg_pinmux_rw_hwprot___pio___width 1
-#define reg_pinmux_rw_hwprot___pio___bit 17
-#define reg_pinmux_rw_hwprot___i2c0___lsb 18
-#define reg_pinmux_rw_hwprot___i2c0___width 1
-#define reg_pinmux_rw_hwprot___i2c0___bit 18
-#define reg_pinmux_rw_hwprot___i2c1___lsb 19
-#define reg_pinmux_rw_hwprot___i2c1___width 1
-#define reg_pinmux_rw_hwprot___i2c1___bit 19
-#define reg_pinmux_rw_hwprot___i2c1_sda1___lsb 20
-#define reg_pinmux_rw_hwprot___i2c1_sda1___width 1
-#define reg_pinmux_rw_hwprot___i2c1_sda1___bit 20
-#define reg_pinmux_rw_hwprot___i2c1_sda2___lsb 21
-#define reg_pinmux_rw_hwprot___i2c1_sda2___width 1
-#define reg_pinmux_rw_hwprot___i2c1_sda2___bit 21
-#define reg_pinmux_rw_hwprot___i2c1_sda3___lsb 22
-#define reg_pinmux_rw_hwprot___i2c1_sda3___width 1
-#define reg_pinmux_rw_hwprot___i2c1_sda3___bit 22
-#define reg_pinmux_rw_hwprot___i2c1_sen___lsb 23
-#define reg_pinmux_rw_hwprot___i2c1_sen___width 1
-#define reg_pinmux_rw_hwprot___i2c1_sen___bit 23
-#define reg_pinmux_rw_hwprot_offset 0
-
-/* Register rw_gio_pa, scope pinmux, type rw */
-#define reg_pinmux_rw_gio_pa___pa0___lsb 0
-#define reg_pinmux_rw_gio_pa___pa0___width 1
-#define reg_pinmux_rw_gio_pa___pa0___bit 0
-#define reg_pinmux_rw_gio_pa___pa1___lsb 1
-#define reg_pinmux_rw_gio_pa___pa1___width 1
-#define reg_pinmux_rw_gio_pa___pa1___bit 1
-#define reg_pinmux_rw_gio_pa___pa2___lsb 2
-#define reg_pinmux_rw_gio_pa___pa2___width 1
-#define reg_pinmux_rw_gio_pa___pa2___bit 2
-#define reg_pinmux_rw_gio_pa___pa3___lsb 3
-#define reg_pinmux_rw_gio_pa___pa3___width 1
-#define reg_pinmux_rw_gio_pa___pa3___bit 3
-#define reg_pinmux_rw_gio_pa___pa4___lsb 4
-#define reg_pinmux_rw_gio_pa___pa4___width 1
-#define reg_pinmux_rw_gio_pa___pa4___bit 4
-#define reg_pinmux_rw_gio_pa___pa5___lsb 5
-#define reg_pinmux_rw_gio_pa___pa5___width 1
-#define reg_pinmux_rw_gio_pa___pa5___bit 5
-#define reg_pinmux_rw_gio_pa___pa6___lsb 6
-#define reg_pinmux_rw_gio_pa___pa6___width 1
-#define reg_pinmux_rw_gio_pa___pa6___bit 6
-#define reg_pinmux_rw_gio_pa___pa7___lsb 7
-#define reg_pinmux_rw_gio_pa___pa7___width 1
-#define reg_pinmux_rw_gio_pa___pa7___bit 7
-#define reg_pinmux_rw_gio_pa___pa8___lsb 8
-#define reg_pinmux_rw_gio_pa___pa8___width 1
-#define reg_pinmux_rw_gio_pa___pa8___bit 8
-#define reg_pinmux_rw_gio_pa___pa9___lsb 9
-#define reg_pinmux_rw_gio_pa___pa9___width 1
-#define reg_pinmux_rw_gio_pa___pa9___bit 9
-#define reg_pinmux_rw_gio_pa___pa10___lsb 10
-#define reg_pinmux_rw_gio_pa___pa10___width 1
-#define reg_pinmux_rw_gio_pa___pa10___bit 10
-#define reg_pinmux_rw_gio_pa___pa11___lsb 11
-#define reg_pinmux_rw_gio_pa___pa11___width 1
-#define reg_pinmux_rw_gio_pa___pa11___bit 11
-#define reg_pinmux_rw_gio_pa___pa12___lsb 12
-#define reg_pinmux_rw_gio_pa___pa12___width 1
-#define reg_pinmux_rw_gio_pa___pa12___bit 12
-#define reg_pinmux_rw_gio_pa___pa13___lsb 13
-#define reg_pinmux_rw_gio_pa___pa13___width 1
-#define reg_pinmux_rw_gio_pa___pa13___bit 13
-#define reg_pinmux_rw_gio_pa___pa14___lsb 14
-#define reg_pinmux_rw_gio_pa___pa14___width 1
-#define reg_pinmux_rw_gio_pa___pa14___bit 14
-#define reg_pinmux_rw_gio_pa___pa15___lsb 15
-#define reg_pinmux_rw_gio_pa___pa15___width 1
-#define reg_pinmux_rw_gio_pa___pa15___bit 15
-#define reg_pinmux_rw_gio_pa___pa16___lsb 16
-#define reg_pinmux_rw_gio_pa___pa16___width 1
-#define reg_pinmux_rw_gio_pa___pa16___bit 16
-#define reg_pinmux_rw_gio_pa___pa17___lsb 17
-#define reg_pinmux_rw_gio_pa___pa17___width 1
-#define reg_pinmux_rw_gio_pa___pa17___bit 17
-#define reg_pinmux_rw_gio_pa___pa18___lsb 18
-#define reg_pinmux_rw_gio_pa___pa18___width 1
-#define reg_pinmux_rw_gio_pa___pa18___bit 18
-#define reg_pinmux_rw_gio_pa___pa19___lsb 19
-#define reg_pinmux_rw_gio_pa___pa19___width 1
-#define reg_pinmux_rw_gio_pa___pa19___bit 19
-#define reg_pinmux_rw_gio_pa___pa20___lsb 20
-#define reg_pinmux_rw_gio_pa___pa20___width 1
-#define reg_pinmux_rw_gio_pa___pa20___bit 20
-#define reg_pinmux_rw_gio_pa___pa21___lsb 21
-#define reg_pinmux_rw_gio_pa___pa21___width 1
-#define reg_pinmux_rw_gio_pa___pa21___bit 21
-#define reg_pinmux_rw_gio_pa___pa22___lsb 22
-#define reg_pinmux_rw_gio_pa___pa22___width 1
-#define reg_pinmux_rw_gio_pa___pa22___bit 22
-#define reg_pinmux_rw_gio_pa___pa23___lsb 23
-#define reg_pinmux_rw_gio_pa___pa23___width 1
-#define reg_pinmux_rw_gio_pa___pa23___bit 23
-#define reg_pinmux_rw_gio_pa___pa24___lsb 24
-#define reg_pinmux_rw_gio_pa___pa24___width 1
-#define reg_pinmux_rw_gio_pa___pa24___bit 24
-#define reg_pinmux_rw_gio_pa___pa25___lsb 25
-#define reg_pinmux_rw_gio_pa___pa25___width 1
-#define reg_pinmux_rw_gio_pa___pa25___bit 25
-#define reg_pinmux_rw_gio_pa___pa26___lsb 26
-#define reg_pinmux_rw_gio_pa___pa26___width 1
-#define reg_pinmux_rw_gio_pa___pa26___bit 26
-#define reg_pinmux_rw_gio_pa___pa27___lsb 27
-#define reg_pinmux_rw_gio_pa___pa27___width 1
-#define reg_pinmux_rw_gio_pa___pa27___bit 27
-#define reg_pinmux_rw_gio_pa___pa28___lsb 28
-#define reg_pinmux_rw_gio_pa___pa28___width 1
-#define reg_pinmux_rw_gio_pa___pa28___bit 28
-#define reg_pinmux_rw_gio_pa___pa29___lsb 29
-#define reg_pinmux_rw_gio_pa___pa29___width 1
-#define reg_pinmux_rw_gio_pa___pa29___bit 29
-#define reg_pinmux_rw_gio_pa___pa30___lsb 30
-#define reg_pinmux_rw_gio_pa___pa30___width 1
-#define reg_pinmux_rw_gio_pa___pa30___bit 30
-#define reg_pinmux_rw_gio_pa___pa31___lsb 31
-#define reg_pinmux_rw_gio_pa___pa31___width 1
-#define reg_pinmux_rw_gio_pa___pa31___bit 31
-#define reg_pinmux_rw_gio_pa_offset 4
-
-/* Register rw_gio_pb, scope pinmux, type rw */
-#define reg_pinmux_rw_gio_pb___pb0___lsb 0
-#define reg_pinmux_rw_gio_pb___pb0___width 1
-#define reg_pinmux_rw_gio_pb___pb0___bit 0
-#define reg_pinmux_rw_gio_pb___pb1___lsb 1
-#define reg_pinmux_rw_gio_pb___pb1___width 1
-#define reg_pinmux_rw_gio_pb___pb1___bit 1
-#define reg_pinmux_rw_gio_pb___pb2___lsb 2
-#define reg_pinmux_rw_gio_pb___pb2___width 1
-#define reg_pinmux_rw_gio_pb___pb2___bit 2
-#define reg_pinmux_rw_gio_pb___pb3___lsb 3
-#define reg_pinmux_rw_gio_pb___pb3___width 1
-#define reg_pinmux_rw_gio_pb___pb3___bit 3
-#define reg_pinmux_rw_gio_pb___pb4___lsb 4
-#define reg_pinmux_rw_gio_pb___pb4___width 1
-#define reg_pinmux_rw_gio_pb___pb4___bit 4
-#define reg_pinmux_rw_gio_pb___pb5___lsb 5
-#define reg_pinmux_rw_gio_pb___pb5___width 1
-#define reg_pinmux_rw_gio_pb___pb5___bit 5
-#define reg_pinmux_rw_gio_pb___pb6___lsb 6
-#define reg_pinmux_rw_gio_pb___pb6___width 1
-#define reg_pinmux_rw_gio_pb___pb6___bit 6
-#define reg_pinmux_rw_gio_pb___pb7___lsb 7
-#define reg_pinmux_rw_gio_pb___pb7___width 1
-#define reg_pinmux_rw_gio_pb___pb7___bit 7
-#define reg_pinmux_rw_gio_pb___pb8___lsb 8
-#define reg_pinmux_rw_gio_pb___pb8___width 1
-#define reg_pinmux_rw_gio_pb___pb8___bit 8
-#define reg_pinmux_rw_gio_pb___pb9___lsb 9
-#define reg_pinmux_rw_gio_pb___pb9___width 1
-#define reg_pinmux_rw_gio_pb___pb9___bit 9
-#define reg_pinmux_rw_gio_pb___pb10___lsb 10
-#define reg_pinmux_rw_gio_pb___pb10___width 1
-#define reg_pinmux_rw_gio_pb___pb10___bit 10
-#define reg_pinmux_rw_gio_pb___pb11___lsb 11
-#define reg_pinmux_rw_gio_pb___pb11___width 1
-#define reg_pinmux_rw_gio_pb___pb11___bit 11
-#define reg_pinmux_rw_gio_pb___pb12___lsb 12
-#define reg_pinmux_rw_gio_pb___pb12___width 1
-#define reg_pinmux_rw_gio_pb___pb12___bit 12
-#define reg_pinmux_rw_gio_pb___pb13___lsb 13
-#define reg_pinmux_rw_gio_pb___pb13___width 1
-#define reg_pinmux_rw_gio_pb___pb13___bit 13
-#define reg_pinmux_rw_gio_pb___pb14___lsb 14
-#define reg_pinmux_rw_gio_pb___pb14___width 1
-#define reg_pinmux_rw_gio_pb___pb14___bit 14
-#define reg_pinmux_rw_gio_pb___pb15___lsb 15
-#define reg_pinmux_rw_gio_pb___pb15___width 1
-#define reg_pinmux_rw_gio_pb___pb15___bit 15
-#define reg_pinmux_rw_gio_pb___pb16___lsb 16
-#define reg_pinmux_rw_gio_pb___pb16___width 1
-#define reg_pinmux_rw_gio_pb___pb16___bit 16
-#define reg_pinmux_rw_gio_pb___pb17___lsb 17
-#define reg_pinmux_rw_gio_pb___pb17___width 1
-#define reg_pinmux_rw_gio_pb___pb17___bit 17
-#define reg_pinmux_rw_gio_pb___pb18___lsb 18
-#define reg_pinmux_rw_gio_pb___pb18___width 1
-#define reg_pinmux_rw_gio_pb___pb18___bit 18
-#define reg_pinmux_rw_gio_pb___pb19___lsb 19
-#define reg_pinmux_rw_gio_pb___pb19___width 1
-#define reg_pinmux_rw_gio_pb___pb19___bit 19
-#define reg_pinmux_rw_gio_pb___pb20___lsb 20
-#define reg_pinmux_rw_gio_pb___pb20___width 1
-#define reg_pinmux_rw_gio_pb___pb20___bit 20
-#define reg_pinmux_rw_gio_pb___pb21___lsb 21
-#define reg_pinmux_rw_gio_pb___pb21___width 1
-#define reg_pinmux_rw_gio_pb___pb21___bit 21
-#define reg_pinmux_rw_gio_pb___pb22___lsb 22
-#define reg_pinmux_rw_gio_pb___pb22___width 1
-#define reg_pinmux_rw_gio_pb___pb22___bit 22
-#define reg_pinmux_rw_gio_pb___pb23___lsb 23
-#define reg_pinmux_rw_gio_pb___pb23___width 1
-#define reg_pinmux_rw_gio_pb___pb23___bit 23
-#define reg_pinmux_rw_gio_pb___pb24___lsb 24
-#define reg_pinmux_rw_gio_pb___pb24___width 1
-#define reg_pinmux_rw_gio_pb___pb24___bit 24
-#define reg_pinmux_rw_gio_pb___pb25___lsb 25
-#define reg_pinmux_rw_gio_pb___pb25___width 1
-#define reg_pinmux_rw_gio_pb___pb25___bit 25
-#define reg_pinmux_rw_gio_pb___pb26___lsb 26
-#define reg_pinmux_rw_gio_pb___pb26___width 1
-#define reg_pinmux_rw_gio_pb___pb26___bit 26
-#define reg_pinmux_rw_gio_pb___pb27___lsb 27
-#define reg_pinmux_rw_gio_pb___pb27___width 1
-#define reg_pinmux_rw_gio_pb___pb27___bit 27
-#define reg_pinmux_rw_gio_pb___pb28___lsb 28
-#define reg_pinmux_rw_gio_pb___pb28___width 1
-#define reg_pinmux_rw_gio_pb___pb28___bit 28
-#define reg_pinmux_rw_gio_pb___pb29___lsb 29
-#define reg_pinmux_rw_gio_pb___pb29___width 1
-#define reg_pinmux_rw_gio_pb___pb29___bit 29
-#define reg_pinmux_rw_gio_pb___pb30___lsb 30
-#define reg_pinmux_rw_gio_pb___pb30___width 1
-#define reg_pinmux_rw_gio_pb___pb30___bit 30
-#define reg_pinmux_rw_gio_pb___pb31___lsb 31
-#define reg_pinmux_rw_gio_pb___pb31___width 1
-#define reg_pinmux_rw_gio_pb___pb31___bit 31
-#define reg_pinmux_rw_gio_pb_offset 8
-
-/* Register rw_gio_pc, scope pinmux, type rw */
-#define reg_pinmux_rw_gio_pc___pc0___lsb 0
-#define reg_pinmux_rw_gio_pc___pc0___width 1
-#define reg_pinmux_rw_gio_pc___pc0___bit 0
-#define reg_pinmux_rw_gio_pc___pc1___lsb 1
-#define reg_pinmux_rw_gio_pc___pc1___width 1
-#define reg_pinmux_rw_gio_pc___pc1___bit 1
-#define reg_pinmux_rw_gio_pc___pc2___lsb 2
-#define reg_pinmux_rw_gio_pc___pc2___width 1
-#define reg_pinmux_rw_gio_pc___pc2___bit 2
-#define reg_pinmux_rw_gio_pc___pc3___lsb 3
-#define reg_pinmux_rw_gio_pc___pc3___width 1
-#define reg_pinmux_rw_gio_pc___pc3___bit 3
-#define reg_pinmux_rw_gio_pc___pc4___lsb 4
-#define reg_pinmux_rw_gio_pc___pc4___width 1
-#define reg_pinmux_rw_gio_pc___pc4___bit 4
-#define reg_pinmux_rw_gio_pc___pc5___lsb 5
-#define reg_pinmux_rw_gio_pc___pc5___width 1
-#define reg_pinmux_rw_gio_pc___pc5___bit 5
-#define reg_pinmux_rw_gio_pc___pc6___lsb 6
-#define reg_pinmux_rw_gio_pc___pc6___width 1
-#define reg_pinmux_rw_gio_pc___pc6___bit 6
-#define reg_pinmux_rw_gio_pc___pc7___lsb 7
-#define reg_pinmux_rw_gio_pc___pc7___width 1
-#define reg_pinmux_rw_gio_pc___pc7___bit 7
-#define reg_pinmux_rw_gio_pc___pc8___lsb 8
-#define reg_pinmux_rw_gio_pc___pc8___width 1
-#define reg_pinmux_rw_gio_pc___pc8___bit 8
-#define reg_pinmux_rw_gio_pc___pc9___lsb 9
-#define reg_pinmux_rw_gio_pc___pc9___width 1
-#define reg_pinmux_rw_gio_pc___pc9___bit 9
-#define reg_pinmux_rw_gio_pc___pc10___lsb 10
-#define reg_pinmux_rw_gio_pc___pc10___width 1
-#define reg_pinmux_rw_gio_pc___pc10___bit 10
-#define reg_pinmux_rw_gio_pc___pc11___lsb 11
-#define reg_pinmux_rw_gio_pc___pc11___width 1
-#define reg_pinmux_rw_gio_pc___pc11___bit 11
-#define reg_pinmux_rw_gio_pc___pc12___lsb 12
-#define reg_pinmux_rw_gio_pc___pc12___width 1
-#define reg_pinmux_rw_gio_pc___pc12___bit 12
-#define reg_pinmux_rw_gio_pc___pc13___lsb 13
-#define reg_pinmux_rw_gio_pc___pc13___width 1
-#define reg_pinmux_rw_gio_pc___pc13___bit 13
-#define reg_pinmux_rw_gio_pc___pc14___lsb 14
-#define reg_pinmux_rw_gio_pc___pc14___width 1
-#define reg_pinmux_rw_gio_pc___pc14___bit 14
-#define reg_pinmux_rw_gio_pc___pc15___lsb 15
-#define reg_pinmux_rw_gio_pc___pc15___width 1
-#define reg_pinmux_rw_gio_pc___pc15___bit 15
-#define reg_pinmux_rw_gio_pc_offset 12
-
-/* Register rw_iop_pa, scope pinmux, type rw */
-#define reg_pinmux_rw_iop_pa___pa0___lsb 0
-#define reg_pinmux_rw_iop_pa___pa0___width 1
-#define reg_pinmux_rw_iop_pa___pa0___bit 0
-#define reg_pinmux_rw_iop_pa___pa1___lsb 1
-#define reg_pinmux_rw_iop_pa___pa1___width 1
-#define reg_pinmux_rw_iop_pa___pa1___bit 1
-#define reg_pinmux_rw_iop_pa___pa2___lsb 2
-#define reg_pinmux_rw_iop_pa___pa2___width 1
-#define reg_pinmux_rw_iop_pa___pa2___bit 2
-#define reg_pinmux_rw_iop_pa___pa3___lsb 3
-#define reg_pinmux_rw_iop_pa___pa3___width 1
-#define reg_pinmux_rw_iop_pa___pa3___bit 3
-#define reg_pinmux_rw_iop_pa___pa4___lsb 4
-#define reg_pinmux_rw_iop_pa___pa4___width 1
-#define reg_pinmux_rw_iop_pa___pa4___bit 4
-#define reg_pinmux_rw_iop_pa___pa5___lsb 5
-#define reg_pinmux_rw_iop_pa___pa5___width 1
-#define reg_pinmux_rw_iop_pa___pa5___bit 5
-#define reg_pinmux_rw_iop_pa___pa6___lsb 6
-#define reg_pinmux_rw_iop_pa___pa6___width 1
-#define reg_pinmux_rw_iop_pa___pa6___bit 6
-#define reg_pinmux_rw_iop_pa___pa7___lsb 7
-#define reg_pinmux_rw_iop_pa___pa7___width 1
-#define reg_pinmux_rw_iop_pa___pa7___bit 7
-#define reg_pinmux_rw_iop_pa___pa8___lsb 8
-#define reg_pinmux_rw_iop_pa___pa8___width 1
-#define reg_pinmux_rw_iop_pa___pa8___bit 8
-#define reg_pinmux_rw_iop_pa___pa9___lsb 9
-#define reg_pinmux_rw_iop_pa___pa9___width 1
-#define reg_pinmux_rw_iop_pa___pa9___bit 9
-#define reg_pinmux_rw_iop_pa___pa10___lsb 10
-#define reg_pinmux_rw_iop_pa___pa10___width 1
-#define reg_pinmux_rw_iop_pa___pa10___bit 10
-#define reg_pinmux_rw_iop_pa___pa11___lsb 11
-#define reg_pinmux_rw_iop_pa___pa11___width 1
-#define reg_pinmux_rw_iop_pa___pa11___bit 11
-#define reg_pinmux_rw_iop_pa___pa12___lsb 12
-#define reg_pinmux_rw_iop_pa___pa12___width 1
-#define reg_pinmux_rw_iop_pa___pa12___bit 12
-#define reg_pinmux_rw_iop_pa___pa13___lsb 13
-#define reg_pinmux_rw_iop_pa___pa13___width 1
-#define reg_pinmux_rw_iop_pa___pa13___bit 13
-#define reg_pinmux_rw_iop_pa___pa14___lsb 14
-#define reg_pinmux_rw_iop_pa___pa14___width 1
-#define reg_pinmux_rw_iop_pa___pa14___bit 14
-#define reg_pinmux_rw_iop_pa___pa15___lsb 15
-#define reg_pinmux_rw_iop_pa___pa15___width 1
-#define reg_pinmux_rw_iop_pa___pa15___bit 15
-#define reg_pinmux_rw_iop_pa___pa16___lsb 16
-#define reg_pinmux_rw_iop_pa___pa16___width 1
-#define reg_pinmux_rw_iop_pa___pa16___bit 16
-#define reg_pinmux_rw_iop_pa___pa17___lsb 17
-#define reg_pinmux_rw_iop_pa___pa17___width 1
-#define reg_pinmux_rw_iop_pa___pa17___bit 17
-#define reg_pinmux_rw_iop_pa___pa18___lsb 18
-#define reg_pinmux_rw_iop_pa___pa18___width 1
-#define reg_pinmux_rw_iop_pa___pa18___bit 18
-#define reg_pinmux_rw_iop_pa___pa19___lsb 19
-#define reg_pinmux_rw_iop_pa___pa19___width 1
-#define reg_pinmux_rw_iop_pa___pa19___bit 19
-#define reg_pinmux_rw_iop_pa___pa20___lsb 20
-#define reg_pinmux_rw_iop_pa___pa20___width 1
-#define reg_pinmux_rw_iop_pa___pa20___bit 20
-#define reg_pinmux_rw_iop_pa___pa21___lsb 21
-#define reg_pinmux_rw_iop_pa___pa21___width 1
-#define reg_pinmux_rw_iop_pa___pa21___bit 21
-#define reg_pinmux_rw_iop_pa___pa22___lsb 22
-#define reg_pinmux_rw_iop_pa___pa22___width 1
-#define reg_pinmux_rw_iop_pa___pa22___bit 22
-#define reg_pinmux_rw_iop_pa___pa23___lsb 23
-#define reg_pinmux_rw_iop_pa___pa23___width 1
-#define reg_pinmux_rw_iop_pa___pa23___bit 23
-#define reg_pinmux_rw_iop_pa___pa24___lsb 24
-#define reg_pinmux_rw_iop_pa___pa24___width 1
-#define reg_pinmux_rw_iop_pa___pa24___bit 24
-#define reg_pinmux_rw_iop_pa___pa25___lsb 25
-#define reg_pinmux_rw_iop_pa___pa25___width 1
-#define reg_pinmux_rw_iop_pa___pa25___bit 25
-#define reg_pinmux_rw_iop_pa___pa26___lsb 26
-#define reg_pinmux_rw_iop_pa___pa26___width 1
-#define reg_pinmux_rw_iop_pa___pa26___bit 26
-#define reg_pinmux_rw_iop_pa___pa27___lsb 27
-#define reg_pinmux_rw_iop_pa___pa27___width 1
-#define reg_pinmux_rw_iop_pa___pa27___bit 27
-#define reg_pinmux_rw_iop_pa___pa28___lsb 28
-#define reg_pinmux_rw_iop_pa___pa28___width 1
-#define reg_pinmux_rw_iop_pa___pa28___bit 28
-#define reg_pinmux_rw_iop_pa___pa29___lsb 29
-#define reg_pinmux_rw_iop_pa___pa29___width 1
-#define reg_pinmux_rw_iop_pa___pa29___bit 29
-#define reg_pinmux_rw_iop_pa___pa30___lsb 30
-#define reg_pinmux_rw_iop_pa___pa30___width 1
-#define reg_pinmux_rw_iop_pa___pa30___bit 30
-#define reg_pinmux_rw_iop_pa___pa31___lsb 31
-#define reg_pinmux_rw_iop_pa___pa31___width 1
-#define reg_pinmux_rw_iop_pa___pa31___bit 31
-#define reg_pinmux_rw_iop_pa_offset 16
-
-/* Register rw_iop_pb, scope pinmux, type rw */
-#define reg_pinmux_rw_iop_pb___pb0___lsb 0
-#define reg_pinmux_rw_iop_pb___pb0___width 1
-#define reg_pinmux_rw_iop_pb___pb0___bit 0
-#define reg_pinmux_rw_iop_pb___pb1___lsb 1
-#define reg_pinmux_rw_iop_pb___pb1___width 1
-#define reg_pinmux_rw_iop_pb___pb1___bit 1
-#define reg_pinmux_rw_iop_pb___pb2___lsb 2
-#define reg_pinmux_rw_iop_pb___pb2___width 1
-#define reg_pinmux_rw_iop_pb___pb2___bit 2
-#define reg_pinmux_rw_iop_pb___pb3___lsb 3
-#define reg_pinmux_rw_iop_pb___pb3___width 1
-#define reg_pinmux_rw_iop_pb___pb3___bit 3
-#define reg_pinmux_rw_iop_pb___pb4___lsb 4
-#define reg_pinmux_rw_iop_pb___pb4___width 1
-#define reg_pinmux_rw_iop_pb___pb4___bit 4
-#define reg_pinmux_rw_iop_pb___pb5___lsb 5
-#define reg_pinmux_rw_iop_pb___pb5___width 1
-#define reg_pinmux_rw_iop_pb___pb5___bit 5
-#define reg_pinmux_rw_iop_pb___pb6___lsb 6
-#define reg_pinmux_rw_iop_pb___pb6___width 1
-#define reg_pinmux_rw_iop_pb___pb6___bit 6
-#define reg_pinmux_rw_iop_pb___pb7___lsb 7
-#define reg_pinmux_rw_iop_pb___pb7___width 1
-#define reg_pinmux_rw_iop_pb___pb7___bit 7
-#define reg_pinmux_rw_iop_pb_offset 20
-
-/* Register rw_iop_pio, scope pinmux, type rw */
-#define reg_pinmux_rw_iop_pio___d0___lsb 0
-#define reg_pinmux_rw_iop_pio___d0___width 1
-#define reg_pinmux_rw_iop_pio___d0___bit 0
-#define reg_pinmux_rw_iop_pio___d1___lsb 1
-#define reg_pinmux_rw_iop_pio___d1___width 1
-#define reg_pinmux_rw_iop_pio___d1___bit 1
-#define reg_pinmux_rw_iop_pio___d2___lsb 2
-#define reg_pinmux_rw_iop_pio___d2___width 1
-#define reg_pinmux_rw_iop_pio___d2___bit 2
-#define reg_pinmux_rw_iop_pio___d3___lsb 3
-#define reg_pinmux_rw_iop_pio___d3___width 1
-#define reg_pinmux_rw_iop_pio___d3___bit 3
-#define reg_pinmux_rw_iop_pio___d4___lsb 4
-#define reg_pinmux_rw_iop_pio___d4___width 1
-#define reg_pinmux_rw_iop_pio___d4___bit 4
-#define reg_pinmux_rw_iop_pio___d5___lsb 5
-#define reg_pinmux_rw_iop_pio___d5___width 1
-#define reg_pinmux_rw_iop_pio___d5___bit 5
-#define reg_pinmux_rw_iop_pio___d6___lsb 6
-#define reg_pinmux_rw_iop_pio___d6___width 1
-#define reg_pinmux_rw_iop_pio___d6___bit 6
-#define reg_pinmux_rw_iop_pio___d7___lsb 7
-#define reg_pinmux_rw_iop_pio___d7___width 1
-#define reg_pinmux_rw_iop_pio___d7___bit 7
-#define reg_pinmux_rw_iop_pio___rd_n___lsb 8
-#define reg_pinmux_rw_iop_pio___rd_n___width 1
-#define reg_pinmux_rw_iop_pio___rd_n___bit 8
-#define reg_pinmux_rw_iop_pio___wr_n___lsb 9
-#define reg_pinmux_rw_iop_pio___wr_n___width 1
-#define reg_pinmux_rw_iop_pio___wr_n___bit 9
-#define reg_pinmux_rw_iop_pio___a0___lsb 10
-#define reg_pinmux_rw_iop_pio___a0___width 1
-#define reg_pinmux_rw_iop_pio___a0___bit 10
-#define reg_pinmux_rw_iop_pio___a1___lsb 11
-#define reg_pinmux_rw_iop_pio___a1___width 1
-#define reg_pinmux_rw_iop_pio___a1___bit 11
-#define reg_pinmux_rw_iop_pio___ce0_n___lsb 12
-#define reg_pinmux_rw_iop_pio___ce0_n___width 1
-#define reg_pinmux_rw_iop_pio___ce0_n___bit 12
-#define reg_pinmux_rw_iop_pio___ce1_n___lsb 13
-#define reg_pinmux_rw_iop_pio___ce1_n___width 1
-#define reg_pinmux_rw_iop_pio___ce1_n___bit 13
-#define reg_pinmux_rw_iop_pio___ce2_n___lsb 14
-#define reg_pinmux_rw_iop_pio___ce2_n___width 1
-#define reg_pinmux_rw_iop_pio___ce2_n___bit 14
-#define reg_pinmux_rw_iop_pio___rdy___lsb 15
-#define reg_pinmux_rw_iop_pio___rdy___width 1
-#define reg_pinmux_rw_iop_pio___rdy___bit 15
-#define reg_pinmux_rw_iop_pio_offset 24
-
-/* Register rw_iop_usb, scope pinmux, type rw */
-#define reg_pinmux_rw_iop_usb___usb0___lsb 0
-#define reg_pinmux_rw_iop_usb___usb0___width 1
-#define reg_pinmux_rw_iop_usb___usb0___bit 0
-#define reg_pinmux_rw_iop_usb_offset 28
-
-
-/* Constants */
-#define regk_pinmux_no                            0x00000000
-#define regk_pinmux_rw_gio_pa_default             0x00000000
-#define regk_pinmux_rw_gio_pb_default             0x00000000
-#define regk_pinmux_rw_gio_pc_default             0x00000000
-#define regk_pinmux_rw_hwprot_default             0x00000000
-#define regk_pinmux_rw_iop_pa_default             0x00000000
-#define regk_pinmux_rw_iop_pb_default             0x00000000
-#define regk_pinmux_rw_iop_pio_default            0x00000000
-#define regk_pinmux_rw_iop_usb_default            0x00000001
-#define regk_pinmux_yes                           0x00000001
-#endif /* __pinmux_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h
deleted file mode 100644
index 3907ef4921c8..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h
+++ /dev/null
@@ -1,337 +0,0 @@
-#ifndef __pio_defs_asm_h
-#define __pio_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           pio.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile pio_defs_asm.h pio.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_data, scope pio, type rw */
-#define reg_pio_rw_data_offset 64
-
-/* Register rw_io_access0, scope pio, type rw */
-#define reg_pio_rw_io_access0___data___lsb 0
-#define reg_pio_rw_io_access0___data___width 8
-#define reg_pio_rw_io_access0_offset 0
-
-/* Register rw_io_access1, scope pio, type rw */
-#define reg_pio_rw_io_access1___data___lsb 0
-#define reg_pio_rw_io_access1___data___width 8
-#define reg_pio_rw_io_access1_offset 4
-
-/* Register rw_io_access2, scope pio, type rw */
-#define reg_pio_rw_io_access2___data___lsb 0
-#define reg_pio_rw_io_access2___data___width 8
-#define reg_pio_rw_io_access2_offset 8
-
-/* Register rw_io_access3, scope pio, type rw */
-#define reg_pio_rw_io_access3___data___lsb 0
-#define reg_pio_rw_io_access3___data___width 8
-#define reg_pio_rw_io_access3_offset 12
-
-/* Register rw_io_access4, scope pio, type rw */
-#define reg_pio_rw_io_access4___data___lsb 0
-#define reg_pio_rw_io_access4___data___width 8
-#define reg_pio_rw_io_access4_offset 16
-
-/* Register rw_io_access5, scope pio, type rw */
-#define reg_pio_rw_io_access5___data___lsb 0
-#define reg_pio_rw_io_access5___data___width 8
-#define reg_pio_rw_io_access5_offset 20
-
-/* Register rw_io_access6, scope pio, type rw */
-#define reg_pio_rw_io_access6___data___lsb 0
-#define reg_pio_rw_io_access6___data___width 8
-#define reg_pio_rw_io_access6_offset 24
-
-/* Register rw_io_access7, scope pio, type rw */
-#define reg_pio_rw_io_access7___data___lsb 0
-#define reg_pio_rw_io_access7___data___width 8
-#define reg_pio_rw_io_access7_offset 28
-
-/* Register rw_io_access8, scope pio, type rw */
-#define reg_pio_rw_io_access8___data___lsb 0
-#define reg_pio_rw_io_access8___data___width 8
-#define reg_pio_rw_io_access8_offset 32
-
-/* Register rw_io_access9, scope pio, type rw */
-#define reg_pio_rw_io_access9___data___lsb 0
-#define reg_pio_rw_io_access9___data___width 8
-#define reg_pio_rw_io_access9_offset 36
-
-/* Register rw_io_access10, scope pio, type rw */
-#define reg_pio_rw_io_access10___data___lsb 0
-#define reg_pio_rw_io_access10___data___width 8
-#define reg_pio_rw_io_access10_offset 40
-
-/* Register rw_io_access11, scope pio, type rw */
-#define reg_pio_rw_io_access11___data___lsb 0
-#define reg_pio_rw_io_access11___data___width 8
-#define reg_pio_rw_io_access11_offset 44
-
-/* Register rw_io_access12, scope pio, type rw */
-#define reg_pio_rw_io_access12___data___lsb 0
-#define reg_pio_rw_io_access12___data___width 8
-#define reg_pio_rw_io_access12_offset 48
-
-/* Register rw_io_access13, scope pio, type rw */
-#define reg_pio_rw_io_access13___data___lsb 0
-#define reg_pio_rw_io_access13___data___width 8
-#define reg_pio_rw_io_access13_offset 52
-
-/* Register rw_io_access14, scope pio, type rw */
-#define reg_pio_rw_io_access14___data___lsb 0
-#define reg_pio_rw_io_access14___data___width 8
-#define reg_pio_rw_io_access14_offset 56
-
-/* Register rw_io_access15, scope pio, type rw */
-#define reg_pio_rw_io_access15___data___lsb 0
-#define reg_pio_rw_io_access15___data___width 8
-#define reg_pio_rw_io_access15_offset 60
-
-/* Register rw_ce0_cfg, scope pio, type rw */
-#define reg_pio_rw_ce0_cfg___lw___lsb 0
-#define reg_pio_rw_ce0_cfg___lw___width 6
-#define reg_pio_rw_ce0_cfg___ew___lsb 6
-#define reg_pio_rw_ce0_cfg___ew___width 3
-#define reg_pio_rw_ce0_cfg___zw___lsb 9
-#define reg_pio_rw_ce0_cfg___zw___width 3
-#define reg_pio_rw_ce0_cfg___aw___lsb 12
-#define reg_pio_rw_ce0_cfg___aw___width 2
-#define reg_pio_rw_ce0_cfg___mode___lsb 14
-#define reg_pio_rw_ce0_cfg___mode___width 2
-#define reg_pio_rw_ce0_cfg_offset 68
-
-/* Register rw_ce1_cfg, scope pio, type rw */
-#define reg_pio_rw_ce1_cfg___lw___lsb 0
-#define reg_pio_rw_ce1_cfg___lw___width 6
-#define reg_pio_rw_ce1_cfg___ew___lsb 6
-#define reg_pio_rw_ce1_cfg___ew___width 3
-#define reg_pio_rw_ce1_cfg___zw___lsb 9
-#define reg_pio_rw_ce1_cfg___zw___width 3
-#define reg_pio_rw_ce1_cfg___aw___lsb 12
-#define reg_pio_rw_ce1_cfg___aw___width 2
-#define reg_pio_rw_ce1_cfg___mode___lsb 14
-#define reg_pio_rw_ce1_cfg___mode___width 2
-#define reg_pio_rw_ce1_cfg_offset 72
-
-/* Register rw_ce2_cfg, scope pio, type rw */
-#define reg_pio_rw_ce2_cfg___lw___lsb 0
-#define reg_pio_rw_ce2_cfg___lw___width 6
-#define reg_pio_rw_ce2_cfg___ew___lsb 6
-#define reg_pio_rw_ce2_cfg___ew___width 3
-#define reg_pio_rw_ce2_cfg___zw___lsb 9
-#define reg_pio_rw_ce2_cfg___zw___width 3
-#define reg_pio_rw_ce2_cfg___aw___lsb 12
-#define reg_pio_rw_ce2_cfg___aw___width 2
-#define reg_pio_rw_ce2_cfg___mode___lsb 14
-#define reg_pio_rw_ce2_cfg___mode___width 2
-#define reg_pio_rw_ce2_cfg_offset 76
-
-/* Register rw_dout, scope pio, type rw */
-#define reg_pio_rw_dout___data___lsb 0
-#define reg_pio_rw_dout___data___width 8
-#define reg_pio_rw_dout___rd_n___lsb 8
-#define reg_pio_rw_dout___rd_n___width 1
-#define reg_pio_rw_dout___rd_n___bit 8
-#define reg_pio_rw_dout___wr_n___lsb 9
-#define reg_pio_rw_dout___wr_n___width 1
-#define reg_pio_rw_dout___wr_n___bit 9
-#define reg_pio_rw_dout___a0___lsb 10
-#define reg_pio_rw_dout___a0___width 1
-#define reg_pio_rw_dout___a0___bit 10
-#define reg_pio_rw_dout___a1___lsb 11
-#define reg_pio_rw_dout___a1___width 1
-#define reg_pio_rw_dout___a1___bit 11
-#define reg_pio_rw_dout___ce0_n___lsb 12
-#define reg_pio_rw_dout___ce0_n___width 1
-#define reg_pio_rw_dout___ce0_n___bit 12
-#define reg_pio_rw_dout___ce1_n___lsb 13
-#define reg_pio_rw_dout___ce1_n___width 1
-#define reg_pio_rw_dout___ce1_n___bit 13
-#define reg_pio_rw_dout___ce2_n___lsb 14
-#define reg_pio_rw_dout___ce2_n___width 1
-#define reg_pio_rw_dout___ce2_n___bit 14
-#define reg_pio_rw_dout___rdy___lsb 15
-#define reg_pio_rw_dout___rdy___width 1
-#define reg_pio_rw_dout___rdy___bit 15
-#define reg_pio_rw_dout_offset 80
-
-/* Register rw_oe, scope pio, type rw */
-#define reg_pio_rw_oe___data___lsb 0
-#define reg_pio_rw_oe___data___width 8
-#define reg_pio_rw_oe___rd_n___lsb 8
-#define reg_pio_rw_oe___rd_n___width 1
-#define reg_pio_rw_oe___rd_n___bit 8
-#define reg_pio_rw_oe___wr_n___lsb 9
-#define reg_pio_rw_oe___wr_n___width 1
-#define reg_pio_rw_oe___wr_n___bit 9
-#define reg_pio_rw_oe___a0___lsb 10
-#define reg_pio_rw_oe___a0___width 1
-#define reg_pio_rw_oe___a0___bit 10
-#define reg_pio_rw_oe___a1___lsb 11
-#define reg_pio_rw_oe___a1___width 1
-#define reg_pio_rw_oe___a1___bit 11
-#define reg_pio_rw_oe___ce0_n___lsb 12
-#define reg_pio_rw_oe___ce0_n___width 1
-#define reg_pio_rw_oe___ce0_n___bit 12
-#define reg_pio_rw_oe___ce1_n___lsb 13
-#define reg_pio_rw_oe___ce1_n___width 1
-#define reg_pio_rw_oe___ce1_n___bit 13
-#define reg_pio_rw_oe___ce2_n___lsb 14
-#define reg_pio_rw_oe___ce2_n___width 1
-#define reg_pio_rw_oe___ce2_n___bit 14
-#define reg_pio_rw_oe___rdy___lsb 15
-#define reg_pio_rw_oe___rdy___width 1
-#define reg_pio_rw_oe___rdy___bit 15
-#define reg_pio_rw_oe_offset 84
-
-/* Register rw_man_ctrl, scope pio, type rw */
-#define reg_pio_rw_man_ctrl___data___lsb 0
-#define reg_pio_rw_man_ctrl___data___width 8
-#define reg_pio_rw_man_ctrl___rd_n___lsb 8
-#define reg_pio_rw_man_ctrl___rd_n___width 1
-#define reg_pio_rw_man_ctrl___rd_n___bit 8
-#define reg_pio_rw_man_ctrl___wr_n___lsb 9
-#define reg_pio_rw_man_ctrl___wr_n___width 1
-#define reg_pio_rw_man_ctrl___wr_n___bit 9
-#define reg_pio_rw_man_ctrl___a0___lsb 10
-#define reg_pio_rw_man_ctrl___a0___width 1
-#define reg_pio_rw_man_ctrl___a0___bit 10
-#define reg_pio_rw_man_ctrl___a1___lsb 11
-#define reg_pio_rw_man_ctrl___a1___width 1
-#define reg_pio_rw_man_ctrl___a1___bit 11
-#define reg_pio_rw_man_ctrl___ce0_n___lsb 12
-#define reg_pio_rw_man_ctrl___ce0_n___width 1
-#define reg_pio_rw_man_ctrl___ce0_n___bit 12
-#define reg_pio_rw_man_ctrl___ce1_n___lsb 13
-#define reg_pio_rw_man_ctrl___ce1_n___width 1
-#define reg_pio_rw_man_ctrl___ce1_n___bit 13
-#define reg_pio_rw_man_ctrl___ce2_n___lsb 14
-#define reg_pio_rw_man_ctrl___ce2_n___width 1
-#define reg_pio_rw_man_ctrl___ce2_n___bit 14
-#define reg_pio_rw_man_ctrl___rdy___lsb 15
-#define reg_pio_rw_man_ctrl___rdy___width 1
-#define reg_pio_rw_man_ctrl___rdy___bit 15
-#define reg_pio_rw_man_ctrl_offset 88
-
-/* Register r_din, scope pio, type r */
-#define reg_pio_r_din___data___lsb 0
-#define reg_pio_r_din___data___width 8
-#define reg_pio_r_din___rd_n___lsb 8
-#define reg_pio_r_din___rd_n___width 1
-#define reg_pio_r_din___rd_n___bit 8
-#define reg_pio_r_din___wr_n___lsb 9
-#define reg_pio_r_din___wr_n___width 1
-#define reg_pio_r_din___wr_n___bit 9
-#define reg_pio_r_din___a0___lsb 10
-#define reg_pio_r_din___a0___width 1
-#define reg_pio_r_din___a0___bit 10
-#define reg_pio_r_din___a1___lsb 11
-#define reg_pio_r_din___a1___width 1
-#define reg_pio_r_din___a1___bit 11
-#define reg_pio_r_din___ce0_n___lsb 12
-#define reg_pio_r_din___ce0_n___width 1
-#define reg_pio_r_din___ce0_n___bit 12
-#define reg_pio_r_din___ce1_n___lsb 13
-#define reg_pio_r_din___ce1_n___width 1
-#define reg_pio_r_din___ce1_n___bit 13
-#define reg_pio_r_din___ce2_n___lsb 14
-#define reg_pio_r_din___ce2_n___width 1
-#define reg_pio_r_din___ce2_n___bit 14
-#define reg_pio_r_din___rdy___lsb 15
-#define reg_pio_r_din___rdy___width 1
-#define reg_pio_r_din___rdy___bit 15
-#define reg_pio_r_din_offset 92
-
-/* Register r_stat, scope pio, type r */
-#define reg_pio_r_stat___busy___lsb 0
-#define reg_pio_r_stat___busy___width 1
-#define reg_pio_r_stat___busy___bit 0
-#define reg_pio_r_stat_offset 96
-
-/* Register rw_intr_mask, scope pio, type rw */
-#define reg_pio_rw_intr_mask___rdy___lsb 0
-#define reg_pio_rw_intr_mask___rdy___width 1
-#define reg_pio_rw_intr_mask___rdy___bit 0
-#define reg_pio_rw_intr_mask_offset 100
-
-/* Register rw_ack_intr, scope pio, type rw */
-#define reg_pio_rw_ack_intr___rdy___lsb 0
-#define reg_pio_rw_ack_intr___rdy___width 1
-#define reg_pio_rw_ack_intr___rdy___bit 0
-#define reg_pio_rw_ack_intr_offset 104
-
-/* Register r_intr, scope pio, type r */
-#define reg_pio_r_intr___rdy___lsb 0
-#define reg_pio_r_intr___rdy___width 1
-#define reg_pio_r_intr___rdy___bit 0
-#define reg_pio_r_intr_offset 108
-
-/* Register r_masked_intr, scope pio, type r */
-#define reg_pio_r_masked_intr___rdy___lsb 0
-#define reg_pio_r_masked_intr___rdy___width 1
-#define reg_pio_r_masked_intr___rdy___bit 0
-#define reg_pio_r_masked_intr_offset 112
-
-
-/* Constants */
-#define regk_pio_a2                               0x00000003
-#define regk_pio_no                               0x00000000
-#define regk_pio_normal                           0x00000000
-#define regk_pio_rd                               0x00000001
-#define regk_pio_rw_ce0_cfg_default               0x00000000
-#define regk_pio_rw_ce1_cfg_default               0x00000000
-#define regk_pio_rw_ce2_cfg_default               0x00000000
-#define regk_pio_rw_intr_mask_default             0x00000000
-#define regk_pio_rw_man_ctrl_default              0x00000000
-#define regk_pio_rw_oe_default                    0x00000000
-#define regk_pio_wr                               0x00000002
-#define regk_pio_wr_ce2                           0x00000003
-#define regk_pio_yes                              0x00000001
-#define regk_pio_yes_all                          0x000000ff
-#endif /* __pio_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h
deleted file mode 100644
index 89439e9610e2..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h
+++ /dev/null
@@ -1,99 +0,0 @@
-#ifndef __reg_map_asm_h
-#define __reg_map_asm_h
-
-/*
- * This file is autogenerated from
- *   file:            reg.rmap
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -asm -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map_asm.h reg.rmap
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-#define regi_ccd                                  0xb0000000
-#define regi_ccd_top                              0xb0000000
-#define regi_ccd_dp                               0xb0000400
-#define regi_ccd_stat                             0xb0000800
-#define regi_ccd_tg                               0xb0001000
-#define regi_cfg                                  0xb0002000
-#define regi_clkgen                               0xb0004000
-#define regi_ddr2_ctrl                            0xb0006000
-#define regi_dma0                                 0xb0008000
-#define regi_dma1                                 0xb000a000
-#define regi_dma11                                0xb000c000
-#define regi_dma2                                 0xb000e000
-#define regi_dma3                                 0xb0010000
-#define regi_dma4                                 0xb0012000
-#define regi_dma5                                 0xb0014000
-#define regi_dma6                                 0xb0016000
-#define regi_dma7                                 0xb0018000
-#define regi_dma9                                 0xb001a000
-#define regi_eth                                  0xb001c000
-#define regi_gio                                  0xb0020000
-#define regi_h264                                 0xb0022000
-#define regi_hist                                 0xb0026000
-#define regi_iop                                  0xb0028000
-#define regi_iop_version                          0xb0028000
-#define regi_iop_fifo_in_extra                    0xb0028040
-#define regi_iop_fifo_out_extra                   0xb0028080
-#define regi_iop_trigger_grp0                     0xb00280c0
-#define regi_iop_trigger_grp1                     0xb0028100
-#define regi_iop_trigger_grp2                     0xb0028140
-#define regi_iop_trigger_grp3                     0xb0028180
-#define regi_iop_trigger_grp4                     0xb00281c0
-#define regi_iop_trigger_grp5                     0xb0028200
-#define regi_iop_trigger_grp6                     0xb0028240
-#define regi_iop_trigger_grp7                     0xb0028280
-#define regi_iop_crc_par                          0xb0028300
-#define regi_iop_dmc_in                           0xb0028380
-#define regi_iop_dmc_out                          0xb0028400
-#define regi_iop_fifo_in                          0xb0028480
-#define regi_iop_fifo_out                         0xb0028500
-#define regi_iop_scrc_in                          0xb0028580
-#define regi_iop_scrc_out                         0xb0028600
-#define regi_iop_timer_grp0                       0xb0028680
-#define regi_iop_timer_grp1                       0xb0028700
-#define regi_iop_sap_in                           0xb0028800
-#define regi_iop_sap_out                          0xb0028900
-#define regi_iop_spu                              0xb0028a00
-#define regi_iop_sw_cfg                           0xb0028b00
-#define regi_iop_sw_cpu                           0xb0028c00
-#define regi_iop_sw_mpu                           0xb0028d00
-#define regi_iop_sw_spu                           0xb0028e00
-#define regi_iop_mpu                              0xb0029000
-#define regi_irq                                  0xb002a000
-#define regi_jpeg                                 0xb002c000
-#define regi_l2cache                              0xb0030000
-#define regi_marb_bar                             0xb0032000
-#define regi_marb_bar_bp0                         0xb0032140
-#define regi_marb_bar_bp1                         0xb0032180
-#define regi_marb_bar_bp2                         0xb00321c0
-#define regi_marb_bar_bp3                         0xb0032200
-#define regi_marb_foo                             0xb0034000
-#define regi_marb_foo_bp0                         0xb0034280
-#define regi_marb_foo_bp1                         0xb00342c0
-#define regi_marb_foo_bp2                         0xb0034300
-#define regi_marb_foo_bp3                         0xb0034340
-#define regi_pinmux                               0xb0038000
-#define regi_pio                                  0xb0036000
-#define regi_sclr                                 0xb003a000
-#define regi_sclr_fifo                            0xb003c000
-#define regi_ser0                                 0xb003e000
-#define regi_ser1                                 0xb0040000
-#define regi_ser2                                 0xb0042000
-#define regi_ser3                                 0xb0044000
-#define regi_ser4                                 0xb0046000
-#define regi_sser                                 0xb0048000
-#define regi_strcop                               0xb004a000
-#define regi_strdma0                              0xb004e000
-#define regi_strdma1                              0xb0050000
-#define regi_strdma2                              0xb0052000
-#define regi_strdma3                              0xb0054000
-#define regi_strdma5                              0xb0056000
-#define regi_strmux                               0xb004c000
-#define regi_timer0                               0xb0058000
-#define regi_timer1                               0xb005a000
-#define regi_trace                                0xb005c000
-#define regi_vin                                  0xb005e000
-#define regi_vout                                 0xb0060000
-#endif /* __reg_map_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h
deleted file mode 100644
index b129e826fc34..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h
+++ /dev/null
@@ -1,228 +0,0 @@
-#ifndef __timer_defs_asm_h
-#define __timer_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           timer.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_tmr0_div, scope timer, type rw */
-#define reg_timer_rw_tmr0_div_offset 0
-
-/* Register r_tmr0_data, scope timer, type r */
-#define reg_timer_r_tmr0_data_offset 4
-
-/* Register rw_tmr0_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr0_ctrl___op___lsb 0
-#define reg_timer_rw_tmr0_ctrl___op___width 2
-#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr0_ctrl___freq___width 3
-#define reg_timer_rw_tmr0_ctrl_offset 8
-
-/* Register rw_tmr1_div, scope timer, type rw */
-#define reg_timer_rw_tmr1_div_offset 16
-
-/* Register r_tmr1_data, scope timer, type r */
-#define reg_timer_r_tmr1_data_offset 20
-
-/* Register rw_tmr1_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr1_ctrl___op___lsb 0
-#define reg_timer_rw_tmr1_ctrl___op___width 2
-#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr1_ctrl___freq___width 3
-#define reg_timer_rw_tmr1_ctrl_offset 24
-
-/* Register rs_cnt_data, scope timer, type rs */
-#define reg_timer_rs_cnt_data___tmr___lsb 0
-#define reg_timer_rs_cnt_data___tmr___width 24
-#define reg_timer_rs_cnt_data___cnt___lsb 24
-#define reg_timer_rs_cnt_data___cnt___width 8
-#define reg_timer_rs_cnt_data_offset 32
-
-/* Register r_cnt_data, scope timer, type r */
-#define reg_timer_r_cnt_data___tmr___lsb 0
-#define reg_timer_r_cnt_data___tmr___width 24
-#define reg_timer_r_cnt_data___cnt___lsb 24
-#define reg_timer_r_cnt_data___cnt___width 8
-#define reg_timer_r_cnt_data_offset 36
-
-/* Register rw_cnt_cfg, scope timer, type rw */
-#define reg_timer_rw_cnt_cfg___clk___lsb 0
-#define reg_timer_rw_cnt_cfg___clk___width 2
-#define reg_timer_rw_cnt_cfg_offset 40
-
-/* Register rw_trig, scope timer, type rw */
-#define reg_timer_rw_trig_offset 48
-
-/* Register rw_trig_cfg, scope timer, type rw */
-#define reg_timer_rw_trig_cfg___tmr___lsb 0
-#define reg_timer_rw_trig_cfg___tmr___width 2
-#define reg_timer_rw_trig_cfg_offset 52
-
-/* Register r_time, scope timer, type r */
-#define reg_timer_r_time_offset 56
-
-/* Register rw_out, scope timer, type rw */
-#define reg_timer_rw_out___tmr___lsb 0
-#define reg_timer_rw_out___tmr___width 2
-#define reg_timer_rw_out_offset 60
-
-/* Register rw_wd_ctrl, scope timer, type rw */
-#define reg_timer_rw_wd_ctrl___cnt___lsb 0
-#define reg_timer_rw_wd_ctrl___cnt___width 8
-#define reg_timer_rw_wd_ctrl___cmd___lsb 8
-#define reg_timer_rw_wd_ctrl___cmd___width 1
-#define reg_timer_rw_wd_ctrl___cmd___bit 8
-#define reg_timer_rw_wd_ctrl___key___lsb 9
-#define reg_timer_rw_wd_ctrl___key___width 7
-#define reg_timer_rw_wd_ctrl_offset 64
-
-/* Register r_wd_stat, scope timer, type r */
-#define reg_timer_r_wd_stat___cnt___lsb 0
-#define reg_timer_r_wd_stat___cnt___width 8
-#define reg_timer_r_wd_stat___cmd___lsb 8
-#define reg_timer_r_wd_stat___cmd___width 1
-#define reg_timer_r_wd_stat___cmd___bit 8
-#define reg_timer_r_wd_stat_offset 68
-
-/* Register rw_intr_mask, scope timer, type rw */
-#define reg_timer_rw_intr_mask___tmr0___lsb 0
-#define reg_timer_rw_intr_mask___tmr0___width 1
-#define reg_timer_rw_intr_mask___tmr0___bit 0
-#define reg_timer_rw_intr_mask___tmr1___lsb 1
-#define reg_timer_rw_intr_mask___tmr1___width 1
-#define reg_timer_rw_intr_mask___tmr1___bit 1
-#define reg_timer_rw_intr_mask___cnt___lsb 2
-#define reg_timer_rw_intr_mask___cnt___width 1
-#define reg_timer_rw_intr_mask___cnt___bit 2
-#define reg_timer_rw_intr_mask___trig___lsb 3
-#define reg_timer_rw_intr_mask___trig___width 1
-#define reg_timer_rw_intr_mask___trig___bit 3
-#define reg_timer_rw_intr_mask_offset 72
-
-/* Register rw_ack_intr, scope timer, type rw */
-#define reg_timer_rw_ack_intr___tmr0___lsb 0
-#define reg_timer_rw_ack_intr___tmr0___width 1
-#define reg_timer_rw_ack_intr___tmr0___bit 0
-#define reg_timer_rw_ack_intr___tmr1___lsb 1
-#define reg_timer_rw_ack_intr___tmr1___width 1
-#define reg_timer_rw_ack_intr___tmr1___bit 1
-#define reg_timer_rw_ack_intr___cnt___lsb 2
-#define reg_timer_rw_ack_intr___cnt___width 1
-#define reg_timer_rw_ack_intr___cnt___bit 2
-#define reg_timer_rw_ack_intr___trig___lsb 3
-#define reg_timer_rw_ack_intr___trig___width 1
-#define reg_timer_rw_ack_intr___trig___bit 3
-#define reg_timer_rw_ack_intr_offset 76
-
-/* Register r_intr, scope timer, type r */
-#define reg_timer_r_intr___tmr0___lsb 0
-#define reg_timer_r_intr___tmr0___width 1
-#define reg_timer_r_intr___tmr0___bit 0
-#define reg_timer_r_intr___tmr1___lsb 1
-#define reg_timer_r_intr___tmr1___width 1
-#define reg_timer_r_intr___tmr1___bit 1
-#define reg_timer_r_intr___cnt___lsb 2
-#define reg_timer_r_intr___cnt___width 1
-#define reg_timer_r_intr___cnt___bit 2
-#define reg_timer_r_intr___trig___lsb 3
-#define reg_timer_r_intr___trig___width 1
-#define reg_timer_r_intr___trig___bit 3
-#define reg_timer_r_intr_offset 80
-
-/* Register r_masked_intr, scope timer, type r */
-#define reg_timer_r_masked_intr___tmr0___lsb 0
-#define reg_timer_r_masked_intr___tmr0___width 1
-#define reg_timer_r_masked_intr___tmr0___bit 0
-#define reg_timer_r_masked_intr___tmr1___lsb 1
-#define reg_timer_r_masked_intr___tmr1___width 1
-#define reg_timer_r_masked_intr___tmr1___bit 1
-#define reg_timer_r_masked_intr___cnt___lsb 2
-#define reg_timer_r_masked_intr___cnt___width 1
-#define reg_timer_r_masked_intr___cnt___bit 2
-#define reg_timer_r_masked_intr___trig___lsb 3
-#define reg_timer_r_masked_intr___trig___width 1
-#define reg_timer_r_masked_intr___trig___bit 3
-#define reg_timer_r_masked_intr_offset 84
-
-/* Register rw_test, scope timer, type rw */
-#define reg_timer_rw_test___dis___lsb 0
-#define reg_timer_rw_test___dis___width 1
-#define reg_timer_rw_test___dis___bit 0
-#define reg_timer_rw_test___en___lsb 1
-#define reg_timer_rw_test___en___width 1
-#define reg_timer_rw_test___en___bit 1
-#define reg_timer_rw_test_offset 88
-
-
-/* Constants */
-#define regk_timer_ext                            0x00000001
-#define regk_timer_f100                           0x00000007
-#define regk_timer_f29_493                        0x00000004
-#define regk_timer_f32                            0x00000005
-#define regk_timer_f32_768                        0x00000006
-#define regk_timer_f90                            0x00000003
-#define regk_timer_hold                           0x00000001
-#define regk_timer_ld                             0x00000000
-#define regk_timer_no                             0x00000000
-#define regk_timer_off                            0x00000000
-#define regk_timer_run                            0x00000002
-#define regk_timer_rw_cnt_cfg_default             0x00000000
-#define regk_timer_rw_intr_mask_default           0x00000000
-#define regk_timer_rw_out_default                 0x00000000
-#define regk_timer_rw_test_default                0x00000000
-#define regk_timer_rw_tmr0_ctrl_default           0x00000000
-#define regk_timer_rw_tmr1_ctrl_default           0x00000000
-#define regk_timer_rw_trig_cfg_default            0x00000000
-#define regk_timer_start                          0x00000001
-#define regk_timer_stop                           0x00000000
-#define regk_timer_time                           0x00000001
-#define regk_timer_tmr0                           0x00000002
-#define regk_timer_tmr1                           0x00000003
-#define regk_timer_vclk                           0x00000002
-#define regk_timer_yes                            0x00000001
-#endif /* __timer_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h
deleted file mode 100644
index c1e9ba93b3a3..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h
+++ /dev/null
@@ -1,159 +0,0 @@
-#ifndef __clkgen_defs_h
-#define __clkgen_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           clkgen.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope clkgen */
-
-/* Register r_bootsel, scope clkgen, type r */
-typedef struct {
-  unsigned int boot_mode       : 5;
-  unsigned int intern_main_clk : 1;
-  unsigned int extern_usb2_clk : 1;
-  unsigned int dummy1          : 25;
-} reg_clkgen_r_bootsel;
-#define REG_RD_ADDR_clkgen_r_bootsel 0
-
-/* Register rw_clk_ctrl, scope clkgen, type rw */
-typedef struct {
-  unsigned int pll             : 1;
-  unsigned int cpu             : 1;
-  unsigned int iop_usb         : 1;
-  unsigned int vin             : 1;
-  unsigned int sclr            : 1;
-  unsigned int h264            : 1;
-  unsigned int ddr2            : 1;
-  unsigned int vout_hist       : 1;
-  unsigned int eth             : 1;
-  unsigned int ccd_tg_200      : 1;
-  unsigned int dma0_1_eth      : 1;
-  unsigned int ccd_tg_100      : 1;
-  unsigned int jpeg            : 1;
-  unsigned int sser_ser_dma6_7 : 1;
-  unsigned int strdma0_2_video : 1;
-  unsigned int dma2_3_strcop   : 1;
-  unsigned int dma4_5_iop      : 1;
-  unsigned int dma9_11         : 1;
-  unsigned int memarb_bar_ddr  : 1;
-  unsigned int sclr_h264       : 1;
-  unsigned int dummy1          : 12;
-} reg_clkgen_rw_clk_ctrl;
-#define REG_RD_ADDR_clkgen_rw_clk_ctrl 4
-#define REG_WR_ADDR_clkgen_rw_clk_ctrl 4
-
-
-/* Constants */
-enum {
-  regk_clkgen_eth1000_rx                   = 0x0000000c,
-  regk_clkgen_eth1000_tx                   = 0x0000000e,
-  regk_clkgen_eth100_rx                    = 0x0000001d,
-  regk_clkgen_eth100_rx_half               = 0x0000001c,
-  regk_clkgen_eth100_tx                    = 0x0000001f,
-  regk_clkgen_eth100_tx_half               = 0x0000001e,
-  regk_clkgen_nand_3_2                     = 0x00000000,
-  regk_clkgen_nand_3_2_0x30                = 0x00000002,
-  regk_clkgen_nand_3_2_0x30_pll            = 0x00000012,
-  regk_clkgen_nand_3_2_pll                 = 0x00000010,
-  regk_clkgen_nand_3_3                     = 0x00000001,
-  regk_clkgen_nand_3_3_0x30                = 0x00000003,
-  regk_clkgen_nand_3_3_0x30_pll            = 0x00000013,
-  regk_clkgen_nand_3_3_pll                 = 0x00000011,
-  regk_clkgen_nand_4_2                     = 0x00000004,
-  regk_clkgen_nand_4_2_0x30                = 0x00000006,
-  regk_clkgen_nand_4_2_0x30_pll            = 0x00000016,
-  regk_clkgen_nand_4_2_pll                 = 0x00000014,
-  regk_clkgen_nand_4_3                     = 0x00000005,
-  regk_clkgen_nand_4_3_0x30                = 0x00000007,
-  regk_clkgen_nand_4_3_0x30_pll            = 0x00000017,
-  regk_clkgen_nand_4_3_pll                 = 0x00000015,
-  regk_clkgen_nand_5_2                     = 0x00000008,
-  regk_clkgen_nand_5_2_0x30                = 0x0000000a,
-  regk_clkgen_nand_5_2_0x30_pll            = 0x0000001a,
-  regk_clkgen_nand_5_2_pll                 = 0x00000018,
-  regk_clkgen_nand_5_3                     = 0x00000009,
-  regk_clkgen_nand_5_3_0x30                = 0x0000000b,
-  regk_clkgen_nand_5_3_0x30_pll            = 0x0000001b,
-  regk_clkgen_nand_5_3_pll                 = 0x00000019,
-  regk_clkgen_no                           = 0x00000000,
-  regk_clkgen_rw_clk_ctrl_default          = 0x00000002,
-  regk_clkgen_ser                          = 0x0000000d,
-  regk_clkgen_ser_pll                      = 0x0000000f,
-  regk_clkgen_yes                          = 0x00000001
-};
-#endif /* __clkgen_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h
deleted file mode 100644
index 0f30e8bf946d..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h
+++ /dev/null
@@ -1,281 +0,0 @@
-#ifndef __ddr2_defs_h
-#define __ddr2_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ddr2.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope ddr2 */
-
-/* Register rw_cfg, scope ddr2, type rw */
-typedef struct {
-  unsigned int col_width        : 4;
-  unsigned int nr_banks         : 1;
-  unsigned int bw               : 1;
-  unsigned int nr_ref           : 4;
-  unsigned int ref_interval     : 11;
-  unsigned int odt_ctrl         : 2;
-  unsigned int odt_mem          : 1;
-  unsigned int imp_strength     : 1;
-  unsigned int auto_imp_cal     : 1;
-  unsigned int imp_cal_override : 1;
-  unsigned int dll_override     : 1;
-  unsigned int dummy1           : 4;
-} reg_ddr2_rw_cfg;
-#define REG_RD_ADDR_ddr2_rw_cfg 0
-#define REG_WR_ADDR_ddr2_rw_cfg 0
-
-/* Register rw_timing, scope ddr2, type rw */
-typedef struct {
-  unsigned int wr  : 3;
-  unsigned int rcd : 3;
-  unsigned int rp  : 3;
-  unsigned int ras : 4;
-  unsigned int rfc : 7;
-  unsigned int rc  : 5;
-  unsigned int rtp : 2;
-  unsigned int rtw : 3;
-  unsigned int wtr : 2;
-} reg_ddr2_rw_timing;
-#define REG_RD_ADDR_ddr2_rw_timing 4
-#define REG_WR_ADDR_ddr2_rw_timing 4
-
-/* Register rw_latency, scope ddr2, type rw */
-typedef struct {
-  unsigned int cas      : 3;
-  unsigned int additive : 3;
-  unsigned int dummy1   : 26;
-} reg_ddr2_rw_latency;
-#define REG_RD_ADDR_ddr2_rw_latency 8
-#define REG_WR_ADDR_ddr2_rw_latency 8
-
-/* Register rw_phy_cfg, scope ddr2, type rw */
-typedef struct {
-  unsigned int en : 1;
-  unsigned int dummy1 : 31;
-} reg_ddr2_rw_phy_cfg;
-#define REG_RD_ADDR_ddr2_rw_phy_cfg 12
-#define REG_WR_ADDR_ddr2_rw_phy_cfg 12
-
-/* Register rw_phy_ctrl, scope ddr2, type rw */
-typedef struct {
-  unsigned int rst       : 1;
-  unsigned int cal_rst   : 1;
-  unsigned int cal_start : 1;
-  unsigned int dummy1    : 29;
-} reg_ddr2_rw_phy_ctrl;
-#define REG_RD_ADDR_ddr2_rw_phy_ctrl 16
-#define REG_WR_ADDR_ddr2_rw_phy_ctrl 16
-
-/* Register rw_ctrl, scope ddr2, type rw */
-typedef struct {
-  unsigned int mrs_data : 16;
-  unsigned int cmd      : 8;
-  unsigned int dummy1   : 8;
-} reg_ddr2_rw_ctrl;
-#define REG_RD_ADDR_ddr2_rw_ctrl 20
-#define REG_WR_ADDR_ddr2_rw_ctrl 20
-
-/* Register rw_pwr_down, scope ddr2, type rw */
-typedef struct {
-  unsigned int self_ref : 2;
-  unsigned int phy_en   : 1;
-  unsigned int dummy1   : 29;
-} reg_ddr2_rw_pwr_down;
-#define REG_RD_ADDR_ddr2_rw_pwr_down 24
-#define REG_WR_ADDR_ddr2_rw_pwr_down 24
-
-/* Register r_stat, scope ddr2, type r */
-typedef struct {
-  unsigned int dll_lock       : 1;
-  unsigned int dll_delay_code : 7;
-  unsigned int imp_cal_done   : 1;
-  unsigned int imp_cal_fault  : 1;
-  unsigned int cal_imp_pu     : 4;
-  unsigned int cal_imp_pd     : 4;
-  unsigned int dummy1         : 14;
-} reg_ddr2_r_stat;
-#define REG_RD_ADDR_ddr2_r_stat 28
-
-/* Register rw_imp_ctrl, scope ddr2, type rw */
-typedef struct {
-  unsigned int imp_pu : 4;
-  unsigned int imp_pd : 4;
-  unsigned int dummy1 : 24;
-} reg_ddr2_rw_imp_ctrl;
-#define REG_RD_ADDR_ddr2_rw_imp_ctrl 32
-#define REG_WR_ADDR_ddr2_rw_imp_ctrl 32
-
-#define STRIDE_ddr2_rw_dll_ctrl 4
-/* Register rw_dll_ctrl, scope ddr2, type rw */
-typedef struct {
-  unsigned int mode      : 1;
-  unsigned int clk_delay : 7;
-  unsigned int dummy1    : 24;
-} reg_ddr2_rw_dll_ctrl;
-#define REG_RD_ADDR_ddr2_rw_dll_ctrl 36
-#define REG_WR_ADDR_ddr2_rw_dll_ctrl 36
-
-#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
-/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
-typedef struct {
-  unsigned int dqs90_delay  : 7;
-  unsigned int dqs180_delay : 7;
-  unsigned int dqs270_delay : 7;
-  unsigned int dqs360_delay : 7;
-  unsigned int dummy1       : 4;
-} reg_ddr2_rw_dqs_dll_ctrl;
-#define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52
-#define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52
-
-
-/* Constants */
-enum {
-  regk_ddr2_al0                            = 0x00000000,
-  regk_ddr2_al1                            = 0x00000008,
-  regk_ddr2_al2                            = 0x00000010,
-  regk_ddr2_al3                            = 0x00000018,
-  regk_ddr2_al4                            = 0x00000020,
-  regk_ddr2_auto                           = 0x00000003,
-  regk_ddr2_bank4                          = 0x00000000,
-  regk_ddr2_bank8                          = 0x00000001,
-  regk_ddr2_bl4                            = 0x00000002,
-  regk_ddr2_bl8                            = 0x00000003,
-  regk_ddr2_bt_il                          = 0x00000008,
-  regk_ddr2_bt_seq                         = 0x00000000,
-  regk_ddr2_bw16                           = 0x00000001,
-  regk_ddr2_bw32                           = 0x00000000,
-  regk_ddr2_cas2                           = 0x00000020,
-  regk_ddr2_cas3                           = 0x00000030,
-  regk_ddr2_cas4                           = 0x00000040,
-  regk_ddr2_cas5                           = 0x00000050,
-  regk_ddr2_deselect                       = 0x000000c0,
-  regk_ddr2_dic_weak                       = 0x00000002,
-  regk_ddr2_direct                         = 0x00000001,
-  regk_ddr2_dis                            = 0x00000000,
-  regk_ddr2_dll_dis                        = 0x00000001,
-  regk_ddr2_dll_en                         = 0x00000000,
-  regk_ddr2_dll_rst                        = 0x00000100,
-  regk_ddr2_emrs                           = 0x00000081,
-  regk_ddr2_emrs2                          = 0x00000082,
-  regk_ddr2_emrs3                          = 0x00000083,
-  regk_ddr2_full                           = 0x00000001,
-  regk_ddr2_hi_ref_rate                    = 0x00000080,
-  regk_ddr2_mrs                            = 0x00000080,
-  regk_ddr2_no                             = 0x00000000,
-  regk_ddr2_nop                            = 0x000000b8,
-  regk_ddr2_ocd_adj                        = 0x00000200,
-  regk_ddr2_ocd_default                    = 0x00000380,
-  regk_ddr2_ocd_drive0                     = 0x00000100,
-  regk_ddr2_ocd_drive1                     = 0x00000080,
-  regk_ddr2_ocd_exit                       = 0x00000000,
-  regk_ddr2_odt_dis                        = 0x00000000,
-  regk_ddr2_offs                           = 0x00000000,
-  regk_ddr2_pre                            = 0x00000090,
-  regk_ddr2_pre_all                        = 0x00000400,
-  regk_ddr2_pwr_down_fast                  = 0x00000000,
-  regk_ddr2_pwr_down_slow                  = 0x00001000,
-  regk_ddr2_ref                            = 0x00000088,
-  regk_ddr2_rtt150                         = 0x00000040,
-  regk_ddr2_rtt50                          = 0x00000044,
-  regk_ddr2_rtt75                          = 0x00000004,
-  regk_ddr2_rw_cfg_default                 = 0x00186000,
-  regk_ddr2_rw_dll_ctrl_default            = 0x00000000,
-  regk_ddr2_rw_dll_ctrl_size               = 0x00000004,
-  regk_ddr2_rw_dqs_dll_ctrl_default        = 0x00000000,
-  regk_ddr2_rw_dqs_dll_ctrl_size           = 0x00000004,
-  regk_ddr2_rw_latency_default             = 0x00000000,
-  regk_ddr2_rw_phy_cfg_default             = 0x00000000,
-  regk_ddr2_rw_pwr_down_default            = 0x00000000,
-  regk_ddr2_rw_timing_default              = 0x00000000,
-  regk_ddr2_s1Gb                           = 0x0000001a,
-  regk_ddr2_s256Mb                         = 0x0000000f,
-  regk_ddr2_s2Gb                           = 0x00000027,
-  regk_ddr2_s4Gb                           = 0x00000042,
-  regk_ddr2_s512Mb                         = 0x00000015,
-  regk_ddr2_temp0_85                       = 0x00000618,
-  regk_ddr2_temp85_95                      = 0x0000030c,
-  regk_ddr2_term150                        = 0x00000002,
-  regk_ddr2_term50                         = 0x00000003,
-  regk_ddr2_term75                         = 0x00000001,
-  regk_ddr2_test                           = 0x00000080,
-  regk_ddr2_weak                           = 0x00000000,
-  regk_ddr2_wr2                            = 0x00000200,
-  regk_ddr2_wr3                            = 0x00000400,
-  regk_ddr2_yes                            = 0x00000001
-};
-#endif /* __ddr2_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h
deleted file mode 100644
index 5d88e0db23ae..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h
+++ /dev/null
@@ -1,837 +0,0 @@
-#ifndef __gio_defs_h
-#define __gio_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           gio.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope gio */
-
-/* Register r_pa_din, scope gio, type r */
-typedef struct {
-  unsigned int data : 32;
-} reg_gio_r_pa_din;
-#define REG_RD_ADDR_gio_r_pa_din 0
-
-/* Register rw_pa_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 32;
-} reg_gio_rw_pa_dout;
-#define REG_RD_ADDR_gio_rw_pa_dout 4
-#define REG_WR_ADDR_gio_rw_pa_dout 4
-
-/* Register rw_pa_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 32;
-} reg_gio_rw_pa_oe;
-#define REG_RD_ADDR_gio_rw_pa_oe 8
-#define REG_WR_ADDR_gio_rw_pa_oe 8
-
-/* Register rw_pa_byte0_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte0_dout;
-#define REG_RD_ADDR_gio_rw_pa_byte0_dout 12
-#define REG_WR_ADDR_gio_rw_pa_byte0_dout 12
-
-/* Register rw_pa_byte0_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte0_oe;
-#define REG_RD_ADDR_gio_rw_pa_byte0_oe 16
-#define REG_WR_ADDR_gio_rw_pa_byte0_oe 16
-
-/* Register rw_pa_byte1_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte1_dout;
-#define REG_RD_ADDR_gio_rw_pa_byte1_dout 20
-#define REG_WR_ADDR_gio_rw_pa_byte1_dout 20
-
-/* Register rw_pa_byte1_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte1_oe;
-#define REG_RD_ADDR_gio_rw_pa_byte1_oe 24
-#define REG_WR_ADDR_gio_rw_pa_byte1_oe 24
-
-/* Register rw_pa_byte2_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte2_dout;
-#define REG_RD_ADDR_gio_rw_pa_byte2_dout 28
-#define REG_WR_ADDR_gio_rw_pa_byte2_dout 28
-
-/* Register rw_pa_byte2_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte2_oe;
-#define REG_RD_ADDR_gio_rw_pa_byte2_oe 32
-#define REG_WR_ADDR_gio_rw_pa_byte2_oe 32
-
-/* Register rw_pa_byte3_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte3_dout;
-#define REG_RD_ADDR_gio_rw_pa_byte3_dout 36
-#define REG_WR_ADDR_gio_rw_pa_byte3_dout 36
-
-/* Register rw_pa_byte3_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte3_oe;
-#define REG_RD_ADDR_gio_rw_pa_byte3_oe 40
-#define REG_WR_ADDR_gio_rw_pa_byte3_oe 40
-
-/* Register r_pb_din, scope gio, type r */
-typedef struct {
-  unsigned int data : 32;
-} reg_gio_r_pb_din;
-#define REG_RD_ADDR_gio_r_pb_din 44
-
-/* Register rw_pb_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 32;
-} reg_gio_rw_pb_dout;
-#define REG_RD_ADDR_gio_rw_pb_dout 48
-#define REG_WR_ADDR_gio_rw_pb_dout 48
-
-/* Register rw_pb_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 32;
-} reg_gio_rw_pb_oe;
-#define REG_RD_ADDR_gio_rw_pb_oe 52
-#define REG_WR_ADDR_gio_rw_pb_oe 52
-
-/* Register rw_pb_byte0_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte0_dout;
-#define REG_RD_ADDR_gio_rw_pb_byte0_dout 56
-#define REG_WR_ADDR_gio_rw_pb_byte0_dout 56
-
-/* Register rw_pb_byte0_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte0_oe;
-#define REG_RD_ADDR_gio_rw_pb_byte0_oe 60
-#define REG_WR_ADDR_gio_rw_pb_byte0_oe 60
-
-/* Register rw_pb_byte1_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte1_dout;
-#define REG_RD_ADDR_gio_rw_pb_byte1_dout 64
-#define REG_WR_ADDR_gio_rw_pb_byte1_dout 64
-
-/* Register rw_pb_byte1_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte1_oe;
-#define REG_RD_ADDR_gio_rw_pb_byte1_oe 68
-#define REG_WR_ADDR_gio_rw_pb_byte1_oe 68
-
-/* Register rw_pb_byte2_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte2_dout;
-#define REG_RD_ADDR_gio_rw_pb_byte2_dout 72
-#define REG_WR_ADDR_gio_rw_pb_byte2_dout 72
-
-/* Register rw_pb_byte2_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte2_oe;
-#define REG_RD_ADDR_gio_rw_pb_byte2_oe 76
-#define REG_WR_ADDR_gio_rw_pb_byte2_oe 76
-
-/* Register rw_pb_byte3_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte3_dout;
-#define REG_RD_ADDR_gio_rw_pb_byte3_dout 80
-#define REG_WR_ADDR_gio_rw_pb_byte3_dout 80
-
-/* Register rw_pb_byte3_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte3_oe;
-#define REG_RD_ADDR_gio_rw_pb_byte3_oe 84
-#define REG_WR_ADDR_gio_rw_pb_byte3_oe 84
-
-/* Register r_pc_din, scope gio, type r */
-typedef struct {
-  unsigned int data : 16;
-  unsigned int dummy1 : 16;
-} reg_gio_r_pc_din;
-#define REG_RD_ADDR_gio_r_pc_din 88
-
-/* Register rw_pc_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 16;
-  unsigned int dummy1 : 16;
-} reg_gio_rw_pc_dout;
-#define REG_RD_ADDR_gio_rw_pc_dout 92
-#define REG_WR_ADDR_gio_rw_pc_dout 92
-
-/* Register rw_pc_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 16;
-  unsigned int dummy1 : 16;
-} reg_gio_rw_pc_oe;
-#define REG_RD_ADDR_gio_rw_pc_oe 96
-#define REG_WR_ADDR_gio_rw_pc_oe 96
-
-/* Register rw_pc_byte0_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pc_byte0_dout;
-#define REG_RD_ADDR_gio_rw_pc_byte0_dout 100
-#define REG_WR_ADDR_gio_rw_pc_byte0_dout 100
-
-/* Register rw_pc_byte0_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pc_byte0_oe;
-#define REG_RD_ADDR_gio_rw_pc_byte0_oe 104
-#define REG_WR_ADDR_gio_rw_pc_byte0_oe 104
-
-/* Register rw_pc_byte1_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pc_byte1_dout;
-#define REG_RD_ADDR_gio_rw_pc_byte1_dout 108
-#define REG_WR_ADDR_gio_rw_pc_byte1_dout 108
-
-/* Register rw_pc_byte1_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pc_byte1_oe;
-#define REG_RD_ADDR_gio_rw_pc_byte1_oe 112
-#define REG_WR_ADDR_gio_rw_pc_byte1_oe 112
-
-/* Register r_pd_din, scope gio, type r */
-typedef struct {
-  unsigned int data : 32;
-} reg_gio_r_pd_din;
-#define REG_RD_ADDR_gio_r_pd_din 116
-
-/* Register rw_intr_cfg, scope gio, type rw */
-typedef struct {
-  unsigned int intr0 : 3;
-  unsigned int intr1 : 3;
-  unsigned int intr2 : 3;
-  unsigned int intr3 : 3;
-  unsigned int intr4 : 3;
-  unsigned int intr5 : 3;
-  unsigned int intr6 : 3;
-  unsigned int intr7 : 3;
-  unsigned int dummy1 : 8;
-} reg_gio_rw_intr_cfg;
-#define REG_RD_ADDR_gio_rw_intr_cfg 120
-#define REG_WR_ADDR_gio_rw_intr_cfg 120
-
-/* Register rw_intr_pins, scope gio, type rw */
-typedef struct {
-  unsigned int intr0 : 4;
-  unsigned int intr1 : 4;
-  unsigned int intr2 : 4;
-  unsigned int intr3 : 4;
-  unsigned int intr4 : 4;
-  unsigned int intr5 : 4;
-  unsigned int intr6 : 4;
-  unsigned int intr7 : 4;
-} reg_gio_rw_intr_pins;
-#define REG_RD_ADDR_gio_rw_intr_pins 124
-#define REG_WR_ADDR_gio_rw_intr_pins 124
-
-/* Register rw_intr_mask, scope gio, type rw */
-typedef struct {
-  unsigned int intr0     : 1;
-  unsigned int intr1     : 1;
-  unsigned int intr2     : 1;
-  unsigned int intr3     : 1;
-  unsigned int intr4     : 1;
-  unsigned int intr5     : 1;
-  unsigned int intr6     : 1;
-  unsigned int intr7     : 1;
-  unsigned int i2c0_done : 1;
-  unsigned int i2c1_done : 1;
-  unsigned int dummy1    : 22;
-} reg_gio_rw_intr_mask;
-#define REG_RD_ADDR_gio_rw_intr_mask 128
-#define REG_WR_ADDR_gio_rw_intr_mask 128
-
-/* Register rw_ack_intr, scope gio, type rw */
-typedef struct {
-  unsigned int intr0     : 1;
-  unsigned int intr1     : 1;
-  unsigned int intr2     : 1;
-  unsigned int intr3     : 1;
-  unsigned int intr4     : 1;
-  unsigned int intr5     : 1;
-  unsigned int intr6     : 1;
-  unsigned int intr7     : 1;
-  unsigned int i2c0_done : 1;
-  unsigned int i2c1_done : 1;
-  unsigned int dummy1    : 22;
-} reg_gio_rw_ack_intr;
-#define REG_RD_ADDR_gio_rw_ack_intr 132
-#define REG_WR_ADDR_gio_rw_ack_intr 132
-
-/* Register r_intr, scope gio, type r */
-typedef struct {
-  unsigned int intr0     : 1;
-  unsigned int intr1     : 1;
-  unsigned int intr2     : 1;
-  unsigned int intr3     : 1;
-  unsigned int intr4     : 1;
-  unsigned int intr5     : 1;
-  unsigned int intr6     : 1;
-  unsigned int intr7     : 1;
-  unsigned int i2c0_done : 1;
-  unsigned int i2c1_done : 1;
-  unsigned int dummy1    : 22;
-} reg_gio_r_intr;
-#define REG_RD_ADDR_gio_r_intr 136
-
-/* Register r_masked_intr, scope gio, type r */
-typedef struct {
-  unsigned int intr0     : 1;
-  unsigned int intr1     : 1;
-  unsigned int intr2     : 1;
-  unsigned int intr3     : 1;
-  unsigned int intr4     : 1;
-  unsigned int intr5     : 1;
-  unsigned int intr6     : 1;
-  unsigned int intr7     : 1;
-  unsigned int i2c0_done : 1;
-  unsigned int i2c1_done : 1;
-  unsigned int dummy1    : 22;
-} reg_gio_r_masked_intr;
-#define REG_RD_ADDR_gio_r_masked_intr 140
-
-/* Register rw_i2c0_start, scope gio, type rw */
-typedef struct {
-  unsigned int run : 1;
-  unsigned int dummy1 : 31;
-} reg_gio_rw_i2c0_start;
-#define REG_RD_ADDR_gio_rw_i2c0_start 144
-#define REG_WR_ADDR_gio_rw_i2c0_start 144
-
-/* Register rw_i2c0_cfg, scope gio, type rw */
-typedef struct {
-  unsigned int en        : 1;
-  unsigned int bit_order : 1;
-  unsigned int scl_io    : 1;
-  unsigned int scl_inv   : 1;
-  unsigned int sda_io    : 1;
-  unsigned int sda_idle  : 1;
-  unsigned int dummy1    : 26;
-} reg_gio_rw_i2c0_cfg;
-#define REG_RD_ADDR_gio_rw_i2c0_cfg 148
-#define REG_WR_ADDR_gio_rw_i2c0_cfg 148
-
-/* Register rw_i2c0_ctrl, scope gio, type rw */
-typedef struct {
-  unsigned int trf_bits    : 6;
-  unsigned int switch_dir  : 6;
-  unsigned int extra_start : 3;
-  unsigned int early_end   : 1;
-  unsigned int start_stop  : 1;
-  unsigned int ack_dir0    : 1;
-  unsigned int ack_dir1    : 1;
-  unsigned int ack_dir2    : 1;
-  unsigned int ack_dir3    : 1;
-  unsigned int ack_dir4    : 1;
-  unsigned int ack_dir5    : 1;
-  unsigned int ack_bit     : 1;
-  unsigned int start_bit   : 1;
-  unsigned int freq        : 2;
-  unsigned int dummy1      : 5;
-} reg_gio_rw_i2c0_ctrl;
-#define REG_RD_ADDR_gio_rw_i2c0_ctrl 152
-#define REG_WR_ADDR_gio_rw_i2c0_ctrl 152
-
-/* Register rw_i2c0_data, scope gio, type rw */
-typedef struct {
-  unsigned int data0 : 8;
-  unsigned int data1 : 8;
-  unsigned int data2 : 8;
-  unsigned int data3 : 8;
-} reg_gio_rw_i2c0_data;
-#define REG_RD_ADDR_gio_rw_i2c0_data 156
-#define REG_WR_ADDR_gio_rw_i2c0_data 156
-
-/* Register rw_i2c0_data2, scope gio, type rw */
-typedef struct {
-  unsigned int data4     : 8;
-  unsigned int data5     : 8;
-  unsigned int start_val : 6;
-  unsigned int ack_val   : 6;
-  unsigned int dummy1    : 4;
-} reg_gio_rw_i2c0_data2;
-#define REG_RD_ADDR_gio_rw_i2c0_data2 160
-#define REG_WR_ADDR_gio_rw_i2c0_data2 160
-
-/* Register rw_i2c1_start, scope gio, type rw */
-typedef struct {
-  unsigned int run : 1;
-  unsigned int dummy1 : 31;
-} reg_gio_rw_i2c1_start;
-#define REG_RD_ADDR_gio_rw_i2c1_start 164
-#define REG_WR_ADDR_gio_rw_i2c1_start 164
-
-/* Register rw_i2c1_cfg, scope gio, type rw */
-typedef struct {
-  unsigned int en        : 1;
-  unsigned int bit_order : 1;
-  unsigned int scl_io    : 1;
-  unsigned int scl_inv   : 1;
-  unsigned int sda0_io   : 1;
-  unsigned int sda0_idle : 1;
-  unsigned int sda1_io   : 1;
-  unsigned int sda1_idle : 1;
-  unsigned int sda2_io   : 1;
-  unsigned int sda2_idle : 1;
-  unsigned int sda3_io   : 1;
-  unsigned int sda3_idle : 1;
-  unsigned int sda_sel   : 2;
-  unsigned int sen_idle  : 1;
-  unsigned int sen_inv   : 1;
-  unsigned int sen_sel   : 2;
-  unsigned int dummy1    : 14;
-} reg_gio_rw_i2c1_cfg;
-#define REG_RD_ADDR_gio_rw_i2c1_cfg 168
-#define REG_WR_ADDR_gio_rw_i2c1_cfg 168
-
-/* Register rw_i2c1_ctrl, scope gio, type rw */
-typedef struct {
-  unsigned int trf_bits    : 6;
-  unsigned int switch_dir  : 6;
-  unsigned int extra_start : 3;
-  unsigned int early_end   : 1;
-  unsigned int start_stop  : 1;
-  unsigned int ack_dir0    : 1;
-  unsigned int ack_dir1    : 1;
-  unsigned int ack_dir2    : 1;
-  unsigned int ack_dir3    : 1;
-  unsigned int ack_dir4    : 1;
-  unsigned int ack_dir5    : 1;
-  unsigned int ack_bit     : 1;
-  unsigned int start_bit   : 1;
-  unsigned int freq        : 2;
-  unsigned int dummy1      : 5;
-} reg_gio_rw_i2c1_ctrl;
-#define REG_RD_ADDR_gio_rw_i2c1_ctrl 172
-#define REG_WR_ADDR_gio_rw_i2c1_ctrl 172
-
-/* Register rw_i2c1_data, scope gio, type rw */
-typedef struct {
-  unsigned int data0 : 8;
-  unsigned int data1 : 8;
-  unsigned int data2 : 8;
-  unsigned int data3 : 8;
-} reg_gio_rw_i2c1_data;
-#define REG_RD_ADDR_gio_rw_i2c1_data 176
-#define REG_WR_ADDR_gio_rw_i2c1_data 176
-
-/* Register rw_i2c1_data2, scope gio, type rw */
-typedef struct {
-  unsigned int data4     : 8;
-  unsigned int data5     : 8;
-  unsigned int start_val : 6;
-  unsigned int ack_val   : 6;
-  unsigned int dummy1    : 4;
-} reg_gio_rw_i2c1_data2;
-#define REG_RD_ADDR_gio_rw_i2c1_data2 180
-#define REG_WR_ADDR_gio_rw_i2c1_data2 180
-
-/* Register r_ppwm_stat, scope gio, type r */
-typedef struct {
-  unsigned int freq : 2;
-  unsigned int dummy1 : 30;
-} reg_gio_r_ppwm_stat;
-#define REG_RD_ADDR_gio_r_ppwm_stat 184
-
-/* Register rw_ppwm_data, scope gio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_ppwm_data;
-#define REG_RD_ADDR_gio_rw_ppwm_data 188
-#define REG_WR_ADDR_gio_rw_ppwm_data 188
-
-/* Register rw_pwm0_ctrl, scope gio, type rw */
-typedef struct {
-  unsigned int mode         : 2;
-  unsigned int ccd_override : 1;
-  unsigned int ccd_val      : 1;
-  unsigned int dummy1       : 28;
-} reg_gio_rw_pwm0_ctrl;
-#define REG_RD_ADDR_gio_rw_pwm0_ctrl 192
-#define REG_WR_ADDR_gio_rw_pwm0_ctrl 192
-
-/* Register rw_pwm0_var, scope gio, type rw */
-typedef struct {
-  unsigned int lo : 13;
-  unsigned int hi : 13;
-  unsigned int dummy1 : 6;
-} reg_gio_rw_pwm0_var;
-#define REG_RD_ADDR_gio_rw_pwm0_var 196
-#define REG_WR_ADDR_gio_rw_pwm0_var 196
-
-/* Register rw_pwm0_data, scope gio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pwm0_data;
-#define REG_RD_ADDR_gio_rw_pwm0_data 200
-#define REG_WR_ADDR_gio_rw_pwm0_data 200
-
-/* Register rw_pwm1_ctrl, scope gio, type rw */
-typedef struct {
-  unsigned int mode         : 2;
-  unsigned int ccd_override : 1;
-  unsigned int ccd_val      : 1;
-  unsigned int dummy1       : 28;
-} reg_gio_rw_pwm1_ctrl;
-#define REG_RD_ADDR_gio_rw_pwm1_ctrl 204
-#define REG_WR_ADDR_gio_rw_pwm1_ctrl 204
-
-/* Register rw_pwm1_var, scope gio, type rw */
-typedef struct {
-  unsigned int lo : 13;
-  unsigned int hi : 13;
-  unsigned int dummy1 : 6;
-} reg_gio_rw_pwm1_var;
-#define REG_RD_ADDR_gio_rw_pwm1_var 208
-#define REG_WR_ADDR_gio_rw_pwm1_var 208
-
-/* Register rw_pwm1_data, scope gio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pwm1_data;
-#define REG_RD_ADDR_gio_rw_pwm1_data 212
-#define REG_WR_ADDR_gio_rw_pwm1_data 212
-
-/* Register rw_pwm2_ctrl, scope gio, type rw */
-typedef struct {
-  unsigned int mode         : 2;
-  unsigned int ccd_override : 1;
-  unsigned int ccd_val      : 1;
-  unsigned int dummy1       : 28;
-} reg_gio_rw_pwm2_ctrl;
-#define REG_RD_ADDR_gio_rw_pwm2_ctrl 216
-#define REG_WR_ADDR_gio_rw_pwm2_ctrl 216
-
-/* Register rw_pwm2_var, scope gio, type rw */
-typedef struct {
-  unsigned int lo : 13;
-  unsigned int hi : 13;
-  unsigned int dummy1 : 6;
-} reg_gio_rw_pwm2_var;
-#define REG_RD_ADDR_gio_rw_pwm2_var 220
-#define REG_WR_ADDR_gio_rw_pwm2_var 220
-
-/* Register rw_pwm2_data, scope gio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pwm2_data;
-#define REG_RD_ADDR_gio_rw_pwm2_data 224
-#define REG_WR_ADDR_gio_rw_pwm2_data 224
-
-/* Register rw_pwm_in_cfg, scope gio, type rw */
-typedef struct {
-  unsigned int pin : 3;
-  unsigned int dummy1 : 29;
-} reg_gio_rw_pwm_in_cfg;
-#define REG_RD_ADDR_gio_rw_pwm_in_cfg 228
-#define REG_WR_ADDR_gio_rw_pwm_in_cfg 228
-
-/* Register r_pwm_in_lo, scope gio, type r */
-typedef struct {
-  unsigned int data : 32;
-} reg_gio_r_pwm_in_lo;
-#define REG_RD_ADDR_gio_r_pwm_in_lo 232
-
-/* Register r_pwm_in_hi, scope gio, type r */
-typedef struct {
-  unsigned int data : 32;
-} reg_gio_r_pwm_in_hi;
-#define REG_RD_ADDR_gio_r_pwm_in_hi 236
-
-/* Register r_pwm_in_cnt, scope gio, type r */
-typedef struct {
-  unsigned int data : 32;
-} reg_gio_r_pwm_in_cnt;
-#define REG_RD_ADDR_gio_r_pwm_in_cnt 240
-
-
-/* Constants */
-enum {
-  regk_gio_anyedge                         = 0x00000007,
-  regk_gio_f100k                           = 0x00000000,
-  regk_gio_f1562                           = 0x00000000,
-  regk_gio_f195                            = 0x00000003,
-  regk_gio_f1m                             = 0x00000002,
-  regk_gio_f390                            = 0x00000002,
-  regk_gio_f400k                           = 0x00000001,
-  regk_gio_f5m                             = 0x00000003,
-  regk_gio_f781                            = 0x00000001,
-  regk_gio_hi                              = 0x00000001,
-  regk_gio_in                              = 0x00000000,
-  regk_gio_intr_pa0                        = 0x00000000,
-  regk_gio_intr_pa1                        = 0x00000000,
-  regk_gio_intr_pa10                       = 0x00000001,
-  regk_gio_intr_pa11                       = 0x00000001,
-  regk_gio_intr_pa12                       = 0x00000001,
-  regk_gio_intr_pa13                       = 0x00000001,
-  regk_gio_intr_pa14                       = 0x00000001,
-  regk_gio_intr_pa15                       = 0x00000001,
-  regk_gio_intr_pa16                       = 0x00000002,
-  regk_gio_intr_pa17                       = 0x00000002,
-  regk_gio_intr_pa18                       = 0x00000002,
-  regk_gio_intr_pa19                       = 0x00000002,
-  regk_gio_intr_pa2                        = 0x00000000,
-  regk_gio_intr_pa20                       = 0x00000002,
-  regk_gio_intr_pa21                       = 0x00000002,
-  regk_gio_intr_pa22                       = 0x00000002,
-  regk_gio_intr_pa23                       = 0x00000002,
-  regk_gio_intr_pa24                       = 0x00000003,
-  regk_gio_intr_pa25                       = 0x00000003,
-  regk_gio_intr_pa26                       = 0x00000003,
-  regk_gio_intr_pa27                       = 0x00000003,
-  regk_gio_intr_pa28                       = 0x00000003,
-  regk_gio_intr_pa29                       = 0x00000003,
-  regk_gio_intr_pa3                        = 0x00000000,
-  regk_gio_intr_pa30                       = 0x00000003,
-  regk_gio_intr_pa31                       = 0x00000003,
-  regk_gio_intr_pa4                        = 0x00000000,
-  regk_gio_intr_pa5                        = 0x00000000,
-  regk_gio_intr_pa6                        = 0x00000000,
-  regk_gio_intr_pa7                        = 0x00000000,
-  regk_gio_intr_pa8                        = 0x00000001,
-  regk_gio_intr_pa9                        = 0x00000001,
-  regk_gio_intr_pb0                        = 0x00000004,
-  regk_gio_intr_pb1                        = 0x00000004,
-  regk_gio_intr_pb10                       = 0x00000005,
-  regk_gio_intr_pb11                       = 0x00000005,
-  regk_gio_intr_pb12                       = 0x00000005,
-  regk_gio_intr_pb13                       = 0x00000005,
-  regk_gio_intr_pb14                       = 0x00000005,
-  regk_gio_intr_pb15                       = 0x00000005,
-  regk_gio_intr_pb16                       = 0x00000006,
-  regk_gio_intr_pb17                       = 0x00000006,
-  regk_gio_intr_pb18                       = 0x00000006,
-  regk_gio_intr_pb19                       = 0x00000006,
-  regk_gio_intr_pb2                        = 0x00000004,
-  regk_gio_intr_pb20                       = 0x00000006,
-  regk_gio_intr_pb21                       = 0x00000006,
-  regk_gio_intr_pb22                       = 0x00000006,
-  regk_gio_intr_pb23                       = 0x00000006,
-  regk_gio_intr_pb24                       = 0x00000007,
-  regk_gio_intr_pb25                       = 0x00000007,
-  regk_gio_intr_pb26                       = 0x00000007,
-  regk_gio_intr_pb27                       = 0x00000007,
-  regk_gio_intr_pb28                       = 0x00000007,
-  regk_gio_intr_pb29                       = 0x00000007,
-  regk_gio_intr_pb3                        = 0x00000004,
-  regk_gio_intr_pb30                       = 0x00000007,
-  regk_gio_intr_pb31                       = 0x00000007,
-  regk_gio_intr_pb4                        = 0x00000004,
-  regk_gio_intr_pb5                        = 0x00000004,
-  regk_gio_intr_pb6                        = 0x00000004,
-  regk_gio_intr_pb7                        = 0x00000004,
-  regk_gio_intr_pb8                        = 0x00000005,
-  regk_gio_intr_pb9                        = 0x00000005,
-  regk_gio_intr_pc0                        = 0x00000008,
-  regk_gio_intr_pc1                        = 0x00000008,
-  regk_gio_intr_pc10                       = 0x00000009,
-  regk_gio_intr_pc11                       = 0x00000009,
-  regk_gio_intr_pc12                       = 0x00000009,
-  regk_gio_intr_pc13                       = 0x00000009,
-  regk_gio_intr_pc14                       = 0x00000009,
-  regk_gio_intr_pc15                       = 0x00000009,
-  regk_gio_intr_pc2                        = 0x00000008,
-  regk_gio_intr_pc3                        = 0x00000008,
-  regk_gio_intr_pc4                        = 0x00000008,
-  regk_gio_intr_pc5                        = 0x00000008,
-  regk_gio_intr_pc6                        = 0x00000008,
-  regk_gio_intr_pc7                        = 0x00000008,
-  regk_gio_intr_pc8                        = 0x00000009,
-  regk_gio_intr_pc9                        = 0x00000009,
-  regk_gio_intr_pd0                        = 0x0000000c,
-  regk_gio_intr_pd1                        = 0x0000000c,
-  regk_gio_intr_pd10                       = 0x0000000d,
-  regk_gio_intr_pd11                       = 0x0000000d,
-  regk_gio_intr_pd12                       = 0x0000000d,
-  regk_gio_intr_pd13                       = 0x0000000d,
-  regk_gio_intr_pd14                       = 0x0000000d,
-  regk_gio_intr_pd15                       = 0x0000000d,
-  regk_gio_intr_pd16                       = 0x0000000e,
-  regk_gio_intr_pd17                       = 0x0000000e,
-  regk_gio_intr_pd18                       = 0x0000000e,
-  regk_gio_intr_pd19                       = 0x0000000e,
-  regk_gio_intr_pd2                        = 0x0000000c,
-  regk_gio_intr_pd20                       = 0x0000000e,
-  regk_gio_intr_pd21                       = 0x0000000e,
-  regk_gio_intr_pd22                       = 0x0000000e,
-  regk_gio_intr_pd23                       = 0x0000000e,
-  regk_gio_intr_pd24                       = 0x0000000f,
-  regk_gio_intr_pd25                       = 0x0000000f,
-  regk_gio_intr_pd26                       = 0x0000000f,
-  regk_gio_intr_pd27                       = 0x0000000f,
-  regk_gio_intr_pd28                       = 0x0000000f,
-  regk_gio_intr_pd29                       = 0x0000000f,
-  regk_gio_intr_pd3                        = 0x0000000c,
-  regk_gio_intr_pd30                       = 0x0000000f,
-  regk_gio_intr_pd31                       = 0x0000000f,
-  regk_gio_intr_pd4                        = 0x0000000c,
-  regk_gio_intr_pd5                        = 0x0000000c,
-  regk_gio_intr_pd6                        = 0x0000000c,
-  regk_gio_intr_pd7                        = 0x0000000c,
-  regk_gio_intr_pd8                        = 0x0000000d,
-  regk_gio_intr_pd9                        = 0x0000000d,
-  regk_gio_lo                              = 0x00000002,
-  regk_gio_lsb                             = 0x00000000,
-  regk_gio_msb                             = 0x00000001,
-  regk_gio_negedge                         = 0x00000006,
-  regk_gio_no                              = 0x00000000,
-  regk_gio_no_switch                       = 0x0000003f,
-  regk_gio_none                            = 0x00000007,
-  regk_gio_off                             = 0x00000000,
-  regk_gio_opendrain                       = 0x00000000,
-  regk_gio_out                             = 0x00000001,
-  regk_gio_posedge                         = 0x00000005,
-  regk_gio_pwm_hfp                         = 0x00000002,
-  regk_gio_pwm_pa0                         = 0x00000001,
-  regk_gio_pwm_pa19                        = 0x00000004,
-  regk_gio_pwm_pa6                         = 0x00000002,
-  regk_gio_pwm_pa7                         = 0x00000003,
-  regk_gio_pwm_pb26                        = 0x00000005,
-  regk_gio_pwm_pd23                        = 0x00000006,
-  regk_gio_pwm_pd31                        = 0x00000007,
-  regk_gio_pwm_std                         = 0x00000001,
-  regk_gio_pwm_var                         = 0x00000003,
-  regk_gio_rw_i2c0_cfg_default             = 0x00000020,
-  regk_gio_rw_i2c0_ctrl_default            = 0x00010000,
-  regk_gio_rw_i2c0_start_default           = 0x00000000,
-  regk_gio_rw_i2c1_cfg_default             = 0x00000aa0,
-  regk_gio_rw_i2c1_ctrl_default            = 0x00010000,
-  regk_gio_rw_i2c1_start_default           = 0x00000000,
-  regk_gio_rw_intr_cfg_default             = 0x00000000,
-  regk_gio_rw_intr_mask_default            = 0x00000000,
-  regk_gio_rw_pa_oe_default                = 0x00000000,
-  regk_gio_rw_pb_oe_default                = 0x00000000,
-  regk_gio_rw_pc_oe_default                = 0x00000000,
-  regk_gio_rw_ppwm_data_default            = 0x00000000,
-  regk_gio_rw_pwm0_ctrl_default            = 0x00000000,
-  regk_gio_rw_pwm1_ctrl_default            = 0x00000000,
-  regk_gio_rw_pwm2_ctrl_default            = 0x00000000,
-  regk_gio_rw_pwm_in_cfg_default           = 0x00000000,
-  regk_gio_sda0                            = 0x00000000,
-  regk_gio_sda1                            = 0x00000001,
-  regk_gio_sda2                            = 0x00000002,
-  regk_gio_sda3                            = 0x00000003,
-  regk_gio_sen                             = 0x00000000,
-  regk_gio_set                             = 0x00000003,
-  regk_gio_yes                             = 0x00000001
-};
-#endif /* __gio_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h
deleted file mode 100644
index bea699aa480e..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Interrupt vector numbers autogenerated by ../../../tools/rdesc/bin/rdes2intr 
-   from intr_vect.r */
-
-#ifndef _INTR_VECT_R
-#define _INTR_VECT_R 
-#define TIMER0_INTR_VECT	0x31
-#define TIMER1_INTR_VECT	0x32
-#define DMA0_INTR_VECT	0x33
-#define DMA1_INTR_VECT	0x34
-#define DMA2_INTR_VECT	0x35
-#define DMA3_INTR_VECT	0x36
-#define DMA4_INTR_VECT	0x37
-#define DMA5_INTR_VECT	0x38
-#define DMA6_INTR_VECT	0x39
-#define DMA7_INTR_VECT	0x3a
-#define DMA9_INTR_VECT	0x3b
-#define DMA11_INTR_VECT	0x3c
-#define GIO_INTR_VECT	0x3d
-#define IOP0_INTR_VECT	0x3e
-#define IOP1_INTR_VECT	0x3f
-#define SER0_INTR_VECT	0x40
-#define SER1_INTR_VECT	0x41
-#define SER2_INTR_VECT	0x42
-#define SER3_INTR_VECT	0x43
-#define SER4_INTR_VECT	0x44
-#define SSER_INTR_VECT	0x45
-#define STRDMA0_INTR_VECT	0x46
-#define STRDMA1_INTR_VECT	0x47
-#define STRDMA2_INTR_VECT	0x48
-#define STRDMA3_INTR_VECT	0x49
-#define STRDMA5_INTR_VECT	0x4a
-#define VIN_INTR_VECT	0x4b
-#define VOUT_INTR_VECT	0x4c
-#define JPEG_INTR_VECT	0x4d
-#define H264_INTR_VECT	0x4e
-#define HISTO_INTR_VECT	0x4f
-#define CCD_INTR_VECT	0x50
-#define ETH_INTR_VECT	0x51
-#define MEMARB_BAR_INTR_VECT	0x52
-#define MEMARB_FOO_INTR_VECT	0x53
-#define PIO_INTR_VECT	0x54
-#define SCLR_INTR_VECT	0x55
-#define SCLR_FIFO_INTR_VECT	0x56
-#define IPI_INTR_VECT   0x57
-#define NBR_INTR_VECT   0x58
-#endif
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h
deleted file mode 100644
index b820f6347c74..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h
+++ /dev/null
@@ -1,341 +0,0 @@
-#ifndef __intr_vect_defs_h
-#define __intr_vect_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           intr_vect.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile intr_vect_defs.h intr_vect.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope intr_vect */
-
-
-#define STRIDE_intr_vect_rw_mask 4
-/* Register rw_mask0, scope intr_vect, type rw */
-typedef struct {
-  unsigned int timer0  : 1;
-  unsigned int timer1  : 1;
-  unsigned int dma0    : 1;
-  unsigned int dma1    : 1;
-  unsigned int dma2    : 1;
-  unsigned int dma3    : 1;
-  unsigned int dma4    : 1;
-  unsigned int dma5    : 1;
-  unsigned int dma6    : 1;
-  unsigned int dma7    : 1;
-  unsigned int dma9    : 1;
-  unsigned int dma11   : 1;
-  unsigned int gio     : 1;
-  unsigned int iop0    : 1;
-  unsigned int iop1    : 1;
-  unsigned int ser0    : 1;
-  unsigned int ser1    : 1;
-  unsigned int ser2    : 1;
-  unsigned int ser3    : 1;
-  unsigned int ser4    : 1;
-  unsigned int sser    : 1;
-  unsigned int strdma0 : 1;
-  unsigned int strdma1 : 1;
-  unsigned int strdma2 : 1;
-  unsigned int strdma3 : 1;
-  unsigned int strdma5 : 1;
-  unsigned int vin     : 1;
-  unsigned int vout    : 1;
-  unsigned int jpeg    : 1;
-  unsigned int h264    : 1;
-  unsigned int histo   : 1;
-  unsigned int ccd     : 1;
-} reg_intr_vect_rw_mask0;
-#define reg_intr_vect_rw_mask reg_intr_vect_rw_mask0
-#define REG_RD_ADDR_intr_vect_rw_mask 0
-#define REG_WR_ADDR_intr_vect_rw_mask 0
-#define REG_RD_ADDR_intr_vect_rw_mask0 0
-#define REG_WR_ADDR_intr_vect_rw_mask0 0
-
-#define STRIDE_intr_vect_r_vect 4
-/* Register r_vect0, scope intr_vect, type r */
-typedef struct {
-  unsigned int timer0  : 1;
-  unsigned int timer1  : 1;
-  unsigned int dma0    : 1;
-  unsigned int dma1    : 1;
-  unsigned int dma2    : 1;
-  unsigned int dma3    : 1;
-  unsigned int dma4    : 1;
-  unsigned int dma5    : 1;
-  unsigned int dma6    : 1;
-  unsigned int dma7    : 1;
-  unsigned int dma9    : 1;
-  unsigned int dma11   : 1;
-  unsigned int gio     : 1;
-  unsigned int iop0    : 1;
-  unsigned int iop1    : 1;
-  unsigned int ser0    : 1;
-  unsigned int ser1    : 1;
-  unsigned int ser2    : 1;
-  unsigned int ser3    : 1;
-  unsigned int ser4    : 1;
-  unsigned int sser    : 1;
-  unsigned int strdma0 : 1;
-  unsigned int strdma1 : 1;
-  unsigned int strdma2 : 1;
-  unsigned int strdma3 : 1;
-  unsigned int strdma5 : 1;
-  unsigned int vin     : 1;
-  unsigned int vout    : 1;
-  unsigned int jpeg    : 1;
-  unsigned int h264    : 1;
-  unsigned int histo   : 1;
-  unsigned int ccd     : 1;
-} reg_intr_vect_r_vect0;
-#define reg_intr_vect_r_vect reg_intr_vect_r_vect0
-#define REG_RD_ADDR_intr_vect_r_vect 8
-#define REG_RD_ADDR_intr_vect_r_vect0 8
-
-#define STRIDE_intr_vect_r_masked_vect 4
-/* Register r_masked_vect0, scope intr_vect, type r */
-typedef struct {
-  unsigned int timer0  : 1;
-  unsigned int timer1  : 1;
-  unsigned int dma0    : 1;
-  unsigned int dma1    : 1;
-  unsigned int dma2    : 1;
-  unsigned int dma3    : 1;
-  unsigned int dma4    : 1;
-  unsigned int dma5    : 1;
-  unsigned int dma6    : 1;
-  unsigned int dma7    : 1;
-  unsigned int dma9    : 1;
-  unsigned int dma11   : 1;
-  unsigned int gio     : 1;
-  unsigned int iop0    : 1;
-  unsigned int iop1    : 1;
-  unsigned int ser0    : 1;
-  unsigned int ser1    : 1;
-  unsigned int ser2    : 1;
-  unsigned int ser3    : 1;
-  unsigned int ser4    : 1;
-  unsigned int sser    : 1;
-  unsigned int strdma0 : 1;
-  unsigned int strdma1 : 1;
-  unsigned int strdma2 : 1;
-  unsigned int strdma3 : 1;
-  unsigned int strdma5 : 1;
-  unsigned int vin     : 1;
-  unsigned int vout    : 1;
-  unsigned int jpeg    : 1;
-  unsigned int h264    : 1;
-  unsigned int histo   : 1;
-  unsigned int ccd     : 1;
-} reg_intr_vect_r_masked_vect0;
-#define reg_intr_vect_r_masked_vect reg_intr_masked_vect_r_vect0
-#define REG_RD_ADDR_intr_vect_r_masked_vect0 16
-#define REG_RD_ADDR_intr_vect_r_masked_vect 16
-
-#define STRIDE_intr_vect_rw_xmask 4
-/* Register rw_xmask0, scope intr_vect, type rw */
-typedef struct {
-  unsigned int timer0  : 1;
-  unsigned int timer1  : 1;
-  unsigned int dma0    : 1;
-  unsigned int dma1    : 1;
-  unsigned int dma2    : 1;
-  unsigned int dma3    : 1;
-  unsigned int dma4    : 1;
-  unsigned int dma5    : 1;
-  unsigned int dma6    : 1;
-  unsigned int dma7    : 1;
-  unsigned int dma9    : 1;
-  unsigned int dma11   : 1;
-  unsigned int gio     : 1;
-  unsigned int iop0    : 1;
-  unsigned int iop1    : 1;
-  unsigned int ser0    : 1;
-  unsigned int ser1    : 1;
-  unsigned int ser2    : 1;
-  unsigned int ser3    : 1;
-  unsigned int ser4    : 1;
-  unsigned int sser    : 1;
-  unsigned int strdma0 : 1;
-  unsigned int strdma1 : 1;
-  unsigned int strdma2 : 1;
-  unsigned int strdma3 : 1;
-  unsigned int strdma5 : 1;
-  unsigned int vin     : 1;
-  unsigned int vout    : 1;
-  unsigned int jpeg    : 1;
-  unsigned int h264    : 1;
-  unsigned int histo   : 1;
-  unsigned int ccd     : 1;
-} reg_intr_vect_rw_xmask0;
-#define reg_intr_vect_rw_xmask reg_intr_vect_rw_xmask0
-#define REG_RD_ADDR_intr_vect_rw_xmask0 24
-#define REG_WR_ADDR_intr_vect_rw_xmask0 24
-#define REG_RD_ADDR_intr_vect_rw_xmask 24
-#define REG_WR_ADDR_intr_vect_rw_xmask 24
-
-/* Register rw_mask1, scope intr_vect, type rw */
-typedef struct {
-  unsigned int eth        : 1;
-  unsigned int memarb_bar : 1;
-  unsigned int memarb_foo : 1;
-  unsigned int pio        : 1;
-  unsigned int sclr       : 1;
-  unsigned int sclr_fifo  : 1;
-  unsigned int dummy1     : 26;
-} reg_intr_vect_rw_mask1;
-#define REG_RD_ADDR_intr_vect_rw_mask1 4
-#define REG_WR_ADDR_intr_vect_rw_mask1 4
-
-/* Register r_vect1, scope intr_vect, type r */
-typedef struct {
-  unsigned int eth        : 1;
-  unsigned int memarb_bar : 1;
-  unsigned int memarb_foo : 1;
-  unsigned int pio        : 1;
-  unsigned int sclr       : 1;
-  unsigned int sclr_fifo  : 1;
-  unsigned int dummy1     : 26;
-} reg_intr_vect_r_vect1;
-#define REG_RD_ADDR_intr_vect_r_vect1 12
-
-/* Register r_masked_vect1, scope intr_vect, type r */
-typedef struct {
-  unsigned int eth        : 1;
-  unsigned int memarb_bar : 1;
-  unsigned int memarb_foo : 1;
-  unsigned int pio        : 1;
-  unsigned int sclr       : 1;
-  unsigned int sclr_fifo  : 1;
-  unsigned int dummy1     : 26;
-} reg_intr_vect_r_masked_vect1;
-#define REG_RD_ADDR_intr_vect_r_masked_vect1 20
-
-/* Register rw_xmask1, scope intr_vect, type rw */
-typedef struct {
-  unsigned int eth        : 1;
-  unsigned int memarb_bar : 1;
-  unsigned int memarb_foo : 1;
-  unsigned int pio        : 1;
-  unsigned int sclr       : 1;
-  unsigned int sclr_fifo  : 1;
-  unsigned int dummy1     : 26;
-} reg_intr_vect_rw_xmask1;
-#define REG_RD_ADDR_intr_vect_rw_xmask1 28
-#define REG_WR_ADDR_intr_vect_rw_xmask1 28
-
-/* Register rw_xmask_ctrl, scope intr_vect, type rw */
-typedef struct {
-  unsigned int en : 1;
-  unsigned int dummy1 : 31;
-} reg_intr_vect_rw_xmask_ctrl;
-#define REG_RD_ADDR_intr_vect_rw_xmask_ctrl 32
-#define REG_WR_ADDR_intr_vect_rw_xmask_ctrl 32
-
-/* Register r_nmi, scope intr_vect, type r */
-typedef struct {
-  unsigned int watchdog0 : 1;
-  unsigned int watchdog1 : 1;
-  unsigned int dummy1    : 30;
-} reg_intr_vect_r_nmi;
-#define REG_RD_ADDR_intr_vect_r_nmi 64
-
-/* Register r_guru, scope intr_vect, type r */
-typedef struct {
-  unsigned int jtag : 1;
-  unsigned int dummy1 : 31;
-} reg_intr_vect_r_guru;
-#define REG_RD_ADDR_intr_vect_r_guru 68
-
-
-/* Register rw_ipi, scope intr_vect, type rw */
-typedef struct 
-{
-  unsigned int vector;
-} reg_intr_vect_rw_ipi;
-#define REG_RD_ADDR_intr_vect_rw_ipi 72
-#define REG_WR_ADDR_intr_vect_rw_ipi 72
-
-/* Constants */
-enum {
-  regk_intr_vect_no                        = 0x00000000,
-  regk_intr_vect_rw_mask0_default          = 0x00000000,
-  regk_intr_vect_rw_mask1_default          = 0x00000000,
-  regk_intr_vect_rw_xmask0_default         = 0x00000000,
-  regk_intr_vect_rw_xmask1_default         = 0x00000000,
-  regk_intr_vect_rw_xmask_ctrl_default     = 0x00000000,
-  regk_intr_vect_yes                       = 0x00000001
-};
-#endif /* __intr_vect_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h
deleted file mode 100644
index d75a74e90458..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Autogenerated Changes here will be lost!
- * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg 
- */
-#define iop_version 0
-#define iop_fifo_in_extra 64
-#define iop_fifo_out_extra 128
-#define iop_trigger_grp0 192
-#define iop_trigger_grp1 256
-#define iop_trigger_grp2 320
-#define iop_trigger_grp3 384
-#define iop_trigger_grp4 448
-#define iop_trigger_grp5 512
-#define iop_trigger_grp6 576
-#define iop_trigger_grp7 640
-#define iop_crc_par 768
-#define iop_dmc_in 896
-#define iop_dmc_out 1024
-#define iop_fifo_in 1152
-#define iop_fifo_out 1280
-#define iop_scrc_in 1408
-#define iop_scrc_out 1536
-#define iop_timer_grp0 1664
-#define iop_timer_grp1 1792
-#define iop_sap_in 2048
-#define iop_sap_out 2304
-#define iop_spu 2560
-#define iop_sw_cfg 2816
-#define iop_sw_cpu 3072
-#define iop_sw_mpu 3328
-#define iop_sw_spu 3584
-#define iop_mpu 4096
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h
deleted file mode 100644
index 7f90b5a0460d..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h
+++ /dev/null
@@ -1,109 +0,0 @@
-#ifndef __iop_sap_in_defs_asm_h
-#define __iop_sap_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           iop_sap_in.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_iop_sap_in_rw_bus_byte 4
-/* Register rw_bus_byte, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0
-#define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2
-#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2
-#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3
-#define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5
-#define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2
-#define reg_iop_sap_in_rw_bus_byte___delay___lsb 7
-#define reg_iop_sap_in_rw_bus_byte___delay___width 2
-#define reg_iop_sap_in_rw_bus_byte_offset 0
-
-#define STRIDE_iop_sap_in_rw_gio 4
-/* Register rw_gio, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
-#define reg_iop_sap_in_rw_gio___sync_sel___width 2
-#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
-#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
-#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
-#define reg_iop_sap_in_rw_gio___sync_edge___width 2
-#define reg_iop_sap_in_rw_gio___delay___lsb 7
-#define reg_iop_sap_in_rw_gio___delay___width 2
-#define reg_iop_sap_in_rw_gio___logic___lsb 9
-#define reg_iop_sap_in_rw_gio___logic___width 2
-#define reg_iop_sap_in_rw_gio_offset 16
-
-
-/* Constants */
-#define regk_iop_sap_in_and                       0x00000002
-#define regk_iop_sap_in_ext_clk200                0x00000003
-#define regk_iop_sap_in_gio0                      0x00000000
-#define regk_iop_sap_in_gio12                     0x00000003
-#define regk_iop_sap_in_gio16                     0x00000004
-#define regk_iop_sap_in_gio20                     0x00000005
-#define regk_iop_sap_in_gio24                     0x00000006
-#define regk_iop_sap_in_gio28                     0x00000007
-#define regk_iop_sap_in_gio4                      0x00000001
-#define regk_iop_sap_in_gio8                      0x00000002
-#define regk_iop_sap_in_inv                       0x00000001
-#define regk_iop_sap_in_neg                       0x00000002
-#define regk_iop_sap_in_no                        0x00000000
-#define regk_iop_sap_in_no_del_ext_clk200         0x00000002
-#define regk_iop_sap_in_none                      0x00000000
-#define regk_iop_sap_in_one                       0x00000001
-#define regk_iop_sap_in_or                        0x00000003
-#define regk_iop_sap_in_pos                       0x00000001
-#define regk_iop_sap_in_pos_neg                   0x00000003
-#define regk_iop_sap_in_rw_bus_byte_default       0x00000000
-#define regk_iop_sap_in_rw_bus_byte_size          0x00000004
-#define regk_iop_sap_in_rw_gio_default            0x00000000
-#define regk_iop_sap_in_rw_gio_size               0x00000020
-#define regk_iop_sap_in_timer_grp0_tmr3           0x00000000
-#define regk_iop_sap_in_timer_grp1_tmr3           0x00000001
-#define regk_iop_sap_in_tmr_clk200                0x00000001
-#define regk_iop_sap_in_two                       0x00000002
-#define regk_iop_sap_in_two_clk200                0x00000000
-#endif /* __iop_sap_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h
deleted file mode 100644
index 399bd656406b..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h
+++ /dev/null
@@ -1,276 +0,0 @@
-#ifndef __iop_sap_out_defs_asm_h
-#define __iop_sap_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           iop_sap_out.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_gen_gated, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0
-#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4
-#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7
-#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9
-#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11
-#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated_offset 0
-
-/* Register rw_bus, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2
-#define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4
-#define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4
-#define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5
-#define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5
-#define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6
-#define reg_iop_sap_out_rw_bus___byte0_delay___width 1
-#define reg_iop_sap_out_rw_bus___byte0_delay___bit 6
-#define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7
-#define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9
-#define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11
-#define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11
-#define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12
-#define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12
-#define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13
-#define reg_iop_sap_out_rw_bus___byte1_delay___width 1
-#define reg_iop_sap_out_rw_bus___byte1_delay___bit 13
-#define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14
-#define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16
-#define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18
-#define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18
-#define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20
-#define reg_iop_sap_out_rw_bus___byte2_delay___width 1
-#define reg_iop_sap_out_rw_bus___byte2_delay___bit 20
-#define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21
-#define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23
-#define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25
-#define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25
-#define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26
-#define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26
-#define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27
-#define reg_iop_sap_out_rw_bus___byte3_delay___width 1
-#define reg_iop_sap_out_rw_bus___byte3_delay___bit 27
-#define reg_iop_sap_out_rw_bus_offset 4
-
-/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe_offset 8
-
-/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe_offset 12
-
-#define STRIDE_iop_sap_out_rw_gio 4
-/* Register rw_gio, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3
-#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_gio___out_clk_ext___width 2
-#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5
-#define reg_iop_sap_out_rw_gio___out_gated_clk___width 1
-#define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5
-#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6
-#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1
-#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6
-#define reg_iop_sap_out_rw_gio___out_delay___lsb 7
-#define reg_iop_sap_out_rw_gio___out_delay___width 1
-#define reg_iop_sap_out_rw_gio___out_delay___bit 7
-#define reg_iop_sap_out_rw_gio___out_logic___lsb 8
-#define reg_iop_sap_out_rw_gio___out_logic___width 2
-#define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10
-#define reg_iop_sap_out_rw_gio___out_logic_src___width 2
-#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12
-#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3
-#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15
-#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2
-#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1
-#define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18
-#define reg_iop_sap_out_rw_gio___oe_delay___lsb 19
-#define reg_iop_sap_out_rw_gio___oe_delay___width 1
-#define reg_iop_sap_out_rw_gio___oe_delay___bit 19
-#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20
-#define reg_iop_sap_out_rw_gio___oe_logic___width 2
-#define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22
-#define reg_iop_sap_out_rw_gio___oe_logic_src___width 2
-#define reg_iop_sap_out_rw_gio_offset 16
-
-
-/* Constants */
-#define regk_iop_sap_out_always                   0x00000001
-#define regk_iop_sap_out_and                      0x00000002
-#define regk_iop_sap_out_clk0                     0x00000000
-#define regk_iop_sap_out_clk1                     0x00000001
-#define regk_iop_sap_out_clk12                    0x00000004
-#define regk_iop_sap_out_clk200                   0x00000000
-#define regk_iop_sap_out_ext                      0x00000002
-#define regk_iop_sap_out_gated                    0x00000003
-#define regk_iop_sap_out_gio0                     0x00000000
-#define regk_iop_sap_out_gio1                     0x00000000
-#define regk_iop_sap_out_gio16                    0x00000002
-#define regk_iop_sap_out_gio17                    0x00000002
-#define regk_iop_sap_out_gio24                    0x00000003
-#define regk_iop_sap_out_gio25                    0x00000003
-#define regk_iop_sap_out_gio8                     0x00000001
-#define regk_iop_sap_out_gio9                     0x00000001
-#define regk_iop_sap_out_gio_out10                0x00000005
-#define regk_iop_sap_out_gio_out18                0x00000006
-#define regk_iop_sap_out_gio_out2                 0x00000004
-#define regk_iop_sap_out_gio_out26                0x00000007
-#define regk_iop_sap_out_inv                      0x00000001
-#define regk_iop_sap_out_nand                     0x00000003
-#define regk_iop_sap_out_no                       0x00000000
-#define regk_iop_sap_out_none                     0x00000000
-#define regk_iop_sap_out_one                      0x00000001
-#define regk_iop_sap_out_rw_bus_default           0x00000000
-#define regk_iop_sap_out_rw_bus_hi_oe_default     0x00000000
-#define regk_iop_sap_out_rw_bus_lo_oe_default     0x00000000
-#define regk_iop_sap_out_rw_gen_gated_default     0x00000000
-#define regk_iop_sap_out_rw_gio_default           0x00000000
-#define regk_iop_sap_out_rw_gio_size              0x00000020
-#define regk_iop_sap_out_spu_gio6                 0x00000002
-#define regk_iop_sap_out_spu_gio7                 0x00000003
-#define regk_iop_sap_out_timer_grp0_tmr2          0x00000000
-#define regk_iop_sap_out_timer_grp0_tmr3          0x00000001
-#define regk_iop_sap_out_timer_grp1_tmr2          0x00000002
-#define regk_iop_sap_out_timer_grp1_tmr3          0x00000003
-#define regk_iop_sap_out_tmr200                   0x00000001
-#define regk_iop_sap_out_yes                      0x00000001
-#endif /* __iop_sap_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
deleted file mode 100644
index 3b3949b51a66..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
+++ /dev/null
@@ -1,739 +0,0 @@
-#ifndef __iop_sw_cfg_defs_asm_h
-#define __iop_sw_cfg_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           iop_sw_cfg.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_crc_par_owner_offset 0
-
-/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4
-
-/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8
-
-/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12
-
-/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16
-
-/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20
-
-/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24
-
-/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_sap_in_owner_offset 28
-
-/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_sap_out_owner_offset 32
-
-/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36
-
-/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40
-
-/* Register rw_spu_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1
-#define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0
-#define reg_iop_sw_cfg_rw_spu_owner_offset 44
-
-/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48
-
-/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52
-
-/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56
-
-/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60
-
-/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64
-
-/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68
-
-/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72
-
-/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76
-
-/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80
-
-/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84
-
-/* Register rw_bus_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8
-#define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8
-#define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8
-#define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16
-#define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8
-#define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24
-#define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8
-#define reg_iop_sw_cfg_rw_bus_mask_offset 88
-
-/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3
-#define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92
-
-/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0
-#define reg_iop_sw_cfg_rw_gio_mask___val___width 32
-#define reg_iop_sw_cfg_rw_gio_mask_offset 96
-
-/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0
-#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32
-#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100
-
-/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8
-#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10
-#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12
-#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14
-#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16
-#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18
-#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20
-#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22
-#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2
-#define reg_iop_sw_cfg_rw_pinmapping_offset 104
-
-/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2
-#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108
-
-/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 112
-
-/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 116
-
-/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 120
-
-/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 124
-
-/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 128
-
-/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 132
-
-/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 136
-
-/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 140
-
-/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___lsb 0
-#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___width 1
-#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___bit 0
-#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___lsb 1
-#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___width 1
-#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___bit 1
-#define reg_iop_sw_cfg_rw_spu_cfg_offset 144
-
-/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 11
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 13
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 15
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 17
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 148
-
-/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 11
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 13
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 15
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 17
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 152
-
-/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156
-
-/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0
-#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4
-#define reg_iop_sw_cfg_rw_pdp_cfg_offset 160
-
-/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg_offset 164
-
-
-/* Constants */
-#define regk_iop_sw_cfg_a                         0x00000001
-#define regk_iop_sw_cfg_b                         0x00000002
-#define regk_iop_sw_cfg_bus                       0x00000000
-#define regk_iop_sw_cfg_bus_rot16                 0x00000002
-#define regk_iop_sw_cfg_bus_rot24                 0x00000003
-#define regk_iop_sw_cfg_bus_rot8                  0x00000001
-#define regk_iop_sw_cfg_clk12                     0x00000000
-#define regk_iop_sw_cfg_cpu                       0x00000000
-#define regk_iop_sw_cfg_gated_clk0                0x0000000e
-#define regk_iop_sw_cfg_gated_clk1                0x0000000f
-#define regk_iop_sw_cfg_gio0                      0x00000004
-#define regk_iop_sw_cfg_gio1                      0x00000001
-#define regk_iop_sw_cfg_gio2                      0x00000005
-#define regk_iop_sw_cfg_gio3                      0x00000002
-#define regk_iop_sw_cfg_gio4                      0x00000006
-#define regk_iop_sw_cfg_gio5                      0x00000003
-#define regk_iop_sw_cfg_gio6                      0x00000007
-#define regk_iop_sw_cfg_gio7                      0x00000004
-#define regk_iop_sw_cfg_gio_in18                  0x00000002
-#define regk_iop_sw_cfg_gio_in19                  0x00000003
-#define regk_iop_sw_cfg_gio_in20                  0x00000004
-#define regk_iop_sw_cfg_gio_in21                  0x00000005
-#define regk_iop_sw_cfg_gio_in26                  0x00000006
-#define regk_iop_sw_cfg_gio_in27                  0x00000007
-#define regk_iop_sw_cfg_gio_in4                   0x00000000
-#define regk_iop_sw_cfg_gio_in5                   0x00000001
-#define regk_iop_sw_cfg_last_timer_grp0_tmr2      0x00000001
-#define regk_iop_sw_cfg_last_timer_grp1_tmr2      0x00000002
-#define regk_iop_sw_cfg_last_timer_grp1_tmr3      0x00000003
-#define regk_iop_sw_cfg_mpu                       0x00000001
-#define regk_iop_sw_cfg_none                      0x00000000
-#define regk_iop_sw_cfg_pdp_out                   0x00000001
-#define regk_iop_sw_cfg_pdp_out_hi                0x00000001
-#define regk_iop_sw_cfg_pdp_out_lo                0x00000000
-#define regk_iop_sw_cfg_rw_bus_mask_default       0x00000000
-#define regk_iop_sw_cfg_rw_bus_oe_mask_default    0x00000000
-#define regk_iop_sw_cfg_rw_bus_out_cfg_default    0x00000000
-#define regk_iop_sw_cfg_rw_crc_par_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_dmc_in_owner_default   0x00000000
-#define regk_iop_sw_cfg_rw_dmc_out_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_mask_default       0x00000000
-#define regk_iop_sw_cfg_rw_gio_oe_mask_default    0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_pdp_cfg_default        0x00000000
-#define regk_iop_sw_cfg_rw_pinmapping_default     0x00555555
-#define regk_iop_sw_cfg_rw_sap_in_owner_default   0x00000000
-#define regk_iop_sw_cfg_rw_sap_out_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_scrc_in_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_scrc_out_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_sdp_cfg_default        0x00000000
-#define regk_iop_sw_cfg_rw_spu_cfg_default        0x00000000
-#define regk_iop_sw_cfg_rw_spu_owner_default      0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default  0x00000000
-#define regk_iop_sw_cfg_sdp_out                   0x00000004
-#define regk_iop_sw_cfg_size16                    0x00000002
-#define regk_iop_sw_cfg_size24                    0x00000003
-#define regk_iop_sw_cfg_size32                    0x00000004
-#define regk_iop_sw_cfg_size8                     0x00000001
-#define regk_iop_sw_cfg_spu                       0x00000002
-#define regk_iop_sw_cfg_spu_bus_out0_hi           0x00000002
-#define regk_iop_sw_cfg_spu_bus_out0_lo           0x00000002
-#define regk_iop_sw_cfg_spu_bus_out1_hi           0x00000003
-#define regk_iop_sw_cfg_spu_bus_out1_lo           0x00000003
-#define regk_iop_sw_cfg_spu_g0                    0x00000007
-#define regk_iop_sw_cfg_spu_g1                    0x00000007
-#define regk_iop_sw_cfg_spu_g2                    0x00000007
-#define regk_iop_sw_cfg_spu_g3                    0x00000007
-#define regk_iop_sw_cfg_spu_g4                    0x00000007
-#define regk_iop_sw_cfg_spu_g5                    0x00000007
-#define regk_iop_sw_cfg_spu_g6                    0x00000007
-#define regk_iop_sw_cfg_spu_g7                    0x00000007
-#define regk_iop_sw_cfg_spu_gio0                  0x00000000
-#define regk_iop_sw_cfg_spu_gio1                  0x00000001
-#define regk_iop_sw_cfg_spu_gio5                  0x00000005
-#define regk_iop_sw_cfg_spu_gio6                  0x00000006
-#define regk_iop_sw_cfg_spu_gio7                  0x00000007
-#define regk_iop_sw_cfg_spu_gio_out0              0x00000008
-#define regk_iop_sw_cfg_spu_gio_out1              0x00000009
-#define regk_iop_sw_cfg_spu_gio_out2              0x0000000a
-#define regk_iop_sw_cfg_spu_gio_out3              0x0000000b
-#define regk_iop_sw_cfg_spu_gio_out4              0x0000000c
-#define regk_iop_sw_cfg_spu_gio_out5              0x0000000d
-#define regk_iop_sw_cfg_spu_gio_out6              0x0000000e
-#define regk_iop_sw_cfg_spu_gio_out7              0x0000000f
-#define regk_iop_sw_cfg_spu_gioout0               0x00000000
-#define regk_iop_sw_cfg_spu_gioout1               0x00000000
-#define regk_iop_sw_cfg_spu_gioout10              0x00000007
-#define regk_iop_sw_cfg_spu_gioout11              0x00000007
-#define regk_iop_sw_cfg_spu_gioout12              0x00000007
-#define regk_iop_sw_cfg_spu_gioout13              0x00000007
-#define regk_iop_sw_cfg_spu_gioout14              0x00000007
-#define regk_iop_sw_cfg_spu_gioout15              0x00000007
-#define regk_iop_sw_cfg_spu_gioout16              0x00000007
-#define regk_iop_sw_cfg_spu_gioout17              0x00000007
-#define regk_iop_sw_cfg_spu_gioout18              0x00000007
-#define regk_iop_sw_cfg_spu_gioout19              0x00000007
-#define regk_iop_sw_cfg_spu_gioout2               0x00000001
-#define regk_iop_sw_cfg_spu_gioout20              0x00000007
-#define regk_iop_sw_cfg_spu_gioout21              0x00000007
-#define regk_iop_sw_cfg_spu_gioout22              0x00000007
-#define regk_iop_sw_cfg_spu_gioout23              0x00000007
-#define regk_iop_sw_cfg_spu_gioout24              0x00000007
-#define regk_iop_sw_cfg_spu_gioout25              0x00000007
-#define regk_iop_sw_cfg_spu_gioout26              0x00000007
-#define regk_iop_sw_cfg_spu_gioout27              0x00000007
-#define regk_iop_sw_cfg_spu_gioout28              0x00000007
-#define regk_iop_sw_cfg_spu_gioout29              0x00000007
-#define regk_iop_sw_cfg_spu_gioout3               0x00000001
-#define regk_iop_sw_cfg_spu_gioout30              0x00000007
-#define regk_iop_sw_cfg_spu_gioout31              0x00000007
-#define regk_iop_sw_cfg_spu_gioout4               0x00000002
-#define regk_iop_sw_cfg_spu_gioout5               0x00000002
-#define regk_iop_sw_cfg_spu_gioout6               0x00000003
-#define regk_iop_sw_cfg_spu_gioout7               0x00000003
-#define regk_iop_sw_cfg_spu_gioout8               0x00000007
-#define regk_iop_sw_cfg_spu_gioout9               0x00000007
-#define regk_iop_sw_cfg_strb_timer_grp0_tmr0      0x00000001
-#define regk_iop_sw_cfg_strb_timer_grp0_tmr1      0x00000002
-#define regk_iop_sw_cfg_strb_timer_grp1_tmr0      0x00000003
-#define regk_iop_sw_cfg_strb_timer_grp1_tmr1      0x00000002
-#define regk_iop_sw_cfg_timer_grp0                0x00000000
-#define regk_iop_sw_cfg_timer_grp0_rot            0x00000001
-#define regk_iop_sw_cfg_timer_grp0_strb0          0x00000005
-#define regk_iop_sw_cfg_timer_grp0_strb1          0x00000005
-#define regk_iop_sw_cfg_timer_grp0_strb2          0x00000005
-#define regk_iop_sw_cfg_timer_grp0_strb3          0x00000005
-#define regk_iop_sw_cfg_timer_grp0_tmr0           0x00000002
-#define regk_iop_sw_cfg_timer_grp1                0x00000000
-#define regk_iop_sw_cfg_timer_grp1_rot            0x00000001
-#define regk_iop_sw_cfg_timer_grp1_strb0          0x00000006
-#define regk_iop_sw_cfg_timer_grp1_strb1          0x00000006
-#define regk_iop_sw_cfg_timer_grp1_strb2          0x00000006
-#define regk_iop_sw_cfg_timer_grp1_strb3          0x00000006
-#define regk_iop_sw_cfg_timer_grp1_tmr0           0x00000003
-#define regk_iop_sw_cfg_trig0_0                   0x00000000
-#define regk_iop_sw_cfg_trig0_1                   0x00000000
-#define regk_iop_sw_cfg_trig0_2                   0x00000000
-#define regk_iop_sw_cfg_trig0_3                   0x00000000
-#define regk_iop_sw_cfg_trig1_0                   0x00000000
-#define regk_iop_sw_cfg_trig1_1                   0x00000000
-#define regk_iop_sw_cfg_trig1_2                   0x00000000
-#define regk_iop_sw_cfg_trig1_3                   0x00000000
-#define regk_iop_sw_cfg_trig2_0                   0x00000001
-#define regk_iop_sw_cfg_trig2_1                   0x00000001
-#define regk_iop_sw_cfg_trig2_2                   0x00000001
-#define regk_iop_sw_cfg_trig2_3                   0x00000001
-#define regk_iop_sw_cfg_trig3_0                   0x00000001
-#define regk_iop_sw_cfg_trig3_1                   0x00000001
-#define regk_iop_sw_cfg_trig3_2                   0x00000001
-#define regk_iop_sw_cfg_trig3_3                   0x00000001
-#define regk_iop_sw_cfg_trig4_0                   0x00000002
-#define regk_iop_sw_cfg_trig4_1                   0x00000002
-#define regk_iop_sw_cfg_trig4_2                   0x00000002
-#define regk_iop_sw_cfg_trig4_3                   0x00000002
-#define regk_iop_sw_cfg_trig5_0                   0x00000002
-#define regk_iop_sw_cfg_trig5_1                   0x00000002
-#define regk_iop_sw_cfg_trig5_2                   0x00000002
-#define regk_iop_sw_cfg_trig5_3                   0x00000002
-#define regk_iop_sw_cfg_trig6_0                   0x00000003
-#define regk_iop_sw_cfg_trig6_1                   0x00000003
-#define regk_iop_sw_cfg_trig6_2                   0x00000003
-#define regk_iop_sw_cfg_trig6_3                   0x00000003
-#define regk_iop_sw_cfg_trig7_0                   0x00000003
-#define regk_iop_sw_cfg_trig7_1                   0x00000003
-#define regk_iop_sw_cfg_trig7_2                   0x00000003
-#define regk_iop_sw_cfg_trig7_3                   0x00000003
-#endif /* __iop_sw_cfg_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
deleted file mode 100644
index 3f4fe1b31815..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
+++ /dev/null
@@ -1,950 +0,0 @@
-#ifndef __iop_sw_cpu_defs_asm_h
-#define __iop_sw_cpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           iop_sw_cpu.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cpu_defs_asm.h iop_sw_cpu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_mpu_trace, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_mpu_trace_offset 0
-
-/* Register r_spu_trace, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_spu_trace_offset 4
-
-/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_spu_fsm_trace_offset 8
-
-/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___lsb 6
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___bit 6
-#define reg_iop_sw_cpu_rw_mc_ctrl_offset 12
-
-/* Register rw_mc_data, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_cpu_rw_mc_data___val___width 32
-#define reg_iop_sw_cpu_rw_mc_data_offset 16
-
-/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_addr_offset 20
-
-/* Register rs_mc_data, scope iop_sw_cpu, type rs */
-#define reg_iop_sw_cpu_rs_mc_data_offset 24
-
-/* Register r_mc_data, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_mc_data_offset 28
-
-/* Register r_mc_stat, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu___lsb 2
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu___bit 2
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 3
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 3
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 4
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 4
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___lsb 5
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___bit 5
-#define reg_iop_sw_cpu_r_mc_stat_offset 32
-
-/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus_clr_mask_offset 36
-
-/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus_set_mask_offset 40
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask_offset 44
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask_offset 48
-
-/* Register r_bus_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_bus_in_offset 52
-
-/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 56
-
-/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_set_mask_offset 60
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 64
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 68
-
-/* Register r_gio_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_gio_in_offset 72
-
-/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___lsb 16
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___bit 16
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___lsb 17
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___bit 17
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___lsb 18
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___bit 18
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___lsb 19
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___bit 19
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___lsb 20
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___bit 20
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___lsb 21
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___bit 21
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___lsb 22
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___bit 22
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___lsb 23
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___bit 23
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___lsb 24
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___bit 24
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___lsb 25
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___bit 25
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___lsb 26
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___bit 26
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___lsb 27
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___bit 27
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___lsb 28
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___bit 28
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___lsb 29
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___bit 29
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___lsb 30
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___bit 30
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___lsb 31
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___bit 31
-#define reg_iop_sw_cpu_rw_intr0_mask_offset 76
-
-/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___lsb 16
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___bit 16
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___lsb 17
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___bit 17
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___lsb 18
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___bit 18
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___lsb 19
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___bit 19
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___lsb 20
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___bit 20
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___lsb 21
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___bit 21
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___lsb 22
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___bit 22
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___lsb 23
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___bit 23
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___lsb 24
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___bit 24
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___lsb 25
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___bit 25
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___lsb 26
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___bit 26
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___lsb 27
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___bit 27
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___lsb 28
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___bit 28
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___lsb 29
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___bit 29
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___lsb 30
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___bit 30
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___lsb 31
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___bit 31
-#define reg_iop_sw_cpu_rw_ack_intr0_offset 80
-
-/* Register r_intr0, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_r_intr0___spu_0___lsb 16
-#define reg_iop_sw_cpu_r_intr0___spu_0___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_0___bit 16
-#define reg_iop_sw_cpu_r_intr0___spu_1___lsb 17
-#define reg_iop_sw_cpu_r_intr0___spu_1___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_1___bit 17
-#define reg_iop_sw_cpu_r_intr0___spu_2___lsb 18
-#define reg_iop_sw_cpu_r_intr0___spu_2___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_2___bit 18
-#define reg_iop_sw_cpu_r_intr0___spu_3___lsb 19
-#define reg_iop_sw_cpu_r_intr0___spu_3___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_3___bit 19
-#define reg_iop_sw_cpu_r_intr0___spu_4___lsb 20
-#define reg_iop_sw_cpu_r_intr0___spu_4___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_4___bit 20
-#define reg_iop_sw_cpu_r_intr0___spu_5___lsb 21
-#define reg_iop_sw_cpu_r_intr0___spu_5___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_5___bit 21
-#define reg_iop_sw_cpu_r_intr0___spu_6___lsb 22
-#define reg_iop_sw_cpu_r_intr0___spu_6___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_6___bit 22
-#define reg_iop_sw_cpu_r_intr0___spu_7___lsb 23
-#define reg_iop_sw_cpu_r_intr0___spu_7___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_7___bit 23
-#define reg_iop_sw_cpu_r_intr0___spu_8___lsb 24
-#define reg_iop_sw_cpu_r_intr0___spu_8___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_8___bit 24
-#define reg_iop_sw_cpu_r_intr0___spu_9___lsb 25
-#define reg_iop_sw_cpu_r_intr0___spu_9___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_9___bit 25
-#define reg_iop_sw_cpu_r_intr0___spu_10___lsb 26
-#define reg_iop_sw_cpu_r_intr0___spu_10___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_10___bit 26
-#define reg_iop_sw_cpu_r_intr0___spu_11___lsb 27
-#define reg_iop_sw_cpu_r_intr0___spu_11___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_11___bit 27
-#define reg_iop_sw_cpu_r_intr0___spu_12___lsb 28
-#define reg_iop_sw_cpu_r_intr0___spu_12___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_12___bit 28
-#define reg_iop_sw_cpu_r_intr0___spu_13___lsb 29
-#define reg_iop_sw_cpu_r_intr0___spu_13___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_13___bit 29
-#define reg_iop_sw_cpu_r_intr0___spu_14___lsb 30
-#define reg_iop_sw_cpu_r_intr0___spu_14___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_14___bit 30
-#define reg_iop_sw_cpu_r_intr0___spu_15___lsb 31
-#define reg_iop_sw_cpu_r_intr0___spu_15___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_15___bit 31
-#define reg_iop_sw_cpu_r_intr0_offset 84
-
-/* Register r_masked_intr0, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_r_masked_intr0___spu_0___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr0___spu_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_0___bit 16
-#define reg_iop_sw_cpu_r_masked_intr0___spu_1___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr0___spu_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_1___bit 17
-#define reg_iop_sw_cpu_r_masked_intr0___spu_2___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr0___spu_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_2___bit 18
-#define reg_iop_sw_cpu_r_masked_intr0___spu_3___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr0___spu_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_3___bit 19
-#define reg_iop_sw_cpu_r_masked_intr0___spu_4___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr0___spu_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_4___bit 20
-#define reg_iop_sw_cpu_r_masked_intr0___spu_5___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr0___spu_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_5___bit 21
-#define reg_iop_sw_cpu_r_masked_intr0___spu_6___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr0___spu_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_6___bit 22
-#define reg_iop_sw_cpu_r_masked_intr0___spu_7___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr0___spu_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_7___bit 23
-#define reg_iop_sw_cpu_r_masked_intr0___spu_8___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr0___spu_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_8___bit 24
-#define reg_iop_sw_cpu_r_masked_intr0___spu_9___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr0___spu_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_9___bit 25
-#define reg_iop_sw_cpu_r_masked_intr0___spu_10___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr0___spu_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_10___bit 26
-#define reg_iop_sw_cpu_r_masked_intr0___spu_11___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr0___spu_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_11___bit 27
-#define reg_iop_sw_cpu_r_masked_intr0___spu_12___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr0___spu_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_12___bit 28
-#define reg_iop_sw_cpu_r_masked_intr0___spu_13___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr0___spu_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_13___bit 29
-#define reg_iop_sw_cpu_r_masked_intr0___spu_14___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr0___spu_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_14___bit 30
-#define reg_iop_sw_cpu_r_masked_intr0___spu_15___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr0___spu_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_15___bit 31
-#define reg_iop_sw_cpu_r_masked_intr0_offset 88
-
-/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___lsb 16
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___bit 16
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___lsb 17
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___bit 17
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___lsb 18
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___bit 18
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___lsb 19
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___bit 19
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___lsb 20
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___bit 20
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___lsb 21
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___bit 21
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___bit 30
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___bit 31
-#define reg_iop_sw_cpu_rw_intr1_mask_offset 92
-
-/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr1_offset 96
-
-/* Register r_intr1, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16
-#define reg_iop_sw_cpu_r_intr1___dmc_in___width 1
-#define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16
-#define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17
-#define reg_iop_sw_cpu_r_intr1___dmc_out___width 1
-#define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17
-#define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18
-#define reg_iop_sw_cpu_r_intr1___fifo_in___width 1
-#define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18
-#define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19
-#define reg_iop_sw_cpu_r_intr1___fifo_out___width 1
-#define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19
-#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20
-#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1
-#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20
-#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21
-#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1
-#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21
-#define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1
-#define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30
-#define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1
-#define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31
-#define reg_iop_sw_cpu_r_intr1_offset 100
-
-/* Register r_masked_intr1, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31
-#define reg_iop_sw_cpu_r_masked_intr1_offset 104
-
-
-/* Constants */
-#define regk_iop_sw_cpu_copy                      0x00000000
-#define regk_iop_sw_cpu_no                        0x00000000
-#define regk_iop_sw_cpu_rd                        0x00000002
-#define regk_iop_sw_cpu_reg_copy                  0x00000001
-#define regk_iop_sw_cpu_rw_bus_clr_mask_default   0x00000000
-#define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_bus_oe_set_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_bus_set_mask_default   0x00000000
-#define regk_iop_sw_cpu_rw_gio_clr_mask_default   0x00000000
-#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_gio_set_mask_default   0x00000000
-#define regk_iop_sw_cpu_rw_intr0_mask_default     0x00000000
-#define regk_iop_sw_cpu_rw_intr1_mask_default     0x00000000
-#define regk_iop_sw_cpu_wr                        0x00000003
-#define regk_iop_sw_cpu_yes                       0x00000001
-#endif /* __iop_sw_cpu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
deleted file mode 100644
index ffcc83b22d21..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
+++ /dev/null
@@ -1,1086 +0,0 @@
-#ifndef __iop_sw_mpu_defs_asm_h
-#define __iop_sw_mpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           iop_sw_mpu.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_mpu_defs_asm.h iop_sw_mpu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0
-#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2
-#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0
-
-/* Register r_spu_trace, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_spu_trace_offset 4
-
-/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_spu_fsm_trace_offset 8
-
-/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___lsb 6
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___bit 6
-#define reg_iop_sw_mpu_rw_mc_ctrl_offset 12
-
-/* Register rw_mc_data, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_mpu_rw_mc_data___val___width 32
-#define reg_iop_sw_mpu_rw_mc_data_offset 16
-
-/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_addr_offset 20
-
-/* Register rs_mc_data, scope iop_sw_mpu, type rs */
-#define reg_iop_sw_mpu_rs_mc_data_offset 24
-
-/* Register r_mc_data, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_mc_data_offset 28
-
-/* Register r_mc_stat, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu___lsb 2
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu___bit 2
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 3
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 3
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 4
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 4
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___lsb 5
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___bit 5
-#define reg_iop_sw_mpu_r_mc_stat_offset 32
-
-/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus_clr_mask_offset 36
-
-/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus_set_mask_offset 40
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask_offset 44
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask_offset 48
-
-/* Register r_bus_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_bus_in_offset 52
-
-/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 56
-
-/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_set_mask_offset 60
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 64
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 68
-
-/* Register r_gio_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_gio_in_offset 72
-
-/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31
-#define reg_iop_sw_mpu_rw_cpu_intr_offset 76
-
-/* Register r_cpu_intr, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31
-#define reg_iop_sw_mpu_r_cpu_intr_offset 80
-
-/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 84
-
-/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___lsb 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___bit 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___lsb 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___bit 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 88
-
-/* Register r_intr_grp0, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___bit 0
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___bit 3
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___bit 4
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 6
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___bit 7
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___bit 8
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___bit 11
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___bit 12
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___bit 15
-#define reg_iop_sw_mpu_r_intr_grp0_offset 92
-
-/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 96
-
-/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 100
-
-/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___lsb 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___bit 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___lsb 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___bit 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 104
-
-/* Register r_intr_grp1, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___bit 0
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___bit 3
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___bit 4
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___bit 7
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___bit 8
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 10
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___bit 11
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___bit 12
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 14
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___bit 15
-#define reg_iop_sw_mpu_r_intr_grp1_offset 108
-
-/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 112
-
-/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 116
-
-/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___lsb 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___bit 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___lsb 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___bit 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 120
-
-/* Register r_intr_grp2, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___bit 0
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___bit 3
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___bit 4
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 6
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___bit 7
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___bit 8
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___bit 11
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___bit 12
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___bit 15
-#define reg_iop_sw_mpu_r_intr_grp2_offset 124
-
-/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 128
-
-/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 132
-
-/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___lsb 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___bit 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___lsb 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___bit 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 136
-
-/* Register r_intr_grp3, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___bit 0
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___bit 3
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___bit 4
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___bit 7
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___bit 8
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 10
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___bit 11
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___bit 12
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 14
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___bit 15
-#define reg_iop_sw_mpu_r_intr_grp3_offset 140
-
-/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 144
-
-
-/* Constants */
-#define regk_iop_sw_mpu_copy                      0x00000000
-#define regk_iop_sw_mpu_cpu                       0x00000000
-#define regk_iop_sw_mpu_mpu                       0x00000001
-#define regk_iop_sw_mpu_no                        0x00000000
-#define regk_iop_sw_mpu_nop                       0x00000000
-#define regk_iop_sw_mpu_rd                        0x00000002
-#define regk_iop_sw_mpu_reg_copy                  0x00000001
-#define regk_iop_sw_mpu_rw_bus_clr_mask_default   0x00000000
-#define regk_iop_sw_mpu_rw_bus_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_bus_oe_set_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_bus_set_mask_default   0x00000000
-#define regk_iop_sw_mpu_rw_gio_clr_mask_default   0x00000000
-#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_gio_set_mask_default   0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp0_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp1_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp2_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp3_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_sw_cfg_owner_default   0x00000000
-#define regk_iop_sw_mpu_set                       0x00000001
-#define regk_iop_sw_mpu_spu                       0x00000002
-#define regk_iop_sw_mpu_wr                        0x00000003
-#define regk_iop_sw_mpu_yes                       0x00000001
-#endif /* __iop_sw_mpu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h
deleted file mode 100644
index 67a745338087..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h
+++ /dev/null
@@ -1,523 +0,0 @@
-#ifndef __iop_sw_spu_defs_asm_h
-#define __iop_sw_spu_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           iop_sw_spu.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_spu_defs_asm.h iop_sw_spu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_mpu_trace, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mpu_trace_offset 0
-
-/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___lsb 6
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___bit 6
-#define reg_iop_sw_spu_rw_mc_ctrl_offset 4
-
-/* Register rw_mc_data, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_spu_rw_mc_data___val___width 32
-#define reg_iop_sw_spu_rw_mc_data_offset 8
-
-/* Register rw_mc_addr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_addr_offset 12
-
-/* Register rs_mc_data, scope iop_sw_spu, type rs */
-#define reg_iop_sw_spu_rs_mc_data_offset 16
-
-/* Register r_mc_data, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mc_data_offset 20
-
-/* Register r_mc_stat, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu___lsb 2
-#define reg_iop_sw_spu_r_mc_stat___busy_spu___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu___bit 2
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 3
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 3
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 4
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 4
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___lsb 5
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___bit 5
-#define reg_iop_sw_spu_r_mc_stat_offset 24
-
-/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_offset 28
-
-/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_set_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus_set_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus_set_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus_set_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask_offset 32
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask_offset 36
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus_oe_set_mask_offset 40
-
-/* Register r_bus_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_bus_in_offset 44
-
-/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_clr_mask_offset 48
-
-/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_set_mask_offset 52
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 56
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 60
-
-/* Register r_gio_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_gio_in_offset 64
-
-/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_lo_offset 68
-
-/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_hi_offset 72
-
-/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask_lo_offset 76
-
-/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask_hi_offset 80
-
-/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 84
-
-/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88
-
-/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 92
-
-/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 96
-
-/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 100
-
-/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 104
-
-/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 108
-
-/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 112
-
-/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_rw_cpu_intr_offset 116
-
-/* Register r_cpu_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_r_cpu_intr_offset 120
-
-/* Register r_hw_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9
-#define reg_iop_sw_spu_r_hw_intr___fifo_out___lsb 10
-#define reg_iop_sw_spu_r_hw_intr___fifo_out___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out___bit 10
-#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___lsb 11
-#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___bit 11
-#define reg_iop_sw_spu_r_hw_intr___fifo_in___lsb 12
-#define reg_iop_sw_spu_r_hw_intr___fifo_in___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in___bit 12
-#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___lsb 13
-#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___bit 13
-#define reg_iop_sw_spu_r_hw_intr___dmc_out___lsb 14
-#define reg_iop_sw_spu_r_hw_intr___dmc_out___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_out___bit 14
-#define reg_iop_sw_spu_r_hw_intr___dmc_in___lsb 15
-#define reg_iop_sw_spu_r_hw_intr___dmc_in___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_in___bit 15
-#define reg_iop_sw_spu_r_hw_intr_offset 124
-
-/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_rw_mpu_intr_offset 128
-
-/* Register r_mpu_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_r_mpu_intr_offset 132
-
-
-/* Constants */
-#define regk_iop_sw_spu_copy                      0x00000000
-#define regk_iop_sw_spu_no                        0x00000000
-#define regk_iop_sw_spu_nop                       0x00000000
-#define regk_iop_sw_spu_rd                        0x00000002
-#define regk_iop_sw_spu_reg_copy                  0x00000001
-#define regk_iop_sw_spu_rw_bus_clr_mask_default   0x00000000
-#define regk_iop_sw_spu_rw_bus_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_bus_oe_set_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_bus_set_mask_default   0x00000000
-#define regk_iop_sw_spu_rw_gio_clr_mask_default   0x00000000
-#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_gio_oe_set_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_gio_set_mask_default   0x00000000
-#define regk_iop_sw_spu_set                       0x00000001
-#define regk_iop_sw_spu_wr                        0x00000003
-#define regk_iop_sw_spu_yes                       0x00000001
-#endif /* __iop_sw_spu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h
deleted file mode 100644
index 4ad671202af0..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef __iop_version_defs_asm_h
-#define __iop_version_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           iop_version.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_version_defs_asm.h iop_version.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_version, scope iop_version, type r */
-#define reg_iop_version_r_version___nr___lsb 0
-#define reg_iop_version_r_version___nr___width 8
-#define reg_iop_version_r_version_offset 0
-
-
-/* Constants */
-#define regk_iop_version_v2_0                     0x00000002
-#endif /* __iop_version_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h
deleted file mode 100644
index af3196c60a46..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Autogenerated Changes here will be lost!
- * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg 
- */
-#define regi_iop_version (regi_iop + 0)
-#define regi_iop_fifo_in_extra (regi_iop + 64)
-#define regi_iop_fifo_out_extra (regi_iop + 128)
-#define regi_iop_trigger_grp0 (regi_iop + 192)
-#define regi_iop_trigger_grp1 (regi_iop + 256)
-#define regi_iop_trigger_grp2 (regi_iop + 320)
-#define regi_iop_trigger_grp3 (regi_iop + 384)
-#define regi_iop_trigger_grp4 (regi_iop + 448)
-#define regi_iop_trigger_grp5 (regi_iop + 512)
-#define regi_iop_trigger_grp6 (regi_iop + 576)
-#define regi_iop_trigger_grp7 (regi_iop + 640)
-#define regi_iop_crc_par (regi_iop + 768)
-#define regi_iop_dmc_in (regi_iop + 896)
-#define regi_iop_dmc_out (regi_iop + 1024)
-#define regi_iop_fifo_in (regi_iop + 1152)
-#define regi_iop_fifo_out (regi_iop + 1280)
-#define regi_iop_scrc_in (regi_iop + 1408)
-#define regi_iop_scrc_out (regi_iop + 1536)
-#define regi_iop_timer_grp0 (regi_iop + 1664)
-#define regi_iop_timer_grp1 (regi_iop + 1792)
-#define regi_iop_sap_in (regi_iop + 2048)
-#define regi_iop_sap_out (regi_iop + 2304)
-#define regi_iop_spu (regi_iop + 2560)
-#define regi_iop_sw_cfg (regi_iop + 2816)
-#define regi_iop_sw_cpu (regi_iop + 3072)
-#define regi_iop_sw_mpu (regi_iop + 3328)
-#define regi_iop_sw_spu (regi_iop + 3584)
-#define regi_iop_mpu (regi_iop + 4096)
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h
deleted file mode 100644
index 51dde016c03a..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h
+++ /dev/null
@@ -1,141 +0,0 @@
-#ifndef __iop_sap_in_defs_h
-#define __iop_sap_in_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           iop_sap_in.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sap_in */
-
-#define STRIDE_iop_sap_in_rw_bus_byte 4
-/* Register rw_bus_byte, scope iop_sap_in, type rw */
-typedef struct {
-  unsigned int sync_sel     : 2;
-  unsigned int sync_ext_src : 3;
-  unsigned int sync_edge    : 2;
-  unsigned int delay        : 2;
-  unsigned int dummy1       : 23;
-} reg_iop_sap_in_rw_bus_byte;
-#define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0
-#define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0
-
-#define STRIDE_iop_sap_in_rw_gio 4
-/* Register rw_gio, scope iop_sap_in, type rw */
-typedef struct {
-  unsigned int sync_sel     : 2;
-  unsigned int sync_ext_src : 3;
-  unsigned int sync_edge    : 2;
-  unsigned int delay        : 2;
-  unsigned int logic        : 2;
-  unsigned int dummy1       : 21;
-} reg_iop_sap_in_rw_gio;
-#define REG_RD_ADDR_iop_sap_in_rw_gio 16
-#define REG_WR_ADDR_iop_sap_in_rw_gio 16
-
-
-/* Constants */
-enum {
-  regk_iop_sap_in_and                      = 0x00000002,
-  regk_iop_sap_in_ext_clk200               = 0x00000003,
-  regk_iop_sap_in_gio0                     = 0x00000000,
-  regk_iop_sap_in_gio12                    = 0x00000003,
-  regk_iop_sap_in_gio16                    = 0x00000004,
-  regk_iop_sap_in_gio20                    = 0x00000005,
-  regk_iop_sap_in_gio24                    = 0x00000006,
-  regk_iop_sap_in_gio28                    = 0x00000007,
-  regk_iop_sap_in_gio4                     = 0x00000001,
-  regk_iop_sap_in_gio8                     = 0x00000002,
-  regk_iop_sap_in_inv                      = 0x00000001,
-  regk_iop_sap_in_neg                      = 0x00000002,
-  regk_iop_sap_in_no                       = 0x00000000,
-  regk_iop_sap_in_no_del_ext_clk200        = 0x00000002,
-  regk_iop_sap_in_none                     = 0x00000000,
-  regk_iop_sap_in_one                      = 0x00000001,
-  regk_iop_sap_in_or                       = 0x00000003,
-  regk_iop_sap_in_pos                      = 0x00000001,
-  regk_iop_sap_in_pos_neg                  = 0x00000003,
-  regk_iop_sap_in_rw_bus_byte_default      = 0x00000000,
-  regk_iop_sap_in_rw_bus_byte_size         = 0x00000004,
-  regk_iop_sap_in_rw_gio_default           = 0x00000000,
-  regk_iop_sap_in_rw_gio_size              = 0x00000020,
-  regk_iop_sap_in_timer_grp0_tmr3          = 0x00000000,
-  regk_iop_sap_in_timer_grp1_tmr3          = 0x00000001,
-  regk_iop_sap_in_tmr_clk200               = 0x00000001,
-  regk_iop_sap_in_two                      = 0x00000002,
-  regk_iop_sap_in_two_clk200               = 0x00000000
-};
-#endif /* __iop_sap_in_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h
deleted file mode 100644
index 5af88baa2ac1..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h
+++ /dev/null
@@ -1,231 +0,0 @@
-#ifndef __iop_sap_out_defs_h
-#define __iop_sap_out_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           iop_sap_out.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sap_out */
-
-/* Register rw_gen_gated, scope iop_sap_out, type rw */
-typedef struct {
-  unsigned int clk0_src       : 2;
-  unsigned int clk0_gate_src  : 2;
-  unsigned int clk0_force_src : 3;
-  unsigned int clk1_src       : 2;
-  unsigned int clk1_gate_src  : 2;
-  unsigned int clk1_force_src : 3;
-  unsigned int dummy1         : 18;
-} reg_iop_sap_out_rw_gen_gated;
-#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0
-#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0
-
-/* Register rw_bus, scope iop_sap_out, type rw */
-typedef struct {
-  unsigned int byte0_clk_sel   : 2;
-  unsigned int byte0_clk_ext   : 2;
-  unsigned int byte0_gated_clk : 1;
-  unsigned int byte0_clk_inv   : 1;
-  unsigned int byte0_delay     : 1;
-  unsigned int byte1_clk_sel   : 2;
-  unsigned int byte1_clk_ext   : 2;
-  unsigned int byte1_gated_clk : 1;
-  unsigned int byte1_clk_inv   : 1;
-  unsigned int byte1_delay     : 1;
-  unsigned int byte2_clk_sel   : 2;
-  unsigned int byte2_clk_ext   : 2;
-  unsigned int byte2_gated_clk : 1;
-  unsigned int byte2_clk_inv   : 1;
-  unsigned int byte2_delay     : 1;
-  unsigned int byte3_clk_sel   : 2;
-  unsigned int byte3_clk_ext   : 2;
-  unsigned int byte3_gated_clk : 1;
-  unsigned int byte3_clk_inv   : 1;
-  unsigned int byte3_delay     : 1;
-  unsigned int dummy1          : 4;
-} reg_iop_sap_out_rw_bus;
-#define REG_RD_ADDR_iop_sap_out_rw_bus 4
-#define REG_WR_ADDR_iop_sap_out_rw_bus 4
-
-/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */
-typedef struct {
-  unsigned int byte0_clk_sel   : 2;
-  unsigned int byte0_clk_ext   : 2;
-  unsigned int byte0_gated_clk : 1;
-  unsigned int byte0_clk_inv   : 1;
-  unsigned int byte0_delay     : 1;
-  unsigned int byte0_logic     : 2;
-  unsigned int byte0_logic_src : 2;
-  unsigned int byte1_clk_sel   : 2;
-  unsigned int byte1_clk_ext   : 2;
-  unsigned int byte1_gated_clk : 1;
-  unsigned int byte1_clk_inv   : 1;
-  unsigned int byte1_delay     : 1;
-  unsigned int byte1_logic     : 2;
-  unsigned int byte1_logic_src : 2;
-  unsigned int dummy1          : 10;
-} reg_iop_sap_out_rw_bus_lo_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8
-#define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8
-
-/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */
-typedef struct {
-  unsigned int byte2_clk_sel   : 2;
-  unsigned int byte2_clk_ext   : 2;
-  unsigned int byte2_gated_clk : 1;
-  unsigned int byte2_clk_inv   : 1;
-  unsigned int byte2_delay     : 1;
-  unsigned int byte2_logic     : 2;
-  unsigned int byte2_logic_src : 2;
-  unsigned int byte3_clk_sel   : 2;
-  unsigned int byte3_clk_ext   : 2;
-  unsigned int byte3_gated_clk : 1;
-  unsigned int byte3_clk_inv   : 1;
-  unsigned int byte3_delay     : 1;
-  unsigned int byte3_logic     : 2;
-  unsigned int byte3_logic_src : 2;
-  unsigned int dummy1          : 10;
-} reg_iop_sap_out_rw_bus_hi_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12
-#define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12
-
-#define STRIDE_iop_sap_out_rw_gio 4
-/* Register rw_gio, scope iop_sap_out, type rw */
-typedef struct {
-  unsigned int out_clk_sel   : 3;
-  unsigned int out_clk_ext   : 2;
-  unsigned int out_gated_clk : 1;
-  unsigned int out_clk_inv   : 1;
-  unsigned int out_delay     : 1;
-  unsigned int out_logic     : 2;
-  unsigned int out_logic_src : 2;
-  unsigned int oe_clk_sel    : 3;
-  unsigned int oe_clk_ext    : 2;
-  unsigned int oe_gated_clk  : 1;
-  unsigned int oe_clk_inv    : 1;
-  unsigned int oe_delay      : 1;
-  unsigned int oe_logic      : 2;
-  unsigned int oe_logic_src  : 2;
-  unsigned int dummy1        : 8;
-} reg_iop_sap_out_rw_gio;
-#define REG_RD_ADDR_iop_sap_out_rw_gio 16
-#define REG_WR_ADDR_iop_sap_out_rw_gio 16
-
-
-/* Constants */
-enum {
-  regk_iop_sap_out_always                  = 0x00000001,
-  regk_iop_sap_out_and                     = 0x00000002,
-  regk_iop_sap_out_clk0                    = 0x00000000,
-  regk_iop_sap_out_clk1                    = 0x00000001,
-  regk_iop_sap_out_clk12                   = 0x00000004,
-  regk_iop_sap_out_clk200                  = 0x00000000,
-  regk_iop_sap_out_ext                     = 0x00000002,
-  regk_iop_sap_out_gated                   = 0x00000003,
-  regk_iop_sap_out_gio0                    = 0x00000000,
-  regk_iop_sap_out_gio1                    = 0x00000000,
-  regk_iop_sap_out_gio16                   = 0x00000002,
-  regk_iop_sap_out_gio17                   = 0x00000002,
-  regk_iop_sap_out_gio24                   = 0x00000003,
-  regk_iop_sap_out_gio25                   = 0x00000003,
-  regk_iop_sap_out_gio8                    = 0x00000001,
-  regk_iop_sap_out_gio9                    = 0x00000001,
-  regk_iop_sap_out_gio_out10               = 0x00000005,
-  regk_iop_sap_out_gio_out18               = 0x00000006,
-  regk_iop_sap_out_gio_out2                = 0x00000004,
-  regk_iop_sap_out_gio_out26               = 0x00000007,
-  regk_iop_sap_out_inv                     = 0x00000001,
-  regk_iop_sap_out_nand                    = 0x00000003,
-  regk_iop_sap_out_no                      = 0x00000000,
-  regk_iop_sap_out_none                    = 0x00000000,
-  regk_iop_sap_out_one                     = 0x00000001,
-  regk_iop_sap_out_rw_bus_default          = 0x00000000,
-  regk_iop_sap_out_rw_bus_hi_oe_default    = 0x00000000,
-  regk_iop_sap_out_rw_bus_lo_oe_default    = 0x00000000,
-  regk_iop_sap_out_rw_gen_gated_default    = 0x00000000,
-  regk_iop_sap_out_rw_gio_default          = 0x00000000,
-  regk_iop_sap_out_rw_gio_size             = 0x00000020,
-  regk_iop_sap_out_spu_gio6                = 0x00000002,
-  regk_iop_sap_out_spu_gio7                = 0x00000003,
-  regk_iop_sap_out_timer_grp0_tmr2         = 0x00000000,
-  regk_iop_sap_out_timer_grp0_tmr3         = 0x00000001,
-  regk_iop_sap_out_timer_grp1_tmr2         = 0x00000002,
-  regk_iop_sap_out_timer_grp1_tmr3         = 0x00000003,
-  regk_iop_sap_out_tmr200                  = 0x00000001,
-  regk_iop_sap_out_yes                     = 0x00000001
-};
-#endif /* __iop_sap_out_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h
deleted file mode 100644
index 98ac95275a1c..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h
+++ /dev/null
@@ -1,725 +0,0 @@
-#ifndef __iop_sw_cfg_defs_h
-#define __iop_sw_cfg_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           iop_sw_cfg.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_cfg */
-
-/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_crc_par_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0
-#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0
-
-/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_in_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4
-
-/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_out_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8
-
-/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12
-
-/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16
-
-/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20
-
-/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24
-
-/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_sap_in_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28
-#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28
-
-/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_sap_out_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32
-#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32
-
-/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_in_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36
-
-/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_out_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40
-
-/* Register rw_spu_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 1;
-  unsigned int dummy1 : 31;
-} reg_iop_sw_cfg_rw_spu_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44
-
-/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48
-
-/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52
-
-/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56
-
-/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60
-
-/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp2_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64
-
-/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp3_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68
-
-/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp4_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72
-
-/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp5_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76
-
-/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp6_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80
-
-/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp7_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84
-
-/* Register rw_bus_mask, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_cfg_rw_bus_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88
-
-/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_cfg_rw_bus_oe_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92
-
-/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_cfg_rw_gio_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96
-
-/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_cfg_rw_gio_oe_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100
-
-/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int bus_byte0 : 2;
-  unsigned int bus_byte1 : 2;
-  unsigned int bus_byte2 : 2;
-  unsigned int bus_byte3 : 2;
-  unsigned int gio3_0    : 2;
-  unsigned int gio7_4    : 2;
-  unsigned int gio11_8   : 2;
-  unsigned int gio15_12  : 2;
-  unsigned int gio19_16  : 2;
-  unsigned int gio23_20  : 2;
-  unsigned int gio27_24  : 2;
-  unsigned int gio31_28  : 2;
-  unsigned int dummy1    : 8;
-} reg_iop_sw_cfg_rw_pinmapping;
-#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104
-#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104
-
-/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int bus_lo    : 2;
-  unsigned int bus_hi    : 2;
-  unsigned int bus_lo_oe : 2;
-  unsigned int bus_hi_oe : 2;
-  unsigned int dummy1    : 24;
-} reg_iop_sw_cfg_rw_bus_out_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108
-
-/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int gio0    : 3;
-  unsigned int gio0_oe : 1;
-  unsigned int gio1    : 3;
-  unsigned int gio1_oe : 1;
-  unsigned int gio2    : 3;
-  unsigned int gio2_oe : 1;
-  unsigned int gio3    : 3;
-  unsigned int gio3_oe : 1;
-  unsigned int dummy1  : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112
-
-/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int gio4    : 3;
-  unsigned int gio4_oe : 1;
-  unsigned int gio5    : 3;
-  unsigned int gio5_oe : 1;
-  unsigned int gio6    : 3;
-  unsigned int gio6_oe : 1;
-  unsigned int gio7    : 3;
-  unsigned int gio7_oe : 1;
-  unsigned int dummy1  : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116
-
-/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int gio8     : 3;
-  unsigned int gio8_oe  : 1;
-  unsigned int gio9     : 3;
-  unsigned int gio9_oe  : 1;
-  unsigned int gio10    : 3;
-  unsigned int gio10_oe : 1;
-  unsigned int gio11    : 3;
-  unsigned int gio11_oe : 1;
-  unsigned int dummy1   : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp2_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120
-
-/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int gio12    : 3;
-  unsigned int gio12_oe : 1;
-  unsigned int gio13    : 3;
-  unsigned int gio13_oe : 1;
-  unsigned int gio14    : 3;
-  unsigned int gio14_oe : 1;
-  unsigned int gio15    : 3;
-  unsigned int gio15_oe : 1;
-  unsigned int dummy1   : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp3_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124
-
-/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int gio16    : 3;
-  unsigned int gio16_oe : 1;
-  unsigned int gio17    : 3;
-  unsigned int gio17_oe : 1;
-  unsigned int gio18    : 3;
-  unsigned int gio18_oe : 1;
-  unsigned int gio19    : 3;
-  unsigned int gio19_oe : 1;
-  unsigned int dummy1   : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp4_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128
-
-/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int gio20    : 3;
-  unsigned int gio20_oe : 1;
-  unsigned int gio21    : 3;
-  unsigned int gio21_oe : 1;
-  unsigned int gio22    : 3;
-  unsigned int gio22_oe : 1;
-  unsigned int gio23    : 3;
-  unsigned int gio23_oe : 1;
-  unsigned int dummy1   : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp5_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132
-
-/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int gio24    : 3;
-  unsigned int gio24_oe : 1;
-  unsigned int gio25    : 3;
-  unsigned int gio25_oe : 1;
-  unsigned int gio26    : 3;
-  unsigned int gio26_oe : 1;
-  unsigned int gio27    : 3;
-  unsigned int gio27_oe : 1;
-  unsigned int dummy1   : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp6_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136
-
-/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int gio28    : 3;
-  unsigned int gio28_oe : 1;
-  unsigned int gio29    : 3;
-  unsigned int gio29_oe : 1;
-  unsigned int gio30    : 3;
-  unsigned int gio30_oe : 1;
-  unsigned int gio31    : 3;
-  unsigned int gio31_oe : 1;
-  unsigned int dummy1   : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp7_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140
-
-/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int bus0_in : 1;
-  unsigned int bus1_in : 1;
-  unsigned int dummy1  : 30;
-} reg_iop_sw_cfg_rw_spu_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144
-
-/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int ext_clk  : 3;
-  unsigned int tmr0_en  : 2;
-  unsigned int tmr1_en  : 2;
-  unsigned int tmr2_en  : 2;
-  unsigned int tmr3_en  : 2;
-  unsigned int tmr0_dis : 2;
-  unsigned int tmr1_dis : 2;
-  unsigned int tmr2_dis : 2;
-  unsigned int tmr3_dis : 2;
-  unsigned int dummy1   : 13;
-} reg_iop_sw_cfg_rw_timer_grp0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148
-
-/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int ext_clk  : 3;
-  unsigned int tmr0_en  : 2;
-  unsigned int tmr1_en  : 2;
-  unsigned int tmr2_en  : 2;
-  unsigned int tmr3_en  : 2;
-  unsigned int tmr0_dis : 2;
-  unsigned int tmr1_dis : 2;
-  unsigned int tmr2_dis : 2;
-  unsigned int tmr3_dis : 2;
-  unsigned int dummy1   : 13;
-} reg_iop_sw_cfg_rw_timer_grp1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152
-
-/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int grp0_dis : 1;
-  unsigned int grp0_en  : 1;
-  unsigned int grp1_dis : 1;
-  unsigned int grp1_en  : 1;
-  unsigned int grp2_dis : 1;
-  unsigned int grp2_en  : 1;
-  unsigned int grp3_dis : 1;
-  unsigned int grp3_en  : 1;
-  unsigned int grp4_dis : 1;
-  unsigned int grp4_en  : 1;
-  unsigned int grp5_dis : 1;
-  unsigned int grp5_en  : 1;
-  unsigned int grp6_dis : 1;
-  unsigned int grp6_en  : 1;
-  unsigned int grp7_dis : 1;
-  unsigned int grp7_en  : 1;
-  unsigned int dummy1   : 16;
-} reg_iop_sw_cfg_rw_trigger_grps_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156
-
-/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int out_strb : 4;
-  unsigned int in_src   : 2;
-  unsigned int in_size  : 3;
-  unsigned int in_last  : 2;
-  unsigned int in_strb  : 4;
-  unsigned int dummy1   : 17;
-} reg_iop_sw_cfg_rw_pdp_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160
-#define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160
-
-/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
-  unsigned int sdp_out_strb : 3;
-  unsigned int sdp_in_data  : 3;
-  unsigned int sdp_in_last  : 2;
-  unsigned int sdp_in_strb  : 3;
-  unsigned int dummy1       : 21;
-} reg_iop_sw_cfg_rw_sdp_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164
-#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164
-
-
-/* Constants */
-enum {
-  regk_iop_sw_cfg_a                        = 0x00000001,
-  regk_iop_sw_cfg_b                        = 0x00000002,
-  regk_iop_sw_cfg_bus                      = 0x00000000,
-  regk_iop_sw_cfg_bus_rot16                = 0x00000002,
-  regk_iop_sw_cfg_bus_rot24                = 0x00000003,
-  regk_iop_sw_cfg_bus_rot8                 = 0x00000001,
-  regk_iop_sw_cfg_clk12                    = 0x00000000,
-  regk_iop_sw_cfg_cpu                      = 0x00000000,
-  regk_iop_sw_cfg_gated_clk0               = 0x0000000e,
-  regk_iop_sw_cfg_gated_clk1               = 0x0000000f,
-  regk_iop_sw_cfg_gio0                     = 0x00000004,
-  regk_iop_sw_cfg_gio1                     = 0x00000001,
-  regk_iop_sw_cfg_gio2                     = 0x00000005,
-  regk_iop_sw_cfg_gio3                     = 0x00000002,
-  regk_iop_sw_cfg_gio4                     = 0x00000006,
-  regk_iop_sw_cfg_gio5                     = 0x00000003,
-  regk_iop_sw_cfg_gio6                     = 0x00000007,
-  regk_iop_sw_cfg_gio7                     = 0x00000004,
-  regk_iop_sw_cfg_gio_in18                 = 0x00000002,
-  regk_iop_sw_cfg_gio_in19                 = 0x00000003,
-  regk_iop_sw_cfg_gio_in20                 = 0x00000004,
-  regk_iop_sw_cfg_gio_in21                 = 0x00000005,
-  regk_iop_sw_cfg_gio_in26                 = 0x00000006,
-  regk_iop_sw_cfg_gio_in27                 = 0x00000007,
-  regk_iop_sw_cfg_gio_in4                  = 0x00000000,
-  regk_iop_sw_cfg_gio_in5                  = 0x00000001,
-  regk_iop_sw_cfg_last_timer_grp0_tmr2     = 0x00000001,
-  regk_iop_sw_cfg_last_timer_grp1_tmr2     = 0x00000002,
-  regk_iop_sw_cfg_last_timer_grp1_tmr3     = 0x00000003,
-  regk_iop_sw_cfg_mpu                      = 0x00000001,
-  regk_iop_sw_cfg_none                     = 0x00000000,
-  regk_iop_sw_cfg_pdp_out                  = 0x00000001,
-  regk_iop_sw_cfg_pdp_out_hi               = 0x00000001,
-  regk_iop_sw_cfg_pdp_out_lo               = 0x00000000,
-  regk_iop_sw_cfg_rw_bus_mask_default      = 0x00000000,
-  regk_iop_sw_cfg_rw_bus_oe_mask_default   = 0x00000000,
-  regk_iop_sw_cfg_rw_bus_out_cfg_default   = 0x00000000,
-  regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_dmc_in_owner_default  = 0x00000000,
-  regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_mask_default      = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_oe_mask_default   = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_pdp_cfg_default       = 0x00000000,
-  regk_iop_sw_cfg_rw_pinmapping_default    = 0x00555555,
-  regk_iop_sw_cfg_rw_sap_in_owner_default  = 0x00000000,
-  regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_sdp_cfg_default       = 0x00000000,
-  regk_iop_sw_cfg_rw_spu_cfg_default       = 0x00000000,
-  regk_iop_sw_cfg_rw_spu_owner_default     = 0x00000000,
-  regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000,
-  regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000,
-  regk_iop_sw_cfg_sdp_out                  = 0x00000004,
-  regk_iop_sw_cfg_size16                   = 0x00000002,
-  regk_iop_sw_cfg_size24                   = 0x00000003,
-  regk_iop_sw_cfg_size32                   = 0x00000004,
-  regk_iop_sw_cfg_size8                    = 0x00000001,
-  regk_iop_sw_cfg_spu                      = 0x00000002,
-  regk_iop_sw_cfg_spu_bus_out0_hi          = 0x00000002,
-  regk_iop_sw_cfg_spu_bus_out0_lo          = 0x00000002,
-  regk_iop_sw_cfg_spu_bus_out1_hi          = 0x00000003,
-  regk_iop_sw_cfg_spu_bus_out1_lo          = 0x00000003,
-  regk_iop_sw_cfg_spu_g0                   = 0x00000007,
-  regk_iop_sw_cfg_spu_g1                   = 0x00000007,
-  regk_iop_sw_cfg_spu_g2                   = 0x00000007,
-  regk_iop_sw_cfg_spu_g3                   = 0x00000007,
-  regk_iop_sw_cfg_spu_g4                   = 0x00000007,
-  regk_iop_sw_cfg_spu_g5                   = 0x00000007,
-  regk_iop_sw_cfg_spu_g6                   = 0x00000007,
-  regk_iop_sw_cfg_spu_g7                   = 0x00000007,
-  regk_iop_sw_cfg_spu_gio0                 = 0x00000000,
-  regk_iop_sw_cfg_spu_gio1                 = 0x00000001,
-  regk_iop_sw_cfg_spu_gio5                 = 0x00000005,
-  regk_iop_sw_cfg_spu_gio6                 = 0x00000006,
-  regk_iop_sw_cfg_spu_gio7                 = 0x00000007,
-  regk_iop_sw_cfg_spu_gio_out0             = 0x00000008,
-  regk_iop_sw_cfg_spu_gio_out1             = 0x00000009,
-  regk_iop_sw_cfg_spu_gio_out2             = 0x0000000a,
-  regk_iop_sw_cfg_spu_gio_out3             = 0x0000000b,
-  regk_iop_sw_cfg_spu_gio_out4             = 0x0000000c,
-  regk_iop_sw_cfg_spu_gio_out5             = 0x0000000d,
-  regk_iop_sw_cfg_spu_gio_out6             = 0x0000000e,
-  regk_iop_sw_cfg_spu_gio_out7             = 0x0000000f,
-  regk_iop_sw_cfg_spu_gioout0              = 0x00000000,
-  regk_iop_sw_cfg_spu_gioout1              = 0x00000000,
-  regk_iop_sw_cfg_spu_gioout10             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout11             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout12             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout13             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout14             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout15             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout16             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout17             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout18             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout19             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout2              = 0x00000001,
-  regk_iop_sw_cfg_spu_gioout20             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout21             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout22             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout23             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout24             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout25             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout26             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout27             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout28             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout29             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout3              = 0x00000001,
-  regk_iop_sw_cfg_spu_gioout30             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout31             = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout4              = 0x00000002,
-  regk_iop_sw_cfg_spu_gioout5              = 0x00000002,
-  regk_iop_sw_cfg_spu_gioout6              = 0x00000003,
-  regk_iop_sw_cfg_spu_gioout7              = 0x00000003,
-  regk_iop_sw_cfg_spu_gioout8              = 0x00000007,
-  regk_iop_sw_cfg_spu_gioout9              = 0x00000007,
-  regk_iop_sw_cfg_strb_timer_grp0_tmr0     = 0x00000001,
-  regk_iop_sw_cfg_strb_timer_grp0_tmr1     = 0x00000002,
-  regk_iop_sw_cfg_strb_timer_grp1_tmr0     = 0x00000003,
-  regk_iop_sw_cfg_strb_timer_grp1_tmr1     = 0x00000002,
-  regk_iop_sw_cfg_timer_grp0               = 0x00000000,
-  regk_iop_sw_cfg_timer_grp0_rot           = 0x00000001,
-  regk_iop_sw_cfg_timer_grp0_strb0         = 0x00000005,
-  regk_iop_sw_cfg_timer_grp0_strb1         = 0x00000005,
-  regk_iop_sw_cfg_timer_grp0_strb2         = 0x00000005,
-  regk_iop_sw_cfg_timer_grp0_strb3         = 0x00000005,
-  regk_iop_sw_cfg_timer_grp0_tmr0          = 0x00000002,
-  regk_iop_sw_cfg_timer_grp1               = 0x00000000,
-  regk_iop_sw_cfg_timer_grp1_rot           = 0x00000001,
-  regk_iop_sw_cfg_timer_grp1_strb0         = 0x00000006,
-  regk_iop_sw_cfg_timer_grp1_strb1         = 0x00000006,
-  regk_iop_sw_cfg_timer_grp1_strb2         = 0x00000006,
-  regk_iop_sw_cfg_timer_grp1_strb3         = 0x00000006,
-  regk_iop_sw_cfg_timer_grp1_tmr0          = 0x00000003,
-  regk_iop_sw_cfg_trig0_0                  = 0x00000000,
-  regk_iop_sw_cfg_trig0_1                  = 0x00000000,
-  regk_iop_sw_cfg_trig0_2                  = 0x00000000,
-  regk_iop_sw_cfg_trig0_3                  = 0x00000000,
-  regk_iop_sw_cfg_trig1_0                  = 0x00000000,
-  regk_iop_sw_cfg_trig1_1                  = 0x00000000,
-  regk_iop_sw_cfg_trig1_2                  = 0x00000000,
-  regk_iop_sw_cfg_trig1_3                  = 0x00000000,
-  regk_iop_sw_cfg_trig2_0                  = 0x00000001,
-  regk_iop_sw_cfg_trig2_1                  = 0x00000001,
-  regk_iop_sw_cfg_trig2_2                  = 0x00000001,
-  regk_iop_sw_cfg_trig2_3                  = 0x00000001,
-  regk_iop_sw_cfg_trig3_0                  = 0x00000001,
-  regk_iop_sw_cfg_trig3_1                  = 0x00000001,
-  regk_iop_sw_cfg_trig3_2                  = 0x00000001,
-  regk_iop_sw_cfg_trig3_3                  = 0x00000001,
-  regk_iop_sw_cfg_trig4_0                  = 0x00000002,
-  regk_iop_sw_cfg_trig4_1                  = 0x00000002,
-  regk_iop_sw_cfg_trig4_2                  = 0x00000002,
-  regk_iop_sw_cfg_trig4_3                  = 0x00000002,
-  regk_iop_sw_cfg_trig5_0                  = 0x00000002,
-  regk_iop_sw_cfg_trig5_1                  = 0x00000002,
-  regk_iop_sw_cfg_trig5_2                  = 0x00000002,
-  regk_iop_sw_cfg_trig5_3                  = 0x00000002,
-  regk_iop_sw_cfg_trig6_0                  = 0x00000003,
-  regk_iop_sw_cfg_trig6_1                  = 0x00000003,
-  regk_iop_sw_cfg_trig6_2                  = 0x00000003,
-  regk_iop_sw_cfg_trig6_3                  = 0x00000003,
-  regk_iop_sw_cfg_trig7_0                  = 0x00000003,
-  regk_iop_sw_cfg_trig7_1                  = 0x00000003,
-  regk_iop_sw_cfg_trig7_2                  = 0x00000003,
-  regk_iop_sw_cfg_trig7_3                  = 0x00000003
-};
-#endif /* __iop_sw_cfg_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h
deleted file mode 100644
index a16f556370eb..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h
+++ /dev/null
@@ -1,522 +0,0 @@
-#ifndef __iop_sw_cpu_defs_h
-#define __iop_sw_cpu_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           iop_sw_cpu.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_cpu */
-
-/* Register r_mpu_trace, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_mpu_trace;
-#define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0
-
-/* Register r_spu_trace, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_spu_trace;
-#define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4
-
-/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace;
-#define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8
-
-/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int keep_owner : 1;
-  unsigned int cmd        : 2;
-  unsigned int size       : 3;
-  unsigned int wr_spu_mem : 1;
-  unsigned int dummy1     : 25;
-} reg_iop_sw_cpu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12
-
-/* Register rw_mc_data, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_cpu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16
-
-/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
-typedef unsigned int reg_iop_sw_cpu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20
-
-/* Register rs_mc_data, scope iop_sw_cpu, type rs */
-typedef unsigned int reg_iop_sw_cpu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24
-
-/* Register r_mc_data, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28
-
-/* Register r_mc_stat, scope iop_sw_cpu, type r */
-typedef struct {
-  unsigned int busy_cpu     : 1;
-  unsigned int busy_mpu     : 1;
-  unsigned int busy_spu     : 1;
-  unsigned int owned_by_cpu : 1;
-  unsigned int owned_by_mpu : 1;
-  unsigned int owned_by_spu : 1;
-  unsigned int dummy1       : 26;
-} reg_iop_sw_cpu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32
-
-/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36
-
-/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48
-
-/* Register r_bus_in, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_bus_in;
-#define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52
-
-/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56
-
-/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68
-
-/* Register r_gio_in, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72
-
-/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int mpu_0  : 1;
-  unsigned int mpu_1  : 1;
-  unsigned int mpu_2  : 1;
-  unsigned int mpu_3  : 1;
-  unsigned int mpu_4  : 1;
-  unsigned int mpu_5  : 1;
-  unsigned int mpu_6  : 1;
-  unsigned int mpu_7  : 1;
-  unsigned int mpu_8  : 1;
-  unsigned int mpu_9  : 1;
-  unsigned int mpu_10 : 1;
-  unsigned int mpu_11 : 1;
-  unsigned int mpu_12 : 1;
-  unsigned int mpu_13 : 1;
-  unsigned int mpu_14 : 1;
-  unsigned int mpu_15 : 1;
-  unsigned int spu_0  : 1;
-  unsigned int spu_1  : 1;
-  unsigned int spu_2  : 1;
-  unsigned int spu_3  : 1;
-  unsigned int spu_4  : 1;
-  unsigned int spu_5  : 1;
-  unsigned int spu_6  : 1;
-  unsigned int spu_7  : 1;
-  unsigned int spu_8  : 1;
-  unsigned int spu_9  : 1;
-  unsigned int spu_10 : 1;
-  unsigned int spu_11 : 1;
-  unsigned int spu_12 : 1;
-  unsigned int spu_13 : 1;
-  unsigned int spu_14 : 1;
-  unsigned int spu_15 : 1;
-} reg_iop_sw_cpu_rw_intr0_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76
-
-/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int mpu_0  : 1;
-  unsigned int mpu_1  : 1;
-  unsigned int mpu_2  : 1;
-  unsigned int mpu_3  : 1;
-  unsigned int mpu_4  : 1;
-  unsigned int mpu_5  : 1;
-  unsigned int mpu_6  : 1;
-  unsigned int mpu_7  : 1;
-  unsigned int mpu_8  : 1;
-  unsigned int mpu_9  : 1;
-  unsigned int mpu_10 : 1;
-  unsigned int mpu_11 : 1;
-  unsigned int mpu_12 : 1;
-  unsigned int mpu_13 : 1;
-  unsigned int mpu_14 : 1;
-  unsigned int mpu_15 : 1;
-  unsigned int spu_0  : 1;
-  unsigned int spu_1  : 1;
-  unsigned int spu_2  : 1;
-  unsigned int spu_3  : 1;
-  unsigned int spu_4  : 1;
-  unsigned int spu_5  : 1;
-  unsigned int spu_6  : 1;
-  unsigned int spu_7  : 1;
-  unsigned int spu_8  : 1;
-  unsigned int spu_9  : 1;
-  unsigned int spu_10 : 1;
-  unsigned int spu_11 : 1;
-  unsigned int spu_12 : 1;
-  unsigned int spu_13 : 1;
-  unsigned int spu_14 : 1;
-  unsigned int spu_15 : 1;
-} reg_iop_sw_cpu_rw_ack_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80
-
-/* Register r_intr0, scope iop_sw_cpu, type r */
-typedef struct {
-  unsigned int mpu_0  : 1;
-  unsigned int mpu_1  : 1;
-  unsigned int mpu_2  : 1;
-  unsigned int mpu_3  : 1;
-  unsigned int mpu_4  : 1;
-  unsigned int mpu_5  : 1;
-  unsigned int mpu_6  : 1;
-  unsigned int mpu_7  : 1;
-  unsigned int mpu_8  : 1;
-  unsigned int mpu_9  : 1;
-  unsigned int mpu_10 : 1;
-  unsigned int mpu_11 : 1;
-  unsigned int mpu_12 : 1;
-  unsigned int mpu_13 : 1;
-  unsigned int mpu_14 : 1;
-  unsigned int mpu_15 : 1;
-  unsigned int spu_0  : 1;
-  unsigned int spu_1  : 1;
-  unsigned int spu_2  : 1;
-  unsigned int spu_3  : 1;
-  unsigned int spu_4  : 1;
-  unsigned int spu_5  : 1;
-  unsigned int spu_6  : 1;
-  unsigned int spu_7  : 1;
-  unsigned int spu_8  : 1;
-  unsigned int spu_9  : 1;
-  unsigned int spu_10 : 1;
-  unsigned int spu_11 : 1;
-  unsigned int spu_12 : 1;
-  unsigned int spu_13 : 1;
-  unsigned int spu_14 : 1;
-  unsigned int spu_15 : 1;
-} reg_iop_sw_cpu_r_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr0 84
-
-/* Register r_masked_intr0, scope iop_sw_cpu, type r */
-typedef struct {
-  unsigned int mpu_0  : 1;
-  unsigned int mpu_1  : 1;
-  unsigned int mpu_2  : 1;
-  unsigned int mpu_3  : 1;
-  unsigned int mpu_4  : 1;
-  unsigned int mpu_5  : 1;
-  unsigned int mpu_6  : 1;
-  unsigned int mpu_7  : 1;
-  unsigned int mpu_8  : 1;
-  unsigned int mpu_9  : 1;
-  unsigned int mpu_10 : 1;
-  unsigned int mpu_11 : 1;
-  unsigned int mpu_12 : 1;
-  unsigned int mpu_13 : 1;
-  unsigned int mpu_14 : 1;
-  unsigned int mpu_15 : 1;
-  unsigned int spu_0  : 1;
-  unsigned int spu_1  : 1;
-  unsigned int spu_2  : 1;
-  unsigned int spu_3  : 1;
-  unsigned int spu_4  : 1;
-  unsigned int spu_5  : 1;
-  unsigned int spu_6  : 1;
-  unsigned int spu_7  : 1;
-  unsigned int spu_8  : 1;
-  unsigned int spu_9  : 1;
-  unsigned int spu_10 : 1;
-  unsigned int spu_11 : 1;
-  unsigned int spu_12 : 1;
-  unsigned int spu_13 : 1;
-  unsigned int spu_14 : 1;
-  unsigned int spu_15 : 1;
-} reg_iop_sw_cpu_r_masked_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88
-
-/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int mpu_16         : 1;
-  unsigned int mpu_17         : 1;
-  unsigned int mpu_18         : 1;
-  unsigned int mpu_19         : 1;
-  unsigned int mpu_20         : 1;
-  unsigned int mpu_21         : 1;
-  unsigned int mpu_22         : 1;
-  unsigned int mpu_23         : 1;
-  unsigned int mpu_24         : 1;
-  unsigned int mpu_25         : 1;
-  unsigned int mpu_26         : 1;
-  unsigned int mpu_27         : 1;
-  unsigned int mpu_28         : 1;
-  unsigned int mpu_29         : 1;
-  unsigned int mpu_30         : 1;
-  unsigned int mpu_31         : 1;
-  unsigned int dmc_in         : 1;
-  unsigned int dmc_out        : 1;
-  unsigned int fifo_in        : 1;
-  unsigned int fifo_out       : 1;
-  unsigned int fifo_in_extra  : 1;
-  unsigned int fifo_out_extra : 1;
-  unsigned int trigger_grp0   : 1;
-  unsigned int trigger_grp1   : 1;
-  unsigned int trigger_grp2   : 1;
-  unsigned int trigger_grp3   : 1;
-  unsigned int trigger_grp4   : 1;
-  unsigned int trigger_grp5   : 1;
-  unsigned int trigger_grp6   : 1;
-  unsigned int trigger_grp7   : 1;
-  unsigned int timer_grp0     : 1;
-  unsigned int timer_grp1     : 1;
-} reg_iop_sw_cpu_rw_intr1_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92
-
-/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
-typedef struct {
-  unsigned int mpu_16 : 1;
-  unsigned int mpu_17 : 1;
-  unsigned int mpu_18 : 1;
-  unsigned int mpu_19 : 1;
-  unsigned int mpu_20 : 1;
-  unsigned int mpu_21 : 1;
-  unsigned int mpu_22 : 1;
-  unsigned int mpu_23 : 1;
-  unsigned int mpu_24 : 1;
-  unsigned int mpu_25 : 1;
-  unsigned int mpu_26 : 1;
-  unsigned int mpu_27 : 1;
-  unsigned int mpu_28 : 1;
-  unsigned int mpu_29 : 1;
-  unsigned int mpu_30 : 1;
-  unsigned int mpu_31 : 1;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_cpu_rw_ack_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96
-
-/* Register r_intr1, scope iop_sw_cpu, type r */
-typedef struct {
-  unsigned int mpu_16         : 1;
-  unsigned int mpu_17         : 1;
-  unsigned int mpu_18         : 1;
-  unsigned int mpu_19         : 1;
-  unsigned int mpu_20         : 1;
-  unsigned int mpu_21         : 1;
-  unsigned int mpu_22         : 1;
-  unsigned int mpu_23         : 1;
-  unsigned int mpu_24         : 1;
-  unsigned int mpu_25         : 1;
-  unsigned int mpu_26         : 1;
-  unsigned int mpu_27         : 1;
-  unsigned int mpu_28         : 1;
-  unsigned int mpu_29         : 1;
-  unsigned int mpu_30         : 1;
-  unsigned int mpu_31         : 1;
-  unsigned int dmc_in         : 1;
-  unsigned int dmc_out        : 1;
-  unsigned int fifo_in        : 1;
-  unsigned int fifo_out       : 1;
-  unsigned int fifo_in_extra  : 1;
-  unsigned int fifo_out_extra : 1;
-  unsigned int trigger_grp0   : 1;
-  unsigned int trigger_grp1   : 1;
-  unsigned int trigger_grp2   : 1;
-  unsigned int trigger_grp3   : 1;
-  unsigned int trigger_grp4   : 1;
-  unsigned int trigger_grp5   : 1;
-  unsigned int trigger_grp6   : 1;
-  unsigned int trigger_grp7   : 1;
-  unsigned int timer_grp0     : 1;
-  unsigned int timer_grp1     : 1;
-} reg_iop_sw_cpu_r_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr1 100
-
-/* Register r_masked_intr1, scope iop_sw_cpu, type r */
-typedef struct {
-  unsigned int mpu_16         : 1;
-  unsigned int mpu_17         : 1;
-  unsigned int mpu_18         : 1;
-  unsigned int mpu_19         : 1;
-  unsigned int mpu_20         : 1;
-  unsigned int mpu_21         : 1;
-  unsigned int mpu_22         : 1;
-  unsigned int mpu_23         : 1;
-  unsigned int mpu_24         : 1;
-  unsigned int mpu_25         : 1;
-  unsigned int mpu_26         : 1;
-  unsigned int mpu_27         : 1;
-  unsigned int mpu_28         : 1;
-  unsigned int mpu_29         : 1;
-  unsigned int mpu_30         : 1;
-  unsigned int mpu_31         : 1;
-  unsigned int dmc_in         : 1;
-  unsigned int dmc_out        : 1;
-  unsigned int fifo_in        : 1;
-  unsigned int fifo_out       : 1;
-  unsigned int fifo_in_extra  : 1;
-  unsigned int fifo_out_extra : 1;
-  unsigned int trigger_grp0   : 1;
-  unsigned int trigger_grp1   : 1;
-  unsigned int trigger_grp2   : 1;
-  unsigned int trigger_grp3   : 1;
-  unsigned int trigger_grp4   : 1;
-  unsigned int trigger_grp5   : 1;
-  unsigned int trigger_grp6   : 1;
-  unsigned int trigger_grp7   : 1;
-  unsigned int timer_grp0     : 1;
-  unsigned int timer_grp1     : 1;
-} reg_iop_sw_cpu_r_masked_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104
-
-
-/* Constants */
-enum {
-  regk_iop_sw_cpu_copy                     = 0x00000000,
-  regk_iop_sw_cpu_no                       = 0x00000000,
-  regk_iop_sw_cpu_rd                       = 0x00000002,
-  regk_iop_sw_cpu_reg_copy                 = 0x00000001,
-  regk_iop_sw_cpu_rw_bus_clr_mask_default  = 0x00000000,
-  regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000,
-  regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000,
-  regk_iop_sw_cpu_rw_bus_set_mask_default  = 0x00000000,
-  regk_iop_sw_cpu_rw_gio_clr_mask_default  = 0x00000000,
-  regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000,
-  regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000,
-  regk_iop_sw_cpu_rw_gio_set_mask_default  = 0x00000000,
-  regk_iop_sw_cpu_rw_intr0_mask_default    = 0x00000000,
-  regk_iop_sw_cpu_rw_intr1_mask_default    = 0x00000000,
-  regk_iop_sw_cpu_wr                       = 0x00000003,
-  regk_iop_sw_cpu_yes                      = 0x00000001
-};
-#endif /* __iop_sw_cpu_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h
deleted file mode 100644
index a2e4e1a33e57..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h
+++ /dev/null
@@ -1,648 +0,0 @@
-#ifndef __iop_sw_mpu_defs_h
-#define __iop_sw_mpu_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           iop_sw_mpu.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_mpu */
-
-/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int cfg : 2;
-  unsigned int dummy1 : 30;
-} reg_iop_sw_mpu_rw_sw_cfg_owner;
-#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
-#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
-
-/* Register r_spu_trace, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_spu_trace;
-#define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4
-
-/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace;
-#define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8
-
-/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int keep_owner : 1;
-  unsigned int cmd        : 2;
-  unsigned int size       : 3;
-  unsigned int wr_spu_mem : 1;
-  unsigned int dummy1     : 25;
-} reg_iop_sw_mpu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12
-
-/* Register rw_mc_data, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_mpu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16
-
-/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
-typedef unsigned int reg_iop_sw_mpu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20
-
-/* Register rs_mc_data, scope iop_sw_mpu, type rs */
-typedef unsigned int reg_iop_sw_mpu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24
-
-/* Register r_mc_data, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28
-
-/* Register r_mc_stat, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int busy_cpu     : 1;
-  unsigned int busy_mpu     : 1;
-  unsigned int busy_spu     : 1;
-  unsigned int owned_by_cpu : 1;
-  unsigned int owned_by_mpu : 1;
-  unsigned int owned_by_spu : 1;
-  unsigned int dummy1       : 26;
-} reg_iop_sw_mpu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32
-
-/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36
-
-/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48
-
-/* Register r_bus_in, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_bus_in;
-#define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52
-
-/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56
-
-/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68
-
-/* Register r_gio_in, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72
-
-/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int intr0  : 1;
-  unsigned int intr1  : 1;
-  unsigned int intr2  : 1;
-  unsigned int intr3  : 1;
-  unsigned int intr4  : 1;
-  unsigned int intr5  : 1;
-  unsigned int intr6  : 1;
-  unsigned int intr7  : 1;
-  unsigned int intr8  : 1;
-  unsigned int intr9  : 1;
-  unsigned int intr10 : 1;
-  unsigned int intr11 : 1;
-  unsigned int intr12 : 1;
-  unsigned int intr13 : 1;
-  unsigned int intr14 : 1;
-  unsigned int intr15 : 1;
-  unsigned int intr16 : 1;
-  unsigned int intr17 : 1;
-  unsigned int intr18 : 1;
-  unsigned int intr19 : 1;
-  unsigned int intr20 : 1;
-  unsigned int intr21 : 1;
-  unsigned int intr22 : 1;
-  unsigned int intr23 : 1;
-  unsigned int intr24 : 1;
-  unsigned int intr25 : 1;
-  unsigned int intr26 : 1;
-  unsigned int intr27 : 1;
-  unsigned int intr28 : 1;
-  unsigned int intr29 : 1;
-  unsigned int intr30 : 1;
-  unsigned int intr31 : 1;
-} reg_iop_sw_mpu_rw_cpu_intr;
-#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76
-#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76
-
-/* Register r_cpu_intr, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int intr0  : 1;
-  unsigned int intr1  : 1;
-  unsigned int intr2  : 1;
-  unsigned int intr3  : 1;
-  unsigned int intr4  : 1;
-  unsigned int intr5  : 1;
-  unsigned int intr6  : 1;
-  unsigned int intr7  : 1;
-  unsigned int intr8  : 1;
-  unsigned int intr9  : 1;
-  unsigned int intr10 : 1;
-  unsigned int intr11 : 1;
-  unsigned int intr12 : 1;
-  unsigned int intr13 : 1;
-  unsigned int intr14 : 1;
-  unsigned int intr15 : 1;
-  unsigned int intr16 : 1;
-  unsigned int intr17 : 1;
-  unsigned int intr18 : 1;
-  unsigned int intr19 : 1;
-  unsigned int intr20 : 1;
-  unsigned int intr21 : 1;
-  unsigned int intr22 : 1;
-  unsigned int intr23 : 1;
-  unsigned int intr24 : 1;
-  unsigned int intr25 : 1;
-  unsigned int intr26 : 1;
-  unsigned int intr27 : 1;
-  unsigned int intr28 : 1;
-  unsigned int intr29 : 1;
-  unsigned int intr30 : 1;
-  unsigned int intr31 : 1;
-} reg_iop_sw_mpu_r_cpu_intr;
-#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80
-
-/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int spu_intr0      : 1;
-  unsigned int trigger_grp0   : 1;
-  unsigned int timer_grp0     : 1;
-  unsigned int fifo_out       : 1;
-  unsigned int spu_intr1      : 1;
-  unsigned int trigger_grp1   : 1;
-  unsigned int timer_grp1     : 1;
-  unsigned int fifo_in        : 1;
-  unsigned int spu_intr2      : 1;
-  unsigned int trigger_grp2   : 1;
-  unsigned int fifo_out_extra : 1;
-  unsigned int dmc_out        : 1;
-  unsigned int spu_intr3      : 1;
-  unsigned int trigger_grp3   : 1;
-  unsigned int fifo_in_extra  : 1;
-  unsigned int dmc_in         : 1;
-  unsigned int dummy1         : 16;
-} reg_iop_sw_mpu_rw_intr_grp0_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84
-
-/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int spu_intr0 : 1;
-  unsigned int dummy1    : 3;
-  unsigned int spu_intr1 : 1;
-  unsigned int dummy2    : 3;
-  unsigned int spu_intr2 : 1;
-  unsigned int dummy3    : 3;
-  unsigned int spu_intr3 : 1;
-  unsigned int dummy4    : 19;
-} reg_iop_sw_mpu_rw_ack_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88
-
-/* Register r_intr_grp0, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int spu_intr0      : 1;
-  unsigned int trigger_grp0   : 1;
-  unsigned int timer_grp0     : 1;
-  unsigned int fifo_out       : 1;
-  unsigned int spu_intr1      : 1;
-  unsigned int trigger_grp1   : 1;
-  unsigned int timer_grp1     : 1;
-  unsigned int fifo_in        : 1;
-  unsigned int spu_intr2      : 1;
-  unsigned int trigger_grp2   : 1;
-  unsigned int fifo_out_extra : 1;
-  unsigned int dmc_out        : 1;
-  unsigned int spu_intr3      : 1;
-  unsigned int trigger_grp3   : 1;
-  unsigned int fifo_in_extra  : 1;
-  unsigned int dmc_in         : 1;
-  unsigned int dummy1         : 16;
-} reg_iop_sw_mpu_r_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92
-
-/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int spu_intr0      : 1;
-  unsigned int trigger_grp0   : 1;
-  unsigned int timer_grp0     : 1;
-  unsigned int fifo_out       : 1;
-  unsigned int spu_intr1      : 1;
-  unsigned int trigger_grp1   : 1;
-  unsigned int timer_grp1     : 1;
-  unsigned int fifo_in        : 1;
-  unsigned int spu_intr2      : 1;
-  unsigned int trigger_grp2   : 1;
-  unsigned int fifo_out_extra : 1;
-  unsigned int dmc_out        : 1;
-  unsigned int spu_intr3      : 1;
-  unsigned int trigger_grp3   : 1;
-  unsigned int fifo_in_extra  : 1;
-  unsigned int dmc_in         : 1;
-  unsigned int dummy1         : 16;
-} reg_iop_sw_mpu_r_masked_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96
-
-/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int spu_intr4      : 1;
-  unsigned int trigger_grp4   : 1;
-  unsigned int fifo_out_extra : 1;
-  unsigned int dmc_out        : 1;
-  unsigned int spu_intr5      : 1;
-  unsigned int trigger_grp5   : 1;
-  unsigned int fifo_in_extra  : 1;
-  unsigned int dmc_in         : 1;
-  unsigned int spu_intr6      : 1;
-  unsigned int trigger_grp6   : 1;
-  unsigned int timer_grp0     : 1;
-  unsigned int fifo_out       : 1;
-  unsigned int spu_intr7      : 1;
-  unsigned int trigger_grp7   : 1;
-  unsigned int timer_grp1     : 1;
-  unsigned int fifo_in        : 1;
-  unsigned int dummy1         : 16;
-} reg_iop_sw_mpu_rw_intr_grp1_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100
-
-/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int spu_intr4 : 1;
-  unsigned int dummy1    : 3;
-  unsigned int spu_intr5 : 1;
-  unsigned int dummy2    : 3;
-  unsigned int spu_intr6 : 1;
-  unsigned int dummy3    : 3;
-  unsigned int spu_intr7 : 1;
-  unsigned int dummy4    : 19;
-} reg_iop_sw_mpu_rw_ack_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104
-
-/* Register r_intr_grp1, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int spu_intr4      : 1;
-  unsigned int trigger_grp4   : 1;
-  unsigned int fifo_out_extra : 1;
-  unsigned int dmc_out        : 1;
-  unsigned int spu_intr5      : 1;
-  unsigned int trigger_grp5   : 1;
-  unsigned int fifo_in_extra  : 1;
-  unsigned int dmc_in         : 1;
-  unsigned int spu_intr6      : 1;
-  unsigned int trigger_grp6   : 1;
-  unsigned int timer_grp0     : 1;
-  unsigned int fifo_out       : 1;
-  unsigned int spu_intr7      : 1;
-  unsigned int trigger_grp7   : 1;
-  unsigned int timer_grp1     : 1;
-  unsigned int fifo_in        : 1;
-  unsigned int dummy1         : 16;
-} reg_iop_sw_mpu_r_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108
-
-/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int spu_intr4      : 1;
-  unsigned int trigger_grp4   : 1;
-  unsigned int fifo_out_extra : 1;
-  unsigned int dmc_out        : 1;
-  unsigned int spu_intr5      : 1;
-  unsigned int trigger_grp5   : 1;
-  unsigned int fifo_in_extra  : 1;
-  unsigned int dmc_in         : 1;
-  unsigned int spu_intr6      : 1;
-  unsigned int trigger_grp6   : 1;
-  unsigned int timer_grp0     : 1;
-  unsigned int fifo_out       : 1;
-  unsigned int spu_intr7      : 1;
-  unsigned int trigger_grp7   : 1;
-  unsigned int timer_grp1     : 1;
-  unsigned int fifo_in        : 1;
-  unsigned int dummy1         : 16;
-} reg_iop_sw_mpu_r_masked_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112
-
-/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int spu_intr8      : 1;
-  unsigned int trigger_grp0   : 1;
-  unsigned int timer_grp0     : 1;
-  unsigned int fifo_out       : 1;
-  unsigned int spu_intr9      : 1;
-  unsigned int trigger_grp1   : 1;
-  unsigned int timer_grp1     : 1;
-  unsigned int fifo_in        : 1;
-  unsigned int spu_intr10     : 1;
-  unsigned int trigger_grp2   : 1;
-  unsigned int fifo_out_extra : 1;
-  unsigned int dmc_out        : 1;
-  unsigned int spu_intr11     : 1;
-  unsigned int trigger_grp3   : 1;
-  unsigned int fifo_in_extra  : 1;
-  unsigned int dmc_in         : 1;
-  unsigned int dummy1         : 16;
-} reg_iop_sw_mpu_rw_intr_grp2_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116
-
-/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int spu_intr8  : 1;
-  unsigned int dummy1     : 3;
-  unsigned int spu_intr9  : 1;
-  unsigned int dummy2     : 3;
-  unsigned int spu_intr10 : 1;
-  unsigned int dummy3     : 3;
-  unsigned int spu_intr11 : 1;
-  unsigned int dummy4     : 19;
-} reg_iop_sw_mpu_rw_ack_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120
-
-/* Register r_intr_grp2, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int spu_intr8      : 1;
-  unsigned int trigger_grp0   : 1;
-  unsigned int timer_grp0     : 1;
-  unsigned int fifo_out       : 1;
-  unsigned int spu_intr9      : 1;
-  unsigned int trigger_grp1   : 1;
-  unsigned int timer_grp1     : 1;
-  unsigned int fifo_in        : 1;
-  unsigned int spu_intr10     : 1;
-  unsigned int trigger_grp2   : 1;
-  unsigned int fifo_out_extra : 1;
-  unsigned int dmc_out        : 1;
-  unsigned int spu_intr11     : 1;
-  unsigned int trigger_grp3   : 1;
-  unsigned int fifo_in_extra  : 1;
-  unsigned int dmc_in         : 1;
-  unsigned int dummy1         : 16;
-} reg_iop_sw_mpu_r_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124
-
-/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int spu_intr8      : 1;
-  unsigned int trigger_grp0   : 1;
-  unsigned int timer_grp0     : 1;
-  unsigned int fifo_out       : 1;
-  unsigned int spu_intr9      : 1;
-  unsigned int trigger_grp1   : 1;
-  unsigned int timer_grp1     : 1;
-  unsigned int fifo_in        : 1;
-  unsigned int spu_intr10     : 1;
-  unsigned int trigger_grp2   : 1;
-  unsigned int fifo_out_extra : 1;
-  unsigned int dmc_out        : 1;
-  unsigned int spu_intr11     : 1;
-  unsigned int trigger_grp3   : 1;
-  unsigned int fifo_in_extra  : 1;
-  unsigned int dmc_in         : 1;
-  unsigned int dummy1         : 16;
-} reg_iop_sw_mpu_r_masked_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128
-
-/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int spu_intr12     : 1;
-  unsigned int trigger_grp4   : 1;
-  unsigned int fifo_out_extra : 1;
-  unsigned int dmc_out        : 1;
-  unsigned int spu_intr13     : 1;
-  unsigned int trigger_grp5   : 1;
-  unsigned int fifo_in_extra  : 1;
-  unsigned int dmc_in         : 1;
-  unsigned int spu_intr14     : 1;
-  unsigned int trigger_grp6   : 1;
-  unsigned int timer_grp0     : 1;
-  unsigned int fifo_out       : 1;
-  unsigned int spu_intr15     : 1;
-  unsigned int trigger_grp7   : 1;
-  unsigned int timer_grp1     : 1;
-  unsigned int fifo_in        : 1;
-  unsigned int dummy1         : 16;
-} reg_iop_sw_mpu_rw_intr_grp3_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132
-
-/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
-typedef struct {
-  unsigned int spu_intr12 : 1;
-  unsigned int dummy1     : 3;
-  unsigned int spu_intr13 : 1;
-  unsigned int dummy2     : 3;
-  unsigned int spu_intr14 : 1;
-  unsigned int dummy3     : 3;
-  unsigned int spu_intr15 : 1;
-  unsigned int dummy4     : 19;
-} reg_iop_sw_mpu_rw_ack_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136
-
-/* Register r_intr_grp3, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int spu_intr12     : 1;
-  unsigned int trigger_grp4   : 1;
-  unsigned int fifo_out_extra : 1;
-  unsigned int dmc_out        : 1;
-  unsigned int spu_intr13     : 1;
-  unsigned int trigger_grp5   : 1;
-  unsigned int fifo_in_extra  : 1;
-  unsigned int dmc_in         : 1;
-  unsigned int spu_intr14     : 1;
-  unsigned int trigger_grp6   : 1;
-  unsigned int timer_grp0     : 1;
-  unsigned int fifo_out       : 1;
-  unsigned int spu_intr15     : 1;
-  unsigned int trigger_grp7   : 1;
-  unsigned int timer_grp1     : 1;
-  unsigned int fifo_in        : 1;
-  unsigned int dummy1         : 16;
-} reg_iop_sw_mpu_r_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140
-
-/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
-typedef struct {
-  unsigned int spu_intr12     : 1;
-  unsigned int trigger_grp4   : 1;
-  unsigned int fifo_out_extra : 1;
-  unsigned int dmc_out        : 1;
-  unsigned int spu_intr13     : 1;
-  unsigned int trigger_grp5   : 1;
-  unsigned int fifo_in_extra  : 1;
-  unsigned int dmc_in         : 1;
-  unsigned int spu_intr14     : 1;
-  unsigned int trigger_grp6   : 1;
-  unsigned int timer_grp0     : 1;
-  unsigned int fifo_out       : 1;
-  unsigned int spu_intr15     : 1;
-  unsigned int trigger_grp7   : 1;
-  unsigned int timer_grp1     : 1;
-  unsigned int fifo_in        : 1;
-  unsigned int dummy1         : 16;
-} reg_iop_sw_mpu_r_masked_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144
-
-
-/* Constants */
-enum {
-  regk_iop_sw_mpu_copy                     = 0x00000000,
-  regk_iop_sw_mpu_cpu                      = 0x00000000,
-  regk_iop_sw_mpu_mpu                      = 0x00000001,
-  regk_iop_sw_mpu_no                       = 0x00000000,
-  regk_iop_sw_mpu_nop                      = 0x00000000,
-  regk_iop_sw_mpu_rd                       = 0x00000002,
-  regk_iop_sw_mpu_reg_copy                 = 0x00000001,
-  regk_iop_sw_mpu_rw_bus_clr_mask_default  = 0x00000000,
-  regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_bus_set_mask_default  = 0x00000000,
-  regk_iop_sw_mpu_rw_gio_clr_mask_default  = 0x00000000,
-  regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_gio_set_mask_default  = 0x00000000,
-  regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
-  regk_iop_sw_mpu_rw_sw_cfg_owner_default  = 0x00000000,
-  regk_iop_sw_mpu_set                      = 0x00000001,
-  regk_iop_sw_mpu_spu                      = 0x00000002,
-  regk_iop_sw_mpu_wr                       = 0x00000003,
-  regk_iop_sw_mpu_yes                      = 0x00000001
-};
-#endif /* __iop_sw_mpu_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h
deleted file mode 100644
index c8560b865a1a..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h
+++ /dev/null
@@ -1,441 +0,0 @@
-#ifndef __iop_sw_spu_defs_h
-#define __iop_sw_spu_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           iop_sw_spu.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_spu */
-
-/* Register r_mpu_trace, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_mpu_trace;
-#define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0
-
-/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int keep_owner : 1;
-  unsigned int cmd        : 2;
-  unsigned int size       : 3;
-  unsigned int wr_spu_mem : 1;
-  unsigned int dummy1     : 25;
-} reg_iop_sw_spu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4
-
-/* Register rw_mc_data, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_spu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8
-
-/* Register rw_mc_addr, scope iop_sw_spu, type rw */
-typedef unsigned int reg_iop_sw_spu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12
-
-/* Register rs_mc_data, scope iop_sw_spu, type rs */
-typedef unsigned int reg_iop_sw_spu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16
-
-/* Register r_mc_data, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_r_mc_data 20
-
-/* Register r_mc_stat, scope iop_sw_spu, type r */
-typedef struct {
-  unsigned int busy_cpu     : 1;
-  unsigned int busy_mpu     : 1;
-  unsigned int busy_spu     : 1;
-  unsigned int owned_by_cpu : 1;
-  unsigned int owned_by_mpu : 1;
-  unsigned int owned_by_spu : 1;
-  unsigned int dummy1       : 26;
-} reg_iop_sw_spu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24
-
-/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28
-
-/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 1;
-  unsigned int byte1 : 1;
-  unsigned int byte2 : 1;
-  unsigned int byte3 : 1;
-  unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40
-
-/* Register r_bus_in, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_bus_in;
-#define REG_RD_ADDR_iop_sw_spu_r_bus_in 44
-
-/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48
-
-/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60
-
-/* Register r_gio_in, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_spu_r_gio_in 64
-
-/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68
-
-/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72
-
-/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte0 : 8;
-  unsigned int byte1 : 8;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76
-
-/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int byte2 : 8;
-  unsigned int byte3 : 8;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80
-
-/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84
-
-/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88
-
-/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92
-
-/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96
-
-/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100
-
-/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104
-
-/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108
-
-/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int val : 16;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112
-
-/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int intr0  : 1;
-  unsigned int intr1  : 1;
-  unsigned int intr2  : 1;
-  unsigned int intr3  : 1;
-  unsigned int intr4  : 1;
-  unsigned int intr5  : 1;
-  unsigned int intr6  : 1;
-  unsigned int intr7  : 1;
-  unsigned int intr8  : 1;
-  unsigned int intr9  : 1;
-  unsigned int intr10 : 1;
-  unsigned int intr11 : 1;
-  unsigned int intr12 : 1;
-  unsigned int intr13 : 1;
-  unsigned int intr14 : 1;
-  unsigned int intr15 : 1;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_cpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116
-#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116
-
-/* Register r_cpu_intr, scope iop_sw_spu, type r */
-typedef struct {
-  unsigned int intr0  : 1;
-  unsigned int intr1  : 1;
-  unsigned int intr2  : 1;
-  unsigned int intr3  : 1;
-  unsigned int intr4  : 1;
-  unsigned int intr5  : 1;
-  unsigned int intr6  : 1;
-  unsigned int intr7  : 1;
-  unsigned int intr8  : 1;
-  unsigned int intr9  : 1;
-  unsigned int intr10 : 1;
-  unsigned int intr11 : 1;
-  unsigned int intr12 : 1;
-  unsigned int intr13 : 1;
-  unsigned int intr14 : 1;
-  unsigned int intr15 : 1;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_r_cpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120
-
-/* Register r_hw_intr, scope iop_sw_spu, type r */
-typedef struct {
-  unsigned int trigger_grp0   : 1;
-  unsigned int trigger_grp1   : 1;
-  unsigned int trigger_grp2   : 1;
-  unsigned int trigger_grp3   : 1;
-  unsigned int trigger_grp4   : 1;
-  unsigned int trigger_grp5   : 1;
-  unsigned int trigger_grp6   : 1;
-  unsigned int trigger_grp7   : 1;
-  unsigned int timer_grp0     : 1;
-  unsigned int timer_grp1     : 1;
-  unsigned int fifo_out       : 1;
-  unsigned int fifo_out_extra : 1;
-  unsigned int fifo_in        : 1;
-  unsigned int fifo_in_extra  : 1;
-  unsigned int dmc_out        : 1;
-  unsigned int dmc_in         : 1;
-  unsigned int dummy1         : 16;
-} reg_iop_sw_spu_r_hw_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124
-
-/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
-typedef struct {
-  unsigned int intr0  : 1;
-  unsigned int intr1  : 1;
-  unsigned int intr2  : 1;
-  unsigned int intr3  : 1;
-  unsigned int intr4  : 1;
-  unsigned int intr5  : 1;
-  unsigned int intr6  : 1;
-  unsigned int intr7  : 1;
-  unsigned int intr8  : 1;
-  unsigned int intr9  : 1;
-  unsigned int intr10 : 1;
-  unsigned int intr11 : 1;
-  unsigned int intr12 : 1;
-  unsigned int intr13 : 1;
-  unsigned int intr14 : 1;
-  unsigned int intr15 : 1;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_mpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128
-#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128
-
-/* Register r_mpu_intr, scope iop_sw_spu, type r */
-typedef struct {
-  unsigned int intr0  : 1;
-  unsigned int intr1  : 1;
-  unsigned int intr2  : 1;
-  unsigned int intr3  : 1;
-  unsigned int intr4  : 1;
-  unsigned int intr5  : 1;
-  unsigned int intr6  : 1;
-  unsigned int intr7  : 1;
-  unsigned int intr8  : 1;
-  unsigned int intr9  : 1;
-  unsigned int intr10 : 1;
-  unsigned int intr11 : 1;
-  unsigned int intr12 : 1;
-  unsigned int intr13 : 1;
-  unsigned int intr14 : 1;
-  unsigned int intr15 : 1;
-  unsigned int dummy1 : 16;
-} reg_iop_sw_spu_r_mpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132
-
-
-/* Constants */
-enum {
-  regk_iop_sw_spu_copy                     = 0x00000000,
-  regk_iop_sw_spu_no                       = 0x00000000,
-  regk_iop_sw_spu_nop                      = 0x00000000,
-  regk_iop_sw_spu_rd                       = 0x00000002,
-  regk_iop_sw_spu_reg_copy                 = 0x00000001,
-  regk_iop_sw_spu_rw_bus_clr_mask_default  = 0x00000000,
-  regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000,
-  regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000,
-  regk_iop_sw_spu_rw_bus_set_mask_default  = 0x00000000,
-  regk_iop_sw_spu_rw_gio_clr_mask_default  = 0x00000000,
-  regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000,
-  regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,
-  regk_iop_sw_spu_rw_gio_set_mask_default  = 0x00000000,
-  regk_iop_sw_spu_set                      = 0x00000001,
-  regk_iop_sw_spu_wr                       = 0x00000003,
-  regk_iop_sw_spu_yes                      = 0x00000001
-};
-#endif /* __iop_sw_spu_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h
deleted file mode 100644
index 20de425e652b..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h
+++ /dev/null
@@ -1,96 +0,0 @@
-#ifndef __iop_version_defs_h
-#define __iop_version_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           iop_version.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile iop_version_defs.h iop_version.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_version */
-
-/* Register r_version, scope iop_version, type r */
-typedef struct {
-  unsigned int nr : 8;
-  unsigned int dummy1 : 24;
-} reg_iop_version_r_version;
-#define REG_RD_ADDR_iop_version_r_version 0
-
-
-/* Constants */
-enum {
-  regk_iop_version_v2_0                    = 0x00000002
-};
-#endif /* __iop_version_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h
deleted file mode 100644
index 243ac3c882cb..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h
+++ /dev/null
@@ -1,142 +0,0 @@
-#ifndef __l2cache_defs_h
-#define __l2cache_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           l2cache.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope l2cache */
-
-/* Register rw_cfg, scope l2cache, type rw */
-typedef struct {
-  unsigned int en : 1;
-  unsigned int dummy1 : 31;
-} reg_l2cache_rw_cfg;
-#define REG_RD_ADDR_l2cache_rw_cfg 0
-#define REG_WR_ADDR_l2cache_rw_cfg 0
-
-/* Register rw_ctrl, scope l2cache, type rw */
-typedef struct {
-  unsigned int dummy1 : 7;
-  unsigned int cbase : 9;
-  unsigned int dummy2 : 4;
-  unsigned int csize : 10;
-  unsigned int dummy3 : 2;
-} reg_l2cache_rw_ctrl;
-#define REG_RD_ADDR_l2cache_rw_ctrl 4
-#define REG_WR_ADDR_l2cache_rw_ctrl 4
-
-/* Register rw_idxop, scope l2cache, type rw */
-typedef struct {
-  unsigned int idx : 10;
-  unsigned int dummy1 : 14;
-  unsigned int way : 3;
-  unsigned int dummy2 : 2;
-  unsigned int cmd : 3;
-} reg_l2cache_rw_idxop;
-#define REG_RD_ADDR_l2cache_rw_idxop 8
-#define REG_WR_ADDR_l2cache_rw_idxop 8
-
-/* Register rw_addrop_addr, scope l2cache, type rw */
-typedef struct {
-  unsigned int addr : 32;
-} reg_l2cache_rw_addrop_addr;
-#define REG_RD_ADDR_l2cache_rw_addrop_addr 12
-#define REG_WR_ADDR_l2cache_rw_addrop_addr 12
-
-/* Register rw_addrop_ctrl, scope l2cache, type rw */
-typedef struct {
-  unsigned int size : 16;
-  unsigned int dummy1 : 13;
-  unsigned int cmd  : 3;
-} reg_l2cache_rw_addrop_ctrl;
-#define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16
-#define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16
-
-
-/* Constants */
-enum {
-  regk_l2cache_flush                       = 0x00000001,
-  regk_l2cache_no                          = 0x00000000,
-  regk_l2cache_rw_addrop_addr_default      = 0x00000000,
-  regk_l2cache_rw_addrop_ctrl_default      = 0x00000000,
-  regk_l2cache_rw_cfg_default              = 0x00000000,
-  regk_l2cache_rw_ctrl_default             = 0x00000000,
-  regk_l2cache_rw_idxop_default            = 0x00000000,
-  regk_l2cache_yes                         = 0x00000001
-};
-#endif /* __l2cache_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h
deleted file mode 100644
index c0e7628cbf7d..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h
+++ /dev/null
@@ -1,482 +0,0 @@
-#ifndef __marb_bar_defs_h
-#define __marb_bar_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           marb_bar.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_bar */
-
-#define STRIDE_marb_bar_rw_ddr2_slots 4
-/* Register rw_ddr2_slots, scope marb_bar, type rw */
-typedef struct {
-  unsigned int owner : 4;
-  unsigned int dummy1 : 28;
-} reg_marb_bar_rw_ddr2_slots;
-#define REG_RD_ADDR_marb_bar_rw_ddr2_slots 0
-#define REG_WR_ADDR_marb_bar_rw_ddr2_slots 0
-
-/* Register rw_h264_rd_burst, scope marb_bar, type rw */
-typedef struct {
-  unsigned int ddr2_bsize : 2;
-  unsigned int dummy1     : 30;
-} reg_marb_bar_rw_h264_rd_burst;
-#define REG_RD_ADDR_marb_bar_rw_h264_rd_burst 256
-#define REG_WR_ADDR_marb_bar_rw_h264_rd_burst 256
-
-/* Register rw_h264_wr_burst, scope marb_bar, type rw */
-typedef struct {
-  unsigned int ddr2_bsize : 2;
-  unsigned int dummy1     : 30;
-} reg_marb_bar_rw_h264_wr_burst;
-#define REG_RD_ADDR_marb_bar_rw_h264_wr_burst 260
-#define REG_WR_ADDR_marb_bar_rw_h264_wr_burst 260
-
-/* Register rw_ccd_burst, scope marb_bar, type rw */
-typedef struct {
-  unsigned int ddr2_bsize : 2;
-  unsigned int dummy1     : 30;
-} reg_marb_bar_rw_ccd_burst;
-#define REG_RD_ADDR_marb_bar_rw_ccd_burst 264
-#define REG_WR_ADDR_marb_bar_rw_ccd_burst 264
-
-/* Register rw_vin_wr_burst, scope marb_bar, type rw */
-typedef struct {
-  unsigned int ddr2_bsize : 2;
-  unsigned int dummy1     : 30;
-} reg_marb_bar_rw_vin_wr_burst;
-#define REG_RD_ADDR_marb_bar_rw_vin_wr_burst 268
-#define REG_WR_ADDR_marb_bar_rw_vin_wr_burst 268
-
-/* Register rw_vin_rd_burst, scope marb_bar, type rw */
-typedef struct {
-  unsigned int ddr2_bsize : 2;
-  unsigned int dummy1     : 30;
-} reg_marb_bar_rw_vin_rd_burst;
-#define REG_RD_ADDR_marb_bar_rw_vin_rd_burst 272
-#define REG_WR_ADDR_marb_bar_rw_vin_rd_burst 272
-
-/* Register rw_sclr_rd_burst, scope marb_bar, type rw */
-typedef struct {
-  unsigned int ddr2_bsize : 2;
-  unsigned int dummy1     : 30;
-} reg_marb_bar_rw_sclr_rd_burst;
-#define REG_RD_ADDR_marb_bar_rw_sclr_rd_burst 276
-#define REG_WR_ADDR_marb_bar_rw_sclr_rd_burst 276
-
-/* Register rw_vout_burst, scope marb_bar, type rw */
-typedef struct {
-  unsigned int ddr2_bsize : 2;
-  unsigned int dummy1     : 30;
-} reg_marb_bar_rw_vout_burst;
-#define REG_RD_ADDR_marb_bar_rw_vout_burst 280
-#define REG_WR_ADDR_marb_bar_rw_vout_burst 280
-
-/* Register rw_sclr_fifo_burst, scope marb_bar, type rw */
-typedef struct {
-  unsigned int ddr2_bsize : 2;
-  unsigned int dummy1     : 30;
-} reg_marb_bar_rw_sclr_fifo_burst;
-#define REG_RD_ADDR_marb_bar_rw_sclr_fifo_burst 284
-#define REG_WR_ADDR_marb_bar_rw_sclr_fifo_burst 284
-
-/* Register rw_l2cache_burst, scope marb_bar, type rw */
-typedef struct {
-  unsigned int ddr2_bsize : 2;
-  unsigned int dummy1     : 30;
-} reg_marb_bar_rw_l2cache_burst;
-#define REG_RD_ADDR_marb_bar_rw_l2cache_burst 288
-#define REG_WR_ADDR_marb_bar_rw_l2cache_burst 288
-
-/* Register rw_intr_mask, scope marb_bar, type rw */
-typedef struct {
-  unsigned int bp0 : 1;
-  unsigned int bp1 : 1;
-  unsigned int bp2 : 1;
-  unsigned int bp3 : 1;
-  unsigned int dummy1 : 28;
-} reg_marb_bar_rw_intr_mask;
-#define REG_RD_ADDR_marb_bar_rw_intr_mask 292
-#define REG_WR_ADDR_marb_bar_rw_intr_mask 292
-
-/* Register rw_ack_intr, scope marb_bar, type rw */
-typedef struct {
-  unsigned int bp0 : 1;
-  unsigned int bp1 : 1;
-  unsigned int bp2 : 1;
-  unsigned int bp3 : 1;
-  unsigned int dummy1 : 28;
-} reg_marb_bar_rw_ack_intr;
-#define REG_RD_ADDR_marb_bar_rw_ack_intr 296
-#define REG_WR_ADDR_marb_bar_rw_ack_intr 296
-
-/* Register r_intr, scope marb_bar, type r */
-typedef struct {
-  unsigned int bp0 : 1;
-  unsigned int bp1 : 1;
-  unsigned int bp2 : 1;
-  unsigned int bp3 : 1;
-  unsigned int dummy1 : 28;
-} reg_marb_bar_r_intr;
-#define REG_RD_ADDR_marb_bar_r_intr 300
-
-/* Register r_masked_intr, scope marb_bar, type r */
-typedef struct {
-  unsigned int bp0 : 1;
-  unsigned int bp1 : 1;
-  unsigned int bp2 : 1;
-  unsigned int bp3 : 1;
-  unsigned int dummy1 : 28;
-} reg_marb_bar_r_masked_intr;
-#define REG_RD_ADDR_marb_bar_r_masked_intr 304
-
-/* Register rw_stop_mask, scope marb_bar, type rw */
-typedef struct {
-  unsigned int h264_rd   : 1;
-  unsigned int h264_wr   : 1;
-  unsigned int ccd       : 1;
-  unsigned int vin_wr    : 1;
-  unsigned int vin_rd    : 1;
-  unsigned int sclr_rd   : 1;
-  unsigned int vout      : 1;
-  unsigned int sclr_fifo : 1;
-  unsigned int l2cache   : 1;
-  unsigned int dummy1    : 23;
-} reg_marb_bar_rw_stop_mask;
-#define REG_RD_ADDR_marb_bar_rw_stop_mask 308
-#define REG_WR_ADDR_marb_bar_rw_stop_mask 308
-
-/* Register r_stopped, scope marb_bar, type r */
-typedef struct {
-  unsigned int h264_rd   : 1;
-  unsigned int h264_wr   : 1;
-  unsigned int ccd       : 1;
-  unsigned int vin_wr    : 1;
-  unsigned int vin_rd    : 1;
-  unsigned int sclr_rd   : 1;
-  unsigned int vout      : 1;
-  unsigned int sclr_fifo : 1;
-  unsigned int l2cache   : 1;
-  unsigned int dummy1    : 23;
-} reg_marb_bar_r_stopped;
-#define REG_RD_ADDR_marb_bar_r_stopped 312
-
-/* Register rw_no_snoop, scope marb_bar, type rw */
-typedef struct {
-  unsigned int h264_rd   : 1;
-  unsigned int h264_wr   : 1;
-  unsigned int ccd       : 1;
-  unsigned int vin_wr    : 1;
-  unsigned int vin_rd    : 1;
-  unsigned int sclr_rd   : 1;
-  unsigned int vout      : 1;
-  unsigned int sclr_fifo : 1;
-  unsigned int l2cache   : 1;
-  unsigned int dummy1    : 23;
-} reg_marb_bar_rw_no_snoop;
-#define REG_RD_ADDR_marb_bar_rw_no_snoop 576
-#define REG_WR_ADDR_marb_bar_rw_no_snoop 576
-
-
-/* Constants */
-enum {
-  regk_marb_bar_ccd                        = 0x00000002,
-  regk_marb_bar_h264_rd                    = 0x00000000,
-  regk_marb_bar_h264_wr                    = 0x00000001,
-  regk_marb_bar_l2cache                    = 0x00000008,
-  regk_marb_bar_no                         = 0x00000000,
-  regk_marb_bar_r_stopped_default          = 0x00000000,
-  regk_marb_bar_rw_ccd_burst_default       = 0x00000000,
-  regk_marb_bar_rw_ddr2_slots_default      = 0x00000000,
-  regk_marb_bar_rw_ddr2_slots_size         = 0x00000040,
-  regk_marb_bar_rw_h264_rd_burst_default   = 0x00000000,
-  regk_marb_bar_rw_h264_wr_burst_default   = 0x00000000,
-  regk_marb_bar_rw_intr_mask_default       = 0x00000000,
-  regk_marb_bar_rw_l2cache_burst_default   = 0x00000000,
-  regk_marb_bar_rw_no_snoop_default        = 0x00000000,
-  regk_marb_bar_rw_sclr_fifo_burst_default = 0x00000000,
-  regk_marb_bar_rw_sclr_rd_burst_default   = 0x00000000,
-  regk_marb_bar_rw_stop_mask_default       = 0x00000000,
-  regk_marb_bar_rw_vin_rd_burst_default    = 0x00000000,
-  regk_marb_bar_rw_vin_wr_burst_default    = 0x00000000,
-  regk_marb_bar_rw_vout_burst_default      = 0x00000000,
-  regk_marb_bar_sclr_fifo                  = 0x00000007,
-  regk_marb_bar_sclr_rd                    = 0x00000005,
-  regk_marb_bar_vin_rd                     = 0x00000004,
-  regk_marb_bar_vin_wr                     = 0x00000003,
-  regk_marb_bar_vout                       = 0x00000006,
-  regk_marb_bar_yes                        = 0x00000001
-};
-#endif /* __marb_bar_defs_h */
-#ifndef __marb_bar_bp_defs_h
-#define __marb_bar_bp_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           marb_bar.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_bar_bp */
-
-/* Register rw_first_addr, scope marb_bar_bp, type rw */
-typedef unsigned int reg_marb_bar_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_bar_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_bar_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_bar_bp, type rw */
-typedef unsigned int reg_marb_bar_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_bar_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_bar_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_bar_bp, type rw */
-typedef struct {
-  unsigned int rd         : 1;
-  unsigned int wr         : 1;
-  unsigned int rd_excl    : 1;
-  unsigned int pri_wr     : 1;
-  unsigned int us_rd      : 1;
-  unsigned int us_wr      : 1;
-  unsigned int us_rd_excl : 1;
-  unsigned int us_pri_wr  : 1;
-  unsigned int dummy1     : 24;
-} reg_marb_bar_bp_rw_op;
-#define REG_RD_ADDR_marb_bar_bp_rw_op 8
-#define REG_WR_ADDR_marb_bar_bp_rw_op 8
-
-/* Register rw_clients, scope marb_bar_bp, type rw */
-typedef struct {
-  unsigned int h264_rd   : 1;
-  unsigned int h264_wr   : 1;
-  unsigned int ccd       : 1;
-  unsigned int vin_wr    : 1;
-  unsigned int vin_rd    : 1;
-  unsigned int sclr_rd   : 1;
-  unsigned int vout      : 1;
-  unsigned int sclr_fifo : 1;
-  unsigned int l2cache   : 1;
-  unsigned int dummy1    : 23;
-} reg_marb_bar_bp_rw_clients;
-#define REG_RD_ADDR_marb_bar_bp_rw_clients 12
-#define REG_WR_ADDR_marb_bar_bp_rw_clients 12
-
-/* Register rw_options, scope marb_bar_bp, type rw */
-typedef struct {
-  unsigned int wrap : 1;
-  unsigned int dummy1 : 31;
-} reg_marb_bar_bp_rw_options;
-#define REG_RD_ADDR_marb_bar_bp_rw_options 16
-#define REG_WR_ADDR_marb_bar_bp_rw_options 16
-
-/* Register r_brk_addr, scope marb_bar_bp, type r */
-typedef unsigned int reg_marb_bar_bp_r_brk_addr;
-#define REG_RD_ADDR_marb_bar_bp_r_brk_addr 20
-
-/* Register r_brk_op, scope marb_bar_bp, type r */
-typedef struct {
-  unsigned int rd         : 1;
-  unsigned int wr         : 1;
-  unsigned int rd_excl    : 1;
-  unsigned int pri_wr     : 1;
-  unsigned int us_rd      : 1;
-  unsigned int us_wr      : 1;
-  unsigned int us_rd_excl : 1;
-  unsigned int us_pri_wr  : 1;
-  unsigned int dummy1     : 24;
-} reg_marb_bar_bp_r_brk_op;
-#define REG_RD_ADDR_marb_bar_bp_r_brk_op 24
-
-/* Register r_brk_clients, scope marb_bar_bp, type r */
-typedef struct {
-  unsigned int h264_rd   : 1;
-  unsigned int h264_wr   : 1;
-  unsigned int ccd       : 1;
-  unsigned int vin_wr    : 1;
-  unsigned int vin_rd    : 1;
-  unsigned int sclr_rd   : 1;
-  unsigned int vout      : 1;
-  unsigned int sclr_fifo : 1;
-  unsigned int l2cache   : 1;
-  unsigned int dummy1    : 23;
-} reg_marb_bar_bp_r_brk_clients;
-#define REG_RD_ADDR_marb_bar_bp_r_brk_clients 28
-
-/* Register r_brk_first_client, scope marb_bar_bp, type r */
-typedef struct {
-  unsigned int h264_rd   : 1;
-  unsigned int h264_wr   : 1;
-  unsigned int ccd       : 1;
-  unsigned int vin_wr    : 1;
-  unsigned int vin_rd    : 1;
-  unsigned int sclr_rd   : 1;
-  unsigned int vout      : 1;
-  unsigned int sclr_fifo : 1;
-  unsigned int l2cache   : 1;
-  unsigned int dummy1    : 23;
-} reg_marb_bar_bp_r_brk_first_client;
-#define REG_RD_ADDR_marb_bar_bp_r_brk_first_client 32
-
-/* Register r_brk_size, scope marb_bar_bp, type r */
-typedef unsigned int reg_marb_bar_bp_r_brk_size;
-#define REG_RD_ADDR_marb_bar_bp_r_brk_size 36
-
-/* Register rw_ack, scope marb_bar_bp, type rw */
-typedef unsigned int reg_marb_bar_bp_rw_ack;
-#define REG_RD_ADDR_marb_bar_bp_rw_ack 40
-#define REG_WR_ADDR_marb_bar_bp_rw_ack 40
-
-
-/* Constants */
-enum {
-  regk_marb_bar_bp_no                      = 0x00000000,
-  regk_marb_bar_bp_rw_op_default           = 0x00000000,
-  regk_marb_bar_bp_rw_options_default      = 0x00000000,
-  regk_marb_bar_bp_yes                     = 0x00000001
-};
-#endif /* __marb_bar_bp_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h
deleted file mode 100644
index 2baa833f109a..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h
+++ /dev/null
@@ -1,626 +0,0 @@
-#ifndef __marb_foo_defs_h
-#define __marb_foo_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           marb_foo.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_foo */
-
-#define STRIDE_marb_foo_rw_intm_slots 4
-/* Register rw_intm_slots, scope marb_foo, type rw */
-typedef struct {
-  unsigned int owner : 4;
-  unsigned int dummy1 : 28;
-} reg_marb_foo_rw_intm_slots;
-#define REG_RD_ADDR_marb_foo_rw_intm_slots 0
-#define REG_WR_ADDR_marb_foo_rw_intm_slots 0
-
-#define STRIDE_marb_foo_rw_l2_slots 4
-/* Register rw_l2_slots, scope marb_foo, type rw */
-typedef struct {
-  unsigned int owner : 4;
-  unsigned int dummy1 : 28;
-} reg_marb_foo_rw_l2_slots;
-#define REG_RD_ADDR_marb_foo_rw_l2_slots 256
-#define REG_WR_ADDR_marb_foo_rw_l2_slots 256
-
-#define STRIDE_marb_foo_rw_regs_slots 4
-/* Register rw_regs_slots, scope marb_foo, type rw */
-typedef struct {
-  unsigned int owner : 4;
-  unsigned int dummy1 : 28;
-} reg_marb_foo_rw_regs_slots;
-#define REG_RD_ADDR_marb_foo_rw_regs_slots 512
-#define REG_WR_ADDR_marb_foo_rw_regs_slots 512
-
-/* Register rw_sclr_burst, scope marb_foo, type rw */
-typedef struct {
-  unsigned int intm_bsize : 2;
-  unsigned int l2_bsize   : 2;
-  unsigned int dummy1     : 28;
-} reg_marb_foo_rw_sclr_burst;
-#define REG_RD_ADDR_marb_foo_rw_sclr_burst 528
-#define REG_WR_ADDR_marb_foo_rw_sclr_burst 528
-
-/* Register rw_dma0_burst, scope marb_foo, type rw */
-typedef struct {
-  unsigned int intm_bsize : 2;
-  unsigned int l2_bsize   : 2;
-  unsigned int dummy1     : 28;
-} reg_marb_foo_rw_dma0_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma0_burst 532
-#define REG_WR_ADDR_marb_foo_rw_dma0_burst 532
-
-/* Register rw_dma1_burst, scope marb_foo, type rw */
-typedef struct {
-  unsigned int intm_bsize : 2;
-  unsigned int l2_bsize   : 2;
-  unsigned int dummy1     : 28;
-} reg_marb_foo_rw_dma1_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma1_burst 536
-#define REG_WR_ADDR_marb_foo_rw_dma1_burst 536
-
-/* Register rw_dma2_burst, scope marb_foo, type rw */
-typedef struct {
-  unsigned int intm_bsize : 2;
-  unsigned int l2_bsize   : 2;
-  unsigned int dummy1     : 28;
-} reg_marb_foo_rw_dma2_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma2_burst 540
-#define REG_WR_ADDR_marb_foo_rw_dma2_burst 540
-
-/* Register rw_dma3_burst, scope marb_foo, type rw */
-typedef struct {
-  unsigned int intm_bsize : 2;
-  unsigned int l2_bsize   : 2;
-  unsigned int dummy1     : 28;
-} reg_marb_foo_rw_dma3_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma3_burst 544
-#define REG_WR_ADDR_marb_foo_rw_dma3_burst 544
-
-/* Register rw_dma4_burst, scope marb_foo, type rw */
-typedef struct {
-  unsigned int intm_bsize : 2;
-  unsigned int l2_bsize   : 2;
-  unsigned int dummy1     : 28;
-} reg_marb_foo_rw_dma4_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma4_burst 548
-#define REG_WR_ADDR_marb_foo_rw_dma4_burst 548
-
-/* Register rw_dma5_burst, scope marb_foo, type rw */
-typedef struct {
-  unsigned int intm_bsize : 2;
-  unsigned int l2_bsize   : 2;
-  unsigned int dummy1     : 28;
-} reg_marb_foo_rw_dma5_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma5_burst 552
-#define REG_WR_ADDR_marb_foo_rw_dma5_burst 552
-
-/* Register rw_dma6_burst, scope marb_foo, type rw */
-typedef struct {
-  unsigned int intm_bsize : 2;
-  unsigned int l2_bsize   : 2;
-  unsigned int dummy1     : 28;
-} reg_marb_foo_rw_dma6_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma6_burst 556
-#define REG_WR_ADDR_marb_foo_rw_dma6_burst 556
-
-/* Register rw_dma7_burst, scope marb_foo, type rw */
-typedef struct {
-  unsigned int intm_bsize : 2;
-  unsigned int l2_bsize   : 2;
-  unsigned int dummy1     : 28;
-} reg_marb_foo_rw_dma7_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma7_burst 560
-#define REG_WR_ADDR_marb_foo_rw_dma7_burst 560
-
-/* Register rw_dma9_burst, scope marb_foo, type rw */
-typedef struct {
-  unsigned int intm_bsize : 2;
-  unsigned int l2_bsize   : 2;
-  unsigned int dummy1     : 28;
-} reg_marb_foo_rw_dma9_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma9_burst 564
-#define REG_WR_ADDR_marb_foo_rw_dma9_burst 564
-
-/* Register rw_dma11_burst, scope marb_foo, type rw */
-typedef struct {
-  unsigned int intm_bsize : 2;
-  unsigned int l2_bsize   : 2;
-  unsigned int dummy1     : 28;
-} reg_marb_foo_rw_dma11_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma11_burst 568
-#define REG_WR_ADDR_marb_foo_rw_dma11_burst 568
-
-/* Register rw_cpui_burst, scope marb_foo, type rw */
-typedef struct {
-  unsigned int intm_bsize : 2;
-  unsigned int l2_bsize   : 2;
-  unsigned int dummy1     : 28;
-} reg_marb_foo_rw_cpui_burst;
-#define REG_RD_ADDR_marb_foo_rw_cpui_burst 572
-#define REG_WR_ADDR_marb_foo_rw_cpui_burst 572
-
-/* Register rw_cpud_burst, scope marb_foo, type rw */
-typedef struct {
-  unsigned int intm_bsize : 2;
-  unsigned int l2_bsize   : 2;
-  unsigned int dummy1     : 28;
-} reg_marb_foo_rw_cpud_burst;
-#define REG_RD_ADDR_marb_foo_rw_cpud_burst 576
-#define REG_WR_ADDR_marb_foo_rw_cpud_burst 576
-
-/* Register rw_iop_burst, scope marb_foo, type rw */
-typedef struct {
-  unsigned int intm_bsize : 2;
-  unsigned int l2_bsize   : 2;
-  unsigned int dummy1     : 28;
-} reg_marb_foo_rw_iop_burst;
-#define REG_RD_ADDR_marb_foo_rw_iop_burst 580
-#define REG_WR_ADDR_marb_foo_rw_iop_burst 580
-
-/* Register rw_ccdstat_burst, scope marb_foo, type rw */
-typedef struct {
-  unsigned int intm_bsize : 2;
-  unsigned int l2_bsize   : 2;
-  unsigned int dummy1     : 28;
-} reg_marb_foo_rw_ccdstat_burst;
-#define REG_RD_ADDR_marb_foo_rw_ccdstat_burst 584
-#define REG_WR_ADDR_marb_foo_rw_ccdstat_burst 584
-
-/* Register rw_intr_mask, scope marb_foo, type rw */
-typedef struct {
-  unsigned int bp0 : 1;
-  unsigned int bp1 : 1;
-  unsigned int bp2 : 1;
-  unsigned int bp3 : 1;
-  unsigned int dummy1 : 28;
-} reg_marb_foo_rw_intr_mask;
-#define REG_RD_ADDR_marb_foo_rw_intr_mask 588
-#define REG_WR_ADDR_marb_foo_rw_intr_mask 588
-
-/* Register rw_ack_intr, scope marb_foo, type rw */
-typedef struct {
-  unsigned int bp0 : 1;
-  unsigned int bp1 : 1;
-  unsigned int bp2 : 1;
-  unsigned int bp3 : 1;
-  unsigned int dummy1 : 28;
-} reg_marb_foo_rw_ack_intr;
-#define REG_RD_ADDR_marb_foo_rw_ack_intr 592
-#define REG_WR_ADDR_marb_foo_rw_ack_intr 592
-
-/* Register r_intr, scope marb_foo, type r */
-typedef struct {
-  unsigned int bp0 : 1;
-  unsigned int bp1 : 1;
-  unsigned int bp2 : 1;
-  unsigned int bp3 : 1;
-  unsigned int dummy1 : 28;
-} reg_marb_foo_r_intr;
-#define REG_RD_ADDR_marb_foo_r_intr 596
-
-/* Register r_masked_intr, scope marb_foo, type r */
-typedef struct {
-  unsigned int bp0 : 1;
-  unsigned int bp1 : 1;
-  unsigned int bp2 : 1;
-  unsigned int bp3 : 1;
-  unsigned int dummy1 : 28;
-} reg_marb_foo_r_masked_intr;
-#define REG_RD_ADDR_marb_foo_r_masked_intr 600
-
-/* Register rw_stop_mask, scope marb_foo, type rw */
-typedef struct {
-  unsigned int sclr    : 1;
-  unsigned int dma0    : 1;
-  unsigned int dma1    : 1;
-  unsigned int dma2    : 1;
-  unsigned int dma3    : 1;
-  unsigned int dma4    : 1;
-  unsigned int dma5    : 1;
-  unsigned int dma6    : 1;
-  unsigned int dma7    : 1;
-  unsigned int dma9    : 1;
-  unsigned int dma11   : 1;
-  unsigned int cpui    : 1;
-  unsigned int cpud    : 1;
-  unsigned int iop     : 1;
-  unsigned int ccdstat : 1;
-  unsigned int dummy1  : 17;
-} reg_marb_foo_rw_stop_mask;
-#define REG_RD_ADDR_marb_foo_rw_stop_mask 604
-#define REG_WR_ADDR_marb_foo_rw_stop_mask 604
-
-/* Register r_stopped, scope marb_foo, type r */
-typedef struct {
-  unsigned int sclr    : 1;
-  unsigned int dma0    : 1;
-  unsigned int dma1    : 1;
-  unsigned int dma2    : 1;
-  unsigned int dma3    : 1;
-  unsigned int dma4    : 1;
-  unsigned int dma5    : 1;
-  unsigned int dma6    : 1;
-  unsigned int dma7    : 1;
-  unsigned int dma9    : 1;
-  unsigned int dma11   : 1;
-  unsigned int cpui    : 1;
-  unsigned int cpud    : 1;
-  unsigned int iop     : 1;
-  unsigned int ccdstat : 1;
-  unsigned int dummy1  : 17;
-} reg_marb_foo_r_stopped;
-#define REG_RD_ADDR_marb_foo_r_stopped 608
-
-/* Register rw_no_snoop, scope marb_foo, type rw */
-typedef struct {
-  unsigned int sclr    : 1;
-  unsigned int dma0    : 1;
-  unsigned int dma1    : 1;
-  unsigned int dma2    : 1;
-  unsigned int dma3    : 1;
-  unsigned int dma4    : 1;
-  unsigned int dma5    : 1;
-  unsigned int dma6    : 1;
-  unsigned int dma7    : 1;
-  unsigned int dma9    : 1;
-  unsigned int dma11   : 1;
-  unsigned int cpui    : 1;
-  unsigned int cpud    : 1;
-  unsigned int iop     : 1;
-  unsigned int ccdstat : 1;
-  unsigned int dummy1  : 17;
-} reg_marb_foo_rw_no_snoop;
-#define REG_RD_ADDR_marb_foo_rw_no_snoop 896
-#define REG_WR_ADDR_marb_foo_rw_no_snoop 896
-
-/* Register rw_no_snoop_rq, scope marb_foo, type rw */
-typedef struct {
-  unsigned int dummy1 : 11;
-  unsigned int cpui : 1;
-  unsigned int cpud : 1;
-  unsigned int dummy2 : 19;
-} reg_marb_foo_rw_no_snoop_rq;
-#define REG_RD_ADDR_marb_foo_rw_no_snoop_rq 900
-#define REG_WR_ADDR_marb_foo_rw_no_snoop_rq 900
-
-
-/* Constants */
-enum {
-  regk_marb_foo_ccdstat                    = 0x0000000e,
-  regk_marb_foo_cpud                       = 0x0000000c,
-  regk_marb_foo_cpui                       = 0x0000000b,
-  regk_marb_foo_dma0                       = 0x00000001,
-  regk_marb_foo_dma1                       = 0x00000002,
-  regk_marb_foo_dma11                      = 0x0000000a,
-  regk_marb_foo_dma2                       = 0x00000003,
-  regk_marb_foo_dma3                       = 0x00000004,
-  regk_marb_foo_dma4                       = 0x00000005,
-  regk_marb_foo_dma5                       = 0x00000006,
-  regk_marb_foo_dma6                       = 0x00000007,
-  regk_marb_foo_dma7                       = 0x00000008,
-  regk_marb_foo_dma9                       = 0x00000009,
-  regk_marb_foo_iop                        = 0x0000000d,
-  regk_marb_foo_no                         = 0x00000000,
-  regk_marb_foo_r_stopped_default          = 0x00000000,
-  regk_marb_foo_rw_ccdstat_burst_default   = 0x00000000,
-  regk_marb_foo_rw_cpud_burst_default      = 0x00000000,
-  regk_marb_foo_rw_cpui_burst_default      = 0x00000000,
-  regk_marb_foo_rw_dma0_burst_default      = 0x00000000,
-  regk_marb_foo_rw_dma11_burst_default     = 0x00000000,
-  regk_marb_foo_rw_dma1_burst_default      = 0x00000000,
-  regk_marb_foo_rw_dma2_burst_default      = 0x00000000,
-  regk_marb_foo_rw_dma3_burst_default      = 0x00000000,
-  regk_marb_foo_rw_dma4_burst_default      = 0x00000000,
-  regk_marb_foo_rw_dma5_burst_default      = 0x00000000,
-  regk_marb_foo_rw_dma6_burst_default      = 0x00000000,
-  regk_marb_foo_rw_dma7_burst_default      = 0x00000000,
-  regk_marb_foo_rw_dma9_burst_default      = 0x00000000,
-  regk_marb_foo_rw_intm_slots_default      = 0x00000000,
-  regk_marb_foo_rw_intm_slots_size         = 0x00000040,
-  regk_marb_foo_rw_intr_mask_default       = 0x00000000,
-  regk_marb_foo_rw_iop_burst_default       = 0x00000000,
-  regk_marb_foo_rw_l2_slots_default        = 0x00000000,
-  regk_marb_foo_rw_l2_slots_size           = 0x00000040,
-  regk_marb_foo_rw_no_snoop_default        = 0x00000000,
-  regk_marb_foo_rw_no_snoop_rq_default     = 0x00000000,
-  regk_marb_foo_rw_regs_slots_default      = 0x00000000,
-  regk_marb_foo_rw_regs_slots_size         = 0x00000004,
-  regk_marb_foo_rw_sclr_burst_default      = 0x00000000,
-  regk_marb_foo_rw_stop_mask_default       = 0x00000000,
-  regk_marb_foo_sclr                       = 0x00000000,
-  regk_marb_foo_yes                        = 0x00000001
-};
-#endif /* __marb_foo_defs_h */
-#ifndef __marb_foo_bp_defs_h
-#define __marb_foo_bp_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           marb_foo.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_foo_bp */
-
-/* Register rw_first_addr, scope marb_foo_bp, type rw */
-typedef unsigned int reg_marb_foo_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_foo_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_foo_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_foo_bp, type rw */
-typedef unsigned int reg_marb_foo_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_foo_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_foo_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_foo_bp, type rw */
-typedef struct {
-  unsigned int rd         : 1;
-  unsigned int wr         : 1;
-  unsigned int rd_excl    : 1;
-  unsigned int pri_wr     : 1;
-  unsigned int us_rd      : 1;
-  unsigned int us_wr      : 1;
-  unsigned int us_rd_excl : 1;
-  unsigned int us_pri_wr  : 1;
-  unsigned int dummy1     : 24;
-} reg_marb_foo_bp_rw_op;
-#define REG_RD_ADDR_marb_foo_bp_rw_op 8
-#define REG_WR_ADDR_marb_foo_bp_rw_op 8
-
-/* Register rw_clients, scope marb_foo_bp, type rw */
-typedef struct {
-  unsigned int sclr    : 1;
-  unsigned int dma0    : 1;
-  unsigned int dma1    : 1;
-  unsigned int dma2    : 1;
-  unsigned int dma3    : 1;
-  unsigned int dma4    : 1;
-  unsigned int dma5    : 1;
-  unsigned int dma6    : 1;
-  unsigned int dma7    : 1;
-  unsigned int dma9    : 1;
-  unsigned int dma11   : 1;
-  unsigned int cpui    : 1;
-  unsigned int cpud    : 1;
-  unsigned int iop     : 1;
-  unsigned int ccdstat : 1;
-  unsigned int dummy1  : 17;
-} reg_marb_foo_bp_rw_clients;
-#define REG_RD_ADDR_marb_foo_bp_rw_clients 12
-#define REG_WR_ADDR_marb_foo_bp_rw_clients 12
-
-/* Register rw_options, scope marb_foo_bp, type rw */
-typedef struct {
-  unsigned int wrap : 1;
-  unsigned int dummy1 : 31;
-} reg_marb_foo_bp_rw_options;
-#define REG_RD_ADDR_marb_foo_bp_rw_options 16
-#define REG_WR_ADDR_marb_foo_bp_rw_options 16
-
-/* Register r_brk_addr, scope marb_foo_bp, type r */
-typedef unsigned int reg_marb_foo_bp_r_brk_addr;
-#define REG_RD_ADDR_marb_foo_bp_r_brk_addr 20
-
-/* Register r_brk_op, scope marb_foo_bp, type r */
-typedef struct {
-  unsigned int rd         : 1;
-  unsigned int wr         : 1;
-  unsigned int rd_excl    : 1;
-  unsigned int pri_wr     : 1;
-  unsigned int us_rd      : 1;
-  unsigned int us_wr      : 1;
-  unsigned int us_rd_excl : 1;
-  unsigned int us_pri_wr  : 1;
-  unsigned int dummy1     : 24;
-} reg_marb_foo_bp_r_brk_op;
-#define REG_RD_ADDR_marb_foo_bp_r_brk_op 24
-
-/* Register r_brk_clients, scope marb_foo_bp, type r */
-typedef struct {
-  unsigned int sclr    : 1;
-  unsigned int dma0    : 1;
-  unsigned int dma1    : 1;
-  unsigned int dma2    : 1;
-  unsigned int dma3    : 1;
-  unsigned int dma4    : 1;
-  unsigned int dma5    : 1;
-  unsigned int dma6    : 1;
-  unsigned int dma7    : 1;
-  unsigned int dma9    : 1;
-  unsigned int dma11   : 1;
-  unsigned int cpui    : 1;
-  unsigned int cpud    : 1;
-  unsigned int iop     : 1;
-  unsigned int ccdstat : 1;
-  unsigned int dummy1  : 17;
-} reg_marb_foo_bp_r_brk_clients;
-#define REG_RD_ADDR_marb_foo_bp_r_brk_clients 28
-
-/* Register r_brk_first_client, scope marb_foo_bp, type r */
-typedef struct {
-  unsigned int sclr    : 1;
-  unsigned int dma0    : 1;
-  unsigned int dma1    : 1;
-  unsigned int dma2    : 1;
-  unsigned int dma3    : 1;
-  unsigned int dma4    : 1;
-  unsigned int dma5    : 1;
-  unsigned int dma6    : 1;
-  unsigned int dma7    : 1;
-  unsigned int dma9    : 1;
-  unsigned int dma11   : 1;
-  unsigned int cpui    : 1;
-  unsigned int cpud    : 1;
-  unsigned int iop     : 1;
-  unsigned int ccdstat : 1;
-  unsigned int dummy1  : 17;
-} reg_marb_foo_bp_r_brk_first_client;
-#define REG_RD_ADDR_marb_foo_bp_r_brk_first_client 32
-
-/* Register r_brk_size, scope marb_foo_bp, type r */
-typedef unsigned int reg_marb_foo_bp_r_brk_size;
-#define REG_RD_ADDR_marb_foo_bp_r_brk_size 36
-
-/* Register rw_ack, scope marb_foo_bp, type rw */
-typedef unsigned int reg_marb_foo_bp_rw_ack;
-#define REG_RD_ADDR_marb_foo_bp_rw_ack 40
-#define REG_WR_ADDR_marb_foo_bp_rw_ack 40
-
-
-/* Constants */
-enum {
-  regk_marb_foo_bp_no                      = 0x00000000,
-  regk_marb_foo_bp_rw_op_default           = 0x00000000,
-  regk_marb_foo_bp_rw_options_default      = 0x00000000,
-  regk_marb_foo_bp_yes                     = 0x00000001
-};
-#endif /* __marb_foo_bp_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h
deleted file mode 100644
index 4b96cd2cba8a..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h
+++ /dev/null
@@ -1,312 +0,0 @@
-#ifndef __pinmux_defs_h
-#define __pinmux_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           pinmux.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile pinmux_defs.h pinmux.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope pinmux */
-
-/* Register rw_hwprot, scope pinmux, type rw */
-typedef struct {
-  unsigned int eth       : 1;
-  unsigned int eth_mdio  : 1;
-  unsigned int geth      : 1;
-  unsigned int tg        : 1;
-  unsigned int tg_clk    : 1;
-  unsigned int vout      : 1;
-  unsigned int vout_sync : 1;
-  unsigned int ser1      : 1;
-  unsigned int ser2      : 1;
-  unsigned int ser3      : 1;
-  unsigned int ser4      : 1;
-  unsigned int sser      : 1;
-  unsigned int pwm0      : 1;
-  unsigned int pwm1      : 1;
-  unsigned int pwm2      : 1;
-  unsigned int timer0    : 1;
-  unsigned int timer1    : 1;
-  unsigned int pio       : 1;
-  unsigned int i2c0      : 1;
-  unsigned int i2c1      : 1;
-  unsigned int i2c1_sda1 : 1;
-  unsigned int i2c1_sda2 : 1;
-  unsigned int i2c1_sda3 : 1;
-  unsigned int i2c1_sen  : 1;
-  unsigned int dummy1    : 8;
-} reg_pinmux_rw_hwprot;
-#define REG_RD_ADDR_pinmux_rw_hwprot 0
-#define REG_WR_ADDR_pinmux_rw_hwprot 0
-
-/* Register rw_gio_pa, scope pinmux, type rw */
-typedef struct {
-  unsigned int pa0  : 1;
-  unsigned int pa1  : 1;
-  unsigned int pa2  : 1;
-  unsigned int pa3  : 1;
-  unsigned int pa4  : 1;
-  unsigned int pa5  : 1;
-  unsigned int pa6  : 1;
-  unsigned int pa7  : 1;
-  unsigned int pa8  : 1;
-  unsigned int pa9  : 1;
-  unsigned int pa10 : 1;
-  unsigned int pa11 : 1;
-  unsigned int pa12 : 1;
-  unsigned int pa13 : 1;
-  unsigned int pa14 : 1;
-  unsigned int pa15 : 1;
-  unsigned int pa16 : 1;
-  unsigned int pa17 : 1;
-  unsigned int pa18 : 1;
-  unsigned int pa19 : 1;
-  unsigned int pa20 : 1;
-  unsigned int pa21 : 1;
-  unsigned int pa22 : 1;
-  unsigned int pa23 : 1;
-  unsigned int pa24 : 1;
-  unsigned int pa25 : 1;
-  unsigned int pa26 : 1;
-  unsigned int pa27 : 1;
-  unsigned int pa28 : 1;
-  unsigned int pa29 : 1;
-  unsigned int pa30 : 1;
-  unsigned int pa31 : 1;
-} reg_pinmux_rw_gio_pa;
-#define REG_RD_ADDR_pinmux_rw_gio_pa 4
-#define REG_WR_ADDR_pinmux_rw_gio_pa 4
-
-/* Register rw_gio_pb, scope pinmux, type rw */
-typedef struct {
-  unsigned int pb0  : 1;
-  unsigned int pb1  : 1;
-  unsigned int pb2  : 1;
-  unsigned int pb3  : 1;
-  unsigned int pb4  : 1;
-  unsigned int pb5  : 1;
-  unsigned int pb6  : 1;
-  unsigned int pb7  : 1;
-  unsigned int pb8  : 1;
-  unsigned int pb9  : 1;
-  unsigned int pb10 : 1;
-  unsigned int pb11 : 1;
-  unsigned int pb12 : 1;
-  unsigned int pb13 : 1;
-  unsigned int pb14 : 1;
-  unsigned int pb15 : 1;
-  unsigned int pb16 : 1;
-  unsigned int pb17 : 1;
-  unsigned int pb18 : 1;
-  unsigned int pb19 : 1;
-  unsigned int pb20 : 1;
-  unsigned int pb21 : 1;
-  unsigned int pb22 : 1;
-  unsigned int pb23 : 1;
-  unsigned int pb24 : 1;
-  unsigned int pb25 : 1;
-  unsigned int pb26 : 1;
-  unsigned int pb27 : 1;
-  unsigned int pb28 : 1;
-  unsigned int pb29 : 1;
-  unsigned int pb30 : 1;
-  unsigned int pb31 : 1;
-} reg_pinmux_rw_gio_pb;
-#define REG_RD_ADDR_pinmux_rw_gio_pb 8
-#define REG_WR_ADDR_pinmux_rw_gio_pb 8
-
-/* Register rw_gio_pc, scope pinmux, type rw */
-typedef struct {
-  unsigned int pc0  : 1;
-  unsigned int pc1  : 1;
-  unsigned int pc2  : 1;
-  unsigned int pc3  : 1;
-  unsigned int pc4  : 1;
-  unsigned int pc5  : 1;
-  unsigned int pc6  : 1;
-  unsigned int pc7  : 1;
-  unsigned int pc8  : 1;
-  unsigned int pc9  : 1;
-  unsigned int pc10 : 1;
-  unsigned int pc11 : 1;
-  unsigned int pc12 : 1;
-  unsigned int pc13 : 1;
-  unsigned int pc14 : 1;
-  unsigned int pc15 : 1;
-  unsigned int dummy1 : 16;
-} reg_pinmux_rw_gio_pc;
-#define REG_RD_ADDR_pinmux_rw_gio_pc 12
-#define REG_WR_ADDR_pinmux_rw_gio_pc 12
-
-/* Register rw_iop_pa, scope pinmux, type rw */
-typedef struct {
-  unsigned int pa0  : 1;
-  unsigned int pa1  : 1;
-  unsigned int pa2  : 1;
-  unsigned int pa3  : 1;
-  unsigned int pa4  : 1;
-  unsigned int pa5  : 1;
-  unsigned int pa6  : 1;
-  unsigned int pa7  : 1;
-  unsigned int pa8  : 1;
-  unsigned int pa9  : 1;
-  unsigned int pa10 : 1;
-  unsigned int pa11 : 1;
-  unsigned int pa12 : 1;
-  unsigned int pa13 : 1;
-  unsigned int pa14 : 1;
-  unsigned int pa15 : 1;
-  unsigned int pa16 : 1;
-  unsigned int pa17 : 1;
-  unsigned int pa18 : 1;
-  unsigned int pa19 : 1;
-  unsigned int pa20 : 1;
-  unsigned int pa21 : 1;
-  unsigned int pa22 : 1;
-  unsigned int pa23 : 1;
-  unsigned int pa24 : 1;
-  unsigned int pa25 : 1;
-  unsigned int pa26 : 1;
-  unsigned int pa27 : 1;
-  unsigned int pa28 : 1;
-  unsigned int pa29 : 1;
-  unsigned int pa30 : 1;
-  unsigned int pa31 : 1;
-} reg_pinmux_rw_iop_pa;
-#define REG_RD_ADDR_pinmux_rw_iop_pa 16
-#define REG_WR_ADDR_pinmux_rw_iop_pa 16
-
-/* Register rw_iop_pb, scope pinmux, type rw */
-typedef struct {
-  unsigned int pb0 : 1;
-  unsigned int pb1 : 1;
-  unsigned int pb2 : 1;
-  unsigned int pb3 : 1;
-  unsigned int pb4 : 1;
-  unsigned int pb5 : 1;
-  unsigned int pb6 : 1;
-  unsigned int pb7 : 1;
-  unsigned int dummy1 : 24;
-} reg_pinmux_rw_iop_pb;
-#define REG_RD_ADDR_pinmux_rw_iop_pb 20
-#define REG_WR_ADDR_pinmux_rw_iop_pb 20
-
-/* Register rw_iop_pio, scope pinmux, type rw */
-typedef struct {
-  unsigned int d0    : 1;
-  unsigned int d1    : 1;
-  unsigned int d2    : 1;
-  unsigned int d3    : 1;
-  unsigned int d4    : 1;
-  unsigned int d5    : 1;
-  unsigned int d6    : 1;
-  unsigned int d7    : 1;
-  unsigned int rd_n  : 1;
-  unsigned int wr_n  : 1;
-  unsigned int a0    : 1;
-  unsigned int a1    : 1;
-  unsigned int ce0_n : 1;
-  unsigned int ce1_n : 1;
-  unsigned int ce2_n : 1;
-  unsigned int rdy   : 1;
-  unsigned int dummy1 : 16;
-} reg_pinmux_rw_iop_pio;
-#define REG_RD_ADDR_pinmux_rw_iop_pio 24
-#define REG_WR_ADDR_pinmux_rw_iop_pio 24
-
-/* Register rw_iop_usb, scope pinmux, type rw */
-typedef struct {
-  unsigned int usb0 : 1;
-  unsigned int dummy1 : 31;
-} reg_pinmux_rw_iop_usb;
-#define REG_RD_ADDR_pinmux_rw_iop_usb 28
-#define REG_WR_ADDR_pinmux_rw_iop_usb 28
-
-
-/* Constants */
-enum {
-  regk_pinmux_no                           = 0x00000000,
-  regk_pinmux_rw_gio_pa_default            = 0x00000000,
-  regk_pinmux_rw_gio_pb_default            = 0x00000000,
-  regk_pinmux_rw_gio_pc_default            = 0x00000000,
-  regk_pinmux_rw_hwprot_default            = 0x00000000,
-  regk_pinmux_rw_iop_pa_default            = 0x00000000,
-  regk_pinmux_rw_iop_pb_default            = 0x00000000,
-  regk_pinmux_rw_iop_pio_default           = 0x00000000,
-  regk_pinmux_rw_iop_usb_default           = 0x00000001,
-  regk_pinmux_yes                          = 0x00000001
-};
-#endif /* __pinmux_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h
deleted file mode 100644
index 2d8e4b4cc602..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h
+++ /dev/null
@@ -1,371 +0,0 @@
-#ifndef __pio_defs_h
-#define __pio_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           pio.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile pio_defs.h pio.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope pio */
-
-/* Register rw_data, scope pio, type rw */
-typedef unsigned int reg_pio_rw_data;
-#define REG_RD_ADDR_pio_rw_data 64
-#define REG_WR_ADDR_pio_rw_data 64
-
-/* Register rw_io_access0, scope pio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_pio_rw_io_access0;
-#define REG_RD_ADDR_pio_rw_io_access0 0
-#define REG_WR_ADDR_pio_rw_io_access0 0
-
-/* Register rw_io_access1, scope pio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_pio_rw_io_access1;
-#define REG_RD_ADDR_pio_rw_io_access1 4
-#define REG_WR_ADDR_pio_rw_io_access1 4
-
-/* Register rw_io_access2, scope pio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_pio_rw_io_access2;
-#define REG_RD_ADDR_pio_rw_io_access2 8
-#define REG_WR_ADDR_pio_rw_io_access2 8
-
-/* Register rw_io_access3, scope pio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_pio_rw_io_access3;
-#define REG_RD_ADDR_pio_rw_io_access3 12
-#define REG_WR_ADDR_pio_rw_io_access3 12
-
-/* Register rw_io_access4, scope pio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_pio_rw_io_access4;
-#define REG_RD_ADDR_pio_rw_io_access4 16
-#define REG_WR_ADDR_pio_rw_io_access4 16
-
-/* Register rw_io_access5, scope pio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_pio_rw_io_access5;
-#define REG_RD_ADDR_pio_rw_io_access5 20
-#define REG_WR_ADDR_pio_rw_io_access5 20
-
-/* Register rw_io_access6, scope pio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_pio_rw_io_access6;
-#define REG_RD_ADDR_pio_rw_io_access6 24
-#define REG_WR_ADDR_pio_rw_io_access6 24
-
-/* Register rw_io_access7, scope pio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_pio_rw_io_access7;
-#define REG_RD_ADDR_pio_rw_io_access7 28
-#define REG_WR_ADDR_pio_rw_io_access7 28
-
-/* Register rw_io_access8, scope pio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_pio_rw_io_access8;
-#define REG_RD_ADDR_pio_rw_io_access8 32
-#define REG_WR_ADDR_pio_rw_io_access8 32
-
-/* Register rw_io_access9, scope pio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_pio_rw_io_access9;
-#define REG_RD_ADDR_pio_rw_io_access9 36
-#define REG_WR_ADDR_pio_rw_io_access9 36
-
-/* Register rw_io_access10, scope pio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_pio_rw_io_access10;
-#define REG_RD_ADDR_pio_rw_io_access10 40
-#define REG_WR_ADDR_pio_rw_io_access10 40
-
-/* Register rw_io_access11, scope pio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_pio_rw_io_access11;
-#define REG_RD_ADDR_pio_rw_io_access11 44
-#define REG_WR_ADDR_pio_rw_io_access11 44
-
-/* Register rw_io_access12, scope pio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_pio_rw_io_access12;
-#define REG_RD_ADDR_pio_rw_io_access12 48
-#define REG_WR_ADDR_pio_rw_io_access12 48
-
-/* Register rw_io_access13, scope pio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_pio_rw_io_access13;
-#define REG_RD_ADDR_pio_rw_io_access13 52
-#define REG_WR_ADDR_pio_rw_io_access13 52
-
-/* Register rw_io_access14, scope pio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_pio_rw_io_access14;
-#define REG_RD_ADDR_pio_rw_io_access14 56
-#define REG_WR_ADDR_pio_rw_io_access14 56
-
-/* Register rw_io_access15, scope pio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_pio_rw_io_access15;
-#define REG_RD_ADDR_pio_rw_io_access15 60
-#define REG_WR_ADDR_pio_rw_io_access15 60
-
-/* Register rw_ce0_cfg, scope pio, type rw */
-typedef struct {
-  unsigned int lw   : 6;
-  unsigned int ew   : 3;
-  unsigned int zw   : 3;
-  unsigned int aw   : 2;
-  unsigned int mode : 2;
-  unsigned int dummy1 : 16;
-} reg_pio_rw_ce0_cfg;
-#define REG_RD_ADDR_pio_rw_ce0_cfg 68
-#define REG_WR_ADDR_pio_rw_ce0_cfg 68
-
-/* Register rw_ce1_cfg, scope pio, type rw */
-typedef struct {
-  unsigned int lw   : 6;
-  unsigned int ew   : 3;
-  unsigned int zw   : 3;
-  unsigned int aw   : 2;
-  unsigned int mode : 2;
-  unsigned int dummy1 : 16;
-} reg_pio_rw_ce1_cfg;
-#define REG_RD_ADDR_pio_rw_ce1_cfg 72
-#define REG_WR_ADDR_pio_rw_ce1_cfg 72
-
-/* Register rw_ce2_cfg, scope pio, type rw */
-typedef struct {
-  unsigned int lw   : 6;
-  unsigned int ew   : 3;
-  unsigned int zw   : 3;
-  unsigned int aw   : 2;
-  unsigned int mode : 2;
-  unsigned int dummy1 : 16;
-} reg_pio_rw_ce2_cfg;
-#define REG_RD_ADDR_pio_rw_ce2_cfg 76
-#define REG_WR_ADDR_pio_rw_ce2_cfg 76
-
-/* Register rw_dout, scope pio, type rw */
-typedef struct {
-  unsigned int data  : 8;
-  unsigned int rd_n  : 1;
-  unsigned int wr_n  : 1;
-  unsigned int a0    : 1;
-  unsigned int a1    : 1;
-  unsigned int ce0_n : 1;
-  unsigned int ce1_n : 1;
-  unsigned int ce2_n : 1;
-  unsigned int rdy   : 1;
-  unsigned int dummy1 : 16;
-} reg_pio_rw_dout;
-#define REG_RD_ADDR_pio_rw_dout 80
-#define REG_WR_ADDR_pio_rw_dout 80
-
-/* Register rw_oe, scope pio, type rw */
-typedef struct {
-  unsigned int data  : 8;
-  unsigned int rd_n  : 1;
-  unsigned int wr_n  : 1;
-  unsigned int a0    : 1;
-  unsigned int a1    : 1;
-  unsigned int ce0_n : 1;
-  unsigned int ce1_n : 1;
-  unsigned int ce2_n : 1;
-  unsigned int rdy   : 1;
-  unsigned int dummy1 : 16;
-} reg_pio_rw_oe;
-#define REG_RD_ADDR_pio_rw_oe 84
-#define REG_WR_ADDR_pio_rw_oe 84
-
-/* Register rw_man_ctrl, scope pio, type rw */
-typedef struct {
-  unsigned int data  : 8;
-  unsigned int rd_n  : 1;
-  unsigned int wr_n  : 1;
-  unsigned int a0    : 1;
-  unsigned int a1    : 1;
-  unsigned int ce0_n : 1;
-  unsigned int ce1_n : 1;
-  unsigned int ce2_n : 1;
-  unsigned int rdy   : 1;
-  unsigned int dummy1 : 16;
-} reg_pio_rw_man_ctrl;
-#define REG_RD_ADDR_pio_rw_man_ctrl 88
-#define REG_WR_ADDR_pio_rw_man_ctrl 88
-
-/* Register r_din, scope pio, type r */
-typedef struct {
-  unsigned int data  : 8;
-  unsigned int rd_n  : 1;
-  unsigned int wr_n  : 1;
-  unsigned int a0    : 1;
-  unsigned int a1    : 1;
-  unsigned int ce0_n : 1;
-  unsigned int ce1_n : 1;
-  unsigned int ce2_n : 1;
-  unsigned int rdy   : 1;
-  unsigned int dummy1 : 16;
-} reg_pio_r_din;
-#define REG_RD_ADDR_pio_r_din 92
-
-/* Register r_stat, scope pio, type r */
-typedef struct {
-  unsigned int busy : 1;
-  unsigned int dummy1 : 31;
-} reg_pio_r_stat;
-#define REG_RD_ADDR_pio_r_stat 96
-
-/* Register rw_intr_mask, scope pio, type rw */
-typedef struct {
-  unsigned int rdy : 1;
-  unsigned int dummy1 : 31;
-} reg_pio_rw_intr_mask;
-#define REG_RD_ADDR_pio_rw_intr_mask 100
-#define REG_WR_ADDR_pio_rw_intr_mask 100
-
-/* Register rw_ack_intr, scope pio, type rw */
-typedef struct {
-  unsigned int rdy : 1;
-  unsigned int dummy1 : 31;
-} reg_pio_rw_ack_intr;
-#define REG_RD_ADDR_pio_rw_ack_intr 104
-#define REG_WR_ADDR_pio_rw_ack_intr 104
-
-/* Register r_intr, scope pio, type r */
-typedef struct {
-  unsigned int rdy : 1;
-  unsigned int dummy1 : 31;
-} reg_pio_r_intr;
-#define REG_RD_ADDR_pio_r_intr 108
-
-/* Register r_masked_intr, scope pio, type r */
-typedef struct {
-  unsigned int rdy : 1;
-  unsigned int dummy1 : 31;
-} reg_pio_r_masked_intr;
-#define REG_RD_ADDR_pio_r_masked_intr 112
-
-
-/* Constants */
-enum {
-  regk_pio_a2                              = 0x00000003,
-  regk_pio_no                              = 0x00000000,
-  regk_pio_normal                          = 0x00000000,
-  regk_pio_rd                              = 0x00000001,
-  regk_pio_rw_ce0_cfg_default              = 0x00000000,
-  regk_pio_rw_ce1_cfg_default              = 0x00000000,
-  regk_pio_rw_ce2_cfg_default              = 0x00000000,
-  regk_pio_rw_intr_mask_default            = 0x00000000,
-  regk_pio_rw_man_ctrl_default             = 0x00000000,
-  regk_pio_rw_oe_default                   = 0x00000000,
-  regk_pio_wr                              = 0x00000002,
-  regk_pio_wr_ce2                          = 0x00000003,
-  regk_pio_yes                             = 0x00000001,
-  regk_pio_yes_all                         = 0x000000ff
-};
-#endif /* __pio_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h b/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h
deleted file mode 100644
index 36e59d6e96b6..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h
+++ /dev/null
@@ -1,103 +0,0 @@
-#ifndef __reg_map_h
-#define __reg_map_h
-
-/*
- * This file is autogenerated from
- *   file:            reg.rmap
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map.h reg.rmap
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-typedef enum {
-  regi_ccd                                 = 0xb0000000,
-  regi_ccd_top                             = 0xb0000000,
-  regi_ccd_dp                              = 0xb0000400,
-  regi_ccd_stat                            = 0xb0000800,
-  regi_ccd_tg                              = 0xb0001000,
-  regi_cfg                                 = 0xb0002000,
-  regi_clkgen                              = 0xb0004000,
-  regi_ddr2_ctrl                           = 0xb0006000,
-  regi_dma0                                = 0xb0008000,
-  regi_dma1                                = 0xb000a000,
-  regi_dma11                               = 0xb000c000,
-  regi_dma2                                = 0xb000e000,
-  regi_dma3                                = 0xb0010000,
-  regi_dma4                                = 0xb0012000,
-  regi_dma5                                = 0xb0014000,
-  regi_dma6                                = 0xb0016000,
-  regi_dma7                                = 0xb0018000,
-  regi_dma9                                = 0xb001a000,
-  regi_eth                                 = 0xb001c000,
-  regi_gio                                 = 0xb0020000,
-  regi_h264                                = 0xb0022000,
-  regi_hist                                = 0xb0026000,
-  regi_iop                                 = 0xb0028000,
-  regi_iop_version                         = 0xb0028000,
-  regi_iop_fifo_in_extra                   = 0xb0028040,
-  regi_iop_fifo_out_extra                  = 0xb0028080,
-  regi_iop_trigger_grp0                    = 0xb00280c0,
-  regi_iop_trigger_grp1                    = 0xb0028100,
-  regi_iop_trigger_grp2                    = 0xb0028140,
-  regi_iop_trigger_grp3                    = 0xb0028180,
-  regi_iop_trigger_grp4                    = 0xb00281c0,
-  regi_iop_trigger_grp5                    = 0xb0028200,
-  regi_iop_trigger_grp6                    = 0xb0028240,
-  regi_iop_trigger_grp7                    = 0xb0028280,
-  regi_iop_crc_par                         = 0xb0028300,
-  regi_iop_dmc_in                          = 0xb0028380,
-  regi_iop_dmc_out                         = 0xb0028400,
-  regi_iop_fifo_in                         = 0xb0028480,
-  regi_iop_fifo_out                        = 0xb0028500,
-  regi_iop_scrc_in                         = 0xb0028580,
-  regi_iop_scrc_out                        = 0xb0028600,
-  regi_iop_timer_grp0                      = 0xb0028680,
-  regi_iop_timer_grp1                      = 0xb0028700,
-  regi_iop_sap_in                          = 0xb0028800,
-  regi_iop_sap_out                         = 0xb0028900,
-  regi_iop_spu                             = 0xb0028a00,
-  regi_iop_sw_cfg                          = 0xb0028b00,
-  regi_iop_sw_cpu                          = 0xb0028c00,
-  regi_iop_sw_mpu                          = 0xb0028d00,
-  regi_iop_sw_spu                          = 0xb0028e00,
-  regi_iop_mpu                             = 0xb0029000,
-  regi_irq                                 = 0xb002a000,
-  regi_irq2                                = 0xb006a000,
-  regi_jpeg                                = 0xb002c000,
-  regi_l2cache                             = 0xb0030000,
-  regi_marb_bar                            = 0xb0032000,
-  regi_marb_bar_bp0                        = 0xb0032140,
-  regi_marb_bar_bp1                        = 0xb0032180,
-  regi_marb_bar_bp2                        = 0xb00321c0,
-  regi_marb_bar_bp3                        = 0xb0032200,
-  regi_marb_foo                            = 0xb0034000,
-  regi_marb_foo_bp0                        = 0xb0034280,
-  regi_marb_foo_bp1                        = 0xb00342c0,
-  regi_marb_foo_bp2                        = 0xb0034300,
-  regi_marb_foo_bp3                        = 0xb0034340,
-  regi_pinmux                              = 0xb0038000,
-  regi_pio                                 = 0xb0036000,
-  regi_sclr                                = 0xb003a000,
-  regi_sclr_fifo                           = 0xb003c000,
-  regi_ser0                                = 0xb003e000,
-  regi_ser1                                = 0xb0040000,
-  regi_ser2                                = 0xb0042000,
-  regi_ser3                                = 0xb0044000,
-  regi_ser4                                = 0xb0046000,
-  regi_sser                                = 0xb0048000,
-  regi_strcop                              = 0xb004a000,
-  regi_strdma0                             = 0xb004e000,
-  regi_strdma1                             = 0xb0050000,
-  regi_strdma2                             = 0xb0052000,
-  regi_strdma3                             = 0xb0054000,
-  regi_strdma5                             = 0xb0056000,
-  regi_strmux                              = 0xb004c000,
-  regi_timer0                              = 0xb0058000,
-  regi_timer1                              = 0xb005a000,
-  regi_timer2                              = 0xb006e000,
-  regi_trace                               = 0xb005c000,
-  regi_vin                                 = 0xb005e000,
-  regi_vout                                = 0xb0060000
-} reg_scope_instances;
-#endif /* __reg_map_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h
deleted file mode 100644
index 14f718a4ecc3..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h
+++ /dev/null
@@ -1,120 +0,0 @@
-#ifndef __strmux_defs_h
-#define __strmux_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           strmux.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile strmux_defs.h strmux.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope strmux */
-
-/* Register rw_cfg, scope strmux, type rw */
-typedef struct {
-  unsigned int dma0  : 2;
-  unsigned int dma1  : 2;
-  unsigned int dma2  : 2;
-  unsigned int dma3  : 2;
-  unsigned int dma4  : 2;
-  unsigned int dma5  : 2;
-  unsigned int dma6  : 2;
-  unsigned int dma7  : 2;
-  unsigned int dummy1 : 2;
-  unsigned int dma9  : 2;
-  unsigned int dummy2 : 2;
-  unsigned int dma11 : 2;
-  unsigned int dummy3 : 8;
-} reg_strmux_rw_cfg;
-#define REG_RD_ADDR_strmux_rw_cfg 0
-#define REG_WR_ADDR_strmux_rw_cfg 0
-
-
-/* Constants */
-enum {
-  regk_strmux_eth                          = 0x00000001,
-  regk_strmux_h264                         = 0x00000001,
-  regk_strmux_iop                          = 0x00000001,
-  regk_strmux_jpeg                         = 0x00000001,
-  regk_strmux_off                          = 0x00000000,
-  regk_strmux_rw_cfg_default               = 0x00000000,
-  regk_strmux_ser0                         = 0x00000002,
-  regk_strmux_ser1                         = 0x00000002,
-  regk_strmux_ser2                         = 0x00000002,
-  regk_strmux_ser3                         = 0x00000002,
-  regk_strmux_ser4                         = 0x00000002,
-  regk_strmux_sser                         = 0x00000001,
-  regk_strmux_strcop                       = 0x00000001
-};
-#endif /* __strmux_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h
deleted file mode 100644
index 2c33e097d60a..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h
+++ /dev/null
@@ -1,265 +0,0 @@
-#ifndef __timer_defs_h
-#define __timer_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           timer.r
- * 
- *   by ../../../tools/rdesc/bin/rdes2c -outfile timer_defs.h timer.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope timer */
-
-/* Register rw_tmr0_div, scope timer, type rw */
-typedef unsigned int reg_timer_rw_tmr0_div;
-#define REG_RD_ADDR_timer_rw_tmr0_div 0
-#define REG_WR_ADDR_timer_rw_tmr0_div 0
-
-/* Register r_tmr0_data, scope timer, type r */
-typedef unsigned int reg_timer_r_tmr0_data;
-#define REG_RD_ADDR_timer_r_tmr0_data 4
-
-/* Register rw_tmr0_ctrl, scope timer, type rw */
-typedef struct {
-  unsigned int op   : 2;
-  unsigned int freq : 3;
-  unsigned int dummy1 : 27;
-} reg_timer_rw_tmr0_ctrl;
-#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
-#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
-
-/* Register rw_tmr1_div, scope timer, type rw */
-typedef unsigned int reg_timer_rw_tmr1_div;
-#define REG_RD_ADDR_timer_rw_tmr1_div 16
-#define REG_WR_ADDR_timer_rw_tmr1_div 16
-
-/* Register r_tmr1_data, scope timer, type r */
-typedef unsigned int reg_timer_r_tmr1_data;
-#define REG_RD_ADDR_timer_r_tmr1_data 20
-
-/* Register rw_tmr1_ctrl, scope timer, type rw */
-typedef struct {
-  unsigned int op   : 2;
-  unsigned int freq : 3;
-  unsigned int dummy1 : 27;
-} reg_timer_rw_tmr1_ctrl;
-#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
-#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
-
-/* Register rs_cnt_data, scope timer, type rs */
-typedef struct {
-  unsigned int tmr : 24;
-  unsigned int cnt : 8;
-} reg_timer_rs_cnt_data;
-#define REG_RD_ADDR_timer_rs_cnt_data 32
-
-/* Register r_cnt_data, scope timer, type r */
-typedef struct {
-  unsigned int tmr : 24;
-  unsigned int cnt : 8;
-} reg_timer_r_cnt_data;
-#define REG_RD_ADDR_timer_r_cnt_data 36
-
-/* Register rw_cnt_cfg, scope timer, type rw */
-typedef struct {
-  unsigned int clk : 2;
-  unsigned int dummy1 : 30;
-} reg_timer_rw_cnt_cfg;
-#define REG_RD_ADDR_timer_rw_cnt_cfg 40
-#define REG_WR_ADDR_timer_rw_cnt_cfg 40
-
-/* Register rw_trig, scope timer, type rw */
-typedef unsigned int reg_timer_rw_trig;
-#define REG_RD_ADDR_timer_rw_trig 48
-#define REG_WR_ADDR_timer_rw_trig 48
-
-/* Register rw_trig_cfg, scope timer, type rw */
-typedef struct {
-  unsigned int tmr : 2;
-  unsigned int dummy1 : 30;
-} reg_timer_rw_trig_cfg;
-#define REG_RD_ADDR_timer_rw_trig_cfg 52
-#define REG_WR_ADDR_timer_rw_trig_cfg 52
-
-/* Register r_time, scope timer, type r */
-typedef unsigned int reg_timer_r_time;
-#define REG_RD_ADDR_timer_r_time 56
-
-/* Register rw_out, scope timer, type rw */
-typedef struct {
-  unsigned int tmr : 2;
-  unsigned int dummy1 : 30;
-} reg_timer_rw_out;
-#define REG_RD_ADDR_timer_rw_out 60
-#define REG_WR_ADDR_timer_rw_out 60
-
-/* Register rw_wd_ctrl, scope timer, type rw */
-typedef struct {
-  unsigned int cnt : 8;
-  unsigned int cmd : 1;
-  unsigned int key : 7;
-  unsigned int dummy1 : 16;
-} reg_timer_rw_wd_ctrl;
-#define REG_RD_ADDR_timer_rw_wd_ctrl 64
-#define REG_WR_ADDR_timer_rw_wd_ctrl 64
-
-/* Register r_wd_stat, scope timer, type r */
-typedef struct {
-  unsigned int cnt : 8;
-  unsigned int cmd : 1;
-  unsigned int dummy1 : 23;
-} reg_timer_r_wd_stat;
-#define REG_RD_ADDR_timer_r_wd_stat 68
-
-/* Register rw_intr_mask, scope timer, type rw */
-typedef struct {
-  unsigned int tmr0 : 1;
-  unsigned int tmr1 : 1;
-  unsigned int cnt  : 1;
-  unsigned int trig : 1;
-  unsigned int dummy1 : 28;
-} reg_timer_rw_intr_mask;
-#define REG_RD_ADDR_timer_rw_intr_mask 72
-#define REG_WR_ADDR_timer_rw_intr_mask 72
-
-/* Register rw_ack_intr, scope timer, type rw */
-typedef struct {
-  unsigned int tmr0 : 1;
-  unsigned int tmr1 : 1;
-  unsigned int cnt  : 1;
-  unsigned int trig : 1;
-  unsigned int dummy1 : 28;
-} reg_timer_rw_ack_intr;
-#define REG_RD_ADDR_timer_rw_ack_intr 76
-#define REG_WR_ADDR_timer_rw_ack_intr 76
-
-/* Register r_intr, scope timer, type r */
-typedef struct {
-  unsigned int tmr0 : 1;
-  unsigned int tmr1 : 1;
-  unsigned int cnt  : 1;
-  unsigned int trig : 1;
-  unsigned int dummy1 : 28;
-} reg_timer_r_intr;
-#define REG_RD_ADDR_timer_r_intr 80
-
-/* Register r_masked_intr, scope timer, type r */
-typedef struct {
-  unsigned int tmr0 : 1;
-  unsigned int tmr1 : 1;
-  unsigned int cnt  : 1;
-  unsigned int trig : 1;
-  unsigned int dummy1 : 28;
-} reg_timer_r_masked_intr;
-#define REG_RD_ADDR_timer_r_masked_intr 84
-
-/* Register rw_test, scope timer, type rw */
-typedef struct {
-  unsigned int dis : 1;
-  unsigned int en  : 1;
-  unsigned int dummy1 : 30;
-} reg_timer_rw_test;
-#define REG_RD_ADDR_timer_rw_test 88
-#define REG_WR_ADDR_timer_rw_test 88
-
-
-/* Constants */
-enum {
-  regk_timer_ext                           = 0x00000001,
-  regk_timer_f100                          = 0x00000007,
-  regk_timer_f29_493                       = 0x00000004,
-  regk_timer_f32                           = 0x00000005,
-  regk_timer_f32_768                       = 0x00000006,
-  regk_timer_f90                           = 0x00000003,
-  regk_timer_hold                          = 0x00000001,
-  regk_timer_ld                            = 0x00000000,
-  regk_timer_no                            = 0x00000000,
-  regk_timer_off                           = 0x00000000,
-  regk_timer_run                           = 0x00000002,
-  regk_timer_rw_cnt_cfg_default            = 0x00000000,
-  regk_timer_rw_intr_mask_default          = 0x00000000,
-  regk_timer_rw_out_default                = 0x00000000,
-  regk_timer_rw_test_default               = 0x00000000,
-  regk_timer_rw_tmr0_ctrl_default          = 0x00000000,
-  regk_timer_rw_tmr1_ctrl_default          = 0x00000000,
-  regk_timer_rw_trig_cfg_default           = 0x00000000,
-  regk_timer_start                         = 0x00000001,
-  regk_timer_stop                          = 0x00000000,
-  regk_timer_time                          = 0x00000001,
-  regk_timer_tmr0                          = 0x00000002,
-  regk_timer_tmr1                          = 0x00000003,
-  regk_timer_vclk                          = 0x00000002,
-  regk_timer_yes                           = 0x00000001
-};
-#endif /* __timer_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-a3/memmap.h b/include/asm-cris/arch-v32/mach-a3/memmap.h
deleted file mode 100644
index 7e15c9eb4e49..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/memmap.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef _ASM_ARCH_MEMMAP_H
-#define _ASM_ARCH_MEMMAP_H
-
-#define MEM_INTMEM_START (0x38000000)
-#define MEM_INTMEM_SIZE (0x00018000)
-#define MEM_DRAM_START (0x40000000)
-
-#define MEM_NON_CACHEABLE (0x80000000)
-
-#endif
diff --git a/include/asm-cris/arch-v32/mach-a3/pinmux.h b/include/asm-cris/arch-v32/mach-a3/pinmux.h
deleted file mode 100644
index db42a7254584..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/pinmux.h
+++ /dev/null
@@ -1,45 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_PINMUX_H
-#define _ASM_CRIS_ARCH_PINMUX_H
-
-#define PORT_A 0
-#define PORT_B 1
-#define PORT_C 2
-
-enum pin_mode {
-	pinmux_none = 0,
-	pinmux_fixed,
-	pinmux_gpio,
-	pinmux_iop
-};
-
-enum fixed_function {
-	pinmux_eth,
-	pinmux_geth,
-	pinmux_tg_ccd,
-	pinmux_tg_cmos,
-	pinmux_vout,
-	pinmux_ser1,
-	pinmux_ser2,
-	pinmux_ser3,
-	pinmux_ser4,
-	pinmux_sser,
-	pinmux_pio,
-	pinmux_pwm0,
-	pinmux_pwm1,
-	pinmux_pwm2,
-	pinmux_i2c0,
-	pinmux_i2c1,
-	pinmux_i2c1_3wire,
-	pinmux_i2c1_sda1,
-	pinmux_i2c1_sda2,
-	pinmux_i2c1_sda3,
-};
-
-int crisv32_pinmux_init(void);
-int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
-int crisv32_pinmux_alloc_fixed(enum fixed_function function);
-int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
-int crisv32_pinmux_dealloc_fixed(enum fixed_function function);
-void crisv32_pinmux_dump(void);
-
-#endif
diff --git a/include/asm-cris/arch-v32/mach-a3/startup.inc b/include/asm-cris/arch-v32/mach-a3/startup.inc
deleted file mode 100644
index 2f23e5e16f4a..000000000000
--- a/include/asm-cris/arch-v32/mach-a3/startup.inc
+++ /dev/null
@@ -1,60 +0,0 @@
-#include <hwregs/asm/reg_map_asm.h>
-#include <hwregs/asm/gio_defs_asm.h>
-#include <hwregs/asm/pio_defs_asm.h>
-#include <hwregs/asm/clkgen_defs_asm.h>
-#include <hwregs/asm/pinmux_defs_asm.h>
-
-	.macro GIO_INIT
-	move.d	CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
-	move.d	REG_ADDR(gio, regi_gio, rw_pa_dout), $r1
-	move.d	$r0, [$r1]
-
-	move.d	CONFIG_ETRAX_DEF_GIO_PA_OE, $r0
-	move.d	REG_ADDR(gio, regi_gio, rw_pa_oe), $r1
-	move.d	$r0, [$r1]
-
-	move.d	CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0
-	move.d	REG_ADDR(gio, regi_gio, rw_pb_dout), $r1
-	move.d	$r0, [$r1]
-
-	move.d	CONFIG_ETRAX_DEF_GIO_PB_OE, $r0
-	move.d	REG_ADDR(gio, regi_gio, rw_pb_oe), $r1
-	move.d	$r0, [$r1]
-
-	move.d	CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0
-	move.d	REG_ADDR(gio, regi_gio, rw_pc_dout), $r1
-	move.d	$r0, [$r1]
-
-	move.d	CONFIG_ETRAX_DEF_GIO_PC_OE, $r0
-	move.d	REG_ADDR(gio, regi_gio, rw_pc_oe), $r1
-	move.d	$r0, [$r1]
-
-	move.d	0xFFFFFFFF, $r0
-	move.d	REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1
-	move.d	$r0, [$r1]
-	move.d	REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1
-	move.d	$r0, [$r1]
-	move.d	REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1
-	move.d	$r0, [$r1]
-	.endm
-
-	.macro START_CLOCKS
-	move.d REG_ADDR(clkgen, regi_clkgen, rw_clk_ctrl), $r1
-	move.d [$r1], $r0
-	or.d REG_STATE(clkgen, rw_clk_ctrl, cpu, yes) | \
-	     REG_STATE(clkgen, rw_clk_ctrl, ddr2, yes) | \
-	     REG_STATE(clkgen, rw_clk_ctrl, memarb_bar_ddr, yes), $r0
-	move.d $r0, [$r1]
-	.endm
-
-	.macro SETUP_WAIT_STATES
-	move.d REG_ADDR(pio, regi_pio, rw_ce0_cfg), $r0
-	move.d CONFIG_ETRAX_PIO_CE0_CFG, $r1
-	move.d $r1, [$r0]
-	move.d REG_ADDR(pio, regi_pio, rw_ce1_cfg), $r0
-	move.d CONFIG_ETRAX_PIO_CE1_CFG, $r1
-	move.d $r1, [$r0]
-	move.d REG_ADDR(pio, regi_pio, rw_ce2_cfg), $r0
-	move.d CONFIG_ETRAX_PIO_CE2_CFG, $r1
-	move.d $r1, [$r0]
-	.endm
diff --git a/include/asm-cris/arch-v32/mach-fs/arbiter.h b/include/asm-cris/arch-v32/mach-fs/arbiter.h
deleted file mode 100644
index a2e0ec8faa7d..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/arbiter.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_ARBITER_H
-#define _ASM_CRIS_ARCH_ARBITER_H
-
-#define EXT_REGION 0
-#define INT_REGION 1
-
-typedef void (watch_callback)(void);
-
-enum {
-	arbiter_all_dmas = 0x3ff,
-	arbiter_cpu = 0xc00,
-	arbiter_all_clients = 0x3fff
-};
-
-enum {
-	arbiter_all_read = 0x55,
-	arbiter_all_write = 0xaa,
-	arbiter_all_accesses = 0xff
-};
-
-int crisv32_arbiter_allocate_bandwidth(int client, int region,
-		unsigned long bandwidth);
-int crisv32_arbiter_watch(unsigned long start, unsigned long size,
-		unsigned long clients, unsigned long accesses,
-		watch_callback * cb);
-int crisv32_arbiter_unwatch(int id);
-
-#endif
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h
deleted file mode 100644
index 0a409c92837e..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h
+++ /dev/null
@@ -1,319 +0,0 @@
-#ifndef __bif_core_defs_asm_h
-#define __bif_core_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/bif/rtl/bif_core_regs.r
- *     id:           bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp 
- *     last modfied: Mon Apr 11 16:06:33 2005
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r
- *      id: $Id: bif_core_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_grp1_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp1_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp1_cfg___lw___width 6
-#define reg_bif_core_rw_grp1_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp1_cfg___ew___width 3
-#define reg_bif_core_rw_grp1_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp1_cfg___zw___width 3
-#define reg_bif_core_rw_grp1_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp1_cfg___aw___width 2
-#define reg_bif_core_rw_grp1_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp1_cfg___dw___width 2
-#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp1_cfg___ewb___width 2
-#define reg_bif_core_rw_grp1_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp1_cfg___bw___width 1
-#define reg_bif_core_rw_grp1_cfg___bw___bit 18
-#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp1_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp1_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp1_cfg___mode___width 1
-#define reg_bif_core_rw_grp1_cfg___mode___bit 21
-#define reg_bif_core_rw_grp1_cfg_offset 0
-
-/* Register rw_grp2_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp2_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp2_cfg___lw___width 6
-#define reg_bif_core_rw_grp2_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp2_cfg___ew___width 3
-#define reg_bif_core_rw_grp2_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp2_cfg___zw___width 3
-#define reg_bif_core_rw_grp2_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp2_cfg___aw___width 2
-#define reg_bif_core_rw_grp2_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp2_cfg___dw___width 2
-#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp2_cfg___ewb___width 2
-#define reg_bif_core_rw_grp2_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp2_cfg___bw___width 1
-#define reg_bif_core_rw_grp2_cfg___bw___bit 18
-#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp2_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp2_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp2_cfg___mode___width 1
-#define reg_bif_core_rw_grp2_cfg___mode___bit 21
-#define reg_bif_core_rw_grp2_cfg_offset 4
-
-/* Register rw_grp3_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp3_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp3_cfg___lw___width 6
-#define reg_bif_core_rw_grp3_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp3_cfg___ew___width 3
-#define reg_bif_core_rw_grp3_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp3_cfg___zw___width 3
-#define reg_bif_core_rw_grp3_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp3_cfg___aw___width 2
-#define reg_bif_core_rw_grp3_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp3_cfg___dw___width 2
-#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp3_cfg___ewb___width 2
-#define reg_bif_core_rw_grp3_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp3_cfg___bw___width 1
-#define reg_bif_core_rw_grp3_cfg___bw___bit 18
-#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp3_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp3_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp3_cfg___mode___width 1
-#define reg_bif_core_rw_grp3_cfg___mode___bit 21
-#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24
-#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26
-#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28
-#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30
-#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2
-#define reg_bif_core_rw_grp3_cfg_offset 8
-
-/* Register rw_grp4_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp4_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp4_cfg___lw___width 6
-#define reg_bif_core_rw_grp4_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp4_cfg___ew___width 3
-#define reg_bif_core_rw_grp4_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp4_cfg___zw___width 3
-#define reg_bif_core_rw_grp4_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp4_cfg___aw___width 2
-#define reg_bif_core_rw_grp4_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp4_cfg___dw___width 2
-#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp4_cfg___ewb___width 2
-#define reg_bif_core_rw_grp4_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp4_cfg___bw___width 1
-#define reg_bif_core_rw_grp4_cfg___bw___bit 18
-#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp4_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp4_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp4_cfg___mode___width 1
-#define reg_bif_core_rw_grp4_cfg___mode___bit 21
-#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26
-#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2
-#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28
-#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2
-#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30
-#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2
-#define reg_bif_core_rw_grp4_cfg_offset 12
-
-/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0
-#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5
-#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3
-#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8
-#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9
-#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10
-#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14
-#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15
-#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp0_offset 16
-
-/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0
-#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5
-#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3
-#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8
-#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9
-#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10
-#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14
-#define reg_bif_core_rw_sdram_cfg_grp1_offset 20
-
-/* Register rw_sdram_timing, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_timing___cl___lsb 0
-#define reg_bif_core_rw_sdram_timing___cl___width 3
-#define reg_bif_core_rw_sdram_timing___rcd___lsb 3
-#define reg_bif_core_rw_sdram_timing___rcd___width 3
-#define reg_bif_core_rw_sdram_timing___rp___lsb 6
-#define reg_bif_core_rw_sdram_timing___rp___width 3
-#define reg_bif_core_rw_sdram_timing___rc___lsb 9
-#define reg_bif_core_rw_sdram_timing___rc___width 2
-#define reg_bif_core_rw_sdram_timing___dpl___lsb 11
-#define reg_bif_core_rw_sdram_timing___dpl___width 2
-#define reg_bif_core_rw_sdram_timing___pde___lsb 13
-#define reg_bif_core_rw_sdram_timing___pde___width 1
-#define reg_bif_core_rw_sdram_timing___pde___bit 13
-#define reg_bif_core_rw_sdram_timing___ref___lsb 14
-#define reg_bif_core_rw_sdram_timing___ref___width 2
-#define reg_bif_core_rw_sdram_timing___cpd___lsb 16
-#define reg_bif_core_rw_sdram_timing___cpd___width 1
-#define reg_bif_core_rw_sdram_timing___cpd___bit 16
-#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17
-#define reg_bif_core_rw_sdram_timing___sdcke___width 1
-#define reg_bif_core_rw_sdram_timing___sdcke___bit 17
-#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18
-#define reg_bif_core_rw_sdram_timing___sdclk___width 1
-#define reg_bif_core_rw_sdram_timing___sdclk___bit 18
-#define reg_bif_core_rw_sdram_timing_offset 24
-
-/* Register rw_sdram_cmd, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0
-#define reg_bif_core_rw_sdram_cmd___cmd___width 3
-#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3
-#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15
-#define reg_bif_core_rw_sdram_cmd_offset 28
-
-/* Register rs_sdram_ref_stat, scope bif_core, type rs */
-#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0
-#define reg_bif_core_rs_sdram_ref_stat___ok___width 1
-#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0
-#define reg_bif_core_rs_sdram_ref_stat_offset 32
-
-/* Register r_sdram_ref_stat, scope bif_core, type r */
-#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0
-#define reg_bif_core_r_sdram_ref_stat___ok___width 1
-#define reg_bif_core_r_sdram_ref_stat___ok___bit 0
-#define reg_bif_core_r_sdram_ref_stat_offset 36
-
-
-/* Constants */
-#define regk_bif_core_bank2                       0x00000000
-#define regk_bif_core_bank4                       0x00000001
-#define regk_bif_core_bit10                       0x0000000a
-#define regk_bif_core_bit11                       0x0000000b
-#define regk_bif_core_bit12                       0x0000000c
-#define regk_bif_core_bit13                       0x0000000d
-#define regk_bif_core_bit14                       0x0000000e
-#define regk_bif_core_bit15                       0x0000000f
-#define regk_bif_core_bit16                       0x00000010
-#define regk_bif_core_bit17                       0x00000011
-#define regk_bif_core_bit18                       0x00000012
-#define regk_bif_core_bit19                       0x00000013
-#define regk_bif_core_bit20                       0x00000014
-#define regk_bif_core_bit21                       0x00000015
-#define regk_bif_core_bit22                       0x00000016
-#define regk_bif_core_bit23                       0x00000017
-#define regk_bif_core_bit24                       0x00000018
-#define regk_bif_core_bit25                       0x00000019
-#define regk_bif_core_bit26                       0x0000001a
-#define regk_bif_core_bit27                       0x0000001b
-#define regk_bif_core_bit28                       0x0000001c
-#define regk_bif_core_bit29                       0x0000001d
-#define regk_bif_core_bit9                        0x00000009
-#define regk_bif_core_bw16                        0x00000001
-#define regk_bif_core_bw32                        0x00000000
-#define regk_bif_core_bwe                         0x00000000
-#define regk_bif_core_cwe                         0x00000001
-#define regk_bif_core_e15us                       0x00000001
-#define regk_bif_core_e7800ns                     0x00000002
-#define regk_bif_core_grp0                        0x00000000
-#define regk_bif_core_grp1                        0x00000001
-#define regk_bif_core_mrs                         0x00000003
-#define regk_bif_core_no                          0x00000000
-#define regk_bif_core_none                        0x00000000
-#define regk_bif_core_nop                         0x00000000
-#define regk_bif_core_off                         0x00000000
-#define regk_bif_core_pre                         0x00000002
-#define regk_bif_core_r_sdram_ref_stat_default    0x00000001
-#define regk_bif_core_rd                          0x00000002
-#define regk_bif_core_ref                         0x00000001
-#define regk_bif_core_rs_sdram_ref_stat_default   0x00000001
-#define regk_bif_core_rw_grp1_cfg_default         0x000006cf
-#define regk_bif_core_rw_grp2_cfg_default         0x000006cf
-#define regk_bif_core_rw_grp3_cfg_default         0x000006cf
-#define regk_bif_core_rw_grp4_cfg_default         0x000006cf
-#define regk_bif_core_rw_sdram_cfg_grp1_default   0x00000000
-#define regk_bif_core_slf                         0x00000004
-#define regk_bif_core_wr                          0x00000001
-#define regk_bif_core_yes                         0x00000001
-#endif /* __bif_core_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h
deleted file mode 100644
index a9908dfc2937..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h
+++ /dev/null
@@ -1,131 +0,0 @@
-#ifndef __config_defs_asm_h
-#define __config_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../rtl/config_regs.r
- *     id:           config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp 
- *     last modfied: Thu Mar  4 12:34:39 2004
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r
- *      id: $Id: config_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_bootsel, scope config, type r */
-#define reg_config_r_bootsel___boot_mode___lsb 0
-#define reg_config_r_bootsel___boot_mode___width 3
-#define reg_config_r_bootsel___full_duplex___lsb 3
-#define reg_config_r_bootsel___full_duplex___width 1
-#define reg_config_r_bootsel___full_duplex___bit 3
-#define reg_config_r_bootsel___user___lsb 4
-#define reg_config_r_bootsel___user___width 1
-#define reg_config_r_bootsel___user___bit 4
-#define reg_config_r_bootsel___pll___lsb 5
-#define reg_config_r_bootsel___pll___width 1
-#define reg_config_r_bootsel___pll___bit 5
-#define reg_config_r_bootsel___flash_bw___lsb 6
-#define reg_config_r_bootsel___flash_bw___width 1
-#define reg_config_r_bootsel___flash_bw___bit 6
-#define reg_config_r_bootsel_offset 0
-
-/* Register rw_clk_ctrl, scope config, type rw */
-#define reg_config_rw_clk_ctrl___pll___lsb 0
-#define reg_config_rw_clk_ctrl___pll___width 1
-#define reg_config_rw_clk_ctrl___pll___bit 0
-#define reg_config_rw_clk_ctrl___cpu___lsb 1
-#define reg_config_rw_clk_ctrl___cpu___width 1
-#define reg_config_rw_clk_ctrl___cpu___bit 1
-#define reg_config_rw_clk_ctrl___iop___lsb 2
-#define reg_config_rw_clk_ctrl___iop___width 1
-#define reg_config_rw_clk_ctrl___iop___bit 2
-#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3
-#define reg_config_rw_clk_ctrl___dma01_eth0___width 1
-#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3
-#define reg_config_rw_clk_ctrl___dma23___lsb 4
-#define reg_config_rw_clk_ctrl___dma23___width 1
-#define reg_config_rw_clk_ctrl___dma23___bit 4
-#define reg_config_rw_clk_ctrl___dma45___lsb 5
-#define reg_config_rw_clk_ctrl___dma45___width 1
-#define reg_config_rw_clk_ctrl___dma45___bit 5
-#define reg_config_rw_clk_ctrl___dma67___lsb 6
-#define reg_config_rw_clk_ctrl___dma67___width 1
-#define reg_config_rw_clk_ctrl___dma67___bit 6
-#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7
-#define reg_config_rw_clk_ctrl___dma89_strcop___width 1
-#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7
-#define reg_config_rw_clk_ctrl___bif___lsb 8
-#define reg_config_rw_clk_ctrl___bif___width 1
-#define reg_config_rw_clk_ctrl___bif___bit 8
-#define reg_config_rw_clk_ctrl___fix_io___lsb 9
-#define reg_config_rw_clk_ctrl___fix_io___width 1
-#define reg_config_rw_clk_ctrl___fix_io___bit 9
-#define reg_config_rw_clk_ctrl_offset 4
-
-/* Register rw_pad_ctrl, scope config, type rw */
-#define reg_config_rw_pad_ctrl___usb_susp___lsb 0
-#define reg_config_rw_pad_ctrl___usb_susp___width 1
-#define reg_config_rw_pad_ctrl___usb_susp___bit 0
-#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1
-#define reg_config_rw_pad_ctrl___phyrst_n___width 1
-#define reg_config_rw_pad_ctrl___phyrst_n___bit 1
-#define reg_config_rw_pad_ctrl_offset 8
-
-
-/* Constants */
-#define regk_config_bw16                          0x00000000
-#define regk_config_bw32                          0x00000001
-#define regk_config_master                        0x00000005
-#define regk_config_nand                          0x00000003
-#define regk_config_net_rx                        0x00000001
-#define regk_config_net_tx_rx                     0x00000002
-#define regk_config_no                            0x00000000
-#define regk_config_none                          0x00000007
-#define regk_config_nor                           0x00000000
-#define regk_config_rw_clk_ctrl_default           0x00000002
-#define regk_config_rw_pad_ctrl_default           0x00000000
-#define regk_config_ser                           0x00000004
-#define regk_config_slave                         0x00000006
-#define regk_config_yes                           0x00000001
-#endif /* __config_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h
deleted file mode 100644
index be4c63936d90..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h
+++ /dev/null
@@ -1,276 +0,0 @@
-#ifndef __gio_defs_asm_h
-#define __gio_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/gio/rtl/gio_regs.r
- *     id:           gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp 
- *     last modfied: Mon Apr 11 16:07:47 2005
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r
- *      id: $Id: gio_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_pa_dout, scope gio, type rw */
-#define reg_gio_rw_pa_dout___data___lsb 0
-#define reg_gio_rw_pa_dout___data___width 8
-#define reg_gio_rw_pa_dout_offset 0
-
-/* Register r_pa_din, scope gio, type r */
-#define reg_gio_r_pa_din___data___lsb 0
-#define reg_gio_r_pa_din___data___width 8
-#define reg_gio_r_pa_din_offset 4
-
-/* Register rw_pa_oe, scope gio, type rw */
-#define reg_gio_rw_pa_oe___oe___lsb 0
-#define reg_gio_rw_pa_oe___oe___width 8
-#define reg_gio_rw_pa_oe_offset 8
-
-/* Register rw_intr_cfg, scope gio, type rw */
-#define reg_gio_rw_intr_cfg___pa0___lsb 0
-#define reg_gio_rw_intr_cfg___pa0___width 3
-#define reg_gio_rw_intr_cfg___pa1___lsb 3
-#define reg_gio_rw_intr_cfg___pa1___width 3
-#define reg_gio_rw_intr_cfg___pa2___lsb 6
-#define reg_gio_rw_intr_cfg___pa2___width 3
-#define reg_gio_rw_intr_cfg___pa3___lsb 9
-#define reg_gio_rw_intr_cfg___pa3___width 3
-#define reg_gio_rw_intr_cfg___pa4___lsb 12
-#define reg_gio_rw_intr_cfg___pa4___width 3
-#define reg_gio_rw_intr_cfg___pa5___lsb 15
-#define reg_gio_rw_intr_cfg___pa5___width 3
-#define reg_gio_rw_intr_cfg___pa6___lsb 18
-#define reg_gio_rw_intr_cfg___pa6___width 3
-#define reg_gio_rw_intr_cfg___pa7___lsb 21
-#define reg_gio_rw_intr_cfg___pa7___width 3
-#define reg_gio_rw_intr_cfg_offset 12
-
-/* Register rw_intr_mask, scope gio, type rw */
-#define reg_gio_rw_intr_mask___pa0___lsb 0
-#define reg_gio_rw_intr_mask___pa0___width 1
-#define reg_gio_rw_intr_mask___pa0___bit 0
-#define reg_gio_rw_intr_mask___pa1___lsb 1
-#define reg_gio_rw_intr_mask___pa1___width 1
-#define reg_gio_rw_intr_mask___pa1___bit 1
-#define reg_gio_rw_intr_mask___pa2___lsb 2
-#define reg_gio_rw_intr_mask___pa2___width 1
-#define reg_gio_rw_intr_mask___pa2___bit 2
-#define reg_gio_rw_intr_mask___pa3___lsb 3
-#define reg_gio_rw_intr_mask___pa3___width 1
-#define reg_gio_rw_intr_mask___pa3___bit 3
-#define reg_gio_rw_intr_mask___pa4___lsb 4
-#define reg_gio_rw_intr_mask___pa4___width 1
-#define reg_gio_rw_intr_mask___pa4___bit 4
-#define reg_gio_rw_intr_mask___pa5___lsb 5
-#define reg_gio_rw_intr_mask___pa5___width 1
-#define reg_gio_rw_intr_mask___pa5___bit 5
-#define reg_gio_rw_intr_mask___pa6___lsb 6
-#define reg_gio_rw_intr_mask___pa6___width 1
-#define reg_gio_rw_intr_mask___pa6___bit 6
-#define reg_gio_rw_intr_mask___pa7___lsb 7
-#define reg_gio_rw_intr_mask___pa7___width 1
-#define reg_gio_rw_intr_mask___pa7___bit 7
-#define reg_gio_rw_intr_mask_offset 16
-
-/* Register rw_ack_intr, scope gio, type rw */
-#define reg_gio_rw_ack_intr___pa0___lsb 0
-#define reg_gio_rw_ack_intr___pa0___width 1
-#define reg_gio_rw_ack_intr___pa0___bit 0
-#define reg_gio_rw_ack_intr___pa1___lsb 1
-#define reg_gio_rw_ack_intr___pa1___width 1
-#define reg_gio_rw_ack_intr___pa1___bit 1
-#define reg_gio_rw_ack_intr___pa2___lsb 2
-#define reg_gio_rw_ack_intr___pa2___width 1
-#define reg_gio_rw_ack_intr___pa2___bit 2
-#define reg_gio_rw_ack_intr___pa3___lsb 3
-#define reg_gio_rw_ack_intr___pa3___width 1
-#define reg_gio_rw_ack_intr___pa3___bit 3
-#define reg_gio_rw_ack_intr___pa4___lsb 4
-#define reg_gio_rw_ack_intr___pa4___width 1
-#define reg_gio_rw_ack_intr___pa4___bit 4
-#define reg_gio_rw_ack_intr___pa5___lsb 5
-#define reg_gio_rw_ack_intr___pa5___width 1
-#define reg_gio_rw_ack_intr___pa5___bit 5
-#define reg_gio_rw_ack_intr___pa6___lsb 6
-#define reg_gio_rw_ack_intr___pa6___width 1
-#define reg_gio_rw_ack_intr___pa6___bit 6
-#define reg_gio_rw_ack_intr___pa7___lsb 7
-#define reg_gio_rw_ack_intr___pa7___width 1
-#define reg_gio_rw_ack_intr___pa7___bit 7
-#define reg_gio_rw_ack_intr_offset 20
-
-/* Register r_intr, scope gio, type r */
-#define reg_gio_r_intr___pa0___lsb 0
-#define reg_gio_r_intr___pa0___width 1
-#define reg_gio_r_intr___pa0___bit 0
-#define reg_gio_r_intr___pa1___lsb 1
-#define reg_gio_r_intr___pa1___width 1
-#define reg_gio_r_intr___pa1___bit 1
-#define reg_gio_r_intr___pa2___lsb 2
-#define reg_gio_r_intr___pa2___width 1
-#define reg_gio_r_intr___pa2___bit 2
-#define reg_gio_r_intr___pa3___lsb 3
-#define reg_gio_r_intr___pa3___width 1
-#define reg_gio_r_intr___pa3___bit 3
-#define reg_gio_r_intr___pa4___lsb 4
-#define reg_gio_r_intr___pa4___width 1
-#define reg_gio_r_intr___pa4___bit 4
-#define reg_gio_r_intr___pa5___lsb 5
-#define reg_gio_r_intr___pa5___width 1
-#define reg_gio_r_intr___pa5___bit 5
-#define reg_gio_r_intr___pa6___lsb 6
-#define reg_gio_r_intr___pa6___width 1
-#define reg_gio_r_intr___pa6___bit 6
-#define reg_gio_r_intr___pa7___lsb 7
-#define reg_gio_r_intr___pa7___width 1
-#define reg_gio_r_intr___pa7___bit 7
-#define reg_gio_r_intr_offset 24
-
-/* Register r_masked_intr, scope gio, type r */
-#define reg_gio_r_masked_intr___pa0___lsb 0
-#define reg_gio_r_masked_intr___pa0___width 1
-#define reg_gio_r_masked_intr___pa0___bit 0
-#define reg_gio_r_masked_intr___pa1___lsb 1
-#define reg_gio_r_masked_intr___pa1___width 1
-#define reg_gio_r_masked_intr___pa1___bit 1
-#define reg_gio_r_masked_intr___pa2___lsb 2
-#define reg_gio_r_masked_intr___pa2___width 1
-#define reg_gio_r_masked_intr___pa2___bit 2
-#define reg_gio_r_masked_intr___pa3___lsb 3
-#define reg_gio_r_masked_intr___pa3___width 1
-#define reg_gio_r_masked_intr___pa3___bit 3
-#define reg_gio_r_masked_intr___pa4___lsb 4
-#define reg_gio_r_masked_intr___pa4___width 1
-#define reg_gio_r_masked_intr___pa4___bit 4
-#define reg_gio_r_masked_intr___pa5___lsb 5
-#define reg_gio_r_masked_intr___pa5___width 1
-#define reg_gio_r_masked_intr___pa5___bit 5
-#define reg_gio_r_masked_intr___pa6___lsb 6
-#define reg_gio_r_masked_intr___pa6___width 1
-#define reg_gio_r_masked_intr___pa6___bit 6
-#define reg_gio_r_masked_intr___pa7___lsb 7
-#define reg_gio_r_masked_intr___pa7___width 1
-#define reg_gio_r_masked_intr___pa7___bit 7
-#define reg_gio_r_masked_intr_offset 28
-
-/* Register rw_pb_dout, scope gio, type rw */
-#define reg_gio_rw_pb_dout___data___lsb 0
-#define reg_gio_rw_pb_dout___data___width 18
-#define reg_gio_rw_pb_dout_offset 32
-
-/* Register r_pb_din, scope gio, type r */
-#define reg_gio_r_pb_din___data___lsb 0
-#define reg_gio_r_pb_din___data___width 18
-#define reg_gio_r_pb_din_offset 36
-
-/* Register rw_pb_oe, scope gio, type rw */
-#define reg_gio_rw_pb_oe___oe___lsb 0
-#define reg_gio_rw_pb_oe___oe___width 18
-#define reg_gio_rw_pb_oe_offset 40
-
-/* Register rw_pc_dout, scope gio, type rw */
-#define reg_gio_rw_pc_dout___data___lsb 0
-#define reg_gio_rw_pc_dout___data___width 18
-#define reg_gio_rw_pc_dout_offset 48
-
-/* Register r_pc_din, scope gio, type r */
-#define reg_gio_r_pc_din___data___lsb 0
-#define reg_gio_r_pc_din___data___width 18
-#define reg_gio_r_pc_din_offset 52
-
-/* Register rw_pc_oe, scope gio, type rw */
-#define reg_gio_rw_pc_oe___oe___lsb 0
-#define reg_gio_rw_pc_oe___oe___width 18
-#define reg_gio_rw_pc_oe_offset 56
-
-/* Register rw_pd_dout, scope gio, type rw */
-#define reg_gio_rw_pd_dout___data___lsb 0
-#define reg_gio_rw_pd_dout___data___width 18
-#define reg_gio_rw_pd_dout_offset 64
-
-/* Register r_pd_din, scope gio, type r */
-#define reg_gio_r_pd_din___data___lsb 0
-#define reg_gio_r_pd_din___data___width 18
-#define reg_gio_r_pd_din_offset 68
-
-/* Register rw_pd_oe, scope gio, type rw */
-#define reg_gio_rw_pd_oe___oe___lsb 0
-#define reg_gio_rw_pd_oe___oe___width 18
-#define reg_gio_rw_pd_oe_offset 72
-
-/* Register rw_pe_dout, scope gio, type rw */
-#define reg_gio_rw_pe_dout___data___lsb 0
-#define reg_gio_rw_pe_dout___data___width 18
-#define reg_gio_rw_pe_dout_offset 80
-
-/* Register r_pe_din, scope gio, type r */
-#define reg_gio_r_pe_din___data___lsb 0
-#define reg_gio_r_pe_din___data___width 18
-#define reg_gio_r_pe_din_offset 84
-
-/* Register rw_pe_oe, scope gio, type rw */
-#define reg_gio_rw_pe_oe___oe___lsb 0
-#define reg_gio_rw_pe_oe___oe___width 18
-#define reg_gio_rw_pe_oe_offset 88
-
-
-/* Constants */
-#define regk_gio_anyedge                          0x00000007
-#define regk_gio_hi                               0x00000001
-#define regk_gio_lo                               0x00000002
-#define regk_gio_negedge                          0x00000006
-#define regk_gio_no                               0x00000000
-#define regk_gio_off                              0x00000000
-#define regk_gio_posedge                          0x00000005
-#define regk_gio_rw_intr_cfg_default              0x00000000
-#define regk_gio_rw_intr_mask_default             0x00000000
-#define regk_gio_rw_pa_oe_default                 0x00000000
-#define regk_gio_rw_pb_oe_default                 0x00000000
-#define regk_gio_rw_pc_oe_default                 0x00000000
-#define regk_gio_rw_pd_oe_default                 0x00000000
-#define regk_gio_rw_pe_oe_default                 0x00000000
-#define regk_gio_set                              0x00000003
-#define regk_gio_yes                              0x00000001
-#endif /* __gio_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h
deleted file mode 100644
index 30cf5a936b64..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h
+++ /dev/null
@@ -1,632 +0,0 @@
-#ifndef __pinmux_defs_asm_h
-#define __pinmux_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/pinmux/rtl/guinness/pinmux_regs.r
- *     id:           pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp 
- *     last modfied: Mon Apr 11 16:09:11 2005
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
- *      id: $Id: pinmux_defs_asm.h,v 1.1 2007/04/11 11:00:39 ricardw Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_pa, scope pinmux, type rw */
-#define reg_pinmux_rw_pa___pa0___lsb 0
-#define reg_pinmux_rw_pa___pa0___width 1
-#define reg_pinmux_rw_pa___pa0___bit 0
-#define reg_pinmux_rw_pa___pa1___lsb 1
-#define reg_pinmux_rw_pa___pa1___width 1
-#define reg_pinmux_rw_pa___pa1___bit 1
-#define reg_pinmux_rw_pa___pa2___lsb 2
-#define reg_pinmux_rw_pa___pa2___width 1
-#define reg_pinmux_rw_pa___pa2___bit 2
-#define reg_pinmux_rw_pa___pa3___lsb 3
-#define reg_pinmux_rw_pa___pa3___width 1
-#define reg_pinmux_rw_pa___pa3___bit 3
-#define reg_pinmux_rw_pa___pa4___lsb 4
-#define reg_pinmux_rw_pa___pa4___width 1
-#define reg_pinmux_rw_pa___pa4___bit 4
-#define reg_pinmux_rw_pa___pa5___lsb 5
-#define reg_pinmux_rw_pa___pa5___width 1
-#define reg_pinmux_rw_pa___pa5___bit 5
-#define reg_pinmux_rw_pa___pa6___lsb 6
-#define reg_pinmux_rw_pa___pa6___width 1
-#define reg_pinmux_rw_pa___pa6___bit 6
-#define reg_pinmux_rw_pa___pa7___lsb 7
-#define reg_pinmux_rw_pa___pa7___width 1
-#define reg_pinmux_rw_pa___pa7___bit 7
-#define reg_pinmux_rw_pa___csp2_n___lsb 8
-#define reg_pinmux_rw_pa___csp2_n___width 1
-#define reg_pinmux_rw_pa___csp2_n___bit 8
-#define reg_pinmux_rw_pa___csp3_n___lsb 9
-#define reg_pinmux_rw_pa___csp3_n___width 1
-#define reg_pinmux_rw_pa___csp3_n___bit 9
-#define reg_pinmux_rw_pa___csp5_n___lsb 10
-#define reg_pinmux_rw_pa___csp5_n___width 1
-#define reg_pinmux_rw_pa___csp5_n___bit 10
-#define reg_pinmux_rw_pa___csp6_n___lsb 11
-#define reg_pinmux_rw_pa___csp6_n___width 1
-#define reg_pinmux_rw_pa___csp6_n___bit 11
-#define reg_pinmux_rw_pa___hsh4___lsb 12
-#define reg_pinmux_rw_pa___hsh4___width 1
-#define reg_pinmux_rw_pa___hsh4___bit 12
-#define reg_pinmux_rw_pa___hsh5___lsb 13
-#define reg_pinmux_rw_pa___hsh5___width 1
-#define reg_pinmux_rw_pa___hsh5___bit 13
-#define reg_pinmux_rw_pa___hsh6___lsb 14
-#define reg_pinmux_rw_pa___hsh6___width 1
-#define reg_pinmux_rw_pa___hsh6___bit 14
-#define reg_pinmux_rw_pa___hsh7___lsb 15
-#define reg_pinmux_rw_pa___hsh7___width 1
-#define reg_pinmux_rw_pa___hsh7___bit 15
-#define reg_pinmux_rw_pa_offset 0
-
-/* Register rw_hwprot, scope pinmux, type rw */
-#define reg_pinmux_rw_hwprot___ser1___lsb 0
-#define reg_pinmux_rw_hwprot___ser1___width 1
-#define reg_pinmux_rw_hwprot___ser1___bit 0
-#define reg_pinmux_rw_hwprot___ser2___lsb 1
-#define reg_pinmux_rw_hwprot___ser2___width 1
-#define reg_pinmux_rw_hwprot___ser2___bit 1
-#define reg_pinmux_rw_hwprot___ser3___lsb 2
-#define reg_pinmux_rw_hwprot___ser3___width 1
-#define reg_pinmux_rw_hwprot___ser3___bit 2
-#define reg_pinmux_rw_hwprot___sser0___lsb 3
-#define reg_pinmux_rw_hwprot___sser0___width 1
-#define reg_pinmux_rw_hwprot___sser0___bit 3
-#define reg_pinmux_rw_hwprot___sser1___lsb 4
-#define reg_pinmux_rw_hwprot___sser1___width 1
-#define reg_pinmux_rw_hwprot___sser1___bit 4
-#define reg_pinmux_rw_hwprot___ata0___lsb 5
-#define reg_pinmux_rw_hwprot___ata0___width 1
-#define reg_pinmux_rw_hwprot___ata0___bit 5
-#define reg_pinmux_rw_hwprot___ata1___lsb 6
-#define reg_pinmux_rw_hwprot___ata1___width 1
-#define reg_pinmux_rw_hwprot___ata1___bit 6
-#define reg_pinmux_rw_hwprot___ata2___lsb 7
-#define reg_pinmux_rw_hwprot___ata2___width 1
-#define reg_pinmux_rw_hwprot___ata2___bit 7
-#define reg_pinmux_rw_hwprot___ata3___lsb 8
-#define reg_pinmux_rw_hwprot___ata3___width 1
-#define reg_pinmux_rw_hwprot___ata3___bit 8
-#define reg_pinmux_rw_hwprot___ata___lsb 9
-#define reg_pinmux_rw_hwprot___ata___width 1
-#define reg_pinmux_rw_hwprot___ata___bit 9
-#define reg_pinmux_rw_hwprot___eth1___lsb 10
-#define reg_pinmux_rw_hwprot___eth1___width 1
-#define reg_pinmux_rw_hwprot___eth1___bit 10
-#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11
-#define reg_pinmux_rw_hwprot___eth1_mgm___width 1
-#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11
-#define reg_pinmux_rw_hwprot___timer___lsb 12
-#define reg_pinmux_rw_hwprot___timer___width 1
-#define reg_pinmux_rw_hwprot___timer___bit 12
-#define reg_pinmux_rw_hwprot___p21___lsb 13
-#define reg_pinmux_rw_hwprot___p21___width 1
-#define reg_pinmux_rw_hwprot___p21___bit 13
-#define reg_pinmux_rw_hwprot_offset 4
-
-/* Register rw_pb_gio, scope pinmux, type rw */
-#define reg_pinmux_rw_pb_gio___pb0___lsb 0
-#define reg_pinmux_rw_pb_gio___pb0___width 1
-#define reg_pinmux_rw_pb_gio___pb0___bit 0
-#define reg_pinmux_rw_pb_gio___pb1___lsb 1
-#define reg_pinmux_rw_pb_gio___pb1___width 1
-#define reg_pinmux_rw_pb_gio___pb1___bit 1
-#define reg_pinmux_rw_pb_gio___pb2___lsb 2
-#define reg_pinmux_rw_pb_gio___pb2___width 1
-#define reg_pinmux_rw_pb_gio___pb2___bit 2
-#define reg_pinmux_rw_pb_gio___pb3___lsb 3
-#define reg_pinmux_rw_pb_gio___pb3___width 1
-#define reg_pinmux_rw_pb_gio___pb3___bit 3
-#define reg_pinmux_rw_pb_gio___pb4___lsb 4
-#define reg_pinmux_rw_pb_gio___pb4___width 1
-#define reg_pinmux_rw_pb_gio___pb4___bit 4
-#define reg_pinmux_rw_pb_gio___pb5___lsb 5
-#define reg_pinmux_rw_pb_gio___pb5___width 1
-#define reg_pinmux_rw_pb_gio___pb5___bit 5
-#define reg_pinmux_rw_pb_gio___pb6___lsb 6
-#define reg_pinmux_rw_pb_gio___pb6___width 1
-#define reg_pinmux_rw_pb_gio___pb6___bit 6
-#define reg_pinmux_rw_pb_gio___pb7___lsb 7
-#define reg_pinmux_rw_pb_gio___pb7___width 1
-#define reg_pinmux_rw_pb_gio___pb7___bit 7
-#define reg_pinmux_rw_pb_gio___pb8___lsb 8
-#define reg_pinmux_rw_pb_gio___pb8___width 1
-#define reg_pinmux_rw_pb_gio___pb8___bit 8
-#define reg_pinmux_rw_pb_gio___pb9___lsb 9
-#define reg_pinmux_rw_pb_gio___pb9___width 1
-#define reg_pinmux_rw_pb_gio___pb9___bit 9
-#define reg_pinmux_rw_pb_gio___pb10___lsb 10
-#define reg_pinmux_rw_pb_gio___pb10___width 1
-#define reg_pinmux_rw_pb_gio___pb10___bit 10
-#define reg_pinmux_rw_pb_gio___pb11___lsb 11
-#define reg_pinmux_rw_pb_gio___pb11___width 1
-#define reg_pinmux_rw_pb_gio___pb11___bit 11
-#define reg_pinmux_rw_pb_gio___pb12___lsb 12
-#define reg_pinmux_rw_pb_gio___pb12___width 1
-#define reg_pinmux_rw_pb_gio___pb12___bit 12
-#define reg_pinmux_rw_pb_gio___pb13___lsb 13
-#define reg_pinmux_rw_pb_gio___pb13___width 1
-#define reg_pinmux_rw_pb_gio___pb13___bit 13
-#define reg_pinmux_rw_pb_gio___pb14___lsb 14
-#define reg_pinmux_rw_pb_gio___pb14___width 1
-#define reg_pinmux_rw_pb_gio___pb14___bit 14
-#define reg_pinmux_rw_pb_gio___pb15___lsb 15
-#define reg_pinmux_rw_pb_gio___pb15___width 1
-#define reg_pinmux_rw_pb_gio___pb15___bit 15
-#define reg_pinmux_rw_pb_gio___pb16___lsb 16
-#define reg_pinmux_rw_pb_gio___pb16___width 1
-#define reg_pinmux_rw_pb_gio___pb16___bit 16
-#define reg_pinmux_rw_pb_gio___pb17___lsb 17
-#define reg_pinmux_rw_pb_gio___pb17___width 1
-#define reg_pinmux_rw_pb_gio___pb17___bit 17
-#define reg_pinmux_rw_pb_gio_offset 8
-
-/* Register rw_pb_iop, scope pinmux, type rw */
-#define reg_pinmux_rw_pb_iop___pb0___lsb 0
-#define reg_pinmux_rw_pb_iop___pb0___width 1
-#define reg_pinmux_rw_pb_iop___pb0___bit 0
-#define reg_pinmux_rw_pb_iop___pb1___lsb 1
-#define reg_pinmux_rw_pb_iop___pb1___width 1
-#define reg_pinmux_rw_pb_iop___pb1___bit 1
-#define reg_pinmux_rw_pb_iop___pb2___lsb 2
-#define reg_pinmux_rw_pb_iop___pb2___width 1
-#define reg_pinmux_rw_pb_iop___pb2___bit 2
-#define reg_pinmux_rw_pb_iop___pb3___lsb 3
-#define reg_pinmux_rw_pb_iop___pb3___width 1
-#define reg_pinmux_rw_pb_iop___pb3___bit 3
-#define reg_pinmux_rw_pb_iop___pb4___lsb 4
-#define reg_pinmux_rw_pb_iop___pb4___width 1
-#define reg_pinmux_rw_pb_iop___pb4___bit 4
-#define reg_pinmux_rw_pb_iop___pb5___lsb 5
-#define reg_pinmux_rw_pb_iop___pb5___width 1
-#define reg_pinmux_rw_pb_iop___pb5___bit 5
-#define reg_pinmux_rw_pb_iop___pb6___lsb 6
-#define reg_pinmux_rw_pb_iop___pb6___width 1
-#define reg_pinmux_rw_pb_iop___pb6___bit 6
-#define reg_pinmux_rw_pb_iop___pb7___lsb 7
-#define reg_pinmux_rw_pb_iop___pb7___width 1
-#define reg_pinmux_rw_pb_iop___pb7___bit 7
-#define reg_pinmux_rw_pb_iop___pb8___lsb 8
-#define reg_pinmux_rw_pb_iop___pb8___width 1
-#define reg_pinmux_rw_pb_iop___pb8___bit 8
-#define reg_pinmux_rw_pb_iop___pb9___lsb 9
-#define reg_pinmux_rw_pb_iop___pb9___width 1
-#define reg_pinmux_rw_pb_iop___pb9___bit 9
-#define reg_pinmux_rw_pb_iop___pb10___lsb 10
-#define reg_pinmux_rw_pb_iop___pb10___width 1
-#define reg_pinmux_rw_pb_iop___pb10___bit 10
-#define reg_pinmux_rw_pb_iop___pb11___lsb 11
-#define reg_pinmux_rw_pb_iop___pb11___width 1
-#define reg_pinmux_rw_pb_iop___pb11___bit 11
-#define reg_pinmux_rw_pb_iop___pb12___lsb 12
-#define reg_pinmux_rw_pb_iop___pb12___width 1
-#define reg_pinmux_rw_pb_iop___pb12___bit 12
-#define reg_pinmux_rw_pb_iop___pb13___lsb 13
-#define reg_pinmux_rw_pb_iop___pb13___width 1
-#define reg_pinmux_rw_pb_iop___pb13___bit 13
-#define reg_pinmux_rw_pb_iop___pb14___lsb 14
-#define reg_pinmux_rw_pb_iop___pb14___width 1
-#define reg_pinmux_rw_pb_iop___pb14___bit 14
-#define reg_pinmux_rw_pb_iop___pb15___lsb 15
-#define reg_pinmux_rw_pb_iop___pb15___width 1
-#define reg_pinmux_rw_pb_iop___pb15___bit 15
-#define reg_pinmux_rw_pb_iop___pb16___lsb 16
-#define reg_pinmux_rw_pb_iop___pb16___width 1
-#define reg_pinmux_rw_pb_iop___pb16___bit 16
-#define reg_pinmux_rw_pb_iop___pb17___lsb 17
-#define reg_pinmux_rw_pb_iop___pb17___width 1
-#define reg_pinmux_rw_pb_iop___pb17___bit 17
-#define reg_pinmux_rw_pb_iop_offset 12
-
-/* Register rw_pc_gio, scope pinmux, type rw */
-#define reg_pinmux_rw_pc_gio___pc0___lsb 0
-#define reg_pinmux_rw_pc_gio___pc0___width 1
-#define reg_pinmux_rw_pc_gio___pc0___bit 0
-#define reg_pinmux_rw_pc_gio___pc1___lsb 1
-#define reg_pinmux_rw_pc_gio___pc1___width 1
-#define reg_pinmux_rw_pc_gio___pc1___bit 1
-#define reg_pinmux_rw_pc_gio___pc2___lsb 2
-#define reg_pinmux_rw_pc_gio___pc2___width 1
-#define reg_pinmux_rw_pc_gio___pc2___bit 2
-#define reg_pinmux_rw_pc_gio___pc3___lsb 3
-#define reg_pinmux_rw_pc_gio___pc3___width 1
-#define reg_pinmux_rw_pc_gio___pc3___bit 3
-#define reg_pinmux_rw_pc_gio___pc4___lsb 4
-#define reg_pinmux_rw_pc_gio___pc4___width 1
-#define reg_pinmux_rw_pc_gio___pc4___bit 4
-#define reg_pinmux_rw_pc_gio___pc5___lsb 5
-#define reg_pinmux_rw_pc_gio___pc5___width 1
-#define reg_pinmux_rw_pc_gio___pc5___bit 5
-#define reg_pinmux_rw_pc_gio___pc6___lsb 6
-#define reg_pinmux_rw_pc_gio___pc6___width 1
-#define reg_pinmux_rw_pc_gio___pc6___bit 6
-#define reg_pinmux_rw_pc_gio___pc7___lsb 7
-#define reg_pinmux_rw_pc_gio___pc7___width 1
-#define reg_pinmux_rw_pc_gio___pc7___bit 7
-#define reg_pinmux_rw_pc_gio___pc8___lsb 8
-#define reg_pinmux_rw_pc_gio___pc8___width 1
-#define reg_pinmux_rw_pc_gio___pc8___bit 8
-#define reg_pinmux_rw_pc_gio___pc9___lsb 9
-#define reg_pinmux_rw_pc_gio___pc9___width 1
-#define reg_pinmux_rw_pc_gio___pc9___bit 9
-#define reg_pinmux_rw_pc_gio___pc10___lsb 10
-#define reg_pinmux_rw_pc_gio___pc10___width 1
-#define reg_pinmux_rw_pc_gio___pc10___bit 10
-#define reg_pinmux_rw_pc_gio___pc11___lsb 11
-#define reg_pinmux_rw_pc_gio___pc11___width 1
-#define reg_pinmux_rw_pc_gio___pc11___bit 11
-#define reg_pinmux_rw_pc_gio___pc12___lsb 12
-#define reg_pinmux_rw_pc_gio___pc12___width 1
-#define reg_pinmux_rw_pc_gio___pc12___bit 12
-#define reg_pinmux_rw_pc_gio___pc13___lsb 13
-#define reg_pinmux_rw_pc_gio___pc13___width 1
-#define reg_pinmux_rw_pc_gio___pc13___bit 13
-#define reg_pinmux_rw_pc_gio___pc14___lsb 14
-#define reg_pinmux_rw_pc_gio___pc14___width 1
-#define reg_pinmux_rw_pc_gio___pc14___bit 14
-#define reg_pinmux_rw_pc_gio___pc15___lsb 15
-#define reg_pinmux_rw_pc_gio___pc15___width 1
-#define reg_pinmux_rw_pc_gio___pc15___bit 15
-#define reg_pinmux_rw_pc_gio___pc16___lsb 16
-#define reg_pinmux_rw_pc_gio___pc16___width 1
-#define reg_pinmux_rw_pc_gio___pc16___bit 16
-#define reg_pinmux_rw_pc_gio___pc17___lsb 17
-#define reg_pinmux_rw_pc_gio___pc17___width 1
-#define reg_pinmux_rw_pc_gio___pc17___bit 17
-#define reg_pinmux_rw_pc_gio_offset 16
-
-/* Register rw_pc_iop, scope pinmux, type rw */
-#define reg_pinmux_rw_pc_iop___pc0___lsb 0
-#define reg_pinmux_rw_pc_iop___pc0___width 1
-#define reg_pinmux_rw_pc_iop___pc0___bit 0
-#define reg_pinmux_rw_pc_iop___pc1___lsb 1
-#define reg_pinmux_rw_pc_iop___pc1___width 1
-#define reg_pinmux_rw_pc_iop___pc1___bit 1
-#define reg_pinmux_rw_pc_iop___pc2___lsb 2
-#define reg_pinmux_rw_pc_iop___pc2___width 1
-#define reg_pinmux_rw_pc_iop___pc2___bit 2
-#define reg_pinmux_rw_pc_iop___pc3___lsb 3
-#define reg_pinmux_rw_pc_iop___pc3___width 1
-#define reg_pinmux_rw_pc_iop___pc3___bit 3
-#define reg_pinmux_rw_pc_iop___pc4___lsb 4
-#define reg_pinmux_rw_pc_iop___pc4___width 1
-#define reg_pinmux_rw_pc_iop___pc4___bit 4
-#define reg_pinmux_rw_pc_iop___pc5___lsb 5
-#define reg_pinmux_rw_pc_iop___pc5___width 1
-#define reg_pinmux_rw_pc_iop___pc5___bit 5
-#define reg_pinmux_rw_pc_iop___pc6___lsb 6
-#define reg_pinmux_rw_pc_iop___pc6___width 1
-#define reg_pinmux_rw_pc_iop___pc6___bit 6
-#define reg_pinmux_rw_pc_iop___pc7___lsb 7
-#define reg_pinmux_rw_pc_iop___pc7___width 1
-#define reg_pinmux_rw_pc_iop___pc7___bit 7
-#define reg_pinmux_rw_pc_iop___pc8___lsb 8
-#define reg_pinmux_rw_pc_iop___pc8___width 1
-#define reg_pinmux_rw_pc_iop___pc8___bit 8
-#define reg_pinmux_rw_pc_iop___pc9___lsb 9
-#define reg_pinmux_rw_pc_iop___pc9___width 1
-#define reg_pinmux_rw_pc_iop___pc9___bit 9
-#define reg_pinmux_rw_pc_iop___pc10___lsb 10
-#define reg_pinmux_rw_pc_iop___pc10___width 1
-#define reg_pinmux_rw_pc_iop___pc10___bit 10
-#define reg_pinmux_rw_pc_iop___pc11___lsb 11
-#define reg_pinmux_rw_pc_iop___pc11___width 1
-#define reg_pinmux_rw_pc_iop___pc11___bit 11
-#define reg_pinmux_rw_pc_iop___pc12___lsb 12
-#define reg_pinmux_rw_pc_iop___pc12___width 1
-#define reg_pinmux_rw_pc_iop___pc12___bit 12
-#define reg_pinmux_rw_pc_iop___pc13___lsb 13
-#define reg_pinmux_rw_pc_iop___pc13___width 1
-#define reg_pinmux_rw_pc_iop___pc13___bit 13
-#define reg_pinmux_rw_pc_iop___pc14___lsb 14
-#define reg_pinmux_rw_pc_iop___pc14___width 1
-#define reg_pinmux_rw_pc_iop___pc14___bit 14
-#define reg_pinmux_rw_pc_iop___pc15___lsb 15
-#define reg_pinmux_rw_pc_iop___pc15___width 1
-#define reg_pinmux_rw_pc_iop___pc15___bit 15
-#define reg_pinmux_rw_pc_iop___pc16___lsb 16
-#define reg_pinmux_rw_pc_iop___pc16___width 1
-#define reg_pinmux_rw_pc_iop___pc16___bit 16
-#define reg_pinmux_rw_pc_iop___pc17___lsb 17
-#define reg_pinmux_rw_pc_iop___pc17___width 1
-#define reg_pinmux_rw_pc_iop___pc17___bit 17
-#define reg_pinmux_rw_pc_iop_offset 20
-
-/* Register rw_pd_gio, scope pinmux, type rw */
-#define reg_pinmux_rw_pd_gio___pd0___lsb 0
-#define reg_pinmux_rw_pd_gio___pd0___width 1
-#define reg_pinmux_rw_pd_gio___pd0___bit 0
-#define reg_pinmux_rw_pd_gio___pd1___lsb 1
-#define reg_pinmux_rw_pd_gio___pd1___width 1
-#define reg_pinmux_rw_pd_gio___pd1___bit 1
-#define reg_pinmux_rw_pd_gio___pd2___lsb 2
-#define reg_pinmux_rw_pd_gio___pd2___width 1
-#define reg_pinmux_rw_pd_gio___pd2___bit 2
-#define reg_pinmux_rw_pd_gio___pd3___lsb 3
-#define reg_pinmux_rw_pd_gio___pd3___width 1
-#define reg_pinmux_rw_pd_gio___pd3___bit 3
-#define reg_pinmux_rw_pd_gio___pd4___lsb 4
-#define reg_pinmux_rw_pd_gio___pd4___width 1
-#define reg_pinmux_rw_pd_gio___pd4___bit 4
-#define reg_pinmux_rw_pd_gio___pd5___lsb 5
-#define reg_pinmux_rw_pd_gio___pd5___width 1
-#define reg_pinmux_rw_pd_gio___pd5___bit 5
-#define reg_pinmux_rw_pd_gio___pd6___lsb 6
-#define reg_pinmux_rw_pd_gio___pd6___width 1
-#define reg_pinmux_rw_pd_gio___pd6___bit 6
-#define reg_pinmux_rw_pd_gio___pd7___lsb 7
-#define reg_pinmux_rw_pd_gio___pd7___width 1
-#define reg_pinmux_rw_pd_gio___pd7___bit 7
-#define reg_pinmux_rw_pd_gio___pd8___lsb 8
-#define reg_pinmux_rw_pd_gio___pd8___width 1
-#define reg_pinmux_rw_pd_gio___pd8___bit 8
-#define reg_pinmux_rw_pd_gio___pd9___lsb 9
-#define reg_pinmux_rw_pd_gio___pd9___width 1
-#define reg_pinmux_rw_pd_gio___pd9___bit 9
-#define reg_pinmux_rw_pd_gio___pd10___lsb 10
-#define reg_pinmux_rw_pd_gio___pd10___width 1
-#define reg_pinmux_rw_pd_gio___pd10___bit 10
-#define reg_pinmux_rw_pd_gio___pd11___lsb 11
-#define reg_pinmux_rw_pd_gio___pd11___width 1
-#define reg_pinmux_rw_pd_gio___pd11___bit 11
-#define reg_pinmux_rw_pd_gio___pd12___lsb 12
-#define reg_pinmux_rw_pd_gio___pd12___width 1
-#define reg_pinmux_rw_pd_gio___pd12___bit 12
-#define reg_pinmux_rw_pd_gio___pd13___lsb 13
-#define reg_pinmux_rw_pd_gio___pd13___width 1
-#define reg_pinmux_rw_pd_gio___pd13___bit 13
-#define reg_pinmux_rw_pd_gio___pd14___lsb 14
-#define reg_pinmux_rw_pd_gio___pd14___width 1
-#define reg_pinmux_rw_pd_gio___pd14___bit 14
-#define reg_pinmux_rw_pd_gio___pd15___lsb 15
-#define reg_pinmux_rw_pd_gio___pd15___width 1
-#define reg_pinmux_rw_pd_gio___pd15___bit 15
-#define reg_pinmux_rw_pd_gio___pd16___lsb 16
-#define reg_pinmux_rw_pd_gio___pd16___width 1
-#define reg_pinmux_rw_pd_gio___pd16___bit 16
-#define reg_pinmux_rw_pd_gio___pd17___lsb 17
-#define reg_pinmux_rw_pd_gio___pd17___width 1
-#define reg_pinmux_rw_pd_gio___pd17___bit 17
-#define reg_pinmux_rw_pd_gio_offset 24
-
-/* Register rw_pd_iop, scope pinmux, type rw */
-#define reg_pinmux_rw_pd_iop___pd0___lsb 0
-#define reg_pinmux_rw_pd_iop___pd0___width 1
-#define reg_pinmux_rw_pd_iop___pd0___bit 0
-#define reg_pinmux_rw_pd_iop___pd1___lsb 1
-#define reg_pinmux_rw_pd_iop___pd1___width 1
-#define reg_pinmux_rw_pd_iop___pd1___bit 1
-#define reg_pinmux_rw_pd_iop___pd2___lsb 2
-#define reg_pinmux_rw_pd_iop___pd2___width 1
-#define reg_pinmux_rw_pd_iop___pd2___bit 2
-#define reg_pinmux_rw_pd_iop___pd3___lsb 3
-#define reg_pinmux_rw_pd_iop___pd3___width 1
-#define reg_pinmux_rw_pd_iop___pd3___bit 3
-#define reg_pinmux_rw_pd_iop___pd4___lsb 4
-#define reg_pinmux_rw_pd_iop___pd4___width 1
-#define reg_pinmux_rw_pd_iop___pd4___bit 4
-#define reg_pinmux_rw_pd_iop___pd5___lsb 5
-#define reg_pinmux_rw_pd_iop___pd5___width 1
-#define reg_pinmux_rw_pd_iop___pd5___bit 5
-#define reg_pinmux_rw_pd_iop___pd6___lsb 6
-#define reg_pinmux_rw_pd_iop___pd6___width 1
-#define reg_pinmux_rw_pd_iop___pd6___bit 6
-#define reg_pinmux_rw_pd_iop___pd7___lsb 7
-#define reg_pinmux_rw_pd_iop___pd7___width 1
-#define reg_pinmux_rw_pd_iop___pd7___bit 7
-#define reg_pinmux_rw_pd_iop___pd8___lsb 8
-#define reg_pinmux_rw_pd_iop___pd8___width 1
-#define reg_pinmux_rw_pd_iop___pd8___bit 8
-#define reg_pinmux_rw_pd_iop___pd9___lsb 9
-#define reg_pinmux_rw_pd_iop___pd9___width 1
-#define reg_pinmux_rw_pd_iop___pd9___bit 9
-#define reg_pinmux_rw_pd_iop___pd10___lsb 10
-#define reg_pinmux_rw_pd_iop___pd10___width 1
-#define reg_pinmux_rw_pd_iop___pd10___bit 10
-#define reg_pinmux_rw_pd_iop___pd11___lsb 11
-#define reg_pinmux_rw_pd_iop___pd11___width 1
-#define reg_pinmux_rw_pd_iop___pd11___bit 11
-#define reg_pinmux_rw_pd_iop___pd12___lsb 12
-#define reg_pinmux_rw_pd_iop___pd12___width 1
-#define reg_pinmux_rw_pd_iop___pd12___bit 12
-#define reg_pinmux_rw_pd_iop___pd13___lsb 13
-#define reg_pinmux_rw_pd_iop___pd13___width 1
-#define reg_pinmux_rw_pd_iop___pd13___bit 13
-#define reg_pinmux_rw_pd_iop___pd14___lsb 14
-#define reg_pinmux_rw_pd_iop___pd14___width 1
-#define reg_pinmux_rw_pd_iop___pd14___bit 14
-#define reg_pinmux_rw_pd_iop___pd15___lsb 15
-#define reg_pinmux_rw_pd_iop___pd15___width 1
-#define reg_pinmux_rw_pd_iop___pd15___bit 15
-#define reg_pinmux_rw_pd_iop___pd16___lsb 16
-#define reg_pinmux_rw_pd_iop___pd16___width 1
-#define reg_pinmux_rw_pd_iop___pd16___bit 16
-#define reg_pinmux_rw_pd_iop___pd17___lsb 17
-#define reg_pinmux_rw_pd_iop___pd17___width 1
-#define reg_pinmux_rw_pd_iop___pd17___bit 17
-#define reg_pinmux_rw_pd_iop_offset 28
-
-/* Register rw_pe_gio, scope pinmux, type rw */
-#define reg_pinmux_rw_pe_gio___pe0___lsb 0
-#define reg_pinmux_rw_pe_gio___pe0___width 1
-#define reg_pinmux_rw_pe_gio___pe0___bit 0
-#define reg_pinmux_rw_pe_gio___pe1___lsb 1
-#define reg_pinmux_rw_pe_gio___pe1___width 1
-#define reg_pinmux_rw_pe_gio___pe1___bit 1
-#define reg_pinmux_rw_pe_gio___pe2___lsb 2
-#define reg_pinmux_rw_pe_gio___pe2___width 1
-#define reg_pinmux_rw_pe_gio___pe2___bit 2
-#define reg_pinmux_rw_pe_gio___pe3___lsb 3
-#define reg_pinmux_rw_pe_gio___pe3___width 1
-#define reg_pinmux_rw_pe_gio___pe3___bit 3
-#define reg_pinmux_rw_pe_gio___pe4___lsb 4
-#define reg_pinmux_rw_pe_gio___pe4___width 1
-#define reg_pinmux_rw_pe_gio___pe4___bit 4
-#define reg_pinmux_rw_pe_gio___pe5___lsb 5
-#define reg_pinmux_rw_pe_gio___pe5___width 1
-#define reg_pinmux_rw_pe_gio___pe5___bit 5
-#define reg_pinmux_rw_pe_gio___pe6___lsb 6
-#define reg_pinmux_rw_pe_gio___pe6___width 1
-#define reg_pinmux_rw_pe_gio___pe6___bit 6
-#define reg_pinmux_rw_pe_gio___pe7___lsb 7
-#define reg_pinmux_rw_pe_gio___pe7___width 1
-#define reg_pinmux_rw_pe_gio___pe7___bit 7
-#define reg_pinmux_rw_pe_gio___pe8___lsb 8
-#define reg_pinmux_rw_pe_gio___pe8___width 1
-#define reg_pinmux_rw_pe_gio___pe8___bit 8
-#define reg_pinmux_rw_pe_gio___pe9___lsb 9
-#define reg_pinmux_rw_pe_gio___pe9___width 1
-#define reg_pinmux_rw_pe_gio___pe9___bit 9
-#define reg_pinmux_rw_pe_gio___pe10___lsb 10
-#define reg_pinmux_rw_pe_gio___pe10___width 1
-#define reg_pinmux_rw_pe_gio___pe10___bit 10
-#define reg_pinmux_rw_pe_gio___pe11___lsb 11
-#define reg_pinmux_rw_pe_gio___pe11___width 1
-#define reg_pinmux_rw_pe_gio___pe11___bit 11
-#define reg_pinmux_rw_pe_gio___pe12___lsb 12
-#define reg_pinmux_rw_pe_gio___pe12___width 1
-#define reg_pinmux_rw_pe_gio___pe12___bit 12
-#define reg_pinmux_rw_pe_gio___pe13___lsb 13
-#define reg_pinmux_rw_pe_gio___pe13___width 1
-#define reg_pinmux_rw_pe_gio___pe13___bit 13
-#define reg_pinmux_rw_pe_gio___pe14___lsb 14
-#define reg_pinmux_rw_pe_gio___pe14___width 1
-#define reg_pinmux_rw_pe_gio___pe14___bit 14
-#define reg_pinmux_rw_pe_gio___pe15___lsb 15
-#define reg_pinmux_rw_pe_gio___pe15___width 1
-#define reg_pinmux_rw_pe_gio___pe15___bit 15
-#define reg_pinmux_rw_pe_gio___pe16___lsb 16
-#define reg_pinmux_rw_pe_gio___pe16___width 1
-#define reg_pinmux_rw_pe_gio___pe16___bit 16
-#define reg_pinmux_rw_pe_gio___pe17___lsb 17
-#define reg_pinmux_rw_pe_gio___pe17___width 1
-#define reg_pinmux_rw_pe_gio___pe17___bit 17
-#define reg_pinmux_rw_pe_gio_offset 32
-
-/* Register rw_pe_iop, scope pinmux, type rw */
-#define reg_pinmux_rw_pe_iop___pe0___lsb 0
-#define reg_pinmux_rw_pe_iop___pe0___width 1
-#define reg_pinmux_rw_pe_iop___pe0___bit 0
-#define reg_pinmux_rw_pe_iop___pe1___lsb 1
-#define reg_pinmux_rw_pe_iop___pe1___width 1
-#define reg_pinmux_rw_pe_iop___pe1___bit 1
-#define reg_pinmux_rw_pe_iop___pe2___lsb 2
-#define reg_pinmux_rw_pe_iop___pe2___width 1
-#define reg_pinmux_rw_pe_iop___pe2___bit 2
-#define reg_pinmux_rw_pe_iop___pe3___lsb 3
-#define reg_pinmux_rw_pe_iop___pe3___width 1
-#define reg_pinmux_rw_pe_iop___pe3___bit 3
-#define reg_pinmux_rw_pe_iop___pe4___lsb 4
-#define reg_pinmux_rw_pe_iop___pe4___width 1
-#define reg_pinmux_rw_pe_iop___pe4___bit 4
-#define reg_pinmux_rw_pe_iop___pe5___lsb 5
-#define reg_pinmux_rw_pe_iop___pe5___width 1
-#define reg_pinmux_rw_pe_iop___pe5___bit 5
-#define reg_pinmux_rw_pe_iop___pe6___lsb 6
-#define reg_pinmux_rw_pe_iop___pe6___width 1
-#define reg_pinmux_rw_pe_iop___pe6___bit 6
-#define reg_pinmux_rw_pe_iop___pe7___lsb 7
-#define reg_pinmux_rw_pe_iop___pe7___width 1
-#define reg_pinmux_rw_pe_iop___pe7___bit 7
-#define reg_pinmux_rw_pe_iop___pe8___lsb 8
-#define reg_pinmux_rw_pe_iop___pe8___width 1
-#define reg_pinmux_rw_pe_iop___pe8___bit 8
-#define reg_pinmux_rw_pe_iop___pe9___lsb 9
-#define reg_pinmux_rw_pe_iop___pe9___width 1
-#define reg_pinmux_rw_pe_iop___pe9___bit 9
-#define reg_pinmux_rw_pe_iop___pe10___lsb 10
-#define reg_pinmux_rw_pe_iop___pe10___width 1
-#define reg_pinmux_rw_pe_iop___pe10___bit 10
-#define reg_pinmux_rw_pe_iop___pe11___lsb 11
-#define reg_pinmux_rw_pe_iop___pe11___width 1
-#define reg_pinmux_rw_pe_iop___pe11___bit 11
-#define reg_pinmux_rw_pe_iop___pe12___lsb 12
-#define reg_pinmux_rw_pe_iop___pe12___width 1
-#define reg_pinmux_rw_pe_iop___pe12___bit 12
-#define reg_pinmux_rw_pe_iop___pe13___lsb 13
-#define reg_pinmux_rw_pe_iop___pe13___width 1
-#define reg_pinmux_rw_pe_iop___pe13___bit 13
-#define reg_pinmux_rw_pe_iop___pe14___lsb 14
-#define reg_pinmux_rw_pe_iop___pe14___width 1
-#define reg_pinmux_rw_pe_iop___pe14___bit 14
-#define reg_pinmux_rw_pe_iop___pe15___lsb 15
-#define reg_pinmux_rw_pe_iop___pe15___width 1
-#define reg_pinmux_rw_pe_iop___pe15___bit 15
-#define reg_pinmux_rw_pe_iop___pe16___lsb 16
-#define reg_pinmux_rw_pe_iop___pe16___width 1
-#define reg_pinmux_rw_pe_iop___pe16___bit 16
-#define reg_pinmux_rw_pe_iop___pe17___lsb 17
-#define reg_pinmux_rw_pe_iop___pe17___width 1
-#define reg_pinmux_rw_pe_iop___pe17___bit 17
-#define reg_pinmux_rw_pe_iop_offset 36
-
-/* Register rw_usb_phy, scope pinmux, type rw */
-#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0
-#define reg_pinmux_rw_usb_phy___en_usb0___width 1
-#define reg_pinmux_rw_usb_phy___en_usb0___bit 0
-#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1
-#define reg_pinmux_rw_usb_phy___en_usb1___width 1
-#define reg_pinmux_rw_usb_phy___en_usb1___bit 1
-#define reg_pinmux_rw_usb_phy_offset 40
-
-
-/* Constants */
-#define regk_pinmux_no                            0x00000000
-#define regk_pinmux_rw_hwprot_default             0x00000000
-#define regk_pinmux_rw_pa_default                 0x00000000
-#define regk_pinmux_rw_pb_gio_default             0x00000000
-#define regk_pinmux_rw_pb_iop_default             0x00000000
-#define regk_pinmux_rw_pc_gio_default             0x00000000
-#define regk_pinmux_rw_pc_iop_default             0x00000000
-#define regk_pinmux_rw_pd_gio_default             0x00000000
-#define regk_pinmux_rw_pd_iop_default             0x00000000
-#define regk_pinmux_rw_pe_gio_default             0x00000000
-#define regk_pinmux_rw_pe_iop_default             0x00000000
-#define regk_pinmux_rw_usb_phy_default            0x00000000
-#define regk_pinmux_yes                           0x00000001
-#endif /* __pinmux_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h
deleted file mode 100644
index 87517aebd2cb..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h
+++ /dev/null
@@ -1,96 +0,0 @@
-#ifndef __reg_map_h
-#define __reg_map_h
-
-/*
- * This file is autogenerated from
- *   file:            ../../mod/fakereg.rmap
- *     id:            fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp 
- *     last modified: Wed Feb 11 20:53:25 2004
- *   file:            ../../rtl/global.rmap
- *     id:            global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp 
- *     last modified: Mon Aug 18 17:08:23 2003
- *   file:            ../../mod/modreg.rmap
- *     id:            modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp 
- *     last modified: Fri Feb 20 16:40:04 2004
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
- *      id: $Id: reg_map_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ 
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-#define regi_artpec_mod                           0xb7044000
-#define regi_ata                                  0xb0032000
-#define regi_ata_mod                              0xb7006000
-#define regi_barber                               0xb701a000
-#define regi_bif_core                             0xb0014000
-#define regi_bif_dma                              0xb0016000
-#define regi_bif_slave                            0xb0018000
-#define regi_bif_slave_ext                        0xac000000
-#define regi_bus_master                           0xb703c000
-#define regi_config                               0xb003c000
-#define regi_dma0                                 0xb0000000
-#define regi_dma1                                 0xb0002000
-#define regi_dma2                                 0xb0004000
-#define regi_dma3                                 0xb0006000
-#define regi_dma4                                 0xb0008000
-#define regi_dma5                                 0xb000a000
-#define regi_dma6                                 0xb000c000
-#define regi_dma7                                 0xb000e000
-#define regi_dma8                                 0xb0010000
-#define regi_dma9                                 0xb0012000
-#define regi_eth0                                 0xb0034000
-#define regi_eth1                                 0xb0036000
-#define regi_eth_mod                              0xb7004000
-#define regi_eth_mod1                             0xb701c000
-#define regi_eth_strmod                           0xb7008000
-#define regi_eth_strmod1                          0xb7032000
-#define regi_ext_dma                              0xb703a000
-#define regi_ext_mem                              0xb7046000
-#define regi_gen_io                               0xb7016000
-#define regi_gio                                  0xb001a000
-#define regi_hook                                 0xb7000000
-#define regi_iop                                  0xb0020000
-#define regi_irq                                  0xb001c000
-#define regi_irq_nmi                              0xb701e000
-#define regi_marb                                 0xb003e000
-#define regi_marb_bp0                             0xb003e240
-#define regi_marb_bp1                             0xb003e280
-#define regi_marb_bp2                             0xb003e2c0
-#define regi_marb_bp3                             0xb003e300
-#define regi_nand_mod                             0xb7014000
-#define regi_p21                                  0xb002e000
-#define regi_p21_mod                              0xb7042000
-#define regi_pci_mod                              0xb7010000
-#define regi_pin_test                             0xb7018000
-#define regi_pinmux                               0xb0038000
-#define regi_sdram_chk                            0xb703e000
-#define regi_sdram_mod                            0xb7012000
-#define regi_ser0                                 0xb0026000
-#define regi_ser1                                 0xb0028000
-#define regi_ser2                                 0xb002a000
-#define regi_ser3                                 0xb002c000
-#define regi_ser_mod0                             0xb7020000
-#define regi_ser_mod1                             0xb7022000
-#define regi_ser_mod2                             0xb7024000
-#define regi_ser_mod3                             0xb7026000
-#define regi_smif_stat                            0xb700e000
-#define regi_sser0                                0xb0022000
-#define regi_sser1                                0xb0024000
-#define regi_sser_mod0                            0xb700a000
-#define regi_sser_mod1                            0xb700c000
-#define regi_strcop                               0xb0030000
-#define regi_strmux                               0xb003a000
-#define regi_strmux_tst                           0xb7040000
-#define regi_tap                                  0xb7002000
-#define regi_timer                                0xb001e000
-#define regi_timer_mod                            0xb7034000
-#define regi_trace                                0xb0040000
-#define regi_usb0                                 0xb7028000
-#define regi_usb1                                 0xb702a000
-#define regi_usb2                                 0xb702c000
-#define regi_usb3                                 0xb702e000
-#define regi_usb_dev                              0xb7030000
-#define regi_utmi_mod0                            0xb7036000
-#define regi_utmi_mod1                            0xb7038000
-#endif /* __reg_map_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h
deleted file mode 100644
index e1197194d5c1..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h
+++ /dev/null
@@ -1,229 +0,0 @@
-#ifndef __timer_defs_asm_h
-#define __timer_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/timer/rtl/timer_regs.r
- *     id:           timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp 
- *     last modfied: Mon Apr 11 16:09:53 2005
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r
- *      id: $Id: timer_defs_asm.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_tmr0_div, scope timer, type rw */
-#define reg_timer_rw_tmr0_div_offset 0
-
-/* Register r_tmr0_data, scope timer, type r */
-#define reg_timer_r_tmr0_data_offset 4
-
-/* Register rw_tmr0_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr0_ctrl___op___lsb 0
-#define reg_timer_rw_tmr0_ctrl___op___width 2
-#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr0_ctrl___freq___width 3
-#define reg_timer_rw_tmr0_ctrl_offset 8
-
-/* Register rw_tmr1_div, scope timer, type rw */
-#define reg_timer_rw_tmr1_div_offset 16
-
-/* Register r_tmr1_data, scope timer, type r */
-#define reg_timer_r_tmr1_data_offset 20
-
-/* Register rw_tmr1_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr1_ctrl___op___lsb 0
-#define reg_timer_rw_tmr1_ctrl___op___width 2
-#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr1_ctrl___freq___width 3
-#define reg_timer_rw_tmr1_ctrl_offset 24
-
-/* Register rs_cnt_data, scope timer, type rs */
-#define reg_timer_rs_cnt_data___tmr___lsb 0
-#define reg_timer_rs_cnt_data___tmr___width 24
-#define reg_timer_rs_cnt_data___cnt___lsb 24
-#define reg_timer_rs_cnt_data___cnt___width 8
-#define reg_timer_rs_cnt_data_offset 32
-
-/* Register r_cnt_data, scope timer, type r */
-#define reg_timer_r_cnt_data___tmr___lsb 0
-#define reg_timer_r_cnt_data___tmr___width 24
-#define reg_timer_r_cnt_data___cnt___lsb 24
-#define reg_timer_r_cnt_data___cnt___width 8
-#define reg_timer_r_cnt_data_offset 36
-
-/* Register rw_cnt_cfg, scope timer, type rw */
-#define reg_timer_rw_cnt_cfg___clk___lsb 0
-#define reg_timer_rw_cnt_cfg___clk___width 2
-#define reg_timer_rw_cnt_cfg_offset 40
-
-/* Register rw_trig, scope timer, type rw */
-#define reg_timer_rw_trig_offset 48
-
-/* Register rw_trig_cfg, scope timer, type rw */
-#define reg_timer_rw_trig_cfg___tmr___lsb 0
-#define reg_timer_rw_trig_cfg___tmr___width 2
-#define reg_timer_rw_trig_cfg_offset 52
-
-/* Register r_time, scope timer, type r */
-#define reg_timer_r_time_offset 56
-
-/* Register rw_out, scope timer, type rw */
-#define reg_timer_rw_out___tmr___lsb 0
-#define reg_timer_rw_out___tmr___width 2
-#define reg_timer_rw_out_offset 60
-
-/* Register rw_wd_ctrl, scope timer, type rw */
-#define reg_timer_rw_wd_ctrl___cnt___lsb 0
-#define reg_timer_rw_wd_ctrl___cnt___width 8
-#define reg_timer_rw_wd_ctrl___cmd___lsb 8
-#define reg_timer_rw_wd_ctrl___cmd___width 1
-#define reg_timer_rw_wd_ctrl___cmd___bit 8
-#define reg_timer_rw_wd_ctrl___key___lsb 9
-#define reg_timer_rw_wd_ctrl___key___width 7
-#define reg_timer_rw_wd_ctrl_offset 64
-
-/* Register r_wd_stat, scope timer, type r */
-#define reg_timer_r_wd_stat___cnt___lsb 0
-#define reg_timer_r_wd_stat___cnt___width 8
-#define reg_timer_r_wd_stat___cmd___lsb 8
-#define reg_timer_r_wd_stat___cmd___width 1
-#define reg_timer_r_wd_stat___cmd___bit 8
-#define reg_timer_r_wd_stat_offset 68
-
-/* Register rw_intr_mask, scope timer, type rw */
-#define reg_timer_rw_intr_mask___tmr0___lsb 0
-#define reg_timer_rw_intr_mask___tmr0___width 1
-#define reg_timer_rw_intr_mask___tmr0___bit 0
-#define reg_timer_rw_intr_mask___tmr1___lsb 1
-#define reg_timer_rw_intr_mask___tmr1___width 1
-#define reg_timer_rw_intr_mask___tmr1___bit 1
-#define reg_timer_rw_intr_mask___cnt___lsb 2
-#define reg_timer_rw_intr_mask___cnt___width 1
-#define reg_timer_rw_intr_mask___cnt___bit 2
-#define reg_timer_rw_intr_mask___trig___lsb 3
-#define reg_timer_rw_intr_mask___trig___width 1
-#define reg_timer_rw_intr_mask___trig___bit 3
-#define reg_timer_rw_intr_mask_offset 72
-
-/* Register rw_ack_intr, scope timer, type rw */
-#define reg_timer_rw_ack_intr___tmr0___lsb 0
-#define reg_timer_rw_ack_intr___tmr0___width 1
-#define reg_timer_rw_ack_intr___tmr0___bit 0
-#define reg_timer_rw_ack_intr___tmr1___lsb 1
-#define reg_timer_rw_ack_intr___tmr1___width 1
-#define reg_timer_rw_ack_intr___tmr1___bit 1
-#define reg_timer_rw_ack_intr___cnt___lsb 2
-#define reg_timer_rw_ack_intr___cnt___width 1
-#define reg_timer_rw_ack_intr___cnt___bit 2
-#define reg_timer_rw_ack_intr___trig___lsb 3
-#define reg_timer_rw_ack_intr___trig___width 1
-#define reg_timer_rw_ack_intr___trig___bit 3
-#define reg_timer_rw_ack_intr_offset 76
-
-/* Register r_intr, scope timer, type r */
-#define reg_timer_r_intr___tmr0___lsb 0
-#define reg_timer_r_intr___tmr0___width 1
-#define reg_timer_r_intr___tmr0___bit 0
-#define reg_timer_r_intr___tmr1___lsb 1
-#define reg_timer_r_intr___tmr1___width 1
-#define reg_timer_r_intr___tmr1___bit 1
-#define reg_timer_r_intr___cnt___lsb 2
-#define reg_timer_r_intr___cnt___width 1
-#define reg_timer_r_intr___cnt___bit 2
-#define reg_timer_r_intr___trig___lsb 3
-#define reg_timer_r_intr___trig___width 1
-#define reg_timer_r_intr___trig___bit 3
-#define reg_timer_r_intr_offset 80
-
-/* Register r_masked_intr, scope timer, type r */
-#define reg_timer_r_masked_intr___tmr0___lsb 0
-#define reg_timer_r_masked_intr___tmr0___width 1
-#define reg_timer_r_masked_intr___tmr0___bit 0
-#define reg_timer_r_masked_intr___tmr1___lsb 1
-#define reg_timer_r_masked_intr___tmr1___width 1
-#define reg_timer_r_masked_intr___tmr1___bit 1
-#define reg_timer_r_masked_intr___cnt___lsb 2
-#define reg_timer_r_masked_intr___cnt___width 1
-#define reg_timer_r_masked_intr___cnt___bit 2
-#define reg_timer_r_masked_intr___trig___lsb 3
-#define reg_timer_r_masked_intr___trig___width 1
-#define reg_timer_r_masked_intr___trig___bit 3
-#define reg_timer_r_masked_intr_offset 84
-
-/* Register rw_test, scope timer, type rw */
-#define reg_timer_rw_test___dis___lsb 0
-#define reg_timer_rw_test___dis___width 1
-#define reg_timer_rw_test___dis___bit 0
-#define reg_timer_rw_test___en___lsb 1
-#define reg_timer_rw_test___en___width 1
-#define reg_timer_rw_test___en___bit 1
-#define reg_timer_rw_test_offset 88
-
-
-/* Constants */
-#define regk_timer_ext                            0x00000001
-#define regk_timer_f100                           0x00000007
-#define regk_timer_f29_493                        0x00000004
-#define regk_timer_f32                            0x00000005
-#define regk_timer_f32_768                        0x00000006
-#define regk_timer_hold                           0x00000001
-#define regk_timer_ld                             0x00000000
-#define regk_timer_no                             0x00000000
-#define regk_timer_off                            0x00000000
-#define regk_timer_run                            0x00000002
-#define regk_timer_rw_cnt_cfg_default             0x00000000
-#define regk_timer_rw_intr_mask_default           0x00000000
-#define regk_timer_rw_out_default                 0x00000000
-#define regk_timer_rw_test_default                0x00000000
-#define regk_timer_rw_tmr0_ctrl_default           0x00000000
-#define regk_timer_rw_tmr1_ctrl_default           0x00000000
-#define regk_timer_rw_trig_cfg_default            0x00000000
-#define regk_timer_start                          0x00000001
-#define regk_timer_stop                           0x00000000
-#define regk_timer_time                           0x00000001
-#define regk_timer_tmr0                           0x00000002
-#define regk_timer_tmr1                           0x00000003
-#define regk_timer_yes                            0x00000001
-#endif /* __timer_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h
deleted file mode 100644
index 44362a62b47c..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h
+++ /dev/null
@@ -1,284 +0,0 @@
-#ifndef __bif_core_defs_h
-#define __bif_core_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/bif/rtl/bif_core_regs.r
- *     id:           bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp 
- *     last modfied: Mon Apr 11 16:06:33 2005
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
- *      id: $Id: bif_core_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_core */
-
-/* Register rw_grp1_cfg, scope bif_core, type rw */
-typedef struct {
-  unsigned int lw        : 6;
-  unsigned int ew        : 3;
-  unsigned int zw        : 3;
-  unsigned int aw        : 2;
-  unsigned int dw        : 2;
-  unsigned int ewb       : 2;
-  unsigned int bw        : 1;
-  unsigned int wr_extend : 1;
-  unsigned int erc_en    : 1;
-  unsigned int mode      : 1;
-  unsigned int dummy1    : 10;
-} reg_bif_core_rw_grp1_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0
-#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0
-
-/* Register rw_grp2_cfg, scope bif_core, type rw */
-typedef struct {
-  unsigned int lw        : 6;
-  unsigned int ew        : 3;
-  unsigned int zw        : 3;
-  unsigned int aw        : 2;
-  unsigned int dw        : 2;
-  unsigned int ewb       : 2;
-  unsigned int bw        : 1;
-  unsigned int wr_extend : 1;
-  unsigned int erc_en    : 1;
-  unsigned int mode      : 1;
-  unsigned int dummy1    : 10;
-} reg_bif_core_rw_grp2_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4
-#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4
-
-/* Register rw_grp3_cfg, scope bif_core, type rw */
-typedef struct {
-  unsigned int lw         : 6;
-  unsigned int ew         : 3;
-  unsigned int zw         : 3;
-  unsigned int aw         : 2;
-  unsigned int dw         : 2;
-  unsigned int ewb        : 2;
-  unsigned int bw         : 1;
-  unsigned int wr_extend  : 1;
-  unsigned int erc_en     : 1;
-  unsigned int mode       : 1;
-  unsigned int dummy1     : 2;
-  unsigned int gated_csp0 : 2;
-  unsigned int gated_csp1 : 2;
-  unsigned int gated_csp2 : 2;
-  unsigned int gated_csp3 : 2;
-} reg_bif_core_rw_grp3_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8
-#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8
-
-/* Register rw_grp4_cfg, scope bif_core, type rw */
-typedef struct {
-  unsigned int lw         : 6;
-  unsigned int ew         : 3;
-  unsigned int zw         : 3;
-  unsigned int aw         : 2;
-  unsigned int dw         : 2;
-  unsigned int ewb        : 2;
-  unsigned int bw         : 1;
-  unsigned int wr_extend  : 1;
-  unsigned int erc_en     : 1;
-  unsigned int mode       : 1;
-  unsigned int dummy1     : 4;
-  unsigned int gated_csp4 : 2;
-  unsigned int gated_csp5 : 2;
-  unsigned int gated_csp6 : 2;
-} reg_bif_core_rw_grp4_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12
-#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12
-
-/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
-typedef struct {
-  unsigned int bank_sel : 5;
-  unsigned int ca       : 3;
-  unsigned int type     : 1;
-  unsigned int bw       : 1;
-  unsigned int sh       : 3;
-  unsigned int wmm      : 1;
-  unsigned int sh16     : 1;
-  unsigned int grp_sel  : 5;
-  unsigned int dummy1   : 12;
-} reg_bif_core_rw_sdram_cfg_grp0;
-#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16
-#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16
-
-/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
-typedef struct {
-  unsigned int bank_sel : 5;
-  unsigned int ca       : 3;
-  unsigned int type     : 1;
-  unsigned int bw       : 1;
-  unsigned int sh       : 3;
-  unsigned int wmm      : 1;
-  unsigned int sh16     : 1;
-  unsigned int dummy1   : 17;
-} reg_bif_core_rw_sdram_cfg_grp1;
-#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20
-#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20
-
-/* Register rw_sdram_timing, scope bif_core, type rw */
-typedef struct {
-  unsigned int cl    : 3;
-  unsigned int rcd   : 3;
-  unsigned int rp    : 3;
-  unsigned int rc    : 2;
-  unsigned int dpl   : 2;
-  unsigned int pde   : 1;
-  unsigned int ref   : 2;
-  unsigned int cpd   : 1;
-  unsigned int sdcke : 1;
-  unsigned int sdclk : 1;
-  unsigned int dummy1 : 13;
-} reg_bif_core_rw_sdram_timing;
-#define REG_RD_ADDR_bif_core_rw_sdram_timing 24
-#define REG_WR_ADDR_bif_core_rw_sdram_timing 24
-
-/* Register rw_sdram_cmd, scope bif_core, type rw */
-typedef struct {
-  unsigned int cmd      : 3;
-  unsigned int mrs_data : 15;
-  unsigned int dummy1   : 14;
-} reg_bif_core_rw_sdram_cmd;
-#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28
-#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28
-
-/* Register rs_sdram_ref_stat, scope bif_core, type rs */
-typedef struct {
-  unsigned int ok : 1;
-  unsigned int dummy1 : 31;
-} reg_bif_core_rs_sdram_ref_stat;
-#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32
-
-/* Register r_sdram_ref_stat, scope bif_core, type r */
-typedef struct {
-  unsigned int ok : 1;
-  unsigned int dummy1 : 31;
-} reg_bif_core_r_sdram_ref_stat;
-#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36
-
-
-/* Constants */
-enum {
-  regk_bif_core_bank2                      = 0x00000000,
-  regk_bif_core_bank4                      = 0x00000001,
-  regk_bif_core_bit10                      = 0x0000000a,
-  regk_bif_core_bit11                      = 0x0000000b,
-  regk_bif_core_bit12                      = 0x0000000c,
-  regk_bif_core_bit13                      = 0x0000000d,
-  regk_bif_core_bit14                      = 0x0000000e,
-  regk_bif_core_bit15                      = 0x0000000f,
-  regk_bif_core_bit16                      = 0x00000010,
-  regk_bif_core_bit17                      = 0x00000011,
-  regk_bif_core_bit18                      = 0x00000012,
-  regk_bif_core_bit19                      = 0x00000013,
-  regk_bif_core_bit20                      = 0x00000014,
-  regk_bif_core_bit21                      = 0x00000015,
-  regk_bif_core_bit22                      = 0x00000016,
-  regk_bif_core_bit23                      = 0x00000017,
-  regk_bif_core_bit24                      = 0x00000018,
-  regk_bif_core_bit25                      = 0x00000019,
-  regk_bif_core_bit26                      = 0x0000001a,
-  regk_bif_core_bit27                      = 0x0000001b,
-  regk_bif_core_bit28                      = 0x0000001c,
-  regk_bif_core_bit29                      = 0x0000001d,
-  regk_bif_core_bit9                       = 0x00000009,
-  regk_bif_core_bw16                       = 0x00000001,
-  regk_bif_core_bw32                       = 0x00000000,
-  regk_bif_core_bwe                        = 0x00000000,
-  regk_bif_core_cwe                        = 0x00000001,
-  regk_bif_core_e15us                      = 0x00000001,
-  regk_bif_core_e7800ns                    = 0x00000002,
-  regk_bif_core_grp0                       = 0x00000000,
-  regk_bif_core_grp1                       = 0x00000001,
-  regk_bif_core_mrs                        = 0x00000003,
-  regk_bif_core_no                         = 0x00000000,
-  regk_bif_core_none                       = 0x00000000,
-  regk_bif_core_nop                        = 0x00000000,
-  regk_bif_core_off                        = 0x00000000,
-  regk_bif_core_pre                        = 0x00000002,
-  regk_bif_core_r_sdram_ref_stat_default   = 0x00000001,
-  regk_bif_core_rd                         = 0x00000002,
-  regk_bif_core_ref                        = 0x00000001,
-  regk_bif_core_rs_sdram_ref_stat_default  = 0x00000001,
-  regk_bif_core_rw_grp1_cfg_default        = 0x000006cf,
-  regk_bif_core_rw_grp2_cfg_default        = 0x000006cf,
-  regk_bif_core_rw_grp3_cfg_default        = 0x000006cf,
-  regk_bif_core_rw_grp4_cfg_default        = 0x000006cf,
-  regk_bif_core_rw_sdram_cfg_grp1_default  = 0x00000000,
-  regk_bif_core_slf                        = 0x00000004,
-  regk_bif_core_wr                         = 0x00000001,
-  regk_bif_core_yes                        = 0x00000001
-};
-#endif /* __bif_core_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h
deleted file mode 100644
index 3cb51a09dba7..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h
+++ /dev/null
@@ -1,473 +0,0 @@
-#ifndef __bif_dma_defs_h
-#define __bif_dma_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/bif/rtl/bif_dma_regs.r
- *     id:           bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp 
- *     last modfied: Mon Apr 11 16:06:33 2005
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r
- *      id: $Id: bif_dma_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_dma */
-
-/* Register rw_ch0_ctrl, scope bif_dma, type rw */
-typedef struct {
-  unsigned int bw         : 2;
-  unsigned int burst_len  : 1;
-  unsigned int cont       : 1;
-  unsigned int end_pad    : 1;
-  unsigned int cnt        : 1;
-  unsigned int dreq_pin   : 3;
-  unsigned int dreq_mode  : 2;
-  unsigned int tc_in_pin  : 3;
-  unsigned int tc_in_mode : 2;
-  unsigned int bus_mode   : 2;
-  unsigned int rate_en    : 1;
-  unsigned int wr_all     : 1;
-  unsigned int dummy1     : 12;
-} reg_bif_dma_rw_ch0_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0
-#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0
-
-/* Register rw_ch0_addr, scope bif_dma, type rw */
-typedef struct {
-  unsigned int addr : 32;
-} reg_bif_dma_rw_ch0_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4
-#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4
-
-/* Register rw_ch0_start, scope bif_dma, type rw */
-typedef struct {
-  unsigned int run : 1;
-  unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch0_start;
-#define REG_RD_ADDR_bif_dma_rw_ch0_start 8
-#define REG_WR_ADDR_bif_dma_rw_ch0_start 8
-
-/* Register rw_ch0_cnt, scope bif_dma, type rw */
-typedef struct {
-  unsigned int start_cnt : 16;
-  unsigned int dummy1    : 16;
-} reg_bif_dma_rw_ch0_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12
-#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12
-
-/* Register r_ch0_stat, scope bif_dma, type r */
-typedef struct {
-  unsigned int cnt : 16;
-  unsigned int dummy1 : 15;
-  unsigned int run : 1;
-} reg_bif_dma_r_ch0_stat;
-#define REG_RD_ADDR_bif_dma_r_ch0_stat 16
-
-/* Register rw_ch1_ctrl, scope bif_dma, type rw */
-typedef struct {
-  unsigned int bw          : 2;
-  unsigned int burst_len   : 1;
-  unsigned int cont        : 1;
-  unsigned int end_discard : 1;
-  unsigned int cnt         : 1;
-  unsigned int dreq_pin    : 3;
-  unsigned int dreq_mode   : 2;
-  unsigned int tc_in_pin   : 3;
-  unsigned int tc_in_mode  : 2;
-  unsigned int bus_mode    : 2;
-  unsigned int rate_en     : 1;
-  unsigned int dummy1      : 13;
-} reg_bif_dma_rw_ch1_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32
-#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32
-
-/* Register rw_ch1_addr, scope bif_dma, type rw */
-typedef struct {
-  unsigned int addr : 32;
-} reg_bif_dma_rw_ch1_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36
-#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36
-
-/* Register rw_ch1_start, scope bif_dma, type rw */
-typedef struct {
-  unsigned int run : 1;
-  unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch1_start;
-#define REG_RD_ADDR_bif_dma_rw_ch1_start 40
-#define REG_WR_ADDR_bif_dma_rw_ch1_start 40
-
-/* Register rw_ch1_cnt, scope bif_dma, type rw */
-typedef struct {
-  unsigned int start_cnt : 16;
-  unsigned int dummy1    : 16;
-} reg_bif_dma_rw_ch1_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44
-#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44
-
-/* Register r_ch1_stat, scope bif_dma, type r */
-typedef struct {
-  unsigned int cnt : 16;
-  unsigned int dummy1 : 15;
-  unsigned int run : 1;
-} reg_bif_dma_r_ch1_stat;
-#define REG_RD_ADDR_bif_dma_r_ch1_stat 48
-
-/* Register rw_ch2_ctrl, scope bif_dma, type rw */
-typedef struct {
-  unsigned int bw         : 2;
-  unsigned int burst_len  : 1;
-  unsigned int cont       : 1;
-  unsigned int end_pad    : 1;
-  unsigned int cnt        : 1;
-  unsigned int dreq_pin   : 3;
-  unsigned int dreq_mode  : 2;
-  unsigned int tc_in_pin  : 3;
-  unsigned int tc_in_mode : 2;
-  unsigned int bus_mode   : 2;
-  unsigned int rate_en    : 1;
-  unsigned int wr_all     : 1;
-  unsigned int dummy1     : 12;
-} reg_bif_dma_rw_ch2_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64
-#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64
-
-/* Register rw_ch2_addr, scope bif_dma, type rw */
-typedef struct {
-  unsigned int addr : 32;
-} reg_bif_dma_rw_ch2_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68
-#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68
-
-/* Register rw_ch2_start, scope bif_dma, type rw */
-typedef struct {
-  unsigned int run : 1;
-  unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch2_start;
-#define REG_RD_ADDR_bif_dma_rw_ch2_start 72
-#define REG_WR_ADDR_bif_dma_rw_ch2_start 72
-
-/* Register rw_ch2_cnt, scope bif_dma, type rw */
-typedef struct {
-  unsigned int start_cnt : 16;
-  unsigned int dummy1    : 16;
-} reg_bif_dma_rw_ch2_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76
-#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76
-
-/* Register r_ch2_stat, scope bif_dma, type r */
-typedef struct {
-  unsigned int cnt : 16;
-  unsigned int dummy1 : 15;
-  unsigned int run : 1;
-} reg_bif_dma_r_ch2_stat;
-#define REG_RD_ADDR_bif_dma_r_ch2_stat 80
-
-/* Register rw_ch3_ctrl, scope bif_dma, type rw */
-typedef struct {
-  unsigned int bw          : 2;
-  unsigned int burst_len   : 1;
-  unsigned int cont        : 1;
-  unsigned int end_discard : 1;
-  unsigned int cnt         : 1;
-  unsigned int dreq_pin    : 3;
-  unsigned int dreq_mode   : 2;
-  unsigned int tc_in_pin   : 3;
-  unsigned int tc_in_mode  : 2;
-  unsigned int bus_mode    : 2;
-  unsigned int rate_en     : 1;
-  unsigned int dummy1      : 13;
-} reg_bif_dma_rw_ch3_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96
-#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96
-
-/* Register rw_ch3_addr, scope bif_dma, type rw */
-typedef struct {
-  unsigned int addr : 32;
-} reg_bif_dma_rw_ch3_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100
-#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100
-
-/* Register rw_ch3_start, scope bif_dma, type rw */
-typedef struct {
-  unsigned int run : 1;
-  unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch3_start;
-#define REG_RD_ADDR_bif_dma_rw_ch3_start 104
-#define REG_WR_ADDR_bif_dma_rw_ch3_start 104
-
-/* Register rw_ch3_cnt, scope bif_dma, type rw */
-typedef struct {
-  unsigned int start_cnt : 16;
-  unsigned int dummy1    : 16;
-} reg_bif_dma_rw_ch3_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108
-#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108
-
-/* Register r_ch3_stat, scope bif_dma, type r */
-typedef struct {
-  unsigned int cnt : 16;
-  unsigned int dummy1 : 15;
-  unsigned int run : 1;
-} reg_bif_dma_r_ch3_stat;
-#define REG_RD_ADDR_bif_dma_r_ch3_stat 112
-
-/* Register rw_intr_mask, scope bif_dma, type rw */
-typedef struct {
-  unsigned int ext_dma0 : 1;
-  unsigned int ext_dma1 : 1;
-  unsigned int ext_dma2 : 1;
-  unsigned int ext_dma3 : 1;
-  unsigned int dummy1   : 28;
-} reg_bif_dma_rw_intr_mask;
-#define REG_RD_ADDR_bif_dma_rw_intr_mask 128
-#define REG_WR_ADDR_bif_dma_rw_intr_mask 128
-
-/* Register rw_ack_intr, scope bif_dma, type rw */
-typedef struct {
-  unsigned int ext_dma0 : 1;
-  unsigned int ext_dma1 : 1;
-  unsigned int ext_dma2 : 1;
-  unsigned int ext_dma3 : 1;
-  unsigned int dummy1   : 28;
-} reg_bif_dma_rw_ack_intr;
-#define REG_RD_ADDR_bif_dma_rw_ack_intr 132
-#define REG_WR_ADDR_bif_dma_rw_ack_intr 132
-
-/* Register r_intr, scope bif_dma, type r */
-typedef struct {
-  unsigned int ext_dma0 : 1;
-  unsigned int ext_dma1 : 1;
-  unsigned int ext_dma2 : 1;
-  unsigned int ext_dma3 : 1;
-  unsigned int dummy1   : 28;
-} reg_bif_dma_r_intr;
-#define REG_RD_ADDR_bif_dma_r_intr 136
-
-/* Register r_masked_intr, scope bif_dma, type r */
-typedef struct {
-  unsigned int ext_dma0 : 1;
-  unsigned int ext_dma1 : 1;
-  unsigned int ext_dma2 : 1;
-  unsigned int ext_dma3 : 1;
-  unsigned int dummy1   : 28;
-} reg_bif_dma_r_masked_intr;
-#define REG_RD_ADDR_bif_dma_r_masked_intr 140
-
-/* Register rw_pin0_cfg, scope bif_dma, type rw */
-typedef struct {
-  unsigned int master_ch   : 2;
-  unsigned int master_mode : 3;
-  unsigned int slave_ch    : 2;
-  unsigned int slave_mode  : 3;
-  unsigned int dummy1      : 22;
-} reg_bif_dma_rw_pin0_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160
-#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160
-
-/* Register rw_pin1_cfg, scope bif_dma, type rw */
-typedef struct {
-  unsigned int master_ch   : 2;
-  unsigned int master_mode : 3;
-  unsigned int slave_ch    : 2;
-  unsigned int slave_mode  : 3;
-  unsigned int dummy1      : 22;
-} reg_bif_dma_rw_pin1_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164
-#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164
-
-/* Register rw_pin2_cfg, scope bif_dma, type rw */
-typedef struct {
-  unsigned int master_ch   : 2;
-  unsigned int master_mode : 3;
-  unsigned int slave_ch    : 2;
-  unsigned int slave_mode  : 3;
-  unsigned int dummy1      : 22;
-} reg_bif_dma_rw_pin2_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168
-#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168
-
-/* Register rw_pin3_cfg, scope bif_dma, type rw */
-typedef struct {
-  unsigned int master_ch   : 2;
-  unsigned int master_mode : 3;
-  unsigned int slave_ch    : 2;
-  unsigned int slave_mode  : 3;
-  unsigned int dummy1      : 22;
-} reg_bif_dma_rw_pin3_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172
-#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172
-
-/* Register rw_pin4_cfg, scope bif_dma, type rw */
-typedef struct {
-  unsigned int master_ch   : 2;
-  unsigned int master_mode : 3;
-  unsigned int slave_ch    : 2;
-  unsigned int slave_mode  : 3;
-  unsigned int dummy1      : 22;
-} reg_bif_dma_rw_pin4_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176
-#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176
-
-/* Register rw_pin5_cfg, scope bif_dma, type rw */
-typedef struct {
-  unsigned int master_ch   : 2;
-  unsigned int master_mode : 3;
-  unsigned int slave_ch    : 2;
-  unsigned int slave_mode  : 3;
-  unsigned int dummy1      : 22;
-} reg_bif_dma_rw_pin5_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180
-#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180
-
-/* Register rw_pin6_cfg, scope bif_dma, type rw */
-typedef struct {
-  unsigned int master_ch   : 2;
-  unsigned int master_mode : 3;
-  unsigned int slave_ch    : 2;
-  unsigned int slave_mode  : 3;
-  unsigned int dummy1      : 22;
-} reg_bif_dma_rw_pin6_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184
-#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184
-
-/* Register rw_pin7_cfg, scope bif_dma, type rw */
-typedef struct {
-  unsigned int master_ch   : 2;
-  unsigned int master_mode : 3;
-  unsigned int slave_ch    : 2;
-  unsigned int slave_mode  : 3;
-  unsigned int dummy1      : 22;
-} reg_bif_dma_rw_pin7_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188
-#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188
-
-/* Register r_pin_stat, scope bif_dma, type r */
-typedef struct {
-  unsigned int pin0 : 1;
-  unsigned int pin1 : 1;
-  unsigned int pin2 : 1;
-  unsigned int pin3 : 1;
-  unsigned int pin4 : 1;
-  unsigned int pin5 : 1;
-  unsigned int pin6 : 1;
-  unsigned int pin7 : 1;
-  unsigned int dummy1 : 24;
-} reg_bif_dma_r_pin_stat;
-#define REG_RD_ADDR_bif_dma_r_pin_stat 192
-
-
-/* Constants */
-enum {
-  regk_bif_dma_as_master                   = 0x00000001,
-  regk_bif_dma_as_slave                    = 0x00000001,
-  regk_bif_dma_burst1                      = 0x00000000,
-  regk_bif_dma_burst8                      = 0x00000001,
-  regk_bif_dma_bw16                        = 0x00000001,
-  regk_bif_dma_bw32                        = 0x00000002,
-  regk_bif_dma_bw8                         = 0x00000000,
-  regk_bif_dma_dack                        = 0x00000006,
-  regk_bif_dma_dack_inv                    = 0x00000007,
-  regk_bif_dma_force                       = 0x00000001,
-  regk_bif_dma_hi                          = 0x00000003,
-  regk_bif_dma_inv                         = 0x00000003,
-  regk_bif_dma_lo                          = 0x00000002,
-  regk_bif_dma_master                      = 0x00000001,
-  regk_bif_dma_no                          = 0x00000000,
-  regk_bif_dma_norm                        = 0x00000002,
-  regk_bif_dma_off                         = 0x00000000,
-  regk_bif_dma_rw_ch0_ctrl_default         = 0x00000000,
-  regk_bif_dma_rw_ch0_start_default        = 0x00000000,
-  regk_bif_dma_rw_ch1_ctrl_default         = 0x00000000,
-  regk_bif_dma_rw_ch1_start_default        = 0x00000000,
-  regk_bif_dma_rw_ch2_ctrl_default         = 0x00000000,
-  regk_bif_dma_rw_ch2_start_default        = 0x00000000,
-  regk_bif_dma_rw_ch3_ctrl_default         = 0x00000000,
-  regk_bif_dma_rw_ch3_start_default        = 0x00000000,
-  regk_bif_dma_rw_intr_mask_default        = 0x00000000,
-  regk_bif_dma_rw_pin0_cfg_default         = 0x00000000,
-  regk_bif_dma_rw_pin1_cfg_default         = 0x00000000,
-  regk_bif_dma_rw_pin2_cfg_default         = 0x00000000,
-  regk_bif_dma_rw_pin3_cfg_default         = 0x00000000,
-  regk_bif_dma_rw_pin4_cfg_default         = 0x00000000,
-  regk_bif_dma_rw_pin5_cfg_default         = 0x00000000,
-  regk_bif_dma_rw_pin6_cfg_default         = 0x00000000,
-  regk_bif_dma_rw_pin7_cfg_default         = 0x00000000,
-  regk_bif_dma_slave                       = 0x00000002,
-  regk_bif_dma_sreq                        = 0x00000006,
-  regk_bif_dma_sreq_inv                    = 0x00000007,
-  regk_bif_dma_tc                          = 0x00000004,
-  regk_bif_dma_tc_inv                      = 0x00000005,
-  regk_bif_dma_yes                         = 0x00000001
-};
-#endif /* __bif_dma_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h
deleted file mode 100644
index 0c434585a3f9..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h
+++ /dev/null
@@ -1,249 +0,0 @@
-#ifndef __bif_slave_defs_h
-#define __bif_slave_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/bif/rtl/bif_slave_regs.r
- *     id:           bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp 
- *     last modfied: Mon Apr 11 16:06:34 2005
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r
- *      id: $Id: bif_slave_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_slave */
-
-/* Register rw_slave_cfg, scope bif_slave, type rw */
-typedef struct {
-  unsigned int slave_id     : 3;
-  unsigned int use_slave_id : 1;
-  unsigned int boot_rdy     : 1;
-  unsigned int loopback     : 1;
-  unsigned int dis          : 1;
-  unsigned int dummy1       : 25;
-} reg_bif_slave_rw_slave_cfg;
-#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0
-#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0
-
-/* Register r_slave_mode, scope bif_slave, type r */
-typedef struct {
-  unsigned int ch0_mode : 1;
-  unsigned int ch1_mode : 1;
-  unsigned int ch2_mode : 1;
-  unsigned int ch3_mode : 1;
-  unsigned int dummy1   : 28;
-} reg_bif_slave_r_slave_mode;
-#define REG_RD_ADDR_bif_slave_r_slave_mode 4
-
-/* Register rw_ch0_cfg, scope bif_slave, type rw */
-typedef struct {
-  unsigned int rd_hold     : 2;
-  unsigned int access_mode : 1;
-  unsigned int access_ctrl : 1;
-  unsigned int data_cs     : 2;
-  unsigned int dummy1      : 26;
-} reg_bif_slave_rw_ch0_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16
-#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16
-
-/* Register rw_ch1_cfg, scope bif_slave, type rw */
-typedef struct {
-  unsigned int rd_hold     : 2;
-  unsigned int access_mode : 1;
-  unsigned int access_ctrl : 1;
-  unsigned int data_cs     : 2;
-  unsigned int dummy1      : 26;
-} reg_bif_slave_rw_ch1_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20
-#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20
-
-/* Register rw_ch2_cfg, scope bif_slave, type rw */
-typedef struct {
-  unsigned int rd_hold     : 2;
-  unsigned int access_mode : 1;
-  unsigned int access_ctrl : 1;
-  unsigned int data_cs     : 2;
-  unsigned int dummy1      : 26;
-} reg_bif_slave_rw_ch2_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24
-#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24
-
-/* Register rw_ch3_cfg, scope bif_slave, type rw */
-typedef struct {
-  unsigned int rd_hold     : 2;
-  unsigned int access_mode : 1;
-  unsigned int access_ctrl : 1;
-  unsigned int data_cs     : 2;
-  unsigned int dummy1      : 26;
-} reg_bif_slave_rw_ch3_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28
-#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28
-
-/* Register rw_arb_cfg, scope bif_slave, type rw */
-typedef struct {
-  unsigned int brin_mode   : 1;
-  unsigned int brout_mode  : 3;
-  unsigned int bg_mode     : 3;
-  unsigned int release     : 2;
-  unsigned int acquire     : 1;
-  unsigned int settle_time : 2;
-  unsigned int dram_ctrl   : 1;
-  unsigned int dummy1      : 19;
-} reg_bif_slave_rw_arb_cfg;
-#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32
-#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32
-
-/* Register r_arb_stat, scope bif_slave, type r */
-typedef struct {
-  unsigned int init_mode : 1;
-  unsigned int mode      : 1;
-  unsigned int brin      : 1;
-  unsigned int brout     : 1;
-  unsigned int bg        : 1;
-  unsigned int dummy1    : 27;
-} reg_bif_slave_r_arb_stat;
-#define REG_RD_ADDR_bif_slave_r_arb_stat 36
-
-/* Register rw_intr_mask, scope bif_slave, type rw */
-typedef struct {
-  unsigned int bus_release : 1;
-  unsigned int bus_acquire : 1;
-  unsigned int dummy1      : 30;
-} reg_bif_slave_rw_intr_mask;
-#define REG_RD_ADDR_bif_slave_rw_intr_mask 64
-#define REG_WR_ADDR_bif_slave_rw_intr_mask 64
-
-/* Register rw_ack_intr, scope bif_slave, type rw */
-typedef struct {
-  unsigned int bus_release : 1;
-  unsigned int bus_acquire : 1;
-  unsigned int dummy1      : 30;
-} reg_bif_slave_rw_ack_intr;
-#define REG_RD_ADDR_bif_slave_rw_ack_intr 68
-#define REG_WR_ADDR_bif_slave_rw_ack_intr 68
-
-/* Register r_intr, scope bif_slave, type r */
-typedef struct {
-  unsigned int bus_release : 1;
-  unsigned int bus_acquire : 1;
-  unsigned int dummy1      : 30;
-} reg_bif_slave_r_intr;
-#define REG_RD_ADDR_bif_slave_r_intr 72
-
-/* Register r_masked_intr, scope bif_slave, type r */
-typedef struct {
-  unsigned int bus_release : 1;
-  unsigned int bus_acquire : 1;
-  unsigned int dummy1      : 30;
-} reg_bif_slave_r_masked_intr;
-#define REG_RD_ADDR_bif_slave_r_masked_intr 76
-
-
-/* Constants */
-enum {
-  regk_bif_slave_active_hi                 = 0x00000003,
-  regk_bif_slave_active_lo                 = 0x00000002,
-  regk_bif_slave_addr                      = 0x00000000,
-  regk_bif_slave_always                    = 0x00000001,
-  regk_bif_slave_at_idle                   = 0x00000002,
-  regk_bif_slave_burst_end                 = 0x00000003,
-  regk_bif_slave_dma                       = 0x00000001,
-  regk_bif_slave_hi                        = 0x00000003,
-  regk_bif_slave_inv                       = 0x00000001,
-  regk_bif_slave_lo                        = 0x00000002,
-  regk_bif_slave_local                     = 0x00000001,
-  regk_bif_slave_master                    = 0x00000000,
-  regk_bif_slave_mode_reg                  = 0x00000001,
-  regk_bif_slave_no                        = 0x00000000,
-  regk_bif_slave_norm                      = 0x00000000,
-  regk_bif_slave_on_access                 = 0x00000000,
-  regk_bif_slave_rw_arb_cfg_default        = 0x00000000,
-  regk_bif_slave_rw_ch0_cfg_default        = 0x00000000,
-  regk_bif_slave_rw_ch1_cfg_default        = 0x00000000,
-  regk_bif_slave_rw_ch2_cfg_default        = 0x00000000,
-  regk_bif_slave_rw_ch3_cfg_default        = 0x00000000,
-  regk_bif_slave_rw_intr_mask_default      = 0x00000000,
-  regk_bif_slave_rw_slave_cfg_default      = 0x00000000,
-  regk_bif_slave_shared                    = 0x00000000,
-  regk_bif_slave_slave                     = 0x00000001,
-  regk_bif_slave_t0ns                      = 0x00000003,
-  regk_bif_slave_t10ns                     = 0x00000002,
-  regk_bif_slave_t20ns                     = 0x00000003,
-  regk_bif_slave_t30ns                     = 0x00000002,
-  regk_bif_slave_t40ns                     = 0x00000001,
-  regk_bif_slave_t50ns                     = 0x00000000,
-  regk_bif_slave_yes                       = 0x00000001,
-  regk_bif_slave_z                         = 0x00000004
-};
-#endif /* __bif_slave_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h
deleted file mode 100644
index abc5f20705f7..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h
+++ /dev/null
@@ -1,142 +0,0 @@
-#ifndef __config_defs_h
-#define __config_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../rtl/config_regs.r
- *     id:           config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp 
- *     last modfied: Thu Mar  4 12:34:39 2004
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r
- *      id: $Id: config_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope config */
-
-/* Register r_bootsel, scope config, type r */
-typedef struct {
-  unsigned int boot_mode   : 3;
-  unsigned int full_duplex : 1;
-  unsigned int user        : 1;
-  unsigned int pll         : 1;
-  unsigned int flash_bw    : 1;
-  unsigned int dummy1      : 25;
-} reg_config_r_bootsel;
-#define REG_RD_ADDR_config_r_bootsel 0
-
-/* Register rw_clk_ctrl, scope config, type rw */
-typedef struct {
-  unsigned int pll          : 1;
-  unsigned int cpu          : 1;
-  unsigned int iop          : 1;
-  unsigned int dma01_eth0   : 1;
-  unsigned int dma23        : 1;
-  unsigned int dma45        : 1;
-  unsigned int dma67        : 1;
-  unsigned int dma89_strcop : 1;
-  unsigned int bif          : 1;
-  unsigned int fix_io       : 1;
-  unsigned int dummy1       : 22;
-} reg_config_rw_clk_ctrl;
-#define REG_RD_ADDR_config_rw_clk_ctrl 4
-#define REG_WR_ADDR_config_rw_clk_ctrl 4
-
-/* Register rw_pad_ctrl, scope config, type rw */
-typedef struct {
-  unsigned int usb_susp : 1;
-  unsigned int phyrst_n : 1;
-  unsigned int dummy1   : 30;
-} reg_config_rw_pad_ctrl;
-#define REG_RD_ADDR_config_rw_pad_ctrl 8
-#define REG_WR_ADDR_config_rw_pad_ctrl 8
-
-
-/* Constants */
-enum {
-  regk_config_bw16                         = 0x00000000,
-  regk_config_bw32                         = 0x00000001,
-  regk_config_master                       = 0x00000005,
-  regk_config_nand                         = 0x00000003,
-  regk_config_net_rx                       = 0x00000001,
-  regk_config_net_tx_rx                    = 0x00000002,
-  regk_config_no                           = 0x00000000,
-  regk_config_none                         = 0x00000007,
-  regk_config_nor                          = 0x00000000,
-  regk_config_rw_clk_ctrl_default          = 0x00000002,
-  regk_config_rw_pad_ctrl_default          = 0x00000000,
-  regk_config_ser                          = 0x00000004,
-  regk_config_slave                        = 0x00000006,
-  regk_config_yes                          = 0x00000001
-};
-#endif /* __config_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h
deleted file mode 100644
index 26aa3efcf91b..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h
+++ /dev/null
@@ -1,295 +0,0 @@
-#ifndef __gio_defs_h
-#define __gio_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/gio/rtl/gio_regs.r
- *     id:           gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp 
- *     last modfied: Mon Apr 11 16:07:47 2005
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r
- *      id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope gio */
-
-/* Register rw_pa_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pa_dout;
-#define REG_RD_ADDR_gio_rw_pa_dout 0
-#define REG_WR_ADDR_gio_rw_pa_dout 0
-
-/* Register r_pa_din, scope gio, type r */
-typedef struct {
-  unsigned int data : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_r_pa_din;
-#define REG_RD_ADDR_gio_r_pa_din 4
-
-/* Register rw_pa_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 8;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_pa_oe;
-#define REG_RD_ADDR_gio_rw_pa_oe 8
-#define REG_WR_ADDR_gio_rw_pa_oe 8
-
-/* Register rw_intr_cfg, scope gio, type rw */
-typedef struct {
-  unsigned int pa0 : 3;
-  unsigned int pa1 : 3;
-  unsigned int pa2 : 3;
-  unsigned int pa3 : 3;
-  unsigned int pa4 : 3;
-  unsigned int pa5 : 3;
-  unsigned int pa6 : 3;
-  unsigned int pa7 : 3;
-  unsigned int dummy1 : 8;
-} reg_gio_rw_intr_cfg;
-#define REG_RD_ADDR_gio_rw_intr_cfg 12
-#define REG_WR_ADDR_gio_rw_intr_cfg 12
-
-/* Register rw_intr_mask, scope gio, type rw */
-typedef struct {
-  unsigned int pa0 : 1;
-  unsigned int pa1 : 1;
-  unsigned int pa2 : 1;
-  unsigned int pa3 : 1;
-  unsigned int pa4 : 1;
-  unsigned int pa5 : 1;
-  unsigned int pa6 : 1;
-  unsigned int pa7 : 1;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_intr_mask;
-#define REG_RD_ADDR_gio_rw_intr_mask 16
-#define REG_WR_ADDR_gio_rw_intr_mask 16
-
-/* Register rw_ack_intr, scope gio, type rw */
-typedef struct {
-  unsigned int pa0 : 1;
-  unsigned int pa1 : 1;
-  unsigned int pa2 : 1;
-  unsigned int pa3 : 1;
-  unsigned int pa4 : 1;
-  unsigned int pa5 : 1;
-  unsigned int pa6 : 1;
-  unsigned int pa7 : 1;
-  unsigned int dummy1 : 24;
-} reg_gio_rw_ack_intr;
-#define REG_RD_ADDR_gio_rw_ack_intr 20
-#define REG_WR_ADDR_gio_rw_ack_intr 20
-
-/* Register r_intr, scope gio, type r */
-typedef struct {
-  unsigned int pa0 : 1;
-  unsigned int pa1 : 1;
-  unsigned int pa2 : 1;
-  unsigned int pa3 : 1;
-  unsigned int pa4 : 1;
-  unsigned int pa5 : 1;
-  unsigned int pa6 : 1;
-  unsigned int pa7 : 1;
-  unsigned int dummy1 : 24;
-} reg_gio_r_intr;
-#define REG_RD_ADDR_gio_r_intr 24
-
-/* Register r_masked_intr, scope gio, type r */
-typedef struct {
-  unsigned int pa0 : 1;
-  unsigned int pa1 : 1;
-  unsigned int pa2 : 1;
-  unsigned int pa3 : 1;
-  unsigned int pa4 : 1;
-  unsigned int pa5 : 1;
-  unsigned int pa6 : 1;
-  unsigned int pa7 : 1;
-  unsigned int dummy1 : 24;
-} reg_gio_r_masked_intr;
-#define REG_RD_ADDR_gio_r_masked_intr 28
-
-/* Register rw_pb_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_rw_pb_dout;
-#define REG_RD_ADDR_gio_rw_pb_dout 32
-#define REG_WR_ADDR_gio_rw_pb_dout 32
-
-/* Register r_pb_din, scope gio, type r */
-typedef struct {
-  unsigned int data : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_r_pb_din;
-#define REG_RD_ADDR_gio_r_pb_din 36
-
-/* Register rw_pb_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_rw_pb_oe;
-#define REG_RD_ADDR_gio_rw_pb_oe 40
-#define REG_WR_ADDR_gio_rw_pb_oe 40
-
-/* Register rw_pc_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_rw_pc_dout;
-#define REG_RD_ADDR_gio_rw_pc_dout 48
-#define REG_WR_ADDR_gio_rw_pc_dout 48
-
-/* Register r_pc_din, scope gio, type r */
-typedef struct {
-  unsigned int data : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_r_pc_din;
-#define REG_RD_ADDR_gio_r_pc_din 52
-
-/* Register rw_pc_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_rw_pc_oe;
-#define REG_RD_ADDR_gio_rw_pc_oe 56
-#define REG_WR_ADDR_gio_rw_pc_oe 56
-
-/* Register rw_pd_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_rw_pd_dout;
-#define REG_RD_ADDR_gio_rw_pd_dout 64
-#define REG_WR_ADDR_gio_rw_pd_dout 64
-
-/* Register r_pd_din, scope gio, type r */
-typedef struct {
-  unsigned int data : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_r_pd_din;
-#define REG_RD_ADDR_gio_r_pd_din 68
-
-/* Register rw_pd_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_rw_pd_oe;
-#define REG_RD_ADDR_gio_rw_pd_oe 72
-#define REG_WR_ADDR_gio_rw_pd_oe 72
-
-/* Register rw_pe_dout, scope gio, type rw */
-typedef struct {
-  unsigned int data : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_rw_pe_dout;
-#define REG_RD_ADDR_gio_rw_pe_dout 80
-#define REG_WR_ADDR_gio_rw_pe_dout 80
-
-/* Register r_pe_din, scope gio, type r */
-typedef struct {
-  unsigned int data : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_r_pe_din;
-#define REG_RD_ADDR_gio_r_pe_din 84
-
-/* Register rw_pe_oe, scope gio, type rw */
-typedef struct {
-  unsigned int oe : 18;
-  unsigned int dummy1 : 14;
-} reg_gio_rw_pe_oe;
-#define REG_RD_ADDR_gio_rw_pe_oe 88
-#define REG_WR_ADDR_gio_rw_pe_oe 88
-
-
-/* Constants */
-enum {
-  regk_gio_anyedge                         = 0x00000007,
-  regk_gio_hi                              = 0x00000001,
-  regk_gio_lo                              = 0x00000002,
-  regk_gio_negedge                         = 0x00000006,
-  regk_gio_no                              = 0x00000000,
-  regk_gio_off                             = 0x00000000,
-  regk_gio_posedge                         = 0x00000005,
-  regk_gio_rw_intr_cfg_default             = 0x00000000,
-  regk_gio_rw_intr_mask_default            = 0x00000000,
-  regk_gio_rw_pa_oe_default                = 0x00000000,
-  regk_gio_rw_pb_oe_default                = 0x00000000,
-  regk_gio_rw_pc_oe_default                = 0x00000000,
-  regk_gio_rw_pd_oe_default                = 0x00000000,
-  regk_gio_rw_pe_oe_default                = 0x00000000,
-  regk_gio_set                             = 0x00000003,
-  regk_gio_yes                             = 0x00000001
-};
-#endif /* __gio_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h
deleted file mode 100644
index bacc2a895c21..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
- from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
-version . */
-
-#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
-#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R 
-#define MEMARB_INTR_VECT	0x31
-#define GEN_IO_INTR_VECT	0x32
-#define GIO_INTR_VECT           GEN_IO_INTR_VECT
-#define IOP0_INTR_VECT	0x33
-#define IOP1_INTR_VECT	0x34
-#define IOP2_INTR_VECT	0x35
-#define IOP3_INTR_VECT	0x36
-#define DMA0_INTR_VECT	0x37
-#define DMA1_INTR_VECT	0x38
-#define DMA2_INTR_VECT	0x39
-#define DMA3_INTR_VECT	0x3a
-#define DMA4_INTR_VECT	0x3b
-#define DMA5_INTR_VECT	0x3c
-#define DMA6_INTR_VECT	0x3d
-#define DMA7_INTR_VECT	0x3e
-#define DMA8_INTR_VECT	0x3f
-#define DMA9_INTR_VECT	0x40
-#define ATA_INTR_VECT	0x41
-#define SSER0_INTR_VECT	0x42
-#define SSER1_INTR_VECT	0x43
-#define SER0_INTR_VECT	0x44
-#define SER1_INTR_VECT	0x45
-#define SER2_INTR_VECT	0x46
-#define SER3_INTR_VECT	0x47
-#define P21_INTR_VECT	0x48
-#define ETH0_INTR_VECT	0x49
-#define ETH1_INTR_VECT	0x4a
-#define TIMER_INTR_VECT	0x4b
-#define TIMER0_INTR_VECT	TIMER_INTR_VECT
-#define BIF_ARB_INTR_VECT	0x4c
-#define BIF_DMA_INTR_VECT	0x4d
-#define EXT_INTR_VECT	0x4e
-#define IPI_INTR_VECT	0x4f
-#define NBR_INTR_VECT   0x50
-#endif
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h
deleted file mode 100644
index aa65128ae1aa..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h
+++ /dev/null
@@ -1,228 +0,0 @@
-#ifndef __intr_vect_defs_h
-#define __intr_vect_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/intr_vect/rtl/guinness/ivmask.config.r
- *     id:           ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp 
- *     last modfied: Mon Apr 11 16:08:03 2005
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
- *      id: $Id: intr_vect_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope intr_vect */
-
-#define STRIDE_intr_vect_rw_mask 0
-/* Register rw_mask, scope intr_vect, type rw */
-typedef struct {
-  unsigned int memarb  : 1;
-  unsigned int gen_io  : 1;
-  unsigned int iop0    : 1;
-  unsigned int iop1    : 1;
-  unsigned int iop2    : 1;
-  unsigned int iop3    : 1;
-  unsigned int dma0    : 1;
-  unsigned int dma1    : 1;
-  unsigned int dma2    : 1;
-  unsigned int dma3    : 1;
-  unsigned int dma4    : 1;
-  unsigned int dma5    : 1;
-  unsigned int dma6    : 1;
-  unsigned int dma7    : 1;
-  unsigned int dma8    : 1;
-  unsigned int dma9    : 1;
-  unsigned int ata     : 1;
-  unsigned int sser0   : 1;
-  unsigned int sser1   : 1;
-  unsigned int ser0    : 1;
-  unsigned int ser1    : 1;
-  unsigned int ser2    : 1;
-  unsigned int ser3    : 1;
-  unsigned int p21     : 1;
-  unsigned int eth0    : 1;
-  unsigned int eth1    : 1;
-  unsigned int timer0  : 1;
-  unsigned int bif_arb : 1;
-  unsigned int bif_dma : 1;
-  unsigned int ext     : 1;
-  unsigned int dummy1  : 2;
-} reg_intr_vect_rw_mask;
-#define REG_RD_ADDR_intr_vect_rw_mask 0
-#define REG_WR_ADDR_intr_vect_rw_mask 0
-
-#define STRIDE_intr_vect_r_vect 0
-/* Register r_vect, scope intr_vect, type r */
-typedef struct {
-  unsigned int memarb  : 1;
-  unsigned int gen_io  : 1;
-  unsigned int iop0    : 1;
-  unsigned int iop1    : 1;
-  unsigned int iop2    : 1;
-  unsigned int iop3    : 1;
-  unsigned int dma0    : 1;
-  unsigned int dma1    : 1;
-  unsigned int dma2    : 1;
-  unsigned int dma3    : 1;
-  unsigned int dma4    : 1;
-  unsigned int dma5    : 1;
-  unsigned int dma6    : 1;
-  unsigned int dma7    : 1;
-  unsigned int dma8    : 1;
-  unsigned int dma9    : 1;
-  unsigned int ata     : 1;
-  unsigned int sser0   : 1;
-  unsigned int sser1   : 1;
-  unsigned int ser0    : 1;
-  unsigned int ser1    : 1;
-  unsigned int ser2    : 1;
-  unsigned int ser3    : 1;
-  unsigned int p21     : 1;
-  unsigned int eth0    : 1;
-  unsigned int eth1    : 1;
-  unsigned int timer   : 1;
-  unsigned int bif_arb : 1;
-  unsigned int bif_dma : 1;
-  unsigned int ext     : 1;
-  unsigned int dummy1  : 2;
-} reg_intr_vect_r_vect;
-#define REG_RD_ADDR_intr_vect_r_vect 4
-
-#define STRIDE_intr_vect_r_masked_vect 0
-/* Register r_masked_vect, scope intr_vect, type r */
-typedef struct {
-  unsigned int memarb  : 1;
-  unsigned int gen_io  : 1;
-  unsigned int iop0    : 1;
-  unsigned int iop1    : 1;
-  unsigned int iop2    : 1;
-  unsigned int iop3    : 1;
-  unsigned int dma0    : 1;
-  unsigned int dma1    : 1;
-  unsigned int dma2    : 1;
-  unsigned int dma3    : 1;
-  unsigned int dma4    : 1;
-  unsigned int dma5    : 1;
-  unsigned int dma6    : 1;
-  unsigned int dma7    : 1;
-  unsigned int dma8    : 1;
-  unsigned int dma9    : 1;
-  unsigned int ata     : 1;
-  unsigned int sser0   : 1;
-  unsigned int sser1   : 1;
-  unsigned int ser0    : 1;
-  unsigned int ser1    : 1;
-  unsigned int ser2    : 1;
-  unsigned int ser3    : 1;
-  unsigned int p21     : 1;
-  unsigned int eth0    : 1;
-  unsigned int eth1    : 1;
-  unsigned int timer   : 1;
-  unsigned int bif_arb : 1;
-  unsigned int bif_dma : 1;
-  unsigned int ext     : 1;
-  unsigned int dummy1  : 2;
-} reg_intr_vect_r_masked_vect;
-#define REG_RD_ADDR_intr_vect_r_masked_vect 8
-
-/* Register r_nmi, scope intr_vect, type r */
-typedef struct {
-  unsigned int ext      : 1;
-  unsigned int watchdog : 1;
-  unsigned int dummy1   : 30;
-} reg_intr_vect_r_nmi;
-#define REG_RD_ADDR_intr_vect_r_nmi 12
-
-/* Register r_guru, scope intr_vect, type r */
-typedef struct {
-  unsigned int jtag : 1;
-  unsigned int dummy1 : 31;
-} reg_intr_vect_r_guru;
-#define REG_RD_ADDR_intr_vect_r_guru 16
-
-/* Register rw_ipi, scope intr_vect, type rw */
-typedef struct 
-{
-  unsigned int vector;
-} reg_intr_vect_rw_ipi;
-#define REG_RD_ADDR_intr_vect_rw_ipi 20
-#define REG_WR_ADDR_intr_vect_rw_ipi 20
-
-/* Constants */
-enum {
-  regk_intr_vect_off                       = 0x00000000,
-  regk_intr_vect_on                        = 0x00000001,
-  regk_intr_vect_rw_mask_default           = 0x00000000
-};
-#endif /* __intr_vect_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h
deleted file mode 100644
index dcaaec4620ba..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h
+++ /dev/null
@@ -1,205 +0,0 @@
-#ifndef __marb_bp_defs_h
-#define __marb_bp_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
- *     id:           <not found>
- *     last modfied: Fri Nov  7 15:36:04 2003
- * 
- *   by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r
- *      id: $Id: marb_bp_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-/* C-code for register scope marb_bp */
-
-/* Register rw_first_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_bp, type rw */
-typedef struct {
-  unsigned int read         : 1;
-  unsigned int write        : 1;
-  unsigned int read_excl    : 1;
-  unsigned int pri_write    : 1;
-  unsigned int us_read      : 1;
-  unsigned int us_write     : 1;
-  unsigned int us_read_excl : 1;
-  unsigned int us_pri_write : 1;
-  unsigned int dummy1       : 24;
-} reg_marb_bp_rw_op;
-#define REG_RD_ADDR_marb_bp_rw_op 8
-#define REG_WR_ADDR_marb_bp_rw_op 8
-
-/* Register rw_clients, scope marb_bp, type rw */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_bp_rw_clients;
-#define REG_RD_ADDR_marb_bp_rw_clients 12
-#define REG_WR_ADDR_marb_bp_rw_clients 12
-
-/* Register rw_options, scope marb_bp, type rw */
-typedef struct {
-  unsigned int wrap : 1;
-  unsigned int dummy1 : 31;
-} reg_marb_bp_rw_options;
-#define REG_RD_ADDR_marb_bp_rw_options 16
-#define REG_WR_ADDR_marb_bp_rw_options 16
-
-/* Register r_break_addr, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_break_addr;
-#define REG_RD_ADDR_marb_bp_r_break_addr 20
-
-/* Register r_break_op, scope marb_bp, type r */
-typedef struct {
-  unsigned int read         : 1;
-  unsigned int write        : 1;
-  unsigned int read_excl    : 1;
-  unsigned int pri_write    : 1;
-  unsigned int us_read      : 1;
-  unsigned int us_write     : 1;
-  unsigned int us_read_excl : 1;
-  unsigned int us_pri_write : 1;
-  unsigned int dummy1       : 24;
-} reg_marb_bp_r_break_op;
-#define REG_RD_ADDR_marb_bp_r_break_op 24
-
-/* Register r_break_clients, scope marb_bp, type r */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_bp_r_break_clients;
-#define REG_RD_ADDR_marb_bp_r_break_clients 28
-
-/* Register r_break_first_client, scope marb_bp, type r */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_bp_r_break_first_client;
-#define REG_RD_ADDR_marb_bp_r_break_first_client 32
-
-/* Register r_break_size, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_break_size;
-#define REG_RD_ADDR_marb_bp_r_break_size 36
-
-/* Register rw_ack, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_ack;
-#define REG_RD_ADDR_marb_bp_rw_ack 40
-#define REG_WR_ADDR_marb_bp_rw_ack 40
-
-
-/* Constants */
-enum {
-  regk_marb_bp_no                          = 0x00000000,
-  regk_marb_bp_rw_op_default               = 0x00000000,
-  regk_marb_bp_rw_options_default          = 0x00000000,
-  regk_marb_bp_yes                         = 0x00000001
-};
-#endif /* __marb_bp_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h
deleted file mode 100644
index 254da0854986..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h
+++ /dev/null
@@ -1,475 +0,0 @@
-#ifndef __marb_defs_h
-#define __marb_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:12:16 2005
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
- *      id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb */
-
-#define STRIDE_marb_rw_int_slots 4
-/* Register rw_int_slots, scope marb, type rw */
-typedef struct {
-  unsigned int owner : 4;
-  unsigned int dummy1 : 28;
-} reg_marb_rw_int_slots;
-#define REG_RD_ADDR_marb_rw_int_slots 0
-#define REG_WR_ADDR_marb_rw_int_slots 0
-
-#define STRIDE_marb_rw_ext_slots 4
-/* Register rw_ext_slots, scope marb, type rw */
-typedef struct {
-  unsigned int owner : 4;
-  unsigned int dummy1 : 28;
-} reg_marb_rw_ext_slots;
-#define REG_RD_ADDR_marb_rw_ext_slots 256
-#define REG_WR_ADDR_marb_rw_ext_slots 256
-
-#define STRIDE_marb_rw_regs_slots 4
-/* Register rw_regs_slots, scope marb, type rw */
-typedef struct {
-  unsigned int owner : 4;
-  unsigned int dummy1 : 28;
-} reg_marb_rw_regs_slots;
-#define REG_RD_ADDR_marb_rw_regs_slots 512
-#define REG_WR_ADDR_marb_rw_regs_slots 512
-
-/* Register rw_intr_mask, scope marb, type rw */
-typedef struct {
-  unsigned int bp0 : 1;
-  unsigned int bp1 : 1;
-  unsigned int bp2 : 1;
-  unsigned int bp3 : 1;
-  unsigned int dummy1 : 28;
-} reg_marb_rw_intr_mask;
-#define REG_RD_ADDR_marb_rw_intr_mask 528
-#define REG_WR_ADDR_marb_rw_intr_mask 528
-
-/* Register rw_ack_intr, scope marb, type rw */
-typedef struct {
-  unsigned int bp0 : 1;
-  unsigned int bp1 : 1;
-  unsigned int bp2 : 1;
-  unsigned int bp3 : 1;
-  unsigned int dummy1 : 28;
-} reg_marb_rw_ack_intr;
-#define REG_RD_ADDR_marb_rw_ack_intr 532
-#define REG_WR_ADDR_marb_rw_ack_intr 532
-
-/* Register r_intr, scope marb, type r */
-typedef struct {
-  unsigned int bp0 : 1;
-  unsigned int bp1 : 1;
-  unsigned int bp2 : 1;
-  unsigned int bp3 : 1;
-  unsigned int dummy1 : 28;
-} reg_marb_r_intr;
-#define REG_RD_ADDR_marb_r_intr 536
-
-/* Register r_masked_intr, scope marb, type r */
-typedef struct {
-  unsigned int bp0 : 1;
-  unsigned int bp1 : 1;
-  unsigned int bp2 : 1;
-  unsigned int bp3 : 1;
-  unsigned int dummy1 : 28;
-} reg_marb_r_masked_intr;
-#define REG_RD_ADDR_marb_r_masked_intr 540
-
-/* Register rw_stop_mask, scope marb, type rw */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_rw_stop_mask;
-#define REG_RD_ADDR_marb_rw_stop_mask 544
-#define REG_WR_ADDR_marb_rw_stop_mask 544
-
-/* Register r_stopped, scope marb, type r */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_r_stopped;
-#define REG_RD_ADDR_marb_r_stopped 548
-
-/* Register rw_no_snoop, scope marb, type rw */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_rw_no_snoop;
-#define REG_RD_ADDR_marb_rw_no_snoop 832
-#define REG_WR_ADDR_marb_rw_no_snoop 832
-
-/* Register rw_no_snoop_rq, scope marb, type rw */
-typedef struct {
-  unsigned int dummy1 : 10;
-  unsigned int cpui : 1;
-  unsigned int cpud : 1;
-  unsigned int dummy2 : 20;
-} reg_marb_rw_no_snoop_rq;
-#define REG_RD_ADDR_marb_rw_no_snoop_rq 836
-#define REG_WR_ADDR_marb_rw_no_snoop_rq 836
-
-
-/* Constants */
-enum {
-  regk_marb_cpud                           = 0x0000000b,
-  regk_marb_cpui                           = 0x0000000a,
-  regk_marb_dma0                           = 0x00000000,
-  regk_marb_dma1                           = 0x00000001,
-  regk_marb_dma2                           = 0x00000002,
-  regk_marb_dma3                           = 0x00000003,
-  regk_marb_dma4                           = 0x00000004,
-  regk_marb_dma5                           = 0x00000005,
-  regk_marb_dma6                           = 0x00000006,
-  regk_marb_dma7                           = 0x00000007,
-  regk_marb_dma8                           = 0x00000008,
-  regk_marb_dma9                           = 0x00000009,
-  regk_marb_iop                            = 0x0000000c,
-  regk_marb_no                             = 0x00000000,
-  regk_marb_r_stopped_default              = 0x00000000,
-  regk_marb_rw_ext_slots_default           = 0x00000000,
-  regk_marb_rw_ext_slots_size              = 0x00000040,
-  regk_marb_rw_int_slots_default           = 0x00000000,
-  regk_marb_rw_int_slots_size              = 0x00000040,
-  regk_marb_rw_intr_mask_default           = 0x00000000,
-  regk_marb_rw_no_snoop_default            = 0x00000000,
-  regk_marb_rw_no_snoop_rq_default         = 0x00000000,
-  regk_marb_rw_regs_slots_default          = 0x00000000,
-  regk_marb_rw_regs_slots_size             = 0x00000004,
-  regk_marb_rw_stop_mask_default           = 0x00000000,
-  regk_marb_slave                          = 0x0000000d,
-  regk_marb_yes                            = 0x00000001
-};
-#endif /* __marb_defs_h */
-#ifndef __marb_bp_defs_h
-#define __marb_bp_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:12:16 2005
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
- *      id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_bp */
-
-/* Register rw_first_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_bp, type rw */
-typedef struct {
-  unsigned int rd         : 1;
-  unsigned int wr         : 1;
-  unsigned int rd_excl    : 1;
-  unsigned int pri_wr     : 1;
-  unsigned int us_rd      : 1;
-  unsigned int us_wr      : 1;
-  unsigned int us_rd_excl : 1;
-  unsigned int us_pri_wr  : 1;
-  unsigned int dummy1     : 24;
-} reg_marb_bp_rw_op;
-#define REG_RD_ADDR_marb_bp_rw_op 8
-#define REG_WR_ADDR_marb_bp_rw_op 8
-
-/* Register rw_clients, scope marb_bp, type rw */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_bp_rw_clients;
-#define REG_RD_ADDR_marb_bp_rw_clients 12
-#define REG_WR_ADDR_marb_bp_rw_clients 12
-
-/* Register rw_options, scope marb_bp, type rw */
-typedef struct {
-  unsigned int wrap : 1;
-  unsigned int dummy1 : 31;
-} reg_marb_bp_rw_options;
-#define REG_RD_ADDR_marb_bp_rw_options 16
-#define REG_WR_ADDR_marb_bp_rw_options 16
-
-/* Register r_brk_addr, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_brk_addr;
-#define REG_RD_ADDR_marb_bp_r_brk_addr 20
-
-/* Register r_brk_op, scope marb_bp, type r */
-typedef struct {
-  unsigned int rd         : 1;
-  unsigned int wr         : 1;
-  unsigned int rd_excl    : 1;
-  unsigned int pri_wr     : 1;
-  unsigned int us_rd      : 1;
-  unsigned int us_wr      : 1;
-  unsigned int us_rd_excl : 1;
-  unsigned int us_pri_wr  : 1;
-  unsigned int dummy1     : 24;
-} reg_marb_bp_r_brk_op;
-#define REG_RD_ADDR_marb_bp_r_brk_op 24
-
-/* Register r_brk_clients, scope marb_bp, type r */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_bp_r_brk_clients;
-#define REG_RD_ADDR_marb_bp_r_brk_clients 28
-
-/* Register r_brk_first_client, scope marb_bp, type r */
-typedef struct {
-  unsigned int dma0  : 1;
-  unsigned int dma1  : 1;
-  unsigned int dma2  : 1;
-  unsigned int dma3  : 1;
-  unsigned int dma4  : 1;
-  unsigned int dma5  : 1;
-  unsigned int dma6  : 1;
-  unsigned int dma7  : 1;
-  unsigned int dma8  : 1;
-  unsigned int dma9  : 1;
-  unsigned int cpui  : 1;
-  unsigned int cpud  : 1;
-  unsigned int iop   : 1;
-  unsigned int slave : 1;
-  unsigned int dummy1 : 18;
-} reg_marb_bp_r_brk_first_client;
-#define REG_RD_ADDR_marb_bp_r_brk_first_client 32
-
-/* Register r_brk_size, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_brk_size;
-#define REG_RD_ADDR_marb_bp_r_brk_size 36
-
-/* Register rw_ack, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_ack;
-#define REG_RD_ADDR_marb_bp_rw_ack 40
-#define REG_WR_ADDR_marb_bp_rw_ack 40
-
-
-/* Constants */
-enum {
-  regk_marb_bp_no                          = 0x00000000,
-  regk_marb_bp_rw_op_default               = 0x00000000,
-  regk_marb_bp_rw_options_default          = 0x00000000,
-  regk_marb_bp_yes                         = 0x00000001
-};
-#endif /* __marb_bp_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h
deleted file mode 100644
index 751eab5f191c..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h
+++ /dev/null
@@ -1,357 +0,0 @@
-#ifndef __pinmux_defs_h
-#define __pinmux_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/pinmux/rtl/guinness/pinmux_regs.r
- *     id:           pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp 
- *     last modfied: Mon Apr 11 16:09:11 2005
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
- *      id: $Id: pinmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope pinmux */
-
-/* Register rw_pa, scope pinmux, type rw */
-typedef struct {
-  unsigned int pa0    : 1;
-  unsigned int pa1    : 1;
-  unsigned int pa2    : 1;
-  unsigned int pa3    : 1;
-  unsigned int pa4    : 1;
-  unsigned int pa5    : 1;
-  unsigned int pa6    : 1;
-  unsigned int pa7    : 1;
-  unsigned int csp2_n : 1;
-  unsigned int csp3_n : 1;
-  unsigned int csp5_n : 1;
-  unsigned int csp6_n : 1;
-  unsigned int hsh4   : 1;
-  unsigned int hsh5   : 1;
-  unsigned int hsh6   : 1;
-  unsigned int hsh7   : 1;
-  unsigned int dummy1 : 16;
-} reg_pinmux_rw_pa;
-#define REG_RD_ADDR_pinmux_rw_pa 0
-#define REG_WR_ADDR_pinmux_rw_pa 0
-
-/* Register rw_hwprot, scope pinmux, type rw */
-typedef struct {
-  unsigned int ser1     : 1;
-  unsigned int ser2     : 1;
-  unsigned int ser3     : 1;
-  unsigned int sser0    : 1;
-  unsigned int sser1    : 1;
-  unsigned int ata0     : 1;
-  unsigned int ata1     : 1;
-  unsigned int ata2     : 1;
-  unsigned int ata3     : 1;
-  unsigned int ata      : 1;
-  unsigned int eth1     : 1;
-  unsigned int eth1_mgm : 1;
-  unsigned int timer    : 1;
-  unsigned int p21      : 1;
-  unsigned int dummy1   : 18;
-} reg_pinmux_rw_hwprot;
-#define REG_RD_ADDR_pinmux_rw_hwprot 4
-#define REG_WR_ADDR_pinmux_rw_hwprot 4
-
-/* Register rw_pb_gio, scope pinmux, type rw */
-typedef struct {
-  unsigned int pb0  : 1;
-  unsigned int pb1  : 1;
-  unsigned int pb2  : 1;
-  unsigned int pb3  : 1;
-  unsigned int pb4  : 1;
-  unsigned int pb5  : 1;
-  unsigned int pb6  : 1;
-  unsigned int pb7  : 1;
-  unsigned int pb8  : 1;
-  unsigned int pb9  : 1;
-  unsigned int pb10 : 1;
-  unsigned int pb11 : 1;
-  unsigned int pb12 : 1;
-  unsigned int pb13 : 1;
-  unsigned int pb14 : 1;
-  unsigned int pb15 : 1;
-  unsigned int pb16 : 1;
-  unsigned int pb17 : 1;
-  unsigned int dummy1 : 14;
-} reg_pinmux_rw_pb_gio;
-#define REG_RD_ADDR_pinmux_rw_pb_gio 8
-#define REG_WR_ADDR_pinmux_rw_pb_gio 8
-
-/* Register rw_pb_iop, scope pinmux, type rw */
-typedef struct {
-  unsigned int pb0  : 1;
-  unsigned int pb1  : 1;
-  unsigned int pb2  : 1;
-  unsigned int pb3  : 1;
-  unsigned int pb4  : 1;
-  unsigned int pb5  : 1;
-  unsigned int pb6  : 1;
-  unsigned int pb7  : 1;
-  unsigned int pb8  : 1;
-  unsigned int pb9  : 1;
-  unsigned int pb10 : 1;
-  unsigned int pb11 : 1;
-  unsigned int pb12 : 1;
-  unsigned int pb13 : 1;
-  unsigned int pb14 : 1;
-  unsigned int pb15 : 1;
-  unsigned int pb16 : 1;
-  unsigned int pb17 : 1;
-  unsigned int dummy1 : 14;
-} reg_pinmux_rw_pb_iop;
-#define REG_RD_ADDR_pinmux_rw_pb_iop 12
-#define REG_WR_ADDR_pinmux_rw_pb_iop 12
-
-/* Register rw_pc_gio, scope pinmux, type rw */
-typedef struct {
-  unsigned int pc0  : 1;
-  unsigned int pc1  : 1;
-  unsigned int pc2  : 1;
-  unsigned int pc3  : 1;
-  unsigned int pc4  : 1;
-  unsigned int pc5  : 1;
-  unsigned int pc6  : 1;
-  unsigned int pc7  : 1;
-  unsigned int pc8  : 1;
-  unsigned int pc9  : 1;
-  unsigned int pc10 : 1;
-  unsigned int pc11 : 1;
-  unsigned int pc12 : 1;
-  unsigned int pc13 : 1;
-  unsigned int pc14 : 1;
-  unsigned int pc15 : 1;
-  unsigned int pc16 : 1;
-  unsigned int pc17 : 1;
-  unsigned int dummy1 : 14;
-} reg_pinmux_rw_pc_gio;
-#define REG_RD_ADDR_pinmux_rw_pc_gio 16
-#define REG_WR_ADDR_pinmux_rw_pc_gio 16
-
-/* Register rw_pc_iop, scope pinmux, type rw */
-typedef struct {
-  unsigned int pc0  : 1;
-  unsigned int pc1  : 1;
-  unsigned int pc2  : 1;
-  unsigned int pc3  : 1;
-  unsigned int pc4  : 1;
-  unsigned int pc5  : 1;
-  unsigned int pc6  : 1;
-  unsigned int pc7  : 1;
-  unsigned int pc8  : 1;
-  unsigned int pc9  : 1;
-  unsigned int pc10 : 1;
-  unsigned int pc11 : 1;
-  unsigned int pc12 : 1;
-  unsigned int pc13 : 1;
-  unsigned int pc14 : 1;
-  unsigned int pc15 : 1;
-  unsigned int pc16 : 1;
-  unsigned int pc17 : 1;
-  unsigned int dummy1 : 14;
-} reg_pinmux_rw_pc_iop;
-#define REG_RD_ADDR_pinmux_rw_pc_iop 20
-#define REG_WR_ADDR_pinmux_rw_pc_iop 20
-
-/* Register rw_pd_gio, scope pinmux, type rw */
-typedef struct {
-  unsigned int pd0  : 1;
-  unsigned int pd1  : 1;
-  unsigned int pd2  : 1;
-  unsigned int pd3  : 1;
-  unsigned int pd4  : 1;
-  unsigned int pd5  : 1;
-  unsigned int pd6  : 1;
-  unsigned int pd7  : 1;
-  unsigned int pd8  : 1;
-  unsigned int pd9  : 1;
-  unsigned int pd10 : 1;
-  unsigned int pd11 : 1;
-  unsigned int pd12 : 1;
-  unsigned int pd13 : 1;
-  unsigned int pd14 : 1;
-  unsigned int pd15 : 1;
-  unsigned int pd16 : 1;
-  unsigned int pd17 : 1;
-  unsigned int dummy1 : 14;
-} reg_pinmux_rw_pd_gio;
-#define REG_RD_ADDR_pinmux_rw_pd_gio 24
-#define REG_WR_ADDR_pinmux_rw_pd_gio 24
-
-/* Register rw_pd_iop, scope pinmux, type rw */
-typedef struct {
-  unsigned int pd0  : 1;
-  unsigned int pd1  : 1;
-  unsigned int pd2  : 1;
-  unsigned int pd3  : 1;
-  unsigned int pd4  : 1;
-  unsigned int pd5  : 1;
-  unsigned int pd6  : 1;
-  unsigned int pd7  : 1;
-  unsigned int pd8  : 1;
-  unsigned int pd9  : 1;
-  unsigned int pd10 : 1;
-  unsigned int pd11 : 1;
-  unsigned int pd12 : 1;
-  unsigned int pd13 : 1;
-  unsigned int pd14 : 1;
-  unsigned int pd15 : 1;
-  unsigned int pd16 : 1;
-  unsigned int pd17 : 1;
-  unsigned int dummy1 : 14;
-} reg_pinmux_rw_pd_iop;
-#define REG_RD_ADDR_pinmux_rw_pd_iop 28
-#define REG_WR_ADDR_pinmux_rw_pd_iop 28
-
-/* Register rw_pe_gio, scope pinmux, type rw */
-typedef struct {
-  unsigned int pe0  : 1;
-  unsigned int pe1  : 1;
-  unsigned int pe2  : 1;
-  unsigned int pe3  : 1;
-  unsigned int pe4  : 1;
-  unsigned int pe5  : 1;
-  unsigned int pe6  : 1;
-  unsigned int pe7  : 1;
-  unsigned int pe8  : 1;
-  unsigned int pe9  : 1;
-  unsigned int pe10 : 1;
-  unsigned int pe11 : 1;
-  unsigned int pe12 : 1;
-  unsigned int pe13 : 1;
-  unsigned int pe14 : 1;
-  unsigned int pe15 : 1;
-  unsigned int pe16 : 1;
-  unsigned int pe17 : 1;
-  unsigned int dummy1 : 14;
-} reg_pinmux_rw_pe_gio;
-#define REG_RD_ADDR_pinmux_rw_pe_gio 32
-#define REG_WR_ADDR_pinmux_rw_pe_gio 32
-
-/* Register rw_pe_iop, scope pinmux, type rw */
-typedef struct {
-  unsigned int pe0  : 1;
-  unsigned int pe1  : 1;
-  unsigned int pe2  : 1;
-  unsigned int pe3  : 1;
-  unsigned int pe4  : 1;
-  unsigned int pe5  : 1;
-  unsigned int pe6  : 1;
-  unsigned int pe7  : 1;
-  unsigned int pe8  : 1;
-  unsigned int pe9  : 1;
-  unsigned int pe10 : 1;
-  unsigned int pe11 : 1;
-  unsigned int pe12 : 1;
-  unsigned int pe13 : 1;
-  unsigned int pe14 : 1;
-  unsigned int pe15 : 1;
-  unsigned int pe16 : 1;
-  unsigned int pe17 : 1;
-  unsigned int dummy1 : 14;
-} reg_pinmux_rw_pe_iop;
-#define REG_RD_ADDR_pinmux_rw_pe_iop 36
-#define REG_WR_ADDR_pinmux_rw_pe_iop 36
-
-/* Register rw_usb_phy, scope pinmux, type rw */
-typedef struct {
-  unsigned int en_usb0 : 1;
-  unsigned int en_usb1 : 1;
-  unsigned int dummy1  : 30;
-} reg_pinmux_rw_usb_phy;
-#define REG_RD_ADDR_pinmux_rw_usb_phy 40
-#define REG_WR_ADDR_pinmux_rw_usb_phy 40
-
-
-/* Constants */
-enum {
-  regk_pinmux_no                           = 0x00000000,
-  regk_pinmux_rw_hwprot_default            = 0x00000000,
-  regk_pinmux_rw_pa_default                = 0x00000000,
-  regk_pinmux_rw_pb_gio_default            = 0x00000000,
-  regk_pinmux_rw_pb_iop_default            = 0x00000000,
-  regk_pinmux_rw_pc_gio_default            = 0x00000000,
-  regk_pinmux_rw_pc_iop_default            = 0x00000000,
-  regk_pinmux_rw_pd_gio_default            = 0x00000000,
-  regk_pinmux_rw_pd_iop_default            = 0x00000000,
-  regk_pinmux_rw_pe_gio_default            = 0x00000000,
-  regk_pinmux_rw_pe_iop_default            = 0x00000000,
-  regk_pinmux_rw_usb_phy_default           = 0x00000000,
-  regk_pinmux_yes                          = 0x00000001
-};
-#endif /* __pinmux_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h b/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h
deleted file mode 100644
index 4146973a58b3..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h
+++ /dev/null
@@ -1,104 +0,0 @@
-#ifndef __reg_map_h
-#define __reg_map_h
-
-/*
- * This file is autogenerated from
- *   file:            ../../mod/fakereg.rmap
- *     id:            fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp 
- *     last modified: Wed Feb 11 20:53:25 2004
- *   file:            ../../rtl/global.rmap
- *     id:            global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp 
- *     last modified: Mon Aug 18 17:08:23 2003
- *   file:            ../../mod/modreg.rmap
- *     id:            modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp 
- *     last modified: Fri Feb 20 16:40:04 2004
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
- *      id: $Id: reg_map.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ 
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-typedef enum {
-  regi_ata                                 = 0xb0032000,
-  regi_bif_core                            = 0xb0014000,
-  regi_bif_dma                             = 0xb0016000,
-  regi_bif_slave                           = 0xb0018000,
-  regi_config                              = 0xb003c000,
-  regi_dma0                                = 0xb0000000,
-  regi_dma1                                = 0xb0002000,
-  regi_dma2                                = 0xb0004000,
-  regi_dma3                                = 0xb0006000,
-  regi_dma4                                = 0xb0008000,
-  regi_dma5                                = 0xb000a000,
-  regi_dma6                                = 0xb000c000,
-  regi_dma7                                = 0xb000e000,
-  regi_dma8                                = 0xb0010000,
-  regi_dma9                                = 0xb0012000,
-  regi_eth0                                = 0xb0034000,
-  regi_eth1                                = 0xb0036000,
-  regi_gio                                 = 0xb001a000,
-  regi_iop                                 = 0xb0020000,
-  regi_iop_version                         = 0xb0020000,
-  regi_iop_fifo_in0_extra                  = 0xb0020040,
-  regi_iop_fifo_in1_extra                  = 0xb0020080,
-  regi_iop_fifo_out0_extra                 = 0xb00200c0,
-  regi_iop_fifo_out1_extra                 = 0xb0020100,
-  regi_iop_trigger_grp0                    = 0xb0020140,
-  regi_iop_trigger_grp1                    = 0xb0020180,
-  regi_iop_trigger_grp2                    = 0xb00201c0,
-  regi_iop_trigger_grp3                    = 0xb0020200,
-  regi_iop_trigger_grp4                    = 0xb0020240,
-  regi_iop_trigger_grp5                    = 0xb0020280,
-  regi_iop_trigger_grp6                    = 0xb00202c0,
-  regi_iop_trigger_grp7                    = 0xb0020300,
-  regi_iop_crc_par0                        = 0xb0020380,
-  regi_iop_crc_par1                        = 0xb0020400,
-  regi_iop_dmc_in0                         = 0xb0020480,
-  regi_iop_dmc_in1                         = 0xb0020500,
-  regi_iop_dmc_out0                        = 0xb0020580,
-  regi_iop_dmc_out1                        = 0xb0020600,
-  regi_iop_fifo_in0                        = 0xb0020680,
-  regi_iop_fifo_in1                        = 0xb0020700,
-  regi_iop_fifo_out0                       = 0xb0020780,
-  regi_iop_fifo_out1                       = 0xb0020800,
-  regi_iop_scrc_in0                        = 0xb0020880,
-  regi_iop_scrc_in1                        = 0xb0020900,
-  regi_iop_scrc_out0                       = 0xb0020980,
-  regi_iop_scrc_out1                       = 0xb0020a00,
-  regi_iop_timer_grp0                      = 0xb0020a80,
-  regi_iop_timer_grp1                      = 0xb0020b00,
-  regi_iop_timer_grp2                      = 0xb0020b80,
-  regi_iop_timer_grp3                      = 0xb0020c00,
-  regi_iop_sap_in                          = 0xb0020d00,
-  regi_iop_sap_out                         = 0xb0020e00,
-  regi_iop_spu0                            = 0xb0020f00,
-  regi_iop_spu1                            = 0xb0021000,
-  regi_iop_sw_cfg                          = 0xb0021100,
-  regi_iop_sw_cpu                          = 0xb0021200,
-  regi_iop_sw_mpu                          = 0xb0021300,
-  regi_iop_sw_spu0                         = 0xb0021400,
-  regi_iop_sw_spu1                         = 0xb0021500,
-  regi_iop_mpu                             = 0xb0021600,
-  regi_irq                                 = 0xb001c000,
-  regi_irq2                                = 0xb005c000,
-  regi_marb                                = 0xb003e000,
-  regi_marb_bp0                            = 0xb003e240,
-  regi_marb_bp1                            = 0xb003e280,
-  regi_marb_bp2                            = 0xb003e2c0,
-  regi_marb_bp3                            = 0xb003e300,
-  regi_pinmux                              = 0xb0038000,
-  regi_ser0                                = 0xb0026000,
-  regi_ser1                                = 0xb0028000,
-  regi_ser2                                = 0xb002a000,
-  regi_ser3                                = 0xb002c000,
-  regi_sser0                               = 0xb0022000,
-  regi_sser1                               = 0xb0024000,
-  regi_strcop                              = 0xb0030000,
-  regi_strmux                              = 0xb003a000,
-  regi_timer                               = 0xb001e000,
-  regi_timer0                              = 0xb001e000,
-  regi_timer2                              = 0xb005e000,
-  regi_trace                               = 0xb0040000,
-} reg_scope_instances;
-#endif /* __reg_map_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h
deleted file mode 100644
index cbfaa867829e..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h
+++ /dev/null
@@ -1,127 +0,0 @@
-#ifndef __strmux_defs_h
-#define __strmux_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/strmux/rtl/guinness/strmux_regs.r
- *     id:           strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp 
- *     last modfied: Mon Apr 11 16:09:43 2005
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r
- *      id: $Id: strmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope strmux */
-
-/* Register rw_cfg, scope strmux, type rw */
-typedef struct {
-  unsigned int dma0 : 3;
-  unsigned int dma1 : 3;
-  unsigned int dma2 : 3;
-  unsigned int dma3 : 3;
-  unsigned int dma4 : 3;
-  unsigned int dma5 : 3;
-  unsigned int dma6 : 3;
-  unsigned int dma7 : 3;
-  unsigned int dma8 : 3;
-  unsigned int dma9 : 3;
-  unsigned int dummy1 : 2;
-} reg_strmux_rw_cfg;
-#define REG_RD_ADDR_strmux_rw_cfg 0
-#define REG_WR_ADDR_strmux_rw_cfg 0
-
-
-/* Constants */
-enum {
-  regk_strmux_ata                          = 0x00000003,
-  regk_strmux_eth0                         = 0x00000001,
-  regk_strmux_eth1                         = 0x00000004,
-  regk_strmux_ext0                         = 0x00000001,
-  regk_strmux_ext1                         = 0x00000001,
-  regk_strmux_ext2                         = 0x00000001,
-  regk_strmux_ext3                         = 0x00000001,
-  regk_strmux_iop0                         = 0x00000002,
-  regk_strmux_iop1                         = 0x00000001,
-  regk_strmux_off                          = 0x00000000,
-  regk_strmux_p21                          = 0x00000004,
-  regk_strmux_rw_cfg_default               = 0x00000000,
-  regk_strmux_ser0                         = 0x00000002,
-  regk_strmux_ser1                         = 0x00000002,
-  regk_strmux_ser2                         = 0x00000004,
-  regk_strmux_ser3                         = 0x00000003,
-  regk_strmux_sser0                        = 0x00000003,
-  regk_strmux_sser1                        = 0x00000003,
-  regk_strmux_strcop                       = 0x00000002
-};
-#endif /* __strmux_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h
deleted file mode 100644
index 76bcc591921d..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h
+++ /dev/null
@@ -1,266 +0,0 @@
-#ifndef __timer_defs_h
-#define __timer_defs_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/timer/rtl/timer_regs.r
- *     id:           timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp 
- *     last modfied: Mon Apr 11 16:09:53 2005
- * 
- *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r
- *      id: $Id: timer_defs.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
-  REG_READ( reg_##scope##_##reg, \
-            (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( reg_##scope##_##reg, \
-             (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
-	    (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
-	     (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
-    (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope timer */
-
-/* Register rw_tmr0_div, scope timer, type rw */
-typedef unsigned int reg_timer_rw_tmr0_div;
-#define REG_RD_ADDR_timer_rw_tmr0_div 0
-#define REG_WR_ADDR_timer_rw_tmr0_div 0
-
-/* Register r_tmr0_data, scope timer, type r */
-typedef unsigned int reg_timer_r_tmr0_data;
-#define REG_RD_ADDR_timer_r_tmr0_data 4
-
-/* Register rw_tmr0_ctrl, scope timer, type rw */
-typedef struct {
-  unsigned int op   : 2;
-  unsigned int freq : 3;
-  unsigned int dummy1 : 27;
-} reg_timer_rw_tmr0_ctrl;
-#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
-#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
-
-/* Register rw_tmr1_div, scope timer, type rw */
-typedef unsigned int reg_timer_rw_tmr1_div;
-#define REG_RD_ADDR_timer_rw_tmr1_div 16
-#define REG_WR_ADDR_timer_rw_tmr1_div 16
-
-/* Register r_tmr1_data, scope timer, type r */
-typedef unsigned int reg_timer_r_tmr1_data;
-#define REG_RD_ADDR_timer_r_tmr1_data 20
-
-/* Register rw_tmr1_ctrl, scope timer, type rw */
-typedef struct {
-  unsigned int op   : 2;
-  unsigned int freq : 3;
-  unsigned int dummy1 : 27;
-} reg_timer_rw_tmr1_ctrl;
-#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
-#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
-
-/* Register rs_cnt_data, scope timer, type rs */
-typedef struct {
-  unsigned int tmr : 24;
-  unsigned int cnt : 8;
-} reg_timer_rs_cnt_data;
-#define REG_RD_ADDR_timer_rs_cnt_data 32
-
-/* Register r_cnt_data, scope timer, type r */
-typedef struct {
-  unsigned int tmr : 24;
-  unsigned int cnt : 8;
-} reg_timer_r_cnt_data;
-#define REG_RD_ADDR_timer_r_cnt_data 36
-
-/* Register rw_cnt_cfg, scope timer, type rw */
-typedef struct {
-  unsigned int clk : 2;
-  unsigned int dummy1 : 30;
-} reg_timer_rw_cnt_cfg;
-#define REG_RD_ADDR_timer_rw_cnt_cfg 40
-#define REG_WR_ADDR_timer_rw_cnt_cfg 40
-
-/* Register rw_trig, scope timer, type rw */
-typedef unsigned int reg_timer_rw_trig;
-#define REG_RD_ADDR_timer_rw_trig 48
-#define REG_WR_ADDR_timer_rw_trig 48
-
-/* Register rw_trig_cfg, scope timer, type rw */
-typedef struct {
-  unsigned int tmr : 2;
-  unsigned int dummy1 : 30;
-} reg_timer_rw_trig_cfg;
-#define REG_RD_ADDR_timer_rw_trig_cfg 52
-#define REG_WR_ADDR_timer_rw_trig_cfg 52
-
-/* Register r_time, scope timer, type r */
-typedef unsigned int reg_timer_r_time;
-#define REG_RD_ADDR_timer_r_time 56
-
-/* Register rw_out, scope timer, type rw */
-typedef struct {
-  unsigned int tmr : 2;
-  unsigned int dummy1 : 30;
-} reg_timer_rw_out;
-#define REG_RD_ADDR_timer_rw_out 60
-#define REG_WR_ADDR_timer_rw_out 60
-
-/* Register rw_wd_ctrl, scope timer, type rw */
-typedef struct {
-  unsigned int cnt : 8;
-  unsigned int cmd : 1;
-  unsigned int key : 7;
-  unsigned int dummy1 : 16;
-} reg_timer_rw_wd_ctrl;
-#define REG_RD_ADDR_timer_rw_wd_ctrl 64
-#define REG_WR_ADDR_timer_rw_wd_ctrl 64
-
-/* Register r_wd_stat, scope timer, type r */
-typedef struct {
-  unsigned int cnt : 8;
-  unsigned int cmd : 1;
-  unsigned int dummy1 : 23;
-} reg_timer_r_wd_stat;
-#define REG_RD_ADDR_timer_r_wd_stat 68
-
-/* Register rw_intr_mask, scope timer, type rw */
-typedef struct {
-  unsigned int tmr0 : 1;
-  unsigned int tmr1 : 1;
-  unsigned int cnt  : 1;
-  unsigned int trig : 1;
-  unsigned int dummy1 : 28;
-} reg_timer_rw_intr_mask;
-#define REG_RD_ADDR_timer_rw_intr_mask 72
-#define REG_WR_ADDR_timer_rw_intr_mask 72
-
-/* Register rw_ack_intr, scope timer, type rw */
-typedef struct {
-  unsigned int tmr0 : 1;
-  unsigned int tmr1 : 1;
-  unsigned int cnt  : 1;
-  unsigned int trig : 1;
-  unsigned int dummy1 : 28;
-} reg_timer_rw_ack_intr;
-#define REG_RD_ADDR_timer_rw_ack_intr 76
-#define REG_WR_ADDR_timer_rw_ack_intr 76
-
-/* Register r_intr, scope timer, type r */
-typedef struct {
-  unsigned int tmr0 : 1;
-  unsigned int tmr1 : 1;
-  unsigned int cnt  : 1;
-  unsigned int trig : 1;
-  unsigned int dummy1 : 28;
-} reg_timer_r_intr;
-#define REG_RD_ADDR_timer_r_intr 80
-
-/* Register r_masked_intr, scope timer, type r */
-typedef struct {
-  unsigned int tmr0 : 1;
-  unsigned int tmr1 : 1;
-  unsigned int cnt  : 1;
-  unsigned int trig : 1;
-  unsigned int dummy1 : 28;
-} reg_timer_r_masked_intr;
-#define REG_RD_ADDR_timer_r_masked_intr 84
-
-/* Register rw_test, scope timer, type rw */
-typedef struct {
-  unsigned int dis : 1;
-  unsigned int en  : 1;
-  unsigned int dummy1 : 30;
-} reg_timer_rw_test;
-#define REG_RD_ADDR_timer_rw_test 88
-#define REG_WR_ADDR_timer_rw_test 88
-
-
-/* Constants */
-enum {
-  regk_timer_ext                           = 0x00000001,
-  regk_timer_f100                          = 0x00000007,
-  regk_timer_f29_493                       = 0x00000004,
-  regk_timer_f32                           = 0x00000005,
-  regk_timer_f32_768                       = 0x00000006,
-  regk_timer_hold                          = 0x00000001,
-  regk_timer_ld                            = 0x00000000,
-  regk_timer_no                            = 0x00000000,
-  regk_timer_off                           = 0x00000000,
-  regk_timer_run                           = 0x00000002,
-  regk_timer_rw_cnt_cfg_default            = 0x00000000,
-  regk_timer_rw_intr_mask_default          = 0x00000000,
-  regk_timer_rw_out_default                = 0x00000000,
-  regk_timer_rw_test_default               = 0x00000000,
-  regk_timer_rw_tmr0_ctrl_default          = 0x00000000,
-  regk_timer_rw_tmr1_ctrl_default          = 0x00000000,
-  regk_timer_rw_trig_cfg_default           = 0x00000000,
-  regk_timer_start                         = 0x00000001,
-  regk_timer_stop                          = 0x00000000,
-  regk_timer_time                          = 0x00000001,
-  regk_timer_tmr0                          = 0x00000002,
-  regk_timer_tmr1                          = 0x00000003,
-  regk_timer_yes                           = 0x00000001
-};
-#endif /* __timer_defs_h */
diff --git a/include/asm-cris/arch-v32/mach-fs/pinmux.h b/include/asm-cris/arch-v32/mach-fs/pinmux.h
deleted file mode 100644
index c2b3036779df..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/pinmux.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_PINMUX_H
-#define _ASM_CRIS_ARCH_PINMUX_H
-
-#define PORT_B 0
-#define PORT_C 1
-#define PORT_D 2
-#define PORT_E 3
-
-enum pin_mode {
-  pinmux_none = 0,
-  pinmux_fixed,
-  pinmux_gpio,
-  pinmux_iop
-};
-
-enum fixed_function {
-  pinmux_ser1,
-  pinmux_ser2,
-  pinmux_ser3,
-  pinmux_sser0,
-  pinmux_sser1,
-  pinmux_ata0,
-  pinmux_ata1,
-  pinmux_ata2,
-  pinmux_ata3,
-  pinmux_ata,
-  pinmux_eth1,
-  pinmux_timer
-};
-
-int crisv32_pinmux_init(void);
-int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
-int crisv32_pinmux_alloc_fixed(enum fixed_function function);
-int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
-int crisv32_pinmux_dealloc_fixed(enum fixed_function function);
-void crisv32_pinmux_dump(void);
-
-#endif
diff --git a/include/asm-cris/arch-v32/mach-fs/startup.inc b/include/asm-cris/arch-v32/mach-fs/startup.inc
deleted file mode 100644
index 4a10ccbd6cc1..000000000000
--- a/include/asm-cris/arch-v32/mach-fs/startup.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-#include <hwregs/asm/reg_map_asm.h>
-#include <hwregs/asm/bif_core_defs_asm.h>
-#include <hwregs/asm/gio_defs_asm.h>
-#include <hwregs/asm/config_defs_asm.h>
-
-	.macro GIO_INIT
-	move.d	CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
-	move.d	REG_ADDR(gio, regi_gio, rw_pa_dout), $r1
-	move.d	$r0, [$r1]
-
-	move.d	CONFIG_ETRAX_DEF_GIO_PA_OE, $r0
-	move.d	REG_ADDR(gio, regi_gio, rw_pa_oe), $r1
-	move.d	$r0, [$r1]
-
-	move.d	CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0
-	move.d	REG_ADDR(gio, regi_gio, rw_pb_dout), $r1
-	move.d	$r0, [$r1]
-
-	move.d	CONFIG_ETRAX_DEF_GIO_PB_OE, $r0
-	move.d	REG_ADDR(gio, regi_gio, rw_pb_oe), $r1
-	move.d	$r0, [$r1]
-
-	move.d	CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0
-	move.d	REG_ADDR(gio, regi_gio, rw_pc_dout), $r1
-	move.d	$r0, [$r1]
-
-	move.d	CONFIG_ETRAX_DEF_GIO_PC_OE, $r0
-	move.d	REG_ADDR(gio, regi_gio, rw_pc_oe), $r1
-	move.d	$r0, [$r1]
-
-	move.d	CONFIG_ETRAX_DEF_GIO_PD_OUT, $r0
-	move.d	REG_ADDR(gio, regi_gio, rw_pd_dout), $r1
-	move.d	$r0, [$r1]
-
-	move.d	CONFIG_ETRAX_DEF_GIO_PD_OE, $r0
-	move.d	REG_ADDR(gio, regi_gio, rw_pd_oe), $r1
-	move.d	$r0, [$r1]
-
-	move.d	CONFIG_ETRAX_DEF_GIO_PE_OUT, $r0
-	move.d	REG_ADDR(gio, regi_gio, rw_pe_dout), $r1
-	move.d	$r0, [$r1]
-
-	move.d	CONFIG_ETRAX_DEF_GIO_PE_OE, $r0
-	move.d	REG_ADDR(gio, regi_gio, rw_pe_oe), $r1
-	move.d	$r0, [$r1]
-	.endm
-
-	.macro START_CLOCKS
-	move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1
-	move.d [$r1], $r0
-	or.d   REG_STATE(config, rw_clk_ctrl, cpu, yes) | \
-	       REG_STATE(config, rw_clk_ctrl, bif, yes) | \
-	       REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0
-	move.d $r0, [$r1]
-	.endm
-
-	.macro SETUP_WAIT_STATES
-	;; Set up waitstates etc
-	move.d   REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0
-	move.d   CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1
-	move.d   $r1, [$r0]
-	move.d   REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0
-	move.d   CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1
-	move.d   $r1, [$r0]
-	move.d   REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0
-	move.d   CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1
-	move.d   $r1, [$r0]
-	move.d   REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0
-	move.d   CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1
-	move.d   $r1, [$r0]
-#ifdef CONFIG_ETRAX_VCS_SIM
-	;; Set up minimal flash waitstates
-	move.d 0, $r10
-	move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r11
-	move.d $r10, [$r11]
-#endif
-	.endm
diff --git a/include/asm-cris/arch-v32/memmap.h b/include/asm-cris/arch-v32/memmap.h
deleted file mode 100644
index d29df5644d3e..000000000000
--- a/include/asm-cris/arch-v32/memmap.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef _ASM_ARCH_MEMMAP_H
-#define _ASM_ARCH_MEMMAP_H
-
-#define MEM_CSE0_START (0x00000000)
-#define MEM_CSE0_SIZE (0x04000000)
-#define MEM_CSE1_START (0x04000000)
-#define MEM_CSE1_SIZE (0x04000000)
-#define MEM_CSR0_START (0x08000000)
-#define MEM_CSR1_START (0x0c000000)
-#define MEM_CSP0_START (0x10000000)
-#define MEM_CSP1_START (0x14000000)
-#define MEM_CSP2_START (0x18000000)
-#define MEM_CSP3_START (0x1c000000)
-#define MEM_CSP4_START (0x20000000)
-#define MEM_CSP5_START (0x24000000)
-#define MEM_CSP6_START (0x28000000)
-#define MEM_CSP7_START (0x2c000000)
-#define MEM_INTMEM_START (0x38000000)
-#define MEM_INTMEM_SIZE (0x00020000)
-#define MEM_DRAM_START (0x40000000)
-
-#define MEM_NON_CACHEABLE (0x80000000)
-
-#endif
diff --git a/include/asm-cris/arch-v32/mmu.h b/include/asm-cris/arch-v32/mmu.h
deleted file mode 100644
index 6bcdc3fdf7dc..000000000000
--- a/include/asm-cris/arch-v32/mmu.h
+++ /dev/null
@@ -1,111 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_MMU_H
-#define _ASM_CRIS_ARCH_MMU_H
-
-/* MMU context type. */
-typedef struct
-{
-  unsigned int page_id;
-} mm_context_t;
-
-/* Kernel memory segments. */
-#define KSEG_F 0xf0000000UL
-#define KSEG_E 0xe0000000UL
-#define KSEG_D 0xd0000000UL
-#define KSEG_C 0xc0000000UL
-#define KSEG_B 0xb0000000UL
-#define KSEG_A 0xa0000000UL
-#define KSEG_9 0x90000000UL
-#define KSEG_8 0x80000000UL
-#define KSEG_7 0x70000000UL
-#define KSEG_6 0x60000000UL
-#define KSEG_5 0x50000000UL
-#define KSEG_4 0x40000000UL
-#define KSEG_3 0x30000000UL
-#define KSEG_2 0x20000000UL
-#define KSEG_1 0x10000000UL
-#define KSEG_0 0x00000000UL
-
-/*
- * CRISv32 PTE bits:
- *
- *  Bit:  31-13  12-5     4        3       2        1        0
- *       +-----+------+--------+-------+--------+-------+---------+
- *       | pfn | zero | global | valid | kernel | write | execute |
- *       +-----+------+--------+-------+--------+-------+---------+
- */
-
-/*
- * Defines for accessing the bits. Also define some synonyms for use with
- * the software-based defined bits below.
- */
-#define _PAGE_EXECUTE       (1 << 0)	/* Execution bit. */
-#define _PAGE_WE            (1 << 1)	/* Write bit. */
-#define _PAGE_SILENT_WRITE  (1 << 1)	/* Same as above. */
-#define _PAGE_KERNEL        (1 << 2)	/* Kernel mode page. */
-#define _PAGE_VALID         (1 << 3)	/* Page is valid. */
-#define _PAGE_SILENT_READ   (1 << 3)	/* Same as above. */
-#define _PAGE_GLOBAL        (1 << 4)	/* Global page. */
-
-/*
- * The hardware doesn't care about these bits, but the kernel uses them in
- * software.
- */
-#define _PAGE_PRESENT   (1 << 5)   /* Page is present in memory. */
-#define _PAGE_FILE      (1 << 6)   /* 1=pagecache, 0=swap (when !present) */
-#define _PAGE_ACCESSED  (1 << 6)   /* Simulated in software using valid bit. */
-#define _PAGE_MODIFIED  (1 << 7)   /* Simulated in software using we bit. */
-#define _PAGE_READ      (1 << 8)   /* Read enabled. */
-#define _PAGE_WRITE     (1 << 9)   /* Write enabled. */
-
-/* Define some higher level generic page attributes. */
-#define __READABLE      (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
-#define __WRITEABLE     (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
-
-#define _PAGE_TABLE	(_PAGE_PRESENT | __READABLE | __WRITEABLE)
-#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED)
-
-#define PAGE_NONE       __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
-#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
-                                 _PAGE_ACCESSED)
-#define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
-                                  _PAGE_ACCESSED | _PAGE_EXECUTE)
-
-#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | __READABLE)
-#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE | _PAGE_ACCESSED)
-
-#define PAGE_COPY       __pgprot(_PAGE_PRESENT | __READABLE)
-#define PAGE_COPY_EXEC	__pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE)
-#define PAGE_KERNEL     __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \
-                                 _PAGE_PRESENT | __READABLE | __WRITEABLE)
-#define PAGE_KERNEL_EXEC __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | _PAGE_EXECUTE | \
-                                 _PAGE_PRESENT | __READABLE | __WRITEABLE)
-#define PAGE_SIGNAL_TRAMPOLINE __pgprot(_PAGE_GLOBAL | _PAGE_EXECUTE | \
-                                       _PAGE_PRESENT | __READABLE)
-
-#define _KERNPG_TABLE   (_PAGE_TABLE | _PAGE_KERNEL)
-
-/* CRISv32 can do page protection for execute.
- * Write permissions imply read permissions.
- * Note that the numbers are in Execute-Write-Read order!
- */
-#define __P000  PAGE_NONE
-#define __P001  PAGE_READONLY
-#define __P010  PAGE_COPY
-#define __P011  PAGE_COPY
-#define __P100  PAGE_READONLY_EXEC
-#define __P101  PAGE_READONLY_EXEC
-#define __P110  PAGE_COPY_EXEC
-#define __P111  PAGE_COPY_EXEC
-
-#define __S000  PAGE_NONE
-#define __S001  PAGE_READONLY
-#define __S010  PAGE_SHARED
-#define __S011  PAGE_SHARED
-#define __S100  PAGE_READONLY_EXEC
-#define __S101  PAGE_READONLY_EXEC
-#define __S110  PAGE_SHARED_EXEC
-#define __S111  PAGE_SHARED_EXEC
-
-#define PTE_FILE_MAX_BITS	25
-
-#endif /* _ASM_CRIS_ARCH_MMU_H */
diff --git a/include/asm-cris/arch-v32/offset.h b/include/asm-cris/arch-v32/offset.h
deleted file mode 100644
index 4442c4bd52f4..000000000000
--- a/include/asm-cris/arch-v32/offset.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef __ASM_OFFSETS_H__
-#define __ASM_OFFSETS_H__
-/*
- * DO NOT MODIFY.
- *
- * This file was generated by arch/cris/Makefile
- *
- */
-
-#define PT_orig_r10 0 /* offsetof(struct pt_regs, orig_r10) */
-#define PT_r13 56 /* offsetof(struct pt_regs, r13) */
-#define PT_r12 52 /* offsetof(struct pt_regs, r12) */
-#define PT_r11 48 /* offsetof(struct pt_regs, r11) */
-#define PT_r10 44 /* offsetof(struct pt_regs, r10) */
-#define PT_r9 40 /* offsetof(struct pt_regs, r9) */
-#define PT_acr 60 /* offsetof(struct pt_regs, acr) */
-#define PT_srs 64 /* offsetof(struct pt_regs, srs) */
-#define PT_mof 68 /* offsetof(struct pt_regs, mof) */
-#define PT_ccs 76 /* offsetof(struct pt_regs, ccs) */
-#define PT_srp 80 /* offsetof(struct pt_regs, srp) */
-
-#define TI_task 0 /* offsetof(struct thread_info, task) */
-#define TI_flags 8 /* offsetof(struct thread_info, flags) */
-#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */
-
-#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */
-#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */
-#define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */
-
-#define TASK_pid 151 /* offsetof(struct task_struct, pid) */
-
-#define LCLONE_VM 256 /* CLONE_VM */
-#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */
-
-#endif
diff --git a/include/asm-cris/arch-v32/page.h b/include/asm-cris/arch-v32/page.h
deleted file mode 100644
index 20f1b4806bfe..000000000000
--- a/include/asm-cris/arch-v32/page.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_PAGE_H
-#define _ASM_CRIS_ARCH_PAGE_H
-
-
-#ifdef __KERNEL__
-
-#define PAGE_OFFSET KSEG_C	/* kseg_c is mapped to physical ram. */
-
-/*
- * Macros to convert between physical and virtual addresses. By stripping a
- * selected bit it's possible to convert between KSEG_x and 0x40000000 where the
- * DRAM really resides. DRAM is virtually at 0xc.
- */
-#ifndef CONFIG_ETRAX_VCS_SIM
-#define __pa(x) ((unsigned long)(x) & 0x7fffffff)
-#define __va(x) ((void *)((unsigned long)(x) | 0x80000000))
-#else
-#define __pa(x) ((unsigned long)(x) & 0x3fffffff)
-#define __va(x) ((void *)((unsigned long)(x) | 0xc0000000))
-#endif
-
-#define VM_STACK_DEFAULT_FLAGS	(VM_READ | VM_WRITE | \
-				 VM_MAYREAD | VM_MAYWRITE)
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_CRIS_ARCH_PAGE_H */
diff --git a/include/asm-cris/arch-v32/pgtable.h b/include/asm-cris/arch-v32/pgtable.h
deleted file mode 100644
index 08cb7ff7e4e7..000000000000
--- a/include/asm-cris/arch-v32/pgtable.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_PGTABLE_H
-#define _ASM_CRIS_ARCH_PGTABLE_H
-
-/* Define the kernels virtual memory area. */
-#define VMALLOC_START		KSEG_D
-#define VMALLOC_END		KSEG_E
-#define VMALLOC_VMADDR(x)	((unsigned long)(x))
-
-#endif /* _ASM_CRIS_ARCH_PGTABLE_H */
diff --git a/include/asm-cris/arch-v32/pinmux.h b/include/asm-cris/arch-v32/pinmux.h
deleted file mode 100644
index bb09bce42e7a..000000000000
--- a/include/asm-cris/arch-v32/pinmux.h
+++ /dev/null
@@ -1,40 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_PINMUX_H
-#define _ASM_CRIS_ARCH_PINMUX_H
-
-#define PORT_B 0
-#define PORT_C 1
-#define PORT_D 2
-#define PORT_E 3
-
-enum pin_mode
-{
-  pinmux_none = 0,
-  pinmux_fixed,
-  pinmux_gpio,
-  pinmux_iop
-};
-
-enum fixed_function
-{
-  pinmux_ser1,
-  pinmux_ser2,
-  pinmux_ser3,
-  pinmux_sser0,
-  pinmux_sser1,
-  pinmux_ata0,
-  pinmux_ata1,
-  pinmux_ata2,
-  pinmux_ata3,
-  pinmux_ata,
-  pinmux_eth1,
-  pinmux_timer
-};
-
-int crisv32_pinmux_init(void);
-int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
-int crisv32_pinmux_alloc_fixed(enum fixed_function function);
-int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
-int crisv32_pinmux_dealloc_fixed(enum fixed_function function);
-void crisv32_pinmux_dump(void);
-
-#endif
diff --git a/include/asm-cris/arch-v32/processor.h b/include/asm-cris/arch-v32/processor.h
deleted file mode 100644
index f80b47790ca6..000000000000
--- a/include/asm-cris/arch-v32/processor.h
+++ /dev/null
@@ -1,59 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_PROCESSOR_H
-#define _ASM_CRIS_ARCH_PROCESSOR_H
-
-
-/* Return current instruction pointer. */
-#define current_text_addr() \
-	({void *pc; __asm__ __volatile__ ("lapcq .,%0" : "=rm" (pc)); pc;})
-
-/*
- * Since CRIS doesn't do hardware task-switching this hasn't really anything to
- * do with the proccessor itself, it's just here for legacy reasons. This is
- * used when task-switching using _resume defined in entry.S. The offsets here
- * are hardcoded into _resume, so if this struct is changed, entry.S needs to be
- * changed as well.
- */
-struct thread_struct {
-	unsigned long ksp;	/* Kernel stack pointer. */
-	unsigned long usp;	/* User stack pointer. */
-	unsigned long ccs;	/* Saved flags register. */
-};
-
-/*
- * User-space process size. This is hardcoded into a few places, so don't
- * changed it unless everything's clear!
- */
-#ifndef CONFIG_ETRAX_VCS_SIM
-#define TASK_SIZE	(0xB0000000UL)
-#else
-#define TASK_SIZE	(0xA0000000UL)
-#endif
-
-/* CCS I=1, enable interrupts. */
-#define INIT_THREAD { 0, 0, (1 << I_CCS_BITNR) }
-
-#define KSTK_EIP(tsk)		\
-({				\
-	unsigned long eip = 0;	\
-	unsigned long regs = (unsigned long)task_pt_regs(tsk); \
-	if (regs > PAGE_SIZE && virt_addr_valid(regs))	    \
-		eip = ((struct pt_regs *)regs)->erp;	    \
-	eip; \
-})
-
-/*
- * Give the thread a program location, set user-mode and switch user
- * stackpointer.
- */
-#define start_thread(regs, ip, usp) \
-do { \
-	set_fs(USER_DS); \
-	regs->erp = ip; \
-	regs->ccs |= 1 << (U_CCS_BITNR + CCS_SHIFT); \
-	wrusp(usp); \
-} while(0)
-
-/* Nothing special to do for v32 when handling a kernel bus fault fixup. */
-#define arch_fixup(regs) {};
-
-#endif /* _ASM_CRIS_ARCH_PROCESSOR_H */
diff --git a/include/asm-cris/arch-v32/ptrace.h b/include/asm-cris/arch-v32/ptrace.h
deleted file mode 100644
index 41f4e8662bc2..000000000000
--- a/include/asm-cris/arch-v32/ptrace.h
+++ /dev/null
@@ -1,118 +0,0 @@
-#ifndef _CRIS_ARCH_PTRACE_H
-#define _CRIS_ARCH_PTRACE_H
-
-/* Register numbers in the ptrace system call interface */
-
-#define PT_ORIG_R10  0
-#define PT_R0        1
-#define PT_R1        2
-#define PT_R2        3
-#define PT_R3        4
-#define PT_R4        5
-#define PT_R5        6
-#define PT_R6        7
-#define PT_R7        8
-#define PT_R8        9
-#define PT_R9        10
-#define PT_R10       11
-#define PT_R11       12
-#define PT_R12       13
-#define PT_R13       14
-#define PT_ACR       15
-#define PT_SRS       16
-#define PT_MOF       17
-#define PT_SPC       18
-#define PT_CCS       19
-#define PT_SRP       20
-#define PT_ERP       21    /* This is actually the debugged process' PC */
-#define PT_EXS       22
-#define PT_EDA       23
-#define PT_USP       24    /* special case - USP is not in the pt_regs */
-#define PT_PPC       25    /* special case - pseudo PC */
-#define PT_BP        26    /* Base number for BP registers. */
-#define PT_BP_CTRL   26    /* BP control register. */
-#define PT_MAX       40
-
-/* Condition code bit numbers. */
-#define C_CCS_BITNR 0
-#define V_CCS_BITNR 1
-#define Z_CCS_BITNR 2
-#define N_CCS_BITNR 3
-#define X_CCS_BITNR 4
-#define I_CCS_BITNR 5
-#define U_CCS_BITNR 6
-#define P_CCS_BITNR 7
-#define R_CCS_BITNR 8
-#define S_CCS_BITNR 9
-#define M_CCS_BITNR 30
-#define Q_CCS_BITNR 31
-#define CCS_SHIFT   10 /* Shift count for each level in CCS */
-
-/* pt_regs not only specifices the format in the user-struct during
- * ptrace but is also the frame format used in the kernel prologue/epilogues
- * themselves
- */
-
-struct pt_regs {
-	unsigned long orig_r10;
-	/* pushed by movem r13, [sp] in SAVE_ALL. */
-	unsigned long r0;
-	unsigned long r1;
-	unsigned long r2;
-	unsigned long r3;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long r11;
-	unsigned long r12;
-	unsigned long r13;
-	unsigned long acr;
-	unsigned long srs;
-	unsigned long mof;
-	unsigned long spc;
-	unsigned long ccs;
-	unsigned long srp;
-	unsigned long erp; /* This is actually the debugged process' PC */
-	/* For debugging purposes; saved only when needed. */
-	unsigned long exs;
-	unsigned long eda;
-};
-
-/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S)
- * when doing a context-switch. it is used (apart from in resume) when a new
- * thread is made and we need to make _resume (which is starting it for the
- * first time) realise what is going on.
- *
- * Actually, the use is very close to the thread struct (TSS) in that both the
- * switch_stack and the TSS are used to keep thread stuff when switching in
- * _resume.
- */
-
-struct switch_stack {
-	unsigned long r0;
-	unsigned long r1;
-	unsigned long r2;
-	unsigned long r3;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long return_ip; /* ip that _resume will return to */
-};
-
-#ifdef __KERNEL__
-
-#define user_mode(regs) (((regs)->ccs & (1 << (U_CCS_BITNR + CCS_SHIFT))) != 0)
-#define instruction_pointer(regs) ((regs)->erp)
-extern void show_regs(struct pt_regs *);
-#define profile_pc(regs) instruction_pointer(regs)
-
-#endif  /*  __KERNEL__  */
-
-#endif
diff --git a/include/asm-cris/arch-v32/spinlock.h b/include/asm-cris/arch-v32/spinlock.h
deleted file mode 100644
index 0d5709b983a1..000000000000
--- a/include/asm-cris/arch-v32/spinlock.h
+++ /dev/null
@@ -1,129 +0,0 @@
-#ifndef __ASM_ARCH_SPINLOCK_H
-#define __ASM_ARCH_SPINLOCK_H
-
-#include <linux/spinlock_types.h>
-
-#define RW_LOCK_BIAS 0x01000000
-
-extern void cris_spin_unlock(void *l, int val);
-extern void cris_spin_lock(void *l);
-extern int cris_spin_trylock(void *l);
-
-static inline int __raw_spin_is_locked(raw_spinlock_t *x)
-{
-	return *(volatile signed char *)(&(x)->slock) <= 0;
-}
-
-static inline void __raw_spin_unlock(raw_spinlock_t *lock)
-{
-	__asm__ volatile ("move.d %1,%0" \
-			  : "=m" (lock->slock) \
-			  : "r" (1) \
-			  : "memory");
-}
-
-static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
-{
-	while (__raw_spin_is_locked(lock))
-		cpu_relax();
-}
-
-static inline int __raw_spin_trylock(raw_spinlock_t *lock)
-{
-	return cris_spin_trylock((void *)&lock->slock);
-}
-
-static inline void __raw_spin_lock(raw_spinlock_t *lock)
-{
-	cris_spin_lock((void *)&lock->slock);
-}
-
-static inline void
-__raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
-{
-	__raw_spin_lock(lock);
-}
-
-/*
- * Read-write spinlocks, allowing multiple readers
- * but only one writer.
- *
- * NOTE! it is quite common to have readers in interrupts
- * but no interrupt writers. For those circumstances we
- * can "mix" irq-safe locks - any writer needs to get a
- * irq-safe write-lock, but readers can get non-irqsafe
- * read-locks.
- *
- */
-
-static inline int __raw_read_can_lock(raw_rwlock_t *x)
-{
-	return (int)(x)->lock > 0;
-}
-
-static inline int __raw_write_can_lock(raw_rwlock_t *x)
-{
-	return (x)->lock == RW_LOCK_BIAS;
-}
-
-static  inline void __raw_read_lock(raw_rwlock_t *rw)
-{
-	__raw_spin_lock(&rw->slock);
-	while (rw->lock == 0);
-	rw->lock--;
-	__raw_spin_unlock(&rw->slock);
-}
-
-static  inline void __raw_write_lock(raw_rwlock_t *rw)
-{
-	__raw_spin_lock(&rw->slock);
-	while (rw->lock != RW_LOCK_BIAS);
-	rw->lock == 0;
-	__raw_spin_unlock(&rw->slock);
-}
-
-static  inline void __raw_read_unlock(raw_rwlock_t *rw)
-{
-	__raw_spin_lock(&rw->slock);
-	rw->lock++;
-	__raw_spin_unlock(&rw->slock);
-}
-
-static  inline void __raw_write_unlock(raw_rwlock_t *rw)
-{
-	__raw_spin_lock(&rw->slock);
-	while (rw->lock != RW_LOCK_BIAS);
-	rw->lock == RW_LOCK_BIAS;
-	__raw_spin_unlock(&rw->slock);
-}
-
-static  inline int __raw_read_trylock(raw_rwlock_t *rw)
-{
-	int ret = 0;
-	__raw_spin_lock(&rw->slock);
-	if (rw->lock != 0) {
-		rw->lock--;
-		ret = 1;
-	}
-	__raw_spin_unlock(&rw->slock);
-	return ret;
-}
-
-static  inline int __raw_write_trylock(raw_rwlock_t *rw)
-{
-	int ret = 0;
-	__raw_spin_lock(&rw->slock);
-	if (rw->lock == RW_LOCK_BIAS) {
-		rw->lock == 0;
-		ret = 1;
-	}
-	__raw_spin_unlock(&rw->slock);
-	return 1;
-}
-
-
-#define _raw_spin_relax(lock)	cpu_relax()
-#define _raw_read_relax(lock)	cpu_relax()
-#define _raw_write_relax(lock)	cpu_relax()
-
-#endif /* __ASM_ARCH_SPINLOCK_H */
diff --git a/include/asm-cris/arch-v32/system.h b/include/asm-cris/arch-v32/system.h
deleted file mode 100644
index 6ca90f1f110a..000000000000
--- a/include/asm-cris/arch-v32/system.h
+++ /dev/null
@@ -1,69 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_SYSTEM_H
-#define _ASM_CRIS_ARCH_SYSTEM_H
-
-
-/* Read the CPU version register. */
-static inline unsigned long rdvr(void)
-{
-	unsigned char vr;
-
-	__asm__ __volatile__ ("move $vr, %0" : "=rm" (vr));
-	return vr;
-}
-
-#define cris_machine_name "crisv32"
-
-/* Read the user-mode stack pointer. */
-static inline unsigned long rdusp(void)
-{
-	unsigned long usp;
-
-	__asm__ __volatile__ ("move $usp, %0" : "=rm" (usp));
-	return usp;
-}
-
-/* Read the current stack pointer. */
-static inline unsigned long rdsp(void)
-{
-	unsigned long sp;
-
-	__asm__ __volatile__ ("move.d $sp, %0" : "=rm" (sp));
-	return sp;
-}
-
-/* Write the user-mode stack pointer. */
-#define wrusp(usp) __asm__ __volatile__ ("move %0, $usp" : : "rm" (usp))
-
-#define nop() __asm__ __volatile__ ("nop");
-
-#define xchg(ptr,x) \
-	((__typeof__(*(ptr)))__xchg((unsigned long) (x),(ptr),sizeof(*(ptr))))
-
-#define tas(ptr) (xchg((ptr),1))
-
-struct __xchg_dummy { unsigned long a[100]; };
-#define __xg(x) ((struct __xchg_dummy *)(x))
-
-/* Used for interrupt control. */
-#define local_save_flags(x) \
-	__asm__ __volatile__ ("move $ccs, %0" : "=rm" (x) : : "memory");
-
-#define local_irq_restore(x) \
-	__asm__ __volatile__ ("move %0, $ccs" : : "rm" (x) : "memory");
-
-#define local_irq_disable()  __asm__ __volatile__ ("di" : : : "memory");
-#define local_irq_enable()   __asm__ __volatile__ ("ei" : : : "memory");
-
-#define irqs_disabled()		\
-({				\
-	unsigned long flags;	\
-				\
-	local_save_flags(flags);\
-	!(flags & (1 << I_CCS_BITNR));	\
-})
-
-/* Used for spinlocks, etc. */
-#define local_irq_save(x) \
-	__asm__ __volatile__ ("move $ccs, %0\n\tdi" : "=rm" (x) : : "memory");
-
-#endif /* _ASM_CRIS_ARCH_SYSTEM_H */
diff --git a/include/asm-cris/arch-v32/thread_info.h b/include/asm-cris/arch-v32/thread_info.h
deleted file mode 100644
index d6936956a3c6..000000000000
--- a/include/asm-cris/arch-v32/thread_info.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_THREAD_INFO_H
-#define _ASM_CRIS_ARCH_THREAD_INFO_H
-
-/* Return a thread_info struct. */
-static inline struct thread_info *current_thread_info(void)
-{
-	struct thread_info *ti;
-
-	__asm__ __volatile__ ("and.d $sp, %0" : "=r" (ti) : "0" (~8191UL));
-	return ti;
-}
-
-#endif /* _ASM_CRIS_ARCH_THREAD_INFO_H */
diff --git a/include/asm-cris/arch-v32/timex.h b/include/asm-cris/arch-v32/timex.h
deleted file mode 100644
index 2591d3c5ed9d..000000000000
--- a/include/asm-cris/arch-v32/timex.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_TIMEX_H
-#define _ASM_CRIS_ARCH_TIMEX_H
-
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/timer_defs.h>
-
-/*
- * The clock runs at 100MHz, we divide it by 1000000. If you change anything
- * here you must check time.c as well.
- */
-
-#define CLOCK_TICK_RATE 100000000	/* Underlying frequency of the HZ timer */
-
-/* The timer0 values gives 10 ns resolution but interrupts at HZ. */
-#define TIMER0_FREQ (CLOCK_TICK_RATE)
-#define TIMER0_DIV (TIMER0_FREQ/(HZ))
-
-/* Convert the value in step of 10 ns to 1us without overflow: */
-#define GET_JIFFIES_USEC() \
-	((TIMER0_DIV - REG_RD(timer, regi_timer0, r_tmr0_data)) / 100)
-
-extern unsigned long get_ns_in_jiffie(void);
-
-static inline unsigned long get_us_in_jiffie_highres(void)
-{
-	return get_ns_in_jiffie() / 1000;
-}
-
-#endif
-
diff --git a/include/asm-cris/arch-v32/tlb.h b/include/asm-cris/arch-v32/tlb.h
deleted file mode 100644
index 4effb1253660..000000000000
--- a/include/asm-cris/arch-v32/tlb.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef _CRIS_ARCH_TLB_H
-#define _CRIS_ARCH_TLB_H
-
-/*
- * The TLB is a 64-entry cache. Each entry has a 8-bit page_id that is used
- * to store the "process" it belongs to (=> fast mm context switch). The
- * last page_id is never used so we can make TLB entries that never matches.
- */
-#define NUM_TLB_ENTRIES 64
-#define NUM_PAGEID 256
-#define INVALID_PAGEID 255
-#define NO_CONTEXT -1
-
-#endif /* _CRIS_ARCH_TLB_H */
diff --git a/include/asm-cris/arch-v32/uaccess.h b/include/asm-cris/arch-v32/uaccess.h
deleted file mode 100644
index 6b207f1b6622..000000000000
--- a/include/asm-cris/arch-v32/uaccess.h
+++ /dev/null
@@ -1,748 +0,0 @@
-/*
- * Authors:    Hans-Peter Nilsson (hp@axis.com)
- *
- */
-#ifndef _CRIS_ARCH_UACCESS_H
-#define _CRIS_ARCH_UACCESS_H
-
-/*
- * We don't tell gcc that we are accessing memory, but this is OK
- * because we do not write to any memory gcc knows about, so there
- * are no aliasing issues.
- *
- * Note that PC at a fault is the address *at* the faulting
- * instruction for CRISv32.
- */
-#define __put_user_asm(x, addr, err, op)			\
-	__asm__ __volatile__(					\
-		"2:	"op" %1,[%2]\n"				\
-		"4:\n"						\
-		"	.section .fixup,\"ax\"\n"		\
-		"3:	move.d %3,%0\n"				\
-		"	jump 4b\n"				\
-		"	nop\n"					\
-		"	.previous\n"				\
-		"	.section __ex_table,\"a\"\n"		\
-		"	.dword 2b,3b\n"				\
-		"	.previous\n"				\
-		: "=r" (err)					\
-		: "r" (x), "r" (addr), "g" (-EFAULT), "0" (err))
-
-#define __put_user_asm_64(x, addr, err) do {			\
-	int dummy_for_put_user_asm_64_;				\
-	__asm__ __volatile__(					\
-		"2:	move.d %M2,[%1+]\n"			\
-		"4:	move.d %H2,[%1]\n"			\
-		"5:\n"						\
-		"	.section .fixup,\"ax\"\n"		\
-		"3:	move.d %4,%0\n"				\
-		"	jump 5b\n"				\
-		"	.previous\n"				\
-		"	.section __ex_table,\"a\"\n"		\
-		"	.dword 2b,3b\n"				\
-		"	.dword 4b,3b\n"				\
-		"	.previous\n"				\
-		: "=r" (err), "=b" (dummy_for_put_user_asm_64_)	\
-		: "r" (x), "1" (addr), "g" (-EFAULT),		\
-		  "0" (err));					\
-	} while (0)
-
-/* See comment before __put_user_asm.  */
-
-#define __get_user_asm(x, addr, err, op)		\
-	__asm__ __volatile__(				\
-		"2:	"op" [%2],%1\n"			\
-		"4:\n"					\
-		"	.section .fixup,\"ax\"\n"	\
-		"3:	move.d %3,%0\n"			\
-		"	jump 4b\n"			\
-		"	moveq 0,%1\n"			\
-		"	.previous\n"			\
-		"	.section __ex_table,\"a\"\n"	\
-		"	.dword 2b,3b\n"			\
-		"	.previous\n"			\
-		: "=r" (err), "=r" (x)			\
-		: "r" (addr), "g" (-EFAULT), "0" (err))
-
-#define __get_user_asm_64(x, addr, err) do {		\
-	int dummy_for_get_user_asm_64_;			\
-	__asm__ __volatile__(				\
-		"2:	move.d [%2+],%M1\n"		\
-		"4:	move.d [%2],%H1\n"		\
-		"5:\n"					\
-		"	.section .fixup,\"ax\"\n"	\
-		"3:	move.d %4,%0\n"			\
-		"	jump 5b\n"			\
-		"	moveq 0,%1\n"			\
-		"	.previous\n"			\
-		"	.section __ex_table,\"a\"\n"	\
-		"	.dword 2b,3b\n"			\
-		"	.dword 4b,3b\n"			\
-		"	.previous\n"			\
-		: "=r" (err), "=r" (x),			\
-		  "=b" (dummy_for_get_user_asm_64_)	\
-		: "2" (addr), "g" (-EFAULT), "0" (err));\
-	} while (0)
-
-/*
- * Copy a null terminated string from userspace.
- *
- * Must return:
- * -EFAULT		for an exception
- * count		if we hit the buffer limit
- * bytes copied		if we hit a null byte
- * (without the null byte)
- */
-static inline long
-__do_strncpy_from_user(char *dst, const char *src, long count)
-{
-	long res;
-
-	if (count == 0)
-		return 0;
-
-	/*
-	 * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop.
-	 *  So do we.
-	 *
-	 *  This code is deduced from:
-	 *
-	 *	char tmp2;
-	 *	long tmp1, tmp3;
-	 *	tmp1 = count;
-	 *	while ((*dst++ = (tmp2 = *src++)) != 0
-	 *	       && --tmp1)
-	 *	  ;
-	 *
-	 *	res = count - tmp1;
-	 *
-	 *  with tweaks.
-	 */
-
-	__asm__ __volatile__ (
-		"	move.d %3,%0\n"
-		"5:	move.b [%2+],$acr\n"
-		"1:	beq 2f\n"
-		"	move.b $acr,[%1+]\n"
-
-		"	subq 1,%0\n"
-		"2:	bne 1b\n"
-		"	move.b [%2+],$acr\n"
-
-		"	sub.d %3,%0\n"
-		"	neg.d %0,%0\n"
-		"3:\n"
-		"	.section .fixup,\"ax\"\n"
-		"4:	move.d %7,%0\n"
-		"	jump 3b\n"
-		"	nop\n"
-
-		/* The address for a fault at the first move is trivial.
-		   The address for a fault at the second move is that of
-		   the preceding branch insn, since the move insn is in
-		   its delay-slot.  That address is also a branch
-		   target.  Just so you don't get confused...  */
-		"	.previous\n"
-		"	.section __ex_table,\"a\"\n"
-		"	.dword 5b,4b\n"
-		"	.dword 2b,4b\n"
-		"	.previous"
-		: "=r" (res), "=b" (dst), "=b" (src), "=r" (count)
-		: "3" (count), "1" (dst), "2" (src), "g" (-EFAULT)
-		: "acr");
-
-	return res;
-}
-
-/* A few copy asms to build up the more complex ones from.
-
-   Note again, a post-increment is performed regardless of whether a bus
-   fault occurred in that instruction, and PC for a faulted insn is the
-   address for the insn, or for the preceding branch when in a delay-slot.  */
-
-#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm__ __volatile__ (				\
-			COPY				\
-		"1:\n"					\
-		"	.section .fixup,\"ax\"\n"	\
-			FIXUP				\
-		"	.previous\n"			\
-		"	.section __ex_table,\"a\"\n"	\
-			TENTRY				\
-		"	.previous\n"			\
-		: "=b" (to), "=b" (from), "=r" (ret)	\
-		: "0" (to), "1" (from), "2" (ret)	\
-		: "acr", "memory")
-
-#define __asm_copy_from_user_1(to, from, ret) \
-	__asm_copy_user_cont(to, from, ret,	\
-		"2:	move.b [%1+],$acr\n"	\
-		"	move.b $acr,[%0+]\n",	\
-		"3:	addq 1,%2\n"		\
-		"	jump 1b\n"		\
-		"	clear.b [%0+]\n",	\
-		"	.dword 2b,3b\n")
-
-#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_user_cont(to, from, ret,		\
-			COPY				\
-		"2:	move.w [%1+],$acr\n"		\
-		"	move.w $acr,[%0+]\n",		\
-			FIXUP				\
-		"3:	addq 2,%2\n"			\
-		"	jump 1b\n"			\
-		"	clear.w [%0+]\n",		\
-			TENTRY				\
-		"	.dword 2b,3b\n")
-
-#define __asm_copy_from_user_2(to, from, ret) \
-	__asm_copy_from_user_2x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_3(to, from, ret)		\
-	__asm_copy_from_user_2x_cont(to, from, ret,	\
-		"4:	move.b [%1+],$acr\n"		\
-		"	move.b $acr,[%0+]\n",		\
-		"5:	addq 1,%2\n"			\
-		"	clear.b [%0+]\n",		\
-		"	.dword 4b,5b\n")
-
-#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_user_cont(to, from, ret,		\
-			COPY				\
-		"2:	move.d [%1+],$acr\n"		\
-		"	move.d $acr,[%0+]\n",		\
-			FIXUP				\
-		"3:	addq 4,%2\n"			\
-		"	jump 1b\n"			\
-		"	clear.d [%0+]\n",		\
-			TENTRY				\
-		"	.dword 2b,3b\n")
-
-#define __asm_copy_from_user_4(to, from, ret) \
-	__asm_copy_from_user_4x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_5(to, from, ret) \
-	__asm_copy_from_user_4x_cont(to, from, ret,	\
-		"4:	move.b [%1+],$acr\n"		\
-		"	move.b $acr,[%0+]\n",		\
-		"5:	addq 1,%2\n"			\
-		"	clear.b [%0+]\n",		\
-		"	.dword 4b,5b\n")
-
-#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_from_user_4x_cont(to, from, ret,	\
-			COPY				\
-		"4:	move.w [%1+],$acr\n"		\
-		"	move.w $acr,[%0+]\n",		\
-			FIXUP				\
-		"5:	addq 2,%2\n"			\
-		"	clear.w [%0+]\n",		\
-			TENTRY				\
-		"	.dword 4b,5b\n")
-
-#define __asm_copy_from_user_6(to, from, ret) \
-	__asm_copy_from_user_6x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_7(to, from, ret) \
-	__asm_copy_from_user_6x_cont(to, from, ret,	\
-		"6:	move.b [%1+],$acr\n"		\
-		"	move.b $acr,[%0+]\n",		\
-		"7:	addq 1,%2\n"			\
-		"	clear.b [%0+]\n",		\
-		"	.dword 6b,7b\n")
-
-#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_from_user_4x_cont(to, from, ret,	\
-			COPY				\
-		"4:	move.d [%1+],$acr\n"		\
-		"	move.d $acr,[%0+]\n",		\
-			FIXUP				\
-		"5:	addq 4,%2\n"			\
-		"	clear.d [%0+]\n",		\
-			TENTRY				\
-		"	.dword 4b,5b\n")
-
-#define __asm_copy_from_user_8(to, from, ret) \
-	__asm_copy_from_user_8x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_9(to, from, ret) \
-	__asm_copy_from_user_8x_cont(to, from, ret,	\
-		"6:	move.b [%1+],$acr\n"		\
-		"	move.b $acr,[%0+]\n",		\
-		"7:	addq 1,%2\n"			\
-		"	clear.b [%0+]\n",		\
-		"	.dword 6b,7b\n")
-
-#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_from_user_8x_cont(to, from, ret,	\
-			COPY				\
-		"6:	move.w [%1+],$acr\n"		\
-		"	move.w $acr,[%0+]\n",		\
-			FIXUP				\
-		"7:	addq 2,%2\n"			\
-		"	clear.w [%0+]\n",		\
-			TENTRY				\
-		"	.dword 6b,7b\n")
-
-#define __asm_copy_from_user_10(to, from, ret) \
-	__asm_copy_from_user_10x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_11(to, from, ret)		\
-	__asm_copy_from_user_10x_cont(to, from, ret,	\
-		"8:	move.b [%1+],$acr\n"		\
-		"	move.b $acr,[%0+]\n",		\
-		"9:	addq 1,%2\n"			\
-		"	clear.b [%0+]\n",		\
-		"	.dword 8b,9b\n")
-
-#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_from_user_8x_cont(to, from, ret,	\
-			COPY				\
-		"6:	move.d [%1+],$acr\n"		\
-		"	move.d $acr,[%0+]\n",		\
-			FIXUP				\
-		"7:	addq 4,%2\n"			\
-		"	clear.d [%0+]\n",		\
-			TENTRY				\
-		"	.dword 6b,7b\n")
-
-#define __asm_copy_from_user_12(to, from, ret) \
-	__asm_copy_from_user_12x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_13(to, from, ret) \
-	__asm_copy_from_user_12x_cont(to, from, ret,	\
-		"8:	move.b [%1+],$acr\n"		\
-		"	move.b $acr,[%0+]\n",		\
-		"9:	addq 1,%2\n"			\
-		"	clear.b [%0+]\n",		\
-		"	.dword 8b,9b\n")
-
-#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_from_user_12x_cont(to, from, ret,	\
-			COPY				\
-		"8:	move.w [%1+],$acr\n"		\
-		"	move.w $acr,[%0+]\n",		\
-			FIXUP				\
-		"9:	addq 2,%2\n"			\
-		"	clear.w [%0+]\n",		\
-			TENTRY				\
-		"	.dword 8b,9b\n")
-
-#define __asm_copy_from_user_14(to, from, ret) \
-	__asm_copy_from_user_14x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_15(to, from, ret) \
-	__asm_copy_from_user_14x_cont(to, from, ret,	\
-		"10:	move.b [%1+],$acr\n"		\
-		"	move.b $acr,[%0+]\n",		\
-		"11:	addq 1,%2\n"			\
-		"	clear.b [%0+]\n",		\
-		"	.dword 10b,11b\n")
-
-#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_from_user_12x_cont(to, from, ret,	\
-			COPY				\
-		"8:	move.d [%1+],$acr\n"		\
-		"	move.d $acr,[%0+]\n",		\
-			FIXUP				\
-		"9:	addq 4,%2\n"			\
-		"	clear.d [%0+]\n",		\
-			TENTRY				\
-		"	.dword 8b,9b\n")
-
-#define __asm_copy_from_user_16(to, from, ret) \
-	__asm_copy_from_user_16x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_from_user_16x_cont(to, from, ret,	\
-			COPY				\
-		"10:	move.d [%1+],$acr\n"		\
-		"	move.d $acr,[%0+]\n",		\
-			FIXUP				\
-		"11:	addq 4,%2\n"			\
-		"	clear.d [%0+]\n",		\
-			TENTRY				\
-		"	.dword 10b,11b\n")
-
-#define __asm_copy_from_user_20(to, from, ret) \
-	__asm_copy_from_user_20x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_from_user_20x_cont(to, from, ret,	\
-			COPY				\
-		"12:	move.d [%1+],$acr\n"		\
-		"	move.d $acr,[%0+]\n",		\
-			FIXUP				\
-		"13:	addq 4,%2\n"			\
-		"	clear.d [%0+]\n",		\
-			TENTRY				\
-		"	.dword 12b,13b\n")
-
-#define __asm_copy_from_user_24(to, from, ret) \
-	__asm_copy_from_user_24x_cont(to, from, ret, "", "", "")
-
-/* And now, the to-user ones.  */
-
-#define __asm_copy_to_user_1(to, from, ret)	\
-	__asm_copy_user_cont(to, from, ret,	\
-		"	move.b [%1+],$acr\n"	\
-		"2:	move.b $acr,[%0+]\n",	\
-		"3:	jump 1b\n"		\
-		"	addq 1,%2\n",		\
-		"	.dword 2b,3b\n")
-
-#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_user_cont(to, from, ret,		\
-			COPY				\
-		"	move.w [%1+],$acr\n"		\
-		"2:	move.w $acr,[%0+]\n",		\
-			FIXUP				\
-		"3:	jump 1b\n"			\
-		"	addq 2,%2\n",			\
-			TENTRY				\
-		"	.dword 2b,3b\n")
-
-#define __asm_copy_to_user_2(to, from, ret) \
-	__asm_copy_to_user_2x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_3(to, from, ret) \
-	__asm_copy_to_user_2x_cont(to, from, ret,	\
-		"	move.b [%1+],$acr\n"		\
-		"4:	move.b $acr,[%0+]\n",		\
-		"5:	addq 1,%2\n",			\
-		"	.dword 4b,5b\n")
-
-#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_user_cont(to, from, ret,		\
-			COPY				\
-		"	move.d [%1+],$acr\n"		\
-		"2:	move.d $acr,[%0+]\n",		\
-			FIXUP				\
-		"3:	jump 1b\n"			\
-		"	addq 4,%2\n",			\
-			TENTRY				\
-		"	.dword 2b,3b\n")
-
-#define __asm_copy_to_user_4(to, from, ret) \
-	__asm_copy_to_user_4x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_5(to, from, ret) \
-	__asm_copy_to_user_4x_cont(to, from, ret,	\
-		"	move.b [%1+],$acr\n"		\
-		"4:	move.b $acr,[%0+]\n",		\
-		"5:	addq 1,%2\n",			\
-		"	.dword 4b,5b\n")
-
-#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_to_user_4x_cont(to, from, ret,	\
-			COPY				\
-		"	move.w [%1+],$acr\n"		\
-		"4:	move.w $acr,[%0+]\n",		\
-			FIXUP				\
-		"5:	addq 2,%2\n",			\
-			TENTRY				\
-		"	.dword 4b,5b\n")
-
-#define __asm_copy_to_user_6(to, from, ret) \
-	__asm_copy_to_user_6x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_7(to, from, ret) \
-	__asm_copy_to_user_6x_cont(to, from, ret,	\
-		"	move.b [%1+],$acr\n"		\
-		"6:	move.b $acr,[%0+]\n",		\
-		"7:	addq 1,%2\n",			\
-		"	.dword 6b,7b\n")
-
-#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_to_user_4x_cont(to, from, ret,	\
-			COPY				\
-		"	move.d [%1+],$acr\n"		\
-		"4:	move.d $acr,[%0+]\n",		\
-			FIXUP				\
-		"5:	addq 4,%2\n",			\
-			TENTRY				\
-		"	.dword 4b,5b\n")
-
-#define __asm_copy_to_user_8(to, from, ret) \
-	__asm_copy_to_user_8x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_9(to, from, ret) \
-	__asm_copy_to_user_8x_cont(to, from, ret,	\
-		"	move.b [%1+],$acr\n"		\
-		"6:	move.b $acr,[%0+]\n",		\
-		"7:	addq 1,%2\n",			\
-		"	.dword 6b,7b\n")
-
-#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_to_user_8x_cont(to, from, ret,	\
-			COPY				\
-		"	move.w [%1+],$acr\n"		\
-		"6:	move.w $acr,[%0+]\n",		\
-			FIXUP				\
-		"7:	addq 2,%2\n",			\
-			TENTRY				\
-		"	.dword 6b,7b\n")
-
-#define __asm_copy_to_user_10(to, from, ret) \
-	__asm_copy_to_user_10x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_11(to, from, ret) \
-	__asm_copy_to_user_10x_cont(to, from, ret,	\
-		"	move.b [%1+],$acr\n"		\
-		"8:	move.b $acr,[%0+]\n",		\
-		"9:	addq 1,%2\n",			\
-		"	.dword 8b,9b\n")
-
-#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_to_user_8x_cont(to, from, ret,	\
-			COPY				\
-		"	move.d [%1+],$acr\n"		\
-		"6:	move.d $acr,[%0+]\n",		\
-			FIXUP				\
-		"7:	addq 4,%2\n",			\
-			TENTRY				\
-		"	.dword 6b,7b\n")
-
-#define __asm_copy_to_user_12(to, from, ret) \
-	__asm_copy_to_user_12x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_13(to, from, ret) \
-	__asm_copy_to_user_12x_cont(to, from, ret,	\
-		"	move.b [%1+],$acr\n"		\
-		"8:	move.b $acr,[%0+]\n",		\
-		"9:	addq 1,%2\n",			\
-		"	.dword 8b,9b\n")
-
-#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_to_user_12x_cont(to, from, ret,	\
-			COPY				\
-		"	move.w [%1+],$acr\n"		\
-		"8:	move.w $acr,[%0+]\n",		\
-			FIXUP				\
-		"9:	addq 2,%2\n",			\
-			TENTRY				\
-		"	.dword 8b,9b\n")
-
-#define __asm_copy_to_user_14(to, from, ret)	\
-	__asm_copy_to_user_14x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_15(to, from, ret) \
-	__asm_copy_to_user_14x_cont(to, from, ret,	\
-		"	move.b [%1+],$acr\n"		\
-		"10:	move.b $acr,[%0+]\n",		\
-		"11:	addq 1,%2\n",			\
-		"	.dword 10b,11b\n")
-
-#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_to_user_12x_cont(to, from, ret,	\
-			COPY				\
-		"	move.d [%1+],$acr\n"		\
-		"8:	move.d $acr,[%0+]\n",		\
-			FIXUP				\
-		"9:	addq 4,%2\n",			\
-			TENTRY				\
-		"	.dword 8b,9b\n")
-
-#define __asm_copy_to_user_16(to, from, ret) \
-	__asm_copy_to_user_16x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
-	__asm_copy_to_user_16x_cont(to, from, ret,	\
-			COPY				\
-		"	move.d [%1+],$acr\n"		\
-		"10:	move.d $acr,[%0+]\n",		\
-			FIXUP				\
-		"11:	addq 4,%2\n",			\
-			TENTRY				\
-		"	.dword 10b,11b\n")
-
-#define __asm_copy_to_user_20(to, from, ret) \
-	__asm_copy_to_user_20x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY)	\
-	__asm_copy_to_user_20x_cont(to, from, ret,	\
-			COPY				\
-		"	move.d [%1+],$acr\n"		\
-		"12:	move.d $acr,[%0+]\n",		\
-			FIXUP				\
-		"13:	addq 4,%2\n",			\
-			TENTRY				\
-		"	.dword 12b,13b\n")
-
-#define __asm_copy_to_user_24(to, from, ret)	\
-	__asm_copy_to_user_24x_cont(to, from, ret, "", "", "")
-
-/* Define a few clearing asms with exception handlers.  */
-
-/* This frame-asm is like the __asm_copy_user_cont one, but has one less
-   input.  */
-
-#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \
-	__asm__ __volatile__ (				\
-			CLEAR				\
-		"1:\n"					\
-		"	.section .fixup,\"ax\"\n"	\
-			FIXUP				\
-		"	.previous\n"			\
-		"	.section __ex_table,\"a\"\n"	\
-			TENTRY				\
-		"	.previous"			\
-		: "=b" (to), "=r" (ret)			\
-		: "0" (to), "1" (ret)			\
-		: "memory")
-
-#define __asm_clear_1(to, ret) \
-	__asm_clear(to, ret,			\
-		"2:	clear.b [%0+]\n",	\
-		"3:	jump 1b\n"		\
-		"	addq 1,%1\n",		\
-		"	.dword 2b,3b\n")
-
-#define __asm_clear_2(to, ret) \
-	__asm_clear(to, ret,			\
-		"2:	clear.w [%0+]\n",	\
-		"3:	jump 1b\n"		\
-		"	addq 2,%1\n",		\
-		"	.dword 2b,3b\n")
-
-#define __asm_clear_3(to, ret) \
-     __asm_clear(to, ret,			\
-		 "2:	clear.w [%0+]\n"	\
-		 "3:	clear.b [%0+]\n",	\
-		 "4:	addq 2,%1\n"		\
-		 "5:	jump 1b\n"		\
-		 "	addq 1,%1\n",		\
-		 "	.dword 2b,4b\n"		\
-		 "	.dword 3b,5b\n")
-
-#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
-	__asm_clear(to, ret,				\
-			CLEAR				\
-		"2:	clear.d [%0+]\n",		\
-			FIXUP				\
-		"3:	jump 1b\n"			\
-		"	addq 4,%1\n",			\
-			TENTRY				\
-		"	.dword 2b,3b\n")
-
-#define __asm_clear_4(to, ret) \
-	__asm_clear_4x_cont(to, ret, "", "", "")
-
-#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
-	__asm_clear_4x_cont(to, ret,			\
-			CLEAR				\
-		"4:	clear.d [%0+]\n",		\
-			FIXUP				\
-		"5:	addq 4,%1\n",			\
-			TENTRY				\
-		"	.dword 4b,5b\n")
-
-#define __asm_clear_8(to, ret) \
-	__asm_clear_8x_cont(to, ret, "", "", "")
-
-#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
-	__asm_clear_8x_cont(to, ret,			\
-			CLEAR				\
-		"6:	clear.d [%0+]\n",		\
-			FIXUP				\
-		"7:	addq 4,%1\n",			\
-			TENTRY				\
-		"	.dword 6b,7b\n")
-
-#define __asm_clear_12(to, ret) \
-	__asm_clear_12x_cont(to, ret, "", "", "")
-
-#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
-	__asm_clear_12x_cont(to, ret,			\
-			CLEAR				\
-		"8:	clear.d [%0+]\n",		\
-			FIXUP				\
-		"9:	addq 4,%1\n",			\
-			TENTRY				\
-		"	.dword 8b,9b\n")
-
-#define __asm_clear_16(to, ret) \
-	__asm_clear_16x_cont(to, ret, "", "", "")
-
-#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
-	__asm_clear_16x_cont(to, ret,			\
-			CLEAR				\
-		"10:	clear.d [%0+]\n",		\
-			FIXUP				\
-		"11:	addq 4,%1\n",			\
-			TENTRY				\
-		"	.dword 10b,11b\n")
-
-#define __asm_clear_20(to, ret) \
-	__asm_clear_20x_cont(to, ret, "", "", "")
-
-#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
-	__asm_clear_20x_cont(to, ret,			\
-			CLEAR				\
-		"12:	clear.d [%0+]\n",		\
-			FIXUP				\
-		"13:	addq 4,%1\n",			\
-			TENTRY				\
-		"	.dword 12b,13b\n")
-
-#define __asm_clear_24(to, ret) \
-	__asm_clear_24x_cont(to, ret, "", "", "")
-
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return length of string in userspace including terminating 0
- * or 0 for error.  Return a value greater than N if too long.
- */
-
-static inline long
-strnlen_user(const char *s, long n)
-{
-	long res, tmp1;
-
-	if (!access_ok(VERIFY_READ, s, 0))
-		return 0;
-
-	/*
-	 * This code is deduced from:
-	 *
-	 *	tmp1 = n;
-	 *	while (tmp1-- > 0 && *s++)
-	 *	  ;
-	 *
-	 *	res = n - tmp1;
-	 *
-	 *  (with tweaks).
-	 */
-
-	__asm__ __volatile__ (
-		"	move.d %1,$acr\n"
-		"	cmpq 0,$acr\n"
-		"0:\n"
-		"	ble 1f\n"
-		"	subq 1,$acr\n"
-
-		"4:	test.b [%0+]\n"
-		"	bne 0b\n"
-		"	cmpq 0,$acr\n"
-		"1:\n"
-		"	move.d %1,%0\n"
-		"	sub.d $acr,%0\n"
-		"2:\n"
-		"	.section .fixup,\"ax\"\n"
-
-		"3:	jump 2b\n"
-		"	clear.d %0\n"
-
-		"	.previous\n"
-		"	.section __ex_table,\"a\"\n"
-		"	.dword 4b,3b\n"
-		"	.previous\n"
-		: "=r" (res), "=r" (tmp1)
-		: "0" (s), "1" (n)
-		: "acr");
-
-	return res;
-}
-
-#endif
diff --git a/include/asm-cris/arch-v32/unistd.h b/include/asm-cris/arch-v32/unistd.h
deleted file mode 100644
index 0051114c63c7..000000000000
--- a/include/asm-cris/arch-v32/unistd.h
+++ /dev/null
@@ -1,155 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_UNISTD_H_
-#define _ASM_CRIS_ARCH_UNISTD_H_
-
-/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
-/*
- * Don't remove the .ifnc tests; they are an insurance against
- * any hard-to-spot gcc register allocation bugs.
- */
-#define _syscall0(type,name) \
-type name(void) \
-{ \
-  register long __a __asm__ ("r10"); \
-  register long __n_ __asm__ ("r9") = (__NR_##name); \
-  __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
-			".err\n\t" \
-			".endif\n\t" \
-			"break 13" \
-			: "=r" (__a) \
-			: "r" (__n_) \
-			: "memory"); \
-  if (__a >= 0) \
-     return (type) __a; \
-  errno = -__a; \
-  return (type) -1; \
-}
-
-#define _syscall1(type,name,type1,arg1) \
-type name(type1 arg1) \
-{ \
-  register long __a __asm__ ("r10") = (long) arg1; \
-  register long __n_ __asm__ ("r9") = (__NR_##name); \
-  __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
-			".err\n\t" \
-			".endif\n\t" \
-			"break 13" \
-			: "=r" (__a) \
-			: "r" (__n_), "0" (__a) \
-			: "memory"); \
-  if (__a >= 0) \
-     return (type) __a; \
-  errno = -__a; \
-  return (type) -1; \
-}
-
-#define _syscall2(type,name,type1,arg1,type2,arg2) \
-type name(type1 arg1,type2 arg2) \
-{ \
-  register long __a __asm__ ("r10") = (long) arg1; \
-  register long __b __asm__ ("r11") = (long) arg2; \
-  register long __n_ __asm__ ("r9") = (__NR_##name); \
-  __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \
-			".err\n\t" \
-			".endif\n\t" \
-			"break 13" \
-			: "=r" (__a) \
-			: "r" (__n_), "0" (__a), "r" (__b) \
-			: "memory"); \
-  if (__a >= 0) \
-     return (type) __a; \
-  errno = -__a; \
-  return (type) -1; \
-}
-
-#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
-type name(type1 arg1,type2 arg2,type3 arg3) \
-{ \
-  register long __a __asm__ ("r10") = (long) arg1; \
-  register long __b __asm__ ("r11") = (long) arg2; \
-  register long __c __asm__ ("r12") = (long) arg3; \
-  register long __n_ __asm__ ("r9") = (__NR_##name); \
-  __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \
-			".err\n\t" \
-			".endif\n\t" \
-			"break 13" \
-			: "=r" (__a) \
-			: "r" (__n_), "0" (__a), "r" (__b), "r" (__c) \
-			: "memory"); \
-  if (__a >= 0) \
-     return (type) __a; \
-  errno = -__a; \
-  return (type) -1; \
-}
-
-#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
-type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
-{ \
-  register long __a __asm__ ("r10") = (long) arg1; \
-  register long __b __asm__ ("r11") = (long) arg2; \
-  register long __c __asm__ ("r12") = (long) arg3; \
-  register long __d __asm__ ("r13") = (long) arg4; \
-  register long __n_ __asm__ ("r9") = (__NR_##name); \
-  __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
-			".err\n\t" \
-			".endif\n\t" \
-			"break 13" \
-			: "=r" (__a) \
-			: "r" (__n_), "0" (__a), "r" (__b), \
-			  "r" (__c), "r" (__d)\
-			: "memory"); \
-  if (__a >= 0) \
-     return (type) __a; \
-  errno = -__a; \
-  return (type) -1; \
-}
-
-#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
-	  type5,arg5) \
-type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \
-{ \
-  register long __a __asm__ ("r10") = (long) arg1; \
-  register long __b __asm__ ("r11") = (long) arg2; \
-  register long __c __asm__ ("r12") = (long) arg3; \
-  register long __d __asm__ ("r13") = (long) arg4; \
-  register long __e __asm__ ("mof") = (long) arg5; \
-  register long __n_ __asm__ ("r9") = (__NR_##name); \
-  __asm__ __volatile__ (".ifnc %0%1%3%4%5%6,$r10$r9$r11$r12$r13$mof\n\t" \
-			".err\n\t" \
-			".endif\n\t" \
-			"break 13" \
-			: "=r" (__a) \
-			: "r" (__n_), "0" (__a), "r" (__b), \
-			  "r" (__c), "r" (__d), "h" (__e) \
-			: "memory"); \
-  if (__a >= 0) \
-     return (type) __a; \
-  errno = -__a; \
-  return (type) -1; \
-}
-
-#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
-	  type5,arg5,type6,arg6) \
-type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \
-{ \
-  register long __a __asm__ ("r10") = (long) arg1; \
-  register long __b __asm__ ("r11") = (long) arg2; \
-  register long __c __asm__ ("r12") = (long) arg3; \
-  register long __d __asm__ ("r13") = (long) arg4; \
-  register long __e __asm__ ("mof") = (long) arg5; \
-  register long __f __asm__ ("srp") = (long) arg6; \
-  register long __n_ __asm__ ("r9") = (__NR_##name); \
-  __asm__ __volatile__ (".ifnc %0%1%3%4%5%6%7,$r10$r9$r11$r12$r13$mof$srp\n\t" \
-			".err\n\t" \
-			".endif\n\t" \
-			"break 13" \
-			: "=r" (__a) \
-			: "r" (__n_), "0" (__a), "r" (__b), \
-			  "r" (__c), "r" (__d), "h" (__e), "x" (__f) \
-			: "memory"); \
-  if (__a >= 0) \
-     return (type) __a; \
-  errno = -__a; \
-  return (type) -1; \
-}
-
-#endif
diff --git a/include/asm-cris/arch-v32/user.h b/include/asm-cris/arch-v32/user.h
deleted file mode 100644
index 03fa1f3c3c00..000000000000
--- a/include/asm-cris/arch-v32/user.h
+++ /dev/null
@@ -1,41 +0,0 @@
-#ifndef _ASM_CRIS_ARCH_USER_H
-#define _ASM_CRIS_ARCH_USER_H
-
-/* User-mode register used for core dumps. */
-
-struct user_regs_struct {
-	unsigned long r0;	/* General registers. */
-	unsigned long r1;
-	unsigned long r2;
-	unsigned long r3;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long r11;
-	unsigned long r12;
-	unsigned long r13;
-	unsigned long sp;	/* R14, Stack pointer. */
-	unsigned long acr;	/* R15, Address calculation register. */
-	unsigned long bz;	/* P0, Constant zero (8-bits). */
-	unsigned long vr;	/* P1, Version register (8-bits). */
-	unsigned long pid;	/* P2, Process ID (8-bits). */
-	unsigned long srs;	/* P3, Support register select (8-bits). */
-	unsigned long wz;	/* P4, Constant zero (16-bits). */
-	unsigned long exs;	/* P5, Exception status. */
-	unsigned long eda;	/* P6, Exception data address. */
-	unsigned long mof;	/* P7, Multiply overflow regiter. */
-	unsigned long dz;	/* P8, Constant zero (32-bits). */
-	unsigned long ebp;	/* P9, Exception base pointer. */
-	unsigned long erp;	/* P10, Exception return pointer. */
-	unsigned long srp;	/* P11, Subroutine return pointer. */
-	unsigned long nrp;	/* P12, NMI return pointer. */
-	unsigned long ccs;	/* P13, Condition code stack. */
-	unsigned long usp;	/* P14, User mode stack pointer. */
-	unsigned long spc;	/* P15, Single step PC. */
-};
-
-#endif /* _ASM_CRIS_ARCH_USER_H */
diff --git a/include/asm-cris/atomic.h b/include/asm-cris/atomic.h
deleted file mode 100644
index 5fc87768774a..000000000000
--- a/include/asm-cris/atomic.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/* $Id: atomic.h,v 1.3 2001/07/25 16:15:19 bjornw Exp $ */
-
-#ifndef __ASM_CRIS_ATOMIC__
-#define __ASM_CRIS_ATOMIC__
-
-#include <linux/compiler.h>
-
-#include <asm/system.h>
-#include <asm/arch/atomic.h>
-
-/*
- * Atomic operations that C can't guarantee us.  Useful for
- * resource counting etc..
- */
-
-typedef struct { volatile int counter; } atomic_t;
-
-#define ATOMIC_INIT(i)  { (i) }
-
-#define atomic_read(v) ((v)->counter)
-#define atomic_set(v,i) (((v)->counter) = (i))
-
-/* These should be written in asm but we do it in C for now. */
-
-static inline void atomic_add(int i, volatile atomic_t *v)
-{
-	unsigned long flags;
-	cris_atomic_save(v, flags);
-	v->counter += i;
-	cris_atomic_restore(v, flags);
-}
-
-static inline void atomic_sub(int i, volatile atomic_t *v)
-{
-	unsigned long flags;
-	cris_atomic_save(v, flags);
-	v->counter -= i;
-	cris_atomic_restore(v, flags);
-}
-
-static inline int atomic_add_return(int i, volatile atomic_t *v)
-{
-	unsigned long flags;
-	int retval;
-	cris_atomic_save(v, flags);
-	retval = (v->counter += i);
-	cris_atomic_restore(v, flags);
-	return retval;
-}
-
-#define atomic_add_negative(a, v)	(atomic_add_return((a), (v)) < 0)
-
-static inline int atomic_sub_return(int i, volatile atomic_t *v)
-{
-	unsigned long flags;
-	int retval;
-	cris_atomic_save(v, flags);
-	retval = (v->counter -= i);
-	cris_atomic_restore(v, flags);
-	return retval;
-}
-
-static inline int atomic_sub_and_test(int i, volatile atomic_t *v)
-{
-	int retval;
-	unsigned long flags;
-	cris_atomic_save(v, flags);
-	retval = (v->counter -= i) == 0;
-	cris_atomic_restore(v, flags);
-	return retval;
-}
-
-static inline void atomic_inc(volatile atomic_t *v)
-{
-	unsigned long flags;
-	cris_atomic_save(v, flags);
-	(v->counter)++;
-	cris_atomic_restore(v, flags);
-}
-
-static inline void atomic_dec(volatile atomic_t *v)
-{
-	unsigned long flags;
-	cris_atomic_save(v, flags);
-	(v->counter)--;
-	cris_atomic_restore(v, flags);
-}
-
-static inline int atomic_inc_return(volatile atomic_t *v)
-{
-	unsigned long flags;
-	int retval;
-	cris_atomic_save(v, flags);
-	retval = ++(v->counter);
-	cris_atomic_restore(v, flags);
-	return retval;
-}
-
-static inline int atomic_dec_return(volatile atomic_t *v)
-{
-	unsigned long flags;
-	int retval;
-	cris_atomic_save(v, flags);
-	retval = --(v->counter);
-	cris_atomic_restore(v, flags);
-	return retval;
-}
-static inline int atomic_dec_and_test(volatile atomic_t *v)
-{
-	int retval;
-	unsigned long flags;
-	cris_atomic_save(v, flags);
-	retval = --(v->counter) == 0;
-	cris_atomic_restore(v, flags);
-	return retval;
-}
-
-static inline int atomic_inc_and_test(volatile atomic_t *v)
-{
-	int retval;
-	unsigned long flags;
-	cris_atomic_save(v, flags);
-	retval = ++(v->counter) == 0;
-	cris_atomic_restore(v, flags);
-	return retval;
-}
-
-static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
-{
-	int ret;
-	unsigned long flags;
-
-	cris_atomic_save(v, flags);
-	ret = v->counter;
-	if (likely(ret == old))
-		v->counter = new;
-	cris_atomic_restore(v, flags);
-	return ret;
-}
-
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-
-static inline int atomic_add_unless(atomic_t *v, int a, int u)
-{
-	int ret;
-	unsigned long flags;
-
-	cris_atomic_save(v, flags);
-	ret = v->counter;
-	if (ret != u)
-		v->counter += a;
-	cris_atomic_restore(v, flags);
-	return ret != u;
-}
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-
-/* Atomic operations are already serializing */
-#define smp_mb__before_atomic_dec()    barrier()
-#define smp_mb__after_atomic_dec()     barrier()
-#define smp_mb__before_atomic_inc()    barrier()
-#define smp_mb__after_atomic_inc()     barrier()
-
-#include <asm-generic/atomic.h>
-#endif
diff --git a/include/asm-cris/auxvec.h b/include/asm-cris/auxvec.h
deleted file mode 100644
index cb30b01bf19f..000000000000
--- a/include/asm-cris/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __ASMCRIS_AUXVEC_H
-#define __ASMCRIS_AUXVEC_H
-
-#endif
diff --git a/include/asm-cris/axisflashmap.h b/include/asm-cris/axisflashmap.h
deleted file mode 100644
index 015ca5445ddd..000000000000
--- a/include/asm-cris/axisflashmap.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef __ASM_AXISFLASHMAP_H
-#define __ASM_AXISFLASHMAP_H
-
-/* Bootblock parameters are stored at 0xc000 and has the FLASH_BOOT_MAGIC 
- * as start, it ends with 0xFFFFFFFF */
-#define FLASH_BOOT_MAGIC 0xbeefcace
-#define BOOTPARAM_OFFSET 0xc000
-/* apps/bootblocktool is used to read and write the parameters,
- * and it has nothing to do with the partition table. 
- */
-
-#define PARTITION_TABLE_OFFSET 10
-#define PARTITION_TABLE_MAGIC 0xbeef	/* Not a good magic */
-
-/* The partitiontable_head is located at offset +10: */
-struct partitiontable_head {
-	__u16 magic;	/* PARTITION_TABLE_MAGIC */
-	__u16 size;	/* Length of ptable block (entries + end marker) */
-	__u32 checksum;	/* simple longword sum, over entries + end marker  */
-};
-
-/* And followed by partition table entries */
-struct partitiontable_entry {
-	__u32 offset;		/* relative to the sector the ptable is in */
-	__u32 size;		/* in bytes */
-	__u32 checksum;		/* simple longword sum */
-	__u16 type;		/* see type codes below */
-	__u16 flags;		/* bit 0: ro/rw = 1/0 */
-	__u32 future0;		/* 16 bytes reserved for future use */
-	__u32 future1;
-	__u32 future2;
-	__u32 future3;
-};
-/* ended by an end marker: */
-#define PARTITIONTABLE_END_MARKER 0xFFFFFFFF
-#define PARTITIONTABLE_END_MARKER_SIZE 4
-
-#define PARTITIONTABLE_END_PAD	10
-
-/* Complete structure for whole partition table */
-/* note that table may end before CONFIG_ETRAX_PTABLE_ENTRIES by setting
- * offset of the last entry + 1 to PARTITIONTABLE_END_MARKER.
- */
-struct partitiontable {
-	__u8 skip[PARTITION_TABLE_OFFSET];
-	struct partitiontable_head head;
-	struct partitiontable_entry entries[];
-};
-
-#define PARTITION_TYPE_PARAM  0x0001
-#define PARTITION_TYPE_KERNEL 0x0002
-#define PARTITION_TYPE_JFFS   0x0003
-#define PARTITION_TYPE_JFFS2  0x0000
-
-#define	PARTITION_FLAGS_READONLY_MASK	0x0001
-#define	PARTITION_FLAGS_READONLY	0x0001
-
-/* The master mtd for the entire flash. */
-extern struct mtd_info *axisflash_mtd;
-
-#endif
diff --git a/include/asm-cris/bitops.h b/include/asm-cris/bitops.h
deleted file mode 100644
index 75ea6e096483..000000000000
--- a/include/asm-cris/bitops.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/* asm/bitops.h for Linux/CRIS
- *
- * TODO: asm versions if speed is needed
- *
- * All bit operations return 0 if the bit was cleared before the
- * operation and != 0 if it was not.
- *
- * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
- */
-
-#ifndef _CRIS_BITOPS_H
-#define _CRIS_BITOPS_H
-
-/* Currently this is unsuitable for consumption outside the kernel.  */
-#ifdef __KERNEL__ 
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <asm/arch/bitops.h>
-#include <asm/system.h>
-#include <asm/atomic.h>
-#include <linux/compiler.h>
-
-/*
- * set_bit - Atomically set a bit in memory
- * @nr: the bit to set
- * @addr: the address to start counting from
- *
- * This function is atomic and may not be reordered.  See __set_bit()
- * if you do not require the atomic guarantees.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-
-#define set_bit(nr, addr)    (void)test_and_set_bit(nr, addr)
-
-/*
- * clear_bit - Clears a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * clear_bit() is atomic and may not be reordered.  However, it does
- * not contain a memory barrier, so if it is used for locking purposes,
- * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
- * in order to ensure changes are visible on other processors.
- */
-
-#define clear_bit(nr, addr)  (void)test_and_clear_bit(nr, addr)
-
-/*
- * change_bit - Toggle a bit in memory
- * @nr: Bit to change
- * @addr: Address to start counting from
- *
- * change_bit() is atomic and may not be reordered.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-
-#define change_bit(nr, addr) (void)test_and_change_bit(nr, addr)
-
-/**
- * test_and_set_bit - Set a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.  
- * It also implies a memory barrier.
- */
-
-static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
-{
-	unsigned int mask, retval;
-	unsigned long flags;
-	unsigned int *adr = (unsigned int *)addr;
-	
-	adr += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	cris_atomic_save(addr, flags);
-	retval = (mask & *adr) != 0;
-	*adr |= mask;
-	cris_atomic_restore(addr, flags);
-	return retval;
-}
-
-/*
- * clear_bit() doesn't provide any barrier for the compiler.
- */
-#define smp_mb__before_clear_bit()      barrier()
-#define smp_mb__after_clear_bit()       barrier()
-
-/**
- * test_and_clear_bit - Clear a bit and return its old value
- * @nr: Bit to clear
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.  
- * It also implies a memory barrier.
- */
-
-static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
-{
-	unsigned int mask, retval;
-	unsigned long flags;
-	unsigned int *adr = (unsigned int *)addr;
-	
-	adr += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	cris_atomic_save(addr, flags);
-	retval = (mask & *adr) != 0;
-	*adr &= ~mask;
-	cris_atomic_restore(addr, flags);
-	return retval;
-}
-
-/**
- * test_and_change_bit - Change a bit and return its old value
- * @nr: Bit to change
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.  
- * It also implies a memory barrier.
- */
-
-static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
-{
-	unsigned int mask, retval;
-	unsigned long flags;
-	unsigned int *adr = (unsigned int *)addr;
-	adr += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	cris_atomic_save(addr, flags);
-	retval = (mask & *adr) != 0;
-	*adr ^= mask;
-	cris_atomic_restore(addr, flags);
-	return retval;
-}
-
-#include <asm-generic/bitops/non-atomic.h>
-
-/*
- * Since we define it "external", it collides with the built-in
- * definition, which doesn't have the same semantics.  We don't want to
- * use -fno-builtin, so just hide the name ffs.
- */
-#define ffs kernel_ffs
-
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/find.h>
-#include <asm-generic/bitops/lock.h>
-
-#include <asm-generic/bitops/ext2-non-atomic.h>
-
-#define ext2_set_bit_atomic(l,n,a)   test_and_set_bit(n,a)
-#define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a)
-
-#include <asm-generic/bitops/minix.h>
-#include <asm-generic/bitops/sched.h>
-
-#endif /* __KERNEL__ */
-
-#endif /* _CRIS_BITOPS_H */
diff --git a/include/asm-cris/bug.h b/include/asm-cris/bug.h
deleted file mode 100644
index fee12d4ae683..000000000000
--- a/include/asm-cris/bug.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _CRIS_BUG_H
-#define _CRIS_BUG_H
-#include <asm/arch/bug.h>
-#endif
diff --git a/include/asm-cris/bugs.h b/include/asm-cris/bugs.h
deleted file mode 100644
index c5907aac1007..000000000000
--- a/include/asm-cris/bugs.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* $Id: bugs.h,v 1.2 2001/01/17 17:03:18 bjornw Exp $
- *
- *  include/asm-cris/bugs.h
- *
- *  Copyright (C) 2001 Axis Communications AB
- */
-
-/*
- * This is included by init/main.c to check for architecture-dependent bugs.
- *
- * Needs:
- *	void check_bugs(void);
- */
-
-static void check_bugs(void)
-{
-}
-
-
-
-
diff --git a/include/asm-cris/byteorder.h b/include/asm-cris/byteorder.h
deleted file mode 100644
index 0cd9db1cc888..000000000000
--- a/include/asm-cris/byteorder.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef _CRIS_BYTEORDER_H
-#define _CRIS_BYTEORDER_H
-
-#ifdef __GNUC__
-
-#ifdef __KERNEL__
-#include <asm/arch/byteorder.h>
-
-/* defines are necessary because the other files detect the presence
- * of a defined __arch_swab32, not an inline
- */
-#define __arch__swab32(x) ___arch__swab32(x)
-#define __arch__swab16(x) ___arch__swab16(x)
-#endif /* __KERNEL__ */
-
-#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-#  define __BYTEORDER_HAS_U64__
-#  define __SWAB_64_THRU_32__
-#endif
-
-#endif /* __GNUC__ */
-
-#include <linux/byteorder/little_endian.h>
-
-#endif
-
-
diff --git a/include/asm-cris/cache.h b/include/asm-cris/cache.h
deleted file mode 100644
index 46a3b26e205a..000000000000
--- a/include/asm-cris/cache.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_CACHE_H
-#define _ASM_CACHE_H
-
-#include <asm/arch/cache.h>
-
-#endif /* _ASM_CACHE_H */
diff --git a/include/asm-cris/cacheflush.h b/include/asm-cris/cacheflush.h
deleted file mode 100644
index cf60e3f69f8d..000000000000
--- a/include/asm-cris/cacheflush.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef _CRIS_CACHEFLUSH_H
-#define _CRIS_CACHEFLUSH_H
-
-/* Keep includes the same across arches.  */
-#include <linux/mm.h>
-
-/* The cache doesn't need to be flushed when TLB entries change because 
- * the cache is mapped to physical memory, not virtual memory
- */
-#define flush_cache_all()			do { } while (0)
-#define flush_cache_mm(mm)			do { } while (0)
-#define flush_cache_dup_mm(mm)			do { } while (0)
-#define flush_cache_range(vma, start, end)	do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn)	do { } while (0)
-#define flush_dcache_page(page)			do { } while (0)
-#define flush_dcache_mmap_lock(mapping)		do { } while (0)
-#define flush_dcache_mmap_unlock(mapping)	do { } while (0)
-#define flush_icache_range(start, end)		do { } while (0)
-#define flush_icache_page(vma,pg)		do { } while (0)
-#define flush_icache_user_range(vma,pg,adr,len)	do { } while (0)
-#define flush_cache_vmap(start, end)		do { } while (0)
-#define flush_cache_vunmap(start, end)		do { } while (0)
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-	memcpy(dst, src, len)
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
-	memcpy(dst, src, len)
-
-int change_page_attr(struct page *page, int numpages, pgprot_t prot);
-
-#endif /* _CRIS_CACHEFLUSH_H */
diff --git a/include/asm-cris/checksum.h b/include/asm-cris/checksum.h
deleted file mode 100644
index c6c5be62c698..000000000000
--- a/include/asm-cris/checksum.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* TODO: csum_tcpudp_magic could be speeded up, and csum_fold as well */
-
-#ifndef _CRIS_CHECKSUM_H
-#define _CRIS_CHECKSUM_H
-
-#include <asm/arch/checksum.h>
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-__wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/*
- * the same as csum_partial, but copies from src while it
- * checksums
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-
-__wsum csum_partial_copy_nocheck(const void *src, void *dst,
-				       int len, __wsum sum);
-
-/*
- *	Fold a partial checksum into a word
- */
-
-static inline __sum16 csum_fold(__wsum csum)
-{
-	u32 sum = (__force u32)csum;
-	sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */
-	sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */
-	return (__force __sum16)~sum;
-}
-
-extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
-						int len, __wsum sum,
-						int *errptr);
-
-/*
- *	This is a version of ip_compute_csum() optimized for IP headers,
- *	which always checksum on 4 octet boundaries.
- *
- */
-
-static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
-{
-	return csum_fold(csum_partial(iph, ihl * 4, 0));
-}
- 
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-
-static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
-						   unsigned short len,
-						   unsigned short proto,
-						   __wsum sum)
-{
-	return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-
-static inline __sum16 ip_compute_csum(const void *buff, int len)
-{
-	return csum_fold (csum_partial(buff, len, 0));
-}
-
-#endif
diff --git a/include/asm-cris/cputime.h b/include/asm-cris/cputime.h
deleted file mode 100644
index 4446a65656fa..000000000000
--- a/include/asm-cris/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __CRIS_CPUTIME_H
-#define __CRIS_CPUTIME_H
-
-#include <asm-generic/cputime.h>
-
-#endif /* __CRIS_CPUTIME_H */
diff --git a/include/asm-cris/current.h b/include/asm-cris/current.h
deleted file mode 100644
index 5f5c0efd00be..000000000000
--- a/include/asm-cris/current.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef _CRIS_CURRENT_H
-#define _CRIS_CURRENT_H
-
-#include <linux/thread_info.h>
-
-struct task_struct;
-
-static inline struct task_struct * get_current(void)
-{
-        return current_thread_info()->task;
-}
- 
-#define current get_current()
-
-#endif /* !(_CRIS_CURRENT_H) */
diff --git a/include/asm-cris/delay.h b/include/asm-cris/delay.h
deleted file mode 100644
index 123e19aef49d..000000000000
--- a/include/asm-cris/delay.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef _CRIS_DELAY_H
-#define _CRIS_DELAY_H
-
-/*
- * Copyright (C) 1998-2002 Axis Communications AB
- *
- * Delay routines, using a pre-computed "loops_per_second" value.
- */
-
-#include <asm/arch/delay.h>
-
-/* Use only for very small delays ( < 1 msec).  */
-
-extern unsigned long loops_per_usec; /* arch/cris/mm/init.c */
-
-/* May be defined by arch/delay.h. */
-#ifndef udelay
-static inline void udelay(unsigned long usecs)
-{
-	__delay(usecs * loops_per_usec);
-}
-#endif
-
-#endif /* defined(_CRIS_DELAY_H) */
-
-
-
diff --git a/include/asm-cris/device.h b/include/asm-cris/device.h
deleted file mode 100644
index d8f9872b0e2d..000000000000
--- a/include/asm-cris/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-#include <asm-generic/device.h>
-
diff --git a/include/asm-cris/div64.h b/include/asm-cris/div64.h
deleted file mode 100644
index 6cd978cefb28..000000000000
--- a/include/asm-cris/div64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/div64.h>
diff --git a/include/asm-cris/dma-mapping.h b/include/asm-cris/dma-mapping.h
deleted file mode 100644
index da8ef8e8f842..000000000000
--- a/include/asm-cris/dma-mapping.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/* DMA mapping. Nothing tricky here, just virt_to_phys */
-
-#ifndef _ASM_CRIS_DMA_MAPPING_H
-#define _ASM_CRIS_DMA_MAPPING_H
-
-#include <linux/mm.h>
-#include <linux/kernel.h>
-
-#include <asm/cache.h>
-#include <asm/io.h>
-#include <asm/scatterlist.h>
-
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-
-#ifdef CONFIG_PCI
-#include <asm-generic/dma-coherent.h>
-
-void *dma_alloc_coherent(struct device *dev, size_t size,
-			   dma_addr_t *dma_handle, gfp_t flag);
-
-void dma_free_coherent(struct device *dev, size_t size,
-			 void *vaddr, dma_addr_t dma_handle);
-#else
-static inline void *
-dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
-                   gfp_t flag)
-{
-        BUG();
-        return NULL;
-}
-
-static inline void
-dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
-                    dma_addr_t dma_handle)
-{
-        BUG();
-}
-#endif
-static inline dma_addr_t
-dma_map_single(struct device *dev, void *ptr, size_t size,
-	       enum dma_data_direction direction)
-{
-	BUG_ON(direction == DMA_NONE);
-	return virt_to_phys(ptr);
-}
-
-static inline void
-dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
-		 enum dma_data_direction direction)
-{
-	BUG_ON(direction == DMA_NONE);
-}
-
-static inline int
-dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-	   enum dma_data_direction direction)
-{
-	printk("Map sg\n");
-	return nents;
-}
-
-static inline dma_addr_t
-dma_map_page(struct device *dev, struct page *page, unsigned long offset,
-	     size_t size, enum dma_data_direction direction)
-{
-	BUG_ON(direction == DMA_NONE);
-	return page_to_phys(page) + offset;
-}
-
-static inline void
-dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
-	       enum dma_data_direction direction)
-{
-	BUG_ON(direction == DMA_NONE);
-}
-
-
-static inline void
-dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
-	     enum dma_data_direction direction)
-{
-	BUG_ON(direction == DMA_NONE);
-}
-
-static inline void
-dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size,
-			enum dma_data_direction direction)
-{
-}
-
-static inline void
-dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size,
-			enum dma_data_direction direction)
-{
-}
-
-static inline void
-dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
-			      unsigned long offset, size_t size,
-			      enum dma_data_direction direction)
-{
-}
-
-static inline void
-dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
-				 unsigned long offset, size_t size,
-				 enum dma_data_direction direction)
-{
-}
-
-static inline void
-dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
-		    enum dma_data_direction direction)
-{
-}
-
-static inline void
-dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
-		    enum dma_data_direction direction)
-{
-}
-
-static inline int
-dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
-{
-	return 0;
-}
-
-static inline int
-dma_supported(struct device *dev, u64 mask)
-{
-        /*
-         * we fall back to GFP_DMA when the mask isn't all 1s,
-         * so we can't guarantee allocations that must be
-         * within a tighter range than GFP_DMA..
-         */
-        if(mask < 0x00ffffff)
-                return 0;
-
-	return 1;
-}
-
-static inline int
-dma_set_mask(struct device *dev, u64 mask)
-{
-	if(!dev->dma_mask || !dma_supported(dev, mask))
-		return -EIO;
-
-	*dev->dma_mask = mask;
-
-	return 0;
-}
-
-static inline int
-dma_get_cache_alignment(void)
-{
-	return (1 << INTERNODE_CACHE_SHIFT);
-}
-
-#define dma_is_consistent(d, h)	(1)
-
-static inline void
-dma_cache_sync(struct device *dev, void *vaddr, size_t size,
-	       enum dma_data_direction direction)
-{
-}
-
-
-#endif
diff --git a/include/asm-cris/dma.h b/include/asm-cris/dma.h
deleted file mode 100644
index 6f188dc56138..000000000000
--- a/include/asm-cris/dma.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* $Id: dma.h,v 1.2 2001/05/09 12:17:42 johana Exp $ */
-
-#ifndef _ASM_DMA_H
-#define _ASM_DMA_H
-
-#include <asm/arch/dma.h>
-
-/* it's useless on the Etrax, but unfortunately needed by the new
-   bootmem allocator (but this should do it for this) */
-
-#define MAX_DMA_ADDRESS PAGE_OFFSET
-
-/* From PCI */
-
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy 	(0)
-#endif
-
-#endif /* _ASM_DMA_H */
diff --git a/include/asm-cris/elf.h b/include/asm-cris/elf.h
deleted file mode 100644
index 001f64ad11e8..000000000000
--- a/include/asm-cris/elf.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef __ASMCRIS_ELF_H
-#define __ASMCRIS_ELF_H
-
-/*
- * ELF register definitions..
- */
-
-#include <asm/user.h>
-
-#define R_CRIS_NONE             0
-#define R_CRIS_8                1
-#define R_CRIS_16               2
-#define R_CRIS_32               3
-#define R_CRIS_8_PCREL          4
-#define R_CRIS_16_PCREL         5
-#define R_CRIS_32_PCREL         6
-#define R_CRIS_GNU_VTINHERIT    7
-#define R_CRIS_GNU_VTENTRY      8
-#define R_CRIS_COPY             9
-#define R_CRIS_GLOB_DAT         10
-#define R_CRIS_JUMP_SLOT        11
-#define R_CRIS_RELATIVE         12
-#define R_CRIS_16_GOT           13
-#define R_CRIS_32_GOT           14
-#define R_CRIS_16_GOTPLT        15
-#define R_CRIS_32_GOTPLT        16
-#define R_CRIS_32_GOTREL        17
-#define R_CRIS_32_PLT_GOTREL    18
-#define R_CRIS_32_PLT_PCREL     19
-
-typedef unsigned long elf_greg_t;
-
-/* Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is
-   thus exposed to user-space. */
-#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-/* A placeholder; CRIS does not have any fp regs.  */
-typedef unsigned long elf_fpregset_t;
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS	ELFCLASS32
-#define ELF_DATA	ELFDATA2LSB
-#define ELF_ARCH	EM_CRIS
-
-#include <asm/arch/elf.h>
-
-/* The master for these definitions is {binutils}/include/elf/cris.h:  */
-/* User symbols in this file have a leading underscore.  */
-#define EF_CRIS_UNDERSCORE		0x00000001
-
-/* This is a mask for different incompatible machine variants.  */
-#define EF_CRIS_VARIANT_MASK		0x0000000e
-
-/* Variant 0; may contain v0..10 object.  */
-#define EF_CRIS_VARIANT_ANY_V0_V10	0x00000000
-
-/* Variant 1; contains v32 object.  */
-#define EF_CRIS_VARIANT_V32		0x00000002
-
-/* Variant 2; contains object compatible with v32 and v10.  */
-#define EF_CRIS_VARIANT_COMMON_V10_V32	0x00000004
-/* End of excerpt from {binutils}/include/elf/cris.h.  */
-
-#define USE_ELF_CORE_DUMP
-
-#define ELF_EXEC_PAGESIZE	8192
-
-/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
-   use of this is to invoke "./ld.so someprog" to test out a new version of
-   the loader.  We need to make sure that it is out of the way of the program
-   that it will "exec", and that there is sufficient room for the brk.  */
-
-#define ELF_ET_DYN_BASE         (2 * TASK_SIZE / 3)
-
-/* This yields a mask that user programs can use to figure out what
-   instruction set this CPU supports.  This could be done in user space,
-   but it's not easy, and we've already done it here.  */
-
-#define ELF_HWCAP       (0)
-
-/* This yields a string that ld.so will use to load implementation
-   specific libraries for optimization.  This is more specific in
-   intent than poking at uname or /proc/cpuinfo.
-*/
-
-#define ELF_PLATFORM  (NULL)
-
-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
-
-#endif
diff --git a/include/asm-cris/emergency-restart.h b/include/asm-cris/emergency-restart.h
deleted file mode 100644
index 108d8c48e42e..000000000000
--- a/include/asm-cris/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_EMERGENCY_RESTART_H
-#define _ASM_EMERGENCY_RESTART_H
-
-#include <asm-generic/emergency-restart.h>
-
-#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-cris/errno.h b/include/asm-cris/errno.h
deleted file mode 100644
index 2bf5eb5fa773..000000000000
--- a/include/asm-cris/errno.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _CRIS_ERRNO_H
-#define _CRIS_ERRNO_H
-
-#include <asm-generic/errno.h>
-
-#endif
diff --git a/include/asm-cris/eshlibld.h b/include/asm-cris/eshlibld.h
deleted file mode 100644
index 10ce36cf79a9..000000000000
--- a/include/asm-cris/eshlibld.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*!**************************************************************************
-*!
-*! FILE NAME  : eshlibld.h
-*!
-*! DESCRIPTION: Prototypes for exported shared library functions
-*!
-*! FUNCTIONS  : perform_cris_aout_relocations, shlibmod_fork, shlibmod_exit
-*! (EXPORTED)
-*!
-*!---------------------------------------------------------------------------
-*!
-*! (C) Copyright 1998, 1999 Axis Communications AB, LUND, SWEDEN
-*!
-*!**************************************************************************/
-/* $Id: eshlibld.h,v 1.2 2001/02/23 13:47:33 bjornw Exp $ */
-
-#ifndef _cris_relocate_h
-#define _cris_relocate_h
-
-/* Please note that this file is also compiled into the xsim simulator.
-   Try to avoid breaking its double use (only works on a little-endian
-   32-bit machine such as the i386 anyway).
-
-   Use __KERNEL__ when you're about to use kernel functions,
-       (which you should not do here anyway, since this file is
-       used by glibc).
-   Use defined(__KERNEL__) || defined(__elinux__) when doing
-       things that only makes sense on an elinux system.
-   Use __CRIS__ when you're about to do (really) CRIS-specific code.
-*/
-
-/* We have dependencies all over the place for the host system
-   for xsim being a linux system, so let's not pretend anything
-   else with #ifdef:s here until fixed.  */
-#include <linux/limits.h>
-
-/* Maybe do sanity checking if file input. */
-#undef SANITYCHECK_RELOC
-
-/* Maybe output debug messages. */
-#undef RELOC_DEBUG
-
-/* Maybe we want to share core as well as disk space.
-   Mainly depends on the config macro CONFIG_SHARE_SHLIB_CORE, but it is
-   assumed that we want to share code when debugging (exposes more
-   trouble). */
-#ifndef SHARE_LIB_CORE
-# if (defined(__KERNEL__) || !defined(RELOC_DEBUG)) \
-     && !defined(CONFIG_SHARE_SHLIB_CORE)
-#  define SHARE_LIB_CORE 0
-# else
-#  define SHARE_LIB_CORE 1
-# endif /* __KERNEL__ etc */
-#endif /* SHARE_LIB_CORE */
-
-
-/* Main exported function; supposed to be called when the program a.out
-   has been read in. */
-extern int
-perform_cris_aout_relocations(unsigned long text, unsigned long tlength,
-			      unsigned long data, unsigned long dlength,
-			      unsigned long baddr, unsigned long blength,
-
-			      /* These may be zero when there's "perfect"
-				 position-independent code. */
-			      unsigned char *trel, unsigned long tsrel,
-			      unsigned long dsrel,
-
-			      /* These will be zero at a first try, to see
-				 if code is statically linked.  Else a
-				 second try, with the symbol table and
-				 string table nonzero should be done. */
-			      unsigned char *symbols, unsigned long symlength,
-			      unsigned char *strings, unsigned long stringlength,
-
-			      /* These will only be used when symbol table
-			       information is present. */
-			      char **env, int envc,
-			      int euid, int is_suid);
-
-
-#ifdef RELOC_DEBUG
-/* Task-specific debug stuff. */
-struct task_reloc_debug {
-	struct memdebug *alloclast;
-	unsigned long alloc_total;
-	unsigned long export_total;
-};
-#endif /* RELOC_DEBUG */
-
-#if SHARE_LIB_CORE
-
-/* When code (and some very specific data) is shared and not just
-   dynamically linked, we need to export hooks for exec beginning and
-   end. */
-
-struct shlibdep;
-
-extern void
-shlibmod_exit(struct shlibdep **deps);
-
-/* Returns 0 if failure, nonzero for ok. */
-extern int
-shlibmod_fork(struct shlibdep **deps);
-
-#else  /* ! SHARE_LIB_CORE */
-# define shlibmod_exit(x)
-# define shlibmod_fork(x) 1
-#endif /* ! SHARE_LIB_CORE */
-
-#endif _cris_relocate_h
-/********************** END OF FILE eshlibld.h *****************************/
-
diff --git a/include/asm-cris/ethernet.h b/include/asm-cris/ethernet.h
deleted file mode 100644
index 4d58652c3a49..000000000000
--- a/include/asm-cris/ethernet.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*  
- * ioctl defines for ethernet driver
- *
- * Copyright (c) 2001 Axis Communications AB
- * 
- * Author: Mikael Starvik 
- *
- */
-
-#ifndef _CRIS_ETHERNET_H
-#define _CRIS_ETHERNET_H
-#define SET_ETH_SPEED_AUTO      SIOCDEVPRIVATE          /* Auto neg speed */
-#define SET_ETH_SPEED_10        SIOCDEVPRIVATE+1        /* 10 Mbps */
-#define SET_ETH_SPEED_100       SIOCDEVPRIVATE+2        /* 100 Mbps. */
-#define SET_ETH_DUPLEX_AUTO     SIOCDEVPRIVATE+3        /* Auto neg duplex */
-#define SET_ETH_DUPLEX_HALF     SIOCDEVPRIVATE+4        /* Full duplex */
-#define SET_ETH_DUPLEX_FULL     SIOCDEVPRIVATE+5        /* Half duplex */
-#define SET_ETH_ENABLE_LEDS     SIOCDEVPRIVATE+6        /* Enable net LEDs */
-#define SET_ETH_DISABLE_LEDS    SIOCDEVPRIVATE+7        /* Disable net LEDs */
-#define SET_ETH_AUTONEG         SIOCDEVPRIVATE+8
-#endif /* _CRIS_ETHERNET_H */
diff --git a/include/asm-cris/etraxgpio.h b/include/asm-cris/etraxgpio.h
deleted file mode 100644
index 38f1c8e1770c..000000000000
--- a/include/asm-cris/etraxgpio.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * The following devices are accessable using this driver using
- * GPIO_MAJOR (120) and a couple of minor numbers.
- *
- * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10):
- * /dev/gpioa  minor 0, 8 bit GPIO, each bit can change direction
- * /dev/gpiob  minor 1, 8 bit GPIO, each bit can change direction
- * /dev/leds   minor 2, Access to leds depending on kernelconfig
- * /dev/gpiog  minor 3
- *       g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG
- *       g1-g7 and g25-g31 is both input and outputs but on different pins
- *       Also note that some bits change pins depending on what interfaces
- *       are enabled.
- *
- * For ETRAX FS (CONFIG_ETRAXFS):
- * /dev/gpioa  minor 0,  8 bit GPIO, each bit can change direction
- * /dev/gpiob  minor 1, 18 bit GPIO, each bit can change direction
- * /dev/gpioc  minor 3, 18 bit GPIO, each bit can change direction
- * /dev/gpiod  minor 4, 18 bit GPIO, each bit can change direction
- * /dev/gpioe  minor 5, 18 bit GPIO, each bit can change direction
- * /dev/leds   minor 2, Access to leds depending on kernelconfig
- *
- * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3):
- * /dev/gpioa  minor 0,  8 bit GPIO, each bit can change direction
- * /dev/gpiob  minor 1, 18 bit GPIO, each bit can change direction
- * /dev/gpioc  minor 3, 18 bit GPIO, each bit can change direction
- * /dev/gpiod  minor 4, 18 bit GPIO, each bit can change direction
- * /dev/leds   minor 2, Access to leds depending on kernelconfig
- * /dev/pwm0   minor 16, PWM channel 0 on PA30
- * /dev/pwm1   minor 17, PWM channel 1 on PA31
- * /dev/pwm2   minor 18, PWM channel 2 on PB26
- *
- */
-#ifndef _ASM_ETRAXGPIO_H
-#define _ASM_ETRAXGPIO_H
-
-/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */
-#ifdef CONFIG_ETRAX_ARCH_V10
-#define ETRAXGPIO_IOCTYPE 43
-#define GPIO_MINOR_A 0
-#define GPIO_MINOR_B 1
-#define GPIO_MINOR_LEDS 2
-#define GPIO_MINOR_G 3
-#define GPIO_MINOR_LAST 3
-#endif
-
-#ifdef CONFIG_ETRAXFS
-#define ETRAXGPIO_IOCTYPE 43
-#define GPIO_MINOR_A 0
-#define GPIO_MINOR_B 1
-#define GPIO_MINOR_LEDS 2
-#define GPIO_MINOR_C 3
-#define GPIO_MINOR_D 4
-#define GPIO_MINOR_E 5
-#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
-#define GPIO_MINOR_V 6
-#define GPIO_MINOR_LAST 6
-#else
-#define GPIO_MINOR_LAST 5
-#endif
-#endif
-
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
-#define ETRAXGPIO_IOCTYPE 43
-#define GPIO_MINOR_A 0
-#define GPIO_MINOR_B 1
-#define GPIO_MINOR_LEDS 2
-#define GPIO_MINOR_C 3
-#define GPIO_MINOR_D 4
-#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
-#define GPIO_MINOR_V 6
-#define GPIO_MINOR_LAST 6
-#else
-#define GPIO_MINOR_LAST 4
-#endif
-#define GPIO_MINOR_PWM0 16
-#define GPIO_MINOR_PWM1 17
-#define GPIO_MINOR_PWM2 18
-#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PWM2
-#endif
-
-/* supported ioctl _IOC_NR's */
-
-#define IO_READBITS  0x1  /* read and return current port bits (obsolete) */
-#define IO_SETBITS   0x2  /* set the bits marked by 1 in the argument */
-#define IO_CLRBITS   0x3  /* clear the bits marked by 1 in the argument */
-
-/* the alarm is waited for by select() */
-
-#define IO_HIGHALARM 0x4  /* set alarm on high for bits marked by 1 */
-#define IO_LOWALARM  0x5  /* set alarm on low for bits marked by 1 */
-#define IO_CLRALARM  0x6  /* clear alarm for bits marked by 1 */
-
-/* LED ioctl */
-#define IO_LEDACTIVE_SET 0x7 /* set active led
-                              * 0=off, 1=green, 2=red, 3=yellow */
-
-/* GPIO direction ioctl's */
-#define IO_READDIR    0x8  /* Read direction 0=input 1=output  (obsolete) */
-#define IO_SETINPUT   0x9  /* Set direction for bits set, 0=unchanged 1=input,
-                              returns mask with current inputs (obsolete) */
-#define IO_SETOUTPUT  0xA  /* Set direction for bits set, 0=unchanged 1=output,
-                              returns mask with current outputs (obsolete)*/
-
-/* LED ioctl extended */
-#define IO_LED_SETBIT 0xB
-#define IO_LED_CLRBIT 0xC
-
-/* SHUTDOWN ioctl */
-#define IO_SHUTDOWN   0xD
-#define IO_GET_PWR_BT 0xE
-
-/* Bit toggling in driver settings */
-/* bit set in low byte0 is CLK mask (0x00FF),
-   bit set in byte1 is DATA mask    (0xFF00)
-   msb, data_mask[7:0] , clk_mask[7:0]
- */
-#define IO_CFG_WRITE_MODE 0xF
-#define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \
-	( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) )
-
-/* The following 4 ioctl's take a pointer as argument and handles
- * 32 bit ports (port G) properly.
- * These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT
- */
-#define IO_READ_INBITS   0x10 /* *arg is result of reading the input pins */
-#define IO_READ_OUTBITS  0x11 /* *arg is result of reading the output shadow */
-#define IO_SETGET_INPUT  0x12 /* bits set in *arg is set to input,
-                               * *arg updated with current input pins.
-                               */
-#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output,
-                               * *arg updated with current output pins.
-                               */
-
-/* The following ioctl's are applicable to the PWM channels only */
-
-#define IO_PWM_SET_MODE     0x20
-
-enum io_pwm_mode {
-	PWM_OFF = 0,		/* disabled, deallocated */
-	PWM_STANDARD = 1,	/* 390 kHz, duty cycle 0..255/256 */
-	PWM_FAST = 2,		/* variable freq, w/ 10ns active pulse len */
-	PWM_VARFREQ = 3		/* individually configurable high/low periods */
-};
-
-struct io_pwm_set_mode {
-	enum io_pwm_mode mode;
-};
-
-/* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns
- * from 10ns (value = 0) to 81920ns (value = 8191)
- * (Resulting frequencies range from 50 MHz (10ns + 10ns) down to
- * 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty
- * cycle (81920 + 10ns or 10ns + 81920ns, respectively).)
- */
-#define IO_PWM_SET_PERIOD   0x21
-
-struct io_pwm_set_period {
-	unsigned int lo;		/* 0..8191 */
-	unsigned int hi;		/* 0..8191 */
-};
-
-/* Only for modes PWM_STANDARD and PWM_FAST.
- * For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from
- * 0 (value = 0) to 255/256 (value = 255).
- * For PWM_FAST, set duty cycle of PWM output signal from
- * 0% (value = 0) to 100% (value = 255). Output signal in this mode
- * is a 10ns pulse surrounded by a high or low level depending on duty
- * cycle (except for 0% and 100% which result in a constant output).
- * Resulting output frequency varies from 50 MHz at 50% duty cycle,
- * down to 390 kHz at min/max duty cycle.
- */
-#define IO_PWM_SET_DUTY     0x22
-
-struct io_pwm_set_duty {
-	int duty;		/* 0..255 */
-};
-
-#endif
diff --git a/include/asm-cris/etraxi2c.h b/include/asm-cris/etraxi2c.h
deleted file mode 100644
index e369a7620893..000000000000
--- a/include/asm-cris/etraxi2c.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* $Id: etraxi2c.h,v 1.1 2001/01/18 15:49:57 bjornw Exp $ */
-
-#ifndef _LINUX_ETRAXI2C_H
-#define _LINUX_ETRAXI2C_H
-
-/* etraxi2c _IOC_TYPE, bits 8 to 15 in ioctl cmd */
-
-#define ETRAXI2C_IOCTYPE 44
-
-/* supported ioctl _IOC_NR's */
-
-/* in write operations, the argument contains both i2c
- * slave, register and value.
- */
-
-#define I2C_WRITEARG(slave, reg, value) (((slave) << 16) | ((reg) << 8) | (value))
-#define I2C_READARG(slave, reg) (((slave) << 16) | ((reg) << 8))
-
-#define I2C_ARGSLAVE(arg) ((arg) >> 16)
-#define I2C_ARGREG(arg) (((arg) >> 8) & 0xff)
-#define I2C_ARGVALUE(arg) ((arg) & 0xff)
-
-#define I2C_WRITEREG 0x1   /* write to an i2c register */
-#define I2C_READREG  0x2   /* read from an i2c register */
-
-/*
-EXAMPLE usage:
-
-    i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val);
-    ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg);
-
-    i2c_arg = I2C_READARG(STA013_READ_ADDR, reg);
-    val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg);
-
-*/
-#endif
diff --git a/include/asm-cris/fasttimer.h b/include/asm-cris/fasttimer.h
deleted file mode 100644
index 8f8a8d6c9653..000000000000
--- a/include/asm-cris/fasttimer.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * linux/include/asm-cris/fasttimer.h
- *
- * Fast timers for ETRAX100LX
- * Copyright (C) 2000-2007 Axis Communications AB
- */
-#include <linux/time.h> /* struct timeval */
-#include <linux/timex.h>
-
-#ifdef CONFIG_ETRAX_FAST_TIMER
-
-typedef void fast_timer_function_type(unsigned long);
-
-struct fasttime_t {
-	unsigned long tv_jiff;  /* jiffies */
-	unsigned long tv_usec;  /* microseconds */
-};
-
-struct fast_timer{ /* Close to timer_list */
-  struct fast_timer *next;
-  struct fast_timer *prev;
-	struct fasttime_t tv_set;
-	struct fasttime_t tv_expires;
-  unsigned long delay_us;
-  fast_timer_function_type *function;
-  unsigned long data;
-  const char *name;
-};
-
-extern struct fast_timer *fast_timer_list;
-
-void start_one_shot_timer(struct fast_timer *t,
-                          fast_timer_function_type *function,
-                          unsigned long data,
-                          unsigned long delay_us,
-                          const char *name);
-
-int del_fast_timer(struct fast_timer * t);
-/* return 1 if deleted */
-
-
-void schedule_usleep(unsigned long us);
-
-
-int fast_timer_init(void);
-
-#endif
diff --git a/include/asm-cris/fb.h b/include/asm-cris/fb.h
deleted file mode 100644
index c7df38030992..000000000000
--- a/include/asm-cris/fb.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _ASM_FB_H_
-#define _ASM_FB_H_
-#include <linux/fb.h>
-
-#define fb_pgprotect(...) do {} while (0)
-
-static inline int fb_is_primary_device(struct fb_info *info)
-{
-	return 0;
-}
-
-#endif /* _ASM_FB_H_ */
diff --git a/include/asm-cris/fcntl.h b/include/asm-cris/fcntl.h
deleted file mode 100644
index 46ab12db5739..000000000000
--- a/include/asm-cris/fcntl.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/fcntl.h>
diff --git a/include/asm-cris/futex.h b/include/asm-cris/futex.h
deleted file mode 100644
index 6a332a9f099c..000000000000
--- a/include/asm-cris/futex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
-
-#include <asm-generic/futex.h>
-
-#endif
diff --git a/include/asm-cris/hardirq.h b/include/asm-cris/hardirq.h
deleted file mode 100644
index 74178adeb1cd..000000000000
--- a/include/asm-cris/hardirq.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef __ASM_HARDIRQ_H
-#define __ASM_HARDIRQ_H
-
-#include <asm/irq.h>
-#include <linux/threads.h>
-#include <linux/cache.h>
-
-typedef struct {
-	unsigned int __softirq_pending;
-} ____cacheline_aligned irq_cpustat_t;
-
-#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
-
-void ack_bad_irq(unsigned int irq);
-
-#define HARDIRQ_BITS	8
-
-/*
- * The hardirq mask has to be large enough to have
- * space for potentially all IRQ sources in the system
- * nesting on a single CPU:
- */
-#if (1 << HARDIRQ_BITS) < NR_IRQS
-# error HARDIRQ_BITS is too low!
-#endif
-
-#endif /* __ASM_HARDIRQ_H */
diff --git a/include/asm-cris/hw_irq.h b/include/asm-cris/hw_irq.h
deleted file mode 100644
index 298066020af2..000000000000
--- a/include/asm-cris/hw_irq.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifndef _ASM_HW_IRQ_H
-#define _ASM_HW_IRQ_H
-
-#endif
-
diff --git a/include/asm-cris/io.h b/include/asm-cris/io.h
deleted file mode 100644
index b87ce63f531f..000000000000
--- a/include/asm-cris/io.h
+++ /dev/null
@@ -1,154 +0,0 @@
-#ifndef _ASM_CRIS_IO_H
-#define _ASM_CRIS_IO_H
-
-#include <asm/page.h>   /* for __va, __pa */
-#include <asm/arch/io.h>
-#include <linux/kernel.h>
-
-struct cris_io_operations
-{
-	u32 (*read_mem)(void *addr, int size);
-	void (*write_mem)(u32 val, int size, void *addr);
-	u32 (*read_io)(u32 port, void *addr, int size, int count);
-	void (*write_io)(u32 port, void *addr, int size, int count);
-};
-
-#ifdef CONFIG_PCI
-extern struct cris_io_operations *cris_iops;
-#else
-#define cris_iops ((struct cris_io_operations*)NULL)
-#endif
-
-/*
- * Change virtual addresses to physical addresses and vv.
- */
-
-static inline unsigned long virt_to_phys(volatile void * address)
-{
-	return __pa(address);
-}
-
-static inline void * phys_to_virt(unsigned long address)
-{
-	return __va(address);
-}
-
-extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
-extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot);
-
-static inline void __iomem * ioremap (unsigned long offset, unsigned long size)
-{
-	return __ioremap(offset, size, 0);
-}
-
-extern void iounmap(volatile void * __iomem addr);
-
-extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size);
-
-/*
- * IO bus memory addresses are also 1:1 with the physical address
- */
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-
-/*
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the CRIS architecture, we just read/write the
- * memory location directly.
- */
-#ifdef CONFIG_PCI
-#define PCI_SPACE(x) ((((unsigned)(x)) & 0x10000000) == 0x10000000)
-#else
-#define PCI_SPACE(x) 0
-#endif
-static inline unsigned char readb(const volatile void __iomem *addr)
-{
-	if (PCI_SPACE(addr) && cris_iops)
-		return cris_iops->read_mem((void*)addr, 1);
-	else
-		return *(volatile unsigned char __force *) addr;
-}
-static inline unsigned short readw(const volatile void __iomem *addr)
-{
-	if (PCI_SPACE(addr) && cris_iops)
-		return cris_iops->read_mem((void*)addr, 2);
-	else
-		return *(volatile unsigned short __force *) addr;
-}
-static inline unsigned int readl(const volatile void __iomem *addr)
-{
-	if (PCI_SPACE(addr) && cris_iops)
-		return cris_iops->read_mem((void*)addr, 4);
-	else
-		return *(volatile unsigned int __force *) addr;
-}
-#define readb_relaxed(addr) readb(addr)
-#define readw_relaxed(addr) readw(addr)
-#define readl_relaxed(addr) readl(addr)
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-
-static inline void writeb(unsigned char b, volatile void __iomem *addr)
-{
-	if (PCI_SPACE(addr) && cris_iops)
-		cris_iops->write_mem(b, 1, (void*)addr);
-	else
-		*(volatile unsigned char __force *) addr = b;
-}
-static inline void writew(unsigned short b, volatile void __iomem *addr)
-{
-	if (PCI_SPACE(addr) && cris_iops)
-		cris_iops->write_mem(b, 2, (void*)addr);
-	else
-		*(volatile unsigned short __force *) addr = b;
-}
-static inline void writel(unsigned int b, volatile void __iomem *addr)
-{
-	if (PCI_SPACE(addr) && cris_iops)
-		cris_iops->write_mem(b, 4, (void*)addr);
-	else
-		*(volatile unsigned int __force *) addr = b;
-}
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-
-#define mmiowb()
-
-#define memset_io(a,b,c)	memset((void *)(a),(b),(c))
-#define memcpy_fromio(a,b,c)	memcpy((a),(void *)(b),(c))
-#define memcpy_toio(a,b,c)	memcpy((void *)(a),(b),(c))
-
-
-/* I/O port access. Normally there is no I/O space on CRIS but when
- * Cardbus/PCI is enabled the request is passed through the bridge.
- */
-
-#define IO_SPACE_LIMIT 0xffff
-#define inb(port) (cris_iops ? cris_iops->read_io(port,NULL,1,1) : 0)
-#define inw(port) (cris_iops ? cris_iops->read_io(port,NULL,2,1) : 0)
-#define inl(port) (cris_iops ? cris_iops->read_io(port,NULL,4,1) : 0)
-#define insb(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,1,count) : 0)
-#define insw(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,2,count) : 0)
-#define insl(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,4,count) : 0)
-#define outb(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,1,1)
-#define outw(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,2,1)
-#define outl(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,4,1)
-#define outsb(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,1,count)
-#define outsw(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,2,count)
-#define outsl(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,3,count)
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)	__va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)	p
-
-#endif
diff --git a/include/asm-cris/ioctl.h b/include/asm-cris/ioctl.h
deleted file mode 100644
index b279fe06dfe5..000000000000
--- a/include/asm-cris/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ioctl.h>
diff --git a/include/asm-cris/ioctls.h b/include/asm-cris/ioctls.h
deleted file mode 100644
index 4f4e52531fa0..000000000000
--- a/include/asm-cris/ioctls.h
+++ /dev/null
@@ -1,91 +0,0 @@
-#ifndef __ARCH_CRIS_IOCTLS_H__
-#define __ARCH_CRIS_IOCTLS_H__
-
-/* verbatim copy of asm-i386/ioctls.h */
-
-#include <asm/ioctl.h>
-
-/* 0x54 is just a magic number to make these relatively unique ('T') */
-
-#define TCGETS		0x5401
-#define TCSETS		0x5402
-#define TCSETSW		0x5403
-#define TCSETSF		0x5404
-#define TCGETA		0x5405
-#define TCSETA		0x5406
-#define TCSETAW		0x5407
-#define TCSETAF		0x5408
-#define TCSBRK		0x5409
-#define TCXONC		0x540A
-#define TCFLSH		0x540B
-#define TIOCEXCL	0x540C
-#define TIOCNXCL	0x540D
-#define TIOCSCTTY	0x540E
-#define TIOCGPGRP	0x540F
-#define TIOCSPGRP	0x5410
-#define TIOCOUTQ	0x5411
-#define TIOCSTI		0x5412
-#define TIOCGWINSZ	0x5413
-#define TIOCSWINSZ	0x5414
-#define TIOCMGET	0x5415
-#define TIOCMBIS	0x5416
-#define TIOCMBIC	0x5417
-#define TIOCMSET	0x5418
-#define TIOCGSOFTCAR	0x5419
-#define TIOCSSOFTCAR	0x541A
-#define FIONREAD	0x541B
-#define TIOCINQ		FIONREAD
-#define TIOCLINUX	0x541C
-#define TIOCCONS	0x541D
-#define TIOCGSERIAL	0x541E
-#define TIOCSSERIAL	0x541F
-#define TIOCPKT		0x5420
-#define FIONBIO		0x5421
-#define TIOCNOTTY	0x5422
-#define TIOCSETD	0x5423
-#define TIOCGETD	0x5424
-#define TCSBRKP		0x5425	/* Needed for POSIX tcsendbreak() */
-#define TIOCSBRK	0x5427  /* BSD compatibility */
-#define TIOCCBRK	0x5428  /* BSD compatibility */
-#define TIOCGSID	0x5429  /* Return the session ID of FD */
-#define TCGETS2		_IOR('T',0x2A, struct termios2)
-#define TCSETS2		_IOW('T',0x2B, struct termios2)
-#define TCSETSW2	_IOW('T',0x2C, struct termios2)
-#define TCSETSF2	_IOW('T',0x2D, struct termios2)
-#define TIOCGPTN	_IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
-#define TIOCSPTLCK	_IOW('T',0x31, int)  /* Lock/unlock Pty */
-
-#define FIONCLEX	0x5450  /* these numbers need to be adjusted. */
-#define FIOCLEX		0x5451
-#define FIOASYNC	0x5452
-#define TIOCSERCONFIG	0x5453
-#define TIOCSERGWILD	0x5454
-#define TIOCSERSWILD	0x5455
-#define TIOCGLCKTRMIOS	0x5456
-#define TIOCSLCKTRMIOS	0x5457
-#define TIOCSERGSTRUCT	0x5458 /* For debugging only */
-#define TIOCSERGETLSR   0x5459 /* Get line status register */
-#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
-#define TIOCSERSETMULTI 0x545B /* Set multiport config */
-
-#define TIOCMIWAIT	0x545C	/* wait for a change on serial input line(s) */
-#define TIOCGICOUNT	0x545D	/* read serial port inline interrupt counts */
-#define TIOCGHAYESESP   0x545E  /* Get Hayes ESP configuration */
-#define TIOCSHAYESESP   0x545F  /* Set Hayes ESP configuration */
-#define FIOQSIZE	0x5460
-
-#define TIOCSERSETRS485 0x5461  /* enable rs-485 */
-#define TIOCSERWRRS485  0x5462  /* write rs-485 */
-
-/* Used for packet mode */
-#define TIOCPKT_DATA		 0
-#define TIOCPKT_FLUSHREAD	 1
-#define TIOCPKT_FLUSHWRITE	 2
-#define TIOCPKT_STOP		 4
-#define TIOCPKT_START		 8
-#define TIOCPKT_NOSTOP		16
-#define TIOCPKT_DOSTOP		32
-
-#define TIOCSER_TEMT    0x01	/* Transmitter physically empty */
-
-#endif
diff --git a/include/asm-cris/ipcbuf.h b/include/asm-cris/ipcbuf.h
deleted file mode 100644
index 8b0c18b02844..000000000000
--- a/include/asm-cris/ipcbuf.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef __CRIS_IPCBUF_H__
-#define __CRIS_IPCBUF_H__
-
-/*
- * The user_ipc_perm structure for CRIS architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 32-bit mode_t and seq
- * - 2 miscellaneous 32-bit values
- */
-
-struct ipc64_perm
-{
-	__kernel_key_t		key;
-	__kernel_uid32_t	uid;
-	__kernel_gid32_t	gid;
-	__kernel_uid32_t	cuid;
-	__kernel_gid32_t	cgid;
-	__kernel_mode_t		mode;
-	unsigned short		__pad1;
-	unsigned short		seq;
-	unsigned short		__pad2;
-	unsigned long		__unused1;
-	unsigned long		__unused2;
-};
-
-#endif /* __CRIS_IPCBUF_H__ */
diff --git a/include/asm-cris/irq.h b/include/asm-cris/irq.h
deleted file mode 100644
index 998cce9f3200..000000000000
--- a/include/asm-cris/irq.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _ASM_IRQ_H
-#define _ASM_IRQ_H
-
-#include <asm/arch/irq.h>
-
-static inline int irq_canonicalize(int irq)
-{  
-  return irq; 
-}
-
-#endif  /* _ASM_IRQ_H */
-
-
diff --git a/include/asm-cris/irq_regs.h b/include/asm-cris/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/include/asm-cris/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/include/asm-cris/kdebug.h b/include/asm-cris/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/include/asm-cris/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/include/asm-cris/kmap_types.h b/include/asm-cris/kmap_types.h
deleted file mode 100644
index 492988cb9077..000000000000
--- a/include/asm-cris/kmap_types.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _ASM_KMAP_TYPES_H
-#define _ASM_KMAP_TYPES_H
-
-/* Dummy header just to define km_type.  None of this
- * is actually used on cris. 
- */
-
-enum km_type {
-	KM_BOUNCE_READ,
-	KM_SKB_SUNRPC_DATA,
-	KM_SKB_DATA_SOFTIRQ,
-	KM_USER0,
-	KM_USER1,
-	KM_BIO_SRC_IRQ,
-	KM_BIO_DST_IRQ,
-	KM_PTE0,
-	KM_PTE1,
-	KM_IRQ0,
-	KM_IRQ1,
-	KM_SOFTIRQ0,
-	KM_SOFTIRQ1,
-	KM_TYPE_NR
-};
-
-#endif
diff --git a/include/asm-cris/linkage.h b/include/asm-cris/linkage.h
deleted file mode 100644
index 291c2d01c44f..000000000000
--- a/include/asm-cris/linkage.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-/* Nothing to see here... */
-
-#endif
diff --git a/include/asm-cris/local.h b/include/asm-cris/local.h
deleted file mode 100644
index c11c530f74d0..000000000000
--- a/include/asm-cris/local.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/local.h>
diff --git a/include/asm-cris/mman.h b/include/asm-cris/mman.h
deleted file mode 100644
index 1c35e1b66b46..000000000000
--- a/include/asm-cris/mman.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef __CRIS_MMAN_H__
-#define __CRIS_MMAN_H__
-
-/* verbatim copy of asm-i386/ version */
-
-#include <asm-generic/mman.h>
-
-#define MAP_GROWSDOWN	0x0100		/* stack-like segment */
-#define MAP_DENYWRITE	0x0800		/* ETXTBSY */
-#define MAP_EXECUTABLE	0x1000		/* mark it as an executable */
-#define MAP_LOCKED	0x2000		/* pages are locked */
-#define MAP_NORESERVE	0x4000		/* don't check for reservations */
-#define MAP_POPULATE	0x8000		/* populate (prefault) pagetables */
-#define MAP_NONBLOCK	0x10000		/* do not block on IO */
-
-#define MCL_CURRENT	1		/* lock all current mappings */
-#define MCL_FUTURE	2		/* lock all future mappings */
-
-#endif /* __CRIS_MMAN_H__ */
diff --git a/include/asm-cris/mmu.h b/include/asm-cris/mmu.h
deleted file mode 100644
index c40a1bcad06c..000000000000
--- a/include/asm-cris/mmu.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * CRIS MMU constants and PTE layout
- */
-
-#ifndef _CRIS_MMU_H
-#define _CRIS_MMU_H
-
-#include <asm/arch/mmu.h>
-
-#endif
diff --git a/include/asm-cris/mmu_context.h b/include/asm-cris/mmu_context.h
deleted file mode 100644
index 72ba08dcfd18..000000000000
--- a/include/asm-cris/mmu_context.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef __CRIS_MMU_CONTEXT_H
-#define __CRIS_MMU_CONTEXT_H
-
-#include <asm-generic/mm_hooks.h>
-
-extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
-extern void get_mmu_context(struct mm_struct *mm);
-extern void destroy_context(struct mm_struct *mm);
-extern void switch_mm(struct mm_struct *prev, struct mm_struct *next,
-		      struct task_struct *tsk);
-
-#define deactivate_mm(tsk,mm)	do { } while (0)
-
-#define activate_mm(prev,next) switch_mm((prev),(next),NULL)
-
-/* current active pgd - this is similar to other processors pgd 
- * registers like cr3 on the i386
- */
-
-extern volatile DEFINE_PER_CPU(pgd_t *,current_pgd); /* defined in arch/cris/mm/fault.c */
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-#endif
diff --git a/include/asm-cris/module.h b/include/asm-cris/module.h
deleted file mode 100644
index 7ee72311bd78..000000000000
--- a/include/asm-cris/module.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef _ASM_CRIS_MODULE_H
-#define _ASM_CRIS_MODULE_H
-/* cris is simple */
-struct mod_arch_specific { };
-
-#define Elf_Shdr Elf32_Shdr
-#define Elf_Sym Elf32_Sym
-#define Elf_Ehdr Elf32_Ehdr
-#endif /* _ASM_CRIS_MODULE_H */
diff --git a/include/asm-cris/msgbuf.h b/include/asm-cris/msgbuf.h
deleted file mode 100644
index ada63df1d574..000000000000
--- a/include/asm-cris/msgbuf.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef _CRIS_MSGBUF_H
-#define _CRIS_MSGBUF_H
-
-/* verbatim copy of asm-i386 version */
-
-/* 
- * The msqid64_ds structure for CRIS architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct msqid64_ds {
-	struct ipc64_perm msg_perm;
-	__kernel_time_t msg_stime;	/* last msgsnd time */
-	unsigned long	__unused1;
-	__kernel_time_t msg_rtime;	/* last msgrcv time */
-	unsigned long	__unused2;
-	__kernel_time_t msg_ctime;	/* last change time */
-	unsigned long	__unused3;
-	unsigned long  msg_cbytes;	/* current number of bytes on queue */
-	unsigned long  msg_qnum;	/* number of messages in queue */
-	unsigned long  msg_qbytes;	/* max number of bytes on queue */
-	__kernel_pid_t msg_lspid;	/* pid of last msgsnd */
-	__kernel_pid_t msg_lrpid;	/* last receive pid */
-	unsigned long  __unused4;
-	unsigned long  __unused5;
-};
-
-#endif /* _CRIS_MSGBUF_H */
diff --git a/include/asm-cris/mutex.h b/include/asm-cris/mutex.h
deleted file mode 100644
index 458c1f7fbc18..000000000000
--- a/include/asm-cris/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Pull in the generic implementation for the mutex fastpath.
- *
- * TODO: implement optimized primitives instead, or leave the generic
- * implementation in place, or pick the atomic_xchg() based generic
- * implementation. (see asm-generic/mutex-xchg.h for details)
- */
-
-#include <asm-generic/mutex-dec.h>
diff --git a/include/asm-cris/page.h b/include/asm-cris/page.h
deleted file mode 100644
index d19272ba6b69..000000000000
--- a/include/asm-cris/page.h
+++ /dev/null
@@ -1,74 +0,0 @@
-#ifndef _CRIS_PAGE_H
-#define _CRIS_PAGE_H
-
-#include <asm/arch/page.h>
-#include <linux/const.h>
-
-/* PAGE_SHIFT determines the page size */
-#define PAGE_SHIFT	13
-#define PAGE_SIZE	(_AC(1, UL) << PAGE_SHIFT)
-#define PAGE_MASK	(~(PAGE_SIZE-1))
-
-#define clear_page(page)        memset((void *)(page), 0, PAGE_SIZE)
-#define copy_page(to,from)      memcpy((void *)(to), (void *)(from), PAGE_SIZE)
-
-#define clear_user_page(page, vaddr, pg)    clear_page(page)
-#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
-
-#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \
-	alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr)
-#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
-
-/*
- * These are used to make use of C type-checking..
- */
-#ifndef __ASSEMBLY__
-typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long pgd; } pgd_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
-typedef struct page *pgtable_t;
-#endif
-
-#define pte_val(x)	((x).pte)
-#define pgd_val(x)	((x).pgd)
-#define pgprot_val(x)	((x).pgprot)
-
-#define __pte(x)	((pte_t) { (x) } )
-#define __pgd(x)	((pgd_t) { (x) } )
-#define __pgprot(x)	((pgprot_t) { (x) } )
-
-/* On CRIS the PFN numbers doesn't start at 0 so we have to compensate */
-/* for that before indexing into the page table starting at mem_map    */
-#define ARCH_PFN_OFFSET		(PAGE_OFFSET >> PAGE_SHIFT)
-#define pfn_valid(pfn)		(((pfn) - (PAGE_OFFSET >> PAGE_SHIFT)) < max_mapnr)
-
-/* to index into the page map. our pages all start at physical addr PAGE_OFFSET so
- * we can let the map start there. notice that we subtract PAGE_OFFSET because
- * we start our mem_map there - in other ports they map mem_map physically and
- * use __pa instead. in our system both the physical and virtual address of DRAM
- * is too high to let mem_map start at 0, so we do it this way instead (similar
- * to arm and m68k I think)
- */ 
-
-#define virt_to_page(kaddr)    (mem_map + (((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT))
-#define VALID_PAGE(page)       (((page) - mem_map) < max_mapnr)
-#define virt_addr_valid(kaddr)	pfn_valid((unsigned)(kaddr) >> PAGE_SHIFT)
-
-/* convert a page (based on mem_map and forward) to a physical address
- * do this by figuring out the virtual address and then use __pa
- */
-
-#define page_to_phys(page)     __pa((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET)
-
-#ifndef __ASSEMBLY__
-
-#endif /* __ASSEMBLY__ */
-
-#define VM_DATA_DEFAULT_FLAGS	(VM_READ | VM_WRITE | VM_EXEC | \
-				 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#include <asm-generic/memory_model.h>
-#include <asm-generic/page.h>
-
-#endif /* _CRIS_PAGE_H */
-
diff --git a/include/asm-cris/param.h b/include/asm-cris/param.h
deleted file mode 100644
index 0e47994e40be..000000000000
--- a/include/asm-cris/param.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef _ASMCRIS_PARAM_H
-#define _ASMCRIS_PARAM_H
-
-/* Currently we assume that HZ=100 is good for CRIS. */
-#ifdef __KERNEL__
-# define HZ		CONFIG_HZ	/* Internal kernel timer frequency */
-# define USER_HZ	100		/* .. some user interfaces are in "ticks" */
-# define CLOCKS_PER_SEC	(USER_HZ)	/* like times() */
-#endif
-
-#ifndef HZ
-#define HZ 100
-#endif
-
-#define EXEC_PAGESIZE	8192
-
-#ifndef NOGROUP
-#define NOGROUP		(-1)
-#endif
-
-#define MAXHOSTNAMELEN	64	/* max length of hostname */
-
-#endif
diff --git a/include/asm-cris/pci.h b/include/asm-cris/pci.h
deleted file mode 100644
index 730ce40fdd0f..000000000000
--- a/include/asm-cris/pci.h
+++ /dev/null
@@ -1,68 +0,0 @@
-#ifndef __ASM_CRIS_PCI_H
-#define __ASM_CRIS_PCI_H
-
-
-#ifdef __KERNEL__
-#include <linux/mm.h>		/* for struct page */
-
-/* Can be used to override the logic in pci_scan_bus for skipping
-   already-configured bus numbers - to be used for buggy BIOSes
-   or architectures with incomplete PCI setup by the loader */
-
-#define pcibios_assign_all_busses(void) 1
-
-extern unsigned long pci_mem_start;
-#define PCIBIOS_MIN_IO		0x1000
-#define PCIBIOS_MIN_MEM		0x10000000
-
-#define PCIBIOS_MIN_CARDBUS_IO	0x4000
-
-void pcibios_config_init(void);
-struct pci_bus * pcibios_scan_root(int bus);
-int pcibios_assign_resources(void);
-
-void pcibios_set_master(struct pci_dev *dev);
-void pcibios_penalize_isa_irq(int irq);
-struct irq_routing_table *pcibios_get_irq_routing_table(void);
-int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
-
-/* Dynamic DMA mapping stuff.
- * i386 has everything mapped statically.
- */
-
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <asm/scatterlist.h>
-#include <linux/string.h>
-#include <asm/io.h>
-
-struct pci_dev;
-
-/* The PCI address space does equal the physical memory
- * address space.  The networking and block device layers use
- * this boolean for bounce buffer decisions.
- */
-#define PCI_DMA_BUS_IS_PHYS	(1)
-
-/* pci_unmap_{page,single} is a nop so... */
-#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
-#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
-#define pci_unmap_addr(PTR, ADDR_NAME)		(0)
-#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)	do { } while (0)
-#define pci_unmap_len(PTR, LEN_NAME)		(0)
-#define pci_unmap_len_set(PTR, LEN_NAME, VAL)	do { } while (0)
-
-#define HAVE_PCI_MMAP
-extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
-			       enum pci_mmap_state mmap_state, int write_combine);
-
-
-#endif /* __KERNEL__ */
-
-/* implement the pci_ DMA API in terms of the generic device dma_ one */
-#include <asm-generic/pci-dma-compat.h>
-
-/* generic pci stuff */
-#include <asm-generic/pci.h>
-
-#endif /* __ASM_CRIS_PCI_H */
diff --git a/include/asm-cris/percpu.h b/include/asm-cris/percpu.h
deleted file mode 100644
index 6db9b43cf80a..000000000000
--- a/include/asm-cris/percpu.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _CRIS_PERCPU_H
-#define _CRIS_PERCPU_H
-
-#include <asm-generic/percpu.h>
-
-#endif /* _CRIS_PERCPU_H */
diff --git a/include/asm-cris/pgalloc.h b/include/asm-cris/pgalloc.h
deleted file mode 100644
index a1ba761d0573..000000000000
--- a/include/asm-cris/pgalloc.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef _CRIS_PGALLOC_H
-#define _CRIS_PGALLOC_H
-
-#include <linux/threads.h>
-#include <linux/mm.h>
-
-#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, pte)
-#define pmd_populate(mm, pmd, pte) pmd_set(pmd, page_address(pte))
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-/*
- * Allocate and free page tables.
- */
-
-static inline pgd_t *pgd_alloc (struct mm_struct *mm)
-{
-	return (pgd_t *)get_zeroed_page(GFP_KERNEL);
-}
-
-static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
-	free_page((unsigned long)pgd);
-}
-
-static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
-{
-  	pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO);
- 	return pte;
-}
-
-static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
-{
-	struct page *pte;
-	pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0);
-	pgtable_page_ctor(pte);
-	return pte;
-}
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
-	free_page((unsigned long)pte);
-}
-
-static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
-{
-	pgtable_page_dtor(pte);
-	__free_page(pte);
-}
-
-#define __pte_free_tlb(tlb,pte)				\
-do {							\
-	pgtable_page_dtor(pte);				\
-	tlb_remove_page((tlb), pte);			\
-} while (0)
-
-#define check_pgt_cache()          do { } while (0)
-
-#endif
diff --git a/include/asm-cris/pgtable.h b/include/asm-cris/pgtable.h
deleted file mode 100644
index 829e7a7d9fb9..000000000000
--- a/include/asm-cris/pgtable.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * CRIS pgtable.h - macros and functions to manipulate page tables.
- */
-
-#ifndef _CRIS_PGTABLE_H
-#define _CRIS_PGTABLE_H
-
-#include <asm/page.h>
-#include <asm-generic/pgtable-nopmd.h>
-
-#ifndef __ASSEMBLY__
-#include <linux/sched.h>
-#include <asm/mmu.h>
-#endif
-#include <asm/arch/pgtable.h>
-
-/*
- * The Linux memory management assumes a three-level page table setup. On
- * CRIS, we use that, but "fold" the mid level into the top-level page
- * table. Since the MMU TLB is software loaded through an interrupt, it
- * supports any page table structure, so we could have used a three-level
- * setup, but for the amounts of memory we normally use, a two-level is
- * probably more efficient.
- *
- * This file contains the functions and defines necessary to modify and use
- * the CRIS page table tree.
- */
-#ifndef __ASSEMBLY__
-extern void paging_init(void);
-#endif
-
-/* Certain architectures need to do special things when pte's
- * within a page table are directly modified.  Thus, the following
- * hook is made available.
- */
-#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
-
-/*
- * (pmds are folded into pgds so this doesn't get actually called,
- * but the define is needed for a generic inline function.)
- */
-#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
-#define set_pgu(pudptr, pudval) (*(pudptr) = pudval)
-
-/* PGDIR_SHIFT determines the size of the area a second-level page table can
- * map. It is equal to the page size times the number of PTE's that fit in
- * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number.
- */
-
-#define PGDIR_SHIFT	(PAGE_SHIFT + (PAGE_SHIFT-2))
-#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
-#define PGDIR_MASK	(~(PGDIR_SIZE-1))
-
-/*
- * entries per page directory level: we use a two-level, so
- * we don't really have any PMD directory physically.
- * pointers are 4 bytes so we can use the page size and 
- * divide it by 4 (shift by 2).
- */
-#define PTRS_PER_PTE	(1UL << (PAGE_SHIFT-2))
-#define PTRS_PER_PGD	(1UL << (PAGE_SHIFT-2))
-
-/* calculate how many PGD entries a user-level program can use
- * the first mappable virtual address is 0
- * (TASK_SIZE is the maximum virtual address space)
- */
-
-#define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
-#define FIRST_USER_ADDRESS      0
-
-/* zero page used for uninitialized stuff */
-#ifndef __ASSEMBLY__
-extern unsigned long empty_zero_page;
-#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
-#endif
-
-/* number of bits that fit into a memory pointer */
-#define BITS_PER_PTR			(8*sizeof(unsigned long))
-
-/* to align the pointer to a pointer address */
-#define PTR_MASK			(~(sizeof(void*)-1))
-
-/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
-/* 64-bit machines, beware!  SRB. */
-#define SIZEOF_PTR_LOG2			2
-
-/* to find an entry in a page-table */
-#define PAGE_PTR(address) \
-((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
-
-/* to set the page-dir */
-#define SET_PAGE_DIR(tsk,pgdir)
-
-#define pte_none(x)	(!pte_val(x))
-#define pte_present(x)	(pte_val(x) & _PAGE_PRESENT)
-#define pte_clear(mm,addr,xp)	do { pte_val(*(xp)) = 0; } while (0)
-
-#define pmd_none(x)     (!pmd_val(x))
-/* by removing the _PAGE_KERNEL bit from the comparision, the same pmd_bad
- * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries.
- */
-#define	pmd_bad(x)	((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE)
-#define pmd_present(x)	(pmd_val(x) & _PAGE_PRESENT)
-#define pmd_clear(xp)	do { pmd_val(*(xp)) = 0; } while (0)
-
-#ifndef __ASSEMBLY__
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-
-static inline int pte_write(pte_t pte)          { return pte_val(pte) & _PAGE_WRITE; }
-static inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_MODIFIED; }
-static inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
-static inline int pte_file(pte_t pte)           { return pte_val(pte) & _PAGE_FILE; }
-static inline int pte_special(pte_t pte)	{ return 0; }
-
-static inline pte_t pte_wrprotect(pte_t pte)
-{
-        pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
-        return pte;
-}
-
-static inline pte_t pte_mkclean(pte_t pte)
-{
-	pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); 
-	return pte; 
-}
-
-static inline pte_t pte_mkold(pte_t pte)
-{
-	pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
-	return pte;
-}
-
-static inline pte_t pte_mkwrite(pte_t pte)
-{
-        pte_val(pte) |= _PAGE_WRITE;
-        if (pte_val(pte) & _PAGE_MODIFIED)
-                pte_val(pte) |= _PAGE_SILENT_WRITE;
-        return pte;
-}
-
-static inline pte_t pte_mkdirty(pte_t pte)
-{
-        pte_val(pte) |= _PAGE_MODIFIED;
-        if (pte_val(pte) & _PAGE_WRITE)
-                pte_val(pte) |= _PAGE_SILENT_WRITE;
-        return pte;
-}
-
-static inline pte_t pte_mkyoung(pte_t pte)
-{
-        pte_val(pte) |= _PAGE_ACCESSED;
-        if (pte_val(pte) & _PAGE_READ)
-        {
-                pte_val(pte) |= _PAGE_SILENT_READ;
-                if ((pte_val(pte) & (_PAGE_WRITE | _PAGE_MODIFIED)) ==
-		    (_PAGE_WRITE | _PAGE_MODIFIED))
-                        pte_val(pte) |= _PAGE_SILENT_WRITE;
-        }
-        return pte;
-}
-static inline pte_t pte_mkspecial(pte_t pte)	{ return pte; }
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-
-/* What actually goes as arguments to the various functions is less than
- * obvious, but a rule of thumb is that struct page's goes as struct page *,
- * really physical DRAM addresses are unsigned long's, and DRAM "virtual"
- * addresses (the 0xc0xxxxxx's) goes as void *'s.
- */
-
-static inline pte_t __mk_pte(void * page, pgprot_t pgprot)
-{
-	pte_t pte;
-	/* the PTE needs a physical address */
-	pte_val(pte) = __pa(page) | pgprot_val(pgprot);
-	return pte;
-}
-
-#define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot))
-
-#define mk_pte_phys(physpage, pgprot) \
-({                                                                      \
-        pte_t __pte;                                                    \
-                                                                        \
-        pte_val(__pte) = (physpage) + pgprot_val(pgprot);               \
-        __pte;                                                          \
-})
-
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
-
-
-/* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval
- * __pte_page(pte_val) refers to the "virtual" DRAM interval
- * pte_pagenr refers to the page-number counted starting from the virtual DRAM start
- */
-
-static inline unsigned long __pte_page(pte_t pte)
-{
-	/* the PTE contains a physical address */
-	return (unsigned long)__va(pte_val(pte) & PAGE_MASK);
-}
-
-#define pte_pagenr(pte)         ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
-
-/* permanent address of a page */
-
-#define __page_address(page)    (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
-#define pte_page(pte)           (mem_map+pte_pagenr(pte))
-
-/* only the pte's themselves need to point to physical DRAM (see above)
- * the pagetable links are purely handled within the kernel SW and thus
- * don't need the __pa and __va transformations.
- */
-
-static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
-{ pmd_val(*pmdp) = _PAGE_TABLE | (unsigned long) ptep; }
-
-#define pmd_page(pmd)		(pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
-#define pmd_page_vaddr(pmd)	((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
-
-/* to find an entry in a page-table-directory. */
-#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
-
-/* to find an entry in a page-table-directory */
-static inline pgd_t * pgd_offset(const struct mm_struct *mm, unsigned long address)
-{
-	return mm->pgd + pgd_index(address);
-}
-
-/* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-/* Find an entry in the third-level page table.. */
-#define __pte_offset(address) \
-	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#define pte_offset_kernel(dir, address) \
-	((pte_t *) pmd_page_vaddr(*(dir)) +  __pte_offset(address))
-#define pte_offset_map(dir, address) \
-	((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
-#define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
-
-#define pte_unmap(pte) do { } while (0)
-#define pte_unmap_nested(pte) do { } while (0)
-#define pte_pfn(x)		((unsigned long)(__va((x).pte)) >> PAGE_SHIFT)
-#define pfn_pte(pfn, prot)	__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-
-#define pte_ERROR(e) \
-        printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
-#define pgd_ERROR(e) \
-        printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
-
-
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
-
-/*
- * CRIS doesn't have any external MMU info: the kernel page
- * tables contain all the necessary information.
- * 
- * Actually I am not sure on what this could be used for.
- */
-static inline void update_mmu_cache(struct vm_area_struct * vma,
-	unsigned long address, pte_t pte)
-{
-}
-
-/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
-/* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */
-
-#define __swp_type(x)			(((x).val >> 5) & 0x7f)
-#define __swp_offset(x)			((x).val >> 12)
-#define __swp_entry(type, offset)	((swp_entry_t) { ((type) << 5) | ((offset) << 12) })
-#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x)		((pte_t) { (x).val })
-
-#define kern_addr_valid(addr)   (1)
-
-#include <asm-generic/pgtable.h>
-
-/*
- * No page table caches to initialise
- */
-#define pgtable_cache_init()   do { } while (0)
-
-#define pte_to_pgoff(x)	(pte_val(x) >> 6)
-#define pgoff_to_pte(x)	__pte(((x) << 6) | _PAGE_FILE)
-
-typedef pte_t *pte_addr_t;
-
-#endif /* __ASSEMBLY__ */
-#endif /* _CRIS_PGTABLE_H */
diff --git a/include/asm-cris/poll.h b/include/asm-cris/poll.h
deleted file mode 100644
index c98509d3149e..000000000000
--- a/include/asm-cris/poll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/poll.h>
diff --git a/include/asm-cris/posix_types.h b/include/asm-cris/posix_types.h
deleted file mode 100644
index ce3fb25a460b..000000000000
--- a/include/asm-cris/posix_types.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* $Id: posix_types.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */
-
-/* We cheat a bit and use our C-coded bitops functions from asm/bitops.h */
-/* I guess we should write these in assembler because they are used often. */
-
-#ifndef __ARCH_CRIS_POSIX_TYPES_H
-#define __ARCH_CRIS_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned long	__kernel_ino_t;
-typedef unsigned short	__kernel_mode_t;
-typedef unsigned short	__kernel_nlink_t;
-typedef long		__kernel_off_t;
-typedef int		__kernel_pid_t;
-typedef unsigned short  __kernel_ipc_pid_t;
-typedef unsigned short	__kernel_uid_t;
-typedef unsigned short	__kernel_gid_t;
-typedef __SIZE_TYPE__	__kernel_size_t;
-typedef long		__kernel_ssize_t;
-typedef int		__kernel_ptrdiff_t;
-typedef long		__kernel_time_t;
-typedef long            __kernel_suseconds_t;
-typedef long		__kernel_clock_t;
-typedef int		__kernel_timer_t;
-typedef int		__kernel_clockid_t;
-typedef int		__kernel_daddr_t;
-typedef char *		__kernel_caddr_t;
-typedef unsigned short  __kernel_uid16_t;
-typedef unsigned short  __kernel_gid16_t;
-typedef unsigned int    __kernel_uid32_t;
-typedef unsigned int    __kernel_gid32_t;
-
-typedef unsigned short  __kernel_old_uid_t;
-typedef unsigned short  __kernel_old_gid_t;
-typedef unsigned short	__kernel_old_dev_t;
-
-#ifdef __GNUC__
-typedef long long	__kernel_loff_t;
-#endif
-
-typedef struct {
-	int	val[2];
-} __kernel_fsid_t;
-
-#ifdef __KERNEL__
-
-#undef	__FD_SET
-#define __FD_SET(fd,fdsetp) set_bit(fd, (void *)(fdsetp))
-
-#undef	__FD_CLR
-#define __FD_CLR(fd,fdsetp) clear_bit(fd, (void *)(fdsetp))
-
-#undef	__FD_ISSET
-#define __FD_ISSET(fd,fdsetp) test_bit(fd, (void *)(fdsetp))
-
-#undef	__FD_ZERO
-#define __FD_ZERO(fdsetp) memset((void *)(fdsetp), 0, __FDSET_LONGS << 2)
-
-#endif /* __KERNEL__ */
-
-#endif /* __ARCH_CRIS_POSIX_TYPES_H */
diff --git a/include/asm-cris/processor.h b/include/asm-cris/processor.h
deleted file mode 100644
index cdc0c1dce6be..000000000000
--- a/include/asm-cris/processor.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * include/asm-cris/processor.h
- *
- * Copyright (C) 2000, 2001 Axis Communications AB
- *
- * Authors:         Bjorn Wesen        Initial version
- *
- */
-
-#ifndef __ASM_CRIS_PROCESSOR_H
-#define __ASM_CRIS_PROCESSOR_H
-
-#include <asm/system.h>
-#include <asm/page.h>
-#include <asm/ptrace.h>
-#include <asm/arch/processor.h>
-
-struct task_struct;
-
-#define STACK_TOP	TASK_SIZE
-#define STACK_TOP_MAX	STACK_TOP
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
-
-/* THREAD_SIZE is the size of the task_struct/kernel_stack combo.
- * normally, the stack is found by doing something like p + THREAD_SIZE
- * in CRIS, a page is 8192 bytes, which seems like a sane size
- */
-
-#define THREAD_SIZE       PAGE_SIZE
-#define KERNEL_STACK_SIZE PAGE_SIZE
-
-/*
- * At user->kernel entry, the pt_regs struct is stacked on the top of the kernel-stack.
- * This macro allows us to find those regs for a task.
- * Notice that subsequent pt_regs stackings, like recursive interrupts occurring while
- * we're in the kernel, won't affect this - only the first user->kernel transition
- * registers are reached by this.
- */
-
-#define user_regs(thread_info) (((struct pt_regs *)((unsigned long)(thread_info) + THREAD_SIZE)) - 1)
-
-/*
- * Dito but for the currently running task
- */
-
-#define task_pt_regs(task) user_regs(task_thread_info(task))
-#define current_regs() task_pt_regs(current)
-
-static inline void prepare_to_copy(struct task_struct *tsk)
-{
-}
-
-extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_ESP(tsk)   ((tsk) == current ? rdusp() : (tsk)->thread.usp)
-
-extern unsigned long thread_saved_pc(struct task_struct *tsk);
-
-/* Free all resources held by a thread. */
-static inline void release_thread(struct task_struct *dead_task)
-{
-        /* Nothing needs to be done.  */
-}
-
-#define init_stack      (init_thread_union.stack)
-
-#define cpu_relax()     barrier()
-
-#endif /* __ASM_CRIS_PROCESSOR_H */
diff --git a/include/asm-cris/ptrace.h b/include/asm-cris/ptrace.h
deleted file mode 100644
index d910925e3174..000000000000
--- a/include/asm-cris/ptrace.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef _CRIS_PTRACE_H
-#define _CRIS_PTRACE_H
-
-#include <asm/arch/ptrace.h>
-
-#ifdef __KERNEL__
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS            12
-#define PTRACE_SETREGS            13
-
-#define profile_pc(regs) instruction_pointer(regs)
-
-#endif /* __KERNEL__ */
-
-#endif /* _CRIS_PTRACE_H */
diff --git a/include/asm-cris/resource.h b/include/asm-cris/resource.h
deleted file mode 100644
index b5d29448de4e..000000000000
--- a/include/asm-cris/resource.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _CRIS_RESOURCE_H
-#define _CRIS_RESOURCE_H
-
-#include <asm-generic/resource.h>
-
-#endif
diff --git a/include/asm-cris/rs485.h b/include/asm-cris/rs485.h
deleted file mode 100644
index c331c51b0c2b..000000000000
--- a/include/asm-cris/rs485.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* RS-485 structures */
-
-/* RS-485 support */
-/* Used with ioctl() TIOCSERSETRS485 */
-struct rs485_control {
-        unsigned short rts_on_send;
-        unsigned short rts_after_sent;
-        unsigned long delay_rts_before_send;
-        unsigned short enabled;
-#ifdef __KERNEL__
-        int disable_serial_loopback;
-#endif
-};
-
-/* Used with ioctl() TIOCSERWRRS485 */
-struct rs485_write {
-        unsigned short outc_size;
-        unsigned char *outc;
-};
-
diff --git a/include/asm-cris/rtc.h b/include/asm-cris/rtc.h
deleted file mode 100644
index 17d3019529e1..000000000000
--- a/include/asm-cris/rtc.h
+++ /dev/null
@@ -1,107 +0,0 @@
-
-#ifndef __RTC_H__
-#define __RTC_H__
-
-#ifdef CONFIG_ETRAX_DS1302
-   /* Dallas DS1302 clock/calendar register numbers. */
-#  define RTC_SECONDS      0
-#  define RTC_MINUTES      1
-#  define RTC_HOURS        2
-#  define RTC_DAY_OF_MONTH 3
-#  define RTC_MONTH        4
-#  define RTC_WEEKDAY      5
-#  define RTC_YEAR         6
-#  define RTC_CONTROL      7
-
-   /* Bits in CONTROL register. */
-#  define RTC_CONTROL_WRITEPROTECT	0x80
-#  define RTC_TRICKLECHARGER		8
-
-  /* Bits in TRICKLECHARGER register TCS TCS TCS TCS DS DS RS RS. */
-#  define RTC_TCR_PATTERN	0xA0	/* 1010xxxx */
-#  define RTC_TCR_1DIOD		0x04	/* xxxx01xx */
-#  define RTC_TCR_2DIOD		0x08	/* xxxx10xx */
-#  define RTC_TCR_DISABLED	0x00	/* xxxxxx00 Disabled */
-#  define RTC_TCR_2KOHM		0x01	/* xxxxxx01 2KOhm */
-#  define RTC_TCR_4KOHM		0x02	/* xxxxxx10 4kOhm */
-#  define RTC_TCR_8KOHM		0x03	/* xxxxxx11 8kOhm */
-
-#elif defined(CONFIG_ETRAX_PCF8563)
-   /* I2C bus slave registers. */
-#  define RTC_I2C_READ		0xa3
-#  define RTC_I2C_WRITE		0xa2
-
-   /* Phillips PCF8563 registers. */
-#  define RTC_CONTROL1		0x00		/* Control/Status register 1. */
-#  define RTC_CONTROL2		0x01		/* Control/Status register 2. */
-#  define RTC_CLOCKOUT_FREQ	0x0d		/* CLKOUT frequency. */
-#  define RTC_TIMER_CONTROL	0x0e		/* Timer control. */
-#  define RTC_TIMER_CNTDOWN	0x0f		/* Timer countdown. */
-
-   /* BCD encoded clock registers. */
-#  define RTC_SECONDS		0x02
-#  define RTC_MINUTES		0x03
-#  define RTC_HOURS		0x04
-#  define RTC_DAY_OF_MONTH	0x05
-#  define RTC_WEEKDAY		0x06	/* Not coded in BCD! */
-#  define RTC_MONTH		0x07
-#  define RTC_YEAR		0x08
-#  define RTC_MINUTE_ALARM	0x09
-#  define RTC_HOUR_ALARM	0x0a
-#  define RTC_DAY_ALARM		0x0b
-#  define RTC_WEEKDAY_ALARM 0x0c
-
-#endif
-
-#ifdef CONFIG_ETRAX_DS1302
-extern unsigned char ds1302_readreg(int reg);
-extern void ds1302_writereg(int reg, unsigned char val);
-extern int ds1302_init(void);
-#  define CMOS_READ(x) ds1302_readreg(x)
-#  define CMOS_WRITE(val,reg) ds1302_writereg(reg,val)
-#  define RTC_INIT() ds1302_init()
-#elif defined(CONFIG_ETRAX_PCF8563)
-extern unsigned char pcf8563_readreg(int reg);
-extern void pcf8563_writereg(int reg, unsigned char val);
-extern int pcf8563_init(void);
-#  define CMOS_READ(x) pcf8563_readreg(x)
-#  define CMOS_WRITE(val,reg) pcf8563_writereg(reg,val)
-#  define RTC_INIT() pcf8563_init()
-#else
-  /* No RTC configured so we shouldn't try to access any. */
-#  define CMOS_READ(x) 42
-#  define CMOS_WRITE(x,y)
-#  define RTC_INIT() (-1)
-#endif
-
-/*
- * The struct used to pass data via the following ioctl. Similar to the
- * struct tm in <time.h>, but it needs to be here so that the kernel
- * source is self contained, allowing cross-compiles, etc. etc.
- */
-struct rtc_time {
-	int tm_sec;
-	int tm_min;
-	int tm_hour;
-	int tm_mday;
-	int tm_mon;
-	int tm_year;
-	int tm_wday;
-	int tm_yday;
-	int tm_isdst;
-};
-
-/* ioctl() calls that are permitted to the /dev/rtc interface. */
-#define RTC_MAGIC 'p'
-/* Read RTC time. */
-#define RTC_RD_TIME		_IOR(RTC_MAGIC, 0x09, struct rtc_time)
-/* Set RTC time. */
-#define RTC_SET_TIME		_IOW(RTC_MAGIC, 0x0a, struct rtc_time)
-#define RTC_SET_CHARGE		_IOW(RTC_MAGIC, 0x0b, int)
-/* Voltage low detector */
-#define RTC_VL_READ		_IOR(RTC_MAGIC, 0x13, int)
-/* Clear voltage low information */
-#define RTC_VL_CLR		_IO(RTC_MAGIC, 0x14)
-#define RTC_MAX_IOCTL 0x14
-
-#endif /* __RTC_H__ */
diff --git a/include/asm-cris/scatterlist.h b/include/asm-cris/scatterlist.h
deleted file mode 100644
index faff53ad1f96..000000000000
--- a/include/asm-cris/scatterlist.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef __ASM_CRIS_SCATTERLIST_H
-#define __ASM_CRIS_SCATTERLIST_H
-
-struct scatterlist {
-#ifdef CONFIG_DEBUG_SG
-	unsigned long sg_magic;
-#endif
-	char *  address;    /* Location data is to be transferred to */
-	unsigned int length;
-
-	/* The following is i386 highmem junk - not used by us */
-	unsigned long page_link;
-	unsigned int offset;/* for highmem, page offset */
-
-};
-
-#define sg_dma_address(sg)	((sg)->address)
-#define sg_dma_len(sg)		((sg)->length)
-/* i386 junk */
-
-#define ISA_DMA_THRESHOLD (0x1fffffff)
-
-#endif /* !(__ASM_CRIS_SCATTERLIST_H) */
diff --git a/include/asm-cris/sections.h b/include/asm-cris/sections.h
deleted file mode 100644
index 2c998ce8967b..000000000000
--- a/include/asm-cris/sections.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _CRIS_SECTIONS_H
-#define _CRIS_SECTIONS_H
-
-/* nothing to see, move along */
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/include/asm-cris/segment.h b/include/asm-cris/segment.h
deleted file mode 100644
index c067513beaaf..000000000000
--- a/include/asm-cris/segment.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _ASM_SEGMENT_H
-#define _ASM_SEGMENT_H
-
-typedef struct {
-  unsigned long seg;
-} mm_segment_t;
-
-#endif
diff --git a/include/asm-cris/sembuf.h b/include/asm-cris/sembuf.h
deleted file mode 100644
index 7fed9843796d..000000000000
--- a/include/asm-cris/sembuf.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _CRIS_SEMBUF_H
-#define _CRIS_SEMBUF_H
-
-/* 
- * The semid64_ds structure for CRIS architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct semid64_ds {
-	struct ipc64_perm sem_perm;		/* permissions .. see ipc.h */
-	__kernel_time_t	sem_otime;		/* last semop time */
-	unsigned long	__unused1;
-	__kernel_time_t	sem_ctime;		/* last change time */
-	unsigned long	__unused2;
-	unsigned long	sem_nsems;		/* no. of semaphores in array */
-	unsigned long	__unused3;
-	unsigned long	__unused4;
-};
-
-#endif /* _CRIS_SEMBUF_H */
diff --git a/include/asm-cris/setup.h b/include/asm-cris/setup.h
deleted file mode 100644
index b90728652d1a..000000000000
--- a/include/asm-cris/setup.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _CRIS_SETUP_H
-#define _CRIS_SETUP_H
-
-#define COMMAND_LINE_SIZE	256
-
-#endif
diff --git a/include/asm-cris/shmbuf.h b/include/asm-cris/shmbuf.h
deleted file mode 100644
index 3239e3f000e8..000000000000
--- a/include/asm-cris/shmbuf.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef _CRIS_SHMBUF_H
-#define _CRIS_SHMBUF_H
-
-/* 
- * The shmid64_ds structure for CRIS architecture (same as for i386)
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct shmid64_ds {
-	struct ipc64_perm	shm_perm;	/* operation perms */
-	size_t			shm_segsz;	/* size of segment (bytes) */
-	__kernel_time_t		shm_atime;	/* last attach time */
-	unsigned long		__unused1;
-	__kernel_time_t		shm_dtime;	/* last detach time */
-	unsigned long		__unused2;
-	__kernel_time_t		shm_ctime;	/* last change time */
-	unsigned long		__unused3;
-	__kernel_pid_t		shm_cpid;	/* pid of creator */
-	__kernel_pid_t		shm_lpid;	/* pid of last operator */
-	unsigned long		shm_nattch;	/* no. of current attaches */
-	unsigned long		__unused4;
-	unsigned long		__unused5;
-};
-
-struct shminfo64 {
-	unsigned long	shmmax;
-	unsigned long	shmmin;
-	unsigned long	shmmni;
-	unsigned long	shmseg;
-	unsigned long	shmall;
-	unsigned long	__unused1;
-	unsigned long	__unused2;
-	unsigned long	__unused3;
-	unsigned long	__unused4;
-};
-
-#endif /* _CRIS_SHMBUF_H */
diff --git a/include/asm-cris/shmparam.h b/include/asm-cris/shmparam.h
deleted file mode 100644
index d29d12270687..000000000000
--- a/include/asm-cris/shmparam.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _ASM_CRIS_SHMPARAM_H
-#define _ASM_CRIS_SHMPARAM_H
-
-/* same as asm-i386/ version.. */
-
-#define	SHMLBA PAGE_SIZE		 /* attach addr a multiple of this */
-
-#endif /* _ASM_CRIS_SHMPARAM_H */
diff --git a/include/asm-cris/sigcontext.h b/include/asm-cris/sigcontext.h
deleted file mode 100644
index a1d634e120df..000000000000
--- a/include/asm-cris/sigcontext.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* $Id: sigcontext.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */
-
-#ifndef _ASM_CRIS_SIGCONTEXT_H
-#define _ASM_CRIS_SIGCONTEXT_H
-
-#include <asm/ptrace.h>
-
-/* This struct is saved by setup_frame in signal.c, to keep the current context while
-   a signal handler is executed. It's restored by sys_sigreturn.
-   
-   To keep things simple, we use pt_regs here even though normally you just specify
-   the list of regs to save. Then we can use copy_from_user on the entire regs instead
-   of a bunch of get_user's as well...
-
-*/
-
-struct sigcontext {
-	struct pt_regs regs;  /* needs to be first */
-	unsigned long oldmask;
-	unsigned long usp;    /* usp before stacking this gunk on it */
-};
-
-#endif
-
diff --git a/include/asm-cris/siginfo.h b/include/asm-cris/siginfo.h
deleted file mode 100644
index c1cd6d16928b..000000000000
--- a/include/asm-cris/siginfo.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _CRIS_SIGINFO_H
-#define _CRIS_SIGINFO_H
-
-#include <asm-generic/siginfo.h>
-
-#endif
diff --git a/include/asm-cris/signal.h b/include/asm-cris/signal.h
deleted file mode 100644
index 349ae682b568..000000000000
--- a/include/asm-cris/signal.h
+++ /dev/null
@@ -1,163 +0,0 @@
-#ifndef _ASM_CRIS_SIGNAL_H
-#define _ASM_CRIS_SIGNAL_H
-
-#include <linux/types.h>
-
-/* Avoid too many header ordering problems.  */
-struct siginfo;
-
-#ifdef __KERNEL__
-/* Most things should be clean enough to redefine this at will, if care
-   is taken to make libc match.  */
-
-#define _NSIG		64
-#define _NSIG_BPW	32
-#define _NSIG_WORDS	(_NSIG / _NSIG_BPW)
-
-typedef unsigned long old_sigset_t;		/* at least 32 bits */
-
-typedef struct {
-	unsigned long sig[_NSIG_WORDS];
-} sigset_t;
-
-#else
-/* Here we must cater to libcs that poke about in kernel headers.  */
-
-#define NSIG		32
-typedef unsigned long sigset_t;
-
-#endif /* __KERNEL__ */
-
-#define SIGHUP		 1
-#define SIGINT		 2
-#define SIGQUIT		 3
-#define SIGILL		 4
-#define SIGTRAP		 5
-#define SIGABRT		 6
-#define SIGIOT		 6
-#define SIGBUS		 7
-#define SIGFPE		 8
-#define SIGKILL		 9
-#define SIGUSR1		10
-#define SIGSEGV		11
-#define SIGUSR2		12
-#define SIGPIPE		13
-#define SIGALRM		14
-#define SIGTERM		15
-#define SIGSTKFLT	16
-#define SIGCHLD		17
-#define SIGCONT		18
-#define SIGSTOP		19
-#define SIGTSTP		20
-#define SIGTTIN		21
-#define SIGTTOU		22
-#define SIGURG		23
-#define SIGXCPU		24
-#define SIGXFSZ		25
-#define SIGVTALRM	26
-#define SIGPROF		27
-#define SIGWINCH	28
-#define SIGIO		29
-#define SIGPOLL		SIGIO
-/*
-#define SIGLOST		29
-*/
-#define SIGPWR		30
-#define SIGSYS          31
-#define	SIGUNUSED	31
-
-/* These should not be considered constants from userland.  */
-#define SIGRTMIN        32
-#define SIGRTMAX        _NSIG
-
-/*
- * SA_FLAGS values:
- *
- * SA_ONSTACK indicates that a registered stack_t will be used.
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
- * SA_RESETHAND clears the handler when the signal is delivered.
- * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
- * SA_NODEFER prevents the current signal from being masked in the handler.
- *
- * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
- * Unix names RESETHAND and NODEFER respectively.
- */
-
-#define SA_NOCLDSTOP	0x00000001u
-#define SA_NOCLDWAIT	0x00000002u
-#define SA_SIGINFO	0x00000004u
-#define SA_ONSTACK	0x08000000u
-#define SA_RESTART	0x10000000u
-#define SA_NODEFER	0x40000000u
-#define SA_RESETHAND	0x80000000u
-
-#define SA_NOMASK	SA_NODEFER
-#define SA_ONESHOT	SA_RESETHAND
-
-#define SA_RESTORER	0x04000000
-
-/* 
- * sigaltstack controls
- */
-#define SS_ONSTACK	1
-#define SS_DISABLE	2
-
-#define MINSIGSTKSZ	2048
-#define SIGSTKSZ	8192
-
-#include <asm-generic/signal.h>
-
-#ifdef __KERNEL__
-struct old_sigaction {
-	__sighandler_t sa_handler;
-	old_sigset_t sa_mask;
-	unsigned long sa_flags;
-	void (*sa_restorer)(void);
-};
-
-struct sigaction {
-	__sighandler_t sa_handler;
-	unsigned long sa_flags;
-	void (*sa_restorer)(void);
-	sigset_t sa_mask;		/* mask last for extensibility */
-};
-
-struct k_sigaction {
-	struct sigaction sa;
-};
-#else
-/* Here we must cater to libcs that poke about in kernel headers.  */
-
-struct sigaction {
-	union {
-	  __sighandler_t _sa_handler;
-	  void (*_sa_sigaction)(int, struct siginfo *, void *);
-	} _u;
-	sigset_t sa_mask;
-	unsigned long sa_flags;
-	void (*sa_restorer)(void);
-};
-
-#define sa_handler	_u._sa_handler
-#define sa_sigaction	_u._sa_sigaction
-
-#endif /* __KERNEL__ */
-
-typedef struct sigaltstack {
-	void *ss_sp;
-	int ss_flags;
-	size_t ss_size;
-} stack_t;
-
-#ifdef __KERNEL__
-#include <asm/sigcontext.h>
-
-/* here we could define asm-optimized sigaddset, sigdelset etc. operations. 
- * if we don't, generic ones are used from linux/signal.h
- */
-#define ptrace_signal_deliver(regs, cookie) do { } while (0)
-
-#endif /* __KERNEL__ */
-
-#endif
diff --git a/include/asm-cris/smp.h b/include/asm-cris/smp.h
deleted file mode 100644
index dba33aba3e95..000000000000
--- a/include/asm-cris/smp.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __ASM_SMP_H
-#define __ASM_SMP_H
-
-#include <linux/cpumask.h>
-
-extern cpumask_t phys_cpu_present_map;
-extern cpumask_t cpu_possible_map;
-
-#define raw_smp_processor_id() (current_thread_info()->cpu)
-
-#endif
diff --git a/include/asm-cris/socket.h b/include/asm-cris/socket.h
deleted file mode 100644
index 9df0ca82f5de..000000000000
--- a/include/asm-cris/socket.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef _ASM_SOCKET_H
-#define _ASM_SOCKET_H
-
-/* almost the same as asm-i386/socket.h */
-
-#include <asm/sockios.h>
-
-/* For setsockoptions(2) */
-#define SOL_SOCKET	1
-
-#define SO_DEBUG	1
-#define SO_REUSEADDR	2
-#define SO_TYPE		3
-#define SO_ERROR	4
-#define SO_DONTROUTE	5
-#define SO_BROADCAST	6
-#define SO_SNDBUF	7
-#define SO_RCVBUF	8
-#define SO_SNDBUFFORCE	32
-#define SO_RCVBUFFORCE	33
-#define SO_KEEPALIVE	9
-#define SO_OOBINLINE	10
-#define SO_NO_CHECK	11
-#define SO_PRIORITY	12
-#define SO_LINGER	13
-#define SO_BSDCOMPAT	14
-/* To add :#define SO_REUSEPORT 15 */
-#define SO_PASSCRED	16
-#define SO_PEERCRED	17
-#define SO_RCVLOWAT	18
-#define SO_SNDLOWAT	19
-#define SO_RCVTIMEO	20
-#define SO_SNDTIMEO	21
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION		22
-#define SO_SECURITY_ENCRYPTION_TRANSPORT	23
-#define SO_SECURITY_ENCRYPTION_NETWORK		24
-
-#define SO_BINDTODEVICE	25
-
-/* Socket filtering */
-#define SO_ATTACH_FILTER        26
-#define SO_DETACH_FILTER        27
-
-#define SO_PEERNAME		28
-#define SO_TIMESTAMP           29
-#define SCM_TIMESTAMP          SO_TIMESTAMP
-
-#define SO_ACCEPTCONN          30
-
-#define SO_PEERSEC             31
-#define SO_PASSSEC		34
-#define SO_TIMESTAMPNS		35
-#define SCM_TIMESTAMPNS		SO_TIMESTAMPNS
-
-#define SO_MARK			36
-
-#endif /* _ASM_SOCKET_H */
-
-
diff --git a/include/asm-cris/sockios.h b/include/asm-cris/sockios.h
deleted file mode 100644
index cfe7bfecf599..000000000000
--- a/include/asm-cris/sockios.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ARCH_CRIS_SOCKIOS__
-#define __ARCH_CRIS_SOCKIOS__
-
-/* Socket-level I/O control calls. */
-#define FIOSETOWN 	0x8901
-#define SIOCSPGRP	0x8902
-#define FIOGETOWN	0x8903
-#define SIOCGPGRP	0x8904
-#define SIOCATMARK	0x8905
-#define SIOCGSTAMP	0x8906		/* Get stamp (timeval) */
-#define SIOCGSTAMPNS	0x8907		/* Get stamp (timespec) */
-
-#endif
diff --git a/include/asm-cris/spinlock.h b/include/asm-cris/spinlock.h
deleted file mode 100644
index 2e8ba8afc7af..000000000000
--- a/include/asm-cris/spinlock.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm/arch/spinlock.h>
diff --git a/include/asm-cris/stat.h b/include/asm-cris/stat.h
deleted file mode 100644
index 9e558cc3c43b..000000000000
--- a/include/asm-cris/stat.h
+++ /dev/null
@@ -1,81 +0,0 @@
-#ifndef _CRIS_STAT_H
-#define _CRIS_STAT_H
-
-/* Keep this a verbatim copy of i386 version; tweak CRIS-specific bits in
-   the kernel if necessary.  */
-
-struct __old_kernel_stat {
-	unsigned short st_dev;
-	unsigned short st_ino;
-	unsigned short st_mode;
-	unsigned short st_nlink;
-	unsigned short st_uid;
-	unsigned short st_gid;
-	unsigned short st_rdev;
-	unsigned long  st_size;
-	unsigned long  st_atime;
-	unsigned long  st_mtime;
-	unsigned long  st_ctime;
-};
-
-#define STAT_HAVE_NSEC 1
-
-struct stat {
-	unsigned long  st_dev;
-	unsigned long  st_ino;
-	unsigned short st_mode;
-	unsigned short st_nlink;
-	unsigned short st_uid;
-	unsigned short st_gid;
-	unsigned long  st_rdev;
-	unsigned long  st_size;
-	unsigned long  st_blksize;
-	unsigned long  st_blocks;
-	unsigned long  st_atime;
-	unsigned long  st_atime_nsec;
-	unsigned long  st_mtime;
-	unsigned long  st_mtime_nsec;
-	unsigned long  st_ctime;
-	unsigned long  st_ctime_nsec;
-	unsigned long  __unused4;
-	unsigned long  __unused5;
-};
-
-/* This matches struct stat64 in glibc2.1, hence the absolutely
- * insane amounts of padding around dev_t's.
- */
-struct stat64 {
-	unsigned long long	st_dev;
-	unsigned char	__pad0[4];
-
-#define STAT64_HAS_BROKEN_ST_INO	1
-	unsigned long	__st_ino;
-
-	unsigned int	st_mode;
-	unsigned int	st_nlink;
-
-	unsigned long	st_uid;
-	unsigned long	st_gid;
-
-	unsigned long long	st_rdev;
-	unsigned char	__pad3[4];
-
-	long long	st_size;
-	unsigned long	st_blksize;
-
-	unsigned long	st_blocks;	/* Number 512-byte blocks allocated. */
-	unsigned long	__pad4;		/* future possible st_blocks high bits */
-
-	unsigned long	st_atime;
-	unsigned long	st_atime_nsec;
-
-	unsigned long	st_mtime;
-	unsigned long	st_mtime_nsec;
-
-	unsigned long	st_ctime;
-	unsigned long	st_ctime_nsec;	/* will be high 32 bits of ctime someday */
-
-	unsigned long long	st_ino;
-};
-
-#endif
diff --git a/include/asm-cris/statfs.h b/include/asm-cris/statfs.h
deleted file mode 100644
index fdaf921844bc..000000000000
--- a/include/asm-cris/statfs.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _CRIS_STATFS_H
-#define _CRIS_STATFS_H
-
-#include <asm-generic/statfs.h>
-
-#endif
diff --git a/include/asm-cris/string.h b/include/asm-cris/string.h
deleted file mode 100644
index 691190e99a27..000000000000
--- a/include/asm-cris/string.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef _ASM_CRIS_STRING_H
-#define _ASM_CRIS_STRING_H
-
-/* the optimized memcpy is in arch/cris/lib/string.c */
-
-#define __HAVE_ARCH_MEMCPY
-extern void *memcpy(void *, const void *, size_t);
-
-/* New and improved.  In arch/cris/lib/memset.c */
-
-#define __HAVE_ARCH_MEMSET
-extern void *memset(void *, int, size_t);
-
-#endif
diff --git a/include/asm-cris/sync_serial.h b/include/asm-cris/sync_serial.h
deleted file mode 100644
index d87c24df2b38..000000000000
--- a/include/asm-cris/sync_serial.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * ioctl defines for synchronous serial port driver
- *
- * Copyright (c) 2001-2003 Axis Communications AB
- *
- * Author: Mikael Starvik
- *
- */
-
-#ifndef SYNC_SERIAL_H
-#define SYNC_SERIAL_H
-
-#include <linux/ioctl.h>
-
-#define SSP_SPEED      _IOR('S', 0, unsigned int)
-#define SSP_MODE       _IOR('S', 1, unsigned int)
-#define SSP_FRAME_SYNC _IOR('S', 2, unsigned int)
-#define SSP_IPOLARITY  _IOR('S', 3, unsigned int)
-#define SSP_OPOLARITY  _IOR('S', 4, unsigned int)
-#define SSP_SPI        _IOR('S', 5, unsigned int)
-#define SSP_INBUFCHUNK _IOR('S', 6, unsigned int)
-
-/* Values for SSP_SPEED */
-#define SSP150        0
-#define SSP300        1
-#define SSP600        2
-#define SSP1200       3
-#define SSP2400       4
-#define SSP4800       5
-#define SSP9600       6
-#define SSP19200      7
-#define SSP28800      8
-#define SSP57600      9
-#define SSP115200    10
-#define SSP230400    11
-#define SSP460800    12
-#define SSP921600    13
-#define SSP3125000   14
-#define CODEC        15
-
-#define FREQ_4MHz   0
-#define FREQ_2MHz   1
-#define FREQ_1MHz   2
-#define FREQ_512kHz 3
-#define FREQ_256kHz 4
-#define FREQ_128kHz 5
-#define FREQ_64kHz  6
-#define FREQ_32kHz  7
-
-/* Used by application to set CODEC divider, word rate and frame rate */
-#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) (CODEC | (freq << 8) | (clk_per_sync << 16) | (sync_per_frame << 28))
-
-/* Used by driver to extract speed */
-#define GET_SPEED(x) (x & 0xff)
-#define GET_FREQ(x) ((x & 0xff00) >> 8)
-#define GET_WORD_RATE(x) (((x & 0x0fff0000) >> 16) - 1)
-#define GET_FRAME_RATE(x) (((x & 0xf0000000) >> 28) - 1)
-
-/* Values for SSP_MODE */
-#define MASTER_OUTPUT 0
-#define SLAVE_OUTPUT  1
-#define MASTER_INPUT  2
-#define SLAVE_INPUT   3
-#define MASTER_BIDIR  4
-#define SLAVE_BIDIR   5
-
-/* Values for SSP_FRAME_SYNC */
-#define NORMAL_SYNC                1
-#define EARLY_SYNC                 2
-#define SECOND_WORD_SYNC     0x40000
-
-#define BIT_SYNC                   4
-#define WORD_SYNC                  8
-#define EXTENDED_SYNC           0x10
-
-#define SYNC_OFF                0x20
-#define SYNC_ON                 0x40
-#define WORD_SIZE_8             0x80
-#define WORD_SIZE_12           0x100
-#define WORD_SIZE_16           0x200
-#define WORD_SIZE_24           0x400
-#define WORD_SIZE_32           0x800
-#define BIT_ORDER_LSB         0x1000
-#define BIT_ORDER_MSB         0x2000
-#define FLOW_CONTROL_ENABLE   0x4000
-#define FLOW_CONTROL_DISABLE  0x8000
-#define CLOCK_GATED          0x10000
-#define CLOCK_NOT_GATED      0x20000
-
-/* Values for SSP_IPOLARITY and SSP_OPOLARITY */
-#define CLOCK_NORMAL         1
-#define CLOCK_INVERT         2
-#define CLOCK_INEGEDGE       CLOCK_NORMAL
-#define CLOCK_IPOSEDGE       CLOCK_INVERT
-#define FRAME_NORMAL         4
-#define FRAME_INVERT         8
-#define STATUS_NORMAL      0x10
-#define STATUS_INVERT      0x20
-
-/* Values for SSP_SPI */
-#define SPI_MASTER           0
-#define SPI_SLAVE            1
-
-/* Values for SSP_INBUFCHUNK */
-/* plain integer with the size of DMA chunks */
-
-#endif
diff --git a/include/asm-cris/system.h b/include/asm-cris/system.h
deleted file mode 100644
index 5bcfe5a10907..000000000000
--- a/include/asm-cris/system.h
+++ /dev/null
@@ -1,88 +0,0 @@
-#ifndef __ASM_CRIS_SYSTEM_H
-#define __ASM_CRIS_SYSTEM_H
-
-#include <asm/arch/system.h>
-
-/* the switch_to macro calls resume, an asm function in entry.S which does the actual
- * task switching.
- */
-
-extern struct task_struct *resume(struct task_struct *prev, struct task_struct *next, int);
-#define switch_to(prev,next,last) last = resume(prev,next, \
-					 (int)&((struct task_struct *)0)->thread)
-
-#define barrier() __asm__ __volatile__("": : :"memory")
-#define mb() barrier()
-#define rmb() mb()
-#define wmb() mb()
-#define read_barrier_depends() do { } while(0)
-#define set_mb(var, value)  do { var = value; mb(); } while (0)
-
-#ifdef CONFIG_SMP
-#define smp_mb()        mb()
-#define smp_rmb()       rmb()
-#define smp_wmb()       wmb()
-#define smp_read_barrier_depends()     read_barrier_depends()
-#else
-#define smp_mb()        barrier()
-#define smp_rmb()       barrier()
-#define smp_wmb()       barrier()
-#define smp_read_barrier_depends()     do { } while(0)
-#endif
-
-#define iret()
-
-/*
- * disable hlt during certain critical i/o operations
- */
-#define HAVE_DISABLE_HLT
-void disable_hlt(void);
-void enable_hlt(void);
-
-static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
-{
-  /* since Etrax doesn't have any atomic xchg instructions, we need to disable
-     irq's (if enabled) and do it with move.d's */
-  unsigned long flags,temp;
-  local_irq_save(flags); /* save flags, including irq enable bit and shut off irqs */
-  switch (size) {
-  case 1:
-    *((unsigned char *)&temp) = x;
-    x = *(unsigned char *)ptr;
-    *(unsigned char *)ptr = *((unsigned char *)&temp);
-    break;
-  case 2:
-    *((unsigned short *)&temp) = x;
-    x = *(unsigned short *)ptr;
-    *(unsigned short *)ptr = *((unsigned short *)&temp);
-    break;
-  case 4:
-    temp = x;
-    x = *(unsigned long *)ptr;
-    *(unsigned long *)ptr = temp;
-    break;
-  }
-  local_irq_restore(flags); /* restore irq enable bit */
-  return x;
-}
-
-#include <asm-generic/cmpxchg-local.h>
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n)				 	       \
-	((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
-			(unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#ifndef CONFIG_SMP
-#include <asm-generic/cmpxchg.h>
-#endif
-
-#define arch_align_stack(x) (x)
-
-void default_idle(void);
-
-#endif
diff --git a/include/asm-cris/termbits.h b/include/asm-cris/termbits.h
deleted file mode 100644
index 66e1a7492a0c..000000000000
--- a/include/asm-cris/termbits.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/* $Id: termbits.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */
-
-#ifndef __ARCH_ETRAX100_TERMBITS_H__
-#define __ARCH_ETRAX100_TERMBITS_H__
-
-#include <linux/posix_types.h>
-
-typedef unsigned char	cc_t;
-typedef unsigned int	speed_t;
-typedef unsigned int	tcflag_t;
-
-#define NCCS 19
-struct termios {
-	tcflag_t c_iflag;		/* input mode flags */
-	tcflag_t c_oflag;		/* output mode flags */
-	tcflag_t c_cflag;		/* control mode flags */
-	tcflag_t c_lflag;		/* local mode flags */
-	cc_t c_line;			/* line discipline */
-	cc_t c_cc[NCCS];		/* control characters */
-};
-
-struct termios2 {
-	tcflag_t c_iflag;		/* input mode flags */
-	tcflag_t c_oflag;		/* output mode flags */
-	tcflag_t c_cflag;		/* control mode flags */
-	tcflag_t c_lflag;		/* local mode flags */
-	cc_t c_line;			/* line discipline */
-	cc_t c_cc[NCCS];		/* control characters */
-	speed_t c_ispeed;		/* input speed */
-	speed_t c_ospeed;		/* output speed */
-};
-
-struct ktermios {
-	tcflag_t c_iflag;		/* input mode flags */
-	tcflag_t c_oflag;		/* output mode flags */
-	tcflag_t c_cflag;		/* control mode flags */
-	tcflag_t c_lflag;		/* local mode flags */
-	cc_t c_line;			/* line discipline */
-	cc_t c_cc[NCCS];		/* control characters */
-	speed_t c_ispeed;		/* input speed */
-	speed_t c_ospeed;		/* output speed */
-};
-
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-
-/* c_iflag bits */
-#define IGNBRK	0000001
-#define BRKINT	0000002
-#define IGNPAR	0000004
-#define PARMRK	0000010
-#define INPCK	0000020
-#define ISTRIP	0000040
-#define INLCR	0000100
-#define IGNCR	0000200
-#define ICRNL	0000400
-#define IUCLC	0001000
-#define IXON	0002000
-#define IXANY	0004000
-#define IXOFF	0010000
-#define IMAXBEL	0020000
-#define IUTF8	0040000
-
-/* c_oflag bits */
-#define OPOST	0000001
-#define OLCUC	0000002
-#define ONLCR	0000004
-#define OCRNL	0000010
-#define ONOCR	0000020
-#define ONLRET	0000040
-#define OFILL	0000100
-#define OFDEL	0000200
-#define NLDLY	0000400
-#define   NL0	0000000
-#define   NL1	0000400
-#define CRDLY	0003000
-#define   CR0	0000000
-#define   CR1	0001000
-#define   CR2	0002000
-#define   CR3	0003000
-#define TABDLY	0014000
-#define   TAB0	0000000
-#define   TAB1	0004000
-#define   TAB2	0010000
-#define   TAB3	0014000
-#define   XTABS	0014000
-#define BSDLY	0020000
-#define   BS0	0000000
-#define   BS1	0020000
-#define VTDLY	0040000
-#define   VT0	0000000
-#define   VT1	0040000
-#define FFDLY	0100000
-#define   FF0	0000000
-#define   FF1	0100000
-
-/* c_cflag bit meaning */
-/*
- *     3             2            1
- *    10 987 654 321 098 765 432 109 876 543 210
- *                             |           | ||| CBAUD
- *                                         obaud    
- *
- *                                       ||CSIZE
- *
- *                                     |CSTOP
- *                                    |CREAD
- *                                   |CPARENB
- *
- *                                 |CPARODD 
- *                                |HUPCL
- *                               |CLOCAL
- *                             |CBAUDEX
- *    10 987 654 321 098 765 432 109 876 543 210
- *        |           || ||   CIBAUD, IBSHIFT=16
- *                    ibaud
- *     |CMSPAR
- *    | CRTSCTS
- *       x x xxx xxx x     x xx Free bits
- */
-
-#define CBAUD	0010017
-#define  B0	0000000		/* hang up */
-#define  B50	0000001
-#define  B75	0000002
-#define  B110	0000003
-#define  B134	0000004
-#define  B150	0000005
-#define  B200	0000006
-#define  B300	0000007
-#define  B600	0000010
-#define  B1200	0000011
-#define  B1800	0000012
-#define  B2400	0000013
-#define  B4800	0000014
-#define  B9600	0000015
-#define  B19200	0000016
-#define  B38400	0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE	0000060
-#define   CS5	0000000
-#define   CS6	0000020
-#define   CS7	0000040
-#define   CS8	0000060
-#define CSTOPB	0000100
-#define CREAD	0000200
-#define PARENB	0000400
-#define PARODD	0001000
-#define HUPCL	0002000
-#define CLOCAL	0004000
-#define CBAUDEX 0010000
-#define  BOTHER  0010000
-#define  B57600  0010001
-#define  B115200 0010002
-#define  B230400 0010003
-#define  B460800 0010004
-
-/* Unsupported rates, but needed to avoid compile error. */
-#define   B500000 0010005
-#define   B576000 0010006
-#define  B1000000 0010010
-#define  B1152000 0010011
-#define  B1500000 0010012
-#define  B2000000 0010013
-#define  B2500000 0010014
-#define  B3000000 0010015
-#define  B3500000 0010016
-#define  B4000000 0010017
-
-/* etrax supports these additional three baud rates */
-#define  B921600   0010005
-#define  B1843200  0010006
-#define  B6250000  0010007
-/* ETRAX FS supports this as well */
-#define  B12500000 0010010
-#define CIBAUD	  002003600000	/* input baud rate (used in v32) */
-/* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX
- * shifted left IBSHIFT bits.
- */
-#define IBSHIFT   16
-#define CMSPAR    010000000000 /* mark or space (stick) parity - PARODD=space*/
-#define CRTSCTS	  020000000000		/* flow control */
-
-/* c_lflag bits */
-#define ISIG	0000001
-#define ICANON	0000002
-#define XCASE	0000004
-#define ECHO	0000010
-#define ECHOE	0000020
-#define ECHOK	0000040
-#define ECHONL	0000100
-#define NOFLSH	0000200
-#define TOSTOP	0000400
-#define ECHOCTL	0001000
-#define ECHOPRT	0002000
-#define ECHOKE	0004000
-#define FLUSHO	0010000
-#define PENDIN	0040000
-#define IEXTEN	0100000
-
-/* tcflow() and TCXONC use these */
-#define	TCOOFF		0
-#define	TCOON		1
-#define	TCIOFF		2
-#define	TCION		3
-
-/* tcflush() and TCFLSH use these */
-#define	TCIFLUSH	0
-#define	TCOFLUSH	1
-#define	TCIOFLUSH	2
-
-/* tcsetattr uses these */
-#define	TCSANOW		0
-#define	TCSADRAIN	1
-#define	TCSAFLUSH	2
-
-#endif
diff --git a/include/asm-cris/termios.h b/include/asm-cris/termios.h
deleted file mode 100644
index b0124e6c2e41..000000000000
--- a/include/asm-cris/termios.h
+++ /dev/null
@@ -1,91 +0,0 @@
-#ifndef _CRIS_TERMIOS_H
-#define _CRIS_TERMIOS_H
-
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-#include <asm/rs485.h>
-
-struct winsize {
-	unsigned short ws_row;
-	unsigned short ws_col;
-	unsigned short ws_xpixel;
-	unsigned short ws_ypixel;
-};
-
-#define NCC 8
-struct termio {
-	unsigned short c_iflag;		/* input mode flags */
-	unsigned short c_oflag;		/* output mode flags */
-	unsigned short c_cflag;		/* control mode flags */
-	unsigned short c_lflag;		/* local mode flags */
-	unsigned char c_line;		/* line discipline */
-	unsigned char c_cc[NCC];	/* control characters */
-};
-
-/* modem lines */
-#define TIOCM_LE	0x001
-#define TIOCM_DTR	0x002
-#define TIOCM_RTS	0x004
-#define TIOCM_ST	0x008
-#define TIOCM_SR	0x010
-#define TIOCM_CTS	0x020
-#define TIOCM_CAR	0x040
-#define TIOCM_RNG	0x080
-#define TIOCM_DSR	0x100
-#define TIOCM_CD	TIOCM_CAR
-#define TIOCM_RI	TIOCM_RNG
-#define TIOCM_OUT1	0x2000
-#define TIOCM_OUT2	0x4000
-#define TIOCM_LOOP	0x8000
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-
-#ifdef __KERNEL__
-
-/*	intr=^C		quit=^\		erase=del	kill=^U
-	eof=^D		vtime=\0	vmin=\1		sxtc=\0
-	start=^Q	stop=^S		susp=^Z		eol=\0
-	reprint=^R	discard=^U	werase=^W	lnext=^V
-	eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
-	unsigned short __tmp; \
-	get_user(__tmp,&(termio)->x); \
-	*(unsigned short *) &(termios)->x = __tmp; \
-}
-
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
-	SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
-	SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
-	SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
-	SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
-	copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
-	put_user((termios)->c_iflag, &(termio)->c_iflag); \
-	put_user((termios)->c_oflag, &(termio)->c_oflag); \
-	put_user((termios)->c_cflag, &(termio)->c_cflag); \
-	put_user((termios)->c_lflag, &(termio)->c_lflag); \
-	put_user((termios)->c_line,  &(termio)->c_line); \
-	copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
-#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
-
-#endif	/* __KERNEL__ */
-
-#endif	/* _CRIS_TERMIOS_H */
diff --git a/include/asm-cris/thread_info.h b/include/asm-cris/thread_info.h
deleted file mode 100644
index 7efe1000f99d..000000000000
--- a/include/asm-cris/thread_info.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* thread_info.h: CRIS low-level thread information
- *
- * Copyright (C) 2002  David Howells (dhowells@redhat.com)
- * - Incorporating suggestions made by Linus Torvalds and Dave Miller
- * 
- * CRIS port by Axis Communications
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#ifdef __KERNEL__
-
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-#include <asm/processor.h>
-#include <asm/arch/thread_info.h>
-#include <asm/segment.h>
-#endif
-
-
-/*
- * low level task data that entry.S needs immediate access to
- * - this struct should fit entirely inside of one cache line
- * - this struct shares the supervisor stack pages
- * - if the contents of this structure are changed, the assembly constants must also be changed
- */
-#ifndef __ASSEMBLY__
-struct thread_info {
-	struct task_struct	*task;		/* main task structure */
-	struct exec_domain	*exec_domain;	/* execution domain */
-	unsigned long		flags;		/* low level flags */
-	__u32			cpu;		/* current CPU */
-	int			preempt_count;	/* 0 => preemptable, <0 => BUG */
-	__u32			tls;		/* TLS for this thread */
-
-	mm_segment_t		addr_limit;	/* thread address space:
-					 	   0-0xBFFFFFFF for user-thead
-						   0-0xFFFFFFFF for kernel-thread
-						*/
-	struct restart_block    restart_block;
-	__u8			supervisor_stack[0];
-};
-
-#endif
-
-#define PREEMPT_ACTIVE		0x10000000
-
-/*
- * macros/functions for gaining access to the thread information structure
- *
- * preempt_count needs to be 1 initially, until the scheduler is functional.
- */
-#ifndef __ASSEMBLY__
-#define INIT_THREAD_INFO(tsk)				\
-{							\
-	.task		= &tsk,				\
-	.exec_domain	= &default_exec_domain,		\
-	.flags		= 0,				\
-	.cpu		= 0,				\
-	.preempt_count	= 1,				\
-	.addr_limit	= KERNEL_DS,			\
-	.restart_block = {				\
-		       .fn = do_no_restart_syscall,	\
-	},						\
-}
-
-#define init_thread_info	(init_thread_union.thread_info)
-
-/* thread information allocation */
-#define alloc_thread_info(tsk) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1))
-#define free_thread_info(ti) free_pages((unsigned long) (ti), 1)
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * thread information flags
- * - these are process state flags that various assembly files may need to access
- * - pending work-to-be-done flags are in LSW
- * - other flags in MSW
- */
-#define TIF_SYSCALL_TRACE	0	/* syscall trace active */
-#define TIF_NOTIFY_RESUME	1	/* resumption notification requested */
-#define TIF_SIGPENDING		2	/* signal pending */
-#define TIF_NEED_RESCHED	3	/* rescheduling necessary */
-#define TIF_RESTORE_SIGMASK	9	/* restore signal mask in do_signal() */
-#define TIF_POLLING_NRFLAG	16	/* true if poll_idle() is polling TIF_NEED_RESCHED */
-#define TIF_MEMDIE		17
-
-#define _TIF_SYSCALL_TRACE	(1<<TIF_SYSCALL_TRACE)
-#define _TIF_NOTIFY_RESUME	(1<<TIF_NOTIFY_RESUME)
-#define _TIF_SIGPENDING		(1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED	(1<<TIF_NEED_RESCHED)
-#define _TIF_RESTORE_SIGMASK	(1<<TIF_RESTORE_SIGMASK)
-#define _TIF_POLLING_NRFLAG	(1<<TIF_POLLING_NRFLAG)
-
-#define _TIF_WORK_MASK		0x0000FFFE	/* work to do on interrupt/exception return */
-#define _TIF_ALLWORK_MASK	0x0000FFFF	/* work to do on any return to u-space */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-cris/timex.h b/include/asm-cris/timex.h
deleted file mode 100644
index b92e0e80fe86..000000000000
--- a/include/asm-cris/timex.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * linux/include/asm-cris/timex.h
- *
- * CRIS architecture timex specifications
- */
-
-#ifndef _ASM_CRIS_TIMEX_H
-#define _ASM_CRIS_TIMEX_H
-
-#include <asm/arch/timex.h>
-
-/*
- * We don't have a cycle-counter.. but we do not support SMP anyway where this is
- * used so it does not matter.
- */
-
-typedef unsigned long long cycles_t;
-
-static inline cycles_t get_cycles(void)
-{
-        return 0;
-}
-
-#endif
diff --git a/include/asm-cris/tlb.h b/include/asm-cris/tlb.h
deleted file mode 100644
index 7724246a2601..000000000000
--- a/include/asm-cris/tlb.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _CRIS_TLB_H
-#define _CRIS_TLB_H
-
-#include <linux/pagemap.h>
-
-#include <asm/arch/tlb.h>
-
-/*
- * cris doesn't need any special per-pte or
- * per-vma handling..
- */
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
-
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-#include <asm-generic/tlb.h>
-
-#endif
diff --git a/include/asm-cris/tlbflush.h b/include/asm-cris/tlbflush.h
deleted file mode 100644
index 20697e7ef4f2..000000000000
--- a/include/asm-cris/tlbflush.h
+++ /dev/null
@@ -1,48 +0,0 @@
-#ifndef _CRIS_TLBFLUSH_H
-#define _CRIS_TLBFLUSH_H
-
-#include <linux/mm.h>
-#include <asm/processor.h>
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-
-/*
- * TLB flushing (implemented in arch/cris/mm/tlb.c):
- *
- *  - flush_tlb() flushes the current mm struct TLBs
- *  - flush_tlb_all() flushes all processes TLBs
- *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
- *  - flush_tlb_page(vma, vmaddr) flushes one page
- *  - flush_tlb_range(mm, start, end) flushes a range of pages
- *
- */
-
-extern void __flush_tlb_all(void);
-extern void __flush_tlb_mm(struct mm_struct *mm);
-extern void __flush_tlb_page(struct vm_area_struct *vma,
-			   unsigned long addr);
-
-#ifdef CONFIG_SMP
-extern void flush_tlb_all(void);
-extern void flush_tlb_mm(struct mm_struct *mm);
-extern void flush_tlb_page(struct vm_area_struct *vma, 
-			   unsigned long addr);
-#else
-#define flush_tlb_all __flush_tlb_all
-#define flush_tlb_mm __flush_tlb_mm
-#define flush_tlb_page __flush_tlb_page
-#endif
-
-static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
-{
-	flush_tlb_mm(vma->vm_mm);
-}
-
-static inline void flush_tlb(void)
-{
-	flush_tlb_mm(current->mm);
-}
-
-#define flush_tlb_kernel_range(start, end) flush_tlb_all()
-
-#endif /* _CRIS_TLBFLUSH_H */
diff --git a/include/asm-cris/topology.h b/include/asm-cris/topology.h
deleted file mode 100644
index 2ac613d32a89..000000000000
--- a/include/asm-cris/topology.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_CRIS_TOPOLOGY_H
-#define _ASM_CRIS_TOPOLOGY_H
-
-#include <asm-generic/topology.h>
-
-#endif /* _ASM_CRIS_TOPOLOGY_H */
diff --git a/include/asm-cris/types.h b/include/asm-cris/types.h
deleted file mode 100644
index 5790262cbe8a..000000000000
--- a/include/asm-cris/types.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef _ETRAX_TYPES_H
-#define _ETRAX_TYPES_H
-
-#include <asm-generic/int-ll64.h>
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned short umode_t;
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-#define BITS_PER_LONG 32
-
-#ifndef __ASSEMBLY__
-
-/* Dma addresses are 32-bits wide, just like our other addresses.  */
- 
-typedef u32 dma_addr_t;
-typedef u32 dma64_addr_t;
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-
-#endif
diff --git a/include/asm-cris/uaccess.h b/include/asm-cris/uaccess.h
deleted file mode 100644
index ea11eaf0e922..000000000000
--- a/include/asm-cris/uaccess.h
+++ /dev/null
@@ -1,404 +0,0 @@
-/* 
- * Authors:    Bjorn Wesen (bjornw@axis.com)
- *	       Hans-Peter Nilsson (hp@axis.com)
- */
-
-/* Asm:s have been tweaked (within the domain of correctness) to give
-   satisfactory results for "gcc version 2.96 20000427 (experimental)".
-
-   Check regularly...
-
-   Register $r9 is chosen for temporaries, being a call-clobbered register
-   first in line to be used (notably for local blocks), not colliding with
-   parameter registers.  */
-
-#ifndef _CRIS_UACCESS_H
-#define _CRIS_UACCESS_H
-
-#ifndef __ASSEMBLY__
-#include <linux/sched.h>
-#include <linux/errno.h>
-#include <asm/processor.h>
-#include <asm/page.h>
-
-#define VERIFY_READ	0
-#define VERIFY_WRITE	1
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not.  If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- *
- * For historical reasons, these macros are grossly misnamed.
- */
-
-#define MAKE_MM_SEG(s)	((mm_segment_t) { (s) })
-
-/* addr_limit is the maximum accessible address for the task. we misuse
- * the KERNEL_DS and USER_DS values to both assign and compare the 
- * addr_limit values through the equally misnamed get/set_fs macros.
- * (see above)
- */
-
-#define KERNEL_DS	MAKE_MM_SEG(0xFFFFFFFF)
-#define USER_DS		MAKE_MM_SEG(TASK_SIZE)
-
-#define get_ds()	(KERNEL_DS)
-#define get_fs()	(current_thread_info()->addr_limit)
-#define set_fs(x)	(current_thread_info()->addr_limit = (x))
-
-#define segment_eq(a,b)	((a).seg == (b).seg)
-
-#define __kernel_ok (segment_eq(get_fs(), KERNEL_DS))
-#define __user_ok(addr,size) (((size) <= TASK_SIZE)&&((addr) <= TASK_SIZE-(size)))
-#define __access_ok(addr,size) (__kernel_ok || __user_ok((addr),(size)))
-#define access_ok(type,addr,size) __access_ok((unsigned long)(addr),(size))
-
-#include <asm/arch/uaccess.h>
-
-/*
- * The exception table consists of pairs of addresses: the first is the
- * address of an instruction that is allowed to fault, and the second is
- * the address at which the program should continue.  No registers are
- * modified, so it is entirely up to the continuation code to figure out
- * what to do.
- *
- * All the routines below use bits of fixup code that are out of line
- * with the main instruction path.  This means when everything is well,
- * we don't even have to jump over them.  Further, they do not intrude
- * on our cache or tlb entries.
- */
-
-struct exception_table_entry
-{
-	unsigned long insn, fixup;
-};
-
-/*
- * These are the main single-value transfer routines.  They automatically
- * use the right size if we just have the right pointer type.
- *
- * This gets kind of ugly. We want to return _two_ values in "get_user()"
- * and yet we don't want to do any pointers, because that is too much
- * of a performance impact. Thus we have a few rather ugly macros here,
- * and hide all the ugliness from the user.
- *
- * The "__xxx" versions of the user access functions are versions that
- * do not verify the address space, that must have been done previously
- * with a separate "access_ok()" call (this is used when we do multiple
- * accesses to the same area of user memory).
- *
- * As we use the same address space for kernel and user data on
- * CRIS, we can just do these as direct assignments.  (Of course, the
- * exception handling means that it's no longer "just"...)
- */
-#define get_user(x,ptr) \
-  __get_user_check((x),(ptr),sizeof(*(ptr)))
-#define put_user(x,ptr) \
-  __put_user_check((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
-
-#define __get_user(x,ptr) \
-  __get_user_nocheck((x),(ptr),sizeof(*(ptr)))
-#define __put_user(x,ptr) \
-  __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
-
-extern long __put_user_bad(void);
-
-#define __put_user_size(x,ptr,size,retval)			\
-do {								\
-	retval = 0;						\
-	switch (size) {						\
-	  case 1: __put_user_asm(x,ptr,retval,"move.b"); break;	\
-	  case 2: __put_user_asm(x,ptr,retval,"move.w"); break;	\
-	  case 4: __put_user_asm(x,ptr,retval,"move.d"); break;	\
-	  case 8: __put_user_asm_64(x,ptr,retval); break;	\
-	  default: __put_user_bad();				\
-	}							\
-} while (0)
-
-#define __get_user_size(x,ptr,size,retval)			\
-do {								\
-	retval = 0;						\
-	switch (size) {						\
-	  case 1: __get_user_asm(x,ptr,retval,"move.b"); break;	\
-	  case 2: __get_user_asm(x,ptr,retval,"move.w"); break;	\
-	  case 4: __get_user_asm(x,ptr,retval,"move.d"); break;	\
-	  case 8: __get_user_asm_64(x,ptr,retval); break;	\
-	  default: (x) = __get_user_bad();			\
-	}							\
-} while (0)
-
-#define __put_user_nocheck(x,ptr,size)			\
-({							\
-	long __pu_err;					\
-	__put_user_size((x),(ptr),(size),__pu_err);	\
-	__pu_err;					\
-})
-
-#define __put_user_check(x,ptr,size)				\
-({								\
-	long __pu_err = -EFAULT;				\
-	__typeof__(*(ptr)) *__pu_addr = (ptr);			\
-	if (access_ok(VERIFY_WRITE,__pu_addr,size))		\
-		__put_user_size((x),__pu_addr,(size),__pu_err);	\
-	__pu_err;						\
-})
-
-struct __large_struct { unsigned long buf[100]; };
-#define __m(x) (*(struct __large_struct *)(x))
-
-
-
-#define __get_user_nocheck(x,ptr,size)				\
-({								\
-	long __gu_err, __gu_val;				\
-	__get_user_size(__gu_val,(ptr),(size),__gu_err);	\
-	(x) = (__typeof__(*(ptr)))__gu_val;			\
-	__gu_err;						\
-})
-
-#define __get_user_check(x,ptr,size)					\
-({									\
-	long __gu_err = -EFAULT, __gu_val = 0;				\
-	const __typeof__(*(ptr)) *__gu_addr = (ptr);			\
-	if (access_ok(VERIFY_READ,__gu_addr,size))			\
-		__get_user_size(__gu_val,__gu_addr,(size),__gu_err);	\
-	(x) = (__typeof__(*(ptr)))__gu_val;				\
-	__gu_err;							\
-})
-
-extern long __get_user_bad(void);
-
-/* More complex functions.  Most are inline, but some call functions that
-   live in lib/usercopy.c  */
-
-extern unsigned long __copy_user(void __user *to, const void *from, unsigned long n);
-extern unsigned long __copy_user_zeroing(void *to, const void __user *from, unsigned long n);
-extern unsigned long __do_clear_user(void __user *to, unsigned long n);
-
-static inline unsigned long
-__generic_copy_to_user(void __user *to, const void *from, unsigned long n)
-{
-	if (access_ok(VERIFY_WRITE, to, n))
-		return __copy_user(to,from,n);
-	return n;
-}
-
-static inline unsigned long
-__generic_copy_from_user(void *to, const void __user *from, unsigned long n)
-{
-	if (access_ok(VERIFY_READ, from, n))
-		return __copy_user_zeroing(to,from,n);
-	return n;
-}
-
-static inline unsigned long
-__generic_clear_user(void __user *to, unsigned long n)
-{
-	if (access_ok(VERIFY_WRITE, to, n))
-		return __do_clear_user(to,n);
-	return n;
-}
-
-static inline long
-__strncpy_from_user(char *dst, const char __user *src, long count)
-{
-	return __do_strncpy_from_user(dst, src, count);
-}
-
-static inline long
-strncpy_from_user(char *dst, const char __user *src, long count)
-{
-	long res = -EFAULT;
-	if (access_ok(VERIFY_READ, src, 1))
-		res = __do_strncpy_from_user(dst, src, count);
-	return res;
-}
-
-
-/* Note that these expand awfully if made into switch constructs, so
-   don't do that.  */
-
-static inline unsigned long
-__constant_copy_from_user(void *to, const void __user *from, unsigned long n)
-{
-	unsigned long ret = 0;
-	if (n == 0)
-		;
-	else if (n == 1)
-		__asm_copy_from_user_1(to, from, ret);
-	else if (n == 2)
-		__asm_copy_from_user_2(to, from, ret);
-	else if (n == 3)
-		__asm_copy_from_user_3(to, from, ret);
-	else if (n == 4)
-		__asm_copy_from_user_4(to, from, ret);
-	else if (n == 5)
-		__asm_copy_from_user_5(to, from, ret);
-	else if (n == 6)
-		__asm_copy_from_user_6(to, from, ret);
-	else if (n == 7)
-		__asm_copy_from_user_7(to, from, ret);
-	else if (n == 8)
-		__asm_copy_from_user_8(to, from, ret);
-	else if (n == 9)
-		__asm_copy_from_user_9(to, from, ret);
-	else if (n == 10)
-		__asm_copy_from_user_10(to, from, ret);
-	else if (n == 11)
-		__asm_copy_from_user_11(to, from, ret);
-	else if (n == 12)
-		__asm_copy_from_user_12(to, from, ret);
-	else if (n == 13)
-		__asm_copy_from_user_13(to, from, ret);
-	else if (n == 14)
-		__asm_copy_from_user_14(to, from, ret);
-	else if (n == 15)
-		__asm_copy_from_user_15(to, from, ret);
-	else if (n == 16)
-		__asm_copy_from_user_16(to, from, ret);
-	else if (n == 20)
-		__asm_copy_from_user_20(to, from, ret);
-	else if (n == 24)
-		__asm_copy_from_user_24(to, from, ret);
-	else
-		ret = __generic_copy_from_user(to, from, n);
-
-	return ret;
-}
-
-/* Ditto, don't make a switch out of this.  */
-
-static inline unsigned long
-__constant_copy_to_user(void __user *to, const void *from, unsigned long n)
-{
-	unsigned long ret = 0;
-	if (n == 0)
-		;
-	else if (n == 1)
-		__asm_copy_to_user_1(to, from, ret);
-	else if (n == 2)
-		__asm_copy_to_user_2(to, from, ret);
-	else if (n == 3)
-		__asm_copy_to_user_3(to, from, ret);
-	else if (n == 4)
-		__asm_copy_to_user_4(to, from, ret);
-	else if (n == 5)
-		__asm_copy_to_user_5(to, from, ret);
-	else if (n == 6)
-		__asm_copy_to_user_6(to, from, ret);
-	else if (n == 7)
-		__asm_copy_to_user_7(to, from, ret);
-	else if (n == 8)
-		__asm_copy_to_user_8(to, from, ret);
-	else if (n == 9)
-		__asm_copy_to_user_9(to, from, ret);
-	else if (n == 10)
-		__asm_copy_to_user_10(to, from, ret);
-	else if (n == 11)
-		__asm_copy_to_user_11(to, from, ret);
-	else if (n == 12)
-		__asm_copy_to_user_12(to, from, ret);
-	else if (n == 13)
-		__asm_copy_to_user_13(to, from, ret);
-	else if (n == 14)
-		__asm_copy_to_user_14(to, from, ret);
-	else if (n == 15)
-		__asm_copy_to_user_15(to, from, ret);
-	else if (n == 16)
-		__asm_copy_to_user_16(to, from, ret);
-	else if (n == 20)
-		__asm_copy_to_user_20(to, from, ret);
-	else if (n == 24)
-		__asm_copy_to_user_24(to, from, ret);
-	else
-		ret = __generic_copy_to_user(to, from, n);
-
-	return ret;
-}
-
-/* No switch, please.  */
-
-static inline unsigned long
-__constant_clear_user(void __user *to, unsigned long n)
-{
-	unsigned long ret = 0;
-	if (n == 0)
-		;
-	else if (n == 1)
-		__asm_clear_1(to, ret);
-	else if (n == 2)
-		__asm_clear_2(to, ret);
-	else if (n == 3)
-		__asm_clear_3(to, ret);
-	else if (n == 4)
-		__asm_clear_4(to, ret);
-	else if (n == 8)
-		__asm_clear_8(to, ret);
-	else if (n == 12)
-		__asm_clear_12(to, ret);
-	else if (n == 16)
-		__asm_clear_16(to, ret);
-	else if (n == 20)
-		__asm_clear_20(to, ret);
-	else if (n == 24)
-		__asm_clear_24(to, ret);
-	else
-		ret = __generic_clear_user(to, n);
-
-	return ret;
-}
-
-
-#define clear_user(to, n)			\
-(__builtin_constant_p(n) ?			\
- __constant_clear_user(to, n) :			\
- __generic_clear_user(to, n))
-
-#define copy_from_user(to, from, n)		\
-(__builtin_constant_p(n) ?			\
- __constant_copy_from_user(to, from, n) :	\
- __generic_copy_from_user(to, from, n))
-
-#define copy_to_user(to, from, n)		\
-(__builtin_constant_p(n) ?			\
- __constant_copy_to_user(to, from, n) :		\
- __generic_copy_to_user(to, from, n))
-
-/* We let the __ versions of copy_from/to_user inline, because they're often
- * used in fast paths and have only a small space overhead.
- */
-
-static inline unsigned long
-__generic_copy_from_user_nocheck(void *to, const void __user *from,
-				 unsigned long n)
-{
-	return __copy_user_zeroing(to,from,n);
-}
-
-static inline unsigned long
-__generic_copy_to_user_nocheck(void __user *to, const void *from,
-			       unsigned long n)
-{
-	return __copy_user(to,from,n);
-}
-
-static inline unsigned long
-__generic_clear_user_nocheck(void __user *to, unsigned long n)
-{
-	return __do_clear_user(to,n);
-}
-
-/* without checking */
-
-#define __copy_to_user(to,from,n)   __generic_copy_to_user_nocheck((to),(from),(n))
-#define __copy_from_user(to,from,n) __generic_copy_from_user_nocheck((to),(from),(n))
-#define __copy_to_user_inatomic __copy_to_user
-#define __copy_from_user_inatomic __copy_from_user
-#define __clear_user(to,n) __generic_clear_user_nocheck((to),(n))
-
-#define strlen_user(str)	strnlen_user((str), 0x7ffffffe)
-
-#endif  /* __ASSEMBLY__ */
-
-#endif	/* _CRIS_UACCESS_H */
diff --git a/include/asm-cris/ucontext.h b/include/asm-cris/ucontext.h
deleted file mode 100644
index eed6ad5eb3f2..000000000000
--- a/include/asm-cris/ucontext.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _ASM_CRIS_UCONTEXT_H
-#define _ASM_CRIS_UCONTEXT_H
-
-struct ucontext {
-	unsigned long	  uc_flags;
-	struct ucontext  *uc_link;
-	stack_t		  uc_stack;
-	struct sigcontext uc_mcontext;
-	sigset_t	  uc_sigmask;	/* mask last for extensibility */
-};
-
-#endif /* !_ASM_CRIS_UCONTEXT_H */
diff --git a/include/asm-cris/unaligned.h b/include/asm-cris/unaligned.h
deleted file mode 100644
index 7b3f3fec567c..000000000000
--- a/include/asm-cris/unaligned.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _ASM_CRIS_UNALIGNED_H
-#define _ASM_CRIS_UNALIGNED_H
-
-/*
- * CRIS can do unaligned accesses itself. 
- */
-#include <linux/unaligned/access_ok.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned	__get_unaligned_le
-#define put_unaligned	__put_unaligned_le
-
-#endif /* _ASM_CRIS_UNALIGNED_H */
diff --git a/include/asm-cris/unistd.h b/include/asm-cris/unistd.h
deleted file mode 100644
index 76398ef87e9b..000000000000
--- a/include/asm-cris/unistd.h
+++ /dev/null
@@ -1,374 +0,0 @@
-#ifndef _ASM_CRIS_UNISTD_H_
-#define _ASM_CRIS_UNISTD_H_
-
-/*
- * This file contains the system call numbers, and stub macros for libc.
- */
-
-#define __NR_restart_syscall      0
-#define __NR_exit		  1
-#define __NR_fork		  2
-#define __NR_read		  3
-#define __NR_write		  4
-#define __NR_open		  5
-#define __NR_close		  6
-#define __NR_waitpid		  7
-#define __NR_creat		  8
-#define __NR_link		  9
-#define __NR_unlink		 10
-#define __NR_execve		 11
-#define __NR_chdir		 12
-#define __NR_time		 13
-#define __NR_mknod		 14
-#define __NR_chmod		 15
-#define __NR_lchown		 16
-#define __NR_break		 17
-#define __NR_oldstat		 18
-#define __NR_lseek		 19
-#define __NR_getpid		 20
-#define __NR_mount		 21
-#define __NR_umount		 22
-#define __NR_setuid		 23
-#define __NR_getuid		 24
-#define __NR_stime		 25
-#define __NR_ptrace		 26
-#define __NR_alarm		 27
-#define __NR_oldfstat		 28
-#define __NR_pause		 29
-#define __NR_utime		 30
-#define __NR_stty		 31
-#define __NR_gtty		 32
-#define __NR_access		 33
-#define __NR_nice		 34
-#define __NR_ftime		 35
-#define __NR_sync		 36
-#define __NR_kill		 37
-#define __NR_rename		 38
-#define __NR_mkdir		 39
-#define __NR_rmdir		 40
-#define __NR_dup		 41
-#define __NR_pipe		 42
-#define __NR_times		 43
-#define __NR_prof		 44
-#define __NR_brk		 45
-#define __NR_setgid		 46
-#define __NR_getgid		 47
-#define __NR_signal		 48
-#define __NR_geteuid		 49
-#define __NR_getegid		 50
-#define __NR_acct		 51
-#define __NR_umount2		 52
-#define __NR_lock		 53
-#define __NR_ioctl		 54
-#define __NR_fcntl		 55
-#define __NR_mpx		 56
-#define __NR_setpgid		 57
-#define __NR_ulimit		 58
-#define __NR_oldolduname	 59
-#define __NR_umask		 60
-#define __NR_chroot		 61
-#define __NR_ustat		 62
-#define __NR_dup2		 63
-#define __NR_getppid		 64
-#define __NR_getpgrp		 65
-#define __NR_setsid		 66
-#define __NR_sigaction		 67
-#define __NR_sgetmask		 68
-#define __NR_ssetmask		 69
-#define __NR_setreuid		 70
-#define __NR_setregid		 71
-#define __NR_sigsuspend		 72
-#define __NR_sigpending		 73
-#define __NR_sethostname	 74
-#define __NR_setrlimit		 75
-#define __NR_getrlimit		 76
-#define __NR_getrusage		 77
-#define __NR_gettimeofday	 78
-#define __NR_settimeofday	 79
-#define __NR_getgroups		 80
-#define __NR_setgroups		 81
-#define __NR_select		 82
-#define __NR_symlink		 83
-#define __NR_oldlstat		 84
-#define __NR_readlink		 85
-#define __NR_uselib		 86
-#define __NR_swapon		 87
-#define __NR_reboot		 88
-#define __NR_readdir		 89
-#define __NR_mmap		 90
-#define __NR_munmap		 91
-#define __NR_truncate		 92
-#define __NR_ftruncate		 93
-#define __NR_fchmod		 94
-#define __NR_fchown		 95
-#define __NR_getpriority	 96
-#define __NR_setpriority	 97
-#define __NR_profil		 98
-#define __NR_statfs		 99
-#define __NR_fstatfs		100
-#define __NR_ioperm		101
-#define __NR_socketcall		102
-#define __NR_syslog		103
-#define __NR_setitimer		104
-#define __NR_getitimer		105
-#define __NR_stat		106
-#define __NR_lstat		107
-#define __NR_fstat		108
-#define __NR_olduname		109
-#define __NR_iopl		110
-#define __NR_vhangup		111
-#define __NR_idle		112
-#define __NR_vm86		113
-#define __NR_wait4		114
-#define __NR_swapoff		115
-#define __NR_sysinfo		116
-#define __NR_ipc		117
-#define __NR_fsync		118
-#define __NR_sigreturn		119
-#define __NR_clone		120
-#define __NR_setdomainname	121
-#define __NR_uname		122
-#define __NR_modify_ldt		123
-#define __NR_adjtimex		124
-#define __NR_mprotect		125
-#define __NR_sigprocmask	126
-#define __NR_create_module	127
-#define __NR_init_module	128
-#define __NR_delete_module	129
-#define __NR_get_kernel_syms	130
-#define __NR_quotactl		131
-#define __NR_getpgid		132
-#define __NR_fchdir		133
-#define __NR_bdflush		134
-#define __NR_sysfs		135
-#define __NR_personality	136
-#define __NR_afs_syscall	137 /* Syscall for Andrew File System */
-#define __NR_setfsuid		138
-#define __NR_setfsgid		139
-#define __NR__llseek		140
-#define __NR_getdents		141
-#define __NR__newselect		142
-#define __NR_flock		143
-#define __NR_msync		144
-#define __NR_readv		145
-#define __NR_writev		146
-#define __NR_getsid		147
-#define __NR_fdatasync		148
-#define __NR__sysctl		149
-#define __NR_mlock		150
-#define __NR_munlock		151
-#define __NR_mlockall		152
-#define __NR_munlockall		153
-#define __NR_sched_setparam		154
-#define __NR_sched_getparam		155
-#define __NR_sched_setscheduler		156
-#define __NR_sched_getscheduler		157
-#define __NR_sched_yield		158
-#define __NR_sched_get_priority_max	159
-#define __NR_sched_get_priority_min	160
-#define __NR_sched_rr_get_interval	161
-#define __NR_nanosleep		162
-#define __NR_mremap		163
-#define __NR_setresuid		164
-#define __NR_getresuid		165
-
-#define __NR_query_module	167
-#define __NR_poll		168
-#define __NR_nfsservctl		169
-#define __NR_setresgid		170
-#define __NR_getresgid		171
-#define __NR_prctl              172
-#define __NR_rt_sigreturn	173
-#define __NR_rt_sigaction	174
-#define __NR_rt_sigprocmask	175
-#define __NR_rt_sigpending	176
-#define __NR_rt_sigtimedwait	177
-#define __NR_rt_sigqueueinfo	178
-#define __NR_rt_sigsuspend	179
-#define __NR_pread64		180
-#define __NR_pwrite64		181
-#define __NR_chown		182
-#define __NR_getcwd		183
-#define __NR_capget		184
-#define __NR_capset		185
-#define __NR_sigaltstack	186
-#define __NR_sendfile		187
-#define __NR_getpmsg		188	/* some people actually want streams */
-#define __NR_putpmsg		189	/* some people actually want streams */
-#define __NR_vfork		190
-#define __NR_ugetrlimit		191	/* SuS compliant getrlimit */
-#define __NR_mmap2		192
-#define __NR_truncate64		193
-#define __NR_ftruncate64	194
-#define __NR_stat64		195
-#define __NR_lstat64		196
-#define __NR_fstat64		197
-#define __NR_lchown32		198
-#define __NR_getuid32		199
-#define __NR_getgid32		200
-#define __NR_geteuid32		201
-#define __NR_getegid32		202
-#define __NR_setreuid32		203
-#define __NR_setregid32		204
-#define __NR_getgroups32	205
-#define __NR_setgroups32	206
-#define __NR_fchown32		207
-#define __NR_setresuid32	208
-#define __NR_getresuid32	209
-#define __NR_setresgid32	210
-#define __NR_getresgid32	211
-#define __NR_chown32		212
-#define __NR_setuid32		213
-#define __NR_setgid32		214
-#define __NR_setfsuid32		215
-#define __NR_setfsgid32		216
-#define __NR_pivot_root		217
-#define __NR_mincore		218
-#define __NR_madvise		219
-#define __NR_getdents64		220
-#define __NR_fcntl64		221
-/* 223 is unused */
-#define __NR_gettid             224
-#define __NR_readahead          225
-#define __NR_setxattr		226
-#define __NR_lsetxattr		227
-#define __NR_fsetxattr		228
-#define __NR_getxattr		229
-#define __NR_lgetxattr		230
-#define __NR_fgetxattr		231
-#define __NR_listxattr		232
-#define __NR_llistxattr		233
-#define __NR_flistxattr		234
-#define __NR_removexattr	235
-#define __NR_lremovexattr	236
-#define __NR_fremovexattr	237
-#define __NR_tkill		238
-#define __NR_sendfile64		239
-#define __NR_futex		240
-#define __NR_sched_setaffinity	241
-#define __NR_sched_getaffinity	242
-#define __NR_set_thread_area	243
-#define __NR_get_thread_area	244
-#define __NR_io_setup		245
-#define __NR_io_destroy		246
-#define __NR_io_getevents	247
-#define __NR_io_submit		248
-#define __NR_io_cancel		249
-#define __NR_fadvise64		250
-/* 251 is available for reuse (was briefly sys_set_zone_reclaim) */
-#define __NR_exit_group		252
-#define __NR_lookup_dcookie	253
-#define __NR_epoll_create	254
-#define __NR_epoll_ctl		255
-#define __NR_epoll_wait		256
-#define __NR_remap_file_pages	257
-#define __NR_set_tid_address	258
-#define __NR_timer_create	259
-#define __NR_timer_settime	(__NR_timer_create+1)
-#define __NR_timer_gettime	(__NR_timer_create+2)
-#define __NR_timer_getoverrun	(__NR_timer_create+3)
-#define __NR_timer_delete	(__NR_timer_create+4)
-#define __NR_clock_settime	(__NR_timer_create+5)
-#define __NR_clock_gettime	(__NR_timer_create+6)
-#define __NR_clock_getres	(__NR_timer_create+7)
-#define __NR_clock_nanosleep	(__NR_timer_create+8)
-#define __NR_statfs64		268
-#define __NR_fstatfs64		269
-#define __NR_tgkill		270
-#define __NR_utimes		271
-#define __NR_fadvise64_64	272
-#define __NR_vserver		273
-#define __NR_mbind		274
-#define __NR_get_mempolicy	275
-#define __NR_set_mempolicy	276
-#define __NR_mq_open 		277
-#define __NR_mq_unlink		(__NR_mq_open+1)
-#define __NR_mq_timedsend	(__NR_mq_open+2)
-#define __NR_mq_timedreceive	(__NR_mq_open+3)
-#define __NR_mq_notify		(__NR_mq_open+4)
-#define __NR_mq_getsetattr	(__NR_mq_open+5)
-#define __NR_kexec_load		283
-#define __NR_waitid		284
-/* #define __NR_sys_setaltroot	285 */
-#define __NR_add_key		286
-#define __NR_request_key	287
-#define __NR_keyctl		288
-#define __NR_ioprio_set		289
-#define __NR_ioprio_get		290
-#define __NR_inotify_init	291
-#define __NR_inotify_add_watch	292
-#define __NR_inotify_rm_watch	293
-#define __NR_migrate_pages	294
-#define __NR_openat		295
-#define __NR_mkdirat		296
-#define __NR_mknodat		297
-#define __NR_fchownat		298
-#define __NR_futimesat		299
-#define __NR_fstatat64		300
-#define __NR_unlinkat		301
-#define __NR_renameat		302
-#define __NR_linkat		303
-#define __NR_symlinkat		304
-#define __NR_readlinkat		305
-#define __NR_fchmodat		306
-#define __NR_faccessat		307
-#define __NR_pselect6		308
-#define __NR_ppoll		309
-#define __NR_unshare		310
-#define __NR_set_robust_list	311
-#define __NR_get_robust_list	312
-#define __NR_splice		313
-#define __NR_sync_file_range	314
-#define __NR_tee		315
-#define __NR_vmsplice		316
-#define __NR_move_pages		317
-#define __NR_getcpu		318
-#define __NR_epoll_pwait	319
-#define __NR_utimensat		320
-#define __NR_signalfd		321
-#define __NR_timerfd_create	322
-#define __NR_eventfd		323
-#define __NR_fallocate		324
-#define __NR_timerfd_settime	325
-#define __NR_timerfd_gettime	326
-
-#ifdef __KERNEL__
-
-#define NR_syscalls 327
-
-#include <asm/arch/unistd.h>
-
-#define __ARCH_WANT_IPC_PARSE_VERSION
-#define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_OLD_STAT
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SGETMASK
-#define __ARCH_WANT_SYS_SIGNAL
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_OLD_GETRLIMIT
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_SIGPENDING
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_RT_SIGACTION
-#define __ARCH_WANT_SYS_RT_SIGSUSPEND
-
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_CRIS_UNISTD_H_ */
diff --git a/include/asm-cris/user.h b/include/asm-cris/user.h
deleted file mode 100644
index 73e60fcbcf38..000000000000
--- a/include/asm-cris/user.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#ifndef __ASM_CRIS_USER_H
-#define __ASM_CRIS_USER_H
-
-#include <linux/types.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-#include <asm/arch/user.h>
-
-/*
- * Core file format: The core file is written in such a way that gdb
- * can understand it and provide useful information to the user (under
- * linux we use the `trad-core' bfd).  The file contents are as follows:
- *
- *  upage: 1 page consisting of a user struct that tells gdb
- *	what is present in the file.  Directly after this is a
- *	copy of the task_struct, which is currently not used by gdb,
- *	but it may come in handy at some point.  All of the registers
- *	are stored as part of the upage.  The upage should always be
- *	only one page long.
- *  data: The data segment follows next.  We use current->end_text to
- *	current->brk to pick up all of the user variables, plus any memory
- *	that may have been sbrk'ed.  No attempt is made to determine if a
- *	page is demand-zero or if a page is totally unused, we just cover
- *	the entire range.  All of the addresses are rounded in such a way
- *	that an integral number of pages is written.
- *  stack: We need the stack information in order to get a meaningful
- *	backtrace.  We need to write the data from usp to
- *	current->start_stack, so we round each of these in order to be able
- *	to write an integer number of pages.
- */
-        
-struct user {
-	struct user_regs_struct	regs;		/* entire machine state */
-	size_t		u_tsize;		/* text size (pages) */
-	size_t		u_dsize;		/* data size (pages) */
-	size_t		u_ssize;		/* stack size (pages) */
-	unsigned long	start_code;		/* text starting address */
-	unsigned long	start_data;		/* data starting address */
-	unsigned long	start_stack;		/* stack starting address */
-	long int	signal;			/* signal causing core dump */
-	unsigned long	u_ar0;			/* help gdb find registers */
-	unsigned long	magic;			/* identifies a core file */
-	char		u_comm[32];		/* user command name */
-};
-
-#define NBPG			PAGE_SIZE
-#define UPAGES			1
-#define HOST_TEXT_START_ADDR	(u.start_code)
-#define HOST_DATA_START_ADDR	(u.start_data)
-#define HOST_STACK_END_ADDR	(u.start_stack + u.u_ssize * NBPG)
-
-#endif /* __ASM_CRIS_USER_H */
diff --git a/include/asm-frv/elf.h b/include/asm-frv/elf.h
index 9fb946bb7dc9..7279ec07d62e 100644
--- a/include/asm-frv/elf.h
+++ b/include/asm-frv/elf.h
@@ -137,6 +137,6 @@ do {											\
 
 #define ELF_PLATFORM  (NULL)
 
-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
 
 #endif
diff --git a/include/asm-frv/ide.h b/include/asm-frv/ide.h
index 7ebcc56a2229..361076611855 100644
--- a/include/asm-frv/ide.h
+++ b/include/asm-frv/ide.h
@@ -18,15 +18,7 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 
-/****************************************************************************/
-/*
- * some bits needed for parts of the IDE subsystem to compile
- */
-#define __ide_mm_insw(port, addr, n)	insw((unsigned long) (port), addr, n)
-#define __ide_mm_insl(port, addr, n)	insl((unsigned long) (port), addr, n)
-#define __ide_mm_outsw(port, addr, n)	outsw((unsigned long) (port), addr, n)
-#define __ide_mm_outsl(port, addr, n)	outsl((unsigned long) (port), addr, n)
-
+#include <asm-generic/ide_iops.h>
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_IDE_H */
diff --git a/include/asm-frv/unaligned.h b/include/asm-frv/unaligned.h
index 839a2fbffa0f..6c61c05b2e0c 100644
--- a/include/asm-frv/unaligned.h
+++ b/include/asm-frv/unaligned.h
@@ -13,7 +13,7 @@
 #define _ASM_UNALIGNED_H
 
 #include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/be_struct.h>
 #include <linux/unaligned/generic.h>
 
 #define get_unaligned	__get_unaligned_be
diff --git a/include/asm-generic/atomic.h b/include/asm-generic/atomic.h
index 4ec0a296bdec..7abdaa91ccd3 100644
--- a/include/asm-generic/atomic.h
+++ b/include/asm-generic/atomic.h
@@ -251,7 +251,7 @@ static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u)
 #define atomic_long_cmpxchg(l, old, new) \
 	(atomic_cmpxchg((atomic_t *)(l), (old), (new)))
 #define atomic_long_xchg(v, new) \
-	(atomic_xchg((atomic_t *)(l), (new)))
+	(atomic_xchg((atomic_t *)(v), (new)))
 
 #endif  /*  BITS_PER_LONG == 64  */
 
diff --git a/include/asm-generic/audit_write.h b/include/asm-generic/audit_write.h
index f10d367fb2a5..c5f1c2c920e2 100644
--- a/include/asm-generic/audit_write.h
+++ b/include/asm-generic/audit_write.h
@@ -1,6 +1,8 @@
 #include <asm-generic/audit_dir_write.h>
 __NR_acct,
+#ifdef __NR_swapon
 __NR_swapon,
+#endif
 __NR_quotactl,
 __NR_truncate,
 #ifdef __NR_truncate64
diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
index edc6ba82e090..8af276361bf2 100644
--- a/include/asm-generic/bug.h
+++ b/include/asm-generic/bug.h
@@ -8,9 +8,17 @@
 #ifdef CONFIG_GENERIC_BUG
 #ifndef __ASSEMBLY__
 struct bug_entry {
+#ifndef CONFIG_GENERIC_BUG_RELATIVE_POINTERS
 	unsigned long	bug_addr;
+#else
+	signed int	bug_addr_disp;
+#endif
 #ifdef CONFIG_DEBUG_BUGVERBOSE
+#ifndef CONFIG_GENERIC_BUG_RELATIVE_POINTERS
 	const char	*file;
+#else
+	signed int	file_disp;
+#endif
 	unsigned short	line;
 #endif
 	unsigned short	flags;
@@ -22,7 +30,7 @@ struct bug_entry {
 
 #ifndef HAVE_ARCH_BUG
 #define BUG() do { \
-	printk("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
+	printk("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
 	panic("BUG!"); \
 } while (0)
 #endif
@@ -33,15 +41,14 @@ struct bug_entry {
 
 #ifndef __WARN
 #ifndef __ASSEMBLY__
-extern void warn_on_slowpath(const char *file, const int line);
 extern void warn_slowpath(const char *file, const int line,
 		const char *fmt, ...) __attribute__((format(printf, 3, 4)));
 #define WANT_WARN_ON_SLOWPATH
 #endif
-#define __WARN() warn_on_slowpath(__FILE__, __LINE__)
-#define __WARN_printf(arg...) warn_slowpath(__FILE__, __LINE__, arg)
+#define __WARN()		warn_slowpath(__FILE__, __LINE__, NULL)
+#define __WARN_printf(arg...)	warn_slowpath(__FILE__, __LINE__, arg)
 #else
-#define __WARN_printf(arg...) __WARN()
+#define __WARN_printf(arg...)	do { printk(arg); __WARN(); } while (0)
 #endif
 
 #ifndef WARN_ON
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 0f99ad38b012..81797ec9ab29 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -35,11 +35,17 @@ struct module;
  * @label: for diagnostics
  * @dev: optional device providing the GPIOs
  * @owner: helps prevent removal of modules exporting active GPIOs
+ * @request: optional hook for chip-specific activation, such as
+ *	enabling module power and clock; may sleep
+ * @free: optional hook for chip-specific deactivation, such as
+ *	disabling module power and clock; may sleep
  * @direction_input: configures signal "offset" as input, or returns error
  * @get: returns value for signal "offset"; for output signals this
  *	returns either the value actually sensed, or zero
  * @direction_output: configures signal "offset" as output, or returns error
  * @set: assigns output value for signal "offset"
+ * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
+ *	implementation may not sleep
  * @dbg_show: optional routine to show contents in debugfs; default code
  *	will be used when this is omitted, but custom code can show extra
  *	state (such as pullup/pulldown configuration).
@@ -61,10 +67,15 @@ struct module;
  * is calculated by subtracting @base from the gpio number.
  */
 struct gpio_chip {
-	char			*label;
+	const char		*label;
 	struct device		*dev;
 	struct module		*owner;
 
+	int			(*request)(struct gpio_chip *chip,
+						unsigned offset);
+	void			(*free)(struct gpio_chip *chip,
+						unsigned offset);
+
 	int			(*direction_input)(struct gpio_chip *chip,
 						unsigned offset);
 	int			(*get)(struct gpio_chip *chip,
@@ -73,6 +84,10 @@ struct gpio_chip {
 						unsigned offset, int value);
 	void			(*set)(struct gpio_chip *chip,
 						unsigned offset, int value);
+
+	int			(*to_irq)(struct gpio_chip *chip,
+						unsigned offset);
+
 	void			(*dbg_show)(struct seq_file *s,
 						struct gpio_chip *chip);
 	int			base;
@@ -112,6 +127,7 @@ extern void __gpio_set_value(unsigned gpio, int value);
 
 extern int __gpio_cansleep(unsigned gpio);
 
+extern int __gpio_to_irq(unsigned gpio);
 
 #ifdef CONFIG_GPIO_SYSFS
 
diff --git a/include/asm-generic/kdebug.h b/include/asm-generic/kdebug.h
index 2b799c90b2d4..11e57b6a85fc 100644
--- a/include/asm-generic/kdebug.h
+++ b/include/asm-generic/kdebug.h
@@ -3,6 +3,7 @@
 
 enum die_val {
 	DIE_UNUSED,
+	DIE_OOPS=1
 };
 
 #endif /* _ASM_GENERIC_KDEBUG_H */
diff --git a/include/asm-generic/memory_model.h b/include/asm-generic/memory_model.h
index ae060c62aff1..36fa286adad5 100644
--- a/include/asm-generic/memory_model.h
+++ b/include/asm-generic/memory_model.h
@@ -34,7 +34,7 @@
 
 #define __pfn_to_page(pfn)			\
 ({	unsigned long __pfn = (pfn);		\
-	unsigned long __nid = arch_pfn_to_nid(pfn);  \
+	unsigned long __nid = arch_pfn_to_nid(__pfn);  \
 	NODE_DATA(__nid)->node_mem_map + arch_local_page_offset(__pfn, __nid);\
 })
 
@@ -49,7 +49,7 @@
 
 /* memmap is virtually contigious.  */
 #define __pfn_to_page(pfn)	(vmemmap + (pfn))
-#define __page_to_pfn(page)	((page) - vmemmap)
+#define __page_to_pfn(page)	(unsigned long)((page) - vmemmap)
 
 #elif defined(CONFIG_SPARSEMEM)
 /*
diff --git a/include/asm-generic/mutex-dec.h b/include/asm-generic/mutex-dec.h
index ed108be6743f..f104af7cf437 100644
--- a/include/asm-generic/mutex-dec.h
+++ b/include/asm-generic/mutex-dec.h
@@ -22,8 +22,6 @@ __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
 {
 	if (unlikely(atomic_dec_return(count) < 0))
 		fail_fn(count);
-	else
-		smp_mb();
 }
 
 /**
@@ -41,10 +39,7 @@ __mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
 {
 	if (unlikely(atomic_dec_return(count) < 0))
 		return fail_fn(count);
-	else {
-		smp_mb();
-		return 0;
-	}
+	return 0;
 }
 
 /**
@@ -63,7 +58,6 @@ __mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
 static inline void
 __mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
 {
-	smp_mb();
 	if (unlikely(atomic_inc_return(count) <= 0))
 		fail_fn(count);
 }
@@ -88,25 +82,9 @@ __mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
 static inline int
 __mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
 {
-	/*
-	 * We have two variants here. The cmpxchg based one is the best one
-	 * because it never induce a false contention state.  It is included
-	 * here because architectures using the inc/dec algorithms over the
-	 * xchg ones are much more likely to support cmpxchg natively.
-	 *
-	 * If not we fall back to the spinlock based variant - that is
-	 * just as efficient (and simpler) as a 'destructive' probing of
-	 * the mutex state would be.
-	 */
-#ifdef __HAVE_ARCH_CMPXCHG
-	if (likely(atomic_cmpxchg(count, 1, 0) == 1)) {
-		smp_mb();
+	if (likely(atomic_cmpxchg(count, 1, 0) == 1))
 		return 1;
-	}
 	return 0;
-#else
-	return fail_fn(count);
-#endif
 }
 
 #endif
diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h
index 7b9cd2cbfebe..580a6d35c700 100644
--- a/include/asm-generic/mutex-xchg.h
+++ b/include/asm-generic/mutex-xchg.h
@@ -27,8 +27,6 @@ __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
 {
 	if (unlikely(atomic_xchg(count, 0) != 1))
 		fail_fn(count);
-	else
-		smp_mb();
 }
 
 /**
@@ -46,10 +44,7 @@ __mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
 {
 	if (unlikely(atomic_xchg(count, 0) != 1))
 		return fail_fn(count);
-	else {
-		smp_mb();
-		return 0;
-	}
+	return 0;
 }
 
 /**
@@ -67,7 +62,6 @@ __mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
 static inline void
 __mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
 {
-	smp_mb();
 	if (unlikely(atomic_xchg(count, 1) != 0))
 		fail_fn(count);
 }
@@ -110,7 +104,6 @@ __mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
 		if (prev < 0)
 			prev = 0;
 	}
-	smp_mb();
 
 	return prev;
 }
diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h
index ef87f889ef62..72ebe91005a8 100644
--- a/include/asm-generic/pgtable.h
+++ b/include/asm-generic/pgtable.h
@@ -129,6 +129,10 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addres
 #define move_pte(pte, prot, old_addr, new_addr)	(pte)
 #endif
 
+#ifndef pgprot_writecombine
+#define pgprot_writecombine pgprot_noncached
+#endif
+
 /*
  * When walking page tables, get the address of the next boundary,
  * or the end address of the range if that comes earlier.  Although no
@@ -289,6 +293,52 @@ static inline void ptep_modify_prot_commit(struct mm_struct *mm,
 #define arch_flush_lazy_cpu_mode()	do {} while (0)
 #endif
 
+#ifndef __HAVE_PFNMAP_TRACKING
+/*
+ * Interface that can be used by architecture code to keep track of
+ * memory type of pfn mappings (remap_pfn_range, vm_insert_pfn)
+ *
+ * track_pfn_vma_new is called when a _new_ pfn mapping is being established
+ * for physical range indicated by pfn and size.
+ */
+static inline int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t prot,
+					unsigned long pfn, unsigned long size)
+{
+	return 0;
+}
+
+/*
+ * Interface that can be used by architecture code to keep track of
+ * memory type of pfn mappings (remap_pfn_range, vm_insert_pfn)
+ *
+ * track_pfn_vma_copy is called when vma that is covering the pfnmap gets
+ * copied through copy_page_range().
+ */
+static inline int track_pfn_vma_copy(struct vm_area_struct *vma)
+{
+	return 0;
+}
+
+/*
+ * Interface that can be used by architecture code to keep track of
+ * memory type of pfn mappings (remap_pfn_range, vm_insert_pfn)
+ *
+ * untrack_pfn_vma is called while unmapping a pfnmap for a region.
+ * untrack can be called for a specific region indicated by pfn and size or
+ * can be for the entire vma (in which case size can be zero).
+ */
+static inline void untrack_pfn_vma(struct vm_area_struct *vma,
+					unsigned long pfn, unsigned long size)
+{
+}
+#else
+extern int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t prot,
+				unsigned long pfn, unsigned long size);
+extern int track_pfn_vma_copy(struct vm_area_struct *vma);
+extern void untrack_pfn_vma(struct vm_area_struct *vma, unsigned long pfn,
+				unsigned long size);
+#endif
+
 #endif /* !__ASSEMBLY__ */
 
 #endif /* _ASM_GENERIC_PGTABLE_H */
diff --git a/include/asm-generic/rtc.h b/include/asm-generic/rtc.h
index 71ef3f0b9685..89061c1a67d4 100644
--- a/include/asm-generic/rtc.h
+++ b/include/asm-generic/rtc.h
@@ -84,12 +84,12 @@ static inline unsigned int get_rtc_time(struct rtc_time *time)
 
 	if (!(ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
 	{
-		BCD_TO_BIN(time->tm_sec);
-		BCD_TO_BIN(time->tm_min);
-		BCD_TO_BIN(time->tm_hour);
-		BCD_TO_BIN(time->tm_mday);
-		BCD_TO_BIN(time->tm_mon);
-		BCD_TO_BIN(time->tm_year);
+		time->tm_sec = bcd2bin(time->tm_sec);
+		time->tm_min = bcd2bin(time->tm_min);
+		time->tm_hour = bcd2bin(time->tm_hour);
+		time->tm_mday = bcd2bin(time->tm_mday);
+		time->tm_mon = bcd2bin(time->tm_mon);
+		time->tm_year = bcd2bin(time->tm_year);
 	}
 
 #ifdef CONFIG_MACH_DECSTATION
@@ -159,12 +159,12 @@ static inline int set_rtc_time(struct rtc_time *time)
 
 	if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY)
 	    || RTC_ALWAYS_BCD) {
-		BIN_TO_BCD(sec);
-		BIN_TO_BCD(min);
-		BIN_TO_BCD(hrs);
-		BIN_TO_BCD(day);
-		BIN_TO_BCD(mon);
-		BIN_TO_BCD(yrs);
+		sec = bin2bcd(sec);
+		min = bin2bcd(min);
+		hrs = bin2bcd(hrs);
+		day = bin2bcd(day);
+		mon = bin2bcd(mon);
+		yrs = bin2bcd(yrs);
 	}
 
 	save_control = CMOS_READ(RTC_CONTROL);
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index 7440a0dceddb..c61fab1dd2f8 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -37,6 +37,29 @@
 #define MEM_DISCARD(sec) *(.mem##sec)
 #endif
 
+#ifdef CONFIG_FTRACE_MCOUNT_RECORD
+#define MCOUNT_REC()	VMLINUX_SYMBOL(__start_mcount_loc) = .; \
+			*(__mcount_loc)				\
+			VMLINUX_SYMBOL(__stop_mcount_loc) = .;
+#else
+#define MCOUNT_REC()
+#endif
+
+#ifdef CONFIG_TRACE_BRANCH_PROFILING
+#define LIKELY_PROFILE()	VMLINUX_SYMBOL(__start_annotated_branch_profile) = .; \
+				*(_ftrace_annotated_branch)			      \
+				VMLINUX_SYMBOL(__stop_annotated_branch_profile) = .;
+#else
+#define LIKELY_PROFILE()
+#endif
+
+#ifdef CONFIG_PROFILE_ALL_BRANCHES
+#define BRANCH_PROFILE()	VMLINUX_SYMBOL(__start_branch_profile) = .;   \
+				*(_ftrace_branch)			      \
+				VMLINUX_SYMBOL(__stop_branch_profile) = .;
+#else
+#define BRANCH_PROFILE()
+#endif
 
 /* .data section */
 #define DATA_DATA							\
@@ -52,7 +75,13 @@
 	. = ALIGN(8);							\
 	VMLINUX_SYMBOL(__start___markers) = .;				\
 	*(__markers)							\
-	VMLINUX_SYMBOL(__stop___markers) = .;
+	VMLINUX_SYMBOL(__stop___markers) = .;				\
+	. = ALIGN(32);							\
+	VMLINUX_SYMBOL(__start___tracepoints) = .;			\
+	*(__tracepoints)						\
+	VMLINUX_SYMBOL(__stop___tracepoints) = .;			\
+	LIKELY_PROFILE()		       				\
+	BRANCH_PROFILE()
 
 #define RO_DATA(align)							\
 	. = ALIGN((align));						\
@@ -61,6 +90,7 @@
 		*(.rodata) *(.rodata.*)					\
 		*(__vermagic)		/* Kernel version magic */	\
 		*(__markers_strings)	/* Markers: strings */		\
+		*(__tracepoints_strings)/* Tracepoints: strings */	\
 	}								\
 									\
 	.rodata1          : AT(ADDR(.rodata1) - LOAD_OFFSET) {		\
@@ -188,6 +218,7 @@
 	/* __*init sections */						\
 	__init_rodata : AT(ADDR(__init_rodata) - LOAD_OFFSET) {		\
 		*(.ref.rodata)						\
+		MCOUNT_REC()						\
 		DEV_KEEP(init.rodata)					\
 		DEV_KEEP(exit.rodata)					\
 		CPU_KEEP(init.rodata)					\
@@ -257,6 +288,16 @@
 		*(.kprobes.text)					\
 		VMLINUX_SYMBOL(__kprobes_text_end) = .;
 
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+#define IRQENTRY_TEXT							\
+		ALIGN_FUNCTION();					\
+		VMLINUX_SYMBOL(__irqentry_text_start) = .;		\
+		*(.irqentry.text)					\
+		VMLINUX_SYMBOL(__irqentry_text_end) = .;
+#else
+#define IRQENTRY_TEXT
+#endif
+
 /* Section used for early init (in .S files) */
 #define HEAD_TEXT  *(.head.text)
 
@@ -268,7 +309,15 @@
 	CPU_DISCARD(init.data)						\
 	CPU_DISCARD(init.rodata)					\
 	MEM_DISCARD(init.data)						\
-	MEM_DISCARD(init.rodata)
+	MEM_DISCARD(init.rodata)					\
+	/* implement dynamic printk debug */				\
+	VMLINUX_SYMBOL(__start___verbose_strings) = .;                  \
+	*(__verbose_strings)                                            \
+	VMLINUX_SYMBOL(__stop___verbose_strings) = .;                   \
+	. = ALIGN(8);							\
+	VMLINUX_SYMBOL(__start___verbose) = .;                          \
+	*(__verbose)                                                    \
+	VMLINUX_SYMBOL(__stop___verbose) = .;
 
 #define INIT_TEXT							\
 	*(.init.text)							\
diff --git a/include/asm-h8300/timer.h b/include/asm-h8300/timer.h
new file mode 100644
index 000000000000..def80464d38f
--- /dev/null
+++ b/include/asm-h8300/timer.h
@@ -0,0 +1,25 @@
+#ifndef __H8300_TIMER_H
+#define __H8300_TIMER_H
+
+void h8300_timer_tick(void);
+void h8300_timer_setup(void);
+void h8300_gettod(unsigned int *year, unsigned int *mon, unsigned int *day,
+		   unsigned int *hour, unsigned int *min, unsigned int *sec);
+
+#define TIMER_FREQ (CONFIG_CPU_CLOCK*10000) /* Timer input freq. */
+
+#define calc_param(cnt, div, rate, limit)			\
+do {								\
+	cnt = TIMER_FREQ / HZ;					\
+	for (div = 0; div < ARRAY_SIZE(divide_rate); div++) {	\
+		if (rate[div] == 0)				\
+			continue;				\
+		if ((cnt / rate[div]) > limit)			\
+			break;					\
+	}							\
+	if (div == ARRAY_SIZE(divide_rate))			\
+		panic("Timer counter overflow");		\
+	cnt /= divide_rate[div];				\
+} while(0)
+
+#endif
diff --git a/include/asm-m32r/elf.h b/include/asm-m32r/elf.h
index 67bcd77494a5..0cc34c94bf2b 100644
--- a/include/asm-m32r/elf.h
+++ b/include/asm-m32r/elf.h
@@ -129,6 +129,6 @@ typedef elf_fpreg_t elf_fpregset_t;
    intent than poking at uname or /proc/cpuinfo.  */
 #define ELF_PLATFORM	(NULL)
 
-#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
 
 #endif  /* _ASM_M32R__ELF_H */
diff --git a/include/asm-m32r/system.h b/include/asm-m32r/system.h
index 70a57c8c002b..c980f5ba8de7 100644
--- a/include/asm-m32r/system.h
+++ b/include/asm-m32r/system.h
@@ -23,7 +23,7 @@
  */
 
 #if defined(CONFIG_FRAME_POINTER) || \
-	!defined(CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER)
+	!defined(CONFIG_SCHED_OMIT_FRAME_POINTER)
 #define M32R_PUSH_FP "	push fp\n"
 #define M32R_POP_FP  "	pop  fp\n"
 #else
diff --git a/include/asm-m68k/byteorder.h b/include/asm-m68k/byteorder.h
index 81d420b35c80..b354acdafec8 100644
--- a/include/asm-m68k/byteorder.h
+++ b/include/asm-m68k/byteorder.h
@@ -4,22 +4,16 @@
 #include <asm/types.h>
 #include <linux/compiler.h>
 
-#ifdef __GNUC__
+#define __BIG_ENDIAN
+#define __SWAB_64_THRU_32__
 
-static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 val)
+static inline __attribute_const__ __u32 __arch_swab32(__u32 val)
 {
 	__asm__("rolw #8,%0; swap %0; rolw #8,%0" : "=d" (val) : "0" (val));
 	return val;
 }
-#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch_swab32 __arch_swab32
 
-#endif
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-#  define __BYTEORDER_HAS_U64__
-#  define __SWAB_64_THRU_32__
-#endif
-
-#include <linux/byteorder/big_endian.h>
+#include <linux/byteorder.h>
 
 #endif /* _M68K_BYTEORDER_H */
diff --git a/include/asm-m68k/elf.h b/include/asm-m68k/elf.h
index 14ea42152b97..0b0f49eb876b 100644
--- a/include/asm-m68k/elf.h
+++ b/include/asm-m68k/elf.h
@@ -114,6 +114,6 @@ typedef struct user_m68kfp_struct elf_fpregset_t;
 
 #define ELF_PLATFORM  (NULL)
 
-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
 
 #endif
diff --git a/include/asm-m68k/ide.h b/include/asm-m68k/ide.h
index 1daf6cbdd9f0..b996a3c8cff5 100644
--- a/include/asm-m68k/ide.h
+++ b/include/asm-m68k/ide.h
@@ -92,15 +92,6 @@
 #define outsw_swapw(port, addr, n)	raw_outsw_swapw((u16 *)port, addr, n)
 #endif
 
-
-/* Q40 and Atari have byteswapped IDE busses and since many interesting
- * values in the identification string are text, chars and words they
- * happened to be almost correct without swapping.. However *_capacity
- * is needed for drives over 8 GB. RZ */
-#if defined(CONFIG_Q40) || defined(CONFIG_ATARI)
-#define M68K_IDE_SWAPW  (MACH_IS_Q40 || MACH_IS_ATARI)
-#endif
-
 #ifdef CONFIG_BLK_DEV_FALCON_IDE
 #define IDE_ARCH_LOCK
 
diff --git a/include/asm-m68k/machdep.h b/include/asm-m68k/machdep.h
index 26d2b91209c5..5637dcef314e 100644
--- a/include/asm-m68k/machdep.h
+++ b/include/asm-m68k/machdep.h
@@ -14,7 +14,7 @@ extern void (*mach_sched_init) (irq_handler_t handler);
 /* machine dependent irq functions */
 extern void (*mach_init_IRQ) (void);
 extern void (*mach_get_model) (char *model);
-extern int (*mach_get_hardware_list) (char *buffer);
+extern void (*mach_get_hardware_list) (struct seq_file *m);
 /* machine dependent timer functions */
 extern unsigned long (*mach_gettimeoffset)(void);
 extern int (*mach_hwclk)(int, struct rtc_time*);
diff --git a/include/asm-m68k/machw.h b/include/asm-m68k/machw.h
index 35624998291c..2b4de0c2ce4a 100644
--- a/include/asm-m68k/machw.h
+++ b/include/asm-m68k/machw.h
@@ -26,28 +26,6 @@
 #include <linux/types.h>
 
 #if 0
-/* Mac SCSI Controller 5380 */
-
-#define	MAC_5380_BAS	(0x50F10000) /* This is definitely wrong!! */
-struct MAC_5380 {
-	u_char	scsi_data;
-	u_char	char_dummy1;
-	u_char	scsi_icr;
-	u_char	char_dummy2;
-	u_char	scsi_mode;
-	u_char	char_dummy3;
-	u_char	scsi_tcr;
-	u_char	char_dummy4;
-	u_char	scsi_idstat;
-	u_char	char_dummy5;
-	u_char	scsi_dmastat;
-	u_char	char_dummy6;
-	u_char	scsi_targrcv;
-	u_char	char_dummy7;
-	u_char	scsi_inircv;
-};
-#define	mac_scsi       ((*(volatile struct MAC_5380 *)MAC_5380_BAS))
-
 /*
 ** SCC Z8530
 */
diff --git a/include/asm-m68k/thread_info.h b/include/asm-m68k/thread_info.h
index abc002798a2b..af0fda46e94b 100644
--- a/include/asm-m68k/thread_info.h
+++ b/include/asm-m68k/thread_info.h
@@ -52,5 +52,6 @@ struct thread_info {
 #define TIF_DELAYED_TRACE	14	/* single step a syscall */
 #define TIF_SYSCALL_TRACE	15	/* syscall trace active */
 #define TIF_MEMDIE		16
+#define TIF_FREEZE		17	/* thread is freezing for suspend */
 
 #endif	/* _ASM_M68K_THREAD_INFO_H */
diff --git a/include/asm-mips/cevt-r4k.h b/include/asm-mips/cevt-r4k.h
deleted file mode 100644
index fa4328f9124f..000000000000
--- a/include/asm-mips/cevt-r4k.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2008 Kevin D. Kissell
- */
-
-/*
- * Definitions used for common event timer implementation
- * for MIPS 4K-type processors and their MIPS MT variants.
- * Avoids unsightly extern declarations in C files.
- */
-#ifndef __ASM_CEVT_R4K_H
-#define __ASM_CEVT_R4K_H
-
-DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
-
-void mips_event_handler(struct clock_event_device *dev);
-int c0_compare_int_usable(void);
-void mips_set_clock_mode(enum clock_event_mode, struct clock_event_device *);
-irqreturn_t c0_compare_interrupt(int, void *);
-
-extern struct irqaction c0_compare_irqaction;
-extern int cp0_timer_irq_installed;
-
-/*
- * Possibly handle a performance counter interrupt.
- * Return true if the timer interrupt should not be checked
- */
-
-static inline int handle_perf_irq(int r2)
-{
-	/*
-	 * The performance counter overflow interrupt may be shared with the
-	 * timer interrupt (cp0_perfcount_irq < 0). If it is and a
-	 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
-	 * and we can't reliably determine if a counter interrupt has also
-	 * happened (!r2) then don't check for a timer interrupt.
-	 */
-	return (cp0_perfcount_irq < 0) &&
-		perf_irq() == IRQ_HANDLED &&
-		!r2;
-}
-
-#endif /* __ASM_CEVT_R4K_H */
diff --git a/include/asm-mn10300/elf.h b/include/asm-mn10300/elf.h
index 256a70466ca4..bf09f8bb392e 100644
--- a/include/asm-mn10300/elf.h
+++ b/include/asm-mn10300/elf.h
@@ -141,7 +141,7 @@ do {						\
 #define ELF_PLATFORM  (NULL)
 
 #ifdef __KERNEL__
-#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
 #endif
 
 #endif /* _ASM_ELF_H */
diff --git a/include/asm-mn10300/uaccess.h b/include/asm-mn10300/uaccess.h
index 46b9b647f3c3..8a3a4dd55763 100644
--- a/include/asm-mn10300/uaccess.h
+++ b/include/asm-mn10300/uaccess.h
@@ -266,7 +266,7 @@ extern int __get_user_unknown(void);
 		"	.section	.fixup,\"ax\"	\n"		\
 		"4:					\n"		\
 		"	mov		%5,%0		\n"		\
-		"	jmp		2b		\n"		\
+		"	jmp		3b		\n"		\
 		"	.previous			\n"		\
 		"	.section	__ex_table,\"a\"\n"		\
 		"	.balign		4		\n"		\
diff --git a/include/asm-parisc/Kbuild b/include/asm-parisc/Kbuild
deleted file mode 100644
index f88b252e419c..000000000000
--- a/include/asm-parisc/Kbuild
+++ /dev/null
@@ -1,3 +0,0 @@
-include include/asm-generic/Kbuild.asm
-
-unifdef-y += pdc.h
diff --git a/include/asm-parisc/agp.h b/include/asm-parisc/agp.h
deleted file mode 100644
index 9651660da639..000000000000
--- a/include/asm-parisc/agp.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef _ASM_PARISC_AGP_H
-#define _ASM_PARISC_AGP_H
-
-/*
- * PARISC specific AGP definitions.
- * Copyright (c) 2006 Kyle McMartin <kyle@parisc-linux.org>
- *
- */
-
-#define map_page_into_agp(page)		/* nothing */
-#define unmap_page_from_agp(page)	/* nothing */
-#define flush_agp_cache()		mb()
-
-/* Convert a physical address to an address suitable for the GART. */
-#define phys_to_gart(x) (x)
-#define gart_to_phys(x) (x)
-
-/* GATT allocation. Returns/accepts GATT kernel virtual address. */
-#define alloc_gatt_pages(order)		\
-	((char *)__get_free_pages(GFP_KERNEL, (order)))
-#define free_gatt_pages(table, order)	\
-	free_pages((unsigned long)(table), (order))
-
-#endif /* _ASM_PARISC_AGP_H */
diff --git a/include/asm-parisc/asmregs.h b/include/asm-parisc/asmregs.h
deleted file mode 100644
index d93c646e1887..000000000000
--- a/include/asm-parisc/asmregs.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
- *
- *	This program is free software; you can redistribute it and/or modify
- *	it under the terms of the GNU General Public License as published by
- *	the Free Software Foundation; either version 2, or (at your option)
- *	any later version.
- *
- *	This program is distributed in the hope that it will be useful,
- *	but WITHOUT ANY WARRANTY; without even the implied warranty of
- *	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *	GNU General Public License for more details.
- *
- *	You should have received a copy of the GNU General Public License
- *	along with this program; if not, write to the Free Software
- *	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _PARISC_ASMREGS_H
-#define _PARISC_ASMREGS_H
-
-;! General Registers
-
-rp:	.reg	%r2
-arg3:	.reg	%r23
-arg2:	.reg	%r24
-arg1:	.reg	%r25
-arg0:	.reg	%r26
-dp:	.reg	%r27
-ret0:	.reg	%r28
-ret1:	.reg	%r29
-sl:	.reg	%r29
-sp:	.reg	%r30
-
-#if 0
-/* PA20_REVISIT */
-arg7:	.reg	r19
-arg6:	.reg	r20
-arg5:	.reg	r21
-arg4:	.reg	r22
-gp:	.reg	r27
-ap:	.reg	r29
-#endif
-
-
-r0:	.reg	%r0
-r1:	.reg	%r1
-r2:	.reg	%r2
-r3:	.reg	%r3
-r4:	.reg	%r4
-r5:	.reg	%r5
-r6:	.reg	%r6
-r7:	.reg	%r7
-r8:	.reg	%r8
-r9:	.reg	%r9
-r10:	.reg	%r10
-r11:	.reg	%r11
-r12:	.reg	%r12
-r13:	.reg	%r13
-r14:	.reg	%r14
-r15:	.reg	%r15
-r16:	.reg	%r16
-r17:	.reg	%r17
-r18:	.reg	%r18
-r19:	.reg	%r19
-r20:	.reg	%r20
-r21:	.reg	%r21
-r22:	.reg	%r22
-r23:	.reg	%r23
-r24:	.reg	%r24
-r25:	.reg	%r25
-r26:	.reg	%r26
-r27:	.reg	%r27
-r28:	.reg	%r28
-r29:	.reg	%r29
-r30:	.reg	%r30
-r31:	.reg	%r31
-
-
-;! Space Registers
-
-sr0:	.reg	%sr0
-sr1:	.reg	%sr1
-sr2:	.reg	%sr2
-sr3:	.reg	%sr3
-sr4:	.reg	%sr4
-sr5:	.reg	%sr5
-sr6:	.reg	%sr6
-sr7:	.reg	%sr7
-
-
-;! Floating Point Registers
-
-fr0:	.reg	%fr0
-fr1:	.reg	%fr1
-fr2:	.reg	%fr2
-fr3:	.reg	%fr3
-fr4:	.reg	%fr4
-fr5:	.reg	%fr5
-fr6:	.reg	%fr6
-fr7:	.reg	%fr7
-fr8:	.reg	%fr8
-fr9:	.reg	%fr9
-fr10:	.reg	%fr10
-fr11:	.reg	%fr11
-fr12:	.reg	%fr12
-fr13:	.reg	%fr13
-fr14:	.reg	%fr14
-fr15:	.reg	%fr15
-fr16:	.reg	%fr16
-fr17:	.reg	%fr17
-fr18:	.reg	%fr18
-fr19:	.reg	%fr19
-fr20:	.reg	%fr20
-fr21:	.reg	%fr21
-fr22:	.reg	%fr22
-fr23:	.reg	%fr23
-fr24:	.reg	%fr24
-fr25:	.reg	%fr25
-fr26:	.reg	%fr26
-fr27:	.reg	%fr27
-fr28:	.reg	%fr28
-fr29:	.reg	%fr29
-fr30:	.reg	%fr30
-fr31:	.reg	%fr31
-
-
-;! Control Registers
-
-rctr:	.reg	%cr0
-pidr1:	.reg	%cr8
-pidr2:	.reg	%cr9
-ccr:	.reg	%cr10
-sar:	.reg	%cr11
-pidr3:	.reg	%cr12
-pidr4:	.reg	%cr13
-iva:	.reg	%cr14
-eiem:	.reg	%cr15
-itmr:	.reg	%cr16
-pcsq:	.reg	%cr17
-pcoq:	.reg	%cr18
-iir:	.reg	%cr19
-isr:	.reg	%cr20
-ior:	.reg	%cr21
-ipsw:	.reg	%cr22
-eirr:	.reg	%cr23
-tr0:	.reg	%cr24
-tr1:	.reg	%cr25
-tr2:	.reg	%cr26
-tr3:	.reg	%cr27
-tr4:	.reg	%cr28
-tr5:	.reg	%cr29
-tr6:	.reg	%cr30
-tr7:	.reg	%cr31
-
-
-cr0:	.reg	%cr0
-cr8:	.reg	%cr8
-cr9:	.reg	%cr9
-cr10:	.reg	%cr10
-cr11:	.reg	%cr11
-cr12:	.reg	%cr12
-cr13:	.reg	%cr13
-cr14:	.reg	%cr14
-cr15:	.reg	%cr15
-cr16:	.reg	%cr16
-cr17:	.reg	%cr17
-cr18:	.reg	%cr18
-cr19:	.reg	%cr19
-cr20:	.reg	%cr20
-cr21:	.reg	%cr21
-cr22:	.reg	%cr22
-cr23:	.reg	%cr23
-cr24:	.reg	%cr24
-cr25:	.reg	%cr25
-cr26:	.reg	%cr26
-cr27:	.reg	%cr27
-cr28:	.reg	%cr28
-cr29:	.reg	%cr29
-cr30:	.reg	%cr30
-cr31:	.reg	%cr31
-
-#endif
diff --git a/include/asm-parisc/assembly.h b/include/asm-parisc/assembly.h
deleted file mode 100644
index ffb208840ecc..000000000000
--- a/include/asm-parisc/assembly.h
+++ /dev/null
@@ -1,519 +0,0 @@
-/*
- * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
- * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org>
- * Copyright (C) 1999 SuSE GmbH
- *
- *    This program is free software; you can redistribute it and/or modify
- *    it under the terms of the GNU General Public License as published by
- *    the Free Software Foundation; either version 2, or (at your option)
- *    any later version.
- *
- *    This program is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *    GNU General Public License for more details.
- *
- *    You should have received a copy of the GNU General Public License
- *    along with this program; if not, write to the Free Software
- *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _PARISC_ASSEMBLY_H
-#define _PARISC_ASSEMBLY_H
-
-#define CALLEE_FLOAT_FRAME_SIZE	80
-
-#ifdef CONFIG_64BIT
-#define LDREG	ldd
-#define STREG	std
-#define LDREGX  ldd,s
-#define LDREGM	ldd,mb
-#define STREGM	std,ma
-#define SHRREG	shrd
-#define SHLREG	shld
-#define ANDCM   andcm,*
-#define	COND(x)	* ## x
-#define RP_OFFSET	16
-#define FRAME_SIZE	128
-#define CALLEE_REG_FRAME_SIZE	144
-#define ASM_ULONG_INSN	.dword
-#else	/* CONFIG_64BIT */
-#define LDREG	ldw
-#define STREG	stw
-#define LDREGX  ldwx,s
-#define LDREGM	ldwm
-#define STREGM	stwm
-#define SHRREG	shr
-#define SHLREG	shlw
-#define ANDCM   andcm
-#define COND(x)	x
-#define RP_OFFSET	20
-#define FRAME_SIZE	64
-#define CALLEE_REG_FRAME_SIZE	128
-#define ASM_ULONG_INSN	.word
-#endif
-
-#define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
-
-#ifdef CONFIG_PA20
-#define LDCW		ldcw,co
-#define BL		b,l
-# ifdef CONFIG_64BIT
-#  define LEVEL		2.0w
-# else
-#  define LEVEL		2.0
-# endif
-#else
-#define LDCW		ldcw
-#define BL		bl
-#define LEVEL		1.1
-#endif
-
-#ifdef __ASSEMBLY__
-
-#ifdef CONFIG_64BIT
-/* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so
- * work around that for now... */
-	.level 2.0w
-#endif
-
-#include <asm/asm-offsets.h>
-#include <asm/page.h>
-
-#include <asm/asmregs.h>
-
-	sp	=	30
-	gp	=	27
-	ipsw	=	22
-
-	/*
-	 * We provide two versions of each macro to convert from physical
-	 * to virtual and vice versa. The "_r1" versions take one argument
-	 * register, but trashes r1 to do the conversion. The other
-	 * version takes two arguments: a src and destination register.
-	 * However, the source and destination registers can not be
-	 * the same register.
-	 */
-
-	.macro  tophys  grvirt, grphys
-	ldil    L%(__PAGE_OFFSET), \grphys
-	sub     \grvirt, \grphys, \grphys
-	.endm
-	
-	.macro  tovirt  grphys, grvirt
-	ldil    L%(__PAGE_OFFSET), \grvirt
-	add     \grphys, \grvirt, \grvirt
-	.endm
-
-	.macro  tophys_r1  gr
-	ldil    L%(__PAGE_OFFSET), %r1
-	sub     \gr, %r1, \gr
-	.endm
-	
-	.macro  tovirt_r1  gr
-	ldil    L%(__PAGE_OFFSET), %r1
-	add     \gr, %r1, \gr
-	.endm
-
-	.macro delay value
-	ldil	L%\value, 1
-	ldo	R%\value(1), 1
-	addib,UV,n -1,1,.
-	addib,NUV,n -1,1,.+8
-	nop
-	.endm
-
-	.macro	debug value
-	.endm
-
-
-	/* Shift Left - note the r and t can NOT be the same! */
-	.macro shl r, sa, t
-	dep,z	\r, 31-\sa, 32-\sa, \t
-	.endm
-
-	/* The PA 2.0 shift left */
-	.macro shlw r, sa, t
-	depw,z	\r, 31-\sa, 32-\sa, \t
-	.endm
-
-	/* And the PA 2.0W shift left */
-	.macro shld r, sa, t
-	depd,z	\r, 63-\sa, 64-\sa, \t
-	.endm
-
-	/* Shift Right - note the r and t can NOT be the same! */
-	.macro shr r, sa, t
-	extru \r, 31-\sa, 32-\sa, \t
-	.endm
-
-	/* pa20w version of shift right */
-	.macro shrd r, sa, t
-	extrd,u \r, 63-\sa, 64-\sa, \t
-	.endm
-
-	/* load 32-bit 'value' into 'reg' compensating for the ldil
-	 * sign-extension when running in wide mode.
-	 * WARNING!! neither 'value' nor 'reg' can be expressions
-	 * containing '.'!!!! */
-	.macro	load32 value, reg
-	ldil	L%\value, \reg
-	ldo	R%\value(\reg), \reg
-	.endm
-
-	.macro loadgp
-#ifdef CONFIG_64BIT
-	ldil		L%__gp, %r27
-	ldo		R%__gp(%r27), %r27
-#else
-	ldil		L%$global$, %r27
-	ldo		R%$global$(%r27), %r27
-#endif
-	.endm
-
-#define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where
-#define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r
-#define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where
-#define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
-
-	.macro	save_general	regs
-	STREG %r1, PT_GR1 (\regs)
-	STREG %r2, PT_GR2 (\regs)
-	STREG %r3, PT_GR3 (\regs)
-	STREG %r4, PT_GR4 (\regs)
-	STREG %r5, PT_GR5 (\regs)
-	STREG %r6, PT_GR6 (\regs)
-	STREG %r7, PT_GR7 (\regs)
-	STREG %r8, PT_GR8 (\regs)
-	STREG %r9, PT_GR9 (\regs)
-	STREG %r10, PT_GR10(\regs)
-	STREG %r11, PT_GR11(\regs)
-	STREG %r12, PT_GR12(\regs)
-	STREG %r13, PT_GR13(\regs)
-	STREG %r14, PT_GR14(\regs)
-	STREG %r15, PT_GR15(\regs)
-	STREG %r16, PT_GR16(\regs)
-	STREG %r17, PT_GR17(\regs)
-	STREG %r18, PT_GR18(\regs)
-	STREG %r19, PT_GR19(\regs)
-	STREG %r20, PT_GR20(\regs)
-	STREG %r21, PT_GR21(\regs)
-	STREG %r22, PT_GR22(\regs)
-	STREG %r23, PT_GR23(\regs)
-	STREG %r24, PT_GR24(\regs)
-	STREG %r25, PT_GR25(\regs)
-	/* r26 is saved in get_stack and used to preserve a value across virt_map */
-	STREG %r27, PT_GR27(\regs)
-	STREG %r28, PT_GR28(\regs)
-	/* r29 is saved in get_stack and used to point to saved registers */
-	/* r30 stack pointer saved in get_stack */
-	STREG %r31, PT_GR31(\regs)
-	.endm
-
-	.macro	rest_general	regs
-	/* r1 used as a temp in rest_stack and is restored there */
-	LDREG PT_GR2 (\regs), %r2
-	LDREG PT_GR3 (\regs), %r3
-	LDREG PT_GR4 (\regs), %r4
-	LDREG PT_GR5 (\regs), %r5
-	LDREG PT_GR6 (\regs), %r6
-	LDREG PT_GR7 (\regs), %r7
-	LDREG PT_GR8 (\regs), %r8
-	LDREG PT_GR9 (\regs), %r9
-	LDREG PT_GR10(\regs), %r10
-	LDREG PT_GR11(\regs), %r11
-	LDREG PT_GR12(\regs), %r12
-	LDREG PT_GR13(\regs), %r13
-	LDREG PT_GR14(\regs), %r14
-	LDREG PT_GR15(\regs), %r15
-	LDREG PT_GR16(\regs), %r16
-	LDREG PT_GR17(\regs), %r17
-	LDREG PT_GR18(\regs), %r18
-	LDREG PT_GR19(\regs), %r19
-	LDREG PT_GR20(\regs), %r20
-	LDREG PT_GR21(\regs), %r21
-	LDREG PT_GR22(\regs), %r22
-	LDREG PT_GR23(\regs), %r23
-	LDREG PT_GR24(\regs), %r24
-	LDREG PT_GR25(\regs), %r25
-	LDREG PT_GR26(\regs), %r26
-	LDREG PT_GR27(\regs), %r27
-	LDREG PT_GR28(\regs), %r28
-	/* r29 points to register save area, and is restored in rest_stack */
-	/* r30 stack pointer restored in rest_stack */
-	LDREG PT_GR31(\regs), %r31
-	.endm
-
-	.macro	save_fp 	regs
-	fstd,ma  %fr0, 8(\regs)
-	fstd,ma	 %fr1, 8(\regs)
-	fstd,ma	 %fr2, 8(\regs)
-	fstd,ma	 %fr3, 8(\regs)
-	fstd,ma	 %fr4, 8(\regs)
-	fstd,ma	 %fr5, 8(\regs)
-	fstd,ma	 %fr6, 8(\regs)
-	fstd,ma	 %fr7, 8(\regs)
-	fstd,ma	 %fr8, 8(\regs)
-	fstd,ma	 %fr9, 8(\regs)
-	fstd,ma	%fr10, 8(\regs)
-	fstd,ma	%fr11, 8(\regs)
-	fstd,ma	%fr12, 8(\regs)
-	fstd,ma	%fr13, 8(\regs)
-	fstd,ma	%fr14, 8(\regs)
-	fstd,ma	%fr15, 8(\regs)
-	fstd,ma	%fr16, 8(\regs)
-	fstd,ma	%fr17, 8(\regs)
-	fstd,ma	%fr18, 8(\regs)
-	fstd,ma	%fr19, 8(\regs)
-	fstd,ma	%fr20, 8(\regs)
-	fstd,ma	%fr21, 8(\regs)
-	fstd,ma	%fr22, 8(\regs)
-	fstd,ma	%fr23, 8(\regs)
-	fstd,ma	%fr24, 8(\regs)
-	fstd,ma	%fr25, 8(\regs)
-	fstd,ma	%fr26, 8(\regs)
-	fstd,ma	%fr27, 8(\regs)
-	fstd,ma	%fr28, 8(\regs)
-	fstd,ma	%fr29, 8(\regs)
-	fstd,ma	%fr30, 8(\regs)
-	fstd	%fr31, 0(\regs)
-	.endm
-
-	.macro	rest_fp 	regs
-	fldd	0(\regs),	 %fr31
-	fldd,mb	-8(\regs),       %fr30
-	fldd,mb	-8(\regs),       %fr29
-	fldd,mb	-8(\regs),       %fr28
-	fldd,mb	-8(\regs),       %fr27
-	fldd,mb	-8(\regs),       %fr26
-	fldd,mb	-8(\regs),       %fr25
-	fldd,mb	-8(\regs),       %fr24
-	fldd,mb	-8(\regs),       %fr23
-	fldd,mb	-8(\regs),       %fr22
-	fldd,mb	-8(\regs),       %fr21
-	fldd,mb	-8(\regs),       %fr20
-	fldd,mb	-8(\regs),       %fr19
-	fldd,mb	-8(\regs),       %fr18
-	fldd,mb	-8(\regs),       %fr17
-	fldd,mb	-8(\regs),       %fr16
-	fldd,mb	-8(\regs),       %fr15
-	fldd,mb	-8(\regs),       %fr14
-	fldd,mb	-8(\regs),       %fr13
-	fldd,mb	-8(\regs),       %fr12
-	fldd,mb	-8(\regs),       %fr11
-	fldd,mb	-8(\regs),       %fr10
-	fldd,mb	-8(\regs),       %fr9
-	fldd,mb	-8(\regs),       %fr8
-	fldd,mb	-8(\regs),       %fr7
-	fldd,mb	-8(\regs),       %fr6
-	fldd,mb	-8(\regs),       %fr5
-	fldd,mb	-8(\regs),       %fr4
-	fldd,mb	-8(\regs),       %fr3
-	fldd,mb	-8(\regs),       %fr2
-	fldd,mb	-8(\regs),       %fr1
-	fldd,mb	-8(\regs),       %fr0
-	.endm
-
-	.macro	callee_save_float
-	fstd,ma	 %fr12,	8(%r30)
-	fstd,ma	 %fr13,	8(%r30)
-	fstd,ma	 %fr14,	8(%r30)
-	fstd,ma	 %fr15,	8(%r30)
-	fstd,ma	 %fr16,	8(%r30)
-	fstd,ma	 %fr17,	8(%r30)
-	fstd,ma	 %fr18,	8(%r30)
-	fstd,ma	 %fr19,	8(%r30)
-	fstd,ma	 %fr20,	8(%r30)
-	fstd,ma	 %fr21,	8(%r30)
-	.endm
-
-	.macro	callee_rest_float
-	fldd,mb	-8(%r30),   %fr21
-	fldd,mb	-8(%r30),   %fr20
-	fldd,mb	-8(%r30),   %fr19
-	fldd,mb	-8(%r30),   %fr18
-	fldd,mb	-8(%r30),   %fr17
-	fldd,mb	-8(%r30),   %fr16
-	fldd,mb	-8(%r30),   %fr15
-	fldd,mb	-8(%r30),   %fr14
-	fldd,mb	-8(%r30),   %fr13
-	fldd,mb	-8(%r30),   %fr12
-	.endm
-
-#ifdef CONFIG_64BIT
-	.macro	callee_save
-	std,ma	  %r3,	 CALLEE_REG_FRAME_SIZE(%r30)
-	mfctl	  %cr27, %r3
-	std	  %r4,	-136(%r30)
-	std	  %r5,	-128(%r30)
-	std	  %r6,	-120(%r30)
-	std	  %r7,	-112(%r30)
-	std	  %r8,	-104(%r30)
-	std	  %r9,	 -96(%r30)
-	std	 %r10,	 -88(%r30)
-	std	 %r11,	 -80(%r30)
-	std	 %r12,	 -72(%r30)
-	std	 %r13,	 -64(%r30)
-	std	 %r14,	 -56(%r30)
-	std	 %r15,	 -48(%r30)
-	std	 %r16,	 -40(%r30)
-	std	 %r17,	 -32(%r30)
-	std	 %r18,	 -24(%r30)
-	std	  %r3,	 -16(%r30)
-	.endm
-
-	.macro	callee_rest
-	ldd	 -16(%r30),    %r3
-	ldd	 -24(%r30),   %r18
-	ldd	 -32(%r30),   %r17
-	ldd	 -40(%r30),   %r16
-	ldd	 -48(%r30),   %r15
-	ldd	 -56(%r30),   %r14
-	ldd	 -64(%r30),   %r13
-	ldd	 -72(%r30),   %r12
-	ldd	 -80(%r30),   %r11
-	ldd	 -88(%r30),   %r10
-	ldd	 -96(%r30),    %r9
-	ldd	-104(%r30),    %r8
-	ldd	-112(%r30),    %r7
-	ldd	-120(%r30),    %r6
-	ldd	-128(%r30),    %r5
-	ldd	-136(%r30),    %r4
-	mtctl	%r3, %cr27
-	ldd,mb	-CALLEE_REG_FRAME_SIZE(%r30),    %r3
-	.endm
-
-#else /* ! CONFIG_64BIT */
-
-	.macro	callee_save
-	stw,ma	 %r3,	CALLEE_REG_FRAME_SIZE(%r30)
-	mfctl	 %cr27, %r3
-	stw	 %r4,	-124(%r30)
-	stw	 %r5,	-120(%r30)
-	stw	 %r6,	-116(%r30)
-	stw	 %r7,	-112(%r30)
-	stw	 %r8,	-108(%r30)
-	stw	 %r9,	-104(%r30)
-	stw	 %r10,	-100(%r30)
-	stw	 %r11,	 -96(%r30)
-	stw	 %r12,	 -92(%r30)
-	stw	 %r13,	 -88(%r30)
-	stw	 %r14,	 -84(%r30)
-	stw	 %r15,	 -80(%r30)
-	stw	 %r16,	 -76(%r30)
-	stw	 %r17,	 -72(%r30)
-	stw	 %r18,	 -68(%r30)
-	stw	  %r3,	 -64(%r30)
-	.endm
-
-	.macro	callee_rest
-	ldw	 -64(%r30),    %r3
-	ldw	 -68(%r30),   %r18
-	ldw	 -72(%r30),   %r17
-	ldw	 -76(%r30),   %r16
-	ldw	 -80(%r30),   %r15
-	ldw	 -84(%r30),   %r14
-	ldw	 -88(%r30),   %r13
-	ldw	 -92(%r30),   %r12
-	ldw	 -96(%r30),   %r11
-	ldw	-100(%r30),   %r10
-	ldw	-104(%r30),   %r9
-	ldw	-108(%r30),   %r8
-	ldw	-112(%r30),   %r7
-	ldw	-116(%r30),   %r6
-	ldw	-120(%r30),   %r5
-	ldw	-124(%r30),   %r4
-	mtctl	%r3, %cr27
-	ldw,mb	-CALLEE_REG_FRAME_SIZE(%r30),   %r3
-	.endm
-#endif /* ! CONFIG_64BIT */
-
-	.macro	save_specials	regs
-
-	SAVE_SP  (%sr0, PT_SR0 (\regs))
-	SAVE_SP  (%sr1, PT_SR1 (\regs))
-	SAVE_SP  (%sr2, PT_SR2 (\regs))
-	SAVE_SP  (%sr3, PT_SR3 (\regs))
-	SAVE_SP  (%sr4, PT_SR4 (\regs))
-	SAVE_SP  (%sr5, PT_SR5 (\regs))
-	SAVE_SP  (%sr6, PT_SR6 (\regs))
-	SAVE_SP  (%sr7, PT_SR7 (\regs))
-
-	SAVE_CR  (%cr17, PT_IASQ0(\regs))
-	mtctl	 %r0,	%cr17
-	SAVE_CR  (%cr17, PT_IASQ1(\regs))
-
-	SAVE_CR  (%cr18, PT_IAOQ0(\regs))
-	mtctl	 %r0,	%cr18
-	SAVE_CR  (%cr18, PT_IAOQ1(\regs))
-
-#ifdef CONFIG_64BIT
-	/* cr11 (sar) is a funny one.  5 bits on PA1.1 and 6 bit on PA2.0
-	 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only
-	 * reads 5 bits.  Use mfctl,w to read all six bits.  Otherwise
-	 * we lose the 6th bit on a save/restore over interrupt.
-	 */
-	mfctl,w  %cr11, %r1
-	STREG    %r1, PT_SAR (\regs)
-#else
-	SAVE_CR  (%cr11, PT_SAR  (\regs))
-#endif
-	SAVE_CR  (%cr19, PT_IIR  (\regs))
-
-	/*
-	 * Code immediately following this macro (in intr_save) relies
-	 * on r8 containing ipsw.
-	 */
-	mfctl    %cr22, %r8
-	STREG    %r8,   PT_PSW(\regs)
-	.endm
-
-	.macro	rest_specials	regs
-
-	REST_SP  (%sr0, PT_SR0 (\regs))
-	REST_SP  (%sr1, PT_SR1 (\regs))
-	REST_SP  (%sr2, PT_SR2 (\regs))
-	REST_SP  (%sr3, PT_SR3 (\regs))
-	REST_SP  (%sr4, PT_SR4 (\regs))
-	REST_SP  (%sr5, PT_SR5 (\regs))
-	REST_SP  (%sr6, PT_SR6 (\regs))
-	REST_SP  (%sr7, PT_SR7 (\regs))
-
-	REST_CR	(%cr17, PT_IASQ0(\regs))
-	REST_CR	(%cr17, PT_IASQ1(\regs))
-
-	REST_CR	(%cr18, PT_IAOQ0(\regs))
-	REST_CR	(%cr18, PT_IAOQ1(\regs))
-
-	REST_CR (%cr11, PT_SAR	(\regs))
-
-	REST_CR	(%cr22, PT_PSW	(\regs))
-	.endm
-
-
-	/* First step to create a "relied upon translation"
-	 * See PA 2.0 Arch. page F-4 and F-5.
-	 *
-	 * The ssm was originally necessary due to a "PCxT bug".
-	 * But someone decided it needed to be added to the architecture
-	 * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
-	 * It's been carried forward into PA 2.0 Arch as well. :^(
-	 *
-	 * "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
-	 * rsm/ssm prevents the ifetch unit from speculatively fetching
-	 * instructions past this line in the code stream.
-	 * PA 2.0 processor will single step all insn in the same QUAD (4 insn).
-	 */
-	.macro	pcxt_ssm_bug
-	rsm	PSW_SM_I,%r0
-	nop	/* 1 */
-	nop	/* 2 */
-	nop	/* 3 */
-	nop	/* 4 */
-	nop	/* 5 */
-	nop	/* 6 */
-	nop	/* 7 */
-	.endm
-
-#endif /* __ASSEMBLY__ */
-#endif
diff --git a/include/asm-parisc/atomic.h b/include/asm-parisc/atomic.h
deleted file mode 100644
index 57fcc4a5ebb4..000000000000
--- a/include/asm-parisc/atomic.h
+++ /dev/null
@@ -1,348 +0,0 @@
-/* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
- * Copyright (C) 2006 Kyle McMartin <kyle@parisc-linux.org>
- */
-
-#ifndef _ASM_PARISC_ATOMIC_H_
-#define _ASM_PARISC_ATOMIC_H_
-
-#include <linux/types.h>
-#include <asm/system.h>
-
-/*
- * Atomic operations that C can't guarantee us.  Useful for
- * resource counting etc..
- *
- * And probably incredibly slow on parisc.  OTOH, we don't
- * have to write any serious assembly.   prumpf
- */
-
-#ifdef CONFIG_SMP
-#include <asm/spinlock.h>
-#include <asm/cache.h>		/* we use L1_CACHE_BYTES */
-
-/* Use an array of spinlocks for our atomic_ts.
- * Hash function to index into a different SPINLOCK.
- * Since "a" is usually an address, use one spinlock per cacheline.
- */
-#  define ATOMIC_HASH_SIZE 4
-#  define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
-
-extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;
-
-/* Can't use raw_spin_lock_irq because of #include problems, so
- * this is the substitute */
-#define _atomic_spin_lock_irqsave(l,f) do {	\
-	raw_spinlock_t *s = ATOMIC_HASH(l);		\
-	local_irq_save(f);			\
-	__raw_spin_lock(s);			\
-} while(0)
-
-#define _atomic_spin_unlock_irqrestore(l,f) do {	\
-	raw_spinlock_t *s = ATOMIC_HASH(l);			\
-	__raw_spin_unlock(s);				\
-	local_irq_restore(f);				\
-} while(0)
-
-
-#else
-#  define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0)
-#  define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0)
-#endif
-
-/* This should get optimized out since it's never called.
-** Or get a link error if xchg is used "wrong".
-*/
-extern void __xchg_called_with_bad_pointer(void);
-
-
-/* __xchg32/64 defined in arch/parisc/lib/bitops.c */
-extern unsigned long __xchg8(char, char *);
-extern unsigned long __xchg32(int, int *);
-#ifdef CONFIG_64BIT
-extern unsigned long __xchg64(unsigned long, unsigned long *);
-#endif
-
-/* optimizer better get rid of switch since size is a constant */
-static __inline__ unsigned long
-__xchg(unsigned long x, __volatile__ void * ptr, int size)
-{
-	switch(size) {
-#ifdef CONFIG_64BIT
-	case 8: return __xchg64(x,(unsigned long *) ptr);
-#endif
-	case 4: return __xchg32((int) x, (int *) ptr);
-	case 1: return __xchg8((char) x, (char *) ptr);
-	}
-	__xchg_called_with_bad_pointer();
-	return x;
-}
-
-
-/*
-** REVISIT - Abandoned use of LDCW in xchg() for now:
-** o need to test sizeof(*ptr) to avoid clearing adjacent bytes
-** o and while we are at it, could CONFIG_64BIT code use LDCD too?
-**
-**	if (__builtin_constant_p(x) && (x == NULL))
-**		if (((unsigned long)p & 0xf) == 0)
-**			return __ldcw(p);
-*/
-#define xchg(ptr,x) \
-	((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-
-
-#define __HAVE_ARCH_CMPXCHG	1
-
-/* bug catcher for when unsupported size is used - won't link */
-extern void __cmpxchg_called_with_bad_pointer(void);
-
-/* __cmpxchg_u32/u64 defined in arch/parisc/lib/bitops.c */
-extern unsigned long __cmpxchg_u32(volatile unsigned int *m, unsigned int old, unsigned int new_);
-extern unsigned long __cmpxchg_u64(volatile unsigned long *ptr, unsigned long old, unsigned long new_);
-
-/* don't worry...optimizer will get rid of most of this */
-static __inline__ unsigned long
-__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
-{
-	switch(size) {
-#ifdef CONFIG_64BIT
-	case 8: return __cmpxchg_u64((unsigned long *)ptr, old, new_);
-#endif
-	case 4: return __cmpxchg_u32((unsigned int *)ptr, (unsigned int) old, (unsigned int) new_);
-	}
-	__cmpxchg_called_with_bad_pointer();
-	return old;
-}
-
-#define cmpxchg(ptr,o,n)						 \
-  ({									 \
-     __typeof__(*(ptr)) _o_ = (o);					 \
-     __typeof__(*(ptr)) _n_ = (n);					 \
-     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,		 \
-				    (unsigned long)_n_, sizeof(*(ptr))); \
-  })
-
-#include <asm-generic/cmpxchg-local.h>
-
-static inline unsigned long __cmpxchg_local(volatile void *ptr,
-				      unsigned long old,
-				      unsigned long new_, int size)
-{
-	switch (size) {
-#ifdef CONFIG_64BIT
-	case 8:	return __cmpxchg_u64((unsigned long *)ptr, old, new_);
-#endif
-	case 4:	return __cmpxchg_u32(ptr, old, new_);
-	default:
-		return __cmpxchg_local_generic(ptr, old, new_, size);
-	}
-}
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n)				  	\
-	((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o),	\
-			(unsigned long)(n), sizeof(*(ptr))))
-#ifdef CONFIG_64BIT
-#define cmpxchg64_local(ptr, o, n)					\
-  ({									\
-	BUILD_BUG_ON(sizeof(*(ptr)) != 8);				\
-	cmpxchg_local((ptr), (o), (n));					\
-  })
-#else
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-#endif
-
-/* Note that we need not lock read accesses - aligned word writes/reads
- * are atomic, so a reader never sees unconsistent values.
- *
- * Cache-line alignment would conflict with, for example, linux/module.h
- */
-
-typedef struct { volatile int counter; } atomic_t;
-
-/* It's possible to reduce all atomic operations to either
- * __atomic_add_return, atomic_set and atomic_read (the latter
- * is there only for consistency).
- */
-
-static __inline__ int __atomic_add_return(int i, atomic_t *v)
-{
-	int ret;
-	unsigned long flags;
-	_atomic_spin_lock_irqsave(v, flags);
-
-	ret = (v->counter += i);
-
-	_atomic_spin_unlock_irqrestore(v, flags);
-	return ret;
-}
-
-static __inline__ void atomic_set(atomic_t *v, int i) 
-{
-	unsigned long flags;
-	_atomic_spin_lock_irqsave(v, flags);
-
-	v->counter = i;
-
-	_atomic_spin_unlock_irqrestore(v, flags);
-}
-
-static __inline__ int atomic_read(const atomic_t *v)
-{
-	return v->counter;
-}
-
-/* exported interface */
-#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-
-/**
- * atomic_add_unless - add unless the number is a given value
- * @v: pointer of type atomic_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as it was not @u.
- * Returns non-zero if @v was not @u, and zero otherwise.
- */
-static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
-{
-	int c, old;
-	c = atomic_read(v);
-	for (;;) {
-		if (unlikely(c == (u)))
-			break;
-		old = atomic_cmpxchg((v), c, c + (a));
-		if (likely(old == c))
-			break;
-		c = old;
-	}
-	return c != (u);
-}
-
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-
-#define atomic_add(i,v)	((void)(__atomic_add_return( ((int)i),(v))))
-#define atomic_sub(i,v)	((void)(__atomic_add_return(-((int)i),(v))))
-#define atomic_inc(v)	((void)(__atomic_add_return(   1,(v))))
-#define atomic_dec(v)	((void)(__atomic_add_return(  -1,(v))))
-
-#define atomic_add_return(i,v)	(__atomic_add_return( ((int)i),(v)))
-#define atomic_sub_return(i,v)	(__atomic_add_return(-((int)i),(v)))
-#define atomic_inc_return(v)	(__atomic_add_return(   1,(v)))
-#define atomic_dec_return(v)	(__atomic_add_return(  -1,(v)))
-
-#define atomic_add_negative(a, v)	(atomic_add_return((a), (v)) < 0)
-
-/*
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-
-#define atomic_dec_and_test(v)	(atomic_dec_return(v) == 0)
-
-#define atomic_sub_and_test(i,v)	(atomic_sub_return((i),(v)) == 0)
-
-#define ATOMIC_INIT(i)	((atomic_t) { (i) })
-
-#define smp_mb__before_atomic_dec()	smp_mb()
-#define smp_mb__after_atomic_dec()	smp_mb()
-#define smp_mb__before_atomic_inc()	smp_mb()
-#define smp_mb__after_atomic_inc()	smp_mb()
-
-#ifdef CONFIG_64BIT
-
-typedef struct { volatile s64 counter; } atomic64_t;
-
-#define ATOMIC64_INIT(i) ((atomic64_t) { (i) })
-
-static __inline__ int
-__atomic64_add_return(s64 i, atomic64_t *v)
-{
-	int ret;
-	unsigned long flags;
-	_atomic_spin_lock_irqsave(v, flags);
-
-	ret = (v->counter += i);
-
-	_atomic_spin_unlock_irqrestore(v, flags);
-	return ret;
-}
-
-static __inline__ void
-atomic64_set(atomic64_t *v, s64 i)
-{
-	unsigned long flags;
-	_atomic_spin_lock_irqsave(v, flags);
-
-	v->counter = i;
-
-	_atomic_spin_unlock_irqrestore(v, flags);
-}
-
-static __inline__ s64
-atomic64_read(const atomic64_t *v)
-{
-	return v->counter;
-}
-
-#define atomic64_add(i,v)	((void)(__atomic64_add_return( ((s64)i),(v))))
-#define atomic64_sub(i,v)	((void)(__atomic64_add_return(-((s64)i),(v))))
-#define atomic64_inc(v)		((void)(__atomic64_add_return(   1,(v))))
-#define atomic64_dec(v)		((void)(__atomic64_add_return(  -1,(v))))
-
-#define atomic64_add_return(i,v)	(__atomic64_add_return( ((s64)i),(v)))
-#define atomic64_sub_return(i,v)	(__atomic64_add_return(-((s64)i),(v)))
-#define atomic64_inc_return(v)		(__atomic64_add_return(   1,(v)))
-#define atomic64_dec_return(v)		(__atomic64_add_return(  -1,(v)))
-
-#define atomic64_add_negative(a, v)	(atomic64_add_return((a), (v)) < 0)
-
-#define atomic64_inc_and_test(v) 	(atomic64_inc_return(v) == 0)
-#define atomic64_dec_and_test(v)	(atomic64_dec_return(v) == 0)
-#define atomic64_sub_and_test(i,v)	(atomic64_sub_return((i),(v)) == 0)
-
-/* exported interface */
-#define atomic64_cmpxchg(v, o, n) \
-	((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
-#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
-
-/**
- * atomic64_add_unless - add unless the number is a given value
- * @v: pointer of type atomic64_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as it was not @u.
- * Returns non-zero if @v was not @u, and zero otherwise.
- */
-static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
-{
-	long c, old;
-	c = atomic64_read(v);
-	for (;;) {
-		if (unlikely(c == (u)))
-			break;
-		old = atomic64_cmpxchg((v), c, c + (a));
-		if (likely(old == c))
-			break;
-		c = old;
-	}
-	return c != (u);
-}
-
-#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
-
-#endif /* CONFIG_64BIT */
-
-#include <asm-generic/atomic.h>
-
-#endif /* _ASM_PARISC_ATOMIC_H_ */
diff --git a/include/asm-parisc/auxvec.h b/include/asm-parisc/auxvec.h
deleted file mode 100644
index 9c3ac4b89dc9..000000000000
--- a/include/asm-parisc/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __ASMPARISC_AUXVEC_H
-#define __ASMPARISC_AUXVEC_H
-
-#endif
diff --git a/include/asm-parisc/bitops.h b/include/asm-parisc/bitops.h
deleted file mode 100644
index 7a6ea10bd231..000000000000
--- a/include/asm-parisc/bitops.h
+++ /dev/null
@@ -1,239 +0,0 @@
-#ifndef _PARISC_BITOPS_H
-#define _PARISC_BITOPS_H
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <linux/compiler.h>
-#include <asm/types.h>		/* for BITS_PER_LONG/SHIFT_PER_LONG */
-#include <asm/byteorder.h>
-#include <asm/atomic.h>
-
-/*
- * HP-PARISC specific bit operations
- * for a detailed description of the functions please refer
- * to include/asm-i386/bitops.h or kerneldoc
- */
-
-#define CHOP_SHIFTCOUNT(x) (((unsigned long) (x)) & (BITS_PER_LONG - 1))
-
-
-#define smp_mb__before_clear_bit()      smp_mb()
-#define smp_mb__after_clear_bit()       smp_mb()
-
-/* See http://marc.theaimsgroup.com/?t=108826637900003 for discussion
- * on use of volatile and __*_bit() (set/clear/change):
- *	*_bit() want use of volatile.
- *	__*_bit() are "relaxed" and don't use spinlock or volatile.
- */
-
-static __inline__ void set_bit(int nr, volatile unsigned long * addr)
-{
-	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
-	unsigned long flags;
-
-	addr += (nr >> SHIFT_PER_LONG);
-	_atomic_spin_lock_irqsave(addr, flags);
-	*addr |= mask;
-	_atomic_spin_unlock_irqrestore(addr, flags);
-}
-
-static __inline__ void clear_bit(int nr, volatile unsigned long * addr)
-{
-	unsigned long mask = ~(1UL << CHOP_SHIFTCOUNT(nr));
-	unsigned long flags;
-
-	addr += (nr >> SHIFT_PER_LONG);
-	_atomic_spin_lock_irqsave(addr, flags);
-	*addr &= mask;
-	_atomic_spin_unlock_irqrestore(addr, flags);
-}
-
-static __inline__ void change_bit(int nr, volatile unsigned long * addr)
-{
-	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
-	unsigned long flags;
-
-	addr += (nr >> SHIFT_PER_LONG);
-	_atomic_spin_lock_irqsave(addr, flags);
-	*addr ^= mask;
-	_atomic_spin_unlock_irqrestore(addr, flags);
-}
-
-static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
-{
-	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
-	unsigned long old;
-	unsigned long flags;
-	int set;
-
-	addr += (nr >> SHIFT_PER_LONG);
-	_atomic_spin_lock_irqsave(addr, flags);
-	old = *addr;
-	set = (old & mask) ? 1 : 0;
-	if (!set)
-		*addr = old | mask;
-	_atomic_spin_unlock_irqrestore(addr, flags);
-
-	return set;
-}
-
-static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
-{
-	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
-	unsigned long old;
-	unsigned long flags;
-	int set;
-
-	addr += (nr >> SHIFT_PER_LONG);
-	_atomic_spin_lock_irqsave(addr, flags);
-	old = *addr;
-	set = (old & mask) ? 1 : 0;
-	if (set)
-		*addr = old & ~mask;
-	_atomic_spin_unlock_irqrestore(addr, flags);
-
-	return set;
-}
-
-static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr)
-{
-	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
-	unsigned long oldbit;
-	unsigned long flags;
-
-	addr += (nr >> SHIFT_PER_LONG);
-	_atomic_spin_lock_irqsave(addr, flags);
-	oldbit = *addr;
-	*addr = oldbit ^ mask;
-	_atomic_spin_unlock_irqrestore(addr, flags);
-
-	return (oldbit & mask) ? 1 : 0;
-}
-
-#include <asm-generic/bitops/non-atomic.h>
-
-#ifdef __KERNEL__
-
-/**
- * __ffs - find first bit in word. returns 0 to "BITS_PER_LONG-1".
- * @word: The word to search
- *
- * __ffs() return is undefined if no bit is set.
- *
- * 32-bit fast __ffs by LaMont Jones "lamont At hp com".
- * 64-bit enhancement by Grant Grundler "grundler At parisc-linux org".
- * (with help from willy/jejb to get the semantics right)
- *
- * This algorithm avoids branches by making use of nullification.
- * One side effect of "extr" instructions is it sets PSW[N] bit.
- * How PSW[N] (nullify next insn) gets set is determined by the 
- * "condition" field (eg "<>" or "TR" below) in the extr* insn.
- * Only the 1st and one of either the 2cd or 3rd insn will get executed.
- * Each set of 3 insn will get executed in 2 cycles on PA8x00 vs 16 or so
- * cycles for each mispredicted branch.
- */
-
-static __inline__ unsigned long __ffs(unsigned long x)
-{
-	unsigned long ret;
-
-	__asm__(
-#ifdef CONFIG_64BIT
-		" ldi       63,%1\n"
-		" extrd,u,*<>  %0,63,32,%%r0\n"
-		" extrd,u,*TR  %0,31,32,%0\n"	/* move top 32-bits down */
-		" addi    -32,%1,%1\n"
-#else
-		" ldi       31,%1\n"
-#endif
-		" extru,<>  %0,31,16,%%r0\n"
-		" extru,TR  %0,15,16,%0\n"	/* xxxx0000 -> 0000xxxx */
-		" addi    -16,%1,%1\n"
-		" extru,<>  %0,31,8,%%r0\n"
-		" extru,TR  %0,23,8,%0\n"	/* 0000xx00 -> 000000xx */
-		" addi    -8,%1,%1\n"
-		" extru,<>  %0,31,4,%%r0\n"
-		" extru,TR  %0,27,4,%0\n"	/* 000000x0 -> 0000000x */
-		" addi    -4,%1,%1\n"
-		" extru,<>  %0,31,2,%%r0\n"
-		" extru,TR  %0,29,2,%0\n"	/* 0000000y, 1100b -> 0011b */
-		" addi    -2,%1,%1\n"
-		" extru,=  %0,31,1,%%r0\n"	/* check last bit */
-		" addi    -1,%1,%1\n"
-			: "+r" (x), "=r" (ret) );
-	return ret;
-}
-
-#include <asm-generic/bitops/ffz.h>
-
-/*
- * ffs: find first bit set. returns 1 to BITS_PER_LONG or 0 (if none set)
- * This is defined the same way as the libc and compiler builtin
- * ffs routines, therefore differs in spirit from the above ffz (man ffs).
- */
-static __inline__ int ffs(int x)
-{
-	return x ? (__ffs((unsigned long)x) + 1) : 0;
-}
-
-/*
- * fls: find last (most significant) bit set.
- * fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
- */
-
-static __inline__ int fls(int x)
-{
-	int ret;
-	if (!x)
-		return 0;
-
-	__asm__(
-	"	ldi		1,%1\n"
-	"	extru,<>	%0,15,16,%%r0\n"
-	"	zdep,TR		%0,15,16,%0\n"		/* xxxx0000 */
-	"	addi		16,%1,%1\n"
-	"	extru,<>	%0,7,8,%%r0\n"
-	"	zdep,TR		%0,23,24,%0\n"		/* xx000000 */
-	"	addi		8,%1,%1\n"
-	"	extru,<>	%0,3,4,%%r0\n"
-	"	zdep,TR		%0,27,28,%0\n"		/* x0000000 */
-	"	addi		4,%1,%1\n"
-	"	extru,<>	%0,1,2,%%r0\n"
-	"	zdep,TR		%0,29,30,%0\n"		/* y0000000 (y&3 = 0) */
-	"	addi		2,%1,%1\n"
-	"	extru,=		%0,0,1,%%r0\n"
-	"	addi		1,%1,%1\n"		/* if y & 8, add 1 */
-		: "+r" (x), "=r" (ret) );
-
-	return ret;
-}
-
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/lock.h>
-#include <asm-generic/bitops/sched.h>
-
-#endif /* __KERNEL__ */
-
-#include <asm-generic/bitops/find.h>
-
-#ifdef __KERNEL__
-
-#include <asm-generic/bitops/ext2-non-atomic.h>
-
-/* '3' is bits per byte */
-#define LE_BYTE_ADDR ((sizeof(unsigned long) - 1) << 3)
-
-#define ext2_set_bit_atomic(l,nr,addr) \
-		test_and_set_bit((nr)   ^ LE_BYTE_ADDR, (unsigned long *)addr)
-#define ext2_clear_bit_atomic(l,nr,addr) \
-		test_and_clear_bit( (nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)
-
-#endif	/* __KERNEL__ */
-
-#include <asm-generic/bitops/minix-le.h>
-
-#endif /* _PARISC_BITOPS_H */
diff --git a/include/asm-parisc/bug.h b/include/asm-parisc/bug.h
deleted file mode 100644
index 8cfc553fc837..000000000000
--- a/include/asm-parisc/bug.h
+++ /dev/null
@@ -1,92 +0,0 @@
-#ifndef _PARISC_BUG_H
-#define _PARISC_BUG_H
-
-/*
- * Tell the user there is some problem.
- * The offending file and line are encoded in the __bug_table section.
- */
-
-#ifdef CONFIG_BUG
-#define HAVE_ARCH_BUG
-#define HAVE_ARCH_WARN_ON
-
-/* the break instruction is used as BUG() marker.  */
-#define	PARISC_BUG_BREAK_ASM	"break 0x1f, 0x1fff"
-#define	PARISC_BUG_BREAK_INSN	0x03ffe01f  /* PARISC_BUG_BREAK_ASM */
-
-#if defined(CONFIG_64BIT)
-#define ASM_WORD_INSN		".dword\t"
-#else
-#define ASM_WORD_INSN		".word\t"
-#endif
-
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-#define BUG()								\
-	do {								\
-		asm volatile("\n"					\
-			     "1:\t" PARISC_BUG_BREAK_ASM "\n"		\
-			     "\t.pushsection __bug_table,\"a\"\n"	\
-			     "2:\t" ASM_WORD_INSN "1b, %c0\n"		\
-			     "\t.short %c1, %c2\n"			\
-			     "\t.org 2b+%c3\n"				\
-			     "\t.popsection"				\
-			     : : "i" (__FILE__), "i" (__LINE__),	\
-			     "i" (0), "i" (sizeof(struct bug_entry)) ); \
-		for(;;) ;						\
-	} while(0)
-
-#else
-#define BUG()								\
-	do {								\
-		asm volatile(PARISC_BUG_BREAK_ASM : : );		\
-		for(;;) ;						\
-	} while(0)
-#endif
-
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-#define __WARN()							\
-	do {								\
-		asm volatile("\n"					\
-			     "1:\t" PARISC_BUG_BREAK_ASM "\n"		\
-			     "\t.pushsection __bug_table,\"a\"\n"	\
-			     "2:\t" ASM_WORD_INSN "1b, %c0\n"		\
-			     "\t.short %c1, %c2\n"			\
-			     "\t.org 2b+%c3\n"				\
-			     "\t.popsection"				\
-			     : : "i" (__FILE__), "i" (__LINE__),	\
-			     "i" (BUGFLAG_WARNING),			\
-			     "i" (sizeof(struct bug_entry)) );		\
-	} while(0)
-#else
-#define __WARN()							\
-	do {								\
-		asm volatile("\n"					\
-			     "1:\t" PARISC_BUG_BREAK_ASM "\n"		\
-			     "\t.pushsection __bug_table,\"a\"\n"	\
-			     "2:\t" ASM_WORD_INSN "1b\n"		\
-			     "\t.short %c0\n"				\
-			     "\t.org 2b+%c1\n"				\
-			     "\t.popsection"				\
-			     : : "i" (BUGFLAG_WARNING),			\
-			     "i" (sizeof(struct bug_entry)) );		\
-	} while(0)
-#endif
-
-
-#define WARN_ON(x) ({						\
-	int __ret_warn_on = !!(x);				\
-	if (__builtin_constant_p(__ret_warn_on)) {		\
-		if (__ret_warn_on)				\
-			__WARN();				\
-	} else {						\
-		if (unlikely(__ret_warn_on))			\
-			__WARN();				\
-	}							\
-	unlikely(__ret_warn_on);				\
-})
-
-#endif
-
-#include <asm-generic/bug.h>
-#endif
-
diff --git a/include/asm-parisc/bugs.h b/include/asm-parisc/bugs.h
deleted file mode 100644
index 9e6284342a5f..000000000000
--- a/include/asm-parisc/bugs.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- *  include/asm-parisc/bugs.h
- *
- *  Copyright (C) 1999	Mike Shaver
- */
-
-/*
- * This is included by init/main.c to check for architecture-dependent bugs.
- *
- * Needs:
- *	void check_bugs(void);
- */
-
-#include <asm/processor.h>
-
-static inline void check_bugs(void)
-{
-//	identify_cpu(&boot_cpu_data);
-}
diff --git a/include/asm-parisc/byteorder.h b/include/asm-parisc/byteorder.h
deleted file mode 100644
index db148313de5d..000000000000
--- a/include/asm-parisc/byteorder.h
+++ /dev/null
@@ -1,82 +0,0 @@
-#ifndef _PARISC_BYTEORDER_H
-#define _PARISC_BYTEORDER_H
-
-#include <asm/types.h>
-#include <linux/compiler.h>
-
-#ifdef __GNUC__
-
-static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
-{
-	__asm__("dep %0, 15, 8, %0\n\t"		/* deposit 00ab -> 0bab */
-		"shd %%r0, %0, 8, %0"		/* shift 000000ab -> 00ba */
-		: "=r" (x)
-		: "0" (x));
-	return x;
-}
-
-static __inline__ __attribute_const__ __u32 ___arch__swab24(__u32 x)
-{
-	__asm__("shd %0, %0, 8, %0\n\t"		/* shift xabcxabc -> cxab */
-		"dep %0, 15, 8, %0\n\t"		/* deposit cxab -> cbab */
-		"shd %%r0, %0, 8, %0"		/* shift 0000cbab -> 0cba */
-		: "=r" (x)
-		: "0" (x));
-	return x;
-}
-
-static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
-{
-	unsigned int temp;
-	__asm__("shd %0, %0, 16, %1\n\t"	/* shift abcdabcd -> cdab */
-		"dep %1, 15, 8, %1\n\t"		/* deposit cdab -> cbab */
-		"shd %0, %1, 8, %0"		/* shift abcdcbab -> dcba */
-		: "=r" (x), "=&r" (temp)
-		: "0" (x));
-	return x;
-}
-
-
-#if BITS_PER_LONG > 32
-/*
-** From "PA-RISC 2.0 Architecture", HP Professional Books.
-** See Appendix I page 8 , "Endian Byte Swapping".
-**
-** Pretty cool algorithm: (* == zero'd bits)
-**      PERMH   01234567 -> 67452301 into %0
-**      HSHL    67452301 -> 7*5*3*1* into %1
-**      HSHR    67452301 -> *6*4*2*0 into %0
-**      OR      %0 | %1  -> 76543210 into %0 (all done!)
-*/
-static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) {
-	__u64 temp;
-	__asm__("permh,3210 %0, %0\n\t"
-		"hshl %0, 8, %1\n\t"
-		"hshr,u %0, 8, %0\n\t"
-		"or %1, %0, %0"
-		: "=r" (x), "=&r" (temp)
-		: "0" (x));
-	return x;
-}
-#define __arch__swab64(x) ___arch__swab64(x)
-#define __BYTEORDER_HAS_U64__
-#elif !defined(__STRICT_ANSI__)
-static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
-{
-	__u32 t1 = ___arch__swab32((__u32) x);
-	__u32 t2 = ___arch__swab32((__u32) (x >> 32));
-	return (((__u64) t1 << 32) | t2);
-}
-#define __arch__swab64(x) ___arch__swab64(x)
-#define __BYTEORDER_HAS_U64__
-#endif
-
-#define __arch__swab16(x) ___arch__swab16(x)
-#define __arch__swab24(x) ___arch__swab24(x)
-#define __arch__swab32(x) ___arch__swab32(x)
-
-#endif /* __GNUC__ */
-
-#include <linux/byteorder/big_endian.h>
-
-#endif /* _PARISC_BYTEORDER_H */
diff --git a/include/asm-parisc/cache.h b/include/asm-parisc/cache.h
deleted file mode 100644
index 32c2cca74345..000000000000
--- a/include/asm-parisc/cache.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * include/asm-parisc/cache.h
- */
-
-#ifndef __ARCH_PARISC_CACHE_H
-#define __ARCH_PARISC_CACHE_H
-
-
-/*
- * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have
- * 32-byte cachelines.  The default configuration is not for SMP anyway,
- * so if you're building for SMP, you should select the appropriate
- * processor type.  There is a potential livelock danger when running
- * a machine with this value set too small, but it's more probable you'll
- * just ruin performance.
- */
-#ifdef CONFIG_PA20
-#define L1_CACHE_BYTES 64
-#define L1_CACHE_SHIFT 6
-#else
-#define L1_CACHE_BYTES 32
-#define L1_CACHE_SHIFT 5
-#endif
-
-#ifndef __ASSEMBLY__
-
-#define L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
-
-#define SMP_CACHE_BYTES L1_CACHE_BYTES
-
-#define __read_mostly __attribute__((__section__(".data.read_mostly")))
-
-void parisc_cache_init(void);	/* initializes cache-flushing */
-void disable_sr_hashing_asm(int); /* low level support for above */
-void disable_sr_hashing(void);   /* turns off space register hashing */
-void free_sid(unsigned long);
-unsigned long alloc_sid(void);
-
-struct seq_file;
-extern void show_cache_info(struct seq_file *m);
-
-extern int split_tlb;
-extern int dcache_stride;
-extern int icache_stride;
-extern struct pdc_cache_info cache_info;
-void parisc_setup_cache_timing(void);
-
-#define pdtlb(addr)         asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr));
-#define pitlb(addr)         asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr));
-#define pdtlb_kernel(addr)  asm volatile("pdtlb 0(%0)" : : "r" (addr));
-
-#endif /* ! __ASSEMBLY__ */
-
-/* Classes of processor wrt: disabling space register hashing */
-
-#define SRHASH_PCXST    0   /* pcxs, pcxt, pcxt_ */
-#define SRHASH_PCXL     1   /* pcxl */
-#define SRHASH_PA20     2   /* pcxu, pcxu_, pcxw, pcxw_ */
-
-#endif
diff --git a/include/asm-parisc/cacheflush.h b/include/asm-parisc/cacheflush.h
deleted file mode 100644
index b7ca6dc7fddc..000000000000
--- a/include/asm-parisc/cacheflush.h
+++ /dev/null
@@ -1,121 +0,0 @@
-#ifndef _PARISC_CACHEFLUSH_H
-#define _PARISC_CACHEFLUSH_H
-
-#include <linux/mm.h>
-
-/* The usual comment is "Caches aren't brain-dead on the <architecture>".
- * Unfortunately, that doesn't apply to PA-RISC. */
-
-/* Internal implementation */
-void flush_data_cache_local(void *);  /* flushes local data-cache only */
-void flush_instruction_cache_local(void *); /* flushes local code-cache only */
-#ifdef CONFIG_SMP
-void flush_data_cache(void); /* flushes data-cache only (all processors) */
-void flush_instruction_cache(void); /* flushes i-cache only (all processors) */
-#else
-#define flush_data_cache() flush_data_cache_local(NULL)
-#define flush_instruction_cache() flush_instruction_cache_local(NULL)
-#endif
-
-#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
-
-void flush_user_icache_range_asm(unsigned long, unsigned long);
-void flush_kernel_icache_range_asm(unsigned long, unsigned long);
-void flush_user_dcache_range_asm(unsigned long, unsigned long);
-void flush_kernel_dcache_range_asm(unsigned long, unsigned long);
-void flush_kernel_dcache_page_asm(void *);
-void flush_kernel_icache_page(void *);
-void flush_user_dcache_page(unsigned long);
-void flush_user_icache_page(unsigned long);
-void flush_user_dcache_range(unsigned long, unsigned long);
-void flush_user_icache_range(unsigned long, unsigned long);
-
-/* Cache flush operations */
-
-void flush_cache_all_local(void);
-void flush_cache_all(void);
-void flush_cache_mm(struct mm_struct *mm);
-
-#define flush_kernel_dcache_range(start,size) \
-	flush_kernel_dcache_range_asm((start), (start)+(size));
-
-#define flush_cache_vmap(start, end)		flush_cache_all()
-#define flush_cache_vunmap(start, end)		flush_cache_all()
-
-extern void flush_dcache_page(struct page *page);
-
-#define flush_dcache_mmap_lock(mapping) \
-	spin_lock_irq(&(mapping)->tree_lock)
-#define flush_dcache_mmap_unlock(mapping) \
-	spin_unlock_irq(&(mapping)->tree_lock)
-
-#define flush_icache_page(vma,page)	do { 		\
-	flush_kernel_dcache_page(page);			\
-	flush_kernel_icache_page(page_address(page)); 	\
-} while (0)
-
-#define flush_icache_range(s,e)		do { 		\
-	flush_kernel_dcache_range_asm(s,e); 		\
-	flush_kernel_icache_range_asm(s,e); 		\
-} while (0)
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-do { \
-	flush_cache_page(vma, vaddr, page_to_pfn(page)); \
-	memcpy(dst, src, len); \
-	flush_kernel_dcache_range_asm((unsigned long)dst, (unsigned long)dst + len); \
-} while (0)
-
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
-do { \
-	flush_cache_page(vma, vaddr, page_to_pfn(page)); \
-	memcpy(dst, src, len); \
-} while (0)
-
-void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn);
-void flush_cache_range(struct vm_area_struct *vma,
-		unsigned long start, unsigned long end);
-
-#define ARCH_HAS_FLUSH_ANON_PAGE
-static inline void
-flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr)
-{
-	if (PageAnon(page))
-		flush_user_dcache_page(vmaddr);
-}
-
-#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
-void flush_kernel_dcache_page_addr(void *addr);
-static inline void flush_kernel_dcache_page(struct page *page)
-{
-	flush_kernel_dcache_page_addr(page_address(page));
-}
-
-#ifdef CONFIG_DEBUG_RODATA
-void mark_rodata_ro(void);
-#endif
-
-#ifdef CONFIG_PA8X00
-/* Only pa8800, pa8900 needs this */
-#define ARCH_HAS_KMAP
-
-void kunmap_parisc(void *addr);
-
-static inline void *kmap(struct page *page)
-{
-	might_sleep();
-	return page_address(page);
-}
-
-#define kunmap(page)			kunmap_parisc(page_address(page))
-
-#define kmap_atomic(page, idx)		page_address(page)
-
-#define kunmap_atomic(addr, idx)	kunmap_parisc(addr)
-
-#define kmap_atomic_pfn(pfn, idx)	page_address(pfn_to_page(pfn))
-#define kmap_atomic_to_page(ptr)	virt_to_page(ptr)
-#endif
-
-#endif /* _PARISC_CACHEFLUSH_H */
-
diff --git a/include/asm-parisc/checksum.h b/include/asm-parisc/checksum.h
deleted file mode 100644
index e9639ccc3fce..000000000000
--- a/include/asm-parisc/checksum.h
+++ /dev/null
@@ -1,210 +0,0 @@
-#ifndef _PARISC_CHECKSUM_H
-#define _PARISC_CHECKSUM_H
-
-#include <linux/in6.h>
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-extern __wsum csum_partial(const void *, int, __wsum);
-
-/*
- * The same as csum_partial, but copies from src while it checksums.
- *
- * Here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-extern __wsum csum_partial_copy_nocheck(const void *, void *, int, __wsum);
-
-/*
- * this is a new version of the above that records errors it finds in *errp,
- * but continues and zeros the rest of the buffer.
- */
-extern __wsum csum_partial_copy_from_user(const void __user *src,
-		void *dst, int len, __wsum sum, int *errp);
-
-/*
- *	Optimized for IP headers, which always checksum on 4 octet boundaries.
- *
- *	Written by Randolph Chung <tausq@debian.org>, and then mucked with by
- *	LaMont Jones <lamont@debian.org>
- */
-static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
-{
-	unsigned int sum;
-
-	__asm__ __volatile__ (
-"	ldws,ma		4(%1), %0\n"
-"	addib,<=	-4, %2, 2f\n"
-"\n"
-"	ldws		4(%1), %%r20\n"
-"	ldws		8(%1), %%r21\n"
-"	add		%0, %%r20, %0\n"
-"	ldws,ma		12(%1), %%r19\n"
-"	addc		%0, %%r21, %0\n"
-"	addc		%0, %%r19, %0\n"
-"1:	ldws,ma		4(%1), %%r19\n"
-"	addib,<		0, %2, 1b\n"
-"	addc		%0, %%r19, %0\n"
-"\n"
-"	extru		%0, 31, 16, %%r20\n"
-"	extru		%0, 15, 16, %%r21\n"
-"	addc		%%r20, %%r21, %0\n"
-"	extru		%0, 15, 16, %%r21\n"
-"	add		%0, %%r21, %0\n"
-"	subi		-1, %0, %0\n"
-"2:\n"
-	: "=r" (sum), "=r" (iph), "=r" (ihl)
-	: "1" (iph), "2" (ihl)
-	: "r19", "r20", "r21", "memory");
-
-	return (__force __sum16)sum;
-}
-
-/*
- *	Fold a partial checksum
- */
-static inline __sum16 csum_fold(__wsum csum)
-{
-	u32 sum = (__force u32)csum;
-	/* add the swapped two 16-bit halves of sum,
-	   a possible carry from adding the two 16-bit halves,
-	   will carry from the lower half into the upper half,
-	   giving us the correct sum in the upper half. */
-	sum += (sum << 16) + (sum >> 16);
-	return (__force __sum16)(~sum >> 16);
-}
- 
-static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
-					       unsigned short len,
-					       unsigned short proto,
-					       __wsum sum)
-{
-	__asm__(
-	"	add  %1, %0, %0\n"
-	"	addc %2, %0, %0\n"
-	"	addc %3, %0, %0\n"
-	"	addc %%r0, %0, %0\n"
-		: "=r" (sum)
-		: "r" (daddr), "r"(saddr), "r"(proto+len), "0"(sum));
-	return sum;
-}
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
-						   unsigned short len,
-						   unsigned short proto,
-						   __wsum sum)
-{
-	return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-static inline __sum16 ip_compute_csum(const void *buf, int len)
-{
-	 return csum_fold (csum_partial(buf, len, 0));
-}
-
-
-#define _HAVE_ARCH_IPV6_CSUM
-static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
-					  const struct in6_addr *daddr,
-					  __u32 len, unsigned short proto,
-					  __wsum sum)
-{
-	__asm__ __volatile__ (
-
-#if BITS_PER_LONG > 32
-
-	/*
-	** We can execute two loads and two adds per cycle on PA 8000.
-	** But add insn's get serialized waiting for the carry bit.
-	** Try to keep 4 registers with "live" values ahead of the ALU.
-	*/
-
-"	ldd,ma		8(%1), %%r19\n"	/* get 1st saddr word */
-"	ldd,ma		8(%2), %%r20\n"	/* get 1st daddr word */
-"	add		%8, %3, %3\n"/* add 16-bit proto + len */
-"	add		%%r19, %0, %0\n"
-"	ldd,ma		8(%1), %%r21\n"	/* 2cd saddr */
-"	ldd,ma		8(%2), %%r22\n"	/* 2cd daddr */
-"	add,dc		%%r20, %0, %0\n"
-"	add,dc		%%r21, %0, %0\n"
-"	add,dc		%%r22, %0, %0\n"
-"	add,dc		%3, %0, %0\n"  /* fold in proto+len | carry bit */
-"	extrd,u		%0, 31, 32, %%r19\n"	/* copy upper half down */
-"	depdi		0, 31, 32, %0\n"	/* clear upper half */
-"	add		%%r19, %0, %0\n"	/* fold into 32-bits */
-"	addc		0, %0, %0\n"		/* add carry */
-
-#else
-
-	/*
-	** For PA 1.x, the insn order doesn't matter as much.
-	** Insn stream is serialized on the carry bit here too.
-	** result from the previous operation (eg r0 + x)
-	*/
-
-"	ldw,ma		4(%1), %%r19\n"	/* get 1st saddr word */
-"	ldw,ma		4(%2), %%r20\n"	/* get 1st daddr word */
-"	add		%8, %3, %3\n"	/* add 16-bit proto + len */
-"	add		%%r19, %0, %0\n"
-"	ldw,ma		4(%1), %%r21\n"	/* 2cd saddr */
-"	addc		%%r20, %0, %0\n"
-"	ldw,ma		4(%2), %%r22\n"	/* 2cd daddr */
-"	addc		%%r21, %0, %0\n"
-"	ldw,ma		4(%1), %%r19\n"	/* 3rd saddr */
-"	addc		%%r22, %0, %0\n"
-"	ldw,ma		4(%2), %%r20\n"	/* 3rd daddr */
-"	addc		%%r19, %0, %0\n"
-"	ldw,ma		4(%1), %%r21\n"	/* 4th saddr */
-"	addc		%%r20, %0, %0\n"
-"	ldw,ma		4(%2), %%r22\n"	/* 4th daddr */
-"	addc		%%r21, %0, %0\n"
-"	addc		%%r22, %0, %0\n"
-"	addc		%3, %0, %0\n"	/* fold in proto+len, catch carry */
-
-#endif
-	: "=r" (sum), "=r" (saddr), "=r" (daddr), "=r" (len)
-	: "0" (sum), "1" (saddr), "2" (daddr), "3" (len), "r" (proto)
-	: "r19", "r20", "r21", "r22");
-	return csum_fold(sum);
-}
-
-/* 
- *	Copy and checksum to user
- */
-#define HAVE_CSUM_COPY_USER
-static __inline__ __wsum csum_and_copy_to_user(const void *src,
-						      void __user *dst,
-						      int len, __wsum sum,
-						      int *err_ptr)
-{
-	/* code stolen from include/asm-mips64 */
-	sum = csum_partial(src, len, sum);
-	 
-	if (copy_to_user(dst, src, len)) {
-		*err_ptr = -EFAULT;
-		return (__force __wsum)-1;
-	}
-
-	return sum;
-}
-
-#endif
-
diff --git a/include/asm-parisc/compat.h b/include/asm-parisc/compat.h
deleted file mode 100644
index 7f32611a7a5e..000000000000
--- a/include/asm-parisc/compat.h
+++ /dev/null
@@ -1,165 +0,0 @@
-#ifndef _ASM_PARISC_COMPAT_H
-#define _ASM_PARISC_COMPAT_H
-/*
- * Architecture specific compatibility types
- */
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/thread_info.h>
-
-#define COMPAT_USER_HZ 100
-
-typedef u32	compat_size_t;
-typedef s32	compat_ssize_t;
-typedef s32	compat_time_t;
-typedef s32	compat_clock_t;
-typedef s32	compat_pid_t;
-typedef u32	__compat_uid_t;
-typedef u32	__compat_gid_t;
-typedef u32	__compat_uid32_t;
-typedef u32	__compat_gid32_t;
-typedef u16	compat_mode_t;
-typedef u32	compat_ino_t;
-typedef u32	compat_dev_t;
-typedef s32	compat_off_t;
-typedef s64	compat_loff_t;
-typedef u16	compat_nlink_t;
-typedef u16	compat_ipc_pid_t;
-typedef s32	compat_daddr_t;
-typedef u32	compat_caddr_t;
-typedef s32	compat_timer_t;
-
-typedef s32	compat_int_t;
-typedef s32	compat_long_t;
-typedef s64	compat_s64;
-typedef u32	compat_uint_t;
-typedef u32	compat_ulong_t;
-typedef u64	compat_u64;
-
-struct compat_timespec {
-	compat_time_t		tv_sec;
-	s32			tv_nsec;
-};
-
-struct compat_timeval {
-	compat_time_t		tv_sec;
-	s32			tv_usec;
-};
-
-struct compat_stat {
-	compat_dev_t		st_dev;	/* dev_t is 32 bits on parisc */
-	compat_ino_t		st_ino;	/* 32 bits */
-	compat_mode_t		st_mode;	/* 16 bits */
-	compat_nlink_t  	st_nlink;	/* 16 bits */
-	u16			st_reserved1;	/* old st_uid */
-	u16			st_reserved2;	/* old st_gid */
-	compat_dev_t		st_rdev;
-	compat_off_t		st_size;
-	compat_time_t		st_atime;
-	u32			st_atime_nsec;
-	compat_time_t		st_mtime;
-	u32			st_mtime_nsec;
-	compat_time_t		st_ctime;
-	u32			st_ctime_nsec;
-	s32			st_blksize;
-	s32			st_blocks;
-	u32			__unused1;	/* ACL stuff */
-	compat_dev_t		__unused2;	/* network */
-	compat_ino_t		__unused3;	/* network */
-	u32			__unused4;	/* cnodes */
-	u16			__unused5;	/* netsite */
-	short			st_fstype;
-	compat_dev_t		st_realdev;
-	u16			st_basemode;
-	u16			st_spareshort;
-	__compat_uid32_t	st_uid;
-	__compat_gid32_t	st_gid;
-	u32			st_spare4[3];
-};
-
-struct compat_flock {
-	short			l_type;
-	short			l_whence;
-	compat_off_t		l_start;
-	compat_off_t		l_len;
-	compat_pid_t		l_pid;
-};
-
-struct compat_flock64 {
-	short			l_type;
-	short			l_whence;
-	compat_loff_t		l_start;
-	compat_loff_t		l_len;
-	compat_pid_t		l_pid;
-};
-
-struct compat_statfs {
-	s32		f_type;
-	s32		f_bsize;
-	s32		f_blocks;
-	s32		f_bfree;
-	s32		f_bavail;
-	s32		f_files;
-	s32		f_ffree;
-	__kernel_fsid_t	f_fsid;
-	s32		f_namelen;
-	s32		f_frsize;
-	s32		f_spare[5];
-};
-
-struct compat_sigcontext {
-	compat_int_t sc_flags;
-	compat_int_t sc_gr[32]; /* PSW in sc_gr[0] */
-	u64 sc_fr[32];
-	compat_int_t sc_iasq[2];
-	compat_int_t sc_iaoq[2];
-	compat_int_t sc_sar; /* cr11 */
-};
-
-#define COMPAT_RLIM_INFINITY 0xffffffff
-
-typedef u32		compat_old_sigset_t;	/* at least 32 bits */
-
-#define _COMPAT_NSIG		64
-#define _COMPAT_NSIG_BPW	32
-
-typedef u32		compat_sigset_word;
-
-#define COMPAT_OFF_T_MAX	0x7fffffff
-#define COMPAT_LOFF_T_MAX	0x7fffffffffffffffL
-
-/*
- * A pointer passed in from user mode. This should not
- * be used for syscall parameters, just declare them
- * as pointers because the syscall entry code will have
- * appropriately converted them already.
- */
-typedef	u32		compat_uptr_t;
-
-static inline void __user *compat_ptr(compat_uptr_t uptr)
-{
-	return (void __user *)(unsigned long)uptr;
-}
-
-static inline compat_uptr_t ptr_to_compat(void __user *uptr)
-{
-	return (u32)(unsigned long)uptr;
-}
-
-static __inline__ void __user *compat_alloc_user_space(long len)
-{
-	struct pt_regs *regs = &current->thread.regs;
-	return (void __user *)regs->gr[30];
-}
-
-static inline int __is_compat_task(struct task_struct *t)
-{
-	return test_ti_thread_flag(task_thread_info(t), TIF_32BIT);
-}
-
-static inline int is_compat_task(void)
-{
-	return __is_compat_task(current);
-}
-
-#endif /* _ASM_PARISC_COMPAT_H */
diff --git a/include/asm-parisc/compat_rt_sigframe.h b/include/asm-parisc/compat_rt_sigframe.h
deleted file mode 100644
index 81bec28bdc48..000000000000
--- a/include/asm-parisc/compat_rt_sigframe.h
+++ /dev/null
@@ -1,50 +0,0 @@
-#include<linux/compat.h>
-#include<linux/compat_siginfo.h>
-#include<asm/compat_ucontext.h>
-
-#ifndef _ASM_PARISC_COMPAT_RT_SIGFRAME_H
-#define _ASM_PARISC_COMPAT_RT_SIGFRAME_H
-
-/* In a deft move of uber-hackery, we decide to carry the top half of all
- * 64-bit registers in a non-portable, non-ABI, hidden structure.
- * Userspace can read the hidden structure if it *wants* but is never
- * guaranteed to be in the same place. Infact the uc_sigmask from the 
- * ucontext_t structure may push the hidden register file downards
- */
-struct compat_regfile {
-	/* Upper half of all the 64-bit registers that were truncated
-	   on a copy to a 32-bit userspace */
-	compat_int_t rf_gr[32];
-	compat_int_t rf_iasq[2];
-	compat_int_t rf_iaoq[2];
-	compat_int_t rf_sar;
-};
-
-#define COMPAT_SIGRETURN_TRAMP 4
-#define COMPAT_SIGRESTARTBLOCK_TRAMP 5 
-#define COMPAT_TRAMP_SIZE (COMPAT_SIGRETURN_TRAMP + COMPAT_SIGRESTARTBLOCK_TRAMP)
-
-struct compat_rt_sigframe {
-	/* XXX: Must match trampoline size in arch/parisc/kernel/signal.c 
-	        Secondary to that it must protect the ERESTART_RESTARTBLOCK
-		trampoline we left on the stack (we were bad and didn't 
-		change sp so we could run really fast.) */
-	compat_uint_t tramp[COMPAT_TRAMP_SIZE];
-	compat_siginfo_t info;
-	struct compat_ucontext uc;
-	/* Hidden location of truncated registers, *must* be last. */
-	struct compat_regfile regs; 
-};
-
-/*
- * The 32-bit ABI wants at least 48 bytes for a function call frame:
- * 16 bytes for arg0-arg3, and 32 bytes for magic (the only part of
- * which Linux/parisc uses is sp-20 for the saved return pointer...)
- * Then, the stack pointer must be rounded to a cache line (64 bytes).
- */
-#define SIGFRAME32		64
-#define FUNCTIONCALLFRAME32	48
-#define PARISC_RT_SIGFRAME_SIZE32					\
-	(((sizeof(struct compat_rt_sigframe) + FUNCTIONCALLFRAME32) + SIGFRAME32) & -SIGFRAME32)
-
-#endif
diff --git a/include/asm-parisc/compat_signal.h b/include/asm-parisc/compat_signal.h
deleted file mode 100644
index 6ad02c360b21..000000000000
--- a/include/asm-parisc/compat_signal.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* Use generic */
-#include <asm-generic/compat_signal.h>
diff --git a/include/asm-parisc/compat_ucontext.h b/include/asm-parisc/compat_ucontext.h
deleted file mode 100644
index 2f7292afde3c..000000000000
--- a/include/asm-parisc/compat_ucontext.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef _ASM_PARISC_COMPAT_UCONTEXT_H
-#define _ASM_PARISC_COMPAT_UCONTEXT_H
-
-#include <linux/compat.h>
-
-/* 32-bit ucontext as seen from an 64-bit kernel */
-struct compat_ucontext {
-	compat_uint_t uc_flags;
-	compat_uptr_t uc_link;
-	compat_stack_t uc_stack;	/* struct compat_sigaltstack (12 bytes)*/	
-	/* FIXME: Pad out to get uc_mcontext to start at an 8-byte aligned boundary */
-	compat_uint_t pad[1];
-	struct compat_sigcontext uc_mcontext;
-	compat_sigset_t uc_sigmask;	/* mask last for extensibility */
-};
-
-#endif /* !_ASM_PARISC_COMPAT_UCONTEXT_H */
diff --git a/include/asm-parisc/cputime.h b/include/asm-parisc/cputime.h
deleted file mode 100644
index dcdf2fbd7e72..000000000000
--- a/include/asm-parisc/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __PARISC_CPUTIME_H
-#define __PARISC_CPUTIME_H
-
-#include <asm-generic/cputime.h>
-
-#endif /* __PARISC_CPUTIME_H */
diff --git a/include/asm-parisc/current.h b/include/asm-parisc/current.h
deleted file mode 100644
index 0fb9338e3bf2..000000000000
--- a/include/asm-parisc/current.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef _PARISC_CURRENT_H
-#define _PARISC_CURRENT_H
-
-#include <linux/thread_info.h>
-
-struct task_struct;
-
-static inline struct task_struct * get_current(void)
-{
-	return current_thread_info()->task;
-}
- 
-#define current get_current()
-
-#endif /* !(_PARISC_CURRENT_H) */
diff --git a/include/asm-parisc/delay.h b/include/asm-parisc/delay.h
deleted file mode 100644
index 7a75e984674b..000000000000
--- a/include/asm-parisc/delay.h
+++ /dev/null
@@ -1,43 +0,0 @@
-#ifndef _PARISC_DELAY_H
-#define _PARISC_DELAY_H
-
-#include <asm/system.h>    /* for mfctl() */
-#include <asm/processor.h> /* for boot_cpu_data */
-
-
-/*
- * Copyright (C) 1993 Linus Torvalds
- *
- * Delay routines
- */
-
-static __inline__ void __delay(unsigned long loops) {
-	asm volatile(
-	"	.balignl	64,0x34000034\n"
-	"	addib,UV -1,%0,.\n"
-	"	nop\n"
-		: "=r" (loops) : "0" (loops));
-}
-
-static __inline__ void __cr16_delay(unsigned long clocks) {
-	unsigned long start;
-
-	/*
-	 * Note: Due to unsigned math, cr16 rollovers shouldn't be
-	 * a problem here. However, on 32 bit, we need to make sure
-	 * we don't pass in too big a value. The current default
-	 * value of MAX_UDELAY_MS should help prevent this.
-	 */
-
-	start = mfctl(16);
-	while ((mfctl(16) - start) < clocks)
-	    ;
-}
-
-static __inline__ void __udelay(unsigned long usecs) {
-	__cr16_delay(usecs * ((unsigned long)boot_cpu_data.cpu_hz / 1000000UL));
-}
-
-#define udelay(n) __udelay(n)
-
-#endif /* defined(_PARISC_DELAY_H) */
diff --git a/include/asm-parisc/device.h b/include/asm-parisc/device.h
deleted file mode 100644
index d8f9872b0e2d..000000000000
--- a/include/asm-parisc/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-#include <asm-generic/device.h>
-
diff --git a/include/asm-parisc/div64.h b/include/asm-parisc/div64.h
deleted file mode 100644
index 6cd978cefb28..000000000000
--- a/include/asm-parisc/div64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/div64.h>
diff --git a/include/asm-parisc/dma-mapping.h b/include/asm-parisc/dma-mapping.h
deleted file mode 100644
index 53af696f23d2..000000000000
--- a/include/asm-parisc/dma-mapping.h
+++ /dev/null
@@ -1,253 +0,0 @@
-#ifndef _PARISC_DMA_MAPPING_H
-#define _PARISC_DMA_MAPPING_H
-
-#include <linux/mm.h>
-#include <asm/cacheflush.h>
-#include <asm/scatterlist.h>
-
-/* See Documentation/DMA-mapping.txt */
-struct hppa_dma_ops {
-	int  (*dma_supported)(struct device *dev, u64 mask);
-	void *(*alloc_consistent)(struct device *dev, size_t size, dma_addr_t *iova, gfp_t flag);
-	void *(*alloc_noncoherent)(struct device *dev, size_t size, dma_addr_t *iova, gfp_t flag);
-	void (*free_consistent)(struct device *dev, size_t size, void *vaddr, dma_addr_t iova);
-	dma_addr_t (*map_single)(struct device *dev, void *addr, size_t size, enum dma_data_direction direction);
-	void (*unmap_single)(struct device *dev, dma_addr_t iova, size_t size, enum dma_data_direction direction);
-	int  (*map_sg)(struct device *dev, struct scatterlist *sg, int nents, enum dma_data_direction direction);
-	void (*unmap_sg)(struct device *dev, struct scatterlist *sg, int nhwents, enum dma_data_direction direction);
-	void (*dma_sync_single_for_cpu)(struct device *dev, dma_addr_t iova, unsigned long offset, size_t size, enum dma_data_direction direction);
-	void (*dma_sync_single_for_device)(struct device *dev, dma_addr_t iova, unsigned long offset, size_t size, enum dma_data_direction direction);
-	void (*dma_sync_sg_for_cpu)(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction direction);
-	void (*dma_sync_sg_for_device)(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction direction);
-};
-
-/*
-** We could live without the hppa_dma_ops indirection if we didn't want
-** to support 4 different coherent dma models with one binary (they will
-** someday be loadable modules):
-**     I/O MMU        consistent method           dma_sync behavior
-**  =============   ======================       =======================
-**  a) PA-7x00LC    uncachable host memory          flush/purge
-**  b) U2/Uturn      cachable host memory              NOP
-**  c) Ike/Astro     cachable host memory              NOP
-**  d) EPIC/SAGA     memory on EPIC/SAGA         flush/reset DMA channel
-**
-** PA-7[13]00LC processors have a GSC bus interface and no I/O MMU.
-**
-** Systems (eg PCX-T workstations) that don't fall into the above
-** categories will need to modify the needed drivers to perform
-** flush/purge and allocate "regular" cacheable pages for everything.
-*/
-
-#ifdef CONFIG_PA11
-extern struct hppa_dma_ops pcxl_dma_ops;
-extern struct hppa_dma_ops pcx_dma_ops;
-#endif
-
-extern struct hppa_dma_ops *hppa_dma_ops;
-
-static inline void *
-dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
-		   gfp_t flag)
-{
-	return hppa_dma_ops->alloc_consistent(dev, size, dma_handle, flag);
-}
-
-static inline void *
-dma_alloc_noncoherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
-		      gfp_t flag)
-{
-	return hppa_dma_ops->alloc_noncoherent(dev, size, dma_handle, flag);
-}
-
-static inline void
-dma_free_coherent(struct device *dev, size_t size, 
-		    void *vaddr, dma_addr_t dma_handle)
-{
-	hppa_dma_ops->free_consistent(dev, size, vaddr, dma_handle);
-}
-
-static inline void
-dma_free_noncoherent(struct device *dev, size_t size, 
-		    void *vaddr, dma_addr_t dma_handle)
-{
-	hppa_dma_ops->free_consistent(dev, size, vaddr, dma_handle);
-}
-
-static inline dma_addr_t
-dma_map_single(struct device *dev, void *ptr, size_t size,
-	       enum dma_data_direction direction)
-{
-	return hppa_dma_ops->map_single(dev, ptr, size, direction);
-}
-
-static inline void
-dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
-		 enum dma_data_direction direction)
-{
-	hppa_dma_ops->unmap_single(dev, dma_addr, size, direction);
-}
-
-static inline int
-dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-	   enum dma_data_direction direction)
-{
-	return hppa_dma_ops->map_sg(dev, sg, nents, direction);
-}
-
-static inline void
-dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
-	     enum dma_data_direction direction)
-{
-	hppa_dma_ops->unmap_sg(dev, sg, nhwentries, direction);
-}
-
-static inline dma_addr_t
-dma_map_page(struct device *dev, struct page *page, unsigned long offset,
-	     size_t size, enum dma_data_direction direction)
-{
-	return dma_map_single(dev, (page_address(page) + (offset)), size, direction);
-}
-
-static inline void
-dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
-	       enum dma_data_direction direction)
-{
-	dma_unmap_single(dev, dma_address, size, direction);
-}
-
-
-static inline void
-dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size,
-		enum dma_data_direction direction)
-{
-	if(hppa_dma_ops->dma_sync_single_for_cpu)
-		hppa_dma_ops->dma_sync_single_for_cpu(dev, dma_handle, 0, size, direction);
-}
-
-static inline void
-dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size,
-		enum dma_data_direction direction)
-{
-	if(hppa_dma_ops->dma_sync_single_for_device)
-		hppa_dma_ops->dma_sync_single_for_device(dev, dma_handle, 0, size, direction);
-}
-
-static inline void
-dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
-		      unsigned long offset, size_t size,
-		      enum dma_data_direction direction)
-{
-	if(hppa_dma_ops->dma_sync_single_for_cpu)
-		hppa_dma_ops->dma_sync_single_for_cpu(dev, dma_handle, offset, size, direction);
-}
-
-static inline void
-dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
-		      unsigned long offset, size_t size,
-		      enum dma_data_direction direction)
-{
-	if(hppa_dma_ops->dma_sync_single_for_device)
-		hppa_dma_ops->dma_sync_single_for_device(dev, dma_handle, offset, size, direction);
-}
-
-static inline void
-dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
-		 enum dma_data_direction direction)
-{
-	if(hppa_dma_ops->dma_sync_sg_for_cpu)
-		hppa_dma_ops->dma_sync_sg_for_cpu(dev, sg, nelems, direction);
-}
-
-static inline void
-dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
-		 enum dma_data_direction direction)
-{
-	if(hppa_dma_ops->dma_sync_sg_for_device)
-		hppa_dma_ops->dma_sync_sg_for_device(dev, sg, nelems, direction);
-}
-
-static inline int
-dma_supported(struct device *dev, u64 mask)
-{
-	return hppa_dma_ops->dma_supported(dev, mask);
-}
-
-static inline int
-dma_set_mask(struct device *dev, u64 mask)
-{
-	if(!dev->dma_mask || !dma_supported(dev, mask))
-		return -EIO;
-
-	*dev->dma_mask = mask;
-
-	return 0;
-}
-
-static inline int
-dma_get_cache_alignment(void)
-{
-	return dcache_stride;
-}
-
-static inline int
-dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
-{
-	return (hppa_dma_ops->dma_sync_single_for_cpu == NULL);
-}
-
-static inline void
-dma_cache_sync(struct device *dev, void *vaddr, size_t size,
-	       enum dma_data_direction direction)
-{
-	if(hppa_dma_ops->dma_sync_single_for_cpu)
-		flush_kernel_dcache_range((unsigned long)vaddr, size);
-}
-
-static inline void *
-parisc_walk_tree(struct device *dev)
-{
-	struct device *otherdev;
-	if(likely(dev->platform_data != NULL))
-		return dev->platform_data;
-	/* OK, just traverse the bus to find it */
-	for(otherdev = dev->parent; otherdev;
-	    otherdev = otherdev->parent) {
-		if(otherdev->platform_data) {
-			dev->platform_data = otherdev->platform_data;
-			break;
-		}
-	}
-	BUG_ON(!dev->platform_data);
-	return dev->platform_data;
-}
-		
-#define GET_IOC(dev) (HBA_DATA(parisc_walk_tree(dev))->iommu);	
-	
-
-#ifdef CONFIG_IOMMU_CCIO
-struct parisc_device;
-struct ioc;
-void * ccio_get_iommu(const struct parisc_device *dev);
-int ccio_request_resource(const struct parisc_device *dev,
-		struct resource *res);
-int ccio_allocate_resource(const struct parisc_device *dev,
-		struct resource *res, unsigned long size,
-		unsigned long min, unsigned long max, unsigned long align);
-#else /* !CONFIG_IOMMU_CCIO */
-#define ccio_get_iommu(dev) NULL
-#define ccio_request_resource(dev, res) insert_resource(&iomem_resource, res)
-#define ccio_allocate_resource(dev, res, size, min, max, align) \
-		allocate_resource(&iomem_resource, res, size, min, max, \
-				align, NULL, NULL)
-#endif /* !CONFIG_IOMMU_CCIO */
-
-#ifdef CONFIG_IOMMU_SBA
-struct parisc_device;
-void * sba_get_iommu(struct parisc_device *dev);
-#endif
-
-/* At the moment, we panic on error for IOMMU resource exaustion */
-#define dma_mapping_error(dev, x)	0
-
-#endif
diff --git a/include/asm-parisc/dma.h b/include/asm-parisc/dma.h
deleted file mode 100644
index 31ad0f05af3d..000000000000
--- a/include/asm-parisc/dma.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/* $Id: dma.h,v 1.2 1999/04/27 00:46:18 deller Exp $
- * linux/include/asm/dma.h: Defines for using and allocating dma channels.
- * Written by Hennus Bergman, 1992.
- * High DMA channel support & info by Hannu Savolainen
- * and John Boyd, Nov. 1992.
- * (c) Copyright 2000, Grant Grundler
- */
-
-#ifndef _ASM_DMA_H
-#define _ASM_DMA_H
-
-#include <asm/io.h>		/* need byte IO */
-#include <asm/system.h>	
-
-#define dma_outb	outb
-#define dma_inb		inb
-
-/*
-** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
-** (or rather not merge) DMAs into manageable chunks.
-** On parisc, this is more of the software/tuning constraint
-** rather than the HW. I/O MMU allocation algorithms can be
-** faster with smaller sizes (to some degree).
-*/
-#define DMA_CHUNK_SIZE	(BITS_PER_LONG*PAGE_SIZE)
-
-/* The maximum address that we can perform a DMA transfer to on this platform
-** New dynamic DMA interfaces should obsolete this....
-*/
-#define MAX_DMA_ADDRESS (~0UL)
-
-/*
-** We don't have DMA channels... well V-class does but the
-** Dynamic DMA Mapping interface will support them... right? :^)
-** Note: this is not relevant right now for PA-RISC, but we cannot 
-** leave this as undefined because some things (e.g. sound)
-** won't compile :-(
-*/
-#define MAX_DMA_CHANNELS 8
-#define DMA_MODE_READ	0x44	/* I/O to memory, no autoinit, increment, single mode */
-#define DMA_MODE_WRITE	0x48	/* memory to I/O, no autoinit, increment, single mode */
-#define DMA_MODE_CASCADE 0xC0	/* pass thru DREQ->HRQ, DACK<-HLDA only */
-
-#define DMA_AUTOINIT	0x10
-
-/* 8237 DMA controllers */
-#define IO_DMA1_BASE	0x00	/* 8 bit slave DMA, channels 0..3 */
-#define IO_DMA2_BASE	0xC0	/* 16 bit master DMA, ch 4(=slave input)..7 */
-
-/* DMA controller registers */
-#define DMA1_CMD_REG		0x08	/* command register (w) */
-#define DMA1_STAT_REG		0x08	/* status register (r) */
-#define DMA1_REQ_REG            0x09    /* request register (w) */
-#define DMA1_MASK_REG		0x0A	/* single-channel mask (w) */
-#define DMA1_MODE_REG		0x0B	/* mode register (w) */
-#define DMA1_CLEAR_FF_REG	0x0C	/* clear pointer flip-flop (w) */
-#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
-#define DMA1_RESET_REG		0x0D	/* Master Clear (w) */
-#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
-#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
-#define DMA1_EXT_MODE_REG	(0x400 | DMA1_MODE_REG)
-
-#define DMA2_CMD_REG		0xD0	/* command register (w) */
-#define DMA2_STAT_REG		0xD0	/* status register (r) */
-#define DMA2_REQ_REG            0xD2    /* request register (w) */
-#define DMA2_MASK_REG		0xD4	/* single-channel mask (w) */
-#define DMA2_MODE_REG		0xD6	/* mode register (w) */
-#define DMA2_CLEAR_FF_REG	0xD8	/* clear pointer flip-flop (w) */
-#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
-#define DMA2_RESET_REG		0xDA	/* Master Clear (w) */
-#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
-#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
-#define DMA2_EXT_MODE_REG	(0x400 | DMA2_MODE_REG)
-
-static __inline__ unsigned long claim_dma_lock(void)
-{
-	return 0;
-}
-
-static __inline__ void release_dma_lock(unsigned long flags)
-{
-}
-
-
-/* Get DMA residue count. After a DMA transfer, this
- * should return zero. Reading this while a DMA transfer is
- * still in progress will return unpredictable results.
- * If called before the channel has been used, it may return 1.
- * Otherwise, it returns the number of _bytes_ left to transfer.
- *
- * Assumes DMA flip-flop is clear.
- */
-static __inline__ int get_dma_residue(unsigned int dmanr)
-{
-	unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
-					 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
-
-	/* using short to get 16-bit wrap around */
-	unsigned short count;
-
-	count = 1 + dma_inb(io_port);
-	count += dma_inb(io_port) << 8;
-	
-	return (dmanr<=3)? count : (count<<1);
-}
-
-/* enable/disable a specific DMA channel */
-static __inline__ void enable_dma(unsigned int dmanr)
-{
-#ifdef CONFIG_SUPERIO
-	if (dmanr<=3)
-		dma_outb(dmanr,  DMA1_MASK_REG);
-	else
-		dma_outb(dmanr & 3,  DMA2_MASK_REG);
-#endif
-}
-
-static __inline__ void disable_dma(unsigned int dmanr)
-{
-#ifdef CONFIG_SUPERIO
-	if (dmanr<=3)
-		dma_outb(dmanr | 4,  DMA1_MASK_REG);
-	else
-		dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
-#endif
-}
-
-/* reserve a DMA channel */
-#define request_dma(dmanr, device_id)	(0)
-
-/* Clear the 'DMA Pointer Flip Flop'.
- * Write 0 for LSB/MSB, 1 for MSB/LSB access.
- * Use this once to initialize the FF to a known state.
- * After that, keep track of it. :-)
- * --- In order to do that, the DMA routines below should ---
- * --- only be used while holding the DMA lock ! ---
- */
-static __inline__ void clear_dma_ff(unsigned int dmanr)
-{
-}
-
-/* set mode (above) for a specific DMA channel */
-static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
-{
-}
-
-/* Set only the page register bits of the transfer address.
- * This is used for successive transfers when we know the contents of
- * the lower 16 bits of the DMA current address register, but a 64k boundary
- * may have been crossed.
- */
-static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
-{
-}
-
-
-/* Set transfer address & page bits for specific DMA channel.
- * Assumes dma flipflop is clear.
- */
-static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
-{
-}
-
-
-/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
- * a specific DMA channel.
- * You must ensure the parameters are valid.
- * NOTE: from a manual: "the number of transfers is one more
- * than the initial word count"! This is taken into account.
- * Assumes dma flip-flop is clear.
- * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
- */
-static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
-{
-}
-
-
-#define free_dma(dmanr)
-
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy 	(0)
-#endif
-
-#endif /* _ASM_DMA_H */
diff --git a/include/asm-parisc/eisa_bus.h b/include/asm-parisc/eisa_bus.h
deleted file mode 100644
index 201085f83dd5..000000000000
--- a/include/asm-parisc/eisa_bus.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * eisa_bus.h interface between the eisa BA driver and the bus enumerator
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * Copyright (c) 2002 Daniel Engstrom <5116@telia.com>
- *
- */
-
-#ifndef ASM_EISA_H
-#define ASM_EISA_H
-
-extern void eisa_make_irq_level(int num);
-extern void eisa_make_irq_edge(int num);
-extern int eisa_enumerator(unsigned long eeprom_addr,
-			   struct resource *io_parent, 
-			   struct resource *mem_parent);
-extern int eisa_eeprom_init(unsigned long addr);
-
-#endif
diff --git a/include/asm-parisc/eisa_eeprom.h b/include/asm-parisc/eisa_eeprom.h
deleted file mode 100644
index 9c9da980402a..000000000000
--- a/include/asm-parisc/eisa_eeprom.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * eisa_eeprom.h - provide support for EISA adapters in PA-RISC machines
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * Copyright (c) 2001, 2002 Daniel Engstrom <5116@telia.com>
- *
- */
-
-#ifndef ASM_EISA_EEPROM_H
-#define ASM_EISA_EEPROM_H
-
-extern void __iomem *eisa_eeprom_addr;
-
-#define HPEE_MAX_LENGTH       0x2000	/* maximum eeprom length */
-
-#define HPEE_SLOT_INFO(slot) (20+(48*slot))
-
-struct eeprom_header 
-{
-   
-	u_int32_t num_writes;       /* number of writes */
- 	u_int8_t  flags;            /* flags, usage? */
-	u_int8_t  ver_maj;
-	u_int8_t  ver_min;
-	u_int8_t  num_slots;        /* number of EISA slots in system */
-	u_int16_t csum;             /* checksum, I don't know how to calulate this */
-	u_int8_t  pad[10];
-} __attribute__ ((packed));
-
-
-struct eeprom_eisa_slot_info
-{
-	u_int32_t eisa_slot_id;
-	u_int32_t config_data_offset;
-	u_int32_t num_writes;
-	u_int16_t csum;
-	u_int16_t num_functions;
-	u_int16_t config_data_length;
-	
-	/* bits 0..3 are the duplicate slot id */ 
-#define HPEE_SLOT_INFO_EMBEDDED  0x10
-#define HPEE_SLOT_INFO_VIRTUAL   0x20
-#define HPEE_SLOT_INFO_NO_READID 0x40
-#define HPEE_SLOT_INFO_DUPLICATE 0x80
-	u_int8_t slot_info;
-	
-#define HPEE_SLOT_FEATURES_ENABLE         0x01
-#define HPEE_SLOT_FEATURES_IOCHK          0x02
-#define HPEE_SLOT_FEATURES_CFG_INCOMPLETE 0x80
-	u_int8_t slot_features;
-	
-	u_int8_t  ver_min;
-	u_int8_t  ver_maj;
-	
-#define HPEE_FUNCTION_INFO_HAVE_TYPE      0x01
-#define HPEE_FUNCTION_INFO_HAVE_MEMORY    0x02
-#define HPEE_FUNCTION_INFO_HAVE_IRQ       0x04
-#define HPEE_FUNCTION_INFO_HAVE_DMA       0x08
-#define HPEE_FUNCTION_INFO_HAVE_PORT      0x10
-#define HPEE_FUNCTION_INFO_HAVE_PORT_INIT 0x20
-/* I think there are two slighty different 
- * versions of the function_info field 
- * one int the fixed header and one optional 
- * in the parsed slot data area */
-#define HPEE_FUNCTION_INFO_HAVE_FUNCTION  0x01
-#define HPEE_FUNCTION_INFO_F_DISABLED     0x80
-#define HPEE_FUNCTION_INFO_CFG_FREE_FORM  0x40
-	u_int8_t  function_info;
-
-#define HPEE_FLAG_BOARD_IS_ISA		  0x01 /* flag and minor version for isa board */
-	u_int8_t  flags;
-	u_int8_t  pad[24];
-} __attribute__ ((packed));
-
-
-#define HPEE_MEMORY_MAX_ENT   9
-/* memory descriptor: byte 0 */
-#define HPEE_MEMORY_WRITABLE  0x01
-#define HPEE_MEMORY_CACHABLE  0x02
-#define HPEE_MEMORY_TYPE_MASK 0x18
-#define HPEE_MEMORY_TYPE_SYS  0x00
-#define HPEE_MEMORY_TYPE_EXP  0x08
-#define HPEE_MEMORY_TYPE_VIR  0x10
-#define HPEE_MEMORY_TYPE_OTH  0x18
-#define HPEE_MEMORY_SHARED    0x20
-#define HPEE_MEMORY_MORE      0x80
-
-/* memory descriptor: byte 1 */
-#define HPEE_MEMORY_WIDTH_MASK 0x03
-#define HPEE_MEMORY_WIDTH_BYTE 0x00
-#define HPEE_MEMORY_WIDTH_WORD 0x01
-#define HPEE_MEMORY_WIDTH_DWORD 0x02
-#define HPEE_MEMORY_DECODE_MASK 0x0c
-#define HPEE_MEMORY_DECODE_20BITS 0x00
-#define HPEE_MEMORY_DECODE_24BITS 0x04
-#define HPEE_MEMORY_DECODE_32BITS 0x08
-/* byte 2 and 3 are a 16bit LE value
- * containging the memory size in kilobytes */
-/* byte 4,5,6 are a 24bit LE value
- * containing the memory base address */
-
-
-#define HPEE_IRQ_MAX_ENT      7
-/* Interrupt entry: byte 0 */
-#define HPEE_IRQ_CHANNEL_MASK 0xf
-#define HPEE_IRQ_TRIG_LEVEL   0x20
-#define HPEE_IRQ_MORE         0x80
-/* byte 1 seems to be unused */
-
-#define HPEE_DMA_MAX_ENT     4
-
-/* dma entry: byte 0 */
-#define HPEE_DMA_CHANNEL_MASK 7
-#define HPEE_DMA_SIZE_MASK	0xc
-#define HPEE_DMA_SIZE_BYTE	0x0
-#define HPEE_DMA_SIZE_WORD	0x4
-#define HPEE_DMA_SIZE_DWORD	0x8
-#define HPEE_DMA_SHARED      0x40
-#define HPEE_DMA_MORE        0x80
-
-/* dma entry: byte 1 */
-#define HPEE_DMA_TIMING_MASK 0x30
-#define HPEE_DMA_TIMING_ISA	0x0
-#define HPEE_DMA_TIMING_TYPEA 0x10
-#define HPEE_DMA_TIMING_TYPEB 0x20
-#define HPEE_DMA_TIMING_TYPEC 0x30
-
-#define HPEE_PORT_MAX_ENT 20
-/* port entry byte 0 */
-#define HPEE_PORT_SIZE_MASK 0x1f
-#define HPEE_PORT_SHARED    0x40
-#define HPEE_PORT_MORE      0x80
-/* byte 1 and 2 is a 16bit LE value
- * conating the start port number */
-
-#define HPEE_PORT_INIT_MAX_LEN     60 /* in bytes here */
-/* port init entry byte 0 */
-#define HPEE_PORT_INIT_WIDTH_MASK  0x3
-#define HPEE_PORT_INIT_WIDTH_BYTE  0x0
-#define HPEE_PORT_INIT_WIDTH_WORD  0x1
-#define HPEE_PORT_INIT_WIDTH_DWORD 0x2
-#define HPEE_PORT_INIT_MASK        0x4
-#define HPEE_PORT_INIT_MORE        0x80
-
-#define HPEE_SELECTION_MAX_ENT 26
-
-#define HPEE_TYPE_MAX_LEN    80
-
-#endif
diff --git a/include/asm-parisc/elf.h b/include/asm-parisc/elf.h
deleted file mode 100644
index d0a4a8262818..000000000000
--- a/include/asm-parisc/elf.h
+++ /dev/null
@@ -1,342 +0,0 @@
-#ifndef __ASMPARISC_ELF_H
-#define __ASMPARISC_ELF_H
-
-/*
- * ELF register definitions..
- */
-
-#include <asm/ptrace.h>
-
-#define EM_PARISC 15
-
-/* HPPA specific definitions.  */
-
-/* Legal values for e_flags field of Elf32_Ehdr.  */
-
-#define EF_PARISC_TRAPNIL	0x00010000 /* Trap nil pointer dereference.  */
-#define EF_PARISC_EXT		0x00020000 /* Program uses arch. extensions. */
-#define EF_PARISC_LSB		0x00040000 /* Program expects little endian. */
-#define EF_PARISC_WIDE		0x00080000 /* Program expects wide mode.  */
-#define EF_PARISC_NO_KABP	0x00100000 /* No kernel assisted branch
-					      prediction.  */
-#define EF_PARISC_LAZYSWAP	0x00400000 /* Allow lazy swapping.  */
-#define EF_PARISC_ARCH		0x0000ffff /* Architecture version.  */
-
-/* Defined values for `e_flags & EF_PARISC_ARCH' are:  */
-
-#define EFA_PARISC_1_0		    0x020b /* PA-RISC 1.0 big-endian.  */
-#define EFA_PARISC_1_1		    0x0210 /* PA-RISC 1.1 big-endian.  */
-#define EFA_PARISC_2_0		    0x0214 /* PA-RISC 2.0 big-endian.  */
-
-/* Additional section indices.  */
-
-#define SHN_PARISC_ANSI_COMMON	0xff00	   /* Section for tenatively declared
-					      symbols in ANSI C.  */
-#define SHN_PARISC_HUGE_COMMON	0xff01	   /* Common blocks in huge model.  */
-
-/* Legal values for sh_type field of Elf32_Shdr.  */
-
-#define SHT_PARISC_EXT		0x70000000 /* Contains product specific ext. */
-#define SHT_PARISC_UNWIND	0x70000001 /* Unwind information.  */
-#define SHT_PARISC_DOC		0x70000002 /* Debug info for optimized code. */
-
-/* Legal values for sh_flags field of Elf32_Shdr.  */
-
-#define SHF_PARISC_SHORT	0x20000000 /* Section with short addressing. */
-#define SHF_PARISC_HUGE		0x40000000 /* Section far from gp.  */
-#define SHF_PARISC_SBP		0x80000000 /* Static branch prediction code. */
-
-/* Legal values for ST_TYPE subfield of st_info (symbol type).  */
-
-#define STT_PARISC_MILLICODE	13	/* Millicode function entry point.  */
-
-#define STT_HP_OPAQUE		(STT_LOOS + 0x1)
-#define STT_HP_STUB		(STT_LOOS + 0x2)
-
-/* HPPA relocs.  */
-
-#define R_PARISC_NONE		0	/* No reloc.  */
-#define R_PARISC_DIR32		1	/* Direct 32-bit reference.  */
-#define R_PARISC_DIR21L		2	/* Left 21 bits of eff. address.  */
-#define R_PARISC_DIR17R		3	/* Right 17 bits of eff. address.  */
-#define R_PARISC_DIR17F		4	/* 17 bits of eff. address.  */
-#define R_PARISC_DIR14R		6	/* Right 14 bits of eff. address.  */
-#define R_PARISC_PCREL32	9	/* 32-bit rel. address.  */
-#define R_PARISC_PCREL21L	10	/* Left 21 bits of rel. address.  */
-#define R_PARISC_PCREL17R	11	/* Right 17 bits of rel. address.  */
-#define R_PARISC_PCREL17F	12	/* 17 bits of rel. address.  */
-#define R_PARISC_PCREL14R	14	/* Right 14 bits of rel. address.  */
-#define R_PARISC_DPREL21L	18	/* Left 21 bits of rel. address.  */
-#define R_PARISC_DPREL14R	22	/* Right 14 bits of rel. address.  */
-#define R_PARISC_GPREL21L	26	/* GP-relative, left 21 bits.  */
-#define R_PARISC_GPREL14R	30	/* GP-relative, right 14 bits.  */
-#define R_PARISC_LTOFF21L	34	/* LT-relative, left 21 bits.  */
-#define R_PARISC_LTOFF14R	38	/* LT-relative, right 14 bits.  */
-#define R_PARISC_SECREL32	41	/* 32 bits section rel. address.  */
-#define R_PARISC_SEGBASE	48	/* No relocation, set segment base.  */
-#define R_PARISC_SEGREL32	49	/* 32 bits segment rel. address.  */
-#define R_PARISC_PLTOFF21L	50	/* PLT rel. address, left 21 bits.  */
-#define R_PARISC_PLTOFF14R	54	/* PLT rel. address, right 14 bits.  */
-#define R_PARISC_LTOFF_FPTR32	57	/* 32 bits LT-rel. function pointer. */
-#define R_PARISC_LTOFF_FPTR21L	58	/* LT-rel. fct ptr, left 21 bits. */
-#define R_PARISC_LTOFF_FPTR14R	62	/* LT-rel. fct ptr, right 14 bits. */
-#define R_PARISC_FPTR64		64	/* 64 bits function address.  */
-#define R_PARISC_PLABEL32	65	/* 32 bits function address.  */
-#define R_PARISC_PCREL64	72	/* 64 bits PC-rel. address.  */
-#define R_PARISC_PCREL22F	74	/* 22 bits PC-rel. address.  */
-#define R_PARISC_PCREL14WR	75	/* PC-rel. address, right 14 bits.  */
-#define R_PARISC_PCREL14DR	76	/* PC rel. address, right 14 bits.  */
-#define R_PARISC_PCREL16F	77	/* 16 bits PC-rel. address.  */
-#define R_PARISC_PCREL16WF	78	/* 16 bits PC-rel. address.  */
-#define R_PARISC_PCREL16DF	79	/* 16 bits PC-rel. address.  */
-#define R_PARISC_DIR64		80	/* 64 bits of eff. address.  */
-#define R_PARISC_DIR14WR	83	/* 14 bits of eff. address.  */
-#define R_PARISC_DIR14DR	84	/* 14 bits of eff. address.  */
-#define R_PARISC_DIR16F		85	/* 16 bits of eff. address.  */
-#define R_PARISC_DIR16WF	86	/* 16 bits of eff. address.  */
-#define R_PARISC_DIR16DF	87	/* 16 bits of eff. address.  */
-#define R_PARISC_GPREL64	88	/* 64 bits of GP-rel. address.  */
-#define R_PARISC_GPREL14WR	91	/* GP-rel. address, right 14 bits.  */
-#define R_PARISC_GPREL14DR	92	/* GP-rel. address, right 14 bits.  */
-#define R_PARISC_GPREL16F	93	/* 16 bits GP-rel. address.  */
-#define R_PARISC_GPREL16WF	94	/* 16 bits GP-rel. address.  */
-#define R_PARISC_GPREL16DF	95	/* 16 bits GP-rel. address.  */
-#define R_PARISC_LTOFF64	96	/* 64 bits LT-rel. address.  */
-#define R_PARISC_LTOFF14WR	99	/* LT-rel. address, right 14 bits.  */
-#define R_PARISC_LTOFF14DR	100	/* LT-rel. address, right 14 bits.  */
-#define R_PARISC_LTOFF16F	101	/* 16 bits LT-rel. address.  */
-#define R_PARISC_LTOFF16WF	102	/* 16 bits LT-rel. address.  */
-#define R_PARISC_LTOFF16DF	103	/* 16 bits LT-rel. address.  */
-#define R_PARISC_SECREL64	104	/* 64 bits section rel. address.  */
-#define R_PARISC_SEGREL64	112	/* 64 bits segment rel. address.  */
-#define R_PARISC_PLTOFF14WR	115	/* PLT-rel. address, right 14 bits.  */
-#define R_PARISC_PLTOFF14DR	116	/* PLT-rel. address, right 14 bits.  */
-#define R_PARISC_PLTOFF16F	117	/* 16 bits LT-rel. address.  */
-#define R_PARISC_PLTOFF16WF	118	/* 16 bits PLT-rel. address.  */
-#define R_PARISC_PLTOFF16DF	119	/* 16 bits PLT-rel. address.  */
-#define R_PARISC_LTOFF_FPTR64	120	/* 64 bits LT-rel. function ptr.  */
-#define R_PARISC_LTOFF_FPTR14WR	123	/* LT-rel. fct. ptr., right 14 bits. */
-#define R_PARISC_LTOFF_FPTR14DR	124	/* LT-rel. fct. ptr., right 14 bits. */
-#define R_PARISC_LTOFF_FPTR16F	125	/* 16 bits LT-rel. function ptr.  */
-#define R_PARISC_LTOFF_FPTR16WF	126	/* 16 bits LT-rel. function ptr.  */
-#define R_PARISC_LTOFF_FPTR16DF	127	/* 16 bits LT-rel. function ptr.  */
-#define R_PARISC_LORESERVE	128
-#define R_PARISC_COPY		128	/* Copy relocation.  */
-#define R_PARISC_IPLT		129	/* Dynamic reloc, imported PLT */
-#define R_PARISC_EPLT		130	/* Dynamic reloc, exported PLT */
-#define R_PARISC_TPREL32	153	/* 32 bits TP-rel. address.  */
-#define R_PARISC_TPREL21L	154	/* TP-rel. address, left 21 bits.  */
-#define R_PARISC_TPREL14R	158	/* TP-rel. address, right 14 bits.  */
-#define R_PARISC_LTOFF_TP21L	162	/* LT-TP-rel. address, left 21 bits. */
-#define R_PARISC_LTOFF_TP14R	166	/* LT-TP-rel. address, right 14 bits.*/
-#define R_PARISC_LTOFF_TP14F	167	/* 14 bits LT-TP-rel. address.  */
-#define R_PARISC_TPREL64	216	/* 64 bits TP-rel. address.  */
-#define R_PARISC_TPREL14WR	219	/* TP-rel. address, right 14 bits.  */
-#define R_PARISC_TPREL14DR	220	/* TP-rel. address, right 14 bits.  */
-#define R_PARISC_TPREL16F	221	/* 16 bits TP-rel. address.  */
-#define R_PARISC_TPREL16WF	222	/* 16 bits TP-rel. address.  */
-#define R_PARISC_TPREL16DF	223	/* 16 bits TP-rel. address.  */
-#define R_PARISC_LTOFF_TP64	224	/* 64 bits LT-TP-rel. address.  */
-#define R_PARISC_LTOFF_TP14WR	227	/* LT-TP-rel. address, right 14 bits.*/
-#define R_PARISC_LTOFF_TP14DR	228	/* LT-TP-rel. address, right 14 bits.*/
-#define R_PARISC_LTOFF_TP16F	229	/* 16 bits LT-TP-rel. address.  */
-#define R_PARISC_LTOFF_TP16WF	230	/* 16 bits LT-TP-rel. address.  */
-#define R_PARISC_LTOFF_TP16DF	231	/* 16 bits LT-TP-rel. address.  */
-#define R_PARISC_HIRESERVE	255
-
-#define PA_PLABEL_FDESC		0x02	/* bit set if PLABEL points to
-					 * a function descriptor, not
-					 * an address */
-
-/* The following are PA function descriptors 
- *
- * addr:	the absolute address of the function
- * gp:		either the data pointer (r27) for non-PIC code or the
- *		the PLT pointer (r19) for PIC code */
-
-/* Format for the Elf32 Function descriptor */
-typedef struct elf32_fdesc {
-	__u32	addr;
-	__u32	gp;
-} Elf32_Fdesc;
-
-/* Format for the Elf64 Function descriptor */
-typedef struct elf64_fdesc {
-	__u64	dummy[2]; /* FIXME: nothing uses these, why waste
-			   * the space */
-	__u64	addr;
-	__u64	gp;
-} Elf64_Fdesc;
-
-/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr.  */
-
-#define PT_HP_TLS		(PT_LOOS + 0x0)
-#define PT_HP_CORE_NONE		(PT_LOOS + 0x1)
-#define PT_HP_CORE_VERSION	(PT_LOOS + 0x2)
-#define PT_HP_CORE_KERNEL	(PT_LOOS + 0x3)
-#define PT_HP_CORE_COMM		(PT_LOOS + 0x4)
-#define PT_HP_CORE_PROC		(PT_LOOS + 0x5)
-#define PT_HP_CORE_LOADABLE	(PT_LOOS + 0x6)
-#define PT_HP_CORE_STACK	(PT_LOOS + 0x7)
-#define PT_HP_CORE_SHM		(PT_LOOS + 0x8)
-#define PT_HP_CORE_MMF		(PT_LOOS + 0x9)
-#define PT_HP_PARALLEL		(PT_LOOS + 0x10)
-#define PT_HP_FASTBIND		(PT_LOOS + 0x11)
-#define PT_HP_OPT_ANNOT		(PT_LOOS + 0x12)
-#define PT_HP_HSL_ANNOT		(PT_LOOS + 0x13)
-#define PT_HP_STACK		(PT_LOOS + 0x14)
-
-#define PT_PARISC_ARCHEXT	0x70000000
-#define PT_PARISC_UNWIND	0x70000001
-
-/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr.  */
-
-#define PF_PARISC_SBP		0x08000000
-
-#define PF_HP_PAGE_SIZE		0x00100000
-#define PF_HP_FAR_SHARED	0x00200000
-#define PF_HP_NEAR_SHARED	0x00400000
-#define PF_HP_CODE		0x01000000
-#define PF_HP_MODIFY		0x02000000
-#define PF_HP_LAZYSWAP		0x04000000
-#define PF_HP_SBP		0x08000000
-
-/*
- * The following definitions are those for 32-bit ELF binaries on a 32-bit
- * kernel and for 64-bit binaries on a 64-bit kernel.  To run 32-bit binaries
- * on a 64-bit kernel, arch/parisc/kernel/binfmt_elf32.c defines these
- * macros appropriately and then #includes binfmt_elf.c, which then includes
- * this file.
- */
-#ifndef ELF_CLASS
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- *
- * Note that this header file is used by default in fs/binfmt_elf.c. So
- * the following macros are for the default case. However, for the 64
- * bit kernel we also support 32 bit parisc binaries. To do that
- * arch/parisc/kernel/binfmt_elf32.c defines its own set of these
- * macros, and then it includes fs/binfmt_elf.c to provide an alternate
- * elf binary handler for 32 bit binaries (on the 64 bit kernel).
- */
-#ifdef CONFIG_64BIT
-#define ELF_CLASS   ELFCLASS64
-#else
-#define ELF_CLASS	ELFCLASS32
-#endif
-
-typedef unsigned long elf_greg_t;
-
-/*
- * This yields a string that ld.so will use to load implementation
- * specific libraries for optimization.  This is more specific in
- * intent than poking at uname or /proc/cpuinfo.
- */
-
-#define ELF_PLATFORM  ("PARISC\0")
-
-#define SET_PERSONALITY(ex, ibcs2) \
-	current->personality = PER_LINUX; \
-	current->thread.map_base = DEFAULT_MAP_BASE; \
-	current->thread.task_size = DEFAULT_TASK_SIZE \
-
-/*
- * Fill in general registers in a core dump.  This saves pretty
- * much the same registers as hp-ux, although in a different order.
- * Registers marked # below are not currently saved in pt_regs, so
- * we use their current values here.
- *
- * 	gr0..gr31
- * 	sr0..sr7
- * 	iaoq0..iaoq1
- * 	iasq0..iasq1
- * 	cr11 (sar)
- * 	cr19 (iir)
- * 	cr20 (isr)
- * 	cr21 (ior)
- *  #	cr22 (ipsw)
- *  #	cr0 (recovery counter)
- *  #	cr24..cr31 (temporary registers)
- *  #	cr8,9,12,13 (protection IDs)
- *  #	cr10 (scr/ccr)
- *  #	cr15 (ext int enable mask)
- *
- */
-
-#define ELF_CORE_COPY_REGS(dst, pt)	\
-	memset(dst, 0, sizeof(dst));	/* don't leak any "random" bits */ \
-	memcpy(dst + 0, pt->gr, 32 * sizeof(elf_greg_t)); \
-	memcpy(dst + 32, pt->sr, 8 * sizeof(elf_greg_t)); \
-	memcpy(dst + 40, pt->iaoq, 2 * sizeof(elf_greg_t)); \
-	memcpy(dst + 42, pt->iasq, 2 * sizeof(elf_greg_t)); \
-	dst[44] = pt->sar;   dst[45] = pt->iir; \
-	dst[46] = pt->isr;   dst[47] = pt->ior; \
-	dst[48] = mfctl(22); dst[49] = mfctl(0); \
-	dst[50] = mfctl(24); dst[51] = mfctl(25); \
-	dst[52] = mfctl(26); dst[53] = mfctl(27); \
-	dst[54] = mfctl(28); dst[55] = mfctl(29); \
-	dst[56] = mfctl(30); dst[57] = mfctl(31); \
-	dst[58] = mfctl( 8); dst[59] = mfctl( 9); \
-	dst[60] = mfctl(12); dst[61] = mfctl(13); \
-	dst[62] = mfctl(10); dst[63] = mfctl(15);
-
-#endif /* ! ELF_CLASS */
-
-#define ELF_NGREG 80	/* We only need 64 at present, but leave space
-			   for expansion. */
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-#define ELF_NFPREG 32
-typedef double elf_fpreg_t;
-typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
-
-struct task_struct;
-
-extern int dump_task_fpu (struct task_struct *, elf_fpregset_t *);
-#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
-
-struct pt_regs;	/* forward declaration... */
-
-
-#define elf_check_arch(x) ((x)->e_machine == EM_PARISC && (x)->e_ident[EI_CLASS] == ELF_CLASS)
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_DATA	ELFDATA2MSB
-#define ELF_ARCH	EM_PARISC
-#define ELF_OSABI 	ELFOSABI_LINUX
-
-/* %r23 is set by ld.so to a pointer to a function which might be 
-   registered using atexit.  This provides a means for the dynamic
-   linker to call DT_FINI functions for shared libraries that have
-   been loaded before the code runs.
-
-   So that we can use the same startup file with static executables,
-   we start programs with a value of 0 to indicate that there is no
-   such function.  */
-#define ELF_PLAT_INIT(_r, load_addr)       _r->gr[23] = 0
-
-#define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE	4096
-
-/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
-   use of this is to invoke "./ld.so someprog" to test out a new version of
-   the loader.  We need to make sure that it is out of the way of the program
-   that it will "exec", and that there is sufficient room for the brk.
-
-   (2 * TASK_SIZE / 3) turns into something undefined when run through a
-   32 bit preprocessor and in some cases results in the kernel trying to map
-   ld.so to the kernel virtual base. Use a sane value instead. /Jes 
-  */
-
-#define ELF_ET_DYN_BASE         (TASK_UNMAPPED_BASE + 0x01000000)
-
-/* This yields a mask that user programs can use to figure out what
-   instruction set this CPU supports.  This could be done in user space,
-   but it's not easy, and we've already done it here.  */
-
-#define ELF_HWCAP	0
-
-#endif
diff --git a/include/asm-parisc/emergency-restart.h b/include/asm-parisc/emergency-restart.h
deleted file mode 100644
index 108d8c48e42e..000000000000
--- a/include/asm-parisc/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_EMERGENCY_RESTART_H
-#define _ASM_EMERGENCY_RESTART_H
-
-#include <asm-generic/emergency-restart.h>
-
-#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-parisc/errno.h b/include/asm-parisc/errno.h
deleted file mode 100644
index e2f3ddc796be..000000000000
--- a/include/asm-parisc/errno.h
+++ /dev/null
@@ -1,124 +0,0 @@
-#ifndef _PARISC_ERRNO_H
-#define _PARISC_ERRNO_H
-
-#include <asm-generic/errno-base.h>
-
-#define	ENOMSG		35	/* No message of desired type */
-#define	EIDRM		36	/* Identifier removed */
-#define	ECHRNG		37	/* Channel number out of range */
-#define	EL2NSYNC	38	/* Level 2 not synchronized */
-#define	EL3HLT		39	/* Level 3 halted */
-#define	EL3RST		40	/* Level 3 reset */
-#define	ELNRNG		41	/* Link number out of range */
-#define	EUNATCH		42	/* Protocol driver not attached */
-#define	ENOCSI		43	/* No CSI structure available */
-#define	EL2HLT		44	/* Level 2 halted */
-#define	EDEADLK		45	/* Resource deadlock would occur */
-#define	EDEADLOCK	EDEADLK
-#define	ENOLCK		46	/* No record locks available */
-#define	EILSEQ		47	/* Illegal byte sequence */
-
-#define	ENONET		50	/* Machine is not on the network */
-#define	ENODATA		51	/* No data available */
-#define	ETIME		52	/* Timer expired */
-#define	ENOSR		53	/* Out of streams resources */
-#define	ENOSTR		54	/* Device not a stream */
-#define	ENOPKG		55	/* Package not installed */
-
-#define	ENOLINK		57	/* Link has been severed */
-#define	EADV		58	/* Advertise error */
-#define	ESRMNT		59	/* Srmount error */
-#define	ECOMM		60	/* Communication error on send */
-#define	EPROTO		61	/* Protocol error */
-
-#define	EMULTIHOP	64	/* Multihop attempted */
-
-#define	EDOTDOT		66	/* RFS specific error */
-#define	EBADMSG		67	/* Not a data message */
-#define	EUSERS		68	/* Too many users */
-#define	EDQUOT		69	/* Quota exceeded */
-#define	ESTALE		70	/* Stale NFS file handle */
-#define	EREMOTE		71	/* Object is remote */
-#define	EOVERFLOW	72	/* Value too large for defined data type */
-
-/* these errnos are defined by Linux but not HPUX. */
-
-#define	EBADE		160	/* Invalid exchange */
-#define	EBADR		161	/* Invalid request descriptor */
-#define	EXFULL		162	/* Exchange full */
-#define	ENOANO		163	/* No anode */
-#define	EBADRQC		164	/* Invalid request code */
-#define	EBADSLT		165	/* Invalid slot */
-#define	EBFONT		166	/* Bad font file format */
-#define	ENOTUNIQ	167	/* Name not unique on network */
-#define	EBADFD		168	/* File descriptor in bad state */
-#define	EREMCHG		169	/* Remote address changed */
-#define	ELIBACC		170	/* Can not access a needed shared library */
-#define	ELIBBAD		171	/* Accessing a corrupted shared library */
-#define	ELIBSCN		172	/* .lib section in a.out corrupted */
-#define	ELIBMAX		173	/* Attempting to link in too many shared libraries */
-#define	ELIBEXEC	174	/* Cannot exec a shared library directly */
-#define	ERESTART	175	/* Interrupted system call should be restarted */
-#define	ESTRPIPE	176	/* Streams pipe error */
-#define	EUCLEAN		177	/* Structure needs cleaning */
-#define	ENOTNAM		178	/* Not a XENIX named type file */
-#define	ENAVAIL		179	/* No XENIX semaphores available */
-#define	EISNAM		180	/* Is a named type file */
-#define	EREMOTEIO	181	/* Remote I/O error */
-#define	ENOMEDIUM	182	/* No medium found */
-#define	EMEDIUMTYPE	183	/* Wrong medium type */
-#define	ENOKEY		184	/* Required key not available */
-#define	EKEYEXPIRED	185	/* Key has expired */
-#define	EKEYREVOKED	186	/* Key has been revoked */
-#define	EKEYREJECTED	187	/* Key was rejected by service */
-
-/* We now return you to your regularly scheduled HPUX. */
-
-#define ENOSYM		215	/* symbol does not exist in executable */
-#define	ENOTSOCK	216	/* Socket operation on non-socket */
-#define	EDESTADDRREQ	217	/* Destination address required */
-#define	EMSGSIZE	218	/* Message too long */
-#define	EPROTOTYPE	219	/* Protocol wrong type for socket */
-#define	ENOPROTOOPT	220	/* Protocol not available */
-#define	EPROTONOSUPPORT	221	/* Protocol not supported */
-#define	ESOCKTNOSUPPORT	222	/* Socket type not supported */
-#define	EOPNOTSUPP	223	/* Operation not supported on transport endpoint */
-#define	EPFNOSUPPORT	224	/* Protocol family not supported */
-#define	EAFNOSUPPORT	225	/* Address family not supported by protocol */
-#define	EADDRINUSE	226	/* Address already in use */
-#define	EADDRNOTAVAIL	227	/* Cannot assign requested address */
-#define	ENETDOWN	228	/* Network is down */
-#define	ENETUNREACH	229	/* Network is unreachable */
-#define	ENETRESET	230	/* Network dropped connection because of reset */
-#define	ECONNABORTED	231	/* Software caused connection abort */
-#define	ECONNRESET	232	/* Connection reset by peer */
-#define	ENOBUFS		233	/* No buffer space available */
-#define	EISCONN		234	/* Transport endpoint is already connected */
-#define	ENOTCONN	235	/* Transport endpoint is not connected */
-#define	ESHUTDOWN	236	/* Cannot send after transport endpoint shutdown */
-#define	ETOOMANYREFS	237	/* Too many references: cannot splice */
-#define EREFUSED	ECONNREFUSED	/* for HP's NFS apparently */
-#define	ETIMEDOUT	238	/* Connection timed out */
-#define	ECONNREFUSED	239	/* Connection refused */
-#define EREMOTERELEASE	240	/* Remote peer released connection */
-#define	EHOSTDOWN	241	/* Host is down */
-#define	EHOSTUNREACH	242	/* No route to host */
-
-#define	EALREADY	244	/* Operation already in progress */
-#define	EINPROGRESS	245	/* Operation now in progress */
-#define	EWOULDBLOCK	246	/* Operation would block (Linux returns EAGAIN) */
-#define	ENOTEMPTY	247	/* Directory not empty */
-#define	ENAMETOOLONG	248	/* File name too long */
-#define	ELOOP		249	/* Too many symbolic links encountered */
-#define	ENOSYS		251	/* Function not implemented */
-
-#define ENOTSUP		252	/* Function not implemented (POSIX.4 / HPUX) */
-#define ECANCELLED	253	/* aio request was canceled before complete (POSIX.4 / HPUX) */
-#define ECANCELED	ECANCELLED	/* SuSv3 and Solaris wants one 'L' */
-
-/* for robust mutexes */
-#define EOWNERDEAD	254	/* Owner died */
-#define ENOTRECOVERABLE	255	/* State not recoverable */
-
-
-#endif
diff --git a/include/asm-parisc/fb.h b/include/asm-parisc/fb.h
deleted file mode 100644
index 4d503a023ab2..000000000000
--- a/include/asm-parisc/fb.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _ASM_FB_H_
-#define _ASM_FB_H_
-
-#include <linux/fb.h>
-#include <linux/fs.h>
-#include <asm/page.h>
-
-static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
-				unsigned long off)
-{
-	pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE;
-}
-
-static inline int fb_is_primary_device(struct fb_info *info)
-{
-	return 0;
-}
-
-#endif /* _ASM_FB_H_ */
diff --git a/include/asm-parisc/fcntl.h b/include/asm-parisc/fcntl.h
deleted file mode 100644
index 1e1c824764ee..000000000000
--- a/include/asm-parisc/fcntl.h
+++ /dev/null
@@ -1,39 +0,0 @@
-#ifndef _PARISC_FCNTL_H
-#define _PARISC_FCNTL_H
-
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_APPEND	000000010
-#define O_BLKSEEK	000000100 /* HPUX only */
-#define O_CREAT		000000400 /* not fcntl */
-#define O_EXCL		000002000 /* not fcntl */
-#define O_LARGEFILE	000004000
-#define O_SYNC		000100000
-#define O_NONBLOCK	000200004 /* HPUX has separate NDELAY & NONBLOCK */
-#define O_NOCTTY	000400000 /* not fcntl */
-#define O_DSYNC		001000000 /* HPUX only */
-#define O_RSYNC		002000000 /* HPUX only */
-#define O_NOATIME	004000000
-#define O_CLOEXEC	010000000 /* set close_on_exec */
-
-#define O_DIRECTORY	000010000 /* must be a directory */
-#define O_NOFOLLOW	000000200 /* don't follow links */
-#define O_INVISIBLE	004000000 /* invisible I/O, for DMAPI/XDSM */
-
-#define F_GETLK64	8
-#define F_SETLK64	9
-#define F_SETLKW64	10
-
-#define F_GETOWN	11	/*  for sockets. */
-#define F_SETOWN	12	/*  for sockets. */
-#define F_SETSIG	13	/*  for sockets. */
-#define F_GETSIG	14	/*  for sockets. */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK		01
-#define F_WRLCK		02
-#define F_UNLCK		03
-
-#include <asm-generic/fcntl.h>
-
-#endif
diff --git a/include/asm-parisc/fixmap.h b/include/asm-parisc/fixmap.h
deleted file mode 100644
index de3fe3a18229..000000000000
--- a/include/asm-parisc/fixmap.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef _ASM_FIXMAP_H
-#define _ASM_FIXMAP_H
-
-/*
- * This file defines the locations of the fixed mappings on parisc.
- *
- * All of the values in this file are machine virtual addresses.
- *
- * All of the values in this file must be <4GB (because of assembly
- * loading restrictions).  If you place this region anywhere above
- * __PAGE_OFFSET, you must adjust the memory map accordingly */
-
-/* The alias region is used in kernel space to do copy/clear to or
- * from areas congruently mapped with user space.  It is 8MB large
- * and must be 16MB aligned */
-#define TMPALIAS_MAP_START	((__PAGE_OFFSET) - 16*1024*1024)
-/* This is the kernel area for all maps (vmalloc, dma etc.)  most
- * usually, it extends up to TMPALIAS_MAP_START.  Virtual addresses
- * 0..GATEWAY_PAGE_SIZE are reserved for the gateway page */
-#define KERNEL_MAP_START	(GATEWAY_PAGE_SIZE)
-#define KERNEL_MAP_END		(TMPALIAS_MAP_START)
-
-#ifndef __ASSEMBLY__
-extern void *vmalloc_start;
-#define PCXL_DMA_MAP_SIZE	(8*1024*1024)
-#define VMALLOC_START		((unsigned long)vmalloc_start)
-#define VMALLOC_END		(KERNEL_MAP_END)
-#endif /*__ASSEMBLY__*/
-
-#endif /*_ASM_FIXMAP_H*/
diff --git a/include/asm-parisc/floppy.h b/include/asm-parisc/floppy.h
deleted file mode 100644
index 4ca69f558fae..000000000000
--- a/include/asm-parisc/floppy.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/*    Architecture specific parts of the Floppy driver
- *
- *    Linux/PA-RISC Project (http://www.parisc-linux.org/)
- *    Copyright (C) 2000 Matthew Wilcox (willy a debian . org)
- *    Copyright (C) 2000 Dave Kennedy
- *
- *    This program is free software; you can redistribute it and/or modify
- *    it under the terms of the GNU General Public License as published by
- *    the Free Software Foundation; either version 2 of the License, or
- *    (at your option) any later version.
- *
- *    This program is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *    GNU General Public License for more details.
- *
- *    You should have received a copy of the GNU General Public License
- *    along with this program; if not, write to the Free Software
- *    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_PARISC_FLOPPY_H
-#define __ASM_PARISC_FLOPPY_H
-
-#include <linux/vmalloc.h>
-
-
-/*
- * The DMA channel used by the floppy controller cannot access data at
- * addresses >= 16MB
- *
- * Went back to the 1MB limit, as some people had problems with the floppy
- * driver otherwise. It doesn't matter much for performance anyway, as most
- * floppy accesses go through the track buffer.
- */
-#define _CROSS_64KB(a,s,vdma) \
-(!vdma && ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64))
-
-#define CROSS_64KB(a,s) _CROSS_64KB(a,s,use_virtual_dma & 1)
-
-
-#define SW fd_routine[use_virtual_dma&1]
-#define CSW fd_routine[can_use_virtual_dma & 1]
-
-
-#define fd_inb(port)			readb(port)
-#define fd_outb(value, port)		writeb(value, port)
-
-#define fd_request_dma()        CSW._request_dma(FLOPPY_DMA,"floppy")
-#define fd_free_dma()           CSW._free_dma(FLOPPY_DMA)
-#define fd_enable_irq()         enable_irq(FLOPPY_IRQ)
-#define fd_disable_irq()        disable_irq(FLOPPY_IRQ)
-#define fd_free_irq()		free_irq(FLOPPY_IRQ, NULL)
-#define fd_get_dma_residue()    SW._get_dma_residue(FLOPPY_DMA)
-#define fd_dma_mem_alloc(size)	SW._dma_mem_alloc(size)
-#define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io)
-
-#define FLOPPY_CAN_FALLBACK_ON_NODMA
-
-static int virtual_dma_count=0;
-static int virtual_dma_residue=0;
-static char *virtual_dma_addr=0;
-static int virtual_dma_mode=0;
-static int doing_pdma=0;
-
-static void floppy_hardint(int irq, void *dev_id, struct pt_regs * regs)
-{
-	register unsigned char st;
-
-#undef TRACE_FLPY_INT
-
-#ifdef TRACE_FLPY_INT
-	static int calls=0;
-	static int bytes=0;
-	static int dma_wait=0;
-#endif
-	if (!doing_pdma) {
-		floppy_interrupt(irq, dev_id, regs);
-		return;
-	}
-
-#ifdef TRACE_FLPY_INT
-	if(!calls)
-		bytes = virtual_dma_count;
-#endif
-
-	{
-		register int lcount;
-		register char *lptr = virtual_dma_addr;
-
-		for (lcount = virtual_dma_count; lcount; lcount--) {
-			st = fd_inb(virtual_dma_port+4) & 0xa0 ;
-			if (st != 0xa0) 
-				break;
-			if (virtual_dma_mode) {
-				fd_outb(*lptr, virtual_dma_port+5);
-			} else {
-				*lptr = fd_inb(virtual_dma_port+5);
-			}
-			lptr++;
-		}
-		virtual_dma_count = lcount;
-		virtual_dma_addr = lptr;
-		st = fd_inb(virtual_dma_port+4);
-	}
-
-#ifdef TRACE_FLPY_INT
-	calls++;
-#endif
-	if (st == 0x20)
-		return;
-	if (!(st & 0x20)) {
-		virtual_dma_residue += virtual_dma_count;
-		virtual_dma_count = 0;
-#ifdef TRACE_FLPY_INT
-		printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n", 
-		       virtual_dma_count, virtual_dma_residue, calls, bytes,
-		       dma_wait);
-		calls = 0;
-		dma_wait=0;
-#endif
-		doing_pdma = 0;
-		floppy_interrupt(irq, dev_id, regs);
-		return;
-	}
-#ifdef TRACE_FLPY_INT
-	if (!virtual_dma_count)
-		dma_wait++;
-#endif
-}
-
-static void fd_disable_dma(void)
-{
-	if(! (can_use_virtual_dma & 1))
-		disable_dma(FLOPPY_DMA);
-	doing_pdma = 0;
-	virtual_dma_residue += virtual_dma_count;
-	virtual_dma_count=0;
-}
-
-static int vdma_request_dma(unsigned int dmanr, const char * device_id)
-{
-	return 0;
-}
-
-static void vdma_nop(unsigned int dummy)
-{
-}
-
-
-static int vdma_get_dma_residue(unsigned int dummy)
-{
-	return virtual_dma_count + virtual_dma_residue;
-}
-
-
-static int fd_request_irq(void)
-{
-	if(can_use_virtual_dma)
-		return request_irq(FLOPPY_IRQ, floppy_hardint,
-				   IRQF_DISABLED, "floppy", NULL);
-	else
-		return request_irq(FLOPPY_IRQ, floppy_interrupt,
-				   IRQF_DISABLED, "floppy", NULL);
-}
-
-static unsigned long dma_mem_alloc(unsigned long size)
-{
-	return __get_dma_pages(GFP_KERNEL, get_order(size));
-}
-
-
-static unsigned long vdma_mem_alloc(unsigned long size)
-{
-	return (unsigned long) vmalloc(size);
-
-}
-
-#define nodma_mem_alloc(size) vdma_mem_alloc(size)
-
-static void _fd_dma_mem_free(unsigned long addr, unsigned long size)
-{
-	if((unsigned int) addr >= (unsigned int) high_memory)
-		return vfree((void *)addr);
-	else
-		free_pages(addr, get_order(size));		
-}
-
-#define fd_dma_mem_free(addr, size)  _fd_dma_mem_free(addr, size) 
-
-static void _fd_chose_dma_mode(char *addr, unsigned long size)
-{
-	if(can_use_virtual_dma == 2) {
-		if((unsigned int) addr >= (unsigned int) high_memory ||
-		   virt_to_bus(addr) >= 0x1000000 ||
-		   _CROSS_64KB(addr, size, 0))
-			use_virtual_dma = 1;
-		else
-			use_virtual_dma = 0;
-	} else {
-		use_virtual_dma = can_use_virtual_dma & 1;
-	}
-}
-
-#define fd_chose_dma_mode(addr, size) _fd_chose_dma_mode(addr, size)
-
-
-static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
-{
-	doing_pdma = 1;
-	virtual_dma_port = io;
-	virtual_dma_mode = (mode  == DMA_MODE_WRITE);
-	virtual_dma_addr = addr;
-	virtual_dma_count = size;
-	virtual_dma_residue = 0;
-	return 0;
-}
-
-static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
-{
-#ifdef FLOPPY_SANITY_CHECK
-	if (CROSS_64KB(addr, size)) {
-		printk("DMA crossing 64-K boundary %p-%p\n", addr, addr+size);
-		return -1;
-	}
-#endif
-	/* actual, physical DMA */
-	doing_pdma = 0;
-	clear_dma_ff(FLOPPY_DMA);
-	set_dma_mode(FLOPPY_DMA,mode);
-	set_dma_addr(FLOPPY_DMA,virt_to_bus(addr));
-	set_dma_count(FLOPPY_DMA,size);
-	enable_dma(FLOPPY_DMA);
-	return 0;
-}
-
-static struct fd_routine_l {
-	int (*_request_dma)(unsigned int dmanr, const char * device_id);
-	void (*_free_dma)(unsigned int dmanr);
-	int (*_get_dma_residue)(unsigned int dummy);
-	unsigned long (*_dma_mem_alloc) (unsigned long size);
-	int (*_dma_setup)(char *addr, unsigned long size, int mode, int io);
-} fd_routine[] = {
-	{
-		request_dma,
-		free_dma,
-		get_dma_residue,
-		dma_mem_alloc,
-		hard_dma_setup
-	},
-	{
-		vdma_request_dma,
-		vdma_nop,
-		vdma_get_dma_residue,
-		vdma_mem_alloc,
-		vdma_dma_setup
-	}
-};
-
-
-static int FDC1 = 0x3f0; /* Lies.  Floppy controller is memory mapped, not io mapped */
-static int FDC2 = -1;
-
-#define FLOPPY0_TYPE	0
-#define FLOPPY1_TYPE	0
-
-#define N_FDC 1
-#define N_DRIVE 8
-
-#define EXTRA_FLOPPY_PARAMS
-
-#endif /* __ASM_PARISC_FLOPPY_H */
diff --git a/include/asm-parisc/futex.h b/include/asm-parisc/futex.h
deleted file mode 100644
index 0c705c3a55ef..000000000000
--- a/include/asm-parisc/futex.h
+++ /dev/null
@@ -1,77 +0,0 @@
-#ifndef _ASM_PARISC_FUTEX_H
-#define _ASM_PARISC_FUTEX_H
-
-#ifdef __KERNEL__
-
-#include <linux/futex.h>
-#include <linux/uaccess.h>
-#include <asm/errno.h>
-
-static inline int
-futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
-{
-	int op = (encoded_op >> 28) & 7;
-	int cmp = (encoded_op >> 24) & 15;
-	int oparg = (encoded_op << 8) >> 20;
-	int cmparg = (encoded_op << 20) >> 20;
-	int oldval = 0, ret;
-	if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
-		oparg = 1 << oparg;
-
-	if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
-		return -EFAULT;
-
-	pagefault_disable();
-
-	switch (op) {
-	case FUTEX_OP_SET:
-	case FUTEX_OP_ADD:
-	case FUTEX_OP_OR:
-	case FUTEX_OP_ANDN:
-	case FUTEX_OP_XOR:
-	default:
-		ret = -ENOSYS;
-	}
-
-	pagefault_enable();
-
-	if (!ret) {
-		switch (cmp) {
-		case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
-		case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
-		case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
-		case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
-		case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
-		case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
-		default: ret = -ENOSYS;
-		}
-	}
-	return ret;
-}
-
-/* Non-atomic version */
-static inline int
-futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
-{
-	int err = 0;
-	int uval;
-
-	/* futex.c wants to do a cmpxchg_inatomic on kernel NULL, which is
-	 * our gateway page, and causes no end of trouble...
-	 */
-	if (segment_eq(KERNEL_DS, get_fs()) && !uaddr)
-		return -EFAULT;
-
-	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
-		return -EFAULT;
-
-	err = get_user(uval, uaddr);
-	if (err) return -EFAULT;
-	if (uval == oldval)
-		err = put_user(newval, uaddr);
-	if (err) return -EFAULT;
-	return uval;
-}
-
-#endif /*__KERNEL__*/
-#endif /*_ASM_PARISC_FUTEX_H*/
diff --git a/include/asm-parisc/grfioctl.h b/include/asm-parisc/grfioctl.h
deleted file mode 100644
index 671e06042b40..000000000000
--- a/include/asm-parisc/grfioctl.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*  Architecture specific parts of HP's STI (framebuffer) driver.
- *  Structures are HP-UX compatible for XFree86 usage.
- * 
- *    Linux/PA-RISC Project (http://www.parisc-linux.org/)
- *    Copyright (C) 2001 Helge Deller (deller a parisc-linux org)
- *
- *    This program is free software; you can redistribute it and/or modify
- *    it under the terms of the GNU General Public License as published by
- *    the Free Software Foundation; either version 2 of the License, or
- *    (at your option) any later version.
- *
- *    This program is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *    GNU General Public License for more details.
- *
- *    You should have received a copy of the GNU General Public License
- *    along with this program; if not, write to the Free Software
- *    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_PARISC_GRFIOCTL_H
-#define __ASM_PARISC_GRFIOCTL_H
-
-/* upper 32 bits of graphics id (HP/UX identifier) */
-
-#define GRFGATOR		8
-#define S9000_ID_S300		9
-#define GRFBOBCAT		9
-#define	GRFCATSEYE		9
-#define S9000_ID_98720		10
-#define GRFRBOX			10
-#define S9000_ID_98550		11
-#define GRFFIREEYE		11
-#define S9000_ID_A1096A		12
-#define GRFHYPERION		12
-#define S9000_ID_FRI		13
-#define S9000_ID_98730		14
-#define GRFDAVINCI		14
-#define S9000_ID_98705		0x26C08070	/* Tigershark */
-#define S9000_ID_98736		0x26D148AB
-#define S9000_ID_A1659A		0x26D1482A	/* CRX 8 plane color (=ELK) */
-#define S9000_ID_ELK		S9000_ID_A1659A
-#define S9000_ID_A1439A		0x26D148EE	/* CRX24 = CRX+ (24-plane color) */
-#define S9000_ID_A1924A		0x26D1488C	/* GRX gray-scale */
-#define S9000_ID_ELM		S9000_ID_A1924A
-#define S9000_ID_98765		0x27480DEF
-#define S9000_ID_ELK_768	0x27482101
-#define S9000_ID_STINGER	0x27A4A402
-#define S9000_ID_TIMBER		0x27F12392	/* Bushmaster (710) Graphics */
-#define S9000_ID_TOMCAT		0x27FCCB6D	/* dual-headed ELK (Dual CRX) */
-#define S9000_ID_ARTIST		0x2B4DED6D	/* Artist (Gecko/712 & 715) onboard Graphics */
-#define S9000_ID_HCRX		0x2BCB015A	/* Hyperdrive/Hyperbowl (A4071A) Graphics */
-#define CRX24_OVERLAY_PLANES	0x920825AA	/* Overlay planes on CRX24 */
-
-#define CRT_ID_ELK_1024		S9000_ID_ELK_768 /* Elk 1024x768  CRX */
-#define CRT_ID_ELK_1280		S9000_ID_A1659A	/* Elk 1280x1024 CRX */
-#define CRT_ID_ELK_1024DB	0x27849CA5      /* Elk 1024x768 double buffer */
-#define CRT_ID_ELK_GS		S9000_ID_A1924A	/* Elk 1280x1024 GreyScale    */
-#define CRT_ID_CRX24		S9000_ID_A1439A	/* Piranha */
-#define CRT_ID_VISUALIZE_EG	0x2D08C0A7      /* Graffiti, A4450A (built-in B132+/B160L) */
-#define CRT_ID_THUNDER		0x2F23E5FC      /* Thunder 1 VISUALIZE 48*/
-#define CRT_ID_THUNDER2		0x2F8D570E      /* Thunder 2 VISUALIZE 48 XP*/
-#define CRT_ID_HCRX		S9000_ID_HCRX	/* Hyperdrive HCRX */
-#define CRT_ID_CRX48Z		S9000_ID_STINGER /* Stinger */
-#define CRT_ID_DUAL_CRX		S9000_ID_TOMCAT	/* Tomcat */
-#define CRT_ID_PVRX		S9000_ID_98705	/* Tigershark */
-#define CRT_ID_TIMBER		S9000_ID_TIMBER	/* Timber (710 builtin) */
-#define CRT_ID_TVRX		S9000_ID_98765	/* TVRX (gto/falcon) */
-#define CRT_ID_ARTIST		S9000_ID_ARTIST	/* Artist */
-#define CRT_ID_SUMMIT		0x2FC1066B      /* Summit FX2, FX4, FX6 ... */
-#define CRT_ID_LEGO		0x35ACDA30	/* Lego FX5, FX10 ... */
-#define CRT_ID_PINNACLE		0x35ACDA16	/* Pinnacle FXe */ 
-
-/* structure for ioctl(GCDESCRIBE) */
-
-#define gaddr_t unsigned long	/* FIXME: PA2.0 (64bit) portable ? */
-
-struct	grf_fbinfo {
-	unsigned int	id;		/* upper 32 bits of graphics id */
-	unsigned int	mapsize;	/* mapped size of framebuffer */
-	unsigned int	dwidth, dlength;/* x and y sizes */
-	unsigned int	width, length;	/* total x and total y size */
-	unsigned int	xlen;		/* x pitch size */
-	unsigned int	bpp, bppu;	/* bits per pixel and used bpp */
-	unsigned int	npl, nplbytes;	/* # of planes and bytes per plane */
-	char		name[32];	/* name of the device (from ROM) */
-	unsigned int	attr;		/* attributes */
-	gaddr_t 	fbbase, regbase;/* framebuffer and register base addr */
-	gaddr_t		regions[6];	/* region bases */
-};
-
-#define	GCID		_IOR('G', 0, int)
-#define	GCON		_IO('G', 1)
-#define	GCOFF		_IO('G', 2)
-#define	GCAON		_IO('G', 3)
-#define	GCAOFF		_IO('G', 4)
-#define	GCMAP		_IOWR('G', 5, int)
-#define	GCUNMAP		_IOWR('G', 6, int)
-#define	GCMAP_HPUX	_IO('G', 5)
-#define	GCUNMAP_HPUX	_IO('G', 6)
-#define	GCLOCK		_IO('G', 7)
-#define	GCUNLOCK	_IO('G', 8)
-#define	GCLOCK_MINIMUM	_IO('G', 9)
-#define	GCUNLOCK_MINIMUM _IO('G', 10)
-#define	GCSTATIC_CMAP	_IO('G', 11)
-#define	GCVARIABLE_CMAP _IO('G', 12)
-#define GCTERM		_IOWR('G',20,int)	/* multi-headed Tomcat */ 
-#define GCDESCRIBE	_IOR('G', 21, struct grf_fbinfo)
-#define GCFASTLOCK	_IO('G', 26)
-
-#endif /* __ASM_PARISC_GRFIOCTL_H */
-
diff --git a/include/asm-parisc/hardirq.h b/include/asm-parisc/hardirq.h
deleted file mode 100644
index ce93133d5112..000000000000
--- a/include/asm-parisc/hardirq.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* hardirq.h: PA-RISC hard IRQ support.
- *
- * Copyright (C) 2001 Matthew Wilcox <matthew@wil.cx>
- *
- * The locking is really quite interesting.  There's a cpu-local
- * count of how many interrupts are being handled, and a global
- * lock.  An interrupt can only be serviced if the global lock
- * is free.  You can't be sure no more interrupts are being
- * serviced until you've acquired the lock and then checked
- * all the per-cpu interrupt counts are all zero.  It's a specialised
- * br_lock, and that's exactly how Sparc does it.  We don't because
- * it's more locking for us.  This way is lock-free in the interrupt path.
- */
-
-#ifndef _PARISC_HARDIRQ_H
-#define _PARISC_HARDIRQ_H
-
-#include <linux/threads.h>
-#include <linux/irq.h>
-
-typedef struct {
-	unsigned long __softirq_pending; /* set_bit is used on this */
-} ____cacheline_aligned irq_cpustat_t;
-
-#include <linux/irq_cpustat.h>	/* Standard mappings for irq_cpustat_t above */
-
-void ack_bad_irq(unsigned int irq);
-
-#endif /* _PARISC_HARDIRQ_H */
diff --git a/include/asm-parisc/hardware.h b/include/asm-parisc/hardware.h
deleted file mode 100644
index 4e9626836bab..000000000000
--- a/include/asm-parisc/hardware.h
+++ /dev/null
@@ -1,127 +0,0 @@
-#ifndef _PARISC_HARDWARE_H
-#define _PARISC_HARDWARE_H
-
-#include <linux/mod_devicetable.h>
-#include <asm/pdc.h>
-
-#define HWTYPE_ANY_ID		PA_HWTYPE_ANY_ID
-#define HVERSION_ANY_ID		PA_HVERSION_ANY_ID
-#define HVERSION_REV_ANY_ID	PA_HVERSION_REV_ANY_ID
-#define SVERSION_ANY_ID		PA_SVERSION_ANY_ID
-
-struct hp_hardware {
-	unsigned short	hw_type:5;	/* HPHW_xxx */
-	unsigned short	hversion;
-	unsigned long	sversion:28;
-	unsigned short	opt;
-	const char	name[80];	/* The hardware description */
-};
-
-struct parisc_device;
-
-enum cpu_type {
-	pcx	= 0, /* pa7000		pa 1.0  */
-	pcxs	= 1, /* pa7000		pa 1.1a */
-	pcxt	= 2, /* pa7100		pa 1.1b */
-	pcxt_	= 3, /* pa7200	(t')	pa 1.1c */
-	pcxl	= 4, /* pa7100lc	pa 1.1d */
-	pcxl2	= 5, /* pa7300lc	pa 1.1e */
-	pcxu	= 6, /* pa8000		pa 2.0  */
-	pcxu_	= 7, /* pa8200	(u+)	pa 2.0  */
-	pcxw	= 8, /* pa8500		pa 2.0  */
-	pcxw_	= 9, /* pa8600	(w+)	pa 2.0  */
-	pcxw2	= 10, /* pa8700		pa 2.0  */
-	mako	= 11, /* pa8800		pa 2.0  */
-	mako2	= 12  /* pa8900		pa 2.0  */
-};
-
-extern const char * const cpu_name_version[][2]; /* mapping from enum cpu_type to strings */
-
-struct parisc_driver;
-
-struct io_module {
-        volatile uint32_t nothing;		/* reg 0 */
-        volatile uint32_t io_eim;
-        volatile uint32_t io_dc_adata;
-        volatile uint32_t io_ii_cdata;
-        volatile uint32_t io_dma_link;		/* reg 4 */
-        volatile uint32_t io_dma_command;
-        volatile uint32_t io_dma_address;
-        volatile uint32_t io_dma_count;
-        volatile uint32_t io_flex;		/* reg 8 */
-        volatile uint32_t io_spa_address;
-        volatile uint32_t reserved1[2];
-        volatile uint32_t io_command;		/* reg 12 */
-        volatile uint32_t io_status;
-        volatile uint32_t io_control;
-        volatile uint32_t io_data;
-        volatile uint32_t reserved2;		/* reg 16 */
-        volatile uint32_t chain_addr;
-        volatile uint32_t sub_mask_clr;
-        volatile uint32_t reserved3[13];
-        volatile uint32_t undefined[480];
-        volatile uint32_t unpriv[512];
-};
-
-struct bc_module {
-        volatile uint32_t unused1[12];
-        volatile uint32_t io_command;
-        volatile uint32_t io_status;
-        volatile uint32_t io_control;
-        volatile uint32_t unused2[1];
-        volatile uint32_t io_err_resp;
-        volatile uint32_t io_err_info;
-        volatile uint32_t io_err_req;
-        volatile uint32_t unused3[11];
-        volatile uint32_t io_io_low;
-        volatile uint32_t io_io_high;
-};
-
-#define HPHW_NPROC     0 
-#define HPHW_MEMORY    1       
-#define HPHW_B_DMA     2
-#define HPHW_OBSOLETE  3
-#define HPHW_A_DMA     4
-#define HPHW_A_DIRECT  5
-#define HPHW_OTHER     6
-#define HPHW_BCPORT    7
-#define HPHW_CIO       8
-#define HPHW_CONSOLE   9
-#define HPHW_FIO       10
-#define HPHW_BA        11
-#define HPHW_IOA       12
-#define HPHW_BRIDGE    13
-#define HPHW_FABRIC    14
-#define HPHW_MC	       15
-#define HPHW_FAULTY    31
-
-
-/* hardware.c: */
-extern const char *parisc_hardware_description(struct parisc_device_id *id);
-extern enum cpu_type parisc_get_cpu_type(unsigned long hversion);
-
-struct pci_dev;
-
-/* drivers.c: */
-extern struct parisc_device *alloc_pa_dev(unsigned long hpa,
-		struct hardware_path *path);
-extern int register_parisc_device(struct parisc_device *dev);
-extern int register_parisc_driver(struct parisc_driver *driver);
-extern int count_parisc_driver(struct parisc_driver *driver);
-extern int unregister_parisc_driver(struct parisc_driver *driver);
-extern void walk_central_bus(void);
-extern const struct parisc_device *find_pa_parent_type(const struct parisc_device *, int);
-extern void print_parisc_devices(void);
-extern char *print_pa_hwpath(struct parisc_device *dev, char *path);
-extern char *print_pci_hwpath(struct pci_dev *dev, char *path);
-extern void get_pci_node_path(struct pci_dev *dev, struct hardware_path *path);
-extern void init_parisc_bus(void);
-extern struct device *hwpath_to_device(struct hardware_path *modpath);
-extern void device_to_hwpath(struct device *dev, struct hardware_path *path);
-
-
-/* inventory.c: */
-extern void do_memory_inventory(void);
-extern void do_device_inventory(void);
-
-#endif /* _PARISC_HARDWARE_H */
diff --git a/include/asm-parisc/hw_irq.h b/include/asm-parisc/hw_irq.h
deleted file mode 100644
index 6707f7df3921..000000000000
--- a/include/asm-parisc/hw_irq.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _ASM_HW_IRQ_H
-#define _ASM_HW_IRQ_H
-
-/*
- *	linux/include/asm/hw_irq.h
- */
-
-#endif
diff --git a/include/asm-parisc/ide.h b/include/asm-parisc/ide.h
deleted file mode 100644
index c246ef75017d..000000000000
--- a/include/asm-parisc/ide.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- *  linux/include/asm-parisc/ide.h
- *
- *  Copyright (C) 1994-1996  Linus Torvalds & authors
- */
-
-/*
- *  This file contains the PARISC architecture specific IDE code.
- */
-
-#ifndef __ASM_PARISC_IDE_H
-#define __ASM_PARISC_IDE_H
-
-#ifdef __KERNEL__
-
-#define ide_request_irq(irq,hand,flg,dev,id)	request_irq((irq),(hand),(flg),(dev),(id))
-#define ide_free_irq(irq,dev_id)		free_irq((irq), (dev_id))
-#define ide_request_region(from,extent,name)	request_region((from), (extent), (name))
-#define ide_release_region(from,extent)		release_region((from), (extent))
-/* Generic I/O and MEMIO string operations.  */
-
-#define __ide_insw	insw
-#define __ide_insl	insl
-#define __ide_outsw	outsw
-#define __ide_outsl	outsl
-
-static __inline__ void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
-{
-	while (count--) {
-		*(u16 *)addr = __raw_readw(port);
-		addr += 2;
-	}
-}
-
-static __inline__ void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
-{
-	while (count--) {
-		*(u32 *)addr = __raw_readl(port);
-		addr += 4;
-	}
-}
-
-static __inline__ void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
-{
-	while (count--) {
-		__raw_writew(*(u16 *)addr, port);
-		addr += 2;
-	}
-}
-
-static __inline__ void __ide_mm_outsl(void __iomem *port, void *addr, u32 count)
-{
-	while (count--) {
-		__raw_writel(*(u32 *)addr, port);
-		addr += 4;
-	}
-}
-
-#endif /* __KERNEL__ */
-
-#endif /* __ASM_PARISC_IDE_H */
diff --git a/include/asm-parisc/io.h b/include/asm-parisc/io.h
deleted file mode 100644
index 55ddb1842107..000000000000
--- a/include/asm-parisc/io.h
+++ /dev/null
@@ -1,293 +0,0 @@
-#ifndef _ASM_IO_H
-#define _ASM_IO_H
-
-#include <linux/types.h>
-#include <asm/pgtable.h>
-
-extern unsigned long parisc_vmerge_boundary;
-extern unsigned long parisc_vmerge_max_size;
-
-#define BIO_VMERGE_BOUNDARY	parisc_vmerge_boundary
-#define BIO_VMERGE_MAX_SIZE	parisc_vmerge_max_size
-
-#define virt_to_phys(a) ((unsigned long)__pa(a))
-#define phys_to_virt(a) __va(a)
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-
-static inline unsigned long isa_bus_to_virt(unsigned long addr) {
-	BUG();
-	return 0;
-}
-
-static inline unsigned long isa_virt_to_bus(void *addr) {
-	BUG();
-	return 0;
-}
-
-/*
- * Memory mapped I/O
- *
- * readX()/writeX() do byteswapping and take an ioremapped address
- * __raw_readX()/__raw_writeX() don't byteswap and take an ioremapped address.
- * gsc_*() don't byteswap and operate on physical addresses;
- *   eg dev->hpa or 0xfee00000.
- */
-
-static inline unsigned char gsc_readb(unsigned long addr)
-{
-	long flags;
-	unsigned char ret;
-
-	__asm__ __volatile__(
-	"	rsm	2,%0\n"
-	"	ldbx	0(%2),%1\n"
-	"	mtsm	%0\n"
-	: "=&r" (flags), "=r" (ret) : "r" (addr) );
-
-	return ret;
-}
-
-static inline unsigned short gsc_readw(unsigned long addr)
-{
-	long flags;
-	unsigned short ret;
-
-	__asm__ __volatile__(
-	"	rsm	2,%0\n"
-	"	ldhx	0(%2),%1\n"
-	"	mtsm	%0\n"
-	: "=&r" (flags), "=r" (ret) : "r" (addr) );
-
-	return ret;
-}
-
-static inline unsigned int gsc_readl(unsigned long addr)
-{
-	u32 ret;
-
-	__asm__ __volatile__(
-	"	ldwax	0(%1),%0\n"
-	: "=r" (ret) : "r" (addr) );
-
-	return ret;
-}
-
-static inline unsigned long long gsc_readq(unsigned long addr)
-{
-	unsigned long long ret;
-
-#ifdef CONFIG_64BIT
-	__asm__ __volatile__(
-	"	ldda	0(%1),%0\n"
-	:  "=r" (ret) : "r" (addr) );
-#else
-	/* two reads may have side effects.. */
-	ret = ((u64) gsc_readl(addr)) << 32;
-	ret |= gsc_readl(addr+4);
-#endif
-	return ret;
-}
-
-static inline void gsc_writeb(unsigned char val, unsigned long addr)
-{
-	long flags;
-	__asm__ __volatile__(
-	"	rsm	2,%0\n"
-	"	stbs	%1,0(%2)\n"
-	"	mtsm	%0\n"
-	: "=&r" (flags) :  "r" (val), "r" (addr) );
-}
-
-static inline void gsc_writew(unsigned short val, unsigned long addr)
-{
-	long flags;
-	__asm__ __volatile__(
-	"	rsm	2,%0\n"
-	"	sths	%1,0(%2)\n"
-	"	mtsm	%0\n"
-	: "=&r" (flags) :  "r" (val), "r" (addr) );
-}
-
-static inline void gsc_writel(unsigned int val, unsigned long addr)
-{
-	__asm__ __volatile__(
-	"	stwas	%0,0(%1)\n"
-	: :  "r" (val), "r" (addr) );
-}
-
-static inline void gsc_writeq(unsigned long long val, unsigned long addr)
-{
-#ifdef CONFIG_64BIT
-	__asm__ __volatile__(
-	"	stda	%0,0(%1)\n"
-	: :  "r" (val), "r" (addr) );
-#else
-	/* two writes may have side effects.. */
-	gsc_writel(val >> 32, addr);
-	gsc_writel(val, addr+4);
-#endif
-}
-
-/*
- * The standard PCI ioremap interfaces
- */
-
-extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
-
-/* Most machines react poorly to I/O-space being cacheable... Instead let's
- * define ioremap() in terms of ioremap_nocache().
- */
-static inline void __iomem * ioremap(unsigned long offset, unsigned long size)
-{
-	return __ioremap(offset, size, _PAGE_NO_CACHE);
-}
-#define ioremap_nocache(off, sz)	ioremap((off), (sz))
-
-extern void iounmap(const volatile void __iomem *addr);
-
-static inline unsigned char __raw_readb(const volatile void __iomem *addr)
-{
-	return (*(volatile unsigned char __force *) (addr));
-}
-static inline unsigned short __raw_readw(const volatile void __iomem *addr)
-{
-	return *(volatile unsigned short __force *) addr;
-}
-static inline unsigned int __raw_readl(const volatile void __iomem *addr)
-{
-	return *(volatile unsigned int __force *) addr;
-}
-static inline unsigned long long __raw_readq(const volatile void __iomem *addr)
-{
-	return *(volatile unsigned long long __force *) addr;
-}
-
-static inline void __raw_writeb(unsigned char b, volatile void __iomem *addr)
-{
-	*(volatile unsigned char __force *) addr = b;
-}
-static inline void __raw_writew(unsigned short b, volatile void __iomem *addr)
-{
-	*(volatile unsigned short __force *) addr = b;
-}
-static inline void __raw_writel(unsigned int b, volatile void __iomem *addr)
-{
-	*(volatile unsigned int __force *) addr = b;
-}
-static inline void __raw_writeq(unsigned long long b, volatile void __iomem *addr)
-{
-	*(volatile unsigned long long __force *) addr = b;
-}
-
-/* readb can never be const, so use __fswab instead of le*_to_cpu */
-#define readb(addr) __raw_readb(addr)
-#define readw(addr) __fswab16(__raw_readw(addr))
-#define readl(addr) __fswab32(__raw_readl(addr))
-#define readq(addr) __fswab64(__raw_readq(addr))
-#define writeb(b, addr) __raw_writeb(b, addr)
-#define writew(b, addr) __raw_writew(cpu_to_le16(b), addr)
-#define writel(b, addr) __raw_writel(cpu_to_le32(b), addr)
-#define writeq(b, addr) __raw_writeq(cpu_to_le64(b), addr)
-
-#define readb_relaxed(addr) readb(addr)
-#define readw_relaxed(addr) readw(addr)
-#define readl_relaxed(addr) readl(addr)
-#define readq_relaxed(addr) readq(addr)
-
-#define mmiowb() do { } while (0)
-
-void memset_io(volatile void __iomem *addr, unsigned char val, int count);
-void memcpy_fromio(void *dst, const volatile void __iomem *src, int count);
-void memcpy_toio(volatile void __iomem *dst, const void *src, int count);
-
-/* Port-space IO */
-
-#define inb_p inb
-#define inw_p inw
-#define inl_p inl
-#define outb_p outb
-#define outw_p outw
-#define outl_p outl
-
-extern unsigned char eisa_in8(unsigned short port);
-extern unsigned short eisa_in16(unsigned short port);
-extern unsigned int eisa_in32(unsigned short port);
-extern void eisa_out8(unsigned char data, unsigned short port);
-extern void eisa_out16(unsigned short data, unsigned short port);
-extern void eisa_out32(unsigned int data, unsigned short port);
-
-#if defined(CONFIG_PCI)
-extern unsigned char inb(int addr);
-extern unsigned short inw(int addr);
-extern unsigned int inl(int addr);
-
-extern void outb(unsigned char b, int addr);
-extern void outw(unsigned short b, int addr);
-extern void outl(unsigned int b, int addr);
-#elif defined(CONFIG_EISA)
-#define inb eisa_in8
-#define inw eisa_in16
-#define inl eisa_in32
-#define outb eisa_out8
-#define outw eisa_out16
-#define outl eisa_out32
-#else
-static inline char inb(unsigned long addr)
-{
-	BUG();
-	return -1;
-}
-
-static inline short inw(unsigned long addr)
-{
-	BUG();
-	return -1;
-}
-
-static inline int inl(unsigned long addr)
-{
-	BUG();
-	return -1;
-}
-
-#define outb(x, y)	BUG()
-#define outw(x, y)	BUG()
-#define outl(x, y)	BUG()
-#endif
-
-/*
- * String versions of in/out ops:
- */
-extern void insb (unsigned long port, void *dst, unsigned long count);
-extern void insw (unsigned long port, void *dst, unsigned long count);
-extern void insl (unsigned long port, void *dst, unsigned long count);
-extern void outsb (unsigned long port, const void *src, unsigned long count);
-extern void outsw (unsigned long port, const void *src, unsigned long count);
-extern void outsl (unsigned long port, const void *src, unsigned long count);
-
-
-/* IO Port space is :      BBiiii   where BB is HBA number. */
-#define IO_SPACE_LIMIT 0x00ffffff
-
-/* PA machines have an MM I/O space from 0xf0000000-0xffffffff in 32
- * bit mode and from 0xfffffffff0000000-0xfffffffffffffff in 64 bit
- * mode (essentially just sign extending.  This macro takes in a 32
- * bit I/O address (still with the leading f) and outputs the correct
- * value for either 32 or 64 bit mode */
-#define F_EXTEND(x) ((unsigned long)((x) | (0xffffffff00000000ULL)))
-
-#include <asm-generic/iomap.h>
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)	__va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)	p
-
-#endif
diff --git a/include/asm-parisc/ioctl.h b/include/asm-parisc/ioctl.h
deleted file mode 100644
index ec8efa02beda..000000000000
--- a/include/asm-parisc/ioctl.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- *    Linux/PA-RISC Project (http://www.parisc-linux.org/)
- *    Copyright (C) 1999,2003 Matthew Wilcox < willy at debian . org >
- *    portions from "linux/ioctl.h for Linux" by H.H. Bergman.
- *
- *    This program is free software; you can redistribute it and/or modify
- *    it under the terms of the GNU General Public License as published by
- *    the Free Software Foundation; either version 2 of the License, or
- *    (at your option) any later version.
- *
- *    This program is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *    GNU General Public License for more details.
- *
- *    You should have received a copy of the GNU General Public License
- *    along with this program; if not, write to the Free Software
- *    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#ifndef _ASM_PARISC_IOCTL_H
-#define _ASM_PARISC_IOCTL_H
-
-/* ioctl command encoding: 32 bits total, command in lower 16 bits,
- * size of the parameter structure in the lower 14 bits of the
- * upper 16 bits.
- * Encoding the size of the parameter structure in the ioctl request
- * is useful for catching programs compiled with old versions
- * and to avoid overwriting user space outside the user buffer area.
- * The highest 2 bits are reserved for indicating the ``access mode''.
- * NOTE: This limits the max parameter size to 16kB -1 !
- */
-
-/*
- * Direction bits.
- */
-#define _IOC_NONE	0U
-#define _IOC_WRITE	2U
-#define _IOC_READ	1U
-
-#include <asm-generic/ioctl.h>
-
-#endif /* _ASM_PARISC_IOCTL_H */
diff --git a/include/asm-parisc/ioctls.h b/include/asm-parisc/ioctls.h
deleted file mode 100644
index 6747fad07a3e..000000000000
--- a/include/asm-parisc/ioctls.h
+++ /dev/null
@@ -1,90 +0,0 @@
-#ifndef __ARCH_PARISC_IOCTLS_H__
-#define __ARCH_PARISC_IOCTLS_H__
-
-#include <asm/ioctl.h>
-
-/* 0x54 is just a magic number to make these relatively unique ('T') */
-
-#define TCGETS		_IOR('T', 16, struct termios) /* TCGETATTR */
-#define TCSETS		_IOW('T', 17, struct termios) /* TCSETATTR */
-#define TCSETSW		_IOW('T', 18, struct termios) /* TCSETATTRD */
-#define TCSETSF		_IOW('T', 19, struct termios) /* TCSETATTRF */
-#define TCGETA		_IOR('T', 1, struct termio)
-#define TCSETA		_IOW('T', 2, struct termio)
-#define TCSETAW		_IOW('T', 3, struct termio)
-#define TCSETAF		_IOW('T', 4, struct termio)
-#define TCSBRK		_IO('T', 5)
-#define TCXONC		_IO('T', 6)
-#define TCFLSH		_IO('T', 7)
-#define TIOCEXCL	0x540C
-#define TIOCNXCL	0x540D
-#define TIOCSCTTY	0x540E
-#define TIOCGPGRP	_IOR('T', 30, int)
-#define TIOCSPGRP	_IOW('T', 29, int)
-#define TIOCOUTQ	0x5411
-#define TIOCSTI		0x5412
-#define TIOCGWINSZ	0x5413
-#define TIOCSWINSZ	0x5414
-#define TIOCMGET	0x5415
-#define TIOCMBIS	0x5416
-#define TIOCMBIC	0x5417
-#define TIOCMSET	0x5418
-#define TIOCGSOFTCAR	0x5419
-#define TIOCSSOFTCAR	0x541A
-#define FIONREAD	0x541B
-#define TIOCINQ		FIONREAD
-#define TIOCLINUX	0x541C
-#define TIOCCONS	0x541D
-#define TIOCGSERIAL	0x541E
-#define TIOCSSERIAL	0x541F
-#define TIOCPKT		0x5420
-#define FIONBIO		0x5421
-#define TIOCNOTTY	0x5422
-#define TIOCSETD	0x5423
-#define TIOCGETD	0x5424
-#define TCSBRKP		0x5425	/* Needed for POSIX tcsendbreak() */
-#define TIOCSBRK	0x5427  /* BSD compatibility */
-#define TIOCCBRK	0x5428  /* BSD compatibility */
-#define TIOCGSID	_IOR('T', 20, int) /* Return the session ID of FD */
-#define TCGETS2		_IOR('T',0x2A, struct termios2)
-#define TCSETS2		_IOW('T',0x2B, struct termios2)
-#define TCSETSW2	_IOW('T',0x2C, struct termios2)
-#define TCSETSF2	_IOW('T',0x2D, struct termios2)
-#define TIOCGPTN	_IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
-#define TIOCSPTLCK	_IOW('T',0x31, int)  /* Lock/unlock Pty */
-
-#define FIONCLEX	0x5450  /* these numbers need to be adjusted. */
-#define FIOCLEX		0x5451
-#define FIOASYNC	0x5452
-#define TIOCSERCONFIG	0x5453
-#define TIOCSERGWILD	0x5454
-#define TIOCSERSWILD	0x5455
-#define TIOCGLCKTRMIOS	0x5456
-#define TIOCSLCKTRMIOS	0x5457
-#define TIOCSERGSTRUCT	0x5458 /* For debugging only */
-#define TIOCSERGETLSR   0x5459 /* Get line status register */
-#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
-#define TIOCSERSETMULTI 0x545B /* Set multiport config */
-
-#define TIOCMIWAIT	0x545C	/* wait for a change on serial input line(s) */
-#define TIOCGICOUNT	0x545D	/* read serial port inline interrupt counts */
-#define TIOCGHAYESESP   0x545E  /* Get Hayes ESP configuration */
-#define TIOCSHAYESESP   0x545F  /* Set Hayes ESP configuration */
-#define FIOQSIZE	0x5460	/* Get exact space used by quota */
-
-#define TIOCSTART	0x5461
-#define TIOCSTOP	0x5462
-#define TIOCSLTC	0x5462
-
-/* Used for packet mode */
-#define TIOCPKT_DATA		 0
-#define TIOCPKT_FLUSHREAD	 1
-#define TIOCPKT_FLUSHWRITE	 2
-#define TIOCPKT_STOP		 4
-#define TIOCPKT_START		 8
-#define TIOCPKT_NOSTOP		16
-#define TIOCPKT_DOSTOP		32
-
-#define TIOCSER_TEMT    0x01	/* Transmitter physically empty */
-
-#endif /* _ASM_PARISC_IOCTLS_H */
diff --git a/include/asm-parisc/ipcbuf.h b/include/asm-parisc/ipcbuf.h
deleted file mode 100644
index bd956c425785..000000000000
--- a/include/asm-parisc/ipcbuf.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef __PARISC_IPCBUF_H__
-#define __PARISC_IPCBUF_H__
-
-/*
- * The ipc64_perm structure for PA-RISC is almost identical to
- * kern_ipc_perm as we have always had 32-bit UIDs and GIDs in the kernel.
- * 'seq' has been changed from long to int so that it's the same size
- * on 64-bit kernels as on 32-bit ones.
- */
-
-struct ipc64_perm
-{
-	key_t           key;
-	uid_t           uid;
-	gid_t           gid;
-	uid_t           cuid;
-	gid_t           cgid;
-	unsigned short int	__pad1;
-	mode_t          mode;
-	unsigned short int	__pad2;
-	unsigned short int	seq;
-	unsigned int	__pad3;
-	unsigned long long int __unused1;
-	unsigned long long int __unused2;
-};
-
-#endif /* __PARISC_IPCBUF_H__ */
diff --git a/include/asm-parisc/irq.h b/include/asm-parisc/irq.h
deleted file mode 100644
index 399c81981ed5..000000000000
--- a/include/asm-parisc/irq.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * include/asm-parisc/irq.h
- *
- * Copyright 2005 Matthew Wilcox <matthew@wil.cx>
- */
-
-#ifndef _ASM_PARISC_IRQ_H
-#define _ASM_PARISC_IRQ_H
-
-#include <linux/cpumask.h>
-#include <asm/types.h>
-
-#define NO_IRQ		(-1)
-
-#ifdef CONFIG_GSC
-#define GSC_IRQ_BASE	16
-#define GSC_IRQ_MAX	63
-#define CPU_IRQ_BASE	64
-#else
-#define CPU_IRQ_BASE	16
-#endif
-
-#define TIMER_IRQ	(CPU_IRQ_BASE + 0)
-#define	IPI_IRQ		(CPU_IRQ_BASE + 1)
-#define CPU_IRQ_MAX	(CPU_IRQ_BASE + (BITS_PER_LONG - 1))
-
-#define NR_IRQS		(CPU_IRQ_MAX + 1)
-
-static __inline__ int irq_canonicalize(int irq)
-{
-	return (irq == 2) ? 9 : irq;
-}
-
-struct irq_chip;
-
-/*
- * Some useful "we don't have to do anything here" handlers.  Should
- * probably be provided by the generic code.
- */
-void no_ack_irq(unsigned int irq);
-void no_end_irq(unsigned int irq);
-void cpu_ack_irq(unsigned int irq);
-void cpu_end_irq(unsigned int irq);
-
-extern int txn_alloc_irq(unsigned int nbits);
-extern int txn_claim_irq(int);
-extern unsigned int txn_alloc_data(unsigned int);
-extern unsigned long txn_alloc_addr(unsigned int);
-extern unsigned long txn_affinity_addr(unsigned int irq, int cpu);
-
-extern int cpu_claim_irq(unsigned int irq, struct irq_chip *, void *);
-extern int cpu_check_affinity(unsigned int irq, cpumask_t *dest);
-
-/* soft power switch support (power.c) */
-extern struct tasklet_struct power_tasklet;
-
-#endif	/* _ASM_PARISC_IRQ_H */
diff --git a/include/asm-parisc/irq_regs.h b/include/asm-parisc/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/include/asm-parisc/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/include/asm-parisc/kdebug.h b/include/asm-parisc/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/include/asm-parisc/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/include/asm-parisc/kmap_types.h b/include/asm-parisc/kmap_types.h
deleted file mode 100644
index 806aae3c5338..000000000000
--- a/include/asm-parisc/kmap_types.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef _ASM_KMAP_TYPES_H
-#define _ASM_KMAP_TYPES_H
-
-
-#ifdef CONFIG_DEBUG_HIGHMEM
-# define D(n) __KM_FENCE_##n ,
-#else
-# define D(n)
-#endif
-
-enum km_type {
-D(0)	KM_BOUNCE_READ,
-D(1)	KM_SKB_SUNRPC_DATA,
-D(2)	KM_SKB_DATA_SOFTIRQ,
-D(3)	KM_USER0,
-D(4)	KM_USER1,
-D(5)	KM_BIO_SRC_IRQ,
-D(6)	KM_BIO_DST_IRQ,
-D(7)	KM_PTE0,
-D(8)	KM_PTE1,
-D(9)	KM_IRQ0,
-D(10)	KM_IRQ1,
-D(11)	KM_SOFTIRQ0,
-D(12)	KM_SOFTIRQ1,
-D(13)	KM_TYPE_NR
-};
-
-#undef D
-
-#endif
diff --git a/include/asm-parisc/led.h b/include/asm-parisc/led.h
deleted file mode 100644
index c3405ab9d60a..000000000000
--- a/include/asm-parisc/led.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef LED_H
-#define LED_H
-
-#define	LED7		0x80		/* top (or furthest right) LED */
-#define	LED6		0x40
-#define	LED5		0x20
-#define	LED4		0x10
-#define	LED3		0x08
-#define	LED2		0x04
-#define	LED1		0x02
-#define	LED0		0x01		/* bottom (or furthest left) LED */
-
-#define	LED_LAN_TX	LED0		/* for LAN transmit activity */
-#define	LED_LAN_RCV	LED1		/* for LAN receive activity */
-#define	LED_DISK_IO	LED2		/* for disk activity */
-#define	LED_HEARTBEAT	LED3		/* heartbeat */
-
-/* values for pdc_chassis_lcd_info_ret_block.model: */
-#define DISPLAY_MODEL_LCD  0		/* KittyHawk LED or LCD */
-#define DISPLAY_MODEL_NONE 1		/* no LED or LCD */
-#define DISPLAY_MODEL_LASI 2		/* LASI style 8 bit LED */
-#define DISPLAY_MODEL_OLD_ASP 0x7F	/* faked: ASP style 8 x 1 bit LED (only very old ASP versions) */
-
-#define LED_CMD_REG_NONE 0		/* NULL == no addr for the cmd register */
-
-/* register_led_driver() */
-int __init register_led_driver(int model, unsigned long cmd_reg, unsigned long data_reg);
-
-/* registers the LED regions for procfs */
-void __init register_led_regions(void);
-
-#ifdef CONFIG_CHASSIS_LCD_LED
-/* writes a string to the LCD display (if possible on this h/w) */
-int lcd_print(const char *str);
-#else
-#define lcd_print(str)
-#endif
-
-/* main LED initialization function (uses PDC) */ 
-int __init led_init(void);
-
-#endif /* LED_H */
diff --git a/include/asm-parisc/linkage.h b/include/asm-parisc/linkage.h
deleted file mode 100644
index 0b19a7242d0c..000000000000
--- a/include/asm-parisc/linkage.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef __ASM_PARISC_LINKAGE_H
-#define __ASM_PARISC_LINKAGE_H
-
-#ifndef __ALIGN
-#define __ALIGN         .align 4
-#define __ALIGN_STR     ".align 4"
-#endif
-
-/*
- * In parisc assembly a semicolon marks a comment while a
- * exclamation mark is used to separate independent lines.
- */
-#ifdef __ASSEMBLY__
-
-#define ENTRY(name) \
-	.export name !\
-	ALIGN !\
-name:
-
-#ifdef CONFIG_64BIT
-#define ENDPROC(name) \
-	END(name)
-#else
-#define ENDPROC(name) \
-	.type name, @function !\
-	END(name)
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif  /* __ASM_PARISC_LINKAGE_H */
diff --git a/include/asm-parisc/local.h b/include/asm-parisc/local.h
deleted file mode 100644
index c11c530f74d0..000000000000
--- a/include/asm-parisc/local.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/local.h>
diff --git a/include/asm-parisc/machdep.h b/include/asm-parisc/machdep.h
deleted file mode 100644
index a231c97d703e..000000000000
--- a/include/asm-parisc/machdep.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef _PARISC_MACHDEP_H
-#define _PARISC_MACHDEP_H
-
-#include <linux/notifier.h>
-
-#define	MACH_RESTART	1
-#define	MACH_HALT	2
-#define MACH_POWER_ON	3
-#define	MACH_POWER_OFF	4
-
-extern struct notifier_block *mach_notifier;
-extern void pa7300lc_init(void);
-
-extern void (*cpu_lpmc)(int, struct pt_regs *);
-
-#endif
diff --git a/include/asm-parisc/mc146818rtc.h b/include/asm-parisc/mc146818rtc.h
deleted file mode 100644
index adf41631449f..000000000000
--- a/include/asm-parisc/mc146818rtc.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Machine dependent access functions for RTC registers.
- */
-#ifndef _ASM_MC146818RTC_H
-#define _ASM_MC146818RTC_H
-
-/* empty include file to satisfy the include in genrtc.c */
-
-#endif /* _ASM_MC146818RTC_H */
diff --git a/include/asm-parisc/mckinley.h b/include/asm-parisc/mckinley.h
deleted file mode 100644
index d1ea6f12915e..000000000000
--- a/include/asm-parisc/mckinley.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef ASM_PARISC_MCKINLEY_H
-#define ASM_PARISC_MCKINLEY_H
-#ifdef __KERNEL__
-
-/* declared in arch/parisc/kernel/setup.c */
-extern struct proc_dir_entry * proc_mckinley_root;
-
-#endif /*__KERNEL__*/
-#endif /*ASM_PARISC_MCKINLEY_H*/
diff --git a/include/asm-parisc/mman.h b/include/asm-parisc/mman.h
deleted file mode 100644
index defe752cc996..000000000000
--- a/include/asm-parisc/mman.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef __PARISC_MMAN_H__
-#define __PARISC_MMAN_H__
-
-#define PROT_READ	0x1		/* page can be read */
-#define PROT_WRITE	0x2		/* page can be written */
-#define PROT_EXEC	0x4		/* page can be executed */
-#define PROT_SEM	0x8		/* page may be used for atomic ops */
-#define PROT_NONE	0x0		/* page can not be accessed */
-#define PROT_GROWSDOWN	0x01000000	/* mprotect flag: extend change to start of growsdown vma */
-#define PROT_GROWSUP	0x02000000	/* mprotect flag: extend change to end of growsup vma */
-
-#define MAP_SHARED	0x01		/* Share changes */
-#define MAP_PRIVATE	0x02		/* Changes are private */
-#define MAP_TYPE	0x03		/* Mask for type of mapping */
-#define MAP_FIXED	0x04		/* Interpret addr exactly */
-#define MAP_ANONYMOUS	0x10		/* don't use a file */
-
-#define MAP_DENYWRITE	0x0800		/* ETXTBSY */
-#define MAP_EXECUTABLE	0x1000		/* mark it as an executable */
-#define MAP_LOCKED	0x2000		/* pages are locked */
-#define MAP_NORESERVE	0x4000		/* don't check for reservations */
-#define MAP_GROWSDOWN	0x8000		/* stack-like segment */
-#define MAP_POPULATE	0x10000		/* populate (prefault) pagetables */
-#define MAP_NONBLOCK	0x20000		/* do not block on IO */
-
-#define MS_SYNC		1		/* synchronous memory sync */
-#define MS_ASYNC	2		/* sync memory asynchronously */
-#define MS_INVALIDATE	4		/* invalidate the caches */
-
-#define MCL_CURRENT	1		/* lock all current mappings */
-#define MCL_FUTURE	2		/* lock all future mappings */
-
-#define MADV_NORMAL     0               /* no further special treatment */
-#define MADV_RANDOM     1               /* expect random page references */
-#define MADV_SEQUENTIAL 2               /* expect sequential page references */
-#define MADV_WILLNEED   3               /* will need these pages */
-#define MADV_DONTNEED   4               /* don't need these pages */
-#define MADV_SPACEAVAIL 5               /* insure that resources are reserved */
-#define MADV_VPS_PURGE  6               /* Purge pages from VM page cache */
-#define MADV_VPS_INHERIT 7              /* Inherit parents page size */
-
-/* common/generic parameters */
-#define MADV_REMOVE	9		/* remove these pages & resources */
-#define MADV_DONTFORK	10		/* don't inherit across fork */
-#define MADV_DOFORK	11		/* do inherit across fork */
-
-/* The range 12-64 is reserved for page size specification. */
-#define MADV_4K_PAGES   12              /* Use 4K pages  */
-#define MADV_16K_PAGES  14              /* Use 16K pages */
-#define MADV_64K_PAGES  16              /* Use 64K pages */
-#define MADV_256K_PAGES 18              /* Use 256K pages */
-#define MADV_1M_PAGES   20              /* Use 1 Megabyte pages */
-#define MADV_4M_PAGES   22              /* Use 4 Megabyte pages */
-#define MADV_16M_PAGES  24              /* Use 16 Megabyte pages */
-#define MADV_64M_PAGES  26              /* Use 64 Megabyte pages */
-
-/* compatibility flags */
-#define MAP_FILE	0
-#define MAP_VARIABLE	0
-
-#endif /* __PARISC_MMAN_H__ */
diff --git a/include/asm-parisc/mmu.h b/include/asm-parisc/mmu.h
deleted file mode 100644
index 6a310cf8b734..000000000000
--- a/include/asm-parisc/mmu.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _PARISC_MMU_H_
-#define _PARISC_MMU_H_
-
-/* On parisc, we store the space id here */
-typedef unsigned long mm_context_t;
-
-#endif /* _PARISC_MMU_H_ */
diff --git a/include/asm-parisc/mmu_context.h b/include/asm-parisc/mmu_context.h
deleted file mode 100644
index 85856c74ad1d..000000000000
--- a/include/asm-parisc/mmu_context.h
+++ /dev/null
@@ -1,75 +0,0 @@
-#ifndef __PARISC_MMU_CONTEXT_H
-#define __PARISC_MMU_CONTEXT_H
-
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <asm/atomic.h>
-#include <asm/pgalloc.h>
-#include <asm/pgtable.h>
-#include <asm-generic/mm_hooks.h>
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-/* on PA-RISC, we actually have enough contexts to justify an allocator
- * for them.  prumpf */
-
-extern unsigned long alloc_sid(void);
-extern void free_sid(unsigned long);
-
-static inline int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
-	BUG_ON(atomic_read(&mm->mm_users) != 1);
-
-	mm->context = alloc_sid();
-	return 0;
-}
-
-static inline void
-destroy_context(struct mm_struct *mm)
-{
-	free_sid(mm->context);
-	mm->context = 0;
-}
-
-static inline void load_context(mm_context_t context)
-{
-	mtsp(context, 3);
-#if SPACEID_SHIFT == 0
-	mtctl(context << 1,8);
-#else
-	mtctl(context >> (SPACEID_SHIFT - 1),8);
-#endif
-}
-
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk)
-{
-
-	if (prev != next) {
-		mtctl(__pa(next->pgd), 25);
-		load_context(next->context);
-	}
-}
-
-#define deactivate_mm(tsk,mm)	do { } while (0)
-
-static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
-{
-	/*
-	 * Activate_mm is our one chance to allocate a space id
-	 * for a new mm created in the exec path. There's also
-	 * some lazy tlb stuff, which is currently dead code, but
-	 * we only allocate a space id if one hasn't been allocated
-	 * already, so we should be OK.
-	 */
-
-	BUG_ON(next == &init_mm); /* Should never happen */
-
-	if (next->context == 0)
-	    next->context = alloc_sid();
-
-	switch_mm(prev,next,current);
-}
-#endif
diff --git a/include/asm-parisc/mmzone.h b/include/asm-parisc/mmzone.h
deleted file mode 100644
index 9608d2cf214a..000000000000
--- a/include/asm-parisc/mmzone.h
+++ /dev/null
@@ -1,73 +0,0 @@
-#ifndef _PARISC_MMZONE_H
-#define _PARISC_MMZONE_H
-
-#ifdef CONFIG_DISCONTIGMEM
-
-#define MAX_PHYSMEM_RANGES 8 /* Fix the size for now (current known max is 3) */
-extern int npmem_ranges;
-
-struct node_map_data {
-    pg_data_t pg_data;
-};
-
-extern struct node_map_data node_data[];
-
-#define NODE_DATA(nid)          (&node_data[nid].pg_data)
-
-#define node_start_pfn(nid)	(NODE_DATA(nid)->node_start_pfn)
-#define node_end_pfn(nid)						\
-({									\
-	pg_data_t *__pgdat = NODE_DATA(nid);				\
-	__pgdat->node_start_pfn + __pgdat->node_spanned_pages;		\
-})
-
-/* We have these possible memory map layouts:
- * Astro: 0-3.75, 67.75-68, 4-64
- * zx1: 0-1, 257-260, 4-256
- * Stretch (N-class): 0-2, 4-32, 34-xxx
- */
-
-/* Since each 1GB can only belong to one region (node), we can create
- * an index table for pfn to nid lookup; each entry in pfnnid_map 
- * represents 1GB, and contains the node that the memory belongs to. */
-
-#define PFNNID_SHIFT (30 - PAGE_SHIFT)
-#define PFNNID_MAP_MAX  512     /* support 512GB */
-extern unsigned char pfnnid_map[PFNNID_MAP_MAX];
-
-#ifndef CONFIG_64BIT
-#define pfn_is_io(pfn) ((pfn & (0xf0000000UL >> PAGE_SHIFT)) == (0xf0000000UL >> PAGE_SHIFT))
-#else
-/* io can be 0xf0f0f0f0f0xxxxxx or 0xfffffffff0000000 */
-#define pfn_is_io(pfn) ((pfn & (0xf000000000000000UL >> PAGE_SHIFT)) == (0xf000000000000000UL >> PAGE_SHIFT))
-#endif
-
-static inline int pfn_to_nid(unsigned long pfn)
-{
-	unsigned int i;
-	unsigned char r;
-
-	if (unlikely(pfn_is_io(pfn)))
-		return 0;
-
-	i = pfn >> PFNNID_SHIFT;
-	BUG_ON(i >= sizeof(pfnnid_map) / sizeof(pfnnid_map[0]));
-	r = pfnnid_map[i];
-	BUG_ON(r == 0xff);
-
-	return (int)r;
-}
-
-static inline int pfn_valid(int pfn)
-{
-	int nid = pfn_to_nid(pfn);
-
-	if (nid >= 0)
-		return (pfn < node_end_pfn(nid));
-	return 0;
-}
-
-#else /* !CONFIG_DISCONTIGMEM */
-#define MAX_PHYSMEM_RANGES 	1 
-#endif
-#endif /* _PARISC_MMZONE_H */
diff --git a/include/asm-parisc/module.h b/include/asm-parisc/module.h
deleted file mode 100644
index c2cb49e934c1..000000000000
--- a/include/asm-parisc/module.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef _ASM_PARISC_MODULE_H
-#define _ASM_PARISC_MODULE_H
-/*
- * This file contains the parisc architecture specific module code.
- */
-#ifdef CONFIG_64BIT
-#define Elf_Shdr Elf64_Shdr
-#define Elf_Sym Elf64_Sym
-#define Elf_Ehdr Elf64_Ehdr
-#define Elf_Addr Elf64_Addr
-#define Elf_Rela Elf64_Rela
-#else
-#define Elf_Shdr Elf32_Shdr
-#define Elf_Sym Elf32_Sym
-#define Elf_Ehdr Elf32_Ehdr
-#define Elf_Addr Elf32_Addr
-#define Elf_Rela Elf32_Rela
-#endif
-
-struct unwind_table;
-
-struct mod_arch_specific
-{
-	unsigned long got_offset, got_count, got_max;
-	unsigned long fdesc_offset, fdesc_count, fdesc_max;
-	unsigned long stub_offset, stub_count, stub_max;
-	unsigned long init_stub_offset, init_stub_count, init_stub_max;
-	int unwind_section;
-	struct unwind_table *unwind;
-};
-
-#endif /* _ASM_PARISC_MODULE_H */
diff --git a/include/asm-parisc/msgbuf.h b/include/asm-parisc/msgbuf.h
deleted file mode 100644
index fe88f2649418..000000000000
--- a/include/asm-parisc/msgbuf.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#ifndef _PARISC_MSGBUF_H
-#define _PARISC_MSGBUF_H
-
-/* 
- * The msqid64_ds structure for parisc architecture, copied from sparc.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct msqid64_ds {
-	struct ipc64_perm msg_perm;
-#ifndef CONFIG_64BIT
-	unsigned int   __pad1;
-#endif
-	__kernel_time_t msg_stime;	/* last msgsnd time */
-#ifndef CONFIG_64BIT
-	unsigned int   __pad2;
-#endif
-	__kernel_time_t msg_rtime;	/* last msgrcv time */
-#ifndef CONFIG_64BIT
-	unsigned int   __pad3;
-#endif
-	__kernel_time_t msg_ctime;	/* last change time */
-	unsigned int  msg_cbytes;	/* current number of bytes on queue */
-	unsigned int  msg_qnum;	/* number of messages in queue */
-	unsigned int  msg_qbytes;	/* max number of bytes on queue */
-	__kernel_pid_t msg_lspid;	/* pid of last msgsnd */
-	__kernel_pid_t msg_lrpid;	/* last receive pid */
-	unsigned int  __unused1;
-	unsigned int  __unused2;
-};
-
-#endif /* _PARISC_MSGBUF_H */
diff --git a/include/asm-parisc/mutex.h b/include/asm-parisc/mutex.h
deleted file mode 100644
index 458c1f7fbc18..000000000000
--- a/include/asm-parisc/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Pull in the generic implementation for the mutex fastpath.
- *
- * TODO: implement optimized primitives instead, or leave the generic
- * implementation in place, or pick the atomic_xchg() based generic
- * implementation. (see asm-generic/mutex-xchg.h for details)
- */
-
-#include <asm-generic/mutex-dec.h>
diff --git a/include/asm-parisc/page.h b/include/asm-parisc/page.h
deleted file mode 100644
index c3941f09a878..000000000000
--- a/include/asm-parisc/page.h
+++ /dev/null
@@ -1,173 +0,0 @@
-#ifndef _PARISC_PAGE_H
-#define _PARISC_PAGE_H
-
-#include <linux/const.h>
-
-#if defined(CONFIG_PARISC_PAGE_SIZE_4KB)
-# define PAGE_SHIFT	12
-#elif defined(CONFIG_PARISC_PAGE_SIZE_16KB)
-# define PAGE_SHIFT	14
-#elif defined(CONFIG_PARISC_PAGE_SIZE_64KB)
-# define PAGE_SHIFT	16
-#else
-# error "unknown default kernel page size"
-#endif
-#define PAGE_SIZE	(_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK	(~(PAGE_SIZE-1))
-
-
-#ifndef __ASSEMBLY__
-
-#include <asm/types.h>
-#include <asm/cache.h>
-
-#define clear_page(page)	memset((void *)(page), 0, PAGE_SIZE)
-#define copy_page(to,from)      copy_user_page_asm((void *)(to), (void *)(from))
-
-struct page;
-
-void copy_user_page_asm(void *to, void *from);
-void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
-			   struct page *pg);
-void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
-
-/*
- * These are used to make use of C type-checking..
- */
-#define STRICT_MM_TYPECHECKS
-#ifdef STRICT_MM_TYPECHECKS
-typedef struct { unsigned long pte;
-#if !defined(CONFIG_64BIT)
-                 unsigned long future_flags;
- /* XXX: it's possible to remove future_flags and change BITS_PER_PTE_ENTRY
-	 to 2, but then strangely the identical 32bit kernel boots on a
-	 c3000(pa20), but not any longer on a 715(pa11).
-	 Still investigating... HelgeD.
-  */
-#endif
-} pte_t; /* either 32 or 64bit */
-
-/* NOTE: even on 64 bits, these entries are __u32 because we allocate
- * the pmd and pgd in ZONE_DMA (i.e. under 4GB) */
-typedef struct { __u32 pmd; } pmd_t;
-typedef struct { __u32 pgd; } pgd_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
-
-#define pte_val(x)	((x).pte)
-/* These do not work lvalues, so make sure we don't use them as such. */
-#define pmd_val(x)	((x).pmd + 0)
-#define pgd_val(x)	((x).pgd + 0)
-#define pgprot_val(x)	((x).pgprot)
-
-#define __pte(x)	((pte_t) { (x) } )
-#define __pmd(x)	((pmd_t) { (x) } )
-#define __pgd(x)	((pgd_t) { (x) } )
-#define __pgprot(x)	((pgprot_t) { (x) } )
-
-#define __pmd_val_set(x,n) (x).pmd = (n)
-#define __pgd_val_set(x,n) (x).pgd = (n)
-
-#else
-/*
- * .. while these make it easier on the compiler
- */
-typedef unsigned long pte_t;
-typedef         __u32 pmd_t;
-typedef         __u32 pgd_t;
-typedef unsigned long pgprot_t;
-
-#define pte_val(x)      (x)
-#define pmd_val(x)      (x)
-#define pgd_val(x)      (x)
-#define pgprot_val(x)   (x)
-
-#define __pte(x)        (x)
-#define __pmd(x)	(x)
-#define __pgd(x)        (x)
-#define __pgprot(x)     (x)
-
-#define __pmd_val_set(x,n) (x) = (n)
-#define __pgd_val_set(x,n) (x) = (n)
-
-#endif /* STRICT_MM_TYPECHECKS */
-
-typedef struct page *pgtable_t;
-
-typedef struct __physmem_range {
-	unsigned long start_pfn;
-	unsigned long pages;       /* PAGE_SIZE pages */
-} physmem_range_t;
-
-extern physmem_range_t pmem_ranges[];
-extern int npmem_ranges;
-
-#endif /* !__ASSEMBLY__ */
-
-/* WARNING: The definitions below must match exactly to sizeof(pte_t)
- * etc
- */
-#ifdef CONFIG_64BIT
-#define BITS_PER_PTE_ENTRY	3
-#define BITS_PER_PMD_ENTRY	2
-#define BITS_PER_PGD_ENTRY	2
-#else
-#define BITS_PER_PTE_ENTRY	3
-#define BITS_PER_PMD_ENTRY	2
-#define BITS_PER_PGD_ENTRY	BITS_PER_PMD_ENTRY
-#endif
-#define PGD_ENTRY_SIZE	(1UL << BITS_PER_PGD_ENTRY)
-#define PMD_ENTRY_SIZE	(1UL << BITS_PER_PMD_ENTRY)
-#define PTE_ENTRY_SIZE	(1UL << BITS_PER_PTE_ENTRY)
-
-#define LINUX_GATEWAY_SPACE     0
-
-/* This governs the relationship between virtual and physical addresses.
- * If you alter it, make sure to take care of our various fixed mapping
- * segments in fixmap.h */
-#ifdef CONFIG_64BIT
-#define __PAGE_OFFSET	(0x40000000)	/* 1GB */
-#else
-#define __PAGE_OFFSET	(0x10000000)	/* 256MB */
-#endif
-
-#define PAGE_OFFSET		((unsigned long)__PAGE_OFFSET)
-
-/* The size of the gateway page (we leave lots of room for expansion) */
-#define GATEWAY_PAGE_SIZE	0x4000
-
-/* The start of the actual kernel binary---used in vmlinux.lds.S
- * Leave some space after __PAGE_OFFSET for detecting kernel null
- * ptr derefs */
-#define KERNEL_BINARY_TEXT_START	(__PAGE_OFFSET + 0x100000)
-
-/* These macros don't work for 64-bit C code -- don't allow in C at all */
-#ifdef __ASSEMBLY__
-#   define PA(x)	((x)-__PAGE_OFFSET)
-#   define VA(x)	((x)+__PAGE_OFFSET)
-#endif
-#define __pa(x)			((unsigned long)(x)-PAGE_OFFSET)
-#define __va(x)			((void *)((unsigned long)(x)+PAGE_OFFSET))
-
-#ifndef CONFIG_DISCONTIGMEM
-#define pfn_valid(pfn)		((pfn) < max_mapnr)
-#endif /* CONFIG_DISCONTIGMEM */
-
-#ifdef CONFIG_HUGETLB_PAGE
-#define HPAGE_SHIFT		22	/* 4MB (is this fixed?) */
-#define HPAGE_SIZE      	((1UL) << HPAGE_SHIFT)
-#define HPAGE_MASK		(~(HPAGE_SIZE - 1))
-#define HUGETLB_PAGE_ORDER	(HPAGE_SHIFT - PAGE_SHIFT)
-#endif
-
-#define virt_addr_valid(kaddr)	pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
-
-#define page_to_phys(page)	(page_to_pfn(page) << PAGE_SHIFT)
-#define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
-
-#define VM_DATA_DEFAULT_FLAGS	(VM_READ | VM_WRITE | VM_EXEC | \
-				 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#include <asm-generic/memory_model.h>
-#include <asm-generic/page.h>
-
-#endif /* _PARISC_PAGE_H */
diff --git a/include/asm-parisc/param.h b/include/asm-parisc/param.h
deleted file mode 100644
index 32e03d877858..000000000000
--- a/include/asm-parisc/param.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef _ASMPARISC_PARAM_H
-#define _ASMPARISC_PARAM_H
-
-#ifdef __KERNEL__
-#define HZ		CONFIG_HZ
-#define USER_HZ		100		/* some user API use "ticks" */
-#define CLOCKS_PER_SEC	(USER_HZ)	/* like times() */
-#endif
-
-#ifndef HZ
-#define HZ 100
-#endif
-
-#define EXEC_PAGESIZE	4096
-
-#ifndef NOGROUP
-#define NOGROUP		(-1)
-#endif
-
-#define MAXHOSTNAMELEN	64	/* max length of hostname */
-
-#endif
diff --git a/include/asm-parisc/parisc-device.h b/include/asm-parisc/parisc-device.h
deleted file mode 100644
index 7aa13f2add7a..000000000000
--- a/include/asm-parisc/parisc-device.h
+++ /dev/null
@@ -1,64 +0,0 @@
-#ifndef _ASM_PARISC_PARISC_DEVICE_H_
-#define _ASM_PARISC_PARISC_DEVICE_H_
-
-#include <linux/device.h>
-
-struct parisc_device {
-	struct resource hpa;		/* Hard Physical Address */
-	struct parisc_device_id id;
-	struct parisc_driver *driver;	/* Driver for this device */
-	char		name[80];	/* The hardware description */
-	int		irq;
-	int		aux_irq;	/* Some devices have a second IRQ */
-
-	char		hw_path;        /* The module number on this bus */
-	unsigned int	num_addrs;	/* some devices have additional address ranges. */
-	unsigned long	*addr;          /* which will be stored here */
- 
-#ifdef CONFIG_64BIT
-	/* parms for pdc_pat_cell_module() call */
-	unsigned long	pcell_loc;	/* Physical Cell location */
-	unsigned long	mod_index;	/* PAT specific - Misc Module info */
-
-	/* generic info returned from pdc_pat_cell_module() */
-	unsigned long	mod_info;	/* PAT specific - Misc Module info */
-	unsigned long	pmod_loc;	/* physical Module location */
-#endif
-	u64		dma_mask;	/* DMA mask for I/O */
-	struct device 	dev;
-};
-
-struct parisc_driver {
-	struct parisc_driver *next;
-	char *name; 
-	const struct parisc_device_id *id_table;
-	int (*probe) (struct parisc_device *dev); /* New device discovered */
-	int (*remove) (struct parisc_device *dev);
-	struct device_driver drv;
-};
-
-
-#define to_parisc_device(d)	container_of(d, struct parisc_device, dev)
-#define to_parisc_driver(d)	container_of(d, struct parisc_driver, drv)
-#define parisc_parent(d)	to_parisc_device(d->dev.parent)
-
-static inline char *parisc_pathname(struct parisc_device *d)
-{
-	return d->dev.bus_id;
-}
-
-static inline void
-parisc_set_drvdata(struct parisc_device *d, void *p)
-{
-	dev_set_drvdata(&d->dev, p);
-}
-
-static inline void *
-parisc_get_drvdata(struct parisc_device *d)
-{
-	return dev_get_drvdata(&d->dev);
-}
-
-extern struct bus_type parisc_bus_type;
-
-#endif /*_ASM_PARISC_PARISC_DEVICE_H_*/
diff --git a/include/asm-parisc/parport.h b/include/asm-parisc/parport.h
deleted file mode 100644
index 00d9cc3e7b97..000000000000
--- a/include/asm-parisc/parport.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* 
- *
- * parport.h: ia32-compatible parport initialisation
- *
- * This file should only be included by drivers/parport/parport_pc.c.
- */
-#ifndef _ASM_PARPORT_H
-#define _ASM_PARPORT_H 1
-
-
-static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
-{
-	/* nothing ! */
-	return 0;
-}
-
-
-#endif /* !(_ASM_PARPORT_H) */
diff --git a/include/asm-parisc/pci.h b/include/asm-parisc/pci.h
deleted file mode 100644
index 4ba868f44a5e..000000000000
--- a/include/asm-parisc/pci.h
+++ /dev/null
@@ -1,294 +0,0 @@
-#ifndef __ASM_PARISC_PCI_H
-#define __ASM_PARISC_PCI_H
-
-#include <asm/scatterlist.h>
-
-
-
-/*
-** HP PCI platforms generally support multiple bus adapters.
-**    (workstations 1-~4, servers 2-~32)
-**
-** Newer platforms number the busses across PCI bus adapters *sparsely*.
-** E.g. 0, 8, 16, ...
-**
-** Under a PCI bus, most HP platforms support PPBs up to two or three
-** levels deep. See "Bit3" product line. 
-*/
-#define PCI_MAX_BUSSES	256
-
-
-/* To be used as: mdelay(pci_post_reset_delay);
- *
- * post_reset is the time the kernel should stall to prevent anyone from
- * accessing the PCI bus once #RESET is de-asserted. 
- * PCI spec somewhere says 1 second but with multi-PCI bus systems,
- * this makes the boot time much longer than necessary.
- * 20ms seems to work for all the HP PCI implementations to date.
- */
-#define pci_post_reset_delay 50
-
-
-/*
-** pci_hba_data (aka H2P_OBJECT in HP/UX)
-**
-** This is the "common" or "base" data structure which HBA drivers
-** (eg Dino or LBA) are required to place at the top of their own
-** platform_data structure.  I've heard this called "C inheritance" too.
-**
-** Data needed by pcibios layer belongs here.
-*/
-struct pci_hba_data {
-	void __iomem   *base_addr;	/* aka Host Physical Address */
-	const struct parisc_device *dev; /* device from PA bus walk */
-	struct pci_bus *hba_bus;	/* primary PCI bus below HBA */
-	int		hba_num;	/* I/O port space access "key" */
-	struct resource bus_num;	/* PCI bus numbers */
-	struct resource io_space;	/* PIOP */
-	struct resource lmmio_space;	/* bus addresses < 4Gb */
-	struct resource elmmio_space;	/* additional bus addresses < 4Gb */
-	struct resource gmmio_space;	/* bus addresses > 4Gb */
-
-	/* NOTE: Dino code assumes it can use *all* of the lmmio_space,
-	 * elmmio_space and gmmio_space as a contiguous array of
-	 * resources.  This #define represents the array size */
-	#define DINO_MAX_LMMIO_RESOURCES	3
-
-	unsigned long   lmmio_space_offset;  /* CPU view - PCI view */
-	void *          iommu;          /* IOMMU this device is under */
-	/* REVISIT - spinlock to protect resources? */
-
-	#define HBA_NAME_SIZE 16
-	char io_name[HBA_NAME_SIZE];
-	char lmmio_name[HBA_NAME_SIZE];
-	char elmmio_name[HBA_NAME_SIZE];
-	char gmmio_name[HBA_NAME_SIZE];
-};
-
-#define HBA_DATA(d)		((struct pci_hba_data *) (d))
-
-/* 
-** We support 2^16 I/O ports per HBA.  These are set up in the form
-** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
-** space address.
-*/
-#define HBA_PORT_SPACE_BITS	16
-
-#define HBA_PORT_BASE(h)	((h) << HBA_PORT_SPACE_BITS)
-#define HBA_PORT_SPACE_SIZE	(1UL << HBA_PORT_SPACE_BITS)
-
-#define PCI_PORT_HBA(a)		((a) >> HBA_PORT_SPACE_BITS)
-#define PCI_PORT_ADDR(a)	((a) & (HBA_PORT_SPACE_SIZE - 1))
-
-#ifdef CONFIG_64BIT
-#define PCI_F_EXTEND		0xffffffff00000000UL
-#define PCI_IS_LMMIO(hba,a)	pci_is_lmmio(hba,a)
-
-/* We need to know if an address is LMMMIO or GMMIO.
- * LMMIO requires mangling and GMMIO we must use as-is.
- */
-static __inline__  int pci_is_lmmio(struct pci_hba_data *hba, unsigned long a)
-{
-	return(((a) & PCI_F_EXTEND) == PCI_F_EXTEND);
-}
-
-/*
-** Convert between PCI (IO_VIEW) addresses and processor (PA_VIEW) addresses.
-** See pci.c for more conversions used by Generic PCI code.
-**
-** Platform characteristics/firmware guarantee that
-**	(1) PA_VIEW - IO_VIEW = lmmio_offset for both LMMIO and ELMMIO
-**	(2) PA_VIEW == IO_VIEW for GMMIO
-*/
-#define PCI_BUS_ADDR(hba,a)	(PCI_IS_LMMIO(hba,a)	\
-		?  ((a) - hba->lmmio_space_offset)	/* mangle LMMIO */ \
-		: (a))					/* GMMIO */
-#define PCI_HOST_ADDR(hba,a)	(((a) & PCI_F_EXTEND) == 0 \
-		? (a) + hba->lmmio_space_offset \
-		: (a))
-
-#else	/* !CONFIG_64BIT */
-
-#define PCI_BUS_ADDR(hba,a)	(a)
-#define PCI_HOST_ADDR(hba,a)	(a)
-#define PCI_F_EXTEND		0UL
-#define PCI_IS_LMMIO(hba,a)	(1)	/* 32-bit doesn't support GMMIO */
-
-#endif /* !CONFIG_64BIT */
-
-/*
-** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus
-** (This eliminates some of the warnings).
-*/
-struct pci_bus;
-struct pci_dev;
-
-/*
- * If the PCI device's view of memory is the same as the CPU's view of memory,
- * PCI_DMA_BUS_IS_PHYS is true.  The networking and block device layers use
- * this boolean for bounce buffer decisions.
- */
-#ifdef CONFIG_PA20
-/* All PA-2.0 machines have an IOMMU. */
-#define PCI_DMA_BUS_IS_PHYS	0
-#define parisc_has_iommu()	do { } while (0)
-#else
-
-#if defined(CONFIG_IOMMU_CCIO) || defined(CONFIG_IOMMU_SBA)
-extern int parisc_bus_is_phys; 	/* in arch/parisc/kernel/setup.c */
-#define PCI_DMA_BUS_IS_PHYS	parisc_bus_is_phys
-#define parisc_has_iommu()	do { parisc_bus_is_phys = 0; } while (0)
-#else
-#define PCI_DMA_BUS_IS_PHYS	1
-#define parisc_has_iommu()	do { } while (0)
-#endif
-
-#endif	/* !CONFIG_PA20 */
-
-
-/*
-** Most PCI devices (eg Tulip, NCR720) also export the same registers
-** to both MMIO and I/O port space.  Due to poor performance of I/O Port
-** access under HP PCI bus adapters, strongly recommend the use of MMIO
-** address space.
-**
-** While I'm at it more PA programming notes:
-**
-** 1) MMIO stores (writes) are posted operations. This means the processor
-**    gets an "ACK" before the write actually gets to the device. A read
-**    to the same device (or typically the bus adapter above it) will
-**    force in-flight write transaction(s) out to the targeted device
-**    before the read can complete.
-**
-** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
-**    respect to DMA on all platforms. Ie PIO data can reach the processor
-**    before in-flight DMA reaches memory. Since most SMP PA platforms
-**    are I/O coherent, it generally doesn't matter...but sometimes
-**    it does.
-**
-** I've helped device driver writers debug both types of problems.
-*/
-struct pci_port_ops {
-	  u8 (*inb)  (struct pci_hba_data *hba, u16 port);
-	 u16 (*inw)  (struct pci_hba_data *hba, u16 port);
-	 u32 (*inl)  (struct pci_hba_data *hba, u16 port);
-	void (*outb) (struct pci_hba_data *hba, u16 port,  u8 data);
-	void (*outw) (struct pci_hba_data *hba, u16 port, u16 data);
-	void (*outl) (struct pci_hba_data *hba, u16 port, u32 data);
-};
-
-
-struct pci_bios_ops {
-	void (*init)(void);
-	void (*fixup_bus)(struct pci_bus *bus);
-};
-
-/* pci_unmap_{single,page} is not a nop, thus... */
-#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)	\
-	dma_addr_t ADDR_NAME;
-#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)		\
-	__u32 LEN_NAME;
-#define pci_unmap_addr(PTR, ADDR_NAME)			\
-	((PTR)->ADDR_NAME)
-#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)		\
-	(((PTR)->ADDR_NAME) = (VAL))
-#define pci_unmap_len(PTR, LEN_NAME)			\
-	((PTR)->LEN_NAME)
-#define pci_unmap_len_set(PTR, LEN_NAME, VAL)		\
-	(((PTR)->LEN_NAME) = (VAL))
-
-/*
-** Stuff declared in arch/parisc/kernel/pci.c
-*/
-extern struct pci_port_ops *pci_port;
-extern struct pci_bios_ops *pci_bios;
-
-#ifdef CONFIG_PCI
-extern void pcibios_register_hba(struct pci_hba_data *);
-extern void pcibios_set_master(struct pci_dev *);
-#else
-static inline void pcibios_register_hba(struct pci_hba_data *x)
-{
-}
-#endif
-
-/*
- * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()
- *   0 == check if bridge is numbered before re-numbering.
- *   1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
- *
- *   We *should* set this to zero for "legacy" platforms and one
- *   for PAT platforms.
- *
- *   But legacy platforms also need to renumber the busses below a Host
- *   Bus controller.  Adding a 4-port Tulip card on the first PCI root
- *   bus of a C200 resulted in the secondary bus being numbered as 1.
- *   The second PCI host bus controller's root bus had already been
- *   assigned bus number 1 by firmware and sysfs complained.
- *
- *   Firmware isn't doing anything wrong here since each controller
- *   is its own PCI domain.  It's simpler and easier for us to renumber
- *   the busses rather than treat each Dino as a separate PCI domain.
- *   Eventually, we may want to introduce PCI domains for Superdome or
- *   rp7420/8420 boxes and then revisit this issue.
- */
-#define pcibios_assign_all_busses()     (1)
-#define pcibios_scan_all_fns(a, b)	(0)
-
-#define PCIBIOS_MIN_IO          0x10
-#define PCIBIOS_MIN_MEM         0x1000 /* NBPG - but pci/setup-res.c dies */
-
-/* export the pci_ DMA API in terms of the dma_ one */
-#include <asm-generic/pci-dma-compat.h>
-
-#ifdef CONFIG_PCI
-static inline void pci_dma_burst_advice(struct pci_dev *pdev,
-					enum pci_dma_burst_strategy *strat,
-					unsigned long *strategy_parameter)
-{
-	unsigned long cacheline_size;
-	u8 byte;
-
-	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
-	if (byte == 0)
-		cacheline_size = 1024;
-	else
-		cacheline_size = (int) byte * 4;
-
-	*strat = PCI_DMA_BURST_MULTIPLE;
-	*strategy_parameter = cacheline_size;
-}
-#endif
-
-extern void
-pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-			 struct resource *res);
-
-extern void
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-			struct pci_bus_region *region);
-
-static inline struct resource *
-pcibios_select_root(struct pci_dev *pdev, struct resource *res)
-{
-	struct resource *root = NULL;
-
-	if (res->flags & IORESOURCE_IO)
-		root = &ioport_resource;
-	if (res->flags & IORESOURCE_MEM)
-		root = &iomem_resource;
-
-	return root;
-}
-
-static inline void pcibios_penalize_isa_irq(int irq, int active)
-{
-	/* We don't need to penalize isa irq's */
-}
-
-static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
-{
-	return channel ? 15 : 14;
-}
-
-#endif /* __ASM_PARISC_PCI_H */
diff --git a/include/asm-parisc/pdc.h b/include/asm-parisc/pdc.h
deleted file mode 100644
index 9eaa794c3e4a..000000000000
--- a/include/asm-parisc/pdc.h
+++ /dev/null
@@ -1,757 +0,0 @@
-#ifndef _PARISC_PDC_H
-#define _PARISC_PDC_H
-
-/*
- *	PDC return values ...
- *	All PDC calls return a subset of these errors. 
- */
-
-#define PDC_WARN		  3	/* Call completed with a warning */
-#define PDC_REQ_ERR_1		  2	/* See above			 */
-#define PDC_REQ_ERR_0		  1	/* Call would generate a requestor error */
-#define PDC_OK			  0	/* Call completed successfully	*/
-#define PDC_BAD_PROC		 -1	/* Called non-existent procedure*/
-#define PDC_BAD_OPTION		 -2	/* Called with non-existent option */
-#define PDC_ERROR		 -3	/* Call could not complete without an error */
-#define PDC_NE_MOD		 -5	/* Module not found		*/
-#define PDC_NE_CELL_MOD		 -7	/* Cell module not found	*/
-#define PDC_INVALID_ARG		-10	/* Called with an invalid argument */
-#define PDC_BUS_POW_WARN	-12	/* Call could not complete in allowed power budget */
-#define PDC_NOT_NARROW		-17	/* Narrow mode not supported	*/
-
-/*
- *	PDC entry points...
- */
-
-#define PDC_POW_FAIL	1		/* perform a power-fail		*/
-#define PDC_POW_FAIL_PREPARE	0	/* prepare for powerfail	*/
-
-#define PDC_CHASSIS	2		/* PDC-chassis functions	*/
-#define PDC_CHASSIS_DISP	0	/* update chassis display	*/
-#define PDC_CHASSIS_WARN	1	/* return chassis warnings	*/
-#define PDC_CHASSIS_DISPWARN	2	/* update&return chassis status */
-#define PDC_RETURN_CHASSIS_INFO 128	/* HVERSION dependent: return chassis LED/LCD info  */
-
-#define PDC_PIM         3               /* Get PIM data                 */
-#define PDC_PIM_HPMC            0       /* Transfer HPMC data           */
-#define PDC_PIM_RETURN_SIZE     1       /* Get Max buffer needed for PIM*/
-#define PDC_PIM_LPMC            2       /* Transfer HPMC data           */
-#define PDC_PIM_SOFT_BOOT       3       /* Transfer Soft Boot data      */
-#define PDC_PIM_TOC             4       /* Transfer TOC data            */
-
-#define PDC_MODEL	4		/* PDC model information call	*/
-#define PDC_MODEL_INFO		0	/* returns information 		*/
-#define PDC_MODEL_BOOTID	1	/* set the BOOT_ID		*/
-#define PDC_MODEL_VERSIONS	2	/* returns cpu-internal versions*/
-#define PDC_MODEL_SYSMODEL	3	/* return system model info	*/
-#define PDC_MODEL_ENSPEC	4	/* enable specific option	*/
-#define PDC_MODEL_DISPEC	5	/* disable specific option	*/
-#define PDC_MODEL_CPU_ID	6	/* returns cpu-id (only newer machines!) */
-#define PDC_MODEL_CAPABILITIES	7	/* returns OS32/OS64-flags	*/
-/* Values for PDC_MODEL_CAPABILITIES non-equivalent virtual aliasing support */
-#define  PDC_MODEL_IOPDIR_FDC		(1 << 2)
-#define  PDC_MODEL_NVA_MASK		(3 << 4)
-#define  PDC_MODEL_NVA_SUPPORTED	(0 << 4)
-#define  PDC_MODEL_NVA_SLOW		(1 << 4)
-#define  PDC_MODEL_NVA_UNSUPPORTED	(3 << 4)
-#define PDC_MODEL_GET_BOOT__OP	8	/* returns boot test options	*/
-#define PDC_MODEL_SET_BOOT__OP	9	/* set boot test options	*/
-
-#define PA89_INSTRUCTION_SET	0x4	/* capatibilies returned	*/
-#define PA90_INSTRUCTION_SET	0x8
-
-#define PDC_CACHE	5		/* return/set cache (& TLB) info*/
-#define PDC_CACHE_INFO		0	/* returns information 		*/
-#define PDC_CACHE_SET_COH	1	/* set coherence state		*/
-#define PDC_CACHE_RET_SPID	2	/* returns space-ID bits	*/
-
-#define PDC_HPA		6		/* return HPA of processor	*/
-#define PDC_HPA_PROCESSOR	0
-#define PDC_HPA_MODULES		1
-
-#define PDC_COPROC	7		/* Co-Processor (usually FP unit(s)) */
-#define PDC_COPROC_CFG		0	/* Co-Processor Cfg (FP unit(s) enabled?) */
-
-#define PDC_IODC	8		/* talk to IODC			*/
-#define PDC_IODC_READ		0	/* read IODC entry point	*/
-/*      PDC_IODC_RI_			 * INDEX parameter of PDC_IODC_READ */
-#define PDC_IODC_RI_DATA_BYTES	0	/* IODC Data Bytes		*/
-/*				1, 2	   obsolete - HVERSION dependent*/
-#define PDC_IODC_RI_INIT	3	/* Initialize module		*/
-#define PDC_IODC_RI_IO		4	/* Module input/output		*/
-#define PDC_IODC_RI_SPA		5	/* Module input/output		*/
-#define PDC_IODC_RI_CONFIG	6	/* Module input/output		*/
-/*				7	  obsolete - HVERSION dependent */
-#define PDC_IODC_RI_TEST	8	/* Module input/output		*/
-#define PDC_IODC_RI_TLB		9	/* Module input/output		*/
-#define PDC_IODC_NINIT		2	/* non-destructive init		*/
-#define PDC_IODC_DINIT		3	/* destructive init		*/
-#define PDC_IODC_MEMERR		4	/* check for memory errors	*/
-#define PDC_IODC_INDEX_DATA	0	/* get first 16 bytes from mod IODC */
-#define PDC_IODC_BUS_ERROR	-4	/* bus error return value	*/
-#define PDC_IODC_INVALID_INDEX	-5	/* invalid index return value	*/
-#define PDC_IODC_COUNT		-6	/* count is too small		*/
-
-#define PDC_TOD		9		/* time-of-day clock (TOD)	*/
-#define PDC_TOD_READ		0	/* read TOD			*/
-#define PDC_TOD_WRITE		1	/* write TOD			*/
-
-
-#define PDC_STABLE	10		/* stable storage (sprockets)	*/
-#define PDC_STABLE_READ		0
-#define PDC_STABLE_WRITE	1
-#define PDC_STABLE_RETURN_SIZE	2
-#define PDC_STABLE_VERIFY_CONTENTS 3
-#define PDC_STABLE_INITIALIZE	4
-
-#define PDC_NVOLATILE	11		/* often not implemented	*/
-
-#define PDC_ADD_VALID	12		/* Memory validation PDC call	*/
-#define PDC_ADD_VALID_VERIFY	0	/* Make PDC_ADD_VALID verify region */
-
-#define PDC_INSTR	15		/* get instr to invoke PDCE_CHECK() */
-
-#define PDC_PROC	16		/* (sprockets)			*/
-
-#define PDC_CONFIG	16		/* (sprockets)			*/
-#define PDC_CONFIG_DECONFIG	0
-#define PDC_CONFIG_DRECONFIG	1
-#define PDC_CONFIG_DRETURN_CONFIG 2
-
-#define PDC_BLOCK_TLB	18		/* manage hardware block-TLB	*/
-#define PDC_BTLB_INFO		0	/* returns parameter 		*/
-#define PDC_BTLB_INSERT		1	/* insert BTLB entry		*/
-#define PDC_BTLB_PURGE		2	/* purge BTLB entries 		*/
-#define PDC_BTLB_PURGE_ALL	3	/* purge all BTLB entries 	*/
-
-#define PDC_TLB		19		/* manage hardware TLB miss handling */
-#define PDC_TLB_INFO		0	/* returns parameter 		*/
-#define PDC_TLB_SETUP		1	/* set up miss handling 	*/
-
-#define PDC_MEM		20		/* Manage memory		*/
-#define PDC_MEM_MEMINFO		0
-#define PDC_MEM_ADD_PAGE	1
-#define PDC_MEM_CLEAR_PDT	2
-#define PDC_MEM_READ_PDT	3
-#define PDC_MEM_RESET_CLEAR	4
-#define PDC_MEM_GOODMEM		5
-#define PDC_MEM_TABLE		128	/* Non contig mem map (sprockets) */
-#define PDC_MEM_RETURN_ADDRESS_TABLE	PDC_MEM_TABLE
-#define PDC_MEM_GET_MEMORY_SYSTEM_TABLES_SIZE	131
-#define PDC_MEM_GET_MEMORY_SYSTEM_TABLES	132
-#define PDC_MEM_GET_PHYSICAL_LOCATION_FROM_MEMORY_ADDRESS 133
-
-#define PDC_MEM_RET_SBE_REPLACED	5	/* PDC_MEM return values */
-#define PDC_MEM_RET_DUPLICATE_ENTRY	4
-#define PDC_MEM_RET_BUF_SIZE_SMALL	1
-#define PDC_MEM_RET_PDT_FULL		-11
-#define PDC_MEM_RET_INVALID_PHYSICAL_LOCATION ~0ULL
-
-#define PDC_PSW		21		/* Get/Set default System Mask  */
-#define PDC_PSW_MASK		0	/* Return mask                  */
-#define PDC_PSW_GET_DEFAULTS	1	/* Return defaults              */
-#define PDC_PSW_SET_DEFAULTS	2	/* Set default                  */
-#define PDC_PSW_ENDIAN_BIT	1	/* set for big endian           */
-#define PDC_PSW_WIDE_BIT	2	/* set for wide mode            */ 
-
-#define PDC_SYSTEM_MAP	22		/* find system modules		*/
-#define PDC_FIND_MODULE 	0
-#define PDC_FIND_ADDRESS	1
-#define PDC_TRANSLATE_PATH	2
-
-#define PDC_SOFT_POWER	23		/* soft power switch		*/
-#define PDC_SOFT_POWER_INFO	0	/* return info about the soft power switch */
-#define PDC_SOFT_POWER_ENABLE	1	/* enable/disable soft power switch */
-
-
-/* HVERSION dependent */
-
-/* The PDC_MEM_MAP calls */
-#define PDC_MEM_MAP	128		/* on s700: return page info	*/
-#define PDC_MEM_MAP_HPA		0	/* returns hpa of a module	*/
-
-#define PDC_EEPROM	129		/* EEPROM access		*/
-#define PDC_EEPROM_READ_WORD	0
-#define PDC_EEPROM_WRITE_WORD	1
-#define PDC_EEPROM_READ_BYTE	2
-#define PDC_EEPROM_WRITE_BYTE	3
-#define PDC_EEPROM_EEPROM_PASSWORD -1000
-
-#define PDC_NVM		130		/* NVM (non-volatile memory) access */
-#define PDC_NVM_READ_WORD	0
-#define PDC_NVM_WRITE_WORD	1
-#define PDC_NVM_READ_BYTE	2
-#define PDC_NVM_WRITE_BYTE	3
-
-#define PDC_SEED_ERROR	132		/* (sprockets)			*/
-
-#define PDC_IO		135		/* log error info, reset IO system */
-#define PDC_IO_READ_AND_CLEAR_ERRORS	0
-#define PDC_IO_RESET			1
-#define PDC_IO_RESET_DEVICES		2
-/* sets bits 6&7 (little endian) of the HcControl Register */
-#define PDC_IO_USB_SUSPEND	0xC000000000000000
-#define PDC_IO_EEPROM_IO_ERR_TABLE_FULL	-5	/* return value */
-#define PDC_IO_NO_SUSPEND		-6	/* return value */
-
-#define PDC_BROADCAST_RESET 136		/* reset all processors		*/
-#define PDC_DO_RESET		0	/* option: perform a broadcast reset */
-#define PDC_DO_FIRM_TEST_RESET	1	/* Do broadcast reset with bitmap */
-#define PDC_BR_RECONFIGURATION	2	/* reset w/reconfiguration	*/
-#define PDC_FIRM_TEST_MAGIC	0xab9ec36fUL    /* for this reboot only	*/
-
-#define PDC_LAN_STATION_ID 138		/* Hversion dependent mechanism for */
-#define PDC_LAN_STATION_ID_READ	0	/* getting the lan station address  */
-
-#define	PDC_LAN_STATION_ID_SIZE	6
-
-#define PDC_CHECK_RANGES 139		/* (sprockets)			*/
-
-#define PDC_NV_SECTIONS	141		/* (sprockets)			*/
-
-#define PDC_PERFORMANCE	142		/* performance monitoring	*/
-
-#define PDC_SYSTEM_INFO	143		/* system information		*/
-#define PDC_SYSINFO_RETURN_INFO_SIZE	0
-#define PDC_SYSINFO_RRETURN_SYS_INFO	1
-#define PDC_SYSINFO_RRETURN_ERRORS	2
-#define PDC_SYSINFO_RRETURN_WARNINGS	3
-#define PDC_SYSINFO_RETURN_REVISIONS	4
-#define PDC_SYSINFO_RRETURN_DIAGNOSE	5
-#define PDC_SYSINFO_RRETURN_HV_DIAGNOSE	1005
-
-#define PDC_RDR		144		/* (sprockets)			*/
-#define PDC_RDR_READ_BUFFER	0
-#define PDC_RDR_READ_SINGLE	1
-#define PDC_RDR_WRITE_SINGLE	2
-
-#define PDC_INTRIGUE	145 		/* (sprockets)			*/
-#define PDC_INTRIGUE_WRITE_BUFFER 	 0
-#define PDC_INTRIGUE_GET_SCRATCH_BUFSIZE 1
-#define PDC_INTRIGUE_START_CPU_COUNTERS	 2
-#define PDC_INTRIGUE_STOP_CPU_COUNTERS	 3
-
-#define PDC_STI		146 		/* STI access			*/
-/* same as PDC_PCI_XXX values (see below) */
-
-/* Legacy PDC definitions for same stuff */
-#define PDC_PCI_INDEX	147
-#define PDC_PCI_INTERFACE_INFO		0
-#define PDC_PCI_SLOT_INFO		1
-#define PDC_PCI_INFLIGHT_BYTES		2
-#define PDC_PCI_READ_CONFIG		3
-#define PDC_PCI_WRITE_CONFIG		4
-#define PDC_PCI_READ_PCI_IO		5
-#define PDC_PCI_WRITE_PCI_IO		6
-#define PDC_PCI_READ_CONFIG_DELAY	7
-#define PDC_PCI_UPDATE_CONFIG_DELAY	8
-#define PDC_PCI_PCI_PATH_TO_PCI_HPA	9
-#define PDC_PCI_PCI_HPA_TO_PCI_PATH	10
-#define PDC_PCI_PCI_PATH_TO_PCI_BUS	11
-#define PDC_PCI_PCI_RESERVED		12
-#define PDC_PCI_PCI_INT_ROUTE_SIZE	13
-#define PDC_PCI_GET_INT_TBL_SIZE	PDC_PCI_PCI_INT_ROUTE_SIZE
-#define PDC_PCI_PCI_INT_ROUTE		14
-#define PDC_PCI_GET_INT_TBL		PDC_PCI_PCI_INT_ROUTE 
-#define PDC_PCI_READ_MON_TYPE		15
-#define PDC_PCI_WRITE_MON_TYPE		16
-
-
-/* Get SCSI Interface Card info:  SDTR, SCSI ID, mode (SE vs LVD) */
-#define PDC_INITIATOR	163
-#define PDC_GET_INITIATOR	0
-#define PDC_SET_INITIATOR	1
-#define PDC_DELETE_INITIATOR	2
-#define PDC_RETURN_TABLE_SIZE	3
-#define PDC_RETURN_TABLE	4
-
-#define PDC_LINK	165 		/* (sprockets)			*/
-#define PDC_LINK_PCI_ENTRY_POINTS	0  /* list (Arg1) = 0 */
-#define PDC_LINK_USB_ENTRY_POINTS	1  /* list (Arg1) = 1 */
-
-/* cl_class
- * page 3-33 of IO-Firmware ARS
- * IODC ENTRY_INIT(Search first) RET[1]
- */
-#define	CL_NULL		0	/* invalid */
-#define	CL_RANDOM	1	/* random access (as disk) */
-#define	CL_SEQU		2	/* sequential access (as tape) */
-#define	CL_DUPLEX	7	/* full-duplex point-to-point (RS-232, Net) */
-#define	CL_KEYBD	8	/* half-duplex console (HIL Keyboard) */
-#define	CL_DISPL	9	/* half-duplex console (display) */
-#define	CL_FC		10	/* FiberChannel access media */
-
-/* IODC ENTRY_INIT() */
-#define ENTRY_INIT_SRCH_FRST	2
-#define ENTRY_INIT_SRCH_NEXT	3
-#define ENTRY_INIT_MOD_DEV	4
-#define ENTRY_INIT_DEV		5
-#define ENTRY_INIT_MOD		6
-#define ENTRY_INIT_MSG		9
-
-/* IODC ENTRY_IO() */
-#define ENTRY_IO_BOOTIN		0
-#define ENTRY_IO_BOOTOUT	1
-#define ENTRY_IO_CIN		2
-#define ENTRY_IO_COUT		3
-#define ENTRY_IO_CLOSE		4
-#define ENTRY_IO_GETMSG		9
-#define ENTRY_IO_BBLOCK_IN	16
-#define ENTRY_IO_BBLOCK_OUT	17
-
-/* IODC ENTRY_SPA() */
-
-/* IODC ENTRY_CONFIG() */
-
-/* IODC ENTRY_TEST() */
-
-/* IODC ENTRY_TLB() */
-
-/* constants for OS (NVM...) */
-#define OS_ID_NONE		0	/* Undefined OS ID	*/
-#define OS_ID_HPUX		1	/* HP-UX OS		*/
-#define OS_ID_MPEXL		2	/* MPE XL OS		*/
-#define OS_ID_OSF		3	/* OSF OS		*/
-#define OS_ID_HPRT		4	/* HP-RT OS		*/
-#define OS_ID_NOVEL		5	/* NOVELL OS		*/
-#define OS_ID_LINUX		6	/* Linux		*/
-
-
-/* constants for PDC_CHASSIS */
-#define OSTAT_OFF		0
-#define OSTAT_FLT		1 
-#define OSTAT_TEST		2
-#define OSTAT_INIT		3
-#define OSTAT_SHUT		4
-#define OSTAT_WARN		5
-#define OSTAT_RUN		6
-#define OSTAT_ON		7
-
-/* Page Zero constant offsets used by the HPMC handler */
-#define BOOT_CONSOLE_HPA_OFFSET  0x3c0
-#define BOOT_CONSOLE_SPA_OFFSET  0x3c4
-#define BOOT_CONSOLE_PATH_OFFSET 0x3a8
-
-#if !defined(__ASSEMBLY__)
-#ifdef __KERNEL__
-
-#include <linux/types.h>
-
-extern int pdc_type;
-
-/* Values for pdc_type */
-#define PDC_TYPE_ILLEGAL	-1
-#define PDC_TYPE_PAT		 0 /* 64-bit PAT-PDC */
-#define PDC_TYPE_SYSTEM_MAP	 1 /* 32-bit, but supports PDC_SYSTEM_MAP */
-#define PDC_TYPE_SNAKE		 2 /* Doesn't support SYSTEM_MAP */
-
-struct pdc_chassis_info {       /* for PDC_CHASSIS_INFO */
-	unsigned long actcnt;   /* actual number of bytes returned */
-	unsigned long maxcnt;   /* maximum number of bytes that could be returned */
-};
-
-struct pdc_coproc_cfg {         /* for PDC_COPROC_CFG */
-        unsigned long ccr_functional;
-        unsigned long ccr_present;
-        unsigned long revision;
-        unsigned long model;
-};
-
-struct pdc_model {		/* for PDC_MODEL */
-	unsigned long hversion;
-	unsigned long sversion;
-	unsigned long hw_id;
-	unsigned long boot_id;
-	unsigned long sw_id;
-	unsigned long sw_cap;
-	unsigned long arch_rev;
-	unsigned long pot_key;
-	unsigned long curr_key;
-};
-
-struct pdc_cache_cf {		/* for PDC_CACHE  (I/D-caches) */
-    unsigned long
-#ifdef CONFIG_64BIT
-		cc_padW:32,
-#endif
-		cc_alias: 4,	/* alias boundaries for virtual addresses   */
-		cc_block: 4,	/* to determine most efficient stride */
-		cc_line	: 3,	/* maximum amount written back as a result of store (multiple of 16 bytes) */
-		cc_shift: 2,	/* how much to shift cc_block left */
-		cc_wt	: 1,	/* 0 = WT-Dcache, 1 = WB-Dcache */
-		cc_sh	: 2,	/* 0 = separate I/D-cache, else shared I/D-cache */
-		cc_cst  : 3,	/* 0 = incoherent D-cache, 1=coherent D-cache */
-		cc_pad1 : 10,	/* reserved */
-		cc_hv   : 3;	/* hversion dependent */
-};
-
-struct pdc_tlb_cf {		/* for PDC_CACHE (I/D-TLB's) */
-    unsigned long tc_pad0:12,	/* reserved */
-#ifdef CONFIG_64BIT
-		tc_padW:32,
-#endif
-		tc_sh	: 2,	/* 0 = separate I/D-TLB, else shared I/D-TLB */
-		tc_hv   : 1,	/* HV */
-		tc_page : 1,	/* 0 = 2K page-size-machine, 1 = 4k page size */
-		tc_cst  : 3,	/* 0 = incoherent operations, else coherent operations */
-		tc_aid  : 5,	/* ITLB: width of access ids of processor (encoded!) */
-		tc_pad1 : 8;	/* ITLB: width of space-registers (encoded) */
-};
-
-struct pdc_cache_info {		/* main-PDC_CACHE-structure (caches & TLB's) */
-	/* I-cache */
-	unsigned long	ic_size;	/* size in bytes */
-	struct pdc_cache_cf ic_conf;	/* configuration */
-	unsigned long	ic_base;	/* base-addr */
-	unsigned long	ic_stride;
-	unsigned long	ic_count;
-	unsigned long	ic_loop;
-	/* D-cache */
-	unsigned long	dc_size;	/* size in bytes */
-	struct pdc_cache_cf dc_conf;	/* configuration */
-	unsigned long	dc_base;	/* base-addr */
-	unsigned long	dc_stride;
-	unsigned long	dc_count;
-	unsigned long	dc_loop;
-	/* Instruction-TLB */
-	unsigned long	it_size;	/* number of entries in I-TLB */
-	struct pdc_tlb_cf it_conf;	/* I-TLB-configuration */
-	unsigned long	it_sp_base;
-	unsigned long	it_sp_stride;
-	unsigned long	it_sp_count;
-	unsigned long	it_off_base;
-	unsigned long	it_off_stride;
-	unsigned long	it_off_count;
-	unsigned long	it_loop;
-	/* data-TLB */
-	unsigned long	dt_size;	/* number of entries in D-TLB */
-	struct pdc_tlb_cf dt_conf;	/* D-TLB-configuration */
-	unsigned long	dt_sp_base;
-	unsigned long	dt_sp_stride;
-	unsigned long	dt_sp_count;
-	unsigned long	dt_off_base;
-	unsigned long	dt_off_stride;
-	unsigned long	dt_off_count;
-	unsigned long	dt_loop;
-};
-
-#if 0
-/* If you start using the next struct, you'll have to adjust it to
- * work with 64-bit firmware I think -PB
- */
-struct pdc_iodc {     /* PDC_IODC */
-	unsigned char   hversion_model;
-	unsigned char 	hversion;
-	unsigned char 	spa;
-	unsigned char 	type;
-	unsigned int	sversion_rev:4;
-	unsigned int	sversion_model:19;
-	unsigned int	sversion_opt:8;
-	unsigned char	rev;
-	unsigned char	dep;
-	unsigned char	features;
-	unsigned char	pad1;
-	unsigned int	checksum:16;
-	unsigned int	length:16;
-	unsigned int    pad[15];
-} __attribute__((aligned(8))) ;
-#endif
-
-#ifndef CONFIG_PA20
-/* no BLTBs in pa2.0 processors */
-struct pdc_btlb_info_range {
-	__u8 res00;
-	__u8 num_i;
-	__u8 num_d;
-	__u8 num_comb;
-};
-
-struct pdc_btlb_info {	/* PDC_BLOCK_TLB, return of PDC_BTLB_INFO */
-	unsigned int min_size;	/* minimum size of BTLB in pages */
-	unsigned int max_size;	/* maximum size of BTLB in pages */
-	struct pdc_btlb_info_range fixed_range_info;
-	struct pdc_btlb_info_range variable_range_info;
-};
-
-#endif /* !CONFIG_PA20 */
-
-#ifdef CONFIG_64BIT
-struct pdc_memory_table_raddr { /* PDC_MEM/PDC_MEM_TABLE (return info) */
-	unsigned long entries_returned;
-	unsigned long entries_total;
-};
-
-struct pdc_memory_table {       /* PDC_MEM/PDC_MEM_TABLE (arguments) */
-	unsigned long paddr;
-	unsigned int  pages;
-	unsigned int  reserved;
-};
-#endif /* CONFIG_64BIT */
-
-struct pdc_system_map_mod_info { /* PDC_SYSTEM_MAP/FIND_MODULE */
-	unsigned long mod_addr;
-	unsigned long mod_pgs;
-	unsigned long add_addrs;
-};
-
-struct pdc_system_map_addr_info { /* PDC_SYSTEM_MAP/FIND_ADDRESS */
-	unsigned long mod_addr;
-	unsigned long mod_pgs;
-};
-
-struct pdc_initiator { /* PDC_INITIATOR */
-	int host_id;
-	int factor;
-	int width;
-	int mode;
-};
-
-struct hardware_path {
-	char  flags;	/* see bit definitions below */
-	char  bc[6];	/* Bus Converter routing info to a specific */
-			/* I/O adaptor (< 0 means none, > 63 resvd) */
-	char  mod;	/* fixed field of specified module */
-};
-
-/*
- * Device path specifications used by PDC.
- */
-struct pdc_module_path {
-	struct hardware_path path;
-	unsigned int layers[6]; /* device-specific info (ctlr #, unit # ...) */
-};
-
-#ifndef CONFIG_PA20
-/* Only used on some pre-PA2.0 boxes */
-struct pdc_memory_map {		/* PDC_MEMORY_MAP */
-	unsigned long hpa;	/* mod's register set address */
-	unsigned long more_pgs;	/* number of additional I/O pgs */
-};
-#endif
-
-struct pdc_tod {
-	unsigned long tod_sec; 
-	unsigned long tod_usec;
-};
-
-/* architected results from PDC_PIM/transfer hpmc on a PA1.1 machine */
-
-struct pdc_hpmc_pim_11 { /* PDC_PIM */
-	__u32 gr[32];
-	__u32 cr[32];
-	__u32 sr[8];
-	__u32 iasq_back;
-	__u32 iaoq_back;
-	__u32 check_type;
-	__u32 cpu_state;
-	__u32 rsvd1;
-	__u32 cache_check;
-	__u32 tlb_check;
-	__u32 bus_check;
-	__u32 assists_check;
-	__u32 rsvd2;
-	__u32 assist_state;
-	__u32 responder_addr;
-	__u32 requestor_addr;
-	__u32 path_info;
-	__u64 fr[32];
-};
-
-/*
- * architected results from PDC_PIM/transfer hpmc on a PA2.0 machine
- *
- * Note that PDC_PIM doesn't care whether or not wide mode was enabled
- * so the results are different on  PA1.1 vs. PA2.0 when in narrow mode.
- *
- * Note also that there are unarchitected results available, which
- * are hversion dependent. Do a "ser pim 0 hpmc" after rebooting, since
- * the firmware is probably the best way of printing hversion dependent
- * data.
- */
-
-struct pdc_hpmc_pim_20 { /* PDC_PIM */
-	__u64 gr[32];
-	__u64 cr[32];
-	__u64 sr[8];
-	__u64 iasq_back;
-	__u64 iaoq_back;
-	__u32 check_type;
-	__u32 cpu_state;
-	__u32 cache_check;
-	__u32 tlb_check;
-	__u32 bus_check;
-	__u32 assists_check;
-	__u32 assist_state;
-	__u32 path_info;
-	__u64 responder_addr;
-	__u64 requestor_addr;
-	__u64 fr[32];
-};
-
-void pdc_console_init(void);	/* in pdc_console.c */
-void pdc_console_restart(void);
-
-void setup_pdc(void);		/* in inventory.c */
-
-/* wrapper-functions from pdc.c */
-
-int pdc_add_valid(unsigned long address);
-int pdc_chassis_info(struct pdc_chassis_info *chassis_info, void *led_info, unsigned long len);
-int pdc_chassis_disp(unsigned long disp);
-int pdc_chassis_warn(unsigned long *warn);
-int pdc_coproc_cfg(struct pdc_coproc_cfg *pdc_coproc_info);
-int pdc_iodc_read(unsigned long *actcnt, unsigned long hpa, unsigned int index,
-		  void *iodc_data, unsigned int iodc_data_size);
-int pdc_system_map_find_mods(struct pdc_system_map_mod_info *pdc_mod_info,
-			     struct pdc_module_path *mod_path, long mod_index);
-int pdc_system_map_find_addrs(struct pdc_system_map_addr_info *pdc_addr_info,
-			      long mod_index, long addr_index);
-int pdc_model_info(struct pdc_model *model);
-int pdc_model_sysmodel(char *name);
-int pdc_model_cpuid(unsigned long *cpu_id);
-int pdc_model_versions(unsigned long *versions, int id);
-int pdc_model_capabilities(unsigned long *capabilities);
-int pdc_cache_info(struct pdc_cache_info *cache);
-int pdc_spaceid_bits(unsigned long *space_bits);
-#ifndef CONFIG_PA20
-int pdc_btlb_info(struct pdc_btlb_info *btlb);
-int pdc_mem_map_hpa(struct pdc_memory_map *r_addr, struct pdc_module_path *mod_path);
-#endif /* !CONFIG_PA20 */
-int pdc_lan_station_id(char *lan_addr, unsigned long net_hpa);
-
-int pdc_stable_read(unsigned long staddr, void *memaddr, unsigned long count);
-int pdc_stable_write(unsigned long staddr, void *memaddr, unsigned long count);
-int pdc_stable_get_size(unsigned long *size);
-int pdc_stable_verify_contents(void);
-int pdc_stable_initialize(void);
-
-int pdc_pci_irt_size(unsigned long *num_entries, unsigned long hpa);
-int pdc_pci_irt(unsigned long num_entries, unsigned long hpa, void *tbl);
-
-int pdc_get_initiator(struct hardware_path *, struct pdc_initiator *);
-int pdc_tod_read(struct pdc_tod *tod);
-int pdc_tod_set(unsigned long sec, unsigned long usec);
-
-#ifdef CONFIG_64BIT
-int pdc_mem_mem_table(struct pdc_memory_table_raddr *r_addr,
-		struct pdc_memory_table *tbl, unsigned long entries);
-#endif
-
-void set_firmware_width(void);
-int pdc_do_firm_test_reset(unsigned long ftc_bitmap);
-int pdc_do_reset(void);
-int pdc_soft_power_info(unsigned long *power_reg);
-int pdc_soft_power_button(int sw_control);
-void pdc_io_reset(void);
-void pdc_io_reset_devices(void);
-int pdc_iodc_getc(void);
-int pdc_iodc_print(const unsigned char *str, unsigned count);
-
-void pdc_emergency_unlock(void);
-int pdc_sti_call(unsigned long func, unsigned long flags,
-                 unsigned long inptr, unsigned long outputr,
-                 unsigned long glob_cfg);
-
-static inline char * os_id_to_string(u16 os_id) {
-	switch(os_id) {
-	case OS_ID_NONE:	return "No OS";
-	case OS_ID_HPUX:	return "HP-UX";
-	case OS_ID_MPEXL:	return "MPE-iX";
-	case OS_ID_OSF:		return "OSF";
-	case OS_ID_HPRT:	return "HP-RT";
-	case OS_ID_NOVEL:	return "Novell Netware";
-	case OS_ID_LINUX:	return "Linux";
-	default:	return "Unknown";
-	}
-}
-
-#endif /* __KERNEL__ */
-
-#define PAGE0   ((struct zeropage *)__PAGE_OFFSET)
-
-/* DEFINITION OF THE ZERO-PAGE (PAG0) */
-/* based on work by Jason Eckhardt (jason@equator.com) */
-
-/* flags of the device_path */
-#define	PF_AUTOBOOT	0x80
-#define	PF_AUTOSEARCH	0x40
-#define	PF_TIMER	0x0F
-
-struct device_path {		/* page 1-69 */
-	unsigned char flags;	/* flags see above! */
-	unsigned char bc[6];	/* bus converter routing info */
-	unsigned char mod;
-	unsigned int  layers[6];/* device-specific layer-info */
-} __attribute__((aligned(8))) ;
-
-struct pz_device {
-	struct	device_path dp;	/* see above */
-	/* struct	iomod *hpa; */
-	unsigned int hpa;	/* HPA base address */
-	/* char	*spa; */
-	unsigned int spa;	/* SPA base address */
-	/* int	(*iodc_io)(struct iomod*, ...); */
-	unsigned int iodc_io;	/* device entry point */
-	short	pad;		/* reserved */
-	unsigned short cl_class;/* see below */
-} __attribute__((aligned(8))) ;
-
-struct zeropage {
-	/* [0x000] initialize vectors (VEC) */
-	unsigned int	vec_special;		/* must be zero */
-	/* int	(*vec_pow_fail)(void);*/
-	unsigned int	vec_pow_fail; /* power failure handler */
-	/* int	(*vec_toc)(void); */
-	unsigned int	vec_toc;
-	unsigned int	vec_toclen;
-	/* int	(*vec_rendz)(void); */
-	unsigned int vec_rendz;
-	int	vec_pow_fail_flen;
-	int	vec_pad[10];		
-	
-	/* [0x040] reserved processor dependent */
-	int	pad0[112];
-
-	/* [0x200] reserved */
-	int	pad1[84];
-
-	/* [0x350] memory configuration (MC) */
-	int	memc_cont;		/* contiguous mem size (bytes) */
-	int	memc_phsize;		/* physical memory size */
-	int	memc_adsize;		/* additional mem size, bytes of SPA space used by PDC */
-	unsigned int mem_pdc_hi;	/* used for 64-bit */
-
-	/* [0x360] various parameters for the boot-CPU */
-	/* unsigned int *mem_booterr[8]; */
-	unsigned int mem_booterr[8];	/* ptr to boot errors */
-	unsigned int mem_free;		/* first location, where OS can be loaded */
-	/* struct iomod *mem_hpa; */
-	unsigned int mem_hpa;		/* HPA of the boot-CPU */
-	/* int (*mem_pdc)(int, ...); */
-	unsigned int mem_pdc;		/* PDC entry point */
-	unsigned int mem_10msec;	/* number of clock ticks in 10msec */
-
-	/* [0x390] initial memory module (IMM) */
-	/* struct iomod *imm_hpa; */
-	unsigned int imm_hpa;		/* HPA of the IMM */
-	int	imm_soft_boot;		/* 0 = was hard boot, 1 = was soft boot */
-	unsigned int	imm_spa_size;		/* SPA size of the IMM in bytes */
-	unsigned int	imm_max_mem;		/* bytes of mem in IMM */
-
-	/* [0x3A0] boot console, display device and keyboard */
-	struct pz_device mem_cons;	/* description of console device */
-	struct pz_device mem_boot;	/* description of boot device */
-	struct pz_device mem_kbd;	/* description of keyboard device */
-
-	/* [0x430] reserved */
-	int	pad430[116];
-
-	/* [0x600] processor dependent */
-	__u32	pad600[1];
-	__u32	proc_sti;		/* pointer to STI ROM */
-	__u32	pad608[126];
-};
-
-#endif /* !defined(__ASSEMBLY__) */
-
-#endif /* _PARISC_PDC_H */
diff --git a/include/asm-parisc/pdc_chassis.h b/include/asm-parisc/pdc_chassis.h
deleted file mode 100644
index a609273dc6bf..000000000000
--- a/include/asm-parisc/pdc_chassis.h
+++ /dev/null
@@ -1,381 +0,0 @@
-/*
- *	include/asm-parisc/pdc_chassis.h
- *
- *	Copyright (C) 2002 Laurent Canet <canetl@esiee.fr>
- *	Copyright (C) 2002 Thibaut Varene <varenet@parisc-linux.org>
- *
- *
- *      This program is free software; you can redistribute it and/or modify
- *      it under the terms of the GNU General Public License, version 2, as
- *      published by the Free Software Foundation.
- *      
- *      This program is distributed in the hope that it will be useful,
- *      but WITHOUT ANY WARRANTY; without even the implied warranty of
- *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *      GNU General Public License for more details.
- *      
- *      You should have received a copy of the GNU General Public License
- *      along with this program; if not, write to the Free Software
- *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *      TODO:	- handle processor number on SMP systems (Reporting Entity ID)
- *      	- handle message ID
- *      	- handle timestamps
- */
- 
-
-#ifndef _PARISC_PDC_CHASSIS_H
-#define _PARISC_PDC_CHASSIS_H
-
-/*
- * ----------
- * Prototypes
- * ----------
- */
-
-int pdc_chassis_send_status(int message);
-void parisc_pdc_chassis_init(void);
-
-
-/*
- * -----------------
- * Direct call names
- * -----------------
- * They setup everything for you, the Log message and the corresponding LED state
- */
-
-#define PDC_CHASSIS_DIRECT_BSTART	0
-#define PDC_CHASSIS_DIRECT_BCOMPLETE	1
-#define PDC_CHASSIS_DIRECT_SHUTDOWN	2
-#define PDC_CHASSIS_DIRECT_PANIC	3
-#define PDC_CHASSIS_DIRECT_HPMC		4
-#define PDC_CHASSIS_DIRECT_LPMC		5
-#define PDC_CHASSIS_DIRECT_DUMP		6	/* not yet implemented */
-#define PDC_CHASSIS_DIRECT_OOPS		7	/* not yet implemented */
-
-
-/*
- * ------------
- * LEDs control
- * ------------
- * Set the three LEDs -- Run, Attn, and Fault.
- */
-
-/* Old PDC LED control */
-#define PDC_CHASSIS_DISP_DATA(v)	((unsigned long)(v) << 17)
-
-/* 
- * Available PDC PAT LED states
- */
-
-#define PDC_CHASSIS_LED_RUN_OFF		(0ULL << 4)
-#define PDC_CHASSIS_LED_RUN_FLASH	(1ULL << 4)
-#define PDC_CHASSIS_LED_RUN_ON		(2ULL << 4)
-#define PDC_CHASSIS_LED_RUN_NC		(3ULL << 4)
-#define PDC_CHASSIS_LED_ATTN_OFF	(0ULL << 6)
-#define PDC_CHASSIS_LED_ATTN_FLASH	(1ULL << 6)
-#define PDC_CHASSIS_LED_ATTN_NC		(3ULL << 6)	/* ATTN ON is invalid */
-#define PDC_CHASSIS_LED_FAULT_OFF	(0ULL << 8)
-#define PDC_CHASSIS_LED_FAULT_FLASH	(1ULL << 8)
-#define PDC_CHASSIS_LED_FAULT_ON	(2ULL << 8)
-#define PDC_CHASSIS_LED_FAULT_NC	(3ULL << 8)
-#define PDC_CHASSIS_LED_VALID		(1ULL << 10)
-
-/* 
- * Valid PDC PAT LED states combinations
- */
-
-/* System running normally */
-#define PDC_CHASSIS_LSTATE_RUN_NORMAL	(PDC_CHASSIS_LED_RUN_ON		| \
-					 PDC_CHASSIS_LED_ATTN_OFF	| \
-					 PDC_CHASSIS_LED_FAULT_OFF	| \
-					 PDC_CHASSIS_LED_VALID		)
-/* System crashed and rebooted itself successfully */
-#define PDC_CHASSIS_LSTATE_RUN_CRASHREC	(PDC_CHASSIS_LED_RUN_ON		| \
-					 PDC_CHASSIS_LED_ATTN_OFF	| \
-					 PDC_CHASSIS_LED_FAULT_FLASH	| \
-					 PDC_CHASSIS_LED_VALID		)
-/* There was a system interruption that did not take the system down */
-#define PDC_CHASSIS_LSTATE_RUN_SYSINT	(PDC_CHASSIS_LED_RUN_ON		| \
-					 PDC_CHASSIS_LED_ATTN_FLASH	| \
-					 PDC_CHASSIS_LED_FAULT_OFF	| \
-					 PDC_CHASSIS_LED_VALID		)
-/* System running and unexpected reboot or non-critical error detected */
-#define PDC_CHASSIS_LSTATE_RUN_NCRIT	(PDC_CHASSIS_LED_RUN_ON		| \
-					 PDC_CHASSIS_LED_ATTN_FLASH	| \
-					 PDC_CHASSIS_LED_FAULT_FLASH	| \
-					 PDC_CHASSIS_LED_VALID		)
-/* Executing non-OS code */
-#define PDC_CHASSIS_LSTATE_NONOS	(PDC_CHASSIS_LED_RUN_FLASH	| \
-					 PDC_CHASSIS_LED_ATTN_OFF	| \
-					 PDC_CHASSIS_LED_FAULT_OFF	| \
-					 PDC_CHASSIS_LED_VALID		)
-/* Boot failed - Executing non-OS code */
-#define PDC_CHASSIS_LSTATE_NONOS_BFAIL	(PDC_CHASSIS_LED_RUN_FLASH	| \
-					 PDC_CHASSIS_LED_ATTN_OFF	| \
-					 PDC_CHASSIS_LED_FAULT_ON	| \
-					 PDC_CHASSIS_LED_VALID		)
-/* Unexpected reboot occurred - Executing non-OS code */
-#define PDC_CHASSIS_LSTATE_NONOS_UNEXP	(PDC_CHASSIS_LED_RUN_FLASH	| \
-					 PDC_CHASSIS_LED_ATTN_OFF	| \
-					 PDC_CHASSIS_LED_FAULT_FLASH	| \
-					 PDC_CHASSIS_LED_VALID		)
-/* Executing non-OS code - Non-critical error detected */
-#define PDC_CHASSIS_LSTATE_NONOS_NCRIT	(PDC_CHASSIS_LED_RUN_FLASH	| \
-					 PDC_CHASSIS_LED_ATTN_FLASH	| \
-					 PDC_CHASSIS_LED_FAULT_OFF	| \
-					 PDC_CHASSIS_LED_VALID		)
-/* Boot failed - Executing non-OS code - Non-critical error detected */
-#define PDC_CHASSIS_LSTATE_BFAIL_NCRIT	(PDC_CHASSIS_LED_RUN_FLASH	| \
-					 PDC_CHASSIS_LED_ATTN_FLASH	| \
-					 PDC_CHASSIS_LED_FAULT_ON	| \
-					 PDC_CHASSIS_LED_VALID		)
-/* Unexpected reboot/recovering - Executing non-OS code - Non-critical error detected */
-#define PDC_CHASSIS_LSTATE_UNEXP_NCRIT	(PDC_CHASSIS_LED_RUN_FLASH	| \
-					 PDC_CHASSIS_LED_ATTN_FLASH	| \
-					 PDC_CHASSIS_LED_FAULT_FLASH	| \
-					 PDC_CHASSIS_LED_VALID		)
-/* Cannot execute PDC */
-#define PDC_CHASSIS_LSTATE_CANNOT_PDC	(PDC_CHASSIS_LED_RUN_OFF	| \
-					 PDC_CHASSIS_LED_ATTN_OFF	| \
-					 PDC_CHASSIS_LED_FAULT_OFF	| \
-					 PDC_CHASSIS_LED_VALID		)
-/* Boot failed - OS not up - PDC has detected a failure that prevents boot */
-#define PDC_CHASSIS_LSTATE_FATAL_BFAIL	(PDC_CHASSIS_LED_RUN_OFF	| \
-					 PDC_CHASSIS_LED_ATTN_OFF	| \
-					 PDC_CHASSIS_LED_FAULT_ON	| \
-					 PDC_CHASSIS_LED_VALID		)
-/* No code running - Non-critical error detected (double fault situation) */
-#define PDC_CHASSIS_LSTATE_NOCODE_NCRIT	(PDC_CHASSIS_LED_RUN_OFF	| \
-					 PDC_CHASSIS_LED_ATTN_FLASH	| \
-					 PDC_CHASSIS_LED_FAULT_OFF	| \
-					 PDC_CHASSIS_LED_VALID		)
-/* Boot failed - OS not up - Fatal failure detected - Non-critical error detected */
-#define PDC_CHASSIS_LSTATE_FATAL_NCRIT	(PDC_CHASSIS_LED_RUN_OFF	| \
-					 PDC_CHASSIS_LED_ATTN_FLASH	| \
-					 PDC_CHASSIS_LED_FAULT_ON	| \
-					 PDC_CHASSIS_LED_VALID		)
-/* All other states are invalid */
-
-
-/*
- * --------------
- * PDC Log events
- * --------------
- * Here follows bits needed to fill up the log event sent to PDC_CHASSIS
- * The log message contains: Alert level, Source, Source detail,
- * Source ID, Problem detail, Caller activity, Activity status, 
- * Caller subactivity, Reporting entity type, Reporting entity ID,
- * Data type, Unique message ID and EOM. 
- */
-
-/* Alert level */
-#define PDC_CHASSIS_ALERT_FORWARD	(0ULL << 36)	/* no failure detected */
-#define PDC_CHASSIS_ALERT_SERPROC	(1ULL << 36)	/* service proc - no failure */
-#define PDC_CHASSIS_ALERT_NURGENT	(2ULL << 36)	/* non-urgent operator attn */
-#define PDC_CHASSIS_ALERT_BLOCKED	(3ULL << 36)	/* system blocked */
-#define PDC_CHASSIS_ALERT_CONF_CHG	(4ULL << 36)	/* unexpected configuration change */
-#define PDC_CHASSIS_ALERT_ENV_PB	(5ULL << 36)	/* boot possible, environmental pb */
-#define PDC_CHASSIS_ALERT_PENDING	(6ULL << 36)	/* boot possible, pending failure */
-#define PDC_CHASSIS_ALERT_PERF_IMP	(8ULL << 36)	/* boot possible, performance impaired */
-#define PDC_CHASSIS_ALERT_FUNC_IMP	(10ULL << 36)	/* boot possible, functionality impaired */
-#define PDC_CHASSIS_ALERT_SOFT_FAIL	(12ULL << 36)	/* software failure */
-#define PDC_CHASSIS_ALERT_HANG		(13ULL << 36)	/* system hang */
-#define PDC_CHASSIS_ALERT_ENV_FATAL	(14ULL << 36)	/* fatal power or environmental pb */
-#define PDC_CHASSIS_ALERT_HW_FATAL	(15ULL << 36)	/* fatal hardware problem */
-
-/* Source */
-#define PDC_CHASSIS_SRC_NONE		(0ULL << 28)	/* unknown, no source stated */
-#define PDC_CHASSIS_SRC_PROC		(1ULL << 28)	/* processor */
-/* For later use ? */
-#define PDC_CHASSIS_SRC_PROC_CACHE	(2ULL << 28)	/* processor cache*/
-#define PDC_CHASSIS_SRC_PDH		(3ULL << 28)	/* processor dependent hardware */
-#define PDC_CHASSIS_SRC_PWR		(4ULL << 28)	/* power */
-#define PDC_CHASSIS_SRC_FAB		(5ULL << 28)	/* fabric connector */
-#define PDC_CHASSIS_SRC_PLATi		(6ULL << 28)	/* platform */
-#define PDC_CHASSIS_SRC_MEM		(7ULL << 28)	/* memory */
-#define PDC_CHASSIS_SRC_IO		(8ULL << 28)	/* I/O */
-#define PDC_CHASSIS_SRC_CELL		(9ULL << 28)	/* cell */
-#define PDC_CHASSIS_SRC_PD		(10ULL << 28)	/* protected domain */
-
-/* Source detail field */
-#define PDC_CHASSIS_SRC_D_PROC		(1ULL << 24)	/* processor general */
-
-/* Source ID - platform dependent */
-#define PDC_CHASSIS_SRC_ID_UNSPEC	(0ULL << 16)
-
-/* Problem detail - problem source dependent */
-#define PDC_CHASSIS_PB_D_PROC_NONE	(0ULL << 32)	/* no problem detail */
-#define PDC_CHASSIS_PB_D_PROC_TIMEOUT	(4ULL << 32)	/* timeout */
-
-/* Caller activity */
-#define PDC_CHASSIS_CALL_ACT_HPUX_BL	(7ULL << 12)	/* Boot Loader */
-#define PDC_CHASSIS_CALL_ACT_HPUX_PD	(8ULL << 12)	/* SAL_PD activities */
-#define PDC_CHASSIS_CALL_ACT_HPUX_EVENT	(9ULL << 12)	/* SAL_EVENTS activities */
-#define PDC_CHASSIS_CALL_ACT_HPUX_IO	(10ULL << 12)	/* SAL_IO activities */
-#define PDC_CHASSIS_CALL_ACT_HPUX_PANIC	(11ULL << 12)	/* System panic */
-#define PDC_CHASSIS_CALL_ACT_HPUX_INIT	(12ULL << 12)	/* System initialization */
-#define PDC_CHASSIS_CALL_ACT_HPUX_SHUT	(13ULL << 12)	/* System shutdown */
-#define PDC_CHASSIS_CALL_ACT_HPUX_WARN	(14ULL << 12)	/* System warning */
-#define PDC_CHASSIS_CALL_ACT_HPUX_DU	(15ULL << 12)	/* Display_Activity() update */
-
-/* Activity status - implementation dependent */
-#define PDC_CHASSIS_ACT_STATUS_UNSPEC	(0ULL << 0)
-
-/* Caller subactivity - implementation dependent */
-/* FIXME: other subactivities ? */
-#define PDC_CHASSIS_CALL_SACT_UNSPEC	(0ULL << 4)	/* implementation dependent */
-
-/* Reporting entity type */
-#define PDC_CHASSIS_RET_GENERICOS	(12ULL << 52)	/* generic OSes */
-#define PDC_CHASSIS_RET_IA64_NT		(13ULL << 52)	/* IA-64 NT */
-#define PDC_CHASSIS_RET_HPUX		(14ULL << 52)	/* HP-UX */
-#define PDC_CHASSIS_RET_DIAG		(15ULL << 52)	/* offline diagnostics & utilities */
-
-/* Reporting entity ID */
-#define PDC_CHASSIS_REID_UNSPEC		(0ULL << 44)
-
-/* Data type */
-#define PDC_CHASSIS_DT_NONE		(0ULL << 59)	/* data field unused */
-/* For later use ? Do we need these ? */
-#define PDC_CHASSIS_DT_PHYS_ADDR	(1ULL << 59)	/* physical address */
-#define PDC_CHASSIS_DT_DATA_EXPECT	(2ULL << 59)	/* expected data */
-#define PDC_CHASSIS_DT_ACTUAL		(3ULL << 59)	/* actual data */
-#define PDC_CHASSIS_DT_PHYS_LOC		(4ULL << 59)	/* physical location */
-#define PDC_CHASSIS_DT_PHYS_LOC_EXT	(5ULL << 59)	/* physical location extension */
-#define PDC_CHASSIS_DT_TAG		(6ULL << 59)	/* tag */
-#define PDC_CHASSIS_DT_SYNDROME		(7ULL << 59)	/* syndrome */
-#define PDC_CHASSIS_DT_CODE_ADDR	(8ULL << 59)	/* code address */
-#define PDC_CHASSIS_DT_ASCII_MSG	(9ULL << 59)	/* ascii message */
-#define PDC_CHASSIS_DT_POST		(10ULL << 59)	/* POST code */
-#define PDC_CHASSIS_DT_TIMESTAMP	(11ULL << 59)	/* timestamp */
-#define PDC_CHASSIS_DT_DEV_STAT		(12ULL << 59)	/* device status */
-#define PDC_CHASSIS_DT_DEV_TYPE		(13ULL << 59)	/* device type */
-#define PDC_CHASSIS_DT_PB_DET		(14ULL << 59)	/* problem detail */
-#define PDC_CHASSIS_DT_ACT_LEV		(15ULL << 59)	/* activity level/timeout */
-#define PDC_CHASSIS_DT_SER_NUM		(16ULL << 59)	/* serial number */
-#define PDC_CHASSIS_DT_REV_NUM		(17ULL << 59)	/* revision number */
-#define PDC_CHASSIS_DT_INTERRUPT	(18ULL << 59)	/* interruption information */
-#define PDC_CHASSIS_DT_TEST_NUM		(19ULL << 59)	/* test number */
-#define PDC_CHASSIS_DT_STATE_CHG	(20ULL << 59)	/* major changes in system state */
-#define PDC_CHASSIS_DT_PROC_DEALLOC	(21ULL << 59)	/* processor deallocate */
-#define PDC_CHASSIS_DT_RESET		(30ULL << 59)	/* reset type and cause */
-#define PDC_CHASSIS_DT_PA_LEGACY	(31ULL << 59)	/* legacy PA hex chassis code */
-
-/* System states - part of major changes in system state data field */
-#define PDC_CHASSIS_SYSTATE_BSTART	(0ULL << 0)	/* boot start */
-#define PDC_CHASSIS_SYSTATE_BCOMP	(1ULL << 0)	/* boot complete */
-#define PDC_CHASSIS_SYSTATE_CHANGE	(2ULL << 0)	/* major change */
-#define PDC_CHASSIS_SYSTATE_LED		(3ULL << 0)	/* LED change */
-#define PDC_CHASSIS_SYSTATE_PANIC	(9ULL << 0)	/* OS Panic */
-#define PDC_CHASSIS_SYSTATE_DUMP	(10ULL << 0)	/* memory dump */
-#define PDC_CHASSIS_SYSTATE_HPMC	(11ULL << 0)	/* processing HPMC */
-#define PDC_CHASSIS_SYSTATE_HALT	(15ULL << 0)	/* system halted */
-
-/* Message ID */
-#define PDC_CHASSIS_MSG_ID		(0ULL << 40)	/* we do not handle msg IDs atm */
-
-/* EOM - separates log entries */
-#define PDC_CHASSIS_EOM_CLEAR		(0ULL << 43)
-#define PDC_CHASSIS_EOM_SET		(1ULL << 43)
-
-/*
- * Preformated well known messages
- */
-
-/* Boot started */
-#define PDC_CHASSIS_PMSG_BSTART		(PDC_CHASSIS_ALERT_SERPROC	| \
-					 PDC_CHASSIS_SRC_PROC		| \
-					 PDC_CHASSIS_SRC_D_PROC		| \
-					 PDC_CHASSIS_SRC_ID_UNSPEC	| \
-					 PDC_CHASSIS_PB_D_PROC_NONE	| \
-					 PDC_CHASSIS_CALL_ACT_HPUX_INIT	| \
-					 PDC_CHASSIS_ACT_STATUS_UNSPEC	| \
-					 PDC_CHASSIS_CALL_SACT_UNSPEC	| \
-					 PDC_CHASSIS_RET_HPUX		| \
-					 PDC_CHASSIS_REID_UNSPEC	| \
-					 PDC_CHASSIS_DT_STATE_CHG	| \
-					 PDC_CHASSIS_SYSTATE_BSTART	| \
-					 PDC_CHASSIS_MSG_ID		| \
-					 PDC_CHASSIS_EOM_SET		)
-
-/* Boot complete */
-#define PDC_CHASSIS_PMSG_BCOMPLETE	(PDC_CHASSIS_ALERT_SERPROC	| \
-					 PDC_CHASSIS_SRC_PROC		| \
-					 PDC_CHASSIS_SRC_D_PROC		| \
-					 PDC_CHASSIS_SRC_ID_UNSPEC	| \
-					 PDC_CHASSIS_PB_D_PROC_NONE	| \
-					 PDC_CHASSIS_CALL_ACT_HPUX_INIT	| \
-					 PDC_CHASSIS_ACT_STATUS_UNSPEC	| \
-					 PDC_CHASSIS_CALL_SACT_UNSPEC	| \
-					 PDC_CHASSIS_RET_HPUX		| \
-					 PDC_CHASSIS_REID_UNSPEC	| \
-					 PDC_CHASSIS_DT_STATE_CHG	| \
-					 PDC_CHASSIS_SYSTATE_BCOMP	| \
-					 PDC_CHASSIS_MSG_ID		| \
-					 PDC_CHASSIS_EOM_SET		)
-
-/* Shutdown */
-#define PDC_CHASSIS_PMSG_SHUTDOWN	(PDC_CHASSIS_ALERT_SERPROC	| \
-					 PDC_CHASSIS_SRC_PROC		| \
-					 PDC_CHASSIS_SRC_D_PROC		| \
-					 PDC_CHASSIS_SRC_ID_UNSPEC	| \
-					 PDC_CHASSIS_PB_D_PROC_NONE	| \
-					 PDC_CHASSIS_CALL_ACT_HPUX_SHUT	| \
-					 PDC_CHASSIS_ACT_STATUS_UNSPEC	| \
-					 PDC_CHASSIS_CALL_SACT_UNSPEC	| \
-					 PDC_CHASSIS_RET_HPUX		| \
-					 PDC_CHASSIS_REID_UNSPEC	| \
-					 PDC_CHASSIS_DT_STATE_CHG	| \
-					 PDC_CHASSIS_SYSTATE_HALT	| \
-					 PDC_CHASSIS_MSG_ID		| \
-					 PDC_CHASSIS_EOM_SET		)
-
-/* Panic */
-#define PDC_CHASSIS_PMSG_PANIC		(PDC_CHASSIS_ALERT_SOFT_FAIL	| \
-					 PDC_CHASSIS_SRC_PROC		| \
-					 PDC_CHASSIS_SRC_D_PROC		| \
-					 PDC_CHASSIS_SRC_ID_UNSPEC	| \
-					 PDC_CHASSIS_PB_D_PROC_NONE	| \
-					 PDC_CHASSIS_CALL_ACT_HPUX_PANIC| \
-					 PDC_CHASSIS_ACT_STATUS_UNSPEC	| \
-					 PDC_CHASSIS_CALL_SACT_UNSPEC	| \
-					 PDC_CHASSIS_RET_HPUX		| \
-					 PDC_CHASSIS_REID_UNSPEC	| \
-					 PDC_CHASSIS_DT_STATE_CHG	| \
-					 PDC_CHASSIS_SYSTATE_PANIC	| \
-					 PDC_CHASSIS_MSG_ID		| \
-					 PDC_CHASSIS_EOM_SET		)
-
-// FIXME: extrapolated data
-/* HPMC */
-#define PDC_CHASSIS_PMSG_HPMC		(PDC_CHASSIS_ALERT_CONF_CHG /*?*/	| \
-					 PDC_CHASSIS_SRC_PROC		| \
-					 PDC_CHASSIS_SRC_D_PROC		| \
-					 PDC_CHASSIS_SRC_ID_UNSPEC	| \
-					 PDC_CHASSIS_PB_D_PROC_NONE	| \
-					 PDC_CHASSIS_CALL_ACT_HPUX_WARN	| \
-					 PDC_CHASSIS_RET_HPUX		| \
-					 PDC_CHASSIS_DT_STATE_CHG	| \
-					 PDC_CHASSIS_SYSTATE_HPMC	| \
-					 PDC_CHASSIS_MSG_ID		| \
-					 PDC_CHASSIS_EOM_SET		)
-
-/* LPMC */
-#define PDC_CHASSIS_PMSG_LPMC		(PDC_CHASSIS_ALERT_BLOCKED /*?*/| \
-					 PDC_CHASSIS_SRC_PROC		| \
-					 PDC_CHASSIS_SRC_D_PROC		| \
-					 PDC_CHASSIS_SRC_ID_UNSPEC	| \
-					 PDC_CHASSIS_PB_D_PROC_NONE	| \
-					 PDC_CHASSIS_CALL_ACT_HPUX_WARN	| \
-					 PDC_CHASSIS_ACT_STATUS_UNSPEC	| \
-					 PDC_CHASSIS_CALL_SACT_UNSPEC	| \
-					 PDC_CHASSIS_RET_HPUX		| \
-					 PDC_CHASSIS_REID_UNSPEC	| \
-					 PDC_CHASSIS_DT_STATE_CHG	| \
-					 PDC_CHASSIS_SYSTATE_CHANGE	| \
-					 PDC_CHASSIS_MSG_ID		| \
-					 PDC_CHASSIS_EOM_SET		)
-
-#endif /* _PARISC_PDC_CHASSIS_H */
-/* vim: set ts=8 */
diff --git a/include/asm-parisc/pdcpat.h b/include/asm-parisc/pdcpat.h
deleted file mode 100644
index 47539f117958..000000000000
--- a/include/asm-parisc/pdcpat.h
+++ /dev/null
@@ -1,308 +0,0 @@
-#ifndef __PARISC_PATPDC_H
-#define __PARISC_PATPDC_H
-
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright 2000 (c) Hewlett Packard (Paul Bame <bame()spam.parisc-linux.org>)
- * Copyright 2000,2004 (c) Grant Grundler <grundler()nahspam.parisc-linux.org>
- */
-
-
-#define PDC_PAT_CELL           	64L   /* Interface for gaining and 
-                                         * manipulatin g cell state within PD */
-#define PDC_PAT_CELL_GET_NUMBER    0L   /* Return Cell number */
-#define PDC_PAT_CELL_GET_INFO      1L   /* Returns info about Cell */
-#define PDC_PAT_CELL_MODULE        2L   /* Returns info about Module */
-#define PDC_PAT_CELL_SET_ATTENTION 9L   /* Set Cell Attention indicator */
-#define PDC_PAT_CELL_NUMBER_TO_LOC 10L   /* Cell Number -> Location */
-#define PDC_PAT_CELL_WALK_FABRIC   11L   /* Walk the Fabric */
-#define PDC_PAT_CELL_GET_RDT_SIZE  12L   /* Return Route Distance Table Sizes */
-#define PDC_PAT_CELL_GET_RDT       13L   /* Return Route Distance Tables */
-#define PDC_PAT_CELL_GET_LOCAL_PDH_SZ 14L /* Read Local PDH Buffer Size */
-#define PDC_PAT_CELL_SET_LOCAL_PDH    15L  /* Write Local PDH Buffer */
-#define PDC_PAT_CELL_GET_REMOTE_PDH_SZ 16L /* Return Remote PDH Buffer Size */
-#define PDC_PAT_CELL_GET_REMOTE_PDH 17L /* Read Remote PDH Buffer */
-#define PDC_PAT_CELL_GET_DBG_INFO   128L  /* Return DBG Buffer Info */
-#define PDC_PAT_CELL_CHANGE_ALIAS   129L  /* Change Non-Equivalent Alias Chacking */
-
-
-/*
-** Arg to PDC_PAT_CELL_MODULE memaddr[4]
-**
-** Addresses on the Merced Bus != all Runway Bus addresses.
-** This is intended for programming SBA/LBA chips range registers.
-*/
-#define IO_VIEW      0UL
-#define PA_VIEW      1UL
-
-/* PDC_PAT_CELL_MODULE entity type values */
-#define	PAT_ENTITY_CA	0	/* central agent */
-#define	PAT_ENTITY_PROC	1	/* processor */
-#define	PAT_ENTITY_MEM	2	/* memory controller */
-#define	PAT_ENTITY_SBA	3	/* system bus adapter */
-#define	PAT_ENTITY_LBA	4	/* local bus adapter */
-#define	PAT_ENTITY_PBC	5	/* processor bus converter */
-#define	PAT_ENTITY_XBC	6	/* crossbar fabric connect */
-#define	PAT_ENTITY_RC	7	/* fabric interconnect */
-
-/* PDC_PAT_CELL_MODULE address range type values */
-#define PAT_PBNUM           0         /* PCI Bus Number */
-#define PAT_LMMIO           1         /* < 4G MMIO Space */
-#define PAT_GMMIO           2         /* > 4G MMIO Space */
-#define PAT_NPIOP           3         /* Non Postable I/O Port Space */
-#define PAT_PIOP            4         /* Postable I/O Port Space */
-#define PAT_AHPA            5         /* Addional HPA Space */
-#define PAT_UFO             6         /* HPA Space (UFO for Mariposa) */
-#define PAT_GNIP            7         /* GNI Reserved Space */
-
-
-
-/* PDC PAT CHASSIS LOG -- Platform logging & forward progress functions */
-
-#define PDC_PAT_CHASSIS_LOG		65L
-#define PDC_PAT_CHASSIS_WRITE_LOG    	0L /* Write Log Entry */
-#define PDC_PAT_CHASSIS_READ_LOG     	1L /* Read  Log Entry */
-
-
-/* PDC PAT CPU  -- CPU configuration within the protection domain */
-
-#define PDC_PAT_CPU                	67L
-#define PDC_PAT_CPU_INFO            	0L /* Return CPU config info */
-#define PDC_PAT_CPU_DELETE          	1L /* Delete CPU */
-#define PDC_PAT_CPU_ADD             	2L /* Add    CPU */
-#define PDC_PAT_CPU_GET_NUMBER      	3L /* Return CPU Number */
-#define PDC_PAT_CPU_GET_HPA         	4L /* Return CPU HPA */
-#define PDC_PAT_CPU_STOP            	5L /* Stop   CPU */
-#define PDC_PAT_CPU_RENDEZVOUS      	6L /* Rendezvous CPU */
-#define PDC_PAT_CPU_GET_CLOCK_INFO  	7L /* Return CPU Clock info */
-#define PDC_PAT_CPU_GET_RENDEZVOUS_STATE 8L /* Return Rendezvous State */
-#define PDC_PAT_CPU_PLUNGE_FABRIC 	128L /* Plunge Fabric */
-#define PDC_PAT_CPU_UPDATE_CACHE_CLEANSING 129L /* Manipulate Cache 
-                                                 * Cleansing Mode */
-/*  PDC PAT EVENT -- Platform Events */
-
-#define PDC_PAT_EVENT              	68L
-#define PDC_PAT_EVENT_GET_CAPS     	0L /* Get Capabilities */
-#define PDC_PAT_EVENT_SET_MODE     	1L /* Set Notification Mode */
-#define PDC_PAT_EVENT_SCAN         	2L /* Scan Event */
-#define PDC_PAT_EVENT_HANDLE       	3L /* Handle Event */
-#define PDC_PAT_EVENT_GET_NB_CALL  	4L /* Get Non-Blocking call Args */
-
-/*  PDC PAT HPMC -- Cause processor to go into spin loop, and wait
- *  			for wake up from Monarch Processor.
- */
-
-#define PDC_PAT_HPMC               70L
-#define PDC_PAT_HPMC_RENDEZ_CPU     0L /* go into spin loop */
-#define PDC_PAT_HPMC_SET_PARAMS     1L /* Allows OS to specify intr which PDC 
-                                        * will use to interrupt OS during
-                                        * machine check rendezvous */
-
-/* parameters for PDC_PAT_HPMC_SET_PARAMS: */
-#define HPMC_SET_PARAMS_INTR 	    1L /* Rendezvous Interrupt */
-#define HPMC_SET_PARAMS_WAKE 	    2L /* Wake up processor */
-
-
-/*  PDC PAT IO  -- On-line services for I/O modules */
-
-#define PDC_PAT_IO                  71L
-#define PDC_PAT_IO_GET_SLOT_STATUS   	5L /* Get Slot Status Info*/
-#define PDC_PAT_IO_GET_LOC_FROM_HARDWARE 6L /* Get Physical Location from */
-                                            /* Hardware Path */
-#define PDC_PAT_IO_GET_HARDWARE_FROM_LOC 7L /* Get Hardware Path from 
-                                             * Physical Location */
-#define PDC_PAT_IO_GET_PCI_CONFIG_FROM_HW 11L /* Get PCI Configuration
-                                               * Address from Hardware Path */
-#define PDC_PAT_IO_GET_HW_FROM_PCI_CONFIG 12L /* Get Hardware Path 
-                                               * from PCI Configuration Address */
-#define PDC_PAT_IO_READ_HOST_BRIDGE_INFO 13L  /* Read Host Bridge State Info */
-#define PDC_PAT_IO_CLEAR_HOST_BRIDGE_INFO 14L /* Clear Host Bridge State Info*/
-#define PDC_PAT_IO_GET_PCI_ROUTING_TABLE_SIZE 15L /* Get PCI INT Routing Table 
-                                                   * Size */
-#define PDC_PAT_IO_GET_PCI_ROUTING_TABLE  16L /* Get PCI INT Routing Table */
-#define PDC_PAT_IO_GET_HINT_TABLE_SIZE 	17L /* Get Hint Table Size */
-#define PDC_PAT_IO_GET_HINT_TABLE   	18L /* Get Hint Table */
-#define PDC_PAT_IO_PCI_CONFIG_READ  	19L /* PCI Config Read */
-#define PDC_PAT_IO_PCI_CONFIG_WRITE 	20L /* PCI Config Write */
-#define PDC_PAT_IO_GET_NUM_IO_SLOTS 	21L /* Get Number of I/O Bay Slots in 
-                                       		  * Cabinet */
-#define PDC_PAT_IO_GET_LOC_IO_SLOTS 	22L /* Get Physical Location of I/O */
-                                   		     /* Bay Slots in Cabinet */
-#define PDC_PAT_IO_BAY_STATUS_INFO  	28L /* Get I/O Bay Slot Status Info */
-#define PDC_PAT_IO_GET_PROC_VIEW        29L /* Get Processor view of IO address */
-#define PDC_PAT_IO_PROG_SBA_DIR_RANGE   30L /* Program directed range */
-
-
-/* PDC PAT MEM  -- Manage memory page deallocation */
-
-#define PDC_PAT_MEM            72L
-#define PDC_PAT_MEM_PD_INFO     	0L /* Return PDT info for PD       */
-#define PDC_PAT_MEM_PD_CLEAR    	1L /* Clear PDT for PD             */
-#define PDC_PAT_MEM_PD_READ     	2L /* Read PDT entries for PD      */
-#define PDC_PAT_MEM_PD_RESET    	3L /* Reset clear bit for PD       */
-#define PDC_PAT_MEM_CELL_INFO   	5L /* Return PDT info For Cell     */
-#define PDC_PAT_MEM_CELL_CLEAR  	6L /* Clear PDT For Cell           */
-#define PDC_PAT_MEM_CELL_READ   	7L /* Read PDT entries For Cell    */
-#define PDC_PAT_MEM_CELL_RESET  	8L /* Reset clear bit For Cell     */
-#define PDC_PAT_MEM_SETGM	  	9L /* Set Golden Memory value      */
-#define PDC_PAT_MEM_ADD_PAGE    	10L /* ADDs a page to the cell      */
-#define PDC_PAT_MEM_ADDRESS     	11L /* Get Physical Location From   */
-                                    		 /* Memory Address               */
-#define PDC_PAT_MEM_GET_TXT_SIZE   	12L /* Get Formatted Text Size   */
-#define PDC_PAT_MEM_GET_PD_TXT     	13L /* Get PD Formatted Text     */
-#define PDC_PAT_MEM_GET_CELL_TXT   	14L /* Get Cell Formatted Text   */
-#define PDC_PAT_MEM_RD_STATE_INFO  	15L /* Read Mem Module State Info*/
-#define PDC_PAT_MEM_CLR_STATE_INFO 	16L /*Clear Mem Module State Info*/
-#define PDC_PAT_MEM_CLEAN_RANGE    	128L /*Clean Mem in specific range*/
-#define PDC_PAT_MEM_GET_TBL_SIZE   	131L /* Get Memory Table Size     */
-#define PDC_PAT_MEM_GET_TBL        	132L /* Get Memory Table          */
-
-
-/* PDC PAT NVOLATILE  --  Access Non-Volatile Memory */
-
-#define PDC_PAT_NVOLATILE	73L
-#define PDC_PAT_NVOLATILE_READ		0L /* Read Non-Volatile Memory   */
-#define PDC_PAT_NVOLATILE_WRITE		1L /* Write Non-Volatile Memory  */
-#define PDC_PAT_NVOLATILE_GET_SIZE	2L /* Return size of NVM         */
-#define PDC_PAT_NVOLATILE_VERIFY	3L /* Verify contents of NVM     */
-#define PDC_PAT_NVOLATILE_INIT		4L /* Initialize NVM             */
-
-/* PDC PAT PD */
-#define PDC_PAT_PD		74L         /* Protection Domain Info   */
-#define PDC_PAT_PD_GET_ADDR_MAP		0L  /* Get Address Map          */
-
-/* PDC_PAT_PD_GET_ADDR_MAP entry types */
-#define PAT_MEMORY_DESCRIPTOR		1   
-
-/* PDC_PAT_PD_GET_ADDR_MAP memory types */
-#define PAT_MEMTYPE_MEMORY		0
-#define PAT_MEMTYPE_FIRMWARE		4
-
-/* PDC_PAT_PD_GET_ADDR_MAP memory usage */
-#define PAT_MEMUSE_GENERAL		0
-#define PAT_MEMUSE_GI			128
-#define PAT_MEMUSE_GNI			129
-
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-
-#ifdef CONFIG_64BIT
-#define is_pdc_pat()	(PDC_TYPE_PAT == pdc_type)
-extern int pdc_pat_get_irt_size(unsigned long *num_entries, unsigned long cell_num);
-extern int pdc_pat_get_irt(void *r_addr, unsigned long cell_num);
-#else	/* ! CONFIG_64BIT */
-/* No PAT support for 32-bit kernels...sorry */
-#define is_pdc_pat()	(0)
-#define pdc_pat_get_irt_size(num_entries, cell_numn)	PDC_BAD_PROC
-#define pdc_pat_get_irt(r_addr, cell_num)		PDC_BAD_PROC
-#endif	/* ! CONFIG_64BIT */
-
-
-struct pdc_pat_cell_num {
-	unsigned long cell_num;
-	unsigned long cell_loc;
-};
-
-struct pdc_pat_cpu_num {
-	unsigned long cpu_num;
-	unsigned long cpu_loc;
-};
-
-struct pdc_pat_pd_addr_map_entry {
-	unsigned char entry_type;       /* 1 = Memory Descriptor Entry Type */
-	unsigned char reserve1[5];
-	unsigned char memory_type;
-	unsigned char memory_usage;
-	unsigned long paddr;
-	unsigned int  pages;            /* Length in 4K pages */
-	unsigned int  reserve2;
-	unsigned long cell_map;
-};
-
-/********************************************************************
-* PDC_PAT_CELL[Return Cell Module] memaddr[0] conf_base_addr
-* ----------------------------------------------------------
-* Bit  0 to 51 - conf_base_addr
-* Bit 52 to 62 - reserved
-* Bit       63 - endianess bit
-********************************************************************/
-#define PAT_GET_CBA(value) ((value) & 0xfffffffffffff000UL)
-
-/********************************************************************
-* PDC_PAT_CELL[Return Cell Module] memaddr[1] mod_info
-* ----------------------------------------------------
-* Bit  0 to  7 - entity type
-*    0 = central agent,            1 = processor,
-*    2 = memory controller,        3 = system bus adapter,
-*    4 = local bus adapter,        5 = processor bus converter,
-*    6 = crossbar fabric connect,  7 = fabric interconnect,
-*    8 to 254 reserved,            255 = unknown.
-* Bit  8 to 15 - DVI
-* Bit 16 to 23 - IOC functions
-* Bit 24 to 39 - reserved
-* Bit 40 to 63 - mod_pages
-*    number of 4K pages a module occupies starting at conf_base_addr
-********************************************************************/
-#define PAT_GET_ENTITY(value)	(((value) >> 56) & 0xffUL)
-#define PAT_GET_DVI(value)	(((value) >> 48) & 0xffUL)
-#define PAT_GET_IOC(value)	(((value) >> 40) & 0xffUL)
-#define PAT_GET_MOD_PAGES(value) ((value) & 0xffffffUL)
-
-
-/*
-** PDC_PAT_CELL_GET_INFO return block
-*/
-typedef struct pdc_pat_cell_info_rtn_block {
-	unsigned long cpu_info;
-	unsigned long cell_info;
-	unsigned long cell_location;
-	unsigned long reo_location;
-	unsigned long mem_size;
-	unsigned long dimm_status;
-	unsigned long pdc_rev;
-	unsigned long fabric_info0;
-	unsigned long fabric_info1;
-	unsigned long fabric_info2;
-	unsigned long fabric_info3;
-	unsigned long reserved[21];
-} pdc_pat_cell_info_rtn_block_t;
-
-
-/* FIXME: mod[508] should really be a union of the various mod components */
-struct pdc_pat_cell_mod_maddr_block {	/* PDC_PAT_CELL_MODULE */
-	unsigned long cba;		/* func 0 cfg space address */
-	unsigned long mod_info;		/* module information */
-	unsigned long mod_location;	/* physical location of the module */
-	struct hardware_path mod_path;	/* module path (device path - layers) */
-	unsigned long mod[508];		/* PAT cell module components */
-} __attribute__((aligned(8))) ;
-
-typedef struct pdc_pat_cell_mod_maddr_block pdc_pat_cell_mod_maddr_block_t;
-
-
-extern int pdc_pat_chassis_send_log(unsigned long status, unsigned long data);
-extern int pdc_pat_cell_get_number(struct pdc_pat_cell_num *cell_info);
-extern int pdc_pat_cell_module(unsigned long *actcnt, unsigned long ploc, unsigned long mod, unsigned long view_type, void *mem_addr);
-extern int pdc_pat_cell_num_to_loc(void *, unsigned long);
-
-extern int pdc_pat_cpu_get_number(struct pdc_pat_cpu_num *cpu_info, void *hpa);
-
-extern int pdc_pat_pd_get_addr_map(unsigned long *actual_len, void *mem_addr, unsigned long count, unsigned long offset);
-
-
-extern int pdc_pat_io_pci_cfg_read(unsigned long pci_addr, int pci_size, u32 *val); 
-extern int pdc_pat_io_pci_cfg_write(unsigned long pci_addr, int pci_size, u32 val); 
-
-
-/* Flag to indicate this is a PAT box...don't use this unless you
-** really have to...it might go away some day.
-*/
-extern int pdc_pat;     /* arch/parisc/kernel/inventory.c */
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* ! __PARISC_PATPDC_H */
diff --git a/include/asm-parisc/percpu.h b/include/asm-parisc/percpu.h
deleted file mode 100644
index a0dcd1970128..000000000000
--- a/include/asm-parisc/percpu.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _PARISC_PERCPU_H
-#define _PARISC_PERCPU_H
-
-#include <asm-generic/percpu.h>
-
-#endif 
-
diff --git a/include/asm-parisc/perf.h b/include/asm-parisc/perf.h
deleted file mode 100644
index a18e11972c09..000000000000
--- a/include/asm-parisc/perf.h
+++ /dev/null
@@ -1,74 +0,0 @@
-#ifndef _ASM_PERF_H_
-#define _ASM_PERF_H_
-
-/* ioctls */
-#define PA_PERF_ON	_IO('p', 1)
-#define PA_PERF_OFF	_IOR('p', 2, unsigned int)
-#define PA_PERF_VERSION	_IOR('p', 3, int)
-
-#define PA_PERF_DEV	"perf"
-#define PA_PERF_MINOR	146
-
-/* Interface types */
-#define UNKNOWN_INTF    255
-#define ONYX_INTF         0
-#define CUDA_INTF         1
-
-/* Common Onyx and Cuda images */
-#define CPI                 0
-#define BUSUTIL             1
-#define TLBMISS             2
-#define TLBHANDMISS         3
-#define PTKN                4
-#define PNTKN               5
-#define IMISS               6
-#define DMISS               7
-#define DMISS_ACCESS        8 
-#define BIG_CPI 	    9
-#define BIG_LS		   10  
-#define BR_ABORT	   11
-#define ISNT		   12 
-#define QUADRANT           13
-#define RW_PDFET           14
-#define RW_WDFET           15
-#define SHLIB_CPI          16
-
-/* Cuda only Images */
-#define FLOPS              17
-#define CACHEMISS          18 
-#define BRANCHES           19             
-#define CRSTACK            20 
-#define I_CACHE_SPEC       21 
-#define MAX_CUDA_IMAGES    22 
-
-/* Onyx only Images */
-#define ADDR_INV_ABORT_ALU 17
-#define BRAD_STALL	   18 
-#define CNTL_IN_PIPEL	   19 
-#define DSNT_XFH	   20 
-#define FET_SIG1	   21 
-#define FET_SIG2	   22 
-#define G7_1		   23 
-#define G7_2		   24 
-#define G7_3 		   25
-#define G7_4		   26
-#define MPB_LABORT         27
-#define PANIC              28
-#define RARE_INST          29 
-#define RW_DFET            30 
-#define RW_IFET            31 
-#define RW_SDFET           32 
-#define SPEC_IFET          33 
-#define ST_COND0           34 
-#define ST_COND1           35 
-#define ST_COND2           36
-#define ST_COND3           37
-#define ST_COND4           38
-#define ST_UNPRED0         39 
-#define ST_UNPRED1         40 
-#define UNPRED             41 
-#define GO_STORE           42
-#define SHLIB_CALL         43
-#define MAX_ONYX_IMAGES    44
-
-#endif
diff --git a/include/asm-parisc/pgalloc.h b/include/asm-parisc/pgalloc.h
deleted file mode 100644
index fc987a1c12a8..000000000000
--- a/include/asm-parisc/pgalloc.h
+++ /dev/null
@@ -1,149 +0,0 @@
-#ifndef _ASM_PGALLOC_H
-#define _ASM_PGALLOC_H
-
-#include <linux/gfp.h>
-#include <linux/mm.h>
-#include <linux/threads.h>
-#include <asm/processor.h>
-#include <asm/fixmap.h>
-
-#include <asm/cache.h>
-
-/* Allocate the top level pgd (page directory)
- *
- * Here (for 64 bit kernels) we implement a Hybrid L2/L3 scheme: we
- * allocate the first pmd adjacent to the pgd.  This means that we can
- * subtract a constant offset to get to it.  The pmd and pgd sizes are
- * arranged so that a single pmd covers 4GB (giving a full 64-bit
- * process access to 8TB) so our lookups are effectively L2 for the
- * first 4GB of the kernel (i.e. for all ILP32 processes and all the
- * kernel for machines with under 4GB of memory) */
-static inline pgd_t *pgd_alloc(struct mm_struct *mm)
-{
-	pgd_t *pgd = (pgd_t *)__get_free_pages(GFP_KERNEL,
-					       PGD_ALLOC_ORDER);
-	pgd_t *actual_pgd = pgd;
-
-	if (likely(pgd != NULL)) {
-		memset(pgd, 0, PAGE_SIZE<<PGD_ALLOC_ORDER);
-#ifdef CONFIG_64BIT
-		actual_pgd += PTRS_PER_PGD;
-		/* Populate first pmd with allocated memory.  We mark it
-		 * with PxD_FLAG_ATTACHED as a signal to the system that this
-		 * pmd entry may not be cleared. */
-		__pgd_val_set(*actual_pgd, (PxD_FLAG_PRESENT | 
-				        PxD_FLAG_VALID | 
-					PxD_FLAG_ATTACHED) 
-			+ (__u32)(__pa((unsigned long)pgd) >> PxD_VALUE_SHIFT));
-		/* The first pmd entry also is marked with _PAGE_GATEWAY as
-		 * a signal that this pmd may not be freed */
-		__pgd_val_set(*pgd, PxD_FLAG_ATTACHED);
-#endif
-	}
-	return actual_pgd;
-}
-
-static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
-#ifdef CONFIG_64BIT
-	pgd -= PTRS_PER_PGD;
-#endif
-	free_pages((unsigned long)pgd, PGD_ALLOC_ORDER);
-}
-
-#if PT_NLEVELS == 3
-
-/* Three Level Page Table Support for pmd's */
-
-static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pmd_t *pmd)
-{
-	__pgd_val_set(*pgd, (PxD_FLAG_PRESENT | PxD_FLAG_VALID) +
-		        (__u32)(__pa((unsigned long)pmd) >> PxD_VALUE_SHIFT));
-}
-
-static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
-{
-	pmd_t *pmd = (pmd_t *)__get_free_pages(GFP_KERNEL|__GFP_REPEAT,
-					       PMD_ORDER);
-	if (pmd)
-		memset(pmd, 0, PAGE_SIZE<<PMD_ORDER);
-	return pmd;
-}
-
-static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
-{
-#ifdef CONFIG_64BIT
-	if(pmd_flag(*pmd) & PxD_FLAG_ATTACHED)
-		/* This is the permanent pmd attached to the pgd;
-		 * cannot free it */
-		return;
-#endif
-	free_pages((unsigned long)pmd, PMD_ORDER);
-}
-
-#else
-
-/* Two Level Page Table Support for pmd's */
-
-/*
- * allocating and freeing a pmd is trivial: the 1-entry pmd is
- * inside the pgd, so has no extra memory associated with it.
- */
-
-#define pmd_alloc_one(mm, addr)		({ BUG(); ((pmd_t *)2); })
-#define pmd_free(mm, x)			do { } while (0)
-#define pgd_populate(mm, pmd, pte)	BUG()
-
-#endif
-
-static inline void
-pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte)
-{
-#ifdef CONFIG_64BIT
-	/* preserve the gateway marker if this is the beginning of
-	 * the permanent pmd */
-	if(pmd_flag(*pmd) & PxD_FLAG_ATTACHED)
-		__pmd_val_set(*pmd, (PxD_FLAG_PRESENT |
-				 PxD_FLAG_VALID |
-				 PxD_FLAG_ATTACHED) 
-			+ (__u32)(__pa((unsigned long)pte) >> PxD_VALUE_SHIFT));
-	else
-#endif
-		__pmd_val_set(*pmd, (PxD_FLAG_PRESENT | PxD_FLAG_VALID) 
-			+ (__u32)(__pa((unsigned long)pte) >> PxD_VALUE_SHIFT));
-}
-
-#define pmd_populate(mm, pmd, pte_page) \
-	pmd_populate_kernel(mm, pmd, page_address(pte_page))
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-static inline pgtable_t
-pte_alloc_one(struct mm_struct *mm, unsigned long address)
-{
-	struct page *page = alloc_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO);
-	if (page)
-		pgtable_page_ctor(page);
-	return page;
-}
-
-static inline pte_t *
-pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr)
-{
-	pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO);
-	return pte;
-}
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
-	free_page((unsigned long)pte);
-}
-
-static inline void pte_free(struct mm_struct *mm, struct page *pte)
-{
-	pgtable_page_dtor(pte);
-	pte_free_kernel(mm, page_address(pte));
-}
-
-#define check_pgt_cache()	do { } while (0)
-
-#endif
diff --git a/include/asm-parisc/pgtable.h b/include/asm-parisc/pgtable.h
deleted file mode 100644
index 470a4b88124d..000000000000
--- a/include/asm-parisc/pgtable.h
+++ /dev/null
@@ -1,508 +0,0 @@
-#ifndef _PARISC_PGTABLE_H
-#define _PARISC_PGTABLE_H
-
-#include <asm-generic/4level-fixup.h>
-
-#include <asm/fixmap.h>
-
-#ifndef __ASSEMBLY__
-/*
- * we simulate an x86-style page table for the linux mm code
- */
-
-#include <linux/mm.h>		/* for vm_area_struct */
-#include <linux/bitops.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-
-/*
- * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
- * memory.  For the return value to be meaningful, ADDR must be >=
- * PAGE_OFFSET.  This operation can be relatively expensive (e.g.,
- * require a hash-, or multi-level tree-lookup or something of that
- * sort) but it guarantees to return TRUE only if accessing the page
- * at that address does not cause an error.  Note that there may be
- * addresses for which kern_addr_valid() returns FALSE even though an
- * access would not cause an error (e.g., this is typically true for
- * memory mapped I/O regions.
- *
- * XXX Need to implement this for parisc.
- */
-#define kern_addr_valid(addr)	(1)
-
-/* Certain architectures need to do special things when PTEs
- * within a page table are directly modified.  Thus, the following
- * hook is made available.
- */
-#define set_pte(pteptr, pteval)                                 \
-        do{                                                     \
-                *(pteptr) = (pteval);                           \
-        } while(0)
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
-
-#endif /* !__ASSEMBLY__ */
-
-#define pte_ERROR(e) \
-	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
-#define pmd_ERROR(e) \
-	printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e))
-#define pgd_ERROR(e) \
-	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e))
-
-/* This is the size of the initially mapped kernel memory */
-#ifdef CONFIG_64BIT
-#define KERNEL_INITIAL_ORDER	24	/* 0 to 1<<24 = 16MB */
-#else
-#define KERNEL_INITIAL_ORDER	23	/* 0 to 1<<23 = 8MB */
-#endif
-#define KERNEL_INITIAL_SIZE	(1 << KERNEL_INITIAL_ORDER)
-
-#if defined(CONFIG_64BIT) && defined(CONFIG_PARISC_PAGE_SIZE_4KB)
-#define PT_NLEVELS	3
-#define PGD_ORDER	1 /* Number of pages per pgd */
-#define PMD_ORDER	1 /* Number of pages per pmd */
-#define PGD_ALLOC_ORDER	2 /* first pgd contains pmd */
-#else
-#define PT_NLEVELS	2
-#define PGD_ORDER	1 /* Number of pages per pgd */
-#define PGD_ALLOC_ORDER	PGD_ORDER
-#endif
-
-/* Definitions for 3rd level (we use PLD here for Page Lower directory
- * because PTE_SHIFT is used lower down to mean shift that has to be
- * done to get usable bits out of the PTE) */
-#define PLD_SHIFT	PAGE_SHIFT
-#define PLD_SIZE	PAGE_SIZE
-#define BITS_PER_PTE	(PAGE_SHIFT - BITS_PER_PTE_ENTRY)
-#define PTRS_PER_PTE    (1UL << BITS_PER_PTE)
-
-/* Definitions for 2nd level */
-#define pgtable_cache_init()	do { } while (0)
-
-#define PMD_SHIFT       (PLD_SHIFT + BITS_PER_PTE)
-#define PMD_SIZE	(1UL << PMD_SHIFT)
-#define PMD_MASK	(~(PMD_SIZE-1))
-#if PT_NLEVELS == 3
-#define BITS_PER_PMD	(PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY)
-#else
-#define BITS_PER_PMD	0
-#endif
-#define PTRS_PER_PMD    (1UL << BITS_PER_PMD)
-
-/* Definitions for 1st level */
-#define PGDIR_SHIFT	(PMD_SHIFT + BITS_PER_PMD)
-#define BITS_PER_PGD	(PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY)
-#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
-#define PGDIR_MASK	(~(PGDIR_SIZE-1))
-#define PTRS_PER_PGD    (1UL << BITS_PER_PGD)
-#define USER_PTRS_PER_PGD       PTRS_PER_PGD
-
-#define MAX_ADDRBITS	(PGDIR_SHIFT + BITS_PER_PGD)
-#define MAX_ADDRESS	(1UL << MAX_ADDRBITS)
-
-#define SPACEID_SHIFT	(MAX_ADDRBITS - 32)
-
-/* This calculates the number of initial pages we need for the initial
- * page tables */
-#if (KERNEL_INITIAL_ORDER) >= (PMD_SHIFT)
-# define PT_INITIAL	(1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT))
-#else
-# define PT_INITIAL	(1)  /* all initial PTEs fit into one page */
-#endif
-
-/*
- * pgd entries used up by user/kernel:
- */
-
-#define FIRST_USER_ADDRESS	0
-
-/* NB: The tlb miss handlers make certain assumptions about the order */
-/*     of the following bits, so be careful (One example, bits 25-31  */
-/*     are moved together in one instruction).                        */
-
-#define _PAGE_READ_BIT     31   /* (0x001) read access allowed */
-#define _PAGE_WRITE_BIT    30   /* (0x002) write access allowed */
-#define _PAGE_EXEC_BIT     29   /* (0x004) execute access allowed */
-#define _PAGE_GATEWAY_BIT  28   /* (0x008) privilege promotion allowed */
-#define _PAGE_DMB_BIT      27   /* (0x010) Data Memory Break enable (B bit) */
-#define _PAGE_DIRTY_BIT    26   /* (0x020) Page Dirty (D bit) */
-#define _PAGE_FILE_BIT	_PAGE_DIRTY_BIT	/* overload this bit */
-#define _PAGE_REFTRAP_BIT  25   /* (0x040) Page Ref. Trap enable (T bit) */
-#define _PAGE_NO_CACHE_BIT 24   /* (0x080) Uncached Page (U bit) */
-#define _PAGE_ACCESSED_BIT 23   /* (0x100) Software: Page Accessed */
-#define _PAGE_PRESENT_BIT  22   /* (0x200) Software: translation valid */
-#define _PAGE_FLUSH_BIT    21   /* (0x400) Software: translation valid */
-				/*             for cache flushing only */
-#define _PAGE_USER_BIT     20   /* (0x800) Software: User accessible page */
-
-/* N.B. The bits are defined in terms of a 32 bit word above, so the */
-/*      following macro is ok for both 32 and 64 bit.                */
-
-#define xlate_pabit(x) (31 - x)
-
-/* this defines the shift to the usable bits in the PTE it is set so
- * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set
- * to zero */
-#define PTE_SHIFT	   	xlate_pabit(_PAGE_USER_BIT)
-
-/* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */
-#define PFN_PTE_SHIFT		12
-
-
-/* this is how many bits may be used by the file functions */
-#define PTE_FILE_MAX_BITS	(BITS_PER_LONG - PTE_SHIFT)
-
-#define pte_to_pgoff(pte) (pte_val(pte) >> PTE_SHIFT)
-#define pgoff_to_pte(off) ((pte_t) { ((off) << PTE_SHIFT) | _PAGE_FILE })
-
-#define _PAGE_READ     (1 << xlate_pabit(_PAGE_READ_BIT))
-#define _PAGE_WRITE    (1 << xlate_pabit(_PAGE_WRITE_BIT))
-#define _PAGE_RW       (_PAGE_READ | _PAGE_WRITE)
-#define _PAGE_EXEC     (1 << xlate_pabit(_PAGE_EXEC_BIT))
-#define _PAGE_GATEWAY  (1 << xlate_pabit(_PAGE_GATEWAY_BIT))
-#define _PAGE_DMB      (1 << xlate_pabit(_PAGE_DMB_BIT))
-#define _PAGE_DIRTY    (1 << xlate_pabit(_PAGE_DIRTY_BIT))
-#define _PAGE_REFTRAP  (1 << xlate_pabit(_PAGE_REFTRAP_BIT))
-#define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT))
-#define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT))
-#define _PAGE_PRESENT  (1 << xlate_pabit(_PAGE_PRESENT_BIT))
-#define _PAGE_FLUSH    (1 << xlate_pabit(_PAGE_FLUSH_BIT))
-#define _PAGE_USER     (1 << xlate_pabit(_PAGE_USER_BIT))
-#define _PAGE_FILE     (1 << xlate_pabit(_PAGE_FILE_BIT))
-
-#define _PAGE_TABLE	(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE |  _PAGE_DIRTY | _PAGE_ACCESSED)
-#define _PAGE_CHG_MASK	(PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
-#define _PAGE_KERNEL	(_PAGE_PRESENT | _PAGE_EXEC | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED)
-
-/* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds
- * are page-aligned, we don't care about the PAGE_OFFSET bits, except
- * for a few meta-information bits, so we shift the address to be
- * able to effectively address 40/42/44-bits of physical address space
- * depending on 4k/16k/64k PAGE_SIZE */
-#define _PxD_PRESENT_BIT   31
-#define _PxD_ATTACHED_BIT  30
-#define _PxD_VALID_BIT     29
-
-#define PxD_FLAG_PRESENT  (1 << xlate_pabit(_PxD_PRESENT_BIT))
-#define PxD_FLAG_ATTACHED (1 << xlate_pabit(_PxD_ATTACHED_BIT))
-#define PxD_FLAG_VALID    (1 << xlate_pabit(_PxD_VALID_BIT))
-#define PxD_FLAG_MASK     (0xf)
-#define PxD_FLAG_SHIFT    (4)
-#define PxD_VALUE_SHIFT   (8) /* (PAGE_SHIFT-PxD_FLAG_SHIFT) */
-
-#ifndef __ASSEMBLY__
-
-#define PAGE_NONE	__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
-#define PAGE_SHARED	__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_ACCESSED)
-/* Others seem to make this executable, I don't know if that's correct
-   or not.  The stack is mapped this way though so this is necessary
-   in the short term - dhd@linuxcare.com, 2000-08-08 */
-#define PAGE_READONLY	__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_ACCESSED)
-#define PAGE_WRITEONLY  __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE | _PAGE_ACCESSED)
-#define PAGE_EXECREAD   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC |_PAGE_ACCESSED)
-#define PAGE_COPY       PAGE_EXECREAD
-#define PAGE_RWX        __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC |_PAGE_ACCESSED)
-#define PAGE_KERNEL	__pgprot(_PAGE_KERNEL)
-#define PAGE_KERNEL_RO	__pgprot(_PAGE_KERNEL & ~_PAGE_WRITE)
-#define PAGE_KERNEL_UNC	__pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
-#define PAGE_GATEWAY    __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_GATEWAY| _PAGE_READ)
-#define PAGE_FLUSH      __pgprot(_PAGE_FLUSH)
-
-
-/*
- * We could have an execute only page using "gateway - promote to priv
- * level 3", but that is kind of silly. So, the way things are defined
- * now, we must always have read permission for pages with execute
- * permission. For the fun of it we'll go ahead and support write only
- * pages.
- */
-
-	 /*xwr*/
-#define __P000  PAGE_NONE
-#define __P001  PAGE_READONLY
-#define __P010  __P000 /* copy on write */
-#define __P011  __P001 /* copy on write */
-#define __P100  PAGE_EXECREAD
-#define __P101  PAGE_EXECREAD
-#define __P110  __P100 /* copy on write */
-#define __P111  __P101 /* copy on write */
-
-#define __S000  PAGE_NONE
-#define __S001  PAGE_READONLY
-#define __S010  PAGE_WRITEONLY
-#define __S011  PAGE_SHARED
-#define __S100  PAGE_EXECREAD
-#define __S101  PAGE_EXECREAD
-#define __S110  PAGE_RWX
-#define __S111  PAGE_RWX
-
-
-extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */
-
-/* initial page tables for 0-8MB for kernel */
-
-extern pte_t pg0[];
-
-/* zero page used for uninitialized stuff */
-
-extern unsigned long *empty_zero_page;
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-
-#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
-
-#define pte_none(x)     ((pte_val(x) == 0) || (pte_val(x) & _PAGE_FLUSH))
-#define pte_present(x)	(pte_val(x) & _PAGE_PRESENT)
-#define pte_clear(mm,addr,xp)	do { pte_val(*(xp)) = 0; } while (0)
-
-#define pmd_flag(x)	(pmd_val(x) & PxD_FLAG_MASK)
-#define pmd_address(x)	((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
-#define pgd_flag(x)	(pgd_val(x) & PxD_FLAG_MASK)
-#define pgd_address(x)	((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
-
-#if PT_NLEVELS == 3
-/* The first entry of the permanent pmd is not there if it contains
- * the gateway marker */
-#define pmd_none(x)	(!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED)
-#else
-#define pmd_none(x)	(!pmd_val(x))
-#endif
-#define pmd_bad(x)	(!(pmd_flag(x) & PxD_FLAG_VALID))
-#define pmd_present(x)	(pmd_flag(x) & PxD_FLAG_PRESENT)
-static inline void pmd_clear(pmd_t *pmd) {
-#if PT_NLEVELS == 3
-	if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED)
-		/* This is the entry pointing to the permanent pmd
-		 * attached to the pgd; cannot clear it */
-		__pmd_val_set(*pmd, PxD_FLAG_ATTACHED);
-	else
-#endif
-		__pmd_val_set(*pmd,  0);
-}
-
-
-
-#if PT_NLEVELS == 3
-#define pgd_page_vaddr(pgd) ((unsigned long) __va(pgd_address(pgd)))
-#define pgd_page(pgd)	virt_to_page((void *)pgd_page_vaddr(pgd))
-
-/* For 64 bit we have three level tables */
-
-#define pgd_none(x)     (!pgd_val(x))
-#define pgd_bad(x)      (!(pgd_flag(x) & PxD_FLAG_VALID))
-#define pgd_present(x)  (pgd_flag(x) & PxD_FLAG_PRESENT)
-static inline void pgd_clear(pgd_t *pgd) {
-#if PT_NLEVELS == 3
-	if(pgd_flag(*pgd) & PxD_FLAG_ATTACHED)
-		/* This is the permanent pmd attached to the pgd; cannot
-		 * free it */
-		return;
-#endif
-	__pgd_val_set(*pgd, 0);
-}
-#else
-/*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pgd is never bad, and a pmd always exists (as it's folded
- * into the pgd entry)
- */
-static inline int pgd_none(pgd_t pgd)		{ return 0; }
-static inline int pgd_bad(pgd_t pgd)		{ return 0; }
-static inline int pgd_present(pgd_t pgd)	{ return 1; }
-static inline void pgd_clear(pgd_t * pgdp)	{ }
-#endif
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-static inline int pte_dirty(pte_t pte)		{ return pte_val(pte) & _PAGE_DIRTY; }
-static inline int pte_young(pte_t pte)		{ return pte_val(pte) & _PAGE_ACCESSED; }
-static inline int pte_write(pte_t pte)		{ return pte_val(pte) & _PAGE_WRITE; }
-static inline int pte_file(pte_t pte)		{ return pte_val(pte) & _PAGE_FILE; }
-static inline int pte_special(pte_t pte)	{ return 0; }
-
-static inline pte_t pte_mkclean(pte_t pte)	{ pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
-static inline pte_t pte_mkold(pte_t pte)	{ pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
-static inline pte_t pte_wrprotect(pte_t pte)	{ pte_val(pte) &= ~_PAGE_WRITE; return pte; }
-static inline pte_t pte_mkdirty(pte_t pte)	{ pte_val(pte) |= _PAGE_DIRTY; return pte; }
-static inline pte_t pte_mkyoung(pte_t pte)	{ pte_val(pte) |= _PAGE_ACCESSED; return pte; }
-static inline pte_t pte_mkwrite(pte_t pte)	{ pte_val(pte) |= _PAGE_WRITE; return pte; }
-static inline pte_t pte_mkspecial(pte_t pte)	{ return pte; }
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-#define __mk_pte(addr,pgprot) \
-({									\
-	pte_t __pte;							\
-									\
-	pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot));	\
-									\
-	__pte;								\
-})
-
-#define mk_pte(page, pgprot)	pfn_pte(page_to_pfn(page), (pgprot))
-
-static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
-{
-	pte_t pte;
-	pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot);
-	return pte;
-}
-
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
-
-/* Permanent address of a page.  On parisc we don't have highmem. */
-
-#define pte_pfn(x)		(pte_val(x) >> PFN_PTE_SHIFT)
-
-#define pte_page(pte)		(pfn_to_page(pte_pfn(pte)))
-
-#define pmd_page_vaddr(pmd)	((unsigned long) __va(pmd_address(pmd)))
-
-#define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd)))
-#define pmd_page(pmd)	virt_to_page((void *)__pmd_page(pmd))
-
-#define pgd_index(address) ((address) >> PGDIR_SHIFT)
-
-/* to find an entry in a page-table-directory */
-#define pgd_offset(mm, address) \
-((mm)->pgd + ((address) >> PGDIR_SHIFT))
-
-/* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-/* Find an entry in the second-level page table.. */
-
-#if PT_NLEVELS == 3
-#define pmd_offset(dir,address) \
-((pmd_t *) pgd_page_vaddr(*(dir)) + (((address)>>PMD_SHIFT) & (PTRS_PER_PMD-1)))
-#else
-#define pmd_offset(dir,addr) ((pmd_t *) dir)
-#endif
-
-/* Find an entry in the third-level page table.. */ 
-#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
-#define pte_offset_kernel(pmd, address) \
-	((pte_t *) pmd_page_vaddr(*(pmd)) + pte_index(address))
-#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
-#define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address)
-#define pte_unmap(pte) do { } while (0)
-#define pte_unmap_nested(pte) do { } while (0)
-
-#define pte_unmap(pte)			do { } while (0)
-#define pte_unmap_nested(pte)		do { } while (0)
-
-extern void paging_init (void);
-
-/* Used for deferring calls to flush_dcache_page() */
-
-#define PG_dcache_dirty         PG_arch_1
-
-extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
-
-/* Encode and de-code a swap entry */
-
-#define __swp_type(x)                     ((x).val & 0x1f)
-#define __swp_offset(x)                   ( (((x).val >> 6) &  0x7) | \
-					  (((x).val >> 8) & ~0x7) )
-#define __swp_entry(type, offset)         ((swp_entry_t) { (type) | \
-					    ((offset &  0x7) << 6) | \
-					    ((offset & ~0x7) << 8) })
-#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x)		((pte_t) { (x).val })
-
-static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
-{
-#ifdef CONFIG_SMP
-	if (!pte_young(*ptep))
-		return 0;
-	return test_and_clear_bit(xlate_pabit(_PAGE_ACCESSED_BIT), &pte_val(*ptep));
-#else
-	pte_t pte = *ptep;
-	if (!pte_young(pte))
-		return 0;
-	set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
-	return 1;
-#endif
-}
-
-extern spinlock_t pa_dbit_lock;
-
-struct mm_struct;
-static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
-{
-	pte_t old_pte;
-	pte_t pte;
-
-	spin_lock(&pa_dbit_lock);
-	pte = old_pte = *ptep;
-	pte_val(pte) &= ~_PAGE_PRESENT;
-	pte_val(pte) |= _PAGE_FLUSH;
-	set_pte_at(mm,addr,ptep,pte);
-	spin_unlock(&pa_dbit_lock);
-
-	return old_pte;
-}
-
-static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
-{
-#ifdef CONFIG_SMP
-	unsigned long new, old;
-
-	do {
-		old = pte_val(*ptep);
-		new = pte_val(pte_wrprotect(__pte (old)));
-	} while (cmpxchg((unsigned long *) ptep, old, new) != old);
-#else
-	pte_t old_pte = *ptep;
-	set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
-#endif
-}
-
-#define pte_same(A,B)	(pte_val(A) == pte_val(B))
-
-#endif /* !__ASSEMBLY__ */
-
-
-/* TLB page size encoding - see table 3-1 in parisc20.pdf */
-#define _PAGE_SIZE_ENCODING_4K		0
-#define _PAGE_SIZE_ENCODING_16K		1
-#define _PAGE_SIZE_ENCODING_64K		2
-#define _PAGE_SIZE_ENCODING_256K	3
-#define _PAGE_SIZE_ENCODING_1M		4
-#define _PAGE_SIZE_ENCODING_4M		5
-#define _PAGE_SIZE_ENCODING_16M		6
-#define _PAGE_SIZE_ENCODING_64M		7
-
-#if defined(CONFIG_PARISC_PAGE_SIZE_4KB)
-# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K
-#elif defined(CONFIG_PARISC_PAGE_SIZE_16KB)
-# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K
-#elif defined(CONFIG_PARISC_PAGE_SIZE_64KB)
-# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K
-#endif
-
-
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)		\
-		remap_pfn_range(vma, vaddr, pfn, size, prot)
-
-#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)
-
-/* We provide our own get_unmapped_area to provide cache coherency */
-
-#define HAVE_ARCH_UNMAPPED_AREA
-
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
-#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
-#define __HAVE_ARCH_PTEP_SET_WRPROTECT
-#define __HAVE_ARCH_PTE_SAME
-#include <asm-generic/pgtable.h>
-
-#endif /* _PARISC_PGTABLE_H */
diff --git a/include/asm-parisc/poll.h b/include/asm-parisc/poll.h
deleted file mode 100644
index c98509d3149e..000000000000
--- a/include/asm-parisc/poll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/poll.h>
diff --git a/include/asm-parisc/posix_types.h b/include/asm-parisc/posix_types.h
deleted file mode 100644
index bb725a6630bb..000000000000
--- a/include/asm-parisc/posix_types.h
+++ /dev/null
@@ -1,129 +0,0 @@
-#ifndef __ARCH_PARISC_POSIX_TYPES_H
-#define __ARCH_PARISC_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-typedef unsigned long		__kernel_ino_t;
-typedef unsigned short		__kernel_mode_t;
-typedef unsigned short		__kernel_nlink_t;
-typedef long			__kernel_off_t;
-typedef int			__kernel_pid_t;
-typedef unsigned short		__kernel_ipc_pid_t;
-typedef unsigned int		__kernel_uid_t;
-typedef unsigned int		__kernel_gid_t;
-typedef int			__kernel_suseconds_t;
-typedef long			__kernel_clock_t;
-typedef int			__kernel_timer_t;
-typedef int			__kernel_clockid_t;
-typedef int			__kernel_daddr_t;
-/* Note these change from narrow to wide kernels */
-#ifdef CONFIG_64BIT
-typedef unsigned long		__kernel_size_t;
-typedef long			__kernel_ssize_t;
-typedef long			__kernel_ptrdiff_t;
-typedef long			__kernel_time_t;
-#else
-typedef unsigned int		__kernel_size_t;
-typedef int			__kernel_ssize_t;
-typedef int			__kernel_ptrdiff_t;
-typedef long			__kernel_time_t;
-#endif
-typedef char *			__kernel_caddr_t;
-
-typedef unsigned short		__kernel_uid16_t;
-typedef unsigned short		__kernel_gid16_t;
-typedef unsigned int		__kernel_uid32_t;
-typedef unsigned int		__kernel_gid32_t;
-
-#ifdef __GNUC__
-typedef long long		__kernel_loff_t;
-typedef long long		__kernel_off64_t;
-typedef unsigned long long	__kernel_ino64_t;
-#endif
-
-typedef unsigned int		__kernel_old_dev_t;
-
-typedef struct {
-	int	val[2];
-} __kernel_fsid_t;
-
-/* compatibility stuff */
-typedef __kernel_uid_t __kernel_old_uid_t;
-typedef __kernel_gid_t __kernel_old_gid_t;
-
-#if defined(__KERNEL__)
-
-#undef __FD_SET
-static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
-{
-	unsigned long __tmp = __fd / __NFDBITS;
-	unsigned long __rem = __fd % __NFDBITS;
-	__fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
-}
-
-#undef __FD_CLR
-static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
-{
-	unsigned long __tmp = __fd / __NFDBITS;
-	unsigned long __rem = __fd % __NFDBITS;
-	__fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
-}
-
-#undef __FD_ISSET
-static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
-{ 
-	unsigned long __tmp = __fd / __NFDBITS;
-	unsigned long __rem = __fd % __NFDBITS;
-	return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
-}
-
-/*
- * This will unroll the loop for the normal constant case (8 ints,
- * for a 256-bit fd_set)
- */
-#undef __FD_ZERO
-static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
-{
-	unsigned long *__tmp = __p->fds_bits;
-	int __i;
-
-	if (__builtin_constant_p(__FDSET_LONGS)) {
-		switch (__FDSET_LONGS) {
-		case 16:
-			__tmp[ 0] = 0; __tmp[ 1] = 0;
-			__tmp[ 2] = 0; __tmp[ 3] = 0;
-			__tmp[ 4] = 0; __tmp[ 5] = 0;
-			__tmp[ 6] = 0; __tmp[ 7] = 0;
-			__tmp[ 8] = 0; __tmp[ 9] = 0;
-			__tmp[10] = 0; __tmp[11] = 0;
-			__tmp[12] = 0; __tmp[13] = 0;
-			__tmp[14] = 0; __tmp[15] = 0;
-			return;
-
-		case 8:
-			__tmp[ 0] = 0; __tmp[ 1] = 0;
-			__tmp[ 2] = 0; __tmp[ 3] = 0;
-			__tmp[ 4] = 0; __tmp[ 5] = 0;
-			__tmp[ 6] = 0; __tmp[ 7] = 0;
-			return;
-
-		case 4:
-			__tmp[ 0] = 0; __tmp[ 1] = 0;
-			__tmp[ 2] = 0; __tmp[ 3] = 0;
-			return;
-		}
-	}
-	__i = __FDSET_LONGS;
-	while (__i) {
-		__i--;
-		*__tmp = 0;
-		__tmp++;
-	}
-}
-
-#endif /* defined(__KERNEL__) */
-
-#endif
diff --git a/include/asm-parisc/prefetch.h b/include/asm-parisc/prefetch.h
deleted file mode 100644
index c5edc60c059f..000000000000
--- a/include/asm-parisc/prefetch.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * include/asm-parisc/prefetch.h
- *
- * PA 2.0 defines data prefetch instructions on page 6-11 of the Kane book.
- * In addition, many implementations do hardware prefetching of both
- * instructions and data.
- *
- * PA7300LC (page 14-4 of the ERS) also implements prefetching by a load
- * to gr0 but not in a way that Linux can use.  If the load would cause an
- * interruption (eg due to prefetching 0), it is suppressed on PA2.0
- * processors, but not on 7300LC.
- *
- */
-
-#ifndef __ASM_PARISC_PREFETCH_H
-#define __ASM_PARISC_PREFETCH_H
-
-#ifndef __ASSEMBLY__
-#ifdef CONFIG_PREFETCH
-
-#define ARCH_HAS_PREFETCH
-static inline void prefetch(const void *addr)
-{
-	__asm__("ldw 0(%0), %%r0" : : "r" (addr));
-}
-
-/* LDD is a PA2.0 addition. */
-#ifdef CONFIG_PA20
-#define ARCH_HAS_PREFETCHW
-static inline void prefetchw(const void *addr)
-{
-	__asm__("ldd 0(%0), %%r0" : : "r" (addr));
-}
-#endif /* CONFIG_PA20 */
-
-#endif /* CONFIG_PREFETCH */
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ASM_PARISC_PROCESSOR_H */
diff --git a/include/asm-parisc/processor.h b/include/asm-parisc/processor.h
deleted file mode 100644
index 3c9d34844c83..000000000000
--- a/include/asm-parisc/processor.h
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * include/asm-parisc/processor.h
- *
- * Copyright (C) 1994 Linus Torvalds
- * Copyright (C) 2001 Grant Grundler
- */
-
-#ifndef __ASM_PARISC_PROCESSOR_H
-#define __ASM_PARISC_PROCESSOR_H
-
-#ifndef __ASSEMBLY__
-#include <linux/threads.h>
-
-#include <asm/prefetch.h>
-#include <asm/hardware.h>
-#include <asm/pdc.h>
-#include <asm/ptrace.h>
-#include <asm/types.h>
-#include <asm/system.h>
-#endif /* __ASSEMBLY__ */
-
-#define KERNEL_STACK_SIZE 	(4*PAGE_SIZE)
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#ifdef CONFIG_PA20
-#define current_ia(x)	__asm__("mfia %0" : "=r"(x))
-#else /* mfia added in pa2.0 */
-#define current_ia(x)	__asm__("blr 0,%0\n\tnop" : "=r"(x))
-#endif
-#define current_text_addr() ({ void *pc; current_ia(pc); pc; })
-
-#define TASK_SIZE_OF(tsk)       ((tsk)->thread.task_size)
-#define TASK_SIZE	        TASK_SIZE_OF(current)
-#define TASK_UNMAPPED_BASE      (current->thread.map_base)
-
-#define DEFAULT_TASK_SIZE32	(0xFFF00000UL)
-#define DEFAULT_MAP_BASE32	(0x40000000UL)
-
-#ifdef CONFIG_64BIT
-#define DEFAULT_TASK_SIZE       (MAX_ADDRESS-0xf000000)
-#define DEFAULT_MAP_BASE        (0x200000000UL)
-#else
-#define DEFAULT_TASK_SIZE	DEFAULT_TASK_SIZE32
-#define DEFAULT_MAP_BASE	DEFAULT_MAP_BASE32
-#endif
-
-#ifdef __KERNEL__
-
-/* XXX: STACK_TOP actually should be STACK_BOTTOM for parisc.
- * prumpf */
-
-#define STACK_TOP	TASK_SIZE
-#define STACK_TOP_MAX	DEFAULT_TASK_SIZE
-
-#endif
-
-#ifndef __ASSEMBLY__
-
-/*
- * Data detected about CPUs at boot time which is the same for all CPU's.
- * HP boxes are SMP - ie identical processors.
- *
- * FIXME: some CPU rev info may be processor specific...
- */
-struct system_cpuinfo_parisc {
-	unsigned int	cpu_count;
-	unsigned int	cpu_hz;
-	unsigned int	hversion;
-	unsigned int	sversion;
-	enum cpu_type	cpu_type;
-
-	struct {
-		struct pdc_model model;
-		unsigned long versions;
-		unsigned long cpuid;
-		unsigned long capabilities;
-		char   sys_model_name[81]; /* PDC-ROM returnes this model name */
-	} pdc;
-
-	const char	*cpu_name;	/* e.g. "PA7300LC (PCX-L2)" */
-	const char	*family_name;	/* e.g. "1.1e" */
-};
-
-
-/* Per CPU data structure - ie varies per CPU.  */
-struct cpuinfo_parisc {
-	unsigned long it_value;     /* Interval Timer at last timer Intr */
-	unsigned long it_delta;     /* Interval delta (tic_10ms / HZ * 100) */
-	unsigned long irq_count;    /* number of IRQ's since boot */
-	unsigned long irq_max_cr16; /* longest time to handle a single IRQ */
-	unsigned long cpuid;        /* aka slot_number or set to NO_PROC_ID */
-	unsigned long hpa;          /* Host Physical address */
-	unsigned long txn_addr;     /* MMIO addr of EIR or id_eid */
-#ifdef CONFIG_SMP
-	unsigned long pending_ipi;  /* bitmap of type ipi_message_type */
-	unsigned long ipi_count;    /* number ipi Interrupts */
-#endif
-	unsigned long bh_count;     /* number of times bh was invoked */
-	unsigned long prof_counter; /* per CPU profiling support */
-	unsigned long prof_multiplier;	/* per CPU profiling support */
-	unsigned long fp_rev;
-	unsigned long fp_model;
-	unsigned int state;
-	struct parisc_device *dev;
-	unsigned long loops_per_jiffy;
-};
-
-extern struct system_cpuinfo_parisc boot_cpu_data;
-extern struct cpuinfo_parisc cpu_data[NR_CPUS];
-#define current_cpu_data cpu_data[smp_processor_id()]
-
-#define CPU_HVERSION ((boot_cpu_data.hversion >> 4) & 0x0FFF)
-
-typedef struct {
-	int seg;  
-} mm_segment_t;
-
-#define ARCH_MIN_TASKALIGN	8
-
-struct thread_struct {
-	struct pt_regs regs;
-	unsigned long  task_size;
-	unsigned long  map_base;
-	unsigned long  flags;
-}; 
-
-/* Thread struct flags. */
-#define PARISC_UAC_NOPRINT	(1UL << 0)	/* see prctl and unaligned.c */
-#define PARISC_UAC_SIGBUS	(1UL << 1)
-#define PARISC_KERNEL_DEATH	(1UL << 31)	/* see die_if_kernel()... */
-
-#define PARISC_UAC_SHIFT	0
-#define PARISC_UAC_MASK		(PARISC_UAC_NOPRINT|PARISC_UAC_SIGBUS)
-
-#define SET_UNALIGN_CTL(task,value)                                       \
-        ({                                                                \
-        (task)->thread.flags = (((task)->thread.flags & ~PARISC_UAC_MASK) \
-                                | (((value) << PARISC_UAC_SHIFT) &        \
-                                   PARISC_UAC_MASK));                     \
-        0;                                                                \
-        })
-
-#define GET_UNALIGN_CTL(task,addr)                                        \
-        ({                                                                \
-        put_user(((task)->thread.flags & PARISC_UAC_MASK)                 \
-                 >> PARISC_UAC_SHIFT, (int __user *) (addr));             \
-        })
-
-#define INIT_THREAD { \
-	.regs = {	.gr	= { 0, }, \
-			.fr	= { 0, }, \
-			.sr	= { 0, }, \
-			.iasq	= { 0, }, \
-			.iaoq	= { 0, }, \
-			.cr27	= 0, \
-		}, \
-	.task_size	= DEFAULT_TASK_SIZE, \
-	.map_base	= DEFAULT_MAP_BASE, \
-	.flags		= 0 \
-	}
-
-/*
- * Return saved PC of a blocked thread.  This is used by ps mostly.
- */
-
-unsigned long thread_saved_pc(struct task_struct *t);
-void show_trace(struct task_struct *task, unsigned long *stack);
-
-/*
- * Start user thread in another space.
- *
- * Note that we set both the iaoq and r31 to the new pc. When
- * the kernel initially calls execve it will return through an
- * rfi path that will use the values in the iaoq. The execve
- * syscall path will return through the gateway page, and
- * that uses r31 to branch to.
- *
- * For ELF we clear r23, because the dynamic linker uses it to pass
- * the address of the finalizer function.
- *
- * We also initialize sr3 to an illegal value (illegal for our
- * implementation, not for the architecture).
- */
-typedef unsigned int elf_caddr_t;
-
-#define start_thread_som(regs, new_pc, new_sp) do {	\
-	unsigned long *sp = (unsigned long *)new_sp;	\
-	__u32 spaceid = (__u32)current->mm->context;	\
-	unsigned long pc = (unsigned long)new_pc;	\
-	/* offset pc for priv. level */			\
-	pc |= 3;					\
-							\
-	set_fs(USER_DS);				\
-	regs->iasq[0] = spaceid;			\
-	regs->iasq[1] = spaceid;			\
-	regs->iaoq[0] = pc;				\
-	regs->iaoq[1] = pc + 4;                         \
-	regs->sr[2] = LINUX_GATEWAY_SPACE;              \
-	regs->sr[3] = 0xffff;				\
-	regs->sr[4] = spaceid;				\
-	regs->sr[5] = spaceid;				\
-	regs->sr[6] = spaceid;				\
-	regs->sr[7] = spaceid;				\
-	regs->gr[ 0] = USER_PSW;                        \
-	regs->gr[30] = ((new_sp)+63)&~63;		\
-	regs->gr[31] = pc;				\
-							\
-	get_user(regs->gr[26],&sp[0]);			\
-	get_user(regs->gr[25],&sp[-1]); 		\
-	get_user(regs->gr[24],&sp[-2]); 		\
-	get_user(regs->gr[23],&sp[-3]); 		\
-} while(0)
-
-/* The ELF abi wants things done a "wee bit" differently than
- * som does.  Supporting this behavior here avoids
- * having our own version of create_elf_tables.
- *
- * Oh, and yes, that is not a typo, we are really passing argc in r25
- * and argv in r24 (rather than r26 and r25).  This is because that's
- * where __libc_start_main wants them.
- *
- * Duplicated from dl-machine.h for the benefit of readers:
- *
- *  Our initial stack layout is rather different from everyone else's
- *  due to the unique PA-RISC ABI.  As far as I know it looks like
- *  this:
-
-   -----------------------------------  (user startup code creates this frame)
-   |         32 bytes of magic       |
-   |---------------------------------|
-   | 32 bytes argument/sp save area  |
-   |---------------------------------| (bprm->p)
-   |	    ELF auxiliary info	     |
-   |         (up to 28 words)        |
-   |---------------------------------|
-   |		   NULL		     |
-   |---------------------------------|
-   |	   Environment pointers	     |
-   |---------------------------------|
-   |		   NULL		     |
-   |---------------------------------|
-   |        Argument pointers        |
-   |---------------------------------| <- argv
-   |          argc (1 word)          |
-   |---------------------------------| <- bprm->exec (HACK!)
-   |         N bytes of slack        |
-   |---------------------------------|
-   |	filename passed to execve    |
-   |---------------------------------| (mm->env_end)
-   |           env strings           |
-   |---------------------------------| (mm->env_start, mm->arg_end)
-   |           arg strings           |
-   |---------------------------------|
-   | additional faked arg strings if |
-   | we're invoked via binfmt_script |
-   |---------------------------------| (mm->arg_start)
-   stack base is at TASK_SIZE - rlim_max.
-
-on downward growing arches, it looks like this:
-   stack base at TASK_SIZE
-   | filename passed to execve
-   | env strings
-   | arg strings
-   | faked arg strings
-   | slack
-   | ELF
-   | envps
-   | argvs
-   | argc
-
- *  The pleasant part of this is that if we need to skip arguments we
- *  can just decrement argc and move argv, because the stack pointer
- *  is utterly unrelated to the location of the environment and
- *  argument vectors.
- *
- * Note that the S/390 people took the easy way out and hacked their
- * GCC to make the stack grow downwards.
- *
- * Final Note: For entry from syscall, the W (wide) bit of the PSW
- * is stuffed into the lowest bit of the user sp (%r30), so we fill
- * it in here from the current->personality
- */
-
-#ifdef CONFIG_64BIT
-#define USER_WIDE_MODE	(!test_thread_flag(TIF_32BIT))
-#else
-#define USER_WIDE_MODE	0
-#endif
-
-#define start_thread(regs, new_pc, new_sp) do {		\
-	elf_addr_t *sp = (elf_addr_t *)new_sp;		\
-	__u32 spaceid = (__u32)current->mm->context;	\
-	elf_addr_t pc = (elf_addr_t)new_pc | 3;		\
-	elf_caddr_t *argv = (elf_caddr_t *)bprm->exec + 1;	\
-							\
-	set_fs(USER_DS);				\
-	regs->iasq[0] = spaceid;			\
-	regs->iasq[1] = spaceid;			\
-	regs->iaoq[0] = pc;				\
-	regs->iaoq[1] = pc + 4;                         \
-	regs->sr[2] = LINUX_GATEWAY_SPACE;              \
-	regs->sr[3] = 0xffff;				\
-	regs->sr[4] = spaceid;				\
-	regs->sr[5] = spaceid;				\
-	regs->sr[6] = spaceid;				\
-	regs->sr[7] = spaceid;				\
-	regs->gr[ 0] = USER_PSW | (USER_WIDE_MODE ? PSW_W : 0); \
-	regs->fr[ 0] = 0LL;                            	\
-	regs->fr[ 1] = 0LL;                            	\
-	regs->fr[ 2] = 0LL;                            	\
-	regs->fr[ 3] = 0LL;                            	\
-	regs->gr[30] = (((unsigned long)sp + 63) &~ 63) | (USER_WIDE_MODE ? 1 : 0); \
-	regs->gr[31] = pc;				\
-							\
-	get_user(regs->gr[25], (argv - 1));		\
-	regs->gr[24] = (long) argv;			\
-	regs->gr[23] = 0;				\
-} while(0)
-
-struct task_struct;
-struct mm_struct;
-
-/* Free all resources held by a thread. */
-extern void release_thread(struct task_struct *);
-extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
-
-/* Prepare to copy thread state - unlazy all lazy status */
-#define prepare_to_copy(tsk)	do { } while (0)
-
-extern void map_hpux_gateway_page(struct task_struct *tsk, struct mm_struct *mm);
-
-extern unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk)	((tsk)->thread.regs.iaoq[0])
-#define KSTK_ESP(tsk)	((tsk)->thread.regs.gr[30])
-
-#define cpu_relax()	barrier()
-
-/* Used as a macro to identify the combined VIPT/PIPT cached
- * CPUs which require a guarantee of coherency (no inequivalent
- * aliases with different data, whether clean or not) to operate */
-static inline int parisc_requires_coherency(void)
-{
-#ifdef CONFIG_PA8X00
-	return (boot_cpu_data.cpu_type == mako) ||
-		(boot_cpu_data.cpu_type == mako2);
-#else
-	return 0;
-#endif
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ASM_PARISC_PROCESSOR_H */
diff --git a/include/asm-parisc/psw.h b/include/asm-parisc/psw.h
deleted file mode 100644
index 5a3e23c9ce63..000000000000
--- a/include/asm-parisc/psw.h
+++ /dev/null
@@ -1,62 +0,0 @@
-#ifndef _PARISC_PSW_H
-
-
-#define	PSW_I	0x00000001
-#define	PSW_D	0x00000002
-#define	PSW_P	0x00000004
-#define	PSW_Q	0x00000008
-
-#define	PSW_R	0x00000010
-#define	PSW_F	0x00000020
-#define	PSW_G	0x00000040	/* PA1.x only */
-#define PSW_O	0x00000080	/* PA2.0 only */
-
-/* ssm/rsm instructions number PSW_W and PSW_E differently */
-#define PSW_SM_I	PSW_I	/* Enable External Interrupts */
-#define PSW_SM_D	PSW_D
-#define PSW_SM_P	PSW_P
-#define PSW_SM_Q	PSW_Q	/* Enable Interrupt State Collection */
-#define PSW_SM_R	PSW_R	/* Enable Recover Counter Trap */
-#define PSW_SM_W	0x200	/* PA2.0 only : Enable Wide Mode */
-
-#define PSW_SM_QUIET	PSW_SM_R+PSW_SM_Q+PSW_SM_P+PSW_SM_D+PSW_SM_I
-
-#define PSW_CB	0x0000ff00
-
-#define	PSW_M	0x00010000
-#define	PSW_V	0x00020000
-#define	PSW_C	0x00040000
-#define	PSW_B	0x00080000
-
-#define	PSW_X	0x00100000
-#define	PSW_N	0x00200000
-#define	PSW_L	0x00400000
-#define	PSW_H	0x00800000
-
-#define	PSW_T	0x01000000
-#define	PSW_S	0x02000000
-#define	PSW_E	0x04000000
-#define PSW_W	0x08000000	/* PA2.0 only */
-#define PSW_W_BIT       36      /* PA2.0 only */
-
-#define	PSW_Z	0x40000000	/* PA1.x only */
-#define	PSW_Y	0x80000000	/* PA1.x only */
-
-#ifdef CONFIG_64BIT
-#  define PSW_HI_CB 0x000000ff    /* PA2.0 only */
-#endif
-
-#ifdef CONFIG_64BIT
-#  define USER_PSW_HI_MASK	PSW_HI_CB
-#  define WIDE_PSW		PSW_W
-#else 
-#  define WIDE_PSW		0
-#endif
-
-/* Used when setting up for rfi */
-#define KERNEL_PSW    (WIDE_PSW | PSW_C | PSW_Q | PSW_P | PSW_D)
-#define REAL_MODE_PSW (WIDE_PSW | PSW_Q)
-#define USER_PSW_MASK (WIDE_PSW | PSW_T | PSW_N | PSW_X | PSW_B | PSW_V | PSW_CB)
-#define USER_PSW      (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I)
-
-#endif
diff --git a/include/asm-parisc/ptrace.h b/include/asm-parisc/ptrace.h
deleted file mode 100644
index 3e94c5d85ff5..000000000000
--- a/include/asm-parisc/ptrace.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef _PARISC_PTRACE_H
-#define _PARISC_PTRACE_H
-
-/* written by Philipp Rumpf, Copyright (C) 1999 SuSE GmbH Nuernberg
-** Copyright (C) 2000 Grant Grundler, Hewlett-Packard
-*/
-
-#include <linux/types.h>
-
-/* This struct defines the way the registers are stored on the 
- * stack during a system call.
- *
- * N.B. gdb/strace care about the size and offsets within this
- * structure. If you change things, you may break object compatibility
- * for those applications.
- */
-
-struct pt_regs {
-	unsigned long gr[32];	/* PSW is in gr[0] */
-	__u64 fr[32];
-	unsigned long sr[ 8];
-	unsigned long iasq[2];
-	unsigned long iaoq[2];
-	unsigned long cr27;
-	unsigned long pad0;     /* available for other uses */
-	unsigned long orig_r28;
-	unsigned long ksp;
-	unsigned long kpc;
-	unsigned long sar;	/* CR11 */
-	unsigned long iir;	/* CR19 */
-	unsigned long isr;	/* CR20 */
-	unsigned long ior;	/* CR21 */
-	unsigned long ipsw;	/* CR22 */
-};
-
-/*
- * The numbers chosen here are somewhat arbitrary but absolutely MUST
- * not overlap with any of the number assigned in <linux/ptrace.h>.
- *
- * These ones are taken from IA-64 on the assumption that theirs are
- * the most correct (and we also want to support PTRACE_SINGLEBLOCK
- * since we have taken branch traps too)
- */
-#define PTRACE_SINGLEBLOCK	12	/* resume execution until next branch */
-
-#ifdef __KERNEL__
-
-#define task_regs(task) ((struct pt_regs *) ((char *)(task) + TASK_REGS))
-
-/* XXX should we use iaoq[1] or iaoq[0] ? */
-#define user_mode(regs)			(((regs)->iaoq[0] & 3) ? 1 : 0)
-#define user_space(regs)		(((regs)->iasq[1] != 0) ? 1 : 0)
-#define instruction_pointer(regs)	((regs)->iaoq[0] & ~3)
-unsigned long profile_pc(struct pt_regs *);
-extern void show_regs(struct pt_regs *);
-#endif
-
-#endif
diff --git a/include/asm-parisc/real.h b/include/asm-parisc/real.h
deleted file mode 100644
index 82acb25db395..000000000000
--- a/include/asm-parisc/real.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifndef _PARISC_REAL_H
-#define _PARISC_REAL_H
-
-
-#endif
diff --git a/include/asm-parisc/resource.h b/include/asm-parisc/resource.h
deleted file mode 100644
index 8b06343b62ed..000000000000
--- a/include/asm-parisc/resource.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _ASM_PARISC_RESOURCE_H
-#define _ASM_PARISC_RESOURCE_H
-
-#define _STK_LIM_MAX	10 * _STK_LIM
-#include <asm-generic/resource.h>
-
-#endif
diff --git a/include/asm-parisc/ropes.h b/include/asm-parisc/ropes.h
deleted file mode 100644
index 007a880615eb..000000000000
--- a/include/asm-parisc/ropes.h
+++ /dev/null
@@ -1,322 +0,0 @@
-#ifndef _ASM_PARISC_ROPES_H_
-#define _ASM_PARISC_ROPES_H_
-
-#include <asm-parisc/parisc-device.h>
-
-#ifdef CONFIG_64BIT
-/* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
-#define ZX1_SUPPORT
-#endif
-
-#ifdef CONFIG_PROC_FS
-/* depends on proc fs support. But costs CPU performance */
-#undef SBA_COLLECT_STATS
-#endif
-
-/*
-** The number of pdir entries to "free" before issuing
-** a read to PCOM register to flush out PCOM writes.
-** Interacts with allocation granularity (ie 4 or 8 entries
-** allocated and free'd/purged at a time might make this
-** less interesting).
-*/
-#define DELAYED_RESOURCE_CNT	16
-
-#define MAX_IOC		2	/* per Ike. Pluto/Astro only have 1. */
-#define ROPES_PER_IOC	8	/* per Ike half or Pluto/Astro */
-
-struct ioc {
-	void __iomem	*ioc_hpa;	/* I/O MMU base address */
-	char		*res_map;	/* resource map, bit == pdir entry */
-	u64		*pdir_base;	/* physical base address */
-	unsigned long	ibase;		/* pdir IOV Space base - shared w/lba_pci */
-	unsigned long	imask;		/* pdir IOV Space mask - shared w/lba_pci */
-#ifdef ZX1_SUPPORT
-	unsigned long	iovp_mask;	/* help convert IOVA to IOVP */
-#endif
-	unsigned long	*res_hint;	/* next avail IOVP - circular search */
-	spinlock_t	res_lock;
-	unsigned int	res_bitshift;	/* from the LEFT! */
-	unsigned int	res_size;	/* size of resource map in bytes */
-#ifdef SBA_HINT_SUPPORT
-/* FIXME : DMA HINTs not used */
-	unsigned long	hint_mask_pdir; /* bits used for DMA hints */
-	unsigned int	hint_shift_pdir;
-#endif
-#if DELAYED_RESOURCE_CNT > 0
-	int		saved_cnt;
-	struct sba_dma_pair {
-			dma_addr_t	iova;
-			size_t		size;
-        } saved[DELAYED_RESOURCE_CNT];
-#endif
-
-#ifdef SBA_COLLECT_STATS
-#define SBA_SEARCH_SAMPLE	0x100
-	unsigned long	avg_search[SBA_SEARCH_SAMPLE];
-	unsigned long	avg_idx;	/* current index into avg_search */
-	unsigned long	used_pages;
-	unsigned long	msingle_calls;
-	unsigned long	msingle_pages;
-	unsigned long	msg_calls;
-	unsigned long	msg_pages;
-	unsigned long	usingle_calls;
-	unsigned long	usingle_pages;
-	unsigned long	usg_calls;
-	unsigned long	usg_pages;
-#endif
-        /* STUFF We don't need in performance path */
-	unsigned int	pdir_size;	/* in bytes, determined by IOV Space size */
-};
-
-struct sba_device {
-	struct sba_device	*next;  /* list of SBA's in system */
-	struct parisc_device	*dev;   /* dev found in bus walk */
-	const char		*name;
-	void __iomem		*sba_hpa; /* base address */
-	spinlock_t		sba_lock;
-	unsigned int		flags;  /* state/functionality enabled */
-	unsigned int		hw_rev;  /* HW revision of chip */
-
-	struct resource		chip_resv; /* MMIO reserved for chip */
-	struct resource		iommu_resv; /* MMIO reserved for iommu */
-
-	unsigned int		num_ioc;  /* number of on-board IOC's */
-	struct ioc		ioc[MAX_IOC];
-};
-
-#define ASTRO_RUNWAY_PORT	0x582
-#define IKE_MERCED_PORT		0x803
-#define REO_MERCED_PORT		0x804
-#define REOG_MERCED_PORT	0x805
-#define PLUTO_MCKINLEY_PORT	0x880
-
-static inline int IS_ASTRO(struct parisc_device *d) {
-	return d->id.hversion == ASTRO_RUNWAY_PORT;
-}
-
-static inline int IS_IKE(struct parisc_device *d) {
-	return d->id.hversion == IKE_MERCED_PORT;
-}
-
-static inline int IS_PLUTO(struct parisc_device *d) {
-	return d->id.hversion == PLUTO_MCKINLEY_PORT;
-}
-
-#define PLUTO_IOVA_BASE	(1UL*1024*1024*1024)	/* 1GB */
-#define PLUTO_IOVA_SIZE	(1UL*1024*1024*1024)	/* 1GB */
-#define PLUTO_GART_SIZE	(PLUTO_IOVA_SIZE / 2)
-
-#define SBA_PDIR_VALID_BIT	0x8000000000000000ULL
-
-#define SBA_AGPGART_COOKIE	0x0000badbadc0ffeeULL
-
-#define SBA_FUNC_ID	0x0000	/* function id */
-#define SBA_FCLASS	0x0008	/* function class, bist, header, rev... */
-
-#define SBA_FUNC_SIZE 4096   /* SBA configuration function reg set */
-
-#define ASTRO_IOC_OFFSET	(32 * SBA_FUNC_SIZE)
-#define PLUTO_IOC_OFFSET	(1 * SBA_FUNC_SIZE)
-/* Ike's IOC's occupy functions 2 and 3 */
-#define IKE_IOC_OFFSET(p)	((p+2) * SBA_FUNC_SIZE)
-
-#define IOC_CTRL          0x8	/* IOC_CTRL offset */
-#define IOC_CTRL_TC       (1 << 0) /* TOC Enable */
-#define IOC_CTRL_CE       (1 << 1) /* Coalesce Enable */
-#define IOC_CTRL_DE       (1 << 2) /* Dillon Enable */
-#define IOC_CTRL_RM       (1 << 8) /* Real Mode */
-#define IOC_CTRL_NC       (1 << 9) /* Non Coherent Mode */
-#define IOC_CTRL_D4       (1 << 11) /* Disable 4-byte coalescing */
-#define IOC_CTRL_DD       (1 << 13) /* Disable distr. LMMIO range coalescing */
-
-/*
-** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
-** Firmware programs this stuff. Don't touch it.
-*/
-#define LMMIO_DIRECT0_BASE  0x300
-#define LMMIO_DIRECT0_MASK  0x308
-#define LMMIO_DIRECT0_ROUTE 0x310
-
-#define LMMIO_DIST_BASE  0x360
-#define LMMIO_DIST_MASK  0x368
-#define LMMIO_DIST_ROUTE 0x370
-
-#define IOS_DIST_BASE	0x390
-#define IOS_DIST_MASK	0x398
-#define IOS_DIST_ROUTE	0x3A0
-
-#define IOS_DIRECT_BASE	0x3C0
-#define IOS_DIRECT_MASK	0x3C8
-#define IOS_DIRECT_ROUTE 0x3D0
-
-/*
-** Offsets into I/O TLB (Function 2 and 3 on Ike)
-*/
-#define ROPE0_CTL	0x200  /* "regbus pci0" */
-#define ROPE1_CTL	0x208
-#define ROPE2_CTL	0x210
-#define ROPE3_CTL	0x218
-#define ROPE4_CTL	0x220
-#define ROPE5_CTL	0x228
-#define ROPE6_CTL	0x230
-#define ROPE7_CTL	0x238
-
-#define IOC_ROPE0_CFG	0x500	/* pluto only */
-#define   IOC_ROPE_AO	  0x10	/* Allow "Relaxed Ordering" */
-
-#define HF_ENABLE	0x40
-
-#define IOC_IBASE	0x300	/* IO TLB */
-#define IOC_IMASK	0x308
-#define IOC_PCOM	0x310
-#define IOC_TCNFG	0x318
-#define IOC_PDIR_BASE	0x320
-
-/*
-** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
-** It's safer (avoid memory corruption) to keep DMA page mappings
-** equivalently sized to VM PAGE_SIZE.
-**
-** We really can't avoid generating a new mapping for each
-** page since the Virtual Coherence Index has to be generated
-** and updated for each page.
-**
-** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse.
-*/
-#define IOVP_SIZE	PAGE_SIZE
-#define IOVP_SHIFT	PAGE_SHIFT
-#define IOVP_MASK	PAGE_MASK
-
-#define SBA_PERF_CFG	0x708	/* Performance Counter stuff */
-#define SBA_PERF_MASK1	0x718
-#define SBA_PERF_MASK2	0x730
-
-/*
-** Offsets into PCI Performance Counters (functions 12 and 13)
-** Controlled by PERF registers in function 2 & 3 respectively.
-*/
-#define SBA_PERF_CNT1	0x200
-#define SBA_PERF_CNT2	0x208
-#define SBA_PERF_CNT3	0x210
-
-/*
-** lba_device: Per instance Elroy data structure
-*/
-struct lba_device {
-	struct pci_hba_data	hba;
-
-	spinlock_t		lba_lock;
-	void			*iosapic_obj;
-
-#ifdef CONFIG_64BIT
-	void __iomem		*iop_base;	/* PA_VIEW - for IO port accessor funcs */
-#endif
-
-	int			flags;		/* state/functionality enabled */
-	int			hw_rev;		/* HW revision of chip */
-};
-
-#define ELROY_HVERS		0x782
-#define MERCURY_HVERS		0x783
-#define QUICKSILVER_HVERS	0x784
-
-static inline int IS_ELROY(struct parisc_device *d) {
-	return (d->id.hversion == ELROY_HVERS);
-}
-
-static inline int IS_MERCURY(struct parisc_device *d) {
-	return (d->id.hversion == MERCURY_HVERS);
-}
-
-static inline int IS_QUICKSILVER(struct parisc_device *d) {
-	return (d->id.hversion == QUICKSILVER_HVERS);
-}
-
-static inline int agp_mode_mercury(void __iomem *hpa) {
-	u64 bus_mode;
-
-	bus_mode = readl(hpa + 0x0620);
-	if (bus_mode & 1)
-		return 1;
-
-	return 0;
-}
-
-/*
-** I/O SAPIC init function
-** Caller knows where an I/O SAPIC is. LBA has an integrated I/O SAPIC.
-** Call setup as part of per instance initialization.
-** (ie *not* init_module() function unless only one is present.)
-** fixup_irq is to initialize PCI IRQ line support and
-** virtualize pcidev->irq value. To be called by pci_fixup_bus().
-*/
-extern void *iosapic_register(unsigned long hpa);
-extern int iosapic_fixup_irq(void *obj, struct pci_dev *pcidev);
-
-#define LBA_FUNC_ID	0x0000	/* function id */
-#define LBA_FCLASS	0x0008	/* function class, bist, header, rev... */
-#define LBA_CAPABLE	0x0030	/* capabilities register */
-
-#define LBA_PCI_CFG_ADDR	0x0040	/* poke CFG address here */
-#define LBA_PCI_CFG_DATA	0x0048	/* read or write data here */
-
-#define LBA_PMC_MTLT	0x0050	/* Firmware sets this - read only. */
-#define LBA_FW_SCRATCH	0x0058	/* Firmware writes the PCI bus number here. */
-#define LBA_ERROR_ADDR	0x0070	/* On error, address gets logged here */
-
-#define LBA_ARB_MASK	0x0080	/* bit 0 enable arbitration. PAT/PDC enables */
-#define LBA_ARB_PRI	0x0088	/* firmware sets this. */
-#define LBA_ARB_MODE	0x0090	/* firmware sets this. */
-#define LBA_ARB_MTLT	0x0098	/* firmware sets this. */
-
-#define LBA_MOD_ID	0x0100	/* Module ID. PDC_PAT_CELL reports 4 */
-
-#define LBA_STAT_CTL	0x0108	/* Status & Control */
-#define   LBA_BUS_RESET		0x01	/*  Deassert PCI Bus Reset Signal */
-#define   CLEAR_ERRLOG		0x10	/*  "Clear Error Log" cmd */
-#define   CLEAR_ERRLOG_ENABLE	0x20	/*  "Clear Error Log" Enable */
-#define   HF_ENABLE	0x40	/*    enable HF mode (default is -1 mode) */
-
-#define LBA_LMMIO_BASE	0x0200	/* < 4GB I/O address range */
-#define LBA_LMMIO_MASK	0x0208
-
-#define LBA_GMMIO_BASE	0x0210	/* > 4GB I/O address range */
-#define LBA_GMMIO_MASK	0x0218
-
-#define LBA_WLMMIO_BASE	0x0220	/* All < 4GB ranges under the same *SBA* */
-#define LBA_WLMMIO_MASK	0x0228
-
-#define LBA_WGMMIO_BASE	0x0230	/* All > 4GB ranges under the same *SBA* */
-#define LBA_WGMMIO_MASK	0x0238
-
-#define LBA_IOS_BASE	0x0240	/* I/O port space for this LBA */
-#define LBA_IOS_MASK	0x0248
-
-#define LBA_ELMMIO_BASE	0x0250	/* Extra LMMIO range */
-#define LBA_ELMMIO_MASK	0x0258
-
-#define LBA_EIOS_BASE	0x0260	/* Extra I/O port space */
-#define LBA_EIOS_MASK	0x0268
-
-#define LBA_GLOBAL_MASK	0x0270	/* Mercury only: Global Address Mask */
-#define LBA_DMA_CTL	0x0278	/* firmware sets this */
-
-#define LBA_IBASE	0x0300	/* SBA DMA support */
-#define LBA_IMASK	0x0308
-
-/* FIXME: ignore DMA Hint stuff until we can measure performance */
-#define LBA_HINT_CFG	0x0310
-#define LBA_HINT_BASE	0x0380	/* 14 registers at every 8 bytes. */
-
-#define LBA_BUS_MODE	0x0620
-
-/* ERROR regs are needed for config cycle kluges */
-#define LBA_ERROR_CONFIG 0x0680
-#define     LBA_SMART_MODE 0x20
-#define LBA_ERROR_STATUS 0x0688
-#define LBA_ROPE_CTL     0x06A0
-
-#define LBA_IOSAPIC_BASE	0x800 /* Offset of IRQ logic */
-
-#endif /*_ASM_PARISC_ROPES_H_*/
diff --git a/include/asm-parisc/rt_sigframe.h b/include/asm-parisc/rt_sigframe.h
deleted file mode 100644
index f0dd3b30f6c4..000000000000
--- a/include/asm-parisc/rt_sigframe.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef _ASM_PARISC_RT_SIGFRAME_H
-#define _ASM_PARISC_RT_SIGFRAME_H
-
-#define SIGRETURN_TRAMP 4
-#define SIGRESTARTBLOCK_TRAMP 5 
-#define TRAMP_SIZE (SIGRETURN_TRAMP + SIGRESTARTBLOCK_TRAMP)
-
-struct rt_sigframe {
-	/* XXX: Must match trampoline size in arch/parisc/kernel/signal.c 
-	        Secondary to that it must protect the ERESTART_RESTARTBLOCK
-		trampoline we left on the stack (we were bad and didn't 
-		change sp so we could run really fast.) */
-	unsigned int tramp[TRAMP_SIZE];
-	struct siginfo info;
-	struct ucontext uc;
-};
-
-#define	SIGFRAME		128
-#define FUNCTIONCALLFRAME	96
-#define PARISC_RT_SIGFRAME_SIZE					\
-	(((sizeof(struct rt_sigframe) + FUNCTIONCALLFRAME) + SIGFRAME) & -SIGFRAME)
-
-#endif
diff --git a/include/asm-parisc/rtc.h b/include/asm-parisc/rtc.h
deleted file mode 100644
index 099d641a42c2..000000000000
--- a/include/asm-parisc/rtc.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/* 
- * include/asm-parisc/rtc.h
- *
- * Copyright 2002 Randolph CHung <tausq@debian.org>
- *
- * Based on: include/asm-ppc/rtc.h and the genrtc driver in the
- * 2.4 parisc linux tree
- */
-
-#ifndef __ASM_RTC_H__
-#define __ASM_RTC_H__
-
-#ifdef __KERNEL__
-
-#include <linux/rtc.h>
-
-#include <asm/pdc.h>
-
-#define SECS_PER_HOUR   (60 * 60)
-#define SECS_PER_DAY    (SECS_PER_HOUR * 24)
-
-
-#define RTC_PIE 0x40		/* periodic interrupt enable */
-#define RTC_AIE 0x20		/* alarm interrupt enable */
-#define RTC_UIE 0x10		/* update-finished interrupt enable */
-
-#define RTC_BATT_BAD 0x100	/* battery bad */
-
-/* some dummy definitions */
-#define RTC_SQWE 0x08		/* enable square-wave output */
-#define RTC_DM_BINARY 0x04	/* all time/date values are BCD if clear */
-#define RTC_24H 0x02		/* 24 hour mode - else hours bit 7 means pm */
-#define RTC_DST_EN 0x01	        /* auto switch DST - works f. USA only */
-
-# define __isleap(year) \
-  ((year) % 4 == 0 && ((year) % 100 != 0 || (year) % 400 == 0))
-
-/* How many days come before each month (0-12).  */
-static const unsigned short int __mon_yday[2][13] =
-{
-	/* Normal years.  */
-	{ 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334, 365 },
-	/* Leap years.  */
-	{ 0, 31, 60, 91, 121, 152, 182, 213, 244, 274, 305, 335, 366 }
-};
-
-static inline unsigned int get_rtc_time(struct rtc_time *wtime)
-{
-	struct pdc_tod tod_data;
-	long int days, rem, y;
-	const unsigned short int *ip;
-
-	memset(wtime, 0, sizeof(*wtime));
-	if (pdc_tod_read(&tod_data) < 0)
-		return RTC_24H | RTC_BATT_BAD;
-
-	// most of the remainder of this function is:
-//	Copyright (C) 1991, 1993, 1997, 1998 Free Software Foundation, Inc.
-//	This was originally a part of the GNU C Library.
-//      It is distributed under the GPL, and was swiped from offtime.c
-
-
-	days = tod_data.tod_sec / SECS_PER_DAY;
-	rem = tod_data.tod_sec % SECS_PER_DAY;
-
-	wtime->tm_hour = rem / SECS_PER_HOUR;
-	rem %= SECS_PER_HOUR;
-	wtime->tm_min = rem / 60;
-	wtime->tm_sec = rem % 60;
-
-	y = 1970;
-
-#define DIV(a, b) ((a) / (b) - ((a) % (b) < 0))
-#define LEAPS_THRU_END_OF(y) (DIV (y, 4) - DIV (y, 100) + DIV (y, 400))
-
-	while (days < 0 || days >= (__isleap (y) ? 366 : 365))
-	{
-		/* Guess a corrected year, assuming 365 days per year.  */
-		long int yg = y + days / 365 - (days % 365 < 0);
-
-		/* Adjust DAYS and Y to match the guessed year.  */
-		days -= ((yg - y) * 365
-			 + LEAPS_THRU_END_OF (yg - 1)
-			 - LEAPS_THRU_END_OF (y - 1));
-		y = yg;
-	}
-	wtime->tm_year = y - 1900;
-
-	ip = __mon_yday[__isleap(y)];
-	for (y = 11; days < (long int) ip[y]; --y)
-		continue;
-	days -= ip[y];
-	wtime->tm_mon = y;
-	wtime->tm_mday = days + 1;
-
-	return RTC_24H;
-}
-
-static int set_rtc_time(struct rtc_time *wtime)
-{
-	u_int32_t secs;
-
-	secs = mktime(wtime->tm_year + 1900, wtime->tm_mon + 1, wtime->tm_mday, 
-		      wtime->tm_hour, wtime->tm_min, wtime->tm_sec);
-
-	if(pdc_tod_set(secs, 0) < 0)
-		return -1;
-	else
-		return 0;
-
-}
-
-static inline unsigned int get_rtc_ss(void)
-{
-	struct rtc_time h;
-
-	get_rtc_time(&h);
-	return h.tm_sec;
-}
-
-static inline int get_rtc_pll(struct rtc_pll_info *pll)
-{
-	return -EINVAL;
-}
-static inline int set_rtc_pll(struct rtc_pll_info *pll)
-{
-	return -EINVAL;
-}
-
-#endif /* __KERNEL__ */
-#endif /* __ASM_RTC_H__ */
diff --git a/include/asm-parisc/runway.h b/include/asm-parisc/runway.h
deleted file mode 100644
index 5bea02da7e22..000000000000
--- a/include/asm-parisc/runway.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef ASM_PARISC_RUNWAY_H
-#define ASM_PARISC_RUNWAY_H
-#ifdef __KERNEL__
-
-/* declared in arch/parisc/kernel/setup.c */
-extern struct proc_dir_entry * proc_runway_root;
-
-#define RUNWAY_STATUS	0x10
-#define RUNWAY_DEBUG	0x40
-
-#endif /* __KERNEL__ */
-#endif /* ASM_PARISC_RUNWAY_H */
diff --git a/include/asm-parisc/scatterlist.h b/include/asm-parisc/scatterlist.h
deleted file mode 100644
index 62269b31ebf4..000000000000
--- a/include/asm-parisc/scatterlist.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef _ASM_PARISC_SCATTERLIST_H
-#define _ASM_PARISC_SCATTERLIST_H
-
-#include <asm/page.h>
-#include <asm/types.h>
-
-struct scatterlist {
-#ifdef CONFIG_DEBUG_SG
-	unsigned long sg_magic;
-#endif
-	unsigned long page_link;
-	unsigned int offset;
-
-	unsigned int length;
-
-	/* an IOVA can be 64-bits on some PA-Risc platforms. */
-	dma_addr_t iova;	/* I/O Virtual Address */
-	__u32      iova_length; /* bytes mapped */
-};
-
-#define sg_virt_addr(sg) ((unsigned long)sg_virt(sg))
-#define sg_dma_address(sg) ((sg)->iova)
-#define sg_dma_len(sg)     ((sg)->iova_length)
-
-#define ISA_DMA_THRESHOLD (~0UL)
-
-#endif /* _ASM_PARISC_SCATTERLIST_H */
diff --git a/include/asm-parisc/sections.h b/include/asm-parisc/sections.h
deleted file mode 100644
index 9d13c3507ad6..000000000000
--- a/include/asm-parisc/sections.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _PARISC_SECTIONS_H
-#define _PARISC_SECTIONS_H
-
-/* nothing to see, move along */
-#include <asm-generic/sections.h>
-
-#ifdef CONFIG_64BIT
-#undef dereference_function_descriptor
-void *dereference_function_descriptor(void *);
-#endif
-
-#endif
diff --git a/include/asm-parisc/segment.h b/include/asm-parisc/segment.h
deleted file mode 100644
index 26794ddb6524..000000000000
--- a/include/asm-parisc/segment.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __PARISC_SEGMENT_H
-#define __PARISC_SEGMENT_H
-
-/* Only here because we have some old header files that expect it.. */
-
-#endif
diff --git a/include/asm-parisc/sembuf.h b/include/asm-parisc/sembuf.h
deleted file mode 100644
index 1e59ffd3bd1e..000000000000
--- a/include/asm-parisc/sembuf.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef _PARISC_SEMBUF_H
-#define _PARISC_SEMBUF_H
-
-/* 
- * The semid64_ds structure for parisc architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct semid64_ds {
-	struct ipc64_perm sem_perm;		/* permissions .. see ipc.h */
-#ifndef CONFIG_64BIT
-	unsigned int	__pad1;
-#endif
-	__kernel_time_t	sem_otime;		/* last semop time */
-#ifndef CONFIG_64BIT
-	unsigned int	__pad2;
-#endif
-	__kernel_time_t	sem_ctime;		/* last change time */
-	unsigned int	sem_nsems;		/* no. of semaphores in array */
-	unsigned int	__unused1;
-	unsigned int	__unused2;
-};
-
-#endif /* _PARISC_SEMBUF_H */
diff --git a/include/asm-parisc/serial.h b/include/asm-parisc/serial.h
deleted file mode 100644
index d7e3cc60dbc3..000000000000
--- a/include/asm-parisc/serial.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * include/asm-parisc/serial.h
- */
-
-/*
- * This is used for 16550-compatible UARTs
- */
-#define BASE_BAUD ( 1843200 / 16 )
-
-#define SERIAL_PORT_DFNS
diff --git a/include/asm-parisc/setup.h b/include/asm-parisc/setup.h
deleted file mode 100644
index 7da2e5b8747e..000000000000
--- a/include/asm-parisc/setup.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _PARISC_SETUP_H
-#define _PARISC_SETUP_H
-
-#define COMMAND_LINE_SIZE	1024
-
-#endif /* _PARISC_SETUP_H */
diff --git a/include/asm-parisc/shmbuf.h b/include/asm-parisc/shmbuf.h
deleted file mode 100644
index 0a3eada1863b..000000000000
--- a/include/asm-parisc/shmbuf.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef _PARISC_SHMBUF_H
-#define _PARISC_SHMBUF_H
-
-/* 
- * The shmid64_ds structure for parisc architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct shmid64_ds {
-	struct ipc64_perm	shm_perm;	/* operation perms */
-#ifndef CONFIG_64BIT
-	unsigned int		__pad1;
-#endif
-	__kernel_time_t		shm_atime;	/* last attach time */
-#ifndef CONFIG_64BIT
-	unsigned int		__pad2;
-#endif
-	__kernel_time_t		shm_dtime;	/* last detach time */
-#ifndef CONFIG_64BIT
-	unsigned int		__pad3;
-#endif
-	__kernel_time_t		shm_ctime;	/* last change time */
-#ifndef CONFIG_64BIT
-	unsigned int		__pad4;
-#endif
-	size_t			shm_segsz;	/* size of segment (bytes) */
-	__kernel_pid_t		shm_cpid;	/* pid of creator */
-	__kernel_pid_t		shm_lpid;	/* pid of last operator */
-	unsigned int		shm_nattch;	/* no. of current attaches */
-	unsigned int		__unused1;
-	unsigned int		__unused2;
-};
-
-#ifdef CONFIG_64BIT
-/* The 'unsigned int' (formerly 'unsigned long') data types below will
- * ensure that a 32-bit app calling shmctl(*,IPC_INFO,*) will work on
- * a wide kernel, but if some of these values are meant to contain pointers
- * they may need to be 'long long' instead. -PB XXX FIXME
- */
-#endif
-struct shminfo64 {
-	unsigned int	shmmax;
-	unsigned int	shmmin;
-	unsigned int	shmmni;
-	unsigned int	shmseg;
-	unsigned int	shmall;
-	unsigned int	__unused1;
-	unsigned int	__unused2;
-	unsigned int	__unused3;
-	unsigned int	__unused4;
-};
-
-#endif /* _PARISC_SHMBUF_H */
diff --git a/include/asm-parisc/shmparam.h b/include/asm-parisc/shmparam.h
deleted file mode 100644
index 628ddc22faa8..000000000000
--- a/include/asm-parisc/shmparam.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _ASMPARISC_SHMPARAM_H
-#define _ASMPARISC_SHMPARAM_H
-
-#define __ARCH_FORCE_SHMLBA 	1
-
-#define SHMLBA 0x00400000   /* attach addr needs to be 4 Mb aligned */
-
-#endif /* _ASMPARISC_SHMPARAM_H */
diff --git a/include/asm-parisc/sigcontext.h b/include/asm-parisc/sigcontext.h
deleted file mode 100644
index 27ef31bb3b6e..000000000000
--- a/include/asm-parisc/sigcontext.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _ASMPARISC_SIGCONTEXT_H
-#define _ASMPARISC_SIGCONTEXT_H
-
-#define PARISC_SC_FLAG_ONSTACK 1<<0
-#define PARISC_SC_FLAG_IN_SYSCALL 1<<1
-
-/* We will add more stuff here as it becomes necessary, until we know
-   it works. */
-struct sigcontext {
-	unsigned long sc_flags;
-
-	unsigned long sc_gr[32]; /* PSW in sc_gr[0] */
-	unsigned long long sc_fr[32]; /* FIXME, do we need other state info? */
-	unsigned long sc_iasq[2];
-	unsigned long sc_iaoq[2];
-	unsigned long sc_sar; /* cr11 */
-};
-
-
-#endif
diff --git a/include/asm-parisc/siginfo.h b/include/asm-parisc/siginfo.h
deleted file mode 100644
index d7034728f377..000000000000
--- a/include/asm-parisc/siginfo.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef _PARISC_SIGINFO_H
-#define _PARISC_SIGINFO_H
-
-#include <asm-generic/siginfo.h>
-
-#undef NSIGTRAP
-#define NSIGTRAP	4
-
-#endif
diff --git a/include/asm-parisc/signal.h b/include/asm-parisc/signal.h
deleted file mode 100644
index c20356375d1d..000000000000
--- a/include/asm-parisc/signal.h
+++ /dev/null
@@ -1,153 +0,0 @@
-#ifndef _ASM_PARISC_SIGNAL_H
-#define _ASM_PARISC_SIGNAL_H
-
-#define SIGHUP		 1
-#define SIGINT		 2
-#define SIGQUIT		 3
-#define SIGILL		 4
-#define SIGTRAP		 5
-#define SIGABRT		 6
-#define SIGIOT		 6
-#define SIGEMT		 7
-#define SIGFPE		 8
-#define SIGKILL		 9
-#define SIGBUS		10
-#define SIGSEGV		11
-#define SIGSYS		12 /* Linux doesn't use this */
-#define SIGPIPE		13
-#define SIGALRM		14
-#define SIGTERM		15
-#define SIGUSR1		16
-#define SIGUSR2		17
-#define SIGCHLD		18
-#define SIGPWR		19
-#define SIGVTALRM	20
-#define SIGPROF		21
-#define SIGIO		22
-#define SIGPOLL		SIGIO
-#define SIGWINCH	23
-#define SIGSTOP		24
-#define SIGTSTP		25
-#define SIGCONT		26
-#define SIGTTIN		27
-#define SIGTTOU		28
-#define SIGURG		29
-#define SIGLOST		30 /* Linux doesn't use this either */
-#define	SIGUNUSED	31
-#define SIGRESERVE	SIGUNUSED
-
-#define SIGXCPU		33
-#define SIGXFSZ		34
-#define SIGSTKFLT	36
-
-/* These should not be considered constants from userland.  */
-#define SIGRTMIN	37
-#define SIGRTMAX	_NSIG /* it's 44 under HP/UX */
-
-/*
- * SA_FLAGS values:
- *
- * SA_ONSTACK indicates that a registered stack_t will be used.
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
- * SA_RESETHAND clears the handler when the signal is delivered.
- * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
- * SA_NODEFER prevents the current signal from being masked in the handler.
- *
- * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
- * Unix names RESETHAND and NODEFER respectively.
- */
-#define SA_ONSTACK	0x00000001
-#define SA_RESETHAND	0x00000004
-#define SA_NOCLDSTOP	0x00000008
-#define SA_SIGINFO	0x00000010
-#define SA_NODEFER	0x00000020
-#define SA_RESTART	0x00000040
-#define SA_NOCLDWAIT	0x00000080
-#define _SA_SIGGFAULT	0x00000100 /* HPUX */
-
-#define SA_NOMASK	SA_NODEFER
-#define SA_ONESHOT	SA_RESETHAND
-
-#define SA_RESTORER	0x04000000 /* obsolete -- ignored */
-
-/* 
- * sigaltstack controls
- */
-#define SS_ONSTACK	1
-#define SS_DISABLE	2
-
-#define MINSIGSTKSZ	2048
-#define SIGSTKSZ	8192
-
-#ifdef __KERNEL__
-
-#define _NSIG		64
-/* bits-per-word, where word apparently means 'long' not 'int' */
-#define _NSIG_BPW	BITS_PER_LONG
-#define _NSIG_WORDS	(_NSIG / _NSIG_BPW)
-
-#endif /* __KERNEL__ */
-
-#define SIG_BLOCK          0	/* for blocking signals */
-#define SIG_UNBLOCK        1	/* for unblocking signals */
-#define SIG_SETMASK        2	/* for setting the signal mask */
-
-#define SIG_DFL	((__sighandler_t)0)	/* default signal handling */
-#define SIG_IGN	((__sighandler_t)1)	/* ignore signal */
-#define SIG_ERR	((__sighandler_t)-1)	/* error return from signal */
-
-# ifndef __ASSEMBLY__
-
-#  include <linux/types.h>
-
-/* Avoid too many header ordering problems.  */
-struct siginfo;
-
-/* Type of a signal handler.  */
-#ifdef CONFIG_64BIT
-/* function pointers on 64-bit parisc are pointers to little structs and the
- * compiler doesn't support code which changes or tests the address of
- * the function in the little struct.  This is really ugly -PB
- */
-typedef char __user *__sighandler_t;
-#else
-typedef void __signalfn_t(int);
-typedef __signalfn_t __user *__sighandler_t;
-#endif
-
-typedef struct sigaltstack {
-	void __user *ss_sp;
-	int ss_flags;
-	size_t ss_size;
-} stack_t;
-
-#ifdef __KERNEL__
-
-/* Most things should be clean enough to redefine this at will, if care
-   is taken to make libc match.  */
-
-typedef unsigned long old_sigset_t;		/* at least 32 bits */
-
-typedef struct {
-	/* next_signal() assumes this is a long - no choice */
-	unsigned long sig[_NSIG_WORDS];
-} sigset_t;
-
-struct sigaction {
-	__sighandler_t sa_handler;
-	unsigned long sa_flags;
-	sigset_t sa_mask;		/* mask last for extensibility */
-};
-
-struct k_sigaction {
-	struct sigaction sa;
-};
-
-#define ptrace_signal_deliver(regs, cookie) do { } while (0)
-
-#include <asm/sigcontext.h>
-
-#endif /* __KERNEL__ */
-#endif /* !__ASSEMBLY */
-#endif /* _ASM_PARISC_SIGNAL_H */
diff --git a/include/asm-parisc/smp.h b/include/asm-parisc/smp.h
deleted file mode 100644
index 398cdbaf4e54..000000000000
--- a/include/asm-parisc/smp.h
+++ /dev/null
@@ -1,68 +0,0 @@
-#ifndef __ASM_SMP_H
-#define __ASM_SMP_H
-
-
-#if defined(CONFIG_SMP)
-
-/* Page Zero Location PDC will look for the address to branch to when we poke
-** slave CPUs still in "Icache loop".
-*/
-#define PDC_OS_BOOT_RENDEZVOUS     0x10
-#define PDC_OS_BOOT_RENDEZVOUS_HI  0x28
-
-#ifndef ASSEMBLY
-#include <linux/bitops.h>
-#include <linux/threads.h>	/* for NR_CPUS */
-#include <linux/cpumask.h>
-typedef unsigned long address_t;
-
-extern cpumask_t cpu_online_map;
-
-
-/*
- *	Private routines/data
- *
- *	physical and logical are equivalent until we support CPU hotplug.
- */
-#define cpu_number_map(cpu)	(cpu)
-#define cpu_logical_map(cpu)	(cpu)
-
-extern void smp_send_reschedule(int cpu);
-extern void smp_send_all_nop(void);
-
-extern void arch_send_call_function_single_ipi(int cpu);
-extern void arch_send_call_function_ipi(cpumask_t mask);
-
-#endif /* !ASSEMBLY */
-
-/*
- *	This magic constant controls our willingness to transfer
- *      a process across CPUs. Such a transfer incurs cache and tlb
- *      misses. The current value is inherited from i386. Still needs
- *      to be tuned for parisc.
- */
- 
-#define PROC_CHANGE_PENALTY	15		/* Schedule penalty */
-
-extern unsigned long cpu_present_mask;
-
-#define raw_smp_processor_id()	(current_thread_info()->cpu)
-
-#else /* CONFIG_SMP */
-
-static inline void smp_send_all_nop(void) { return; }
-
-#endif
-
-#define NO_PROC_ID		0xFF		/* No processor magic marker */
-#define ANY_PROC_ID		0xFF		/* Any processor magic marker */
-static inline int __cpu_disable (void) {
-  return 0;
-}
-static inline void __cpu_die (unsigned int cpu) {
-  while(1)
-    ;
-}
-extern int __cpu_up (unsigned int cpu);
-
-#endif /*  __ASM_SMP_H */
diff --git a/include/asm-parisc/socket.h b/include/asm-parisc/socket.h
deleted file mode 100644
index fba402c95ac2..000000000000
--- a/include/asm-parisc/socket.h
+++ /dev/null
@@ -1,62 +0,0 @@
-#ifndef _ASM_SOCKET_H
-#define _ASM_SOCKET_H
-
-#include <asm/sockios.h>
-
-/* For setsockopt(2) */
-#define SOL_SOCKET	0xffff
-
-#define SO_DEBUG	0x0001
-#define SO_REUSEADDR	0x0004
-#define SO_KEEPALIVE	0x0008
-#define SO_DONTROUTE	0x0010
-#define SO_BROADCAST	0x0020
-#define SO_LINGER	0x0080
-#define SO_OOBINLINE	0x0100
-/* To add :#define SO_REUSEPORT 0x0200 */
-#define SO_SNDBUF	0x1001
-#define SO_RCVBUF	0x1002
-#define SO_SNDBUFFORCE	0x100a
-#define SO_RCVBUFFORCE	0x100b
-#define SO_SNDLOWAT	0x1003
-#define SO_RCVLOWAT	0x1004
-#define SO_SNDTIMEO	0x1005
-#define SO_RCVTIMEO	0x1006
-#define SO_ERROR	0x1007
-#define SO_TYPE		0x1008
-#define SO_PEERNAME	0x2000
-
-#define SO_NO_CHECK	0x400b
-#define SO_PRIORITY	0x400c
-#define SO_BSDCOMPAT	0x400e
-#define SO_PASSCRED	0x4010
-#define SO_PEERCRED	0x4011
-#define SO_TIMESTAMP	0x4012
-#define SCM_TIMESTAMP	SO_TIMESTAMP
-#define SO_TIMESTAMPNS	0x4013
-#define SCM_TIMESTAMPNS	SO_TIMESTAMPNS
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION		0x4016
-#define SO_SECURITY_ENCRYPTION_TRANSPORT	0x4017
-#define SO_SECURITY_ENCRYPTION_NETWORK		0x4018
-
-#define SO_BINDTODEVICE	0x4019
-
-/* Socket filtering */
-#define SO_ATTACH_FILTER        0x401a
-#define SO_DETACH_FILTER        0x401b
-
-#define SO_ACCEPTCONN		0x401c
-
-#define SO_PEERSEC		0x401d
-#define SO_PASSSEC		0x401e
-
-#define SO_MARK			0x401f
-
-/* O_NONBLOCK clashes with the bits used for socket types.  Therefore we
- * have to define SOCK_NONBLOCK to a different value here.
- */
-#define SOCK_NONBLOCK   0x40000000
-
-#endif /* _ASM_SOCKET_H */
diff --git a/include/asm-parisc/sockios.h b/include/asm-parisc/sockios.h
deleted file mode 100644
index dabfbc7483f6..000000000000
--- a/include/asm-parisc/sockios.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ARCH_PARISC_SOCKIOS__
-#define __ARCH_PARISC_SOCKIOS__
-
-/* Socket-level I/O control calls. */
-#define FIOSETOWN 	0x8901
-#define SIOCSPGRP	0x8902
-#define FIOGETOWN	0x8903
-#define SIOCGPGRP	0x8904
-#define SIOCATMARK	0x8905
-#define SIOCGSTAMP	0x8906		/* Get stamp (timeval) */
-#define SIOCGSTAMPNS	0x8907		/* Get stamp (timespec) */
-
-#endif
diff --git a/include/asm-parisc/spinlock.h b/include/asm-parisc/spinlock.h
deleted file mode 100644
index f3d2090a18dc..000000000000
--- a/include/asm-parisc/spinlock.h
+++ /dev/null
@@ -1,194 +0,0 @@
-#ifndef __ASM_SPINLOCK_H
-#define __ASM_SPINLOCK_H
-
-#include <asm/system.h>
-#include <asm/processor.h>
-#include <asm/spinlock_types.h>
-
-static inline int __raw_spin_is_locked(raw_spinlock_t *x)
-{
-	volatile unsigned int *a = __ldcw_align(x);
-	return *a == 0;
-}
-
-#define __raw_spin_lock(lock) __raw_spin_lock_flags(lock, 0)
-#define __raw_spin_unlock_wait(x) \
-		do { cpu_relax(); } while (__raw_spin_is_locked(x))
-
-static inline void __raw_spin_lock_flags(raw_spinlock_t *x,
-					 unsigned long flags)
-{
-	volatile unsigned int *a;
-
-	mb();
-	a = __ldcw_align(x);
-	while (__ldcw(a) == 0)
-		while (*a == 0)
-			if (flags & PSW_SM_I) {
-				local_irq_enable();
-				cpu_relax();
-				local_irq_disable();
-			} else
-				cpu_relax();
-	mb();
-}
-
-static inline void __raw_spin_unlock(raw_spinlock_t *x)
-{
-	volatile unsigned int *a;
-	mb();
-	a = __ldcw_align(x);
-	*a = 1;
-	mb();
-}
-
-static inline int __raw_spin_trylock(raw_spinlock_t *x)
-{
-	volatile unsigned int *a;
-	int ret;
-
-	mb();
-	a = __ldcw_align(x);
-        ret = __ldcw(a) != 0;
-	mb();
-
-	return ret;
-}
-
-/*
- * Read-write spinlocks, allowing multiple readers but only one writer.
- * Linux rwlocks are unfair to writers; they can be starved for an indefinite
- * time by readers.  With care, they can also be taken in interrupt context.
- *
- * In the PA-RISC implementation, we have a spinlock and a counter.
- * Readers use the lock to serialise their access to the counter (which
- * records how many readers currently hold the lock).
- * Writers hold the spinlock, preventing any readers or other writers from
- * grabbing the rwlock.
- */
-
-/* Note that we have to ensure interrupts are disabled in case we're
- * interrupted by some other code that wants to grab the same read lock */
-static  __inline__ void __raw_read_lock(raw_rwlock_t *rw)
-{
-	unsigned long flags;
-	local_irq_save(flags);
-	__raw_spin_lock_flags(&rw->lock, flags);
-	rw->counter++;
-	__raw_spin_unlock(&rw->lock);
-	local_irq_restore(flags);
-}
-
-/* Note that we have to ensure interrupts are disabled in case we're
- * interrupted by some other code that wants to grab the same read lock */
-static  __inline__ void __raw_read_unlock(raw_rwlock_t *rw)
-{
-	unsigned long flags;
-	local_irq_save(flags);
-	__raw_spin_lock_flags(&rw->lock, flags);
-	rw->counter--;
-	__raw_spin_unlock(&rw->lock);
-	local_irq_restore(flags);
-}
-
-/* Note that we have to ensure interrupts are disabled in case we're
- * interrupted by some other code that wants to grab the same read lock */
-static __inline__ int __raw_read_trylock(raw_rwlock_t *rw)
-{
-	unsigned long flags;
- retry:
-	local_irq_save(flags);
-	if (__raw_spin_trylock(&rw->lock)) {
-		rw->counter++;
-		__raw_spin_unlock(&rw->lock);
-		local_irq_restore(flags);
-		return 1;
-	}
-
-	local_irq_restore(flags);
-	/* If write-locked, we fail to acquire the lock */
-	if (rw->counter < 0)
-		return 0;
-
-	/* Wait until we have a realistic chance at the lock */
-	while (__raw_spin_is_locked(&rw->lock) && rw->counter >= 0)
-		cpu_relax();
-
-	goto retry;
-}
-
-/* Note that we have to ensure interrupts are disabled in case we're
- * interrupted by some other code that wants to read_trylock() this lock */
-static __inline__ void __raw_write_lock(raw_rwlock_t *rw)
-{
-	unsigned long flags;
-retry:
-	local_irq_save(flags);
-	__raw_spin_lock_flags(&rw->lock, flags);
-
-	if (rw->counter != 0) {
-		__raw_spin_unlock(&rw->lock);
-		local_irq_restore(flags);
-
-		while (rw->counter != 0)
-			cpu_relax();
-
-		goto retry;
-	}
-
-	rw->counter = -1; /* mark as write-locked */
-	mb();
-	local_irq_restore(flags);
-}
-
-static __inline__ void __raw_write_unlock(raw_rwlock_t *rw)
-{
-	rw->counter = 0;
-	__raw_spin_unlock(&rw->lock);
-}
-
-/* Note that we have to ensure interrupts are disabled in case we're
- * interrupted by some other code that wants to read_trylock() this lock */
-static __inline__ int __raw_write_trylock(raw_rwlock_t *rw)
-{
-	unsigned long flags;
-	int result = 0;
-
-	local_irq_save(flags);
-	if (__raw_spin_trylock(&rw->lock)) {
-		if (rw->counter == 0) {
-			rw->counter = -1;
-			result = 1;
-		} else {
-			/* Read-locked.  Oh well. */
-			__raw_spin_unlock(&rw->lock);
-		}
-	}
-	local_irq_restore(flags);
-
-	return result;
-}
-
-/*
- * read_can_lock - would read_trylock() succeed?
- * @lock: the rwlock in question.
- */
-static __inline__ int __raw_read_can_lock(raw_rwlock_t *rw)
-{
-	return rw->counter >= 0;
-}
-
-/*
- * write_can_lock - would write_trylock() succeed?
- * @lock: the rwlock in question.
- */
-static __inline__ int __raw_write_can_lock(raw_rwlock_t *rw)
-{
-	return !rw->counter;
-}
-
-#define _raw_spin_relax(lock)	cpu_relax()
-#define _raw_read_relax(lock)	cpu_relax()
-#define _raw_write_relax(lock)	cpu_relax()
-
-#endif /* __ASM_SPINLOCK_H */
diff --git a/include/asm-parisc/spinlock_types.h b/include/asm-parisc/spinlock_types.h
deleted file mode 100644
index 3f72f47cf4b2..000000000000
--- a/include/asm-parisc/spinlock_types.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef __ASM_SPINLOCK_TYPES_H
-#define __ASM_SPINLOCK_TYPES_H
-
-typedef struct {
-#ifdef CONFIG_PA20
-	volatile unsigned int slock;
-# define __RAW_SPIN_LOCK_UNLOCKED { 1 }
-#else
-	volatile unsigned int lock[4];
-# define __RAW_SPIN_LOCK_UNLOCKED	{ { 1, 1, 1, 1 } }
-#endif
-} raw_spinlock_t;
-
-typedef struct {
-	raw_spinlock_t lock;
-	volatile int counter;
-} raw_rwlock_t;
-
-#define __RAW_RW_LOCK_UNLOCKED		{ __RAW_SPIN_LOCK_UNLOCKED, 0 }
-
-#endif
diff --git a/include/asm-parisc/stat.h b/include/asm-parisc/stat.h
deleted file mode 100644
index 9d5fbbc5c31f..000000000000
--- a/include/asm-parisc/stat.h
+++ /dev/null
@@ -1,100 +0,0 @@
-#ifndef _PARISC_STAT_H
-#define _PARISC_STAT_H
-
-#include <linux/types.h>
-
-struct stat {
-	unsigned int	st_dev;		/* dev_t is 32 bits on parisc */
-	ino_t		st_ino;		/* 32 bits */
-	mode_t		st_mode;	/* 16 bits */
-	nlink_t		st_nlink;	/* 16 bits */
-	unsigned short	st_reserved1;	/* old st_uid */
-	unsigned short	st_reserved2;	/* old st_gid */
-	unsigned int	st_rdev;
-	off_t		st_size;
-	time_t		st_atime;
-	unsigned int	st_atime_nsec;
-	time_t		st_mtime;
-	unsigned int	st_mtime_nsec;
-	time_t		st_ctime;
-	unsigned int	st_ctime_nsec;
-	int		st_blksize;
-	int		st_blocks;
-	unsigned int	__unused1;	/* ACL stuff */
-	unsigned int	__unused2;	/* network */
-	ino_t		__unused3;	/* network */
-	unsigned int	__unused4;	/* cnodes */
-	unsigned short	__unused5;	/* netsite */
-	short		st_fstype;
-	unsigned int	st_realdev;
-	unsigned short	st_basemode;
-	unsigned short	st_spareshort;
-	uid_t		st_uid;
-	gid_t		st_gid;
-	unsigned int	st_spare4[3];
-};
-
-#define STAT_HAVE_NSEC
-
-typedef __kernel_off64_t	off64_t;
-
-struct hpux_stat64 {
-	unsigned int	st_dev;		/* dev_t is 32 bits on parisc */
-	ino_t           st_ino;         /* 32 bits */
-	mode_t		st_mode;	/* 16 bits */
-	nlink_t		st_nlink;	/* 16 bits */
-	unsigned short	st_reserved1;	/* old st_uid */
-	unsigned short	st_reserved2;	/* old st_gid */
-	unsigned int	st_rdev;
-	off64_t		st_size;
-	time_t		st_atime;
-	unsigned int	st_spare1;
-	time_t		st_mtime;
-	unsigned int	st_spare2;
-	time_t		st_ctime;
-	unsigned int	st_spare3;
-	int		st_blksize;
-	__u64		st_blocks;
-	unsigned int	__unused1;	/* ACL stuff */
-	unsigned int	__unused2;	/* network */
-	ino_t           __unused3;      /* network */
-	unsigned int	__unused4;	/* cnodes */
-	unsigned short	__unused5;	/* netsite */
-	short		st_fstype;
-	unsigned int	st_realdev;
-	unsigned short	st_basemode;
-	unsigned short	st_spareshort;
-	uid_t		st_uid;
-	gid_t		st_gid;
-	unsigned int	st_spare4[3];
-};
-
-/* This is the struct that 32-bit userspace applications are expecting.
- * How 64-bit apps are going to be compiled, I have no idea.  But at least
- * this way, we don't have a wrapper in the kernel.
- */
-struct stat64 {
-	unsigned long long	st_dev;
-	unsigned int		__pad1;
-
-	unsigned int		__st_ino;	/* Not actually filled in */
-	unsigned int		st_mode;
-	unsigned int		st_nlink;
-	unsigned int		st_uid;
-	unsigned int		st_gid;
-	unsigned long long	st_rdev;
-	unsigned int		__pad2;
-	signed long long	st_size;
-	signed int		st_blksize;
-
-	signed long long	st_blocks;
-	signed int		st_atime;
-	unsigned int		st_atime_nsec;
-	signed int		st_mtime;
-	unsigned int		st_mtime_nsec;
-	signed int		st_ctime;
-	unsigned int		st_ctime_nsec;
-	unsigned long long	st_ino;
-};
-
-#endif
diff --git a/include/asm-parisc/statfs.h b/include/asm-parisc/statfs.h
deleted file mode 100644
index 324bea905dc6..000000000000
--- a/include/asm-parisc/statfs.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _PARISC_STATFS_H
-#define _PARISC_STATFS_H
-
-#define __statfs_word long
-#include <asm-generic/statfs.h>
-
-#endif
diff --git a/include/asm-parisc/string.h b/include/asm-parisc/string.h
deleted file mode 100644
index eda01be65e35..000000000000
--- a/include/asm-parisc/string.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef _PA_STRING_H_
-#define _PA_STRING_H_
-
-#define __HAVE_ARCH_MEMSET
-extern void * memset(void *, int, size_t);
-
-#define __HAVE_ARCH_MEMCPY
-void * memcpy(void * dest,const void *src,size_t count);
-
-#endif
diff --git a/include/asm-parisc/superio.h b/include/asm-parisc/superio.h
deleted file mode 100644
index 6598acb4d46d..000000000000
--- a/include/asm-parisc/superio.h
+++ /dev/null
@@ -1,85 +0,0 @@
-#ifndef _PARISC_SUPERIO_H
-#define _PARISC_SUPERIO_H
-
-#define IC_PIC1    0x20		/* PCI I/O address of master 8259 */
-#define IC_PIC2    0xA0		/* PCI I/O address of slave */
-
-/* Config Space Offsets to configuration and base address registers */
-#define SIO_CR     0x5A		/* Configuration Register */
-#define SIO_ACPIBAR 0x88	/* ACPI BAR */
-#define SIO_FDCBAR 0x90		/* Floppy Disk Controller BAR */
-#define SIO_SP1BAR 0x94		/* Serial 1 BAR */
-#define SIO_SP2BAR 0x98		/* Serial 2 BAR */
-#define SIO_PPBAR  0x9C		/* Parallel BAR */
-
-#define TRIGGER_1  0x67		/* Edge/level trigger register 1 */
-#define TRIGGER_2  0x68		/* Edge/level trigger register 2 */
-
-/* Interrupt Routing Control registers */
-#define CFG_IR_SER    0x69	/* Serial 1 [0:3] and Serial 2 [4:7] */
-#define CFG_IR_PFD    0x6a	/* Parallel [0:3] and Floppy [4:7] */
-#define CFG_IR_IDE    0x6b	/* IDE1     [0:3] and IDE2 [4:7] */
-#define CFG_IR_INTAB  0x6c	/* PCI INTA [0:3] and INT B [4:7] */
-#define CFG_IR_INTCD  0x6d	/* PCI INTC [0:3] and INT D [4:7] */
-#define CFG_IR_PS2    0x6e	/* PS/2 KBINT [0:3] and Mouse [4:7] */
-#define CFG_IR_FXBUS  0x6f	/* FXIRQ[0] [0:3] and FXIRQ[1] [4:7] */
-#define CFG_IR_USB    0x70	/* FXIRQ[2] [0:3] and USB [4:7] */
-#define CFG_IR_ACPI   0x71	/* ACPI SCI [0:3] and reserved [4:7] */
-
-#define CFG_IR_LOW     CFG_IR_SER	/* Lowest interrupt routing reg */
-#define CFG_IR_HIGH    CFG_IR_ACPI	/* Highest interrupt routing reg */
-
-/* 8259 operational control words */
-#define OCW2_EOI   0x20		/* Non-specific EOI */
-#define OCW2_SEOI  0x60		/* Specific EOI */
-#define OCW3_IIR   0x0A		/* Read request register */
-#define OCW3_ISR   0x0B		/* Read service register */
-#define OCW3_POLL  0x0C		/* Poll the PIC for an interrupt vector */
-
-/* Interrupt lines. Only PIC1 is used */
-#define USB_IRQ    1		/* USB */
-#define SP1_IRQ    3		/* Serial port 1 */
-#define SP2_IRQ    4		/* Serial port 2 */
-#define PAR_IRQ    5		/* Parallel port */
-#define FDC_IRQ    6		/* Floppy controller */
-#define IDE_IRQ    7		/* IDE (pri+sec) */
-
-/* ACPI registers */
-#define USB_REG_CR	0x1f	/* USB Regulator Control Register */
-
-#define SUPERIO_NIRQS   8
-
-struct superio_device {
-	u32 fdc_base;
-	u32 sp1_base;
-	u32 sp2_base;
-	u32 pp_base;
-	u32 acpi_base;
-	int suckyio_irq_enabled;
-	struct pci_dev *lio_pdev;       /* pci device for legacy IO (fn 1) */
-	struct pci_dev *usb_pdev;       /* pci device for USB (fn 2) */
-};
-
-/*
- * Does NS make a 87415 based plug in PCI card? If so, because of this
- * macro we currently don't support it being plugged into a machine
- * that contains a SuperIO chip AND has CONFIG_SUPERIO enabled.
- *
- * This could be fixed by checking to see if function 1 exists, and
- * if it is SuperIO Legacy IO; but really now, is this combination
- * going to EVER happen?
- */
-
-#define SUPERIO_IDE_FN 0 /* Function number of IDE controller */
-#define SUPERIO_LIO_FN 1 /* Function number of Legacy IO controller */
-#define SUPERIO_USB_FN 2 /* Function number of USB controller */
-
-#define is_superio_device(x) \
-	(((x)->vendor == PCI_VENDOR_ID_NS) && \
-	(  ((x)->device == PCI_DEVICE_ID_NS_87415) \
-	|| ((x)->device == PCI_DEVICE_ID_NS_87560_LIO) \
-	|| ((x)->device == PCI_DEVICE_ID_NS_87560_USB) ) )
-
-extern int superio_fixup_irq(struct pci_dev *pcidev); /* called by iosapic */
-
-#endif /* _PARISC_SUPERIO_H */
diff --git a/include/asm-parisc/system.h b/include/asm-parisc/system.h
deleted file mode 100644
index ee80c920b464..000000000000
--- a/include/asm-parisc/system.h
+++ /dev/null
@@ -1,182 +0,0 @@
-#ifndef __PARISC_SYSTEM_H
-#define __PARISC_SYSTEM_H
-
-#include <asm/psw.h>
-
-/* The program status word as bitfields.  */
-struct pa_psw {
-	unsigned int y:1;
-	unsigned int z:1;
-	unsigned int rv:2;
-	unsigned int w:1;
-	unsigned int e:1;
-	unsigned int s:1;
-	unsigned int t:1;
-
-	unsigned int h:1;
-	unsigned int l:1;
-	unsigned int n:1;
-	unsigned int x:1;
-	unsigned int b:1;
-	unsigned int c:1;
-	unsigned int v:1;
-	unsigned int m:1;
-
-	unsigned int cb:8;
-
-	unsigned int o:1;
-	unsigned int g:1;
-	unsigned int f:1;
-	unsigned int r:1;
-	unsigned int q:1;
-	unsigned int p:1;
-	unsigned int d:1;
-	unsigned int i:1;
-};
-
-#ifdef CONFIG_64BIT
-#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW + 4))
-#else
-#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW))
-#endif
-
-struct task_struct;
-
-extern struct task_struct *_switch_to(struct task_struct *, struct task_struct *);
-
-#define switch_to(prev, next, last) do {			\
-	(last) = _switch_to(prev, next);			\
-} while(0)
-
-/* interrupt control */
-#define local_save_flags(x)	__asm__ __volatile__("ssm 0, %0" : "=r" (x) : : "memory")
-#define local_irq_disable()	__asm__ __volatile__("rsm %0,%%r0\n" : : "i" (PSW_I) : "memory" )
-#define local_irq_enable()	__asm__ __volatile__("ssm %0,%%r0\n" : : "i" (PSW_I) : "memory" )
-
-#define local_irq_save(x) \
-	__asm__ __volatile__("rsm %1,%0" : "=r" (x) :"i" (PSW_I) : "memory" )
-#define local_irq_restore(x) \
-	__asm__ __volatile__("mtsm %0" : : "r" (x) : "memory" )
-
-#define irqs_disabled()			\
-({					\
-	unsigned long flags;		\
-	local_save_flags(flags);	\
-	(flags & PSW_I) == 0;		\
-})
-
-#define mfctl(reg)	({		\
-	unsigned long cr;		\
-	__asm__ __volatile__(		\
-		"mfctl " #reg ",%0" :	\
-		 "=r" (cr)		\
-	);				\
-	cr;				\
-})
-
-#define mtctl(gr, cr) \
-	__asm__ __volatile__("mtctl %0,%1" \
-		: /* no outputs */ \
-		: "r" (gr), "i" (cr) : "memory")
-
-/* these are here to de-mystefy the calling code, and to provide hooks */
-/* which I needed for debugging EIEM problems -PB */
-#define get_eiem() mfctl(15)
-static inline void set_eiem(unsigned long val)
-{
-	mtctl(val, 15);
-}
-
-#define mfsp(reg)	({		\
-	unsigned long cr;		\
-	__asm__ __volatile__(		\
-		"mfsp " #reg ",%0" :	\
-		 "=r" (cr)		\
-	);				\
-	cr;				\
-})
-
-#define mtsp(gr, cr) \
-	__asm__ __volatile__("mtsp %0,%1" \
-		: /* no outputs */ \
-		: "r" (gr), "i" (cr) : "memory")
-
-
-/*
-** This is simply the barrier() macro from linux/kernel.h but when serial.c
-** uses tqueue.h uses smp_mb() defined using barrier(), linux/kernel.h
-** hasn't yet been included yet so it fails, thus repeating the macro here.
-**
-** PA-RISC architecture allows for weakly ordered memory accesses although
-** none of the processors use it. There is a strong ordered bit that is
-** set in the O-bit of the page directory entry. Operating systems that
-** can not tolerate out of order accesses should set this bit when mapping
-** pages. The O-bit of the PSW should also be set to 1 (I don't believe any
-** of the processor implemented the PSW O-bit). The PCX-W ERS states that
-** the TLB O-bit is not implemented so the page directory does not need to
-** have the O-bit set when mapping pages (section 3.1). This section also
-** states that the PSW Y, Z, G, and O bits are not implemented.
-** So it looks like nothing needs to be done for parisc-linux (yet).
-** (thanks to chada for the above comment -ggg)
-**
-** The __asm__ op below simple prevents gcc/ld from reordering
-** instructions across the mb() "call".
-*/
-#define mb()		__asm__ __volatile__("":::"memory")	/* barrier() */
-#define rmb()		mb()
-#define wmb()		mb()
-#define smp_mb()	mb()
-#define smp_rmb()	mb()
-#define smp_wmb()	mb()
-#define smp_read_barrier_depends()	do { } while(0)
-#define read_barrier_depends()		do { } while(0)
-
-#define set_mb(var, value)		do { var = value; mb(); } while (0)
-
-#ifndef CONFIG_PA20
-/* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
-   and GCC only guarantees 8-byte alignment for stack locals, we can't
-   be assured of 16-byte alignment for atomic lock data even if we
-   specify "__attribute ((aligned(16)))" in the type declaration.  So,
-   we use a struct containing an array of four ints for the atomic lock
-   type and dynamically select the 16-byte aligned int from the array
-   for the semaphore.  */
-
-#define __PA_LDCW_ALIGNMENT	16
-#define __ldcw_align(a) ({					\
-	unsigned long __ret = (unsigned long) &(a)->lock[0];	\
-	__ret = (__ret + __PA_LDCW_ALIGNMENT - 1)		\
-		& ~(__PA_LDCW_ALIGNMENT - 1);			\
-	(volatile unsigned int *) __ret;			\
-})
-#define __LDCW	"ldcw"
-
-#else /*CONFIG_PA20*/
-/* From: "Jim Hull" <jim.hull of hp.com>
-   I've attached a summary of the change, but basically, for PA 2.0, as
-   long as the ",CO" (coherent operation) completer is specified, then the
-   16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
-   they only require "natural" alignment (4-byte for ldcw, 8-byte for
-   ldcd). */
-
-#define __PA_LDCW_ALIGNMENT	4
-#define __ldcw_align(a) ((volatile unsigned int *)a)
-#define __LDCW	"ldcw,co"
-
-#endif /*!CONFIG_PA20*/
-
-/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.  */
-#define __ldcw(a) ({						\
-	unsigned __ret;						\
-	__asm__ __volatile__(__LDCW " 0(%1),%0"			\
-		: "=r" (__ret) : "r" (a));			\
-	__ret;							\
-})
-
-#ifdef CONFIG_SMP
-# define __lock_aligned __attribute__((__section__(".data.lock_aligned")))
-#endif
-
-#define arch_align_stack(x) (x)
-
-#endif
diff --git a/include/asm-parisc/termbits.h b/include/asm-parisc/termbits.h
deleted file mode 100644
index d8bbc73b16b7..000000000000
--- a/include/asm-parisc/termbits.h
+++ /dev/null
@@ -1,200 +0,0 @@
-#ifndef __ARCH_PARISC_TERMBITS_H__
-#define __ARCH_PARISC_TERMBITS_H__
-
-#include <linux/posix_types.h>
-
-typedef unsigned char	cc_t;
-typedef unsigned int	speed_t;
-typedef unsigned int	tcflag_t;
-
-#define NCCS 19
-struct termios {
-	tcflag_t c_iflag;		/* input mode flags */
-	tcflag_t c_oflag;		/* output mode flags */
-	tcflag_t c_cflag;		/* control mode flags */
-	tcflag_t c_lflag;		/* local mode flags */
-	cc_t c_line;			/* line discipline */
-	cc_t c_cc[NCCS];		/* control characters */
-};
-
-struct termios2 {
-	tcflag_t c_iflag;		/* input mode flags */
-	tcflag_t c_oflag;		/* output mode flags */
-	tcflag_t c_cflag;		/* control mode flags */
-	tcflag_t c_lflag;		/* local mode flags */
-	cc_t c_line;			/* line discipline */
-	cc_t c_cc[NCCS];		/* control characters */
-	speed_t c_ispeed;		/* input speed */
-	speed_t c_ospeed;		/* output speed */
-};
-
-struct ktermios {
-	tcflag_t c_iflag;		/* input mode flags */
-	tcflag_t c_oflag;		/* output mode flags */
-	tcflag_t c_cflag;		/* control mode flags */
-	tcflag_t c_lflag;		/* local mode flags */
-	cc_t c_line;			/* line discipline */
-	cc_t c_cc[NCCS];		/* control characters */
-	speed_t c_ispeed;		/* input speed */
-	speed_t c_ospeed;		/* output speed */
-};
-
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-
-
-/* c_iflag bits */
-#define IGNBRK	0000001
-#define BRKINT	0000002
-#define IGNPAR	0000004
-#define PARMRK	0000010
-#define INPCK	0000020
-#define ISTRIP	0000040
-#define INLCR	0000100
-#define IGNCR	0000200
-#define ICRNL	0000400
-#define IUCLC	0001000
-#define IXON	0002000
-#define IXANY	0004000
-#define IXOFF	0010000
-#define IMAXBEL	0040000
-#define IUTF8	0100000
-
-/* c_oflag bits */
-#define OPOST	0000001
-#define OLCUC	0000002
-#define ONLCR	0000004
-#define OCRNL	0000010
-#define ONOCR	0000020
-#define ONLRET	0000040
-#define OFILL	0000100
-#define OFDEL	0000200
-#define NLDLY	0000400
-#define   NL0	0000000
-#define   NL1	0000400
-#define CRDLY	0003000
-#define   CR0	0000000
-#define   CR1	0001000
-#define   CR2	0002000
-#define   CR3	0003000
-#define TABDLY	0014000
-#define   TAB0	0000000
-#define   TAB1	0004000
-#define   TAB2	0010000
-#define   TAB3	0014000
-#define   XTABS	0014000
-#define BSDLY	0020000
-#define   BS0	0000000
-#define   BS1	0020000
-#define VTDLY	0040000
-#define   VT0	0000000
-#define   VT1	0040000
-#define FFDLY	0100000
-#define   FF0	0000000
-#define   FF1	0100000
-
-/* c_cflag bit meaning */
-#define CBAUD   0010017
-#define  B0     0000000         /* hang up */
-#define  B50    0000001
-#define  B75    0000002
-#define  B110   0000003
-#define  B134   0000004
-#define  B150   0000005
-#define  B200   0000006
-#define  B300   0000007
-#define  B600   0000010
-#define  B1200  0000011
-#define  B1800  0000012
-#define  B2400  0000013
-#define  B4800  0000014
-#define  B9600  0000015
-#define  B19200 0000016
-#define  B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE   0000060
-#define   CS5   0000000
-#define   CS6   0000020
-#define   CS7   0000040
-#define   CS8   0000060
-#define CSTOPB  0000100
-#define CREAD   0000200
-#define PARENB  0000400
-#define PARODD  0001000
-#define HUPCL   0002000
-#define CLOCAL  0004000
-#define CBAUDEX 0010000
-#define    BOTHER 0010000
-#define    B57600 0010001
-#define   B115200 0010002
-#define   B230400 0010003
-#define   B460800 0010004
-#define   B500000 0010005
-#define   B576000 0010006
-#define   B921600 0010007
-#define  B1000000 0010010
-#define  B1152000 0010011
-#define  B1500000 0010012
-#define  B2000000 0010013
-#define  B2500000 0010014
-#define  B3000000 0010015
-#define  B3500000 0010016
-#define  B4000000 0010017
-#define CIBAUD    002003600000		/* input baud rate */
-#define CMSPAR    010000000000          /* mark or space (stick) parity */
-#define CRTSCTS   020000000000          /* flow control */
-
-#define IBSHIFT	16		/* Shift from CBAUD to CIBAUD */
-
-
-/* c_lflag bits */
-#define ISIG    0000001
-#define ICANON  0000002
-#define XCASE   0000004
-#define ECHO    0000010
-#define ECHOE   0000020
-#define ECHOK   0000040
-#define ECHONL  0000100
-#define NOFLSH  0000200
-#define TOSTOP  0000400
-#define ECHOCTL 0001000
-#define ECHOPRT 0002000
-#define ECHOKE  0004000
-#define FLUSHO  0010000
-#define PENDIN  0040000
-#define IEXTEN  0100000
-
-/* tcflow() and TCXONC use these */
-#define	TCOOFF		0
-#define	TCOON		1
-#define	TCIOFF		2
-#define	TCION		3
-
-/* tcflush() and TCFLSH use these */
-#define	TCIFLUSH	0
-#define	TCOFLUSH	1
-#define	TCIOFLUSH	2
-
-/* tcsetattr uses these */
-#define	TCSANOW		0
-#define	TCSADRAIN	1
-#define	TCSAFLUSH	2
-
-#endif
diff --git a/include/asm-parisc/termios.h b/include/asm-parisc/termios.h
deleted file mode 100644
index a2a57a4548af..000000000000
--- a/include/asm-parisc/termios.h
+++ /dev/null
@@ -1,90 +0,0 @@
-#ifndef _PARISC_TERMIOS_H
-#define _PARISC_TERMIOS_H
-
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-
-struct winsize {
-	unsigned short ws_row;
-	unsigned short ws_col;
-	unsigned short ws_xpixel;
-	unsigned short ws_ypixel;
-};
-
-#define NCC 8
-struct termio {
-	unsigned short c_iflag;		/* input mode flags */
-	unsigned short c_oflag;		/* output mode flags */
-	unsigned short c_cflag;		/* control mode flags */
-	unsigned short c_lflag;		/* local mode flags */
-	unsigned char c_line;		/* line discipline */
-	unsigned char c_cc[NCC];	/* control characters */
-};
-
-/* modem lines */
-#define TIOCM_LE	0x001
-#define TIOCM_DTR	0x002
-#define TIOCM_RTS	0x004
-#define TIOCM_ST	0x008
-#define TIOCM_SR	0x010
-#define TIOCM_CTS	0x020
-#define TIOCM_CAR	0x040
-#define TIOCM_RNG	0x080
-#define TIOCM_DSR	0x100
-#define TIOCM_CD	TIOCM_CAR
-#define TIOCM_RI	TIOCM_RNG
-#define TIOCM_OUT1	0x2000
-#define TIOCM_OUT2	0x4000
-#define TIOCM_LOOP	0x8000
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-
-#ifdef __KERNEL__
-
-/*	intr=^C		quit=^\		erase=del	kill=^U
-	eof=^D		vtime=\0	vmin=\1		sxtc=\0
-	start=^Q	stop=^S		susp=^Z		eol=\0
-	reprint=^R	discard=^U	werase=^W	lnext=^V
-	eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
-	unsigned short __tmp; \
-	get_user(__tmp,&(termio)->x); \
-	*(unsigned short *) &(termios)->x = __tmp; \
-}
-
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
-	SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
-	SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
-	SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
-	SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
-	copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
-	put_user((termios)->c_iflag, &(termio)->c_iflag); \
-	put_user((termios)->c_oflag, &(termio)->c_oflag); \
-	put_user((termios)->c_cflag, &(termio)->c_cflag); \
-	put_user((termios)->c_lflag, &(termio)->c_lflag); \
-	put_user((termios)->c_line,  &(termio)->c_line); \
-	copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
-#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
-
-#endif	/* __KERNEL__ */
-
-#endif	/* _PARISC_TERMIOS_H */
diff --git a/include/asm-parisc/thread_info.h b/include/asm-parisc/thread_info.h
deleted file mode 100644
index 9f812741c355..000000000000
--- a/include/asm-parisc/thread_info.h
+++ /dev/null
@@ -1,74 +0,0 @@
-#ifndef _ASM_PARISC_THREAD_INFO_H
-#define _ASM_PARISC_THREAD_INFO_H
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-#include <asm/processor.h>
-
-struct thread_info {
-	struct task_struct *task;	/* main task structure */
-	struct exec_domain *exec_domain;/* execution domain */
-	unsigned long flags;		/* thread_info flags (see TIF_*) */
-	mm_segment_t addr_limit;	/* user-level address space limit */
-	__u32 cpu;			/* current CPU */
-	int preempt_count;		/* 0=premptable, <0=BUG; will also serve as bh-counter */
-	struct restart_block restart_block;
-};
-
-#define INIT_THREAD_INFO(tsk)			\
-{						\
-	.task		= &tsk,			\
-	.exec_domain	= &default_exec_domain,	\
-	.flags		= 0,			\
-	.cpu		= 0,			\
-	.addr_limit	= KERNEL_DS,		\
-	.preempt_count	= 1,			\
-  	.restart_block	= {			\
-		.fn = do_no_restart_syscall	\
-	}					\
-}
-
-#define init_thread_info        (init_thread_union.thread_info)
-#define init_stack              (init_thread_union.stack)
-
-/* thread information allocation */
-
-#define THREAD_SIZE_ORDER            2
-/* Be sure to hunt all references to this down when you change the size of
- * the kernel stack */
-#define THREAD_SIZE             (PAGE_SIZE << THREAD_SIZE_ORDER)
-#define THREAD_SHIFT            (PAGE_SHIFT + THREAD_SIZE_ORDER)
-
-/* how to get the thread information struct from C */
-#define current_thread_info()	((struct thread_info *)mfctl(30))
-
-#endif /* !__ASSEMBLY */
-
-#define PREEMPT_ACTIVE_BIT	28
-#define PREEMPT_ACTIVE		(1 << PREEMPT_ACTIVE_BIT)
-
-/*
- * thread information flags
- */
-#define TIF_SYSCALL_TRACE	0	/* syscall trace active */
-#define TIF_SIGPENDING		1	/* signal pending */
-#define TIF_NEED_RESCHED	2	/* rescheduling necessary */
-#define TIF_POLLING_NRFLAG	3	/* true if poll_idle() is polling TIF_NEED_RESCHED */
-#define TIF_32BIT               4       /* 32 bit binary */
-#define TIF_MEMDIE		5
-#define TIF_RESTORE_SIGMASK	6	/* restore saved signal mask */
-
-#define _TIF_SYSCALL_TRACE	(1 << TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING		(1 << TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED	(1 << TIF_NEED_RESCHED)
-#define _TIF_POLLING_NRFLAG	(1 << TIF_POLLING_NRFLAG)
-#define _TIF_32BIT		(1 << TIF_32BIT)
-#define _TIF_RESTORE_SIGMASK	(1 << TIF_RESTORE_SIGMASK)
-
-#define _TIF_USER_WORK_MASK     (_TIF_SIGPENDING | \
-                                 _TIF_NEED_RESCHED | _TIF_RESTORE_SIGMASK)
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_PARISC_THREAD_INFO_H */
diff --git a/include/asm-parisc/timex.h b/include/asm-parisc/timex.h
deleted file mode 100644
index 3b68d77273d9..000000000000
--- a/include/asm-parisc/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * linux/include/asm-parisc/timex.h
- *
- * PARISC architecture timex specifications
- */
-#ifndef _ASMPARISC_TIMEX_H
-#define _ASMPARISC_TIMEX_H
-
-#include <asm/system.h>
-
-#define CLOCK_TICK_RATE	1193180 /* Underlying HZ */
-
-typedef unsigned long cycles_t;
-
-static inline cycles_t get_cycles (void)
-{
-	return mfctl(16);
-}
-
-#endif
diff --git a/include/asm-parisc/tlb.h b/include/asm-parisc/tlb.h
deleted file mode 100644
index 383b1db310ee..000000000000
--- a/include/asm-parisc/tlb.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef _PARISC_TLB_H
-#define _PARISC_TLB_H
-
-#define tlb_flush(tlb)			\
-do {	if ((tlb)->fullmm)		\
-		flush_tlb_mm((tlb)->mm);\
-} while (0)
-
-#define tlb_start_vma(tlb, vma) \
-do {	if (!(tlb)->fullmm)	\
-		flush_cache_range(vma, vma->vm_start, vma->vm_end); \
-} while (0)
-
-#define tlb_end_vma(tlb, vma)	\
-do {	if (!(tlb)->fullmm)	\
-		flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
-} while (0)
-
-#define __tlb_remove_tlb_entry(tlb, pte, address) \
-	do { } while (0)
-
-#include <asm-generic/tlb.h>
-
-#define __pmd_free_tlb(tlb, pmd)	pmd_free((tlb)->mm, pmd)
-#define __pte_free_tlb(tlb, pte)	pte_free((tlb)->mm, pte)
-
-#endif
diff --git a/include/asm-parisc/tlbflush.h b/include/asm-parisc/tlbflush.h
deleted file mode 100644
index b72ec66db699..000000000000
--- a/include/asm-parisc/tlbflush.h
+++ /dev/null
@@ -1,80 +0,0 @@
-#ifndef _PARISC_TLBFLUSH_H
-#define _PARISC_TLBFLUSH_H
-
-/* TLB flushing routines.... */
-
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <asm/mmu_context.h>
-
-
-/* This is for the serialisation of PxTLB broadcasts.  At least on the
- * N class systems, only one PxTLB inter processor broadcast can be
- * active at any one time on the Merced bus.  This tlb purge
- * synchronisation is fairly lightweight and harmless so we activate
- * it on all SMP systems not just the N class.  We also need to have
- * preemption disabled on uniprocessor machines, and spin_lock does that
- * nicely.
- */
-extern spinlock_t pa_tlb_lock;
-
-#define purge_tlb_start(x) spin_lock(&pa_tlb_lock)
-#define purge_tlb_end(x) spin_unlock(&pa_tlb_lock)
-
-extern void flush_tlb_all(void);
-extern void flush_tlb_all_local(void *);
-
-/*
- * flush_tlb_mm()
- *
- * XXX This code is NOT valid for HP-UX compatibility processes,
- * (although it will probably work 99% of the time). HP-UX
- * processes are free to play with the space id's and save them
- * over long periods of time, etc. so we have to preserve the
- * space and just flush the entire tlb. We need to check the
- * personality in order to do that, but the personality is not
- * currently being set correctly.
- *
- * Of course, Linux processes could do the same thing, but
- * we don't support that (and the compilers, dynamic linker,
- * etc. do not do that).
- */
-
-static inline void flush_tlb_mm(struct mm_struct *mm)
-{
-	BUG_ON(mm == &init_mm); /* Should never happen */
-
-#ifdef CONFIG_SMP
-	flush_tlb_all();
-#else
-	if (mm) {
-		if (mm->context != 0)
-			free_sid(mm->context);
-		mm->context = alloc_sid();
-		if (mm == current->active_mm)
-			load_context(mm->context);
-	}
-#endif
-}
-
-static inline void flush_tlb_page(struct vm_area_struct *vma,
-	unsigned long addr)
-{
-	/* For one page, it's not worth testing the split_tlb variable */
-
-	mb();
-	mtsp(vma->vm_mm->context,1);
-	purge_tlb_start();
-	pdtlb(addr);
-	pitlb(addr);
-	purge_tlb_end();
-}
-
-void __flush_tlb_range(unsigned long sid,
-	unsigned long start, unsigned long end);
-
-#define flush_tlb_range(vma,start,end) __flush_tlb_range((vma)->vm_mm->context,start,end)
-
-#define flush_tlb_kernel_range(start, end) __flush_tlb_range(0,start,end)
-
-#endif
diff --git a/include/asm-parisc/topology.h b/include/asm-parisc/topology.h
deleted file mode 100644
index d8133eb0b1e7..000000000000
--- a/include/asm-parisc/topology.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_PARISC_TOPOLOGY_H
-#define _ASM_PARISC_TOPOLOGY_H
-
-#include <asm-generic/topology.h>
-
-#endif /* _ASM_PARISC_TOPOLOGY_H */
diff --git a/include/asm-parisc/traps.h b/include/asm-parisc/traps.h
deleted file mode 100644
index 1945f995f2df..000000000000
--- a/include/asm-parisc/traps.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __ASM_TRAPS_H
-#define __ASM_TRAPS_H
-
-#ifdef __KERNEL__
-struct pt_regs;
-
-/* traps.c */
-void parisc_terminate(char *msg, struct pt_regs *regs,
-		int code, unsigned long offset);
-
-/* mm/fault.c */
-void do_page_fault(struct pt_regs *regs, unsigned long code,
-		unsigned long address);
-#endif
-
-#endif
diff --git a/include/asm-parisc/types.h b/include/asm-parisc/types.h
deleted file mode 100644
index 7f5a39bfb4ce..000000000000
--- a/include/asm-parisc/types.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef _PARISC_TYPES_H
-#define _PARISC_TYPES_H
-
-#include <asm-generic/int-ll64.h>
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned short umode_t;
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-#ifdef CONFIG_64BIT
-#define BITS_PER_LONG 64
-#define SHIFT_PER_LONG 6
-#else
-#define BITS_PER_LONG 32
-#define SHIFT_PER_LONG 5
-#endif
-
-#ifndef __ASSEMBLY__
-
-/* Dma addresses are 32-bits wide.  */
-
-typedef u32 dma_addr_t;
-typedef u64 dma64_addr_t;
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-
-#endif
diff --git a/include/asm-parisc/uaccess.h b/include/asm-parisc/uaccess.h
deleted file mode 100644
index 4878b9501f24..000000000000
--- a/include/asm-parisc/uaccess.h
+++ /dev/null
@@ -1,244 +0,0 @@
-#ifndef __PARISC_UACCESS_H
-#define __PARISC_UACCESS_H
-
-/*
- * User space memory access functions
- */
-#include <asm/page.h>
-#include <asm/system.h>
-#include <asm/cache.h>
-#include <asm-generic/uaccess.h>
-
-#define VERIFY_READ 0
-#define VERIFY_WRITE 1
-
-#define KERNEL_DS	((mm_segment_t){0})
-#define USER_DS 	((mm_segment_t){1})
-
-#define segment_eq(a,b)	((a).seg == (b).seg)
-
-#define get_ds()	(KERNEL_DS)
-#define get_fs()	(current_thread_info()->addr_limit)
-#define set_fs(x)	(current_thread_info()->addr_limit = (x))
-
-/*
- * Note that since kernel addresses are in a separate address space on
- * parisc, we don't need to do anything for access_ok().
- * We just let the page fault handler do the right thing. This also means
- * that put_user is the same as __put_user, etc.
- */
-
-extern int __get_kernel_bad(void);
-extern int __get_user_bad(void);
-extern int __put_kernel_bad(void);
-extern int __put_user_bad(void);
-
-static inline long access_ok(int type, const void __user * addr,
-		unsigned long size)
-{
-	return 1;
-}
-
-#define put_user __put_user
-#define get_user __get_user
-
-#if !defined(CONFIG_64BIT)
-#define LDD_KERNEL(ptr)		__get_kernel_bad();
-#define LDD_USER(ptr)		__get_user_bad();
-#define STD_KERNEL(x, ptr)	__put_kernel_asm64(x,ptr)
-#define STD_USER(x, ptr)	__put_user_asm64(x,ptr)
-#define ASM_WORD_INSN		".word\t"
-#else
-#define LDD_KERNEL(ptr)		__get_kernel_asm("ldd",ptr)
-#define LDD_USER(ptr)		__get_user_asm("ldd",ptr)
-#define STD_KERNEL(x, ptr)	__put_kernel_asm("std",x,ptr)
-#define STD_USER(x, ptr)	__put_user_asm("std",x,ptr)
-#define ASM_WORD_INSN		".dword\t"
-#endif
-
-/*
- * The exception table contains two values: the first is an address
- * for an instruction that is allowed to fault, and the second is
- * the address to the fixup routine. 
- */
-
-struct exception_table_entry {
-	unsigned long insn;  /* address of insn that is allowed to fault.   */
-	long fixup;          /* fixup routine */
-};
-
-#define ASM_EXCEPTIONTABLE_ENTRY( fault_addr, except_addr )\
-	".section __ex_table,\"aw\"\n"			   \
-	ASM_WORD_INSN #fault_addr ", " #except_addr "\n\t" \
-	".previous\n"
-
-/*
- * The page fault handler stores, in a per-cpu area, the following information
- * if a fixup routine is available.
- */
-struct exception_data {
-	unsigned long fault_ip;
-	unsigned long fault_space;
-	unsigned long fault_addr;
-};
-
-#define __get_user(x,ptr)                               \
-({                                                      \
-	register long __gu_err __asm__ ("r8") = 0;      \
-	register long __gu_val __asm__ ("r9") = 0;      \
-							\
-	if (segment_eq(get_fs(),KERNEL_DS)) {           \
-	    switch (sizeof(*(ptr))) {                   \
-	    case 1: __get_kernel_asm("ldb",ptr); break; \
-	    case 2: __get_kernel_asm("ldh",ptr); break; \
-	    case 4: __get_kernel_asm("ldw",ptr); break; \
-	    case 8: LDD_KERNEL(ptr); break;		\
-	    default: __get_kernel_bad(); break;         \
-	    }                                           \
-	}                                               \
-	else {                                          \
-	    switch (sizeof(*(ptr))) {                   \
-	    case 1: __get_user_asm("ldb",ptr); break;   \
-	    case 2: __get_user_asm("ldh",ptr); break;   \
-	    case 4: __get_user_asm("ldw",ptr); break;   \
-	    case 8: LDD_USER(ptr);  break;		\
-	    default: __get_user_bad(); break;           \
-	    }                                           \
-	}                                               \
-							\
-	(x) = (__typeof__(*(ptr))) __gu_val;            \
-	__gu_err;                                       \
-})
-
-#define __get_kernel_asm(ldx,ptr)                       \
-	__asm__("\n1:\t" ldx "\t0(%2),%0\n\t"		\
-		ASM_EXCEPTIONTABLE_ENTRY(1b, fixup_get_user_skip_1)\
-		: "=r"(__gu_val), "=r"(__gu_err)        \
-		: "r"(ptr), "1"(__gu_err)		\
-		: "r1");
-
-#define __get_user_asm(ldx,ptr)                         \
-	__asm__("\n1:\t" ldx "\t0(%%sr3,%2),%0\n\t"	\
-		ASM_EXCEPTIONTABLE_ENTRY(1b,fixup_get_user_skip_1)\
-		: "=r"(__gu_val), "=r"(__gu_err)        \
-		: "r"(ptr), "1"(__gu_err)		\
-		: "r1");
-
-#define __put_user(x,ptr)                                       \
-({								\
-	register long __pu_err __asm__ ("r8") = 0;      	\
-        __typeof__(*(ptr)) __x = (__typeof__(*(ptr)))(x);	\
-								\
-	if (segment_eq(get_fs(),KERNEL_DS)) {                   \
-	    switch (sizeof(*(ptr))) {                           \
-	    case 1: __put_kernel_asm("stb",__x,ptr); break;     \
-	    case 2: __put_kernel_asm("sth",__x,ptr); break;     \
-	    case 4: __put_kernel_asm("stw",__x,ptr); break;     \
-	    case 8: STD_KERNEL(__x,ptr); break;			\
-	    default: __put_kernel_bad(); break;			\
-	    }                                                   \
-	}                                                       \
-	else {                                                  \
-	    switch (sizeof(*(ptr))) {                           \
-	    case 1: __put_user_asm("stb",__x,ptr); break;       \
-	    case 2: __put_user_asm("sth",__x,ptr); break;       \
-	    case 4: __put_user_asm("stw",__x,ptr); break;       \
-	    case 8: STD_USER(__x,ptr); break;			\
-	    default: __put_user_bad(); break;			\
-	    }                                                   \
-	}                                                       \
-								\
-	__pu_err;						\
-})
-
-/*
- * The "__put_user/kernel_asm()" macros tell gcc they read from memory
- * instead of writing. This is because they do not write to any memory
- * gcc knows about, so there are no aliasing issues. These macros must
- * also be aware that "fixup_put_user_skip_[12]" are executed in the
- * context of the fault, and any registers used there must be listed
- * as clobbers. In this case only "r1" is used by the current routines.
- * r8/r9 are already listed as err/val.
- */
-
-#define __put_kernel_asm(stx,x,ptr)                         \
-	__asm__ __volatile__ (                              \
-		"\n1:\t" stx "\t%2,0(%1)\n\t"		    \
-		ASM_EXCEPTIONTABLE_ENTRY(1b,fixup_put_user_skip_1)\
-		: "=r"(__pu_err)                            \
-		: "r"(ptr), "r"(x), "0"(__pu_err)	    \
-	    	: "r1")
-
-#define __put_user_asm(stx,x,ptr)                           \
-	__asm__ __volatile__ (                              \
-		"\n1:\t" stx "\t%2,0(%%sr3,%1)\n\t"	    \
-		ASM_EXCEPTIONTABLE_ENTRY(1b,fixup_put_user_skip_1)\
-		: "=r"(__pu_err)                            \
-		: "r"(ptr), "r"(x), "0"(__pu_err)	    \
-		: "r1")
-
-
-#if !defined(CONFIG_64BIT)
-
-#define __put_kernel_asm64(__val,ptr) do {		    \
-	u64 __val64 = (u64)(__val);			    \
-	u32 hi = (__val64) >> 32;			    \
-	u32 lo = (__val64) & 0xffffffff;		    \
-	__asm__ __volatile__ (				    \
-		"\n1:\tstw %2,0(%1)"			    \
-		"\n2:\tstw %3,4(%1)\n\t"		    \
-		ASM_EXCEPTIONTABLE_ENTRY(1b,fixup_put_user_skip_2)\
-		ASM_EXCEPTIONTABLE_ENTRY(2b,fixup_put_user_skip_1)\
-		: "=r"(__pu_err)                            \
-		: "r"(ptr), "r"(hi), "r"(lo), "0"(__pu_err) \
-		: "r1");				    \
-} while (0)
-
-#define __put_user_asm64(__val,ptr) do {	    	    \
-	u64 __val64 = (u64)(__val);			    \
-	u32 hi = (__val64) >> 32;			    \
-	u32 lo = (__val64) & 0xffffffff;		    \
-	__asm__ __volatile__ (				    \
-		"\n1:\tstw %2,0(%%sr3,%1)"		    \
-		"\n2:\tstw %3,4(%%sr3,%1)\n\t"		    \
-		ASM_EXCEPTIONTABLE_ENTRY(1b,fixup_put_user_skip_2)\
-		ASM_EXCEPTIONTABLE_ENTRY(2b,fixup_put_user_skip_1)\
-		: "=r"(__pu_err)                            \
-		: "r"(ptr), "r"(hi), "r"(lo), "0"(__pu_err) \
-		: "r1");				    \
-} while (0)
-
-#endif /* !defined(CONFIG_64BIT) */
-
-
-/*
- * Complex access routines -- external declarations
- */
-
-extern unsigned long lcopy_to_user(void __user *, const void *, unsigned long);
-extern unsigned long lcopy_from_user(void *, const void __user *, unsigned long);
-extern unsigned long lcopy_in_user(void __user *, const void __user *, unsigned long);
-extern long lstrncpy_from_user(char *, const char __user *, long);
-extern unsigned lclear_user(void __user *,unsigned long);
-extern long lstrnlen_user(const char __user *,long);
-
-/*
- * Complex access routines -- macros
- */
-
-#define strncpy_from_user lstrncpy_from_user
-#define strnlen_user lstrnlen_user
-#define strlen_user(str) lstrnlen_user(str, 0x7fffffffL)
-#define clear_user lclear_user
-#define __clear_user lclear_user
-
-unsigned long copy_to_user(void __user *dst, const void *src, unsigned long len);
-#define __copy_to_user copy_to_user
-unsigned long copy_from_user(void *dst, const void __user *src, unsigned long len);
-#define __copy_from_user copy_from_user
-unsigned long copy_in_user(void __user *dst, const void __user *src, unsigned long len);
-#define __copy_in_user copy_in_user
-#define __copy_to_user_inatomic __copy_to_user
-#define __copy_from_user_inatomic __copy_from_user
-
-#endif /* __PARISC_UACCESS_H */
diff --git a/include/asm-parisc/ucontext.h b/include/asm-parisc/ucontext.h
deleted file mode 100644
index 6c8883e4b0bd..000000000000
--- a/include/asm-parisc/ucontext.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _ASM_PARISC_UCONTEXT_H
-#define _ASM_PARISC_UCONTEXT_H
-
-struct ucontext {
-	unsigned int	  uc_flags;
-	struct ucontext  *uc_link;
-	stack_t		  uc_stack;
-	struct sigcontext uc_mcontext;
-	sigset_t	  uc_sigmask;	/* mask last for extensibility */
-};
-
-#endif /* !_ASM_PARISC_UCONTEXT_H */
diff --git a/include/asm-parisc/unaligned.h b/include/asm-parisc/unaligned.h
deleted file mode 100644
index dfc5d3321a54..000000000000
--- a/include/asm-parisc/unaligned.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef _ASM_PARISC_UNALIGNED_H
-#define _ASM_PARISC_UNALIGNED_H
-
-#include <linux/unaligned/be_struct.h>
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/generic.h>
-#define get_unaligned	__get_unaligned_be
-#define put_unaligned	__put_unaligned_be
-
-#ifdef __KERNEL__
-struct pt_regs;
-void handle_unaligned(struct pt_regs *regs);
-int check_unaligned(struct pt_regs *regs);
-#endif
-
-#endif /* _ASM_PARISC_UNALIGNED_H */
diff --git a/include/asm-parisc/unistd.h b/include/asm-parisc/unistd.h
deleted file mode 100644
index a7d857f0e4f4..000000000000
--- a/include/asm-parisc/unistd.h
+++ /dev/null
@@ -1,991 +0,0 @@
-#ifndef _ASM_PARISC_UNISTD_H_
-#define _ASM_PARISC_UNISTD_H_
-
-/*
- * This file contains the system call numbers.
- */
-
-/*
- *   HP-UX system calls get their native numbers for binary compatibility.
- */
-
-#define __NR_HPUX_exit                    1
-#define __NR_HPUX_fork                    2
-#define __NR_HPUX_read                    3
-#define __NR_HPUX_write                   4
-#define __NR_HPUX_open                    5
-#define __NR_HPUX_close                   6
-#define __NR_HPUX_wait                    7
-#define __NR_HPUX_creat                   8
-#define __NR_HPUX_link                    9
-#define __NR_HPUX_unlink                 10
-#define __NR_HPUX_execv                  11
-#define __NR_HPUX_chdir                  12
-#define __NR_HPUX_time                   13
-#define __NR_HPUX_mknod                  14
-#define __NR_HPUX_chmod                  15
-#define __NR_HPUX_chown                  16
-#define __NR_HPUX_break                  17
-#define __NR_HPUX_lchmod                 18
-#define __NR_HPUX_lseek                  19
-#define __NR_HPUX_getpid                 20
-#define __NR_HPUX_mount                  21
-#define __NR_HPUX_umount                 22
-#define __NR_HPUX_setuid                 23
-#define __NR_HPUX_getuid                 24
-#define __NR_HPUX_stime                  25
-#define __NR_HPUX_ptrace                 26
-#define __NR_HPUX_alarm                  27
-#define __NR_HPUX_oldfstat               28
-#define __NR_HPUX_pause                  29
-#define __NR_HPUX_utime                  30
-#define __NR_HPUX_stty                   31
-#define __NR_HPUX_gtty                   32
-#define __NR_HPUX_access                 33
-#define __NR_HPUX_nice                   34
-#define __NR_HPUX_ftime                  35
-#define __NR_HPUX_sync                   36
-#define __NR_HPUX_kill                   37
-#define __NR_HPUX_stat                   38
-#define __NR_HPUX_setpgrp3               39
-#define __NR_HPUX_lstat                  40
-#define __NR_HPUX_dup                    41
-#define __NR_HPUX_pipe                   42
-#define __NR_HPUX_times                  43
-#define __NR_HPUX_profil                 44
-#define __NR_HPUX_ki_call                45
-#define __NR_HPUX_setgid                 46
-#define __NR_HPUX_getgid                 47
-#define __NR_HPUX_sigsys                 48
-#define __NR_HPUX_reserved1              49
-#define __NR_HPUX_reserved2              50
-#define __NR_HPUX_acct                   51
-#define __NR_HPUX_set_userthreadid       52
-#define __NR_HPUX_oldlock                53
-#define __NR_HPUX_ioctl                  54
-#define __NR_HPUX_reboot                 55
-#define __NR_HPUX_symlink                56
-#define __NR_HPUX_utssys                 57
-#define __NR_HPUX_readlink               58
-#define __NR_HPUX_execve                 59
-#define __NR_HPUX_umask                  60
-#define __NR_HPUX_chroot                 61
-#define __NR_HPUX_fcntl                  62
-#define __NR_HPUX_ulimit                 63
-#define __NR_HPUX_getpagesize            64
-#define __NR_HPUX_mremap                 65
-#define __NR_HPUX_vfork                  66
-#define __NR_HPUX_vread                  67
-#define __NR_HPUX_vwrite                 68
-#define __NR_HPUX_sbrk                   69
-#define __NR_HPUX_sstk                   70
-#define __NR_HPUX_mmap                   71
-#define __NR_HPUX_vadvise                72
-#define __NR_HPUX_munmap                 73
-#define __NR_HPUX_mprotect               74
-#define __NR_HPUX_madvise                75
-#define __NR_HPUX_vhangup                76
-#define __NR_HPUX_swapoff                77
-#define __NR_HPUX_mincore                78
-#define __NR_HPUX_getgroups              79
-#define __NR_HPUX_setgroups              80
-#define __NR_HPUX_getpgrp2               81
-#define __NR_HPUX_setpgrp2               82
-#define __NR_HPUX_setitimer              83
-#define __NR_HPUX_wait3                  84
-#define __NR_HPUX_swapon                 85
-#define __NR_HPUX_getitimer              86
-#define __NR_HPUX_gethostname42          87
-#define __NR_HPUX_sethostname42          88
-#define __NR_HPUX_getdtablesize          89
-#define __NR_HPUX_dup2                   90
-#define __NR_HPUX_getdopt                91
-#define __NR_HPUX_fstat                  92
-#define __NR_HPUX_select                 93
-#define __NR_HPUX_setdopt                94
-#define __NR_HPUX_fsync                  95
-#define __NR_HPUX_setpriority            96
-#define __NR_HPUX_socket_old             97
-#define __NR_HPUX_connect_old            98
-#define __NR_HPUX_accept_old             99
-#define __NR_HPUX_getpriority           100
-#define __NR_HPUX_send_old              101
-#define __NR_HPUX_recv_old              102
-#define __NR_HPUX_socketaddr_old        103
-#define __NR_HPUX_bind_old              104
-#define __NR_HPUX_setsockopt_old        105
-#define __NR_HPUX_listen_old            106
-#define __NR_HPUX_vtimes_old            107
-#define __NR_HPUX_sigvector             108
-#define __NR_HPUX_sigblock              109
-#define __NR_HPUX_siggetmask            110
-#define __NR_HPUX_sigpause              111
-#define __NR_HPUX_sigstack              112
-#define __NR_HPUX_recvmsg_old           113
-#define __NR_HPUX_sendmsg_old           114
-#define __NR_HPUX_vtrace_old            115
-#define __NR_HPUX_gettimeofday          116
-#define __NR_HPUX_getrusage             117
-#define __NR_HPUX_getsockopt_old        118
-#define __NR_HPUX_resuba_old            119
-#define __NR_HPUX_readv                 120
-#define __NR_HPUX_writev                121
-#define __NR_HPUX_settimeofday          122
-#define __NR_HPUX_fchown                123
-#define __NR_HPUX_fchmod                124
-#define __NR_HPUX_recvfrom_old          125
-#define __NR_HPUX_setresuid             126
-#define __NR_HPUX_setresgid             127
-#define __NR_HPUX_rename                128
-#define __NR_HPUX_truncate              129
-#define __NR_HPUX_ftruncate             130
-#define __NR_HPUX_flock_old             131
-#define __NR_HPUX_sysconf               132
-#define __NR_HPUX_sendto_old            133
-#define __NR_HPUX_shutdown_old          134
-#define __NR_HPUX_socketpair_old        135
-#define __NR_HPUX_mkdir                 136
-#define __NR_HPUX_rmdir                 137
-#define __NR_HPUX_utimes_old            138
-#define __NR_HPUX_sigcleanup_old        139
-#define __NR_HPUX_setcore               140
-#define __NR_HPUX_getpeername_old       141
-#define __NR_HPUX_gethostid             142
-#define __NR_HPUX_sethostid             143
-#define __NR_HPUX_getrlimit             144
-#define __NR_HPUX_setrlimit             145
-#define __NR_HPUX_killpg_old            146
-#define __NR_HPUX_cachectl              147
-#define __NR_HPUX_quotactl              148
-#define __NR_HPUX_get_sysinfo           149
-#define __NR_HPUX_getsockname_old       150
-#define __NR_HPUX_privgrp               151
-#define __NR_HPUX_rtprio                152
-#define __NR_HPUX_plock                 153
-#define __NR_HPUX_reserved3             154
-#define __NR_HPUX_lockf                 155
-#define __NR_HPUX_semget                156
-#define __NR_HPUX_osemctl               157
-#define __NR_HPUX_semop                 158
-#define __NR_HPUX_msgget                159
-#define __NR_HPUX_omsgctl               160
-#define __NR_HPUX_msgsnd                161
-#define __NR_HPUX_msgrecv               162
-#define __NR_HPUX_shmget                163
-#define __NR_HPUX_oshmctl               164
-#define __NR_HPUX_shmat                 165
-#define __NR_HPUX_shmdt                 166
-#define __NR_HPUX_m68020_advise         167
-/* [168,189] are for Discless/DUX */
-#define __NR_HPUX_csp                   168
-#define __NR_HPUX_cluster               169
-#define __NR_HPUX_mkrnod                170
-#define __NR_HPUX_test                  171
-#define __NR_HPUX_unsp_open             172
-#define __NR_HPUX_reserved4             173
-#define __NR_HPUX_getcontext_old        174
-#define __NR_HPUX_osetcontext           175
-#define __NR_HPUX_bigio                 176
-#define __NR_HPUX_pipenode              177
-#define __NR_HPUX_lsync                 178
-#define __NR_HPUX_getmachineid          179
-#define __NR_HPUX_cnodeid               180
-#define __NR_HPUX_cnodes                181
-#define __NR_HPUX_swapclients           182
-#define __NR_HPUX_rmt_process           183
-#define __NR_HPUX_dskless_stats         184
-#define __NR_HPUX_sigprocmask           185
-#define __NR_HPUX_sigpending            186
-#define __NR_HPUX_sigsuspend            187
-#define __NR_HPUX_sigaction             188
-#define __NR_HPUX_reserved5             189
-#define __NR_HPUX_nfssvc                190
-#define __NR_HPUX_getfh                 191
-#define __NR_HPUX_getdomainname         192
-#define __NR_HPUX_setdomainname         193
-#define __NR_HPUX_async_daemon          194
-#define __NR_HPUX_getdirentries         195
-#define __NR_HPUX_statfs                196
-#define __NR_HPUX_fstatfs               197
-#define __NR_HPUX_vfsmount              198
-#define __NR_HPUX_reserved6             199
-#define __NR_HPUX_waitpid               200
-/* 201 - 223 missing */
-#define __NR_HPUX_sigsetreturn          224
-#define __NR_HPUX_sigsetstatemask       225
-/* 226 missing */
-#define __NR_HPUX_cs                    227
-#define __NR_HPUX_cds                   228
-#define __NR_HPUX_set_no_trunc          229
-#define __NR_HPUX_pathconf              230
-#define __NR_HPUX_fpathconf             231
-/* 232, 233 missing */
-#define __NR_HPUX_nfs_fcntl             234
-#define __NR_HPUX_ogetacl               235
-#define __NR_HPUX_ofgetacl              236
-#define __NR_HPUX_osetacl               237
-#define __NR_HPUX_ofsetacl              238
-#define __NR_HPUX_pstat                 239
-#define __NR_HPUX_getaudid              240
-#define __NR_HPUX_setaudid              241
-#define __NR_HPUX_getaudproc            242
-#define __NR_HPUX_setaudproc            243
-#define __NR_HPUX_getevent              244
-#define __NR_HPUX_setevent              245
-#define __NR_HPUX_audwrite              246
-#define __NR_HPUX_audswitch             247
-#define __NR_HPUX_audctl                248
-#define __NR_HPUX_ogetaccess            249
-#define __NR_HPUX_fsctl                 250
-/* 251 - 258 missing */
-#define __NR_HPUX_swapfs                259
-#define __NR_HPUX_fss                   260
-/* 261 - 266 missing */
-#define __NR_HPUX_tsync                 267
-#define __NR_HPUX_getnumfds             268
-#define __NR_HPUX_poll                  269
-#define __NR_HPUX_getmsg                270
-#define __NR_HPUX_putmsg                271
-#define __NR_HPUX_fchdir                272
-#define __NR_HPUX_getmount_cnt          273
-#define __NR_HPUX_getmount_entry        274
-#define __NR_HPUX_accept                275
-#define __NR_HPUX_bind                  276
-#define __NR_HPUX_connect               277
-#define __NR_HPUX_getpeername           278
-#define __NR_HPUX_getsockname           279
-#define __NR_HPUX_getsockopt            280
-#define __NR_HPUX_listen                281
-#define __NR_HPUX_recv                  282
-#define __NR_HPUX_recvfrom              283
-#define __NR_HPUX_recvmsg               284
-#define __NR_HPUX_send                  285
-#define __NR_HPUX_sendmsg               286
-#define __NR_HPUX_sendto                287
-#define __NR_HPUX_setsockopt            288
-#define __NR_HPUX_shutdown              289
-#define __NR_HPUX_socket                290
-#define __NR_HPUX_socketpair            291
-#define __NR_HPUX_proc_open             292
-#define __NR_HPUX_proc_close            293
-#define __NR_HPUX_proc_send             294
-#define __NR_HPUX_proc_recv             295
-#define __NR_HPUX_proc_sendrecv         296
-#define __NR_HPUX_proc_syscall          297
-/* 298 - 311 missing */
-#define __NR_HPUX_semctl                312
-#define __NR_HPUX_msgctl                313
-#define __NR_HPUX_shmctl                314
-#define __NR_HPUX_mpctl                 315
-#define __NR_HPUX_exportfs              316
-#define __NR_HPUX_getpmsg               317
-#define __NR_HPUX_putpmsg               318
-/* 319 missing */
-#define __NR_HPUX_msync                 320
-#define __NR_HPUX_msleep                321
-#define __NR_HPUX_mwakeup               322
-#define __NR_HPUX_msem_init             323
-#define __NR_HPUX_msem_remove           324
-#define __NR_HPUX_adjtime               325
-#define __NR_HPUX_kload                 326
-#define __NR_HPUX_fattach               327
-#define __NR_HPUX_fdetach               328
-#define __NR_HPUX_serialize             329
-#define __NR_HPUX_statvfs               330
-#define __NR_HPUX_fstatvfs              331
-#define __NR_HPUX_lchown                332
-#define __NR_HPUX_getsid                333
-#define __NR_HPUX_sysfs                 334
-/* 335, 336 missing */
-#define __NR_HPUX_sched_setparam        337
-#define __NR_HPUX_sched_getparam        338
-#define __NR_HPUX_sched_setscheduler    339
-#define __NR_HPUX_sched_getscheduler    340
-#define __NR_HPUX_sched_yield           341
-#define __NR_HPUX_sched_get_priority_max 342
-#define __NR_HPUX_sched_get_priority_min 343
-#define __NR_HPUX_sched_rr_get_interval 344
-#define __NR_HPUX_clock_settime         345
-#define __NR_HPUX_clock_gettime         346
-#define __NR_HPUX_clock_getres          347
-#define __NR_HPUX_timer_create          348
-#define __NR_HPUX_timer_delete          349
-#define __NR_HPUX_timer_settime         350
-#define __NR_HPUX_timer_gettime         351
-#define __NR_HPUX_timer_getoverrun      352
-#define __NR_HPUX_nanosleep             353
-#define __NR_HPUX_toolbox               354
-/* 355 missing */
-#define __NR_HPUX_getdents              356
-#define __NR_HPUX_getcontext            357
-#define __NR_HPUX_sysinfo               358
-#define __NR_HPUX_fcntl64               359
-#define __NR_HPUX_ftruncate64           360
-#define __NR_HPUX_fstat64               361
-#define __NR_HPUX_getdirentries64       362
-#define __NR_HPUX_getrlimit64           363
-#define __NR_HPUX_lockf64               364
-#define __NR_HPUX_lseek64               365
-#define __NR_HPUX_lstat64               366
-#define __NR_HPUX_mmap64                367
-#define __NR_HPUX_setrlimit64           368
-#define __NR_HPUX_stat64                369
-#define __NR_HPUX_truncate64            370
-#define __NR_HPUX_ulimit64              371
-#define __NR_HPUX_pread                 372
-#define __NR_HPUX_preadv                373
-#define __NR_HPUX_pwrite                374
-#define __NR_HPUX_pwritev               375
-#define __NR_HPUX_pread64               376
-#define __NR_HPUX_preadv64              377
-#define __NR_HPUX_pwrite64              378
-#define __NR_HPUX_pwritev64             379
-#define __NR_HPUX_setcontext            380
-#define __NR_HPUX_sigaltstack           381
-#define __NR_HPUX_waitid                382
-#define __NR_HPUX_setpgrp               383
-#define __NR_HPUX_recvmsg2              384
-#define __NR_HPUX_sendmsg2              385
-#define __NR_HPUX_socket2               386
-#define __NR_HPUX_socketpair2           387
-#define __NR_HPUX_setregid              388
-#define __NR_HPUX_lwp_create            389
-#define __NR_HPUX_lwp_terminate         390
-#define __NR_HPUX_lwp_wait              391
-#define __NR_HPUX_lwp_suspend           392
-#define __NR_HPUX_lwp_resume            393
-/* 394 missing */
-#define __NR_HPUX_lwp_abort_syscall     395
-#define __NR_HPUX_lwp_info              396
-#define __NR_HPUX_lwp_kill              397
-#define __NR_HPUX_ksleep                398
-#define __NR_HPUX_kwakeup               399
-/* 400 missing */
-#define __NR_HPUX_pstat_getlwp          401
-#define __NR_HPUX_lwp_exit              402
-#define __NR_HPUX_lwp_continue          403
-#define __NR_HPUX_getacl                404
-#define __NR_HPUX_fgetacl               405
-#define __NR_HPUX_setacl                406
-#define __NR_HPUX_fsetacl               407
-#define __NR_HPUX_getaccess             408
-#define __NR_HPUX_lwp_mutex_init        409
-#define __NR_HPUX_lwp_mutex_lock_sys    410
-#define __NR_HPUX_lwp_mutex_unlock      411
-#define __NR_HPUX_lwp_cond_init         412
-#define __NR_HPUX_lwp_cond_signal       413
-#define __NR_HPUX_lwp_cond_broadcast    414
-#define __NR_HPUX_lwp_cond_wait_sys     415
-#define __NR_HPUX_lwp_getscheduler      416
-#define __NR_HPUX_lwp_setscheduler      417
-#define __NR_HPUX_lwp_getstate          418
-#define __NR_HPUX_lwp_setstate          419
-#define __NR_HPUX_lwp_detach            420
-#define __NR_HPUX_mlock                 421
-#define __NR_HPUX_munlock               422
-#define __NR_HPUX_mlockall              423
-#define __NR_HPUX_munlockall            424
-#define __NR_HPUX_shm_open              425
-#define __NR_HPUX_shm_unlink            426
-#define __NR_HPUX_sigqueue              427
-#define __NR_HPUX_sigwaitinfo           428
-#define __NR_HPUX_sigtimedwait          429
-#define __NR_HPUX_sigwait               430
-#define __NR_HPUX_aio_read              431
-#define __NR_HPUX_aio_write             432
-#define __NR_HPUX_lio_listio            433
-#define __NR_HPUX_aio_error             434
-#define __NR_HPUX_aio_return            435
-#define __NR_HPUX_aio_cancel            436
-#define __NR_HPUX_aio_suspend           437
-#define __NR_HPUX_aio_fsync             438
-#define __NR_HPUX_mq_open               439
-#define __NR_HPUX_mq_close              440
-#define __NR_HPUX_mq_unlink             441
-#define __NR_HPUX_mq_send               442
-#define __NR_HPUX_mq_receive            443
-#define __NR_HPUX_mq_notify             444
-#define __NR_HPUX_mq_setattr            445
-#define __NR_HPUX_mq_getattr            446
-#define __NR_HPUX_ksem_open             447
-#define __NR_HPUX_ksem_unlink           448
-#define __NR_HPUX_ksem_close            449
-#define __NR_HPUX_ksem_post             450
-#define __NR_HPUX_ksem_wait             451
-#define __NR_HPUX_ksem_read             452
-#define __NR_HPUX_ksem_trywait          453
-#define __NR_HPUX_lwp_rwlock_init       454
-#define __NR_HPUX_lwp_rwlock_destroy    455
-#define __NR_HPUX_lwp_rwlock_rdlock_sys 456
-#define __NR_HPUX_lwp_rwlock_wrlock_sys 457
-#define __NR_HPUX_lwp_rwlock_tryrdlock  458
-#define __NR_HPUX_lwp_rwlock_trywrlock  459
-#define __NR_HPUX_lwp_rwlock_unlock     460
-#define __NR_HPUX_ttrace                461
-#define __NR_HPUX_ttrace_wait           462
-#define __NR_HPUX_lf_wire_mem           463
-#define __NR_HPUX_lf_unwire_mem         464
-#define __NR_HPUX_lf_send_pin_map       465
-#define __NR_HPUX_lf_free_buf           466
-#define __NR_HPUX_lf_wait_nq            467
-#define __NR_HPUX_lf_wakeup_conn_q      468
-#define __NR_HPUX_lf_unused             469
-#define __NR_HPUX_lwp_sema_init         470
-#define __NR_HPUX_lwp_sema_post         471
-#define __NR_HPUX_lwp_sema_wait         472
-#define __NR_HPUX_lwp_sema_trywait      473
-#define __NR_HPUX_lwp_sema_destroy      474
-#define __NR_HPUX_statvfs64             475
-#define __NR_HPUX_fstatvfs64            476
-#define __NR_HPUX_msh_register          477
-#define __NR_HPUX_ptrace64              478
-#define __NR_HPUX_sendfile              479
-#define __NR_HPUX_sendpath              480
-#define __NR_HPUX_sendfile64            481
-#define __NR_HPUX_sendpath64            482
-#define __NR_HPUX_modload               483
-#define __NR_HPUX_moduload              484
-#define __NR_HPUX_modpath               485
-#define __NR_HPUX_getksym               486
-#define __NR_HPUX_modadm                487
-#define __NR_HPUX_modstat               488
-#define __NR_HPUX_lwp_detached_exit     489
-#define __NR_HPUX_crashconf             490
-#define __NR_HPUX_siginhibit            491
-#define __NR_HPUX_sigenable             492
-#define __NR_HPUX_spuctl                493
-#define __NR_HPUX_zerokernelsum         494
-#define __NR_HPUX_nfs_kstat             495
-#define __NR_HPUX_aio_read64            496
-#define __NR_HPUX_aio_write64           497
-#define __NR_HPUX_aio_error64           498
-#define __NR_HPUX_aio_return64          499
-#define __NR_HPUX_aio_cancel64          500
-#define __NR_HPUX_aio_suspend64         501
-#define __NR_HPUX_aio_fsync64           502
-#define __NR_HPUX_lio_listio64          503
-#define __NR_HPUX_recv2                 504
-#define __NR_HPUX_recvfrom2             505
-#define __NR_HPUX_send2                 506
-#define __NR_HPUX_sendto2               507
-#define __NR_HPUX_acl                   508
-#define __NR_HPUX___cnx_p2p_ctl         509
-#define __NR_HPUX___cnx_gsched_ctl      510
-#define __NR_HPUX___cnx_pmon_ctl        511
-
-#define __NR_HPUX_syscalls		512
-
-/*
- * Linux system call numbers.
- *
- * Cary Coutant says that we should just use another syscall gateway
- * page to avoid clashing with the HPUX space, and I think he's right:
- * it will would keep a branch out of our syscall entry path, at the
- * very least.  If we decide to change it later, we can ``just'' tweak
- * the LINUX_GATEWAY_ADDR define at the bottom and make __NR_Linux be
- * 1024 or something.  Oh, and recompile libc. =)
- *
- * 64-bit HPUX binaries get the syscall gateway address passed in a register
- * from the kernel at startup, which seems a sane strategy.
- */
-
-#define __NR_Linux                0
-#define __NR_restart_syscall      (__NR_Linux + 0)
-#define __NR_exit                 (__NR_Linux + 1)
-#define __NR_fork                 (__NR_Linux + 2)
-#define __NR_read                 (__NR_Linux + 3)
-#define __NR_write                (__NR_Linux + 4)
-#define __NR_open                 (__NR_Linux + 5)
-#define __NR_close                (__NR_Linux + 6)
-#define __NR_waitpid              (__NR_Linux + 7)
-#define __NR_creat                (__NR_Linux + 8)
-#define __NR_link                 (__NR_Linux + 9)
-#define __NR_unlink              (__NR_Linux + 10)
-#define __NR_execve              (__NR_Linux + 11)
-#define __NR_chdir               (__NR_Linux + 12)
-#define __NR_time                (__NR_Linux + 13)
-#define __NR_mknod               (__NR_Linux + 14)
-#define __NR_chmod               (__NR_Linux + 15)
-#define __NR_lchown              (__NR_Linux + 16)
-#define __NR_socket              (__NR_Linux + 17)
-#define __NR_stat                (__NR_Linux + 18)
-#define __NR_lseek               (__NR_Linux + 19)
-#define __NR_getpid              (__NR_Linux + 20)
-#define __NR_mount               (__NR_Linux + 21)
-#define __NR_bind                (__NR_Linux + 22)
-#define __NR_setuid              (__NR_Linux + 23)
-#define __NR_getuid              (__NR_Linux + 24)
-#define __NR_stime               (__NR_Linux + 25)
-#define __NR_ptrace              (__NR_Linux + 26)
-#define __NR_alarm               (__NR_Linux + 27)
-#define __NR_fstat               (__NR_Linux + 28)
-#define __NR_pause               (__NR_Linux + 29)
-#define __NR_utime               (__NR_Linux + 30)
-#define __NR_connect             (__NR_Linux + 31)
-#define __NR_listen              (__NR_Linux + 32)
-#define __NR_access              (__NR_Linux + 33)
-#define __NR_nice                (__NR_Linux + 34)
-#define __NR_accept              (__NR_Linux + 35)
-#define __NR_sync                (__NR_Linux + 36)
-#define __NR_kill                (__NR_Linux + 37)
-#define __NR_rename              (__NR_Linux + 38)
-#define __NR_mkdir               (__NR_Linux + 39)
-#define __NR_rmdir               (__NR_Linux + 40)
-#define __NR_dup                 (__NR_Linux + 41)
-#define __NR_pipe                (__NR_Linux + 42)
-#define __NR_times               (__NR_Linux + 43)
-#define __NR_getsockname         (__NR_Linux + 44)
-#define __NR_brk                 (__NR_Linux + 45)
-#define __NR_setgid              (__NR_Linux + 46)
-#define __NR_getgid              (__NR_Linux + 47)
-#define __NR_signal              (__NR_Linux + 48)
-#define __NR_geteuid             (__NR_Linux + 49)
-#define __NR_getegid             (__NR_Linux + 50)
-#define __NR_acct                (__NR_Linux + 51)
-#define __NR_umount2             (__NR_Linux + 52)
-#define __NR_getpeername         (__NR_Linux + 53)
-#define __NR_ioctl               (__NR_Linux + 54)
-#define __NR_fcntl               (__NR_Linux + 55)
-#define __NR_socketpair          (__NR_Linux + 56)
-#define __NR_setpgid             (__NR_Linux + 57)
-#define __NR_send                (__NR_Linux + 58)
-#define __NR_uname               (__NR_Linux + 59)
-#define __NR_umask               (__NR_Linux + 60)
-#define __NR_chroot              (__NR_Linux + 61)
-#define __NR_ustat               (__NR_Linux + 62)
-#define __NR_dup2                (__NR_Linux + 63)
-#define __NR_getppid             (__NR_Linux + 64)
-#define __NR_getpgrp             (__NR_Linux + 65)
-#define __NR_setsid              (__NR_Linux + 66)
-#define __NR_pivot_root          (__NR_Linux + 67)
-#define __NR_sgetmask            (__NR_Linux + 68)
-#define __NR_ssetmask            (__NR_Linux + 69)
-#define __NR_setreuid            (__NR_Linux + 70)
-#define __NR_setregid            (__NR_Linux + 71)
-#define __NR_mincore             (__NR_Linux + 72)
-#define __NR_sigpending          (__NR_Linux + 73)
-#define __NR_sethostname         (__NR_Linux + 74)
-#define __NR_setrlimit           (__NR_Linux + 75)
-#define __NR_getrlimit           (__NR_Linux + 76)
-#define __NR_getrusage           (__NR_Linux + 77)
-#define __NR_gettimeofday        (__NR_Linux + 78)
-#define __NR_settimeofday        (__NR_Linux + 79)
-#define __NR_getgroups           (__NR_Linux + 80)
-#define __NR_setgroups           (__NR_Linux + 81)
-#define __NR_sendto              (__NR_Linux + 82)
-#define __NR_symlink             (__NR_Linux + 83)
-#define __NR_lstat               (__NR_Linux + 84)
-#define __NR_readlink            (__NR_Linux + 85)
-#define __NR_uselib              (__NR_Linux + 86)
-#define __NR_swapon              (__NR_Linux + 87)
-#define __NR_reboot              (__NR_Linux + 88)
-#define __NR_mmap2             (__NR_Linux + 89)
-#define __NR_mmap                (__NR_Linux + 90)
-#define __NR_munmap              (__NR_Linux + 91)
-#define __NR_truncate            (__NR_Linux + 92)
-#define __NR_ftruncate           (__NR_Linux + 93)
-#define __NR_fchmod              (__NR_Linux + 94)
-#define __NR_fchown              (__NR_Linux + 95)
-#define __NR_getpriority         (__NR_Linux + 96)
-#define __NR_setpriority         (__NR_Linux + 97)
-#define __NR_recv                (__NR_Linux + 98)
-#define __NR_statfs              (__NR_Linux + 99)
-#define __NR_fstatfs            (__NR_Linux + 100)
-#define __NR_stat64           (__NR_Linux + 101)
-/* #define __NR_socketcall         (__NR_Linux + 102) */
-#define __NR_syslog             (__NR_Linux + 103)
-#define __NR_setitimer          (__NR_Linux + 104)
-#define __NR_getitimer          (__NR_Linux + 105)
-#define __NR_capget             (__NR_Linux + 106)
-#define __NR_capset             (__NR_Linux + 107)
-#define __NR_pread64            (__NR_Linux + 108)
-#define __NR_pwrite64           (__NR_Linux + 109)
-#define __NR_getcwd             (__NR_Linux + 110)
-#define __NR_vhangup            (__NR_Linux + 111)
-#define __NR_fstat64            (__NR_Linux + 112)
-#define __NR_vfork              (__NR_Linux + 113)
-#define __NR_wait4              (__NR_Linux + 114)
-#define __NR_swapoff            (__NR_Linux + 115)
-#define __NR_sysinfo            (__NR_Linux + 116)
-#define __NR_shutdown           (__NR_Linux + 117)
-#define __NR_fsync              (__NR_Linux + 118)
-#define __NR_madvise            (__NR_Linux + 119)
-#define __NR_clone              (__NR_Linux + 120)
-#define __NR_setdomainname      (__NR_Linux + 121)
-#define __NR_sendfile           (__NR_Linux + 122)
-#define __NR_recvfrom           (__NR_Linux + 123)
-#define __NR_adjtimex           (__NR_Linux + 124)
-#define __NR_mprotect           (__NR_Linux + 125)
-#define __NR_sigprocmask        (__NR_Linux + 126)
-#define __NR_create_module      (__NR_Linux + 127)
-#define __NR_init_module        (__NR_Linux + 128)
-#define __NR_delete_module      (__NR_Linux + 129)
-#define __NR_get_kernel_syms    (__NR_Linux + 130)
-#define __NR_quotactl           (__NR_Linux + 131)
-#define __NR_getpgid            (__NR_Linux + 132)
-#define __NR_fchdir             (__NR_Linux + 133)
-#define __NR_bdflush            (__NR_Linux + 134)
-#define __NR_sysfs              (__NR_Linux + 135)
-#define __NR_personality        (__NR_Linux + 136)
-#define __NR_afs_syscall        (__NR_Linux + 137) /* Syscall for Andrew File System */
-#define __NR_setfsuid           (__NR_Linux + 138)
-#define __NR_setfsgid           (__NR_Linux + 139)
-#define __NR__llseek            (__NR_Linux + 140)
-#define __NR_getdents           (__NR_Linux + 141)
-#define __NR__newselect         (__NR_Linux + 142)
-#define __NR_flock              (__NR_Linux + 143)
-#define __NR_msync              (__NR_Linux + 144)
-#define __NR_readv              (__NR_Linux + 145)
-#define __NR_writev             (__NR_Linux + 146)
-#define __NR_getsid             (__NR_Linux + 147)
-#define __NR_fdatasync          (__NR_Linux + 148)
-#define __NR__sysctl            (__NR_Linux + 149)
-#define __NR_mlock              (__NR_Linux + 150)
-#define __NR_munlock            (__NR_Linux + 151)
-#define __NR_mlockall           (__NR_Linux + 152)
-#define __NR_munlockall         (__NR_Linux + 153)
-#define __NR_sched_setparam             (__NR_Linux + 154)
-#define __NR_sched_getparam             (__NR_Linux + 155)
-#define __NR_sched_setscheduler         (__NR_Linux + 156)
-#define __NR_sched_getscheduler         (__NR_Linux + 157)
-#define __NR_sched_yield                (__NR_Linux + 158)
-#define __NR_sched_get_priority_max     (__NR_Linux + 159)
-#define __NR_sched_get_priority_min     (__NR_Linux + 160)
-#define __NR_sched_rr_get_interval      (__NR_Linux + 161)
-#define __NR_nanosleep          (__NR_Linux + 162)
-#define __NR_mremap             (__NR_Linux + 163)
-#define __NR_setresuid          (__NR_Linux + 164)
-#define __NR_getresuid          (__NR_Linux + 165)
-#define __NR_sigaltstack        (__NR_Linux + 166)
-#define __NR_query_module       (__NR_Linux + 167)
-#define __NR_poll               (__NR_Linux + 168)
-#define __NR_nfsservctl         (__NR_Linux + 169)
-#define __NR_setresgid          (__NR_Linux + 170)
-#define __NR_getresgid          (__NR_Linux + 171)
-#define __NR_prctl              (__NR_Linux + 172)
-#define __NR_rt_sigreturn       (__NR_Linux + 173)
-#define __NR_rt_sigaction       (__NR_Linux + 174)
-#define __NR_rt_sigprocmask     (__NR_Linux + 175)
-#define __NR_rt_sigpending      (__NR_Linux + 176)
-#define __NR_rt_sigtimedwait    (__NR_Linux + 177)
-#define __NR_rt_sigqueueinfo    (__NR_Linux + 178)
-#define __NR_rt_sigsuspend      (__NR_Linux + 179)
-#define __NR_chown              (__NR_Linux + 180)
-#define __NR_setsockopt         (__NR_Linux + 181)
-#define __NR_getsockopt         (__NR_Linux + 182)
-#define __NR_sendmsg            (__NR_Linux + 183)
-#define __NR_recvmsg            (__NR_Linux + 184)
-#define __NR_semop              (__NR_Linux + 185)
-#define __NR_semget             (__NR_Linux + 186)
-#define __NR_semctl             (__NR_Linux + 187)
-#define __NR_msgsnd             (__NR_Linux + 188)
-#define __NR_msgrcv             (__NR_Linux + 189)
-#define __NR_msgget             (__NR_Linux + 190)
-#define __NR_msgctl             (__NR_Linux + 191)
-#define __NR_shmat              (__NR_Linux + 192)
-#define __NR_shmdt              (__NR_Linux + 193)
-#define __NR_shmget             (__NR_Linux + 194)
-#define __NR_shmctl             (__NR_Linux + 195)
-
-#define __NR_getpmsg		(__NR_Linux + 196) /* Somebody *wants* streams? */
-#define __NR_putpmsg		(__NR_Linux + 197)
-
-#define __NR_lstat64            (__NR_Linux + 198)
-#define __NR_truncate64         (__NR_Linux + 199)
-#define __NR_ftruncate64        (__NR_Linux + 200)
-#define __NR_getdents64         (__NR_Linux + 201)
-#define __NR_fcntl64            (__NR_Linux + 202)
-#define __NR_attrctl            (__NR_Linux + 203)
-#define __NR_acl_get            (__NR_Linux + 204)
-#define __NR_acl_set            (__NR_Linux + 205)
-#define __NR_gettid             (__NR_Linux + 206)
-#define __NR_readahead          (__NR_Linux + 207)
-#define __NR_tkill              (__NR_Linux + 208)
-#define __NR_sendfile64         (__NR_Linux + 209)
-#define __NR_futex              (__NR_Linux + 210)
-#define __NR_sched_setaffinity  (__NR_Linux + 211)
-#define __NR_sched_getaffinity  (__NR_Linux + 212)
-#define __NR_set_thread_area    (__NR_Linux + 213)
-#define __NR_get_thread_area    (__NR_Linux + 214)
-#define __NR_io_setup           (__NR_Linux + 215)
-#define __NR_io_destroy         (__NR_Linux + 216)
-#define __NR_io_getevents       (__NR_Linux + 217)
-#define __NR_io_submit          (__NR_Linux + 218)
-#define __NR_io_cancel          (__NR_Linux + 219)
-#define __NR_alloc_hugepages    (__NR_Linux + 220)
-#define __NR_free_hugepages     (__NR_Linux + 221)
-#define __NR_exit_group         (__NR_Linux + 222)
-#define __NR_lookup_dcookie     (__NR_Linux + 223)
-#define __NR_epoll_create       (__NR_Linux + 224)
-#define __NR_epoll_ctl          (__NR_Linux + 225)
-#define __NR_epoll_wait         (__NR_Linux + 226)
-#define __NR_remap_file_pages   (__NR_Linux + 227)
-#define __NR_semtimedop         (__NR_Linux + 228)
-#define __NR_mq_open            (__NR_Linux + 229)
-#define __NR_mq_unlink          (__NR_Linux + 230)
-#define __NR_mq_timedsend       (__NR_Linux + 231)
-#define __NR_mq_timedreceive    (__NR_Linux + 232)
-#define __NR_mq_notify          (__NR_Linux + 233)
-#define __NR_mq_getsetattr      (__NR_Linux + 234)
-#define __NR_waitid		(__NR_Linux + 235)
-#define __NR_fadvise64_64	(__NR_Linux + 236)
-#define __NR_set_tid_address	(__NR_Linux + 237)
-#define __NR_setxattr		(__NR_Linux + 238)
-#define __NR_lsetxattr		(__NR_Linux + 239)
-#define __NR_fsetxattr		(__NR_Linux + 240)
-#define __NR_getxattr		(__NR_Linux + 241)
-#define __NR_lgetxattr		(__NR_Linux + 242)
-#define __NR_fgetxattr		(__NR_Linux + 243)
-#define __NR_listxattr		(__NR_Linux + 244)
-#define __NR_llistxattr		(__NR_Linux + 245)
-#define __NR_flistxattr		(__NR_Linux + 246)
-#define __NR_removexattr	(__NR_Linux + 247)
-#define __NR_lremovexattr	(__NR_Linux + 248)
-#define __NR_fremovexattr	(__NR_Linux + 249)
-#define __NR_timer_create	(__NR_Linux + 250)
-#define __NR_timer_settime	(__NR_Linux + 251)
-#define __NR_timer_gettime	(__NR_Linux + 252)
-#define __NR_timer_getoverrun	(__NR_Linux + 253)
-#define __NR_timer_delete	(__NR_Linux + 254)
-#define __NR_clock_settime	(__NR_Linux + 255)
-#define __NR_clock_gettime	(__NR_Linux + 256)
-#define __NR_clock_getres	(__NR_Linux + 257)
-#define __NR_clock_nanosleep	(__NR_Linux + 258)
-#define __NR_tgkill		(__NR_Linux + 259)
-#define __NR_mbind		(__NR_Linux + 260)
-#define __NR_get_mempolicy	(__NR_Linux + 261)
-#define __NR_set_mempolicy	(__NR_Linux + 262)
-#define __NR_vserver		(__NR_Linux + 263)
-#define __NR_add_key		(__NR_Linux + 264)
-#define __NR_request_key	(__NR_Linux + 265)
-#define __NR_keyctl		(__NR_Linux + 266)
-#define __NR_ioprio_set		(__NR_Linux + 267)
-#define __NR_ioprio_get		(__NR_Linux + 268)
-#define __NR_inotify_init	(__NR_Linux + 269)
-#define __NR_inotify_add_watch	(__NR_Linux + 270)
-#define __NR_inotify_rm_watch	(__NR_Linux + 271)
-#define __NR_migrate_pages	(__NR_Linux + 272)
-#define __NR_pselect6		(__NR_Linux + 273)
-#define __NR_ppoll		(__NR_Linux + 274)
-#define __NR_openat		(__NR_Linux + 275)
-#define __NR_mkdirat		(__NR_Linux + 276)
-#define __NR_mknodat		(__NR_Linux + 277)
-#define __NR_fchownat		(__NR_Linux + 278)
-#define __NR_futimesat		(__NR_Linux + 279)
-#define __NR_fstatat64		(__NR_Linux + 280)
-#define __NR_unlinkat		(__NR_Linux + 281)
-#define __NR_renameat		(__NR_Linux + 282)
-#define __NR_linkat		(__NR_Linux + 283)
-#define __NR_symlinkat		(__NR_Linux + 284)
-#define __NR_readlinkat		(__NR_Linux + 285)
-#define __NR_fchmodat		(__NR_Linux + 286)
-#define __NR_faccessat		(__NR_Linux + 287)
-#define __NR_unshare		(__NR_Linux + 288)
-#define __NR_set_robust_list	(__NR_Linux + 289)
-#define __NR_get_robust_list	(__NR_Linux + 290)
-#define __NR_splice		(__NR_Linux + 291)
-#define __NR_sync_file_range	(__NR_Linux + 292)
-#define __NR_tee		(__NR_Linux + 293)
-#define __NR_vmsplice		(__NR_Linux + 294)
-#define __NR_move_pages		(__NR_Linux + 295)
-#define __NR_getcpu		(__NR_Linux + 296)
-#define __NR_epoll_pwait	(__NR_Linux + 297)
-#define __NR_statfs64		(__NR_Linux + 298)
-#define __NR_fstatfs64		(__NR_Linux + 299)
-#define __NR_kexec_load		(__NR_Linux + 300)
-#define __NR_utimensat		(__NR_Linux + 301)
-#define __NR_signalfd		(__NR_Linux + 302)
-#define __NR_timerfd		(__NR_Linux + 303)
-#define __NR_eventfd		(__NR_Linux + 304)
-#define __NR_fallocate		(__NR_Linux + 305)
-#define __NR_timerfd_create	(__NR_Linux + 306)
-#define __NR_timerfd_settime	(__NR_Linux + 307)
-#define __NR_timerfd_gettime	(__NR_Linux + 308)
-
-#define __NR_Linux_syscalls	(__NR_timerfd_gettime + 1)
-
-
-#define __IGNORE_select		/* newselect */
-#define __IGNORE_fadvise64	/* fadvise64_64 */
-#define __IGNORE_utimes		/* utime */
-
-
-#define HPUX_GATEWAY_ADDR       0xC0000004
-#define LINUX_GATEWAY_ADDR      0x100
-
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-
-#define SYS_ify(syscall_name)   __NR_##syscall_name
-
-#ifndef ASM_LINE_SEP
-# define ASM_LINE_SEP ;
-#endif
-
-/* Definition taken from glibc 2.3.3
- * sysdeps/unix/sysv/linux/hppa/sysdep.h
- */
-
-#ifdef PIC
-/* WARNING: CANNOT BE USED IN A NOP! */
-# define K_STW_ASM_PIC	"       copy %%r19, %%r4\n"
-# define K_LDW_ASM_PIC	"       copy %%r4, %%r19\n"
-# define K_USING_GR4	"%r4",
-#else
-# define K_STW_ASM_PIC	" \n"
-# define K_LDW_ASM_PIC	" \n"
-# define K_USING_GR4
-#endif
-
-/* GCC has to be warned that a syscall may clobber all the ABI
-   registers listed as "caller-saves", see page 8, Table 2
-   in section 2.2.6 of the PA-RISC RUN-TIME architecture
-   document. However! r28 is the result and will conflict with
-   the clobber list so it is left out. Also the input arguments
-   registers r20 -> r26 will conflict with the list so they
-   are treated specially. Although r19 is clobbered by the syscall
-   we cannot say this because it would violate ABI, thus we say
-   r4 is clobbered and use that register to save/restore r19
-   across the syscall. */
-
-#define K_CALL_CLOB_REGS "%r1", "%r2", K_USING_GR4 \
-	        	 "%r20", "%r29", "%r31"
-
-#undef K_INLINE_SYSCALL
-#define K_INLINE_SYSCALL(name, nr, args...)	({			\
-	long __sys_res;							\
-	{								\
-		register unsigned long __res __asm__("r28");		\
-		K_LOAD_ARGS_##nr(args)					\
-		/* FIXME: HACK stw/ldw r19 around syscall */		\
-		__asm__ volatile(					\
-			K_STW_ASM_PIC					\
-			"	ble  0x100(%%sr2, %%r0)\n"		\
-			"	ldi %1, %%r20\n"			\
-			K_LDW_ASM_PIC					\
-			: "=r" (__res)					\
-			: "i" (SYS_ify(name)) K_ASM_ARGS_##nr   	\
-			: "memory", K_CALL_CLOB_REGS K_CLOB_ARGS_##nr	\
-		);							\
-		__sys_res = (long)__res;				\
-	}								\
-	if ( (unsigned long)__sys_res >= (unsigned long)-4095 ){	\
-		errno = -__sys_res;		        		\
-		__sys_res = -1;						\
-	}								\
-	__sys_res;							\
-})
-
-#define K_LOAD_ARGS_0()
-#define K_LOAD_ARGS_1(r26)					\
-	register unsigned long __r26 __asm__("r26") = (unsigned long)(r26);   \
-	K_LOAD_ARGS_0()
-#define K_LOAD_ARGS_2(r26,r25)					\
-	register unsigned long __r25 __asm__("r25") = (unsigned long)(r25);   \
-	K_LOAD_ARGS_1(r26)
-#define K_LOAD_ARGS_3(r26,r25,r24)				\
-	register unsigned long __r24 __asm__("r24") = (unsigned long)(r24);   \
-	K_LOAD_ARGS_2(r26,r25)
-#define K_LOAD_ARGS_4(r26,r25,r24,r23)				\
-	register unsigned long __r23 __asm__("r23") = (unsigned long)(r23);   \
-	K_LOAD_ARGS_3(r26,r25,r24)
-#define K_LOAD_ARGS_5(r26,r25,r24,r23,r22)			\
-	register unsigned long __r22 __asm__("r22") = (unsigned long)(r22);   \
-	K_LOAD_ARGS_4(r26,r25,r24,r23)
-#define K_LOAD_ARGS_6(r26,r25,r24,r23,r22,r21)			\
-	register unsigned long __r21 __asm__("r21") = (unsigned long)(r21);   \
-	K_LOAD_ARGS_5(r26,r25,r24,r23,r22)
-
-/* Even with zero args we use r20 for the syscall number */
-#define K_ASM_ARGS_0
-#define K_ASM_ARGS_1 K_ASM_ARGS_0, "r" (__r26)
-#define K_ASM_ARGS_2 K_ASM_ARGS_1, "r" (__r25)
-#define K_ASM_ARGS_3 K_ASM_ARGS_2, "r" (__r24)
-#define K_ASM_ARGS_4 K_ASM_ARGS_3, "r" (__r23)
-#define K_ASM_ARGS_5 K_ASM_ARGS_4, "r" (__r22)
-#define K_ASM_ARGS_6 K_ASM_ARGS_5, "r" (__r21)
-
-/* The registers not listed as inputs but clobbered */
-#define K_CLOB_ARGS_6
-#define K_CLOB_ARGS_5 K_CLOB_ARGS_6, "%r21"
-#define K_CLOB_ARGS_4 K_CLOB_ARGS_5, "%r22"
-#define K_CLOB_ARGS_3 K_CLOB_ARGS_4, "%r23"
-#define K_CLOB_ARGS_2 K_CLOB_ARGS_3, "%r24"
-#define K_CLOB_ARGS_1 K_CLOB_ARGS_2, "%r25"
-#define K_CLOB_ARGS_0 K_CLOB_ARGS_1, "%r26"
-
-#define _syscall0(type,name)						\
-type name(void)								\
-{									\
-    return K_INLINE_SYSCALL(name, 0);	                                \
-}
-
-#define _syscall1(type,name,type1,arg1)					\
-type name(type1 arg1)							\
-{									\
-    return K_INLINE_SYSCALL(name, 1, arg1);	                        \
-}
-
-#define _syscall2(type,name,type1,arg1,type2,arg2)			\
-type name(type1 arg1, type2 arg2)					\
-{									\
-    return K_INLINE_SYSCALL(name, 2, arg1, arg2);	                \
-}
-
-#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3)		\
-type name(type1 arg1, type2 arg2, type3 arg3)				\
-{									\
-    return K_INLINE_SYSCALL(name, 3, arg1, arg2, arg3);	                \
-}
-
-#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
-type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4)		\
-{									\
-    return K_INLINE_SYSCALL(name, 4, arg1, arg2, arg3, arg4);	        \
-}
-
-/* select takes 5 arguments */
-#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \
-type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5)	\
-{									\
-    return K_INLINE_SYSCALL(name, 5, arg1, arg2, arg3, arg4, arg5);	\
-}
-
-#define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SGETMASK
-#define __ARCH_WANT_SYS_SIGNAL
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_COMPAT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_OLD_GETRLIMIT
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_SIGPENDING
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_RT_SIGACTION
-#define __ARCH_WANT_SYS_RT_SIGSUSPEND
-#define __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND
-
-#endif /* __ASSEMBLY__ */
-
-#undef STR
-
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_PARISC_UNISTD_H_ */
diff --git a/include/asm-parisc/unwind.h b/include/asm-parisc/unwind.h
deleted file mode 100644
index 2f7e6e50a158..000000000000
--- a/include/asm-parisc/unwind.h
+++ /dev/null
@@ -1,77 +0,0 @@
-#ifndef _UNWIND_H_
-#define _UNWIND_H_
-
-#include <linux/list.h>
-
-/* From ABI specifications */
-struct unwind_table_entry {
-	unsigned int region_start;
-	unsigned int region_end;
-	unsigned int Cannot_unwind:1; /* 0 */
-	unsigned int Millicode:1;	/* 1 */
-	unsigned int Millicode_save_sr0:1;	/* 2 */
-	unsigned int Region_description:2;	/* 3..4 */
-	unsigned int reserved1:1;	/* 5 */
-	unsigned int Entry_SR:1;	/* 6 */
-	unsigned int Entry_FR:4;	/* number saved *//* 7..10 */
-	unsigned int Entry_GR:5;	/* number saved *//* 11..15 */
-	unsigned int Args_stored:1;	/* 16 */
-	unsigned int Variable_Frame:1;	/* 17 */
-	unsigned int Separate_Package_Body:1;	/* 18 */
-	unsigned int Frame_Extension_Millicode:1;	/* 19 */
-	unsigned int Stack_Overflow_Check:1;	/* 20 */
-	unsigned int Two_Instruction_SP_Increment:1;	/* 21 */
-	unsigned int Ada_Region:1;	/* 22 */
-	unsigned int cxx_info:1;	/* 23 */
-	unsigned int cxx_try_catch:1;	/* 24 */
-	unsigned int sched_entry_seq:1;	/* 25 */
-	unsigned int reserved2:1;	/* 26 */
-	unsigned int Save_SP:1;	/* 27 */
-	unsigned int Save_RP:1;	/* 28 */
-	unsigned int Save_MRP_in_frame:1;	/* 29 */
-	unsigned int extn_ptr_defined:1;	/* 30 */
-	unsigned int Cleanup_defined:1;	/* 31 */
-	
-	unsigned int MPE_XL_interrupt_marker:1;	/* 0 */
-	unsigned int HP_UX_interrupt_marker:1;	/* 1 */
-	unsigned int Large_frame:1;	/* 2 */
-	unsigned int Pseudo_SP_Set:1;	/* 3 */
-	unsigned int reserved4:1;	/* 4 */
-	unsigned int Total_frame_size:27;	/* 5..31 */
-};
-
-struct unwind_table {
-	struct list_head list;
-	const char *name;
-	unsigned long gp;
-	unsigned long base_addr;
-	unsigned long start;
-	unsigned long end;
-	const struct unwind_table_entry *table;
-	unsigned long length;
-};
-
-struct unwind_frame_info {
-	struct task_struct *t;
-	/* Eventually we would like to be able to get at any of the registers
-	   available; but for now we only try to get the sp and ip for each
-	   frame */
-	/* struct pt_regs regs; */
-	unsigned long sp, ip, rp, r31;
-	unsigned long prev_sp, prev_ip;
-};
-
-struct unwind_table *
-unwind_table_add(const char *name, unsigned long base_addr, 
-		 unsigned long gp, void *start, void *end);
-void
-unwind_table_remove(struct unwind_table *table);
-
-void unwind_frame_init(struct unwind_frame_info *info, struct task_struct *t, 
-		       struct pt_regs *regs);
-void unwind_frame_init_from_blocked_task(struct unwind_frame_info *info, struct task_struct *t);
-void unwind_frame_init_running(struct unwind_frame_info *info, struct pt_regs *regs);
-int unwind_once(struct unwind_frame_info *info);
-int unwind_to_user(struct unwind_frame_info *info);
-
-#endif
diff --git a/include/asm-parisc/user.h b/include/asm-parisc/user.h
deleted file mode 100644
index 80224753e508..000000000000
--- a/include/asm-parisc/user.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* This file should not exist, but lots of generic code still includes
-   it. It's a hangover from old a.out days and the traditional core
-   dump format.  We are ELF-only, and so are our core dumps.  If we
-   need to support HP/UX core format then we'll do it here
-   eventually. */
diff --git a/include/asm-parisc/vga.h b/include/asm-parisc/vga.h
deleted file mode 100644
index 171399a88ca6..000000000000
--- a/include/asm-parisc/vga.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_PARISC_VGA_H__
-#define __ASM_PARISC_VGA_H__
-
-/* nothing */
-
-#endif /* __ASM_PARISC_VGA_H__ */
diff --git a/include/asm-parisc/xor.h b/include/asm-parisc/xor.h
deleted file mode 100644
index c82eb12a5b18..000000000000
--- a/include/asm-parisc/xor.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/xor.h>
diff --git a/include/asm-um/a.out-core.h b/include/asm-um/a.out-core.h
deleted file mode 100644
index 995643b18309..000000000000
--- a/include/asm-um/a.out-core.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* a.out coredump register dumper
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef __UM_A_OUT_CORE_H
-#define __UM_A_OUT_CORE_H
-
-#ifdef __KERNEL__
-
-#include <linux/user.h>
-
-/*
- * fill in the user structure for an a.out core dump
- */
-static inline void aout_dump_thread(struct pt_regs *regs, struct user *u)
-{
-}
-
-#endif /* __KERNEL__ */
-#endif /* __UM_A_OUT_CORE_H */
diff --git a/include/asm-um/a.out.h b/include/asm-um/a.out.h
deleted file mode 100644
index 754181ee8683..000000000000
--- a/include/asm-um/a.out.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (C) 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-
-#ifndef __UM_A_OUT_H
-#define __UM_A_OUT_H
-
-#include "asm/arch/a.out.h"
-
-#endif
diff --git a/include/asm-um/alternative-asm.h b/include/asm-um/alternative-asm.h
deleted file mode 100644
index 9aa9fa2402a4..000000000000
--- a/include/asm-um/alternative-asm.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_ALTERNATIVE_ASM_I
-#define __UM_ALTERNATIVE_ASM_I
-
-#include "asm/arch/alternative-asm.h"
-
-#endif
diff --git a/include/asm-um/alternative.h b/include/asm-um/alternative.h
deleted file mode 100644
index b6434396bd42..000000000000
--- a/include/asm-um/alternative.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_ALTERNATIVE_H
-#define __UM_ALTERNATIVE_H
-
-#include "asm/arch/alternative.h"
-
-#endif
diff --git a/include/asm-um/apic.h b/include/asm-um/apic.h
deleted file mode 100644
index 876dee84ab11..000000000000
--- a/include/asm-um/apic.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __UM_APIC_H
-#define __UM_APIC_H
-
-#endif
diff --git a/include/asm-um/archparam-i386.h b/include/asm-um/archparam-i386.h
deleted file mode 100644
index 49e89b8d7e58..000000000000
--- a/include/asm-um/archparam-i386.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* 
- * Copyright (C) 2000 - 2003 Jeff Dike (jdike@addtoit.com)
- * Licensed under the GPL
- */
-
-#ifndef __UM_ARCHPARAM_I386_H
-#define __UM_ARCHPARAM_I386_H
-
-/********* Nothing for asm-um/hardirq.h **********/
-
-/********* Nothing for asm-um/hw_irq.h **********/
-
-/********* Nothing for asm-um/string.h **********/
-
-#endif
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff --git a/include/asm-um/archparam-ppc.h b/include/asm-um/archparam-ppc.h
deleted file mode 100644
index 4269d8a37b4f..000000000000
--- a/include/asm-um/archparam-ppc.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __UM_ARCHPARAM_PPC_H
-#define __UM_ARCHPARAM_PPC_H
-
-/********* Bits for asm-um/string.h **********/
-
-#define __HAVE_ARCH_STRRCHR
-
-#endif
diff --git a/include/asm-um/archparam-x86_64.h b/include/asm-um/archparam-x86_64.h
deleted file mode 100644
index 270ed9586b68..000000000000
--- a/include/asm-um/archparam-x86_64.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright 2003 PathScale, Inc.
- *
- * Licensed under the GPL
- */
-
-#ifndef __UM_ARCHPARAM_X86_64_H
-#define __UM_ARCHPARAM_X86_64_H
-
-
-/* No user-accessible fixmap addresses, i.e. vsyscall */
-#define FIXADDR_USER_START	0
-#define FIXADDR_USER_END	0
-
-#endif
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff --git a/include/asm-um/asm.h b/include/asm-um/asm.h
deleted file mode 100644
index af1269a1e9eb..000000000000
--- a/include/asm-um/asm.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_ASM_H
-#define __UM_ASM_H
-
-#include "asm/arch/asm.h"
-
-#endif
diff --git a/include/asm-um/atomic.h b/include/asm-um/atomic.h
deleted file mode 100644
index b683f1034d1e..000000000000
--- a/include/asm-um/atomic.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __UM_ATOMIC_H
-#define __UM_ATOMIC_H
-
-/* The i386 atomic.h calls printk, but doesn't include kernel.h, so we
- * include it here.
- */
-#include "linux/kernel.h"
-
-#include "asm/arch/atomic.h"
-
-#endif
diff --git a/include/asm-um/auxvec.h b/include/asm-um/auxvec.h
deleted file mode 100644
index 1e5e1c2fc9b1..000000000000
--- a/include/asm-um/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __UM_AUXVEC_H
-#define __UM_AUXVEC_H
-
-#endif
diff --git a/include/asm-um/bitops.h b/include/asm-um/bitops.h
deleted file mode 100644
index e4d38d437b97..000000000000
--- a/include/asm-um/bitops.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __UM_BITOPS_H
-#define __UM_BITOPS_H
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include "asm/arch/bitops.h"
-
-#endif
diff --git a/include/asm-um/boot.h b/include/asm-um/boot.h
deleted file mode 100644
index 09548c3e784e..000000000000
--- a/include/asm-um/boot.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_BOOT_H
-#define __UM_BOOT_H
-
-#include "asm/arch/boot.h"
-
-#endif
diff --git a/include/asm-um/bug.h b/include/asm-um/bug.h
deleted file mode 100644
index 9e33b864c359..000000000000
--- a/include/asm-um/bug.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_BUG_H
-#define __UM_BUG_H
-
-#include <asm-generic/bug.h>
-
-#endif
diff --git a/include/asm-um/bugs.h b/include/asm-um/bugs.h
deleted file mode 100644
index 6a72e240d5fc..000000000000
--- a/include/asm-um/bugs.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_BUGS_H
-#define __UM_BUGS_H
-
-void check_bugs(void);
-
-#endif
diff --git a/include/asm-um/byteorder.h b/include/asm-um/byteorder.h
deleted file mode 100644
index eee0a834f447..000000000000
--- a/include/asm-um/byteorder.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_BYTEORDER_H
-#define __UM_BYTEORDER_H
-
-#include "asm/arch/byteorder.h"
-
-#endif
diff --git a/include/asm-um/cache.h b/include/asm-um/cache.h
deleted file mode 100644
index 19e1bdd67416..000000000000
--- a/include/asm-um/cache.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef __UM_CACHE_H
-#define __UM_CACHE_H
-
-
-#if defined(CONFIG_UML_X86) && !defined(CONFIG_64BIT)
-# define L1_CACHE_SHIFT		(CONFIG_X86_L1_CACHE_SHIFT)
-#elif defined(CONFIG_UML_X86) /* 64-bit */
-# define L1_CACHE_SHIFT		6 /* Should be 7 on Intel */
-#else
-/* XXX: this was taken from x86, now it's completely random. Luckily only
- * affects SMP padding. */
-# define L1_CACHE_SHIFT		5
-#endif
-
-#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
-
-#endif
diff --git a/include/asm-um/cacheflush.h b/include/asm-um/cacheflush.h
deleted file mode 100644
index 12e9d4b74c8f..000000000000
--- a/include/asm-um/cacheflush.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_CACHEFLUSH_H
-#define __UM_CACHEFLUSH_H
-
-#include "asm/arch/cacheflush.h"
-
-#endif
diff --git a/include/asm-um/calling.h b/include/asm-um/calling.h
deleted file mode 100644
index 0b2384cc99fd..000000000000
--- a/include/asm-um/calling.h
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2003 - 2004 Pathscale, Inc
-# Released under the GPL
-
-#ifndef __UM_CALLING_H /* XXX x86_64 */
-#define __UM_CALLING_H
-
-#include "asm/arch/calling.h"
-
-#endif
diff --git a/include/asm-um/checksum.h b/include/asm-um/checksum.h
deleted file mode 100644
index 5b501361e361..000000000000
--- a/include/asm-um/checksum.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_CHECKSUM_H
-#define __UM_CHECKSUM_H
-
-#include "sysdep/checksum.h"
-
-#endif
diff --git a/include/asm-um/cmpxchg.h b/include/asm-um/cmpxchg.h
deleted file mode 100644
index 529376a99885..000000000000
--- a/include/asm-um/cmpxchg.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_CMPXCHG_H
-#define __UM_CMPXCHG_H
-
-#include "asm/arch/cmpxchg.h"
-
-#endif
diff --git a/include/asm-um/cobalt.h b/include/asm-um/cobalt.h
deleted file mode 100644
index f813a684be98..000000000000
--- a/include/asm-um/cobalt.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_COBALT_H
-#define __UM_COBALT_H
-
-#include "asm/arch/cobalt.h"
-
-#endif
diff --git a/include/asm-um/common.lds.S b/include/asm-um/common.lds.S
deleted file mode 100644
index cb0248616d49..000000000000
--- a/include/asm-um/common.lds.S
+++ /dev/null
@@ -1,130 +0,0 @@
-#include <asm-generic/vmlinux.lds.h>
-
-  .fini      : { *(.fini)    } =0x9090
-  _etext = .;
-  PROVIDE (etext = .);
-
-  . = ALIGN(4096);
-  _sdata = .;
-  PROVIDE (sdata = .);
-
-  RODATA
-
-  .unprotected : { *(.unprotected) }
-  . = ALIGN(4096);
-  PROVIDE (_unprotected_end = .);
-
-  . = ALIGN(4096);
-  .note : { *(.note.*) }
-  __ex_table : {
-	__start___ex_table = .;
-	*(__ex_table)
-	__stop___ex_table = .;
-  }
-
-  BUG_TABLE
-
-  .uml.setup.init : {
-	__uml_setup_start = .;
-	*(.uml.setup.init)
-	__uml_setup_end = .;
-  }
-	
-  .uml.help.init : {
-	__uml_help_start = .;
-	*(.uml.help.init)
-	__uml_help_end = .;
-  }
-	
-  .uml.postsetup.init : {
-	__uml_postsetup_start = .;
-	*(.uml.postsetup.init)
-	__uml_postsetup_end = .;
-  }
-	
-  .init.setup : {
-	__setup_start = .;
-	*(.init.setup)
-	__setup_end = .;
-  }
-
-  . = ALIGN(32);
-  .data.percpu : {
-	__per_cpu_start = . ;
-	*(.data.percpu)
-	__per_cpu_end = . ;
-  }
-	
-  .initcall.init : {
-	__initcall_start = .;
-	INITCALLS
-	__initcall_end = .;
-  }
-
-  .con_initcall.init : {
-	__con_initcall_start = .;
-	*(.con_initcall.init)
-	__con_initcall_end = .;
-  }
-
-  .uml.initcall.init : {
-	__uml_initcall_start = .;
-	*(.uml.initcall.init)
-	__uml_initcall_end = .;
-  }
-  __init_end = .;
-
-  SECURITY_INIT
-
-  .exitcall : {
-	__exitcall_begin = .;
-	*(.exitcall.exit)
-	__exitcall_end = .;
-  }
-
-  .uml.exitcall : {
-	__uml_exitcall_begin = .;
-	*(.uml.exitcall.exit)
-	__uml_exitcall_end = .;
-  }
-
-  . = ALIGN(4);
-  .altinstructions : {
-	__alt_instructions = .;
-	*(.altinstructions)
-	__alt_instructions_end = .;
-  }
-  .altinstr_replacement : { *(.altinstr_replacement) }
-  /* .exit.text is discard at runtime, not link time, to deal with references
-     from .altinstructions and .eh_frame */
-  .exit.text : { *(.exit.text) }
-  .exit.data : { *(.exit.data) }
-
-  .preinit_array : {
-	__preinit_array_start = .;
-	*(.preinit_array)
-	__preinit_array_end = .;
-  }
-  .init_array : {
-	__init_array_start = .;
-	*(.init_array)
-	__init_array_end = .;
-  }
-  .fini_array : {
-	__fini_array_start = .;
-	*(.fini_array)
-	__fini_array_end = .;
-  }
-
-   . = ALIGN(4096);
-  .init.ramfs : {
-	__initramfs_start = .;
-	*(.init.ramfs)
-	__initramfs_end = .;
-  }
-
-  /* Sections to be discarded */
-  /DISCARD/ : {
- 	*(.exitcall.exit)
-  }
-
diff --git a/include/asm-um/cpufeature.h b/include/asm-um/cpufeature.h
deleted file mode 100644
index fb7bd42a4d96..000000000000
--- a/include/asm-um/cpufeature.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_CPUFEATURE_H
-#define __UM_CPUFEATURE_H
-
-#include "asm/arch/cpufeature.h"
-
-#endif
diff --git a/include/asm-um/cputime.h b/include/asm-um/cputime.h
deleted file mode 100644
index c84acbadfa2f..000000000000
--- a/include/asm-um/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_CPUTIME_H
-#define __UM_CPUTIME_H
-
-#include <asm-generic/cputime.h>
-
-#endif /* __UM_CPUTIME_H */
diff --git a/include/asm-um/current.h b/include/asm-um/current.h
deleted file mode 100644
index c2191d9aa03d..000000000000
--- a/include/asm-um/current.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-
-#ifndef __UM_CURRENT_H
-#define __UM_CURRENT_H
-
-#include "linux/thread_info.h"
-
-#define current (current_thread_info()->task)
-
-#endif
diff --git a/include/asm-um/delay.h b/include/asm-um/delay.h
deleted file mode 100644
index c71e32b6741e..000000000000
--- a/include/asm-um/delay.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __UM_DELAY_H
-#define __UM_DELAY_H
-
-#define MILLION 1000000
-
-/* Undefined on purpose */
-extern void __bad_udelay(void);
-
-extern void __udelay(unsigned long usecs);
-extern void __delay(unsigned long loops);
-
-#define udelay(n) ((__builtin_constant_p(n) && (n) > 20000) ? \
-	__bad_udelay() : __udelay(n))
-
-/* It appears that ndelay is not used at all for UML, and has never been
- * implemented. */
-extern void __unimplemented_ndelay(void);
-#define ndelay(n) __unimplemented_ndelay()
-
-#endif
diff --git a/include/asm-um/desc.h b/include/asm-um/desc.h
deleted file mode 100644
index 4ec34a51b62c..000000000000
--- a/include/asm-um/desc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __UM_DESC_H
-#define __UM_DESC_H
-
-/* Taken from asm-i386/desc.h, it's the only thing we need. The rest wouldn't
- * compile, and has never been used. */
-#define LDT_empty(info) (\
-	(info)->base_addr	== 0	&& \
-	(info)->limit		== 0	&& \
-	(info)->contents	== 0	&& \
-	(info)->read_exec_only	== 1	&& \
-	(info)->seg_32bit	== 0	&& \
-	(info)->limit_in_pages	== 0	&& \
-	(info)->seg_not_present	== 1	&& \
-	(info)->useable		== 0	)
-
-#endif
diff --git a/include/asm-um/device.h b/include/asm-um/device.h
deleted file mode 100644
index d8f9872b0e2d..000000000000
--- a/include/asm-um/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-#include <asm-generic/device.h>
-
diff --git a/include/asm-um/div64.h b/include/asm-um/div64.h
deleted file mode 100644
index 1e17f7409cab..000000000000
--- a/include/asm-um/div64.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _UM_DIV64_H
-#define _UM_DIV64_H
-
-#include "asm/arch/div64.h"
-
-#endif
diff --git a/include/asm-um/dma-mapping.h b/include/asm-um/dma-mapping.h
deleted file mode 100644
index 90fc708b320e..000000000000
--- a/include/asm-um/dma-mapping.h
+++ /dev/null
@@ -1,128 +0,0 @@
-#ifndef _ASM_DMA_MAPPING_H
-#define _ASM_DMA_MAPPING_H
-
-#include <asm/scatterlist.h>
-
-static inline int
-dma_supported(struct device *dev, u64 mask)
-{
-	BUG();
-	return(0);
-}
-
-static inline int
-dma_set_mask(struct device *dev, u64 dma_mask)
-{
-	BUG();
-	return(0);
-}
-
-static inline void *
-dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
-		   gfp_t flag)
-{
-	BUG();
-	return((void *) 0);
-}
-
-static inline void
-dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
-		  dma_addr_t dma_handle)
-{
-	BUG();
-}
-
-static inline dma_addr_t
-dma_map_single(struct device *dev, void *cpu_addr, size_t size,
-	       enum dma_data_direction direction)
-{
-	BUG();
-	return(0);
-}
-
-static inline void
-dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
-		 enum dma_data_direction direction)
-{
-	BUG();
-}
-
-static inline dma_addr_t
-dma_map_page(struct device *dev, struct page *page,
-	     unsigned long offset, size_t size,
-	     enum dma_data_direction direction)
-{
-	BUG();
-	return(0);
-}
-
-static inline void
-dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
-	       enum dma_data_direction direction)
-{
-	BUG();
-}
-
-static inline int
-dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-	   enum dma_data_direction direction)
-{
-	BUG();
-	return(0);
-}
-
-static inline void
-dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
-	     enum dma_data_direction direction)
-{
-	BUG();
-}
-
-static inline void
-dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size,
-		enum dma_data_direction direction)
-{
-	BUG();
-}
-
-static inline void
-dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems,
-	    enum dma_data_direction direction)
-{
-	BUG();
-}
-
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-#define dma_is_consistent(d, h) (1)
-
-static inline int
-dma_get_cache_alignment(void)
-{
-	BUG();
-	return(0);
-}
-
-static inline void
-dma_sync_single_range(struct device *dev, dma_addr_t dma_handle,
-		      unsigned long offset, size_t size,
-		      enum dma_data_direction direction)
-{
-	BUG();
-}
-
-static inline void
-dma_cache_sync(struct device *dev, void *vaddr, size_t size,
-	       enum dma_data_direction direction)
-{
-	BUG();
-}
-
-static inline int
-dma_mapping_error(struct device *dev, dma_addr_t dma_handle)
-{
-	BUG();
-	return 0;
-}
-
-#endif
diff --git a/include/asm-um/dma.h b/include/asm-um/dma.h
deleted file mode 100644
index 9f6139a8a525..000000000000
--- a/include/asm-um/dma.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __UM_DMA_H
-#define __UM_DMA_H
-
-#include "asm/io.h"
-
-extern unsigned long uml_physmem;
-
-#define MAX_DMA_ADDRESS (uml_physmem)
-
-#endif
diff --git a/include/asm-um/dwarf2.h b/include/asm-um/dwarf2.h
deleted file mode 100644
index d1a02e762931..000000000000
--- a/include/asm-um/dwarf2.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2003 - 2004 Pathscale, Inc
- * Released under the GPL
- */
-
-/* Needed on x86_64 by thunk.S */
-#ifndef __UM_DWARF2_H
-#define __UM_DWARF2_H
-
-#include "asm/arch/dwarf2.h"
-
-#endif
diff --git a/include/asm-um/elf-i386.h b/include/asm-um/elf-i386.h
deleted file mode 100644
index 23d6893e8617..000000000000
--- a/include/asm-um/elf-i386.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-#ifndef __UM_ELF_I386_H
-#define __UM_ELF_I386_H
-
-#include <asm/user.h>
-#include "skas.h"
-
-#define R_386_NONE	0
-#define R_386_32	1
-#define R_386_PC32	2
-#define R_386_GOT32	3
-#define R_386_PLT32	4
-#define R_386_COPY	5
-#define R_386_GLOB_DAT	6
-#define R_386_JMP_SLOT	7
-#define R_386_RELATIVE	8
-#define R_386_GOTOFF	9
-#define R_386_GOTPC	10
-#define R_386_NUM	11
-
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct user_i387_struct elf_fpregset_t;
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) \
-	(((x)->e_machine == EM_386) || ((x)->e_machine == EM_486))
-
-#define ELF_CLASS	ELFCLASS32
-#define ELF_DATA        ELFDATA2LSB
-#define ELF_ARCH        EM_386
-
-#define ELF_PLAT_INIT(regs, load_addr) do { \
-	PT_REGS_EBX(regs) = 0; \
-	PT_REGS_ECX(regs) = 0; \
-	PT_REGS_EDX(regs) = 0; \
-	PT_REGS_ESI(regs) = 0; \
-	PT_REGS_EDI(regs) = 0; \
-	PT_REGS_EBP(regs) = 0; \
-	PT_REGS_EAX(regs) = 0; \
-} while (0)
-
-#define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE 4096
-
-#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
-
-/* Shamelessly stolen from include/asm-i386/elf.h */
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs) do {	\
-	pr_reg[0] = PT_REGS_EBX(regs);		\
-	pr_reg[1] = PT_REGS_ECX(regs);		\
-	pr_reg[2] = PT_REGS_EDX(regs);		\
-	pr_reg[3] = PT_REGS_ESI(regs);		\
-	pr_reg[4] = PT_REGS_EDI(regs);		\
-	pr_reg[5] = PT_REGS_EBP(regs);		\
-	pr_reg[6] = PT_REGS_EAX(regs);		\
-	pr_reg[7] = PT_REGS_DS(regs);		\
-	pr_reg[8] = PT_REGS_ES(regs);		\
-	/* fake once used fs and gs selectors? */	\
-	pr_reg[9] = PT_REGS_DS(regs);		\
-	pr_reg[10] = PT_REGS_DS(regs);		\
-	pr_reg[11] = PT_REGS_SYSCALL_NR(regs);	\
-	pr_reg[12] = PT_REGS_IP(regs);		\
-	pr_reg[13] = PT_REGS_CS(regs);		\
-	pr_reg[14] = PT_REGS_EFLAGS(regs);	\
-	pr_reg[15] = PT_REGS_SP(regs);		\
-	pr_reg[16] = PT_REGS_SS(regs);		\
-} while (0);
-
-extern int elf_core_copy_fpregs(struct task_struct *t, elf_fpregset_t *fpu);
-
-#define ELF_CORE_COPY_FPREGS(t, fpu) elf_core_copy_fpregs(t, fpu)
-
-extern long elf_aux_hwcap;
-#define ELF_HWCAP (elf_aux_hwcap)
-
-extern char * elf_aux_platform;
-#define ELF_PLATFORM (elf_aux_platform)
-
-#define SET_PERSONALITY(ex, ibcs2) do { } while (0)
-
-extern unsigned long vsyscall_ehdr;
-extern unsigned long vsyscall_end;
-extern unsigned long __kernel_vsyscall;
-
-#define VSYSCALL_BASE vsyscall_ehdr
-#define VSYSCALL_END vsyscall_end
-
-/*
- * This is the range that is readable by user mode, and things
- * acting like user mode such as get_user_pages.
- */
-#define FIXADDR_USER_START      VSYSCALL_BASE
-#define FIXADDR_USER_END        VSYSCALL_END
-
-/*
- * Architecture-neutral AT_ values in 0-17, leave some room
- * for more of them, start the x86-specific ones at 32.
- */
-#define AT_SYSINFO		32
-#define AT_SYSINFO_EHDR		33
-
-#define ARCH_DLINFO						\
-do {								\
-	if ( vsyscall_ehdr ) {					\
-		NEW_AUX_ENT(AT_SYSINFO,	__kernel_vsyscall);	\
-		NEW_AUX_ENT(AT_SYSINFO_EHDR, vsyscall_ehdr);	\
-	}							\
-} while (0)
-
-/*
- * These macros parameterize elf_core_dump in fs/binfmt_elf.c to write out
- * extra segments containing the vsyscall DSO contents.  Dumping its
- * contents makes post-mortem fully interpretable later without matching up
- * the same kernel and hardware config to see what PC values meant.
- * Dumping its extra ELF program headers includes all the other information
- * a debugger needs to easily find how the vsyscall DSO was being used.
- */
-#define ELF_CORE_EXTRA_PHDRS						      \
-	(vsyscall_ehdr ? (((struct elfhdr *)vsyscall_ehdr)->e_phnum) : 0 )
-
-#define ELF_CORE_WRITE_EXTRA_PHDRS					      \
-if ( vsyscall_ehdr ) {							      \
-	const struct elfhdr *const ehdrp = (struct elfhdr *)vsyscall_ehdr;    \
-	const struct elf_phdr *const phdrp =				      \
-		(const struct elf_phdr *) (vsyscall_ehdr + ehdrp->e_phoff);   \
-	int i;								      \
-	Elf32_Off ofs = 0;						      \
-	for (i = 0; i < ehdrp->e_phnum; ++i) {				      \
-		struct elf_phdr phdr = phdrp[i];			      \
-		if (phdr.p_type == PT_LOAD) {				      \
-			ofs = phdr.p_offset = offset;			      \
-			offset += phdr.p_filesz;			      \
-		}							      \
-		else							      \
-			phdr.p_offset += ofs;				      \
-		phdr.p_paddr = 0; /* match other core phdrs */		      \
-		DUMP_WRITE(&phdr, sizeof(phdr));			      \
-	}								      \
-}
-#define ELF_CORE_WRITE_EXTRA_DATA					      \
-if ( vsyscall_ehdr ) {							      \
-	const struct elfhdr *const ehdrp = (struct elfhdr *)vsyscall_ehdr;    \
-	const struct elf_phdr *const phdrp =				      \
-		(const struct elf_phdr *) (vsyscall_ehdr + ehdrp->e_phoff);   \
-	int i;								      \
-	for (i = 0; i < ehdrp->e_phnum; ++i) {				      \
-		if (phdrp[i].p_type == PT_LOAD)				      \
-			DUMP_WRITE((void *) phdrp[i].p_vaddr,		      \
-				   phdrp[i].p_filesz);			      \
-	}								      \
-}
-
-#endif
diff --git a/include/asm-um/elf-ppc.h b/include/asm-um/elf-ppc.h
deleted file mode 100644
index d3b90b7ac3e9..000000000000
--- a/include/asm-um/elf-ppc.h
+++ /dev/null
@@ -1,53 +0,0 @@
-#ifndef __UM_ELF_PPC_H
-#define __UM_ELF_PPC_H
-
-
-extern long elf_aux_hwcap;
-#define ELF_HWCAP (elf_aux_hwcap)
-
-#define SET_PERSONALITY(ex, ibcs2) do ; while(0)
-
-#define ELF_EXEC_PAGESIZE 4096
-
-#define elf_check_arch(x) (1)
-
-#ifdef CONFIG_64BIT
-#define ELF_CLASS ELFCLASS64
-#else
-#define ELF_CLASS ELFCLASS32
-#endif
-
-#define USE_ELF_CORE_DUMP
-
-#define R_386_NONE	0
-#define R_386_32	1
-#define R_386_PC32	2
-#define R_386_GOT32	3
-#define R_386_PLT32	4
-#define R_386_COPY	5
-#define R_386_GLOB_DAT	6
-#define R_386_JMP_SLOT	7
-#define R_386_RELATIVE	8
-#define R_386_GOTOFF	9
-#define R_386_GOTPC	10
-#define R_386_NUM	11
-
-#define ELF_PLATFORM (0)
-
-#define ELF_ET_DYN_BASE (0x08000000)
-
-/* the following stolen from asm-ppc/elf.h */
-#define ELF_NGREG	48	/* includes nip, msr, lr, etc. */
-#define ELF_NFPREG	33	/* includes fpscr */
-/* General registers */
-typedef unsigned long elf_greg_t;
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-/* Floating point registers */
-typedef double elf_fpreg_t;
-typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
-
-#define ELF_DATA        ELFDATA2MSB
-#define ELF_ARCH	EM_PPC
-
-#endif
diff --git a/include/asm-um/elf-x86_64.h b/include/asm-um/elf-x86_64.h
deleted file mode 100644
index 3b2d5224a7e1..000000000000
--- a/include/asm-um/elf-x86_64.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright 2003 PathScale, Inc.
- * Copyright (C) 2003 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- *
- * Licensed under the GPL
- */
-#ifndef __UM_ELF_X86_64_H
-#define __UM_ELF_X86_64_H
-
-#include <asm/user.h>
-#include "skas.h"
-
-/* x86-64 relocation types, taken from asm-x86_64/elf.h */
-#define R_X86_64_NONE		0	/* No reloc */
-#define R_X86_64_64		1	/* Direct 64 bit  */
-#define R_X86_64_PC32		2	/* PC relative 32 bit signed */
-#define R_X86_64_GOT32		3	/* 32 bit GOT entry */
-#define R_X86_64_PLT32		4	/* 32 bit PLT address */
-#define R_X86_64_COPY		5	/* Copy symbol at runtime */
-#define R_X86_64_GLOB_DAT	6	/* Create GOT entry */
-#define R_X86_64_JUMP_SLOT	7	/* Create PLT entry */
-#define R_X86_64_RELATIVE	8	/* Adjust by program base */
-#define R_X86_64_GOTPCREL	9	/* 32 bit signed pc relative
-					   offset to GOT */
-#define R_X86_64_32		10	/* Direct 32 bit zero extended */
-#define R_X86_64_32S		11	/* Direct 32 bit sign extended */
-#define R_X86_64_16		12	/* Direct 16 bit zero extended */
-#define R_X86_64_PC16		13	/* 16 bit sign extended pc relative */
-#define R_X86_64_8		14	/* Direct 8 bit sign extended  */
-#define R_X86_64_PC8		15	/* 8 bit sign extended pc relative */
-
-#define R_X86_64_NUM		16
-
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct user_i387_struct elf_fpregset_t;
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) \
-	((x)->e_machine == EM_X86_64)
-
-#define ELF_CLASS	ELFCLASS64
-#define ELF_DATA        ELFDATA2LSB
-#define ELF_ARCH        EM_X86_64
-
-#define ELF_PLAT_INIT(regs, load_addr)    do { \
-	PT_REGS_RBX(regs) = 0; \
-	PT_REGS_RCX(regs) = 0; \
-	PT_REGS_RDX(regs) = 0; \
-	PT_REGS_RSI(regs) = 0; \
-	PT_REGS_RDI(regs) = 0; \
-	PT_REGS_RBP(regs) = 0; \
-	PT_REGS_RAX(regs) = 0; \
-	PT_REGS_R8(regs) = 0; \
-	PT_REGS_R9(regs) = 0; \
-	PT_REGS_R10(regs) = 0; \
-	PT_REGS_R11(regs) = 0; \
-	PT_REGS_R12(regs) = 0; \
-	PT_REGS_R13(regs) = 0; \
-	PT_REGS_R14(regs) = 0; \
-	PT_REGS_R15(regs) = 0; \
-} while (0)
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs)		\
-	(pr_reg)[0] = (regs)->regs.gp[0];			\
-	(pr_reg)[1] = (regs)->regs.gp[1];			\
-	(pr_reg)[2] = (regs)->regs.gp[2];			\
-	(pr_reg)[3] = (regs)->regs.gp[3];			\
-	(pr_reg)[4] = (regs)->regs.gp[4];			\
-	(pr_reg)[5] = (regs)->regs.gp[5];			\
-	(pr_reg)[6] = (regs)->regs.gp[6];			\
-	(pr_reg)[7] = (regs)->regs.gp[7];			\
-	(pr_reg)[8] = (regs)->regs.gp[8];			\
-	(pr_reg)[9] = (regs)->regs.gp[9];			\
-	(pr_reg)[10] = (regs)->regs.gp[10];			\
-	(pr_reg)[11] = (regs)->regs.gp[11];			\
-	(pr_reg)[12] = (regs)->regs.gp[12];			\
-	(pr_reg)[13] = (regs)->regs.gp[13];			\
-	(pr_reg)[14] = (regs)->regs.gp[14];			\
-	(pr_reg)[15] = (regs)->regs.gp[15];			\
-	(pr_reg)[16] = (regs)->regs.gp[16];			\
-	(pr_reg)[17] = (regs)->regs.gp[17];			\
-	(pr_reg)[18] = (regs)->regs.gp[18];			\
-	(pr_reg)[19] = (regs)->regs.gp[19];			\
-	(pr_reg)[20] = (regs)->regs.gp[20];			\
-	(pr_reg)[21] = current->thread.arch.fs;			\
-	(pr_reg)[22] = 0;					\
-	(pr_reg)[23] = 0;					\
-	(pr_reg)[24] = 0;					\
-	(pr_reg)[25] = 0;					\
-	(pr_reg)[26] = 0;
-
-extern int elf_core_copy_fpregs(struct task_struct *t, elf_fpregset_t *fpu);
-
-#define ELF_CORE_COPY_FPREGS(t, fpu) elf_core_copy_fpregs(t, fpu)
-
-#ifdef TIF_IA32 /* XXX */
-#error XXX, indeed
-        clear_thread_flag(TIF_IA32);
-#endif
-
-#define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE 4096
-
-#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
-
-extern long elf_aux_hwcap;
-#define ELF_HWCAP (elf_aux_hwcap)
-
-#define ELF_PLATFORM "x86_64"
-
-#define SET_PERSONALITY(ex, ibcs2) do ; while(0)
-
-#endif
diff --git a/include/asm-um/emergency-restart.h b/include/asm-um/emergency-restart.h
deleted file mode 100644
index 108d8c48e42e..000000000000
--- a/include/asm-um/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_EMERGENCY_RESTART_H
-#define _ASM_EMERGENCY_RESTART_H
-
-#include <asm-generic/emergency-restart.h>
-
-#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-um/errno.h b/include/asm-um/errno.h
deleted file mode 100644
index b7a9e37fd8d8..000000000000
--- a/include/asm-um/errno.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_ERRNO_H
-#define __UM_ERRNO_H
-
-#include "asm/arch/errno.h"
-
-#endif
diff --git a/include/asm-um/fcntl.h b/include/asm-um/fcntl.h
deleted file mode 100644
index 812a65446d92..000000000000
--- a/include/asm-um/fcntl.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_FCNTL_H
-#define __UM_FCNTL_H
-
-#include "asm/arch/fcntl.h"
-
-#endif
diff --git a/include/asm-um/fixmap.h b/include/asm-um/fixmap.h
deleted file mode 100644
index 9d2be52b8655..000000000000
--- a/include/asm-um/fixmap.h
+++ /dev/null
@@ -1,98 +0,0 @@
-#ifndef __UM_FIXMAP_H
-#define __UM_FIXMAP_H
-
-#include <asm/processor.h>
-#include <asm/system.h>
-#include <asm/kmap_types.h>
-#include <asm/archparam.h>
-#include <asm/page.h>
-
-/*
- * Here we define all the compile-time 'special' virtual
- * addresses. The point is to have a constant address at
- * compile time, but to set the physical address only
- * in the boot process. We allocate these special  addresses
- * from the end of virtual memory (0xfffff000) backwards.
- * Also this lets us do fail-safe vmalloc(), we
- * can guarantee that these special addresses and
- * vmalloc()-ed addresses never overlap.
- *
- * these 'compile-time allocated' memory buffers are
- * fixed-size 4k pages. (or larger if used with an increment
- * highger than 1) use fixmap_set(idx,phys) to associate
- * physical memory with fixmap indices.
- *
- * TLB entries of such buffers will not be flushed across
- * task switches.
- */
-
-/*
- * on UP currently we will have no trace of the fixmap mechanizm,
- * no page table allocations, etc. This might change in the
- * future, say framebuffers for the console driver(s) could be
- * fix-mapped?
- */
-enum fixed_addresses {
-#ifdef CONFIG_HIGHMEM
-	FIX_KMAP_BEGIN,	/* reserved pte's for temporary kernel mappings */
-	FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
-#endif
-	__end_of_fixed_addresses
-};
-
-extern void __set_fixmap (enum fixed_addresses idx,
-			  unsigned long phys, pgprot_t flags);
-
-#define set_fixmap(idx, phys) \
-		__set_fixmap(idx, phys, PAGE_KERNEL)
-/*
- * Some hardware wants to get fixmapped without caching.
- */
-#define set_fixmap_nocache(idx, phys) \
-		__set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
-/*
- * used by vmalloc.c.
- *
- * Leave one empty page between vmalloc'ed areas and
- * the start of the fixmap, and leave one page empty
- * at the top of mem..
- */
-
-#define FIXADDR_TOP	(TASK_SIZE - 2 * PAGE_SIZE)
-#define FIXADDR_SIZE	(__end_of_fixed_addresses << PAGE_SHIFT)
-#define FIXADDR_START	(FIXADDR_TOP - FIXADDR_SIZE)
-
-#define __fix_to_virt(x)	(FIXADDR_TOP - ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x)      ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
-
-extern void __this_fixmap_does_not_exist(void);
-
-/*
- * 'index to address' translation. If anyone tries to use the idx
- * directly without tranlation, we catch the bug with a NULL-deference
- * kernel oops. Illegal ranges of incoming indices are caught too.
- */
-static inline unsigned long fix_to_virt(const unsigned int idx)
-{
-	/*
-	 * this branch gets completely eliminated after inlining,
-	 * except when someone tries to use fixaddr indices in an
-	 * illegal way. (such as mixing up address types or using
-	 * out-of-range indices).
-	 *
-	 * If it doesn't get removed, the linker will complain
-	 * loudly with a reasonably clear error message..
-	 */
-	if (idx >= __end_of_fixed_addresses)
-		__this_fixmap_does_not_exist();
-
-        return __fix_to_virt(idx);
-}
-
-static inline unsigned long virt_to_fix(const unsigned long vaddr)
-{
-      BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
-      return __virt_to_fix(vaddr);
-}
-
-#endif
diff --git a/include/asm-um/floppy.h b/include/asm-um/floppy.h
deleted file mode 100644
index 453e7415fb6f..000000000000
--- a/include/asm-um/floppy.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_FLOPPY_H
-#define __UM_FLOPPY_H
-
-#include "asm/arch/floppy.h"
-
-#endif
diff --git a/include/asm-um/frame.h b/include/asm-um/frame.h
deleted file mode 100644
index 8a8c1cb415b4..000000000000
--- a/include/asm-um/frame.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_FRAME_I
-#define __UM_FRAME_I
-
-#include "asm/arch/frame.h"
-
-#endif
diff --git a/include/asm-um/futex.h b/include/asm-um/futex.h
deleted file mode 100644
index 6a332a9f099c..000000000000
--- a/include/asm-um/futex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
-
-#include <asm-generic/futex.h>
-
-#endif
diff --git a/include/asm-um/hardirq.h b/include/asm-um/hardirq.h
deleted file mode 100644
index 313ebb8a2566..000000000000
--- a/include/asm-um/hardirq.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* (c) 2004 cw@f00f.org, GPLv2 blah blah */
-
-#ifndef __ASM_UM_HARDIRQ_H
-#define __ASM_UM_HARDIRQ_H
-
-#include <linux/threads.h>
-#include <linux/irq.h>
-
-/* NOTE: When SMP works again we might want to make this
- * ____cacheline_aligned or maybe use per_cpu state? --cw */
-typedef struct {
-	unsigned int __softirq_pending;
-} irq_cpustat_t;
-
-#include <linux/irq_cpustat.h>
-
-/* As this would be very strange for UML to get we BUG() after the
- * printk. */
-static inline void ack_bad_irq(unsigned int irq)
-{
-	printk(KERN_ERR "unexpected IRQ %02x\n", irq);
-	BUG();
-}
-
-#endif /* __ASM_UM_HARDIRQ_H */
diff --git a/include/asm-um/highmem.h b/include/asm-um/highmem.h
deleted file mode 100644
index 36974cb8abc7..000000000000
--- a/include/asm-um/highmem.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __UM_HIGHMEM_H
-#define __UM_HIGHMEM_H
-
-#include "asm/page.h"
-#include "asm/fixmap.h"
-#include "asm/arch/highmem.h"
-
-#undef PKMAP_BASE
-
-#define PKMAP_BASE ((FIXADDR_START - LAST_PKMAP * PAGE_SIZE) & PMD_MASK)
-
-#endif
diff --git a/include/asm-um/host_ldt-i386.h b/include/asm-um/host_ldt-i386.h
deleted file mode 100644
index b27cb0a9dd30..000000000000
--- a/include/asm-um/host_ldt-i386.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef __ASM_HOST_LDT_I386_H
-#define __ASM_HOST_LDT_I386_H
-
-#include "asm/arch/ldt.h"
-
-/*
- * macros stolen from include/asm-i386/desc.h
- */
-#define LDT_entry_a(info) \
-	((((info)->base_addr & 0x0000ffff) << 16) | ((info)->limit & 0x0ffff))
-
-#define LDT_entry_b(info) \
-	(((info)->base_addr & 0xff000000) | \
-	(((info)->base_addr & 0x00ff0000) >> 16) | \
-	((info)->limit & 0xf0000) | \
-	(((info)->read_exec_only ^ 1) << 9) | \
-	((info)->contents << 10) | \
-	(((info)->seg_not_present ^ 1) << 15) | \
-	((info)->seg_32bit << 22) | \
-	((info)->limit_in_pages << 23) | \
-	((info)->useable << 20) | \
-	0x7000)
-
-#define LDT_empty(info) (\
-	(info)->base_addr	== 0	&& \
-	(info)->limit		== 0	&& \
-	(info)->contents	== 0	&& \
-	(info)->read_exec_only	== 1	&& \
-	(info)->seg_32bit	== 0	&& \
-	(info)->limit_in_pages	== 0	&& \
-	(info)->seg_not_present	== 1	&& \
-	(info)->useable		== 0	)
-
-#endif
diff --git a/include/asm-um/host_ldt-x86_64.h b/include/asm-um/host_ldt-x86_64.h
deleted file mode 100644
index 74a63f7d9a90..000000000000
--- a/include/asm-um/host_ldt-x86_64.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef __ASM_HOST_LDT_X86_64_H
-#define __ASM_HOST_LDT_X86_64_H
-
-#include "asm/arch/ldt.h"
-
-/*
- * macros stolen from include/asm-x86_64/desc.h
- */
-#define LDT_entry_a(info) \
-	((((info)->base_addr & 0x0000ffff) << 16) | ((info)->limit & 0x0ffff))
-
-/* Don't allow setting of the lm bit. It is useless anyways because
- * 64bit system calls require __USER_CS. */
-#define LDT_entry_b(info) \
-	(((info)->base_addr & 0xff000000) | \
-	(((info)->base_addr & 0x00ff0000) >> 16) | \
-	((info)->limit & 0xf0000) | \
-	(((info)->read_exec_only ^ 1) << 9) | \
-	((info)->contents << 10) | \
-	(((info)->seg_not_present ^ 1) << 15) | \
-	((info)->seg_32bit << 22) | \
-	((info)->limit_in_pages << 23) | \
-	((info)->useable << 20) | \
-	/* ((info)->lm << 21) | */ \
-	0x7000)
-
-#define LDT_empty(info) (\
-	(info)->base_addr	== 0	&& \
-	(info)->limit		== 0	&& \
-	(info)->contents	== 0	&& \
-	(info)->read_exec_only	== 1	&& \
-	(info)->seg_32bit	== 0	&& \
-	(info)->limit_in_pages	== 0	&& \
-	(info)->seg_not_present	== 1	&& \
-	(info)->useable		== 0	&& \
-	(info)->lm              == 0)
-
-#endif
diff --git a/include/asm-um/hw_irq.h b/include/asm-um/hw_irq.h
deleted file mode 100644
index 1cf84cf5f21a..000000000000
--- a/include/asm-um/hw_irq.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _ASM_UM_HW_IRQ_H
-#define _ASM_UM_HW_IRQ_H
-
-#include "asm/irq.h"
-#include "asm/archparam.h"
-
-#endif
diff --git a/include/asm-um/ide.h b/include/asm-um/ide.h
deleted file mode 100644
index 3d1ccebcfbaf..000000000000
--- a/include/asm-um/ide.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_IDE_H
-#define __UM_IDE_H
-
-#include "asm/arch/ide.h"
-
-#endif
diff --git a/include/asm-um/io.h b/include/asm-um/io.h
deleted file mode 100644
index 44e8b8c772ae..000000000000
--- a/include/asm-um/io.h
+++ /dev/null
@@ -1,57 +0,0 @@
-#ifndef __UM_IO_H
-#define __UM_IO_H
-
-#include "asm/page.h"
-
-#define IO_SPACE_LIMIT 0xdeadbeef /* Sure hope nothing uses this */
-
-static inline int inb(unsigned long i) { return(0); }
-static inline void outb(char c, unsigned long i) { }
-
-/*
- * Change virtual addresses to physical addresses and vv.
- * These are pretty trivial
- */
-static inline unsigned long virt_to_phys(volatile void * address)
-{
-	return __pa((void *) address);
-}
-
-static inline void * phys_to_virt(unsigned long address)
-{
-	return __va(address);
-}
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)	__va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)	p
-
-static inline void writeb(unsigned char b, volatile void __iomem *addr)
-{
-	*(volatile unsigned char __force *) addr = b;
-}
-static inline void writew(unsigned short b, volatile void __iomem *addr)
-{
-	*(volatile unsigned short __force *) addr = b;
-}
-static inline void writel(unsigned int b, volatile void __iomem *addr)
-{
-	*(volatile unsigned int __force *) addr = b;
-}
-static inline void writeq(unsigned int b, volatile void __iomem *addr)
-{
-	*(volatile unsigned long long __force *) addr = b;
-}
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-#define __raw_writeq writeq
-
-#endif
diff --git a/include/asm-um/ioctl.h b/include/asm-um/ioctl.h
deleted file mode 100644
index cc22157346db..000000000000
--- a/include/asm-um/ioctl.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_IOCTL_H
-#define __UM_IOCTL_H
-
-#include "asm/arch/ioctl.h"
-
-#endif
diff --git a/include/asm-um/ioctls.h b/include/asm-um/ioctls.h
deleted file mode 100644
index 9a1a017de6a7..000000000000
--- a/include/asm-um/ioctls.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_IOCTLS_H
-#define __UM_IOCTLS_H
-
-#include "asm/arch/ioctls.h"
-
-#endif
diff --git a/include/asm-um/ipcbuf.h b/include/asm-um/ipcbuf.h
deleted file mode 100644
index bb2ad31dc434..000000000000
--- a/include/asm-um/ipcbuf.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_IPCBUF_H
-#define __UM_IPCBUF_H
-
-#include "asm/arch/ipcbuf.h"
-
-#endif
diff --git a/include/asm-um/irq.h b/include/asm-um/irq.h
deleted file mode 100644
index 4a2037f8204b..000000000000
--- a/include/asm-um/irq.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef __UM_IRQ_H
-#define __UM_IRQ_H
-
-#define TIMER_IRQ		0
-#define UMN_IRQ			1
-#define CONSOLE_IRQ		2
-#define CONSOLE_WRITE_IRQ	3
-#define UBD_IRQ			4
-#define UM_ETH_IRQ		5
-#define SSL_IRQ			6
-#define SSL_WRITE_IRQ		7
-#define ACCEPT_IRQ		8
-#define MCONSOLE_IRQ		9
-#define WINCH_IRQ		10
-#define SIGIO_WRITE_IRQ 	11
-#define TELNETD_IRQ 		12
-#define XTERM_IRQ 		13
-#define RANDOM_IRQ 		14
-
-#define LAST_IRQ RANDOM_IRQ
-#define NR_IRQS (LAST_IRQ + 1)
-
-#endif
diff --git a/include/asm-um/irq_regs.h b/include/asm-um/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/include/asm-um/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/include/asm-um/irq_vectors.h b/include/asm-um/irq_vectors.h
deleted file mode 100644
index 62ddba6fc733..000000000000
--- a/include/asm-um/irq_vectors.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* 
- * Copyright (C) 2002 Jeff Dike (jdike@karaya.com)
- * Licensed under the GPL
- */
-
-#ifndef __UM_IRQ_VECTORS_H
-#define __UM_IRQ_VECTORS_H
-
-#endif
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff --git a/include/asm-um/irqflags.h b/include/asm-um/irqflags.h
deleted file mode 100644
index 659b9abdfdba..000000000000
--- a/include/asm-um/irqflags.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_IRQFLAGS_H
-#define __UM_IRQFLAGS_H
-
-/* Empty for now */
-
-#endif
diff --git a/include/asm-um/kdebug.h b/include/asm-um/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/include/asm-um/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/include/asm-um/kmap_types.h b/include/asm-um/kmap_types.h
deleted file mode 100644
index 6c03acdb4405..000000000000
--- a/include/asm-um/kmap_types.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* 
- * Copyright (C) 2002 Jeff Dike (jdike@karaya.com)
- * Licensed under the GPL
- */
-
-#ifndef __UM_KMAP_TYPES_H
-#define __UM_KMAP_TYPES_H
-
-/* No more #include "asm/arch/kmap_types.h" ! */
-
-enum km_type {
-	KM_BOUNCE_READ,
-	KM_SKB_SUNRPC_DATA,
-	KM_SKB_DATA_SOFTIRQ,
-	KM_USER0,
-	KM_USER1,
-	KM_UML_USERCOPY,	/* UML specific, for copy_*_user - used in do_op_one_page */
-	KM_BIO_SRC_IRQ,
-	KM_BIO_DST_IRQ,
-	KM_PTE0,
-	KM_PTE1,
-	KM_IRQ0,
-	KM_IRQ1,
-	KM_SOFTIRQ0,
-	KM_SOFTIRQ1,
-	KM_TYPE_NR
-};
-
-#endif
diff --git a/include/asm-um/ldt.h b/include/asm-um/ldt.h
deleted file mode 100644
index 52af512f5e7d..000000000000
--- a/include/asm-um/ldt.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2004 Fujitsu Siemens Computers GmbH
- * Licensed under the GPL
- *
- * Author: Bodo Stroesser <bstroesser@fujitsu-siemens.com>
- */
-
-#ifndef __ASM_LDT_H
-#define __ASM_LDT_H
-
-#include <linux/mutex.h>
-#include "asm/host_ldt.h"
-
-extern void ldt_host_info(void);
-
-#define LDT_PAGES_MAX \
-	((LDT_ENTRIES * LDT_ENTRY_SIZE)/PAGE_SIZE)
-#define LDT_ENTRIES_PER_PAGE \
-	(PAGE_SIZE/LDT_ENTRY_SIZE)
-#define LDT_DIRECT_ENTRIES \
-	((LDT_PAGES_MAX*sizeof(void *))/LDT_ENTRY_SIZE)
-
-struct ldt_entry {
-	__u32 a;
-	__u32 b;
-};
-
-typedef struct uml_ldt {
-	int entry_count;
-	struct mutex lock;
-	union {
-		struct ldt_entry * pages[LDT_PAGES_MAX];
-		struct ldt_entry entries[LDT_DIRECT_ENTRIES];
-	} u;
-} uml_ldt_t;
-
-#endif
diff --git a/include/asm-um/linkage.h b/include/asm-um/linkage.h
deleted file mode 100644
index 7dfce37adc8b..000000000000
--- a/include/asm-um/linkage.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_UM_LINKAGE_H
-#define __ASM_UM_LINKAGE_H
-
-#include "asm/arch/linkage.h"
-
-#endif
diff --git a/include/asm-um/local.h b/include/asm-um/local.h
deleted file mode 100644
index 9a280c5bb609..000000000000
--- a/include/asm-um/local.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_LOCAL_H
-#define __UM_LOCAL_H
-
-#include "asm/arch/local.h"
-
-#endif
diff --git a/include/asm-um/locks.h b/include/asm-um/locks.h
deleted file mode 100644
index f80030a3ef5a..000000000000
--- a/include/asm-um/locks.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_LOCKS_H
-#define __UM_LOCKS_H
-
-#include "asm/arch/locks.h"
-
-#endif
diff --git a/include/asm-um/mca_dma.h b/include/asm-um/mca_dma.h
deleted file mode 100644
index e492e4ec1392..000000000000
--- a/include/asm-um/mca_dma.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef mca___UM_DMA_H
-#define mca___UM_DMA_H
-
-#include "asm/arch/mca_dma.h"
-
-#endif
diff --git a/include/asm-um/mman.h b/include/asm-um/mman.h
deleted file mode 100644
index b09ed523019b..000000000000
--- a/include/asm-um/mman.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_MMAN_H
-#define __UM_MMAN_H
-
-#include "asm/arch/mman.h"
-
-#endif
diff --git a/include/asm-um/mmu.h b/include/asm-um/mmu.h
deleted file mode 100644
index 2cf35c21d694..000000000000
--- a/include/asm-um/mmu.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* 
- * Copyright (C) 2002 Jeff Dike (jdike@karaya.com)
- * Licensed under the GPL
- */
-
-#ifndef __MMU_H
-#define __MMU_H
-
-#include "um_mmu.h"
-
-#endif
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff --git a/include/asm-um/mmu_context.h b/include/asm-um/mmu_context.h
deleted file mode 100644
index 54f42e8b0105..000000000000
--- a/include/asm-um/mmu_context.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* 
- * Copyright (C) 2002 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-
-#ifndef __UM_MMU_CONTEXT_H
-#define __UM_MMU_CONTEXT_H
-
-#include "linux/sched.h"
-#include "um_mmu.h"
-
-extern void arch_dup_mmap(struct mm_struct *oldmm, struct mm_struct *mm);
-extern void arch_exit_mmap(struct mm_struct *mm);
-
-#define get_mmu_context(task) do ; while(0)
-#define activate_context(tsk) do ; while(0)
-
-#define deactivate_mm(tsk,mm)	do { } while (0)
-
-extern void force_flush_all(void);
-
-static inline void activate_mm(struct mm_struct *old, struct mm_struct *new)
-{
-	/*
-	 * This is called by fs/exec.c and sys_unshare()
-	 * when the new ->mm is used for the first time.
-	 */
-	__switch_mm(&new->context.id);
-	arch_dup_mmap(old, new);
-}
-
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 
-			     struct task_struct *tsk)
-{
-	unsigned cpu = smp_processor_id();
-
-	if(prev != next){
-		cpu_clear(cpu, prev->cpu_vm_mask);
-		cpu_set(cpu, next->cpu_vm_mask);
-		if(next != &init_mm)
-			__switch_mm(&next->context.id);
-	}
-}
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, 
-				  struct task_struct *tsk)
-{
-}
-
-extern int init_new_context(struct task_struct *task, struct mm_struct *mm);
-
-extern void destroy_context(struct mm_struct *mm);
-
-#endif
diff --git a/include/asm-um/module-generic.h b/include/asm-um/module-generic.h
deleted file mode 100644
index 5a265f56b174..000000000000
--- a/include/asm-um/module-generic.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_MODULE_GENERIC_H
-#define __UM_MODULE_GENERIC_H
-
-#include "asm/arch/module.h"
-
-#endif
diff --git a/include/asm-um/module-i386.h b/include/asm-um/module-i386.h
deleted file mode 100644
index 5ead4a0b2e35..000000000000
--- a/include/asm-um/module-i386.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __UM_MODULE_I386_H
-#define __UM_MODULE_I386_H
-
-/* UML is simple */
-struct mod_arch_specific
-{
-};
-
-#define Elf_Shdr Elf32_Shdr
-#define Elf_Sym Elf32_Sym
-#define Elf_Ehdr Elf32_Ehdr
-
-#endif
diff --git a/include/asm-um/module-x86_64.h b/include/asm-um/module-x86_64.h
deleted file mode 100644
index 35b5491d3e96..000000000000
--- a/include/asm-um/module-x86_64.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright 2003 PathScale, Inc.
- *
- * Licensed under the GPL
- */
-
-#ifndef __UM_MODULE_X86_64_H
-#define __UM_MODULE_X86_64_H
-
-/* UML is simple */
-struct mod_arch_specific
-{
-};
-
-#define Elf_Shdr Elf64_Shdr
-#define Elf_Sym Elf64_Sym
-#define Elf_Ehdr Elf64_Ehdr
-
-#endif
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff --git a/include/asm-um/msgbuf.h b/include/asm-um/msgbuf.h
deleted file mode 100644
index 8ce8c30d5377..000000000000
--- a/include/asm-um/msgbuf.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_MSGBUF_H
-#define __UM_MSGBUF_H
-
-#include "asm/arch/msgbuf.h"
-
-#endif
diff --git a/include/asm-um/mtrr.h b/include/asm-um/mtrr.h
deleted file mode 100644
index 5e9cd12c578d..000000000000
--- a/include/asm-um/mtrr.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_MTRR_H
-#define __UM_MTRR_H
-
-#include "asm/arch/mtrr.h"
-
-#endif
diff --git a/include/asm-um/mutex.h b/include/asm-um/mutex.h
deleted file mode 100644
index 458c1f7fbc18..000000000000
--- a/include/asm-um/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Pull in the generic implementation for the mutex fastpath.
- *
- * TODO: implement optimized primitives instead, or leave the generic
- * implementation in place, or pick the atomic_xchg() based generic
- * implementation. (see asm-generic/mutex-xchg.h for details)
- */
-
-#include <asm-generic/mutex-dec.h>
diff --git a/include/asm-um/nops.h b/include/asm-um/nops.h
deleted file mode 100644
index 814e9bf5dea6..000000000000
--- a/include/asm-um/nops.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_NOPS_H
-#define __UM_NOPS_H
-
-#include "asm/arch/nops.h"
-
-#endif
diff --git a/include/asm-um/page.h b/include/asm-um/page.h
deleted file mode 100644
index a6df1f13d732..000000000000
--- a/include/asm-um/page.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright (C) 2000 - 2003 Jeff Dike (jdike@addtoit.com)
- * Copyright 2003 PathScale, Inc.
- * Licensed under the GPL
- */
-
-#ifndef __UM_PAGE_H
-#define __UM_PAGE_H
-
-#include <linux/const.h>
-
-/* PAGE_SHIFT determines the page size */
-#define PAGE_SHIFT	12
-#define PAGE_SIZE	(_AC(1, UL) << PAGE_SHIFT)
-#define PAGE_MASK	(~(PAGE_SIZE-1))
-
-#ifndef __ASSEMBLY__
-
-struct page;
-
-#include <linux/types.h>
-#include <asm/vm-flags.h>
-
-/*
- * These are used to make use of C type-checking..
- */
-
-#define clear_page(page)	memset((void *)(page), 0, PAGE_SIZE)
-#define copy_page(to,from)	memcpy((void *)(to), (void *)(from), PAGE_SIZE)
-
-#define clear_user_page(page, vaddr, pg)	clear_page(page)
-#define copy_user_page(to, from, vaddr, pg)	copy_page(to, from)
-
-#if defined(CONFIG_3_LEVEL_PGTABLES) && !defined(CONFIG_64BIT)
-
-typedef struct { unsigned long pte_low, pte_high; } pte_t;
-typedef struct { unsigned long pmd; } pmd_t;
-typedef struct { unsigned long pgd; } pgd_t;
-#define pte_val(x) ((x).pte_low | ((unsigned long long) (x).pte_high << 32))
-
-#define pte_get_bits(pte, bits) ((pte).pte_low & (bits))
-#define pte_set_bits(pte, bits) ((pte).pte_low |= (bits))
-#define pte_clear_bits(pte, bits) ((pte).pte_low &= ~(bits))
-#define pte_copy(to, from) ({ (to).pte_high = (from).pte_high; \
-			      smp_wmb(); \
-			      (to).pte_low = (from).pte_low; })
-#define pte_is_zero(pte) (!((pte).pte_low & ~_PAGE_NEWPAGE) && !(pte).pte_high)
-#define pte_set_val(pte, phys, prot) \
-	({ (pte).pte_high = (phys) >> 32; \
-	   (pte).pte_low = (phys) | pgprot_val(prot); })
-
-#define pmd_val(x)	((x).pmd)
-#define __pmd(x) ((pmd_t) { (x) } )
-
-typedef unsigned long long pfn_t;
-typedef unsigned long long phys_t;
-
-#else
-
-typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long pgd; } pgd_t;
-
-#ifdef CONFIG_3_LEVEL_PGTABLES
-typedef struct { unsigned long pmd; } pmd_t;
-#define pmd_val(x)	((x).pmd)
-#define __pmd(x) ((pmd_t) { (x) } )
-#endif
-
-#define pte_val(x)	((x).pte)
-
-
-#define pte_get_bits(p, bits) ((p).pte & (bits))
-#define pte_set_bits(p, bits) ((p).pte |= (bits))
-#define pte_clear_bits(p, bits) ((p).pte &= ~(bits))
-#define pte_copy(to, from) ((to).pte = (from).pte)
-#define pte_is_zero(p) (!((p).pte & ~_PAGE_NEWPAGE))
-#define pte_set_val(p, phys, prot) (p).pte = (phys | pgprot_val(prot))
-
-typedef unsigned long pfn_t;
-typedef unsigned long phys_t;
-
-#endif
-
-typedef struct { unsigned long pgprot; } pgprot_t;
-
-typedef struct page *pgtable_t;
-
-#define pgd_val(x)	((x).pgd)
-#define pgprot_val(x)	((x).pgprot)
-
-#define __pte(x) ((pte_t) { (x) } )
-#define __pgd(x) ((pgd_t) { (x) } )
-#define __pgprot(x)	((pgprot_t) { (x) } )
-
-extern unsigned long uml_physmem;
-
-#define PAGE_OFFSET (uml_physmem)
-#define KERNELBASE PAGE_OFFSET
-
-#define __va_space (8*1024*1024)
-
-#include "mem.h"
-
-/* Cast to unsigned long before casting to void * to avoid a warning from
- * mmap_kmem about cutting a long long down to a void *.  Not sure that
- * casting is the right thing, but 32-bit UML can't have 64-bit virtual
- * addresses
- */
-#define __pa(virt) to_phys((void *) (unsigned long) (virt))
-#define __va(phys) to_virt((unsigned long) (phys))
-
-#define phys_to_pfn(p) ((pfn_t) ((p) >> PAGE_SHIFT))
-#define pfn_to_phys(pfn) ((phys_t) ((pfn) << PAGE_SHIFT))
-
-#define pfn_valid(pfn) ((pfn) < max_mapnr)
-#define virt_addr_valid(v) pfn_valid(phys_to_pfn(__pa(v)))
-
-#include <asm-generic/memory_model.h>
-#include <asm-generic/page.h>
-
-#endif	/* __ASSEMBLY__ */
-#endif	/* __UM_PAGE_H */
diff --git a/include/asm-um/page_offset.h b/include/asm-um/page_offset.h
deleted file mode 100644
index 1c168dfbf359..000000000000
--- a/include/asm-um/page_offset.h
+++ /dev/null
@@ -1 +0,0 @@
-#define PAGE_OFFSET_RAW (uml_physmem)
diff --git a/include/asm-um/param.h b/include/asm-um/param.h
deleted file mode 100644
index e44f4e60d16d..000000000000
--- a/include/asm-um/param.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _UM_PARAM_H
-#define _UM_PARAM_H
-
-#define EXEC_PAGESIZE   4096
-
-#ifndef NOGROUP
-#define NOGROUP         (-1)
-#endif
-
-#define MAXHOSTNAMELEN  64      /* max length of hostname */
-
-#ifdef __KERNEL__
-#define HZ CONFIG_HZ
-#define USER_HZ	100	   /* .. some user interfaces are in "ticks" */
-#define CLOCKS_PER_SEC (USER_HZ)  /* frequency at which times() counts */
-#else
-#define HZ 100
-#endif
-
-#endif
diff --git a/include/asm-um/paravirt.h b/include/asm-um/paravirt.h
deleted file mode 100644
index 9d6aaad80b5f..000000000000
--- a/include/asm-um/paravirt.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_PARAVIRT_H
-#define __UM_PARAVIRT_H
-
-#include "asm/arch/paravirt.h"
-
-#endif
diff --git a/include/asm-um/pci.h b/include/asm-um/pci.h
deleted file mode 100644
index 59923199cdc3..000000000000
--- a/include/asm-um/pci.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __UM_PCI_H
-#define __UM_PCI_H
-
-#define PCI_DMA_BUS_IS_PHYS     (1)
-#define pcibios_scan_all_fns(a, b)	0
-
-#endif
diff --git a/include/asm-um/pda.h b/include/asm-um/pda.h
deleted file mode 100644
index 0d8bf33ffd42..000000000000
--- a/include/asm-um/pda.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2003 PathScale, Inc.
- *
- * Licensed under the GPL
- */
-
-#ifndef __UM_PDA_X86_64_H
-#define __UM_PDA_X86_64_H
-
-/* XXX */
-struct foo {
-	unsigned int __softirq_pending;
-	unsigned int __nmi_count;
-};
-
-extern struct foo me;
-
-#define read_pda(me) (&me)
-
-#endif
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff --git a/include/asm-um/percpu.h b/include/asm-um/percpu.h
deleted file mode 100644
index 5723e2aab8e7..000000000000
--- a/include/asm-um/percpu.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_PERCPU_H
-#define __UM_PERCPU_H
-
-#include "asm/arch/percpu.h"
-
-#endif
diff --git a/include/asm-um/pgalloc.h b/include/asm-um/pgalloc.h
deleted file mode 100644
index 9062a6e72241..000000000000
--- a/include/asm-um/pgalloc.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* 
- * Copyright (C) 2000, 2001, 2002 Jeff Dike (jdike@karaya.com)
- * Copyright 2003 PathScale, Inc.
- * Derived from include/asm-i386/pgalloc.h and include/asm-i386/pgtable.h
- * Licensed under the GPL
- */
-
-#ifndef __UM_PGALLOC_H
-#define __UM_PGALLOC_H
-
-#include "linux/mm.h"
-#include "asm/fixmap.h"
-
-#define pmd_populate_kernel(mm, pmd, pte) \
-	set_pmd(pmd, __pmd(_PAGE_TABLE + (unsigned long) __pa(pte)))
-
-#define pmd_populate(mm, pmd, pte) 				\
-	set_pmd(pmd, __pmd(_PAGE_TABLE +			\
-		((unsigned long long)page_to_pfn(pte) <<	\
-			(unsigned long long) PAGE_SHIFT)))
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-/*
- * Allocate and free page tables.
- */
-extern pgd_t *pgd_alloc(struct mm_struct *);
-extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
-
-extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long);
-extern pgtable_t pte_alloc_one(struct mm_struct *, unsigned long);
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
-	free_page((unsigned long) pte);
-}
-
-static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
-{
-	pgtable_page_dtor(pte);
-	__free_page(pte);
-}
-
-#define __pte_free_tlb(tlb,pte)				\
-do {							\
-	pgtable_page_dtor(pte);				\
-	tlb_remove_page((tlb),(pte));			\
-} while (0)
-
-#ifdef CONFIG_3_LEVEL_PGTABLES
-
-static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
-{
-	free_page((unsigned long)pmd);
-}
-
-#define __pmd_free_tlb(tlb,x)   tlb_remove_page((tlb),virt_to_page(x))
-#endif
-
-#define check_pgt_cache()	do { } while (0)
-
-#endif
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff --git a/include/asm-um/pgtable-2level.h b/include/asm-um/pgtable-2level.h
deleted file mode 100644
index f534b73e753e..000000000000
--- a/include/asm-um/pgtable-2level.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (C) 2000, 2001, 2002 Jeff Dike (jdike@karaya.com)
- * Copyright 2003 PathScale, Inc.
- * Derived from include/asm-i386/pgtable.h
- * Licensed under the GPL
- */
-
-#ifndef __UM_PGTABLE_2LEVEL_H
-#define __UM_PGTABLE_2LEVEL_H
-
-#include <asm-generic/pgtable-nopmd.h>
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-
-#define PGDIR_SHIFT	22
-#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
-#define PGDIR_MASK	(~(PGDIR_SIZE-1))
-
-/*
- * entries per page directory level: the i386 is two-level, so
- * we don't really have any PMD directory physically.
- */
-#define PTRS_PER_PTE	1024
-#define USER_PTRS_PER_PGD ((TASK_SIZE + (PGDIR_SIZE - 1)) / PGDIR_SIZE)
-#define PTRS_PER_PGD	1024
-#define FIRST_USER_ADDRESS	0
-
-#define pte_ERROR(e) \
-        printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), \
-	       pte_val(e))
-#define pgd_ERROR(e) \
-        printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), \
-	       pgd_val(e))
-
-static inline int pgd_newpage(pgd_t pgd)	{ return 0; }
-static inline void pgd_mkuptodate(pgd_t pgd)	{ }
-
-#define set_pmd(pmdptr, pmdval) (*(pmdptr) = (pmdval))
-
-#define pte_pfn(x) phys_to_pfn(pte_val(x))
-#define pfn_pte(pfn, prot) __pte(pfn_to_phys(pfn) | pgprot_val(prot))
-#define pfn_pmd(pfn, prot) __pmd(pfn_to_phys(pfn) | pgprot_val(prot))
-
-/*
- * Bits 0 through 4 are taken
- */
-#define PTE_FILE_MAX_BITS	27
-
-#define pte_to_pgoff(pte) (pte_val(pte) >> 5)
-
-#define pgoff_to_pte(off) ((pte_t) { ((off) << 5) + _PAGE_FILE })
-
-#endif
diff --git a/include/asm-um/pgtable-3level.h b/include/asm-um/pgtable-3level.h
deleted file mode 100644
index 0446f456b428..000000000000
--- a/include/asm-um/pgtable-3level.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Copyright 2003 PathScale Inc
- * Derived from include/asm-i386/pgtable.h
- * Licensed under the GPL
- */
-
-#ifndef __UM_PGTABLE_3LEVEL_H
-#define __UM_PGTABLE_3LEVEL_H
-
-#include <asm-generic/pgtable-nopud.h>
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-
-#ifdef CONFIG_64BIT
-#define PGDIR_SHIFT	30
-#else
-#define PGDIR_SHIFT	31
-#endif
-#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
-#define PGDIR_MASK	(~(PGDIR_SIZE-1))
-
-/* PMD_SHIFT determines the size of the area a second-level page table can
- * map
- */
-
-#define PMD_SHIFT	21
-#define PMD_SIZE	(1UL << PMD_SHIFT)
-#define PMD_MASK	(~(PMD_SIZE-1))
-
-/*
- * entries per page directory level
- */
-
-#define PTRS_PER_PTE 512
-#ifdef CONFIG_64BIT
-#define PTRS_PER_PMD 512
-#define PTRS_PER_PGD 512
-#else
-#define PTRS_PER_PMD 1024
-#define PTRS_PER_PGD 1024
-#endif
-
-#define USER_PTRS_PER_PGD ((TASK_SIZE + (PGDIR_SIZE - 1)) / PGDIR_SIZE)
-#define FIRST_USER_ADDRESS	0
-
-#define pte_ERROR(e) \
-        printk("%s:%d: bad pte %p(%016lx).\n", __FILE__, __LINE__, &(e), \
-	       pte_val(e))
-#define pmd_ERROR(e) \
-        printk("%s:%d: bad pmd %p(%016lx).\n", __FILE__, __LINE__, &(e), \
-	       pmd_val(e))
-#define pgd_ERROR(e) \
-        printk("%s:%d: bad pgd %p(%016lx).\n", __FILE__, __LINE__, &(e), \
-	       pgd_val(e))
-
-#define pud_none(x)	(!(pud_val(x) & ~_PAGE_NEWPAGE))
-#define	pud_bad(x)	((pud_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
-#define pud_present(x)	(pud_val(x) & _PAGE_PRESENT)
-#define pud_populate(mm, pud, pmd) \
-	set_pud(pud, __pud(_PAGE_TABLE + __pa(pmd)))
-
-#ifdef CONFIG_64BIT
-#define set_pud(pudptr, pudval) set_64bit((phys_t *) (pudptr), pud_val(pudval))
-#else
-#define set_pud(pudptr, pudval) (*(pudptr) = (pudval))
-#endif
-
-static inline int pgd_newpage(pgd_t pgd)
-{
-	return(pgd_val(pgd) & _PAGE_NEWPAGE);
-}
-
-static inline void pgd_mkuptodate(pgd_t pgd) { pgd_val(pgd) &= ~_PAGE_NEWPAGE; }
-
-#ifdef CONFIG_64BIT
-#define set_pmd(pmdptr, pmdval) set_64bit((phys_t *) (pmdptr), pmd_val(pmdval))
-#else
-#define set_pmd(pmdptr, pmdval) (*(pmdptr) = (pmdval))
-#endif
-
-struct mm_struct;
-extern pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address);
-
-static inline void pud_clear (pud_t *pud)
-{
-	set_pud(pud, __pud(_PAGE_NEWPAGE));
-}
-
-#define pud_page(pud) phys_to_page(pud_val(pud) & PAGE_MASK)
-#define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & PAGE_MASK))
-
-/* Find an entry in the second-level page table.. */
-#define pmd_offset(pud, address) ((pmd_t *) pud_page_vaddr(*(pud)) + \
-			pmd_index(address))
-
-static inline unsigned long pte_pfn(pte_t pte)
-{
-	return phys_to_pfn(pte_val(pte));
-}
-
-static inline pte_t pfn_pte(pfn_t page_nr, pgprot_t pgprot)
-{
-	pte_t pte;
-	phys_t phys = pfn_to_phys(page_nr);
-
-	pte_set_val(pte, phys, pgprot);
-	return pte;
-}
-
-static inline pmd_t pfn_pmd(pfn_t page_nr, pgprot_t pgprot)
-{
-	return __pmd((page_nr << PAGE_SHIFT) | pgprot_val(pgprot));
-}
-
-/*
- * Bits 0 through 3 are taken in the low part of the pte,
- * put the 32 bits of offset into the high part.
- */
-#define PTE_FILE_MAX_BITS	32
-
-#ifdef CONFIG_64BIT
-
-#define pte_to_pgoff(p) ((p).pte >> 32)
-
-#define pgoff_to_pte(off) ((pte_t) { ((off) << 32) | _PAGE_FILE })
-
-#else
-
-#define pte_to_pgoff(pte) ((pte).pte_high)
-
-#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
-
-#endif
-
-#endif
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff --git a/include/asm-um/pgtable.h b/include/asm-um/pgtable.h
deleted file mode 100644
index 02db81b7b86e..000000000000
--- a/include/asm-um/pgtable.h
+++ /dev/null
@@ -1,358 +0,0 @@
-/* 
- * Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Copyright 2003 PathScale, Inc.
- * Derived from include/asm-i386/pgtable.h
- * Licensed under the GPL
- */
-
-#ifndef __UM_PGTABLE_H
-#define __UM_PGTABLE_H
-
-#include <asm/fixmap.h>
-
-#define _PAGE_PRESENT	0x001
-#define _PAGE_NEWPAGE	0x002
-#define _PAGE_NEWPROT	0x004
-#define _PAGE_RW	0x020
-#define _PAGE_USER	0x040
-#define _PAGE_ACCESSED	0x080
-#define _PAGE_DIRTY	0x100
-/* If _PAGE_PRESENT is clear, we use these: */
-#define _PAGE_FILE	0x008	/* nonlinear file mapping, saved PTE; unset:swap */
-#define _PAGE_PROTNONE	0x010	/* if the user mapped it with PROT_NONE;
-				   pte_present gives true */
-
-#ifdef CONFIG_3_LEVEL_PGTABLES
-#include "asm/pgtable-3level.h"
-#else
-#include "asm/pgtable-2level.h"
-#endif
-
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
-
-/* zero page used for uninitialized stuff */
-extern unsigned long *empty_zero_page;
-
-#define pgtable_cache_init() do ; while (0)
-
-/* Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 8MB value just means that there will be a 8MB "hole" after the
- * physical memory until the kernel virtual memory starts.  That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- */
-
-extern unsigned long end_iomem;
-
-#define VMALLOC_OFFSET	(__va_space)
-#define VMALLOC_START ((end_iomem + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
-#ifdef CONFIG_HIGHMEM
-# define VMALLOC_END	(PKMAP_BASE-2*PAGE_SIZE)
-#else
-# define VMALLOC_END	(FIXADDR_START-2*PAGE_SIZE)
-#endif
-
-#define _PAGE_TABLE	(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
-#define _KERNPG_TABLE	(_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
-#define _PAGE_CHG_MASK	(PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
-
-#define PAGE_NONE	__pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
-#define PAGE_SHARED	__pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
-#define PAGE_COPY	__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
-#define PAGE_READONLY	__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
-#define PAGE_KERNEL	__pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
-
-/*
- * The i386 can't do page protection for execute, and considers that the same
- * are read.
- * Also, write permissions imply read permissions. This is the closest we can
- * get..
- */
-#define __P000	PAGE_NONE
-#define __P001	PAGE_READONLY
-#define __P010	PAGE_COPY
-#define __P011	PAGE_COPY
-#define __P100	PAGE_READONLY
-#define __P101	PAGE_READONLY
-#define __P110	PAGE_COPY
-#define __P111	PAGE_COPY
-
-#define __S000	PAGE_NONE
-#define __S001	PAGE_READONLY
-#define __S010	PAGE_SHARED
-#define __S011	PAGE_SHARED
-#define __S100	PAGE_READONLY
-#define __S101	PAGE_READONLY
-#define __S110	PAGE_SHARED
-#define __S111	PAGE_SHARED
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-#define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page)
-
-#define pte_clear(mm,addr,xp) pte_set_val(*(xp), (phys_t) 0, __pgprot(_PAGE_NEWPAGE))
-
-#define pmd_none(x)	(!((unsigned long)pmd_val(x) & ~_PAGE_NEWPAGE))
-#define	pmd_bad(x)	((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
-
-#define pmd_present(x)	(pmd_val(x) & _PAGE_PRESENT)
-#define pmd_clear(xp)	do { pmd_val(*(xp)) = _PAGE_NEWPAGE; } while (0)
-
-#define pmd_newpage(x)  (pmd_val(x) & _PAGE_NEWPAGE)
-#define pmd_mkuptodate(x) (pmd_val(x) &= ~_PAGE_NEWPAGE)
-
-#define pud_newpage(x)  (pud_val(x) & _PAGE_NEWPAGE)
-#define pud_mkuptodate(x) (pud_val(x) &= ~_PAGE_NEWPAGE)
-
-#define pmd_page(pmd) phys_to_page(pmd_val(pmd) & PAGE_MASK)
-
-#define pte_page(x) pfn_to_page(pte_pfn(x))
-
-#define pte_present(x)	pte_get_bits(x, (_PAGE_PRESENT | _PAGE_PROTNONE))
-
-/*
- * =================================
- * Flags checking section.
- * =================================
- */
-
-static inline int pte_none(pte_t pte)
-{
-	return pte_is_zero(pte);
-}
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-static inline int pte_read(pte_t pte)
-{ 
-	return((pte_get_bits(pte, _PAGE_USER)) &&
-	       !(pte_get_bits(pte, _PAGE_PROTNONE)));
-}
-
-static inline int pte_exec(pte_t pte){
-	return((pte_get_bits(pte, _PAGE_USER)) &&
-	       !(pte_get_bits(pte, _PAGE_PROTNONE)));
-}
-
-static inline int pte_write(pte_t pte)
-{
-	return((pte_get_bits(pte, _PAGE_RW)) &&
-	       !(pte_get_bits(pte, _PAGE_PROTNONE)));
-}
-
-/*
- * The following only works if pte_present() is not true.
- */
-static inline int pte_file(pte_t pte)
-{
-	return pte_get_bits(pte, _PAGE_FILE);
-}
-
-static inline int pte_dirty(pte_t pte)
-{
-	return pte_get_bits(pte, _PAGE_DIRTY);
-}
-
-static inline int pte_young(pte_t pte)
-{
-	return pte_get_bits(pte, _PAGE_ACCESSED);
-}
-
-static inline int pte_newpage(pte_t pte)
-{
-	return pte_get_bits(pte, _PAGE_NEWPAGE);
-}
-
-static inline int pte_newprot(pte_t pte)
-{ 
-	return(pte_present(pte) && (pte_get_bits(pte, _PAGE_NEWPROT)));
-}
-
-static inline int pte_special(pte_t pte)
-{
-	return 0;
-}
-
-/*
- * =================================
- * Flags setting section.
- * =================================
- */
-
-static inline pte_t pte_mknewprot(pte_t pte)
-{
-	pte_set_bits(pte, _PAGE_NEWPROT);
-	return(pte);
-}
-
-static inline pte_t pte_mkclean(pte_t pte)
-{
-	pte_clear_bits(pte, _PAGE_DIRTY);
-	return(pte);
-}
-
-static inline pte_t pte_mkold(pte_t pte)	
-{ 
-	pte_clear_bits(pte, _PAGE_ACCESSED);
-	return(pte);
-}
-
-static inline pte_t pte_wrprotect(pte_t pte)
-{ 
-	pte_clear_bits(pte, _PAGE_RW);
-	return(pte_mknewprot(pte)); 
-}
-
-static inline pte_t pte_mkread(pte_t pte)
-{ 
-	pte_set_bits(pte, _PAGE_USER);
-	return(pte_mknewprot(pte)); 
-}
-
-static inline pte_t pte_mkdirty(pte_t pte)
-{ 
-	pte_set_bits(pte, _PAGE_DIRTY);
-	return(pte);
-}
-
-static inline pte_t pte_mkyoung(pte_t pte)
-{
-	pte_set_bits(pte, _PAGE_ACCESSED);
-	return(pte);
-}
-
-static inline pte_t pte_mkwrite(pte_t pte)	
-{
-	pte_set_bits(pte, _PAGE_RW);
-	return(pte_mknewprot(pte)); 
-}
-
-static inline pte_t pte_mkuptodate(pte_t pte)	
-{
-	pte_clear_bits(pte, _PAGE_NEWPAGE);
-	if(pte_present(pte))
-		pte_clear_bits(pte, _PAGE_NEWPROT);
-	return(pte); 
-}
-
-static inline pte_t pte_mknewpage(pte_t pte)
-{
-	pte_set_bits(pte, _PAGE_NEWPAGE);
-	return(pte);
-}
-
-static inline pte_t pte_mkspecial(pte_t pte)
-{
-	return(pte);
-}
-
-static inline void set_pte(pte_t *pteptr, pte_t pteval)
-{
-	pte_copy(*pteptr, pteval);
-
-	/* If it's a swap entry, it needs to be marked _PAGE_NEWPAGE so
-	 * fix_range knows to unmap it.  _PAGE_NEWPROT is specific to
-	 * mapped pages.
-	 */
-
-	*pteptr = pte_mknewpage(*pteptr);
-	if(pte_present(*pteptr)) *pteptr = pte_mknewprot(*pteptr);
-}
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-
-#define phys_to_page(phys) pfn_to_page(phys_to_pfn(phys))
-#define __virt_to_page(virt) phys_to_page(__pa(virt))
-#define page_to_phys(page) pfn_to_phys((pfn_t) page_to_pfn(page))
-#define virt_to_page(addr) __virt_to_page((const unsigned long) addr)
-
-#define mk_pte(page, pgprot) \
-	({ pte_t pte;					\
-							\
-	pte_set_val(pte, page_to_phys(page), (pgprot));	\
-	if (pte_present(pte))				\
-		pte_mknewprot(pte_mknewpage(pte));	\
-	pte;})
-
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{
-	pte_set_val(pte, (pte_val(pte) & _PAGE_CHG_MASK), newprot);
-	return pte; 
-}
-
-/*
- * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
- *
- * this macro returns the index of the entry in the pgd page which would
- * control the given virtual address
- */
-#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
-
-/*
- * pgd_offset() returns a (pgd_t *)
- * pgd_index() is used get the offset into the pgd page's array of pgd_t's;
- */
-#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
-
-/*
- * a shortcut which implies the use of the kernel's pgd, instead
- * of a process's
- */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-/*
- * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD]
- *
- * this macro returns the index of the entry in the pmd page which would
- * control the given virtual address
- */
-#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
-#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
-
-#define pmd_page_vaddr(pmd) \
-	((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
-
-/*
- * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
- *
- * this macro returns the index of the entry in the pte page which would
- * control the given virtual address
- */
-#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#define pte_offset_kernel(dir, address) \
-	((pte_t *) pmd_page_vaddr(*(dir)) +  pte_index(address))
-#define pte_offset_map(dir, address) \
-	((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
-#define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
-#define pte_unmap(pte) do { } while (0)
-#define pte_unmap_nested(pte) do { } while (0)
-
-struct mm_struct;
-extern pte_t *virt_to_pte(struct mm_struct *mm, unsigned long addr);
-
-#define update_mmu_cache(vma,address,pte) do ; while (0)
-
-/* Encode and de-code a swap entry */
-#define __swp_type(x)			(((x).val >> 4) & 0x3f)
-#define __swp_offset(x)			((x).val >> 11)
-
-#define __swp_entry(type, offset) \
-	((swp_entry_t) { ((type) << 4) | ((offset) << 11) })
-#define __pte_to_swp_entry(pte) \
-	((swp_entry_t) { pte_val(pte_mkuptodate(pte)) })
-#define __swp_entry_to_pte(x)		((pte_t) { (x).val })
-
-#define kern_addr_valid(addr) (1)
-
-#include <asm-generic/pgtable.h>
-
-#endif
diff --git a/include/asm-um/poll.h b/include/asm-um/poll.h
deleted file mode 100644
index 1eb4e1bc6383..000000000000
--- a/include/asm-um/poll.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_POLL_H
-#define __UM_POLL_H
-
-#include "asm/arch/poll.h"
-
-#endif
diff --git a/include/asm-um/posix_types.h b/include/asm-um/posix_types.h
deleted file mode 100644
index 32fb4198f644..000000000000
--- a/include/asm-um/posix_types.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_POSIX_TYPES_H
-#define __UM_POSIX_TYPES_H
-
-#include "asm/arch/posix_types.h"
-
-#endif
diff --git a/include/asm-um/prctl.h b/include/asm-um/prctl.h
deleted file mode 100644
index 64b6d099bdd5..000000000000
--- a/include/asm-um/prctl.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_PRCTL_H
-#define __UM_PRCTL_H
-
-#include "asm/arch/prctl.h"
-
-#endif
diff --git a/include/asm-um/processor-generic.h b/include/asm-um/processor-generic.h
deleted file mode 100644
index bed668824b5f..000000000000
--- a/include/asm-um/processor-generic.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/* 
- * Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-
-#ifndef __UM_PROCESSOR_GENERIC_H
-#define __UM_PROCESSOR_GENERIC_H
-
-struct pt_regs;
-
-struct task_struct;
-
-#include "asm/ptrace.h"
-#include "registers.h"
-#include "sysdep/archsetjmp.h"
-
-struct mm_struct;
-
-struct thread_struct {
-	struct task_struct *saved_task;
-	/*
-	 * This flag is set to 1 before calling do_fork (and analyzed in
-	 * copy_thread) to mark that we are begin called from userspace (fork /
-	 * vfork / clone), and reset to 0 after. It is left to 0 when called
-	 * from kernelspace (i.e. kernel_thread() or fork_idle(),
-	 * as of 2.6.11).
-	 */
-	int forking;
-	struct pt_regs regs;
-	int singlestep_syscall;
-	void *fault_addr;
-	jmp_buf *fault_catcher;
-	struct task_struct *prev_sched;
-	unsigned long temp_stack;
-	jmp_buf *exec_buf;
-	struct arch_thread arch;
-	jmp_buf switch_buf;
-	int mm_count;
-	struct {
-		int op;
-		union {
-			struct {
-				int pid;
-			} fork, exec;
-			struct {
-				int (*proc)(void *);
-				void *arg;
-			} thread;
-			struct {
-				void (*proc)(void *);
-				void *arg;
-			} cb;
-		} u;
-	} request;
-};
-
-#define INIT_THREAD \
-{ \
-	.forking		= 0, \
-	.regs		   	= EMPTY_REGS,	\
-	.fault_addr		= NULL, \
-	.prev_sched		= NULL, \
-	.temp_stack		= 0, \
-	.exec_buf		= NULL, \
-	.arch			= INIT_ARCH_THREAD, \
-	.request		= { 0 } \
-}
-
-extern struct task_struct *alloc_task_struct(void);
-
-static inline void release_thread(struct task_struct *task)
-{
-}
-
-extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
-
-static inline void prepare_to_copy(struct task_struct *tsk)
-{
-}
-
-
-extern unsigned long thread_saved_pc(struct task_struct *t);
-
-static inline void mm_copy_segments(struct mm_struct *from_mm,
-				    struct mm_struct *new_mm)
-{
-}
-
-#define init_stack	(init_thread_union.stack)
-
-/*
- * User space process size: 3GB (default).
- */
-extern unsigned long task_size;
-
-#define TASK_SIZE (task_size)
-
-#undef STACK_TOP
-#undef STACK_TOP_MAX
-
-extern unsigned long stacksizelim;
-
-#define STACK_ROOM	(stacksizelim)
-#define STACK_TOP	(TASK_SIZE - 2 * PAGE_SIZE)
-#define STACK_TOP_MAX	STACK_TOP
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE	(0x40000000)
-
-extern void start_thread(struct pt_regs *regs, unsigned long entry, 
-			 unsigned long stack);
-
-struct cpuinfo_um {
-	unsigned long loops_per_jiffy;
-	int ipi_pipe[2];
-};
-
-extern struct cpuinfo_um boot_cpu_data;
-
-#define my_cpu_data		cpu_data[smp_processor_id()]
-
-#ifdef CONFIG_SMP
-extern struct cpuinfo_um cpu_data[];
-#define current_cpu_data cpu_data[smp_processor_id()]
-#else
-#define cpu_data (&boot_cpu_data)
-#define current_cpu_data boot_cpu_data
-#endif
-
-
-#define KSTK_REG(tsk, reg) get_thread_reg(reg, &tsk->thread.switch_buf)
-extern unsigned long get_wchan(struct task_struct *p);
-
-#endif
diff --git a/include/asm-um/processor-i386.h b/include/asm-um/processor-i386.h
deleted file mode 100644
index a2b7fe13fe1e..000000000000
--- a/include/asm-um/processor-i386.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (C) 2002 Jeff Dike (jdike@karaya.com)
- * Licensed under the GPL
- */
-
-#ifndef __UM_PROCESSOR_I386_H
-#define __UM_PROCESSOR_I386_H
-
-#include "linux/string.h"
-#include "asm/host_ldt.h"
-#include "asm/segment.h"
-
-extern int host_has_cmov;
-
-/* include faultinfo structure */
-#include "sysdep/faultinfo.h"
-
-struct uml_tls_struct {
-	struct user_desc tls;
-	unsigned flushed:1;
-	unsigned present:1;
-};
-
-struct arch_thread {
-	struct uml_tls_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
-	unsigned long debugregs[8];
-	int debugregs_seq;
-	struct faultinfo faultinfo;
-};
-
-#define INIT_ARCH_THREAD { \
-	.tls_array  		= { [ 0 ... GDT_ENTRY_TLS_ENTRIES - 1 ] = \
-				    { .present = 0, .flushed = 0 } }, \
-	.debugregs  		= { [ 0 ... 7 ] = 0 }, \
-	.debugregs_seq		= 0, \
-	.faultinfo		= { 0, 0, 0 } \
-}
-
-static inline void arch_flush_thread(struct arch_thread *thread)
-{
-	/* Clear any TLS still hanging */
-	memset(&thread->tls_array, 0, sizeof(thread->tls_array));
-}
-
-static inline void arch_copy_thread(struct arch_thread *from,
-                                    struct arch_thread *to)
-{
-        memcpy(&to->tls_array, &from->tls_array, sizeof(from->tls_array));
-}
-
-#include "asm/arch/user.h"
-
-/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
-static inline void rep_nop(void)
-{
-	__asm__ __volatile__("rep;nop": : :"memory");
-}
-
-#define cpu_relax()	rep_nop()
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter"). Stolen
- * from asm-i386/processor.h
- */
-#define current_text_addr() \
-	({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
-
-#define ARCH_IS_STACKGROW(address) \
-       (address + 32 >= UPT_SP(&current->thread.regs.regs))
-
-#define KSTK_EIP(tsk) KSTK_REG(tsk, EIP)
-#define KSTK_ESP(tsk) KSTK_REG(tsk, UESP)
-#define KSTK_EBP(tsk) KSTK_REG(tsk, EBP)
-
-#include "asm/processor-generic.h"
-
-#endif
diff --git a/include/asm-um/processor-ppc.h b/include/asm-um/processor-ppc.h
deleted file mode 100644
index 959323151229..000000000000
--- a/include/asm-um/processor-ppc.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef __UM_PROCESSOR_PPC_H
-#define __UM_PROCESSOR_PPC_H
-
-#if defined(__ASSEMBLY__)
-
-#define CONFIG_PPC_MULTIPLATFORM
-#include "arch/processor.h"
-
-#else
-
-#include "asm/processor-generic.h"
-
-#endif
-
-#endif
diff --git a/include/asm-um/processor-x86_64.h b/include/asm-um/processor-x86_64.h
deleted file mode 100644
index e50933175e91..000000000000
--- a/include/asm-um/processor-x86_64.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2003 PathScale, Inc.
- *
- * Licensed under the GPL
- */
-
-#ifndef __UM_PROCESSOR_X86_64_H
-#define __UM_PROCESSOR_X86_64_H
-
-/* include faultinfo structure */
-#include "sysdep/faultinfo.h"
-
-struct arch_thread {
-        unsigned long debugregs[8];
-        int debugregs_seq;
-        unsigned long fs;
-        struct faultinfo faultinfo;
-};
-
-/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
-static inline void rep_nop(void)
-{
-	__asm__ __volatile__("rep;nop": : :"memory");
-}
-
-#define cpu_relax()   rep_nop()
-
-#define INIT_ARCH_THREAD { .debugregs  		= { [ 0 ... 7 ] = 0 }, \
-			   .debugregs_seq	= 0, \
-			   .fs			= 0, \
-			   .faultinfo		= { 0, 0, 0 } }
-
-static inline void arch_flush_thread(struct arch_thread *thread)
-{
-}
-
-static inline void arch_copy_thread(struct arch_thread *from,
-                                    struct arch_thread *to)
-{
-	to->fs = from->fs;
-}
-
-#include "asm/arch/user.h"
-
-#define current_text_addr() \
-	({ void *pc; __asm__("movq $1f,%0\n1:":"=g" (pc)); pc; })
-
-#define ARCH_IS_STACKGROW(address) \
-        (address + 128 >= UPT_SP(&current->thread.regs.regs))
-
-#define KSTK_EIP(tsk) KSTK_REG(tsk, RIP)
-#define KSTK_ESP(tsk) KSTK_REG(tsk, RSP)
-
-#include "asm/processor-generic.h"
-
-#endif
diff --git a/include/asm-um/ptrace-generic.h b/include/asm-um/ptrace-generic.h
deleted file mode 100644
index 315749705ea1..000000000000
--- a/include/asm-um/ptrace-generic.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* 
- * Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-
-#ifndef __UM_PTRACE_GENERIC_H
-#define __UM_PTRACE_GENERIC_H
-
-#ifndef __ASSEMBLY__
-
-#include "asm/arch/ptrace-abi.h"
-#include <asm/user.h>
-#include "sysdep/ptrace.h"
-
-struct pt_regs {
-	struct uml_pt_regs regs;
-};
-
-#define EMPTY_REGS { .regs = EMPTY_UML_PT_REGS }
-
-#define PT_REGS_IP(r) UPT_IP(&(r)->regs)
-#define PT_REGS_SP(r) UPT_SP(&(r)->regs)
-
-#define PT_REG(r, reg) UPT_REG(&(r)->regs, reg)
-#define PT_REGS_SET(r, reg, val) UPT_SET(&(r)->regs, reg, val)
-
-#define PT_REGS_SET_SYSCALL_RETURN(r, res) \
-	UPT_SET_SYSCALL_RETURN(&(r)->regs, res)
-#define PT_REGS_RESTART_SYSCALL(r) UPT_RESTART_SYSCALL(&(r)->regs)
-
-#define PT_REGS_SYSCALL_NR(r) UPT_SYSCALL_NR(&(r)->regs)
-
-#define PT_REGS_SC(r) UPT_SC(&(r)->regs)
-
-#define instruction_pointer(regs) PT_REGS_IP(regs)
-
-struct task_struct;
-
-extern long subarch_ptrace(struct task_struct *child, long request, long addr,
-			   long data);
-extern unsigned long getreg(struct task_struct *child, int regno);
-extern int putreg(struct task_struct *child, int regno, unsigned long value);
-extern int get_fpregs(struct user_i387_struct __user *buf,
-		      struct task_struct *child);
-extern int set_fpregs(struct user_i387_struct __user *buf,
-		      struct task_struct *child);
-
-extern void show_regs(struct pt_regs *regs);
-
-extern int arch_copy_tls(struct task_struct *new);
-extern void clear_flushed_tls(struct task_struct *task);
-
-#endif
-
-#endif
diff --git a/include/asm-um/ptrace-i386.h b/include/asm-um/ptrace-i386.h
deleted file mode 100644
index b2d24c5ea2c3..000000000000
--- a/include/asm-um/ptrace-i386.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* 
- * Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-
-#ifndef __UM_PTRACE_I386_H
-#define __UM_PTRACE_I386_H
-
-#define HOST_AUDIT_ARCH AUDIT_ARCH_I386
-
-#include "linux/compiler.h"
-#include "asm/ptrace-generic.h"
-#include <asm/user.h>
-#include "sysdep/ptrace.h"
-
-#define PT_REGS_EAX(r) UPT_EAX(&(r)->regs)
-#define PT_REGS_EBX(r) UPT_EBX(&(r)->regs)
-#define PT_REGS_ECX(r) UPT_ECX(&(r)->regs)
-#define PT_REGS_EDX(r) UPT_EDX(&(r)->regs)
-#define PT_REGS_ESI(r) UPT_ESI(&(r)->regs)
-#define PT_REGS_EDI(r) UPT_EDI(&(r)->regs)
-#define PT_REGS_EBP(r) UPT_EBP(&(r)->regs)
-
-#define PT_REGS_CS(r) UPT_CS(&(r)->regs)
-#define PT_REGS_SS(r) UPT_SS(&(r)->regs)
-#define PT_REGS_DS(r) UPT_DS(&(r)->regs)
-#define PT_REGS_ES(r) UPT_ES(&(r)->regs)
-#define PT_REGS_FS(r) UPT_FS(&(r)->regs)
-#define PT_REGS_GS(r) UPT_GS(&(r)->regs)
-
-#define PT_REGS_EFLAGS(r) UPT_EFLAGS(&(r)->regs)
-
-#define PT_REGS_ORIG_SYSCALL(r) PT_REGS_EAX(r)
-#define PT_REGS_SYSCALL_RET(r) PT_REGS_EAX(r)
-#define PT_FIX_EXEC_STACK(sp) do ; while(0)
-
-/* Cope with a conditional i386 definition. */
-#undef profile_pc
-#define profile_pc(regs) PT_REGS_IP(regs)
-
-#define user_mode(r) UPT_IS_USER(&(r)->regs)
-
-/*
- * Forward declaration to avoid including sysdep/tls.h, which causes a
- * circular include, and compilation failures.
- */
-struct user_desc;
-
-extern int get_fpxregs(struct user_fxsr_struct __user *buf,
-		       struct task_struct *child);
-extern int set_fpxregs(struct user_fxsr_struct __user *buf,
-		       struct task_struct *tsk);
-
-extern int ptrace_get_thread_area(struct task_struct *child, int idx,
-                                  struct user_desc __user *user_desc);
-
-extern int ptrace_set_thread_area(struct task_struct *child, int idx,
-                                  struct user_desc __user *user_desc);
-
-#endif
diff --git a/include/asm-um/ptrace-x86_64.h b/include/asm-um/ptrace-x86_64.h
deleted file mode 100644
index 4c475350dcf0..000000000000
--- a/include/asm-um/ptrace-x86_64.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright 2003 PathScale, Inc.
- *
- * Licensed under the GPL
- */
-
-#ifndef __UM_PTRACE_X86_64_H
-#define __UM_PTRACE_X86_64_H
-
-#include "linux/compiler.h"
-#include "asm/errno.h"
-#include "asm/host_ldt.h"
-
-#define __FRAME_OFFSETS /* Needed to get the R* macros */
-#include "asm/ptrace-generic.h"
-
-#define HOST_AUDIT_ARCH AUDIT_ARCH_X86_64
-
-/* Also defined in sysdep/ptrace.h, so may already be defined. */
-#ifndef FS_BASE
-#define FS_BASE (21 * sizeof(unsigned long))
-#define GS_BASE (22 * sizeof(unsigned long))
-#define DS (23 * sizeof(unsigned long))
-#define ES (24 * sizeof(unsigned long))
-#define FS (25 * sizeof(unsigned long))
-#define GS (26 * sizeof(unsigned long))
-#endif
-
-#define PT_REGS_RBX(r) UPT_RBX(&(r)->regs)
-#define PT_REGS_RCX(r) UPT_RCX(&(r)->regs)
-#define PT_REGS_RDX(r) UPT_RDX(&(r)->regs)
-#define PT_REGS_RSI(r) UPT_RSI(&(r)->regs)
-#define PT_REGS_RDI(r) UPT_RDI(&(r)->regs)
-#define PT_REGS_RBP(r) UPT_RBP(&(r)->regs)
-#define PT_REGS_RAX(r) UPT_RAX(&(r)->regs)
-#define PT_REGS_R8(r) UPT_R8(&(r)->regs)
-#define PT_REGS_R9(r) UPT_R9(&(r)->regs)
-#define PT_REGS_R10(r) UPT_R10(&(r)->regs)
-#define PT_REGS_R11(r) UPT_R11(&(r)->regs)
-#define PT_REGS_R12(r) UPT_R12(&(r)->regs)
-#define PT_REGS_R13(r) UPT_R13(&(r)->regs)
-#define PT_REGS_R14(r) UPT_R14(&(r)->regs)
-#define PT_REGS_R15(r) UPT_R15(&(r)->regs)
-
-#define PT_REGS_FS(r) UPT_FS(&(r)->regs)
-#define PT_REGS_GS(r) UPT_GS(&(r)->regs)
-#define PT_REGS_DS(r) UPT_DS(&(r)->regs)
-#define PT_REGS_ES(r) UPT_ES(&(r)->regs)
-#define PT_REGS_SS(r) UPT_SS(&(r)->regs)
-#define PT_REGS_CS(r) UPT_CS(&(r)->regs)
-
-#define PT_REGS_ORIG_RAX(r) UPT_ORIG_RAX(&(r)->regs)
-#define PT_REGS_RIP(r) UPT_IP(&(r)->regs)
-#define PT_REGS_RSP(r) UPT_SP(&(r)->regs)
-
-#define PT_REGS_EFLAGS(r) UPT_EFLAGS(&(r)->regs)
-
-/* XXX */
-#define user_mode(r) UPT_IS_USER(&(r)->regs)
-#define PT_REGS_ORIG_SYSCALL(r) PT_REGS_RAX(r)
-#define PT_REGS_SYSCALL_RET(r) PT_REGS_RAX(r)
-
-#define PT_FIX_EXEC_STACK(sp) do ; while(0)
-
-#define profile_pc(regs) PT_REGS_IP(regs)
-
-static inline int ptrace_get_thread_area(struct task_struct *child, int idx,
-                                         struct user_desc __user *user_desc)
-{
-        return -ENOSYS;
-}
-
-static inline int ptrace_set_thread_area(struct task_struct *child, int idx,
-                                         struct user_desc __user *user_desc)
-{
-        return -ENOSYS;
-}
-
-extern long arch_prctl(struct task_struct *task, int code,
-		       unsigned long __user *addr);
-#endif
diff --git a/include/asm-um/required-features.h b/include/asm-um/required-features.h
deleted file mode 100644
index dfb967b2d2f3..000000000000
--- a/include/asm-um/required-features.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __UM_REQUIRED_FEATURES_H
-#define __UM_REQUIRED_FEATURES_H
-
-/*
- * Nothing to see, just need something for the i386 and x86_64 asm
- * headers to include.
- */
-
-#endif
diff --git a/include/asm-um/resource.h b/include/asm-um/resource.h
deleted file mode 100644
index c9b074001252..000000000000
--- a/include/asm-um/resource.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_RESOURCE_H
-#define __UM_RESOURCE_H
-
-#include "asm/arch/resource.h"
-
-#endif
diff --git a/include/asm-um/rwlock.h b/include/asm-um/rwlock.h
deleted file mode 100644
index ff383aafc9fe..000000000000
--- a/include/asm-um/rwlock.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_RWLOCK_H
-#define __UM_RWLOCK_H
-
-#include "asm/arch/rwlock.h"
-
-#endif
diff --git a/include/asm-um/rwsem.h b/include/asm-um/rwsem.h
deleted file mode 100644
index b5fc449dc86b..000000000000
--- a/include/asm-um/rwsem.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_RWSEM_H__
-#define __UM_RWSEM_H__
-
-#include "asm/arch/rwsem.h"
-
-#endif
diff --git a/include/asm-um/scatterlist.h b/include/asm-um/scatterlist.h
deleted file mode 100644
index e92016aa2079..000000000000
--- a/include/asm-um/scatterlist.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_SCATTERLIST_H
-#define __UM_SCATTERLIST_H
-
-#include "asm/arch/scatterlist.h"
-
-#endif
diff --git a/include/asm-um/sections.h b/include/asm-um/sections.h
deleted file mode 100644
index 6b0231eefea8..000000000000
--- a/include/asm-um/sections.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _UM_SECTIONS_H
-#define _UM_SECTIONS_H
-
-/* nothing to see, move along */
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/include/asm-um/segment.h b/include/asm-um/segment.h
deleted file mode 100644
index 45183fcd10b6..000000000000
--- a/include/asm-um/segment.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __UM_SEGMENT_H
-#define __UM_SEGMENT_H
-
-extern int host_gdt_entry_tls_min;
-
-#define GDT_ENTRY_TLS_ENTRIES 3
-#define GDT_ENTRY_TLS_MIN host_gdt_entry_tls_min
-#define GDT_ENTRY_TLS_MAX (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
-
-#endif
diff --git a/include/asm-um/sembuf.h b/include/asm-um/sembuf.h
deleted file mode 100644
index 1ae82c14ff86..000000000000
--- a/include/asm-um/sembuf.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_SEMBUF_H
-#define __UM_SEMBUF_H
-
-#include "asm/arch/sembuf.h"
-
-#endif
diff --git a/include/asm-um/serial.h b/include/asm-um/serial.h
deleted file mode 100644
index 61ad07cfd2d5..000000000000
--- a/include/asm-um/serial.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_SERIAL_H
-#define __UM_SERIAL_H
-
-#include "asm/arch/serial.h"
-
-#endif
diff --git a/include/asm-um/setup.h b/include/asm-um/setup.h
deleted file mode 100644
index 99f086301f4c..000000000000
--- a/include/asm-um/setup.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef SETUP_H_INCLUDED
-#define SETUP_H_INCLUDED
-
-/* POSIX mandated with _POSIX_ARG_MAX that we can rely on 4096 chars in the
- * command line, so this choice is ok.
- */
-
-#define COMMAND_LINE_SIZE 4096
-
-#endif		/* SETUP_H_INCLUDED */
diff --git a/include/asm-um/shmbuf.h b/include/asm-um/shmbuf.h
deleted file mode 100644
index 9684d4a284a6..000000000000
--- a/include/asm-um/shmbuf.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_SHMBUF_H
-#define __UM_SHMBUF_H
-
-#include "asm/arch/shmbuf.h"
-
-#endif
diff --git a/include/asm-um/shmparam.h b/include/asm-um/shmparam.h
deleted file mode 100644
index 124c00174f6a..000000000000
--- a/include/asm-um/shmparam.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_SHMPARAM_H
-#define __UM_SHMPARAM_H
-
-#include "asm/arch/shmparam.h"
-
-#endif
diff --git a/include/asm-um/sigcontext-generic.h b/include/asm-um/sigcontext-generic.h
deleted file mode 100644
index 164587014c61..000000000000
--- a/include/asm-um/sigcontext-generic.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_SIGCONTEXT_GENERIC_H
-#define __UM_SIGCONTEXT_GENERIC_H
-
-#include "asm/arch/sigcontext.h"
-
-#endif
diff --git a/include/asm-um/sigcontext-i386.h b/include/asm-um/sigcontext-i386.h
deleted file mode 100644
index b88333f488bb..000000000000
--- a/include/asm-um/sigcontext-i386.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_SIGCONTEXT_I386_H
-#define __UM_SIGCONTEXT_I386_H
-
-#include "asm/sigcontext-generic.h"
-
-#endif
diff --git a/include/asm-um/sigcontext-ppc.h b/include/asm-um/sigcontext-ppc.h
deleted file mode 100644
index 2467f20eda99..000000000000
--- a/include/asm-um/sigcontext-ppc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __UM_SIGCONTEXT_PPC_H
-#define __UM_SIGCONTEXT_PPC_H
-
-#define pt_regs sys_pt_regs
-
-#include "asm/sigcontext-generic.h"
-
-#undef pt_regs
-
-#endif
diff --git a/include/asm-um/sigcontext-x86_64.h b/include/asm-um/sigcontext-x86_64.h
deleted file mode 100644
index b600e0b01e48..000000000000
--- a/include/asm-um/sigcontext-x86_64.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2003 PathScale, Inc.
- *
- * Licensed under the GPL
- */
-
-#ifndef __UM_SIGCONTEXT_X86_64_H
-#define __UM_SIGCONTEXT_X86_64_H
-
-#include "asm/sigcontext-generic.h"
-
-#endif
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff --git a/include/asm-um/siginfo.h b/include/asm-um/siginfo.h
deleted file mode 100644
index bec6124c36d0..000000000000
--- a/include/asm-um/siginfo.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_SIGINFO_H
-#define __UM_SIGINFO_H
-
-#include "asm/arch/siginfo.h"
-
-#endif
diff --git a/include/asm-um/signal.h b/include/asm-um/signal.h
deleted file mode 100644
index 52ed92cbce4c..000000000000
--- a/include/asm-um/signal.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* 
- * Copyright (C) 2002 Jeff Dike (jdike@karaya.com)
- * Licensed under the GPL
- */
-
-#ifndef __UM_SIGNAL_H
-#define __UM_SIGNAL_H
-
-/* Need to kill the do_signal() declaration in the i386 signal.h */
-
-#define do_signal do_signal_renamed
-#include "asm/arch/signal.h"
-#undef do_signal
-#undef ptrace_signal_deliver
-
-#define ptrace_signal_deliver(regs, cookie) do {} while(0)
-
-#endif
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff --git a/include/asm-um/smp.h b/include/asm-um/smp.h
deleted file mode 100644
index f27a96313174..000000000000
--- a/include/asm-um/smp.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef __UM_SMP_H
-#define __UM_SMP_H
-
-#ifdef CONFIG_SMP
-
-#include "linux/bitops.h"
-#include "asm/current.h"
-#include "linux/cpumask.h"
-
-#define raw_smp_processor_id() (current_thread->cpu)
-
-#define cpu_logical_map(n) (n)
-#define cpu_number_map(n) (n)
-#define PROC_CHANGE_PENALTY	15 /* Pick a number, any number */
-extern int hard_smp_processor_id(void);
-#define NO_PROC_ID -1
-
-extern int ncpus;
-
-
-static inline void smp_cpus_done(unsigned int maxcpus)
-{
-}
-
-extern struct task_struct *idle_threads[NR_CPUS];
-
-#else
-
-#define hard_smp_processor_id()		0
-
-#endif
-
-#endif
diff --git a/include/asm-um/socket.h b/include/asm-um/socket.h
deleted file mode 100644
index 67886e42ef04..000000000000
--- a/include/asm-um/socket.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_SOCKET_H
-#define __UM_SOCKET_H
-
-#include "asm/arch/socket.h"
-
-#endif
diff --git a/include/asm-um/sockios.h b/include/asm-um/sockios.h
deleted file mode 100644
index 93ee1c55c4d6..000000000000
--- a/include/asm-um/sockios.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_SOCKIOS_H
-#define __UM_SOCKIOS_H
-
-#include "asm/arch/sockios.h"
-
-#endif
diff --git a/include/asm-um/spinlock.h b/include/asm-um/spinlock.h
deleted file mode 100644
index f18c82886992..000000000000
--- a/include/asm-um/spinlock.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_SPINLOCK_H
-#define __UM_SPINLOCK_H
-
-#include "asm/arch/spinlock.h"
-
-#endif
diff --git a/include/asm-um/spinlock_types.h b/include/asm-um/spinlock_types.h
deleted file mode 100644
index e5a94294bf82..000000000000
--- a/include/asm-um/spinlock_types.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_SPINLOCK_TYPES_H
-#define __UM_SPINLOCK_TYPES_H
-
-#include "asm/arch/spinlock_types.h"
-
-#endif
diff --git a/include/asm-um/stat.h b/include/asm-um/stat.h
deleted file mode 100644
index 83ed85ad2539..000000000000
--- a/include/asm-um/stat.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_STAT_H
-#define __UM_STAT_H
-
-#include "asm/arch/stat.h"
-
-#endif
diff --git a/include/asm-um/statfs.h b/include/asm-um/statfs.h
deleted file mode 100644
index ba6fb53e7f87..000000000000
--- a/include/asm-um/statfs.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _UM_STATFS_H
-#define _UM_STATFS_H
-
-#include "asm/arch/statfs.h"
-
-#endif
diff --git a/include/asm-um/string.h b/include/asm-um/string.h
deleted file mode 100644
index 9a0571f6dd61..000000000000
--- a/include/asm-um/string.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __UM_STRING_H
-#define __UM_STRING_H
-
-#include "asm/arch/string.h"
-#include "asm/archparam.h"
-
-#endif
diff --git a/include/asm-um/suspend.h b/include/asm-um/suspend.h
deleted file mode 100644
index f4e8e007f468..000000000000
--- a/include/asm-um/suspend.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __UM_SUSPEND_H
-#define __UM_SUSPEND_H
-
-#endif
diff --git a/include/asm-um/system-generic.h b/include/asm-um/system-generic.h
deleted file mode 100644
index 5bcfa35e7a22..000000000000
--- a/include/asm-um/system-generic.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef __UM_SYSTEM_GENERIC_H
-#define __UM_SYSTEM_GENERIC_H
-
-#include "asm/arch/system.h"
-
-#undef switch_to
-#undef local_irq_save
-#undef local_irq_restore
-#undef local_irq_disable
-#undef local_irq_enable
-#undef local_save_flags
-#undef local_irq_restore
-#undef local_irq_enable
-#undef local_irq_disable
-#undef local_irq_save
-#undef irqs_disabled
-
-extern void *switch_to(void *prev, void *next, void *last);
-
-extern int get_signals(void);
-extern int set_signals(int enable);
-extern int get_signals(void);
-extern void block_signals(void);
-extern void unblock_signals(void);
-
-#define local_save_flags(flags) do { typecheck(unsigned long, flags); \
-				     (flags) = get_signals(); } while(0)
-#define local_irq_restore(flags) do { typecheck(unsigned long, flags); \
-				      set_signals(flags); } while(0)
-
-#define local_irq_save(flags) do { local_save_flags(flags); \
-                                   local_irq_disable(); } while(0)
-
-#define local_irq_enable() unblock_signals()
-#define local_irq_disable() block_signals()
-
-#define irqs_disabled()                 \
-({                                      \
-        unsigned long flags;            \
-        local_save_flags(flags);        \
-        (flags == 0);                   \
-})
-
-extern void *_switch_to(void *prev, void *next, void *last);
-#define switch_to(prev, next, last) prev = _switch_to(prev, next, last)
-
-#endif
diff --git a/include/asm-um/system-i386.h b/include/asm-um/system-i386.h
deleted file mode 100644
index c436263e67ba..000000000000
--- a/include/asm-um/system-i386.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_SYSTEM_I386_H
-#define __UM_SYSTEM_I386_H
-
-#include "asm/system-generic.h"
-    
-#endif
diff --git a/include/asm-um/system-ppc.h b/include/asm-um/system-ppc.h
deleted file mode 100644
index 17cde6640bf5..000000000000
--- a/include/asm-um/system-ppc.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __UM_SYSTEM_PPC_H
-#define __UM_SYSTEM_PPC_H
-
-#define _switch_to _ppc_switch_to
-
-#include "asm/arch/system.h"
-
-#undef _switch_to
- 
-#include "asm/system-generic.h"
-
-#endif
diff --git a/include/asm-um/system-x86_64.h b/include/asm-um/system-x86_64.h
deleted file mode 100644
index e1b61b580734..000000000000
--- a/include/asm-um/system-x86_64.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2003 PathScale, Inc.
- *
- * Licensed under the GPL
- */
-
-#ifndef __UM_SYSTEM_X86_64_H
-#define __UM_SYSTEM_X86_64_H
-
-#include "asm/system-generic.h"
-
-#endif
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff --git a/include/asm-um/termbits.h b/include/asm-um/termbits.h
deleted file mode 100644
index 5739c608a2cb..000000000000
--- a/include/asm-um/termbits.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_TERMBITS_H
-#define __UM_TERMBITS_H
-
-#include "asm/arch/termbits.h"
-
-#endif
diff --git a/include/asm-um/termios.h b/include/asm-um/termios.h
deleted file mode 100644
index d9f97b303311..000000000000
--- a/include/asm-um/termios.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_TERMIOS_H
-#define __UM_TERMIOS_H
-
-#include "asm/arch/termios.h"
-
-#endif
diff --git a/include/asm-um/thread_info.h b/include/asm-um/thread_info.h
deleted file mode 100644
index e07e72846c7a..000000000000
--- a/include/asm-um/thread_info.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2002 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-
-#ifndef __UM_THREAD_INFO_H
-#define __UM_THREAD_INFO_H
-
-#ifndef __ASSEMBLY__
-
-#include <asm/types.h>
-#include <asm/page.h>
-#include <asm/uaccess.h>
-
-struct thread_info {
-	struct task_struct	*task;		/* main task structure */
-	struct exec_domain	*exec_domain;	/* execution domain */
-	unsigned long		flags;		/* low level flags */
-	__u32			cpu;		/* current CPU */
-	int			preempt_count;  /* 0 => preemptable,
-						   <0 => BUG */
-	mm_segment_t		addr_limit;	/* thread address space:
-					 	   0-0xBFFFFFFF for user
-						   0-0xFFFFFFFF for kernel */
-	struct restart_block    restart_block;
-	struct thread_info	*real_thread;    /* Points to non-IRQ stack */
-};
-
-#define INIT_THREAD_INFO(tsk)			\
-{						\
-	.task =		&tsk,			\
-	.exec_domain =	&default_exec_domain,	\
-	.flags =		0,		\
-	.cpu =		0,			\
-	.preempt_count =	1,		\
-	.addr_limit =	KERNEL_DS,		\
-	.restart_block =  {			\
-		.fn =  do_no_restart_syscall,	\
-	},					\
-	.real_thread = NULL,			\
-}
-
-#define init_thread_info	(init_thread_union.thread_info)
-#define init_stack		(init_thread_union.stack)
-
-#define THREAD_SIZE ((1 << CONFIG_KERNEL_STACK_ORDER) * PAGE_SIZE)
-/* how to get the thread information struct from C */
-static inline struct thread_info *current_thread_info(void)
-{
-	struct thread_info *ti;
-	unsigned long mask = THREAD_SIZE - 1;
-	ti = (struct thread_info *) (((unsigned long) &ti) & ~mask);
-	return ti;
-}
-
-#define THREAD_SIZE_ORDER CONFIG_KERNEL_STACK_ORDER
-
-#endif
-
-#define PREEMPT_ACTIVE		0x10000000
-
-#define TIF_SYSCALL_TRACE	0	/* syscall trace active */
-#define TIF_SIGPENDING		1	/* signal pending */
-#define TIF_NEED_RESCHED	2	/* rescheduling necessary */
-#define TIF_POLLING_NRFLAG      3       /* true if poll_idle() is polling
-					 * TIF_NEED_RESCHED
-					 */
-#define TIF_RESTART_BLOCK 	4
-#define TIF_MEMDIE	 	5
-#define TIF_SYSCALL_AUDIT	6
-#define TIF_RESTORE_SIGMASK	7
-
-#define _TIF_SYSCALL_TRACE	(1 << TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING		(1 << TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED	(1 << TIF_NEED_RESCHED)
-#define _TIF_POLLING_NRFLAG     (1 << TIF_POLLING_NRFLAG)
-#define _TIF_MEMDIE		(1 << TIF_MEMDIE)
-#define _TIF_SYSCALL_AUDIT	(1 << TIF_SYSCALL_AUDIT)
-#define _TIF_RESTORE_SIGMASK	(1 << TIF_RESTORE_SIGMASK)
-
-#endif
diff --git a/include/asm-um/timex.h b/include/asm-um/timex.h
deleted file mode 100644
index 0f4ada08f748..000000000000
--- a/include/asm-um/timex.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __UM_TIMEX_H
-#define __UM_TIMEX_H
-
-typedef unsigned long cycles_t;
-
-static inline cycles_t get_cycles (void)
-{
-	return 0;
-}
-
-#define CLOCK_TICK_RATE (HZ)
-
-#endif
diff --git a/include/asm-um/tlb.h b/include/asm-um/tlb.h
deleted file mode 100644
index 5240fa1c5e08..000000000000
--- a/include/asm-um/tlb.h
+++ /dev/null
@@ -1,127 +0,0 @@
-#ifndef __UM_TLB_H
-#define __UM_TLB_H
-
-#include <linux/pagemap.h>
-#include <linux/swap.h>
-#include <asm/percpu.h>
-#include <asm/pgalloc.h>
-#include <asm/tlbflush.h>
-
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-
-/* struct mmu_gather is an opaque type used by the mm code for passing around
- * any data needed by arch specific code for tlb_remove_page.
- */
-struct mmu_gather {
-	struct mm_struct	*mm;
-	unsigned int		need_flush; /* Really unmapped some ptes? */
-	unsigned long		start;
-	unsigned long		end;
-	unsigned int		fullmm; /* non-zero means full mm flush */
-};
-
-/* Users of the generic TLB shootdown code must declare this storage space. */
-DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
-
-static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
-					  unsigned long address)
-{
-	if (tlb->start > address)
-		tlb->start = address;
-	if (tlb->end < address + PAGE_SIZE)
-		tlb->end = address + PAGE_SIZE;
-}
-
-static inline void init_tlb_gather(struct mmu_gather *tlb)
-{
-	tlb->need_flush = 0;
-
-	tlb->start = TASK_SIZE;
-	tlb->end = 0;
-
-	if (tlb->fullmm) {
-		tlb->start = 0;
-		tlb->end = TASK_SIZE;
-	}
-}
-
-/* tlb_gather_mmu
- *	Return a pointer to an initialized struct mmu_gather.
- */
-static inline struct mmu_gather *
-tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
-{
-	struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
-
-	tlb->mm = mm;
-	tlb->fullmm = full_mm_flush;
-
-	init_tlb_gather(tlb);
-
-	return tlb;
-}
-
-extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
-			       unsigned long end);
-
-static inline void
-tlb_flush_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
-{
-	if (!tlb->need_flush)
-		return;
-
-	flush_tlb_mm_range(tlb->mm, tlb->start, tlb->end);
-	init_tlb_gather(tlb);
-}
-
-/* tlb_finish_mmu
- *	Called at the end of the shootdown operation to free up any resources
- *	that were required.
- */
-static inline void
-tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
-{
-	tlb_flush_mmu(tlb, start, end);
-
-	/* keep the page table cache within bounds */
-	check_pgt_cache();
-
-	put_cpu_var(mmu_gathers);
-}
-
-/* tlb_remove_page
- *	Must perform the equivalent to __free_pte(pte_get_and_clear(ptep)),
- *	while handling the additional races in SMP caused by other CPUs
- *	caching valid mappings in their TLBs.
- */
-static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
-{
-	tlb->need_flush = 1;
-	free_page_and_swap_cache(page);
-	return;
-}
-
-/**
- * tlb_remove_tlb_entry - remember a pte unmapping for later tlb invalidation.
- *
- * Record the fact that pte's were really umapped in ->need_flush, so we can
- * later optimise away the tlb invalidate.   This helps when userspace is
- * unmapping already-unmapped pages, which happens quite a lot.
- */
-#define tlb_remove_tlb_entry(tlb, ptep, address)		\
-	do {							\
-		tlb->need_flush = 1;				\
-		__tlb_remove_tlb_entry(tlb, ptep, address);	\
-	} while (0)
-
-#define pte_free_tlb(tlb, ptep) __pte_free_tlb(tlb, ptep)
-
-#define pud_free_tlb(tlb, pudp) __pud_free_tlb(tlb, pudp)
-
-#define pmd_free_tlb(tlb, pmdp) __pmd_free_tlb(tlb, pmdp)
-
-#define tlb_migrate_finish(mm) do {} while (0)
-
-#endif
diff --git a/include/asm-um/tlbflush.h b/include/asm-um/tlbflush.h
deleted file mode 100644
index 614f2c091178..000000000000
--- a/include/asm-um/tlbflush.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2002 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-
-#ifndef __UM_TLBFLUSH_H
-#define __UM_TLBFLUSH_H
-
-#include <linux/mm.h>
-
-/*
- * TLB flushing:
- *
- *  - flush_tlb() flushes the current mm struct TLBs
- *  - flush_tlb_all() flushes all processes TLBs
- *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
- *  - flush_tlb_page(vma, vmaddr) flushes one page
- *  - flush_tlb_kernel_vm() flushes the kernel vm area
- *  - flush_tlb_range(vma, start, end) flushes a range of pages
- */
-
-extern void flush_tlb_all(void);
-extern void flush_tlb_mm(struct mm_struct *mm);
-extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, 
-			    unsigned long end);
-extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long address);
-extern void flush_tlb_kernel_vm(void);
-extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
-extern void __flush_tlb_one(unsigned long addr);
-
-#endif
diff --git a/include/asm-um/topology.h b/include/asm-um/topology.h
deleted file mode 100644
index 0905e4f21d42..000000000000
--- a/include/asm-um/topology.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_UM_TOPOLOGY_H
-#define _ASM_UM_TOPOLOGY_H
-
-#include <asm-generic/topology.h>
-
-#endif
diff --git a/include/asm-um/types.h b/include/asm-um/types.h
deleted file mode 100644
index 816e9590fc73..000000000000
--- a/include/asm-um/types.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_TYPES_H
-#define __UM_TYPES_H
-
-#include "asm/arch/types.h"
-
-#endif
diff --git a/include/asm-um/uaccess.h b/include/asm-um/uaccess.h
deleted file mode 100644
index b9a895d6fa1d..000000000000
--- a/include/asm-um/uaccess.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* 
- * Copyright (C) 2002 Jeff Dike (jdike@karaya.com)
- * Licensed under the GPL
- */
-
-#ifndef __UM_UACCESS_H
-#define __UM_UACCESS_H
-
-#include <asm/errno.h>
-#include <asm/processor.h>
-
-/* thread_info has a mm_segment_t in it, so put the definition up here */
-typedef struct {
-	unsigned long seg;
-} mm_segment_t;
-
-#include "linux/thread_info.h"
-
-#define VERIFY_READ 0
-#define VERIFY_WRITE 1
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not.  If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- *
- * For historical reasons, these macros are grossly misnamed.
- */
-
-#define MAKE_MM_SEG(s)	((mm_segment_t) { (s) })
-
-#define KERNEL_DS	MAKE_MM_SEG(0xFFFFFFFF)
-#define USER_DS		MAKE_MM_SEG(TASK_SIZE)
-
-#define get_ds()	(KERNEL_DS)
-#define get_fs()	(current_thread_info()->addr_limit)
-#define set_fs(x)	(current_thread_info()->addr_limit = (x))
-
-#define segment_eq(a, b) ((a).seg == (b).seg)
-
-#include "um_uaccess.h"
-
-#define __copy_from_user(to, from, n) copy_from_user(to, from, n)
-
-#define __copy_to_user(to, from, n) copy_to_user(to, from, n)
-
-#define __copy_to_user_inatomic __copy_to_user
-#define __copy_from_user_inatomic __copy_from_user
-
-#define __get_user(x, ptr) \
-({ \
-	const __typeof__(*(ptr)) __user *__private_ptr = (ptr);	\
-	__typeof__(x) __private_val;			\
-	int __private_ret = -EFAULT;			\
-	(x) = (__typeof__(*(__private_ptr)))0;				\
-	if (__copy_from_user((__force void *)&__private_val, (__private_ptr),\
-			     sizeof(*(__private_ptr))) == 0) {		\
-		(x) = (__typeof__(*(__private_ptr))) __private_val;	\
-		__private_ret = 0;					\
-	}								\
-	__private_ret;							\
-}) 
-
-#define get_user(x, ptr) \
-({ \
-        const __typeof__((*(ptr))) __user *private_ptr = (ptr); \
-        (access_ok(VERIFY_READ, private_ptr, sizeof(*private_ptr)) ? \
-	 __get_user(x, private_ptr) : ((x) = (__typeof__(*ptr))0, -EFAULT)); \
-})
-
-#define __put_user(x, ptr) \
-({ \
-        __typeof__(*(ptr)) __user *__private_ptr = ptr; \
-        __typeof__(*(__private_ptr)) __private_val; \
-        int __private_ret = -EFAULT; \
-        __private_val = (__typeof__(*(__private_ptr))) (x); \
-        if (__copy_to_user((__private_ptr), &__private_val, \
-			   sizeof(*(__private_ptr))) == 0) { \
-		__private_ret = 0; \
-	} \
-        __private_ret; \
-})
-
-#define put_user(x, ptr) \
-({ \
-        __typeof__(*(ptr)) __user *private_ptr = (ptr); \
-        (access_ok(VERIFY_WRITE, private_ptr, sizeof(*private_ptr)) ? \
-	 __put_user(x, private_ptr) : -EFAULT); \
-})
-
-#define strlen_user(str) strnlen_user(str, ~0U >> 1)
-
-struct exception_table_entry
-{
-        unsigned long insn;
-	unsigned long fixup;
-};
-
-#endif
diff --git a/include/asm-um/ucontext.h b/include/asm-um/ucontext.h
deleted file mode 100644
index 5c96c0e607f0..000000000000
--- a/include/asm-um/ucontext.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_UM_UCONTEXT_H
-#define _ASM_UM_UCONTEXT_H
-
-#include "asm/arch/ucontext.h"
-
-#endif
diff --git a/include/asm-um/unaligned.h b/include/asm-um/unaligned.h
deleted file mode 100644
index a47196974e39..000000000000
--- a/include/asm-um/unaligned.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_UM_UNALIGNED_H
-#define _ASM_UM_UNALIGNED_H
-
-#include "asm/arch/unaligned.h"
-
-#endif /* _ASM_UM_UNALIGNED_H */
diff --git a/include/asm-um/unistd.h b/include/asm-um/unistd.h
deleted file mode 100644
index 38bd9d94ee46..000000000000
--- a/include/asm-um/unistd.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* 
- * Copyright (C) 2000 - 2004  Jeff Dike (jdike@karaya.com)
- * Licensed under the GPL
- */
-
-#ifndef _UM_UNISTD_H_
-#define _UM_UNISTD_H_
-
-#include <linux/syscalls.h>
-#include "linux/resource.h"
-#include "asm/uaccess.h"
-
-extern int um_execve(const char *file, char *const argv[], char *const env[]);
-
-#ifdef __KERNEL__
-/* We get __ARCH_WANT_OLD_STAT and __ARCH_WANT_STAT64 from the base arch */
-#define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SGETMASK
-#define __ARCH_WANT_SYS_SIGNAL
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_OLD_GETRLIMIT
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_SIGPENDING
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_RT_SIGACTION
-#define __ARCH_WANT_SYS_RT_SIGSUSPEND
-#endif
-
-#include "asm/arch/unistd.h"
-
-#endif /* _UM_UNISTD_H_*/
diff --git a/include/asm-um/user.h b/include/asm-um/user.h
deleted file mode 100644
index aae414ee1f5e..000000000000
--- a/include/asm-um/user.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_USER_H
-#define __UM_USER_H
-
-#include "asm/arch/user.h"
-
-#endif
diff --git a/include/asm-um/vga.h b/include/asm-um/vga.h
deleted file mode 100644
index 903a592b00d0..000000000000
--- a/include/asm-um/vga.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_VGA_H
-#define __UM_VGA_H
-
-#include "asm/arch/vga.h"
-
-#endif
diff --git a/include/asm-um/vm-flags-i386.h b/include/asm-um/vm-flags-i386.h
deleted file mode 100644
index e0d24c568dbc..000000000000
--- a/include/asm-um/vm-flags-i386.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2004 Jeff Dike (jdike@addtoit.com)
- * Licensed under the GPL
- */
-
-#ifndef __VM_FLAGS_I386_H
-#define __VM_FLAGS_I386_H
-
-#define VM_DATA_DEFAULT_FLAGS \
-	(VM_READ | VM_WRITE | \
-	((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
-		 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#endif
diff --git a/include/asm-um/vm-flags-x86_64.h b/include/asm-um/vm-flags-x86_64.h
deleted file mode 100644
index 3213edfa7888..000000000000
--- a/include/asm-um/vm-flags-x86_64.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (C) 2004 Jeff Dike (jdike@addtoit.com)
- * Copyright 2003 PathScale, Inc.
- * Licensed under the GPL
- */
-
-#ifndef __VM_FLAGS_X86_64_H
-#define __VM_FLAGS_X86_64_H
-
-#define __VM_DATA_DEFAULT_FLAGS	(VM_READ | VM_WRITE | VM_EXEC | \
-				 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-#define __VM_STACK_FLAGS 	(VM_GROWSDOWN | VM_READ | VM_WRITE | \
-				 VM_EXEC | VM_MAYREAD | VM_MAYWRITE | \
-				 VM_MAYEXEC)
-
-extern unsigned long vm_stack_flags, vm_stack_flags32;
-extern unsigned long vm_data_default_flags, vm_data_default_flags32;
-extern unsigned long vm_force_exec32;
-
-#ifdef TIF_IA32
-#define VM_DATA_DEFAULT_FLAGS \
-	(test_thread_flag(TIF_IA32) ? vm_data_default_flags32 : \
-	  vm_data_default_flags)
-
-#define VM_STACK_DEFAULT_FLAGS \
-	(test_thread_flag(TIF_IA32) ? vm_stack_flags32 : vm_stack_flags)
-#endif
-
-#define VM_DATA_DEFAULT_FLAGS vm_data_default_flags
-
-#define VM_STACK_DEFAULT_FLAGS vm_stack_flags
-
-#endif
diff --git a/include/asm-um/vm86.h b/include/asm-um/vm86.h
deleted file mode 100644
index 7801f82de1f4..000000000000
--- a/include/asm-um/vm86.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_VM86_H
-#define __UM_VM86_H
-
-#include "asm/arch/vm86.h"
-
-#endif
diff --git a/include/asm-um/xor.h b/include/asm-um/xor.h
deleted file mode 100644
index a19db3e17241..000000000000
--- a/include/asm-um/xor.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_XOR_H
-#define __UM_XOR_H
-
-#include "asm-generic/xor.h"
-
-#endif
diff --git a/include/asm-x86/Kbuild b/include/asm-x86/Kbuild
deleted file mode 100644
index 4a8e80cdcfa5..000000000000
--- a/include/asm-x86/Kbuild
+++ /dev/null
@@ -1,24 +0,0 @@
-include include/asm-generic/Kbuild.asm
-
-header-y += boot.h
-header-y += bootparam.h
-header-y += debugreg.h
-header-y += ldt.h
-header-y += msr-index.h
-header-y += prctl.h
-header-y += ptrace-abi.h
-header-y += sigcontext32.h
-header-y += ucontext.h
-header-y += processor-flags.h
-
-unifdef-y += e820.h
-unifdef-y += ist.h
-unifdef-y += mce.h
-unifdef-y += msr.h
-unifdef-y += mtrr.h
-unifdef-y += posix_types_32.h
-unifdef-y += posix_types_64.h
-unifdef-y += unistd_32.h
-unifdef-y += unistd_64.h
-unifdef-y += vm86.h
-unifdef-y += vsyscall.h
diff --git a/include/asm-x86/a.out-core.h b/include/asm-x86/a.out-core.h
deleted file mode 100644
index f5705761a37b..000000000000
--- a/include/asm-x86/a.out-core.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* a.out coredump register dumper
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef ASM_X86__A_OUT_CORE_H
-#define ASM_X86__A_OUT_CORE_H
-
-#ifdef __KERNEL__
-#ifdef CONFIG_X86_32
-
-#include <linux/user.h>
-#include <linux/elfcore.h>
-
-/*
- * fill in the user structure for an a.out core dump
- */
-static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)
-{
-	u16 gs;
-
-/* changed the size calculations - should hopefully work better. lbt */
-	dump->magic = CMAGIC;
-	dump->start_code = 0;
-	dump->start_stack = regs->sp & ~(PAGE_SIZE - 1);
-	dump->u_tsize = ((unsigned long)current->mm->end_code) >> PAGE_SHIFT;
-	dump->u_dsize = ((unsigned long)(current->mm->brk + (PAGE_SIZE - 1)))
-			>> PAGE_SHIFT;
-	dump->u_dsize -= dump->u_tsize;
-	dump->u_ssize = 0;
-	dump->u_debugreg[0] = current->thread.debugreg0;
-	dump->u_debugreg[1] = current->thread.debugreg1;
-	dump->u_debugreg[2] = current->thread.debugreg2;
-	dump->u_debugreg[3] = current->thread.debugreg3;
-	dump->u_debugreg[4] = 0;
-	dump->u_debugreg[5] = 0;
-	dump->u_debugreg[6] = current->thread.debugreg6;
-	dump->u_debugreg[7] = current->thread.debugreg7;
-
-	if (dump->start_stack < TASK_SIZE)
-		dump->u_ssize = ((unsigned long)(TASK_SIZE - dump->start_stack))
-				>> PAGE_SHIFT;
-
-	dump->regs.bx = regs->bx;
-	dump->regs.cx = regs->cx;
-	dump->regs.dx = regs->dx;
-	dump->regs.si = regs->si;
-	dump->regs.di = regs->di;
-	dump->regs.bp = regs->bp;
-	dump->regs.ax = regs->ax;
-	dump->regs.ds = (u16)regs->ds;
-	dump->regs.es = (u16)regs->es;
-	dump->regs.fs = (u16)regs->fs;
-	savesegment(gs, gs);
-	dump->regs.orig_ax = regs->orig_ax;
-	dump->regs.ip = regs->ip;
-	dump->regs.cs = (u16)regs->cs;
-	dump->regs.flags = regs->flags;
-	dump->regs.sp = regs->sp;
-	dump->regs.ss = (u16)regs->ss;
-
-	dump->u_fpvalid = dump_fpu(regs, &dump->i387);
-}
-
-#endif /* CONFIG_X86_32 */
-#endif /* __KERNEL__ */
-#endif /* ASM_X86__A_OUT_CORE_H */
diff --git a/include/asm-x86/a.out.h b/include/asm-x86/a.out.h
deleted file mode 100644
index 0948748bc69c..000000000000
--- a/include/asm-x86/a.out.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef ASM_X86__A_OUT_H
-#define ASM_X86__A_OUT_H
-
-struct exec
-{
-	unsigned int a_info;	/* Use macros N_MAGIC, etc for access */
-	unsigned a_text;	/* length of text, in bytes */
-	unsigned a_data;	/* length of data, in bytes */
-	unsigned a_bss;		/* length of uninitialized data area for file, in bytes */
-	unsigned a_syms;	/* length of symbol table data in file, in bytes */
-	unsigned a_entry;	/* start address */
-	unsigned a_trsize;	/* length of relocation info for text, in bytes */
-	unsigned a_drsize;	/* length of relocation info for data, in bytes */
-};
-
-#define N_TRSIZE(a)	((a).a_trsize)
-#define N_DRSIZE(a)	((a).a_drsize)
-#define N_SYMSIZE(a)	((a).a_syms)
-
-#endif /* ASM_X86__A_OUT_H */
diff --git a/include/asm-x86/acpi.h b/include/asm-x86/acpi.h
deleted file mode 100644
index 392e17336be1..000000000000
--- a/include/asm-x86/acpi.h
+++ /dev/null
@@ -1,178 +0,0 @@
-#ifndef ASM_X86__ACPI_H
-#define ASM_X86__ACPI_H
-
-/*
- *  Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
- *  Copyright (C) 2001 Patrick Mochel <mochel@osdl.org>
- *
- * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- */
-#include <acpi/pdc_intel.h>
-
-#include <asm/numa.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/mpspec.h>
-
-#define COMPILER_DEPENDENT_INT64   long long
-#define COMPILER_DEPENDENT_UINT64  unsigned long long
-
-/*
- * Calling conventions:
- *
- * ACPI_SYSTEM_XFACE        - Interfaces to host OS (handlers, threads)
- * ACPI_EXTERNAL_XFACE      - External ACPI interfaces
- * ACPI_INTERNAL_XFACE      - Internal ACPI interfaces
- * ACPI_INTERNAL_VAR_XFACE  - Internal variable-parameter list interfaces
- */
-#define ACPI_SYSTEM_XFACE
-#define ACPI_EXTERNAL_XFACE
-#define ACPI_INTERNAL_XFACE
-#define ACPI_INTERNAL_VAR_XFACE
-
-/* Asm macros */
-
-#define ACPI_ASM_MACROS
-#define BREAKPOINT3
-#define ACPI_DISABLE_IRQS() local_irq_disable()
-#define ACPI_ENABLE_IRQS()  local_irq_enable()
-#define ACPI_FLUSH_CPU_CACHE()	wbinvd()
-
-int __acpi_acquire_global_lock(unsigned int *lock);
-int __acpi_release_global_lock(unsigned int *lock);
-
-#define ACPI_ACQUIRE_GLOBAL_LOCK(facs, Acq) \
-	((Acq) = __acpi_acquire_global_lock(&facs->global_lock))
-
-#define ACPI_RELEASE_GLOBAL_LOCK(facs, Acq) \
-	((Acq) = __acpi_release_global_lock(&facs->global_lock))
-
-/*
- * Math helper asm macros
- */
-#define ACPI_DIV_64_BY_32(n_hi, n_lo, d32, q32, r32) \
-	asm("divl %2;"				     \
-	    : "=a"(q32), "=d"(r32)		     \
-	    : "r"(d32),				     \
-	     "0"(n_lo), "1"(n_hi))
-
-
-#define ACPI_SHIFT_RIGHT_64(n_hi, n_lo) \
-	asm("shrl   $1,%2	;"	\
-	    "rcrl   $1,%3;"		\
-	    : "=r"(n_hi), "=r"(n_lo)	\
-	    : "0"(n_hi), "1"(n_lo))
-
-#ifdef CONFIG_ACPI
-extern int acpi_lapic;
-extern int acpi_ioapic;
-extern int acpi_noirq;
-extern int acpi_strict;
-extern int acpi_disabled;
-extern int acpi_ht;
-extern int acpi_pci_disabled;
-extern int acpi_skip_timer_override;
-extern int acpi_use_timer_override;
-
-extern u8 acpi_sci_flags;
-extern int acpi_sci_override_gsi;
-void acpi_pic_sci_set_trigger(unsigned int, u16);
-
-static inline void disable_acpi(void)
-{
-	acpi_disabled = 1;
-	acpi_ht = 0;
-	acpi_pci_disabled = 1;
-	acpi_noirq = 1;
-}
-
-/* Fixmap pages to reserve for ACPI boot-time tables (see fixmap.h) */
-#define FIX_ACPI_PAGES 4
-
-extern int acpi_gsi_to_irq(u32 gsi, unsigned int *irq);
-
-static inline void acpi_noirq_set(void) { acpi_noirq = 1; }
-static inline void acpi_disable_pci(void)
-{
-	acpi_pci_disabled = 1;
-	acpi_noirq_set();
-}
-extern int acpi_irq_balance_set(char *str);
-
-/* routines for saving/restoring kernel state */
-extern int acpi_save_state_mem(void);
-extern void acpi_restore_state_mem(void);
-
-extern unsigned long acpi_wakeup_address;
-
-/* early initialization routine */
-extern void acpi_reserve_bootmem(void);
-
-/*
- * Check if the CPU can handle C2 and deeper
- */
-static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
-{
-	/*
-	 * Early models (<=5) of AMD Opterons are not supposed to go into
-	 * C2 state.
-	 *
-	 * Steppings 0x0A and later are good
-	 */
-	if (boot_cpu_data.x86 == 0x0F &&
-	    boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
-	    boot_cpu_data.x86_model <= 0x05 &&
-	    boot_cpu_data.x86_mask < 0x0A)
-		return 1;
-	else if (boot_cpu_has(X86_FEATURE_AMDC1E))
-		return 1;
-	else
-		return max_cstate;
-}
-
-#else /* !CONFIG_ACPI */
-
-#define acpi_lapic 0
-#define acpi_ioapic 0
-static inline void acpi_noirq_set(void) { }
-static inline void acpi_disable_pci(void) { }
-static inline void disable_acpi(void) { }
-
-#endif /* !CONFIG_ACPI */
-
-#define ARCH_HAS_POWER_INIT	1
-
-struct bootnode;
-
-#ifdef CONFIG_ACPI_NUMA
-extern int acpi_numa;
-extern int acpi_scan_nodes(unsigned long start, unsigned long end);
-#define NR_NODE_MEMBLKS (MAX_NUMNODES*2)
-extern void acpi_fake_nodes(const struct bootnode *fake_nodes,
-				   int num_nodes);
-#else
-static inline void acpi_fake_nodes(const struct bootnode *fake_nodes,
-				   int num_nodes)
-{
-}
-#endif
-
-#define acpi_unlazy_tlb(x)	leave_mm(x)
-
-#endif /* ASM_X86__ACPI_H */
diff --git a/include/asm-x86/agp.h b/include/asm-x86/agp.h
deleted file mode 100644
index 3617fd4fcdf9..000000000000
--- a/include/asm-x86/agp.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef ASM_X86__AGP_H
-#define ASM_X86__AGP_H
-
-#include <asm/pgtable.h>
-#include <asm/cacheflush.h>
-
-/*
- * Functions to keep the agpgart mappings coherent with the MMU. The
- * GART gives the CPU a physical alias of pages in memory. The alias
- * region is mapped uncacheable. Make sure there are no conflicting
- * mappings with different cachability attributes for the same
- * page. This avoids data corruption on some CPUs.
- */
-
-#define map_page_into_agp(page) set_pages_uc(page, 1)
-#define unmap_page_from_agp(page) set_pages_wb(page, 1)
-
-/*
- * Could use CLFLUSH here if the cpu supports it. But then it would
- * need to be called for each cacheline of the whole page so it may
- * not be worth it. Would need a page for it.
- */
-#define flush_agp_cache() wbinvd()
-
-/* Convert a physical address to an address suitable for the GART. */
-#define phys_to_gart(x) (x)
-#define gart_to_phys(x) (x)
-
-/* GATT allocation. Returns/accepts GATT kernel virtual address. */
-#define alloc_gatt_pages(order)		\
-	((char *)__get_free_pages(GFP_KERNEL, (order)))
-#define free_gatt_pages(table, order)	\
-	free_pages((unsigned long)(table), (order))
-
-#endif /* ASM_X86__AGP_H */
diff --git a/include/asm-x86/alternative-asm.h b/include/asm-x86/alternative-asm.h
deleted file mode 100644
index e2077d343c33..000000000000
--- a/include/asm-x86/alternative-asm.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifdef __ASSEMBLY__
-
-#ifdef CONFIG_X86_32
-# define X86_ALIGN .long
-#else
-# define X86_ALIGN .quad
-#endif
-
-#ifdef CONFIG_SMP
-	.macro LOCK_PREFIX
-1:	lock
-	.section .smp_locks,"a"
-	.align 4
-	X86_ALIGN 1b
-	.previous
-	.endm
-#else
-	.macro LOCK_PREFIX
-	.endm
-#endif
-
-#endif  /*  __ASSEMBLY__  */
diff --git a/include/asm-x86/alternative.h b/include/asm-x86/alternative.h
deleted file mode 100644
index 22d3c9862bf3..000000000000
--- a/include/asm-x86/alternative.h
+++ /dev/null
@@ -1,183 +0,0 @@
-#ifndef ASM_X86__ALTERNATIVE_H
-#define ASM_X86__ALTERNATIVE_H
-
-#include <linux/types.h>
-#include <linux/stddef.h>
-#include <asm/asm.h>
-
-/*
- * Alternative inline assembly for SMP.
- *
- * The LOCK_PREFIX macro defined here replaces the LOCK and
- * LOCK_PREFIX macros used everywhere in the source tree.
- *
- * SMP alternatives use the same data structures as the other
- * alternatives and the X86_FEATURE_UP flag to indicate the case of a
- * UP system running a SMP kernel.  The existing apply_alternatives()
- * works fine for patching a SMP kernel for UP.
- *
- * The SMP alternative tables can be kept after boot and contain both
- * UP and SMP versions of the instructions to allow switching back to
- * SMP at runtime, when hotplugging in a new CPU, which is especially
- * useful in virtualized environments.
- *
- * The very common lock prefix is handled as special case in a
- * separate table which is a pure address list without replacement ptr
- * and size information.  That keeps the table sizes small.
- */
-
-#ifdef CONFIG_SMP
-#define LOCK_PREFIX \
-		".section .smp_locks,\"a\"\n"	\
-		_ASM_ALIGN "\n"			\
-		_ASM_PTR "661f\n" /* address */	\
-		".previous\n"			\
-		"661:\n\tlock; "
-
-#else /* ! CONFIG_SMP */
-#define LOCK_PREFIX ""
-#endif
-
-/* This must be included *after* the definition of LOCK_PREFIX */
-#include <asm/cpufeature.h>
-
-struct alt_instr {
-	u8 *instr;		/* original instruction */
-	u8 *replacement;
-	u8  cpuid;		/* cpuid bit set for replacement */
-	u8  instrlen;		/* length of original instruction */
-	u8  replacementlen;	/* length of new instruction, <= instrlen */
-	u8  pad1;
-#ifdef CONFIG_X86_64
-	u32 pad2;
-#endif
-};
-
-extern void alternative_instructions(void);
-extern void apply_alternatives(struct alt_instr *start, struct alt_instr *end);
-
-struct module;
-
-#ifdef CONFIG_SMP
-extern void alternatives_smp_module_add(struct module *mod, char *name,
-					void *locks, void *locks_end,
-					void *text, void *text_end);
-extern void alternatives_smp_module_del(struct module *mod);
-extern void alternatives_smp_switch(int smp);
-#else
-static inline void alternatives_smp_module_add(struct module *mod, char *name,
-					       void *locks, void *locks_end,
-					       void *text, void *text_end) {}
-static inline void alternatives_smp_module_del(struct module *mod) {}
-static inline void alternatives_smp_switch(int smp) {}
-#endif	/* CONFIG_SMP */
-
-const unsigned char *const *find_nop_table(void);
-
-/*
- * Alternative instructions for different CPU types or capabilities.
- *
- * This allows to use optimized instructions even on generic binary
- * kernels.
- *
- * length of oldinstr must be longer or equal the length of newinstr
- * It can be padded with nops as needed.
- *
- * For non barrier like inlines please define new variants
- * without volatile and memory clobber.
- */
-#define alternative(oldinstr, newinstr, feature)			\
-	asm volatile ("661:\n\t" oldinstr "\n662:\n"			\
-		      ".section .altinstructions,\"a\"\n"		\
-		      _ASM_ALIGN "\n"					\
-		      _ASM_PTR "661b\n"		/* label */		\
-		      _ASM_PTR "663f\n"		/* new instruction */	\
-		      "	 .byte %c0\n"		/* feature bit */	\
-		      "	 .byte 662b-661b\n"	/* sourcelen */		\
-		      "	 .byte 664f-663f\n"	/* replacementlen */	\
-		      ".previous\n"					\
-		      ".section .altinstr_replacement,\"ax\"\n"		\
-		      "663:\n\t" newinstr "\n664:\n"  /* replacement */	\
-		      ".previous" :: "i" (feature) : "memory")
-
-/*
- * Alternative inline assembly with input.
- *
- * Pecularities:
- * No memory clobber here.
- * Argument numbers start with 1.
- * Best is to use constraints that are fixed size (like (%1) ... "r")
- * If you use variable sized constraints like "m" or "g" in the
- * replacement make sure to pad to the worst case length.
- */
-#define alternative_input(oldinstr, newinstr, feature, input...)	\
-	asm volatile ("661:\n\t" oldinstr "\n662:\n"			\
-		      ".section .altinstructions,\"a\"\n"		\
-		      _ASM_ALIGN "\n"					\
-		      _ASM_PTR "661b\n"		/* label */		\
-		      _ASM_PTR "663f\n"		/* new instruction */	\
-		      "	 .byte %c0\n"		/* feature bit */	\
-		      "	 .byte 662b-661b\n"	/* sourcelen */		\
-		      "	 .byte 664f-663f\n"	/* replacementlen */	\
-		      ".previous\n"					\
-		      ".section .altinstr_replacement,\"ax\"\n"		\
-		      "663:\n\t" newinstr "\n664:\n"  /* replacement */	\
-		      ".previous" :: "i" (feature), ##input)
-
-/* Like alternative_input, but with a single output argument */
-#define alternative_io(oldinstr, newinstr, feature, output, input...)	\
-	asm volatile ("661:\n\t" oldinstr "\n662:\n"			\
-		      ".section .altinstructions,\"a\"\n"		\
-		      _ASM_ALIGN "\n"					\
-		      _ASM_PTR "661b\n"		/* label */		\
-		      _ASM_PTR "663f\n"		/* new instruction */	\
-		      "	 .byte %c[feat]\n"	/* feature bit */	\
-		      "	 .byte 662b-661b\n"	/* sourcelen */		\
-		      "	 .byte 664f-663f\n"	/* replacementlen */	\
-		      ".previous\n"					\
-		      ".section .altinstr_replacement,\"ax\"\n"		\
-		      "663:\n\t" newinstr "\n664:\n"  /* replacement */ \
-		      ".previous" : output : [feat] "i" (feature), ##input)
-
-/*
- * use this macro(s) if you need more than one output parameter
- * in alternative_io
- */
-#define ASM_OUTPUT2(a, b) a, b
-
-struct paravirt_patch_site;
-#ifdef CONFIG_PARAVIRT
-void apply_paravirt(struct paravirt_patch_site *start,
-		    struct paravirt_patch_site *end);
-#else
-static inline void apply_paravirt(struct paravirt_patch_site *start,
-				  struct paravirt_patch_site *end)
-{}
-#define __parainstructions	NULL
-#define __parainstructions_end	NULL
-#endif
-
-extern void add_nops(void *insns, unsigned int len);
-
-/*
- * Clear and restore the kernel write-protection flag on the local CPU.
- * Allows the kernel to edit read-only pages.
- * Side-effect: any interrupt handler running between save and restore will have
- * the ability to write to read-only pages.
- *
- * Warning:
- * Code patching in the UP case is safe if NMIs and MCE handlers are stopped and
- * no thread can be preempted in the instructions being modified (no iret to an
- * invalid instruction possible) or if the instructions are changed from a
- * consistent state to another consistent state atomically.
- * More care must be taken when modifying code in the SMP case because of
- * Intel's errata.
- * On the local CPU you need to be protected again NMI or MCE handlers seeing an
- * inconsistent instruction while you patch.
- * The _early version expects the memory to already be RW.
- */
-
-extern void *text_poke(void *addr, const void *opcode, size_t len);
-extern void *text_poke_early(void *addr, const void *opcode, size_t len);
-
-#endif /* ASM_X86__ALTERNATIVE_H */
diff --git a/include/asm-x86/amd_iommu.h b/include/asm-x86/amd_iommu.h
deleted file mode 100644
index 041d0db7da27..000000000000
--- a/include/asm-x86/amd_iommu.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
- * Author: Joerg Roedel <joerg.roedel@amd.com>
- *         Leo Duran <leo.duran@amd.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef ASM_X86__AMD_IOMMU_H
-#define ASM_X86__AMD_IOMMU_H
-
-#include <linux/irqreturn.h>
-
-#ifdef CONFIG_AMD_IOMMU
-extern int amd_iommu_init(void);
-extern int amd_iommu_init_dma_ops(void);
-extern void amd_iommu_detect(void);
-extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
-#else
-static inline int amd_iommu_init(void) { return -ENODEV; }
-static inline void amd_iommu_detect(void) { }
-#endif
-
-#endif /* ASM_X86__AMD_IOMMU_H */
diff --git a/include/asm-x86/amd_iommu_types.h b/include/asm-x86/amd_iommu_types.h
deleted file mode 100644
index b3085869a17b..000000000000
--- a/include/asm-x86/amd_iommu_types.h
+++ /dev/null
@@ -1,404 +0,0 @@
-/*
- * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
- * Author: Joerg Roedel <joerg.roedel@amd.com>
- *         Leo Duran <leo.duran@amd.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef ASM_X86__AMD_IOMMU_TYPES_H
-#define ASM_X86__AMD_IOMMU_TYPES_H
-
-#include <linux/types.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-
-/*
- * some size calculation constants
- */
-#define DEV_TABLE_ENTRY_SIZE		32
-#define ALIAS_TABLE_ENTRY_SIZE		2
-#define RLOOKUP_TABLE_ENTRY_SIZE	(sizeof(void *))
-
-/* Length of the MMIO region for the AMD IOMMU */
-#define MMIO_REGION_LENGTH       0x4000
-
-/* Capability offsets used by the driver */
-#define MMIO_CAP_HDR_OFFSET	0x00
-#define MMIO_RANGE_OFFSET	0x0c
-#define MMIO_MISC_OFFSET	0x10
-
-/* Masks, shifts and macros to parse the device range capability */
-#define MMIO_RANGE_LD_MASK	0xff000000
-#define MMIO_RANGE_FD_MASK	0x00ff0000
-#define MMIO_RANGE_BUS_MASK	0x0000ff00
-#define MMIO_RANGE_LD_SHIFT	24
-#define MMIO_RANGE_FD_SHIFT	16
-#define MMIO_RANGE_BUS_SHIFT	8
-#define MMIO_GET_LD(x)  (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
-#define MMIO_GET_FD(x)  (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
-#define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
-#define MMIO_MSI_NUM(x)	((x) & 0x1f)
-
-/* Flag masks for the AMD IOMMU exclusion range */
-#define MMIO_EXCL_ENABLE_MASK 0x01ULL
-#define MMIO_EXCL_ALLOW_MASK  0x02ULL
-
-/* Used offsets into the MMIO space */
-#define MMIO_DEV_TABLE_OFFSET   0x0000
-#define MMIO_CMD_BUF_OFFSET     0x0008
-#define MMIO_EVT_BUF_OFFSET     0x0010
-#define MMIO_CONTROL_OFFSET     0x0018
-#define MMIO_EXCL_BASE_OFFSET   0x0020
-#define MMIO_EXCL_LIMIT_OFFSET  0x0028
-#define MMIO_CMD_HEAD_OFFSET	0x2000
-#define MMIO_CMD_TAIL_OFFSET	0x2008
-#define MMIO_EVT_HEAD_OFFSET	0x2010
-#define MMIO_EVT_TAIL_OFFSET	0x2018
-#define MMIO_STATUS_OFFSET	0x2020
-
-/* MMIO status bits */
-#define MMIO_STATUS_COM_WAIT_INT_MASK	0x04
-
-/* event logging constants */
-#define EVENT_ENTRY_SIZE	0x10
-#define EVENT_TYPE_SHIFT	28
-#define EVENT_TYPE_MASK		0xf
-#define EVENT_TYPE_ILL_DEV	0x1
-#define EVENT_TYPE_IO_FAULT	0x2
-#define EVENT_TYPE_DEV_TAB_ERR	0x3
-#define EVENT_TYPE_PAGE_TAB_ERR	0x4
-#define EVENT_TYPE_ILL_CMD	0x5
-#define EVENT_TYPE_CMD_HARD_ERR	0x6
-#define EVENT_TYPE_IOTLB_INV_TO	0x7
-#define EVENT_TYPE_INV_DEV_REQ	0x8
-#define EVENT_DEVID_MASK	0xffff
-#define EVENT_DEVID_SHIFT	0
-#define EVENT_DOMID_MASK	0xffff
-#define EVENT_DOMID_SHIFT	0
-#define EVENT_FLAGS_MASK	0xfff
-#define EVENT_FLAGS_SHIFT	0x10
-
-/* feature control bits */
-#define CONTROL_IOMMU_EN        0x00ULL
-#define CONTROL_HT_TUN_EN       0x01ULL
-#define CONTROL_EVT_LOG_EN      0x02ULL
-#define CONTROL_EVT_INT_EN      0x03ULL
-#define CONTROL_COMWAIT_EN      0x04ULL
-#define CONTROL_PASSPW_EN       0x08ULL
-#define CONTROL_RESPASSPW_EN    0x09ULL
-#define CONTROL_COHERENT_EN     0x0aULL
-#define CONTROL_ISOC_EN         0x0bULL
-#define CONTROL_CMDBUF_EN       0x0cULL
-#define CONTROL_PPFLOG_EN       0x0dULL
-#define CONTROL_PPFINT_EN       0x0eULL
-
-/* command specific defines */
-#define CMD_COMPL_WAIT          0x01
-#define CMD_INV_DEV_ENTRY       0x02
-#define CMD_INV_IOMMU_PAGES     0x03
-
-#define CMD_COMPL_WAIT_STORE_MASK	0x01
-#define CMD_COMPL_WAIT_INT_MASK		0x02
-#define CMD_INV_IOMMU_PAGES_SIZE_MASK	0x01
-#define CMD_INV_IOMMU_PAGES_PDE_MASK	0x02
-
-#define CMD_INV_IOMMU_ALL_PAGES_ADDRESS	0x7fffffffffffffffULL
-
-/* macros and definitions for device table entries */
-#define DEV_ENTRY_VALID         0x00
-#define DEV_ENTRY_TRANSLATION   0x01
-#define DEV_ENTRY_IR            0x3d
-#define DEV_ENTRY_IW            0x3e
-#define DEV_ENTRY_NO_PAGE_FAULT	0x62
-#define DEV_ENTRY_EX            0x67
-#define DEV_ENTRY_SYSMGT1       0x68
-#define DEV_ENTRY_SYSMGT2       0x69
-#define DEV_ENTRY_INIT_PASS     0xb8
-#define DEV_ENTRY_EINT_PASS     0xb9
-#define DEV_ENTRY_NMI_PASS      0xba
-#define DEV_ENTRY_LINT0_PASS    0xbe
-#define DEV_ENTRY_LINT1_PASS    0xbf
-#define DEV_ENTRY_MODE_MASK	0x07
-#define DEV_ENTRY_MODE_SHIFT	0x09
-
-/* constants to configure the command buffer */
-#define CMD_BUFFER_SIZE    8192
-#define CMD_BUFFER_ENTRIES 512
-#define MMIO_CMD_SIZE_SHIFT 56
-#define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
-
-/* constants for event buffer handling */
-#define EVT_BUFFER_SIZE		8192 /* 512 entries */
-#define EVT_LEN_MASK		(0x9ULL << 56)
-
-#define PAGE_MODE_1_LEVEL 0x01
-#define PAGE_MODE_2_LEVEL 0x02
-#define PAGE_MODE_3_LEVEL 0x03
-
-#define IOMMU_PDE_NL_0   0x000ULL
-#define IOMMU_PDE_NL_1   0x200ULL
-#define IOMMU_PDE_NL_2   0x400ULL
-#define IOMMU_PDE_NL_3   0x600ULL
-
-#define IOMMU_PTE_L2_INDEX(address) (((address) >> 30) & 0x1ffULL)
-#define IOMMU_PTE_L1_INDEX(address) (((address) >> 21) & 0x1ffULL)
-#define IOMMU_PTE_L0_INDEX(address) (((address) >> 12) & 0x1ffULL)
-
-#define IOMMU_MAP_SIZE_L1 (1ULL << 21)
-#define IOMMU_MAP_SIZE_L2 (1ULL << 30)
-#define IOMMU_MAP_SIZE_L3 (1ULL << 39)
-
-#define IOMMU_PTE_P  (1ULL << 0)
-#define IOMMU_PTE_TV (1ULL << 1)
-#define IOMMU_PTE_U  (1ULL << 59)
-#define IOMMU_PTE_FC (1ULL << 60)
-#define IOMMU_PTE_IR (1ULL << 61)
-#define IOMMU_PTE_IW (1ULL << 62)
-
-#define IOMMU_L1_PDE(address) \
-	((address) | IOMMU_PDE_NL_1 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
-#define IOMMU_L2_PDE(address) \
-	((address) | IOMMU_PDE_NL_2 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
-
-#define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
-#define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
-#define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
-#define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
-
-#define IOMMU_PROT_MASK 0x03
-#define IOMMU_PROT_IR 0x01
-#define IOMMU_PROT_IW 0x02
-
-/* IOMMU capabilities */
-#define IOMMU_CAP_IOTLB   24
-#define IOMMU_CAP_NPCACHE 26
-
-#define MAX_DOMAIN_ID 65536
-
-/* FIXME: move this macro to <linux/pci.h> */
-#define PCI_BUS(x) (((x) >> 8) & 0xff)
-
-/*
- * This structure contains generic data for  IOMMU protection domains
- * independent of their use.
- */
-struct protection_domain {
-	spinlock_t lock; /* mostly used to lock the page table*/
-	u16 id;		 /* the domain id written to the device table */
-	int mode;	 /* paging mode (0-6 levels) */
-	u64 *pt_root;	 /* page table root pointer */
-	void *priv;	 /* private data */
-};
-
-/*
- * Data container for a dma_ops specific protection domain
- */
-struct dma_ops_domain {
-	struct list_head list;
-
-	/* generic protection domain information */
-	struct protection_domain domain;
-
-	/* size of the aperture for the mappings */
-	unsigned long aperture_size;
-
-	/* address we start to search for free addresses */
-	unsigned long next_bit;
-
-	/* address allocation bitmap */
-	unsigned long *bitmap;
-
-	/*
-	 * Array of PTE pages for the aperture. In this array we save all the
-	 * leaf pages of the domain page table used for the aperture. This way
-	 * we don't need to walk the page table to find a specific PTE. We can
-	 * just calculate its address in constant time.
-	 */
-	u64 **pte_pages;
-
-	/* This will be set to true when TLB needs to be flushed */
-	bool need_flush;
-
-	/*
-	 * if this is a preallocated domain, keep the device for which it was
-	 * preallocated in this variable
-	 */
-	u16 target_dev;
-};
-
-/*
- * Structure where we save information about one hardware AMD IOMMU in the
- * system.
- */
-struct amd_iommu {
-	struct list_head list;
-
-	/* locks the accesses to the hardware */
-	spinlock_t lock;
-
-	/* Pointer to PCI device of this IOMMU */
-	struct pci_dev *dev;
-
-	/*
-	 * Capability pointer. There could be more than one IOMMU per PCI
-	 * device function if there are more than one AMD IOMMU capability
-	 * pointers.
-	 */
-	u16 cap_ptr;
-
-	/* physical address of MMIO space */
-	u64 mmio_phys;
-	/* virtual address of MMIO space */
-	u8 *mmio_base;
-
-	/* capabilities of that IOMMU read from ACPI */
-	u32 cap;
-
-	/* pci domain of this IOMMU */
-	u16 pci_seg;
-
-	/* first device this IOMMU handles. read from PCI */
-	u16 first_device;
-	/* last device this IOMMU handles. read from PCI */
-	u16 last_device;
-
-	/* start of exclusion range of that IOMMU */
-	u64 exclusion_start;
-	/* length of exclusion range of that IOMMU */
-	u64 exclusion_length;
-
-	/* command buffer virtual address */
-	u8 *cmd_buf;
-	/* size of command buffer */
-	u32 cmd_buf_size;
-
-	/* event buffer virtual address */
-	u8 *evt_buf;
-	/* size of event buffer */
-	u32 evt_buf_size;
-	/* MSI number for event interrupt */
-	u16 evt_msi_num;
-
-	/* if one, we need to send a completion wait command */
-	int need_sync;
-
-	/* true if interrupts for this IOMMU are already enabled */
-	bool int_enabled;
-
-	/* default dma_ops domain for that IOMMU */
-	struct dma_ops_domain *default_dom;
-};
-
-/*
- * List with all IOMMUs in the system. This list is not locked because it is
- * only written and read at driver initialization or suspend time
- */
-extern struct list_head amd_iommu_list;
-
-/*
- * Structure defining one entry in the device table
- */
-struct dev_table_entry {
-	u32 data[8];
-};
-
-/*
- * One entry for unity mappings parsed out of the ACPI table.
- */
-struct unity_map_entry {
-	struct list_head list;
-
-	/* starting device id this entry is used for (including) */
-	u16 devid_start;
-	/* end device id this entry is used for (including) */
-	u16 devid_end;
-
-	/* start address to unity map (including) */
-	u64 address_start;
-	/* end address to unity map (including) */
-	u64 address_end;
-
-	/* required protection */
-	int prot;
-};
-
-/*
- * List of all unity mappings. It is not locked because as runtime it is only
- * read. It is created at ACPI table parsing time.
- */
-extern struct list_head amd_iommu_unity_map;
-
-/*
- * Data structures for device handling
- */
-
-/*
- * Device table used by hardware. Read and write accesses by software are
- * locked with the amd_iommu_pd_table lock.
- */
-extern struct dev_table_entry *amd_iommu_dev_table;
-
-/*
- * Alias table to find requestor ids to device ids. Not locked because only
- * read on runtime.
- */
-extern u16 *amd_iommu_alias_table;
-
-/*
- * Reverse lookup table to find the IOMMU which translates a specific device.
- */
-extern struct amd_iommu **amd_iommu_rlookup_table;
-
-/* size of the dma_ops aperture as power of 2 */
-extern unsigned amd_iommu_aperture_order;
-
-/* largest PCI device id we expect translation requests for */
-extern u16 amd_iommu_last_bdf;
-
-/* data structures for protection domain handling */
-extern struct protection_domain **amd_iommu_pd_table;
-
-/* allocation bitmap for domain ids */
-extern unsigned long *amd_iommu_pd_alloc_bitmap;
-
-/* will be 1 if device isolation is enabled */
-extern int amd_iommu_isolate;
-
-/*
- * If true, the addresses will be flushed on unmap time, not when
- * they are reused
- */
-extern bool amd_iommu_unmap_flush;
-
-/* takes a PCI device id and prints it out in a readable form */
-static inline void print_devid(u16 devid, int nl)
-{
-	int bus = devid >> 8;
-	int dev = devid >> 3 & 0x1f;
-	int fn  = devid & 0x07;
-
-	printk("%02x:%02x.%x", bus, dev, fn);
-	if (nl)
-		printk("\n");
-}
-
-/* takes bus and device/function and returns the device id
- * FIXME: should that be in generic PCI code? */
-static inline u16 calc_devid(u8 bus, u8 devfn)
-{
-	return (((u16)bus) << 8) | devfn;
-}
-
-#endif /* ASM_X86__AMD_IOMMU_TYPES_H */
diff --git a/include/asm-x86/apic.h b/include/asm-x86/apic.h
deleted file mode 100644
index d76a0839abe9..000000000000
--- a/include/asm-x86/apic.h
+++ /dev/null
@@ -1,187 +0,0 @@
-#ifndef ASM_X86__APIC_H
-#define ASM_X86__APIC_H
-
-#include <linux/pm.h>
-#include <linux/delay.h>
-
-#include <asm/alternative.h>
-#include <asm/fixmap.h>
-#include <asm/apicdef.h>
-#include <asm/processor.h>
-#include <asm/system.h>
-#include <asm/cpufeature.h>
-#include <asm/msr.h>
-
-#define ARCH_APICTIMER_STOPS_ON_C3	1
-
-/*
- * Debugging macros
- */
-#define APIC_QUIET   0
-#define APIC_VERBOSE 1
-#define APIC_DEBUG   2
-
-/*
- * Define the default level of output to be very little
- * This can be turned up by using apic=verbose for more
- * information and apic=debug for _lots_ of information.
- * apic_verbosity is defined in apic.c
- */
-#define apic_printk(v, s, a...) do {       \
-		if ((v) <= apic_verbosity) \
-			printk(s, ##a);    \
-	} while (0)
-
-
-extern void generic_apic_probe(void);
-
-#ifdef CONFIG_X86_LOCAL_APIC
-
-extern unsigned int apic_verbosity;
-extern int local_apic_timer_c2_ok;
-
-extern int ioapic_force;
-
-extern int disable_apic;
-/*
- * Basic functions accessing APICs.
- */
-#ifdef CONFIG_PARAVIRT
-#include <asm/paravirt.h>
-#else
-#define setup_boot_clock setup_boot_APIC_clock
-#define setup_secondary_clock setup_secondary_APIC_clock
-#endif
-
-extern int is_vsmp_box(void);
-extern void xapic_wait_icr_idle(void);
-extern u32 safe_xapic_wait_icr_idle(void);
-extern u64 xapic_icr_read(void);
-extern void xapic_icr_write(u32, u32);
-extern int setup_profiling_timer(unsigned int);
-
-static inline void native_apic_mem_write(u32 reg, u32 v)
-{
-	volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
-
-	alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
-		       ASM_OUTPUT2("=r" (v), "=m" (*addr)),
-		       ASM_OUTPUT2("0" (v), "m" (*addr)));
-}
-
-static inline u32 native_apic_mem_read(u32 reg)
-{
-	return *((volatile u32 *)(APIC_BASE + reg));
-}
-
-static inline void native_apic_msr_write(u32 reg, u32 v)
-{
-	if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
-	    reg == APIC_LVR)
-		return;
-
-	wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
-}
-
-static inline u32 native_apic_msr_read(u32 reg)
-{
-	u32 low, high;
-
-	if (reg == APIC_DFR)
-		return -1;
-
-	rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
-	return low;
-}
-
-#ifndef CONFIG_X86_32
-extern int x2apic, x2apic_preenabled;
-extern void check_x2apic(void);
-extern void enable_x2apic(void);
-extern void enable_IR_x2apic(void);
-extern void x2apic_icr_write(u32 low, u32 id);
-#endif
-
-struct apic_ops {
-	u32 (*read)(u32 reg);
-	void (*write)(u32 reg, u32 v);
-	u64 (*icr_read)(void);
-	void (*icr_write)(u32 low, u32 high);
-	void (*wait_icr_idle)(void);
-	u32 (*safe_wait_icr_idle)(void);
-};
-
-extern struct apic_ops *apic_ops;
-
-#define apic_read (apic_ops->read)
-#define apic_write (apic_ops->write)
-#define apic_icr_read (apic_ops->icr_read)
-#define apic_icr_write (apic_ops->icr_write)
-#define apic_wait_icr_idle (apic_ops->wait_icr_idle)
-#define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle)
-
-extern int get_physical_broadcast(void);
-
-#ifdef CONFIG_X86_64
-static inline void ack_x2APIC_irq(void)
-{
-	/* Docs say use 0 for future compatibility */
-	native_apic_msr_write(APIC_EOI, 0);
-}
-#endif
-
-
-static inline void ack_APIC_irq(void)
-{
-	/*
-	 * ack_APIC_irq() actually gets compiled as a single instruction
-	 * ... yummie.
-	 */
-
-	/* Docs say use 0 for future compatibility */
-	apic_write(APIC_EOI, 0);
-}
-
-extern int lapic_get_maxlvt(void);
-extern void clear_local_APIC(void);
-extern void connect_bsp_APIC(void);
-extern void disconnect_bsp_APIC(int virt_wire_setup);
-extern void disable_local_APIC(void);
-extern void lapic_shutdown(void);
-extern int verify_local_APIC(void);
-extern void cache_APIC_registers(void);
-extern void sync_Arb_IDs(void);
-extern void init_bsp_APIC(void);
-extern void setup_local_APIC(void);
-extern void end_local_APIC_setup(void);
-extern void init_apic_mappings(void);
-extern void setup_boot_APIC_clock(void);
-extern void setup_secondary_APIC_clock(void);
-extern int APIC_init_uniprocessor(void);
-extern void enable_NMI_through_LVT0(void);
-
-/*
- * On 32bit this is mach-xxx local
- */
-#ifdef CONFIG_X86_64
-extern void early_init_lapic_mapping(void);
-extern int apic_is_clustered_box(void);
-#else
-static inline int apic_is_clustered_box(void)
-{
-	return 0;
-}
-#endif
-
-extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
-extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
-
-
-#else /* !CONFIG_X86_LOCAL_APIC */
-static inline void lapic_shutdown(void) { }
-#define local_apic_timer_c2_ok		1
-static inline void init_apic_mappings(void) { }
-
-#endif /* !CONFIG_X86_LOCAL_APIC */
-
-#endif /* ASM_X86__APIC_H */
diff --git a/include/asm-x86/apicdef.h b/include/asm-x86/apicdef.h
deleted file mode 100644
index b922c85ac91d..000000000000
--- a/include/asm-x86/apicdef.h
+++ /dev/null
@@ -1,417 +0,0 @@
-#ifndef ASM_X86__APICDEF_H
-#define ASM_X86__APICDEF_H
-
-/*
- * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
- *
- * Alan Cox <Alan.Cox@linux.org>, 1995.
- * Ingo Molnar <mingo@redhat.com>, 1999, 2000
- */
-
-#define	APIC_DEFAULT_PHYS_BASE	0xfee00000
-
-#define	APIC_ID		0x20
-
-#define	APIC_LVR	0x30
-#define		APIC_LVR_MASK		0xFF00FF
-#define		GET_APIC_VERSION(x)	((x) & 0xFFu)
-#define		GET_APIC_MAXLVT(x)	(((x) >> 16) & 0xFFu)
-#ifdef CONFIG_X86_32
-#  define	APIC_INTEGRATED(x)	((x) & 0xF0u)
-#else
-#  define	APIC_INTEGRATED(x)	(1)
-#endif
-#define		APIC_XAPIC(x)		((x) >= 0x14)
-#define	APIC_TASKPRI	0x80
-#define		APIC_TPRI_MASK		0xFFu
-#define	APIC_ARBPRI	0x90
-#define		APIC_ARBPRI_MASK	0xFFu
-#define	APIC_PROCPRI	0xA0
-#define	APIC_EOI	0xB0
-#define		APIC_EIO_ACK		0x0
-#define	APIC_RRR	0xC0
-#define	APIC_LDR	0xD0
-#define		APIC_LDR_MASK		(0xFFu << 24)
-#define		GET_APIC_LOGICAL_ID(x)	(((x) >> 24) & 0xFFu)
-#define		SET_APIC_LOGICAL_ID(x)	(((x) << 24))
-#define		APIC_ALL_CPUS		0xFFu
-#define	APIC_DFR	0xE0
-#define		APIC_DFR_CLUSTER		0x0FFFFFFFul
-#define		APIC_DFR_FLAT			0xFFFFFFFFul
-#define	APIC_SPIV	0xF0
-#define		APIC_SPIV_FOCUS_DISABLED	(1 << 9)
-#define		APIC_SPIV_APIC_ENABLED		(1 << 8)
-#define	APIC_ISR	0x100
-#define	APIC_ISR_NR     0x8     /* Number of 32 bit ISR registers. */
-#define	APIC_TMR	0x180
-#define	APIC_IRR	0x200
-#define	APIC_ESR	0x280
-#define		APIC_ESR_SEND_CS	0x00001
-#define		APIC_ESR_RECV_CS	0x00002
-#define		APIC_ESR_SEND_ACC	0x00004
-#define		APIC_ESR_RECV_ACC	0x00008
-#define		APIC_ESR_SENDILL	0x00020
-#define		APIC_ESR_RECVILL	0x00040
-#define		APIC_ESR_ILLREGA	0x00080
-#define	APIC_ICR	0x300
-#define		APIC_DEST_SELF		0x40000
-#define		APIC_DEST_ALLINC	0x80000
-#define		APIC_DEST_ALLBUT	0xC0000
-#define		APIC_ICR_RR_MASK	0x30000
-#define		APIC_ICR_RR_INVALID	0x00000
-#define		APIC_ICR_RR_INPROG	0x10000
-#define		APIC_ICR_RR_VALID	0x20000
-#define		APIC_INT_LEVELTRIG	0x08000
-#define		APIC_INT_ASSERT		0x04000
-#define		APIC_ICR_BUSY		0x01000
-#define		APIC_DEST_LOGICAL	0x00800
-#define		APIC_DEST_PHYSICAL	0x00000
-#define		APIC_DM_FIXED		0x00000
-#define		APIC_DM_LOWEST		0x00100
-#define		APIC_DM_SMI		0x00200
-#define		APIC_DM_REMRD		0x00300
-#define		APIC_DM_NMI		0x00400
-#define		APIC_DM_INIT		0x00500
-#define		APIC_DM_STARTUP		0x00600
-#define		APIC_DM_EXTINT		0x00700
-#define		APIC_VECTOR_MASK	0x000FF
-#define	APIC_ICR2	0x310
-#define		GET_APIC_DEST_FIELD(x)	(((x) >> 24) & 0xFF)
-#define		SET_APIC_DEST_FIELD(x)	((x) << 24)
-#define	APIC_LVTT	0x320
-#define	APIC_LVTTHMR	0x330
-#define	APIC_LVTPC	0x340
-#define	APIC_LVT0	0x350
-#define		APIC_LVT_TIMER_BASE_MASK	(0x3 << 18)
-#define		GET_APIC_TIMER_BASE(x)		(((x) >> 18) & 0x3)
-#define		SET_APIC_TIMER_BASE(x)		(((x) << 18))
-#define		APIC_TIMER_BASE_CLKIN		0x0
-#define		APIC_TIMER_BASE_TMBASE		0x1
-#define		APIC_TIMER_BASE_DIV		0x2
-#define		APIC_LVT_TIMER_PERIODIC		(1 << 17)
-#define		APIC_LVT_MASKED			(1 << 16)
-#define		APIC_LVT_LEVEL_TRIGGER		(1 << 15)
-#define		APIC_LVT_REMOTE_IRR		(1 << 14)
-#define		APIC_INPUT_POLARITY		(1 << 13)
-#define		APIC_SEND_PENDING		(1 << 12)
-#define		APIC_MODE_MASK			0x700
-#define		GET_APIC_DELIVERY_MODE(x)	(((x) >> 8) & 0x7)
-#define		SET_APIC_DELIVERY_MODE(x, y)	(((x) & ~0x700) | ((y) << 8))
-#define			APIC_MODE_FIXED		0x0
-#define			APIC_MODE_NMI		0x4
-#define			APIC_MODE_EXTINT	0x7
-#define	APIC_LVT1	0x360
-#define	APIC_LVTERR	0x370
-#define	APIC_TMICT	0x380
-#define	APIC_TMCCT	0x390
-#define	APIC_TDCR	0x3E0
-#define APIC_SELF_IPI	0x3F0
-#define		APIC_TDR_DIV_TMBASE	(1 << 2)
-#define		APIC_TDR_DIV_1		0xB
-#define		APIC_TDR_DIV_2		0x0
-#define		APIC_TDR_DIV_4		0x1
-#define		APIC_TDR_DIV_8		0x2
-#define		APIC_TDR_DIV_16		0x3
-#define		APIC_TDR_DIV_32		0x8
-#define		APIC_TDR_DIV_64		0x9
-#define		APIC_TDR_DIV_128	0xA
-#define	APIC_EILVT0     0x500
-#define		APIC_EILVT_NR_AMD_K8	1	/* # of extended interrupts */
-#define		APIC_EILVT_NR_AMD_10H	4
-#define		APIC_EILVT_LVTOFF(x)	(((x) >> 4) & 0xF)
-#define		APIC_EILVT_MSG_FIX	0x0
-#define		APIC_EILVT_MSG_SMI	0x2
-#define		APIC_EILVT_MSG_NMI	0x4
-#define		APIC_EILVT_MSG_EXT	0x7
-#define		APIC_EILVT_MASKED	(1 << 16)
-#define	APIC_EILVT1     0x510
-#define	APIC_EILVT2     0x520
-#define	APIC_EILVT3     0x530
-
-#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
-#define APIC_BASE_MSR	0x800
-#define X2APIC_ENABLE	(1UL << 10)
-
-#ifdef CONFIG_X86_32
-# define MAX_IO_APICS 64
-#else
-# define MAX_IO_APICS 128
-# define MAX_LOCAL_APIC 32768
-#endif
-
-/*
- * All x86-64 systems are xAPIC compatible.
- * In the following, "apicid" is a physical APIC ID.
- */
-#define XAPIC_DEST_CPUS_SHIFT	4
-#define XAPIC_DEST_CPUS_MASK	((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
-#define XAPIC_DEST_CLUSTER_MASK	(XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
-#define APIC_CLUSTER(apicid)	((apicid) & XAPIC_DEST_CLUSTER_MASK)
-#define APIC_CLUSTERID(apicid)	(APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
-#define APIC_CPUID(apicid)	((apicid) & XAPIC_DEST_CPUS_MASK)
-#define NUM_APIC_CLUSTERS	((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
-
-/*
- * the local APIC register structure, memory mapped. Not terribly well
- * tested, but we might eventually use this one in the future - the
- * problem why we cannot use it right now is the P5 APIC, it has an
- * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
- */
-#define u32 unsigned int
-
-struct local_apic {
-
-/*000*/	struct { u32 __reserved[4]; } __reserved_01;
-
-/*010*/	struct { u32 __reserved[4]; } __reserved_02;
-
-/*020*/	struct { /* APIC ID Register */
-		u32   __reserved_1	: 24,
-			phys_apic_id	:  4,
-			__reserved_2	:  4;
-		u32 __reserved[3];
-	} id;
-
-/*030*/	const
-	struct { /* APIC Version Register */
-		u32   version		:  8,
-			__reserved_1	:  8,
-			max_lvt		:  8,
-			__reserved_2	:  8;
-		u32 __reserved[3];
-	} version;
-
-/*040*/	struct { u32 __reserved[4]; } __reserved_03;
-
-/*050*/	struct { u32 __reserved[4]; } __reserved_04;
-
-/*060*/	struct { u32 __reserved[4]; } __reserved_05;
-
-/*070*/	struct { u32 __reserved[4]; } __reserved_06;
-
-/*080*/	struct { /* Task Priority Register */
-		u32   priority	:  8,
-			__reserved_1	: 24;
-		u32 __reserved_2[3];
-	} tpr;
-
-/*090*/	const
-	struct { /* Arbitration Priority Register */
-		u32   priority	:  8,
-			__reserved_1	: 24;
-		u32 __reserved_2[3];
-	} apr;
-
-/*0A0*/	const
-	struct { /* Processor Priority Register */
-		u32   priority	:  8,
-			__reserved_1	: 24;
-		u32 __reserved_2[3];
-	} ppr;
-
-/*0B0*/	struct { /* End Of Interrupt Register */
-		u32   eoi;
-		u32 __reserved[3];
-	} eoi;
-
-/*0C0*/	struct { u32 __reserved[4]; } __reserved_07;
-
-/*0D0*/	struct { /* Logical Destination Register */
-		u32   __reserved_1	: 24,
-			logical_dest	:  8;
-		u32 __reserved_2[3];
-	} ldr;
-
-/*0E0*/	struct { /* Destination Format Register */
-		u32   __reserved_1	: 28,
-			model		:  4;
-		u32 __reserved_2[3];
-	} dfr;
-
-/*0F0*/	struct { /* Spurious Interrupt Vector Register */
-		u32	spurious_vector	:  8,
-			apic_enabled	:  1,
-			focus_cpu	:  1,
-			__reserved_2	: 22;
-		u32 __reserved_3[3];
-	} svr;
-
-/*100*/	struct { /* In Service Register */
-/*170*/		u32 bitfield;
-		u32 __reserved[3];
-	} isr [8];
-
-/*180*/	struct { /* Trigger Mode Register */
-/*1F0*/		u32 bitfield;
-		u32 __reserved[3];
-	} tmr [8];
-
-/*200*/	struct { /* Interrupt Request Register */
-/*270*/		u32 bitfield;
-		u32 __reserved[3];
-	} irr [8];
-
-/*280*/	union { /* Error Status Register */
-		struct {
-			u32   send_cs_error			:  1,
-				receive_cs_error		:  1,
-				send_accept_error		:  1,
-				receive_accept_error		:  1,
-				__reserved_1			:  1,
-				send_illegal_vector		:  1,
-				receive_illegal_vector		:  1,
-				illegal_register_address	:  1,
-				__reserved_2			: 24;
-			u32 __reserved_3[3];
-		} error_bits;
-		struct {
-			u32 errors;
-			u32 __reserved_3[3];
-		} all_errors;
-	} esr;
-
-/*290*/	struct { u32 __reserved[4]; } __reserved_08;
-
-/*2A0*/	struct { u32 __reserved[4]; } __reserved_09;
-
-/*2B0*/	struct { u32 __reserved[4]; } __reserved_10;
-
-/*2C0*/	struct { u32 __reserved[4]; } __reserved_11;
-
-/*2D0*/	struct { u32 __reserved[4]; } __reserved_12;
-
-/*2E0*/	struct { u32 __reserved[4]; } __reserved_13;
-
-/*2F0*/	struct { u32 __reserved[4]; } __reserved_14;
-
-/*300*/	struct { /* Interrupt Command Register 1 */
-		u32   vector			:  8,
-			delivery_mode		:  3,
-			destination_mode	:  1,
-			delivery_status		:  1,
-			__reserved_1		:  1,
-			level			:  1,
-			trigger			:  1,
-			__reserved_2		:  2,
-			shorthand		:  2,
-			__reserved_3		:  12;
-		u32 __reserved_4[3];
-	} icr1;
-
-/*310*/	struct { /* Interrupt Command Register 2 */
-		union {
-			u32   __reserved_1	: 24,
-				phys_dest	:  4,
-				__reserved_2	:  4;
-			u32   __reserved_3	: 24,
-				logical_dest	:  8;
-		} dest;
-		u32 __reserved_4[3];
-	} icr2;
-
-/*320*/	struct { /* LVT - Timer */
-		u32   vector		:  8,
-			__reserved_1	:  4,
-			delivery_status	:  1,
-			__reserved_2	:  3,
-			mask		:  1,
-			timer_mode	:  1,
-			__reserved_3	: 14;
-		u32 __reserved_4[3];
-	} lvt_timer;
-
-/*330*/	struct { /* LVT - Thermal Sensor */
-		u32  vector		:  8,
-			delivery_mode	:  3,
-			__reserved_1	:  1,
-			delivery_status	:  1,
-			__reserved_2	:  3,
-			mask		:  1,
-			__reserved_3	: 15;
-		u32 __reserved_4[3];
-	} lvt_thermal;
-
-/*340*/	struct { /* LVT - Performance Counter */
-		u32   vector		:  8,
-			delivery_mode	:  3,
-			__reserved_1	:  1,
-			delivery_status	:  1,
-			__reserved_2	:  3,
-			mask		:  1,
-			__reserved_3	: 15;
-		u32 __reserved_4[3];
-	} lvt_pc;
-
-/*350*/	struct { /* LVT - LINT0 */
-		u32   vector		:  8,
-			delivery_mode	:  3,
-			__reserved_1	:  1,
-			delivery_status	:  1,
-			polarity	:  1,
-			remote_irr	:  1,
-			trigger		:  1,
-			mask		:  1,
-			__reserved_2	: 15;
-		u32 __reserved_3[3];
-	} lvt_lint0;
-
-/*360*/	struct { /* LVT - LINT1 */
-		u32   vector		:  8,
-			delivery_mode	:  3,
-			__reserved_1	:  1,
-			delivery_status	:  1,
-			polarity	:  1,
-			remote_irr	:  1,
-			trigger		:  1,
-			mask		:  1,
-			__reserved_2	: 15;
-		u32 __reserved_3[3];
-	} lvt_lint1;
-
-/*370*/	struct { /* LVT - Error */
-		u32   vector		:  8,
-			__reserved_1	:  4,
-			delivery_status	:  1,
-			__reserved_2	:  3,
-			mask		:  1,
-			__reserved_3	: 15;
-		u32 __reserved_4[3];
-	} lvt_error;
-
-/*380*/	struct { /* Timer Initial Count Register */
-		u32   initial_count;
-		u32 __reserved_2[3];
-	} timer_icr;
-
-/*390*/	const
-	struct { /* Timer Current Count Register */
-		u32   curr_count;
-		u32 __reserved_2[3];
-	} timer_ccr;
-
-/*3A0*/	struct { u32 __reserved[4]; } __reserved_16;
-
-/*3B0*/	struct { u32 __reserved[4]; } __reserved_17;
-
-/*3C0*/	struct { u32 __reserved[4]; } __reserved_18;
-
-/*3D0*/	struct { u32 __reserved[4]; } __reserved_19;
-
-/*3E0*/	struct { /* Timer Divide Configuration Register */
-		u32   divisor		:  4,
-			__reserved_1	: 28;
-		u32 __reserved_2[3];
-	} timer_dcr;
-
-/*3F0*/	struct { u32 __reserved[4]; } __reserved_20;
-
-} __attribute__ ((packed));
-
-#undef u32
-
-#ifdef CONFIG_X86_32
- #define BAD_APICID 0xFFu
-#else
- #define BAD_APICID 0xFFFFu
-#endif
-#endif /* ASM_X86__APICDEF_H */
diff --git a/include/asm-x86/arch_hooks.h b/include/asm-x86/arch_hooks.h
deleted file mode 100644
index de4596b24c23..000000000000
--- a/include/asm-x86/arch_hooks.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef ASM_X86__ARCH_HOOKS_H
-#define ASM_X86__ARCH_HOOKS_H
-
-#include <linux/interrupt.h>
-
-/*
- *	linux/include/asm/arch_hooks.h
- *
- *	define the architecture specific hooks
- */
-
-/* these aren't arch hooks, they are generic routines
- * that can be used by the hooks */
-extern void init_ISA_irqs(void);
-extern irqreturn_t timer_interrupt(int irq, void *dev_id);
-
-/* these are the defined hooks */
-extern void intr_init_hook(void);
-extern void pre_intr_init_hook(void);
-extern void pre_setup_arch_hook(void);
-extern void trap_init_hook(void);
-extern void pre_time_init_hook(void);
-extern void time_init_hook(void);
-extern void mca_nmi_hook(void);
-
-#endif /* ASM_X86__ARCH_HOOKS_H */
diff --git a/include/asm-x86/asm.h b/include/asm-x86/asm.h
deleted file mode 100644
index e1355f44d7c3..000000000000
--- a/include/asm-x86/asm.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef ASM_X86__ASM_H
-#define ASM_X86__ASM_H
-
-#ifdef __ASSEMBLY__
-# define __ASM_FORM(x)	x
-# define __ASM_EX_SEC	.section __ex_table
-#else
-# define __ASM_FORM(x)	" " #x " "
-# define __ASM_EX_SEC	" .section __ex_table,\"a\"\n"
-#endif
-
-#ifdef CONFIG_X86_32
-# define __ASM_SEL(a,b) __ASM_FORM(a)
-#else
-# define __ASM_SEL(a,b) __ASM_FORM(b)
-#endif
-
-#define __ASM_SIZE(inst)	__ASM_SEL(inst##l, inst##q)
-#define __ASM_REG(reg)		__ASM_SEL(e##reg, r##reg)
-
-#define _ASM_PTR	__ASM_SEL(.long, .quad)
-#define _ASM_ALIGN	__ASM_SEL(.balign 4, .balign 8)
-
-#define _ASM_MOV	__ASM_SIZE(mov)
-#define _ASM_INC	__ASM_SIZE(inc)
-#define _ASM_DEC	__ASM_SIZE(dec)
-#define _ASM_ADD	__ASM_SIZE(add)
-#define _ASM_SUB	__ASM_SIZE(sub)
-#define _ASM_XADD	__ASM_SIZE(xadd)
-
-#define _ASM_AX		__ASM_REG(ax)
-#define _ASM_BX		__ASM_REG(bx)
-#define _ASM_CX		__ASM_REG(cx)
-#define _ASM_DX		__ASM_REG(dx)
-#define _ASM_SP		__ASM_REG(sp)
-#define _ASM_BP		__ASM_REG(bp)
-#define _ASM_SI		__ASM_REG(si)
-#define _ASM_DI		__ASM_REG(di)
-
-/* Exception table entry */
-# define _ASM_EXTABLE(from,to) \
-	__ASM_EX_SEC	\
-	_ASM_ALIGN "\n" \
-	_ASM_PTR #from "," #to "\n" \
-	" .previous\n"
-
-#endif /* ASM_X86__ASM_H */
diff --git a/include/asm-x86/atomic.h b/include/asm-x86/atomic.h
deleted file mode 100644
index 4e1b8873c474..000000000000
--- a/include/asm-x86/atomic.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifdef CONFIG_X86_32
-# include "atomic_32.h"
-#else
-# include "atomic_64.h"
-#endif
diff --git a/include/asm-x86/atomic_32.h b/include/asm-x86/atomic_32.h
deleted file mode 100644
index 14d3f0beb889..000000000000
--- a/include/asm-x86/atomic_32.h
+++ /dev/null
@@ -1,259 +0,0 @@
-#ifndef ASM_X86__ATOMIC_32_H
-#define ASM_X86__ATOMIC_32_H
-
-#include <linux/compiler.h>
-#include <asm/processor.h>
-#include <asm/cmpxchg.h>
-
-/*
- * Atomic operations that C can't guarantee us.  Useful for
- * resource counting etc..
- */
-
-/*
- * Make sure gcc doesn't try to be clever and move things around
- * on us. We need to use _exactly_ the address the user gave us,
- * not some alias that contains the same information.
- */
-typedef struct {
-	int counter;
-} atomic_t;
-
-#define ATOMIC_INIT(i)	{ (i) }
-
-/**
- * atomic_read - read atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically reads the value of @v.
- */
-#define atomic_read(v)		((v)->counter)
-
-/**
- * atomic_set - set atomic variable
- * @v: pointer of type atomic_t
- * @i: required value
- *
- * Atomically sets the value of @v to @i.
- */
-#define atomic_set(v, i)	(((v)->counter) = (i))
-
-/**
- * atomic_add - add integer to atomic variable
- * @i: integer value to add
- * @v: pointer of type atomic_t
- *
- * Atomically adds @i to @v.
- */
-static inline void atomic_add(int i, atomic_t *v)
-{
-	asm volatile(LOCK_PREFIX "addl %1,%0"
-		     : "+m" (v->counter)
-		     : "ir" (i));
-}
-
-/**
- * atomic_sub - subtract integer from atomic variable
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically subtracts @i from @v.
- */
-static inline void atomic_sub(int i, atomic_t *v)
-{
-	asm volatile(LOCK_PREFIX "subl %1,%0"
-		     : "+m" (v->counter)
-		     : "ir" (i));
-}
-
-/**
- * atomic_sub_and_test - subtract value from variable and test result
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically subtracts @i from @v and returns
- * true if the result is zero, or false for all
- * other cases.
- */
-static inline int atomic_sub_and_test(int i, atomic_t *v)
-{
-	unsigned char c;
-
-	asm volatile(LOCK_PREFIX "subl %2,%0; sete %1"
-		     : "+m" (v->counter), "=qm" (c)
-		     : "ir" (i) : "memory");
-	return c;
-}
-
-/**
- * atomic_inc - increment atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1.
- */
-static inline void atomic_inc(atomic_t *v)
-{
-	asm volatile(LOCK_PREFIX "incl %0"
-		     : "+m" (v->counter));
-}
-
-/**
- * atomic_dec - decrement atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1.
- */
-static inline void atomic_dec(atomic_t *v)
-{
-	asm volatile(LOCK_PREFIX "decl %0"
-		     : "+m" (v->counter));
-}
-
-/**
- * atomic_dec_and_test - decrement and test
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1 and
- * returns true if the result is 0, or false for all other
- * cases.
- */
-static inline int atomic_dec_and_test(atomic_t *v)
-{
-	unsigned char c;
-
-	asm volatile(LOCK_PREFIX "decl %0; sete %1"
-		     : "+m" (v->counter), "=qm" (c)
-		     : : "memory");
-	return c != 0;
-}
-
-/**
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-static inline int atomic_inc_and_test(atomic_t *v)
-{
-	unsigned char c;
-
-	asm volatile(LOCK_PREFIX "incl %0; sete %1"
-		     : "+m" (v->counter), "=qm" (c)
-		     : : "memory");
-	return c != 0;
-}
-
-/**
- * atomic_add_negative - add and test if negative
- * @v: pointer of type atomic_t
- * @i: integer value to add
- *
- * Atomically adds @i to @v and returns true
- * if the result is negative, or false when
- * result is greater than or equal to zero.
- */
-static inline int atomic_add_negative(int i, atomic_t *v)
-{
-	unsigned char c;
-
-	asm volatile(LOCK_PREFIX "addl %2,%0; sets %1"
-		     : "+m" (v->counter), "=qm" (c)
-		     : "ir" (i) : "memory");
-	return c;
-}
-
-/**
- * atomic_add_return - add integer and return
- * @v: pointer of type atomic_t
- * @i: integer value to add
- *
- * Atomically adds @i to @v and returns @i + @v
- */
-static inline int atomic_add_return(int i, atomic_t *v)
-{
-	int __i;
-#ifdef CONFIG_M386
-	unsigned long flags;
-	if (unlikely(boot_cpu_data.x86 <= 3))
-		goto no_xadd;
-#endif
-	/* Modern 486+ processor */
-	__i = i;
-	asm volatile(LOCK_PREFIX "xaddl %0, %1"
-		     : "+r" (i), "+m" (v->counter)
-		     : : "memory");
-	return i + __i;
-
-#ifdef CONFIG_M386
-no_xadd: /* Legacy 386 processor */
-	local_irq_save(flags);
-	__i = atomic_read(v);
-	atomic_set(v, i + __i);
-	local_irq_restore(flags);
-	return i + __i;
-#endif
-}
-
-/**
- * atomic_sub_return - subtract integer and return
- * @v: pointer of type atomic_t
- * @i: integer value to subtract
- *
- * Atomically subtracts @i from @v and returns @v - @i
- */
-static inline int atomic_sub_return(int i, atomic_t *v)
-{
-	return atomic_add_return(-i, v);
-}
-
-#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new)))
-#define atomic_xchg(v, new) (xchg(&((v)->counter), (new)))
-
-/**
- * atomic_add_unless - add unless the number is already a given value
- * @v: pointer of type atomic_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as @v was not already @u.
- * Returns non-zero if @v was not @u, and zero otherwise.
- */
-static inline int atomic_add_unless(atomic_t *v, int a, int u)
-{
-	int c, old;
-	c = atomic_read(v);
-	for (;;) {
-		if (unlikely(c == (u)))
-			break;
-		old = atomic_cmpxchg((v), c, c + (a));
-		if (likely(old == c))
-			break;
-		c = old;
-	}
-	return c != (u);
-}
-
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-
-#define atomic_inc_return(v)  (atomic_add_return(1, v))
-#define atomic_dec_return(v)  (atomic_sub_return(1, v))
-
-/* These are x86-specific, used by some header files */
-#define atomic_clear_mask(mask, addr)				\
-	asm volatile(LOCK_PREFIX "andl %0,%1"			\
-		     : : "r" (~(mask)), "m" (*(addr)) : "memory")
-
-#define atomic_set_mask(mask, addr)				\
-	asm volatile(LOCK_PREFIX "orl %0,%1"				\
-		     : : "r" (mask), "m" (*(addr)) : "memory")
-
-/* Atomic operations are already serializing on x86 */
-#define smp_mb__before_atomic_dec()	barrier()
-#define smp_mb__after_atomic_dec()	barrier()
-#define smp_mb__before_atomic_inc()	barrier()
-#define smp_mb__after_atomic_inc()	barrier()
-
-#include <asm-generic/atomic.h>
-#endif /* ASM_X86__ATOMIC_32_H */
diff --git a/include/asm-x86/atomic_64.h b/include/asm-x86/atomic_64.h
deleted file mode 100644
index 2cb218c4a356..000000000000
--- a/include/asm-x86/atomic_64.h
+++ /dev/null
@@ -1,473 +0,0 @@
-#ifndef ASM_X86__ATOMIC_64_H
-#define ASM_X86__ATOMIC_64_H
-
-#include <asm/alternative.h>
-#include <asm/cmpxchg.h>
-
-/* atomic_t should be 32 bit signed type */
-
-/*
- * Atomic operations that C can't guarantee us.  Useful for
- * resource counting etc..
- */
-
-/*
- * Make sure gcc doesn't try to be clever and move things around
- * on us. We need to use _exactly_ the address the user gave us,
- * not some alias that contains the same information.
- */
-typedef struct {
-	int counter;
-} atomic_t;
-
-#define ATOMIC_INIT(i)	{ (i) }
-
-/**
- * atomic_read - read atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically reads the value of @v.
- */
-#define atomic_read(v)		((v)->counter)
-
-/**
- * atomic_set - set atomic variable
- * @v: pointer of type atomic_t
- * @i: required value
- *
- * Atomically sets the value of @v to @i.
- */
-#define atomic_set(v, i)		(((v)->counter) = (i))
-
-/**
- * atomic_add - add integer to atomic variable
- * @i: integer value to add
- * @v: pointer of type atomic_t
- *
- * Atomically adds @i to @v.
- */
-static inline void atomic_add(int i, atomic_t *v)
-{
-	asm volatile(LOCK_PREFIX "addl %1,%0"
-		     : "=m" (v->counter)
-		     : "ir" (i), "m" (v->counter));
-}
-
-/**
- * atomic_sub - subtract the atomic variable
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically subtracts @i from @v.
- */
-static inline void atomic_sub(int i, atomic_t *v)
-{
-	asm volatile(LOCK_PREFIX "subl %1,%0"
-		     : "=m" (v->counter)
-		     : "ir" (i), "m" (v->counter));
-}
-
-/**
- * atomic_sub_and_test - subtract value from variable and test result
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically subtracts @i from @v and returns
- * true if the result is zero, or false for all
- * other cases.
- */
-static inline int atomic_sub_and_test(int i, atomic_t *v)
-{
-	unsigned char c;
-
-	asm volatile(LOCK_PREFIX "subl %2,%0; sete %1"
-		     : "=m" (v->counter), "=qm" (c)
-		     : "ir" (i), "m" (v->counter) : "memory");
-	return c;
-}
-
-/**
- * atomic_inc - increment atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1.
- */
-static inline void atomic_inc(atomic_t *v)
-{
-	asm volatile(LOCK_PREFIX "incl %0"
-		     : "=m" (v->counter)
-		     : "m" (v->counter));
-}
-
-/**
- * atomic_dec - decrement atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1.
- */
-static inline void atomic_dec(atomic_t *v)
-{
-	asm volatile(LOCK_PREFIX "decl %0"
-		     : "=m" (v->counter)
-		     : "m" (v->counter));
-}
-
-/**
- * atomic_dec_and_test - decrement and test
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1 and
- * returns true if the result is 0, or false for all other
- * cases.
- */
-static inline int atomic_dec_and_test(atomic_t *v)
-{
-	unsigned char c;
-
-	asm volatile(LOCK_PREFIX "decl %0; sete %1"
-		     : "=m" (v->counter), "=qm" (c)
-		     : "m" (v->counter) : "memory");
-	return c != 0;
-}
-
-/**
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-static inline int atomic_inc_and_test(atomic_t *v)
-{
-	unsigned char c;
-
-	asm volatile(LOCK_PREFIX "incl %0; sete %1"
-		     : "=m" (v->counter), "=qm" (c)
-		     : "m" (v->counter) : "memory");
-	return c != 0;
-}
-
-/**
- * atomic_add_negative - add and test if negative
- * @i: integer value to add
- * @v: pointer of type atomic_t
- *
- * Atomically adds @i to @v and returns true
- * if the result is negative, or false when
- * result is greater than or equal to zero.
- */
-static inline int atomic_add_negative(int i, atomic_t *v)
-{
-	unsigned char c;
-
-	asm volatile(LOCK_PREFIX "addl %2,%0; sets %1"
-		     : "=m" (v->counter), "=qm" (c)
-		     : "ir" (i), "m" (v->counter) : "memory");
-	return c;
-}
-
-/**
- * atomic_add_return - add and return
- * @i: integer value to add
- * @v: pointer of type atomic_t
- *
- * Atomically adds @i to @v and returns @i + @v
- */
-static inline int atomic_add_return(int i, atomic_t *v)
-{
-	int __i = i;
-	asm volatile(LOCK_PREFIX "xaddl %0, %1"
-		     : "+r" (i), "+m" (v->counter)
-		     : : "memory");
-	return i + __i;
-}
-
-static inline int atomic_sub_return(int i, atomic_t *v)
-{
-	return atomic_add_return(-i, v);
-}
-
-#define atomic_inc_return(v)  (atomic_add_return(1, v))
-#define atomic_dec_return(v)  (atomic_sub_return(1, v))
-
-/* An 64bit atomic type */
-
-typedef struct {
-	long counter;
-} atomic64_t;
-
-#define ATOMIC64_INIT(i)	{ (i) }
-
-/**
- * atomic64_read - read atomic64 variable
- * @v: pointer of type atomic64_t
- *
- * Atomically reads the value of @v.
- * Doesn't imply a read memory barrier.
- */
-#define atomic64_read(v)		((v)->counter)
-
-/**
- * atomic64_set - set atomic64 variable
- * @v: pointer to type atomic64_t
- * @i: required value
- *
- * Atomically sets the value of @v to @i.
- */
-#define atomic64_set(v, i)		(((v)->counter) = (i))
-
-/**
- * atomic64_add - add integer to atomic64 variable
- * @i: integer value to add
- * @v: pointer to type atomic64_t
- *
- * Atomically adds @i to @v.
- */
-static inline void atomic64_add(long i, atomic64_t *v)
-{
-	asm volatile(LOCK_PREFIX "addq %1,%0"
-		     : "=m" (v->counter)
-		     : "er" (i), "m" (v->counter));
-}
-
-/**
- * atomic64_sub - subtract the atomic64 variable
- * @i: integer value to subtract
- * @v: pointer to type atomic64_t
- *
- * Atomically subtracts @i from @v.
- */
-static inline void atomic64_sub(long i, atomic64_t *v)
-{
-	asm volatile(LOCK_PREFIX "subq %1,%0"
-		     : "=m" (v->counter)
-		     : "er" (i), "m" (v->counter));
-}
-
-/**
- * atomic64_sub_and_test - subtract value from variable and test result
- * @i: integer value to subtract
- * @v: pointer to type atomic64_t
- *
- * Atomically subtracts @i from @v and returns
- * true if the result is zero, or false for all
- * other cases.
- */
-static inline int atomic64_sub_and_test(long i, atomic64_t *v)
-{
-	unsigned char c;
-
-	asm volatile(LOCK_PREFIX "subq %2,%0; sete %1"
-		     : "=m" (v->counter), "=qm" (c)
-		     : "er" (i), "m" (v->counter) : "memory");
-	return c;
-}
-
-/**
- * atomic64_inc - increment atomic64 variable
- * @v: pointer to type atomic64_t
- *
- * Atomically increments @v by 1.
- */
-static inline void atomic64_inc(atomic64_t *v)
-{
-	asm volatile(LOCK_PREFIX "incq %0"
-		     : "=m" (v->counter)
-		     : "m" (v->counter));
-}
-
-/**
- * atomic64_dec - decrement atomic64 variable
- * @v: pointer to type atomic64_t
- *
- * Atomically decrements @v by 1.
- */
-static inline void atomic64_dec(atomic64_t *v)
-{
-	asm volatile(LOCK_PREFIX "decq %0"
-		     : "=m" (v->counter)
-		     : "m" (v->counter));
-}
-
-/**
- * atomic64_dec_and_test - decrement and test
- * @v: pointer to type atomic64_t
- *
- * Atomically decrements @v by 1 and
- * returns true if the result is 0, or false for all other
- * cases.
- */
-static inline int atomic64_dec_and_test(atomic64_t *v)
-{
-	unsigned char c;
-
-	asm volatile(LOCK_PREFIX "decq %0; sete %1"
-		     : "=m" (v->counter), "=qm" (c)
-		     : "m" (v->counter) : "memory");
-	return c != 0;
-}
-
-/**
- * atomic64_inc_and_test - increment and test
- * @v: pointer to type atomic64_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-static inline int atomic64_inc_and_test(atomic64_t *v)
-{
-	unsigned char c;
-
-	asm volatile(LOCK_PREFIX "incq %0; sete %1"
-		     : "=m" (v->counter), "=qm" (c)
-		     : "m" (v->counter) : "memory");
-	return c != 0;
-}
-
-/**
- * atomic64_add_negative - add and test if negative
- * @i: integer value to add
- * @v: pointer to type atomic64_t
- *
- * Atomically adds @i to @v and returns true
- * if the result is negative, or false when
- * result is greater than or equal to zero.
- */
-static inline int atomic64_add_negative(long i, atomic64_t *v)
-{
-	unsigned char c;
-
-	asm volatile(LOCK_PREFIX "addq %2,%0; sets %1"
-		     : "=m" (v->counter), "=qm" (c)
-		     : "er" (i), "m" (v->counter) : "memory");
-	return c;
-}
-
-/**
- * atomic64_add_return - add and return
- * @i: integer value to add
- * @v: pointer to type atomic64_t
- *
- * Atomically adds @i to @v and returns @i + @v
- */
-static inline long atomic64_add_return(long i, atomic64_t *v)
-{
-	long __i = i;
-	asm volatile(LOCK_PREFIX "xaddq %0, %1;"
-		     : "+r" (i), "+m" (v->counter)
-		     : : "memory");
-	return i + __i;
-}
-
-static inline long atomic64_sub_return(long i, atomic64_t *v)
-{
-	return atomic64_add_return(-i, v);
-}
-
-#define atomic64_inc_return(v)  (atomic64_add_return(1, (v)))
-#define atomic64_dec_return(v)  (atomic64_sub_return(1, (v)))
-
-#define atomic64_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new)))
-#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
-
-#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new)))
-#define atomic_xchg(v, new) (xchg(&((v)->counter), (new)))
-
-/**
- * atomic_add_unless - add unless the number is a given value
- * @v: pointer of type atomic_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as it was not @u.
- * Returns non-zero if @v was not @u, and zero otherwise.
- */
-static inline int atomic_add_unless(atomic_t *v, int a, int u)
-{
-	int c, old;
-	c = atomic_read(v);
-	for (;;) {
-		if (unlikely(c == (u)))
-			break;
-		old = atomic_cmpxchg((v), c, c + (a));
-		if (likely(old == c))
-			break;
-		c = old;
-	}
-	return c != (u);
-}
-
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-
-/**
- * atomic64_add_unless - add unless the number is a given value
- * @v: pointer of type atomic64_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as it was not @u.
- * Returns non-zero if @v was not @u, and zero otherwise.
- */
-static inline int atomic64_add_unless(atomic64_t *v, long a, long u)
-{
-	long c, old;
-	c = atomic64_read(v);
-	for (;;) {
-		if (unlikely(c == (u)))
-			break;
-		old = atomic64_cmpxchg((v), c, c + (a));
-		if (likely(old == c))
-			break;
-		c = old;
-	}
-	return c != (u);
-}
-
-/**
- * atomic_inc_short - increment of a short integer
- * @v: pointer to type int
- *
- * Atomically adds 1 to @v
- * Returns the new value of @u
- */
-static inline short int atomic_inc_short(short int *v)
-{
-	asm(LOCK_PREFIX "addw $1, %0" : "+m" (*v));
-	return *v;
-}
-
-/**
- * atomic_or_long - OR of two long integers
- * @v1: pointer to type unsigned long
- * @v2: pointer to type unsigned long
- *
- * Atomically ORs @v1 and @v2
- * Returns the result of the OR
- */
-static inline void atomic_or_long(unsigned long *v1, unsigned long v2)
-{
-	asm(LOCK_PREFIX "orq %1, %0" : "+m" (*v1) : "r" (v2));
-}
-
-#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
-
-/* These are x86-specific, used by some header files */
-#define atomic_clear_mask(mask, addr)					\
-	asm volatile(LOCK_PREFIX "andl %0,%1"				\
-		     : : "r" (~(mask)), "m" (*(addr)) : "memory")
-
-#define atomic_set_mask(mask, addr)					\
-	asm volatile(LOCK_PREFIX "orl %0,%1"				\
-		     : : "r" ((unsigned)(mask)), "m" (*(addr))		\
-		     : "memory")
-
-/* Atomic operations are already serializing on x86 */
-#define smp_mb__before_atomic_dec()	barrier()
-#define smp_mb__after_atomic_dec()	barrier()
-#define smp_mb__before_atomic_inc()	barrier()
-#define smp_mb__after_atomic_inc()	barrier()
-
-#include <asm-generic/atomic.h>
-#endif /* ASM_X86__ATOMIC_64_H */
diff --git a/include/asm-x86/auxvec.h b/include/asm-x86/auxvec.h
deleted file mode 100644
index 12c7cac74202..000000000000
--- a/include/asm-x86/auxvec.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef ASM_X86__AUXVEC_H
-#define ASM_X86__AUXVEC_H
-/*
- * Architecture-neutral AT_ values in 0-17, leave some room
- * for more of them, start the x86-specific ones at 32.
- */
-#ifdef __i386__
-#define AT_SYSINFO		32
-#endif
-#define AT_SYSINFO_EHDR		33
-
-#endif /* ASM_X86__AUXVEC_H */
diff --git a/include/asm-x86/bigsmp/apic.h b/include/asm-x86/bigsmp/apic.h
deleted file mode 100644
index 0a9cd7c5ca0c..000000000000
--- a/include/asm-x86/bigsmp/apic.h
+++ /dev/null
@@ -1,144 +0,0 @@
-#ifndef __ASM_MACH_APIC_H
-#define __ASM_MACH_APIC_H
-
-#define xapic_phys_to_log_apicid(cpu) (per_cpu(x86_bios_cpu_apicid, cpu))
-#define esr_disable (1)
-
-static inline int apic_id_registered(void)
-{
-	return (1);
-}
-
-/* Round robin the irqs amoung the online cpus */
-static inline cpumask_t target_cpus(void)
-{
-	static unsigned long cpu = NR_CPUS;
-	do {
-		if (cpu >= NR_CPUS)
-			cpu = first_cpu(cpu_online_map);
-		else
-			cpu = next_cpu(cpu, cpu_online_map);
-	} while (cpu >= NR_CPUS);
-	return cpumask_of_cpu(cpu);
-}
-
-#undef APIC_DEST_LOGICAL
-#define APIC_DEST_LOGICAL	0
-#define TARGET_CPUS		(target_cpus())
-#define APIC_DFR_VALUE		(APIC_DFR_FLAT)
-#define INT_DELIVERY_MODE	(dest_Fixed)
-#define INT_DEST_MODE		(0)    /* phys delivery to target proc */
-#define NO_BALANCE_IRQ		(0)
-#define WAKE_SECONDARY_VIA_INIT
-
-
-static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
-{
-	return (0);
-}
-
-static inline unsigned long check_apicid_present(int bit)
-{
-	return (1);
-}
-
-static inline unsigned long calculate_ldr(int cpu)
-{
-	unsigned long val, id;
-	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
-	id = xapic_phys_to_log_apicid(cpu);
-	val |= SET_APIC_LOGICAL_ID(id);
-	return val;
-}
-
-/*
- * Set up the logical destination ID.
- *
- * Intel recommends to set DFR, LDR and TPR before enabling
- * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
- * document number 292116).  So here it goes...
- */
-static inline void init_apic_ldr(void)
-{
-	unsigned long val;
-	int cpu = smp_processor_id();
-
-	apic_write(APIC_DFR, APIC_DFR_VALUE);
-	val = calculate_ldr(cpu);
-	apic_write(APIC_LDR, val);
-}
-
-static inline void setup_apic_routing(void)
-{
-	printk("Enabling APIC mode:  %s.  Using %d I/O APICs\n",
-		"Physflat", nr_ioapics);
-}
-
-static inline int multi_timer_check(int apic, int irq)
-{
-	return (0);
-}
-
-static inline int apicid_to_node(int logical_apicid)
-{
-	return apicid_2_node[hard_smp_processor_id()];
-}
-
-static inline int cpu_present_to_apicid(int mps_cpu)
-{
-	if (mps_cpu < NR_CPUS)
-		return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);
-
-	return BAD_APICID;
-}
-
-static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
-{
-	return physid_mask_of_physid(phys_apicid);
-}
-
-extern u8 cpu_2_logical_apicid[];
-/* Mapping from cpu number to logical apicid */
-static inline int cpu_to_logical_apicid(int cpu)
-{
-	if (cpu >= NR_CPUS)
-		return BAD_APICID;
-	return cpu_physical_id(cpu);
-}
-
-static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
-{
-	/* For clustered we don't have a good way to do this yet - hack */
-	return physids_promote(0xFFL);
-}
-
-static inline void setup_portio_remap(void)
-{
-}
-
-static inline void enable_apic_mode(void)
-{
-}
-
-static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
-{
-	return (1);
-}
-
-/* As we are using single CPU as destination, pick only one CPU here */
-static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
-{
-	int cpu;
-	int apicid;	
-
-	cpu = first_cpu(cpumask);
-	apicid = cpu_to_logical_apicid(cpu);
-	return apicid;
-}
-
-static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
-{
-	return cpuid_apic >> index_msb;
-}
-
-#endif /* __ASM_MACH_APIC_H */
diff --git a/include/asm-x86/bigsmp/apicdef.h b/include/asm-x86/bigsmp/apicdef.h
deleted file mode 100644
index 392c3f5ef2fe..000000000000
--- a/include/asm-x86/bigsmp/apicdef.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ASM_MACH_APICDEF_H
-#define __ASM_MACH_APICDEF_H
-
-#define		APIC_ID_MASK		(0xFF<<24)
-
-static inline unsigned get_apic_id(unsigned long x)
-{
-	return (((x)>>24)&0xFF);
-}
-
-#define		GET_APIC_ID(x)	get_apic_id(x)
-
-#endif
diff --git a/include/asm-x86/bigsmp/ipi.h b/include/asm-x86/bigsmp/ipi.h
deleted file mode 100644
index 9404c535b7ec..000000000000
--- a/include/asm-x86/bigsmp/ipi.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef __ASM_MACH_IPI_H
-#define __ASM_MACH_IPI_H
-
-void send_IPI_mask_sequence(cpumask_t mask, int vector);
-
-static inline void send_IPI_mask(cpumask_t mask, int vector)
-{
-	send_IPI_mask_sequence(mask, vector);
-}
-
-static inline void send_IPI_allbutself(int vector)
-{
-	cpumask_t mask = cpu_online_map;
-	cpu_clear(smp_processor_id(), mask);
-
-	if (!cpus_empty(mask))
-		send_IPI_mask(mask, vector);
-}
-
-static inline void send_IPI_all(int vector)
-{
-	send_IPI_mask(cpu_online_map, vector);
-}
-
-#endif /* __ASM_MACH_IPI_H */
diff --git a/include/asm-x86/bios_ebda.h b/include/asm-x86/bios_ebda.h
deleted file mode 100644
index 79b4b88505d7..000000000000
--- a/include/asm-x86/bios_ebda.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef ASM_X86__BIOS_EBDA_H
-#define ASM_X86__BIOS_EBDA_H
-
-#include <asm/io.h>
-
-/*
- * there is a real-mode segmented pointer pointing to the
- * 4K EBDA area at 0x40E.
- */
-static inline unsigned int get_bios_ebda(void)
-{
-	unsigned int address = *(unsigned short *)phys_to_virt(0x40E);
-	address <<= 4;
-	return address;	/* 0 means none */
-}
-
-void reserve_ebda_region(void);
-
-#ifdef CONFIG_X86_CHECK_BIOS_CORRUPTION
-/*
- * This is obviously not a great place for this, but we want to be
- * able to scatter it around anywhere in the kernel.
- */
-void check_for_bios_corruption(void);
-void start_periodic_check_for_corruption(void);
-#else
-static inline void check_for_bios_corruption(void)
-{
-}
-
-static inline void start_periodic_check_for_corruption(void)
-{
-}
-#endif
-
-#endif /* ASM_X86__BIOS_EBDA_H */
diff --git a/include/asm-x86/bitops.h b/include/asm-x86/bitops.h
deleted file mode 100644
index 451a74762bd4..000000000000
--- a/include/asm-x86/bitops.h
+++ /dev/null
@@ -1,451 +0,0 @@
-#ifndef ASM_X86__BITOPS_H
-#define ASM_X86__BITOPS_H
-
-/*
- * Copyright 1992, Linus Torvalds.
- */
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <linux/compiler.h>
-#include <asm/alternative.h>
-
-/*
- * These have to be done with inline assembly: that way the bit-setting
- * is guaranteed to be atomic. All bit operations return 0 if the bit
- * was cleared before the operation and != 0 if it was not.
- *
- * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
- */
-
-#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 1)
-/* Technically wrong, but this avoids compilation errors on some gcc
-   versions. */
-#define BITOP_ADDR(x) "=m" (*(volatile long *) (x))
-#else
-#define BITOP_ADDR(x) "+m" (*(volatile long *) (x))
-#endif
-
-#define ADDR				BITOP_ADDR(addr)
-
-/*
- * We do the locked ops that don't return the old value as
- * a mask operation on a byte.
- */
-#define IS_IMMEDIATE(nr)		(__builtin_constant_p(nr))
-#define CONST_MASK_ADDR(nr, addr)	BITOP_ADDR((void *)(addr) + ((nr)>>3))
-#define CONST_MASK(nr)			(1 << ((nr) & 7))
-
-/**
- * set_bit - Atomically set a bit in memory
- * @nr: the bit to set
- * @addr: the address to start counting from
- *
- * This function is atomic and may not be reordered.  See __set_bit()
- * if you do not require the atomic guarantees.
- *
- * Note: there are no guarantees that this function will not be reordered
- * on non x86 architectures, so if you are writing portable code,
- * make sure not to rely on its reordering guarantees.
- *
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static inline void set_bit(unsigned int nr, volatile unsigned long *addr)
-{
-	if (IS_IMMEDIATE(nr)) {
-		asm volatile(LOCK_PREFIX "orb %1,%0"
-			: CONST_MASK_ADDR(nr, addr)
-			: "iq" ((u8)CONST_MASK(nr))
-			: "memory");
-	} else {
-		asm volatile(LOCK_PREFIX "bts %1,%0"
-			: BITOP_ADDR(addr) : "Ir" (nr) : "memory");
-	}
-}
-
-/**
- * __set_bit - Set a bit in memory
- * @nr: the bit to set
- * @addr: the address to start counting from
- *
- * Unlike set_bit(), this function is non-atomic and may be reordered.
- * If it's called on the same region of memory simultaneously, the effect
- * may be that only one operation succeeds.
- */
-static inline void __set_bit(int nr, volatile unsigned long *addr)
-{
-	asm volatile("bts %1,%0" : ADDR : "Ir" (nr) : "memory");
-}
-
-/**
- * clear_bit - Clears a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * clear_bit() is atomic and may not be reordered.  However, it does
- * not contain a memory barrier, so if it is used for locking purposes,
- * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
- * in order to ensure changes are visible on other processors.
- */
-static inline void clear_bit(int nr, volatile unsigned long *addr)
-{
-	if (IS_IMMEDIATE(nr)) {
-		asm volatile(LOCK_PREFIX "andb %1,%0"
-			: CONST_MASK_ADDR(nr, addr)
-			: "iq" ((u8)~CONST_MASK(nr)));
-	} else {
-		asm volatile(LOCK_PREFIX "btr %1,%0"
-			: BITOP_ADDR(addr)
-			: "Ir" (nr));
-	}
-}
-
-/*
- * clear_bit_unlock - Clears a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * clear_bit() is atomic and implies release semantics before the memory
- * operation. It can be used for an unlock.
- */
-static inline void clear_bit_unlock(unsigned nr, volatile unsigned long *addr)
-{
-	barrier();
-	clear_bit(nr, addr);
-}
-
-static inline void __clear_bit(int nr, volatile unsigned long *addr)
-{
-	asm volatile("btr %1,%0" : ADDR : "Ir" (nr));
-}
-
-/*
- * __clear_bit_unlock - Clears a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * __clear_bit() is non-atomic and implies release semantics before the memory
- * operation. It can be used for an unlock if no other CPUs can concurrently
- * modify other bits in the word.
- *
- * No memory barrier is required here, because x86 cannot reorder stores past
- * older loads. Same principle as spin_unlock.
- */
-static inline void __clear_bit_unlock(unsigned nr, volatile unsigned long *addr)
-{
-	barrier();
-	__clear_bit(nr, addr);
-}
-
-#define smp_mb__before_clear_bit()	barrier()
-#define smp_mb__after_clear_bit()	barrier()
-
-/**
- * __change_bit - Toggle a bit in memory
- * @nr: the bit to change
- * @addr: the address to start counting from
- *
- * Unlike change_bit(), this function is non-atomic and may be reordered.
- * If it's called on the same region of memory simultaneously, the effect
- * may be that only one operation succeeds.
- */
-static inline void __change_bit(int nr, volatile unsigned long *addr)
-{
-	asm volatile("btc %1,%0" : ADDR : "Ir" (nr));
-}
-
-/**
- * change_bit - Toggle a bit in memory
- * @nr: Bit to change
- * @addr: Address to start counting from
- *
- * change_bit() is atomic and may not be reordered.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static inline void change_bit(int nr, volatile unsigned long *addr)
-{
-	asm volatile(LOCK_PREFIX "btc %1,%0" : ADDR : "Ir" (nr));
-}
-
-/**
- * test_and_set_bit - Set a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
-{
-	int oldbit;
-
-	asm volatile(LOCK_PREFIX "bts %2,%1\n\t"
-		     "sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory");
-
-	return oldbit;
-}
-
-/**
- * test_and_set_bit_lock - Set a bit and return its old value for lock
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This is the same as test_and_set_bit on x86.
- */
-static inline int test_and_set_bit_lock(int nr, volatile unsigned long *addr)
-{
-	return test_and_set_bit(nr, addr);
-}
-
-/**
- * __test_and_set_bit - Set a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is non-atomic and can be reordered.
- * If two examples of this operation race, one can appear to succeed
- * but actually fail.  You must protect multiple accesses with a lock.
- */
-static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
-{
-	int oldbit;
-
-	asm("bts %2,%1\n\t"
-	    "sbb %0,%0"
-	    : "=r" (oldbit), ADDR
-	    : "Ir" (nr));
-	return oldbit;
-}
-
-/**
- * test_and_clear_bit - Clear a bit and return its old value
- * @nr: Bit to clear
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
-{
-	int oldbit;
-
-	asm volatile(LOCK_PREFIX "btr %2,%1\n\t"
-		     "sbb %0,%0"
-		     : "=r" (oldbit), ADDR : "Ir" (nr) : "memory");
-
-	return oldbit;
-}
-
-/**
- * __test_and_clear_bit - Clear a bit and return its old value
- * @nr: Bit to clear
- * @addr: Address to count from
- *
- * This operation is non-atomic and can be reordered.
- * If two examples of this operation race, one can appear to succeed
- * but actually fail.  You must protect multiple accesses with a lock.
- */
-static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
-{
-	int oldbit;
-
-	asm volatile("btr %2,%1\n\t"
-		     "sbb %0,%0"
-		     : "=r" (oldbit), ADDR
-		     : "Ir" (nr));
-	return oldbit;
-}
-
-/* WARNING: non atomic and it can be reordered! */
-static inline int __test_and_change_bit(int nr, volatile unsigned long *addr)
-{
-	int oldbit;
-
-	asm volatile("btc %2,%1\n\t"
-		     "sbb %0,%0"
-		     : "=r" (oldbit), ADDR
-		     : "Ir" (nr) : "memory");
-
-	return oldbit;
-}
-
-/**
- * test_and_change_bit - Change a bit and return its old value
- * @nr: Bit to change
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
-{
-	int oldbit;
-
-	asm volatile(LOCK_PREFIX "btc %2,%1\n\t"
-		     "sbb %0,%0"
-		     : "=r" (oldbit), ADDR : "Ir" (nr) : "memory");
-
-	return oldbit;
-}
-
-static inline int constant_test_bit(int nr, const volatile unsigned long *addr)
-{
-	return ((1UL << (nr % BITS_PER_LONG)) &
-		(((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0;
-}
-
-static inline int variable_test_bit(int nr, volatile const unsigned long *addr)
-{
-	int oldbit;
-
-	asm volatile("bt %2,%1\n\t"
-		     "sbb %0,%0"
-		     : "=r" (oldbit)
-		     : "m" (*(unsigned long *)addr), "Ir" (nr));
-
-	return oldbit;
-}
-
-#if 0 /* Fool kernel-doc since it doesn't do macros yet */
-/**
- * test_bit - Determine whether a bit is set
- * @nr: bit number to test
- * @addr: Address to start counting from
- */
-static int test_bit(int nr, const volatile unsigned long *addr);
-#endif
-
-#define test_bit(nr, addr)			\
-	(__builtin_constant_p((nr))		\
-	 ? constant_test_bit((nr), (addr))	\
-	 : variable_test_bit((nr), (addr)))
-
-/**
- * __ffs - find first set bit in word
- * @word: The word to search
- *
- * Undefined if no bit exists, so code should check against 0 first.
- */
-static inline unsigned long __ffs(unsigned long word)
-{
-	asm("bsf %1,%0"
-		: "=r" (word)
-		: "rm" (word));
-	return word;
-}
-
-/**
- * ffz - find first zero bit in word
- * @word: The word to search
- *
- * Undefined if no zero exists, so code should check against ~0UL first.
- */
-static inline unsigned long ffz(unsigned long word)
-{
-	asm("bsf %1,%0"
-		: "=r" (word)
-		: "r" (~word));
-	return word;
-}
-
-/*
- * __fls: find last set bit in word
- * @word: The word to search
- *
- * Undefined if no set bit exists, so code should check against 0 first.
- */
-static inline unsigned long __fls(unsigned long word)
-{
-	asm("bsr %1,%0"
-	    : "=r" (word)
-	    : "rm" (word));
-	return word;
-}
-
-#ifdef __KERNEL__
-/**
- * ffs - find first set bit in word
- * @x: the word to search
- *
- * This is defined the same way as the libc and compiler builtin ffs
- * routines, therefore differs in spirit from the other bitops.
- *
- * ffs(value) returns 0 if value is 0 or the position of the first
- * set bit if value is nonzero. The first (least significant) bit
- * is at position 1.
- */
-static inline int ffs(int x)
-{
-	int r;
-#ifdef CONFIG_X86_CMOV
-	asm("bsfl %1,%0\n\t"
-	    "cmovzl %2,%0"
-	    : "=r" (r) : "rm" (x), "r" (-1));
-#else
-	asm("bsfl %1,%0\n\t"
-	    "jnz 1f\n\t"
-	    "movl $-1,%0\n"
-	    "1:" : "=r" (r) : "rm" (x));
-#endif
-	return r + 1;
-}
-
-/**
- * fls - find last set bit in word
- * @x: the word to search
- *
- * This is defined in a similar way as the libc and compiler builtin
- * ffs, but returns the position of the most significant set bit.
- *
- * fls(value) returns 0 if value is 0 or the position of the last
- * set bit if value is nonzero. The last (most significant) bit is
- * at position 32.
- */
-static inline int fls(int x)
-{
-	int r;
-#ifdef CONFIG_X86_CMOV
-	asm("bsrl %1,%0\n\t"
-	    "cmovzl %2,%0"
-	    : "=&r" (r) : "rm" (x), "rm" (-1));
-#else
-	asm("bsrl %1,%0\n\t"
-	    "jnz 1f\n\t"
-	    "movl $-1,%0\n"
-	    "1:" : "=r" (r) : "rm" (x));
-#endif
-	return r + 1;
-}
-#endif /* __KERNEL__ */
-
-#undef ADDR
-
-#ifdef __KERNEL__
-
-#include <asm-generic/bitops/sched.h>
-
-#define ARCH_HAS_FAST_MULTIPLIER 1
-
-#include <asm-generic/bitops/hweight.h>
-
-#endif /* __KERNEL__ */
-
-#include <asm-generic/bitops/fls64.h>
-
-#ifdef __KERNEL__
-
-#include <asm-generic/bitops/ext2-non-atomic.h>
-
-#define ext2_set_bit_atomic(lock, nr, addr)			\
-	test_and_set_bit((nr), (unsigned long *)(addr))
-#define ext2_clear_bit_atomic(lock, nr, addr)			\
-	test_and_clear_bit((nr), (unsigned long *)(addr))
-
-#include <asm-generic/bitops/minix.h>
-
-#endif /* __KERNEL__ */
-#endif /* ASM_X86__BITOPS_H */
diff --git a/include/asm-x86/boot.h b/include/asm-x86/boot.h
deleted file mode 100644
index 1d63bd5d5946..000000000000
--- a/include/asm-x86/boot.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef ASM_X86__BOOT_H
-#define ASM_X86__BOOT_H
-
-/* Don't touch these, unless you really know what you're doing. */
-#define DEF_SYSSEG	0x1000
-#define DEF_SYSSIZE	0x7F00
-
-/* Internal svga startup constants */
-#define NORMAL_VGA	0xffff		/* 80x25 mode */
-#define EXTENDED_VGA	0xfffe		/* 80x50 mode */
-#define ASK_VGA		0xfffd		/* ask for it at bootup */
-
-/* Physical address where kernel should be loaded. */
-#define LOAD_PHYSICAL_ADDR ((CONFIG_PHYSICAL_START \
-				+ (CONFIG_PHYSICAL_ALIGN - 1)) \
-				& ~(CONFIG_PHYSICAL_ALIGN - 1))
-
-#ifdef CONFIG_X86_64
-#define BOOT_HEAP_SIZE	0x7000
-#define BOOT_STACK_SIZE	0x4000
-#else
-#define BOOT_HEAP_SIZE	0x4000
-#define BOOT_STACK_SIZE	0x1000
-#endif
-
-#endif /* ASM_X86__BOOT_H */
diff --git a/include/asm-x86/bootparam.h b/include/asm-x86/bootparam.h
deleted file mode 100644
index ccf027e2d97d..000000000000
--- a/include/asm-x86/bootparam.h
+++ /dev/null
@@ -1,111 +0,0 @@
-#ifndef ASM_X86__BOOTPARAM_H
-#define ASM_X86__BOOTPARAM_H
-
-#include <linux/types.h>
-#include <linux/screen_info.h>
-#include <linux/apm_bios.h>
-#include <linux/edd.h>
-#include <asm/e820.h>
-#include <asm/ist.h>
-#include <video/edid.h>
-
-/* setup data types */
-#define SETUP_NONE			0
-#define SETUP_E820_EXT			1
-
-/* extensible setup data list node */
-struct setup_data {
-	__u64 next;
-	__u32 type;
-	__u32 len;
-	__u8 data[0];
-};
-
-struct setup_header {
-	__u8	setup_sects;
-	__u16	root_flags;
-	__u32	syssize;
-	__u16	ram_size;
-#define RAMDISK_IMAGE_START_MASK	0x07FF
-#define RAMDISK_PROMPT_FLAG		0x8000
-#define RAMDISK_LOAD_FLAG		0x4000
-	__u16	vid_mode;
-	__u16	root_dev;
-	__u16	boot_flag;
-	__u16	jump;
-	__u32	header;
-	__u16	version;
-	__u32	realmode_swtch;
-	__u16	start_sys;
-	__u16	kernel_version;
-	__u8	type_of_loader;
-	__u8	loadflags;
-#define LOADED_HIGH	(1<<0)
-#define QUIET_FLAG	(1<<5)
-#define KEEP_SEGMENTS	(1<<6)
-#define CAN_USE_HEAP	(1<<7)
-	__u16	setup_move_size;
-	__u32	code32_start;
-	__u32	ramdisk_image;
-	__u32	ramdisk_size;
-	__u32	bootsect_kludge;
-	__u16	heap_end_ptr;
-	__u16	_pad1;
-	__u32	cmd_line_ptr;
-	__u32	initrd_addr_max;
-	__u32	kernel_alignment;
-	__u8	relocatable_kernel;
-	__u8	_pad2[3];
-	__u32	cmdline_size;
-	__u32	hardware_subarch;
-	__u64	hardware_subarch_data;
-	__u32	payload_offset;
-	__u32	payload_length;
-	__u64	setup_data;
-} __attribute__((packed));
-
-struct sys_desc_table {
-	__u16 length;
-	__u8  table[14];
-};
-
-struct efi_info {
-	__u32 efi_loader_signature;
-	__u32 efi_systab;
-	__u32 efi_memdesc_size;
-	__u32 efi_memdesc_version;
-	__u32 efi_memmap;
-	__u32 efi_memmap_size;
-	__u32 efi_systab_hi;
-	__u32 efi_memmap_hi;
-};
-
-/* The so-called "zeropage" */
-struct boot_params {
-	struct screen_info screen_info;			/* 0x000 */
-	struct apm_bios_info apm_bios_info;		/* 0x040 */
-	__u8  _pad2[12];				/* 0x054 */
-	struct ist_info ist_info;			/* 0x060 */
-	__u8  _pad3[16];				/* 0x070 */
-	__u8  hd0_info[16];	/* obsolete! */		/* 0x080 */
-	__u8  hd1_info[16];	/* obsolete! */		/* 0x090 */
-	struct sys_desc_table sys_desc_table;		/* 0x0a0 */
-	__u8  _pad4[144];				/* 0x0b0 */
-	struct edid_info edid_info;			/* 0x140 */
-	struct efi_info efi_info;			/* 0x1c0 */
-	__u32 alt_mem_k;				/* 0x1e0 */
-	__u32 scratch;		/* Scratch field! */	/* 0x1e4 */
-	__u8  e820_entries;				/* 0x1e8 */
-	__u8  eddbuf_entries;				/* 0x1e9 */
-	__u8  edd_mbr_sig_buf_entries;			/* 0x1ea */
-	__u8  _pad6[6];					/* 0x1eb */
-	struct setup_header hdr;    /* setup header */	/* 0x1f1 */
-	__u8  _pad7[0x290-0x1f1-sizeof(struct setup_header)];
-	__u32 edd_mbr_sig_buffer[EDD_MBR_SIG_MAX];	/* 0x290 */
-	struct e820entry e820_map[E820MAX];		/* 0x2d0 */
-	__u8  _pad8[48];				/* 0xcd0 */
-	struct edd_info eddbuf[EDDMAXNR];		/* 0xd00 */
-	__u8  _pad9[276];				/* 0xeec */
-} __attribute__((packed));
-
-#endif /* ASM_X86__BOOTPARAM_H */
diff --git a/include/asm-x86/bug.h b/include/asm-x86/bug.h
deleted file mode 100644
index 91ad43a54c47..000000000000
--- a/include/asm-x86/bug.h
+++ /dev/null
@@ -1,39 +0,0 @@
-#ifndef ASM_X86__BUG_H
-#define ASM_X86__BUG_H
-
-#ifdef CONFIG_BUG
-#define HAVE_ARCH_BUG
-
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-
-#ifdef CONFIG_X86_32
-# define __BUG_C0	"2:\t.long 1b, %c0\n"
-#else
-# define __BUG_C0	"2:\t.quad 1b, %c0\n"
-#endif
-
-#define BUG()							\
-do {								\
-	asm volatile("1:\tud2\n"				\
-		     ".pushsection __bug_table,\"a\"\n"		\
-		     __BUG_C0					\
-		     "\t.word %c1, 0\n"				\
-		     "\t.org 2b+%c2\n"				\
-		     ".popsection"				\
-		     : : "i" (__FILE__), "i" (__LINE__),	\
-		     "i" (sizeof(struct bug_entry)));		\
-	for (;;) ;						\
-} while (0)
-
-#else
-#define BUG()							\
-do {								\
-	asm volatile("ud2");					\
-	for (;;) ;						\
-} while (0)
-#endif
-
-#endif /* !CONFIG_BUG */
-
-#include <asm-generic/bug.h>
-#endif /* ASM_X86__BUG_H */
diff --git a/include/asm-x86/bugs.h b/include/asm-x86/bugs.h
deleted file mode 100644
index dc604985f2ad..000000000000
--- a/include/asm-x86/bugs.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef ASM_X86__BUGS_H
-#define ASM_X86__BUGS_H
-
-extern void check_bugs(void);
-
-#if defined(CONFIG_CPU_SUP_INTEL) && defined(CONFIG_X86_32)
-int ppro_with_ram_bug(void);
-#else
-static inline int ppro_with_ram_bug(void) { return 0; }
-#endif
-
-#endif /* ASM_X86__BUGS_H */
diff --git a/include/asm-x86/byteorder.h b/include/asm-x86/byteorder.h
deleted file mode 100644
index 722f27d68105..000000000000
--- a/include/asm-x86/byteorder.h
+++ /dev/null
@@ -1,81 +0,0 @@
-#ifndef ASM_X86__BYTEORDER_H
-#define ASM_X86__BYTEORDER_H
-
-#include <asm/types.h>
-#include <linux/compiler.h>
-
-#ifdef __GNUC__
-
-#ifdef __i386__
-
-static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
-{
-#ifdef CONFIG_X86_BSWAP
-	asm("bswap %0" : "=r" (x) : "0" (x));
-#else
-	asm("xchgb %b0,%h0\n\t"	/* swap lower bytes	*/
-	    "rorl $16,%0\n\t"	/* swap words		*/
-	    "xchgb %b0,%h0"	/* swap higher bytes	*/
-	    : "=q" (x)
-	    : "0" (x));
-#endif
-	return x;
-}
-
-static inline __attribute_const__ __u64 ___arch__swab64(__u64 val)
-{
-	union {
-		struct {
-			__u32 a;
-			__u32 b;
-		} s;
-		__u64 u;
-	} v;
-	v.u = val;
-#ifdef CONFIG_X86_BSWAP
-	asm("bswapl %0 ; bswapl %1 ; xchgl %0,%1"
-	    : "=r" (v.s.a), "=r" (v.s.b)
-	    : "0" (v.s.a), "1" (v.s.b));
-#else
-	v.s.a = ___arch__swab32(v.s.a);
-	v.s.b = ___arch__swab32(v.s.b);
-	asm("xchgl %0,%1"
-	    : "=r" (v.s.a), "=r" (v.s.b)
-	    : "0" (v.s.a), "1" (v.s.b));
-#endif
-	return v.u;
-}
-
-#else /* __i386__ */
-
-static inline __attribute_const__ __u64 ___arch__swab64(__u64 x)
-{
-	asm("bswapq %0"
-	    : "=r" (x)
-	    : "0" (x));
-	return x;
-}
-
-static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
-{
-	asm("bswapl %0"
-	    : "=r" (x)
-	    : "0" (x));
-	return x;
-}
-
-#endif
-
-/* Do not define swab16.  Gcc is smart enough to recognize "C" version and
-   convert it into rotation or exhange.  */
-
-#define __arch__swab64(x) ___arch__swab64(x)
-#define __arch__swab32(x) ___arch__swab32(x)
-
-#define __BYTEORDER_HAS_U64__
-
-#endif /* __GNUC__ */
-
-#include <linux/byteorder/little_endian.h>
-
-#endif /* ASM_X86__BYTEORDER_H */
diff --git a/include/asm-x86/cache.h b/include/asm-x86/cache.h
deleted file mode 100644
index ea3f1cc06a97..000000000000
--- a/include/asm-x86/cache.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef ASM_X86__CACHE_H
-#define ASM_X86__CACHE_H
-
-/* L1 cache line size */
-#define L1_CACHE_SHIFT	(CONFIG_X86_L1_CACHE_SHIFT)
-#define L1_CACHE_BYTES	(1 << L1_CACHE_SHIFT)
-
-#define __read_mostly __attribute__((__section__(".data.read_mostly")))
-
-#ifdef CONFIG_X86_VSMP
-/* vSMP Internode cacheline shift */
-#define INTERNODE_CACHE_SHIFT (12)
-#ifdef CONFIG_SMP
-#define __cacheline_aligned_in_smp					\
-	__attribute__((__aligned__(1 << (INTERNODE_CACHE_SHIFT))))	\
-	__attribute__((__section__(".data.page_aligned")))
-#endif
-#endif
-
-#endif /* ASM_X86__CACHE_H */
diff --git a/include/asm-x86/cacheflush.h b/include/asm-x86/cacheflush.h
deleted file mode 100644
index 68840ef1b35a..000000000000
--- a/include/asm-x86/cacheflush.h
+++ /dev/null
@@ -1,118 +0,0 @@
-#ifndef ASM_X86__CACHEFLUSH_H
-#define ASM_X86__CACHEFLUSH_H
-
-/* Keep includes the same across arches.  */
-#include <linux/mm.h>
-
-/* Caches aren't brain-dead on the intel. */
-#define flush_cache_all()			do { } while (0)
-#define flush_cache_mm(mm)			do { } while (0)
-#define flush_cache_dup_mm(mm)			do { } while (0)
-#define flush_cache_range(vma, start, end)	do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn)	do { } while (0)
-#define flush_dcache_page(page)			do { } while (0)
-#define flush_dcache_mmap_lock(mapping)		do { } while (0)
-#define flush_dcache_mmap_unlock(mapping)	do { } while (0)
-#define flush_icache_range(start, end)		do { } while (0)
-#define flush_icache_page(vma, pg)		do { } while (0)
-#define flush_icache_user_range(vma, pg, adr, len)	do { } while (0)
-#define flush_cache_vmap(start, end)		do { } while (0)
-#define flush_cache_vunmap(start, end)		do { } while (0)
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len)	\
-	memcpy((dst), (src), (len))
-#define copy_from_user_page(vma, page, vaddr, dst, src, len)	\
-	memcpy((dst), (src), (len))
-
-#define PG_non_WB				PG_arch_1
-PAGEFLAG(NonWB, non_WB)
-
-/*
- * The set_memory_* API can be used to change various attributes of a virtual
- * address range. The attributes include:
- * Cachability   : UnCached, WriteCombining, WriteBack
- * Executability : eXeutable, NoteXecutable
- * Read/Write    : ReadOnly, ReadWrite
- * Presence      : NotPresent
- *
- * Within a catagory, the attributes are mutually exclusive.
- *
- * The implementation of this API will take care of various aspects that
- * are associated with changing such attributes, such as:
- * - Flushing TLBs
- * - Flushing CPU caches
- * - Making sure aliases of the memory behind the mapping don't violate
- *   coherency rules as defined by the CPU in the system.
- *
- * What this API does not do:
- * - Provide exclusion between various callers - including callers that
- *   operation on other mappings of the same physical page
- * - Restore default attributes when a page is freed
- * - Guarantee that mappings other than the requested one are
- *   in any state, other than that these do not violate rules for
- *   the CPU you have. Do not depend on any effects on other mappings,
- *   CPUs other than the one you have may have more relaxed rules.
- * The caller is required to take care of these.
- */
-
-int _set_memory_uc(unsigned long addr, int numpages);
-int _set_memory_wc(unsigned long addr, int numpages);
-int _set_memory_wb(unsigned long addr, int numpages);
-int set_memory_uc(unsigned long addr, int numpages);
-int set_memory_wc(unsigned long addr, int numpages);
-int set_memory_wb(unsigned long addr, int numpages);
-int set_memory_x(unsigned long addr, int numpages);
-int set_memory_nx(unsigned long addr, int numpages);
-int set_memory_ro(unsigned long addr, int numpages);
-int set_memory_rw(unsigned long addr, int numpages);
-int set_memory_np(unsigned long addr, int numpages);
-int set_memory_4k(unsigned long addr, int numpages);
-
-int set_memory_array_uc(unsigned long *addr, int addrinarray);
-int set_memory_array_wb(unsigned long *addr, int addrinarray);
-
-/*
- * For legacy compatibility with the old APIs, a few functions
- * are provided that work on a "struct page".
- * These functions operate ONLY on the 1:1 kernel mapping of the
- * memory that the struct page represents, and internally just
- * call the set_memory_* function. See the description of the
- * set_memory_* function for more details on conventions.
- *
- * These APIs should be considered *deprecated* and are likely going to
- * be removed in the future.
- * The reason for this is the implicit operation on the 1:1 mapping only,
- * making this not a generally useful API.
- *
- * Specifically, many users of the old APIs had a virtual address,
- * called virt_to_page() or vmalloc_to_page() on that address to
- * get a struct page* that the old API required.
- * To convert these cases, use set_memory_*() on the original
- * virtual address, do not use these functions.
- */
-
-int set_pages_uc(struct page *page, int numpages);
-int set_pages_wb(struct page *page, int numpages);
-int set_pages_x(struct page *page, int numpages);
-int set_pages_nx(struct page *page, int numpages);
-int set_pages_ro(struct page *page, int numpages);
-int set_pages_rw(struct page *page, int numpages);
-
-
-void clflush_cache_range(void *addr, unsigned int size);
-
-#ifdef CONFIG_DEBUG_RODATA
-void mark_rodata_ro(void);
-extern const int rodata_test_data;
-#endif
-
-#ifdef CONFIG_DEBUG_RODATA_TEST
-int rodata_test(void);
-#else
-static inline int rodata_test(void)
-{
-	return 0;
-}
-#endif
-
-#endif /* ASM_X86__CACHEFLUSH_H */
diff --git a/include/asm-x86/calgary.h b/include/asm-x86/calgary.h
deleted file mode 100644
index 933fd272f826..000000000000
--- a/include/asm-x86/calgary.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Derived from include/asm-powerpc/iommu.h
- *
- * Copyright IBM Corporation, 2006-2007
- *
- * Author: Jon Mason <jdmason@us.ibm.com>
- * Author: Muli Ben-Yehuda <muli@il.ibm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef ASM_X86__CALGARY_H
-#define ASM_X86__CALGARY_H
-
-#include <linux/spinlock.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/timer.h>
-#include <asm/types.h>
-
-struct iommu_table {
-	struct cal_chipset_ops *chip_ops; /* chipset specific funcs */
-	unsigned long  it_base;      /* mapped address of tce table */
-	unsigned long  it_hint;      /* Hint for next alloc */
-	unsigned long *it_map;       /* A simple allocation bitmap for now */
-	void __iomem  *bbar;         /* Bridge BAR */
-	u64	       tar_val;      /* Table Address Register */
-	struct timer_list watchdog_timer;
-	spinlock_t     it_lock;      /* Protects it_map */
-	unsigned int   it_size;      /* Size of iommu table in entries */
-	unsigned char  it_busno;     /* Bus number this table belongs to */
-};
-
-struct cal_chipset_ops {
-	void (*handle_quirks)(struct iommu_table *tbl, struct pci_dev *dev);
-	void (*tce_cache_blast)(struct iommu_table *tbl);
-	void (*dump_error_regs)(struct iommu_table *tbl);
-};
-
-#define TCE_TABLE_SIZE_UNSPECIFIED	~0
-#define TCE_TABLE_SIZE_64K		0
-#define TCE_TABLE_SIZE_128K		1
-#define TCE_TABLE_SIZE_256K		2
-#define TCE_TABLE_SIZE_512K		3
-#define TCE_TABLE_SIZE_1M		4
-#define TCE_TABLE_SIZE_2M		5
-#define TCE_TABLE_SIZE_4M		6
-#define TCE_TABLE_SIZE_8M		7
-
-extern int use_calgary;
-
-#ifdef CONFIG_CALGARY_IOMMU
-extern int calgary_iommu_init(void);
-extern void detect_calgary(void);
-#else
-static inline int calgary_iommu_init(void) { return 1; }
-static inline void detect_calgary(void) { return; }
-#endif
-
-#endif /* ASM_X86__CALGARY_H */
diff --git a/include/asm-x86/calling.h b/include/asm-x86/calling.h
deleted file mode 100644
index 2bc162e0ec6e..000000000000
--- a/include/asm-x86/calling.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Some macros to handle stack frames in assembly.
- */
-
-#define R15		  0
-#define R14		  8
-#define R13		 16
-#define R12		 24
-#define RBP		 32
-#define RBX		 40
-
-/* arguments: interrupts/non tracing syscalls only save upto here*/
-#define R11		 48
-#define R10		 56
-#define R9		 64
-#define R8		 72
-#define RAX		 80
-#define RCX		 88
-#define RDX		 96
-#define RSI		104
-#define RDI		112
-#define ORIG_RAX	120       /* + error_code */
-/* end of arguments */
-
-/* cpu exception frame or undefined in case of fast syscall. */
-#define RIP		128
-#define CS		136
-#define EFLAGS		144
-#define RSP		152
-#define SS		160
-
-#define ARGOFFSET	R11
-#define SWFRAME		ORIG_RAX
-
-	.macro SAVE_ARGS addskip=0, norcx=0, nor891011=0
-	subq  $9*8+\addskip, %rsp
-	CFI_ADJUST_CFA_OFFSET	9*8+\addskip
-	movq  %rdi, 8*8(%rsp)
-	CFI_REL_OFFSET	rdi, 8*8
-	movq  %rsi, 7*8(%rsp)
-	CFI_REL_OFFSET	rsi, 7*8
-	movq  %rdx, 6*8(%rsp)
-	CFI_REL_OFFSET	rdx, 6*8
-	.if \norcx
-	.else
-	movq  %rcx, 5*8(%rsp)
-	CFI_REL_OFFSET	rcx, 5*8
-	.endif
-	movq  %rax, 4*8(%rsp)
-	CFI_REL_OFFSET	rax, 4*8
-	.if \nor891011
-	.else
-	movq  %r8, 3*8(%rsp)
-	CFI_REL_OFFSET	r8,  3*8
-	movq  %r9, 2*8(%rsp)
-	CFI_REL_OFFSET	r9,  2*8
-	movq  %r10, 1*8(%rsp)
-	CFI_REL_OFFSET	r10, 1*8
-	movq  %r11, (%rsp)
-	CFI_REL_OFFSET	r11, 0*8
-	.endif
-	.endm
-
-#define ARG_SKIP	9*8
-
-	.macro RESTORE_ARGS skiprax=0, addskip=0, skiprcx=0, skipr11=0, \
-			    skipr8910=0, skiprdx=0
-	.if \skipr11
-	.else
-	movq (%rsp), %r11
-	CFI_RESTORE r11
-	.endif
-	.if \skipr8910
-	.else
-	movq 1*8(%rsp), %r10
-	CFI_RESTORE r10
-	movq 2*8(%rsp), %r9
-	CFI_RESTORE r9
-	movq 3*8(%rsp), %r8
-	CFI_RESTORE r8
-	.endif
-	.if \skiprax
-	.else
-	movq 4*8(%rsp), %rax
-	CFI_RESTORE rax
-	.endif
-	.if \skiprcx
-	.else
-	movq 5*8(%rsp), %rcx
-	CFI_RESTORE rcx
-	.endif
-	.if \skiprdx
-	.else
-	movq 6*8(%rsp), %rdx
-	CFI_RESTORE rdx
-	.endif
-	movq 7*8(%rsp), %rsi
-	CFI_RESTORE rsi
-	movq 8*8(%rsp), %rdi
-	CFI_RESTORE rdi
-	.if ARG_SKIP+\addskip > 0
-	addq $ARG_SKIP+\addskip, %rsp
-	CFI_ADJUST_CFA_OFFSET	-(ARG_SKIP+\addskip)
-	.endif
-	.endm
-
-	.macro LOAD_ARGS offset, skiprax=0
-	movq \offset(%rsp),    %r11
-	movq \offset+8(%rsp),  %r10
-	movq \offset+16(%rsp), %r9
-	movq \offset+24(%rsp), %r8
-	movq \offset+40(%rsp), %rcx
-	movq \offset+48(%rsp), %rdx
-	movq \offset+56(%rsp), %rsi
-	movq \offset+64(%rsp), %rdi
-	.if \skiprax
-	.else
-	movq \offset+72(%rsp), %rax
-	.endif
-	.endm
-
-#define REST_SKIP	6*8
-
-	.macro SAVE_REST
-	subq $REST_SKIP, %rsp
-	CFI_ADJUST_CFA_OFFSET	REST_SKIP
-	movq %rbx, 5*8(%rsp)
-	CFI_REL_OFFSET	rbx, 5*8
-	movq %rbp, 4*8(%rsp)
-	CFI_REL_OFFSET	rbp, 4*8
-	movq %r12, 3*8(%rsp)
-	CFI_REL_OFFSET	r12, 3*8
-	movq %r13, 2*8(%rsp)
-	CFI_REL_OFFSET	r13, 2*8
-	movq %r14, 1*8(%rsp)
-	CFI_REL_OFFSET	r14, 1*8
-	movq %r15, (%rsp)
-	CFI_REL_OFFSET	r15, 0*8
-	.endm
-
-	.macro RESTORE_REST
-	movq (%rsp),     %r15
-	CFI_RESTORE r15
-	movq 1*8(%rsp),  %r14
-	CFI_RESTORE r14
-	movq 2*8(%rsp),  %r13
-	CFI_RESTORE r13
-	movq 3*8(%rsp),  %r12
-	CFI_RESTORE r12
-	movq 4*8(%rsp),  %rbp
-	CFI_RESTORE rbp
-	movq 5*8(%rsp),  %rbx
-	CFI_RESTORE rbx
-	addq $REST_SKIP, %rsp
-	CFI_ADJUST_CFA_OFFSET	-(REST_SKIP)
-	.endm
-
-	.macro SAVE_ALL
-	SAVE_ARGS
-	SAVE_REST
-	.endm
-
-	.macro RESTORE_ALL addskip=0
-	RESTORE_REST
-	RESTORE_ARGS 0, \addskip
-	.endm
-
-	.macro icebp
-	.byte 0xf1
-	.endm
diff --git a/include/asm-x86/checksum.h b/include/asm-x86/checksum.h
deleted file mode 100644
index 848850fd7d62..000000000000
--- a/include/asm-x86/checksum.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifdef CONFIG_X86_32
-# include "checksum_32.h"
-#else
-# include "checksum_64.h"
-#endif
diff --git a/include/asm-x86/checksum_32.h b/include/asm-x86/checksum_32.h
deleted file mode 100644
index d041e8cda227..000000000000
--- a/include/asm-x86/checksum_32.h
+++ /dev/null
@@ -1,189 +0,0 @@
-#ifndef ASM_X86__CHECKSUM_32_H
-#define ASM_X86__CHECKSUM_32_H
-
-#include <linux/in6.h>
-
-#include <asm/uaccess.h>
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-asmlinkage __wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/*
- * the same as csum_partial, but copies from src while it
- * checksums, and handles user-space pointer exceptions correctly, when needed.
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-
-asmlinkage __wsum csum_partial_copy_generic(const void *src, void *dst,
-					    int len, __wsum sum,
-					    int *src_err_ptr, int *dst_err_ptr);
-
-/*
- *	Note: when you get a NULL pointer exception here this means someone
- *	passed in an incorrect kernel address to one of these functions.
- *
- *	If you use these functions directly please don't forget the
- *	access_ok().
- */
-static inline __wsum csum_partial_copy_nocheck(const void *src, void *dst,
-					       int len, __wsum sum)
-{
-	return csum_partial_copy_generic(src, dst, len, sum, NULL, NULL);
-}
-
-static inline __wsum csum_partial_copy_from_user(const void __user *src,
-						 void *dst,
-						 int len, __wsum sum,
-						 int *err_ptr)
-{
-	might_sleep();
-	return csum_partial_copy_generic((__force void *)src, dst,
-					 len, sum, err_ptr, NULL);
-}
-
-/*
- *	This is a version of ip_compute_csum() optimized for IP headers,
- *	which always checksum on 4 octet boundaries.
- *
- *	By Jorge Cwik <jorge@laser.satlink.net>, adapted for linux by
- *	Arnt Gulbrandsen.
- */
-static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
-{
-	unsigned int sum;
-
-	asm volatile("movl (%1), %0	;\n"
-		     "subl $4, %2	;\n"
-		     "jbe 2f		;\n"
-		     "addl 4(%1), %0	;\n"
-		     "adcl 8(%1), %0	;\n"
-		     "adcl 12(%1), %0;\n"
-		     "1:	adcl 16(%1), %0	;\n"
-		     "lea 4(%1), %1	;\n"
-		     "decl %2	;\n"
-		     "jne 1b		;\n"
-		     "adcl $0, %0	;\n"
-		     "movl %0, %2	;\n"
-		     "shrl $16, %0	;\n"
-		     "addw %w2, %w0	;\n"
-		     "adcl $0, %0	;\n"
-		     "notl %0	;\n"
-		     "2:		;\n"
-	/* Since the input registers which are loaded with iph and ihl
-	   are modified, we must also specify them as outputs, or gcc
-	   will assume they contain their original values. */
-		     : "=r" (sum), "=r" (iph), "=r" (ihl)
-		     : "1" (iph), "2" (ihl)
-		     : "memory");
-	return (__force __sum16)sum;
-}
-
-/*
- *	Fold a partial checksum
- */
-
-static inline __sum16 csum_fold(__wsum sum)
-{
-	asm("addl %1, %0		;\n"
-	    "adcl $0xffff, %0	;\n"
-	    : "=r" (sum)
-	    : "r" ((__force u32)sum << 16),
-	      "0" ((__force u32)sum & 0xffff0000));
-	return (__force __sum16)(~(__force u32)sum >> 16);
-}
-
-static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
-					unsigned short len,
-					unsigned short proto,
-					__wsum sum)
-{
-	asm("addl %1, %0	;\n"
-	    "adcl %2, %0	;\n"
-	    "adcl %3, %0	;\n"
-	    "adcl $0, %0	;\n"
-	    : "=r" (sum)
-	    : "g" (daddr), "g"(saddr),
-	      "g" ((len + proto) << 8), "0" (sum));
-	return sum;
-}
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
-					unsigned short len,
-					unsigned short proto,
-					__wsum sum)
-{
-	return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-
-static inline __sum16 ip_compute_csum(const void *buff, int len)
-{
-    return csum_fold(csum_partial(buff, len, 0));
-}
-
-#define _HAVE_ARCH_IPV6_CSUM
-static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
-				      const struct in6_addr *daddr,
-				      __u32 len, unsigned short proto,
-				      __wsum sum)
-{
-	asm("addl 0(%1), %0	;\n"
-	    "adcl 4(%1), %0	;\n"
-	    "adcl 8(%1), %0	;\n"
-	    "adcl 12(%1), %0	;\n"
-	    "adcl 0(%2), %0	;\n"
-	    "adcl 4(%2), %0	;\n"
-	    "adcl 8(%2), %0	;\n"
-	    "adcl 12(%2), %0	;\n"
-	    "adcl %3, %0	;\n"
-	    "adcl %4, %0	;\n"
-	    "adcl $0, %0	;\n"
-	    : "=&r" (sum)
-	    : "r" (saddr), "r" (daddr),
-	      "r" (htonl(len)), "r" (htonl(proto)), "0" (sum));
-
-	return csum_fold(sum);
-}
-
-/*
- *	Copy and checksum to user
- */
-#define HAVE_CSUM_COPY_USER
-static inline __wsum csum_and_copy_to_user(const void *src,
-					   void __user *dst,
-					   int len, __wsum sum,
-					   int *err_ptr)
-{
-	might_sleep();
-	if (access_ok(VERIFY_WRITE, dst, len))
-		return csum_partial_copy_generic(src, (__force void *)dst,
-						 len, sum, NULL, err_ptr);
-
-	if (len)
-		*err_ptr = -EFAULT;
-
-	return (__force __wsum)-1; /* invalid checksum */
-}
-
-#endif /* ASM_X86__CHECKSUM_32_H */
diff --git a/include/asm-x86/checksum_64.h b/include/asm-x86/checksum_64.h
deleted file mode 100644
index 110f403beb89..000000000000
--- a/include/asm-x86/checksum_64.h
+++ /dev/null
@@ -1,191 +0,0 @@
-#ifndef ASM_X86__CHECKSUM_64_H
-#define ASM_X86__CHECKSUM_64_H
-
-/*
- * Checksums for x86-64
- * Copyright 2002 by Andi Kleen, SuSE Labs
- * with some code from asm-x86/checksum.h
- */
-
-#include <linux/compiler.h>
-#include <asm/uaccess.h>
-#include <asm/byteorder.h>
-
-/**
- * csum_fold - Fold and invert a 32bit checksum.
- * sum: 32bit unfolded sum
- *
- * Fold a 32bit running checksum to 16bit and invert it. This is usually
- * the last step before putting a checksum into a packet.
- * Make sure not to mix with 64bit checksums.
- */
-static inline __sum16 csum_fold(__wsum sum)
-{
-	asm("  addl %1,%0\n"
-	    "  adcl $0xffff,%0"
-	    : "=r" (sum)
-	    : "r" ((__force u32)sum << 16),
-	      "0" ((__force u32)sum & 0xffff0000));
-	return (__force __sum16)(~(__force u32)sum >> 16);
-}
-
-/*
- *	This is a version of ip_compute_csum() optimized for IP headers,
- *	which always checksum on 4 octet boundaries.
- *
- *	By Jorge Cwik <jorge@laser.satlink.net>, adapted for linux by
- *	Arnt Gulbrandsen.
- */
-
-/**
- * ip_fast_csum - Compute the IPv4 header checksum efficiently.
- * iph: ipv4 header
- * ihl: length of header / 4
- */
-static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
-{
-	unsigned int sum;
-
-	asm("  movl (%1), %0\n"
-	    "  subl $4, %2\n"
-	    "  jbe 2f\n"
-	    "  addl 4(%1), %0\n"
-	    "  adcl 8(%1), %0\n"
-	    "  adcl 12(%1), %0\n"
-	    "1: adcl 16(%1), %0\n"
-	    "  lea 4(%1), %1\n"
-	    "  decl %2\n"
-	    "  jne	1b\n"
-	    "  adcl $0, %0\n"
-	    "  movl %0, %2\n"
-	    "  shrl $16, %0\n"
-	    "  addw %w2, %w0\n"
-	    "  adcl $0, %0\n"
-	    "  notl %0\n"
-	    "2:"
-	/* Since the input registers which are loaded with iph and ihl
-	   are modified, we must also specify them as outputs, or gcc
-	   will assume they contain their original values. */
-	    : "=r" (sum), "=r" (iph), "=r" (ihl)
-	    : "1" (iph), "2" (ihl)
-	    : "memory");
-	return (__force __sum16)sum;
-}
-
-/**
- * csum_tcpup_nofold - Compute an IPv4 pseudo header checksum.
- * @saddr: source address
- * @daddr: destination address
- * @len: length of packet
- * @proto: ip protocol of packet
- * @sum: initial sum to be added in (32bit unfolded)
- *
- * Returns the pseudo header checksum the input data. Result is
- * 32bit unfolded.
- */
-static inline __wsum
-csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
-		   unsigned short proto, __wsum sum)
-{
-	asm("  addl %1, %0\n"
-	    "  adcl %2, %0\n"
-	    "  adcl %3, %0\n"
-	    "  adcl $0, %0\n"
-	    : "=r" (sum)
-	    : "g" (daddr), "g" (saddr),
-	      "g" ((len + proto)<<8), "0" (sum));
-	return sum;
-}
-
-
-/**
- * csum_tcpup_magic - Compute an IPv4 pseudo header checksum.
- * @saddr: source address
- * @daddr: destination address
- * @len: length of packet
- * @proto: ip protocol of packet
- * @sum: initial sum to be added in (32bit unfolded)
- *
- * Returns the 16bit pseudo header checksum the input data already
- * complemented and ready to be filled in.
- */
-static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
-					unsigned short len,
-					unsigned short proto, __wsum sum)
-{
-	return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
-}
-
-/**
- * csum_partial - Compute an internet checksum.
- * @buff: buffer to be checksummed
- * @len: length of buffer.
- * @sum: initial sum to be added in (32bit unfolded)
- *
- * Returns the 32bit unfolded internet checksum of the buffer.
- * Before filling it in it needs to be csum_fold()'ed.
- * buff should be aligned to a 64bit boundary if possible.
- */
-extern __wsum csum_partial(const void *buff, int len, __wsum sum);
-
-#define  _HAVE_ARCH_COPY_AND_CSUM_FROM_USER 1
-#define HAVE_CSUM_COPY_USER 1
-
-
-/* Do not call this directly. Use the wrappers below */
-extern __wsum csum_partial_copy_generic(const void *src, const void *dst,
-					int len, __wsum sum,
-					int *src_err_ptr, int *dst_err_ptr);
-
-
-extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
-					  int len, __wsum isum, int *errp);
-extern __wsum csum_partial_copy_to_user(const void *src, void __user *dst,
-					int len, __wsum isum, int *errp);
-extern __wsum csum_partial_copy_nocheck(const void *src, void *dst,
-					int len, __wsum sum);
-
-/* Old names. To be removed. */
-#define csum_and_copy_to_user csum_partial_copy_to_user
-#define csum_and_copy_from_user csum_partial_copy_from_user
-
-/**
- * ip_compute_csum - Compute an 16bit IP checksum.
- * @buff: buffer address.
- * @len: length of buffer.
- *
- * Returns the 16bit folded/inverted checksum of the passed buffer.
- * Ready to fill in.
- */
-extern __sum16 ip_compute_csum(const void *buff, int len);
-
-/**
- * csum_ipv6_magic - Compute checksum of an IPv6 pseudo header.
- * @saddr: source address
- * @daddr: destination address
- * @len: length of packet
- * @proto: protocol of packet
- * @sum: initial sum (32bit unfolded) to be added in
- *
- * Computes an IPv6 pseudo header checksum. This sum is added the checksum
- * into UDP/TCP packets and contains some link layer information.
- * Returns the unfolded 32bit checksum.
- */
-
-struct in6_addr;
-
-#define _HAVE_ARCH_IPV6_CSUM 1
-extern __sum16
-csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr,
-		__u32 len, unsigned short proto, __wsum sum);
-
-static inline unsigned add32_with_carry(unsigned a, unsigned b)
-{
-	asm("addl %2,%0\n\t"
-	    "adcl $0,%0"
-	    : "=r" (a)
-	    : "0" (a), "r" (b));
-	return a;
-}
-
-#endif /* ASM_X86__CHECKSUM_64_H */
diff --git a/include/asm-x86/cmpxchg.h b/include/asm-x86/cmpxchg.h
deleted file mode 100644
index a460fa088d4c..000000000000
--- a/include/asm-x86/cmpxchg.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifdef CONFIG_X86_32
-# include "cmpxchg_32.h"
-#else
-# include "cmpxchg_64.h"
-#endif
diff --git a/include/asm-x86/cmpxchg_32.h b/include/asm-x86/cmpxchg_32.h
deleted file mode 100644
index 0622e45cdf7c..000000000000
--- a/include/asm-x86/cmpxchg_32.h
+++ /dev/null
@@ -1,344 +0,0 @@
-#ifndef ASM_X86__CMPXCHG_32_H
-#define ASM_X86__CMPXCHG_32_H
-
-#include <linux/bitops.h> /* for LOCK_PREFIX */
-
-/*
- * Note: if you use set64_bit(), __cmpxchg64(), or their variants, you
- *       you need to test for the feature in boot_cpu_data.
- */
-
-#define xchg(ptr, v)							\
-	((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), sizeof(*(ptr))))
-
-struct __xchg_dummy {
-	unsigned long a[100];
-};
-#define __xg(x) ((struct __xchg_dummy *)(x))
-
-/*
- * The semantics of XCHGCMP8B are a bit strange, this is why
- * there is a loop and the loading of %%eax and %%edx has to
- * be inside. This inlines well in most cases, the cached
- * cost is around ~38 cycles. (in the future we might want
- * to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
- * might have an implicit FPU-save as a cost, so it's not
- * clear which path to go.)
- *
- * cmpxchg8b must be used with the lock prefix here to allow
- * the instruction to be executed atomically, see page 3-102
- * of the instruction set reference 24319102.pdf. We need
- * the reader side to see the coherent 64bit value.
- */
-static inline void __set_64bit(unsigned long long *ptr,
-			       unsigned int low, unsigned int high)
-{
-	asm volatile("\n1:\t"
-		     "movl (%0), %%eax\n\t"
-		     "movl 4(%0), %%edx\n\t"
-		     LOCK_PREFIX "cmpxchg8b (%0)\n\t"
-		     "jnz 1b"
-		     : /* no outputs */
-		     : "D"(ptr),
-		       "b"(low),
-		       "c"(high)
-		     : "ax", "dx", "memory");
-}
-
-static inline void __set_64bit_constant(unsigned long long *ptr,
-					unsigned long long value)
-{
-	__set_64bit(ptr, (unsigned int)value, (unsigned int)(value >> 32));
-}
-
-#define ll_low(x)	*(((unsigned int *)&(x)) + 0)
-#define ll_high(x)	*(((unsigned int *)&(x)) + 1)
-
-static inline void __set_64bit_var(unsigned long long *ptr,
-				   unsigned long long value)
-{
-	__set_64bit(ptr, ll_low(value), ll_high(value));
-}
-
-#define set_64bit(ptr, value)			\
-	(__builtin_constant_p((value))		\
-	 ? __set_64bit_constant((ptr), (value))	\
-	 : __set_64bit_var((ptr), (value)))
-
-#define _set_64bit(ptr, value)						\
-	(__builtin_constant_p(value)					\
-	 ? __set_64bit(ptr, (unsigned int)(value),			\
-		       (unsigned int)((value) >> 32))			\
-	 : __set_64bit(ptr, ll_low((value)), ll_high((value))))
-
-/*
- * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
- * Note 2: xchg has side effect, so that attribute volatile is necessary,
- *	  but generally the primitive is invalid, *ptr is output argument. --ANK
- */
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
-				   int size)
-{
-	switch (size) {
-	case 1:
-		asm volatile("xchgb %b0,%1"
-			     : "=q" (x)
-			     : "m" (*__xg(ptr)), "0" (x)
-			     : "memory");
-		break;
-	case 2:
-		asm volatile("xchgw %w0,%1"
-			     : "=r" (x)
-			     : "m" (*__xg(ptr)), "0" (x)
-			     : "memory");
-		break;
-	case 4:
-		asm volatile("xchgl %0,%1"
-			     : "=r" (x)
-			     : "m" (*__xg(ptr)), "0" (x)
-			     : "memory");
-		break;
-	}
-	return x;
-}
-
-/*
- * Atomic compare and exchange.  Compare OLD with MEM, if identical,
- * store NEW in MEM.  Return the initial value in MEM.  Success is
- * indicated by comparing RETURN with OLD.
- */
-
-#ifdef CONFIG_X86_CMPXCHG
-#define __HAVE_ARCH_CMPXCHG 1
-#define cmpxchg(ptr, o, n)						\
-	((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o),	\
-				       (unsigned long)(n),		\
-				       sizeof(*(ptr))))
-#define sync_cmpxchg(ptr, o, n)						\
-	((__typeof__(*(ptr)))__sync_cmpxchg((ptr), (unsigned long)(o),	\
-					    (unsigned long)(n),		\
-					    sizeof(*(ptr))))
-#define cmpxchg_local(ptr, o, n)					\
-	((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o),	\
-					     (unsigned long)(n),	\
-					     sizeof(*(ptr))))
-#endif
-
-#ifdef CONFIG_X86_CMPXCHG64
-#define cmpxchg64(ptr, o, n)						\
-	((__typeof__(*(ptr)))__cmpxchg64((ptr), (unsigned long long)(o), \
-					 (unsigned long long)(n)))
-#define cmpxchg64_local(ptr, o, n)					\
-	((__typeof__(*(ptr)))__cmpxchg64_local((ptr), (unsigned long long)(o), \
-					       (unsigned long long)(n)))
-#endif
-
-static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
-				      unsigned long new, int size)
-{
-	unsigned long prev;
-	switch (size) {
-	case 1:
-		asm volatile(LOCK_PREFIX "cmpxchgb %b1,%2"
-			     : "=a"(prev)
-			     : "q"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	case 2:
-		asm volatile(LOCK_PREFIX "cmpxchgw %w1,%2"
-			     : "=a"(prev)
-			     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	case 4:
-		asm volatile(LOCK_PREFIX "cmpxchgl %1,%2"
-			     : "=a"(prev)
-			     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	}
-	return old;
-}
-
-/*
- * Always use locked operations when touching memory shared with a
- * hypervisor, since the system may be SMP even if the guest kernel
- * isn't.
- */
-static inline unsigned long __sync_cmpxchg(volatile void *ptr,
-					   unsigned long old,
-					   unsigned long new, int size)
-{
-	unsigned long prev;
-	switch (size) {
-	case 1:
-		asm volatile("lock; cmpxchgb %b1,%2"
-			     : "=a"(prev)
-			     : "q"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	case 2:
-		asm volatile("lock; cmpxchgw %w1,%2"
-			     : "=a"(prev)
-			     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	case 4:
-		asm volatile("lock; cmpxchgl %1,%2"
-			     : "=a"(prev)
-			     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	}
-	return old;
-}
-
-static inline unsigned long __cmpxchg_local(volatile void *ptr,
-					    unsigned long old,
-					    unsigned long new, int size)
-{
-	unsigned long prev;
-	switch (size) {
-	case 1:
-		asm volatile("cmpxchgb %b1,%2"
-			     : "=a"(prev)
-			     : "q"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	case 2:
-		asm volatile("cmpxchgw %w1,%2"
-			     : "=a"(prev)
-			     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	case 4:
-		asm volatile("cmpxchgl %1,%2"
-			     : "=a"(prev)
-			     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	}
-	return old;
-}
-
-static inline unsigned long long __cmpxchg64(volatile void *ptr,
-					     unsigned long long old,
-					     unsigned long long new)
-{
-	unsigned long long prev;
-	asm volatile(LOCK_PREFIX "cmpxchg8b %3"
-		     : "=A"(prev)
-		     : "b"((unsigned long)new),
-		       "c"((unsigned long)(new >> 32)),
-		       "m"(*__xg(ptr)),
-		       "0"(old)
-		     : "memory");
-	return prev;
-}
-
-static inline unsigned long long __cmpxchg64_local(volatile void *ptr,
-						   unsigned long long old,
-						   unsigned long long new)
-{
-	unsigned long long prev;
-	asm volatile("cmpxchg8b %3"
-		     : "=A"(prev)
-		     : "b"((unsigned long)new),
-		       "c"((unsigned long)(new >> 32)),
-		       "m"(*__xg(ptr)),
-		       "0"(old)
-		     : "memory");
-	return prev;
-}
-
-#ifndef CONFIG_X86_CMPXCHG
-/*
- * Building a kernel capable running on 80386. It may be necessary to
- * simulate the cmpxchg on the 80386 CPU. For that purpose we define
- * a function for each of the sizes we support.
- */
-
-extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8);
-extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16);
-extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32);
-
-static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
-					unsigned long new, int size)
-{
-	switch (size) {
-	case 1:
-		return cmpxchg_386_u8(ptr, old, new);
-	case 2:
-		return cmpxchg_386_u16(ptr, old, new);
-	case 4:
-		return cmpxchg_386_u32(ptr, old, new);
-	}
-	return old;
-}
-
-#define cmpxchg(ptr, o, n)						\
-({									\
-	__typeof__(*(ptr)) __ret;					\
-	if (likely(boot_cpu_data.x86 > 3))				\
-		__ret = (__typeof__(*(ptr)))__cmpxchg((ptr),		\
-				(unsigned long)(o), (unsigned long)(n),	\
-				sizeof(*(ptr)));			\
-	else								\
-		__ret = (__typeof__(*(ptr)))cmpxchg_386((ptr),		\
-				(unsigned long)(o), (unsigned long)(n),	\
-				sizeof(*(ptr)));			\
-	__ret;								\
-})
-#define cmpxchg_local(ptr, o, n)					\
-({									\
-	__typeof__(*(ptr)) __ret;					\
-	if (likely(boot_cpu_data.x86 > 3))				\
-		__ret = (__typeof__(*(ptr)))__cmpxchg_local((ptr),	\
-				(unsigned long)(o), (unsigned long)(n),	\
-				sizeof(*(ptr)));			\
-	else								\
-		__ret = (__typeof__(*(ptr)))cmpxchg_386((ptr),		\
-				(unsigned long)(o), (unsigned long)(n),	\
-				sizeof(*(ptr)));			\
-	__ret;								\
-})
-#endif
-
-#ifndef CONFIG_X86_CMPXCHG64
-/*
- * Building a kernel capable running on 80386 and 80486. It may be necessary
- * to simulate the cmpxchg8b on the 80386 and 80486 CPU.
- */
-
-extern unsigned long long cmpxchg_486_u64(volatile void *, u64, u64);
-
-#define cmpxchg64(ptr, o, n)						\
-({									\
-	__typeof__(*(ptr)) __ret;					\
-	if (likely(boot_cpu_data.x86 > 4))				\
-		__ret = (__typeof__(*(ptr)))__cmpxchg64((ptr),		\
-				(unsigned long long)(o),		\
-				(unsigned long long)(n));		\
-	else								\
-		__ret = (__typeof__(*(ptr)))cmpxchg_486_u64((ptr),	\
-				(unsigned long long)(o),		\
-				(unsigned long long)(n));		\
-	__ret;								\
-})
-#define cmpxchg64_local(ptr, o, n)					\
-({									\
-	__typeof__(*(ptr)) __ret;					\
-	if (likely(boot_cpu_data.x86 > 4))				\
-		__ret = (__typeof__(*(ptr)))__cmpxchg64_local((ptr),	\
-				(unsigned long long)(o),		\
-				(unsigned long long)(n));		\
-	else								\
-		__ret = (__typeof__(*(ptr)))cmpxchg_486_u64((ptr),	\
-				(unsigned long long)(o),		\
-				(unsigned long long)(n));		\
-	__ret;								\
-})
-
-#endif
-
-#endif /* ASM_X86__CMPXCHG_32_H */
diff --git a/include/asm-x86/cmpxchg_64.h b/include/asm-x86/cmpxchg_64.h
deleted file mode 100644
index 63c1a5e61b99..000000000000
--- a/include/asm-x86/cmpxchg_64.h
+++ /dev/null
@@ -1,185 +0,0 @@
-#ifndef ASM_X86__CMPXCHG_64_H
-#define ASM_X86__CMPXCHG_64_H
-
-#include <asm/alternative.h> /* Provides LOCK_PREFIX */
-
-#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), \
-						 (ptr), sizeof(*(ptr))))
-
-#define __xg(x) ((volatile long *)(x))
-
-static inline void set_64bit(volatile unsigned long *ptr, unsigned long val)
-{
-	*ptr = val;
-}
-
-#define _set_64bit set_64bit
-
-/*
- * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
- * Note 2: xchg has side effect, so that attribute volatile is necessary,
- *	  but generally the primitive is invalid, *ptr is output argument. --ANK
- */
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
-				   int size)
-{
-	switch (size) {
-	case 1:
-		asm volatile("xchgb %b0,%1"
-			     : "=q" (x)
-			     : "m" (*__xg(ptr)), "0" (x)
-			     : "memory");
-		break;
-	case 2:
-		asm volatile("xchgw %w0,%1"
-			     : "=r" (x)
-			     : "m" (*__xg(ptr)), "0" (x)
-			     : "memory");
-		break;
-	case 4:
-		asm volatile("xchgl %k0,%1"
-			     : "=r" (x)
-			     : "m" (*__xg(ptr)), "0" (x)
-			     : "memory");
-		break;
-	case 8:
-		asm volatile("xchgq %0,%1"
-			     : "=r" (x)
-			     : "m" (*__xg(ptr)), "0" (x)
-			     : "memory");
-		break;
-	}
-	return x;
-}
-
-/*
- * Atomic compare and exchange.  Compare OLD with MEM, if identical,
- * store NEW in MEM.  Return the initial value in MEM.  Success is
- * indicated by comparing RETURN with OLD.
- */
-
-#define __HAVE_ARCH_CMPXCHG 1
-
-static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
-				      unsigned long new, int size)
-{
-	unsigned long prev;
-	switch (size) {
-	case 1:
-		asm volatile(LOCK_PREFIX "cmpxchgb %b1,%2"
-			     : "=a"(prev)
-			     : "q"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	case 2:
-		asm volatile(LOCK_PREFIX "cmpxchgw %w1,%2"
-			     : "=a"(prev)
-			     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	case 4:
-		asm volatile(LOCK_PREFIX "cmpxchgl %k1,%2"
-			     : "=a"(prev)
-			     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	case 8:
-		asm volatile(LOCK_PREFIX "cmpxchgq %1,%2"
-			     : "=a"(prev)
-			     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	}
-	return old;
-}
-
-/*
- * Always use locked operations when touching memory shared with a
- * hypervisor, since the system may be SMP even if the guest kernel
- * isn't.
- */
-static inline unsigned long __sync_cmpxchg(volatile void *ptr,
-					   unsigned long old,
-					   unsigned long new, int size)
-{
-	unsigned long prev;
-	switch (size) {
-	case 1:
-		asm volatile("lock; cmpxchgb %b1,%2"
-			     : "=a"(prev)
-			     : "q"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	case 2:
-		asm volatile("lock; cmpxchgw %w1,%2"
-			     : "=a"(prev)
-			     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	case 4:
-		asm volatile("lock; cmpxchgl %1,%2"
-			     : "=a"(prev)
-			     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	}
-	return old;
-}
-
-static inline unsigned long __cmpxchg_local(volatile void *ptr,
-					    unsigned long old,
-					    unsigned long new, int size)
-{
-	unsigned long prev;
-	switch (size) {
-	case 1:
-		asm volatile("cmpxchgb %b1,%2"
-			     : "=a"(prev)
-			     : "q"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	case 2:
-		asm volatile("cmpxchgw %w1,%2"
-			     : "=a"(prev)
-			     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	case 4:
-		asm volatile("cmpxchgl %k1,%2"
-			     : "=a"(prev)
-			     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	case 8:
-		asm volatile("cmpxchgq %1,%2"
-			     : "=a"(prev)
-			     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-			     : "memory");
-		return prev;
-	}
-	return old;
-}
-
-#define cmpxchg(ptr, o, n)						\
-	((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o),	\
-				       (unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64(ptr, o, n)						\
-({									\
-	BUILD_BUG_ON(sizeof(*(ptr)) != 8);				\
-	cmpxchg((ptr), (o), (n));					\
-})
-#define cmpxchg_local(ptr, o, n)					\
-	((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o),	\
-					     (unsigned long)(n),	\
-					     sizeof(*(ptr))))
-#define sync_cmpxchg(ptr, o, n)						\
-	((__typeof__(*(ptr)))__sync_cmpxchg((ptr), (unsigned long)(o),	\
-					    (unsigned long)(n),		\
-					    sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n)					\
-({									\
-	BUILD_BUG_ON(sizeof(*(ptr)) != 8);				\
-	cmpxchg_local((ptr), (o), (n));					\
-})
-
-#endif /* ASM_X86__CMPXCHG_64_H */
diff --git a/include/asm-x86/compat.h b/include/asm-x86/compat.h
deleted file mode 100644
index 6732b150949e..000000000000
--- a/include/asm-x86/compat.h
+++ /dev/null
@@ -1,218 +0,0 @@
-#ifndef ASM_X86__COMPAT_H
-#define ASM_X86__COMPAT_H
-
-/*
- * Architecture specific compatibility types
- */
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <asm/user32.h>
-
-#define COMPAT_USER_HZ	100
-
-typedef u32		compat_size_t;
-typedef s32		compat_ssize_t;
-typedef s32		compat_time_t;
-typedef s32		compat_clock_t;
-typedef s32		compat_pid_t;
-typedef u16		__compat_uid_t;
-typedef u16		__compat_gid_t;
-typedef u32		__compat_uid32_t;
-typedef u32		__compat_gid32_t;
-typedef u16		compat_mode_t;
-typedef u32		compat_ino_t;
-typedef u16		compat_dev_t;
-typedef s32		compat_off_t;
-typedef s64		compat_loff_t;
-typedef u16		compat_nlink_t;
-typedef u16		compat_ipc_pid_t;
-typedef s32		compat_daddr_t;
-typedef u32		compat_caddr_t;
-typedef __kernel_fsid_t	compat_fsid_t;
-typedef s32		compat_timer_t;
-typedef s32		compat_key_t;
-
-typedef s32		compat_int_t;
-typedef s32		compat_long_t;
-typedef s64 __attribute__((aligned(4))) compat_s64;
-typedef u32		compat_uint_t;
-typedef u32		compat_ulong_t;
-typedef u64 __attribute__((aligned(4))) compat_u64;
-
-struct compat_timespec {
-	compat_time_t	tv_sec;
-	s32		tv_nsec;
-};
-
-struct compat_timeval {
-	compat_time_t	tv_sec;
-	s32		tv_usec;
-};
-
-struct compat_stat {
-	compat_dev_t	st_dev;
-	u16		__pad1;
-	compat_ino_t	st_ino;
-	compat_mode_t	st_mode;
-	compat_nlink_t	st_nlink;
-	__compat_uid_t	st_uid;
-	__compat_gid_t	st_gid;
-	compat_dev_t	st_rdev;
-	u16		__pad2;
-	u32		st_size;
-	u32		st_blksize;
-	u32		st_blocks;
-	u32		st_atime;
-	u32		st_atime_nsec;
-	u32		st_mtime;
-	u32		st_mtime_nsec;
-	u32		st_ctime;
-	u32		st_ctime_nsec;
-	u32		__unused4;
-	u32		__unused5;
-};
-
-struct compat_flock {
-	short		l_type;
-	short		l_whence;
-	compat_off_t	l_start;
-	compat_off_t	l_len;
-	compat_pid_t	l_pid;
-};
-
-#define F_GETLK64	12	/*  using 'struct flock64' */
-#define F_SETLK64	13
-#define F_SETLKW64	14
-
-/*
- * IA32 uses 4 byte alignment for 64 bit quantities,
- * so we need to pack this structure.
- */
-struct compat_flock64 {
-	short		l_type;
-	short		l_whence;
-	compat_loff_t	l_start;
-	compat_loff_t	l_len;
-	compat_pid_t	l_pid;
-} __attribute__((packed));
-
-struct compat_statfs {
-	int		f_type;
-	int		f_bsize;
-	int		f_blocks;
-	int		f_bfree;
-	int		f_bavail;
-	int		f_files;
-	int		f_ffree;
-	compat_fsid_t	f_fsid;
-	int		f_namelen;	/* SunOS ignores this field. */
-	int		f_frsize;
-	int		f_spare[5];
-};
-
-#define COMPAT_RLIM_OLD_INFINITY	0x7fffffff
-#define COMPAT_RLIM_INFINITY		0xffffffff
-
-typedef u32		compat_old_sigset_t;	/* at least 32 bits */
-
-#define _COMPAT_NSIG		64
-#define _COMPAT_NSIG_BPW	32
-
-typedef u32               compat_sigset_word;
-
-#define COMPAT_OFF_T_MAX	0x7fffffff
-#define COMPAT_LOFF_T_MAX	0x7fffffffffffffffL
-
-struct compat_ipc64_perm {
-	compat_key_t key;
-	__compat_uid32_t uid;
-	__compat_gid32_t gid;
-	__compat_uid32_t cuid;
-	__compat_gid32_t cgid;
-	unsigned short mode;
-	unsigned short __pad1;
-	unsigned short seq;
-	unsigned short __pad2;
-	compat_ulong_t unused1;
-	compat_ulong_t unused2;
-};
-
-struct compat_semid64_ds {
-	struct compat_ipc64_perm sem_perm;
-	compat_time_t  sem_otime;
-	compat_ulong_t __unused1;
-	compat_time_t  sem_ctime;
-	compat_ulong_t __unused2;
-	compat_ulong_t sem_nsems;
-	compat_ulong_t __unused3;
-	compat_ulong_t __unused4;
-};
-
-struct compat_msqid64_ds {
-	struct compat_ipc64_perm msg_perm;
-	compat_time_t  msg_stime;
-	compat_ulong_t __unused1;
-	compat_time_t  msg_rtime;
-	compat_ulong_t __unused2;
-	compat_time_t  msg_ctime;
-	compat_ulong_t __unused3;
-	compat_ulong_t msg_cbytes;
-	compat_ulong_t msg_qnum;
-	compat_ulong_t msg_qbytes;
-	compat_pid_t   msg_lspid;
-	compat_pid_t   msg_lrpid;
-	compat_ulong_t __unused4;
-	compat_ulong_t __unused5;
-};
-
-struct compat_shmid64_ds {
-	struct compat_ipc64_perm shm_perm;
-	compat_size_t  shm_segsz;
-	compat_time_t  shm_atime;
-	compat_ulong_t __unused1;
-	compat_time_t  shm_dtime;
-	compat_ulong_t __unused2;
-	compat_time_t  shm_ctime;
-	compat_ulong_t __unused3;
-	compat_pid_t   shm_cpid;
-	compat_pid_t   shm_lpid;
-	compat_ulong_t shm_nattch;
-	compat_ulong_t __unused4;
-	compat_ulong_t __unused5;
-};
-
-/*
- * The type of struct elf_prstatus.pr_reg in compatible core dumps.
- */
-typedef struct user_regs_struct32 compat_elf_gregset_t;
-
-/*
- * A pointer passed in from user mode. This should not
- * be used for syscall parameters, just declare them
- * as pointers because the syscall entry code will have
- * appropriately converted them already.
- */
-typedef	u32		compat_uptr_t;
-
-static inline void __user *compat_ptr(compat_uptr_t uptr)
-{
-	return (void __user *)(unsigned long)uptr;
-}
-
-static inline compat_uptr_t ptr_to_compat(void __user *uptr)
-{
-	return (u32)(unsigned long)uptr;
-}
-
-static inline void __user *compat_alloc_user_space(long len)
-{
-	struct pt_regs *regs = task_pt_regs(current);
-	return (void __user *)regs->sp - len;
-}
-
-static inline int is_compat_task(void)
-{
-	return current_thread_info()->status & TS_COMPAT;
-}
-
-#endif /* ASM_X86__COMPAT_H */
diff --git a/include/asm-x86/cpu.h b/include/asm-x86/cpu.h
deleted file mode 100644
index 83a115083f0d..000000000000
--- a/include/asm-x86/cpu.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef ASM_X86__CPU_H
-#define ASM_X86__CPU_H
-
-#include <linux/device.h>
-#include <linux/cpu.h>
-#include <linux/topology.h>
-#include <linux/nodemask.h>
-#include <linux/percpu.h>
-
-struct x86_cpu {
-	struct cpu cpu;
-};
-
-#ifdef CONFIG_HOTPLUG_CPU
-extern int arch_register_cpu(int num);
-extern void arch_unregister_cpu(int);
-#endif
-
-DECLARE_PER_CPU(int, cpu_state);
-#endif /* ASM_X86__CPU_H */
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
deleted file mode 100644
index adfeae6586e1..000000000000
--- a/include/asm-x86/cpufeature.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * Defines x86 CPU feature bits
- */
-#ifndef ASM_X86__CPUFEATURE_H
-#define ASM_X86__CPUFEATURE_H
-
-#include <asm/required-features.h>
-
-#define NCAPINTS	9	/* N 32-bit words worth of info */
-
-/*
- * Note: If the comment begins with a quoted string, that string is used
- * in /proc/cpuinfo instead of the macro name.  If the string is "",
- * this feature bit is not displayed in /proc/cpuinfo at all.
- */
-
-/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
-#define X86_FEATURE_FPU		(0*32+ 0) /* Onboard FPU */
-#define X86_FEATURE_VME		(0*32+ 1) /* Virtual Mode Extensions */
-#define X86_FEATURE_DE		(0*32+ 2) /* Debugging Extensions */
-#define X86_FEATURE_PSE		(0*32+ 3) /* Page Size Extensions */
-#define X86_FEATURE_TSC		(0*32+ 4) /* Time Stamp Counter */
-#define X86_FEATURE_MSR		(0*32+ 5) /* Model-Specific Registers */
-#define X86_FEATURE_PAE		(0*32+ 6) /* Physical Address Extensions */
-#define X86_FEATURE_MCE		(0*32+ 7) /* Machine Check Architecture */
-#define X86_FEATURE_CX8		(0*32+ 8) /* CMPXCHG8 instruction */
-#define X86_FEATURE_APIC	(0*32+ 9) /* Onboard APIC */
-#define X86_FEATURE_SEP		(0*32+11) /* SYSENTER/SYSEXIT */
-#define X86_FEATURE_MTRR	(0*32+12) /* Memory Type Range Registers */
-#define X86_FEATURE_PGE		(0*32+13) /* Page Global Enable */
-#define X86_FEATURE_MCA		(0*32+14) /* Machine Check Architecture */
-#define X86_FEATURE_CMOV	(0*32+15) /* CMOV instructions */
-					  /* (plus FCMOVcc, FCOMI with FPU) */
-#define X86_FEATURE_PAT		(0*32+16) /* Page Attribute Table */
-#define X86_FEATURE_PSE36	(0*32+17) /* 36-bit PSEs */
-#define X86_FEATURE_PN		(0*32+18) /* Processor serial number */
-#define X86_FEATURE_CLFLSH	(0*32+19) /* "clflush" CLFLUSH instruction */
-#define X86_FEATURE_DS		(0*32+21) /* "dts" Debug Store */
-#define X86_FEATURE_ACPI	(0*32+22) /* ACPI via MSR */
-#define X86_FEATURE_MMX		(0*32+23) /* Multimedia Extensions */
-#define X86_FEATURE_FXSR	(0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
-#define X86_FEATURE_XMM		(0*32+25) /* "sse" */
-#define X86_FEATURE_XMM2	(0*32+26) /* "sse2" */
-#define X86_FEATURE_SELFSNOOP	(0*32+27) /* "ss" CPU self snoop */
-#define X86_FEATURE_HT		(0*32+28) /* Hyper-Threading */
-#define X86_FEATURE_ACC		(0*32+29) /* "tm" Automatic clock control */
-#define X86_FEATURE_IA64	(0*32+30) /* IA-64 processor */
-#define X86_FEATURE_PBE		(0*32+31) /* Pending Break Enable */
-
-/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
-/* Don't duplicate feature flags which are redundant with Intel! */
-#define X86_FEATURE_SYSCALL	(1*32+11) /* SYSCALL/SYSRET */
-#define X86_FEATURE_MP		(1*32+19) /* MP Capable. */
-#define X86_FEATURE_NX		(1*32+20) /* Execute Disable */
-#define X86_FEATURE_MMXEXT	(1*32+22) /* AMD MMX extensions */
-#define X86_FEATURE_FXSR_OPT	(1*32+25) /* FXSAVE/FXRSTOR optimizations */
-#define X86_FEATURE_GBPAGES	(1*32+26) /* "pdpe1gb" GB pages */
-#define X86_FEATURE_RDTSCP	(1*32+27) /* RDTSCP */
-#define X86_FEATURE_LM		(1*32+29) /* Long Mode (x86-64) */
-#define X86_FEATURE_3DNOWEXT	(1*32+30) /* AMD 3DNow! extensions */
-#define X86_FEATURE_3DNOW	(1*32+31) /* 3DNow! */
-
-/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
-#define X86_FEATURE_RECOVERY	(2*32+ 0) /* CPU in recovery mode */
-#define X86_FEATURE_LONGRUN	(2*32+ 1) /* Longrun power control */
-#define X86_FEATURE_LRTI	(2*32+ 3) /* LongRun table interface */
-
-/* Other features, Linux-defined mapping, word 3 */
-/* This range is used for feature bits which conflict or are synthesized */
-#define X86_FEATURE_CXMMX	(3*32+ 0) /* Cyrix MMX extensions */
-#define X86_FEATURE_K6_MTRR	(3*32+ 1) /* AMD K6 nonstandard MTRRs */
-#define X86_FEATURE_CYRIX_ARR	(3*32+ 2) /* Cyrix ARRs (= MTRRs) */
-#define X86_FEATURE_CENTAUR_MCR	(3*32+ 3) /* Centaur MCRs (= MTRRs) */
-/* cpu types for specific tunings: */
-#define X86_FEATURE_K8		(3*32+ 4) /* "" Opteron, Athlon64 */
-#define X86_FEATURE_K7		(3*32+ 5) /* "" Athlon */
-#define X86_FEATURE_P3		(3*32+ 6) /* "" P3 */
-#define X86_FEATURE_P4		(3*32+ 7) /* "" P4 */
-#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
-#define X86_FEATURE_UP		(3*32+ 9) /* smp kernel running on up */
-#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */
-#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
-#define X86_FEATURE_NOPL	(3*32+20) /* The NOPL (0F 1F) instructions */
-#define X86_FEATURE_PEBS	(3*32+12) /* Precise-Event Based Sampling */
-#define X86_FEATURE_BTS		(3*32+13) /* Branch Trace Store */
-#define X86_FEATURE_SYSCALL32	(3*32+14) /* "" syscall in ia32 userspace */
-#define X86_FEATURE_SYSENTER32	(3*32+15) /* "" sysenter in ia32 userspace */
-#define X86_FEATURE_REP_GOOD	(3*32+16) /* rep microcode works well */
-#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */
-#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */
-#define X86_FEATURE_11AP	(3*32+19) /* "" Bad local APIC aka 11AP */
-#define X86_FEATURE_NOPL	(3*32+20) /* The NOPL (0F 1F) instructions */
-#define X86_FEATURE_AMDC1E	(3*32+21) /* AMD C1E detected */
-#define X86_FEATURE_XTOPOLOGY	(3*32+21) /* cpu topology enum extensions */
-
-/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
-#define X86_FEATURE_XMM3	(4*32+ 0) /* "pni" SSE-3 */
-#define X86_FEATURE_PCLMULQDQ	(4*32+ 1) /* PCLMULQDQ instruction */
-#define X86_FEATURE_DTES64	(4*32+ 2) /* 64-bit Debug Store */
-#define X86_FEATURE_MWAIT	(4*32+ 3) /* "monitor" Monitor/Mwait support */
-#define X86_FEATURE_DSCPL	(4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
-#define X86_FEATURE_VMX		(4*32+ 5) /* Hardware virtualization */
-#define X86_FEATURE_SMX		(4*32+ 6) /* Safer mode */
-#define X86_FEATURE_EST		(4*32+ 7) /* Enhanced SpeedStep */
-#define X86_FEATURE_TM2		(4*32+ 8) /* Thermal Monitor 2 */
-#define X86_FEATURE_SSSE3	(4*32+ 9) /* Supplemental SSE-3 */
-#define X86_FEATURE_CID		(4*32+10) /* Context ID */
-#define X86_FEATURE_FMA		(4*32+12) /* Fused multiply-add */
-#define X86_FEATURE_CX16	(4*32+13) /* CMPXCHG16B */
-#define X86_FEATURE_XTPR	(4*32+14) /* Send Task Priority Messages */
-#define X86_FEATURE_PDCM	(4*32+15) /* Performance Capabilities */
-#define X86_FEATURE_DCA		(4*32+18) /* Direct Cache Access */
-#define X86_FEATURE_XMM4_1	(4*32+19) /* "sse4_1" SSE-4.1 */
-#define X86_FEATURE_XMM4_2	(4*32+20) /* "sse4_2" SSE-4.2 */
-#define X86_FEATURE_X2APIC	(4*32+21) /* x2APIC */
-#define X86_FEATURE_AES		(4*32+25) /* AES instructions */
-#define X86_FEATURE_XSAVE	(4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
-#define X86_FEATURE_OSXSAVE	(4*32+27) /* "" XSAVE enabled in the OS */
-#define X86_FEATURE_AVX		(4*32+28) /* Advanced Vector Extensions */
-
-/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
-#define X86_FEATURE_XSTORE	(5*32+ 2) /* "rng" RNG present (xstore) */
-#define X86_FEATURE_XSTORE_EN	(5*32+ 3) /* "rng_en" RNG enabled */
-#define X86_FEATURE_XCRYPT	(5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
-#define X86_FEATURE_XCRYPT_EN	(5*32+ 7) /* "ace_en" on-CPU crypto enabled */
-#define X86_FEATURE_ACE2	(5*32+ 8) /* Advanced Cryptography Engine v2 */
-#define X86_FEATURE_ACE2_EN	(5*32+ 9) /* ACE v2 enabled */
-#define X86_FEATURE_PHE		(5*32+10) /* PadLock Hash Engine */
-#define X86_FEATURE_PHE_EN	(5*32+11) /* PHE enabled */
-#define X86_FEATURE_PMM		(5*32+12) /* PadLock Montgomery Multiplier */
-#define X86_FEATURE_PMM_EN	(5*32+13) /* PMM enabled */
-
-/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
-#define X86_FEATURE_LAHF_LM	(6*32+ 0) /* LAHF/SAHF in long mode */
-#define X86_FEATURE_CMP_LEGACY	(6*32+ 1) /* If yes HyperThreading not valid */
-#define X86_FEATURE_SVM		(6*32+ 2) /* Secure virtual machine */
-#define X86_FEATURE_EXTAPIC	(6*32+ 3) /* Extended APIC space */
-#define X86_FEATURE_CR8_LEGACY	(6*32+ 4) /* CR8 in 32-bit mode */
-#define X86_FEATURE_ABM		(6*32+ 5) /* Advanced bit manipulation */
-#define X86_FEATURE_SSE4A	(6*32+ 6) /* SSE-4A */
-#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
-#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
-#define X86_FEATURE_OSVW	(6*32+ 9) /* OS Visible Workaround */
-#define X86_FEATURE_IBS		(6*32+10) /* Instruction Based Sampling */
-#define X86_FEATURE_SSE5	(6*32+11) /* SSE-5 */
-#define X86_FEATURE_SKINIT	(6*32+12) /* SKINIT/STGI instructions */
-#define X86_FEATURE_WDT		(6*32+13) /* Watchdog timer */
-
-/*
- * Auxiliary flags: Linux defined - For features scattered in various
- * CPUID levels like 0x6, 0xA etc
- */
-#define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration */
-
-/* Virtualization flags: Linux defined */
-#define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
-#define X86_FEATURE_VNMI        (8*32+ 1) /* Intel Virtual NMI */
-#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
-#define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
-#define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
-
-#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
-
-#include <linux/bitops.h>
-
-extern const char * const x86_cap_flags[NCAPINTS*32];
-extern const char * const x86_power_flags[32];
-
-#define test_cpu_cap(c, bit)						\
-	 test_bit(bit, (unsigned long *)((c)->x86_capability))
-
-#define cpu_has(c, bit)							\
-	(__builtin_constant_p(bit) &&					\
-	 ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) ||	\
-	   (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) ||	\
-	   (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) ||	\
-	   (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) ||	\
-	   (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) ||	\
-	   (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) ||	\
-	   (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) ||	\
-	   (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) )	\
-	  ? 1 :								\
-	 test_cpu_cap(c, bit))
-
-#define boot_cpu_has(bit)	cpu_has(&boot_cpu_data, bit)
-
-#define set_cpu_cap(c, bit)	set_bit(bit, (unsigned long *)((c)->x86_capability))
-#define clear_cpu_cap(c, bit)	clear_bit(bit, (unsigned long *)((c)->x86_capability))
-#define setup_clear_cpu_cap(bit) do { \
-	clear_cpu_cap(&boot_cpu_data, bit);	\
-	set_bit(bit, (unsigned long *)cleared_cpu_caps); \
-} while (0)
-#define setup_force_cpu_cap(bit) do { \
-	set_cpu_cap(&boot_cpu_data, bit);	\
-	clear_bit(bit, (unsigned long *)cleared_cpu_caps);	\
-} while (0)
-
-#define cpu_has_fpu		boot_cpu_has(X86_FEATURE_FPU)
-#define cpu_has_vme		boot_cpu_has(X86_FEATURE_VME)
-#define cpu_has_de		boot_cpu_has(X86_FEATURE_DE)
-#define cpu_has_pse		boot_cpu_has(X86_FEATURE_PSE)
-#define cpu_has_tsc		boot_cpu_has(X86_FEATURE_TSC)
-#define cpu_has_pae		boot_cpu_has(X86_FEATURE_PAE)
-#define cpu_has_pge		boot_cpu_has(X86_FEATURE_PGE)
-#define cpu_has_apic		boot_cpu_has(X86_FEATURE_APIC)
-#define cpu_has_sep		boot_cpu_has(X86_FEATURE_SEP)
-#define cpu_has_mtrr		boot_cpu_has(X86_FEATURE_MTRR)
-#define cpu_has_mmx		boot_cpu_has(X86_FEATURE_MMX)
-#define cpu_has_fxsr		boot_cpu_has(X86_FEATURE_FXSR)
-#define cpu_has_xmm		boot_cpu_has(X86_FEATURE_XMM)
-#define cpu_has_xmm2		boot_cpu_has(X86_FEATURE_XMM2)
-#define cpu_has_xmm3		boot_cpu_has(X86_FEATURE_XMM3)
-#define cpu_has_ht		boot_cpu_has(X86_FEATURE_HT)
-#define cpu_has_mp		boot_cpu_has(X86_FEATURE_MP)
-#define cpu_has_nx		boot_cpu_has(X86_FEATURE_NX)
-#define cpu_has_k6_mtrr		boot_cpu_has(X86_FEATURE_K6_MTRR)
-#define cpu_has_cyrix_arr	boot_cpu_has(X86_FEATURE_CYRIX_ARR)
-#define cpu_has_centaur_mcr	boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
-#define cpu_has_xstore		boot_cpu_has(X86_FEATURE_XSTORE)
-#define cpu_has_xstore_enabled	boot_cpu_has(X86_FEATURE_XSTORE_EN)
-#define cpu_has_xcrypt		boot_cpu_has(X86_FEATURE_XCRYPT)
-#define cpu_has_xcrypt_enabled	boot_cpu_has(X86_FEATURE_XCRYPT_EN)
-#define cpu_has_ace2		boot_cpu_has(X86_FEATURE_ACE2)
-#define cpu_has_ace2_enabled	boot_cpu_has(X86_FEATURE_ACE2_EN)
-#define cpu_has_phe		boot_cpu_has(X86_FEATURE_PHE)
-#define cpu_has_phe_enabled	boot_cpu_has(X86_FEATURE_PHE_EN)
-#define cpu_has_pmm		boot_cpu_has(X86_FEATURE_PMM)
-#define cpu_has_pmm_enabled	boot_cpu_has(X86_FEATURE_PMM_EN)
-#define cpu_has_ds		boot_cpu_has(X86_FEATURE_DS)
-#define cpu_has_pebs		boot_cpu_has(X86_FEATURE_PEBS)
-#define cpu_has_clflush		boot_cpu_has(X86_FEATURE_CLFLSH)
-#define cpu_has_bts		boot_cpu_has(X86_FEATURE_BTS)
-#define cpu_has_gbpages		boot_cpu_has(X86_FEATURE_GBPAGES)
-#define cpu_has_arch_perfmon	boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
-#define cpu_has_pat		boot_cpu_has(X86_FEATURE_PAT)
-#define cpu_has_xmm4_1		boot_cpu_has(X86_FEATURE_XMM4_1)
-#define cpu_has_xmm4_2		boot_cpu_has(X86_FEATURE_XMM4_2)
-#define cpu_has_x2apic		boot_cpu_has(X86_FEATURE_X2APIC)
-#define cpu_has_xsave		boot_cpu_has(X86_FEATURE_XSAVE)
-
-#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
-# define cpu_has_invlpg		1
-#else
-# define cpu_has_invlpg		(boot_cpu_data.x86 > 3)
-#endif
-
-#ifdef CONFIG_X86_64
-
-#undef  cpu_has_vme
-#define cpu_has_vme		0
-
-#undef  cpu_has_pae
-#define cpu_has_pae		___BUG___
-
-#undef  cpu_has_mp
-#define cpu_has_mp		1
-
-#undef  cpu_has_k6_mtrr
-#define cpu_has_k6_mtrr		0
-
-#undef  cpu_has_cyrix_arr
-#define cpu_has_cyrix_arr	0
-
-#undef  cpu_has_centaur_mcr
-#define cpu_has_centaur_mcr	0
-
-#endif /* CONFIG_X86_64 */
-
-#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
-
-#endif /* ASM_X86__CPUFEATURE_H */
diff --git a/include/asm-x86/cputime.h b/include/asm-x86/cputime.h
deleted file mode 100644
index 6d68ad7e0ea3..000000000000
--- a/include/asm-x86/cputime.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/cputime.h>
diff --git a/include/asm-x86/current.h b/include/asm-x86/current.h
deleted file mode 100644
index a863ead856f3..000000000000
--- a/include/asm-x86/current.h
+++ /dev/null
@@ -1,39 +0,0 @@
-#ifndef ASM_X86__CURRENT_H
-#define ASM_X86__CURRENT_H
-
-#ifdef CONFIG_X86_32
-#include <linux/compiler.h>
-#include <asm/percpu.h>
-
-struct task_struct;
-
-DECLARE_PER_CPU(struct task_struct *, current_task);
-static __always_inline struct task_struct *get_current(void)
-{
-	return x86_read_percpu(current_task);
-}
-
-#else /* X86_32 */
-
-#ifndef __ASSEMBLY__
-#include <asm/pda.h>
-
-struct task_struct;
-
-static __always_inline struct task_struct *get_current(void)
-{
-	return read_pda(pcurrent);
-}
-
-#else /* __ASSEMBLY__ */
-
-#include <asm/asm-offsets.h>
-#define GET_CURRENT(reg) movq %gs:(pda_pcurrent),reg
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* X86_32 */
-
-#define current get_current()
-
-#endif /* ASM_X86__CURRENT_H */
diff --git a/include/asm-x86/debugreg.h b/include/asm-x86/debugreg.h
deleted file mode 100644
index ecb6907c3ea4..000000000000
--- a/include/asm-x86/debugreg.h
+++ /dev/null
@@ -1,70 +0,0 @@
-#ifndef ASM_X86__DEBUGREG_H
-#define ASM_X86__DEBUGREG_H
-
-
-/* Indicate the register numbers for a number of the specific
-   debug registers.  Registers 0-3 contain the addresses we wish to trap on */
-#define DR_FIRSTADDR 0        /* u_debugreg[DR_FIRSTADDR] */
-#define DR_LASTADDR 3         /* u_debugreg[DR_LASTADDR]  */
-
-#define DR_STATUS 6           /* u_debugreg[DR_STATUS]     */
-#define DR_CONTROL 7          /* u_debugreg[DR_CONTROL] */
-
-/* Define a few things for the status register.  We can use this to determine
-   which debugging register was responsible for the trap.  The other bits
-   are either reserved or not of interest to us. */
-
-#define DR_TRAP0	(0x1)		/* db0 */
-#define DR_TRAP1	(0x2)		/* db1 */
-#define DR_TRAP2	(0x4)		/* db2 */
-#define DR_TRAP3	(0x8)		/* db3 */
-
-#define DR_STEP		(0x4000)	/* single-step */
-#define DR_SWITCH	(0x8000)	/* task switch */
-
-/* Now define a bunch of things for manipulating the control register.
-   The top two bytes of the control register consist of 4 fields of 4
-   bits - each field corresponds to one of the four debug registers,
-   and indicates what types of access we trap on, and how large the data
-   field is that we are looking at */
-
-#define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
-#define DR_CONTROL_SIZE 4   /* 4 control bits per register */
-
-#define DR_RW_EXECUTE (0x0)   /* Settings for the access types to trap on */
-#define DR_RW_WRITE (0x1)
-#define DR_RW_READ (0x3)
-
-#define DR_LEN_1 (0x0) /* Settings for data length to trap on */
-#define DR_LEN_2 (0x4)
-#define DR_LEN_4 (0xC)
-#define DR_LEN_8 (0x8)
-
-/* The low byte to the control register determine which registers are
-   enabled.  There are 4 fields of two bits.  One bit is "local", meaning
-   that the processor will reset the bit after a task switch and the other
-   is global meaning that we have to explicitly reset the bit.  With linux,
-   you can use either one, since we explicitly zero the register when we enter
-   kernel mode. */
-
-#define DR_LOCAL_ENABLE_SHIFT 0    /* Extra shift to the local enable bit */
-#define DR_GLOBAL_ENABLE_SHIFT 1   /* Extra shift to the global enable bit */
-#define DR_ENABLE_SIZE 2           /* 2 enable bits per register */
-
-#define DR_LOCAL_ENABLE_MASK (0x55)  /* Set  local bits for all 4 regs */
-#define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
-
-/* The second byte to the control register has a few special things.
-   We can slow the instruction pipeline for instructions coming via the
-   gdt or the ldt if we want to.  I am not sure why this is an advantage */
-
-#ifdef __i386__
-#define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
-#else
-#define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */
-#endif
-
-#define DR_LOCAL_SLOWDOWN (0x100)   /* Local slow the pipeline */
-#define DR_GLOBAL_SLOWDOWN (0x200)  /* Global slow the pipeline */
-
-#endif /* ASM_X86__DEBUGREG_H */
diff --git a/include/asm-x86/delay.h b/include/asm-x86/delay.h
deleted file mode 100644
index 8a0da95b4fc5..000000000000
--- a/include/asm-x86/delay.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef ASM_X86__DELAY_H
-#define ASM_X86__DELAY_H
-
-/*
- * Copyright (C) 1993 Linus Torvalds
- *
- * Delay routines calling functions in arch/x86/lib/delay.c
- */
-
-/* Undefined functions to get compile-time errors */
-extern void __bad_udelay(void);
-extern void __bad_ndelay(void);
-
-extern void __udelay(unsigned long usecs);
-extern void __ndelay(unsigned long nsecs);
-extern void __const_udelay(unsigned long xloops);
-extern void __delay(unsigned long loops);
-
-/* 0x10c7 is 2**32 / 1000000 (rounded up) */
-#define udelay(n) (__builtin_constant_p(n) ? \
-	((n) > 20000 ? __bad_udelay() : __const_udelay((n) * 0x10c7ul)) : \
-	__udelay(n))
-
-/* 0x5 is 2**32 / 1000000000 (rounded up) */
-#define ndelay(n) (__builtin_constant_p(n) ? \
-	((n) > 20000 ? __bad_ndelay() : __const_udelay((n) * 5ul)) : \
-	__ndelay(n))
-
-void use_tsc_delay(void);
-
-#endif /* ASM_X86__DELAY_H */
diff --git a/include/asm-x86/desc.h b/include/asm-x86/desc.h
deleted file mode 100644
index f06adac7938c..000000000000
--- a/include/asm-x86/desc.h
+++ /dev/null
@@ -1,409 +0,0 @@
-#ifndef ASM_X86__DESC_H
-#define ASM_X86__DESC_H
-
-#ifndef __ASSEMBLY__
-#include <asm/desc_defs.h>
-#include <asm/ldt.h>
-#include <asm/mmu.h>
-#include <linux/smp.h>
-
-static inline void fill_ldt(struct desc_struct *desc,
-			    const struct user_desc *info)
-{
-	desc->limit0 = info->limit & 0x0ffff;
-	desc->base0 = info->base_addr & 0x0000ffff;
-
-	desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
-	desc->type = (info->read_exec_only ^ 1) << 1;
-	desc->type |= info->contents << 2;
-	desc->s = 1;
-	desc->dpl = 0x3;
-	desc->p = info->seg_not_present ^ 1;
-	desc->limit = (info->limit & 0xf0000) >> 16;
-	desc->avl = info->useable;
-	desc->d = info->seg_32bit;
-	desc->g = info->limit_in_pages;
-	desc->base2 = (info->base_addr & 0xff000000) >> 24;
-	/*
-	 * Don't allow setting of the lm bit. It is useless anyway
-	 * because 64bit system calls require __USER_CS:
-	 */
-	desc->l = 0;
-}
-
-extern struct desc_ptr idt_descr;
-extern gate_desc idt_table[];
-
-struct gdt_page {
-	struct desc_struct gdt[GDT_ENTRIES];
-} __attribute__((aligned(PAGE_SIZE)));
-DECLARE_PER_CPU(struct gdt_page, gdt_page);
-
-static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
-{
-	return per_cpu(gdt_page, cpu).gdt;
-}
-
-#ifdef CONFIG_X86_64
-
-static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
-			     unsigned dpl, unsigned ist, unsigned seg)
-{
-	gate->offset_low = PTR_LOW(func);
-	gate->segment = __KERNEL_CS;
-	gate->ist = ist;
-	gate->p = 1;
-	gate->dpl = dpl;
-	gate->zero0 = 0;
-	gate->zero1 = 0;
-	gate->type = type;
-	gate->offset_middle = PTR_MIDDLE(func);
-	gate->offset_high = PTR_HIGH(func);
-}
-
-#else
-static inline void pack_gate(gate_desc *gate, unsigned char type,
-			     unsigned long base, unsigned dpl, unsigned flags,
-			     unsigned short seg)
-{
-	gate->a = (seg << 16) | (base & 0xffff);
-	gate->b = (base & 0xffff0000) |
-		  (((0x80 | type | (dpl << 5)) & 0xff) << 8);
-}
-
-#endif
-
-static inline int desc_empty(const void *ptr)
-{
-	const u32 *desc = ptr;
-	return !(desc[0] | desc[1]);
-}
-
-#ifdef CONFIG_PARAVIRT
-#include <asm/paravirt.h>
-#else
-#define load_TR_desc() native_load_tr_desc()
-#define load_gdt(dtr) native_load_gdt(dtr)
-#define load_idt(dtr) native_load_idt(dtr)
-#define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
-#define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))
-
-#define store_gdt(dtr) native_store_gdt(dtr)
-#define store_idt(dtr) native_store_idt(dtr)
-#define store_tr(tr) (tr = native_store_tr())
-#define store_ldt(ldt) asm("sldt %0":"=m" (ldt))
-
-#define load_TLS(t, cpu) native_load_tls(t, cpu)
-#define set_ldt native_set_ldt
-
-#define write_ldt_entry(dt, entry, desc)	\
-	native_write_ldt_entry(dt, entry, desc)
-#define write_gdt_entry(dt, entry, desc, type)		\
-	native_write_gdt_entry(dt, entry, desc, type)
-#define write_idt_entry(dt, entry, g)		\
-	native_write_idt_entry(dt, entry, g)
-
-static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
-{
-}
-
-static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
-{
-}
-#endif	/* CONFIG_PARAVIRT */
-
-static inline void native_write_idt_entry(gate_desc *idt, int entry,
-					  const gate_desc *gate)
-{
-	memcpy(&idt[entry], gate, sizeof(*gate));
-}
-
-static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry,
-					  const void *desc)
-{
-	memcpy(&ldt[entry], desc, 8);
-}
-
-static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry,
-					  const void *desc, int type)
-{
-	unsigned int size;
-	switch (type) {
-	case DESC_TSS:
-		size = sizeof(tss_desc);
-		break;
-	case DESC_LDT:
-		size = sizeof(ldt_desc);
-		break;
-	default:
-		size = sizeof(struct desc_struct);
-		break;
-	}
-	memcpy(&gdt[entry], desc, size);
-}
-
-static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
-				   unsigned long limit, unsigned char type,
-				   unsigned char flags)
-{
-	desc->a = ((base & 0xffff) << 16) | (limit & 0xffff);
-	desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) |
-		(limit & 0x000f0000) | ((type & 0xff) << 8) |
-		((flags & 0xf) << 20);
-	desc->p = 1;
-}
-
-
-static inline void set_tssldt_descriptor(void *d, unsigned long addr,
-					 unsigned type, unsigned size)
-{
-#ifdef CONFIG_X86_64
-	struct ldttss_desc64 *desc = d;
-	memset(desc, 0, sizeof(*desc));
-	desc->limit0 = size & 0xFFFF;
-	desc->base0 = PTR_LOW(addr);
-	desc->base1 = PTR_MIDDLE(addr) & 0xFF;
-	desc->type = type;
-	desc->p = 1;
-	desc->limit1 = (size >> 16) & 0xF;
-	desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF;
-	desc->base3 = PTR_HIGH(addr);
-#else
-	pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0);
-#endif
-}
-
-static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
-{
-	struct desc_struct *d = get_cpu_gdt_table(cpu);
-	tss_desc tss;
-
-	/*
-	 * sizeof(unsigned long) coming from an extra "long" at the end
-	 * of the iobitmap. See tss_struct definition in processor.h
-	 *
-	 * -1? seg base+limit should be pointing to the address of the
-	 * last valid byte
-	 */
-	set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
-			      IO_BITMAP_OFFSET + IO_BITMAP_BYTES +
-			      sizeof(unsigned long) - 1);
-	write_gdt_entry(d, entry, &tss, DESC_TSS);
-}
-
-#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
-
-static inline void native_set_ldt(const void *addr, unsigned int entries)
-{
-	if (likely(entries == 0))
-		asm volatile("lldt %w0"::"q" (0));
-	else {
-		unsigned cpu = smp_processor_id();
-		ldt_desc ldt;
-
-		set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
-				      entries * LDT_ENTRY_SIZE - 1);
-		write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT,
-				&ldt, DESC_LDT);
-		asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
-	}
-}
-
-static inline void native_load_tr_desc(void)
-{
-	asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
-}
-
-static inline void native_load_gdt(const struct desc_ptr *dtr)
-{
-	asm volatile("lgdt %0"::"m" (*dtr));
-}
-
-static inline void native_load_idt(const struct desc_ptr *dtr)
-{
-	asm volatile("lidt %0"::"m" (*dtr));
-}
-
-static inline void native_store_gdt(struct desc_ptr *dtr)
-{
-	asm volatile("sgdt %0":"=m" (*dtr));
-}
-
-static inline void native_store_idt(struct desc_ptr *dtr)
-{
-	asm volatile("sidt %0":"=m" (*dtr));
-}
-
-static inline unsigned long native_store_tr(void)
-{
-	unsigned long tr;
-	asm volatile("str %0":"=r" (tr));
-	return tr;
-}
-
-static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
-{
-	unsigned int i;
-	struct desc_struct *gdt = get_cpu_gdt_table(cpu);
-
-	for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
-		gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
-}
-
-#define _LDT_empty(info)				\
-	((info)->base_addr		== 0	&&	\
-	 (info)->limit			== 0	&&	\
-	 (info)->contents		== 0	&&	\
-	 (info)->read_exec_only		== 1	&&	\
-	 (info)->seg_32bit		== 0	&&	\
-	 (info)->limit_in_pages		== 0	&&	\
-	 (info)->seg_not_present	== 1	&&	\
-	 (info)->useable		== 0)
-
-#ifdef CONFIG_X86_64
-#define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
-#else
-#define LDT_empty(info) (_LDT_empty(info))
-#endif
-
-static inline void clear_LDT(void)
-{
-	set_ldt(NULL, 0);
-}
-
-/*
- * load one particular LDT into the current CPU
- */
-static inline void load_LDT_nolock(mm_context_t *pc)
-{
-	set_ldt(pc->ldt, pc->size);
-}
-
-static inline void load_LDT(mm_context_t *pc)
-{
-	preempt_disable();
-	load_LDT_nolock(pc);
-	preempt_enable();
-}
-
-static inline unsigned long get_desc_base(const struct desc_struct *desc)
-{
-	return desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24);
-}
-
-static inline unsigned long get_desc_limit(const struct desc_struct *desc)
-{
-	return desc->limit0 | (desc->limit << 16);
-}
-
-static inline void _set_gate(int gate, unsigned type, void *addr,
-			     unsigned dpl, unsigned ist, unsigned seg)
-{
-	gate_desc s;
-	pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
-	/*
-	 * does not need to be atomic because it is only done once at
-	 * setup time
-	 */
-	write_idt_entry(idt_table, gate, &s);
-}
-
-/*
- * This needs to use 'idt_table' rather than 'idt', and
- * thus use the _nonmapped_ version of the IDT, as the
- * Pentium F0 0F bugfix can have resulted in the mapped
- * IDT being write-protected.
- */
-static inline void set_intr_gate(unsigned int n, void *addr)
-{
-	BUG_ON((unsigned)n > 0xFF);
-	_set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS);
-}
-
-#define SYS_VECTOR_FREE		0
-#define SYS_VECTOR_ALLOCED	1
-
-extern int first_system_vector;
-extern char system_vectors[];
-
-static inline void alloc_system_vector(int vector)
-{
-	if (system_vectors[vector] == SYS_VECTOR_FREE) {
-		system_vectors[vector] = SYS_VECTOR_ALLOCED;
-		if (first_system_vector > vector)
-			first_system_vector = vector;
-	} else
-		BUG();
-}
-
-static inline void alloc_intr_gate(unsigned int n, void *addr)
-{
-	alloc_system_vector(n);
-	set_intr_gate(n, addr);
-}
-
-/*
- * This routine sets up an interrupt gate at directory privilege level 3.
- */
-static inline void set_system_intr_gate(unsigned int n, void *addr)
-{
-	BUG_ON((unsigned)n > 0xFF);
-	_set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
-}
-
-static inline void set_system_trap_gate(unsigned int n, void *addr)
-{
-	BUG_ON((unsigned)n > 0xFF);
-	_set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
-}
-
-static inline void set_trap_gate(unsigned int n, void *addr)
-{
-	BUG_ON((unsigned)n > 0xFF);
-	_set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
-}
-
-static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
-{
-	BUG_ON((unsigned)n > 0xFF);
-	_set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
-}
-
-static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
-{
-	BUG_ON((unsigned)n > 0xFF);
-	_set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
-}
-
-static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist)
-{
-	BUG_ON((unsigned)n > 0xFF);
-	_set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
-}
-
-#else
-/*
- * GET_DESC_BASE reads the descriptor base of the specified segment.
- *
- * Args:
- *    idx - descriptor index
- *    gdt - GDT pointer
- *    base - 32bit register to which the base will be written
- *    lo_w - lo word of the "base" register
- *    lo_b - lo byte of the "base" register
- *    hi_b - hi byte of the low word of the "base" register
- *
- * Example:
- *    GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah)
- *    Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax.
- */
-#define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \
-	movb idx * 8 + 4(gdt), lo_b;			\
-	movb idx * 8 + 7(gdt), hi_b;			\
-	shll $16, base;					\
-	movw idx * 8 + 2(gdt), lo_w;
-
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* ASM_X86__DESC_H */
diff --git a/include/asm-x86/desc_defs.h b/include/asm-x86/desc_defs.h
deleted file mode 100644
index b881db664b46..000000000000
--- a/include/asm-x86/desc_defs.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* Written 2000 by Andi Kleen */
-#ifndef ASM_X86__DESC_DEFS_H
-#define ASM_X86__DESC_DEFS_H
-
-/*
- * Segment descriptor structure definitions, usable from both x86_64 and i386
- * archs.
- */
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-/*
- * FIXME: Acessing the desc_struct through its fields is more elegant,
- * and should be the one valid thing to do. However, a lot of open code
- * still touches the a and b acessors, and doing this allow us to do it
- * incrementally. We keep the signature as a struct, rather than an union,
- * so we can get rid of it transparently in the future -- glommer
- */
-/* 8 byte segment descriptor */
-struct desc_struct {
-	union {
-		struct {
-			unsigned int a;
-			unsigned int b;
-		};
-		struct {
-			u16 limit0;
-			u16 base0;
-			unsigned base1: 8, type: 4, s: 1, dpl: 2, p: 1;
-			unsigned limit: 4, avl: 1, l: 1, d: 1, g: 1, base2: 8;
-		};
-	};
-} __attribute__((packed));
-
-enum {
-	GATE_INTERRUPT = 0xE,
-	GATE_TRAP = 0xF,
-	GATE_CALL = 0xC,
-	GATE_TASK = 0x5,
-};
-
-/* 16byte gate */
-struct gate_struct64 {
-	u16 offset_low;
-	u16 segment;
-	unsigned ist : 3, zero0 : 5, type : 5, dpl : 2, p : 1;
-	u16 offset_middle;
-	u32 offset_high;
-	u32 zero1;
-} __attribute__((packed));
-
-#define PTR_LOW(x) ((unsigned long long)(x) & 0xFFFF)
-#define PTR_MIDDLE(x) (((unsigned long long)(x) >> 16) & 0xFFFF)
-#define PTR_HIGH(x) ((unsigned long long)(x) >> 32)
-
-enum {
-	DESC_TSS = 0x9,
-	DESC_LDT = 0x2,
-	DESCTYPE_S = 0x10,	/* !system */
-};
-
-/* LDT or TSS descriptor in the GDT. 16 bytes. */
-struct ldttss_desc64 {
-	u16 limit0;
-	u16 base0;
-	unsigned base1 : 8, type : 5, dpl : 2, p : 1;
-	unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
-	u32 base3;
-	u32 zero1;
-} __attribute__((packed));
-
-#ifdef CONFIG_X86_64
-typedef struct gate_struct64 gate_desc;
-typedef struct ldttss_desc64 ldt_desc;
-typedef struct ldttss_desc64 tss_desc;
-#define gate_offset(g) ((g).offset_low | ((unsigned long)(g).offset_middle << 16) | ((unsigned long)(g).offset_high << 32))
-#define gate_segment(g) ((g).segment)
-#else
-typedef struct desc_struct gate_desc;
-typedef struct desc_struct ldt_desc;
-typedef struct desc_struct tss_desc;
-#define gate_offset(g)		(((g).b & 0xffff0000) | ((g).a & 0x0000ffff))
-#define gate_segment(g)		((g).a >> 16)
-#endif
-
-struct desc_ptr {
-	unsigned short size;
-	unsigned long address;
-} __attribute__((packed)) ;
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* ASM_X86__DESC_DEFS_H */
diff --git a/include/asm-x86/device.h b/include/asm-x86/device.h
deleted file mode 100644
index 1bece04c7d9d..000000000000
--- a/include/asm-x86/device.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef ASM_X86__DEVICE_H
-#define ASM_X86__DEVICE_H
-
-struct dev_archdata {
-#ifdef CONFIG_ACPI
-	void	*acpi_handle;
-#endif
-#ifdef CONFIG_X86_64
-struct dma_mapping_ops *dma_ops;
-#endif
-#ifdef CONFIG_DMAR
-	void *iommu; /* hook for IOMMU specific extension */
-#endif
-};
-
-#endif /* ASM_X86__DEVICE_H */
diff --git a/include/asm-x86/div64.h b/include/asm-x86/div64.h
deleted file mode 100644
index f9530f23f1d6..000000000000
--- a/include/asm-x86/div64.h
+++ /dev/null
@@ -1,60 +0,0 @@
-#ifndef ASM_X86__DIV64_H
-#define ASM_X86__DIV64_H
-
-#ifdef CONFIG_X86_32
-
-#include <linux/types.h>
-
-/*
- * do_div() is NOT a C function. It wants to return
- * two values (the quotient and the remainder), but
- * since that doesn't work very well in C, what it
- * does is:
- *
- * - modifies the 64-bit dividend _in_place_
- * - returns the 32-bit remainder
- *
- * This ends up being the most efficient "calling
- * convention" on x86.
- */
-#define do_div(n, base)						\
-({								\
-	unsigned long __upper, __low, __high, __mod, __base;	\
-	__base = (base);					\
-	asm("":"=a" (__low), "=d" (__high) : "A" (n));		\
-	__upper = __high;					\
-	if (__high) {						\
-		__upper = __high % (__base);			\
-		__high = __high / (__base);			\
-	}							\
-	asm("divl %2":"=a" (__low), "=d" (__mod)		\
-	    : "rm" (__base), "0" (__low), "1" (__upper));	\
-	asm("":"=A" (n) : "a" (__low), "d" (__high));		\
-	__mod;							\
-})
-
-static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder)
-{
-	union {
-		u64 v64;
-		u32 v32[2];
-	} d = { dividend };
-	u32 upper;
-
-	upper = d.v32[1];
-	d.v32[1] = 0;
-	if (upper >= divisor) {
-		d.v32[1] = upper / divisor;
-		upper %= divisor;
-	}
-	asm ("divl %2" : "=a" (d.v32[0]), "=d" (*remainder) :
-		"rm" (divisor), "0" (d.v32[0]), "1" (upper));
-	return d.v64;
-}
-#define div_u64_rem	div_u64_rem
-
-#else
-# include <asm-generic/div64.h>
-#endif /* CONFIG_X86_32 */
-
-#endif /* ASM_X86__DIV64_H */
diff --git a/include/asm-x86/dma-mapping.h b/include/asm-x86/dma-mapping.h
deleted file mode 100644
index 219c33d6361c..000000000000
--- a/include/asm-x86/dma-mapping.h
+++ /dev/null
@@ -1,308 +0,0 @@
-#ifndef ASM_X86__DMA_MAPPING_H
-#define ASM_X86__DMA_MAPPING_H
-
-/*
- * IOMMU interface. See Documentation/DMA-mapping.txt and DMA-API.txt for
- * documentation.
- */
-
-#include <linux/scatterlist.h>
-#include <asm/io.h>
-#include <asm/swiotlb.h>
-#include <asm-generic/dma-coherent.h>
-
-extern dma_addr_t bad_dma_address;
-extern int iommu_merge;
-extern struct device x86_dma_fallback_dev;
-extern int panic_on_overflow;
-
-struct dma_mapping_ops {
-	int             (*mapping_error)(struct device *dev,
-					 dma_addr_t dma_addr);
-	void*           (*alloc_coherent)(struct device *dev, size_t size,
-				dma_addr_t *dma_handle, gfp_t gfp);
-	void            (*free_coherent)(struct device *dev, size_t size,
-				void *vaddr, dma_addr_t dma_handle);
-	dma_addr_t      (*map_single)(struct device *hwdev, phys_addr_t ptr,
-				size_t size, int direction);
-	void            (*unmap_single)(struct device *dev, dma_addr_t addr,
-				size_t size, int direction);
-	void            (*sync_single_for_cpu)(struct device *hwdev,
-				dma_addr_t dma_handle, size_t size,
-				int direction);
-	void            (*sync_single_for_device)(struct device *hwdev,
-				dma_addr_t dma_handle, size_t size,
-				int direction);
-	void            (*sync_single_range_for_cpu)(struct device *hwdev,
-				dma_addr_t dma_handle, unsigned long offset,
-				size_t size, int direction);
-	void            (*sync_single_range_for_device)(struct device *hwdev,
-				dma_addr_t dma_handle, unsigned long offset,
-				size_t size, int direction);
-	void            (*sync_sg_for_cpu)(struct device *hwdev,
-				struct scatterlist *sg, int nelems,
-				int direction);
-	void            (*sync_sg_for_device)(struct device *hwdev,
-				struct scatterlist *sg, int nelems,
-				int direction);
-	int             (*map_sg)(struct device *hwdev, struct scatterlist *sg,
-				int nents, int direction);
-	void            (*unmap_sg)(struct device *hwdev,
-				struct scatterlist *sg, int nents,
-				int direction);
-	int             (*dma_supported)(struct device *hwdev, u64 mask);
-	int		is_phys;
-};
-
-extern struct dma_mapping_ops *dma_ops;
-
-static inline struct dma_mapping_ops *get_dma_ops(struct device *dev)
-{
-#ifdef CONFIG_X86_32
-	return dma_ops;
-#else
-	if (unlikely(!dev) || !dev->archdata.dma_ops)
-		return dma_ops;
-	else
-		return dev->archdata.dma_ops;
-#endif /* ASM_X86__DMA_MAPPING_H */
-}
-
-/* Make sure we keep the same behaviour */
-static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
-{
-#ifdef CONFIG_X86_32
-	return 0;
-#else
-	struct dma_mapping_ops *ops = get_dma_ops(dev);
-	if (ops->mapping_error)
-		return ops->mapping_error(dev, dma_addr);
-
-	return (dma_addr == bad_dma_address);
-#endif
-}
-
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-#define dma_is_consistent(d, h)	(1)
-
-extern int dma_supported(struct device *hwdev, u64 mask);
-extern int dma_set_mask(struct device *dev, u64 mask);
-
-extern void *dma_generic_alloc_coherent(struct device *dev, size_t size,
-					dma_addr_t *dma_addr, gfp_t flag);
-
-static inline dma_addr_t
-dma_map_single(struct device *hwdev, void *ptr, size_t size,
-	       int direction)
-{
-	struct dma_mapping_ops *ops = get_dma_ops(hwdev);
-
-	BUG_ON(!valid_dma_direction(direction));
-	return ops->map_single(hwdev, virt_to_phys(ptr), size, direction);
-}
-
-static inline void
-dma_unmap_single(struct device *dev, dma_addr_t addr, size_t size,
-		 int direction)
-{
-	struct dma_mapping_ops *ops = get_dma_ops(dev);
-
-	BUG_ON(!valid_dma_direction(direction));
-	if (ops->unmap_single)
-		ops->unmap_single(dev, addr, size, direction);
-}
-
-static inline int
-dma_map_sg(struct device *hwdev, struct scatterlist *sg,
-	   int nents, int direction)
-{
-	struct dma_mapping_ops *ops = get_dma_ops(hwdev);
-
-	BUG_ON(!valid_dma_direction(direction));
-	return ops->map_sg(hwdev, sg, nents, direction);
-}
-
-static inline void
-dma_unmap_sg(struct device *hwdev, struct scatterlist *sg, int nents,
-	     int direction)
-{
-	struct dma_mapping_ops *ops = get_dma_ops(hwdev);
-
-	BUG_ON(!valid_dma_direction(direction));
-	if (ops->unmap_sg)
-		ops->unmap_sg(hwdev, sg, nents, direction);
-}
-
-static inline void
-dma_sync_single_for_cpu(struct device *hwdev, dma_addr_t dma_handle,
-			size_t size, int direction)
-{
-	struct dma_mapping_ops *ops = get_dma_ops(hwdev);
-
-	BUG_ON(!valid_dma_direction(direction));
-	if (ops->sync_single_for_cpu)
-		ops->sync_single_for_cpu(hwdev, dma_handle, size, direction);
-	flush_write_buffers();
-}
-
-static inline void
-dma_sync_single_for_device(struct device *hwdev, dma_addr_t dma_handle,
-			   size_t size, int direction)
-{
-	struct dma_mapping_ops *ops = get_dma_ops(hwdev);
-
-	BUG_ON(!valid_dma_direction(direction));
-	if (ops->sync_single_for_device)
-		ops->sync_single_for_device(hwdev, dma_handle, size, direction);
-	flush_write_buffers();
-}
-
-static inline void
-dma_sync_single_range_for_cpu(struct device *hwdev, dma_addr_t dma_handle,
-			      unsigned long offset, size_t size, int direction)
-{
-	struct dma_mapping_ops *ops = get_dma_ops(hwdev);
-
-	BUG_ON(!valid_dma_direction(direction));
-	if (ops->sync_single_range_for_cpu)
-		ops->sync_single_range_for_cpu(hwdev, dma_handle, offset,
-					       size, direction);
-	flush_write_buffers();
-}
-
-static inline void
-dma_sync_single_range_for_device(struct device *hwdev, dma_addr_t dma_handle,
-				 unsigned long offset, size_t size,
-				 int direction)
-{
-	struct dma_mapping_ops *ops = get_dma_ops(hwdev);
-
-	BUG_ON(!valid_dma_direction(direction));
-	if (ops->sync_single_range_for_device)
-		ops->sync_single_range_for_device(hwdev, dma_handle,
-						  offset, size, direction);
-	flush_write_buffers();
-}
-
-static inline void
-dma_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg,
-		    int nelems, int direction)
-{
-	struct dma_mapping_ops *ops = get_dma_ops(hwdev);
-
-	BUG_ON(!valid_dma_direction(direction));
-	if (ops->sync_sg_for_cpu)
-		ops->sync_sg_for_cpu(hwdev, sg, nelems, direction);
-	flush_write_buffers();
-}
-
-static inline void
-dma_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg,
-		       int nelems, int direction)
-{
-	struct dma_mapping_ops *ops = get_dma_ops(hwdev);
-
-	BUG_ON(!valid_dma_direction(direction));
-	if (ops->sync_sg_for_device)
-		ops->sync_sg_for_device(hwdev, sg, nelems, direction);
-
-	flush_write_buffers();
-}
-
-static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
-				      size_t offset, size_t size,
-				      int direction)
-{
-	struct dma_mapping_ops *ops = get_dma_ops(dev);
-
-	BUG_ON(!valid_dma_direction(direction));
-	return ops->map_single(dev, page_to_phys(page) + offset,
-			       size, direction);
-}
-
-static inline void dma_unmap_page(struct device *dev, dma_addr_t addr,
-				  size_t size, int direction)
-{
-	dma_unmap_single(dev, addr, size, direction);
-}
-
-static inline void
-dma_cache_sync(struct device *dev, void *vaddr, size_t size,
-	enum dma_data_direction dir)
-{
-	flush_write_buffers();
-}
-
-static inline int dma_get_cache_alignment(void)
-{
-	/* no easy way to get cache size on all x86, so return the
-	 * maximum possible, to be safe */
-	return boot_cpu_data.x86_clflush_size;
-}
-
-static inline unsigned long dma_alloc_coherent_mask(struct device *dev,
-						    gfp_t gfp)
-{
-	unsigned long dma_mask = 0;
-
-	dma_mask = dev->coherent_dma_mask;
-	if (!dma_mask)
-		dma_mask = (gfp & GFP_DMA) ? DMA_24BIT_MASK : DMA_32BIT_MASK;
-
-	return dma_mask;
-}
-
-static inline gfp_t dma_alloc_coherent_gfp_flags(struct device *dev, gfp_t gfp)
-{
-#ifdef CONFIG_X86_64
-	unsigned long dma_mask = dma_alloc_coherent_mask(dev, gfp);
-
-	if (dma_mask <= DMA_32BIT_MASK && !(gfp & GFP_DMA))
-		gfp |= GFP_DMA32;
-#endif
-       return gfp;
-}
-
-static inline void *
-dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
-		gfp_t gfp)
-{
-	struct dma_mapping_ops *ops = get_dma_ops(dev);
-	void *memory;
-
-	gfp &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
-
-	if (dma_alloc_from_coherent(dev, size, dma_handle, &memory))
-		return memory;
-
-	if (!dev) {
-		dev = &x86_dma_fallback_dev;
-		gfp |= GFP_DMA;
-	}
-
-	if (!is_device_dma_capable(dev))
-		return NULL;
-
-	if (!ops->alloc_coherent)
-		return NULL;
-
-	return ops->alloc_coherent(dev, size, dma_handle,
-				   dma_alloc_coherent_gfp_flags(dev, gfp));
-}
-
-static inline void dma_free_coherent(struct device *dev, size_t size,
-				     void *vaddr, dma_addr_t bus)
-{
-	struct dma_mapping_ops *ops = get_dma_ops(dev);
-
-	WARN_ON(irqs_disabled());       /* for portability */
-
-	if (dma_release_from_coherent(dev, get_order(size), vaddr))
-		return;
-
-	if (ops->free_coherent)
-		ops->free_coherent(dev, size, vaddr, bus);
-}
-
-#endif
diff --git a/include/asm-x86/dma.h b/include/asm-x86/dma.h
deleted file mode 100644
index c9f7a4eec555..000000000000
--- a/include/asm-x86/dma.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- * linux/include/asm/dma.h: Defines for using and allocating dma channels.
- * Written by Hennus Bergman, 1992.
- * High DMA channel support & info by Hannu Savolainen
- * and John Boyd, Nov. 1992.
- */
-
-#ifndef ASM_X86__DMA_H
-#define ASM_X86__DMA_H
-
-#include <linux/spinlock.h>	/* And spinlocks */
-#include <asm/io.h>		/* need byte IO */
-#include <linux/delay.h>
-
-#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
-#define dma_outb	outb_p
-#else
-#define dma_outb	outb
-#endif
-
-#define dma_inb		inb
-
-/*
- * NOTES about DMA transfers:
- *
- *  controller 1: channels 0-3, byte operations, ports 00-1F
- *  controller 2: channels 4-7, word operations, ports C0-DF
- *
- *  - ALL registers are 8 bits only, regardless of transfer size
- *  - channel 4 is not used - cascades 1 into 2.
- *  - channels 0-3 are byte - addresses/counts are for physical bytes
- *  - channels 5-7 are word - addresses/counts are for physical words
- *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
- *  - transfer count loaded to registers is 1 less than actual count
- *  - controller 2 offsets are all even (2x offsets for controller 1)
- *  - page registers for 5-7 don't use data bit 0, represent 128K pages
- *  - page registers for 0-3 use bit 0, represent 64K pages
- *
- * DMA transfers are limited to the lower 16MB of _physical_ memory.
- * Note that addresses loaded into registers must be _physical_ addresses,
- * not logical addresses (which may differ if paging is active).
- *
- *  Address mapping for channels 0-3:
- *
- *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *   P7  ...  P0  A7 ... A0  A7 ... A0
- * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
- *
- *  Address mapping for channels 5-7:
- *
- *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
- *    |  ...  |   \   \   ... \  \  \  ... \  \
- *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
- *    |  ...  |     \   \   ... \  \  \  ... \
- *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
- * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
- *
- * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
- * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
- * the hardware level, so odd-byte transfers aren't possible).
- *
- * Transfer count (_not # bytes_) is limited to 64K, represented as actual
- * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
- * and up to 128K bytes may be transferred on channels 5-7 in one operation.
- *
- */
-
-#define MAX_DMA_CHANNELS	8
-
-#ifdef CONFIG_X86_32
-
-/* The maximum address that we can perform a DMA transfer to on this platform */
-#define MAX_DMA_ADDRESS      (PAGE_OFFSET + 0x1000000)
-
-#else
-
-/* 16MB ISA DMA zone */
-#define MAX_DMA_PFN   ((16 * 1024 * 1024) >> PAGE_SHIFT)
-
-/* 4GB broken PCI/AGP hardware bus master zone */
-#define MAX_DMA32_PFN ((4UL * 1024 * 1024 * 1024) >> PAGE_SHIFT)
-
-/* Compat define for old dma zone */
-#define MAX_DMA_ADDRESS ((unsigned long)__va(MAX_DMA_PFN << PAGE_SHIFT))
-
-#endif
-
-/* 8237 DMA controllers */
-#define IO_DMA1_BASE	0x00	/* 8 bit slave DMA, channels 0..3 */
-#define IO_DMA2_BASE	0xC0	/* 16 bit master DMA, ch 4(=slave input)..7 */
-
-/* DMA controller registers */
-#define DMA1_CMD_REG		0x08	/* command register (w) */
-#define DMA1_STAT_REG		0x08	/* status register (r) */
-#define DMA1_REQ_REG		0x09    /* request register (w) */
-#define DMA1_MASK_REG		0x0A	/* single-channel mask (w) */
-#define DMA1_MODE_REG		0x0B	/* mode register (w) */
-#define DMA1_CLEAR_FF_REG	0x0C	/* clear pointer flip-flop (w) */
-#define DMA1_TEMP_REG		0x0D    /* Temporary Register (r) */
-#define DMA1_RESET_REG		0x0D	/* Master Clear (w) */
-#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
-#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
-
-#define DMA2_CMD_REG		0xD0	/* command register (w) */
-#define DMA2_STAT_REG		0xD0	/* status register (r) */
-#define DMA2_REQ_REG		0xD2    /* request register (w) */
-#define DMA2_MASK_REG		0xD4	/* single-channel mask (w) */
-#define DMA2_MODE_REG		0xD6	/* mode register (w) */
-#define DMA2_CLEAR_FF_REG	0xD8	/* clear pointer flip-flop (w) */
-#define DMA2_TEMP_REG		0xDA    /* Temporary Register (r) */
-#define DMA2_RESET_REG		0xDA	/* Master Clear (w) */
-#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
-#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
-
-#define DMA_ADDR_0		0x00    /* DMA address registers */
-#define DMA_ADDR_1		0x02
-#define DMA_ADDR_2		0x04
-#define DMA_ADDR_3		0x06
-#define DMA_ADDR_4		0xC0
-#define DMA_ADDR_5		0xC4
-#define DMA_ADDR_6		0xC8
-#define DMA_ADDR_7		0xCC
-
-#define DMA_CNT_0		0x01    /* DMA count registers */
-#define DMA_CNT_1		0x03
-#define DMA_CNT_2		0x05
-#define DMA_CNT_3		0x07
-#define DMA_CNT_4		0xC2
-#define DMA_CNT_5		0xC6
-#define DMA_CNT_6		0xCA
-#define DMA_CNT_7		0xCE
-
-#define DMA_PAGE_0		0x87    /* DMA page registers */
-#define DMA_PAGE_1		0x83
-#define DMA_PAGE_2		0x81
-#define DMA_PAGE_3		0x82
-#define DMA_PAGE_5		0x8B
-#define DMA_PAGE_6		0x89
-#define DMA_PAGE_7		0x8A
-
-/* I/O to memory, no autoinit, increment, single mode */
-#define DMA_MODE_READ		0x44
-/* memory to I/O, no autoinit, increment, single mode */
-#define DMA_MODE_WRITE		0x48
-/* pass thru DREQ->HRQ, DACK<-HLDA only */
-#define DMA_MODE_CASCADE	0xC0
-
-#define DMA_AUTOINIT		0x10
-
-
-extern spinlock_t  dma_spin_lock;
-
-static inline unsigned long claim_dma_lock(void)
-{
-	unsigned long flags;
-	spin_lock_irqsave(&dma_spin_lock, flags);
-	return flags;
-}
-
-static inline void release_dma_lock(unsigned long flags)
-{
-	spin_unlock_irqrestore(&dma_spin_lock, flags);
-}
-
-/* enable/disable a specific DMA channel */
-static inline void enable_dma(unsigned int dmanr)
-{
-	if (dmanr <= 3)
-		dma_outb(dmanr, DMA1_MASK_REG);
-	else
-		dma_outb(dmanr & 3, DMA2_MASK_REG);
-}
-
-static inline void disable_dma(unsigned int dmanr)
-{
-	if (dmanr <= 3)
-		dma_outb(dmanr | 4, DMA1_MASK_REG);
-	else
-		dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
-}
-
-/* Clear the 'DMA Pointer Flip Flop'.
- * Write 0 for LSB/MSB, 1 for MSB/LSB access.
- * Use this once to initialize the FF to a known state.
- * After that, keep track of it. :-)
- * --- In order to do that, the DMA routines below should ---
- * --- only be used while holding the DMA lock ! ---
- */
-static inline void clear_dma_ff(unsigned int dmanr)
-{
-	if (dmanr <= 3)
-		dma_outb(0, DMA1_CLEAR_FF_REG);
-	else
-		dma_outb(0, DMA2_CLEAR_FF_REG);
-}
-
-/* set mode (above) for a specific DMA channel */
-static inline void set_dma_mode(unsigned int dmanr, char mode)
-{
-	if (dmanr <= 3)
-		dma_outb(mode | dmanr, DMA1_MODE_REG);
-	else
-		dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
-}
-
-/* Set only the page register bits of the transfer address.
- * This is used for successive transfers when we know the contents of
- * the lower 16 bits of the DMA current address register, but a 64k boundary
- * may have been crossed.
- */
-static inline void set_dma_page(unsigned int dmanr, char pagenr)
-{
-	switch (dmanr) {
-	case 0:
-		dma_outb(pagenr, DMA_PAGE_0);
-		break;
-	case 1:
-		dma_outb(pagenr, DMA_PAGE_1);
-		break;
-	case 2:
-		dma_outb(pagenr, DMA_PAGE_2);
-		break;
-	case 3:
-		dma_outb(pagenr, DMA_PAGE_3);
-		break;
-	case 5:
-		dma_outb(pagenr & 0xfe, DMA_PAGE_5);
-		break;
-	case 6:
-		dma_outb(pagenr & 0xfe, DMA_PAGE_6);
-		break;
-	case 7:
-		dma_outb(pagenr & 0xfe, DMA_PAGE_7);
-		break;
-	}
-}
-
-
-/* Set transfer address & page bits for specific DMA channel.
- * Assumes dma flipflop is clear.
- */
-static inline void set_dma_addr(unsigned int dmanr, unsigned int a)
-{
-	set_dma_page(dmanr, a>>16);
-	if (dmanr <= 3)  {
-		dma_outb(a & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
-		dma_outb((a >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
-	}  else  {
-		dma_outb((a >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
-		dma_outb((a >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
-	}
-}
-
-
-/* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
- * a specific DMA channel.
- * You must ensure the parameters are valid.
- * NOTE: from a manual: "the number of transfers is one more
- * than the initial word count"! This is taken into account.
- * Assumes dma flip-flop is clear.
- * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
- */
-static inline void set_dma_count(unsigned int dmanr, unsigned int count)
-{
-	count--;
-	if (dmanr <= 3)  {
-		dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
-		dma_outb((count >> 8) & 0xff,
-			 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
-	} else {
-		dma_outb((count >> 1) & 0xff,
-			 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
-		dma_outb((count >> 9) & 0xff,
-			 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
-	}
-}
-
-
-/* Get DMA residue count. After a DMA transfer, this
- * should return zero. Reading this while a DMA transfer is
- * still in progress will return unpredictable results.
- * If called before the channel has been used, it may return 1.
- * Otherwise, it returns the number of _bytes_ left to transfer.
- *
- * Assumes DMA flip-flop is clear.
- */
-static inline int get_dma_residue(unsigned int dmanr)
-{
-	unsigned int io_port;
-	/* using short to get 16-bit wrap around */
-	unsigned short count;
-
-	io_port = (dmanr <= 3) ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
-		: ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
-
-	count = 1 + dma_inb(io_port);
-	count += dma_inb(io_port) << 8;
-
-	return (dmanr <= 3) ? count : (count << 1);
-}
-
-
-/* These are in kernel/dma.c: */
-extern int request_dma(unsigned int dmanr, const char *device_id);
-extern void free_dma(unsigned int dmanr);
-
-/* From PCI */
-
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy	(0)
-#endif
-
-#endif /* ASM_X86__DMA_H */
diff --git a/include/asm-x86/dmi.h b/include/asm-x86/dmi.h
deleted file mode 100644
index 1cff6fe81fa5..000000000000
--- a/include/asm-x86/dmi.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef ASM_X86__DMI_H
-#define ASM_X86__DMI_H
-
-#include <asm/io.h>
-
-#define DMI_MAX_DATA 2048
-
-extern int dmi_alloc_index;
-extern char dmi_alloc_data[DMI_MAX_DATA];
-
-/* This is so early that there is no good way to allocate dynamic memory.
-   Allocate data in an BSS array. */
-static inline void *dmi_alloc(unsigned len)
-{
-	int idx = dmi_alloc_index;
-	if ((dmi_alloc_index + len) > DMI_MAX_DATA)
-		return NULL;
-	dmi_alloc_index += len;
-	return dmi_alloc_data + idx;
-}
-
-/* Use early IO mappings for DMI because it's initialized early */
-#define dmi_ioremap early_ioremap
-#define dmi_iounmap early_iounmap
-
-#endif /* ASM_X86__DMI_H */
diff --git a/include/asm-x86/ds.h b/include/asm-x86/ds.h
deleted file mode 100644
index c3c953a45b21..000000000000
--- a/include/asm-x86/ds.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * Debug Store (DS) support
- *
- * This provides a low-level interface to the hardware's Debug Store
- * feature that is used for branch trace store (BTS) and
- * precise-event based sampling (PEBS).
- *
- * It manages:
- * - per-thread and per-cpu allocation of BTS and PEBS
- * - buffer memory allocation (optional)
- * - buffer overflow handling
- * - buffer access
- *
- * It assumes:
- * - get_task_struct on all parameter tasks
- * - current is allowed to trace parameter tasks
- *
- *
- * Copyright (C) 2007-2008 Intel Corporation.
- * Markus Metzger <markus.t.metzger@intel.com>, 2007-2008
- */
-
-#ifndef ASM_X86__DS_H
-#define ASM_X86__DS_H
-
-#ifdef CONFIG_X86_DS
-
-#include <linux/types.h>
-#include <linux/init.h>
-
-
-struct task_struct;
-
-/*
- * Request BTS or PEBS
- *
- * Due to alignement constraints, the actual buffer may be slightly
- * smaller than the requested or provided buffer.
- *
- * Returns 0 on success; -Eerrno otherwise
- *
- * task: the task to request recording for;
- *       NULL for per-cpu recording on the current cpu
- * base: the base pointer for the (non-pageable) buffer;
- *       NULL if buffer allocation requested
- * size: the size of the requested or provided buffer
- * ovfl: pointer to a function to be called on buffer overflow;
- *       NULL if cyclic buffer requested
- */
-typedef void (*ds_ovfl_callback_t)(struct task_struct *);
-extern int ds_request_bts(struct task_struct *task, void *base, size_t size,
-			  ds_ovfl_callback_t ovfl);
-extern int ds_request_pebs(struct task_struct *task, void *base, size_t size,
-			   ds_ovfl_callback_t ovfl);
-
-/*
- * Release BTS or PEBS resources
- *
- * Frees buffers allocated on ds_request.
- *
- * Returns 0 on success; -Eerrno otherwise
- *
- * task: the task to release resources for;
- *       NULL to release resources for the current cpu
- */
-extern int ds_release_bts(struct task_struct *task);
-extern int ds_release_pebs(struct task_struct *task);
-
-/*
- * Return the (array) index of the write pointer.
- * (assuming an array of BTS/PEBS records)
- *
- * Returns -Eerrno on error
- *
- * task: the task to access;
- *       NULL to access the current cpu
- * pos (out): if not NULL, will hold the result
- */
-extern int ds_get_bts_index(struct task_struct *task, size_t *pos);
-extern int ds_get_pebs_index(struct task_struct *task, size_t *pos);
-
-/*
- * Return the (array) index one record beyond the end of the array.
- * (assuming an array of BTS/PEBS records)
- *
- * Returns -Eerrno on error
- *
- * task: the task to access;
- *       NULL to access the current cpu
- * pos (out): if not NULL, will hold the result
- */
-extern int ds_get_bts_end(struct task_struct *task, size_t *pos);
-extern int ds_get_pebs_end(struct task_struct *task, size_t *pos);
-
-/*
- * Provide a pointer to the BTS/PEBS record at parameter index.
- * (assuming an array of BTS/PEBS records)
- *
- * The pointer points directly into the buffer. The user is
- * responsible for copying the record.
- *
- * Returns the size of a single record on success; -Eerrno on error
- *
- * task: the task to access;
- *       NULL to access the current cpu
- * index: the index of the requested record
- * record (out): pointer to the requested record
- */
-extern int ds_access_bts(struct task_struct *task,
-			 size_t index, const void **record);
-extern int ds_access_pebs(struct task_struct *task,
-			  size_t index, const void **record);
-
-/*
- * Write one or more BTS/PEBS records at the write pointer index and
- * advance the write pointer.
- *
- * If size is not a multiple of the record size, trailing bytes are
- * zeroed out.
- *
- * May result in one or more overflow notifications.
- *
- * If called during overflow handling, that is, with index >=
- * interrupt threshold, the write will wrap around.
- *
- * An overflow notification is given if and when the interrupt
- * threshold is reached during or after the write.
- *
- * Returns the number of bytes written or -Eerrno.
- *
- * task: the task to access;
- *       NULL to access the current cpu
- * buffer: the buffer to write
- * size: the size of the buffer
- */
-extern int ds_write_bts(struct task_struct *task,
-			const void *buffer, size_t size);
-extern int ds_write_pebs(struct task_struct *task,
-			 const void *buffer, size_t size);
-
-/*
- * Same as ds_write_bts/pebs, but omit ownership checks.
- *
- * This is needed to have some other task than the owner of the
- * BTS/PEBS buffer or the parameter task itself write into the
- * respective buffer.
- */
-extern int ds_unchecked_write_bts(struct task_struct *task,
-				  const void *buffer, size_t size);
-extern int ds_unchecked_write_pebs(struct task_struct *task,
-				   const void *buffer, size_t size);
-
-/*
- * Reset the write pointer of the BTS/PEBS buffer.
- *
- * Returns 0 on success; -Eerrno on error
- *
- * task: the task to access;
- *       NULL to access the current cpu
- */
-extern int ds_reset_bts(struct task_struct *task);
-extern int ds_reset_pebs(struct task_struct *task);
-
-/*
- * Clear the BTS/PEBS buffer and reset the write pointer.
- * The entire buffer will be zeroed out.
- *
- * Returns 0 on success; -Eerrno on error
- *
- * task: the task to access;
- *       NULL to access the current cpu
- */
-extern int ds_clear_bts(struct task_struct *task);
-extern int ds_clear_pebs(struct task_struct *task);
-
-/*
- * Provide the PEBS counter reset value.
- *
- * Returns 0 on success; -Eerrno on error
- *
- * task: the task to access;
- *       NULL to access the current cpu
- * value (out): the counter reset value
- */
-extern int ds_get_pebs_reset(struct task_struct *task, u64 *value);
-
-/*
- * Set the PEBS counter reset value.
- *
- * Returns 0 on success; -Eerrno on error
- *
- * task: the task to access;
- *       NULL to access the current cpu
- * value: the new counter reset value
- */
-extern int ds_set_pebs_reset(struct task_struct *task, u64 value);
-
-/*
- * Initialization
- */
-struct cpuinfo_x86;
-extern void __cpuinit ds_init_intel(struct cpuinfo_x86 *);
-
-
-
-/*
- * The DS context - part of struct thread_struct.
- */
-struct ds_context {
-	/* pointer to the DS configuration; goes into MSR_IA32_DS_AREA */
-	unsigned char *ds;
-	/* the owner of the BTS and PEBS configuration, respectively */
-	struct task_struct *owner[2];
-	/* buffer overflow notification function for BTS and PEBS */
-	ds_ovfl_callback_t callback[2];
-	/* the original buffer address */
-	void *buffer[2];
-	/* the number of allocated pages for on-request allocated buffers */
-	unsigned int pages[2];
-	/* use count */
-	unsigned long count;
-	/* a pointer to the context location inside the thread_struct
-	 * or the per_cpu context array */
-	struct ds_context **this;
-	/* a pointer to the task owning this context, or NULL, if the
-	 * context is owned by a cpu */
-	struct task_struct *task;
-};
-
-/* called by exit_thread() to free leftover contexts */
-extern void ds_free(struct ds_context *context);
-
-#else /* CONFIG_X86_DS */
-
-#define ds_init_intel(config) do {} while (0)
-
-#endif /* CONFIG_X86_DS */
-#endif /* ASM_X86__DS_H */
diff --git a/include/asm-x86/dwarf2.h b/include/asm-x86/dwarf2.h
deleted file mode 100644
index 21d1bc32ad7c..000000000000
--- a/include/asm-x86/dwarf2.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef ASM_X86__DWARF2_H
-#define ASM_X86__DWARF2_H
-
-#ifndef __ASSEMBLY__
-#warning "asm/dwarf2.h should be only included in pure assembly files"
-#endif
-
-/*
-   Macros for dwarf2 CFI unwind table entries.
-   See "as.info" for details on these pseudo ops. Unfortunately
-   they are only supported in very new binutils, so define them
-   away for older version.
- */
-
-#ifdef CONFIG_AS_CFI
-
-#define CFI_STARTPROC .cfi_startproc
-#define CFI_ENDPROC .cfi_endproc
-#define CFI_DEF_CFA .cfi_def_cfa
-#define CFI_DEF_CFA_REGISTER .cfi_def_cfa_register
-#define CFI_DEF_CFA_OFFSET .cfi_def_cfa_offset
-#define CFI_ADJUST_CFA_OFFSET .cfi_adjust_cfa_offset
-#define CFI_OFFSET .cfi_offset
-#define CFI_REL_OFFSET .cfi_rel_offset
-#define CFI_REGISTER .cfi_register
-#define CFI_RESTORE .cfi_restore
-#define CFI_REMEMBER_STATE .cfi_remember_state
-#define CFI_RESTORE_STATE .cfi_restore_state
-#define CFI_UNDEFINED .cfi_undefined
-
-#ifdef CONFIG_AS_CFI_SIGNAL_FRAME
-#define CFI_SIGNAL_FRAME .cfi_signal_frame
-#else
-#define CFI_SIGNAL_FRAME
-#endif
-
-#else
-
-/* Due to the structure of pre-exisiting code, don't use assembler line
-   comment character # to ignore the arguments. Instead, use a dummy macro. */
-.macro cfi_ignore a=0, b=0, c=0, d=0
-.endm
-
-#define CFI_STARTPROC	cfi_ignore
-#define CFI_ENDPROC	cfi_ignore
-#define CFI_DEF_CFA	cfi_ignore
-#define CFI_DEF_CFA_REGISTER	cfi_ignore
-#define CFI_DEF_CFA_OFFSET	cfi_ignore
-#define CFI_ADJUST_CFA_OFFSET	cfi_ignore
-#define CFI_OFFSET	cfi_ignore
-#define CFI_REL_OFFSET	cfi_ignore
-#define CFI_REGISTER	cfi_ignore
-#define CFI_RESTORE	cfi_ignore
-#define CFI_REMEMBER_STATE cfi_ignore
-#define CFI_RESTORE_STATE cfi_ignore
-#define CFI_UNDEFINED cfi_ignore
-#define CFI_SIGNAL_FRAME cfi_ignore
-
-#endif
-
-#endif /* ASM_X86__DWARF2_H */
diff --git a/include/asm-x86/e820.h b/include/asm-x86/e820.h
deleted file mode 100644
index 5abbdec06bd2..000000000000
--- a/include/asm-x86/e820.h
+++ /dev/null
@@ -1,146 +0,0 @@
-#ifndef ASM_X86__E820_H
-#define ASM_X86__E820_H
-#define E820MAP	0x2d0		/* our map */
-#define E820MAX	128		/* number of entries in E820MAP */
-
-/*
- * Legacy E820 BIOS limits us to 128 (E820MAX) nodes due to the
- * constrained space in the zeropage.  If we have more nodes than
- * that, and if we've booted off EFI firmware, then the EFI tables
- * passed us from the EFI firmware can list more nodes.  Size our
- * internal memory map tables to have room for these additional
- * nodes, based on up to three entries per node for which the
- * kernel was built: MAX_NUMNODES == (1 << CONFIG_NODES_SHIFT),
- * plus E820MAX, allowing space for the possible duplicate E820
- * entries that might need room in the same arrays, prior to the
- * call to sanitize_e820_map() to remove duplicates.  The allowance
- * of three memory map entries per node is "enough" entries for
- * the initial hardware platform motivating this mechanism to make
- * use of additional EFI map entries.  Future platforms may want
- * to allow more than three entries per node or otherwise refine
- * this size.
- */
-
-/*
- * Odd: 'make headers_check' complains about numa.h if I try
- * to collapse the next two #ifdef lines to a single line:
- *	#if defined(__KERNEL__) && defined(CONFIG_EFI)
- */
-#ifdef __KERNEL__
-#ifdef CONFIG_EFI
-#include <linux/numa.h>
-#define E820_X_MAX (E820MAX + 3 * MAX_NUMNODES)
-#else	/* ! CONFIG_EFI */
-#define E820_X_MAX E820MAX
-#endif
-#else	/* ! __KERNEL__ */
-#define E820_X_MAX E820MAX
-#endif
-
-#define E820NR	0x1e8		/* # entries in E820MAP */
-
-#define E820_RAM	1
-#define E820_RESERVED	2
-#define E820_ACPI	3
-#define E820_NVS	4
-#define E820_UNUSABLE	5
-
-/* reserved RAM used by kernel itself */
-#define E820_RESERVED_KERN        128
-
-#ifndef __ASSEMBLY__
-struct e820entry {
-	__u64 addr;	/* start of memory segment */
-	__u64 size;	/* size of memory segment */
-	__u32 type;	/* type of memory segment */
-} __attribute__((packed));
-
-struct e820map {
-	__u32 nr_map;
-	struct e820entry map[E820_X_MAX];
-};
-
-#ifdef __KERNEL__
-/* see comment in arch/x86/kernel/e820.c */
-extern struct e820map e820;
-extern struct e820map e820_saved;
-
-extern unsigned long pci_mem_start;
-extern int e820_any_mapped(u64 start, u64 end, unsigned type);
-extern int e820_all_mapped(u64 start, u64 end, unsigned type);
-extern void e820_add_region(u64 start, u64 size, int type);
-extern void e820_print_map(char *who);
-extern int
-sanitize_e820_map(struct e820entry *biosmap, int max_nr_map, int *pnr_map);
-extern u64 e820_update_range(u64 start, u64 size, unsigned old_type,
-			       unsigned new_type);
-extern u64 e820_remove_range(u64 start, u64 size, unsigned old_type,
-			     int checktype);
-extern void update_e820(void);
-extern void e820_setup_gap(void);
-extern int e820_search_gap(unsigned long *gapstart, unsigned long *gapsize,
-			unsigned long start_addr, unsigned long long end_addr);
-struct setup_data;
-extern void parse_e820_ext(struct setup_data *data, unsigned long pa_data);
-
-#if defined(CONFIG_X86_64) || \
-	(defined(CONFIG_X86_32) && defined(CONFIG_HIBERNATION))
-extern void e820_mark_nosave_regions(unsigned long limit_pfn);
-#else
-static inline void e820_mark_nosave_regions(unsigned long limit_pfn)
-{
-}
-#endif
-
-#ifdef CONFIG_MEMTEST
-extern void early_memtest(unsigned long start, unsigned long end);
-#else
-static inline void early_memtest(unsigned long start, unsigned long end)
-{
-}
-#endif
-
-extern unsigned long end_user_pfn;
-
-extern u64 find_e820_area(u64 start, u64 end, u64 size, u64 align);
-extern u64 find_e820_area_size(u64 start, u64 *sizep, u64 align);
-extern void reserve_early(u64 start, u64 end, char *name);
-extern void reserve_early_overlap_ok(u64 start, u64 end, char *name);
-extern void free_early(u64 start, u64 end);
-extern void early_res_to_bootmem(u64 start, u64 end);
-extern u64 early_reserve_e820(u64 startt, u64 sizet, u64 align);
-
-extern unsigned long e820_end_of_ram_pfn(void);
-extern unsigned long e820_end_of_low_ram_pfn(void);
-extern int e820_find_active_region(const struct e820entry *ei,
-				  unsigned long start_pfn,
-				  unsigned long last_pfn,
-				  unsigned long *ei_startpfn,
-				  unsigned long *ei_endpfn);
-extern void e820_register_active_regions(int nid, unsigned long start_pfn,
-					 unsigned long end_pfn);
-extern u64 e820_hole_size(u64 start, u64 end);
-extern void finish_e820_parsing(void);
-extern void e820_reserve_resources(void);
-extern void e820_reserve_resources_late(void);
-extern void setup_memory_map(void);
-extern char *default_machine_specific_memory_setup(void);
-extern char *machine_specific_memory_setup(void);
-extern char *memory_setup(void);
-#endif /* __KERNEL__ */
-#endif /* __ASSEMBLY__ */
-
-#define ISA_START_ADDRESS	0xa0000
-#define ISA_END_ADDRESS		0x100000
-#define is_ISA_range(s, e) ((s) >= ISA_START_ADDRESS && (e) < ISA_END_ADDRESS)
-
-#define BIOS_BEGIN		0x000a0000
-#define BIOS_END		0x00100000
-
-#ifdef __KERNEL__
-#include <linux/ioport.h>
-
-#define HIGH_MEMORY	(1024*1024)
-#endif /* __KERNEL__ */
-
-#endif /* ASM_X86__E820_H */
diff --git a/include/asm-x86/edac.h b/include/asm-x86/edac.h
deleted file mode 100644
index 9493c5b27bbd..000000000000
--- a/include/asm-x86/edac.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef ASM_X86__EDAC_H
-#define ASM_X86__EDAC_H
-
-/* ECC atomic, DMA, SMP and interrupt safe scrub function */
-
-static inline void atomic_scrub(void *va, u32 size)
-{
-	u32 i, *virt_addr = va;
-
-	/*
-	 * Very carefully read and write to memory atomically so we
-	 * are interrupt, DMA and SMP safe.
-	 */
-	for (i = 0; i < size / 4; i++, virt_addr++)
-		asm volatile("lock; addl $0, %0"::"m" (*virt_addr));
-}
-
-#endif /* ASM_X86__EDAC_H */
diff --git a/include/asm-x86/efi.h b/include/asm-x86/efi.h
deleted file mode 100644
index ed2de22e8705..000000000000
--- a/include/asm-x86/efi.h
+++ /dev/null
@@ -1,97 +0,0 @@
-#ifndef ASM_X86__EFI_H
-#define ASM_X86__EFI_H
-
-#ifdef CONFIG_X86_32
-
-extern unsigned long asmlinkage efi_call_phys(void *, ...);
-
-#define efi_call_phys0(f)		efi_call_phys(f)
-#define efi_call_phys1(f, a1)		efi_call_phys(f, a1)
-#define efi_call_phys2(f, a1, a2)	efi_call_phys(f, a1, a2)
-#define efi_call_phys3(f, a1, a2, a3)	efi_call_phys(f, a1, a2, a3)
-#define efi_call_phys4(f, a1, a2, a3, a4)	\
-	efi_call_phys(f, a1, a2, a3, a4)
-#define efi_call_phys5(f, a1, a2, a3, a4, a5)	\
-	efi_call_phys(f, a1, a2, a3, a4, a5)
-#define efi_call_phys6(f, a1, a2, a3, a4, a5, a6)	\
-	efi_call_phys(f, a1, a2, a3, a4, a5, a6)
-/*
- * Wrap all the virtual calls in a way that forces the parameters on the stack.
- */
-
-#define efi_call_virt(f, args...) \
-	((efi_##f##_t __attribute__((regparm(0)))*)efi.systab->runtime->f)(args)
-
-#define efi_call_virt0(f)		efi_call_virt(f)
-#define efi_call_virt1(f, a1)		efi_call_virt(f, a1)
-#define efi_call_virt2(f, a1, a2)	efi_call_virt(f, a1, a2)
-#define efi_call_virt3(f, a1, a2, a3)	efi_call_virt(f, a1, a2, a3)
-#define efi_call_virt4(f, a1, a2, a3, a4)	\
-	efi_call_virt(f, a1, a2, a3, a4)
-#define efi_call_virt5(f, a1, a2, a3, a4, a5)	\
-	efi_call_virt(f, a1, a2, a3, a4, a5)
-#define efi_call_virt6(f, a1, a2, a3, a4, a5, a6)	\
-	efi_call_virt(f, a1, a2, a3, a4, a5, a6)
-
-#define efi_ioremap(addr, size)			ioremap_cache(addr, size)
-
-#else /* !CONFIG_X86_32 */
-
-#define MAX_EFI_IO_PAGES	100
-
-extern u64 efi_call0(void *fp);
-extern u64 efi_call1(void *fp, u64 arg1);
-extern u64 efi_call2(void *fp, u64 arg1, u64 arg2);
-extern u64 efi_call3(void *fp, u64 arg1, u64 arg2, u64 arg3);
-extern u64 efi_call4(void *fp, u64 arg1, u64 arg2, u64 arg3, u64 arg4);
-extern u64 efi_call5(void *fp, u64 arg1, u64 arg2, u64 arg3,
-		     u64 arg4, u64 arg5);
-extern u64 efi_call6(void *fp, u64 arg1, u64 arg2, u64 arg3,
-		     u64 arg4, u64 arg5, u64 arg6);
-
-#define efi_call_phys0(f)			\
-	efi_call0((void *)(f))
-#define efi_call_phys1(f, a1)			\
-	efi_call1((void *)(f), (u64)(a1))
-#define efi_call_phys2(f, a1, a2)			\
-	efi_call2((void *)(f), (u64)(a1), (u64)(a2))
-#define efi_call_phys3(f, a1, a2, a3)				\
-	efi_call3((void *)(f), (u64)(a1), (u64)(a2), (u64)(a3))
-#define efi_call_phys4(f, a1, a2, a3, a4)				\
-	efi_call4((void *)(f), (u64)(a1), (u64)(a2), (u64)(a3),		\
-		  (u64)(a4))
-#define efi_call_phys5(f, a1, a2, a3, a4, a5)				\
-	efi_call5((void *)(f), (u64)(a1), (u64)(a2), (u64)(a3),		\
-		  (u64)(a4), (u64)(a5))
-#define efi_call_phys6(f, a1, a2, a3, a4, a5, a6)			\
-	efi_call6((void *)(f), (u64)(a1), (u64)(a2), (u64)(a3),		\
-		  (u64)(a4), (u64)(a5), (u64)(a6))
-
-#define efi_call_virt0(f)				\
-	efi_call0((void *)(efi.systab->runtime->f))
-#define efi_call_virt1(f, a1)					\
-	efi_call1((void *)(efi.systab->runtime->f), (u64)(a1))
-#define efi_call_virt2(f, a1, a2)					\
-	efi_call2((void *)(efi.systab->runtime->f), (u64)(a1), (u64)(a2))
-#define efi_call_virt3(f, a1, a2, a3)					\
-	efi_call3((void *)(efi.systab->runtime->f), (u64)(a1), (u64)(a2), \
-		  (u64)(a3))
-#define efi_call_virt4(f, a1, a2, a3, a4)				\
-	efi_call4((void *)(efi.systab->runtime->f), (u64)(a1), (u64)(a2), \
-		  (u64)(a3), (u64)(a4))
-#define efi_call_virt5(f, a1, a2, a3, a4, a5)				\
-	efi_call5((void *)(efi.systab->runtime->f), (u64)(a1), (u64)(a2), \
-		  (u64)(a3), (u64)(a4), (u64)(a5))
-#define efi_call_virt6(f, a1, a2, a3, a4, a5, a6)			\
-	efi_call6((void *)(efi.systab->runtime->f), (u64)(a1), (u64)(a2), \
-		  (u64)(a3), (u64)(a4), (u64)(a5), (u64)(a6))
-
-extern void __iomem *efi_ioremap(unsigned long addr, unsigned long size);
-
-#endif /* CONFIG_X86_32 */
-
-extern void efi_reserve_early(void);
-extern void efi_call_phys_prelog(void);
-extern void efi_call_phys_epilog(void);
-
-#endif /* ASM_X86__EFI_H */
diff --git a/include/asm-x86/elf.h b/include/asm-x86/elf.h
deleted file mode 100644
index 5c4745bec906..000000000000
--- a/include/asm-x86/elf.h
+++ /dev/null
@@ -1,336 +0,0 @@
-#ifndef ASM_X86__ELF_H
-#define ASM_X86__ELF_H
-
-/*
- * ELF register definitions..
- */
-
-#include <asm/ptrace.h>
-#include <asm/user.h>
-#include <asm/auxvec.h>
-
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct user_i387_struct elf_fpregset_t;
-
-#ifdef __i386__
-
-typedef struct user_fxsr_struct elf_fpxregset_t;
-
-#define R_386_NONE	0
-#define R_386_32	1
-#define R_386_PC32	2
-#define R_386_GOT32	3
-#define R_386_PLT32	4
-#define R_386_COPY	5
-#define R_386_GLOB_DAT	6
-#define R_386_JMP_SLOT	7
-#define R_386_RELATIVE	8
-#define R_386_GOTOFF	9
-#define R_386_GOTPC	10
-#define R_386_NUM	11
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS	ELFCLASS32
-#define ELF_DATA	ELFDATA2LSB
-#define ELF_ARCH	EM_386
-
-#else
-
-/* x86-64 relocation types */
-#define R_X86_64_NONE		0	/* No reloc */
-#define R_X86_64_64		1	/* Direct 64 bit  */
-#define R_X86_64_PC32		2	/* PC relative 32 bit signed */
-#define R_X86_64_GOT32		3	/* 32 bit GOT entry */
-#define R_X86_64_PLT32		4	/* 32 bit PLT address */
-#define R_X86_64_COPY		5	/* Copy symbol at runtime */
-#define R_X86_64_GLOB_DAT	6	/* Create GOT entry */
-#define R_X86_64_JUMP_SLOT	7	/* Create PLT entry */
-#define R_X86_64_RELATIVE	8	/* Adjust by program base */
-#define R_X86_64_GOTPCREL	9	/* 32 bit signed pc relative
-					   offset to GOT */
-#define R_X86_64_32		10	/* Direct 32 bit zero extended */
-#define R_X86_64_32S		11	/* Direct 32 bit sign extended */
-#define R_X86_64_16		12	/* Direct 16 bit zero extended */
-#define R_X86_64_PC16		13	/* 16 bit sign extended pc relative */
-#define R_X86_64_8		14	/* Direct 8 bit sign extended  */
-#define R_X86_64_PC8		15	/* 8 bit sign extended pc relative */
-
-#define R_X86_64_NUM		16
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS	ELFCLASS64
-#define ELF_DATA	ELFDATA2LSB
-#define ELF_ARCH	EM_X86_64
-
-#endif
-
-#include <asm/vdso.h>
-
-extern unsigned int vdso_enabled;
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch_ia32(x) \
-	(((x)->e_machine == EM_386) || ((x)->e_machine == EM_486))
-
-#include <asm/processor.h>
-#include <asm/system.h>
-
-#ifdef CONFIG_X86_32
-#include <asm/desc.h>
-
-#define elf_check_arch(x)	elf_check_arch_ia32(x)
-
-/* SVR4/i386 ABI (pages 3-31, 3-32) says that when the program starts %edx
-   contains a pointer to a function which might be registered using `atexit'.
-   This provides a mean for the dynamic linker to call DT_FINI functions for
-   shared libraries that have been loaded before the code runs.
-
-   A value of 0 tells we have no such handler.
-
-   We might as well make sure everything else is cleared too (except for %esp),
-   just to make things more deterministic.
- */
-#define ELF_PLAT_INIT(_r, load_addr)		\
-	do {					\
-	_r->bx = 0; _r->cx = 0; _r->dx = 0;	\
-	_r->si = 0; _r->di = 0; _r->bp = 0;	\
-	_r->ax = 0;				\
-} while (0)
-
-/*
- * regs is struct pt_regs, pr_reg is elf_gregset_t (which is
- * now struct_user_regs, they are different)
- */
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs)	\
-do {						\
-	pr_reg[0] = regs->bx;			\
-	pr_reg[1] = regs->cx;			\
-	pr_reg[2] = regs->dx;			\
-	pr_reg[3] = regs->si;			\
-	pr_reg[4] = regs->di;			\
-	pr_reg[5] = regs->bp;			\
-	pr_reg[6] = regs->ax;			\
-	pr_reg[7] = regs->ds & 0xffff;		\
-	pr_reg[8] = regs->es & 0xffff;		\
-	pr_reg[9] = regs->fs & 0xffff;		\
-	savesegment(gs, pr_reg[10]);		\
-	pr_reg[11] = regs->orig_ax;		\
-	pr_reg[12] = regs->ip;			\
-	pr_reg[13] = regs->cs & 0xffff;		\
-	pr_reg[14] = regs->flags;		\
-	pr_reg[15] = regs->sp;			\
-	pr_reg[16] = regs->ss & 0xffff;		\
-} while (0);
-
-#define ELF_PLATFORM	(utsname()->machine)
-#define set_personality_64bit()	do { } while (0)
-
-#else /* CONFIG_X86_32 */
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x)			\
-	((x)->e_machine == EM_X86_64)
-
-#define compat_elf_check_arch(x)	elf_check_arch_ia32(x)
-
-static inline void start_ia32_thread(struct pt_regs *regs, u32 ip, u32 sp)
-{
-	loadsegment(fs, 0);
-	loadsegment(ds, __USER32_DS);
-	loadsegment(es, __USER32_DS);
-	load_gs_index(0);
-	regs->ip = ip;
-	regs->sp = sp;
-	regs->flags = X86_EFLAGS_IF;
-	regs->cs = __USER32_CS;
-	regs->ss = __USER32_DS;
-}
-
-static inline void elf_common_init(struct thread_struct *t,
-				   struct pt_regs *regs, const u16 ds)
-{
-	regs->ax = regs->bx = regs->cx = regs->dx = 0;
-	regs->si = regs->di = regs->bp = 0;
-	regs->r8 = regs->r9 = regs->r10 = regs->r11 = 0;
-	regs->r12 = regs->r13 = regs->r14 = regs->r15 = 0;
-	t->fs = t->gs = 0;
-	t->fsindex = t->gsindex = 0;
-	t->ds = t->es = ds;
-}
-
-#define ELF_PLAT_INIT(_r, load_addr)			\
-do {							\
-	elf_common_init(&current->thread, _r, 0);	\
-	clear_thread_flag(TIF_IA32);			\
-} while (0)
-
-#define	COMPAT_ELF_PLAT_INIT(regs, load_addr)		\
-	elf_common_init(&current->thread, regs, __USER_DS)
-
-#define	compat_start_thread(regs, ip, sp)		\
-do {							\
-	start_ia32_thread(regs, ip, sp);		\
-	set_fs(USER_DS);				\
-} while (0)
-
-#define COMPAT_SET_PERSONALITY(ex, ibcs2)		\
-do {							\
-	if (test_thread_flag(TIF_IA32))			\
-		clear_thread_flag(TIF_ABI_PENDING);	\
-	else						\
-		set_thread_flag(TIF_ABI_PENDING);	\
-	current->personality |= force_personality32;	\
-} while (0)
-
-#define COMPAT_ELF_PLATFORM			("i686")
-
-/*
- * regs is struct pt_regs, pr_reg is elf_gregset_t (which is
- * now struct_user_regs, they are different). Assumes current is the process
- * getting dumped.
- */
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs)			\
-do {								\
-	unsigned v;						\
-	(pr_reg)[0] = (regs)->r15;				\
-	(pr_reg)[1] = (regs)->r14;				\
-	(pr_reg)[2] = (regs)->r13;				\
-	(pr_reg)[3] = (regs)->r12;				\
-	(pr_reg)[4] = (regs)->bp;				\
-	(pr_reg)[5] = (regs)->bx;				\
-	(pr_reg)[6] = (regs)->r11;				\
-	(pr_reg)[7] = (regs)->r10;				\
-	(pr_reg)[8] = (regs)->r9;				\
-	(pr_reg)[9] = (regs)->r8;				\
-	(pr_reg)[10] = (regs)->ax;				\
-	(pr_reg)[11] = (regs)->cx;				\
-	(pr_reg)[12] = (regs)->dx;				\
-	(pr_reg)[13] = (regs)->si;				\
-	(pr_reg)[14] = (regs)->di;				\
-	(pr_reg)[15] = (regs)->orig_ax;				\
-	(pr_reg)[16] = (regs)->ip;				\
-	(pr_reg)[17] = (regs)->cs;				\
-	(pr_reg)[18] = (regs)->flags;				\
-	(pr_reg)[19] = (regs)->sp;				\
-	(pr_reg)[20] = (regs)->ss;				\
-	(pr_reg)[21] = current->thread.fs;			\
-	(pr_reg)[22] = current->thread.gs;			\
-	asm("movl %%ds,%0" : "=r" (v)); (pr_reg)[23] = v;	\
-	asm("movl %%es,%0" : "=r" (v)); (pr_reg)[24] = v;	\
-	asm("movl %%fs,%0" : "=r" (v)); (pr_reg)[25] = v;	\
-	asm("movl %%gs,%0" : "=r" (v)); (pr_reg)[26] = v;	\
-} while (0);
-
-/* I'm not sure if we can use '-' here */
-#define ELF_PLATFORM       ("x86_64")
-extern void set_personality_64bit(void);
-extern unsigned int sysctl_vsyscall32;
-extern int force_personality32;
-
-#endif /* !CONFIG_X86_32 */
-
-#define CORE_DUMP_USE_REGSET
-#define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE	4096
-
-/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
-   use of this is to invoke "./ld.so someprog" to test out a new version of
-   the loader.  We need to make sure that it is out of the way of the program
-   that it will "exec", and that there is sufficient room for the brk.  */
-
-#define ELF_ET_DYN_BASE		(TASK_SIZE / 3 * 2)
-
-/* This yields a mask that user programs can use to figure out what
-   instruction set this CPU supports.  This could be done in user space,
-   but it's not easy, and we've already done it here.  */
-
-#define ELF_HWCAP		(boot_cpu_data.x86_capability[0])
-
-/* This yields a string that ld.so will use to load implementation
-   specific libraries for optimization.  This is more specific in
-   intent than poking at uname or /proc/cpuinfo.
-
-   For the moment, we have only optimizations for the Intel generations,
-   but that could change... */
-
-#define SET_PERSONALITY(ex, ibcs2) set_personality_64bit()
-
-/*
- * An executable for which elf_read_implies_exec() returns TRUE will
- * have the READ_IMPLIES_EXEC personality flag set automatically.
- */
-#define elf_read_implies_exec(ex, executable_stack)	\
-	(executable_stack != EXSTACK_DISABLE_X)
-
-struct task_struct;
-
-#define	ARCH_DLINFO_IA32(vdso_enabled)					\
-do {									\
-	if (vdso_enabled) {						\
-		NEW_AUX_ENT(AT_SYSINFO,	VDSO_ENTRY);			\
-		NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_CURRENT_BASE);	\
-	}								\
-} while (0)
-
-#ifdef CONFIG_X86_32
-
-#define VDSO_HIGH_BASE		(__fix_to_virt(FIX_VDSO))
-
-#define ARCH_DLINFO		ARCH_DLINFO_IA32(vdso_enabled)
-
-/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
-
-#else /* CONFIG_X86_32 */
-
-#define VDSO_HIGH_BASE		0xffffe000U /* CONFIG_COMPAT_VDSO address */
-
-/* 1GB for 64bit, 8MB for 32bit */
-#define STACK_RND_MASK (test_thread_flag(TIF_IA32) ? 0x7ff : 0x3fffff)
-
-#define ARCH_DLINFO							\
-do {									\
-	if (vdso_enabled)						\
-		NEW_AUX_ENT(AT_SYSINFO_EHDR,				\
-			    (unsigned long)current->mm->context.vdso);	\
-} while (0)
-
-#define AT_SYSINFO		32
-
-#define COMPAT_ARCH_DLINFO	ARCH_DLINFO_IA32(sysctl_vsyscall32)
-
-#define COMPAT_ELF_ET_DYN_BASE	(TASK_UNMAPPED_BASE + 0x1000000)
-
-#endif /* !CONFIG_X86_32 */
-
-#define VDSO_CURRENT_BASE	((unsigned long)current->mm->context.vdso)
-
-#define VDSO_ENTRY							\
-	((unsigned long)VDSO32_SYMBOL(VDSO_CURRENT_BASE, vsyscall))
-
-struct linux_binprm;
-
-#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1
-extern int arch_setup_additional_pages(struct linux_binprm *bprm,
-				       int executable_stack);
-
-extern int syscall32_setup_pages(struct linux_binprm *, int exstack);
-#define compat_arch_setup_additional_pages	syscall32_setup_pages
-
-extern unsigned long arch_randomize_brk(struct mm_struct *mm);
-#define arch_randomize_brk arch_randomize_brk
-
-#endif /* ASM_X86__ELF_H */
diff --git a/include/asm-x86/emergency-restart.h b/include/asm-x86/emergency-restart.h
deleted file mode 100644
index 190d0d8b71e3..000000000000
--- a/include/asm-x86/emergency-restart.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef ASM_X86__EMERGENCY_RESTART_H
-#define ASM_X86__EMERGENCY_RESTART_H
-
-enum reboot_type {
-	BOOT_TRIPLE = 't',
-	BOOT_KBD = 'k',
-#ifdef CONFIG_X86_32
-	BOOT_BIOS = 'b',
-#endif
-	BOOT_ACPI = 'a',
-	BOOT_EFI = 'e'
-};
-
-extern enum reboot_type reboot_type;
-
-extern void machine_emergency_restart(void);
-
-#endif /* ASM_X86__EMERGENCY_RESTART_H */
diff --git a/include/asm-x86/errno.h b/include/asm-x86/errno.h
deleted file mode 100644
index 4c82b503d92f..000000000000
--- a/include/asm-x86/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/include/asm-x86/es7000/apic.h b/include/asm-x86/es7000/apic.h
deleted file mode 100644
index bd2c44d1f7ac..000000000000
--- a/include/asm-x86/es7000/apic.h
+++ /dev/null
@@ -1,194 +0,0 @@
-#ifndef __ASM_ES7000_APIC_H
-#define __ASM_ES7000_APIC_H
-
-#define xapic_phys_to_log_apicid(cpu) per_cpu(x86_bios_cpu_apicid, cpu)
-#define esr_disable (1)
-
-static inline int apic_id_registered(void)
-{
-	        return (1);
-}
-
-static inline cpumask_t target_cpus(void)
-{
-#if defined CONFIG_ES7000_CLUSTERED_APIC
-	return CPU_MASK_ALL;
-#else
-	return cpumask_of_cpu(smp_processor_id());
-#endif
-}
-#define TARGET_CPUS	(target_cpus())
-
-#if defined CONFIG_ES7000_CLUSTERED_APIC
-#define APIC_DFR_VALUE		(APIC_DFR_CLUSTER)
-#define INT_DELIVERY_MODE	(dest_LowestPrio)
-#define INT_DEST_MODE		(1)    /* logical delivery broadcast to all procs */
-#define NO_BALANCE_IRQ		(1)
-#undef  WAKE_SECONDARY_VIA_INIT
-#define WAKE_SECONDARY_VIA_MIP
-#else
-#define APIC_DFR_VALUE		(APIC_DFR_FLAT)
-#define INT_DELIVERY_MODE	(dest_Fixed)
-#define INT_DEST_MODE		(0)    /* phys delivery to target procs */
-#define NO_BALANCE_IRQ		(0)
-#undef  APIC_DEST_LOGICAL
-#define APIC_DEST_LOGICAL	0x0
-#define WAKE_SECONDARY_VIA_INIT
-#endif
-
-static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
-{
-	return 0;
-}
-static inline unsigned long check_apicid_present(int bit)
-{
-	return physid_isset(bit, phys_cpu_present_map);
-}
-
-#define apicid_cluster(apicid) (apicid & 0xF0)
-
-static inline unsigned long calculate_ldr(int cpu)
-{
-	unsigned long id;
-	id = xapic_phys_to_log_apicid(cpu);
-	return (SET_APIC_LOGICAL_ID(id));
-}
-
-/*
- * Set up the logical destination ID.
- *
- * Intel recommends to set DFR, LdR and TPR before enabling
- * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
- * document number 292116).  So here it goes...
- */
-static inline void init_apic_ldr(void)
-{
-	unsigned long val;
-	int cpu = smp_processor_id();
-
-	apic_write(APIC_DFR, APIC_DFR_VALUE);
-	val = calculate_ldr(cpu);
-	apic_write(APIC_LDR, val);
-}
-
-#ifndef CONFIG_X86_GENERICARCH
-extern void enable_apic_mode(void);
-#endif
-
-extern int apic_version [MAX_APICS];
-static inline void setup_apic_routing(void)
-{
-	int apic = per_cpu(x86_bios_cpu_apicid, smp_processor_id());
-	printk("Enabling APIC mode:  %s.  Using %d I/O APICs, target cpus %lx\n",
-		(apic_version[apic] == 0x14) ?
-		"Physical Cluster" : "Logical Cluster", nr_ioapics, cpus_addr(TARGET_CPUS)[0]);
-}
-
-static inline int multi_timer_check(int apic, int irq)
-{
-	return 0;
-}
-
-static inline int apicid_to_node(int logical_apicid)
-{
-	return 0;
-}
-
-
-static inline int cpu_present_to_apicid(int mps_cpu)
-{
-	if (!mps_cpu)
-		return boot_cpu_physical_apicid;
-	else if (mps_cpu < NR_CPUS)
-		return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);
-	else
-		return BAD_APICID;
-}
-
-static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
-{
-	static int id = 0;
-	physid_mask_t mask;
-	mask = physid_mask_of_physid(id);
-	++id;
-	return mask;
-}
-
-extern u8 cpu_2_logical_apicid[];
-/* Mapping from cpu number to logical apicid */
-static inline int cpu_to_logical_apicid(int cpu)
-{
-#ifdef CONFIG_SMP
-       if (cpu >= NR_CPUS)
-	       return BAD_APICID;
-       return (int)cpu_2_logical_apicid[cpu];
-#else
-	return logical_smp_processor_id();
-#endif
-}
-
-static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
-{
-	/* For clustered we don't have a good way to do this yet - hack */
-	return physids_promote(0xff);
-}
-
-
-static inline void setup_portio_remap(void)
-{
-}
-
-extern unsigned int boot_cpu_physical_apicid;
-static inline int check_phys_apicid_present(int cpu_physical_apicid)
-{
-	boot_cpu_physical_apicid = read_apic_id();
-	return (1);
-}
-
-static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
-{
-	int num_bits_set;
-	int cpus_found = 0;
-	int cpu;
-	int apicid;
-
-	num_bits_set = cpus_weight(cpumask);
-	/* Return id to all */
-	if (num_bits_set == NR_CPUS)
-#if defined CONFIG_ES7000_CLUSTERED_APIC
-		return 0xFF;
-#else
-		return cpu_to_logical_apicid(0);
-#endif
-	/*
-	 * The cpus in the mask must all be on the apic cluster.  If are not
-	 * on the same apicid cluster return default value of TARGET_CPUS.
-	 */
-	cpu = first_cpu(cpumask);
-	apicid = cpu_to_logical_apicid(cpu);
-	while (cpus_found < num_bits_set) {
-		if (cpu_isset(cpu, cpumask)) {
-			int new_apicid = cpu_to_logical_apicid(cpu);
-			if (apicid_cluster(apicid) !=
-					apicid_cluster(new_apicid)){
-				printk ("%s: Not a valid mask!\n",__FUNCTION__);
-#if defined CONFIG_ES7000_CLUSTERED_APIC
-				return 0xFF;
-#else
-				return cpu_to_logical_apicid(0);
-#endif
-			}
-			apicid = new_apicid;
-			cpus_found++;
-		}
-		cpu++;
-	}
-	return apicid;
-}
-
-static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
-{
-	return cpuid_apic >> index_msb;
-}
-
-#endif /* __ASM_ES7000_APIC_H */
diff --git a/include/asm-x86/es7000/apicdef.h b/include/asm-x86/es7000/apicdef.h
deleted file mode 100644
index 8b234a3cb851..000000000000
--- a/include/asm-x86/es7000/apicdef.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ASM_ES7000_APICDEF_H
-#define __ASM_ES7000_APICDEF_H
-
-#define		APIC_ID_MASK		(0xFF<<24)
-
-static inline unsigned get_apic_id(unsigned long x)
-{
-	return (((x)>>24)&0xFF);
-}
-
-#define		GET_APIC_ID(x)	get_apic_id(x)
-
-#endif
diff --git a/include/asm-x86/es7000/ipi.h b/include/asm-x86/es7000/ipi.h
deleted file mode 100644
index 632a955fcc0a..000000000000
--- a/include/asm-x86/es7000/ipi.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef __ASM_ES7000_IPI_H
-#define __ASM_ES7000_IPI_H
-
-void send_IPI_mask_sequence(cpumask_t mask, int vector);
-
-static inline void send_IPI_mask(cpumask_t mask, int vector)
-{
-	send_IPI_mask_sequence(mask, vector);
-}
-
-static inline void send_IPI_allbutself(int vector)
-{
-	cpumask_t mask = cpu_online_map;
-	cpu_clear(smp_processor_id(), mask);
-	if (!cpus_empty(mask))
-		send_IPI_mask(mask, vector);
-}
-
-static inline void send_IPI_all(int vector)
-{
-	send_IPI_mask(cpu_online_map, vector);
-}
-
-#endif /* __ASM_ES7000_IPI_H */
diff --git a/include/asm-x86/es7000/mpparse.h b/include/asm-x86/es7000/mpparse.h
deleted file mode 100644
index ed5a3caae141..000000000000
--- a/include/asm-x86/es7000/mpparse.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef __ASM_ES7000_MPPARSE_H
-#define __ASM_ES7000_MPPARSE_H
-
-#include <linux/acpi.h>
-
-extern int parse_unisys_oem (char *oemptr);
-extern int find_unisys_acpi_oem_table(unsigned long *oem_addr);
-extern void unmap_unisys_acpi_oem_table(unsigned long oem_addr);
-extern void setup_unisys(void);
-
-#ifndef CONFIG_X86_GENERICARCH
-extern int acpi_madt_oem_check(char *oem_id, char *oem_table_id);
-extern int mps_oem_check(struct mp_config_table *mpc, char *oem,
-				char *productid);
-#endif
-
-#ifdef CONFIG_ACPI
-
-static inline int es7000_check_dsdt(void)
-{
-	struct acpi_table_header header;
-
-	if (ACPI_SUCCESS(acpi_get_table_header(ACPI_SIG_DSDT, 0, &header)) &&
-	    !strncmp(header.oem_id, "UNISYS", 6))
-		return 1;
-	return 0;
-}
-#endif
-
-#endif /* __ASM_MACH_MPPARSE_H */
diff --git a/include/asm-x86/es7000/wakecpu.h b/include/asm-x86/es7000/wakecpu.h
deleted file mode 100644
index 3ffc5a7bf667..000000000000
--- a/include/asm-x86/es7000/wakecpu.h
+++ /dev/null
@@ -1,59 +0,0 @@
-#ifndef __ASM_ES7000_WAKECPU_H
-#define __ASM_ES7000_WAKECPU_H
-
-/*
- * This file copes with machines that wakeup secondary CPUs by the
- * INIT, INIT, STARTUP sequence.
- */
-
-#ifdef CONFIG_ES7000_CLUSTERED_APIC
-#define WAKE_SECONDARY_VIA_MIP
-#else
-#define WAKE_SECONDARY_VIA_INIT
-#endif
-
-#ifdef WAKE_SECONDARY_VIA_MIP
-extern int es7000_start_cpu(int cpu, unsigned long eip);
-static inline int
-wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
-{
-	int boot_error = 0;
-	boot_error = es7000_start_cpu(phys_apicid, start_eip);
-	return boot_error;
-}
-#endif
-
-#define TRAMPOLINE_LOW phys_to_virt(0x467)
-#define TRAMPOLINE_HIGH phys_to_virt(0x469)
-
-#define boot_cpu_apicid boot_cpu_physical_apicid
-
-static inline void wait_for_init_deassert(atomic_t *deassert)
-{
-#ifdef WAKE_SECONDARY_VIA_INIT
-	while (!atomic_read(deassert))
-		cpu_relax();
-#endif
-	return;
-}
-
-/* Nothing to do for most platforms, since cleared by the INIT cycle */
-static inline void smp_callin_clear_local_apic(void)
-{
-}
-
-static inline void store_NMI_vector(unsigned short *high, unsigned short *low)
-{
-}
-
-static inline void restore_NMI_vector(unsigned short *high, unsigned short *low)
-{
-}
-
-#if APIC_DEBUG
- #define inquire_remote_apic(apicid) __inquire_remote_apic(apicid)
-#else
- #define inquire_remote_apic(apicid) {}
-#endif
-
-#endif /* __ASM_MACH_WAKECPU_H */
diff --git a/include/asm-x86/fb.h b/include/asm-x86/fb.h
deleted file mode 100644
index aca38dbd9a64..000000000000
--- a/include/asm-x86/fb.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef ASM_X86__FB_H
-#define ASM_X86__FB_H
-
-#include <linux/fb.h>
-#include <linux/fs.h>
-#include <asm/page.h>
-
-static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
-				unsigned long off)
-{
-	if (boot_cpu_data.x86 > 3)
-		pgprot_val(vma->vm_page_prot) |= _PAGE_PCD;
-}
-
-#ifdef CONFIG_X86_32
-extern int fb_is_primary_device(struct fb_info *info);
-#else
-static inline int fb_is_primary_device(struct fb_info *info) { return 0; }
-#endif
-
-#endif /* ASM_X86__FB_H */
diff --git a/include/asm-x86/fcntl.h b/include/asm-x86/fcntl.h
deleted file mode 100644
index 46ab12db5739..000000000000
--- a/include/asm-x86/fcntl.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/fcntl.h>
diff --git a/include/asm-x86/fixmap.h b/include/asm-x86/fixmap.h
deleted file mode 100644
index 78e33a1bc591..000000000000
--- a/include/asm-x86/fixmap.h
+++ /dev/null
@@ -1,68 +0,0 @@
-#ifndef ASM_X86__FIXMAP_H
-#define ASM_X86__FIXMAP_H
-
-#ifdef CONFIG_X86_32
-# include "fixmap_32.h"
-#else
-# include "fixmap_64.h"
-#endif
-
-extern int fixmaps_set;
-
-void __native_set_fixmap(enum fixed_addresses idx, pte_t pte);
-void native_set_fixmap(enum fixed_addresses idx,
-		       unsigned long phys, pgprot_t flags);
-
-#ifndef CONFIG_PARAVIRT
-static inline void __set_fixmap(enum fixed_addresses idx,
-				unsigned long phys, pgprot_t flags)
-{
-	native_set_fixmap(idx, phys, flags);
-}
-#endif
-
-#define set_fixmap(idx, phys)				\
-	__set_fixmap(idx, phys, PAGE_KERNEL)
-
-/*
- * Some hardware wants to get fixmapped without caching.
- */
-#define set_fixmap_nocache(idx, phys)			\
-	__set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
-
-#define clear_fixmap(idx)			\
-	__set_fixmap(idx, 0, __pgprot(0))
-
-#define __fix_to_virt(x)	(FIXADDR_TOP - ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x)	((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
-
-extern void __this_fixmap_does_not_exist(void);
-
-/*
- * 'index to address' translation. If anyone tries to use the idx
- * directly without translation, we catch the bug with a NULL-deference
- * kernel oops. Illegal ranges of incoming indices are caught too.
- */
-static __always_inline unsigned long fix_to_virt(const unsigned int idx)
-{
-	/*
-	 * this branch gets completely eliminated after inlining,
-	 * except when someone tries to use fixaddr indices in an
-	 * illegal way. (such as mixing up address types or using
-	 * out-of-range indices).
-	 *
-	 * If it doesn't get removed, the linker will complain
-	 * loudly with a reasonably clear error message..
-	 */
-	if (idx >= __end_of_fixed_addresses)
-		__this_fixmap_does_not_exist();
-
-	return __fix_to_virt(idx);
-}
-
-static inline unsigned long virt_to_fix(const unsigned long vaddr)
-{
-	BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
-	return __virt_to_fix(vaddr);
-}
-#endif /* ASM_X86__FIXMAP_H */
diff --git a/include/asm-x86/fixmap_32.h b/include/asm-x86/fixmap_32.h
deleted file mode 100644
index 8844002da0e0..000000000000
--- a/include/asm-x86/fixmap_32.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * fixmap.h: compile-time virtual memory allocation
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998 Ingo Molnar
- *
- * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
- */
-
-#ifndef ASM_X86__FIXMAP_32_H
-#define ASM_X86__FIXMAP_32_H
-
-
-/* used by vmalloc.c, vsyscall.lds.S.
- *
- * Leave one empty page between vmalloc'ed areas and
- * the start of the fixmap.
- */
-extern unsigned long __FIXADDR_TOP;
-#define FIXADDR_USER_START     __fix_to_virt(FIX_VDSO)
-#define FIXADDR_USER_END       __fix_to_virt(FIX_VDSO - 1)
-
-#ifndef __ASSEMBLY__
-#include <linux/kernel.h>
-#include <asm/acpi.h>
-#include <asm/apicdef.h>
-#include <asm/page.h>
-#ifdef CONFIG_HIGHMEM
-#include <linux/threads.h>
-#include <asm/kmap_types.h>
-#endif
-
-/*
- * Here we define all the compile-time 'special' virtual
- * addresses. The point is to have a constant address at
- * compile time, but to set the physical address only
- * in the boot process. We allocate these special addresses
- * from the end of virtual memory (0xfffff000) backwards.
- * Also this lets us do fail-safe vmalloc(), we
- * can guarantee that these special addresses and
- * vmalloc()-ed addresses never overlap.
- *
- * these 'compile-time allocated' memory buffers are
- * fixed-size 4k pages. (or larger if used with an increment
- * highger than 1) use fixmap_set(idx,phys) to associate
- * physical memory with fixmap indices.
- *
- * TLB entries of such buffers will not be flushed across
- * task switches.
- */
-enum fixed_addresses {
-	FIX_HOLE,
-	FIX_VDSO,
-	FIX_DBGP_BASE,
-	FIX_EARLYCON_MEM_BASE,
-#ifdef CONFIG_X86_LOCAL_APIC
-	FIX_APIC_BASE,	/* local (CPU) APIC) -- required for SMP or not */
-#endif
-#ifdef CONFIG_X86_IO_APIC
-	FIX_IO_APIC_BASE_0,
-	FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS-1,
-#endif
-#ifdef CONFIG_X86_VISWS_APIC
-	FIX_CO_CPU,	/* Cobalt timer */
-	FIX_CO_APIC,	/* Cobalt APIC Redirection Table */
-	FIX_LI_PCIA,	/* Lithium PCI Bridge A */
-	FIX_LI_PCIB,	/* Lithium PCI Bridge B */
-#endif
-#ifdef CONFIG_X86_F00F_BUG
-	FIX_F00F_IDT,	/* Virtual mapping for IDT */
-#endif
-#ifdef CONFIG_X86_CYCLONE_TIMER
-	FIX_CYCLONE_TIMER, /*cyclone timer register*/
-#endif
-#ifdef CONFIG_HIGHMEM
-	FIX_KMAP_BEGIN,	/* reserved pte's for temporary kernel mappings */
-	FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
-#endif
-#ifdef CONFIG_PCI_MMCONFIG
-	FIX_PCIE_MCFG,
-#endif
-#ifdef CONFIG_PARAVIRT
-	FIX_PARAVIRT_BOOTMAP,
-#endif
-	__end_of_permanent_fixed_addresses,
-	/*
-	 * 256 temporary boot-time mappings, used by early_ioremap(),
-	 * before ioremap() is functional.
-	 *
-	 * We round it up to the next 256 pages boundary so that we
-	 * can have a single pgd entry and a single pte table:
-	 */
-#define NR_FIX_BTMAPS		64
-#define FIX_BTMAPS_SLOTS	4
-	FIX_BTMAP_END = __end_of_permanent_fixed_addresses + 256 -
-			(__end_of_permanent_fixed_addresses & 255),
-	FIX_BTMAP_BEGIN = FIX_BTMAP_END + NR_FIX_BTMAPS*FIX_BTMAPS_SLOTS - 1,
-	FIX_WP_TEST,
-#ifdef CONFIG_ACPI
-	FIX_ACPI_BEGIN,
-	FIX_ACPI_END = FIX_ACPI_BEGIN + FIX_ACPI_PAGES - 1,
-#endif
-#ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
-	FIX_OHCI1394_BASE,
-#endif
-	__end_of_fixed_addresses
-};
-
-extern void reserve_top_address(unsigned long reserve);
-
-
-#define FIXADDR_TOP	((unsigned long)__FIXADDR_TOP)
-
-#define __FIXADDR_SIZE	(__end_of_permanent_fixed_addresses << PAGE_SHIFT)
-#define __FIXADDR_BOOT_SIZE	(__end_of_fixed_addresses << PAGE_SHIFT)
-#define FIXADDR_START		(FIXADDR_TOP - __FIXADDR_SIZE)
-#define FIXADDR_BOOT_START	(FIXADDR_TOP - __FIXADDR_BOOT_SIZE)
-
-#endif /* !__ASSEMBLY__ */
-#endif /* ASM_X86__FIXMAP_32_H */
diff --git a/include/asm-x86/fixmap_64.h b/include/asm-x86/fixmap_64.h
deleted file mode 100644
index dab4751d1307..000000000000
--- a/include/asm-x86/fixmap_64.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * fixmap.h: compile-time virtual memory allocation
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998 Ingo Molnar
- */
-
-#ifndef ASM_X86__FIXMAP_64_H
-#define ASM_X86__FIXMAP_64_H
-
-#include <linux/kernel.h>
-#include <asm/acpi.h>
-#include <asm/apicdef.h>
-#include <asm/page.h>
-#include <asm/vsyscall.h>
-#include <asm/efi.h>
-
-/*
- * Here we define all the compile-time 'special' virtual
- * addresses. The point is to have a constant address at
- * compile time, but to set the physical address only
- * in the boot process.
- *
- * These 'compile-time allocated' memory buffers are
- * fixed-size 4k pages (or larger if used with an increment
- * higher than 1). Use set_fixmap(idx,phys) to associate
- * physical memory with fixmap indices.
- *
- * TLB entries of such buffers will not be flushed across
- * task switches.
- */
-
-enum fixed_addresses {
-	VSYSCALL_LAST_PAGE,
-	VSYSCALL_FIRST_PAGE = VSYSCALL_LAST_PAGE
-			    + ((VSYSCALL_END-VSYSCALL_START) >> PAGE_SHIFT) - 1,
-	VSYSCALL_HPET,
-	FIX_DBGP_BASE,
-	FIX_EARLYCON_MEM_BASE,
-	FIX_APIC_BASE,	/* local (CPU) APIC) -- required for SMP or not */
-	FIX_IO_APIC_BASE_0,
-	FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1,
-	FIX_EFI_IO_MAP_LAST_PAGE,
-	FIX_EFI_IO_MAP_FIRST_PAGE = FIX_EFI_IO_MAP_LAST_PAGE
-				  + MAX_EFI_IO_PAGES - 1,
-#ifdef CONFIG_PARAVIRT
-	FIX_PARAVIRT_BOOTMAP,
-#endif
-	__end_of_permanent_fixed_addresses,
-#ifdef CONFIG_ACPI
-	FIX_ACPI_BEGIN,
-	FIX_ACPI_END = FIX_ACPI_BEGIN + FIX_ACPI_PAGES - 1,
-#endif
-#ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
-	FIX_OHCI1394_BASE,
-#endif
-	/*
-	 * 256 temporary boot-time mappings, used by early_ioremap(),
-	 * before ioremap() is functional.
-	 *
-	 * We round it up to the next 256 pages boundary so that we
-	 * can have a single pgd entry and a single pte table:
-	 */
-#define NR_FIX_BTMAPS		64
-#define FIX_BTMAPS_SLOTS	4
-	FIX_BTMAP_END = __end_of_permanent_fixed_addresses + 256 -
-			(__end_of_permanent_fixed_addresses & 255),
-	FIX_BTMAP_BEGIN = FIX_BTMAP_END + NR_FIX_BTMAPS*FIX_BTMAPS_SLOTS - 1,
-	__end_of_fixed_addresses
-};
-
-#define FIXADDR_TOP	(VSYSCALL_END-PAGE_SIZE)
-#define FIXADDR_SIZE	(__end_of_fixed_addresses << PAGE_SHIFT)
-#define FIXADDR_START	(FIXADDR_TOP - FIXADDR_SIZE)
-
-/* Only covers 32bit vsyscalls currently. Need another set for 64bit. */
-#define FIXADDR_USER_START	((unsigned long)VSYSCALL32_VSYSCALL)
-#define FIXADDR_USER_END	(FIXADDR_USER_START + PAGE_SIZE)
-
-#endif /* ASM_X86__FIXMAP_64_H */
diff --git a/include/asm-x86/floppy.h b/include/asm-x86/floppy.h
deleted file mode 100644
index 7d83a3a83e37..000000000000
--- a/include/asm-x86/floppy.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
- * Architecture specific parts of the Floppy driver
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995
- */
-#ifndef ASM_X86__FLOPPY_H
-#define ASM_X86__FLOPPY_H
-
-#include <linux/vmalloc.h>
-
-/*
- * The DMA channel used by the floppy controller cannot access data at
- * addresses >= 16MB
- *
- * Went back to the 1MB limit, as some people had problems with the floppy
- * driver otherwise. It doesn't matter much for performance anyway, as most
- * floppy accesses go through the track buffer.
- */
-#define _CROSS_64KB(a, s, vdma)						\
-	(!(vdma) &&							\
-	 ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64))
-
-#define CROSS_64KB(a, s) _CROSS_64KB(a, s, use_virtual_dma & 1)
-
-
-#define SW fd_routine[use_virtual_dma & 1]
-#define CSW fd_routine[can_use_virtual_dma & 1]
-
-
-#define fd_inb(port)		inb_p(port)
-#define fd_outb(value, port)	outb_p(value, port)
-
-#define fd_request_dma()	CSW._request_dma(FLOPPY_DMA, "floppy")
-#define fd_free_dma()		CSW._free_dma(FLOPPY_DMA)
-#define fd_enable_irq()		enable_irq(FLOPPY_IRQ)
-#define fd_disable_irq()	disable_irq(FLOPPY_IRQ)
-#define fd_free_irq()		free_irq(FLOPPY_IRQ, NULL)
-#define fd_get_dma_residue()	SW._get_dma_residue(FLOPPY_DMA)
-#define fd_dma_mem_alloc(size)	SW._dma_mem_alloc(size)
-#define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io)
-
-#define FLOPPY_CAN_FALLBACK_ON_NODMA
-
-static int virtual_dma_count;
-static int virtual_dma_residue;
-static char *virtual_dma_addr;
-static int virtual_dma_mode;
-static int doing_pdma;
-
-static irqreturn_t floppy_hardint(int irq, void *dev_id)
-{
-	unsigned char st;
-
-#undef TRACE_FLPY_INT
-
-#ifdef TRACE_FLPY_INT
-	static int calls;
-	static int bytes;
-	static int dma_wait;
-#endif
-	if (!doing_pdma)
-		return floppy_interrupt(irq, dev_id);
-
-#ifdef TRACE_FLPY_INT
-	if (!calls)
-		bytes = virtual_dma_count;
-#endif
-
-	{
-		int lcount;
-		char *lptr;
-
-		st = 1;
-		for (lcount = virtual_dma_count, lptr = virtual_dma_addr;
-		     lcount; lcount--, lptr++) {
-			st = inb(virtual_dma_port + 4) & 0xa0;
-			if (st != 0xa0)
-				break;
-			if (virtual_dma_mode)
-				outb_p(*lptr, virtual_dma_port + 5);
-			else
-				*lptr = inb_p(virtual_dma_port + 5);
-		}
-		virtual_dma_count = lcount;
-		virtual_dma_addr = lptr;
-		st = inb(virtual_dma_port + 4);
-	}
-
-#ifdef TRACE_FLPY_INT
-	calls++;
-#endif
-	if (st == 0x20)
-		return IRQ_HANDLED;
-	if (!(st & 0x20)) {
-		virtual_dma_residue += virtual_dma_count;
-		virtual_dma_count = 0;
-#ifdef TRACE_FLPY_INT
-		printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n",
-		       virtual_dma_count, virtual_dma_residue, calls, bytes,
-		       dma_wait);
-		calls = 0;
-		dma_wait = 0;
-#endif
-		doing_pdma = 0;
-		floppy_interrupt(irq, dev_id);
-		return IRQ_HANDLED;
-	}
-#ifdef TRACE_FLPY_INT
-	if (!virtual_dma_count)
-		dma_wait++;
-#endif
-	return IRQ_HANDLED;
-}
-
-static void fd_disable_dma(void)
-{
-	if (!(can_use_virtual_dma & 1))
-		disable_dma(FLOPPY_DMA);
-	doing_pdma = 0;
-	virtual_dma_residue += virtual_dma_count;
-	virtual_dma_count = 0;
-}
-
-static int vdma_request_dma(unsigned int dmanr, const char *device_id)
-{
-	return 0;
-}
-
-static void vdma_nop(unsigned int dummy)
-{
-}
-
-
-static int vdma_get_dma_residue(unsigned int dummy)
-{
-	return virtual_dma_count + virtual_dma_residue;
-}
-
-
-static int fd_request_irq(void)
-{
-	if (can_use_virtual_dma)
-		return request_irq(FLOPPY_IRQ, floppy_hardint,
-				   IRQF_DISABLED, "floppy", NULL);
-	else
-		return request_irq(FLOPPY_IRQ, floppy_interrupt,
-				   IRQF_DISABLED, "floppy", NULL);
-}
-
-static unsigned long dma_mem_alloc(unsigned long size)
-{
-	return __get_dma_pages(GFP_KERNEL|__GFP_NORETRY, get_order(size));
-}
-
-
-static unsigned long vdma_mem_alloc(unsigned long size)
-{
-	return (unsigned long)vmalloc(size);
-
-}
-
-#define nodma_mem_alloc(size) vdma_mem_alloc(size)
-
-static void _fd_dma_mem_free(unsigned long addr, unsigned long size)
-{
-	if ((unsigned long)addr >= (unsigned long)high_memory)
-		vfree((void *)addr);
-	else
-		free_pages(addr, get_order(size));
-}
-
-#define fd_dma_mem_free(addr, size)  _fd_dma_mem_free(addr, size)
-
-static void _fd_chose_dma_mode(char *addr, unsigned long size)
-{
-	if (can_use_virtual_dma == 2) {
-		if ((unsigned long)addr >= (unsigned long)high_memory ||
-		    isa_virt_to_bus(addr) >= 0x1000000 ||
-		    _CROSS_64KB(addr, size, 0))
-			use_virtual_dma = 1;
-		else
-			use_virtual_dma = 0;
-	} else {
-		use_virtual_dma = can_use_virtual_dma & 1;
-	}
-}
-
-#define fd_chose_dma_mode(addr, size) _fd_chose_dma_mode(addr, size)
-
-
-static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
-{
-	doing_pdma = 1;
-	virtual_dma_port = io;
-	virtual_dma_mode = (mode == DMA_MODE_WRITE);
-	virtual_dma_addr = addr;
-	virtual_dma_count = size;
-	virtual_dma_residue = 0;
-	return 0;
-}
-
-static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
-{
-#ifdef FLOPPY_SANITY_CHECK
-	if (CROSS_64KB(addr, size)) {
-		printk("DMA crossing 64-K boundary %p-%p\n", addr, addr+size);
-		return -1;
-	}
-#endif
-	/* actual, physical DMA */
-	doing_pdma = 0;
-	clear_dma_ff(FLOPPY_DMA);
-	set_dma_mode(FLOPPY_DMA, mode);
-	set_dma_addr(FLOPPY_DMA, isa_virt_to_bus(addr));
-	set_dma_count(FLOPPY_DMA, size);
-	enable_dma(FLOPPY_DMA);
-	return 0;
-}
-
-static struct fd_routine_l {
-	int (*_request_dma)(unsigned int dmanr, const char *device_id);
-	void (*_free_dma)(unsigned int dmanr);
-	int (*_get_dma_residue)(unsigned int dummy);
-	unsigned long (*_dma_mem_alloc)(unsigned long size);
-	int (*_dma_setup)(char *addr, unsigned long size, int mode, int io);
-} fd_routine[] = {
-	{
-		request_dma,
-		free_dma,
-		get_dma_residue,
-		dma_mem_alloc,
-		hard_dma_setup
-	},
-	{
-		vdma_request_dma,
-		vdma_nop,
-		vdma_get_dma_residue,
-		vdma_mem_alloc,
-		vdma_dma_setup
-	}
-};
-
-
-static int FDC1 = 0x3f0;
-static int FDC2 = -1;
-
-/*
- * Floppy types are stored in the rtc's CMOS RAM and so rtc_lock
- * is needed to prevent corrupted CMOS RAM in case "insmod floppy"
- * coincides with another rtc CMOS user.		Paul G.
- */
-#define FLOPPY0_TYPE					\
-({							\
-	unsigned long flags;				\
-	unsigned char val;				\
-	spin_lock_irqsave(&rtc_lock, flags);		\
-	val = (CMOS_READ(0x10) >> 4) & 15;		\
-	spin_unlock_irqrestore(&rtc_lock, flags);	\
-	val;						\
-})
-
-#define FLOPPY1_TYPE					\
-({							\
-	unsigned long flags;				\
-	unsigned char val;				\
-	spin_lock_irqsave(&rtc_lock, flags);		\
-	val = CMOS_READ(0x10) & 15;			\
-	spin_unlock_irqrestore(&rtc_lock, flags);	\
-	val;						\
-})
-
-#define N_FDC 2
-#define N_DRIVE 8
-
-#define EXTRA_FLOPPY_PARAMS
-
-#endif /* ASM_X86__FLOPPY_H */
diff --git a/include/asm-x86/frame.h b/include/asm-x86/frame.h
deleted file mode 100644
index 06850a7194e1..000000000000
--- a/include/asm-x86/frame.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifdef __ASSEMBLY__
-
-#include <asm/dwarf2.h>
-
-/* The annotation hides the frame from the unwinder and makes it look
-   like a ordinary ebp save/restore. This avoids some special cases for
-   frame pointer later */
-#ifdef CONFIG_FRAME_POINTER
-	.macro FRAME
-	pushl %ebp
-	CFI_ADJUST_CFA_OFFSET 4
-	CFI_REL_OFFSET ebp,0
-	movl %esp,%ebp
-	.endm
-	.macro ENDFRAME
-	popl %ebp
-	CFI_ADJUST_CFA_OFFSET -4
-	CFI_RESTORE ebp
-	.endm
-#else
-	.macro FRAME
-	.endm
-	.macro ENDFRAME
-	.endm
-#endif
-
-#endif  /*  __ASSEMBLY__  */
diff --git a/include/asm-x86/ftrace.h b/include/asm-x86/ftrace.h
deleted file mode 100644
index be0e004ad148..000000000000
--- a/include/asm-x86/ftrace.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef ASM_X86__FTRACE_H
-#define ASM_X86__FTRACE_H
-
-#ifdef CONFIG_FTRACE
-#define MCOUNT_ADDR		((long)(mcount))
-#define MCOUNT_INSN_SIZE	5 /* sizeof mcount call */
-
-#ifndef __ASSEMBLY__
-extern void mcount(void);
-#endif
-
-#endif /* CONFIG_FTRACE */
-
-#endif /* ASM_X86__FTRACE_H */
diff --git a/include/asm-x86/futex.h b/include/asm-x86/futex.h
deleted file mode 100644
index 06b924ef6fa5..000000000000
--- a/include/asm-x86/futex.h
+++ /dev/null
@@ -1,140 +0,0 @@
-#ifndef ASM_X86__FUTEX_H
-#define ASM_X86__FUTEX_H
-
-#ifdef __KERNEL__
-
-#include <linux/futex.h>
-#include <linux/uaccess.h>
-
-#include <asm/asm.h>
-#include <asm/errno.h>
-#include <asm/processor.h>
-#include <asm/system.h>
-
-#define __futex_atomic_op1(insn, ret, oldval, uaddr, oparg)	\
-	asm volatile("1:\t" insn "\n"				\
-		     "2:\t.section .fixup,\"ax\"\n"		\
-		     "3:\tmov\t%3, %1\n"			\
-		     "\tjmp\t2b\n"				\
-		     "\t.previous\n"				\
-		     _ASM_EXTABLE(1b, 3b)			\
-		     : "=r" (oldval), "=r" (ret), "+m" (*uaddr)	\
-		     : "i" (-EFAULT), "0" (oparg), "1" (0))
-
-#define __futex_atomic_op2(insn, ret, oldval, uaddr, oparg)	\
-	asm volatile("1:\tmovl	%2, %0\n"			\
-		     "\tmovl\t%0, %3\n"				\
-		     "\t" insn "\n"				\
-		     "2:\t" LOCK_PREFIX "cmpxchgl %3, %2\n"	\
-		     "\tjnz\t1b\n"				\
-		     "3:\t.section .fixup,\"ax\"\n"		\
-		     "4:\tmov\t%5, %1\n"			\
-		     "\tjmp\t3b\n"				\
-		     "\t.previous\n"				\
-		     _ASM_EXTABLE(1b, 4b)			\
-		     _ASM_EXTABLE(2b, 4b)			\
-		     : "=&a" (oldval), "=&r" (ret),		\
-		       "+m" (*uaddr), "=&r" (tem)		\
-		     : "r" (oparg), "i" (-EFAULT), "1" (0))
-
-static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
-{
-	int op = (encoded_op >> 28) & 7;
-	int cmp = (encoded_op >> 24) & 15;
-	int oparg = (encoded_op << 8) >> 20;
-	int cmparg = (encoded_op << 20) >> 20;
-	int oldval = 0, ret, tem;
-
-	if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
-		oparg = 1 << oparg;
-
-	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
-		return -EFAULT;
-
-#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_BSWAP)
-	/* Real i386 machines can only support FUTEX_OP_SET */
-	if (op != FUTEX_OP_SET && boot_cpu_data.x86 == 3)
-		return -ENOSYS;
-#endif
-
-	pagefault_disable();
-
-	switch (op) {
-	case FUTEX_OP_SET:
-		__futex_atomic_op1("xchgl %0, %2", ret, oldval, uaddr, oparg);
-		break;
-	case FUTEX_OP_ADD:
-		__futex_atomic_op1(LOCK_PREFIX "xaddl %0, %2", ret, oldval,
-				   uaddr, oparg);
-		break;
-	case FUTEX_OP_OR:
-		__futex_atomic_op2("orl %4, %3", ret, oldval, uaddr, oparg);
-		break;
-	case FUTEX_OP_ANDN:
-		__futex_atomic_op2("andl %4, %3", ret, oldval, uaddr, ~oparg);
-		break;
-	case FUTEX_OP_XOR:
-		__futex_atomic_op2("xorl %4, %3", ret, oldval, uaddr, oparg);
-		break;
-	default:
-		ret = -ENOSYS;
-	}
-
-	pagefault_enable();
-
-	if (!ret) {
-		switch (cmp) {
-		case FUTEX_OP_CMP_EQ:
-			ret = (oldval == cmparg);
-			break;
-		case FUTEX_OP_CMP_NE:
-			ret = (oldval != cmparg);
-			break;
-		case FUTEX_OP_CMP_LT:
-			ret = (oldval < cmparg);
-			break;
-		case FUTEX_OP_CMP_GE:
-			ret = (oldval >= cmparg);
-			break;
-		case FUTEX_OP_CMP_LE:
-			ret = (oldval <= cmparg);
-			break;
-		case FUTEX_OP_CMP_GT:
-			ret = (oldval > cmparg);
-			break;
-		default:
-			ret = -ENOSYS;
-		}
-	}
-	return ret;
-}
-
-static inline int futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval,
-						int newval)
-{
-
-#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_BSWAP)
-	/* Real i386 machines have no cmpxchg instruction */
-	if (boot_cpu_data.x86 == 3)
-		return -ENOSYS;
-#endif
-
-	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
-		return -EFAULT;
-
-	asm volatile("1:\t" LOCK_PREFIX "cmpxchgl %3, %1\n"
-		     "2:\t.section .fixup, \"ax\"\n"
-		     "3:\tmov     %2, %0\n"
-		     "\tjmp     2b\n"
-		     "\t.previous\n"
-		     _ASM_EXTABLE(1b, 3b)
-		     : "=a" (oldval), "+m" (*uaddr)
-		     : "i" (-EFAULT), "r" (newval), "0" (oldval)
-		     : "memory"
-	);
-
-	return oldval;
-}
-
-#endif
-#endif /* ASM_X86__FUTEX_H */
diff --git a/include/asm-x86/gart.h b/include/asm-x86/gart.h
deleted file mode 100644
index 605edb39ef9e..000000000000
--- a/include/asm-x86/gart.h
+++ /dev/null
@@ -1,73 +0,0 @@
-#ifndef ASM_X86__GART_H
-#define ASM_X86__GART_H
-
-#include <asm/e820.h>
-
-extern void set_up_gart_resume(u32, u32);
-
-extern int fallback_aper_order;
-extern int fallback_aper_force;
-extern int fix_aperture;
-
-/* PTE bits. */
-#define GPTE_VALID	1
-#define GPTE_COHERENT	2
-
-/* Aperture control register bits. */
-#define GARTEN		(1<<0)
-#define DISGARTCPU	(1<<4)
-#define DISGARTIO	(1<<5)
-
-/* GART cache control register bits. */
-#define INVGART		(1<<0)
-#define GARTPTEERR	(1<<1)
-
-/* K8 On-cpu GART registers */
-#define AMD64_GARTAPERTURECTL	0x90
-#define AMD64_GARTAPERTUREBASE	0x94
-#define AMD64_GARTTABLEBASE	0x98
-#define AMD64_GARTCACHECTL	0x9c
-#define AMD64_GARTEN		(1<<0)
-
-extern int agp_amd64_init(void);
-
-static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
-{
-	u32 tmp, ctl;
-
-        /* address of the mappings table */
-        addr >>= 12;
-        tmp = (u32) addr<<4;
-        tmp &= ~0xf;
-        pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);
-
-        /* Enable GART translation for this hammer. */
-        pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
-        ctl |= GARTEN;
-        ctl &= ~(DISGARTCPU | DISGARTIO);
-        pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
-}
-
-static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
-{
-	if (!aper_base)
-		return 0;
-
-	if (aper_base + aper_size > 0x100000000ULL) {
-		printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n");
-		return 0;
-	}
-	if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
-		printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n");
-		return 0;
-	}
-	if (aper_size < min_size) {
-		printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n",
-				 aper_size>>20, min_size>>20);
-		return 0;
-	}
-
-	return 1;
-}
-
-#endif /* ASM_X86__GART_H */
diff --git a/include/asm-x86/genapic.h b/include/asm-x86/genapic.h
deleted file mode 100644
index d48bee663a6f..000000000000
--- a/include/asm-x86/genapic.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifdef CONFIG_X86_32
-# include "genapic_32.h"
-#else
-# include "genapic_64.h"
-#endif
diff --git a/include/asm-x86/genapic_32.h b/include/asm-x86/genapic_32.h
deleted file mode 100644
index 34280f027664..000000000000
--- a/include/asm-x86/genapic_32.h
+++ /dev/null
@@ -1,124 +0,0 @@
-#ifndef ASM_X86__GENAPIC_32_H
-#define ASM_X86__GENAPIC_32_H
-
-#include <asm/mpspec.h>
-
-/*
- * Generic APIC driver interface.
- *
- * An straight forward mapping of the APIC related parts of the
- * x86 subarchitecture interface to a dynamic object.
- *
- * This is used by the "generic" x86 subarchitecture.
- *
- * Copyright 2003 Andi Kleen, SuSE Labs.
- */
-
-struct mpc_config_bus;
-struct mp_config_table;
-struct mpc_config_processor;
-
-struct genapic {
-	char *name;
-	int (*probe)(void);
-
-	int (*apic_id_registered)(void);
-	cpumask_t (*target_cpus)(void);
-	int int_delivery_mode;
-	int int_dest_mode;
-	int ESR_DISABLE;
-	int apic_destination_logical;
-	unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid);
-	unsigned long (*check_apicid_present)(int apicid);
-	int no_balance_irq;
-	int no_ioapic_check;
-	void (*init_apic_ldr)(void);
-	physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map);
-
-	void (*setup_apic_routing)(void);
-	int (*multi_timer_check)(int apic, int irq);
-	int (*apicid_to_node)(int logical_apicid);
-	int (*cpu_to_logical_apicid)(int cpu);
-	int (*cpu_present_to_apicid)(int mps_cpu);
-	physid_mask_t (*apicid_to_cpu_present)(int phys_apicid);
-	void (*setup_portio_remap)(void);
-	int (*check_phys_apicid_present)(int boot_cpu_physical_apicid);
-	void (*enable_apic_mode)(void);
-	u32 (*phys_pkg_id)(u32 cpuid_apic, int index_msb);
-
-	/* mpparse */
-	/* When one of the next two hooks returns 1 the genapic
-	   is switched to this. Essentially they are additional probe
-	   functions. */
-	int (*mps_oem_check)(struct mp_config_table *mpc, char *oem,
-			     char *productid);
-	int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
-
-	unsigned (*get_apic_id)(unsigned long x);
-	unsigned long apic_id_mask;
-	unsigned int (*cpu_mask_to_apicid)(cpumask_t cpumask);
-
-#ifdef CONFIG_SMP
-	/* ipi */
-	void (*send_IPI_mask)(cpumask_t mask, int vector);
-	void (*send_IPI_allbutself)(int vector);
-	void (*send_IPI_all)(int vector);
-#endif
-};
-
-#define APICFUNC(x) .x = x,
-
-/* More functions could be probably marked IPIFUNC and save some space
-   in UP GENERICARCH kernels, but I don't have the nerve right now
-   to untangle this mess. -AK  */
-#ifdef CONFIG_SMP
-#define IPIFUNC(x) APICFUNC(x)
-#else
-#define IPIFUNC(x)
-#endif
-
-#define APIC_INIT(aname, aprobe)			\
-{							\
-	.name = aname,					\
-	.probe = aprobe,				\
-	.int_delivery_mode = INT_DELIVERY_MODE,		\
-	.int_dest_mode = INT_DEST_MODE,			\
-	.no_balance_irq = NO_BALANCE_IRQ,		\
-	.ESR_DISABLE = esr_disable,			\
-	.apic_destination_logical = APIC_DEST_LOGICAL,	\
-	APICFUNC(apic_id_registered)			\
-	APICFUNC(target_cpus)				\
-	APICFUNC(check_apicid_used)			\
-	APICFUNC(check_apicid_present)			\
-	APICFUNC(init_apic_ldr)				\
-	APICFUNC(ioapic_phys_id_map)			\
-	APICFUNC(setup_apic_routing)			\
-	APICFUNC(multi_timer_check)			\
-	APICFUNC(apicid_to_node)			\
-	APICFUNC(cpu_to_logical_apicid)			\
-	APICFUNC(cpu_present_to_apicid)			\
-	APICFUNC(apicid_to_cpu_present)			\
-	APICFUNC(setup_portio_remap)			\
-	APICFUNC(check_phys_apicid_present)		\
-	APICFUNC(mps_oem_check)				\
-	APICFUNC(get_apic_id)				\
-	.apic_id_mask = APIC_ID_MASK,			\
-	APICFUNC(cpu_mask_to_apicid)			\
-	APICFUNC(acpi_madt_oem_check)			\
-	IPIFUNC(send_IPI_mask)				\
-	IPIFUNC(send_IPI_allbutself)			\
-	IPIFUNC(send_IPI_all)				\
-	APICFUNC(enable_apic_mode)			\
-	APICFUNC(phys_pkg_id)				\
-}
-
-extern struct genapic *genapic;
-
-enum uv_system_type {UV_NONE, UV_LEGACY_APIC, UV_X2APIC, UV_NON_UNIQUE_APIC};
-#define get_uv_system_type()		UV_NONE
-#define is_uv_system()			0
-#define uv_wakeup_secondary(a, b)	1
-#define uv_system_init()		do {} while (0)
-
-
-#endif /* ASM_X86__GENAPIC_32_H */
diff --git a/include/asm-x86/genapic_64.h b/include/asm-x86/genapic_64.h
deleted file mode 100644
index ed6a4886c082..000000000000
--- a/include/asm-x86/genapic_64.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef ASM_X86__GENAPIC_64_H
-#define ASM_X86__GENAPIC_64_H
-
-/*
- * Copyright 2004 James Cleverdon, IBM.
- * Subject to the GNU Public License, v.2
- *
- * Generic APIC sub-arch data struct.
- *
- * Hacked for x86-64 by James Cleverdon from i386 architecture code by
- * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
- * James Cleverdon.
- */
-
-struct genapic {
-	char *name;
-	int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
-	u32 int_delivery_mode;
-	u32 int_dest_mode;
-	int (*apic_id_registered)(void);
-	cpumask_t (*target_cpus)(void);
-	cpumask_t (*vector_allocation_domain)(int cpu);
-	void (*init_apic_ldr)(void);
-	/* ipi */
-	void (*send_IPI_mask)(cpumask_t mask, int vector);
-	void (*send_IPI_allbutself)(int vector);
-	void (*send_IPI_all)(int vector);
-	void (*send_IPI_self)(int vector);
-	/* */
-	unsigned int (*cpu_mask_to_apicid)(cpumask_t cpumask);
-	unsigned int (*phys_pkg_id)(int index_msb);
-	unsigned int (*get_apic_id)(unsigned long x);
-	unsigned long (*set_apic_id)(unsigned int id);
-	unsigned long apic_id_mask;
-};
-
-extern struct genapic *genapic;
-
-extern struct genapic apic_flat;
-extern struct genapic apic_physflat;
-extern struct genapic apic_x2apic_cluster;
-extern struct genapic apic_x2apic_phys;
-extern int acpi_madt_oem_check(char *, char *);
-
-extern void apic_send_IPI_self(int vector);
-enum uv_system_type {UV_NONE, UV_LEGACY_APIC, UV_X2APIC, UV_NON_UNIQUE_APIC};
-extern enum uv_system_type get_uv_system_type(void);
-extern int is_uv_system(void);
-
-extern struct genapic apic_x2apic_uv_x;
-DECLARE_PER_CPU(int, x2apic_extra_bits);
-extern void uv_cpu_init(void);
-extern void uv_system_init(void);
-extern int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip);
-
-extern void setup_apic_routing(void);
-
-#endif /* ASM_X86__GENAPIC_64_H */
diff --git a/include/asm-x86/geode.h b/include/asm-x86/geode.h
deleted file mode 100644
index 3f3444be2638..000000000000
--- a/include/asm-x86/geode.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * AMD Geode definitions
- * Copyright (C) 2006, Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of version 2 of the GNU General Public License
- * as published by the Free Software Foundation.
- */
-
-#ifndef ASM_X86__GEODE_H
-#define ASM_X86__GEODE_H
-
-#include <asm/processor.h>
-#include <linux/io.h>
-
-/* Generic southbridge functions */
-
-#define GEODE_DEV_PMS 0
-#define GEODE_DEV_ACPI 1
-#define GEODE_DEV_GPIO 2
-#define GEODE_DEV_MFGPT 3
-
-extern int geode_get_dev_base(unsigned int dev);
-
-/* Useful macros */
-#define geode_pms_base()	geode_get_dev_base(GEODE_DEV_PMS)
-#define geode_acpi_base()	geode_get_dev_base(GEODE_DEV_ACPI)
-#define geode_gpio_base()	geode_get_dev_base(GEODE_DEV_GPIO)
-#define geode_mfgpt_base()	geode_get_dev_base(GEODE_DEV_MFGPT)
-
-/* MSRS */
-
-#define MSR_GLIU_P2D_RO0	0x10000029
-
-#define MSR_LX_GLD_MSR_CONFIG	0x48002001
-#define MSR_LX_MSR_PADSEL	0x48002011	/* NOT 0x48000011; the data
-						 * sheet has the wrong value */
-#define MSR_GLCP_SYS_RSTPLL	0x4C000014
-#define MSR_GLCP_DOTPLL		0x4C000015
-
-#define MSR_LBAR_SMB		0x5140000B
-#define MSR_LBAR_GPIO		0x5140000C
-#define MSR_LBAR_MFGPT		0x5140000D
-#define MSR_LBAR_ACPI		0x5140000E
-#define MSR_LBAR_PMS		0x5140000F
-
-#define MSR_DIVIL_SOFT_RESET	0x51400017
-
-#define MSR_PIC_YSEL_LOW	0x51400020
-#define MSR_PIC_YSEL_HIGH	0x51400021
-#define MSR_PIC_ZSEL_LOW	0x51400022
-#define MSR_PIC_ZSEL_HIGH	0x51400023
-#define MSR_PIC_IRQM_LPC	0x51400025
-
-#define MSR_MFGPT_IRQ		0x51400028
-#define MSR_MFGPT_NR		0x51400029
-#define MSR_MFGPT_SETUP		0x5140002B
-
-#define MSR_LX_SPARE_MSR	0x80000011	/* DC-specific */
-
-#define MSR_GX_GLD_MSR_CONFIG	0xC0002001
-#define MSR_GX_MSR_PADSEL	0xC0002011
-
-/* Resource Sizes */
-
-#define LBAR_GPIO_SIZE		0xFF
-#define LBAR_MFGPT_SIZE		0x40
-#define LBAR_ACPI_SIZE		0x40
-#define LBAR_PMS_SIZE		0x80
-
-/* ACPI registers (PMS block) */
-
-/*
- * PM1_EN is only valid when VSA is enabled for 16 bit reads.
- * When VSA is not enabled, *always* read both PM1_STS and PM1_EN
- * with a 32 bit read at offset 0x0
- */
-
-#define PM1_STS			0x00
-#define PM1_EN			0x02
-#define PM1_CNT			0x08
-#define PM2_CNT			0x0C
-#define PM_TMR			0x10
-#define PM_GPE0_STS		0x18
-#define PM_GPE0_EN		0x1C
-
-/* PMC registers (PMS block) */
-
-#define PM_SSD			0x00
-#define PM_SCXA			0x04
-#define PM_SCYA			0x08
-#define PM_OUT_SLPCTL		0x0C
-#define PM_SCLK			0x10
-#define PM_SED			0x1
-#define PM_SCXD			0x18
-#define PM_SCYD			0x1C
-#define PM_IN_SLPCTL		0x20
-#define PM_WKD			0x30
-#define PM_WKXD			0x34
-#define PM_RD			0x38
-#define PM_WKXA			0x3C
-#define PM_FSD			0x40
-#define PM_TSD			0x44
-#define PM_PSD			0x48
-#define PM_NWKD			0x4C
-#define PM_AWKD			0x50
-#define PM_SSC			0x54
-
-/* VSA2 magic values */
-
-#define VSA_VRC_INDEX		0xAC1C
-#define VSA_VRC_DATA		0xAC1E
-#define VSA_VR_UNLOCK		0xFC53	/* unlock virtual register */
-#define VSA_VR_SIGNATURE	0x0003
-#define VSA_VR_MEM_SIZE		0x0200
-#define AMD_VSA_SIG		0x4132	/* signature is ascii 'VSA2' */
-#define GSW_VSA_SIG		0x534d  /* General Software signature */
-/* GPIO */
-
-#define GPIO_OUTPUT_VAL		0x00
-#define GPIO_OUTPUT_ENABLE	0x04
-#define GPIO_OUTPUT_OPEN_DRAIN	0x08
-#define GPIO_OUTPUT_INVERT	0x0C
-#define GPIO_OUTPUT_AUX1	0x10
-#define GPIO_OUTPUT_AUX2	0x14
-#define GPIO_PULL_UP		0x18
-#define GPIO_PULL_DOWN		0x1C
-#define GPIO_INPUT_ENABLE	0x20
-#define GPIO_INPUT_INVERT	0x24
-#define GPIO_INPUT_FILTER	0x28
-#define GPIO_INPUT_EVENT_COUNT	0x2C
-#define GPIO_READ_BACK		0x30
-#define GPIO_INPUT_AUX1		0x34
-#define GPIO_EVENTS_ENABLE	0x38
-#define GPIO_LOCK_ENABLE	0x3C
-#define GPIO_POSITIVE_EDGE_EN	0x40
-#define GPIO_NEGATIVE_EDGE_EN	0x44
-#define GPIO_POSITIVE_EDGE_STS	0x48
-#define GPIO_NEGATIVE_EDGE_STS	0x4C
-
-#define GPIO_MAP_X		0xE0
-#define GPIO_MAP_Y		0xE4
-#define GPIO_MAP_Z		0xE8
-#define GPIO_MAP_W		0xEC
-
-static inline u32 geode_gpio(unsigned int nr)
-{
-	BUG_ON(nr > 28);
-	return 1 << nr;
-}
-
-extern void geode_gpio_set(u32, unsigned int);
-extern void geode_gpio_clear(u32, unsigned int);
-extern int geode_gpio_isset(u32, unsigned int);
-extern void geode_gpio_setup_event(unsigned int, int, int);
-extern void geode_gpio_set_irq(unsigned int, unsigned int);
-
-static inline void geode_gpio_event_irq(unsigned int gpio, int pair)
-{
-	geode_gpio_setup_event(gpio, pair, 0);
-}
-
-static inline void geode_gpio_event_pme(unsigned int gpio, int pair)
-{
-	geode_gpio_setup_event(gpio, pair, 1);
-}
-
-/* Specific geode tests */
-
-static inline int is_geode_gx(void)
-{
-	return ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC) &&
-		(boot_cpu_data.x86 == 5) &&
-		(boot_cpu_data.x86_model == 5));
-}
-
-static inline int is_geode_lx(void)
-{
-	return ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
-		(boot_cpu_data.x86 == 5) &&
-		(boot_cpu_data.x86_model == 10));
-}
-
-static inline int is_geode(void)
-{
-	return (is_geode_gx() || is_geode_lx());
-}
-
-#ifdef CONFIG_MGEODE_LX
-extern int geode_has_vsa2(void);
-#else
-static inline int geode_has_vsa2(void)
-{
-	return 0;
-}
-#endif
-
-/* MFGPTs */
-
-#define MFGPT_MAX_TIMERS	8
-#define MFGPT_TIMER_ANY		(-1)
-
-#define MFGPT_DOMAIN_WORKING	1
-#define MFGPT_DOMAIN_STANDBY	2
-#define MFGPT_DOMAIN_ANY	(MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)
-
-#define MFGPT_CMP1		0
-#define MFGPT_CMP2		1
-
-#define MFGPT_EVENT_IRQ		0
-#define MFGPT_EVENT_NMI		1
-#define MFGPT_EVENT_RESET	3
-
-#define MFGPT_REG_CMP1		0
-#define MFGPT_REG_CMP2		2
-#define MFGPT_REG_COUNTER	4
-#define MFGPT_REG_SETUP		6
-
-#define MFGPT_SETUP_CNTEN	(1 << 15)
-#define MFGPT_SETUP_CMP2	(1 << 14)
-#define MFGPT_SETUP_CMP1	(1 << 13)
-#define MFGPT_SETUP_SETUP	(1 << 12)
-#define MFGPT_SETUP_STOPEN	(1 << 11)
-#define MFGPT_SETUP_EXTEN	(1 << 10)
-#define MFGPT_SETUP_REVEN	(1 << 5)
-#define MFGPT_SETUP_CLKSEL	(1 << 4)
-
-static inline void geode_mfgpt_write(int timer, u16 reg, u16 value)
-{
-	u32 base = geode_get_dev_base(GEODE_DEV_MFGPT);
-	outw(value, base + reg + (timer * 8));
-}
-
-static inline u16 geode_mfgpt_read(int timer, u16 reg)
-{
-	u32 base = geode_get_dev_base(GEODE_DEV_MFGPT);
-	return inw(base + reg + (timer * 8));
-}
-
-extern int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable);
-extern int geode_mfgpt_set_irq(int timer, int cmp, int *irq, int enable);
-extern int geode_mfgpt_alloc_timer(int timer, int domain);
-
-#define geode_mfgpt_setup_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 1)
-#define geode_mfgpt_release_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 0)
-
-#ifdef CONFIG_GEODE_MFGPT_TIMER
-extern int __init mfgpt_timer_setup(void);
-#else
-static inline int mfgpt_timer_setup(void) { return 0; }
-#endif
-
-#endif /* ASM_X86__GEODE_H */
diff --git a/include/asm-x86/gpio.h b/include/asm-x86/gpio.h
deleted file mode 100644
index 497fb980d962..000000000000
--- a/include/asm-x86/gpio.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Generic GPIO API implementation for x86.
- *
- * Derived from the generic GPIO API for powerpc:
- *
- * Copyright (c) 2007-2008  MontaVista Software, Inc.
- *
- * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef _ASM_I386_GPIO_H
-#define _ASM_I386_GPIO_H
-
-#include <asm-generic/gpio.h>
-
-#ifdef CONFIG_GPIOLIB
-
-/*
- * Just call gpiolib.
- */
-static inline int gpio_get_value(unsigned int gpio)
-{
-	return __gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned int gpio, int value)
-{
-	__gpio_set_value(gpio, value);
-}
-
-static inline int gpio_cansleep(unsigned int gpio)
-{
-	return __gpio_cansleep(gpio);
-}
-
-/*
- * Not implemented, yet.
- */
-static inline int gpio_to_irq(unsigned int gpio)
-{
-	return -ENOSYS;
-}
-
-static inline int irq_to_gpio(unsigned int irq)
-{
-	return -EINVAL;
-}
-
-#endif /* CONFIG_GPIOLIB */
-
-#endif /* ASM_X86__GPIO_H */
diff --git a/include/asm-x86/hardirq.h b/include/asm-x86/hardirq.h
deleted file mode 100644
index 000787df66e6..000000000000
--- a/include/asm-x86/hardirq.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifdef CONFIG_X86_32
-# include "hardirq_32.h"
-#else
-# include "hardirq_64.h"
-#endif
-
-extern u64 arch_irq_stat_cpu(unsigned int cpu);
-#define arch_irq_stat_cpu	arch_irq_stat_cpu
-
-extern u64 arch_irq_stat(void);
-#define arch_irq_stat		arch_irq_stat
diff --git a/include/asm-x86/hardirq_32.h b/include/asm-x86/hardirq_32.h
deleted file mode 100644
index 700fe230d919..000000000000
--- a/include/asm-x86/hardirq_32.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef ASM_X86__HARDIRQ_32_H
-#define ASM_X86__HARDIRQ_32_H
-
-#include <linux/threads.h>
-#include <linux/irq.h>
-
-typedef struct {
-	unsigned int __softirq_pending;
-	unsigned long idle_timestamp;
-	unsigned int __nmi_count;	/* arch dependent */
-	unsigned int apic_timer_irqs;	/* arch dependent */
-	unsigned int irq0_irqs;
-	unsigned int irq_resched_count;
-	unsigned int irq_call_count;
-	unsigned int irq_tlb_count;
-	unsigned int irq_thermal_count;
-	unsigned int irq_spurious_count;
-} ____cacheline_aligned irq_cpustat_t;
-
-DECLARE_PER_CPU(irq_cpustat_t, irq_stat);
-
-#define __ARCH_IRQ_STAT
-#define __IRQ_STAT(cpu, member) (per_cpu(irq_stat, cpu).member)
-
-void ack_bad_irq(unsigned int irq);
-#include <linux/irq_cpustat.h>
-
-#endif /* ASM_X86__HARDIRQ_32_H */
diff --git a/include/asm-x86/hardirq_64.h b/include/asm-x86/hardirq_64.h
deleted file mode 100644
index f8bd2919a8ce..000000000000
--- a/include/asm-x86/hardirq_64.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef ASM_X86__HARDIRQ_64_H
-#define ASM_X86__HARDIRQ_64_H
-
-#include <linux/threads.h>
-#include <linux/irq.h>
-#include <asm/pda.h>
-#include <asm/apic.h>
-
-/* We can have at most NR_VECTORS irqs routed to a cpu at a time */
-#define MAX_HARDIRQS_PER_CPU NR_VECTORS
-
-#define __ARCH_IRQ_STAT 1
-
-#define local_softirq_pending() read_pda(__softirq_pending)
-
-#define __ARCH_SET_SOFTIRQ_PENDING 1
-
-#define set_softirq_pending(x) write_pda(__softirq_pending, (x))
-#define or_softirq_pending(x)  or_pda(__softirq_pending, (x))
-
-extern void ack_bad_irq(unsigned int irq);
-
-#endif /* ASM_X86__HARDIRQ_64_H */
diff --git a/include/asm-x86/highmem.h b/include/asm-x86/highmem.h
deleted file mode 100644
index bc3f6a280316..000000000000
--- a/include/asm-x86/highmem.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * highmem.h: virtual kernel memory mappings for high memory
- *
- * Used in CONFIG_HIGHMEM systems for memory pages which
- * are not addressable by direct kernel virtual addresses.
- *
- * Copyright (C) 1999 Gerhard Wichert, Siemens AG
- *		      Gerhard.Wichert@pdb.siemens.de
- *
- *
- * Redesigned the x86 32-bit VM architecture to deal with
- * up to 16 Terabyte physical memory. With current x86 CPUs
- * we now support up to 64 Gigabytes physical RAM.
- *
- * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
- */
-
-#ifndef ASM_X86__HIGHMEM_H
-#define ASM_X86__HIGHMEM_H
-
-#ifdef __KERNEL__
-
-#include <linux/interrupt.h>
-#include <linux/threads.h>
-#include <asm/kmap_types.h>
-#include <asm/tlbflush.h>
-#include <asm/paravirt.h>
-
-/* declarations for highmem.c */
-extern unsigned long highstart_pfn, highend_pfn;
-
-extern pte_t *kmap_pte;
-extern pgprot_t kmap_prot;
-extern pte_t *pkmap_page_table;
-
-/*
- * Right now we initialize only a single pte table. It can be extended
- * easily, subsequent pte tables have to be allocated in one physical
- * chunk of RAM.
- */
-/*
- * Ordering is:
- *
- * FIXADDR_TOP
- * 			fixed_addresses
- * FIXADDR_START
- * 			temp fixed addresses
- * FIXADDR_BOOT_START
- * 			Persistent kmap area
- * PKMAP_BASE
- * VMALLOC_END
- * 			Vmalloc area
- * VMALLOC_START
- * high_memory
- */
-#define LAST_PKMAP_MASK (LAST_PKMAP-1)
-#define PKMAP_NR(virt)  ((virt-PKMAP_BASE) >> PAGE_SHIFT)
-#define PKMAP_ADDR(nr)  (PKMAP_BASE + ((nr) << PAGE_SHIFT))
-
-extern void *kmap_high(struct page *page);
-extern void kunmap_high(struct page *page);
-
-void *kmap(struct page *page);
-void kunmap(struct page *page);
-void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot);
-void *kmap_atomic(struct page *page, enum km_type type);
-void kunmap_atomic(void *kvaddr, enum km_type type);
-void *kmap_atomic_pfn(unsigned long pfn, enum km_type type);
-struct page *kmap_atomic_to_page(void *ptr);
-
-#ifndef CONFIG_PARAVIRT
-#define kmap_atomic_pte(page, type)	kmap_atomic(page, type)
-#endif
-
-#define flush_cache_kmaps()	do { } while (0)
-
-extern void add_highpages_with_active_regions(int nid, unsigned long start_pfn,
-					unsigned long end_pfn);
-
-#endif /* __KERNEL__ */
-
-#endif /* ASM_X86__HIGHMEM_H */
diff --git a/include/asm-x86/hpet.h b/include/asm-x86/hpet.h
deleted file mode 100644
index cbbbb6d4dd32..000000000000
--- a/include/asm-x86/hpet.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef ASM_X86__HPET_H
-#define ASM_X86__HPET_H
-
-#ifdef CONFIG_HPET_TIMER
-
-#define HPET_MMAP_SIZE		1024
-
-#define HPET_ID			0x000
-#define HPET_PERIOD		0x004
-#define HPET_CFG		0x010
-#define HPET_STATUS		0x020
-#define HPET_COUNTER		0x0f0
-#define HPET_T0_CFG		0x100
-#define HPET_T0_CMP		0x108
-#define HPET_T0_ROUTE		0x110
-#define HPET_T1_CFG		0x120
-#define HPET_T1_CMP		0x128
-#define HPET_T1_ROUTE		0x130
-#define HPET_T2_CFG		0x140
-#define HPET_T2_CMP		0x148
-#define HPET_T2_ROUTE		0x150
-
-#define HPET_ID_REV		0x000000ff
-#define HPET_ID_NUMBER		0x00001f00
-#define HPET_ID_64BIT		0x00002000
-#define HPET_ID_LEGSUP		0x00008000
-#define HPET_ID_VENDOR		0xffff0000
-#define	HPET_ID_NUMBER_SHIFT	8
-#define HPET_ID_VENDOR_SHIFT	16
-
-#define HPET_ID_VENDOR_8086	0x8086
-
-#define HPET_CFG_ENABLE		0x001
-#define HPET_CFG_LEGACY		0x002
-#define	HPET_LEGACY_8254	2
-#define	HPET_LEGACY_RTC		8
-
-#define HPET_TN_LEVEL		0x0002
-#define HPET_TN_ENABLE		0x0004
-#define HPET_TN_PERIODIC	0x0008
-#define HPET_TN_PERIODIC_CAP	0x0010
-#define HPET_TN_64BIT_CAP	0x0020
-#define HPET_TN_SETVAL		0x0040
-#define HPET_TN_32BIT		0x0100
-#define HPET_TN_ROUTE		0x3e00
-#define HPET_TN_FSB		0x4000
-#define HPET_TN_FSB_CAP		0x8000
-#define HPET_TN_ROUTE_SHIFT	9
-
-/* Max HPET Period is 10^8 femto sec as in HPET spec */
-#define HPET_MAX_PERIOD		100000000UL
-/*
- * Min HPET period is 10^5 femto sec just for safety. If it is less than this,
- * then 32 bit HPET counter wrapsaround in less than 0.5 sec.
- */
-#define HPET_MIN_PERIOD		100000UL
-
-/* hpet memory map physical address */
-extern unsigned long hpet_address;
-extern unsigned long force_hpet_address;
-extern int hpet_force_user;
-extern int is_hpet_enabled(void);
-extern int hpet_enable(void);
-extern void hpet_disable(void);
-extern unsigned long hpet_readl(unsigned long a);
-extern void force_hpet_resume(void);
-
-#ifdef CONFIG_HPET_EMULATE_RTC
-
-#include <linux/interrupt.h>
-
-typedef irqreturn_t (*rtc_irq_handler)(int interrupt, void *cookie);
-extern int hpet_mask_rtc_irq_bit(unsigned long bit_mask);
-extern int hpet_set_rtc_irq_bit(unsigned long bit_mask);
-extern int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
-			       unsigned char sec);
-extern int hpet_set_periodic_freq(unsigned long freq);
-extern int hpet_rtc_dropped_irq(void);
-extern int hpet_rtc_timer_init(void);
-extern irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id);
-extern int hpet_register_irq_handler(rtc_irq_handler handler);
-extern void hpet_unregister_irq_handler(rtc_irq_handler handler);
-
-#endif /* CONFIG_HPET_EMULATE_RTC */
-
-#else /* CONFIG_HPET_TIMER */
-
-static inline int hpet_enable(void) { return 0; }
-static inline int is_hpet_enabled(void) { return 0; }
-#define hpet_readl(a) 0
-
-#endif
-#endif /* ASM_X86__HPET_H */
diff --git a/include/asm-x86/hugetlb.h b/include/asm-x86/hugetlb.h
deleted file mode 100644
index 0b7ec5dc0884..000000000000
--- a/include/asm-x86/hugetlb.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef ASM_X86__HUGETLB_H
-#define ASM_X86__HUGETLB_H
-
-#include <asm/page.h>
-
-
-static inline int is_hugepage_only_range(struct mm_struct *mm,
-					 unsigned long addr,
-					 unsigned long len) {
-	return 0;
-}
-
-/*
- * If the arch doesn't supply something else, assume that hugepage
- * size aligned regions are ok without further preparation.
- */
-static inline int prepare_hugepage_range(struct file *file,
-			unsigned long addr, unsigned long len)
-{
-	struct hstate *h = hstate_file(file);
-	if (len & ~huge_page_mask(h))
-		return -EINVAL;
-	if (addr & ~huge_page_mask(h))
-		return -EINVAL;
-	return 0;
-}
-
-static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm) {
-}
-
-static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
-					  unsigned long addr, unsigned long end,
-					  unsigned long floor,
-					  unsigned long ceiling)
-{
-	free_pgd_range(tlb, addr, end, floor, ceiling);
-}
-
-static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
-				   pte_t *ptep, pte_t pte)
-{
-	set_pte_at(mm, addr, ptep, pte);
-}
-
-static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
-					    unsigned long addr, pte_t *ptep)
-{
-	return ptep_get_and_clear(mm, addr, ptep);
-}
-
-static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
-					 unsigned long addr, pte_t *ptep)
-{
-}
-
-static inline int huge_pte_none(pte_t pte)
-{
-	return pte_none(pte);
-}
-
-static inline pte_t huge_pte_wrprotect(pte_t pte)
-{
-	return pte_wrprotect(pte);
-}
-
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
-					   unsigned long addr, pte_t *ptep)
-{
-	ptep_set_wrprotect(mm, addr, ptep);
-}
-
-static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
-					     unsigned long addr, pte_t *ptep,
-					     pte_t pte, int dirty)
-{
-	return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
-}
-
-static inline pte_t huge_ptep_get(pte_t *ptep)
-{
-	return *ptep;
-}
-
-static inline int arch_prepare_hugepage(struct page *page)
-{
-	return 0;
-}
-
-static inline void arch_release_hugepage(struct page *page)
-{
-}
-
-#endif /* ASM_X86__HUGETLB_H */
diff --git a/include/asm-x86/hw_irq.h b/include/asm-x86/hw_irq.h
deleted file mode 100644
index 50f6e0316b50..000000000000
--- a/include/asm-x86/hw_irq.h
+++ /dev/null
@@ -1,136 +0,0 @@
-#ifndef ASM_X86__HW_IRQ_H
-#define ASM_X86__HW_IRQ_H
-
-/*
- * (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar
- *
- * moved some of the old arch/i386/kernel/irq.h to here. VY
- *
- * IRQ/IPI changes taken from work by Thomas Radke
- * <tomsoft@informatik.tu-chemnitz.de>
- *
- * hacked by Andi Kleen for x86-64.
- * unified by tglx
- */
-
-#include <asm/irq_vectors.h>
-
-#ifndef __ASSEMBLY__
-
-#include <linux/percpu.h>
-#include <linux/profile.h>
-#include <linux/smp.h>
-
-#include <asm/atomic.h>
-#include <asm/irq.h>
-#include <asm/sections.h>
-
-#define platform_legacy_irq(irq)	((irq) < 16)
-
-/* Interrupt handlers registered during init_IRQ */
-extern void apic_timer_interrupt(void);
-extern void error_interrupt(void);
-extern void spurious_interrupt(void);
-extern void thermal_interrupt(void);
-extern void reschedule_interrupt(void);
-
-extern void invalidate_interrupt(void);
-extern void invalidate_interrupt0(void);
-extern void invalidate_interrupt1(void);
-extern void invalidate_interrupt2(void);
-extern void invalidate_interrupt3(void);
-extern void invalidate_interrupt4(void);
-extern void invalidate_interrupt5(void);
-extern void invalidate_interrupt6(void);
-extern void invalidate_interrupt7(void);
-
-extern void irq_move_cleanup_interrupt(void);
-extern void threshold_interrupt(void);
-
-extern void call_function_interrupt(void);
-extern void call_function_single_interrupt(void);
-
-/* PIC specific functions */
-extern void disable_8259A_irq(unsigned int irq);
-extern void enable_8259A_irq(unsigned int irq);
-extern int i8259A_irq_pending(unsigned int irq);
-extern void make_8259A_irq(unsigned int irq);
-extern void init_8259A(int aeoi);
-
-/* IOAPIC */
-#define IO_APIC_IRQ(x) (((x) >= 16) || ((1<<(x)) & io_apic_irqs))
-extern unsigned long io_apic_irqs;
-
-extern void init_VISWS_APIC_irqs(void);
-extern void setup_IO_APIC(void);
-extern void disable_IO_APIC(void);
-extern int IO_APIC_get_PCI_irq_vector(int bus, int slot, int fn);
-extern void setup_ioapic_dest(void);
-
-#ifdef CONFIG_X86_64
-extern void enable_IO_APIC(void);
-#endif
-
-/* IPI functions */
-#ifdef CONFIG_X86_32
-extern void send_IPI_self(int vector);
-#endif
-extern void send_IPI(int dest, int vector);
-
-/* Statistics */
-extern atomic_t irq_err_count;
-extern atomic_t irq_mis_count;
-
-/* EISA */
-extern void eisa_set_level_irq(unsigned int irq);
-
-/* Voyager functions */
-extern asmlinkage void vic_cpi_interrupt(void);
-extern asmlinkage void vic_sys_interrupt(void);
-extern asmlinkage void vic_cmn_interrupt(void);
-extern asmlinkage void qic_timer_interrupt(void);
-extern asmlinkage void qic_invalidate_interrupt(void);
-extern asmlinkage void qic_reschedule_interrupt(void);
-extern asmlinkage void qic_enable_irq_interrupt(void);
-extern asmlinkage void qic_call_function_interrupt(void);
-
-/* SMP */
-extern void smp_apic_timer_interrupt(struct pt_regs *);
-#ifdef CONFIG_X86_32
-extern void smp_spurious_interrupt(struct pt_regs *);
-extern void smp_error_interrupt(struct pt_regs *);
-#else
-extern asmlinkage void smp_spurious_interrupt(void);
-extern asmlinkage void smp_error_interrupt(void);
-#endif
-#ifdef CONFIG_X86_SMP
-extern void smp_reschedule_interrupt(struct pt_regs *);
-extern void smp_call_function_interrupt(struct pt_regs *);
-extern void smp_call_function_single_interrupt(struct pt_regs *);
-#ifdef CONFIG_X86_32
-extern void smp_invalidate_interrupt(struct pt_regs *);
-#else
-extern asmlinkage void smp_invalidate_interrupt(struct pt_regs *);
-#endif
-#endif
-
-#ifdef CONFIG_X86_32
-extern void (*const interrupt[NR_IRQS])(void);
-#else
-typedef int vector_irq_t[NR_VECTORS];
-DECLARE_PER_CPU(vector_irq_t, vector_irq);
-#endif
-
-#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_X86_64)
-extern void lock_vector_lock(void);
-extern void unlock_vector_lock(void);
-extern void __setup_vector_irq(int cpu);
-#else
-static inline void lock_vector_lock(void) {}
-static inline void unlock_vector_lock(void) {}
-static inline void __setup_vector_irq(int cpu) {}
-#endif
-
-#endif /* !ASSEMBLY_ */
-
-#endif /* ASM_X86__HW_IRQ_H */
diff --git a/include/asm-x86/hypertransport.h b/include/asm-x86/hypertransport.h
deleted file mode 100644
index cc011a3bc1c2..000000000000
--- a/include/asm-x86/hypertransport.h
+++ /dev/null
@@ -1,45 +0,0 @@
-#ifndef ASM_X86__HYPERTRANSPORT_H
-#define ASM_X86__HYPERTRANSPORT_H
-
-/*
- * Constants for x86 Hypertransport Interrupts.
- */
-
-#define HT_IRQ_LOW_BASE			0xf8000000
-
-#define HT_IRQ_LOW_VECTOR_SHIFT		16
-#define HT_IRQ_LOW_VECTOR_MASK		0x00ff0000
-#define HT_IRQ_LOW_VECTOR(v)						\
-	(((v) << HT_IRQ_LOW_VECTOR_SHIFT) & HT_IRQ_LOW_VECTOR_MASK)
-
-#define HT_IRQ_LOW_DEST_ID_SHIFT	8
-#define HT_IRQ_LOW_DEST_ID_MASK		0x0000ff00
-#define HT_IRQ_LOW_DEST_ID(v)						\
-	(((v) << HT_IRQ_LOW_DEST_ID_SHIFT) & HT_IRQ_LOW_DEST_ID_MASK)
-
-#define HT_IRQ_LOW_DM_PHYSICAL		0x0000000
-#define HT_IRQ_LOW_DM_LOGICAL		0x0000040
-
-#define HT_IRQ_LOW_RQEOI_EDGE		0x0000000
-#define HT_IRQ_LOW_RQEOI_LEVEL		0x0000020
-
-
-#define HT_IRQ_LOW_MT_FIXED		0x0000000
-#define HT_IRQ_LOW_MT_ARBITRATED	0x0000004
-#define HT_IRQ_LOW_MT_SMI		0x0000008
-#define HT_IRQ_LOW_MT_NMI		0x000000c
-#define HT_IRQ_LOW_MT_INIT		0x0000010
-#define HT_IRQ_LOW_MT_STARTUP		0x0000014
-#define HT_IRQ_LOW_MT_EXTINT		0x0000018
-#define HT_IRQ_LOW_MT_LINT1		0x000008c
-#define HT_IRQ_LOW_MT_LINT0		0x0000098
-
-#define HT_IRQ_LOW_IRQ_MASKED		0x0000001
-
-
-#define HT_IRQ_HIGH_DEST_ID_SHIFT	0
-#define HT_IRQ_HIGH_DEST_ID_MASK	0x00ffffff
-#define HT_IRQ_HIGH_DEST_ID(v)						\
-	((((v) >> 8) << HT_IRQ_HIGH_DEST_ID_SHIFT) & HT_IRQ_HIGH_DEST_ID_MASK)
-
-#endif /* ASM_X86__HYPERTRANSPORT_H */
diff --git a/include/asm-x86/i387.h b/include/asm-x86/i387.h
deleted file mode 100644
index 9ba862a4eac0..000000000000
--- a/include/asm-x86/i387.h
+++ /dev/null
@@ -1,400 +0,0 @@
-/*
- * Copyright (C) 1994 Linus Torvalds
- *
- * Pentium III FXSR, SSE support
- * General FPU state handling cleanups
- *	Gareth Hughes <gareth@valinux.com>, May 2000
- * x86-64 work by Andi Kleen 2002
- */
-
-#ifndef ASM_X86__I387_H
-#define ASM_X86__I387_H
-
-#include <linux/sched.h>
-#include <linux/kernel_stat.h>
-#include <linux/regset.h>
-#include <linux/hardirq.h>
-#include <asm/asm.h>
-#include <asm/processor.h>
-#include <asm/sigcontext.h>
-#include <asm/user.h>
-#include <asm/uaccess.h>
-#include <asm/xsave.h>
-
-extern unsigned int sig_xstate_size;
-extern void fpu_init(void);
-extern void mxcsr_feature_mask_init(void);
-extern int init_fpu(struct task_struct *child);
-extern asmlinkage void math_state_restore(void);
-extern void init_thread_xstate(void);
-extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
-
-extern user_regset_active_fn fpregs_active, xfpregs_active;
-extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
-extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;
-
-extern struct _fpx_sw_bytes fx_sw_reserved;
-#ifdef CONFIG_IA32_EMULATION
-extern unsigned int sig_xstate_ia32_size;
-extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
-struct _fpstate_ia32;
-struct _xstate_ia32;
-extern int save_i387_xstate_ia32(void __user *buf);
-extern int restore_i387_xstate_ia32(void __user *buf);
-#endif
-
-#define X87_FSW_ES (1 << 7)	/* Exception Summary */
-
-#ifdef CONFIG_X86_64
-
-/* Ignore delayed exceptions from user space */
-static inline void tolerant_fwait(void)
-{
-	asm volatile("1: fwait\n"
-		     "2:\n"
-		     _ASM_EXTABLE(1b, 2b));
-}
-
-static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
-{
-	int err;
-
-	asm volatile("1:  rex64/fxrstor (%[fx])\n\t"
-		     "2:\n"
-		     ".section .fixup,\"ax\"\n"
-		     "3:  movl $-1,%[err]\n"
-		     "    jmp  2b\n"
-		     ".previous\n"
-		     _ASM_EXTABLE(1b, 3b)
-		     : [err] "=r" (err)
-#if 0 /* See comment in __save_init_fpu() below. */
-		     : [fx] "r" (fx), "m" (*fx), "0" (0));
-#else
-		     : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
-#endif
-	return err;
-}
-
-static inline int restore_fpu_checking(struct task_struct *tsk)
-{
-	if (task_thread_info(tsk)->status & TS_XSAVE)
-		return xrstor_checking(&tsk->thread.xstate->xsave);
-	else
-		return fxrstor_checking(&tsk->thread.xstate->fxsave);
-}
-
-/* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
-   is pending. Clear the x87 state here by setting it to fixed
-   values. The kernel data segment can be sometimes 0 and sometimes
-   new user value. Both should be ok.
-   Use the PDA as safe address because it should be already in L1. */
-static inline void clear_fpu_state(struct task_struct *tsk)
-{
-	struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
-	struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
-
-	/*
-	 * xsave header may indicate the init state of the FP.
-	 */
-	if ((task_thread_info(tsk)->status & TS_XSAVE) &&
-	    !(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
-		return;
-
-	if (unlikely(fx->swd & X87_FSW_ES))
-		asm volatile("fnclex");
-	alternative_input(ASM_NOP8 ASM_NOP2,
-			  "    emms\n"		/* clear stack tags */
-			  "    fildl %%gs:0",	/* load to clear state */
-			  X86_FEATURE_FXSAVE_LEAK);
-}
-
-static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
-{
-	int err;
-
-	asm volatile("1:  rex64/fxsave (%[fx])\n\t"
-		     "2:\n"
-		     ".section .fixup,\"ax\"\n"
-		     "3:  movl $-1,%[err]\n"
-		     "    jmp  2b\n"
-		     ".previous\n"
-		     _ASM_EXTABLE(1b, 3b)
-		     : [err] "=r" (err), "=m" (*fx)
-#if 0 /* See comment in __fxsave_clear() below. */
-		     : [fx] "r" (fx), "0" (0));
-#else
-		     : [fx] "cdaSDb" (fx), "0" (0));
-#endif
-	if (unlikely(err) &&
-	    __clear_user(fx, sizeof(struct i387_fxsave_struct)))
-		err = -EFAULT;
-	/* No need to clear here because the caller clears USED_MATH */
-	return err;
-}
-
-static inline void fxsave(struct task_struct *tsk)
-{
-	/* Using "rex64; fxsave %0" is broken because, if the memory operand
-	   uses any extended registers for addressing, a second REX prefix
-	   will be generated (to the assembler, rex64 followed by semicolon
-	   is a separate instruction), and hence the 64-bitness is lost. */
-#if 0
-	/* Using "fxsaveq %0" would be the ideal choice, but is only supported
-	   starting with gas 2.16. */
-	__asm__ __volatile__("fxsaveq %0"
-			     : "=m" (tsk->thread.xstate->fxsave));
-#elif 0
-	/* Using, as a workaround, the properly prefixed form below isn't
-	   accepted by any binutils version so far released, complaining that
-	   the same type of prefix is used twice if an extended register is
-	   needed for addressing (fix submitted to mainline 2005-11-21). */
-	__asm__ __volatile__("rex64/fxsave %0"
-			     : "=m" (tsk->thread.xstate->fxsave));
-#else
-	/* This, however, we can work around by forcing the compiler to select
-	   an addressing mode that doesn't require extended registers. */
-	__asm__ __volatile__("rex64/fxsave (%1)"
-			     : "=m" (tsk->thread.xstate->fxsave)
-			     : "cdaSDb" (&tsk->thread.xstate->fxsave));
-#endif
-}
-
-static inline void __save_init_fpu(struct task_struct *tsk)
-{
-	if (task_thread_info(tsk)->status & TS_XSAVE)
-		xsave(tsk);
-	else
-		fxsave(tsk);
-
-	clear_fpu_state(tsk);
-	task_thread_info(tsk)->status &= ~TS_USEDFPU;
-}
-
-#else  /* CONFIG_X86_32 */
-
-extern void finit(void);
-
-static inline void tolerant_fwait(void)
-{
-	asm volatile("fnclex ; fwait");
-}
-
-static inline void restore_fpu(struct task_struct *tsk)
-{
-	if (task_thread_info(tsk)->status & TS_XSAVE) {
-		xrstor_checking(&tsk->thread.xstate->xsave);
-		return;
-	}
-	/*
-	 * The "nop" is needed to make the instructions the same
-	 * length.
-	 */
-	alternative_input(
-		"nop ; frstor %1",
-		"fxrstor %1",
-		X86_FEATURE_FXSR,
-		"m" (tsk->thread.xstate->fxsave));
-}
-
-/* We need a safe address that is cheap to find and that is already
-   in L1 during context switch. The best choices are unfortunately
-   different for UP and SMP */
-#ifdef CONFIG_SMP
-#define safe_address (__per_cpu_offset[0])
-#else
-#define safe_address (kstat_cpu(0).cpustat.user)
-#endif
-
-/*
- * These must be called with preempt disabled
- */
-static inline void __save_init_fpu(struct task_struct *tsk)
-{
-	if (task_thread_info(tsk)->status & TS_XSAVE) {
-		struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
-		struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
-
-		xsave(tsk);
-
-		/*
-		 * xsave header may indicate the init state of the FP.
-		 */
-		if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
-			goto end;
-
-		if (unlikely(fx->swd & X87_FSW_ES))
-			asm volatile("fnclex");
-
-		/*
-		 * we can do a simple return here or be paranoid :)
-		 */
-		goto clear_state;
-	}
-
-	/* Use more nops than strictly needed in case the compiler
-	   varies code */
-	alternative_input(
-		"fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
-		"fxsave %[fx]\n"
-		"bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
-		X86_FEATURE_FXSR,
-		[fx] "m" (tsk->thread.xstate->fxsave),
-		[fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
-clear_state:
-	/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
-	   is pending.  Clear the x87 state here by setting it to fixed
-	   values. safe_address is a random variable that should be in L1 */
-	alternative_input(
-		GENERIC_NOP8 GENERIC_NOP2,
-		"emms\n\t"	  	/* clear stack tags */
-		"fildl %[addr]", 	/* set F?P to defined value */
-		X86_FEATURE_FXSAVE_LEAK,
-		[addr] "m" (safe_address));
-end:
-	task_thread_info(tsk)->status &= ~TS_USEDFPU;
-}
-
-#endif	/* CONFIG_X86_64 */
-
-/*
- * Signal frame handlers...
- */
-extern int save_i387_xstate(void __user *buf);
-extern int restore_i387_xstate(void __user *buf);
-
-static inline void __unlazy_fpu(struct task_struct *tsk)
-{
-	if (task_thread_info(tsk)->status & TS_USEDFPU) {
-		__save_init_fpu(tsk);
-		stts();
-	} else
-		tsk->fpu_counter = 0;
-}
-
-static inline void __clear_fpu(struct task_struct *tsk)
-{
-	if (task_thread_info(tsk)->status & TS_USEDFPU) {
-		tolerant_fwait();
-		task_thread_info(tsk)->status &= ~TS_USEDFPU;
-		stts();
-	}
-}
-
-static inline void kernel_fpu_begin(void)
-{
-	struct thread_info *me = current_thread_info();
-	preempt_disable();
-	if (me->status & TS_USEDFPU)
-		__save_init_fpu(me->task);
-	else
-		clts();
-}
-
-static inline void kernel_fpu_end(void)
-{
-	stts();
-	preempt_enable();
-}
-
-/*
- * Some instructions like VIA's padlock instructions generate a spurious
- * DNA fault but don't modify SSE registers. And these instructions
- * get used from interrupt context aswell. To prevent these kernel instructions
- * in interrupt context interact wrongly with other user/kernel fpu usage, we
- * should use them only in the context of irq_ts_save/restore()
- */
-static inline int irq_ts_save(void)
-{
-	/*
-	 * If we are in process context, we are ok to take a spurious DNA fault.
-	 * Otherwise, doing clts() in process context require pre-emption to
-	 * be disabled or some heavy lifting like kernel_fpu_begin()
-	 */
-	if (!in_interrupt())
-		return 0;
-
-	if (read_cr0() & X86_CR0_TS) {
-		clts();
-		return 1;
-	}
-
-	return 0;
-}
-
-static inline void irq_ts_restore(int TS_state)
-{
-	if (TS_state)
-		stts();
-}
-
-#ifdef CONFIG_X86_64
-
-static inline void save_init_fpu(struct task_struct *tsk)
-{
-	__save_init_fpu(tsk);
-	stts();
-}
-
-#define unlazy_fpu	__unlazy_fpu
-#define clear_fpu	__clear_fpu
-
-#else  /* CONFIG_X86_32 */
-
-/*
- * These disable preemption on their own and are safe
- */
-static inline void save_init_fpu(struct task_struct *tsk)
-{
-	preempt_disable();
-	__save_init_fpu(tsk);
-	stts();
-	preempt_enable();
-}
-
-static inline void unlazy_fpu(struct task_struct *tsk)
-{
-	preempt_disable();
-	__unlazy_fpu(tsk);
-	preempt_enable();
-}
-
-static inline void clear_fpu(struct task_struct *tsk)
-{
-	preempt_disable();
-	__clear_fpu(tsk);
-	preempt_enable();
-}
-
-#endif	/* CONFIG_X86_64 */
-
-/*
- * i387 state interaction
- */
-static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
-{
-	if (cpu_has_fxsr) {
-		return tsk->thread.xstate->fxsave.cwd;
-	} else {
-		return (unsigned short)tsk->thread.xstate->fsave.cwd;
-	}
-}
-
-static inline unsigned short get_fpu_swd(struct task_struct *tsk)
-{
-	if (cpu_has_fxsr) {
-		return tsk->thread.xstate->fxsave.swd;
-	} else {
-		return (unsigned short)tsk->thread.xstate->fsave.swd;
-	}
-}
-
-static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
-{
-	if (cpu_has_xmm) {
-		return tsk->thread.xstate->fxsave.mxcsr;
-	} else {
-		return MXCSR_DEFAULT;
-	}
-}
-
-#endif /* ASM_X86__I387_H */
diff --git a/include/asm-x86/i8253.h b/include/asm-x86/i8253.h
deleted file mode 100644
index 15a5b530044e..000000000000
--- a/include/asm-x86/i8253.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef ASM_X86__I8253_H
-#define ASM_X86__I8253_H
-
-/* i8253A PIT registers */
-#define PIT_MODE		0x43
-#define PIT_CH0			0x40
-#define PIT_CH2			0x42
-
-extern spinlock_t i8253_lock;
-
-extern struct clock_event_device *global_clock_event;
-
-extern void setup_pit_timer(void);
-
-#define inb_pit		inb_p
-#define outb_pit	outb_p
-
-#endif /* ASM_X86__I8253_H */
diff --git a/include/asm-x86/i8259.h b/include/asm-x86/i8259.h
deleted file mode 100644
index 23c1b3baaecd..000000000000
--- a/include/asm-x86/i8259.h
+++ /dev/null
@@ -1,63 +0,0 @@
-#ifndef ASM_X86__I8259_H
-#define ASM_X86__I8259_H
-
-#include <linux/delay.h>
-
-extern unsigned int cached_irq_mask;
-
-#define __byte(x, y)		(((unsigned char *)&(y))[x])
-#define cached_master_mask	(__byte(0, cached_irq_mask))
-#define cached_slave_mask	(__byte(1, cached_irq_mask))
-
-/* i8259A PIC registers */
-#define PIC_MASTER_CMD		0x20
-#define PIC_MASTER_IMR		0x21
-#define PIC_MASTER_ISR		PIC_MASTER_CMD
-#define PIC_MASTER_POLL		PIC_MASTER_ISR
-#define PIC_MASTER_OCW3		PIC_MASTER_ISR
-#define PIC_SLAVE_CMD		0xa0
-#define PIC_SLAVE_IMR		0xa1
-
-/* i8259A PIC related value */
-#define PIC_CASCADE_IR		2
-#define MASTER_ICW4_DEFAULT	0x01
-#define SLAVE_ICW4_DEFAULT	0x01
-#define PIC_ICW4_AEOI		2
-
-extern spinlock_t i8259A_lock;
-
-extern void init_8259A(int auto_eoi);
-extern void enable_8259A_irq(unsigned int irq);
-extern void disable_8259A_irq(unsigned int irq);
-extern unsigned int startup_8259A_irq(unsigned int irq);
-
-/* the PIC may need a careful delay on some platforms, hence specific calls */
-static inline unsigned char inb_pic(unsigned int port)
-{
-	unsigned char value = inb(port);
-
-	/*
-	 * delay for some accesses to PIC on motherboard or in chipset
-	 * must be at least one microsecond, so be safe here:
-	 */
-	udelay(2);
-
-	return value;
-}
-
-static inline void outb_pic(unsigned char value, unsigned int port)
-{
-	outb(value, port);
-	/*
-	 * delay for some accesses to PIC on motherboard or in chipset
-	 * must be at least one microsecond, so be safe here:
-	 */
-	udelay(2);
-}
-
-extern struct irq_chip i8259A_chip;
-
-extern void mask_8259A(void);
-extern void unmask_8259A(void);
-
-#endif /* ASM_X86__I8259_H */
diff --git a/include/asm-x86/ia32.h b/include/asm-x86/ia32.h
deleted file mode 100644
index f932f7ad51dd..000000000000
--- a/include/asm-x86/ia32.h
+++ /dev/null
@@ -1,170 +0,0 @@
-#ifndef ASM_X86__IA32_H
-#define ASM_X86__IA32_H
-
-
-#ifdef CONFIG_IA32_EMULATION
-
-#include <linux/compat.h>
-
-/*
- * 32 bit structures for IA32 support.
- */
-
-#include <asm/sigcontext32.h>
-
-/* signal.h */
-struct sigaction32 {
-	unsigned int  sa_handler;	/* Really a pointer, but need to deal
-					   with 32 bits */
-	unsigned int sa_flags;
-	unsigned int sa_restorer;	/* Another 32 bit pointer */
-	compat_sigset_t sa_mask;	/* A 32 bit mask */
-};
-
-struct old_sigaction32 {
-	unsigned int  sa_handler;	/* Really a pointer, but need to deal
-					   with 32 bits */
-	compat_old_sigset_t sa_mask;	/* A 32 bit mask */
-	unsigned int sa_flags;
-	unsigned int sa_restorer;	/* Another 32 bit pointer */
-};
-
-typedef struct sigaltstack_ia32 {
-	unsigned int	ss_sp;
-	int		ss_flags;
-	unsigned int	ss_size;
-} stack_ia32_t;
-
-struct ucontext_ia32 {
-	unsigned int	  uc_flags;
-	unsigned int 	  uc_link;
-	stack_ia32_t	  uc_stack;
-	struct sigcontext_ia32 uc_mcontext;
-	compat_sigset_t	  uc_sigmask;	/* mask last for extensibility */
-};
-
-/* This matches struct stat64 in glibc2.2, hence the absolutely
- * insane amounts of padding around dev_t's.
- */
-struct stat64 {
-	unsigned long long	st_dev;
-	unsigned char		__pad0[4];
-
-#define STAT64_HAS_BROKEN_ST_INO	1
-	unsigned int		__st_ino;
-
-	unsigned int		st_mode;
-	unsigned int		st_nlink;
-
-	unsigned int		st_uid;
-	unsigned int		st_gid;
-
-	unsigned long long	st_rdev;
-	unsigned char		__pad3[4];
-
-	long long		st_size;
-	unsigned int		st_blksize;
-
-	long long		st_blocks;/* Number 512-byte blocks allocated */
-
-	unsigned 		st_atime;
-	unsigned 		st_atime_nsec;
-	unsigned 		st_mtime;
-	unsigned 		st_mtime_nsec;
-	unsigned 		st_ctime;
-	unsigned 		st_ctime_nsec;
-
-	unsigned long long	st_ino;
-} __attribute__((packed));
-
-typedef struct compat_siginfo {
-	int si_signo;
-	int si_errno;
-	int si_code;
-
-	union {
-		int _pad[((128 / sizeof(int)) - 3)];
-
-		/* kill() */
-		struct {
-			unsigned int _pid;	/* sender's pid */
-			unsigned int _uid;	/* sender's uid */
-		} _kill;
-
-		/* POSIX.1b timers */
-		struct {
-			compat_timer_t _tid;	/* timer id */
-			int _overrun;		/* overrun count */
-			compat_sigval_t _sigval;	/* same as below */
-			int _sys_private;	/* not to be passed to user */
-			int _overrun_incr;	/* amount to add to overrun */
-		} _timer;
-
-		/* POSIX.1b signals */
-		struct {
-			unsigned int _pid;	/* sender's pid */
-			unsigned int _uid;	/* sender's uid */
-			compat_sigval_t _sigval;
-		} _rt;
-
-		/* SIGCHLD */
-		struct {
-			unsigned int _pid;	/* which child */
-			unsigned int _uid;	/* sender's uid */
-			int _status;		/* exit code */
-			compat_clock_t _utime;
-			compat_clock_t _stime;
-		} _sigchld;
-
-		/* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
-		struct {
-			unsigned int _addr;	/* faulting insn/memory ref. */
-		} _sigfault;
-
-		/* SIGPOLL */
-		struct {
-			int _band;	/* POLL_IN, POLL_OUT, POLL_MSG */
-			int _fd;
-		} _sigpoll;
-	} _sifields;
-} compat_siginfo_t;
-
-struct sigframe32 {
-	u32 pretcode;
-	int sig;
-	struct sigcontext_ia32 sc;
-	struct _fpstate_ia32 fpstate;
-	unsigned int extramask[_COMPAT_NSIG_WORDS-1];
-};
-
-struct rt_sigframe32 {
-	u32 pretcode;
-	int sig;
-	u32 pinfo;
-	u32 puc;
-	compat_siginfo_t info;
-	struct ucontext_ia32 uc;
-	struct _fpstate_ia32 fpstate;
-};
-
-struct ustat32 {
-	__u32			f_tfree;
-	compat_ino_t		f_tinode;
-	char			f_fname[6];
-	char			f_fpack[6];
-};
-
-#define IA32_STACK_TOP IA32_PAGE_OFFSET
-
-#ifdef __KERNEL__
-struct linux_binprm;
-extern int ia32_setup_arg_pages(struct linux_binprm *bprm,
-				unsigned long stack_top, int exec_stack);
-struct mm_struct;
-extern void ia32_pick_mmap_layout(struct mm_struct *mm);
-
-#endif
-
-#endif /* !CONFIG_IA32_SUPPORT */
-
-#endif /* ASM_X86__IA32_H */
diff --git a/include/asm-x86/ia32_unistd.h b/include/asm-x86/ia32_unistd.h
deleted file mode 100644
index dbd887d8a5a5..000000000000
--- a/include/asm-x86/ia32_unistd.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef ASM_X86__IA32_UNISTD_H
-#define ASM_X86__IA32_UNISTD_H
-
-/*
- * This file contains the system call numbers of the ia32 port,
- * this is for the kernel only.
- * Only add syscalls here where some part of the kernel needs to know
- * the number. This should be otherwise in sync with asm-x86/unistd_32.h. -AK
- */
-
-#define __NR_ia32_restart_syscall 0
-#define __NR_ia32_exit		  1
-#define __NR_ia32_read		  3
-#define __NR_ia32_write		  4
-#define __NR_ia32_sigreturn	119
-#define __NR_ia32_rt_sigreturn	173
-
-#endif /* ASM_X86__IA32_UNISTD_H */
diff --git a/include/asm-x86/idle.h b/include/asm-x86/idle.h
deleted file mode 100644
index baa3f783d27d..000000000000
--- a/include/asm-x86/idle.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef ASM_X86__IDLE_H
-#define ASM_X86__IDLE_H
-
-#define IDLE_START 1
-#define IDLE_END 2
-
-struct notifier_block;
-void idle_notifier_register(struct notifier_block *n);
-
-void enter_idle(void);
-void exit_idle(void);
-
-void c1e_remove_cpu(int cpu);
-
-#endif /* ASM_X86__IDLE_H */
diff --git a/include/asm-x86/intel_arch_perfmon.h b/include/asm-x86/intel_arch_perfmon.h
deleted file mode 100644
index 07c03c6c9a16..000000000000
--- a/include/asm-x86/intel_arch_perfmon.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef ASM_X86__INTEL_ARCH_PERFMON_H
-#define ASM_X86__INTEL_ARCH_PERFMON_H
-
-#define MSR_ARCH_PERFMON_PERFCTR0		0xc1
-#define MSR_ARCH_PERFMON_PERFCTR1		0xc2
-
-#define MSR_ARCH_PERFMON_EVENTSEL0		0x186
-#define MSR_ARCH_PERFMON_EVENTSEL1		0x187
-
-#define ARCH_PERFMON_EVENTSEL0_ENABLE	(1 << 22)
-#define ARCH_PERFMON_EVENTSEL_INT	(1 << 20)
-#define ARCH_PERFMON_EVENTSEL_OS	(1 << 17)
-#define ARCH_PERFMON_EVENTSEL_USR	(1 << 16)
-
-#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL	(0x3c)
-#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK	(0x00 << 8)
-#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX (0)
-#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
-	(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
-
-union cpuid10_eax {
-	struct {
-		unsigned int version_id:8;
-		unsigned int num_counters:8;
-		unsigned int bit_width:8;
-		unsigned int mask_length:8;
-	} split;
-	unsigned int full;
-};
-
-#endif /* ASM_X86__INTEL_ARCH_PERFMON_H */
diff --git a/include/asm-x86/io.h b/include/asm-x86/io.h
deleted file mode 100644
index a233f835e0b5..000000000000
--- a/include/asm-x86/io.h
+++ /dev/null
@@ -1,91 +0,0 @@
-#ifndef ASM_X86__IO_H
-#define ASM_X86__IO_H
-
-#define ARCH_HAS_IOREMAP_WC
-
-#include <linux/compiler.h>
-
-#define build_mmio_read(name, size, type, reg, barrier) \
-static inline type name(const volatile void __iomem *addr) \
-{ type ret; asm volatile("mov" size " %1,%0":reg (ret) \
-:"m" (*(volatile type __force *)addr) barrier); return ret; }
-
-#define build_mmio_write(name, size, type, reg, barrier) \
-static inline void name(type val, volatile void __iomem *addr) \
-{ asm volatile("mov" size " %0,%1": :reg (val), \
-"m" (*(volatile type __force *)addr) barrier); }
-
-build_mmio_read(readb, "b", unsigned char, "=q", :"memory")
-build_mmio_read(readw, "w", unsigned short, "=r", :"memory")
-build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
-
-build_mmio_read(__readb, "b", unsigned char, "=q", )
-build_mmio_read(__readw, "w", unsigned short, "=r", )
-build_mmio_read(__readl, "l", unsigned int, "=r", )
-
-build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
-build_mmio_write(writew, "w", unsigned short, "r", :"memory")
-build_mmio_write(writel, "l", unsigned int, "r", :"memory")
-
-build_mmio_write(__writeb, "b", unsigned char, "q", )
-build_mmio_write(__writew, "w", unsigned short, "r", )
-build_mmio_write(__writel, "l", unsigned int, "r", )
-
-#define readb_relaxed(a) __readb(a)
-#define readw_relaxed(a) __readw(a)
-#define readl_relaxed(a) __readl(a)
-#define __raw_readb __readb
-#define __raw_readw __readw
-#define __raw_readl __readl
-
-#define __raw_writeb __writeb
-#define __raw_writew __writew
-#define __raw_writel __writel
-
-#define mmiowb() barrier()
-
-#ifdef CONFIG_X86_64
-build_mmio_read(readq, "q", unsigned long, "=r", :"memory")
-build_mmio_read(__readq, "q", unsigned long, "=r", )
-build_mmio_write(writeq, "q", unsigned long, "r", :"memory")
-build_mmio_write(__writeq, "q", unsigned long, "r", )
-
-#define readq_relaxed(a) __readq(a)
-#define __raw_readq __readq
-#define __raw_writeq writeq
-
-/* Let people know we have them */
-#define readq readq
-#define writeq writeq
-#endif
-
-extern int iommu_bio_merge;
-
-#ifdef CONFIG_X86_32
-# include "io_32.h"
-#else
-# include "io_64.h"
-#endif
-
-extern void *xlate_dev_mem_ptr(unsigned long phys);
-extern void unxlate_dev_mem_ptr(unsigned long phys, void *addr);
-
-extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
-				unsigned long prot_val);
-extern void __iomem *ioremap_wc(unsigned long offset, unsigned long size);
-
-/*
- * early_ioremap() and early_iounmap() are for temporary early boot-time
- * mappings, before the real ioremap() is functional.
- * A boot-time mapping is currently limited to at most 16 pages.
- */
-extern void early_ioremap_init(void);
-extern void early_ioremap_clear(void);
-extern void early_ioremap_reset(void);
-extern void *early_ioremap(unsigned long offset, unsigned long size);
-extern void *early_memremap(unsigned long offset, unsigned long size);
-extern void early_iounmap(void *addr, unsigned long size);
-extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys);
-
-
-#endif /* ASM_X86__IO_H */
diff --git a/include/asm-x86/io_32.h b/include/asm-x86/io_32.h
deleted file mode 100644
index 4f7d878bda18..000000000000
--- a/include/asm-x86/io_32.h
+++ /dev/null
@@ -1,284 +0,0 @@
-#ifndef ASM_X86__IO_32_H
-#define ASM_X86__IO_32_H
-
-#include <linux/string.h>
-#include <linux/compiler.h>
-
-/*
- * This file contains the definitions for the x86 IO instructions
- * inb/inw/inl/outb/outw/outl and the "string versions" of the same
- * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
- * versions of the single-IO instructions (inb_p/inw_p/..).
- *
- * This file is not meant to be obfuscating: it's just complicated
- * to (a) handle it all in a way that makes gcc able to optimize it
- * as well as possible and (b) trying to avoid writing the same thing
- * over and over again with slight variations and possibly making a
- * mistake somewhere.
- */
-
-/*
- * Thanks to James van Artsdalen for a better timing-fix than
- * the two short jumps: using outb's to a nonexistent port seems
- * to guarantee better timings even on fast machines.
- *
- * On the other hand, I'd like to be sure of a non-existent port:
- * I feel a bit unsafe about using 0x80 (should be safe, though)
- *
- *		Linus
- */
-
- /*
-  *  Bit simplified and optimized by Jan Hubicka
-  *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
-  *
-  *  isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
-  *  isa_read[wl] and isa_write[wl] fixed
-  *  - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
-  */
-
-#define IO_SPACE_LIMIT 0xffff
-
-#define XQUAD_PORTIO_BASE 0xfe400000
-#define XQUAD_PORTIO_QUAD 0x40000  /* 256k per quad. */
-
-#ifdef __KERNEL__
-
-#include <asm-generic/iomap.h>
-
-#include <linux/vmalloc.h>
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)	p
-
-/**
- *	virt_to_phys	-	map virtual addresses to physical
- *	@address: address to remap
- *
- *	The returned physical address is the physical (CPU) mapping for
- *	the memory address given. It is only valid to use this function on
- *	addresses directly mapped or allocated via kmalloc.
- *
- *	This function does not give bus mappings for DMA transfers. In
- *	almost all conceivable cases a device driver should not be using
- *	this function
- */
-
-static inline unsigned long virt_to_phys(volatile void *address)
-{
-	return __pa(address);
-}
-
-/**
- *	phys_to_virt	-	map physical address to virtual
- *	@address: address to remap
- *
- *	The returned virtual address is a current CPU mapping for
- *	the memory address given. It is only valid to use this function on
- *	addresses that have a kernel mapping
- *
- *	This function does not handle bus mappings for DMA transfers. In
- *	almost all conceivable cases a device driver should not be using
- *	this function
- */
-
-static inline void *phys_to_virt(unsigned long address)
-{
-	return __va(address);
-}
-
-/*
- * Change "struct page" to physical address.
- */
-#define page_to_phys(page)    ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
-
-/**
- * ioremap     -   map bus memory into CPU space
- * @offset:    bus address of the memory
- * @size:      size of the resource to map
- *
- * ioremap performs a platform specific sequence of operations to
- * make bus memory CPU accessible via the readb/readw/readl/writeb/
- * writew/writel functions and the other mmio helpers. The returned
- * address is not guaranteed to be usable directly as a virtual
- * address.
- *
- * If the area you are trying to map is a PCI BAR you should have a
- * look at pci_iomap().
- */
-extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size);
-extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size);
-extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size,
-				unsigned long prot_val);
-
-/*
- * The default ioremap() behavior is non-cached:
- */
-static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
-{
-	return ioremap_nocache(offset, size);
-}
-
-extern void iounmap(volatile void __iomem *addr);
-
-/*
- * ISA I/O bus memory addresses are 1:1 with the physical address.
- */
-#define isa_virt_to_bus virt_to_phys
-#define isa_page_to_bus page_to_phys
-#define isa_bus_to_virt phys_to_virt
-
-/*
- * However PCI ones are not necessarily 1:1 and therefore these interfaces
- * are forbidden in portable PCI drivers.
- *
- * Allow them on x86 for legacy drivers, though.
- */
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-
-static inline void
-memset_io(volatile void __iomem *addr, unsigned char val, int count)
-{
-	memset((void __force *)addr, val, count);
-}
-
-static inline void
-memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
-{
-	__memcpy(dst, (const void __force *)src, count);
-}
-
-static inline void
-memcpy_toio(volatile void __iomem *dst, const void *src, int count)
-{
-	__memcpy((void __force *)dst, src, count);
-}
-
-/*
- * ISA space is 'always mapped' on a typical x86 system, no need to
- * explicitly ioremap() it. The fact that the ISA IO space is mapped
- * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
- * are physical addresses. The following constant pointer can be
- * used as the IO-area pointer (it can be iounmapped as well, so the
- * analogy with PCI is quite large):
- */
-#define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
-
-/*
- *	Cache management
- *
- *	This needed for two cases
- *	1. Out of order aware processors
- *	2. Accidentally out of order processors (PPro errata #51)
- */
-
-#if defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE)
-
-static inline void flush_write_buffers(void)
-{
-	asm volatile("lock; addl $0,0(%%esp)": : :"memory");
-}
-
-#else
-
-#define flush_write_buffers() do { } while (0)
-
-#endif
-
-#endif /* __KERNEL__ */
-
-extern void native_io_delay(void);
-
-extern int io_delay_type;
-extern void io_delay_init(void);
-
-#if defined(CONFIG_PARAVIRT)
-#include <asm/paravirt.h>
-#else
-
-static inline void slow_down_io(void)
-{
-	native_io_delay();
-#ifdef REALLY_SLOW_IO
-	native_io_delay();
-	native_io_delay();
-	native_io_delay();
-#endif
-}
-
-#endif
-
-#define __BUILDIO(bwl, bw, type)				\
-static inline void out##bwl(unsigned type value, int port)	\
-{								\
-	out##bwl##_local(value, port);				\
-}								\
-								\
-static inline unsigned type in##bwl(int port)			\
-{								\
-	return in##bwl##_local(port);				\
-}
-
-#define BUILDIO(bwl, bw, type)						\
-static inline void out##bwl##_local(unsigned type value, int port)	\
-{									\
-	asm volatile("out" #bwl " %" #bw "0, %w1"		\
-		     : : "a"(value), "Nd"(port));			\
-}									\
-									\
-static inline unsigned type in##bwl##_local(int port)			\
-{									\
-	unsigned type value;						\
-	asm volatile("in" #bwl " %w1, %" #bw "0"		\
-		     : "=a"(value) : "Nd"(port));			\
-	return value;							\
-}									\
-									\
-static inline void out##bwl##_local_p(unsigned type value, int port)	\
-{									\
-	out##bwl##_local(value, port);					\
-	slow_down_io();							\
-}									\
-									\
-static inline unsigned type in##bwl##_local_p(int port)			\
-{									\
-	unsigned type value = in##bwl##_local(port);			\
-	slow_down_io();							\
-	return value;							\
-}									\
-									\
-__BUILDIO(bwl, bw, type)						\
-									\
-static inline void out##bwl##_p(unsigned type value, int port)		\
-{									\
-	out##bwl(value, port);						\
-	slow_down_io();							\
-}									\
-									\
-static inline unsigned type in##bwl##_p(int port)			\
-{									\
-	unsigned type value = in##bwl(port);				\
-	slow_down_io();							\
-	return value;							\
-}									\
-									\
-static inline void outs##bwl(int port, const void *addr, unsigned long count) \
-{									\
-	asm volatile("rep; outs" #bwl					\
-		     : "+S"(addr), "+c"(count) : "d"(port));		\
-}									\
-									\
-static inline void ins##bwl(int port, void *addr, unsigned long count)	\
-{									\
-	asm volatile("rep; ins" #bwl					\
-		     : "+D"(addr), "+c"(count) : "d"(port));		\
-}
-
-BUILDIO(b, b, char)
-BUILDIO(w, w, short)
-BUILDIO(l, , int)
-
-#endif /* ASM_X86__IO_32_H */
diff --git a/include/asm-x86/io_64.h b/include/asm-x86/io_64.h
deleted file mode 100644
index ee6e086b7dfe..000000000000
--- a/include/asm-x86/io_64.h
+++ /dev/null
@@ -1,244 +0,0 @@
-#ifndef ASM_X86__IO_64_H
-#define ASM_X86__IO_64_H
-
-
-/*
- * This file contains the definitions for the x86 IO instructions
- * inb/inw/inl/outb/outw/outl and the "string versions" of the same
- * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
- * versions of the single-IO instructions (inb_p/inw_p/..).
- *
- * This file is not meant to be obfuscating: it's just complicated
- * to (a) handle it all in a way that makes gcc able to optimize it
- * as well as possible and (b) trying to avoid writing the same thing
- * over and over again with slight variations and possibly making a
- * mistake somewhere.
- */
-
-/*
- * Thanks to James van Artsdalen for a better timing-fix than
- * the two short jumps: using outb's to a nonexistent port seems
- * to guarantee better timings even on fast machines.
- *
- * On the other hand, I'd like to be sure of a non-existent port:
- * I feel a bit unsafe about using 0x80 (should be safe, though)
- *
- *		Linus
- */
-
- /*
-  *  Bit simplified and optimized by Jan Hubicka
-  *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
-  *
-  *  isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
-  *  isa_read[wl] and isa_write[wl] fixed
-  *  - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
-  */
-
-extern void native_io_delay(void);
-
-extern int io_delay_type;
-extern void io_delay_init(void);
-
-#if defined(CONFIG_PARAVIRT)
-#include <asm/paravirt.h>
-#else
-
-static inline void slow_down_io(void)
-{
-	native_io_delay();
-#ifdef REALLY_SLOW_IO
-	native_io_delay();
-	native_io_delay();
-	native_io_delay();
-#endif
-}
-#endif
-
-/*
- * Talk about misusing macros..
- */
-#define __OUT1(s, x)							\
-static inline void out##s(unsigned x value, unsigned short port) {
-
-#define __OUT2(s, s1, s2)				\
-asm volatile ("out" #s " %" s1 "0,%" s2 "1"
-
-#ifndef REALLY_SLOW_IO
-#define REALLY_SLOW_IO
-#define UNSET_REALLY_SLOW_IO
-#endif
-
-#define __OUT(s, s1, x)							\
-	__OUT1(s, x) __OUT2(s, s1, "w") : : "a" (value), "Nd" (port));	\
-	}								\
-	__OUT1(s##_p, x) __OUT2(s, s1, "w") : : "a" (value), "Nd" (port)); \
-	slow_down_io();							\
-}
-
-#define __IN1(s)							\
-static inline RETURN_TYPE in##s(unsigned short port)			\
-{									\
-	RETURN_TYPE _v;
-
-#define __IN2(s, s1, s2)						\
-	asm volatile ("in" #s " %" s2 "1,%" s1 "0"
-
-#define __IN(s, s1, i...)						\
-	__IN1(s) __IN2(s, s1, "w") : "=a" (_v) : "Nd" (port), ##i);	\
-	return _v;							\
-	}								\
-	__IN1(s##_p) __IN2(s, s1, "w") : "=a" (_v) : "Nd" (port), ##i);	\
-	slow_down_io(); \
-	return _v; }
-
-#ifdef UNSET_REALLY_SLOW_IO
-#undef REALLY_SLOW_IO
-#endif
-
-#define __INS(s)							\
-static inline void ins##s(unsigned short port, void *addr,		\
-			  unsigned long count)				\
-{									\
-	asm volatile ("rep ; ins" #s					\
-		      : "=D" (addr), "=c" (count)			\
-		      : "d" (port), "0" (addr), "1" (count));		\
-}
-
-#define __OUTS(s)							\
-static inline void outs##s(unsigned short port, const void *addr,	\
-			   unsigned long count)				\
-{									\
-	asm volatile ("rep ; outs" #s					\
-		      : "=S" (addr), "=c" (count)			\
-		      : "d" (port), "0" (addr), "1" (count));		\
-}
-
-#define RETURN_TYPE unsigned char
-__IN(b, "")
-#undef RETURN_TYPE
-#define RETURN_TYPE unsigned short
-__IN(w, "")
-#undef RETURN_TYPE
-#define RETURN_TYPE unsigned int
-__IN(l, "")
-#undef RETURN_TYPE
-
-__OUT(b, "b", char)
-__OUT(w, "w", short)
-__OUT(l, , int)
-
-__INS(b)
-__INS(w)
-__INS(l)
-
-__OUTS(b)
-__OUTS(w)
-__OUTS(l)
-
-#define IO_SPACE_LIMIT 0xffff
-
-#if defined(__KERNEL__) && defined(__x86_64__)
-
-#include <linux/vmalloc.h>
-
-#ifndef __i386__
-/*
- * Change virtual addresses to physical addresses and vv.
- * These are pretty trivial
- */
-static inline unsigned long virt_to_phys(volatile void *address)
-{
-	return __pa(address);
-}
-
-static inline void *phys_to_virt(unsigned long address)
-{
-	return __va(address);
-}
-#endif
-
-/*
- * Change "struct page" to physical address.
- */
-#define page_to_phys(page)    ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
-
-#include <asm-generic/iomap.h>
-
-/*
- * This one maps high address device memory and turns off caching for that area.
- * it's useful if some control registers are in such an area and write combining
- * or read caching is not desirable:
- */
-extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size);
-extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size);
-extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size,
-				unsigned long prot_val);
-
-/*
- * The default ioremap() behavior is non-cached:
- */
-static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
-{
-	return ioremap_nocache(offset, size);
-}
-
-extern void iounmap(volatile void __iomem *addr);
-
-extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys);
-
-/*
- * ISA I/O bus memory addresses are 1:1 with the physical address.
- */
-#define isa_virt_to_bus virt_to_phys
-#define isa_page_to_bus page_to_phys
-#define isa_bus_to_virt phys_to_virt
-
-/*
- * However PCI ones are not necessarily 1:1 and therefore these interfaces
- * are forbidden in portable PCI drivers.
- *
- * Allow them on x86 for legacy drivers, though.
- */
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-
-void __memcpy_fromio(void *, unsigned long, unsigned);
-void __memcpy_toio(unsigned long, const void *, unsigned);
-
-static inline void memcpy_fromio(void *to, const volatile void __iomem *from,
-				 unsigned len)
-{
-	__memcpy_fromio(to, (unsigned long)from, len);
-}
-
-static inline void memcpy_toio(volatile void __iomem *to, const void *from,
-			       unsigned len)
-{
-	__memcpy_toio((unsigned long)to, from, len);
-}
-
-void memset_io(volatile void __iomem *a, int b, size_t c);
-
-/*
- * ISA space is 'always mapped' on a typical x86 system, no need to
- * explicitly ioremap() it. The fact that the ISA IO space is mapped
- * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
- * are physical addresses. The following constant pointer can be
- * used as the IO-area pointer (it can be iounmapped as well, so the
- * analogy with PCI is quite large):
- */
-#define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
-
-#define flush_write_buffers()
-
-#define BIO_VMERGE_BOUNDARY iommu_bio_merge
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)	p
-
-#endif /* __KERNEL__ */
-
-#endif /* ASM_X86__IO_64_H */
diff --git a/include/asm-x86/io_apic.h b/include/asm-x86/io_apic.h
deleted file mode 100644
index 8ec68a50cf10..000000000000
--- a/include/asm-x86/io_apic.h
+++ /dev/null
@@ -1,212 +0,0 @@
-#ifndef ASM_X86__IO_APIC_H
-#define ASM_X86__IO_APIC_H
-
-#include <linux/types.h>
-#include <asm/mpspec.h>
-#include <asm/apicdef.h>
-
-/*
- * Intel IO-APIC support for SMP and UP systems.
- *
- * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
- */
-
-/* I/O Unit Redirection Table */
-#define IO_APIC_REDIR_VECTOR_MASK	0x000FF
-#define IO_APIC_REDIR_DEST_LOGICAL	0x00800
-#define IO_APIC_REDIR_DEST_PHYSICAL	0x00000
-#define IO_APIC_REDIR_SEND_PENDING	(1 << 12)
-#define IO_APIC_REDIR_REMOTE_IRR	(1 << 14)
-#define IO_APIC_REDIR_LEVEL_TRIGGER	(1 << 15)
-#define IO_APIC_REDIR_MASKED		(1 << 16)
-
-/*
- * The structure of the IO-APIC:
- */
-union IO_APIC_reg_00 {
-	u32	raw;
-	struct {
-		u32	__reserved_2	: 14,
-			LTS		:  1,
-			delivery_type	:  1,
-			__reserved_1	:  8,
-			ID		:  8;
-	} __attribute__ ((packed)) bits;
-};
-
-union IO_APIC_reg_01 {
-	u32	raw;
-	struct {
-		u32	version		:  8,
-			__reserved_2	:  7,
-			PRQ		:  1,
-			entries		:  8,
-			__reserved_1	:  8;
-	} __attribute__ ((packed)) bits;
-};
-
-union IO_APIC_reg_02 {
-	u32	raw;
-	struct {
-		u32	__reserved_2	: 24,
-			arbitration	:  4,
-			__reserved_1	:  4;
-	} __attribute__ ((packed)) bits;
-};
-
-union IO_APIC_reg_03 {
-	u32	raw;
-	struct {
-		u32	boot_DT		:  1,
-			__reserved_1	: 31;
-	} __attribute__ ((packed)) bits;
-};
-
-enum ioapic_irq_destination_types {
-	dest_Fixed = 0,
-	dest_LowestPrio = 1,
-	dest_SMI = 2,
-	dest__reserved_1 = 3,
-	dest_NMI = 4,
-	dest_INIT = 5,
-	dest__reserved_2 = 6,
-	dest_ExtINT = 7
-};
-
-struct IO_APIC_route_entry {
-	__u32	vector		:  8,
-		delivery_mode	:  3,	/* 000: FIXED
-					 * 001: lowest prio
-					 * 111: ExtINT
-					 */
-		dest_mode	:  1,	/* 0: physical, 1: logical */
-		delivery_status	:  1,
-		polarity	:  1,
-		irr		:  1,
-		trigger		:  1,	/* 0: edge, 1: level */
-		mask		:  1,	/* 0: enabled, 1: disabled */
-		__reserved_2	: 15;
-
-#ifdef CONFIG_X86_32
-	union {
-		struct {
-			__u32	__reserved_1	: 24,
-				physical_dest	:  4,
-				__reserved_2	:  4;
-		} physical;
-
-		struct {
-			__u32	__reserved_1	: 24,
-				logical_dest	:  8;
-		} logical;
-	} dest;
-#else
-	__u32	__reserved_3	: 24,
-		dest		:  8;
-#endif
-
-} __attribute__ ((packed));
-
-struct IR_IO_APIC_route_entry {
-	__u64	vector		: 8,
-		zero		: 3,
-		index2		: 1,
-		delivery_status : 1,
-		polarity	: 1,
-		irr		: 1,
-		trigger		: 1,
-		mask		: 1,
-		reserved	: 31,
-		format		: 1,
-		index		: 15;
-} __attribute__ ((packed));
-
-#ifdef CONFIG_X86_IO_APIC
-
-/*
- * # of IO-APICs and # of IRQ routing registers
- */
-extern int nr_ioapics;
-extern int nr_ioapic_registers[MAX_IO_APICS];
-
-/*
- * MP-BIOS irq configuration table structures:
- */
-
-#define MP_MAX_IOAPIC_PIN 127
-
-struct mp_config_ioapic {
-	unsigned long mp_apicaddr;
-	unsigned int mp_apicid;
-	unsigned char mp_type;
-	unsigned char mp_apicver;
-	unsigned char mp_flags;
-};
-
-struct mp_config_intsrc {
-	unsigned int mp_dstapic;
-	unsigned char mp_type;
-	unsigned char mp_irqtype;
-	unsigned short mp_irqflag;
-	unsigned char mp_srcbus;
-	unsigned char mp_srcbusirq;
-	unsigned char mp_dstirq;
-};
-
-/* I/O APIC entries */
-extern struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
-
-/* # of MP IRQ source entries */
-extern int mp_irq_entries;
-
-/* MP IRQ source entries */
-extern struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
-
-/* non-0 if default (table-less) MP configuration */
-extern int mpc_default_type;
-
-/* Older SiS APIC requires we rewrite the index register */
-extern int sis_apic_bug;
-
-/* 1 if "noapic" boot option passed */
-extern int skip_ioapic_setup;
-
-/* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */
-extern int timer_through_8259;
-
-static inline void disable_ioapic_setup(void)
-{
-	skip_ioapic_setup = 1;
-}
-
-/*
- * If we use the IO-APIC for IRQ routing, disable automatic
- * assignment of PCI IRQ's.
- */
-#define io_apic_assign_pci_irqs \
-	(mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
-
-#ifdef CONFIG_ACPI
-extern int io_apic_get_unique_id(int ioapic, int apic_id);
-extern int io_apic_get_version(int ioapic);
-extern int io_apic_get_redir_entries(int ioapic);
-extern int io_apic_set_pci_routing(int ioapic, int pin, int irq,
-				   int edge_level, int active_high_low);
-#endif /* CONFIG_ACPI */
-
-extern int (*ioapic_renumber_irq)(int ioapic, int irq);
-extern void ioapic_init_mappings(void);
-
-#ifdef CONFIG_X86_64
-extern int save_mask_IO_APIC_setup(void);
-extern void restore_IO_APIC_setup(void);
-extern void reinit_intr_remapped_IO_APIC(int);
-#endif
-
-#else  /* !CONFIG_X86_IO_APIC */
-#define io_apic_assign_pci_irqs 0
-static const int timer_through_8259 = 0;
-static inline void ioapic_init_mappings(void) { }
-#endif
-
-#endif /* ASM_X86__IO_APIC_H */
diff --git a/include/asm-x86/ioctl.h b/include/asm-x86/ioctl.h
deleted file mode 100644
index b279fe06dfe5..000000000000
--- a/include/asm-x86/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ioctl.h>
diff --git a/include/asm-x86/ioctls.h b/include/asm-x86/ioctls.h
deleted file mode 100644
index 06752a649044..000000000000
--- a/include/asm-x86/ioctls.h
+++ /dev/null
@@ -1,94 +0,0 @@
-#ifndef ASM_X86__IOCTLS_H
-#define ASM_X86__IOCTLS_H
-
-#include <asm/ioctl.h>
-
-/* 0x54 is just a magic number to make these relatively unique ('T') */
-
-#define TCGETS		0x5401
-#define TCSETS		0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */
-#define TCSETSW		0x5403
-#define TCSETSF		0x5404
-#define TCGETA		0x5405
-#define TCSETA		0x5406
-#define TCSETAW		0x5407
-#define TCSETAF		0x5408
-#define TCSBRK		0x5409
-#define TCXONC		0x540A
-#define TCFLSH		0x540B
-#define TIOCEXCL	0x540C
-#define TIOCNXCL	0x540D
-#define TIOCSCTTY	0x540E
-#define TIOCGPGRP	0x540F
-#define TIOCSPGRP	0x5410
-#define TIOCOUTQ	0x5411
-#define TIOCSTI		0x5412
-#define TIOCGWINSZ	0x5413
-#define TIOCSWINSZ	0x5414
-#define TIOCMGET	0x5415
-#define TIOCMBIS	0x5416
-#define TIOCMBIC	0x5417
-#define TIOCMSET	0x5418
-#define TIOCGSOFTCAR	0x5419
-#define TIOCSSOFTCAR	0x541A
-#define FIONREAD	0x541B
-#define TIOCINQ		FIONREAD
-#define TIOCLINUX	0x541C
-#define TIOCCONS	0x541D
-#define TIOCGSERIAL	0x541E
-#define TIOCSSERIAL	0x541F
-#define TIOCPKT		0x5420
-#define FIONBIO		0x5421
-#define TIOCNOTTY	0x5422
-#define TIOCSETD	0x5423
-#define TIOCGETD	0x5424
-#define TCSBRKP		0x5425	/* Needed for POSIX tcsendbreak() */
-/* #define TIOCTTYGSTRUCT 0x5426 - Former debugging-only ioctl */
-#define TIOCSBRK	0x5427  /* BSD compatibility */
-#define TIOCCBRK	0x5428  /* BSD compatibility */
-#define TIOCGSID	0x5429  /* Return the session ID of FD */
-#define TCGETS2		_IOR('T', 0x2A, struct termios2)
-#define TCSETS2		_IOW('T', 0x2B, struct termios2)
-#define TCSETSW2	_IOW('T', 0x2C, struct termios2)
-#define TCSETSF2	_IOW('T', 0x2D, struct termios2)
-#define TIOCGRS485	0x542E
-#define TIOCSRS485	0x542F
-#define TIOCGPTN	_IOR('T', 0x30, unsigned int)
-				/* Get Pty Number (of pty-mux device) */
-#define TIOCSPTLCK	_IOW('T', 0x31, int)  /* Lock/unlock Pty */
-#define TCGETX		0x5432 /* SYS5 TCGETX compatibility */
-#define TCSETX		0x5433
-#define TCSETXF		0x5434
-#define TCSETXW		0x5435
-
-#define FIONCLEX	0x5450
-#define FIOCLEX		0x5451
-#define FIOASYNC	0x5452
-#define TIOCSERCONFIG	0x5453
-#define TIOCSERGWILD	0x5454
-#define TIOCSERSWILD	0x5455
-#define TIOCGLCKTRMIOS	0x5456
-#define TIOCSLCKTRMIOS	0x5457
-#define TIOCSERGSTRUCT	0x5458 /* For debugging only */
-#define TIOCSERGETLSR   0x5459 /* Get line status register */
-#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
-#define TIOCSERSETMULTI 0x545B /* Set multiport config */
-
-#define TIOCMIWAIT	0x545C	/* wait for a change on serial input line(s) */
-#define TIOCGICOUNT	0x545D	/* read serial port inline interrupt counts */
-#define TIOCGHAYESESP   0x545E  /* Get Hayes ESP configuration */
-#define TIOCSHAYESESP   0x545F  /* Set Hayes ESP configuration */
-#define FIOQSIZE	0x5460
-
-/* Used for packet mode */
-#define TIOCPKT_DATA		 0
-#define TIOCPKT_FLUSHREAD	 1
-#define TIOCPKT_FLUSHWRITE	 2
-#define TIOCPKT_STOP		 4
-#define TIOCPKT_START		 8
-#define TIOCPKT_NOSTOP		16
-#define TIOCPKT_DOSTOP		32
-
-#define TIOCSER_TEMT    0x01	/* Transmitter physically empty */
-
-#endif /* ASM_X86__IOCTLS_H */
diff --git a/include/asm-x86/iommu.h b/include/asm-x86/iommu.h
deleted file mode 100644
index 546ad3110fea..000000000000
--- a/include/asm-x86/iommu.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef ASM_X86__IOMMU_H
-#define ASM_X86__IOMMU_H
-
-extern void pci_iommu_shutdown(void);
-extern void no_iommu_init(void);
-extern struct dma_mapping_ops nommu_dma_ops;
-extern int force_iommu, no_iommu;
-extern int iommu_detected;
-extern int dmar_disabled;
-
-extern unsigned long iommu_num_pages(unsigned long addr, unsigned long len);
-
-#ifdef CONFIG_GART_IOMMU
-extern int gart_iommu_aperture;
-extern int gart_iommu_aperture_allowed;
-extern int gart_iommu_aperture_disabled;
-
-extern void early_gart_iommu_check(void);
-extern void gart_iommu_init(void);
-extern void gart_iommu_shutdown(void);
-extern void __init gart_parse_options(char *);
-extern void gart_iommu_hole_init(void);
-
-#else
-#define gart_iommu_aperture            0
-#define gart_iommu_aperture_allowed    0
-#define gart_iommu_aperture_disabled   1
-
-static inline void early_gart_iommu_check(void)
-{
-}
-static inline void gart_iommu_init(void)
-{
-}
-static inline void gart_iommu_shutdown(void)
-{
-}
-static inline void gart_parse_options(char *options)
-{
-}
-static inline void gart_iommu_hole_init(void)
-{
-}
-#endif
-
-#endif /* ASM_X86__IOMMU_H */
diff --git a/include/asm-x86/ipcbuf.h b/include/asm-x86/ipcbuf.h
deleted file mode 100644
index 910304fbdc8f..000000000000
--- a/include/asm-x86/ipcbuf.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef ASM_X86__IPCBUF_H
-#define ASM_X86__IPCBUF_H
-
-/*
- * The ipc64_perm structure for x86 architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 32-bit mode_t and seq
- * - 2 miscellaneous 32-bit values
- */
-
-struct ipc64_perm {
-	__kernel_key_t		key;
-	__kernel_uid32_t	uid;
-	__kernel_gid32_t	gid;
-	__kernel_uid32_t	cuid;
-	__kernel_gid32_t	cgid;
-	__kernel_mode_t		mode;
-	unsigned short		__pad1;
-	unsigned short		seq;
-	unsigned short		__pad2;
-	unsigned long		__unused1;
-	unsigned long		__unused2;
-};
-
-#endif /* ASM_X86__IPCBUF_H */
diff --git a/include/asm-x86/ipi.h b/include/asm-x86/ipi.h
deleted file mode 100644
index 30a692cfaff8..000000000000
--- a/include/asm-x86/ipi.h
+++ /dev/null
@@ -1,138 +0,0 @@
-#ifndef ASM_X86__IPI_H
-#define ASM_X86__IPI_H
-
-/*
- * Copyright 2004 James Cleverdon, IBM.
- * Subject to the GNU Public License, v.2
- *
- * Generic APIC InterProcessor Interrupt code.
- *
- * Moved to include file by James Cleverdon from
- * arch/x86-64/kernel/smp.c
- *
- * Copyrights from kernel/smp.c:
- *
- * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
- * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
- * (c) 2002,2003 Andi Kleen, SuSE Labs.
- * Subject to the GNU Public License, v.2
- */
-
-#include <asm/hw_irq.h>
-#include <asm/apic.h>
-#include <asm/smp.h>
-
-/*
- * the following functions deal with sending IPIs between CPUs.
- *
- * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
- */
-
-static inline unsigned int __prepare_ICR(unsigned int shortcut, int vector,
-					 unsigned int dest)
-{
-	unsigned int icr = shortcut | dest;
-
-	switch (vector) {
-	default:
-		icr |= APIC_DM_FIXED | vector;
-		break;
-	case NMI_VECTOR:
-		icr |= APIC_DM_NMI;
-		break;
-	}
-	return icr;
-}
-
-static inline int __prepare_ICR2(unsigned int mask)
-{
-	return SET_APIC_DEST_FIELD(mask);
-}
-
-static inline void __xapic_wait_icr_idle(void)
-{
-	while (native_apic_mem_read(APIC_ICR) & APIC_ICR_BUSY)
-		cpu_relax();
-}
-
-static inline void __send_IPI_shortcut(unsigned int shortcut, int vector,
-				       unsigned int dest)
-{
-	/*
-	 * Subtle. In the case of the 'never do double writes' workaround
-	 * we have to lock out interrupts to be safe.  As we don't care
-	 * of the value read we use an atomic rmw access to avoid costly
-	 * cli/sti.  Otherwise we use an even cheaper single atomic write
-	 * to the APIC.
-	 */
-	unsigned int cfg;
-
-	/*
-	 * Wait for idle.
-	 */
-	__xapic_wait_icr_idle();
-
-	/*
-	 * No need to touch the target chip field
-	 */
-	cfg = __prepare_ICR(shortcut, vector, dest);
-
-	/*
-	 * Send the IPI. The write to APIC_ICR fires this off.
-	 */
-	native_apic_mem_write(APIC_ICR, cfg);
-}
-
-/*
- * This is used to send an IPI with no shorthand notation (the destination is
- * specified in bits 56 to 63 of the ICR).
- */
-static inline void __send_IPI_dest_field(unsigned int mask, int vector,
-					 unsigned int dest)
-{
-	unsigned long cfg;
-
-	/*
-	 * Wait for idle.
-	 */
-	if (unlikely(vector == NMI_VECTOR))
-		safe_apic_wait_icr_idle();
-	else
-		__xapic_wait_icr_idle();
-
-	/*
-	 * prepare target chip field
-	 */
-	cfg = __prepare_ICR2(mask);
-	native_apic_mem_write(APIC_ICR2, cfg);
-
-	/*
-	 * program the ICR
-	 */
-	cfg = __prepare_ICR(0, vector, dest);
-
-	/*
-	 * Send the IPI. The write to APIC_ICR fires this off.
-	 */
-	native_apic_mem_write(APIC_ICR, cfg);
-}
-
-static inline void send_IPI_mask_sequence(cpumask_t mask, int vector)
-{
-	unsigned long flags;
-	unsigned long query_cpu;
-
-	/*
-	 * Hack. The clustered APIC addressing mode doesn't allow us to send
-	 * to an arbitrary mask, so I do a unicast to each CPU instead.
-	 * - mbligh
-	 */
-	local_irq_save(flags);
-	for_each_cpu_mask_nr(query_cpu, mask) {
-		__send_IPI_dest_field(per_cpu(x86_cpu_to_apicid, query_cpu),
-				      vector, APIC_DEST_PHYSICAL);
-	}
-	local_irq_restore(flags);
-}
-
-#endif /* ASM_X86__IPI_H */
diff --git a/include/asm-x86/irq.h b/include/asm-x86/irq.h
deleted file mode 100644
index 1e5f2909c1db..000000000000
--- a/include/asm-x86/irq.h
+++ /dev/null
@@ -1,50 +0,0 @@
-#ifndef ASM_X86__IRQ_H
-#define ASM_X86__IRQ_H
-/*
- *	(C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar
- *
- *	IRQ/IPI changes taken from work by Thomas Radke
- *	<tomsoft@informatik.tu-chemnitz.de>
- */
-
-#include <asm/apicdef.h>
-#include <asm/irq_vectors.h>
-
-static inline int irq_canonicalize(int irq)
-{
-	return ((irq == 2) ? 9 : irq);
-}
-
-#ifdef CONFIG_X86_LOCAL_APIC
-# define ARCH_HAS_NMI_WATCHDOG
-#endif
-
-#ifdef CONFIG_4KSTACKS
-  extern void irq_ctx_init(int cpu);
-  extern void irq_ctx_exit(int cpu);
-# define __ARCH_HAS_DO_SOFTIRQ
-#else
-# define irq_ctx_init(cpu) do { } while (0)
-# define irq_ctx_exit(cpu) do { } while (0)
-# ifdef CONFIG_X86_64
-#  define __ARCH_HAS_DO_SOFTIRQ
-# endif
-#endif
-
-#ifdef CONFIG_IRQBALANCE
-extern int irqbalance_disable(char *str);
-#endif
-
-#ifdef CONFIG_HOTPLUG_CPU
-#include <linux/cpumask.h>
-extern void fixup_irqs(cpumask_t map);
-#endif
-
-extern unsigned int do_IRQ(struct pt_regs *regs);
-extern void init_IRQ(void);
-extern void native_init_IRQ(void);
-
-/* Interrupt vector management */
-extern DECLARE_BITMAP(used_vectors, NR_VECTORS);
-
-#endif /* ASM_X86__IRQ_H */
diff --git a/include/asm-x86/irq_regs.h b/include/asm-x86/irq_regs.h
deleted file mode 100644
index 89c898ab298b..000000000000
--- a/include/asm-x86/irq_regs.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifdef CONFIG_X86_32
-# include "irq_regs_32.h"
-#else
-# include "irq_regs_64.h"
-#endif
diff --git a/include/asm-x86/irq_regs_32.h b/include/asm-x86/irq_regs_32.h
deleted file mode 100644
index 316a3b258871..000000000000
--- a/include/asm-x86/irq_regs_32.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Per-cpu current frame pointer - the location of the last exception frame on
- * the stack, stored in the per-cpu area.
- *
- * Jeremy Fitzhardinge <jeremy@goop.org>
- */
-#ifndef ASM_X86__IRQ_REGS_32_H
-#define ASM_X86__IRQ_REGS_32_H
-
-#include <asm/percpu.h>
-
-DECLARE_PER_CPU(struct pt_regs *, irq_regs);
-
-static inline struct pt_regs *get_irq_regs(void)
-{
-	return x86_read_percpu(irq_regs);
-}
-
-static inline struct pt_regs *set_irq_regs(struct pt_regs *new_regs)
-{
-	struct pt_regs *old_regs;
-
-	old_regs = get_irq_regs();
-	x86_write_percpu(irq_regs, new_regs);
-
-	return old_regs;
-}
-
-#endif /* ASM_X86__IRQ_REGS_32_H */
diff --git a/include/asm-x86/irq_regs_64.h b/include/asm-x86/irq_regs_64.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/include/asm-x86/irq_regs_64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/include/asm-x86/irq_remapping.h b/include/asm-x86/irq_remapping.h
deleted file mode 100644
index 78242c6ffa58..000000000000
--- a/include/asm-x86/irq_remapping.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _ASM_IRQ_REMAPPING_H
-#define _ASM_IRQ_REMAPPING_H
-
-extern int x2apic;
-
-#define IRTE_DEST(dest) ((x2apic) ? dest : dest << 8)
-
-#endif
diff --git a/include/asm-x86/irq_vectors.h b/include/asm-x86/irq_vectors.h
deleted file mode 100644
index c5d2d767a1f3..000000000000
--- a/include/asm-x86/irq_vectors.h
+++ /dev/null
@@ -1,182 +0,0 @@
-#ifndef ASM_X86__IRQ_VECTORS_H
-#define ASM_X86__IRQ_VECTORS_H
-
-#include <linux/threads.h>
-
-#define NMI_VECTOR		0x02
-
-/*
- * IDT vectors usable for external interrupt sources start
- * at 0x20:
- */
-#define FIRST_EXTERNAL_VECTOR	0x20
-
-#ifdef CONFIG_X86_32
-# define SYSCALL_VECTOR		0x80
-#else
-# define IA32_SYSCALL_VECTOR	0x80
-#endif
-
-/*
- * Reserve the lowest usable priority level 0x20 - 0x2f for triggering
- * cleanup after irq migration on 64 bit.
- */
-#define IRQ_MOVE_CLEANUP_VECTOR	FIRST_EXTERNAL_VECTOR
-
-/*
- * Vectors 0x20-0x2f are used for ISA interrupts on 32 bit.
- * Vectors 0x30-0x3f are used for ISA interrupts on 64 bit.
- */
-#ifdef CONFIG_X86_32
-#define IRQ0_VECTOR		(FIRST_EXTERNAL_VECTOR)
-#else
-#define IRQ0_VECTOR		(FIRST_EXTERNAL_VECTOR + 0x10)
-#endif
-#define IRQ1_VECTOR		(IRQ0_VECTOR + 1)
-#define IRQ2_VECTOR		(IRQ0_VECTOR + 2)
-#define IRQ3_VECTOR		(IRQ0_VECTOR + 3)
-#define IRQ4_VECTOR		(IRQ0_VECTOR + 4)
-#define IRQ5_VECTOR		(IRQ0_VECTOR + 5)
-#define IRQ6_VECTOR		(IRQ0_VECTOR + 6)
-#define IRQ7_VECTOR		(IRQ0_VECTOR + 7)
-#define IRQ8_VECTOR		(IRQ0_VECTOR + 8)
-#define IRQ9_VECTOR		(IRQ0_VECTOR + 9)
-#define IRQ10_VECTOR		(IRQ0_VECTOR + 10)
-#define IRQ11_VECTOR		(IRQ0_VECTOR + 11)
-#define IRQ12_VECTOR		(IRQ0_VECTOR + 12)
-#define IRQ13_VECTOR		(IRQ0_VECTOR + 13)
-#define IRQ14_VECTOR		(IRQ0_VECTOR + 14)
-#define IRQ15_VECTOR		(IRQ0_VECTOR + 15)
-
-/*
- * Special IRQ vectors used by the SMP architecture, 0xf0-0xff
- *
- *  some of the following vectors are 'rare', they are merged
- *  into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
- *  TLB, reschedule and local APIC vectors are performance-critical.
- *
- *  Vectors 0xf0-0xfa are free (reserved for future Linux use).
- */
-#ifdef CONFIG_X86_32
-
-# define SPURIOUS_APIC_VECTOR		0xff
-# define ERROR_APIC_VECTOR		0xfe
-# define INVALIDATE_TLB_VECTOR		0xfd
-# define RESCHEDULE_VECTOR		0xfc
-# define CALL_FUNCTION_VECTOR		0xfb
-# define CALL_FUNCTION_SINGLE_VECTOR	0xfa
-# define THERMAL_APIC_VECTOR		0xf0
-
-#else
-
-#define SPURIOUS_APIC_VECTOR		0xff
-#define ERROR_APIC_VECTOR		0xfe
-#define RESCHEDULE_VECTOR		0xfd
-#define CALL_FUNCTION_VECTOR		0xfc
-#define CALL_FUNCTION_SINGLE_VECTOR	0xfb
-#define THERMAL_APIC_VECTOR		0xfa
-#define THRESHOLD_APIC_VECTOR		0xf9
-#define UV_BAU_MESSAGE			0xf8
-#define INVALIDATE_TLB_VECTOR_END	0xf7
-#define INVALIDATE_TLB_VECTOR_START	0xf0	/* f0-f7 used for TLB flush */
-
-#define NUM_INVALIDATE_TLB_VECTORS	8
-
-#endif
-
-/*
- * Local APIC timer IRQ vector is on a different priority level,
- * to work around the 'lost local interrupt if more than 2 IRQ
- * sources per level' errata.
- */
-#define LOCAL_TIMER_VECTOR	0xef
-
-/*
- * First APIC vector available to drivers: (vectors 0x30-0xee) we
- * start at 0x31(0x41) to spread out vectors evenly between priority
- * levels. (0x80 is the syscall vector)
- */
-#ifdef CONFIG_X86_32
-# define FIRST_DEVICE_VECTOR	0x31
-#else
-# define FIRST_DEVICE_VECTOR	(IRQ15_VECTOR + 2)
-#endif
-
-#define NR_VECTORS		256
-
-#define FPU_IRQ			13
-
-#define	FIRST_VM86_IRQ		3
-#define LAST_VM86_IRQ		15
-#define invalid_vm86_irq(irq)	((irq) < 3 || (irq) > 15)
-
-#ifdef CONFIG_X86_64
-# if NR_CPUS < MAX_IO_APICS
-#  define NR_IRQS (NR_VECTORS + (32 * NR_CPUS))
-# else
-#  define NR_IRQS (NR_VECTORS + (32 * MAX_IO_APICS))
-# endif
-# define NR_IRQ_VECTORS NR_IRQS
-
-#elif !defined(CONFIG_X86_VOYAGER)
-
-# if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_PARAVIRT) || defined(CONFIG_X86_VISWS)
-
-#  define NR_IRQS		224
-
-#  if (224 >= 32 * NR_CPUS)
-#   define NR_IRQ_VECTORS	NR_IRQS
-#  else
-#   define NR_IRQ_VECTORS	(32 * NR_CPUS)
-#  endif
-
-# else /* IO_APIC || PARAVIRT */
-
-#  define NR_IRQS		16
-#  define NR_IRQ_VECTORS	NR_IRQS
-
-# endif
-
-#else /* !VISWS && !VOYAGER */
-
-# define NR_IRQS		224
-# define NR_IRQ_VECTORS		NR_IRQS
-
-#endif /* VISWS */
-
-/* Voyager specific defines */
-/* These define the CPIs we use in linux */
-#define VIC_CPI_LEVEL0			0
-#define VIC_CPI_LEVEL1			1
-/* now the fake CPIs */
-#define VIC_TIMER_CPI			2
-#define VIC_INVALIDATE_CPI		3
-#define VIC_RESCHEDULE_CPI		4
-#define VIC_ENABLE_IRQ_CPI		5
-#define VIC_CALL_FUNCTION_CPI		6
-#define VIC_CALL_FUNCTION_SINGLE_CPI	7
-
-/* Now the QIC CPIs:  Since we don't need the two initial levels,
- * these are 2 less than the VIC CPIs */
-#define QIC_CPI_OFFSET			1
-#define QIC_TIMER_CPI			(VIC_TIMER_CPI - QIC_CPI_OFFSET)
-#define QIC_INVALIDATE_CPI		(VIC_INVALIDATE_CPI - QIC_CPI_OFFSET)
-#define QIC_RESCHEDULE_CPI		(VIC_RESCHEDULE_CPI - QIC_CPI_OFFSET)
-#define QIC_ENABLE_IRQ_CPI		(VIC_ENABLE_IRQ_CPI - QIC_CPI_OFFSET)
-#define QIC_CALL_FUNCTION_CPI		(VIC_CALL_FUNCTION_CPI - QIC_CPI_OFFSET)
-#define QIC_CALL_FUNCTION_SINGLE_CPI	(VIC_CALL_FUNCTION_SINGLE_CPI - QIC_CPI_OFFSET)
-
-#define VIC_START_FAKE_CPI		VIC_TIMER_CPI
-#define VIC_END_FAKE_CPI		VIC_CALL_FUNCTION_SINGLE_CPI
-
-/* this is the SYS_INT CPI. */
-#define VIC_SYS_INT			8
-#define VIC_CMN_INT			15
-
-/* This is the boot CPI for alternate processors.  It gets overwritten
- * by the above once the system has activated all available processors */
-#define VIC_CPU_BOOT_CPI		VIC_CPI_LEVEL0
-#define VIC_CPU_BOOT_ERRATA_CPI		(VIC_CPI_LEVEL0 + 8)
-
-
-#endif /* ASM_X86__IRQ_VECTORS_H */
diff --git a/include/asm-x86/irqflags.h b/include/asm-x86/irqflags.h
deleted file mode 100644
index 2bdab21f0898..000000000000
--- a/include/asm-x86/irqflags.h
+++ /dev/null
@@ -1,211 +0,0 @@
-#ifndef _X86_IRQFLAGS_H_
-#define _X86_IRQFLAGS_H_
-
-#include <asm/processor-flags.h>
-
-#ifndef __ASSEMBLY__
-/*
- * Interrupt control:
- */
-
-static inline unsigned long native_save_fl(void)
-{
-	unsigned long flags;
-
-	asm volatile("# __raw_save_flags\n\t"
-		     "pushf ; pop %0"
-		     : "=g" (flags)
-		     : /* no input */
-		     : "memory");
-
-	return flags;
-}
-
-static inline void native_restore_fl(unsigned long flags)
-{
-	asm volatile("push %0 ; popf"
-		     : /* no output */
-		     :"g" (flags)
-		     :"memory", "cc");
-}
-
-static inline void native_irq_disable(void)
-{
-	asm volatile("cli": : :"memory");
-}
-
-static inline void native_irq_enable(void)
-{
-	asm volatile("sti": : :"memory");
-}
-
-static inline void native_safe_halt(void)
-{
-	asm volatile("sti; hlt": : :"memory");
-}
-
-static inline void native_halt(void)
-{
-	asm volatile("hlt": : :"memory");
-}
-
-#endif
-
-#ifdef CONFIG_PARAVIRT
-#include <asm/paravirt.h>
-#else
-#ifndef __ASSEMBLY__
-
-static inline unsigned long __raw_local_save_flags(void)
-{
-	return native_save_fl();
-}
-
-static inline void raw_local_irq_restore(unsigned long flags)
-{
-	native_restore_fl(flags);
-}
-
-static inline void raw_local_irq_disable(void)
-{
-	native_irq_disable();
-}
-
-static inline void raw_local_irq_enable(void)
-{
-	native_irq_enable();
-}
-
-/*
- * Used in the idle loop; sti takes one instruction cycle
- * to complete:
- */
-static inline void raw_safe_halt(void)
-{
-	native_safe_halt();
-}
-
-/*
- * Used when interrupts are already enabled or to
- * shutdown the processor:
- */
-static inline void halt(void)
-{
-	native_halt();
-}
-
-/*
- * For spinlocks, etc:
- */
-static inline unsigned long __raw_local_irq_save(void)
-{
-	unsigned long flags = __raw_local_save_flags();
-
-	raw_local_irq_disable();
-
-	return flags;
-}
-#else
-
-#define ENABLE_INTERRUPTS(x)	sti
-#define DISABLE_INTERRUPTS(x)	cli
-
-#ifdef CONFIG_X86_64
-#define SWAPGS	swapgs
-/*
- * Currently paravirt can't handle swapgs nicely when we
- * don't have a stack we can rely on (such as a user space
- * stack).  So we either find a way around these or just fault
- * and emulate if a guest tries to call swapgs directly.
- *
- * Either way, this is a good way to document that we don't
- * have a reliable stack. x86_64 only.
- */
-#define SWAPGS_UNSAFE_STACK	swapgs
-
-#define PARAVIRT_ADJUST_EXCEPTION_FRAME	/*  */
-
-#define INTERRUPT_RETURN	iretq
-#define USERGS_SYSRET64				\
-	swapgs;					\
-	sysretq;
-#define USERGS_SYSRET32				\
-	swapgs;					\
-	sysretl
-#define ENABLE_INTERRUPTS_SYSEXIT32		\
-	swapgs;					\
-	sti;					\
-	sysexit
-
-#else
-#define INTERRUPT_RETURN		iret
-#define ENABLE_INTERRUPTS_SYSEXIT	sti; sysexit
-#define GET_CR0_INTO_EAX		movl %cr0, %eax
-#endif
-
-
-#endif /* __ASSEMBLY__ */
-#endif /* CONFIG_PARAVIRT */
-
-#ifndef __ASSEMBLY__
-#define raw_local_save_flags(flags)				\
-	do { (flags) = __raw_local_save_flags(); } while (0)
-
-#define raw_local_irq_save(flags)				\
-	do { (flags) = __raw_local_irq_save(); } while (0)
-
-static inline int raw_irqs_disabled_flags(unsigned long flags)
-{
-	return !(flags & X86_EFLAGS_IF);
-}
-
-static inline int raw_irqs_disabled(void)
-{
-	unsigned long flags = __raw_local_save_flags();
-
-	return raw_irqs_disabled_flags(flags);
-}
-
-#else
-
-#ifdef CONFIG_X86_64
-#define ARCH_LOCKDEP_SYS_EXIT		call lockdep_sys_exit_thunk
-#define ARCH_LOCKDEP_SYS_EXIT_IRQ	\
-	TRACE_IRQS_ON; \
-	sti; \
-	SAVE_REST; \
-	LOCKDEP_SYS_EXIT; \
-	RESTORE_REST; \
-	cli; \
-	TRACE_IRQS_OFF;
-
-#else
-#define ARCH_LOCKDEP_SYS_EXIT			\
-	pushl %eax;				\
-	pushl %ecx;				\
-	pushl %edx;				\
-	call lockdep_sys_exit;			\
-	popl %edx;				\
-	popl %ecx;				\
-	popl %eax;
-
-#define ARCH_LOCKDEP_SYS_EXIT_IRQ
-#endif
-
-#ifdef CONFIG_TRACE_IRQFLAGS
-#  define TRACE_IRQS_ON		call trace_hardirqs_on_thunk;
-#  define TRACE_IRQS_OFF	call trace_hardirqs_off_thunk;
-#else
-#  define TRACE_IRQS_ON
-#  define TRACE_IRQS_OFF
-#endif
-#ifdef CONFIG_DEBUG_LOCK_ALLOC
-#  define LOCKDEP_SYS_EXIT	ARCH_LOCKDEP_SYS_EXIT
-#  define LOCKDEP_SYS_EXIT_IRQ	ARCH_LOCKDEP_SYS_EXIT_IRQ
-# else
-#  define LOCKDEP_SYS_EXIT
-#  define LOCKDEP_SYS_EXIT_IRQ
-# endif
-
-#endif /* __ASSEMBLY__ */
-#endif
diff --git a/include/asm-x86/ist.h b/include/asm-x86/ist.h
deleted file mode 100644
index 35a2fe9bc921..000000000000
--- a/include/asm-x86/ist.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef ASM_X86__IST_H
-#define ASM_X86__IST_H
-
-/*
- * Include file for the interface to IST BIOS
- * Copyright 2002 Andy Grover <andrew.grover@intel.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2, or (at your option) any
- * later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- */
-
-
-#include <linux/types.h>
-
-struct ist_info {
-	__u32 signature;
-	__u32 command;
-	__u32 event;
-	__u32 perf_level;
-};
-
-#ifdef __KERNEL__
-
-extern struct ist_info ist_info;
-
-#endif	/* __KERNEL__ */
-#endif /* ASM_X86__IST_H */
diff --git a/include/asm-x86/k8.h b/include/asm-x86/k8.h
deleted file mode 100644
index 2bbaf4370a55..000000000000
--- a/include/asm-x86/k8.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef ASM_X86__K8_H
-#define ASM_X86__K8_H
-
-#include <linux/pci.h>
-
-extern struct pci_device_id k8_nb_ids[];
-
-extern int early_is_k8_nb(u32 value);
-extern struct pci_dev **k8_northbridges;
-extern int num_k8_northbridges;
-extern int cache_k8_northbridges(void);
-extern void k8_flush_garts(void);
-extern int k8_scan_nodes(unsigned long start, unsigned long end);
-
-#endif /* ASM_X86__K8_H */
diff --git a/include/asm-x86/kdebug.h b/include/asm-x86/kdebug.h
deleted file mode 100644
index fbbab66ee9df..000000000000
--- a/include/asm-x86/kdebug.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#ifndef ASM_X86__KDEBUG_H
-#define ASM_X86__KDEBUG_H
-
-#include <linux/notifier.h>
-
-struct pt_regs;
-
-/* Grossly misnamed. */
-enum die_val {
-	DIE_OOPS = 1,
-	DIE_INT3,
-	DIE_DEBUG,
-	DIE_PANIC,
-	DIE_NMI,
-	DIE_DIE,
-	DIE_NMIWATCHDOG,
-	DIE_KERNELDEBUG,
-	DIE_TRAP,
-	DIE_GPF,
-	DIE_CALL,
-	DIE_NMI_IPI,
-	DIE_PAGE_FAULT,
-	DIE_NMIUNKNOWN,
-};
-
-extern void printk_address(unsigned long address, int reliable);
-extern void die(const char *, struct pt_regs *,long);
-extern int __must_check __die(const char *, struct pt_regs *, long);
-extern void show_registers(struct pt_regs *regs);
-extern void show_trace(struct task_struct *t, struct pt_regs *regs,
-		       unsigned long *sp, unsigned long bp);
-extern void __show_regs(struct pt_regs *regs, int all);
-extern void show_regs(struct pt_regs *regs);
-extern unsigned long oops_begin(void);
-extern void oops_end(unsigned long, struct pt_regs *, int signr);
-
-#endif /* ASM_X86__KDEBUG_H */
diff --git a/include/asm-x86/kexec.h b/include/asm-x86/kexec.h
deleted file mode 100644
index ea09600d6129..000000000000
--- a/include/asm-x86/kexec.h
+++ /dev/null
@@ -1,175 +0,0 @@
-#ifndef ASM_X86__KEXEC_H
-#define ASM_X86__KEXEC_H
-
-#ifdef CONFIG_X86_32
-# define PA_CONTROL_PAGE	0
-# define VA_CONTROL_PAGE	1
-# define PA_PGD			2
-# define VA_PGD			3
-# define PA_PTE_0		4
-# define VA_PTE_0		5
-# define PA_PTE_1		6
-# define VA_PTE_1		7
-# define PA_SWAP_PAGE		8
-# ifdef CONFIG_X86_PAE
-#  define PA_PMD_0		9
-#  define VA_PMD_0		10
-#  define PA_PMD_1		11
-#  define VA_PMD_1		12
-#  define PAGES_NR		13
-# else
-#  define PAGES_NR		9
-# endif
-#else
-# define PA_CONTROL_PAGE	0
-# define VA_CONTROL_PAGE	1
-# define PA_PGD			2
-# define VA_PGD			3
-# define PA_PUD_0		4
-# define VA_PUD_0		5
-# define PA_PMD_0		6
-# define VA_PMD_0		7
-# define PA_PTE_0		8
-# define VA_PTE_0		9
-# define PA_PUD_1		10
-# define VA_PUD_1		11
-# define PA_PMD_1		12
-# define VA_PMD_1		13
-# define PA_PTE_1		14
-# define VA_PTE_1		15
-# define PA_TABLE_PAGE		16
-# define PAGES_NR		17
-#endif
-
-#ifdef CONFIG_X86_32
-# define KEXEC_CONTROL_CODE_MAX_SIZE	2048
-#endif
-
-#ifndef __ASSEMBLY__
-
-#include <linux/string.h>
-
-#include <asm/page.h>
-#include <asm/ptrace.h>
-
-/*
- * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
- * I.e. Maximum page that is mapped directly into kernel memory,
- * and kmap is not required.
- *
- * So far x86_64 is limited to 40 physical address bits.
- */
-#ifdef CONFIG_X86_32
-/* Maximum physical address we can use pages from */
-# define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
-/* Maximum address we can reach in physical address mode */
-# define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
-/* Maximum address we can use for the control code buffer */
-# define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
-
-# define KEXEC_CONTROL_PAGE_SIZE	4096
-
-/* The native architecture */
-# define KEXEC_ARCH KEXEC_ARCH_386
-
-/* We can also handle crash dumps from 64 bit kernel. */
-# define vmcore_elf_check_arch_cross(x) ((x)->e_machine == EM_X86_64)
-#else
-/* Maximum physical address we can use pages from */
-# define KEXEC_SOURCE_MEMORY_LIMIT      (0xFFFFFFFFFFUL)
-/* Maximum address we can reach in physical address mode */
-# define KEXEC_DESTINATION_MEMORY_LIMIT (0xFFFFFFFFFFUL)
-/* Maximum address we can use for the control pages */
-# define KEXEC_CONTROL_MEMORY_LIMIT     (0xFFFFFFFFFFUL)
-
-/* Allocate one page for the pdp and the second for the code */
-# define KEXEC_CONTROL_PAGE_SIZE  (4096UL + 4096UL)
-
-/* The native architecture */
-# define KEXEC_ARCH KEXEC_ARCH_X86_64
-#endif
-
-/*
- * CPU does not save ss and sp on stack if execution is already
- * running in kernel mode at the time of NMI occurrence. This code
- * fixes it.
- */
-static inline void crash_fixup_ss_esp(struct pt_regs *newregs,
-				      struct pt_regs *oldregs)
-{
-#ifdef CONFIG_X86_32
-	newregs->sp = (unsigned long)&(oldregs->sp);
-	asm volatile("xorl %%eax, %%eax\n\t"
-		     "movw %%ss, %%ax\n\t"
-		     :"=a"(newregs->ss));
-#endif
-}
-
-/*
- * This function is responsible for capturing register states if coming
- * via panic otherwise just fix up the ss and sp if coming via kernel
- * mode exception.
- */
-static inline void crash_setup_regs(struct pt_regs *newregs,
-				    struct pt_regs *oldregs)
-{
-	if (oldregs) {
-		memcpy(newregs, oldregs, sizeof(*newregs));
-		crash_fixup_ss_esp(newregs, oldregs);
-	} else {
-#ifdef CONFIG_X86_32
-		asm volatile("movl %%ebx,%0" : "=m"(newregs->bx));
-		asm volatile("movl %%ecx,%0" : "=m"(newregs->cx));
-		asm volatile("movl %%edx,%0" : "=m"(newregs->dx));
-		asm volatile("movl %%esi,%0" : "=m"(newregs->si));
-		asm volatile("movl %%edi,%0" : "=m"(newregs->di));
-		asm volatile("movl %%ebp,%0" : "=m"(newregs->bp));
-		asm volatile("movl %%eax,%0" : "=m"(newregs->ax));
-		asm volatile("movl %%esp,%0" : "=m"(newregs->sp));
-		asm volatile("movl %%ss, %%eax;" :"=a"(newregs->ss));
-		asm volatile("movl %%cs, %%eax;" :"=a"(newregs->cs));
-		asm volatile("movl %%ds, %%eax;" :"=a"(newregs->ds));
-		asm volatile("movl %%es, %%eax;" :"=a"(newregs->es));
-		asm volatile("pushfl; popl %0" :"=m"(newregs->flags));
-#else
-		asm volatile("movq %%rbx,%0" : "=m"(newregs->bx));
-		asm volatile("movq %%rcx,%0" : "=m"(newregs->cx));
-		asm volatile("movq %%rdx,%0" : "=m"(newregs->dx));
-		asm volatile("movq %%rsi,%0" : "=m"(newregs->si));
-		asm volatile("movq %%rdi,%0" : "=m"(newregs->di));
-		asm volatile("movq %%rbp,%0" : "=m"(newregs->bp));
-		asm volatile("movq %%rax,%0" : "=m"(newregs->ax));
-		asm volatile("movq %%rsp,%0" : "=m"(newregs->sp));
-		asm volatile("movq %%r8,%0" : "=m"(newregs->r8));
-		asm volatile("movq %%r9,%0" : "=m"(newregs->r9));
-		asm volatile("movq %%r10,%0" : "=m"(newregs->r10));
-		asm volatile("movq %%r11,%0" : "=m"(newregs->r11));
-		asm volatile("movq %%r12,%0" : "=m"(newregs->r12));
-		asm volatile("movq %%r13,%0" : "=m"(newregs->r13));
-		asm volatile("movq %%r14,%0" : "=m"(newregs->r14));
-		asm volatile("movq %%r15,%0" : "=m"(newregs->r15));
-		asm volatile("movl %%ss, %%eax;" :"=a"(newregs->ss));
-		asm volatile("movl %%cs, %%eax;" :"=a"(newregs->cs));
-		asm volatile("pushfq; popq %0" :"=m"(newregs->flags));
-#endif
-		newregs->ip = (unsigned long)current_text_addr();
-	}
-}
-
-#ifdef CONFIG_X86_32
-asmlinkage unsigned long
-relocate_kernel(unsigned long indirection_page,
-		unsigned long control_page,
-		unsigned long start_address,
-		unsigned int has_pae,
-		unsigned int preserve_context);
-#else
-NORET_TYPE void
-relocate_kernel(unsigned long indirection_page,
-		unsigned long page_list,
-		unsigned long start_address) ATTRIB_NORET;
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* ASM_X86__KEXEC_H */
diff --git a/include/asm-x86/kgdb.h b/include/asm-x86/kgdb.h
deleted file mode 100644
index d283863354de..000000000000
--- a/include/asm-x86/kgdb.h
+++ /dev/null
@@ -1,79 +0,0 @@
-#ifndef ASM_X86__KGDB_H
-#define ASM_X86__KGDB_H
-
-/*
- * Copyright (C) 2001-2004 Amit S. Kale
- * Copyright (C) 2008 Wind River Systems, Inc.
- */
-
-/*
- * BUFMAX defines the maximum number of characters in inbound/outbound
- * buffers at least NUMREGBYTES*2 are needed for register packets
- * Longer buffer is needed to list all threads
- */
-#define BUFMAX			1024
-
-/*
- *  Note that this register image is in a different order than
- *  the register image that Linux produces at interrupt time.
- *
- *  Linux's register image is defined by struct pt_regs in ptrace.h.
- *  Just why GDB uses a different order is a historical mystery.
- */
-#ifdef CONFIG_X86_32
-enum regnames {
-	GDB_AX,			/* 0 */
-	GDB_CX,			/* 1 */
-	GDB_DX,			/* 2 */
-	GDB_BX,			/* 3 */
-	GDB_SP,			/* 4 */
-	GDB_BP,			/* 5 */
-	GDB_SI,			/* 6 */
-	GDB_DI,			/* 7 */
-	GDB_PC,			/* 8 also known as eip */
-	GDB_PS,			/* 9 also known as eflags */
-	GDB_CS,			/* 10 */
-	GDB_SS,			/* 11 */
-	GDB_DS,			/* 12 */
-	GDB_ES,			/* 13 */
-	GDB_FS,			/* 14 */
-	GDB_GS,			/* 15 */
-};
-#define NUMREGBYTES		((GDB_GS+1)*4)
-#else /* ! CONFIG_X86_32 */
-enum regnames64 {
-	GDB_AX,			/* 0 */
-	GDB_BX,			/* 1 */
-	GDB_CX,			/* 2 */
-	GDB_DX,			/* 3 */
-	GDB_SI,			/* 4 */
-	GDB_DI,			/* 5 */
-	GDB_BP,			/* 6 */
-	GDB_SP,			/* 7 */
-	GDB_R8,			/* 8 */
-	GDB_R9,			/* 9 */
-	GDB_R10,		/* 10 */
-	GDB_R11,		/* 11 */
-	GDB_R12,		/* 12 */
-	GDB_R13,		/* 13 */
-	GDB_R14,		/* 14 */
-	GDB_R15,		/* 15 */
-	GDB_PC,			/* 16 */
-};
-
-enum regnames32 {
-	GDB_PS = 34,
-	GDB_CS,
-	GDB_SS,
-};
-#define NUMREGBYTES		((GDB_SS+1)*4)
-#endif /* CONFIG_X86_32 */
-
-static inline void arch_kgdb_breakpoint(void)
-{
-	asm("   int $3");
-}
-#define BREAK_INSTR_SIZE	1
-#define CACHE_FLUSH_IS_SAFE	1
-
-#endif /* ASM_X86__KGDB_H */
diff --git a/include/asm-x86/kmap_types.h b/include/asm-x86/kmap_types.h
deleted file mode 100644
index 89f44493e643..000000000000
--- a/include/asm-x86/kmap_types.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef ASM_X86__KMAP_TYPES_H
-#define ASM_X86__KMAP_TYPES_H
-
-#if defined(CONFIG_X86_32) && defined(CONFIG_DEBUG_HIGHMEM)
-# define D(n) __KM_FENCE_##n ,
-#else
-# define D(n)
-#endif
-
-enum km_type {
-D(0)	KM_BOUNCE_READ,
-D(1)	KM_SKB_SUNRPC_DATA,
-D(2)	KM_SKB_DATA_SOFTIRQ,
-D(3)	KM_USER0,
-D(4)	KM_USER1,
-D(5)	KM_BIO_SRC_IRQ,
-D(6)	KM_BIO_DST_IRQ,
-D(7)	KM_PTE0,
-D(8)	KM_PTE1,
-D(9)	KM_IRQ0,
-D(10)	KM_IRQ1,
-D(11)	KM_SOFTIRQ0,
-D(12)	KM_SOFTIRQ1,
-D(13)	KM_TYPE_NR
-};
-
-#undef D
-
-#endif /* ASM_X86__KMAP_TYPES_H */
diff --git a/include/asm-x86/kprobes.h b/include/asm-x86/kprobes.h
deleted file mode 100644
index 8a0748d01036..000000000000
--- a/include/asm-x86/kprobes.h
+++ /dev/null
@@ -1,88 +0,0 @@
-#ifndef ASM_X86__KPROBES_H
-#define ASM_X86__KPROBES_H
-/*
- *  Kernel Probes (KProbes)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) IBM Corporation, 2002, 2004
- *
- * See arch/x86/kernel/kprobes.c for x86 kprobes history.
- */
-#include <linux/types.h>
-#include <linux/ptrace.h>
-#include <linux/percpu.h>
-
-#define  __ARCH_WANT_KPROBES_INSN_SLOT
-
-struct pt_regs;
-struct kprobe;
-
-typedef u8 kprobe_opcode_t;
-#define BREAKPOINT_INSTRUCTION	0xcc
-#define RELATIVEJUMP_INSTRUCTION 0xe9
-#define MAX_INSN_SIZE 16
-#define MAX_STACK_SIZE 64
-#define MIN_STACK_SIZE(ADDR)					       \
-	(((MAX_STACK_SIZE) < (((unsigned long)current_thread_info()) + \
-			      THREAD_SIZE - (unsigned long)(ADDR)))    \
-	 ? (MAX_STACK_SIZE)					       \
-	 : (((unsigned long)current_thread_info()) +		       \
-	    THREAD_SIZE - (unsigned long)(ADDR)))
-
-#define flush_insn_slot(p)	do { } while (0)
-
-extern const int kretprobe_blacklist_size;
-
-void arch_remove_kprobe(struct kprobe *p);
-void kretprobe_trampoline(void);
-
-/* Architecture specific copy of original instruction*/
-struct arch_specific_insn {
-	/* copy of the original instruction */
-	kprobe_opcode_t *insn;
-	/*
-	 * boostable = -1: This instruction type is not boostable.
-	 * boostable = 0: This instruction type is boostable.
-	 * boostable = 1: This instruction has been boosted: we have
-	 * added a relative jump after the instruction copy in insn,
-	 * so no single-step and fixup are needed (unless there's
-	 * a post_handler or break_handler).
-	 */
-	int boostable;
-};
-
-struct prev_kprobe {
-	struct kprobe *kp;
-	unsigned long status;
-	unsigned long old_flags;
-	unsigned long saved_flags;
-};
-
-/* per-cpu kprobe control block */
-struct kprobe_ctlblk {
-	unsigned long kprobe_status;
-	unsigned long kprobe_old_flags;
-	unsigned long kprobe_saved_flags;
-	unsigned long *jprobe_saved_sp;
-	struct pt_regs jprobe_saved_regs;
-	kprobe_opcode_t jprobes_stack[MAX_STACK_SIZE];
-	struct prev_kprobe prev_kprobe;
-};
-
-extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
-extern int kprobe_exceptions_notify(struct notifier_block *self,
-				    unsigned long val, void *data);
-#endif /* ASM_X86__KPROBES_H */
diff --git a/include/asm-x86/kvm.h b/include/asm-x86/kvm.h
deleted file mode 100644
index 78e954db1e7f..000000000000
--- a/include/asm-x86/kvm.h
+++ /dev/null
@@ -1,233 +0,0 @@
-#ifndef ASM_X86__KVM_H
-#define ASM_X86__KVM_H
-
-/*
- * KVM x86 specific structures and definitions
- *
- */
-
-#include <asm/types.h>
-#include <linux/ioctl.h>
-
-/* Architectural interrupt line count. */
-#define KVM_NR_INTERRUPTS 256
-
-struct kvm_memory_alias {
-	__u32 slot;  /* this has a different namespace than memory slots */
-	__u32 flags;
-	__u64 guest_phys_addr;
-	__u64 memory_size;
-	__u64 target_phys_addr;
-};
-
-/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
-struct kvm_pic_state {
-	__u8 last_irr;	/* edge detection */
-	__u8 irr;		/* interrupt request register */
-	__u8 imr;		/* interrupt mask register */
-	__u8 isr;		/* interrupt service register */
-	__u8 priority_add;	/* highest irq priority */
-	__u8 irq_base;
-	__u8 read_reg_select;
-	__u8 poll;
-	__u8 special_mask;
-	__u8 init_state;
-	__u8 auto_eoi;
-	__u8 rotate_on_auto_eoi;
-	__u8 special_fully_nested_mode;
-	__u8 init4;		/* true if 4 byte init */
-	__u8 elcr;		/* PIIX edge/trigger selection */
-	__u8 elcr_mask;
-};
-
-#define KVM_IOAPIC_NUM_PINS  24
-struct kvm_ioapic_state {
-	__u64 base_address;
-	__u32 ioregsel;
-	__u32 id;
-	__u32 irr;
-	__u32 pad;
-	union {
-		__u64 bits;
-		struct {
-			__u8 vector;
-			__u8 delivery_mode:3;
-			__u8 dest_mode:1;
-			__u8 delivery_status:1;
-			__u8 polarity:1;
-			__u8 remote_irr:1;
-			__u8 trig_mode:1;
-			__u8 mask:1;
-			__u8 reserve:7;
-			__u8 reserved[4];
-			__u8 dest_id;
-		} fields;
-	} redirtbl[KVM_IOAPIC_NUM_PINS];
-};
-
-#define KVM_IRQCHIP_PIC_MASTER   0
-#define KVM_IRQCHIP_PIC_SLAVE    1
-#define KVM_IRQCHIP_IOAPIC       2
-
-/* for KVM_GET_REGS and KVM_SET_REGS */
-struct kvm_regs {
-	/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
-	__u64 rax, rbx, rcx, rdx;
-	__u64 rsi, rdi, rsp, rbp;
-	__u64 r8,  r9,  r10, r11;
-	__u64 r12, r13, r14, r15;
-	__u64 rip, rflags;
-};
-
-/* for KVM_GET_LAPIC and KVM_SET_LAPIC */
-#define KVM_APIC_REG_SIZE 0x400
-struct kvm_lapic_state {
-	char regs[KVM_APIC_REG_SIZE];
-};
-
-struct kvm_segment {
-	__u64 base;
-	__u32 limit;
-	__u16 selector;
-	__u8  type;
-	__u8  present, dpl, db, s, l, g, avl;
-	__u8  unusable;
-	__u8  padding;
-};
-
-struct kvm_dtable {
-	__u64 base;
-	__u16 limit;
-	__u16 padding[3];
-};
-
-
-/* for KVM_GET_SREGS and KVM_SET_SREGS */
-struct kvm_sregs {
-	/* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
-	struct kvm_segment cs, ds, es, fs, gs, ss;
-	struct kvm_segment tr, ldt;
-	struct kvm_dtable gdt, idt;
-	__u64 cr0, cr2, cr3, cr4, cr8;
-	__u64 efer;
-	__u64 apic_base;
-	__u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
-};
-
-/* for KVM_GET_FPU and KVM_SET_FPU */
-struct kvm_fpu {
-	__u8  fpr[8][16];
-	__u16 fcw;
-	__u16 fsw;
-	__u8  ftwx;  /* in fxsave format */
-	__u8  pad1;
-	__u16 last_opcode;
-	__u64 last_ip;
-	__u64 last_dp;
-	__u8  xmm[16][16];
-	__u32 mxcsr;
-	__u32 pad2;
-};
-
-struct kvm_msr_entry {
-	__u32 index;
-	__u32 reserved;
-	__u64 data;
-};
-
-/* for KVM_GET_MSRS and KVM_SET_MSRS */
-struct kvm_msrs {
-	__u32 nmsrs; /* number of msrs in entries */
-	__u32 pad;
-
-	struct kvm_msr_entry entries[0];
-};
-
-/* for KVM_GET_MSR_INDEX_LIST */
-struct kvm_msr_list {
-	__u32 nmsrs; /* number of msrs in entries */
-	__u32 indices[0];
-};
-
-
-struct kvm_cpuid_entry {
-	__u32 function;
-	__u32 eax;
-	__u32 ebx;
-	__u32 ecx;
-	__u32 edx;
-	__u32 padding;
-};
-
-/* for KVM_SET_CPUID */
-struct kvm_cpuid {
-	__u32 nent;
-	__u32 padding;
-	struct kvm_cpuid_entry entries[0];
-};
-
-struct kvm_cpuid_entry2 {
-	__u32 function;
-	__u32 index;
-	__u32 flags;
-	__u32 eax;
-	__u32 ebx;
-	__u32 ecx;
-	__u32 edx;
-	__u32 padding[3];
-};
-
-#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1
-#define KVM_CPUID_FLAG_STATEFUL_FUNC    2
-#define KVM_CPUID_FLAG_STATE_READ_NEXT  4
-
-/* for KVM_SET_CPUID2 */
-struct kvm_cpuid2 {
-	__u32 nent;
-	__u32 padding;
-	struct kvm_cpuid_entry2 entries[0];
-};
-
-/* for KVM_GET_PIT and KVM_SET_PIT */
-struct kvm_pit_channel_state {
-	__u32 count; /* can be 65536 */
-	__u16 latched_count;
-	__u8 count_latched;
-	__u8 status_latched;
-	__u8 status;
-	__u8 read_state;
-	__u8 write_state;
-	__u8 write_latch;
-	__u8 rw_mode;
-	__u8 mode;
-	__u8 bcd;
-	__u8 gate;
-	__s64 count_load_time;
-};
-
-struct kvm_pit_state {
-	struct kvm_pit_channel_state channels[3];
-};
-
-#define KVM_TRC_INJ_VIRQ         (KVM_TRC_HANDLER + 0x02)
-#define KVM_TRC_REDELIVER_EVT    (KVM_TRC_HANDLER + 0x03)
-#define KVM_TRC_PEND_INTR        (KVM_TRC_HANDLER + 0x04)
-#define KVM_TRC_IO_READ          (KVM_TRC_HANDLER + 0x05)
-#define KVM_TRC_IO_WRITE         (KVM_TRC_HANDLER + 0x06)
-#define KVM_TRC_CR_READ          (KVM_TRC_HANDLER + 0x07)
-#define KVM_TRC_CR_WRITE         (KVM_TRC_HANDLER + 0x08)
-#define KVM_TRC_DR_READ          (KVM_TRC_HANDLER + 0x09)
-#define KVM_TRC_DR_WRITE         (KVM_TRC_HANDLER + 0x0A)
-#define KVM_TRC_MSR_READ         (KVM_TRC_HANDLER + 0x0B)
-#define KVM_TRC_MSR_WRITE        (KVM_TRC_HANDLER + 0x0C)
-#define KVM_TRC_CPUID            (KVM_TRC_HANDLER + 0x0D)
-#define KVM_TRC_INTR             (KVM_TRC_HANDLER + 0x0E)
-#define KVM_TRC_NMI              (KVM_TRC_HANDLER + 0x0F)
-#define KVM_TRC_VMMCALL          (KVM_TRC_HANDLER + 0x10)
-#define KVM_TRC_HLT              (KVM_TRC_HANDLER + 0x11)
-#define KVM_TRC_CLTS             (KVM_TRC_HANDLER + 0x12)
-#define KVM_TRC_LMSW             (KVM_TRC_HANDLER + 0x13)
-#define KVM_TRC_APIC_ACCESS      (KVM_TRC_HANDLER + 0x14)
-#define KVM_TRC_TDP_FAULT        (KVM_TRC_HANDLER + 0x15)
-
-#endif /* ASM_X86__KVM_H */
diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h
deleted file mode 100644
index 69794547f514..000000000000
--- a/include/asm-x86/kvm_host.h
+++ /dev/null
@@ -1,738 +0,0 @@
-/*
- * Kernel-based Virtual Machine driver for Linux
- *
- * This header defines architecture specific interfaces, x86 version
- *
- * This work is licensed under the terms of the GNU GPL, version 2.  See
- * the COPYING file in the top-level directory.
- *
- */
-
-#ifndef ASM_X86__KVM_HOST_H
-#define ASM_X86__KVM_HOST_H
-
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/mmu_notifier.h>
-
-#include <linux/kvm.h>
-#include <linux/kvm_para.h>
-#include <linux/kvm_types.h>
-
-#include <asm/pvclock-abi.h>
-#include <asm/desc.h>
-
-#define KVM_MAX_VCPUS 16
-#define KVM_MEMORY_SLOTS 32
-/* memory slots that does not exposed to userspace */
-#define KVM_PRIVATE_MEM_SLOTS 4
-
-#define KVM_PIO_PAGE_OFFSET 1
-#define KVM_COALESCED_MMIO_PAGE_OFFSET 2
-
-#define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1)
-#define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD))
-#define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS |	\
-				  0xFFFFFF0000000000ULL)
-
-#define KVM_GUEST_CR0_MASK				   \
-	(X86_CR0_PG | X86_CR0_PE | X86_CR0_WP | X86_CR0_NE \
-	 | X86_CR0_NW | X86_CR0_CD)
-#define KVM_VM_CR0_ALWAYS_ON						\
-	(X86_CR0_PG | X86_CR0_PE | X86_CR0_WP | X86_CR0_NE | X86_CR0_TS \
-	 | X86_CR0_MP)
-#define KVM_GUEST_CR4_MASK						\
-	(X86_CR4_VME | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_PGE | X86_CR4_VMXE)
-#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
-#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
-
-#define INVALID_PAGE (~(hpa_t)0)
-#define UNMAPPED_GVA (~(gpa_t)0)
-
-/* shadow tables are PAE even on non-PAE hosts */
-#define KVM_HPAGE_SHIFT 21
-#define KVM_HPAGE_SIZE (1UL << KVM_HPAGE_SHIFT)
-#define KVM_HPAGE_MASK (~(KVM_HPAGE_SIZE - 1))
-
-#define KVM_PAGES_PER_HPAGE (KVM_HPAGE_SIZE / PAGE_SIZE)
-
-#define DE_VECTOR 0
-#define UD_VECTOR 6
-#define NM_VECTOR 7
-#define DF_VECTOR 8
-#define TS_VECTOR 10
-#define NP_VECTOR 11
-#define SS_VECTOR 12
-#define GP_VECTOR 13
-#define PF_VECTOR 14
-#define MC_VECTOR 18
-
-#define SELECTOR_TI_MASK (1 << 2)
-#define SELECTOR_RPL_MASK 0x03
-
-#define IOPL_SHIFT 12
-
-#define KVM_ALIAS_SLOTS 4
-
-#define KVM_PERMILLE_MMU_PAGES 20
-#define KVM_MIN_ALLOC_MMU_PAGES 64
-#define KVM_MMU_HASH_SHIFT 10
-#define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT)
-#define KVM_MIN_FREE_MMU_PAGES 5
-#define KVM_REFILL_PAGES 25
-#define KVM_MAX_CPUID_ENTRIES 40
-#define KVM_NR_VAR_MTRR 8
-
-extern spinlock_t kvm_lock;
-extern struct list_head vm_list;
-
-struct kvm_vcpu;
-struct kvm;
-
-enum {
-	VCPU_REGS_RAX = 0,
-	VCPU_REGS_RCX = 1,
-	VCPU_REGS_RDX = 2,
-	VCPU_REGS_RBX = 3,
-	VCPU_REGS_RSP = 4,
-	VCPU_REGS_RBP = 5,
-	VCPU_REGS_RSI = 6,
-	VCPU_REGS_RDI = 7,
-#ifdef CONFIG_X86_64
-	VCPU_REGS_R8 = 8,
-	VCPU_REGS_R9 = 9,
-	VCPU_REGS_R10 = 10,
-	VCPU_REGS_R11 = 11,
-	VCPU_REGS_R12 = 12,
-	VCPU_REGS_R13 = 13,
-	VCPU_REGS_R14 = 14,
-	VCPU_REGS_R15 = 15,
-#endif
-	NR_VCPU_REGS
-};
-
-enum {
-	VCPU_SREG_ES,
-	VCPU_SREG_CS,
-	VCPU_SREG_SS,
-	VCPU_SREG_DS,
-	VCPU_SREG_FS,
-	VCPU_SREG_GS,
-	VCPU_SREG_TR,
-	VCPU_SREG_LDTR,
-};
-
-#include <asm/kvm_x86_emulate.h>
-
-#define KVM_NR_MEM_OBJS 40
-
-struct kvm_guest_debug {
-	int enabled;
-	unsigned long bp[4];
-	int singlestep;
-};
-
-/*
- * We don't want allocation failures within the mmu code, so we preallocate
- * enough memory for a single page fault in a cache.
- */
-struct kvm_mmu_memory_cache {
-	int nobjs;
-	void *objects[KVM_NR_MEM_OBJS];
-};
-
-#define NR_PTE_CHAIN_ENTRIES 5
-
-struct kvm_pte_chain {
-	u64 *parent_ptes[NR_PTE_CHAIN_ENTRIES];
-	struct hlist_node link;
-};
-
-/*
- * kvm_mmu_page_role, below, is defined as:
- *
- *   bits 0:3 - total guest paging levels (2-4, or zero for real mode)
- *   bits 4:7 - page table level for this shadow (1-4)
- *   bits 8:9 - page table quadrant for 2-level guests
- *   bit   16 - "metaphysical" - gfn is not a real page (huge page/real mode)
- *   bits 17:19 - common access permissions for all ptes in this shadow page
- */
-union kvm_mmu_page_role {
-	unsigned word;
-	struct {
-		unsigned glevels:4;
-		unsigned level:4;
-		unsigned quadrant:2;
-		unsigned pad_for_nice_hex_output:6;
-		unsigned metaphysical:1;
-		unsigned access:3;
-		unsigned invalid:1;
-	};
-};
-
-struct kvm_mmu_page {
-	struct list_head link;
-	struct hlist_node hash_link;
-
-	/*
-	 * The following two entries are used to key the shadow page in the
-	 * hash table.
-	 */
-	gfn_t gfn;
-	union kvm_mmu_page_role role;
-
-	u64 *spt;
-	/* hold the gfn of each spte inside spt */
-	gfn_t *gfns;
-	unsigned long slot_bitmap; /* One bit set per slot which has memory
-				    * in this shadow page.
-				    */
-	int multimapped;         /* More than one parent_pte? */
-	int root_count;          /* Currently serving as active root */
-	union {
-		u64 *parent_pte;               /* !multimapped */
-		struct hlist_head parent_ptes; /* multimapped, kvm_pte_chain */
-	};
-};
-
-/*
- * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level
- * 32-bit).  The kvm_mmu structure abstracts the details of the current mmu
- * mode.
- */
-struct kvm_mmu {
-	void (*new_cr3)(struct kvm_vcpu *vcpu);
-	int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err);
-	void (*free)(struct kvm_vcpu *vcpu);
-	gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva);
-	void (*prefetch_page)(struct kvm_vcpu *vcpu,
-			      struct kvm_mmu_page *page);
-	hpa_t root_hpa;
-	int root_level;
-	int shadow_root_level;
-
-	u64 *pae_root;
-};
-
-struct kvm_vcpu_arch {
-	u64 host_tsc;
-	int interrupt_window_open;
-	unsigned long irq_summary; /* bit vector: 1 per word in irq_pending */
-	DECLARE_BITMAP(irq_pending, KVM_NR_INTERRUPTS);
-	unsigned long regs[NR_VCPU_REGS]; /* for rsp: vcpu_load_rsp_rip() */
-	unsigned long rip;      /* needs vcpu_load_rsp_rip() */
-
-	unsigned long cr0;
-	unsigned long cr2;
-	unsigned long cr3;
-	unsigned long cr4;
-	unsigned long cr8;
-	u64 pdptrs[4]; /* pae */
-	u64 shadow_efer;
-	u64 apic_base;
-	struct kvm_lapic *apic;    /* kernel irqchip context */
-	int mp_state;
-	int sipi_vector;
-	u64 ia32_misc_enable_msr;
-	bool tpr_access_reporting;
-
-	struct kvm_mmu mmu;
-
-	struct kvm_mmu_memory_cache mmu_pte_chain_cache;
-	struct kvm_mmu_memory_cache mmu_rmap_desc_cache;
-	struct kvm_mmu_memory_cache mmu_page_cache;
-	struct kvm_mmu_memory_cache mmu_page_header_cache;
-
-	gfn_t last_pt_write_gfn;
-	int   last_pt_write_count;
-	u64  *last_pte_updated;
-	gfn_t last_pte_gfn;
-
-	struct {
-		gfn_t gfn;	/* presumed gfn during guest pte update */
-		pfn_t pfn;	/* pfn corresponding to that gfn */
-		int largepage;
-		unsigned long mmu_seq;
-	} update_pte;
-
-	struct i387_fxsave_struct host_fx_image;
-	struct i387_fxsave_struct guest_fx_image;
-
-	gva_t mmio_fault_cr2;
-	struct kvm_pio_request pio;
-	void *pio_data;
-
-	struct kvm_queued_exception {
-		bool pending;
-		bool has_error_code;
-		u8 nr;
-		u32 error_code;
-	} exception;
-
-	struct {
-		int active;
-		u8 save_iopl;
-		struct kvm_save_segment {
-			u16 selector;
-			unsigned long base;
-			u32 limit;
-			u32 ar;
-		} tr, es, ds, fs, gs;
-	} rmode;
-	int halt_request; /* real mode on Intel only */
-
-	int cpuid_nent;
-	struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES];
-	/* emulate context */
-
-	struct x86_emulate_ctxt emulate_ctxt;
-
-	gpa_t time;
-	struct pvclock_vcpu_time_info hv_clock;
-	unsigned int hv_clock_tsc_khz;
-	unsigned int time_offset;
-	struct page *time_page;
-
-	bool nmi_pending;
-
-	u64 mtrr[0x100];
-};
-
-struct kvm_mem_alias {
-	gfn_t base_gfn;
-	unsigned long npages;
-	gfn_t target_gfn;
-};
-
-struct kvm_arch{
-	int naliases;
-	struct kvm_mem_alias aliases[KVM_ALIAS_SLOTS];
-
-	unsigned int n_free_mmu_pages;
-	unsigned int n_requested_mmu_pages;
-	unsigned int n_alloc_mmu_pages;
-	struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
-	/*
-	 * Hash table of struct kvm_mmu_page.
-	 */
-	struct list_head active_mmu_pages;
-	struct kvm_pic *vpic;
-	struct kvm_ioapic *vioapic;
-	struct kvm_pit *vpit;
-
-	int round_robin_prev_vcpu;
-	unsigned int tss_addr;
-	struct page *apic_access_page;
-
-	gpa_t wall_clock;
-
-	struct page *ept_identity_pagetable;
-	bool ept_identity_pagetable_done;
-};
-
-struct kvm_vm_stat {
-	u32 mmu_shadow_zapped;
-	u32 mmu_pte_write;
-	u32 mmu_pte_updated;
-	u32 mmu_pde_zapped;
-	u32 mmu_flooded;
-	u32 mmu_recycled;
-	u32 mmu_cache_miss;
-	u32 remote_tlb_flush;
-	u32 lpages;
-};
-
-struct kvm_vcpu_stat {
-	u32 pf_fixed;
-	u32 pf_guest;
-	u32 tlb_flush;
-	u32 invlpg;
-
-	u32 exits;
-	u32 io_exits;
-	u32 mmio_exits;
-	u32 signal_exits;
-	u32 irq_window_exits;
-	u32 nmi_window_exits;
-	u32 halt_exits;
-	u32 halt_wakeup;
-	u32 request_irq_exits;
-	u32 irq_exits;
-	u32 host_state_reload;
-	u32 efer_reload;
-	u32 fpu_reload;
-	u32 insn_emulation;
-	u32 insn_emulation_fail;
-	u32 hypercalls;
-};
-
-struct descriptor_table {
-	u16 limit;
-	unsigned long base;
-} __attribute__((packed));
-
-struct kvm_x86_ops {
-	int (*cpu_has_kvm_support)(void);          /* __init */
-	int (*disabled_by_bios)(void);             /* __init */
-	void (*hardware_enable)(void *dummy);      /* __init */
-	void (*hardware_disable)(void *dummy);
-	void (*check_processor_compatibility)(void *rtn);
-	int (*hardware_setup)(void);               /* __init */
-	void (*hardware_unsetup)(void);            /* __exit */
-	bool (*cpu_has_accelerated_tpr)(void);
-
-	/* Create, but do not attach this VCPU */
-	struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id);
-	void (*vcpu_free)(struct kvm_vcpu *vcpu);
-	int (*vcpu_reset)(struct kvm_vcpu *vcpu);
-
-	void (*prepare_guest_switch)(struct kvm_vcpu *vcpu);
-	void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
-	void (*vcpu_put)(struct kvm_vcpu *vcpu);
-
-	int (*set_guest_debug)(struct kvm_vcpu *vcpu,
-			       struct kvm_debug_guest *dbg);
-	void (*guest_debug_pre)(struct kvm_vcpu *vcpu);
-	int (*get_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata);
-	int (*set_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 data);
-	u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg);
-	void (*get_segment)(struct kvm_vcpu *vcpu,
-			    struct kvm_segment *var, int seg);
-	int (*get_cpl)(struct kvm_vcpu *vcpu);
-	void (*set_segment)(struct kvm_vcpu *vcpu,
-			    struct kvm_segment *var, int seg);
-	void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l);
-	void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu);
-	void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
-	void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
-	void (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
-	void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer);
-	void (*get_idt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt);
-	void (*set_idt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt);
-	void (*get_gdt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt);
-	void (*set_gdt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt);
-	unsigned long (*get_dr)(struct kvm_vcpu *vcpu, int dr);
-	void (*set_dr)(struct kvm_vcpu *vcpu, int dr, unsigned long value,
-		       int *exception);
-	void (*cache_regs)(struct kvm_vcpu *vcpu);
-	void (*decache_regs)(struct kvm_vcpu *vcpu);
-	unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
-	void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags);
-
-	void (*tlb_flush)(struct kvm_vcpu *vcpu);
-
-	void (*run)(struct kvm_vcpu *vcpu, struct kvm_run *run);
-	int (*handle_exit)(struct kvm_run *run, struct kvm_vcpu *vcpu);
-	void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu);
-	void (*patch_hypercall)(struct kvm_vcpu *vcpu,
-				unsigned char *hypercall_addr);
-	int (*get_irq)(struct kvm_vcpu *vcpu);
-	void (*set_irq)(struct kvm_vcpu *vcpu, int vec);
-	void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr,
-				bool has_error_code, u32 error_code);
-	bool (*exception_injected)(struct kvm_vcpu *vcpu);
-	void (*inject_pending_irq)(struct kvm_vcpu *vcpu);
-	void (*inject_pending_vectors)(struct kvm_vcpu *vcpu,
-				       struct kvm_run *run);
-
-	int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
-	int (*get_tdp_level)(void);
-};
-
-extern struct kvm_x86_ops *kvm_x86_ops;
-
-int kvm_mmu_module_init(void);
-void kvm_mmu_module_exit(void);
-
-void kvm_mmu_destroy(struct kvm_vcpu *vcpu);
-int kvm_mmu_create(struct kvm_vcpu *vcpu);
-int kvm_mmu_setup(struct kvm_vcpu *vcpu);
-void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte);
-void kvm_mmu_set_base_ptes(u64 base_pte);
-void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
-		u64 dirty_mask, u64 nx_mask, u64 x_mask);
-
-int kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
-void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot);
-void kvm_mmu_zap_all(struct kvm *kvm);
-unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm);
-void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages);
-
-int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3);
-
-int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
-			  const void *val, int bytes);
-int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
-		  gpa_t addr, unsigned long *ret);
-
-extern bool tdp_enabled;
-
-enum emulation_result {
-	EMULATE_DONE,       /* no further processing */
-	EMULATE_DO_MMIO,      /* kvm_run filled with mmio request */
-	EMULATE_FAIL,         /* can't emulate this instruction */
-};
-
-#define EMULTYPE_NO_DECODE	    (1 << 0)
-#define EMULTYPE_TRAP_UD	    (1 << 1)
-int emulate_instruction(struct kvm_vcpu *vcpu, struct kvm_run *run,
-			unsigned long cr2, u16 error_code, int emulation_type);
-void kvm_report_emulation_failure(struct kvm_vcpu *cvpu, const char *context);
-void realmode_lgdt(struct kvm_vcpu *vcpu, u16 size, unsigned long address);
-void realmode_lidt(struct kvm_vcpu *vcpu, u16 size, unsigned long address);
-void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
-		   unsigned long *rflags);
-
-unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr);
-void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long value,
-		     unsigned long *rflags);
-void kvm_enable_efer_bits(u64);
-int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *data);
-int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data);
-
-struct x86_emulate_ctxt;
-
-int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
-		     int size, unsigned port);
-int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
-			   int size, unsigned long count, int down,
-			    gva_t address, int rep, unsigned port);
-void kvm_emulate_cpuid(struct kvm_vcpu *vcpu);
-int kvm_emulate_halt(struct kvm_vcpu *vcpu);
-int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address);
-int emulate_clts(struct kvm_vcpu *vcpu);
-int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
-		    unsigned long *dest);
-int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
-		    unsigned long value);
-
-void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
-int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
-				int type_bits, int seg);
-
-int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason);
-
-void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
-void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
-void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
-void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8);
-unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu);
-void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw);
-void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l);
-
-int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
-int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data);
-
-void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr);
-void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
-void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long cr2,
-			   u32 error_code);
-
-void kvm_inject_nmi(struct kvm_vcpu *vcpu);
-
-void fx_init(struct kvm_vcpu *vcpu);
-
-int emulator_read_std(unsigned long addr,
-		      void *val,
-		      unsigned int bytes,
-		      struct kvm_vcpu *vcpu);
-int emulator_write_emulated(unsigned long addr,
-			    const void *val,
-			    unsigned int bytes,
-			    struct kvm_vcpu *vcpu);
-
-unsigned long segment_base(u16 selector);
-
-void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu);
-void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
-		       const u8 *new, int bytes);
-int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva);
-void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu);
-int kvm_mmu_load(struct kvm_vcpu *vcpu);
-void kvm_mmu_unload(struct kvm_vcpu *vcpu);
-
-int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
-
-int kvm_fix_hypercall(struct kvm_vcpu *vcpu);
-
-int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code);
-
-void kvm_enable_tdp(void);
-void kvm_disable_tdp(void);
-
-int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3);
-int complete_pio(struct kvm_vcpu *vcpu);
-
-static inline struct kvm_mmu_page *page_header(hpa_t shadow_page)
-{
-	struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT);
-
-	return (struct kvm_mmu_page *)page_private(page);
-}
-
-static inline u16 kvm_read_fs(void)
-{
-	u16 seg;
-	asm("mov %%fs, %0" : "=g"(seg));
-	return seg;
-}
-
-static inline u16 kvm_read_gs(void)
-{
-	u16 seg;
-	asm("mov %%gs, %0" : "=g"(seg));
-	return seg;
-}
-
-static inline u16 kvm_read_ldt(void)
-{
-	u16 ldt;
-	asm("sldt %0" : "=g"(ldt));
-	return ldt;
-}
-
-static inline void kvm_load_fs(u16 sel)
-{
-	asm("mov %0, %%fs" : : "rm"(sel));
-}
-
-static inline void kvm_load_gs(u16 sel)
-{
-	asm("mov %0, %%gs" : : "rm"(sel));
-}
-
-static inline void kvm_load_ldt(u16 sel)
-{
-	asm("lldt %0" : : "rm"(sel));
-}
-
-static inline void kvm_get_idt(struct descriptor_table *table)
-{
-	asm("sidt %0" : "=m"(*table));
-}
-
-static inline void kvm_get_gdt(struct descriptor_table *table)
-{
-	asm("sgdt %0" : "=m"(*table));
-}
-
-static inline unsigned long kvm_read_tr_base(void)
-{
-	u16 tr;
-	asm("str %0" : "=g"(tr));
-	return segment_base(tr);
-}
-
-#ifdef CONFIG_X86_64
-static inline unsigned long read_msr(unsigned long msr)
-{
-	u64 value;
-
-	rdmsrl(msr, value);
-	return value;
-}
-#endif
-
-static inline void kvm_fx_save(struct i387_fxsave_struct *image)
-{
-	asm("fxsave (%0)":: "r" (image));
-}
-
-static inline void kvm_fx_restore(struct i387_fxsave_struct *image)
-{
-	asm("fxrstor (%0)":: "r" (image));
-}
-
-static inline void kvm_fx_finit(void)
-{
-	asm("finit");
-}
-
-static inline u32 get_rdx_init_val(void)
-{
-	return 0x600; /* P6 family */
-}
-
-static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code)
-{
-	kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
-}
-
-#define ASM_VMX_VMCLEAR_RAX       ".byte 0x66, 0x0f, 0xc7, 0x30"
-#define ASM_VMX_VMLAUNCH          ".byte 0x0f, 0x01, 0xc2"
-#define ASM_VMX_VMRESUME          ".byte 0x0f, 0x01, 0xc3"
-#define ASM_VMX_VMPTRLD_RAX       ".byte 0x0f, 0xc7, 0x30"
-#define ASM_VMX_VMREAD_RDX_RAX    ".byte 0x0f, 0x78, 0xd0"
-#define ASM_VMX_VMWRITE_RAX_RDX   ".byte 0x0f, 0x79, 0xd0"
-#define ASM_VMX_VMWRITE_RSP_RDX   ".byte 0x0f, 0x79, 0xd4"
-#define ASM_VMX_VMXOFF            ".byte 0x0f, 0x01, 0xc4"
-#define ASM_VMX_VMXON_RAX         ".byte 0xf3, 0x0f, 0xc7, 0x30"
-#define ASM_VMX_INVEPT		  ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
-#define ASM_VMX_INVVPID		  ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
-
-#define MSR_IA32_TIME_STAMP_COUNTER		0x010
-
-#define TSS_IOPB_BASE_OFFSET 0x66
-#define TSS_BASE_SIZE 0x68
-#define TSS_IOPB_SIZE (65536 / 8)
-#define TSS_REDIRECTION_SIZE (256 / 8)
-#define RMODE_TSS_SIZE							\
-	(TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1)
-
-enum {
-	TASK_SWITCH_CALL = 0,
-	TASK_SWITCH_IRET = 1,
-	TASK_SWITCH_JMP = 2,
-	TASK_SWITCH_GATE = 3,
-};
-
-#define KVMTRACE_5D(evt, vcpu, d1, d2, d3, d4, d5, name) \
-	trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
-						vcpu, 5, d1, d2, d3, d4, d5)
-#define KVMTRACE_4D(evt, vcpu, d1, d2, d3, d4, name) \
-	trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
-						vcpu, 4, d1, d2, d3, d4, 0)
-#define KVMTRACE_3D(evt, vcpu, d1, d2, d3, name) \
-	trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
-						vcpu, 3, d1, d2, d3, 0, 0)
-#define KVMTRACE_2D(evt, vcpu, d1, d2, name) \
-	trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
-						vcpu, 2, d1, d2, 0, 0, 0)
-#define KVMTRACE_1D(evt, vcpu, d1, name) \
-	trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
-						vcpu, 1, d1, 0, 0, 0, 0)
-#define KVMTRACE_0D(evt, vcpu, name) \
-	trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
-						vcpu, 0, 0, 0, 0, 0, 0)
-
-#ifdef CONFIG_64BIT
-# define KVM_EX_ENTRY ".quad"
-# define KVM_EX_PUSH "pushq"
-#else
-# define KVM_EX_ENTRY ".long"
-# define KVM_EX_PUSH "pushl"
-#endif
-
-/*
- * Hardware virtualization extension instructions may fault if a
- * reboot turns off virtualization while processes are running.
- * Trap the fault and ignore the instruction if that happens.
- */
-asmlinkage void kvm_handle_fault_on_reboot(void);
-
-#define __kvm_handle_fault_on_reboot(insn) \
-	"666: " insn "\n\t" \
-	".pushsection .fixup, \"ax\" \n" \
-	"667: \n\t" \
-	KVM_EX_PUSH " $666b \n\t" \
-	"jmp kvm_handle_fault_on_reboot \n\t" \
-	".popsection \n\t" \
-	".pushsection __ex_table, \"a\" \n\t" \
-	KVM_EX_ENTRY " 666b, 667b \n\t" \
-	".popsection"
-
-#define KVM_ARCH_WANT_MMU_NOTIFIER
-int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
-int kvm_age_hva(struct kvm *kvm, unsigned long hva);
-
-#endif /* ASM_X86__KVM_HOST_H */
diff --git a/include/asm-x86/kvm_para.h b/include/asm-x86/kvm_para.h
deleted file mode 100644
index 30054fded4fb..000000000000
--- a/include/asm-x86/kvm_para.h
+++ /dev/null
@@ -1,147 +0,0 @@
-#ifndef ASM_X86__KVM_PARA_H
-#define ASM_X86__KVM_PARA_H
-
-/* This CPUID returns the signature 'KVMKVMKVM' in ebx, ecx, and edx.  It
- * should be used to determine that a VM is running under KVM.
- */
-#define KVM_CPUID_SIGNATURE	0x40000000
-
-/* This CPUID returns a feature bitmap in eax.  Before enabling a particular
- * paravirtualization, the appropriate feature bit should be checked.
- */
-#define KVM_CPUID_FEATURES	0x40000001
-#define KVM_FEATURE_CLOCKSOURCE		0
-#define KVM_FEATURE_NOP_IO_DELAY	1
-#define KVM_FEATURE_MMU_OP		2
-
-#define MSR_KVM_WALL_CLOCK  0x11
-#define MSR_KVM_SYSTEM_TIME 0x12
-
-#define KVM_MAX_MMU_OP_BATCH           32
-
-/* Operations for KVM_HC_MMU_OP */
-#define KVM_MMU_OP_WRITE_PTE            1
-#define KVM_MMU_OP_FLUSH_TLB	        2
-#define KVM_MMU_OP_RELEASE_PT	        3
-
-/* Payload for KVM_HC_MMU_OP */
-struct kvm_mmu_op_header {
-	__u32 op;
-	__u32 pad;
-};
-
-struct kvm_mmu_op_write_pte {
-	struct kvm_mmu_op_header header;
-	__u64 pte_phys;
-	__u64 pte_val;
-};
-
-struct kvm_mmu_op_flush_tlb {
-	struct kvm_mmu_op_header header;
-};
-
-struct kvm_mmu_op_release_pt {
-	struct kvm_mmu_op_header header;
-	__u64 pt_phys;
-};
-
-#ifdef __KERNEL__
-#include <asm/processor.h>
-
-extern void kvmclock_init(void);
-
-
-/* This instruction is vmcall.  On non-VT architectures, it will generate a
- * trap that we will then rewrite to the appropriate instruction.
- */
-#define KVM_HYPERCALL ".byte 0x0f,0x01,0xc1"
-
-/* For KVM hypercalls, a three-byte sequence of either the vmrun or the vmmrun
- * instruction.  The hypervisor may replace it with something else but only the
- * instructions are guaranteed to be supported.
- *
- * Up to four arguments may be passed in rbx, rcx, rdx, and rsi respectively.
- * The hypercall number should be placed in rax and the return value will be
- * placed in rax.  No other registers will be clobbered unless explicited
- * noted by the particular hypercall.
- */
-
-static inline long kvm_hypercall0(unsigned int nr)
-{
-	long ret;
-	asm volatile(KVM_HYPERCALL
-		     : "=a"(ret)
-		     : "a"(nr)
-		     : "memory");
-	return ret;
-}
-
-static inline long kvm_hypercall1(unsigned int nr, unsigned long p1)
-{
-	long ret;
-	asm volatile(KVM_HYPERCALL
-		     : "=a"(ret)
-		     : "a"(nr), "b"(p1)
-		     : "memory");
-	return ret;
-}
-
-static inline long kvm_hypercall2(unsigned int nr, unsigned long p1,
-				  unsigned long p2)
-{
-	long ret;
-	asm volatile(KVM_HYPERCALL
-		     : "=a"(ret)
-		     : "a"(nr), "b"(p1), "c"(p2)
-		     : "memory");
-	return ret;
-}
-
-static inline long kvm_hypercall3(unsigned int nr, unsigned long p1,
-				  unsigned long p2, unsigned long p3)
-{
-	long ret;
-	asm volatile(KVM_HYPERCALL
-		     : "=a"(ret)
-		     : "a"(nr), "b"(p1), "c"(p2), "d"(p3)
-		     : "memory");
-	return ret;
-}
-
-static inline long kvm_hypercall4(unsigned int nr, unsigned long p1,
-				  unsigned long p2, unsigned long p3,
-				  unsigned long p4)
-{
-	long ret;
-	asm volatile(KVM_HYPERCALL
-		     : "=a"(ret)
-		     : "a"(nr), "b"(p1), "c"(p2), "d"(p3), "S"(p4)
-		     : "memory");
-	return ret;
-}
-
-static inline int kvm_para_available(void)
-{
-	unsigned int eax, ebx, ecx, edx;
-	char signature[13];
-
-	cpuid(KVM_CPUID_SIGNATURE, &eax, &ebx, &ecx, &edx);
-	memcpy(signature + 0, &ebx, 4);
-	memcpy(signature + 4, &ecx, 4);
-	memcpy(signature + 8, &edx, 4);
-	signature[12] = 0;
-
-	if (strcmp(signature, "KVMKVMKVM") == 0)
-		return 1;
-
-	return 0;
-}
-
-static inline unsigned int kvm_arch_para_features(void)
-{
-	return cpuid_eax(KVM_CPUID_FEATURES);
-}
-
-#endif
-
-#endif /* ASM_X86__KVM_PARA_H */
diff --git a/include/asm-x86/kvm_x86_emulate.h b/include/asm-x86/kvm_x86_emulate.h
deleted file mode 100644
index e2d9b030c1ac..000000000000
--- a/include/asm-x86/kvm_x86_emulate.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/******************************************************************************
- * x86_emulate.h
- *
- * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
- *
- * Copyright (c) 2005 Keir Fraser
- *
- * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
- */
-
-#ifndef ASM_X86__KVM_X86_EMULATE_H
-#define ASM_X86__KVM_X86_EMULATE_H
-
-struct x86_emulate_ctxt;
-
-/*
- * x86_emulate_ops:
- *
- * These operations represent the instruction emulator's interface to memory.
- * There are two categories of operation: those that act on ordinary memory
- * regions (*_std), and those that act on memory regions known to require
- * special treatment or emulation (*_emulated).
- *
- * The emulator assumes that an instruction accesses only one 'emulated memory'
- * location, that this location is the given linear faulting address (cr2), and
- * that this is one of the instruction's data operands. Instruction fetches and
- * stack operations are assumed never to access emulated memory. The emulator
- * automatically deduces which operand of a string-move operation is accessing
- * emulated memory, and assumes that the other operand accesses normal memory.
- *
- * NOTES:
- *  1. The emulator isn't very smart about emulated vs. standard memory.
- *     'Emulated memory' access addresses should be checked for sanity.
- *     'Normal memory' accesses may fault, and the caller must arrange to
- *     detect and handle reentrancy into the emulator via recursive faults.
- *     Accesses may be unaligned and may cross page boundaries.
- *  2. If the access fails (cannot emulate, or a standard access faults) then
- *     it is up to the memop to propagate the fault to the guest VM via
- *     some out-of-band mechanism, unknown to the emulator. The memop signals
- *     failure by returning X86EMUL_PROPAGATE_FAULT to the emulator, which will
- *     then immediately bail.
- *  3. Valid access sizes are 1, 2, 4 and 8 bytes. On x86/32 systems only
- *     cmpxchg8b_emulated need support 8-byte accesses.
- *  4. The emulator cannot handle 64-bit mode emulation on an x86/32 system.
- */
-/* Access completed successfully: continue emulation as normal. */
-#define X86EMUL_CONTINUE        0
-/* Access is unhandleable: bail from emulation and return error to caller. */
-#define X86EMUL_UNHANDLEABLE    1
-/* Terminate emulation but return success to the caller. */
-#define X86EMUL_PROPAGATE_FAULT 2 /* propagate a generated fault to guest */
-#define X86EMUL_RETRY_INSTR     2 /* retry the instruction for some reason */
-#define X86EMUL_CMPXCHG_FAILED  2 /* cmpxchg did not see expected value */
-struct x86_emulate_ops {
-	/*
-	 * read_std: Read bytes of standard (non-emulated/special) memory.
-	 *           Used for instruction fetch, stack operations, and others.
-	 *  @addr:  [IN ] Linear address from which to read.
-	 *  @val:   [OUT] Value read from memory, zero-extended to 'u_long'.
-	 *  @bytes: [IN ] Number of bytes to read from memory.
-	 */
-	int (*read_std)(unsigned long addr, void *val,
-			unsigned int bytes, struct kvm_vcpu *vcpu);
-
-	/*
-	 * read_emulated: Read bytes from emulated/special memory area.
-	 *  @addr:  [IN ] Linear address from which to read.
-	 *  @val:   [OUT] Value read from memory, zero-extended to 'u_long'.
-	 *  @bytes: [IN ] Number of bytes to read from memory.
-	 */
-	int (*read_emulated)(unsigned long addr,
-			     void *val,
-			     unsigned int bytes,
-			     struct kvm_vcpu *vcpu);
-
-	/*
-	 * write_emulated: Read bytes from emulated/special memory area.
-	 *  @addr:  [IN ] Linear address to which to write.
-	 *  @val:   [IN ] Value to write to memory (low-order bytes used as
-	 *                required).
-	 *  @bytes: [IN ] Number of bytes to write to memory.
-	 */
-	int (*write_emulated)(unsigned long addr,
-			      const void *val,
-			      unsigned int bytes,
-			      struct kvm_vcpu *vcpu);
-
-	/*
-	 * cmpxchg_emulated: Emulate an atomic (LOCKed) CMPXCHG operation on an
-	 *                   emulated/special memory area.
-	 *  @addr:  [IN ] Linear address to access.
-	 *  @old:   [IN ] Value expected to be current at @addr.
-	 *  @new:   [IN ] Value to write to @addr.
-	 *  @bytes: [IN ] Number of bytes to access using CMPXCHG.
-	 */
-	int (*cmpxchg_emulated)(unsigned long addr,
-				const void *old,
-				const void *new,
-				unsigned int bytes,
-				struct kvm_vcpu *vcpu);
-
-};
-
-/* Type, address-of, and value of an instruction's operand. */
-struct operand {
-	enum { OP_REG, OP_MEM, OP_IMM, OP_NONE } type;
-	unsigned int bytes;
-	unsigned long val, orig_val, *ptr;
-};
-
-struct fetch_cache {
-	u8 data[15];
-	unsigned long start;
-	unsigned long end;
-};
-
-struct decode_cache {
-	u8 twobyte;
-	u8 b;
-	u8 lock_prefix;
-	u8 rep_prefix;
-	u8 op_bytes;
-	u8 ad_bytes;
-	u8 rex_prefix;
-	struct operand src;
-	struct operand dst;
-	bool has_seg_override;
-	u8 seg_override;
-	unsigned int d;
-	unsigned long regs[NR_VCPU_REGS];
-	unsigned long eip;
-	/* modrm */
-	u8 modrm;
-	u8 modrm_mod;
-	u8 modrm_reg;
-	u8 modrm_rm;
-	u8 use_modrm_ea;
-	bool rip_relative;
-	unsigned long modrm_ea;
-	void *modrm_ptr;
-	unsigned long modrm_val;
-	struct fetch_cache fetch;
-};
-
-struct x86_emulate_ctxt {
-	/* Register state before/after emulation. */
-	struct kvm_vcpu *vcpu;
-
-	/* Linear faulting address (if emulating a page-faulting instruction) */
-	unsigned long eflags;
-
-	/* Emulated execution mode, represented by an X86EMUL_MODE value. */
-	int mode;
-
-	u32 cs_base;
-
-	/* decode cache */
-
-	struct decode_cache decode;
-};
-
-/* Repeat String Operation Prefix */
-#define REPE_PREFIX  1
-#define REPNE_PREFIX    2
-
-/* Execution mode, passed to the emulator. */
-#define X86EMUL_MODE_REAL     0	/* Real mode.             */
-#define X86EMUL_MODE_PROT16   2	/* 16-bit protected mode. */
-#define X86EMUL_MODE_PROT32   4	/* 32-bit protected mode. */
-#define X86EMUL_MODE_PROT64   8	/* 64-bit (long) mode.    */
-
-/* Host execution mode. */
-#if defined(__i386__)
-#define X86EMUL_MODE_HOST X86EMUL_MODE_PROT32
-#elif defined(CONFIG_X86_64)
-#define X86EMUL_MODE_HOST X86EMUL_MODE_PROT64
-#endif
-
-int x86_decode_insn(struct x86_emulate_ctxt *ctxt,
-		    struct x86_emulate_ops *ops);
-int x86_emulate_insn(struct x86_emulate_ctxt *ctxt,
-		     struct x86_emulate_ops *ops);
-
-#endif /* ASM_X86__KVM_X86_EMULATE_H */
diff --git a/include/asm-x86/ldt.h b/include/asm-x86/ldt.h
deleted file mode 100644
index a5228504d867..000000000000
--- a/include/asm-x86/ldt.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * ldt.h
- *
- * Definitions of structures used with the modify_ldt system call.
- */
-#ifndef ASM_X86__LDT_H
-#define ASM_X86__LDT_H
-
-/* Maximum number of LDT entries supported. */
-#define LDT_ENTRIES	8192
-/* The size of each LDT entry. */
-#define LDT_ENTRY_SIZE	8
-
-#ifndef __ASSEMBLY__
-/*
- * Note on 64bit base and limit is ignored and you cannot set DS/ES/CS
- * not to the default values if you still want to do syscalls. This
- * call is more for 32bit mode therefore.
- */
-struct user_desc {
-	unsigned int  entry_number;
-	unsigned int  base_addr;
-	unsigned int  limit;
-	unsigned int  seg_32bit:1;
-	unsigned int  contents:2;
-	unsigned int  read_exec_only:1;
-	unsigned int  limit_in_pages:1;
-	unsigned int  seg_not_present:1;
-	unsigned int  useable:1;
-#ifdef __x86_64__
-	unsigned int  lm:1;
-#endif
-};
-
-#define MODIFY_LDT_CONTENTS_DATA	0
-#define MODIFY_LDT_CONTENTS_STACK	1
-#define MODIFY_LDT_CONTENTS_CODE	2
-
-#endif /* !__ASSEMBLY__ */
-#endif /* ASM_X86__LDT_H */
diff --git a/include/asm-x86/lguest.h b/include/asm-x86/lguest.h
deleted file mode 100644
index 7505e947ed27..000000000000
--- a/include/asm-x86/lguest.h
+++ /dev/null
@@ -1,94 +0,0 @@
-#ifndef ASM_X86__LGUEST_H
-#define ASM_X86__LGUEST_H
-
-#define GDT_ENTRY_LGUEST_CS	10
-#define GDT_ENTRY_LGUEST_DS	11
-#define LGUEST_CS		(GDT_ENTRY_LGUEST_CS * 8)
-#define LGUEST_DS		(GDT_ENTRY_LGUEST_DS * 8)
-
-#ifndef __ASSEMBLY__
-#include <asm/desc.h>
-
-#define GUEST_PL 1
-
-/* Every guest maps the core switcher code. */
-#define SHARED_SWITCHER_PAGES \
-	DIV_ROUND_UP(end_switcher_text - start_switcher_text, PAGE_SIZE)
-/* Pages for switcher itself, then two pages per cpu */
-#define TOTAL_SWITCHER_PAGES (SHARED_SWITCHER_PAGES + 2 * NR_CPUS)
-
-/* We map at -4M for ease of mapping into the guest (one PTE page). */
-#define SWITCHER_ADDR 0xFFC00000
-
-/* Found in switcher.S */
-extern unsigned long default_idt_entries[];
-
-/* Declarations for definitions in lguest_guest.S */
-extern char lguest_noirq_start[], lguest_noirq_end[];
-extern const char lgstart_cli[], lgend_cli[];
-extern const char lgstart_sti[], lgend_sti[];
-extern const char lgstart_popf[], lgend_popf[];
-extern const char lgstart_pushf[], lgend_pushf[];
-extern const char lgstart_iret[], lgend_iret[];
-
-extern void lguest_iret(void);
-extern void lguest_init(void);
-
-struct lguest_regs {
-	/* Manually saved part. */
-	unsigned long eax, ebx, ecx, edx;
-	unsigned long esi, edi, ebp;
-	unsigned long gs;
-	unsigned long fs, ds, es;
-	unsigned long trapnum, errcode;
-	/* Trap pushed part */
-	unsigned long eip;
-	unsigned long cs;
-	unsigned long eflags;
-	unsigned long esp;
-	unsigned long ss;
-};
-
-/* This is a guest-specific page (mapped ro) into the guest. */
-struct lguest_ro_state {
-	/* Host information we need to restore when we switch back. */
-	u32 host_cr3;
-	struct desc_ptr host_idt_desc;
-	struct desc_ptr host_gdt_desc;
-	u32 host_sp;
-
-	/* Fields which are used when guest is running. */
-	struct desc_ptr guest_idt_desc;
-	struct desc_ptr guest_gdt_desc;
-	struct x86_hw_tss guest_tss;
-	struct desc_struct guest_idt[IDT_ENTRIES];
-	struct desc_struct guest_gdt[GDT_ENTRIES];
-};
-
-struct lg_cpu_arch {
-	/* The GDT entries copied into lguest_ro_state when running. */
-	struct desc_struct gdt[GDT_ENTRIES];
-
-	/* The IDT entries: some copied into lguest_ro_state when running. */
-	struct desc_struct idt[IDT_ENTRIES];
-
-	/* The address of the last guest-visible pagefault (ie. cr2). */
-	unsigned long last_pagefault;
-};
-
-static inline void lguest_set_ts(void)
-{
-	u32 cr0;
-
-	cr0 = read_cr0();
-	if (!(cr0 & 8))
-		write_cr0(cr0 | 8);
-}
-
-/* Full 4G segment descriptors, suitable for CS and DS. */
-#define FULL_EXEC_SEGMENT ((struct desc_struct){ { {0x0000ffff, 0x00cf9b00} } })
-#define FULL_SEGMENT ((struct desc_struct){ { {0x0000ffff, 0x00cf9300} } })
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* ASM_X86__LGUEST_H */
diff --git a/include/asm-x86/lguest_hcall.h b/include/asm-x86/lguest_hcall.h
deleted file mode 100644
index 8f034ba4b53e..000000000000
--- a/include/asm-x86/lguest_hcall.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Architecture specific portion of the lguest hypercalls */
-#ifndef ASM_X86__LGUEST_HCALL_H
-#define ASM_X86__LGUEST_HCALL_H
-
-#define LHCALL_FLUSH_ASYNC	0
-#define LHCALL_LGUEST_INIT	1
-#define LHCALL_SHUTDOWN		2
-#define LHCALL_LOAD_GDT		3
-#define LHCALL_NEW_PGTABLE	4
-#define LHCALL_FLUSH_TLB	5
-#define LHCALL_LOAD_IDT_ENTRY	6
-#define LHCALL_SET_STACK	7
-#define LHCALL_TS		8
-#define LHCALL_SET_CLOCKEVENT	9
-#define LHCALL_HALT		10
-#define LHCALL_SET_PTE		14
-#define LHCALL_SET_PMD		15
-#define LHCALL_LOAD_TLS		16
-#define LHCALL_NOTIFY		17
-
-#define LGUEST_TRAP_ENTRY 0x1F
-
-/* Argument number 3 to LHCALL_LGUEST_SHUTDOWN */
-#define LGUEST_SHUTDOWN_POWEROFF	1
-#define LGUEST_SHUTDOWN_RESTART		2
-
-#ifndef __ASSEMBLY__
-#include <asm/hw_irq.h>
-
-/*G:031 But first, how does our Guest contact the Host to ask for privileged
- * operations?  There are two ways: the direct way is to make a "hypercall",
- * to make requests of the Host Itself.
- *
- * Our hypercall mechanism uses the highest unused trap code (traps 32 and
- * above are used by real hardware interrupts).  Fifteen hypercalls are
- * available: the hypercall number is put in the %eax register, and the
- * arguments (when required) are placed in %edx, %ebx and %ecx.  If a return
- * value makes sense, it's returned in %eax.
- *
- * Grossly invalid calls result in Sudden Death at the hands of the vengeful
- * Host, rather than returning failure.  This reflects Winston Churchill's
- * definition of a gentleman: "someone who is only rude intentionally". */
-static inline unsigned long
-hcall(unsigned long call,
-      unsigned long arg1, unsigned long arg2, unsigned long arg3)
-{
-	/* "int" is the Intel instruction to trigger a trap. */
-	asm volatile("int $" __stringify(LGUEST_TRAP_ENTRY)
-		     /* The call in %eax (aka "a") might be overwritten */
-		     : "=a"(call)
-		       /* The arguments are in %eax, %edx, %ebx & %ecx */
-		     : "a"(call), "d"(arg1), "b"(arg2), "c"(arg3)
-		       /* "memory" means this might write somewhere in memory.
-			* This isn't true for all calls, but it's safe to tell
-			* gcc that it might happen so it doesn't get clever. */
-		     : "memory");
-	return call;
-}
-/*:*/
-
-/* Can't use our min() macro here: needs to be a constant */
-#define LGUEST_IRQS (NR_IRQS < 32 ? NR_IRQS: 32)
-
-#define LHCALL_RING_SIZE 64
-struct hcall_args {
-	/* These map directly onto eax, ebx, ecx, edx in struct lguest_regs */
-	unsigned long arg0, arg2, arg3, arg1;
-};
-
-#endif /* !__ASSEMBLY__ */
-#endif /* ASM_X86__LGUEST_HCALL_H */
diff --git a/include/asm-x86/linkage.h b/include/asm-x86/linkage.h
deleted file mode 100644
index 42d8b62ee8ab..000000000000
--- a/include/asm-x86/linkage.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef ASM_X86__LINKAGE_H
-#define ASM_X86__LINKAGE_H
-
-#undef notrace
-#define notrace __attribute__((no_instrument_function))
-
-#ifdef CONFIG_X86_64
-#define __ALIGN .p2align 4,,15
-#define __ALIGN_STR ".p2align 4,,15"
-#endif
-
-#ifdef CONFIG_X86_32
-#define asmlinkage CPP_ASMLINKAGE __attribute__((regparm(0)))
-/*
- * For 32-bit UML - mark functions implemented in assembly that use
- * regparm input parameters:
- */
-#define asmregparm __attribute__((regparm(3)))
-
-/*
- * Make sure the compiler doesn't do anything stupid with the
- * arguments on the stack - they are owned by the *caller*, not
- * the callee. This just fools gcc into not spilling into them,
- * and keeps it from doing tailcall recursion and/or using the
- * stack slots for temporaries, since they are live and "used"
- * all the way to the end of the function.
- *
- * NOTE! On x86-64, all the arguments are in registers, so this
- * only matters on a 32-bit kernel.
- */
-#define asmlinkage_protect(n, ret, args...) \
-	__asmlinkage_protect##n(ret, ##args)
-#define __asmlinkage_protect_n(ret, args...) \
-	__asm__ __volatile__ ("" : "=r" (ret) : "0" (ret), ##args)
-#define __asmlinkage_protect0(ret) \
-	__asmlinkage_protect_n(ret)
-#define __asmlinkage_protect1(ret, arg1) \
-	__asmlinkage_protect_n(ret, "g" (arg1))
-#define __asmlinkage_protect2(ret, arg1, arg2) \
-	__asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2))
-#define __asmlinkage_protect3(ret, arg1, arg2, arg3) \
-	__asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2), "g" (arg3))
-#define __asmlinkage_protect4(ret, arg1, arg2, arg3, arg4) \
-	__asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2), "g" (arg3), \
-			      "g" (arg4))
-#define __asmlinkage_protect5(ret, arg1, arg2, arg3, arg4, arg5) \
-	__asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2), "g" (arg3), \
-			      "g" (arg4), "g" (arg5))
-#define __asmlinkage_protect6(ret, arg1, arg2, arg3, arg4, arg5, arg6) \
-	__asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2), "g" (arg3), \
-			      "g" (arg4), "g" (arg5), "g" (arg6))
-
-#endif
-
-#ifdef CONFIG_X86_ALIGNMENT_16
-#define __ALIGN .align 16,0x90
-#define __ALIGN_STR ".align 16,0x90"
-#endif
-
-#endif /* ASM_X86__LINKAGE_H */
-
diff --git a/include/asm-x86/local.h b/include/asm-x86/local.h
deleted file mode 100644
index ae91994fd6c9..000000000000
--- a/include/asm-x86/local.h
+++ /dev/null
@@ -1,235 +0,0 @@
-#ifndef ASM_X86__LOCAL_H
-#define ASM_X86__LOCAL_H
-
-#include <linux/percpu.h>
-
-#include <asm/system.h>
-#include <asm/atomic.h>
-#include <asm/asm.h>
-
-typedef struct {
-	atomic_long_t a;
-} local_t;
-
-#define LOCAL_INIT(i)	{ ATOMIC_LONG_INIT(i) }
-
-#define local_read(l)	atomic_long_read(&(l)->a)
-#define local_set(l, i)	atomic_long_set(&(l)->a, (i))
-
-static inline void local_inc(local_t *l)
-{
-	asm volatile(_ASM_INC "%0"
-		     : "+m" (l->a.counter));
-}
-
-static inline void local_dec(local_t *l)
-{
-	asm volatile(_ASM_DEC "%0"
-		     : "+m" (l->a.counter));
-}
-
-static inline void local_add(long i, local_t *l)
-{
-	asm volatile(_ASM_ADD "%1,%0"
-		     : "+m" (l->a.counter)
-		     : "ir" (i));
-}
-
-static inline void local_sub(long i, local_t *l)
-{
-	asm volatile(_ASM_SUB "%1,%0"
-		     : "+m" (l->a.counter)
-		     : "ir" (i));
-}
-
-/**
- * local_sub_and_test - subtract value from variable and test result
- * @i: integer value to subtract
- * @l: pointer to type local_t
- *
- * Atomically subtracts @i from @l and returns
- * true if the result is zero, or false for all
- * other cases.
- */
-static inline int local_sub_and_test(long i, local_t *l)
-{
-	unsigned char c;
-
-	asm volatile(_ASM_SUB "%2,%0; sete %1"
-		     : "+m" (l->a.counter), "=qm" (c)
-		     : "ir" (i) : "memory");
-	return c;
-}
-
-/**
- * local_dec_and_test - decrement and test
- * @l: pointer to type local_t
- *
- * Atomically decrements @l by 1 and
- * returns true if the result is 0, or false for all other
- * cases.
- */
-static inline int local_dec_and_test(local_t *l)
-{
-	unsigned char c;
-
-	asm volatile(_ASM_DEC "%0; sete %1"
-		     : "+m" (l->a.counter), "=qm" (c)
-		     : : "memory");
-	return c != 0;
-}
-
-/**
- * local_inc_and_test - increment and test
- * @l: pointer to type local_t
- *
- * Atomically increments @l by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-static inline int local_inc_and_test(local_t *l)
-{
-	unsigned char c;
-
-	asm volatile(_ASM_INC "%0; sete %1"
-		     : "+m" (l->a.counter), "=qm" (c)
-		     : : "memory");
-	return c != 0;
-}
-
-/**
- * local_add_negative - add and test if negative
- * @i: integer value to add
- * @l: pointer to type local_t
- *
- * Atomically adds @i to @l and returns true
- * if the result is negative, or false when
- * result is greater than or equal to zero.
- */
-static inline int local_add_negative(long i, local_t *l)
-{
-	unsigned char c;
-
-	asm volatile(_ASM_ADD "%2,%0; sets %1"
-		     : "+m" (l->a.counter), "=qm" (c)
-		     : "ir" (i) : "memory");
-	return c;
-}
-
-/**
- * local_add_return - add and return
- * @i: integer value to add
- * @l: pointer to type local_t
- *
- * Atomically adds @i to @l and returns @i + @l
- */
-static inline long local_add_return(long i, local_t *l)
-{
-	long __i;
-#ifdef CONFIG_M386
-	unsigned long flags;
-	if (unlikely(boot_cpu_data.x86 <= 3))
-		goto no_xadd;
-#endif
-	/* Modern 486+ processor */
-	__i = i;
-	asm volatile(_ASM_XADD "%0, %1;"
-		     : "+r" (i), "+m" (l->a.counter)
-		     : : "memory");
-	return i + __i;
-
-#ifdef CONFIG_M386
-no_xadd: /* Legacy 386 processor */
-	local_irq_save(flags);
-	__i = local_read(l);
-	local_set(l, i + __i);
-	local_irq_restore(flags);
-	return i + __i;
-#endif
-}
-
-static inline long local_sub_return(long i, local_t *l)
-{
-	return local_add_return(-i, l);
-}
-
-#define local_inc_return(l)  (local_add_return(1, l))
-#define local_dec_return(l)  (local_sub_return(1, l))
-
-#define local_cmpxchg(l, o, n) \
-	(cmpxchg_local(&((l)->a.counter), (o), (n)))
-/* Always has a lock prefix */
-#define local_xchg(l, n) (xchg(&((l)->a.counter), (n)))
-
-/**
- * local_add_unless - add unless the number is a given value
- * @l: pointer of type local_t
- * @a: the amount to add to l...
- * @u: ...unless l is equal to u.
- *
- * Atomically adds @a to @l, so long as it was not @u.
- * Returns non-zero if @l was not @u, and zero otherwise.
- */
-#define local_add_unless(l, a, u)				\
-({								\
-	long c, old;						\
-	c = local_read((l));					\
-	for (;;) {						\
-		if (unlikely(c == (u)))				\
-			break;					\
-		old = local_cmpxchg((l), c, c + (a));		\
-		if (likely(old == c))				\
-			break;					\
-		c = old;					\
-	}							\
-	c != (u);						\
-})
-#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
-
-/* On x86_32, these are no better than the atomic variants.
- * On x86-64 these are better than the atomic variants on SMP kernels
- * because they dont use a lock prefix.
- */
-#define __local_inc(l)		local_inc(l)
-#define __local_dec(l)		local_dec(l)
-#define __local_add(i, l)	local_add((i), (l))
-#define __local_sub(i, l)	local_sub((i), (l))
-
-/* Use these for per-cpu local_t variables: on some archs they are
- * much more efficient than these naive implementations.  Note they take
- * a variable, not an address.
- *
- * X86_64: This could be done better if we moved the per cpu data directly
- * after GS.
- */
-
-/* Need to disable preemption for the cpu local counters otherwise we could
-   still access a variable of a previous CPU in a non atomic way. */
-#define cpu_local_wrap_v(l)		\
-({					\
-	local_t res__;			\
-	preempt_disable(); 		\
-	res__ = (l);			\
-	preempt_enable();		\
-	res__;				\
-})
-#define cpu_local_wrap(l)		\
-({					\
-	preempt_disable();		\
-	(l);				\
-	preempt_enable();		\
-})					\
-
-#define cpu_local_read(l)    cpu_local_wrap_v(local_read(&__get_cpu_var((l))))
-#define cpu_local_set(l, i)  cpu_local_wrap(local_set(&__get_cpu_var((l)), (i)))
-#define cpu_local_inc(l)     cpu_local_wrap(local_inc(&__get_cpu_var((l))))
-#define cpu_local_dec(l)     cpu_local_wrap(local_dec(&__get_cpu_var((l))))
-#define cpu_local_add(i, l)  cpu_local_wrap(local_add((i), &__get_cpu_var((l))))
-#define cpu_local_sub(i, l)  cpu_local_wrap(local_sub((i), &__get_cpu_var((l))))
-
-#define __cpu_local_inc(l)	cpu_local_inc((l))
-#define __cpu_local_dec(l)	cpu_local_dec((l))
-#define __cpu_local_add(i, l)	cpu_local_add((i), (l))
-#define __cpu_local_sub(i, l)	cpu_local_sub((i), (l))
-
-#endif /* ASM_X86__LOCAL_H */
diff --git a/include/asm-x86/mach-default/apm.h b/include/asm-x86/mach-default/apm.h
deleted file mode 100644
index 2aa61b54fbd5..000000000000
--- a/include/asm-x86/mach-default/apm.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- *  Machine specific APM BIOS functions for generic.
- *  Split out from apm.c by Osamu Tomita <tomita@cinet.co.jp>
- */
-
-#ifndef ASM_X86__MACH_DEFAULT__APM_H
-#define ASM_X86__MACH_DEFAULT__APM_H
-
-#ifdef APM_ZERO_SEGS
-#	define APM_DO_ZERO_SEGS \
-		"pushl %%ds\n\t" \
-		"pushl %%es\n\t" \
-		"xorl %%edx, %%edx\n\t" \
-		"mov %%dx, %%ds\n\t" \
-		"mov %%dx, %%es\n\t" \
-		"mov %%dx, %%fs\n\t" \
-		"mov %%dx, %%gs\n\t"
-#	define APM_DO_POP_SEGS \
-		"popl %%es\n\t" \
-		"popl %%ds\n\t"
-#else
-#	define APM_DO_ZERO_SEGS
-#	define APM_DO_POP_SEGS
-#endif
-
-static inline void apm_bios_call_asm(u32 func, u32 ebx_in, u32 ecx_in,
-					u32 *eax, u32 *ebx, u32 *ecx,
-					u32 *edx, u32 *esi)
-{
-	/*
-	 * N.B. We do NOT need a cld after the BIOS call
-	 * because we always save and restore the flags.
-	 */
-	__asm__ __volatile__(APM_DO_ZERO_SEGS
-		"pushl %%edi\n\t"
-		"pushl %%ebp\n\t"
-		"lcall *%%cs:apm_bios_entry\n\t"
-		"setc %%al\n\t"
-		"popl %%ebp\n\t"
-		"popl %%edi\n\t"
-		APM_DO_POP_SEGS
-		: "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx),
-		  "=S" (*esi)
-		: "a" (func), "b" (ebx_in), "c" (ecx_in)
-		: "memory", "cc");
-}
-
-static inline u8 apm_bios_call_simple_asm(u32 func, u32 ebx_in,
-						u32 ecx_in, u32 *eax)
-{
-	int	cx, dx, si;
-	u8	error;
-
-	/*
-	 * N.B. We do NOT need a cld after the BIOS call
-	 * because we always save and restore the flags.
-	 */
-	__asm__ __volatile__(APM_DO_ZERO_SEGS
-		"pushl %%edi\n\t"
-		"pushl %%ebp\n\t"
-		"lcall *%%cs:apm_bios_entry\n\t"
-		"setc %%bl\n\t"
-		"popl %%ebp\n\t"
-		"popl %%edi\n\t"
-		APM_DO_POP_SEGS
-		: "=a" (*eax), "=b" (error), "=c" (cx), "=d" (dx),
-		  "=S" (si)
-		: "a" (func), "b" (ebx_in), "c" (ecx_in)
-		: "memory", "cc");
-	return error;
-}
-
-#endif /* ASM_X86__MACH_DEFAULT__APM_H */
diff --git a/include/asm-x86/mach-default/do_timer.h b/include/asm-x86/mach-default/do_timer.h
deleted file mode 100644
index 23ecda0b28a0..000000000000
--- a/include/asm-x86/mach-default/do_timer.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* defines for inline arch setup functions */
-#include <linux/clockchips.h>
-
-#include <asm/i8259.h>
-#include <asm/i8253.h>
-
-/**
- * do_timer_interrupt_hook - hook into timer tick
- *
- * Call the pit clock event handler. see asm/i8253.h
- **/
-
-static inline void do_timer_interrupt_hook(void)
-{
-	global_clock_event->event_handler(global_clock_event);
-}
diff --git a/include/asm-x86/mach-default/entry_arch.h b/include/asm-x86/mach-default/entry_arch.h
deleted file mode 100644
index 9283b60a1dd2..000000000000
--- a/include/asm-x86/mach-default/entry_arch.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is designed to contain the BUILD_INTERRUPT specifications for
- * all of the extra named interrupt vectors used by the architecture.
- * Usually this is the Inter Process Interrupts (IPIs)
- */
-
-/*
- * The following vectors are part of the Linux architecture, there
- * is no hardware IRQ pin equivalent for them, they are triggered
- * through the ICC by us (IPIs)
- */
-#ifdef CONFIG_X86_SMP
-BUILD_INTERRUPT(reschedule_interrupt,RESCHEDULE_VECTOR)
-BUILD_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
-BUILD_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
-BUILD_INTERRUPT(call_function_single_interrupt,CALL_FUNCTION_SINGLE_VECTOR)
-#endif
-
-/*
- * every pentium local APIC has two 'local interrupts', with a
- * soft-definable vector attached to both interrupts, one of
- * which is a timer interrupt, the other one is error counter
- * overflow. Linux uses the local APIC timer interrupt to get
- * a much simpler SMP time architecture:
- */
-#ifdef CONFIG_X86_LOCAL_APIC
-BUILD_INTERRUPT(apic_timer_interrupt,LOCAL_TIMER_VECTOR)
-BUILD_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR)
-BUILD_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR)
-
-#ifdef CONFIG_X86_MCE_P4THERMAL
-BUILD_INTERRUPT(thermal_interrupt,THERMAL_APIC_VECTOR)
-#endif
-
-#endif
diff --git a/include/asm-x86/mach-default/mach_apic.h b/include/asm-x86/mach-default/mach_apic.h
deleted file mode 100644
index 2a330a41b3dd..000000000000
--- a/include/asm-x86/mach-default/mach_apic.h
+++ /dev/null
@@ -1,143 +0,0 @@
-#ifndef ASM_X86__MACH_DEFAULT__MACH_APIC_H
-#define ASM_X86__MACH_DEFAULT__MACH_APIC_H
-
-#ifdef CONFIG_X86_LOCAL_APIC
-
-#include <mach_apicdef.h>
-#include <asm/smp.h>
-
-#define APIC_DFR_VALUE	(APIC_DFR_FLAT)
-
-static inline cpumask_t target_cpus(void)
-{ 
-#ifdef CONFIG_SMP
-	return cpu_online_map;
-#else
-	return cpumask_of_cpu(0);
-#endif
-} 
-
-#define NO_BALANCE_IRQ (0)
-#define esr_disable (0)
-
-#ifdef CONFIG_X86_64
-#include <asm/genapic.h>
-#define INT_DELIVERY_MODE (genapic->int_delivery_mode)
-#define INT_DEST_MODE (genapic->int_dest_mode)
-#define TARGET_CPUS	  (genapic->target_cpus())
-#define apic_id_registered (genapic->apic_id_registered)
-#define init_apic_ldr (genapic->init_apic_ldr)
-#define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
-#define phys_pkg_id	(genapic->phys_pkg_id)
-#define vector_allocation_domain    (genapic->vector_allocation_domain)
-#define read_apic_id()  (GET_APIC_ID(apic_read(APIC_ID)))
-#define send_IPI_self (genapic->send_IPI_self)
-extern void setup_apic_routing(void);
-#else
-#define INT_DELIVERY_MODE dest_LowestPrio
-#define INT_DEST_MODE 1     /* logical delivery broadcast to all procs */
-#define TARGET_CPUS (target_cpus())
-/*
- * Set up the logical destination ID.
- *
- * Intel recommends to set DFR, LDR and TPR before enabling
- * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
- * document number 292116).  So here it goes...
- */
-static inline void init_apic_ldr(void)
-{
-	unsigned long val;
-
-	apic_write(APIC_DFR, APIC_DFR_VALUE);
-	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
-	val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
-	apic_write(APIC_LDR, val);
-}
-
-static inline int apic_id_registered(void)
-{
-	return physid_isset(read_apic_id(), phys_cpu_present_map);
-}
-
-static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
-{
-	return cpus_addr(cpumask)[0];
-}
-
-static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
-{
-	return cpuid_apic >> index_msb;
-}
-
-static inline void setup_apic_routing(void)
-{
-#ifdef CONFIG_X86_IO_APIC
-	printk("Enabling APIC mode:  %s.  Using %d I/O APICs\n",
-					"Flat", nr_ioapics);
-#endif
-}
-
-static inline int apicid_to_node(int logical_apicid)
-{
-#ifdef CONFIG_SMP
-	return apicid_2_node[hard_smp_processor_id()];
-#else
-	return 0;
-#endif
-}
-#endif
-
-static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
-{
-	return physid_isset(apicid, bitmap);
-}
-
-static inline unsigned long check_apicid_present(int bit)
-{
-	return physid_isset(bit, phys_cpu_present_map);
-}
-
-static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
-{
-	return phys_map;
-}
-
-static inline int multi_timer_check(int apic, int irq)
-{
-	return 0;
-}
-
-/* Mapping from cpu number to logical apicid */
-static inline int cpu_to_logical_apicid(int cpu)
-{
-	return 1 << cpu;
-}
-
-static inline int cpu_present_to_apicid(int mps_cpu)
-{
-	if (mps_cpu < NR_CPUS && cpu_present(mps_cpu))
-		return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
-	else
-		return BAD_APICID;
-}
-
-static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
-{
-	return physid_mask_of_physid(phys_apicid);
-}
-
-static inline void setup_portio_remap(void)
-{
-}
-
-static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
-{
-	return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
-}
-
-static inline void enable_apic_mode(void)
-{
-}
-
-#endif /* CONFIG_X86_LOCAL_APIC */
-#endif /* ASM_X86__MACH_DEFAULT__MACH_APIC_H */
diff --git a/include/asm-x86/mach-default/mach_apicdef.h b/include/asm-x86/mach-default/mach_apicdef.h
deleted file mode 100644
index 0c2d41c41b20..000000000000
--- a/include/asm-x86/mach-default/mach_apicdef.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef ASM_X86__MACH_DEFAULT__MACH_APICDEF_H
-#define ASM_X86__MACH_DEFAULT__MACH_APICDEF_H
-
-#include <asm/apic.h>
-
-#ifdef CONFIG_X86_64
-#define	APIC_ID_MASK		(genapic->apic_id_mask)
-#define GET_APIC_ID(x)		(genapic->get_apic_id(x))
-#define	SET_APIC_ID(x)		(genapic->set_apic_id(x))
-#else
-#define		APIC_ID_MASK		(0xF<<24)
-static inline unsigned get_apic_id(unsigned long x) 
-{
-	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
-	if (APIC_XAPIC(ver))
-		return (((x)>>24)&0xFF);
-	else
-		return (((x)>>24)&0xF);
-} 
-
-#define		GET_APIC_ID(x)	get_apic_id(x)
-#endif
-
-#endif /* ASM_X86__MACH_DEFAULT__MACH_APICDEF_H */
diff --git a/include/asm-x86/mach-default/mach_ipi.h b/include/asm-x86/mach-default/mach_ipi.h
deleted file mode 100644
index 674bc7e50c35..000000000000
--- a/include/asm-x86/mach-default/mach_ipi.h
+++ /dev/null
@@ -1,64 +0,0 @@
-#ifndef ASM_X86__MACH_DEFAULT__MACH_IPI_H
-#define ASM_X86__MACH_DEFAULT__MACH_IPI_H
-
-/* Avoid include hell */
-#define NMI_VECTOR 0x02
-
-void send_IPI_mask_bitmask(cpumask_t mask, int vector);
-void __send_IPI_shortcut(unsigned int shortcut, int vector);
-
-extern int no_broadcast;
-
-#ifdef CONFIG_X86_64
-#include <asm/genapic.h>
-#define send_IPI_mask (genapic->send_IPI_mask)
-#else
-static inline void send_IPI_mask(cpumask_t mask, int vector)
-{
-	send_IPI_mask_bitmask(mask, vector);
-}
-#endif
-
-static inline void __local_send_IPI_allbutself(int vector)
-{
-	if (no_broadcast || vector == NMI_VECTOR) {
-		cpumask_t mask = cpu_online_map;
-
-		cpu_clear(smp_processor_id(), mask);
-		send_IPI_mask(mask, vector);
-	} else
-		__send_IPI_shortcut(APIC_DEST_ALLBUT, vector);
-}
-
-static inline void __local_send_IPI_all(int vector)
-{
-	if (no_broadcast || vector == NMI_VECTOR)
-		send_IPI_mask(cpu_online_map, vector);
-	else
-		__send_IPI_shortcut(APIC_DEST_ALLINC, vector);
-}
-
-#ifdef CONFIG_X86_64
-#define send_IPI_allbutself (genapic->send_IPI_allbutself)
-#define send_IPI_all (genapic->send_IPI_all)
-#else
-static inline void send_IPI_allbutself(int vector)
-{
-	/*
-	 * if there are no other CPUs in the system then we get an APIC send 
-	 * error if we try to broadcast, thus avoid sending IPIs in this case.
-	 */
-	if (!(num_online_cpus() > 1))
-		return;
-
-	__local_send_IPI_allbutself(vector);
-	return;
-}
-
-static inline void send_IPI_all(int vector)
-{
-	__local_send_IPI_all(vector);
-}
-#endif
-
-#endif /* ASM_X86__MACH_DEFAULT__MACH_IPI_H */
diff --git a/include/asm-x86/mach-default/mach_mpparse.h b/include/asm-x86/mach-default/mach_mpparse.h
deleted file mode 100644
index 9c381f2815ac..000000000000
--- a/include/asm-x86/mach-default/mach_mpparse.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef ASM_X86__MACH_DEFAULT__MACH_MPPARSE_H
-#define ASM_X86__MACH_DEFAULT__MACH_MPPARSE_H
-
-static inline int mps_oem_check(struct mp_config_table *mpc, char *oem, 
-		char *productid)
-{
-	return 0;
-}
-
-/* Hook from generic ACPI tables.c */
-static inline int acpi_madt_oem_check(char *oem_id, char *oem_table_id)
-{
-	return 0;
-}
-
-
-#endif /* ASM_X86__MACH_DEFAULT__MACH_MPPARSE_H */
diff --git a/include/asm-x86/mach-default/mach_mpspec.h b/include/asm-x86/mach-default/mach_mpspec.h
deleted file mode 100644
index d77646f011f1..000000000000
--- a/include/asm-x86/mach-default/mach_mpspec.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef ASM_X86__MACH_DEFAULT__MACH_MPSPEC_H
-#define ASM_X86__MACH_DEFAULT__MACH_MPSPEC_H
-
-#define MAX_IRQ_SOURCES 256
-
-#if CONFIG_BASE_SMALL == 0
-#define MAX_MP_BUSSES 256
-#else
-#define MAX_MP_BUSSES 32
-#endif
-
-#endif /* ASM_X86__MACH_DEFAULT__MACH_MPSPEC_H */
diff --git a/include/asm-x86/mach-default/mach_timer.h b/include/asm-x86/mach-default/mach_timer.h
deleted file mode 100644
index 990b15833834..000000000000
--- a/include/asm-x86/mach-default/mach_timer.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *  Machine specific calibrate_tsc() for generic.
- *  Split out from timer_tsc.c by Osamu Tomita <tomita@cinet.co.jp>
- */
-/* ------ Calibrate the TSC ------- 
- * Return 2^32 * (1 / (TSC clocks per usec)) for do_fast_gettimeoffset().
- * Too much 64-bit arithmetic here to do this cleanly in C, and for
- * accuracy's sake we want to keep the overhead on the CTC speaker (channel 2)
- * output busy loop as low as possible. We avoid reading the CTC registers
- * directly because of the awkward 8-bit access mechanism of the 82C54
- * device.
- */
-#ifndef ASM_X86__MACH_DEFAULT__MACH_TIMER_H
-#define ASM_X86__MACH_DEFAULT__MACH_TIMER_H
-
-#define CALIBRATE_TIME_MSEC 30 /* 30 msecs */
-#define CALIBRATE_LATCH	\
-	((CLOCK_TICK_RATE * CALIBRATE_TIME_MSEC + 1000/2)/1000)
-
-static inline void mach_prepare_counter(void)
-{
-       /* Set the Gate high, disable speaker */
-	outb((inb(0x61) & ~0x02) | 0x01, 0x61);
-
-	/*
-	 * Now let's take care of CTC channel 2
-	 *
-	 * Set the Gate high, program CTC channel 2 for mode 0,
-	 * (interrupt on terminal count mode), binary count,
-	 * load 5 * LATCH count, (LSB and MSB) to begin countdown.
-	 *
-	 * Some devices need a delay here.
-	 */
-	outb(0xb0, 0x43);			/* binary, mode 0, LSB/MSB, Ch 2 */
-	outb_p(CALIBRATE_LATCH & 0xff, 0x42);	/* LSB of count */
-	outb_p(CALIBRATE_LATCH >> 8, 0x42);       /* MSB of count */
-}
-
-static inline void mach_countup(unsigned long *count_p)
-{
-	unsigned long count = 0;
-	do {
-		count++;
-	} while ((inb_p(0x61) & 0x20) == 0);
-	*count_p = count;
-}
-
-#endif /* ASM_X86__MACH_DEFAULT__MACH_TIMER_H */
diff --git a/include/asm-x86/mach-default/mach_traps.h b/include/asm-x86/mach-default/mach_traps.h
deleted file mode 100644
index ff8778f26b84..000000000000
--- a/include/asm-x86/mach-default/mach_traps.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  Machine specific NMI handling for generic.
- *  Split out from traps.c by Osamu Tomita <tomita@cinet.co.jp>
- */
-#ifndef ASM_X86__MACH_DEFAULT__MACH_TRAPS_H
-#define ASM_X86__MACH_DEFAULT__MACH_TRAPS_H
-
-#include <asm/mc146818rtc.h>
-
-static inline unsigned char get_nmi_reason(void)
-{
-	return inb(0x61);
-}
-
-static inline void reassert_nmi(void)
-{
-	int old_reg = -1;
-
-	if (do_i_have_lock_cmos())
-		old_reg = current_lock_cmos_reg();
-	else
-		lock_cmos(0); /* register doesn't matter here */
-	outb(0x8f, 0x70);
-	inb(0x71);		/* dummy */
-	outb(0x0f, 0x70);
-	inb(0x71);		/* dummy */
-	if (old_reg >= 0)
-		outb(old_reg, 0x70);
-	else
-		unlock_cmos();
-}
-
-#endif /* ASM_X86__MACH_DEFAULT__MACH_TRAPS_H */
diff --git a/include/asm-x86/mach-default/mach_wakecpu.h b/include/asm-x86/mach-default/mach_wakecpu.h
deleted file mode 100644
index 361b810f5160..000000000000
--- a/include/asm-x86/mach-default/mach_wakecpu.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef ASM_X86__MACH_DEFAULT__MACH_WAKECPU_H
-#define ASM_X86__MACH_DEFAULT__MACH_WAKECPU_H
-
-/* 
- * This file copes with machines that wakeup secondary CPUs by the
- * INIT, INIT, STARTUP sequence.
- */
-
-#define WAKE_SECONDARY_VIA_INIT
-
-#define TRAMPOLINE_LOW phys_to_virt(0x467)
-#define TRAMPOLINE_HIGH phys_to_virt(0x469)
-
-#define boot_cpu_apicid boot_cpu_physical_apicid
-
-static inline void wait_for_init_deassert(atomic_t *deassert)
-{
-	while (!atomic_read(deassert))
-		cpu_relax();
-	return;
-}
-
-/* Nothing to do for most platforms, since cleared by the INIT cycle */
-static inline void smp_callin_clear_local_apic(void)
-{
-}
-
-static inline void store_NMI_vector(unsigned short *high, unsigned short *low)
-{
-}
-
-static inline void restore_NMI_vector(unsigned short *high, unsigned short *low)
-{
-}
-
-#if APIC_DEBUG
- #define inquire_remote_apic(apicid) __inquire_remote_apic(apicid)
-#else
- #define inquire_remote_apic(apicid) {}
-#endif
-
-#endif /* ASM_X86__MACH_DEFAULT__MACH_WAKECPU_H */
diff --git a/include/asm-x86/mach-default/pci-functions.h b/include/asm-x86/mach-default/pci-functions.h
deleted file mode 100644
index ed0bab427354..000000000000
--- a/include/asm-x86/mach-default/pci-functions.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- *	PCI BIOS function numbering for conventional PCI BIOS 
- *	systems
- */
-
-#define PCIBIOS_PCI_FUNCTION_ID 	0xb1XX
-#define PCIBIOS_PCI_BIOS_PRESENT 	0xb101
-#define PCIBIOS_FIND_PCI_DEVICE		0xb102
-#define PCIBIOS_FIND_PCI_CLASS_CODE	0xb103
-#define PCIBIOS_GENERATE_SPECIAL_CYCLE	0xb106
-#define PCIBIOS_READ_CONFIG_BYTE	0xb108
-#define PCIBIOS_READ_CONFIG_WORD	0xb109
-#define PCIBIOS_READ_CONFIG_DWORD	0xb10a
-#define PCIBIOS_WRITE_CONFIG_BYTE	0xb10b
-#define PCIBIOS_WRITE_CONFIG_WORD	0xb10c
-#define PCIBIOS_WRITE_CONFIG_DWORD	0xb10d
-#define PCIBIOS_GET_ROUTING_OPTIONS	0xb10e
-#define PCIBIOS_SET_PCI_HW_INT		0xb10f
-
diff --git a/include/asm-x86/mach-default/setup_arch.h b/include/asm-x86/mach-default/setup_arch.h
deleted file mode 100644
index 38846208b548..000000000000
--- a/include/asm-x86/mach-default/setup_arch.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/* Hook to call BIOS initialisation function */
-
-/* no action for generic */
diff --git a/include/asm-x86/mach-default/smpboot_hooks.h b/include/asm-x86/mach-default/smpboot_hooks.h
deleted file mode 100644
index dbab36d64d48..000000000000
--- a/include/asm-x86/mach-default/smpboot_hooks.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* two abstractions specific to kernel/smpboot.c, mainly to cater to visws
- * which needs to alter them. */
-
-static inline void smpboot_clear_io_apic_irqs(void)
-{
-#ifdef CONFIG_X86_IO_APIC
-	io_apic_irqs = 0;
-#endif
-}
-
-static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
-{
-	CMOS_WRITE(0xa, 0xf);
-	local_flush_tlb();
-	pr_debug("1.\n");
-	*((volatile unsigned short *) TRAMPOLINE_HIGH) = start_eip >> 4;
-	pr_debug("2.\n");
-	*((volatile unsigned short *) TRAMPOLINE_LOW) = start_eip & 0xf;
-	pr_debug("3.\n");
-}
-
-static inline void smpboot_restore_warm_reset_vector(void)
-{
-	/*
-	 * Install writable page 0 entry to set BIOS data area.
-	 */
-	local_flush_tlb();
-
-	/*
-	 * Paranoid:  Set warm reset code and vector here back
-	 * to default values.
-	 */
-	CMOS_WRITE(0, 0xf);
-
-	*((volatile long *) phys_to_virt(0x467)) = 0;
-}
-
-static inline void __init smpboot_setup_io_apic(void)
-{
-#ifdef CONFIG_X86_IO_APIC
-	/*
-	 * Here we can be sure that there is an IO-APIC in the system. Let's
-	 * go and set it up:
-	 */
-	if (!skip_ioapic_setup && nr_ioapics)
-		setup_IO_APIC();
-	else {
-		nr_ioapics = 0;
-		localise_nmi_watchdog();
-	}
-#endif
-}
-
-static inline void smpboot_clear_io_apic(void)
-{
-#ifdef CONFIG_X86_IO_APIC
-	nr_ioapics = 0;
-#endif
-}
diff --git a/include/asm-x86/mach-generic/gpio.h b/include/asm-x86/mach-generic/gpio.h
deleted file mode 100644
index 6ce0f7786ef8..000000000000
--- a/include/asm-x86/mach-generic/gpio.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef ASM_X86__MACH_GENERIC__GPIO_H
-#define ASM_X86__MACH_GENERIC__GPIO_H
-
-int gpio_request(unsigned gpio, const char *label);
-void gpio_free(unsigned gpio);
-int gpio_direction_input(unsigned gpio);
-int gpio_direction_output(unsigned gpio, int value);
-int gpio_get_value(unsigned gpio);
-void gpio_set_value(unsigned gpio, int value);
-int gpio_to_irq(unsigned gpio);
-int irq_to_gpio(unsigned irq);
-
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-
-#endif /* ASM_X86__MACH_GENERIC__GPIO_H */
diff --git a/include/asm-x86/mach-generic/irq_vectors_limits.h b/include/asm-x86/mach-generic/irq_vectors_limits.h
deleted file mode 100644
index f7870e1a220d..000000000000
--- a/include/asm-x86/mach-generic/irq_vectors_limits.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef ASM_X86__MACH_GENERIC__IRQ_VECTORS_LIMITS_H
-#define ASM_X86__MACH_GENERIC__IRQ_VECTORS_LIMITS_H
-
-/*
- * For Summit or generic (i.e. installer) kernels, we have lots of I/O APICs,
- * even with uni-proc kernels, so use a big array.
- *
- * This value should be the same in both the generic and summit subarches.
- * Change one, change 'em both.
- */
-#define NR_IRQS	224
-#define NR_IRQ_VECTORS	1024
-
-#endif /* ASM_X86__MACH_GENERIC__IRQ_VECTORS_LIMITS_H */
diff --git a/include/asm-x86/mach-generic/mach_apic.h b/include/asm-x86/mach-generic/mach_apic.h
deleted file mode 100644
index 5d010c6881dd..000000000000
--- a/include/asm-x86/mach-generic/mach_apic.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef ASM_X86__MACH_GENERIC__MACH_APIC_H
-#define ASM_X86__MACH_GENERIC__MACH_APIC_H
-
-#include <asm/genapic.h>
-
-#define esr_disable (genapic->ESR_DISABLE)
-#define NO_BALANCE_IRQ (genapic->no_balance_irq)
-#define INT_DELIVERY_MODE (genapic->int_delivery_mode)
-#define INT_DEST_MODE (genapic->int_dest_mode)
-#undef APIC_DEST_LOGICAL
-#define APIC_DEST_LOGICAL (genapic->apic_destination_logical)
-#define TARGET_CPUS	  (genapic->target_cpus())
-#define apic_id_registered (genapic->apic_id_registered)
-#define init_apic_ldr (genapic->init_apic_ldr)
-#define ioapic_phys_id_map (genapic->ioapic_phys_id_map)
-#define setup_apic_routing (genapic->setup_apic_routing)
-#define multi_timer_check (genapic->multi_timer_check)
-#define apicid_to_node (genapic->apicid_to_node)
-#define cpu_to_logical_apicid (genapic->cpu_to_logical_apicid) 
-#define cpu_present_to_apicid (genapic->cpu_present_to_apicid)
-#define apicid_to_cpu_present (genapic->apicid_to_cpu_present)
-#define setup_portio_remap (genapic->setup_portio_remap)
-#define check_apicid_present (genapic->check_apicid_present)
-#define check_phys_apicid_present (genapic->check_phys_apicid_present)
-#define check_apicid_used (genapic->check_apicid_used)
-#define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
-#define enable_apic_mode (genapic->enable_apic_mode)
-#define phys_pkg_id (genapic->phys_pkg_id)
-
-extern void generic_bigsmp_probe(void);
-
-#endif /* ASM_X86__MACH_GENERIC__MACH_APIC_H */
diff --git a/include/asm-x86/mach-generic/mach_apicdef.h b/include/asm-x86/mach-generic/mach_apicdef.h
deleted file mode 100644
index 1657f38b8f27..000000000000
--- a/include/asm-x86/mach-generic/mach_apicdef.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef ASM_X86__MACH_GENERIC__MACH_APICDEF_H
-#define ASM_X86__MACH_GENERIC__MACH_APICDEF_H
-
-#ifndef APIC_DEFINITION
-#include <asm/genapic.h>
-
-#define GET_APIC_ID (genapic->get_apic_id)
-#define APIC_ID_MASK (genapic->apic_id_mask)
-#endif
-
-#endif /* ASM_X86__MACH_GENERIC__MACH_APICDEF_H */
diff --git a/include/asm-x86/mach-generic/mach_ipi.h b/include/asm-x86/mach-generic/mach_ipi.h
deleted file mode 100644
index f67433dbd65f..000000000000
--- a/include/asm-x86/mach-generic/mach_ipi.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef ASM_X86__MACH_GENERIC__MACH_IPI_H
-#define ASM_X86__MACH_GENERIC__MACH_IPI_H
-
-#include <asm/genapic.h>
-
-#define send_IPI_mask (genapic->send_IPI_mask)
-#define send_IPI_allbutself (genapic->send_IPI_allbutself)
-#define send_IPI_all (genapic->send_IPI_all)
-
-#endif /* ASM_X86__MACH_GENERIC__MACH_IPI_H */
diff --git a/include/asm-x86/mach-generic/mach_mpparse.h b/include/asm-x86/mach-generic/mach_mpparse.h
deleted file mode 100644
index 3115564e557c..000000000000
--- a/include/asm-x86/mach-generic/mach_mpparse.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef ASM_X86__MACH_GENERIC__MACH_MPPARSE_H
-#define ASM_X86__MACH_GENERIC__MACH_MPPARSE_H
-
-
-extern int mps_oem_check(struct mp_config_table *mpc, char *oem,
-			 char *productid);
-
-extern int acpi_madt_oem_check(char *oem_id, char *oem_table_id);
-
-#endif /* ASM_X86__MACH_GENERIC__MACH_MPPARSE_H */
diff --git a/include/asm-x86/mach-generic/mach_mpspec.h b/include/asm-x86/mach-generic/mach_mpspec.h
deleted file mode 100644
index 6061b153613e..000000000000
--- a/include/asm-x86/mach-generic/mach_mpspec.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef ASM_X86__MACH_GENERIC__MACH_MPSPEC_H
-#define ASM_X86__MACH_GENERIC__MACH_MPSPEC_H
-
-#define MAX_IRQ_SOURCES 256
-
-/* Summit or generic (i.e. installer) kernels need lots of bus entries. */
-/* Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets. */
-#define MAX_MP_BUSSES 260
-
-extern void numaq_mps_oem_check(struct mp_config_table *mpc, char *oem,
-				char *productid);
-#endif /* ASM_X86__MACH_GENERIC__MACH_MPSPEC_H */
diff --git a/include/asm-x86/mach-rdc321x/gpio.h b/include/asm-x86/mach-rdc321x/gpio.h
deleted file mode 100644
index 94b6cdf532e2..000000000000
--- a/include/asm-x86/mach-rdc321x/gpio.h
+++ /dev/null
@@ -1,60 +0,0 @@
-#ifndef ASM_X86__MACH_RDC321X__GPIO_H
-#define ASM_X86__MACH_RDC321X__GPIO_H
-
-#include <linux/kernel.h>
-
-extern int rdc_gpio_get_value(unsigned gpio);
-extern void rdc_gpio_set_value(unsigned gpio, int value);
-extern int rdc_gpio_direction_input(unsigned gpio);
-extern int rdc_gpio_direction_output(unsigned gpio, int value);
-extern int rdc_gpio_request(unsigned gpio, const char *label);
-extern void rdc_gpio_free(unsigned gpio);
-extern void __init rdc321x_gpio_setup(void);
-
-/* Wrappers for the arch-neutral GPIO API */
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-	return rdc_gpio_request(gpio, label);
-}
-
-static inline void gpio_free(unsigned gpio)
-{
-	might_sleep();
-	rdc_gpio_free(gpio);
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
-	return rdc_gpio_direction_input(gpio);
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
-	return rdc_gpio_direction_output(gpio, value);
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
-	return rdc_gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-	rdc_gpio_set_value(gpio, value);
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
-	return gpio;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
-	return irq;
-}
-
-/* For cansleep */
-#include <asm-generic/gpio.h>
-
-#endif /* ASM_X86__MACH_RDC321X__GPIO_H */
diff --git a/include/asm-x86/mach-rdc321x/rdc321x_defs.h b/include/asm-x86/mach-rdc321x/rdc321x_defs.h
deleted file mode 100644
index c8e9c8bed3d0..000000000000
--- a/include/asm-x86/mach-rdc321x/rdc321x_defs.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#define PFX	"rdc321x: "
-
-/* General purpose configuration and data registers */
-#define RDC3210_CFGREG_ADDR     0x0CF8
-#define RDC3210_CFGREG_DATA     0x0CFC
-
-#define RDC321X_GPIO_CTRL_REG1	0x48
-#define RDC321X_GPIO_CTRL_REG2	0x84
-#define RDC321X_GPIO_DATA_REG1	0x4c
-#define RDC321X_GPIO_DATA_REG2	0x88
-
-#define RDC321X_MAX_GPIO	58
diff --git a/include/asm-x86/mach-voyager/do_timer.h b/include/asm-x86/mach-voyager/do_timer.h
deleted file mode 100644
index 9e5a459fd15b..000000000000
--- a/include/asm-x86/mach-voyager/do_timer.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* defines for inline arch setup functions */
-#include <linux/clockchips.h>
-
-#include <asm/voyager.h>
-#include <asm/i8253.h>
-
-/**
- * do_timer_interrupt_hook - hook into timer tick
- *
- * Call the pit clock event handler. see asm/i8253.h
- **/
-static inline void do_timer_interrupt_hook(void)
-{
-	global_clock_event->event_handler(global_clock_event);
-	voyager_timer_interrupt();
-}
-
diff --git a/include/asm-x86/mach-voyager/entry_arch.h b/include/asm-x86/mach-voyager/entry_arch.h
deleted file mode 100644
index ae52624b5937..000000000000
--- a/include/asm-x86/mach-voyager/entry_arch.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* -*- mode: c; c-basic-offset: 8 -*- */
-
-/* Copyright (C) 2002
- *
- * Author: James.Bottomley@HansenPartnership.com
- *
- * linux/arch/i386/voyager/entry_arch.h
- *
- * This file builds the VIC and QIC CPI gates
- */
-
-/* initialise the voyager interrupt gates 
- *
- * This uses the macros in irq.h to set up assembly jump gates.  The
- * calls are then redirected to the same routine with smp_ prefixed */
-BUILD_INTERRUPT(vic_sys_interrupt, VIC_SYS_INT)
-BUILD_INTERRUPT(vic_cmn_interrupt, VIC_CMN_INT)
-BUILD_INTERRUPT(vic_cpi_interrupt, VIC_CPI_LEVEL0);
-
-/* do all the QIC interrupts */
-BUILD_INTERRUPT(qic_timer_interrupt, QIC_TIMER_CPI);
-BUILD_INTERRUPT(qic_invalidate_interrupt, QIC_INVALIDATE_CPI);
-BUILD_INTERRUPT(qic_reschedule_interrupt, QIC_RESCHEDULE_CPI);
-BUILD_INTERRUPT(qic_enable_irq_interrupt, QIC_ENABLE_IRQ_CPI);
-BUILD_INTERRUPT(qic_call_function_interrupt, QIC_CALL_FUNCTION_CPI);
-BUILD_INTERRUPT(qic_call_function_single_interrupt, QIC_CALL_FUNCTION_SINGLE_CPI);
diff --git a/include/asm-x86/mach-voyager/setup_arch.h b/include/asm-x86/mach-voyager/setup_arch.h
deleted file mode 100644
index 71729ca05cd7..000000000000
--- a/include/asm-x86/mach-voyager/setup_arch.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#include <asm/voyager.h>
-#include <asm/setup.h>
-#define VOYAGER_BIOS_INFO ((struct voyager_bios_info *) \
-			(&boot_params.apm_bios_info))
-
-/* Hook to call BIOS initialisation function */
-
-/* for voyager, pass the voyager BIOS/SUS info area to the detection
- * routines */
-
-#define ARCH_SETUP	voyager_detect(VOYAGER_BIOS_INFO);
-
diff --git a/include/asm-x86/math_emu.h b/include/asm-x86/math_emu.h
deleted file mode 100644
index 5768d8e95c8c..000000000000
--- a/include/asm-x86/math_emu.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef ASM_X86__MATH_EMU_H
-#define ASM_X86__MATH_EMU_H
-
-/* This structure matches the layout of the data saved to the stack
-   following a device-not-present interrupt, part of it saved
-   automatically by the 80386/80486.
-   */
-struct info {
-	long ___orig_eip;
-	long ___ebx;
-	long ___ecx;
-	long ___edx;
-	long ___esi;
-	long ___edi;
-	long ___ebp;
-	long ___eax;
-	long ___ds;
-	long ___es;
-	long ___fs;
-	long ___orig_eax;
-	long ___eip;
-	long ___cs;
-	long ___eflags;
-	long ___esp;
-	long ___ss;
-	long ___vm86_es; /* This and the following only in vm86 mode */
-	long ___vm86_ds;
-	long ___vm86_fs;
-	long ___vm86_gs;
-};
-#endif /* ASM_X86__MATH_EMU_H */
diff --git a/include/asm-x86/mc146818rtc.h b/include/asm-x86/mc146818rtc.h
deleted file mode 100644
index a995f33176cd..000000000000
--- a/include/asm-x86/mc146818rtc.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Machine dependent access functions for RTC registers.
- */
-#ifndef ASM_X86__MC146818RTC_H
-#define ASM_X86__MC146818RTC_H
-
-#include <asm/io.h>
-#include <asm/system.h>
-#include <asm/processor.h>
-#include <linux/mc146818rtc.h>
-
-#ifndef RTC_PORT
-#define RTC_PORT(x)	(0x70 + (x))
-#define RTC_ALWAYS_BCD	1	/* RTC operates in binary mode */
-#endif
-
-#if defined(CONFIG_X86_32) && defined(__HAVE_ARCH_CMPXCHG)
-/*
- * This lock provides nmi access to the CMOS/RTC registers.  It has some
- * special properties.  It is owned by a CPU and stores the index register
- * currently being accessed (if owned).  The idea here is that it works
- * like a normal lock (normally).  However, in an NMI, the NMI code will
- * first check to see if its CPU owns the lock, meaning that the NMI
- * interrupted during the read/write of the device.  If it does, it goes ahead
- * and performs the access and then restores the index register.  If it does
- * not, it locks normally.
- *
- * Note that since we are working with NMIs, we need this lock even in
- * a non-SMP machine just to mark that the lock is owned.
- *
- * This only works with compare-and-swap.  There is no other way to
- * atomically claim the lock and set the owner.
- */
-#include <linux/smp.h>
-extern volatile unsigned long cmos_lock;
-
-/*
- * All of these below must be called with interrupts off, preempt
- * disabled, etc.
- */
-
-static inline void lock_cmos(unsigned char reg)
-{
-	unsigned long new;
-	new = ((smp_processor_id() + 1) << 8) | reg;
-	for (;;) {
-		if (cmos_lock) {
-			cpu_relax();
-			continue;
-		}
-		if (__cmpxchg(&cmos_lock, 0, new, sizeof(cmos_lock)) == 0)
-			return;
-	}
-}
-
-static inline void unlock_cmos(void)
-{
-	cmos_lock = 0;
-}
-
-static inline int do_i_have_lock_cmos(void)
-{
-	return (cmos_lock >> 8) == (smp_processor_id() + 1);
-}
-
-static inline unsigned char current_lock_cmos_reg(void)
-{
-	return cmos_lock & 0xff;
-}
-
-#define lock_cmos_prefix(reg)			\
-	do {					\
-		unsigned long cmos_flags;	\
-		local_irq_save(cmos_flags);	\
-		lock_cmos(reg)
-
-#define lock_cmos_suffix(reg)			\
-	unlock_cmos();				\
-	local_irq_restore(cmos_flags);		\
-	} while (0)
-#else
-#define lock_cmos_prefix(reg) do {} while (0)
-#define lock_cmos_suffix(reg) do {} while (0)
-#define lock_cmos(reg)
-#define unlock_cmos()
-#define do_i_have_lock_cmos() 0
-#define current_lock_cmos_reg() 0
-#endif
-
-/*
- * The yet supported machines all access the RTC index register via
- * an ISA port access but the way to access the date register differs ...
- */
-#define CMOS_READ(addr) rtc_cmos_read(addr)
-#define CMOS_WRITE(val, addr) rtc_cmos_write(val, addr)
-unsigned char rtc_cmos_read(unsigned char addr);
-void rtc_cmos_write(unsigned char val, unsigned char addr);
-
-extern int mach_set_rtc_mmss(unsigned long nowtime);
-extern unsigned long mach_get_cmos_time(void);
-
-#define RTC_IRQ 8
-
-#endif /* ASM_X86__MC146818RTC_H */
diff --git a/include/asm-x86/mca.h b/include/asm-x86/mca.h
deleted file mode 100644
index 60d1ed287b13..000000000000
--- a/include/asm-x86/mca.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* -*- mode: c; c-basic-offset: 8 -*- */
-
-/* Platform specific MCA defines */
-#ifndef ASM_X86__MCA_H
-#define ASM_X86__MCA_H
-
-/* Maximal number of MCA slots - actually, some machines have less, but
- * they all have sufficient number of POS registers to cover 8.
- */
-#define MCA_MAX_SLOT_NR  8
-
-/* Most machines have only one MCA bus.  The only multiple bus machines
- * I know have at most two */
-#define MAX_MCA_BUSSES 2
-
-#define MCA_PRIMARY_BUS		0
-#define MCA_SECONDARY_BUS	1
-
-/* Dummy slot numbers on primary MCA for integrated functions */
-#define MCA_INTEGSCSI	(MCA_MAX_SLOT_NR)
-#define MCA_INTEGVIDEO	(MCA_MAX_SLOT_NR+1)
-#define MCA_MOTHERBOARD (MCA_MAX_SLOT_NR+2)
-
-/* Dummy POS values for integrated functions */
-#define MCA_DUMMY_POS_START	0x10000
-#define MCA_INTEGSCSI_POS	(MCA_DUMMY_POS_START+1)
-#define MCA_INTEGVIDEO_POS	(MCA_DUMMY_POS_START+2)
-#define MCA_MOTHERBOARD_POS	(MCA_DUMMY_POS_START+3)
-
-/* MCA registers */
-
-#define MCA_MOTHERBOARD_SETUP_REG	0x94
-#define MCA_ADAPTER_SETUP_REG		0x96
-#define MCA_POS_REG(n)			(0x100+(n))
-
-#define MCA_ENABLED	0x01	/* POS 2, set if adapter enabled */
-
-/* Max number of adapters, including both slots and various integrated
- * things.
- */
-#define MCA_NUMADAPTERS (MCA_MAX_SLOT_NR+3)
-
-#endif /* ASM_X86__MCA_H */
diff --git a/include/asm-x86/mca_dma.h b/include/asm-x86/mca_dma.h
deleted file mode 100644
index 49f22be237d2..000000000000
--- a/include/asm-x86/mca_dma.h
+++ /dev/null
@@ -1,201 +0,0 @@
-#ifndef ASM_X86__MCA_DMA_H
-#define ASM_X86__MCA_DMA_H
-
-#include <asm/io.h>
-#include <linux/ioport.h>
-
-/*
- * Microchannel specific DMA stuff.  DMA on an MCA machine is fairly similar to
- *   standard PC dma, but it certainly has its quirks.  DMA register addresses
- *   are in a different place and there are some added functions.  Most of this
- *   should be pretty obvious on inspection.  Note that the user must divide
- *   count by 2 when using 16-bit dma; that is not handled by these functions.
- *
- * Ramen Noodles are yummy.
- *
- *  1998 Tymm Twillman <tymm@computer.org>
- */
-
-/*
- * Registers that are used by the DMA controller; FN is the function register
- *   (tell the controller what to do) and EXE is the execution register (how
- *   to do it)
- */
-
-#define MCA_DMA_REG_FN  0x18
-#define MCA_DMA_REG_EXE 0x1A
-
-/*
- * Functions that the DMA controller can do
- */
-
-#define MCA_DMA_FN_SET_IO       0x00
-#define MCA_DMA_FN_SET_ADDR     0x20
-#define MCA_DMA_FN_GET_ADDR     0x30
-#define MCA_DMA_FN_SET_COUNT    0x40
-#define MCA_DMA_FN_GET_COUNT    0x50
-#define MCA_DMA_FN_GET_STATUS   0x60
-#define MCA_DMA_FN_SET_MODE     0x70
-#define MCA_DMA_FN_SET_ARBUS    0x80
-#define MCA_DMA_FN_MASK         0x90
-#define MCA_DMA_FN_RESET_MASK   0xA0
-#define MCA_DMA_FN_MASTER_CLEAR 0xD0
-
-/*
- * Modes (used by setting MCA_DMA_FN_MODE in the function register)
- *
- * Note that the MODE_READ is read from memory (write to device), and
- *   MODE_WRITE is vice-versa.
- */
-
-#define MCA_DMA_MODE_XFER  0x04  /* read by default */
-#define MCA_DMA_MODE_READ  0x04  /* same as XFER */
-#define MCA_DMA_MODE_WRITE 0x08  /* OR with MODE_XFER to use */
-#define MCA_DMA_MODE_IO    0x01  /* DMA from IO register */
-#define MCA_DMA_MODE_16    0x40  /* 16 bit xfers */
-
-
-/**
- *	mca_enable_dma	-	channel to enable DMA on
- *	@dmanr: DMA channel
- *
- *	Enable the MCA bus DMA on a channel. This can be called from
- *	IRQ context.
- */
-
-static inline void mca_enable_dma(unsigned int dmanr)
-{
-	outb(MCA_DMA_FN_RESET_MASK | dmanr, MCA_DMA_REG_FN);
-}
-
-/**
- *	mca_disble_dma	-	channel to disable DMA on
- *	@dmanr: DMA channel
- *
- *	Enable the MCA bus DMA on a channel. This can be called from
- *	IRQ context.
- */
-
-static inline void mca_disable_dma(unsigned int dmanr)
-{
-	outb(MCA_DMA_FN_MASK | dmanr, MCA_DMA_REG_FN);
-}
-
-/**
- *	mca_set_dma_addr -	load a 24bit DMA address
- *	@dmanr: DMA channel
- *	@a: 24bit bus address
- *
- *	Load the address register in the DMA controller. This has a 24bit
- *	limitation (16Mb).
- */
-
-static inline void mca_set_dma_addr(unsigned int dmanr, unsigned int a)
-{
-	outb(MCA_DMA_FN_SET_ADDR | dmanr, MCA_DMA_REG_FN);
-	outb(a & 0xff, MCA_DMA_REG_EXE);
-	outb((a >> 8) & 0xff, MCA_DMA_REG_EXE);
-	outb((a >> 16) & 0xff, MCA_DMA_REG_EXE);
-}
-
-/**
- *	mca_get_dma_addr -	load a 24bit DMA address
- *	@dmanr: DMA channel
- *
- *	Read the address register in the DMA controller. This has a 24bit
- *	limitation (16Mb). The return is a bus address.
- */
-
-static inline unsigned int mca_get_dma_addr(unsigned int dmanr)
-{
-	unsigned int addr;
-
-	outb(MCA_DMA_FN_GET_ADDR | dmanr, MCA_DMA_REG_FN);
-	addr = inb(MCA_DMA_REG_EXE);
-	addr |= inb(MCA_DMA_REG_EXE) << 8;
-	addr |= inb(MCA_DMA_REG_EXE) << 16;
-
-	return addr;
-}
-
-/**
- *	mca_set_dma_count -	load a 16bit transfer count
- *	@dmanr: DMA channel
- *	@count: count
- *
- *	Set the DMA count for this channel. This can be up to 64Kbytes.
- *	Setting a count of zero will not do what you expect.
- */
-
-static inline void mca_set_dma_count(unsigned int dmanr, unsigned int count)
-{
-	count--;  /* transfers one more than count -- correct for this */
-
-	outb(MCA_DMA_FN_SET_COUNT | dmanr, MCA_DMA_REG_FN);
-	outb(count & 0xff, MCA_DMA_REG_EXE);
-	outb((count >> 8) & 0xff, MCA_DMA_REG_EXE);
-}
-
-/**
- *	mca_get_dma_residue -	get the remaining bytes to transfer
- *	@dmanr: DMA channel
- *
- *	This function returns the number of bytes left to transfer
- *	on this DMA channel.
- */
-
-static inline unsigned int mca_get_dma_residue(unsigned int dmanr)
-{
-	unsigned short count;
-
-	outb(MCA_DMA_FN_GET_COUNT | dmanr, MCA_DMA_REG_FN);
-	count = 1 + inb(MCA_DMA_REG_EXE);
-	count += inb(MCA_DMA_REG_EXE) << 8;
-
-	return count;
-}
-
-/**
- *	mca_set_dma_io -	set the port for an I/O transfer
- *	@dmanr: DMA channel
- *	@io_addr: an I/O port number
- *
- *	Unlike the ISA bus DMA controllers the DMA on MCA bus can transfer
- *	with an I/O port target.
- */
-
-static inline void mca_set_dma_io(unsigned int dmanr, unsigned int io_addr)
-{
-	/*
-	 * DMA from a port address -- set the io address
-	 */
-
-	outb(MCA_DMA_FN_SET_IO | dmanr, MCA_DMA_REG_FN);
-	outb(io_addr & 0xff, MCA_DMA_REG_EXE);
-	outb((io_addr >>  8) & 0xff, MCA_DMA_REG_EXE);
-}
-
-/**
- *	mca_set_dma_mode -	set the DMA mode
- *	@dmanr: DMA channel
- *	@mode: mode to set
- *
- *	The DMA controller supports several modes. The mode values you can
- *	set are-
- *
- *	%MCA_DMA_MODE_READ when reading from the DMA device.
- *
- *	%MCA_DMA_MODE_WRITE to writing to the DMA device.
- *
- *	%MCA_DMA_MODE_IO to do DMA to or from an I/O port.
- *
- *	%MCA_DMA_MODE_16 to do 16bit transfers.
- */
-
-static inline void mca_set_dma_mode(unsigned int dmanr, unsigned int mode)
-{
-	outb(MCA_DMA_FN_SET_MODE | dmanr, MCA_DMA_REG_FN);
-	outb(mode, MCA_DMA_REG_EXE);
-}
-
-#endif /* ASM_X86__MCA_DMA_H */
diff --git a/include/asm-x86/mce.h b/include/asm-x86/mce.h
deleted file mode 100644
index 036133eaf744..000000000000
--- a/include/asm-x86/mce.h
+++ /dev/null
@@ -1,130 +0,0 @@
-#ifndef ASM_X86__MCE_H
-#define ASM_X86__MCE_H
-
-#ifdef __x86_64__
-
-#include <asm/ioctls.h>
-#include <asm/types.h>
-
-/*
- * Machine Check support for x86
- */
-
-#define MCG_CTL_P	 (1UL<<8)   /* MCG_CAP register available */
-
-#define MCG_STATUS_RIPV  (1UL<<0)   /* restart ip valid */
-#define MCG_STATUS_EIPV  (1UL<<1)   /* ip points to correct instruction */
-#define MCG_STATUS_MCIP  (1UL<<2)   /* machine check in progress */
-
-#define MCI_STATUS_VAL   (1UL<<63)  /* valid error */
-#define MCI_STATUS_OVER  (1UL<<62)  /* previous errors lost */
-#define MCI_STATUS_UC    (1UL<<61)  /* uncorrected error */
-#define MCI_STATUS_EN    (1UL<<60)  /* error enabled */
-#define MCI_STATUS_MISCV (1UL<<59)  /* misc error reg. valid */
-#define MCI_STATUS_ADDRV (1UL<<58)  /* addr reg. valid */
-#define MCI_STATUS_PCC   (1UL<<57)  /* processor context corrupt */
-
-/* Fields are zero when not available */
-struct mce {
-	__u64 status;
-	__u64 misc;
-	__u64 addr;
-	__u64 mcgstatus;
-	__u64 ip;
-	__u64 tsc;	/* cpu time stamp counter */
-	__u64 res1;	/* for future extension */
-	__u64 res2;	/* dito. */
-	__u8  cs;		/* code segment */
-	__u8  bank;	/* machine check bank */
-	__u8  cpu;	/* cpu that raised the error */
-	__u8  finished;   /* entry is valid */
-	__u32 pad;
-};
-
-/*
- * This structure contains all data related to the MCE log.  Also
- * carries a signature to make it easier to find from external
- * debugging tools.  Each entry is only valid when its finished flag
- * is set.
- */
-
-#define MCE_LOG_LEN 32
-
-struct mce_log {
-	char signature[12]; /* "MACHINECHECK" */
-	unsigned len;	    /* = MCE_LOG_LEN */
-	unsigned next;
-	unsigned flags;
-	unsigned pad0;
-	struct mce entry[MCE_LOG_LEN];
-};
-
-#define MCE_OVERFLOW 0		/* bit 0 in flags means overflow */
-
-#define MCE_LOG_SIGNATURE	"MACHINECHECK"
-
-#define MCE_GET_RECORD_LEN   _IOR('M', 1, int)
-#define MCE_GET_LOG_LEN      _IOR('M', 2, int)
-#define MCE_GETCLEAR_FLAGS   _IOR('M', 3, int)
-
-/* Software defined banks */
-#define MCE_EXTENDED_BANK	128
-#define MCE_THERMAL_BANK	MCE_EXTENDED_BANK + 0
-
-#define K8_MCE_THRESHOLD_BASE      (MCE_EXTENDED_BANK + 1)      /* MCE_AMD */
-#define K8_MCE_THRESHOLD_BANK_0    (MCE_THRESHOLD_BASE + 0 * 9)
-#define K8_MCE_THRESHOLD_BANK_1    (MCE_THRESHOLD_BASE + 1 * 9)
-#define K8_MCE_THRESHOLD_BANK_2    (MCE_THRESHOLD_BASE + 2 * 9)
-#define K8_MCE_THRESHOLD_BANK_3    (MCE_THRESHOLD_BASE + 3 * 9)
-#define K8_MCE_THRESHOLD_BANK_4    (MCE_THRESHOLD_BASE + 4 * 9)
-#define K8_MCE_THRESHOLD_BANK_5    (MCE_THRESHOLD_BASE + 5 * 9)
-#define K8_MCE_THRESHOLD_DRAM_ECC  (MCE_THRESHOLD_BANK_4 + 0)
-
-#endif /* __x86_64__ */
-
-#ifdef __KERNEL__
-
-#ifdef CONFIG_X86_32
-extern int mce_disabled;
-#else /* CONFIG_X86_32 */
-
-#include <asm/atomic.h>
-
-void mce_log(struct mce *m);
-DECLARE_PER_CPU(struct sys_device, device_mce);
-extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
-
-#ifdef CONFIG_X86_MCE_INTEL
-void mce_intel_feature_init(struct cpuinfo_x86 *c);
-#else
-static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
-#endif
-
-#ifdef CONFIG_X86_MCE_AMD
-void mce_amd_feature_init(struct cpuinfo_x86 *c);
-#else
-static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
-#endif
-
-void mce_log_therm_throt_event(unsigned int cpu, __u64 status);
-
-extern atomic_t mce_entry;
-
-extern void do_machine_check(struct pt_regs *, long);
-extern int mce_notify_user(void);
-
-#endif /* !CONFIG_X86_32 */
-
-
-
-#ifdef CONFIG_X86_MCE
-extern void mcheck_init(struct cpuinfo_x86 *c);
-#else
-#define mcheck_init(c) do { } while (0)
-#endif
-extern void stop_mce(void);
-extern void restart_mce(void);
-
-#endif /* __KERNEL__ */
-
-#endif /* ASM_X86__MCE_H */
diff --git a/include/asm-x86/microcode.h b/include/asm-x86/microcode.h
deleted file mode 100644
index 62c793bb70ca..000000000000
--- a/include/asm-x86/microcode.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef ASM_X86__MICROCODE_H
-#define ASM_X86__MICROCODE_H
-
-struct cpu_signature {
-	unsigned int sig;
-	unsigned int pf;
-	unsigned int rev;
-};
-
-struct device;
-
-struct microcode_ops {
-	int  (*request_microcode_user) (int cpu, const void __user *buf, size_t size);
-	int  (*request_microcode_fw) (int cpu, struct device *device);
-
-	void (*apply_microcode) (int cpu);
-
-	int  (*collect_cpu_info) (int cpu, struct cpu_signature *csig);
-	void (*microcode_fini_cpu) (int cpu);
-};
-
-struct ucode_cpu_info {
-	struct cpu_signature cpu_sig;
-	int valid;
-	void *mc;
-};
-extern struct ucode_cpu_info ucode_cpu_info[];
-
-#ifdef CONFIG_MICROCODE_INTEL
-extern struct microcode_ops * __init init_intel_microcode(void);
-#else
-static inline struct microcode_ops * __init init_intel_microcode(void)
-{
-	return NULL;
-}
-#endif /* CONFIG_MICROCODE_INTEL */
-
-#ifdef CONFIG_MICROCODE_AMD
-extern struct microcode_ops * __init init_amd_microcode(void);
-#else
-static inline struct microcode_ops * __init init_amd_microcode(void)
-{
-	return NULL;
-}
-#endif
-
-#endif /* ASM_X86__MICROCODE_H */
diff --git a/include/asm-x86/mman.h b/include/asm-x86/mman.h
deleted file mode 100644
index 4ef28e6de383..000000000000
--- a/include/asm-x86/mman.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef ASM_X86__MMAN_H
-#define ASM_X86__MMAN_H
-
-#include <asm-generic/mman.h>
-
-#define MAP_32BIT	0x40		/* only give out 32bit addresses */
-
-#define MAP_GROWSDOWN	0x0100		/* stack-like segment */
-#define MAP_DENYWRITE	0x0800		/* ETXTBSY */
-#define MAP_EXECUTABLE	0x1000		/* mark it as an executable */
-#define MAP_LOCKED	0x2000		/* pages are locked */
-#define MAP_NORESERVE	0x4000		/* don't check for reservations */
-#define MAP_POPULATE	0x8000		/* populate (prefault) pagetables */
-#define MAP_NONBLOCK	0x10000		/* do not block on IO */
-#define MAP_STACK	0x20000		/* give out an address that is best suited for process/thread stacks */
-
-#define MCL_CURRENT	1		/* lock all current mappings */
-#define MCL_FUTURE	2		/* lock all future mappings */
-
-#endif /* ASM_X86__MMAN_H */
diff --git a/include/asm-x86/mmconfig.h b/include/asm-x86/mmconfig.h
deleted file mode 100644
index fb79b1cf5d07..000000000000
--- a/include/asm-x86/mmconfig.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef ASM_X86__MMCONFIG_H
-#define ASM_X86__MMCONFIG_H
-
-#ifdef CONFIG_PCI_MMCONFIG
-extern void __cpuinit fam10h_check_enable_mmcfg(void);
-extern void __cpuinit check_enable_amd_mmconf_dmi(void);
-#else
-static inline void fam10h_check_enable_mmcfg(void) { }
-static inline void check_enable_amd_mmconf_dmi(void) { }
-#endif
-
-#endif /* ASM_X86__MMCONFIG_H */
diff --git a/include/asm-x86/mmu.h b/include/asm-x86/mmu.h
deleted file mode 100644
index 9d5aff14334a..000000000000
--- a/include/asm-x86/mmu.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef ASM_X86__MMU_H
-#define ASM_X86__MMU_H
-
-#include <linux/spinlock.h>
-#include <linux/mutex.h>
-
-/*
- * The x86 doesn't have a mmu context, but
- * we put the segment information here.
- */
-typedef struct {
-	void *ldt;
-	int size;
-	struct mutex lock;
-	void *vdso;
-} mm_context_t;
-
-#ifdef CONFIG_SMP
-void leave_mm(int cpu);
-#else
-static inline void leave_mm(int cpu)
-{
-}
-#endif
-
-#endif /* ASM_X86__MMU_H */
diff --git a/include/asm-x86/mmu_context.h b/include/asm-x86/mmu_context.h
deleted file mode 100644
index 8ec940bfd079..000000000000
--- a/include/asm-x86/mmu_context.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#ifndef ASM_X86__MMU_CONTEXT_H
-#define ASM_X86__MMU_CONTEXT_H
-
-#include <asm/desc.h>
-#include <asm/atomic.h>
-#include <asm/pgalloc.h>
-#include <asm/tlbflush.h>
-#include <asm/paravirt.h>
-#ifndef CONFIG_PARAVIRT
-#include <asm-generic/mm_hooks.h>
-
-static inline void paravirt_activate_mm(struct mm_struct *prev,
-					struct mm_struct *next)
-{
-}
-#endif	/* !CONFIG_PARAVIRT */
-
-/*
- * Used for LDT copy/destruction.
- */
-int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
-void destroy_context(struct mm_struct *mm);
-
-#ifdef CONFIG_X86_32
-# include "mmu_context_32.h"
-#else
-# include "mmu_context_64.h"
-#endif
-
-#define activate_mm(prev, next)			\
-do {						\
-	paravirt_activate_mm((prev), (next));	\
-	switch_mm((prev), (next), NULL);	\
-} while (0);
-
-
-#endif /* ASM_X86__MMU_CONTEXT_H */
diff --git a/include/asm-x86/mmu_context_32.h b/include/asm-x86/mmu_context_32.h
deleted file mode 100644
index cce6f6e4afd6..000000000000
--- a/include/asm-x86/mmu_context_32.h
+++ /dev/null
@@ -1,56 +0,0 @@
-#ifndef ASM_X86__MMU_CONTEXT_32_H
-#define ASM_X86__MMU_CONTEXT_32_H
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-#ifdef CONFIG_SMP
-	unsigned cpu = smp_processor_id();
-	if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
-		per_cpu(cpu_tlbstate, cpu).state = TLBSTATE_LAZY;
-#endif
-}
-
-static inline void switch_mm(struct mm_struct *prev,
-			     struct mm_struct *next,
-			     struct task_struct *tsk)
-{
-	int cpu = smp_processor_id();
-
-	if (likely(prev != next)) {
-		/* stop flush ipis for the previous mm */
-		cpu_clear(cpu, prev->cpu_vm_mask);
-#ifdef CONFIG_SMP
-		per_cpu(cpu_tlbstate, cpu).state = TLBSTATE_OK;
-		per_cpu(cpu_tlbstate, cpu).active_mm = next;
-#endif
-		cpu_set(cpu, next->cpu_vm_mask);
-
-		/* Re-load page tables */
-		load_cr3(next->pgd);
-
-		/*
-		 * load the LDT, if the LDT is different:
-		 */
-		if (unlikely(prev->context.ldt != next->context.ldt))
-			load_LDT_nolock(&next->context);
-	}
-#ifdef CONFIG_SMP
-	else {
-		per_cpu(cpu_tlbstate, cpu).state = TLBSTATE_OK;
-		BUG_ON(per_cpu(cpu_tlbstate, cpu).active_mm != next);
-
-		if (!cpu_test_and_set(cpu, next->cpu_vm_mask)) {
-			/* We were in lazy tlb mode and leave_mm disabled
-			 * tlb flush IPI delivery. We must reload %cr3.
-			 */
-			load_cr3(next->pgd);
-			load_LDT_nolock(&next->context);
-		}
-	}
-#endif
-}
-
-#define deactivate_mm(tsk, mm)			\
-	asm("movl %0,%%gs": :"r" (0));
-
-#endif /* ASM_X86__MMU_CONTEXT_32_H */
diff --git a/include/asm-x86/mmu_context_64.h b/include/asm-x86/mmu_context_64.h
deleted file mode 100644
index 26758673c828..000000000000
--- a/include/asm-x86/mmu_context_64.h
+++ /dev/null
@@ -1,54 +0,0 @@
-#ifndef ASM_X86__MMU_CONTEXT_64_H
-#define ASM_X86__MMU_CONTEXT_64_H
-
-#include <asm/pda.h>
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-#ifdef CONFIG_SMP
-	if (read_pda(mmu_state) == TLBSTATE_OK)
-		write_pda(mmu_state, TLBSTATE_LAZY);
-#endif
-}
-
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
-			     struct task_struct *tsk)
-{
-	unsigned cpu = smp_processor_id();
-	if (likely(prev != next)) {
-		/* stop flush ipis for the previous mm */
-		cpu_clear(cpu, prev->cpu_vm_mask);
-#ifdef CONFIG_SMP
-		write_pda(mmu_state, TLBSTATE_OK);
-		write_pda(active_mm, next);
-#endif
-		cpu_set(cpu, next->cpu_vm_mask);
-		load_cr3(next->pgd);
-
-		if (unlikely(next->context.ldt != prev->context.ldt))
-			load_LDT_nolock(&next->context);
-	}
-#ifdef CONFIG_SMP
-	else {
-		write_pda(mmu_state, TLBSTATE_OK);
-		if (read_pda(active_mm) != next)
-			BUG();
-		if (!cpu_test_and_set(cpu, next->cpu_vm_mask)) {
-			/* We were in lazy tlb mode and leave_mm disabled
-			 * tlb flush IPI delivery. We must reload CR3
-			 * to make sure to use no freed page tables.
-			 */
-			load_cr3(next->pgd);
-			load_LDT_nolock(&next->context);
-		}
-	}
-#endif
-}
-
-#define deactivate_mm(tsk, mm)			\
-do {						\
-	load_gs_index(0);			\
-	asm volatile("movl %0,%%fs"::"r"(0));	\
-} while (0)
-
-#endif /* ASM_X86__MMU_CONTEXT_64_H */
diff --git a/include/asm-x86/mmx.h b/include/asm-x86/mmx.h
deleted file mode 100644
index 2e7299bb3653..000000000000
--- a/include/asm-x86/mmx.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef ASM_X86__MMX_H
-#define ASM_X86__MMX_H
-
-/*
- *	MMX 3Dnow! helper operations
- */
-
-#include <linux/types.h>
-
-extern void *_mmx_memcpy(void *to, const void *from, size_t size);
-extern void mmx_clear_page(void *page);
-extern void mmx_copy_page(void *to, void *from);
-
-#endif /* ASM_X86__MMX_H */
diff --git a/include/asm-x86/mmzone.h b/include/asm-x86/mmzone.h
deleted file mode 100644
index 64217ea16a36..000000000000
--- a/include/asm-x86/mmzone.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifdef CONFIG_X86_32
-# include "mmzone_32.h"
-#else
-# include "mmzone_64.h"
-#endif
diff --git a/include/asm-x86/mmzone_32.h b/include/asm-x86/mmzone_32.h
deleted file mode 100644
index 121b65d61d86..000000000000
--- a/include/asm-x86/mmzone_32.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * Written by Pat Gaughen (gone@us.ibm.com) Mar 2002
- *
- */
-
-#ifndef ASM_X86__MMZONE_32_H
-#define ASM_X86__MMZONE_32_H
-
-#include <asm/smp.h>
-
-#ifdef CONFIG_NUMA
-extern struct pglist_data *node_data[];
-#define NODE_DATA(nid)	(node_data[nid])
-
-#include <asm/numaq.h>
-/* summit or generic arch */
-#include <asm/srat.h>
-
-extern int get_memcfg_numa_flat(void);
-/*
- * This allows any one NUMA architecture to be compiled
- * for, and still fall back to the flat function if it
- * fails.
- */
-static inline void get_memcfg_numa(void)
-{
-
-	if (get_memcfg_numaq())
-		return;
-	if (get_memcfg_from_srat())
-		return;
-	get_memcfg_numa_flat();
-}
-
-extern int early_pfn_to_nid(unsigned long pfn);
-
-#else /* !CONFIG_NUMA */
-
-#define get_memcfg_numa get_memcfg_numa_flat
-
-#endif /* CONFIG_NUMA */
-
-#ifdef CONFIG_DISCONTIGMEM
-
-/*
- * generic node memory support, the following assumptions apply:
- *
- * 1) memory comes in 64Mb contigious chunks which are either present or not
- * 2) we will not have more than 64Gb in total
- *
- * for now assume that 64Gb is max amount of RAM for whole system
- *    64Gb / 4096bytes/page = 16777216 pages
- */
-#define MAX_NR_PAGES 16777216
-#define MAX_ELEMENTS 1024
-#define PAGES_PER_ELEMENT (MAX_NR_PAGES/MAX_ELEMENTS)
-
-extern s8 physnode_map[];
-
-static inline int pfn_to_nid(unsigned long pfn)
-{
-#ifdef CONFIG_NUMA
-	return((int) physnode_map[(pfn) / PAGES_PER_ELEMENT]);
-#else
-	return 0;
-#endif
-}
-
-/*
- * Following are macros that each numa implmentation must define.
- */
-
-#define node_start_pfn(nid)	(NODE_DATA(nid)->node_start_pfn)
-#define node_end_pfn(nid)						\
-({									\
-	pg_data_t *__pgdat = NODE_DATA(nid);				\
-	__pgdat->node_start_pfn + __pgdat->node_spanned_pages;		\
-})
-
-static inline int pfn_valid(int pfn)
-{
-	int nid = pfn_to_nid(pfn);
-
-	if (nid >= 0)
-		return (pfn < node_end_pfn(nid));
-	return 0;
-}
-
-#endif /* CONFIG_DISCONTIGMEM */
-
-#ifdef CONFIG_NEED_MULTIPLE_NODES
-
-/*
- * Following are macros that are specific to this numa platform.
- */
-#define reserve_bootmem(addr, size, flags) \
-	reserve_bootmem_node(NODE_DATA(0), (addr), (size), (flags))
-#define alloc_bootmem(x) \
-	__alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
-#define alloc_bootmem_nopanic(x) \
-	__alloc_bootmem_node_nopanic(NODE_DATA(0), (x), SMP_CACHE_BYTES, \
-				__pa(MAX_DMA_ADDRESS))
-#define alloc_bootmem_low(x) \
-	__alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, 0)
-#define alloc_bootmem_pages(x) \
-	__alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
-#define alloc_bootmem_pages_nopanic(x) \
-	__alloc_bootmem_node_nopanic(NODE_DATA(0), (x), PAGE_SIZE, \
-				__pa(MAX_DMA_ADDRESS))
-#define alloc_bootmem_low_pages(x) \
-	__alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, 0)
-#define alloc_bootmem_node(pgdat, x)					\
-({									\
-	struct pglist_data  __maybe_unused			\
-				*__alloc_bootmem_node__pgdat = (pgdat);	\
-	__alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES,	\
-						__pa(MAX_DMA_ADDRESS));	\
-})
-#define alloc_bootmem_pages_node(pgdat, x)				\
-({									\
-	struct pglist_data  __maybe_unused			\
-				*__alloc_bootmem_node__pgdat = (pgdat);	\
-	__alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE,		\
-						__pa(MAX_DMA_ADDRESS));	\
-})
-#define alloc_bootmem_low_pages_node(pgdat, x)				\
-({									\
-	struct pglist_data  __maybe_unused			\
-				*__alloc_bootmem_node__pgdat = (pgdat);	\
-	__alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, 0);		\
-})
-#endif /* CONFIG_NEED_MULTIPLE_NODES */
-
-#endif /* ASM_X86__MMZONE_32_H */
diff --git a/include/asm-x86/mmzone_64.h b/include/asm-x86/mmzone_64.h
deleted file mode 100644
index 6480f3333b2a..000000000000
--- a/include/asm-x86/mmzone_64.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* K8 NUMA support */
-/* Copyright 2002,2003 by Andi Kleen, SuSE Labs */
-/* 2.5 Version loosely based on the NUMAQ Code by Pat Gaughen. */
-#ifndef ASM_X86__MMZONE_64_H
-#define ASM_X86__MMZONE_64_H
-
-
-#ifdef CONFIG_NUMA
-
-#include <linux/mmdebug.h>
-
-#include <asm/smp.h>
-
-/* Simple perfect hash to map physical addresses to node numbers */
-struct memnode {
-	int shift;
-	unsigned int mapsize;
-	s16 *map;
-	s16 embedded_map[64 - 8];
-} ____cacheline_aligned; /* total size = 128 bytes */
-extern struct memnode memnode;
-#define memnode_shift memnode.shift
-#define memnodemap memnode.map
-#define memnodemapsize memnode.mapsize
-
-extern struct pglist_data *node_data[];
-
-static inline __attribute__((pure)) int phys_to_nid(unsigned long addr)
-{
-	unsigned nid;
-	VIRTUAL_BUG_ON(!memnodemap);
-	nid = memnodemap[addr >> memnode_shift];
-	VIRTUAL_BUG_ON(nid >= MAX_NUMNODES || !node_data[nid]);
-	return nid;
-}
-
-#define NODE_DATA(nid)		(node_data[nid])
-
-#define node_start_pfn(nid)	(NODE_DATA(nid)->node_start_pfn)
-#define node_end_pfn(nid)       (NODE_DATA(nid)->node_start_pfn +	\
-				 NODE_DATA(nid)->node_spanned_pages)
-
-extern int early_pfn_to_nid(unsigned long pfn);
-
-#ifdef CONFIG_NUMA_EMU
-#define FAKE_NODE_MIN_SIZE	(64 * 1024 * 1024)
-#define FAKE_NODE_MIN_HASH_MASK	(~(FAKE_NODE_MIN_SIZE - 1UL))
-#endif
-
-#endif
-#endif /* ASM_X86__MMZONE_64_H */
diff --git a/include/asm-x86/module.h b/include/asm-x86/module.h
deleted file mode 100644
index 864f2005fc1d..000000000000
--- a/include/asm-x86/module.h
+++ /dev/null
@@ -1,80 +0,0 @@
-#ifndef ASM_X86__MODULE_H
-#define ASM_X86__MODULE_H
-
-/* x86_32/64 are simple */
-struct mod_arch_specific {};
-
-#ifdef CONFIG_X86_32
-# define Elf_Shdr Elf32_Shdr
-# define Elf_Sym Elf32_Sym
-# define Elf_Ehdr Elf32_Ehdr
-#else
-# define Elf_Shdr Elf64_Shdr
-# define Elf_Sym Elf64_Sym
-# define Elf_Ehdr Elf64_Ehdr
-#endif
-
-#ifdef CONFIG_X86_64
-/* X86_64 does not define MODULE_PROC_FAMILY */
-#elif defined CONFIG_M386
-#define MODULE_PROC_FAMILY "386 "
-#elif defined CONFIG_M486
-#define MODULE_PROC_FAMILY "486 "
-#elif defined CONFIG_M586
-#define MODULE_PROC_FAMILY "586 "
-#elif defined CONFIG_M586TSC
-#define MODULE_PROC_FAMILY "586TSC "
-#elif defined CONFIG_M586MMX
-#define MODULE_PROC_FAMILY "586MMX "
-#elif defined CONFIG_MCORE2
-#define MODULE_PROC_FAMILY "CORE2 "
-#elif defined CONFIG_M686
-#define MODULE_PROC_FAMILY "686 "
-#elif defined CONFIG_MPENTIUMII
-#define MODULE_PROC_FAMILY "PENTIUMII "
-#elif defined CONFIG_MPENTIUMIII
-#define MODULE_PROC_FAMILY "PENTIUMIII "
-#elif defined CONFIG_MPENTIUMM
-#define MODULE_PROC_FAMILY "PENTIUMM "
-#elif defined CONFIG_MPENTIUM4
-#define MODULE_PROC_FAMILY "PENTIUM4 "
-#elif defined CONFIG_MK6
-#define MODULE_PROC_FAMILY "K6 "
-#elif defined CONFIG_MK7
-#define MODULE_PROC_FAMILY "K7 "
-#elif defined CONFIG_MK8
-#define MODULE_PROC_FAMILY "K8 "
-#elif defined CONFIG_X86_ELAN
-#define MODULE_PROC_FAMILY "ELAN "
-#elif defined CONFIG_MCRUSOE
-#define MODULE_PROC_FAMILY "CRUSOE "
-#elif defined CONFIG_MEFFICEON
-#define MODULE_PROC_FAMILY "EFFICEON "
-#elif defined CONFIG_MWINCHIPC6
-#define MODULE_PROC_FAMILY "WINCHIPC6 "
-#elif defined CONFIG_MWINCHIP3D
-#define MODULE_PROC_FAMILY "WINCHIP3D "
-#elif defined CONFIG_MCYRIXIII
-#define MODULE_PROC_FAMILY "CYRIXIII "
-#elif defined CONFIG_MVIAC3_2
-#define MODULE_PROC_FAMILY "VIAC3-2 "
-#elif defined CONFIG_MVIAC7
-#define MODULE_PROC_FAMILY "VIAC7 "
-#elif defined CONFIG_MGEODEGX1
-#define MODULE_PROC_FAMILY "GEODEGX1 "
-#elif defined CONFIG_MGEODE_LX
-#define MODULE_PROC_FAMILY "GEODE "
-#else
-#error unknown processor family
-#endif
-
-#ifdef CONFIG_X86_32
-# ifdef CONFIG_4KSTACKS
-#  define MODULE_STACKSIZE "4KSTACKS "
-# else
-#  define MODULE_STACKSIZE ""
-# endif
-# define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY MODULE_STACKSIZE
-#endif
-
-#endif /* ASM_X86__MODULE_H */
diff --git a/include/asm-x86/mpspec.h b/include/asm-x86/mpspec.h
deleted file mode 100644
index be2241a818f1..000000000000
--- a/include/asm-x86/mpspec.h
+++ /dev/null
@@ -1,145 +0,0 @@
-#ifndef ASM_X86__MPSPEC_H
-#define ASM_X86__MPSPEC_H
-
-#include <linux/init.h>
-
-#include <asm/mpspec_def.h>
-
-extern int apic_version[MAX_APICS];
-
-#ifdef CONFIG_X86_32
-#include <mach_mpspec.h>
-
-extern unsigned int def_to_bigsmp;
-extern u8 apicid_2_node[];
-extern int pic_mode;
-
-#ifdef CONFIG_X86_NUMAQ
-extern int mp_bus_id_to_node[MAX_MP_BUSSES];
-extern int mp_bus_id_to_local[MAX_MP_BUSSES];
-extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
-#endif
-
-#define MAX_APICID 256
-
-#else
-
-#define MAX_MP_BUSSES 256
-/* Each PCI slot may be a combo card with its own bus.  4 IRQ pins per slot. */
-#define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
-
-#endif
-
-extern void early_find_smp_config(void);
-extern void early_get_smp_config(void);
-
-#if defined(CONFIG_MCA) || defined(CONFIG_EISA)
-extern int mp_bus_id_to_type[MAX_MP_BUSSES];
-#endif
-
-extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
-
-extern unsigned int boot_cpu_physical_apicid;
-extern unsigned int max_physical_apicid;
-extern int smp_found_config;
-extern int mpc_default_type;
-extern unsigned long mp_lapic_addr;
-
-extern void find_smp_config(void);
-extern void get_smp_config(void);
-#ifdef CONFIG_X86_MPPARSE
-extern void early_reserve_e820_mpc_new(void);
-#else
-static inline void early_reserve_e820_mpc_new(void) { }
-#endif
-
-void __cpuinit generic_processor_info(int apicid, int version);
-#ifdef CONFIG_ACPI
-extern void mp_register_ioapic(int id, u32 address, u32 gsi_base);
-extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
-				   u32 gsi);
-extern void mp_config_acpi_legacy_irqs(void);
-extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low);
-#ifdef CONFIG_X86_IO_APIC
-extern int mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin,
-				u32 gsi, int triggering, int polarity);
-#else
-static inline int
-mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin,
-		   u32 gsi, int triggering, int polarity)
-{
-	return 0;
-}
-#endif
-#endif /* CONFIG_ACPI */
-
-#define PHYSID_ARRAY_SIZE	BITS_TO_LONGS(MAX_APICS)
-
-struct physid_mask {
-	unsigned long mask[PHYSID_ARRAY_SIZE];
-};
-
-typedef struct physid_mask physid_mask_t;
-
-#define physid_set(physid, map)			set_bit(physid, (map).mask)
-#define physid_clear(physid, map)		clear_bit(physid, (map).mask)
-#define physid_isset(physid, map)		test_bit(physid, (map).mask)
-#define physid_test_and_set(physid, map)			\
-	test_and_set_bit(physid, (map).mask)
-
-#define physids_and(dst, src1, src2)					\
-	bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
-
-#define physids_or(dst, src1, src2)					\
-	bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
-
-#define physids_clear(map)					\
-	bitmap_zero((map).mask, MAX_APICS)
-
-#define physids_complement(dst, src)				\
-	bitmap_complement((dst).mask, (src).mask, MAX_APICS)
-
-#define physids_empty(map)					\
-	bitmap_empty((map).mask, MAX_APICS)
-
-#define physids_equal(map1, map2)				\
-	bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
-
-#define physids_weight(map)					\
-	bitmap_weight((map).mask, MAX_APICS)
-
-#define physids_shift_right(d, s, n)				\
-	bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
-
-#define physids_shift_left(d, s, n)				\
-	bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
-
-#define physids_coerce(map)			((map).mask[0])
-
-#define physids_promote(physids)					\
-	({								\
-		physid_mask_t __physid_mask = PHYSID_MASK_NONE;		\
-		__physid_mask.mask[0] = physids;			\
-		__physid_mask;						\
-	})
-
-/* Note: will create very large stack frames if physid_mask_t is big */
-#define physid_mask_of_physid(physid)					\
-	({								\
-		physid_mask_t __physid_mask = PHYSID_MASK_NONE;		\
-		physid_set(physid, __physid_mask);			\
-		__physid_mask;						\
-	})
-
-static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map)
-{
-	physids_clear(*map);
-	physid_set(physid, *map);
-}
-
-#define PHYSID_MASK_ALL		{ {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
-#define PHYSID_MASK_NONE	{ {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
-
-extern physid_mask_t phys_cpu_present_map;
-
-#endif /* ASM_X86__MPSPEC_H */
diff --git a/include/asm-x86/mpspec_def.h b/include/asm-x86/mpspec_def.h
deleted file mode 100644
index 79166b048012..000000000000
--- a/include/asm-x86/mpspec_def.h
+++ /dev/null
@@ -1,180 +0,0 @@
-#ifndef ASM_X86__MPSPEC_DEF_H
-#define ASM_X86__MPSPEC_DEF_H
-
-/*
- * Structure definitions for SMP machines following the
- * Intel Multiprocessing Specification 1.1 and 1.4.
- */
-
-/*
- * This tag identifies where the SMP configuration
- * information is.
- */
-
-#define SMP_MAGIC_IDENT	(('_'<<24) | ('P'<<16) | ('M'<<8) | '_')
-
-#ifdef CONFIG_X86_32
-# define MAX_MPC_ENTRY 1024
-# define MAX_APICS      256
-#else
-# if NR_CPUS <= 255
-#  define MAX_APICS     255
-# else
-#  define MAX_APICS   32768
-# endif
-#endif
-
-struct intel_mp_floating {
-	char mpf_signature[4];		/* "_MP_"			*/
-	unsigned int mpf_physptr;	/* Configuration table address	*/
-	unsigned char mpf_length;	/* Our length (paragraphs)	*/
-	unsigned char mpf_specification;/* Specification version	*/
-	unsigned char mpf_checksum;	/* Checksum (makes sum 0)	*/
-	unsigned char mpf_feature1;	/* Standard or configuration ?	*/
-	unsigned char mpf_feature2;	/* Bit7 set for IMCR|PIC	*/
-	unsigned char mpf_feature3;	/* Unused (0)			*/
-	unsigned char mpf_feature4;	/* Unused (0)			*/
-	unsigned char mpf_feature5;	/* Unused (0)			*/
-};
-
-#define MPC_SIGNATURE "PCMP"
-
-struct mp_config_table {
-	char mpc_signature[4];
-	unsigned short mpc_length;	/* Size of table */
-	char mpc_spec;			/* 0x01 */
-	char mpc_checksum;
-	char mpc_oem[8];
-	char mpc_productid[12];
-	unsigned int mpc_oemptr;	/* 0 if not present */
-	unsigned short mpc_oemsize;	/* 0 if not present */
-	unsigned short mpc_oemcount;
-	unsigned int mpc_lapic;	/* APIC address */
-	unsigned int reserved;
-};
-
-/* Followed by entries */
-
-#define	MP_PROCESSOR		0
-#define	MP_BUS			1
-#define	MP_IOAPIC		2
-#define	MP_INTSRC		3
-#define	MP_LINTSRC		4
-/* Used by IBM NUMA-Q to describe node locality */
-#define	MP_TRANSLATION		192
-
-#define CPU_ENABLED		1	/* Processor is available */
-#define CPU_BOOTPROCESSOR	2	/* Processor is the BP */
-
-#define CPU_STEPPING_MASK	0x000F
-#define CPU_MODEL_MASK		0x00F0
-#define CPU_FAMILY_MASK		0x0F00
-
-struct mpc_config_processor {
-	unsigned char mpc_type;
-	unsigned char mpc_apicid;	/* Local APIC number */
-	unsigned char mpc_apicver;	/* Its versions */
-	unsigned char mpc_cpuflag;
-	unsigned int mpc_cpufeature;
-	unsigned int mpc_featureflag;	/* CPUID feature value */
-	unsigned int mpc_reserved[2];
-};
-
-struct mpc_config_bus {
-	unsigned char mpc_type;
-	unsigned char mpc_busid;
-	unsigned char mpc_bustype[6];
-};
-
-/* List of Bus Type string values, Intel MP Spec. */
-#define BUSTYPE_EISA	"EISA"
-#define BUSTYPE_ISA	"ISA"
-#define BUSTYPE_INTERN	"INTERN"	/* Internal BUS */
-#define BUSTYPE_MCA	"MCA"
-#define BUSTYPE_VL	"VL"		/* Local bus */
-#define BUSTYPE_PCI	"PCI"
-#define BUSTYPE_PCMCIA	"PCMCIA"
-#define BUSTYPE_CBUS	"CBUS"
-#define BUSTYPE_CBUSII	"CBUSII"
-#define BUSTYPE_FUTURE	"FUTURE"
-#define BUSTYPE_MBI	"MBI"
-#define BUSTYPE_MBII	"MBII"
-#define BUSTYPE_MPI	"MPI"
-#define BUSTYPE_MPSA	"MPSA"
-#define BUSTYPE_NUBUS	"NUBUS"
-#define BUSTYPE_TC	"TC"
-#define BUSTYPE_VME	"VME"
-#define BUSTYPE_XPRESS	"XPRESS"
-
-#define MPC_APIC_USABLE		0x01
-
-struct mpc_config_ioapic {
-	unsigned char mpc_type;
-	unsigned char mpc_apicid;
-	unsigned char mpc_apicver;
-	unsigned char mpc_flags;
-	unsigned int mpc_apicaddr;
-};
-
-struct mpc_config_intsrc {
-	unsigned char mpc_type;
-	unsigned char mpc_irqtype;
-	unsigned short mpc_irqflag;
-	unsigned char mpc_srcbus;
-	unsigned char mpc_srcbusirq;
-	unsigned char mpc_dstapic;
-	unsigned char mpc_dstirq;
-};
-
-enum mp_irq_source_types {
-	mp_INT = 0,
-	mp_NMI = 1,
-	mp_SMI = 2,
-	mp_ExtINT = 3
-};
-
-#define MP_IRQDIR_DEFAULT	0
-#define MP_IRQDIR_HIGH		1
-#define MP_IRQDIR_LOW		3
-
-#define MP_APIC_ALL	0xFF
-
-struct mpc_config_lintsrc {
-	unsigned char mpc_type;
-	unsigned char mpc_irqtype;
-	unsigned short mpc_irqflag;
-	unsigned char mpc_srcbusid;
-	unsigned char mpc_srcbusirq;
-	unsigned char mpc_destapic;
-	unsigned char mpc_destapiclint;
-};
-
-#define MPC_OEM_SIGNATURE "_OEM"
-
-struct mp_config_oemtable {
-	char oem_signature[4];
-	unsigned short oem_length;	/* Size of table */
-	char  oem_rev;			/* 0x01 */
-	char  oem_checksum;
-	char  mpc_oem[8];
-};
-
-/*
- *	Default configurations
- *
- *	1	2 CPU ISA 82489DX
- *	2	2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
- *	3	2 CPU EISA 82489DX
- *	4	2 CPU MCA 82489DX
- *	5	2 CPU ISA+PCI
- *	6	2 CPU EISA+PCI
- *	7	2 CPU MCA+PCI
- */
-
-enum mp_bustype {
-	MP_BUS_ISA = 1,
-	MP_BUS_EISA,
-	MP_BUS_PCI,
-	MP_BUS_MCA,
-};
-#endif /* ASM_X86__MPSPEC_DEF_H */
diff --git a/include/asm-x86/msgbuf.h b/include/asm-x86/msgbuf.h
deleted file mode 100644
index 1b538c907a3d..000000000000
--- a/include/asm-x86/msgbuf.h
+++ /dev/null
@@ -1,39 +0,0 @@
-#ifndef ASM_X86__MSGBUF_H
-#define ASM_X86__MSGBUF_H
-
-/*
- * The msqid64_ds structure for i386 architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space on i386 is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- *
- * Pad space on x8664 is left for:
- * - 2 miscellaneous 64-bit values
- */
-struct msqid64_ds {
-	struct ipc64_perm msg_perm;
-	__kernel_time_t msg_stime;	/* last msgsnd time */
-#ifdef __i386__
-	unsigned long	__unused1;
-#endif
-	__kernel_time_t msg_rtime;	/* last msgrcv time */
-#ifdef __i386__
-	unsigned long	__unused2;
-#endif
-	__kernel_time_t msg_ctime;	/* last change time */
-#ifdef __i386__
-	unsigned long	__unused3;
-#endif
-	unsigned long  msg_cbytes;	/* current number of bytes on queue */
-	unsigned long  msg_qnum;	/* number of messages in queue */
-	unsigned long  msg_qbytes;	/* max number of bytes on queue */
-	__kernel_pid_t msg_lspid;	/* pid of last msgsnd */
-	__kernel_pid_t msg_lrpid;	/* last receive pid */
-	unsigned long  __unused4;
-	unsigned long  __unused5;
-};
-
-#endif /* ASM_X86__MSGBUF_H */
diff --git a/include/asm-x86/msidef.h b/include/asm-x86/msidef.h
deleted file mode 100644
index ed9190246876..000000000000
--- a/include/asm-x86/msidef.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef ASM_X86__MSIDEF_H
-#define ASM_X86__MSIDEF_H
-
-/*
- * Constants for Intel APIC based MSI messages.
- */
-
-/*
- * Shifts for MSI data
- */
-
-#define MSI_DATA_VECTOR_SHIFT		0
-#define  MSI_DATA_VECTOR_MASK		0x000000ff
-#define	 MSI_DATA_VECTOR(v)		(((v) << MSI_DATA_VECTOR_SHIFT) & \
-					 MSI_DATA_VECTOR_MASK)
-
-#define MSI_DATA_DELIVERY_MODE_SHIFT	8
-#define  MSI_DATA_DELIVERY_FIXED	(0 << MSI_DATA_DELIVERY_MODE_SHIFT)
-#define  MSI_DATA_DELIVERY_LOWPRI	(1 << MSI_DATA_DELIVERY_MODE_SHIFT)
-
-#define MSI_DATA_LEVEL_SHIFT		14
-#define	 MSI_DATA_LEVEL_DEASSERT	(0 << MSI_DATA_LEVEL_SHIFT)
-#define	 MSI_DATA_LEVEL_ASSERT		(1 << MSI_DATA_LEVEL_SHIFT)
-
-#define MSI_DATA_TRIGGER_SHIFT		15
-#define  MSI_DATA_TRIGGER_EDGE		(0 << MSI_DATA_TRIGGER_SHIFT)
-#define  MSI_DATA_TRIGGER_LEVEL		(1 << MSI_DATA_TRIGGER_SHIFT)
-
-/*
- * Shift/mask fields for msi address
- */
-
-#define MSI_ADDR_BASE_HI		0
-#define MSI_ADDR_BASE_LO		0xfee00000
-
-#define MSI_ADDR_DEST_MODE_SHIFT	2
-#define  MSI_ADDR_DEST_MODE_PHYSICAL	(0 << MSI_ADDR_DEST_MODE_SHIFT)
-#define	 MSI_ADDR_DEST_MODE_LOGICAL	(1 << MSI_ADDR_DEST_MODE_SHIFT)
-
-#define MSI_ADDR_REDIRECTION_SHIFT	3
-#define  MSI_ADDR_REDIRECTION_CPU	(0 << MSI_ADDR_REDIRECTION_SHIFT)
-					/* dedicated cpu */
-#define  MSI_ADDR_REDIRECTION_LOWPRI	(1 << MSI_ADDR_REDIRECTION_SHIFT)
-					/* lowest priority */
-
-#define MSI_ADDR_DEST_ID_SHIFT		12
-#define	 MSI_ADDR_DEST_ID_MASK		0x00ffff0
-#define  MSI_ADDR_DEST_ID(dest)		(((dest) << MSI_ADDR_DEST_ID_SHIFT) & \
-					 MSI_ADDR_DEST_ID_MASK)
-
-#define MSI_ADDR_IR_EXT_INT		(1 << 4)
-#define MSI_ADDR_IR_SHV			(1 << 3)
-#define MSI_ADDR_IR_INDEX1(index)	((index & 0x8000) >> 13)
-#define MSI_ADDR_IR_INDEX2(index)	((index & 0x7fff) << 5)
-#endif /* ASM_X86__MSIDEF_H */
diff --git a/include/asm-x86/msr-index.h b/include/asm-x86/msr-index.h
deleted file mode 100644
index 0bb43301a202..000000000000
--- a/include/asm-x86/msr-index.h
+++ /dev/null
@@ -1,329 +0,0 @@
-#ifndef ASM_X86__MSR_INDEX_H
-#define ASM_X86__MSR_INDEX_H
-
-/* CPU model specific register (MSR) numbers */
-
-/* x86-64 specific MSRs */
-#define MSR_EFER		0xc0000080 /* extended feature register */
-#define MSR_STAR		0xc0000081 /* legacy mode SYSCALL target */
-#define MSR_LSTAR		0xc0000082 /* long mode SYSCALL target */
-#define MSR_CSTAR		0xc0000083 /* compat mode SYSCALL target */
-#define MSR_SYSCALL_MASK	0xc0000084 /* EFLAGS mask for syscall */
-#define MSR_FS_BASE		0xc0000100 /* 64bit FS base */
-#define MSR_GS_BASE		0xc0000101 /* 64bit GS base */
-#define MSR_KERNEL_GS_BASE	0xc0000102 /* SwapGS GS shadow */
-
-/* EFER bits: */
-#define _EFER_SCE		0  /* SYSCALL/SYSRET */
-#define _EFER_LME		8  /* Long mode enable */
-#define _EFER_LMA		10 /* Long mode active (read-only) */
-#define _EFER_NX		11 /* No execute enable */
-
-#define EFER_SCE		(1<<_EFER_SCE)
-#define EFER_LME		(1<<_EFER_LME)
-#define EFER_LMA		(1<<_EFER_LMA)
-#define EFER_NX			(1<<_EFER_NX)
-
-/* Intel MSRs. Some also available on other CPUs */
-#define MSR_IA32_PERFCTR0		0x000000c1
-#define MSR_IA32_PERFCTR1		0x000000c2
-#define MSR_FSB_FREQ			0x000000cd
-
-#define MSR_MTRRcap			0x000000fe
-#define MSR_IA32_BBL_CR_CTL		0x00000119
-
-#define MSR_IA32_SYSENTER_CS		0x00000174
-#define MSR_IA32_SYSENTER_ESP		0x00000175
-#define MSR_IA32_SYSENTER_EIP		0x00000176
-
-#define MSR_IA32_MCG_CAP		0x00000179
-#define MSR_IA32_MCG_STATUS		0x0000017a
-#define MSR_IA32_MCG_CTL		0x0000017b
-
-#define MSR_IA32_PEBS_ENABLE		0x000003f1
-#define MSR_IA32_DS_AREA		0x00000600
-#define MSR_IA32_PERF_CAPABILITIES	0x00000345
-
-#define MSR_MTRRfix64K_00000		0x00000250
-#define MSR_MTRRfix16K_80000		0x00000258
-#define MSR_MTRRfix16K_A0000		0x00000259
-#define MSR_MTRRfix4K_C0000		0x00000268
-#define MSR_MTRRfix4K_C8000		0x00000269
-#define MSR_MTRRfix4K_D0000		0x0000026a
-#define MSR_MTRRfix4K_D8000		0x0000026b
-#define MSR_MTRRfix4K_E0000		0x0000026c
-#define MSR_MTRRfix4K_E8000		0x0000026d
-#define MSR_MTRRfix4K_F0000		0x0000026e
-#define MSR_MTRRfix4K_F8000		0x0000026f
-#define MSR_MTRRdefType			0x000002ff
-
-#define MSR_IA32_CR_PAT			0x00000277
-
-#define MSR_IA32_DEBUGCTLMSR		0x000001d9
-#define MSR_IA32_LASTBRANCHFROMIP	0x000001db
-#define MSR_IA32_LASTBRANCHTOIP		0x000001dc
-#define MSR_IA32_LASTINTFROMIP		0x000001dd
-#define MSR_IA32_LASTINTTOIP		0x000001de
-
-/* DEBUGCTLMSR bits (others vary by model): */
-#define _DEBUGCTLMSR_LBR	0 /* last branch recording */
-#define _DEBUGCTLMSR_BTF	1 /* single-step on branches */
-
-#define DEBUGCTLMSR_LBR		(1UL << _DEBUGCTLMSR_LBR)
-#define DEBUGCTLMSR_BTF		(1UL << _DEBUGCTLMSR_BTF)
-
-#define MSR_IA32_MC0_CTL		0x00000400
-#define MSR_IA32_MC0_STATUS		0x00000401
-#define MSR_IA32_MC0_ADDR		0x00000402
-#define MSR_IA32_MC0_MISC		0x00000403
-
-#define MSR_P6_PERFCTR0			0x000000c1
-#define MSR_P6_PERFCTR1			0x000000c2
-#define MSR_P6_EVNTSEL0			0x00000186
-#define MSR_P6_EVNTSEL1			0x00000187
-
-/* AMD64 MSRs. Not complete. See the architecture manual for a more
-   complete list. */
-
-#define MSR_AMD64_NB_CFG		0xc001001f
-#define MSR_AMD64_IBSFETCHCTL		0xc0011030
-#define MSR_AMD64_IBSFETCHLINAD		0xc0011031
-#define MSR_AMD64_IBSFETCHPHYSAD	0xc0011032
-#define MSR_AMD64_IBSOPCTL		0xc0011033
-#define MSR_AMD64_IBSOPRIP		0xc0011034
-#define MSR_AMD64_IBSOPDATA		0xc0011035
-#define MSR_AMD64_IBSOPDATA2		0xc0011036
-#define MSR_AMD64_IBSOPDATA3		0xc0011037
-#define MSR_AMD64_IBSDCLINAD		0xc0011038
-#define MSR_AMD64_IBSDCPHYSAD		0xc0011039
-#define MSR_AMD64_IBSCTL		0xc001103a
-
-/* Fam 10h MSRs */
-#define MSR_FAM10H_MMIO_CONF_BASE	0xc0010058
-#define FAM10H_MMIO_CONF_ENABLE		(1<<0)
-#define FAM10H_MMIO_CONF_BUSRANGE_MASK	0xf
-#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
-#define FAM10H_MMIO_CONF_BASE_MASK	0xfffffff
-#define FAM10H_MMIO_CONF_BASE_SHIFT	20
-
-/* K8 MSRs */
-#define MSR_K8_TOP_MEM1			0xc001001a
-#define MSR_K8_TOP_MEM2			0xc001001d
-#define MSR_K8_SYSCFG			0xc0010010
-#define MSR_K8_HWCR			0xc0010015
-#define MSR_K8_INT_PENDING_MSG		0xc0010055
-/* C1E active bits in int pending message */
-#define K8_INTP_C1E_ACTIVE_MASK		0x18000000
-#define MSR_K8_TSEG_ADDR		0xc0010112
-#define K8_MTRRFIXRANGE_DRAM_ENABLE	0x00040000 /* MtrrFixDramEn bit    */
-#define K8_MTRRFIXRANGE_DRAM_MODIFY	0x00080000 /* MtrrFixDramModEn bit */
-#define K8_MTRR_RDMEM_WRMEM_MASK	0x18181818 /* Mask: RdMem|WrMem    */
-
-/* K7 MSRs */
-#define MSR_K7_EVNTSEL0			0xc0010000
-#define MSR_K7_PERFCTR0			0xc0010004
-#define MSR_K7_EVNTSEL1			0xc0010001
-#define MSR_K7_PERFCTR1			0xc0010005
-#define MSR_K7_EVNTSEL2			0xc0010002
-#define MSR_K7_PERFCTR2			0xc0010006
-#define MSR_K7_EVNTSEL3			0xc0010003
-#define MSR_K7_PERFCTR3			0xc0010007
-#define MSR_K7_CLK_CTL			0xc001001b
-#define MSR_K7_HWCR			0xc0010015
-#define MSR_K7_FID_VID_CTL		0xc0010041
-#define MSR_K7_FID_VID_STATUS		0xc0010042
-
-/* K6 MSRs */
-#define MSR_K6_EFER			0xc0000080
-#define MSR_K6_STAR			0xc0000081
-#define MSR_K6_WHCR			0xc0000082
-#define MSR_K6_UWCCR			0xc0000085
-#define MSR_K6_EPMR			0xc0000086
-#define MSR_K6_PSOR			0xc0000087
-#define MSR_K6_PFIR			0xc0000088
-
-/* Centaur-Hauls/IDT defined MSRs. */
-#define MSR_IDT_FCR1			0x00000107
-#define MSR_IDT_FCR2			0x00000108
-#define MSR_IDT_FCR3			0x00000109
-#define MSR_IDT_FCR4			0x0000010a
-
-#define MSR_IDT_MCR0			0x00000110
-#define MSR_IDT_MCR1			0x00000111
-#define MSR_IDT_MCR2			0x00000112
-#define MSR_IDT_MCR3			0x00000113
-#define MSR_IDT_MCR4			0x00000114
-#define MSR_IDT_MCR5			0x00000115
-#define MSR_IDT_MCR6			0x00000116
-#define MSR_IDT_MCR7			0x00000117
-#define MSR_IDT_MCR_CTRL		0x00000120
-
-/* VIA Cyrix defined MSRs*/
-#define MSR_VIA_FCR			0x00001107
-#define MSR_VIA_LONGHAUL		0x0000110a
-#define MSR_VIA_RNG			0x0000110b
-#define MSR_VIA_BCR2			0x00001147
-
-/* Transmeta defined MSRs */
-#define MSR_TMTA_LONGRUN_CTRL		0x80868010
-#define MSR_TMTA_LONGRUN_FLAGS		0x80868011
-#define MSR_TMTA_LRTI_READOUT		0x80868018
-#define MSR_TMTA_LRTI_VOLT_MHZ		0x8086801a
-
-/* Intel defined MSRs. */
-#define MSR_IA32_P5_MC_ADDR		0x00000000
-#define MSR_IA32_P5_MC_TYPE		0x00000001
-#define MSR_IA32_TSC			0x00000010
-#define MSR_IA32_PLATFORM_ID		0x00000017
-#define MSR_IA32_EBL_CR_POWERON		0x0000002a
-#define MSR_IA32_FEATURE_CONTROL        0x0000003a
-
-#define MSR_IA32_APICBASE		0x0000001b
-#define MSR_IA32_APICBASE_BSP		(1<<8)
-#define MSR_IA32_APICBASE_ENABLE	(1<<11)
-#define MSR_IA32_APICBASE_BASE		(0xfffff<<12)
-
-#define MSR_IA32_UCODE_WRITE		0x00000079
-#define MSR_IA32_UCODE_REV		0x0000008b
-
-#define MSR_IA32_PERF_STATUS		0x00000198
-#define MSR_IA32_PERF_CTL		0x00000199
-
-#define MSR_IA32_MPERF			0x000000e7
-#define MSR_IA32_APERF			0x000000e8
-
-#define MSR_IA32_THERM_CONTROL		0x0000019a
-#define MSR_IA32_THERM_INTERRUPT	0x0000019b
-#define MSR_IA32_THERM_STATUS		0x0000019c
-#define MSR_IA32_MISC_ENABLE		0x000001a0
-
-/* Intel Model 6 */
-#define MSR_P6_EVNTSEL0			0x00000186
-#define MSR_P6_EVNTSEL1			0x00000187
-
-/* P4/Xeon+ specific */
-#define MSR_IA32_MCG_EAX		0x00000180
-#define MSR_IA32_MCG_EBX		0x00000181
-#define MSR_IA32_MCG_ECX		0x00000182
-#define MSR_IA32_MCG_EDX		0x00000183
-#define MSR_IA32_MCG_ESI		0x00000184
-#define MSR_IA32_MCG_EDI		0x00000185
-#define MSR_IA32_MCG_EBP		0x00000186
-#define MSR_IA32_MCG_ESP		0x00000187
-#define MSR_IA32_MCG_EFLAGS		0x00000188
-#define MSR_IA32_MCG_EIP		0x00000189
-#define MSR_IA32_MCG_RESERVED		0x0000018a
-
-/* Pentium IV performance counter MSRs */
-#define MSR_P4_BPU_PERFCTR0		0x00000300
-#define MSR_P4_BPU_PERFCTR1		0x00000301
-#define MSR_P4_BPU_PERFCTR2		0x00000302
-#define MSR_P4_BPU_PERFCTR3		0x00000303
-#define MSR_P4_MS_PERFCTR0		0x00000304
-#define MSR_P4_MS_PERFCTR1		0x00000305
-#define MSR_P4_MS_PERFCTR2		0x00000306
-#define MSR_P4_MS_PERFCTR3		0x00000307
-#define MSR_P4_FLAME_PERFCTR0		0x00000308
-#define MSR_P4_FLAME_PERFCTR1		0x00000309
-#define MSR_P4_FLAME_PERFCTR2		0x0000030a
-#define MSR_P4_FLAME_PERFCTR3		0x0000030b
-#define MSR_P4_IQ_PERFCTR0		0x0000030c
-#define MSR_P4_IQ_PERFCTR1		0x0000030d
-#define MSR_P4_IQ_PERFCTR2		0x0000030e
-#define MSR_P4_IQ_PERFCTR3		0x0000030f
-#define MSR_P4_IQ_PERFCTR4		0x00000310
-#define MSR_P4_IQ_PERFCTR5		0x00000311
-#define MSR_P4_BPU_CCCR0		0x00000360
-#define MSR_P4_BPU_CCCR1		0x00000361
-#define MSR_P4_BPU_CCCR2		0x00000362
-#define MSR_P4_BPU_CCCR3		0x00000363
-#define MSR_P4_MS_CCCR0			0x00000364
-#define MSR_P4_MS_CCCR1			0x00000365
-#define MSR_P4_MS_CCCR2			0x00000366
-#define MSR_P4_MS_CCCR3			0x00000367
-#define MSR_P4_FLAME_CCCR0		0x00000368
-#define MSR_P4_FLAME_CCCR1		0x00000369
-#define MSR_P4_FLAME_CCCR2		0x0000036a
-#define MSR_P4_FLAME_CCCR3		0x0000036b
-#define MSR_P4_IQ_CCCR0			0x0000036c
-#define MSR_P4_IQ_CCCR1			0x0000036d
-#define MSR_P4_IQ_CCCR2			0x0000036e
-#define MSR_P4_IQ_CCCR3			0x0000036f
-#define MSR_P4_IQ_CCCR4			0x00000370
-#define MSR_P4_IQ_CCCR5			0x00000371
-#define MSR_P4_ALF_ESCR0		0x000003ca
-#define MSR_P4_ALF_ESCR1		0x000003cb
-#define MSR_P4_BPU_ESCR0		0x000003b2
-#define MSR_P4_BPU_ESCR1		0x000003b3
-#define MSR_P4_BSU_ESCR0		0x000003a0
-#define MSR_P4_BSU_ESCR1		0x000003a1
-#define MSR_P4_CRU_ESCR0		0x000003b8
-#define MSR_P4_CRU_ESCR1		0x000003b9
-#define MSR_P4_CRU_ESCR2		0x000003cc
-#define MSR_P4_CRU_ESCR3		0x000003cd
-#define MSR_P4_CRU_ESCR4		0x000003e0
-#define MSR_P4_CRU_ESCR5		0x000003e1
-#define MSR_P4_DAC_ESCR0		0x000003a8
-#define MSR_P4_DAC_ESCR1		0x000003a9
-#define MSR_P4_FIRM_ESCR0		0x000003a4
-#define MSR_P4_FIRM_ESCR1		0x000003a5
-#define MSR_P4_FLAME_ESCR0		0x000003a6
-#define MSR_P4_FLAME_ESCR1		0x000003a7
-#define MSR_P4_FSB_ESCR0		0x000003a2
-#define MSR_P4_FSB_ESCR1		0x000003a3
-#define MSR_P4_IQ_ESCR0			0x000003ba
-#define MSR_P4_IQ_ESCR1			0x000003bb
-#define MSR_P4_IS_ESCR0			0x000003b4
-#define MSR_P4_IS_ESCR1			0x000003b5
-#define MSR_P4_ITLB_ESCR0		0x000003b6
-#define MSR_P4_ITLB_ESCR1		0x000003b7
-#define MSR_P4_IX_ESCR0			0x000003c8
-#define MSR_P4_IX_ESCR1			0x000003c9
-#define MSR_P4_MOB_ESCR0		0x000003aa
-#define MSR_P4_MOB_ESCR1		0x000003ab
-#define MSR_P4_MS_ESCR0			0x000003c0
-#define MSR_P4_MS_ESCR1			0x000003c1
-#define MSR_P4_PMH_ESCR0		0x000003ac
-#define MSR_P4_PMH_ESCR1		0x000003ad
-#define MSR_P4_RAT_ESCR0		0x000003bc
-#define MSR_P4_RAT_ESCR1		0x000003bd
-#define MSR_P4_SAAT_ESCR0		0x000003ae
-#define MSR_P4_SAAT_ESCR1		0x000003af
-#define MSR_P4_SSU_ESCR0		0x000003be
-#define MSR_P4_SSU_ESCR1		0x000003bf /* guess: not in manual */
-
-#define MSR_P4_TBPU_ESCR0		0x000003c2
-#define MSR_P4_TBPU_ESCR1		0x000003c3
-#define MSR_P4_TC_ESCR0			0x000003c4
-#define MSR_P4_TC_ESCR1			0x000003c5
-#define MSR_P4_U2L_ESCR0		0x000003b0
-#define MSR_P4_U2L_ESCR1		0x000003b1
-
-/* Intel Core-based CPU performance counters */
-#define MSR_CORE_PERF_FIXED_CTR0	0x00000309
-#define MSR_CORE_PERF_FIXED_CTR1	0x0000030a
-#define MSR_CORE_PERF_FIXED_CTR2	0x0000030b
-#define MSR_CORE_PERF_FIXED_CTR_CTRL	0x0000038d
-#define MSR_CORE_PERF_GLOBAL_STATUS	0x0000038e
-#define MSR_CORE_PERF_GLOBAL_CTRL	0x0000038f
-#define MSR_CORE_PERF_GLOBAL_OVF_CTRL	0x00000390
-
-/* Geode defined MSRs */
-#define MSR_GEODE_BUSCONT_CONF0		0x00001900
-
-/* Intel VT MSRs */
-#define MSR_IA32_VMX_BASIC              0x00000480
-#define MSR_IA32_VMX_PINBASED_CTLS      0x00000481
-#define MSR_IA32_VMX_PROCBASED_CTLS     0x00000482
-#define MSR_IA32_VMX_EXIT_CTLS          0x00000483
-#define MSR_IA32_VMX_ENTRY_CTLS         0x00000484
-#define MSR_IA32_VMX_MISC               0x00000485
-#define MSR_IA32_VMX_CR0_FIXED0         0x00000486
-#define MSR_IA32_VMX_CR0_FIXED1         0x00000487
-#define MSR_IA32_VMX_CR4_FIXED0         0x00000488
-#define MSR_IA32_VMX_CR4_FIXED1         0x00000489
-#define MSR_IA32_VMX_VMCS_ENUM          0x0000048a
-#define MSR_IA32_VMX_PROCBASED_CTLS2    0x0000048b
-#define MSR_IA32_VMX_EPT_VPID_CAP       0x0000048c
-
-#endif /* ASM_X86__MSR_INDEX_H */
diff --git a/include/asm-x86/msr.h b/include/asm-x86/msr.h
deleted file mode 100644
index 530af1f6389e..000000000000
--- a/include/asm-x86/msr.h
+++ /dev/null
@@ -1,247 +0,0 @@
-#ifndef ASM_X86__MSR_H
-#define ASM_X86__MSR_H
-
-#include <asm/msr-index.h>
-
-#ifndef __ASSEMBLY__
-# include <linux/types.h>
-#endif
-
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-
-#include <asm/asm.h>
-#include <asm/errno.h>
-
-static inline unsigned long long native_read_tscp(unsigned int *aux)
-{
-	unsigned long low, high;
-	asm volatile(".byte 0x0f,0x01,0xf9"
-		     : "=a" (low), "=d" (high), "=c" (*aux));
-	return low | ((u64)high << 32);
-}
-
-/*
- * i386 calling convention returns 64-bit value in edx:eax, while
- * x86_64 returns at rax. Also, the "A" constraint does not really
- * mean rdx:rax in x86_64, so we need specialized behaviour for each
- * architecture
- */
-#ifdef CONFIG_X86_64
-#define DECLARE_ARGS(val, low, high)	unsigned low, high
-#define EAX_EDX_VAL(val, low, high)	((low) | ((u64)(high) << 32))
-#define EAX_EDX_ARGS(val, low, high)	"a" (low), "d" (high)
-#define EAX_EDX_RET(val, low, high)	"=a" (low), "=d" (high)
-#else
-#define DECLARE_ARGS(val, low, high)	unsigned long long val
-#define EAX_EDX_VAL(val, low, high)	(val)
-#define EAX_EDX_ARGS(val, low, high)	"A" (val)
-#define EAX_EDX_RET(val, low, high)	"=A" (val)
-#endif
-
-static inline unsigned long long native_read_msr(unsigned int msr)
-{
-	DECLARE_ARGS(val, low, high);
-
-	asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr));
-	return EAX_EDX_VAL(val, low, high);
-}
-
-static inline unsigned long long native_read_msr_safe(unsigned int msr,
-						      int *err)
-{
-	DECLARE_ARGS(val, low, high);
-
-	asm volatile("2: rdmsr ; xor %[err],%[err]\n"
-		     "1:\n\t"
-		     ".section .fixup,\"ax\"\n\t"
-		     "3:  mov %[fault],%[err] ; jmp 1b\n\t"
-		     ".previous\n\t"
-		     _ASM_EXTABLE(2b, 3b)
-		     : [err] "=r" (*err), EAX_EDX_RET(val, low, high)
-		     : "c" (msr), [fault] "i" (-EFAULT));
-	return EAX_EDX_VAL(val, low, high);
-}
-
-static inline unsigned long long native_read_msr_amd_safe(unsigned int msr,
-						      int *err)
-{
-	DECLARE_ARGS(val, low, high);
-
-	asm volatile("2: rdmsr ; xor %0,%0\n"
-		     "1:\n\t"
-		     ".section .fixup,\"ax\"\n\t"
-		     "3:  mov %3,%0 ; jmp 1b\n\t"
-		     ".previous\n\t"
-		     _ASM_EXTABLE(2b, 3b)
-		     : "=r" (*err), EAX_EDX_RET(val, low, high)
-		     : "c" (msr), "D" (0x9c5a203a), "i" (-EFAULT));
-	return EAX_EDX_VAL(val, low, high);
-}
-
-static inline void native_write_msr(unsigned int msr,
-				    unsigned low, unsigned high)
-{
-	asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory");
-}
-
-static inline int native_write_msr_safe(unsigned int msr,
-					unsigned low, unsigned high)
-{
-	int err;
-	asm volatile("2: wrmsr ; xor %[err],%[err]\n"
-		     "1:\n\t"
-		     ".section .fixup,\"ax\"\n\t"
-		     "3:  mov %[fault],%[err] ; jmp 1b\n\t"
-		     ".previous\n\t"
-		     _ASM_EXTABLE(2b, 3b)
-		     : [err] "=a" (err)
-		     : "c" (msr), "0" (low), "d" (high),
-		       [fault] "i" (-EFAULT)
-		     : "memory");
-	return err;
-}
-
-extern unsigned long long native_read_tsc(void);
-
-static __always_inline unsigned long long __native_read_tsc(void)
-{
-	DECLARE_ARGS(val, low, high);
-
-	rdtsc_barrier();
-	asm volatile("rdtsc" : EAX_EDX_RET(val, low, high));
-	rdtsc_barrier();
-
-	return EAX_EDX_VAL(val, low, high);
-}
-
-static inline unsigned long long native_read_pmc(int counter)
-{
-	DECLARE_ARGS(val, low, high);
-
-	asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
-	return EAX_EDX_VAL(val, low, high);
-}
-
-#ifdef CONFIG_PARAVIRT
-#include <asm/paravirt.h>
-#else
-#include <linux/errno.h>
-/*
- * Access to machine-specific registers (available on 586 and better only)
- * Note: the rd* operations modify the parameters directly (without using
- * pointer indirection), this allows gcc to optimize better
- */
-
-#define rdmsr(msr, val1, val2)					\
-do {								\
-	u64 __val = native_read_msr((msr));			\
-	(val1) = (u32)__val;					\
-	(val2) = (u32)(__val >> 32);				\
-} while (0)
-
-static inline void wrmsr(unsigned msr, unsigned low, unsigned high)
-{
-	native_write_msr(msr, low, high);
-}
-
-#define rdmsrl(msr, val)			\
-	((val) = native_read_msr((msr)))
-
-#define wrmsrl(msr, val)						\
-	native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32))
-
-/* wrmsr with exception handling */
-static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high)
-{
-	return native_write_msr_safe(msr, low, high);
-}
-
-/* rdmsr with exception handling */
-#define rdmsr_safe(msr, p1, p2)					\
-({								\
-	int __err;						\
-	u64 __val = native_read_msr_safe((msr), &__err);	\
-	(*p1) = (u32)__val;					\
-	(*p2) = (u32)(__val >> 32);				\
-	__err;							\
-})
-
-static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
-{
-	int err;
-
-	*p = native_read_msr_safe(msr, &err);
-	return err;
-}
-static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
-{
-	int err;
-
-	*p = native_read_msr_amd_safe(msr, &err);
-	return err;
-}
-
-#define rdtscl(low)						\
-	((low) = (u32)native_read_tsc())
-
-#define rdtscll(val)						\
-	((val) = native_read_tsc())
-
-#define rdpmc(counter, low, high)			\
-do {							\
-	u64 _l = native_read_pmc((counter));		\
-	(low)  = (u32)_l;				\
-	(high) = (u32)(_l >> 32);			\
-} while (0)
-
-#define rdtscp(low, high, aux)					\
-do {                                                            \
-	unsigned long long _val = native_read_tscp(&(aux));     \
-	(low) = (u32)_val;                                      \
-	(high) = (u32)(_val >> 32);                             \
-} while (0)
-
-#define rdtscpll(val, aux) (val) = native_read_tscp(&(aux))
-
-#endif	/* !CONFIG_PARAVIRT */
-
-
-#define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val),		\
-					     (u32)((val) >> 32))
-
-#define write_tsc(val1, val2) wrmsr(0x10, (val1), (val2))
-
-#define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0)
-
-#ifdef CONFIG_SMP
-int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
-int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
-int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
-int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
-#else  /*  CONFIG_SMP  */
-static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
-{
-	rdmsr(msr_no, *l, *h);
-	return 0;
-}
-static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
-{
-	wrmsr(msr_no, l, h);
-	return 0;
-}
-static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
-				    u32 *l, u32 *h)
-{
-	return rdmsr_safe(msr_no, l, h);
-}
-static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
-{
-	return wrmsr_safe(msr_no, l, h);
-}
-#endif  /* CONFIG_SMP */
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL__ */
-
-
-#endif /* ASM_X86__MSR_H */
diff --git a/include/asm-x86/mtrr.h b/include/asm-x86/mtrr.h
deleted file mode 100644
index 23a7f83da953..000000000000
--- a/include/asm-x86/mtrr.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*  Generic MTRR (Memory Type Range Register) ioctls.
-
-    Copyright (C) 1997-1999  Richard Gooch
-
-    This library is free software; you can redistribute it and/or
-    modify it under the terms of the GNU Library General Public
-    License as published by the Free Software Foundation; either
-    version 2 of the License, or (at your option) any later version.
-
-    This library is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-    Library General Public License for more details.
-
-    You should have received a copy of the GNU Library General Public
-    License along with this library; if not, write to the Free
-    Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-    Richard Gooch may be reached by email at  rgooch@atnf.csiro.au
-    The postal address is:
-      Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
-*/
-#ifndef ASM_X86__MTRR_H
-#define ASM_X86__MTRR_H
-
-#include <linux/ioctl.h>
-#include <linux/errno.h>
-
-#define	MTRR_IOCTL_BASE	'M'
-
-struct mtrr_sentry {
-    unsigned long base;    /*  Base address     */
-    unsigned int size;    /*  Size of region   */
-    unsigned int type;     /*  Type of region   */
-};
-
-/* Warning: this structure has a different order from i386
-   on x86-64. The 32bit emulation code takes care of that.
-   But you need to use this for 64bit, otherwise your X server
-   will break. */
-
-#ifdef __i386__
-struct mtrr_gentry {
-    unsigned int regnum;   /*  Register number  */
-    unsigned long base;    /*  Base address     */
-    unsigned int size;    /*  Size of region   */
-    unsigned int type;     /*  Type of region   */
-};
-
-#else /* __i386__ */
-
-struct mtrr_gentry {
-    unsigned long base;    /*  Base address     */
-    unsigned int size;    /*  Size of region   */
-    unsigned int regnum;   /*  Register number  */
-    unsigned int type;     /*  Type of region   */
-};
-#endif /* !__i386__ */
-
-/*  These are the various ioctls  */
-#define MTRRIOC_ADD_ENTRY        _IOW(MTRR_IOCTL_BASE,  0, struct mtrr_sentry)
-#define MTRRIOC_SET_ENTRY        _IOW(MTRR_IOCTL_BASE,  1, struct mtrr_sentry)
-#define MTRRIOC_DEL_ENTRY        _IOW(MTRR_IOCTL_BASE,  2, struct mtrr_sentry)
-#define MTRRIOC_GET_ENTRY        _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry)
-#define MTRRIOC_KILL_ENTRY       _IOW(MTRR_IOCTL_BASE,  4, struct mtrr_sentry)
-#define MTRRIOC_ADD_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  5, struct mtrr_sentry)
-#define MTRRIOC_SET_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  6, struct mtrr_sentry)
-#define MTRRIOC_DEL_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  7, struct mtrr_sentry)
-#define MTRRIOC_GET_PAGE_ENTRY   _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry)
-#define MTRRIOC_KILL_PAGE_ENTRY  _IOW(MTRR_IOCTL_BASE,  9, struct mtrr_sentry)
-
-/*  These are the region types  */
-#define MTRR_TYPE_UNCACHABLE 0
-#define MTRR_TYPE_WRCOMB     1
-/*#define MTRR_TYPE_         2*/
-/*#define MTRR_TYPE_         3*/
-#define MTRR_TYPE_WRTHROUGH  4
-#define MTRR_TYPE_WRPROT     5
-#define MTRR_TYPE_WRBACK     6
-#define MTRR_NUM_TYPES       7
-
-#ifdef __KERNEL__
-
-/*  The following functions are for use by other drivers  */
-# ifdef CONFIG_MTRR
-extern u8 mtrr_type_lookup(u64 addr, u64 end);
-extern void mtrr_save_fixed_ranges(void *);
-extern void mtrr_save_state(void);
-extern int mtrr_add(unsigned long base, unsigned long size,
-		    unsigned int type, bool increment);
-extern int mtrr_add_page(unsigned long base, unsigned long size,
-			 unsigned int type, bool increment);
-extern int mtrr_del(int reg, unsigned long base, unsigned long size);
-extern int mtrr_del_page(int reg, unsigned long base, unsigned long size);
-extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi);
-extern void mtrr_ap_init(void);
-extern void mtrr_bp_init(void);
-extern int mtrr_trim_uncached_memory(unsigned long end_pfn);
-extern int amd_special_default_mtrr(void);
-#  else
-static inline u8 mtrr_type_lookup(u64 addr, u64 end)
-{
-	/*
-	 * Return no-MTRRs:
-	 */
-	return 0xff;
-}
-#define mtrr_save_fixed_ranges(arg) do {} while (0)
-#define mtrr_save_state() do {} while (0)
-static inline int mtrr_add(unsigned long base, unsigned long size,
-			   unsigned int type, bool increment)
-{
-    return -ENODEV;
-}
-static inline int mtrr_add_page(unsigned long base, unsigned long size,
-				unsigned int type, bool increment)
-{
-    return -ENODEV;
-}
-static inline int mtrr_del(int reg, unsigned long base, unsigned long size)
-{
-    return -ENODEV;
-}
-static inline int mtrr_del_page(int reg, unsigned long base, unsigned long size)
-{
-    return -ENODEV;
-}
-static inline int mtrr_trim_uncached_memory(unsigned long end_pfn)
-{
-	return 0;
-}
-static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)
-{
-}
-
-#define mtrr_ap_init() do {} while (0)
-#define mtrr_bp_init() do {} while (0)
-#  endif
-
-#ifdef CONFIG_COMPAT
-#include <linux/compat.h>
-
-struct mtrr_sentry32 {
-    compat_ulong_t base;    /*  Base address     */
-    compat_uint_t size;    /*  Size of region   */
-    compat_uint_t type;     /*  Type of region   */
-};
-
-struct mtrr_gentry32 {
-    compat_ulong_t regnum;   /*  Register number  */
-    compat_uint_t base;    /*  Base address     */
-    compat_uint_t size;    /*  Size of region   */
-    compat_uint_t type;     /*  Type of region   */
-};
-
-#define MTRR_IOCTL_BASE 'M'
-
-#define MTRRIOC32_ADD_ENTRY      _IOW(MTRR_IOCTL_BASE,  0, struct mtrr_sentry32)
-#define MTRRIOC32_SET_ENTRY      _IOW(MTRR_IOCTL_BASE,  1, struct mtrr_sentry32)
-#define MTRRIOC32_DEL_ENTRY      _IOW(MTRR_IOCTL_BASE,  2, struct mtrr_sentry32)
-#define MTRRIOC32_GET_ENTRY      _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry32)
-#define MTRRIOC32_KILL_ENTRY     _IOW(MTRR_IOCTL_BASE,  4, struct mtrr_sentry32)
-#define MTRRIOC32_ADD_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE,  5, struct mtrr_sentry32)
-#define MTRRIOC32_SET_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE,  6, struct mtrr_sentry32)
-#define MTRRIOC32_DEL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE,  7, struct mtrr_sentry32)
-#define MTRRIOC32_GET_PAGE_ENTRY _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry32)
-#define MTRRIOC32_KILL_PAGE_ENTRY		\
-				 _IOW(MTRR_IOCTL_BASE,  9, struct mtrr_sentry32)
-#endif /* CONFIG_COMPAT */
-
-#endif /* __KERNEL__ */
-
-#endif /* ASM_X86__MTRR_H */
diff --git a/include/asm-x86/mutex.h b/include/asm-x86/mutex.h
deleted file mode 100644
index a731b9c573a6..000000000000
--- a/include/asm-x86/mutex.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifdef CONFIG_X86_32
-# include "mutex_32.h"
-#else
-# include "mutex_64.h"
-#endif
diff --git a/include/asm-x86/mutex_32.h b/include/asm-x86/mutex_32.h
deleted file mode 100644
index 25c16d8ba3c7..000000000000
--- a/include/asm-x86/mutex_32.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Assembly implementation of the mutex fastpath, based on atomic
- * decrement/increment.
- *
- * started by Ingo Molnar:
- *
- *  Copyright (C) 2004, 2005, 2006 Red Hat, Inc., Ingo Molnar <mingo@redhat.com>
- */
-#ifndef ASM_X86__MUTEX_32_H
-#define ASM_X86__MUTEX_32_H
-
-#include <asm/alternative.h>
-
-/**
- *  __mutex_fastpath_lock - try to take the lock by moving the count
- *                          from 1 to a 0 value
- *  @count: pointer of type atomic_t
- *  @fn: function to call if the original value was not 1
- *
- * Change the count from 1 to a value lower than 1, and call <fn> if it
- * wasn't 1 originally. This function MUST leave the value lower than 1
- * even when the "1" assertion wasn't true.
- */
-#define __mutex_fastpath_lock(count, fail_fn)			\
-do {								\
-	unsigned int dummy;					\
-								\
-	typecheck(atomic_t *, count);				\
-	typecheck_fn(void (*)(atomic_t *), fail_fn);		\
-								\
-	asm volatile(LOCK_PREFIX "   decl (%%eax)\n"		\
-		     "   jns 1f	\n"				\
-		     "   call " #fail_fn "\n"			\
-		     "1:\n"					\
-		     : "=a" (dummy)				\
-		     : "a" (count)				\
-		     : "memory", "ecx", "edx");			\
-} while (0)
-
-
-/**
- *  __mutex_fastpath_lock_retval - try to take the lock by moving the count
- *                                 from 1 to a 0 value
- *  @count: pointer of type atomic_t
- *  @fail_fn: function to call if the original value was not 1
- *
- * Change the count from 1 to a value lower than 1, and call <fail_fn> if it
- * wasn't 1 originally. This function returns 0 if the fastpath succeeds,
- * or anything the slow path function returns
- */
-static inline int __mutex_fastpath_lock_retval(atomic_t *count,
-					       int (*fail_fn)(atomic_t *))
-{
-	if (unlikely(atomic_dec_return(count) < 0))
-		return fail_fn(count);
-	else
-		return 0;
-}
-
-/**
- *  __mutex_fastpath_unlock - try to promote the mutex from 0 to 1
- *  @count: pointer of type atomic_t
- *  @fail_fn: function to call if the original value was not 0
- *
- * try to promote the mutex from 0 to 1. if it wasn't 0, call <fail_fn>.
- * In the failure case, this function is allowed to either set the value
- * to 1, or to set it to a value lower than 1.
- *
- * If the implementation sets it to a value of lower than 1, the
- * __mutex_slowpath_needs_to_unlock() macro needs to return 1, it needs
- * to return 0 otherwise.
- */
-#define __mutex_fastpath_unlock(count, fail_fn)			\
-do {								\
-	unsigned int dummy;					\
-								\
-	typecheck(atomic_t *, count);				\
-	typecheck_fn(void (*)(atomic_t *), fail_fn);		\
-								\
-	asm volatile(LOCK_PREFIX "   incl (%%eax)\n"		\
-		     "   jg	1f\n"				\
-		     "   call " #fail_fn "\n"			\
-		     "1:\n"					\
-		     : "=a" (dummy)				\
-		     : "a" (count)				\
-		     : "memory", "ecx", "edx");			\
-} while (0)
-
-#define __mutex_slowpath_needs_to_unlock()	1
-
-/**
- * __mutex_fastpath_trylock - try to acquire the mutex, without waiting
- *
- *  @count: pointer of type atomic_t
- *  @fail_fn: fallback function
- *
- * Change the count from 1 to a value lower than 1, and return 0 (failure)
- * if it wasn't 1 originally, or return 1 (success) otherwise. This function
- * MUST leave the value lower than 1 even when the "1" assertion wasn't true.
- * Additionally, if the value was < 0 originally, this function must not leave
- * it to 0 on failure.
- */
-static inline int __mutex_fastpath_trylock(atomic_t *count,
-					   int (*fail_fn)(atomic_t *))
-{
-	/*
-	 * We have two variants here. The cmpxchg based one is the best one
-	 * because it never induce a false contention state.  It is included
-	 * here because architectures using the inc/dec algorithms over the
-	 * xchg ones are much more likely to support cmpxchg natively.
-	 *
-	 * If not we fall back to the spinlock based variant - that is
-	 * just as efficient (and simpler) as a 'destructive' probing of
-	 * the mutex state would be.
-	 */
-#ifdef __HAVE_ARCH_CMPXCHG
-	if (likely(atomic_cmpxchg(count, 1, 0) == 1))
-		return 1;
-	return 0;
-#else
-	return fail_fn(count);
-#endif
-}
-
-#endif /* ASM_X86__MUTEX_32_H */
diff --git a/include/asm-x86/mutex_64.h b/include/asm-x86/mutex_64.h
deleted file mode 100644
index 918ba21ab9d9..000000000000
--- a/include/asm-x86/mutex_64.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Assembly implementation of the mutex fastpath, based on atomic
- * decrement/increment.
- *
- * started by Ingo Molnar:
- *
- *  Copyright (C) 2004, 2005, 2006 Red Hat, Inc., Ingo Molnar <mingo@redhat.com>
- */
-#ifndef ASM_X86__MUTEX_64_H
-#define ASM_X86__MUTEX_64_H
-
-/**
- * __mutex_fastpath_lock - decrement and call function if negative
- * @v: pointer of type atomic_t
- * @fail_fn: function to call if the result is negative
- *
- * Atomically decrements @v and calls <fail_fn> if the result is negative.
- */
-#define __mutex_fastpath_lock(v, fail_fn)			\
-do {								\
-	unsigned long dummy;					\
-								\
-	typecheck(atomic_t *, v);				\
-	typecheck_fn(void (*)(atomic_t *), fail_fn);		\
-								\
-	asm volatile(LOCK_PREFIX "   decl (%%rdi)\n"		\
-		     "   jns 1f		\n"			\
-		     "   call " #fail_fn "\n"			\
-		     "1:"					\
-		     : "=D" (dummy)				\
-		     : "D" (v)					\
-		     : "rax", "rsi", "rdx", "rcx",		\
-		       "r8", "r9", "r10", "r11", "memory");	\
-} while (0)
-
-/**
- *  __mutex_fastpath_lock_retval - try to take the lock by moving the count
- *                                 from 1 to a 0 value
- *  @count: pointer of type atomic_t
- *  @fail_fn: function to call if the original value was not 1
- *
- * Change the count from 1 to a value lower than 1, and call <fail_fn> if
- * it wasn't 1 originally. This function returns 0 if the fastpath succeeds,
- * or anything the slow path function returns
- */
-static inline int __mutex_fastpath_lock_retval(atomic_t *count,
-					       int (*fail_fn)(atomic_t *))
-{
-	if (unlikely(atomic_dec_return(count) < 0))
-		return fail_fn(count);
-	else
-		return 0;
-}
-
-/**
- * __mutex_fastpath_unlock - increment and call function if nonpositive
- * @v: pointer of type atomic_t
- * @fail_fn: function to call if the result is nonpositive
- *
- * Atomically increments @v and calls <fail_fn> if the result is nonpositive.
- */
-#define __mutex_fastpath_unlock(v, fail_fn)			\
-do {								\
-	unsigned long dummy;					\
-								\
-	typecheck(atomic_t *, v);				\
-	typecheck_fn(void (*)(atomic_t *), fail_fn);		\
-								\
-	asm volatile(LOCK_PREFIX "   incl (%%rdi)\n"		\
-		     "   jg 1f\n"				\
-		     "   call " #fail_fn "\n"			\
-		     "1:"					\
-		     : "=D" (dummy)				\
-		     : "D" (v)					\
-		     : "rax", "rsi", "rdx", "rcx",		\
-		       "r8", "r9", "r10", "r11", "memory");	\
-} while (0)
-
-#define __mutex_slowpath_needs_to_unlock()	1
-
-/**
- * __mutex_fastpath_trylock - try to acquire the mutex, without waiting
- *
- *  @count: pointer of type atomic_t
- *  @fail_fn: fallback function
- *
- * Change the count from 1 to 0 and return 1 (success), or return 0 (failure)
- * if it wasn't 1 originally. [the fallback function is never used on
- * x86_64, because all x86_64 CPUs have a CMPXCHG instruction.]
- */
-static inline int __mutex_fastpath_trylock(atomic_t *count,
-					   int (*fail_fn)(atomic_t *))
-{
-	if (likely(atomic_cmpxchg(count, 1, 0) == 1))
-		return 1;
-	else
-		return 0;
-}
-
-#endif /* ASM_X86__MUTEX_64_H */
diff --git a/include/asm-x86/nmi.h b/include/asm-x86/nmi.h
deleted file mode 100644
index a53f829a97c5..000000000000
--- a/include/asm-x86/nmi.h
+++ /dev/null
@@ -1,81 +0,0 @@
-#ifndef ASM_X86__NMI_H
-#define ASM_X86__NMI_H
-
-#include <linux/pm.h>
-#include <asm/irq.h>
-#include <asm/io.h>
-
-#ifdef ARCH_HAS_NMI_WATCHDOG
-
-/**
- * do_nmi_callback
- *
- * Check to see if a callback exists and execute it.  Return 1
- * if the handler exists and was handled successfully.
- */
-int do_nmi_callback(struct pt_regs *regs, int cpu);
-
-extern void die_nmi(char *str, struct pt_regs *regs, int do_panic);
-extern int check_nmi_watchdog(void);
-extern int nmi_watchdog_enabled;
-extern int avail_to_resrv_perfctr_nmi_bit(unsigned int);
-extern int avail_to_resrv_perfctr_nmi(unsigned int);
-extern int reserve_perfctr_nmi(unsigned int);
-extern void release_perfctr_nmi(unsigned int);
-extern int reserve_evntsel_nmi(unsigned int);
-extern void release_evntsel_nmi(unsigned int);
-
-extern void setup_apic_nmi_watchdog(void *);
-extern void stop_apic_nmi_watchdog(void *);
-extern void disable_timer_nmi_watchdog(void);
-extern void enable_timer_nmi_watchdog(void);
-extern int nmi_watchdog_tick(struct pt_regs *regs, unsigned reason);
-extern void cpu_nmi_set_wd_enabled(void);
-
-extern atomic_t nmi_active;
-extern unsigned int nmi_watchdog;
-#define NMI_NONE	0
-#define NMI_IO_APIC	1
-#define NMI_LOCAL_APIC	2
-#define NMI_INVALID	3
-
-struct ctl_table;
-struct file;
-extern int proc_nmi_enabled(struct ctl_table *, int , struct file *,
-			void __user *, size_t *, loff_t *);
-extern int unknown_nmi_panic;
-
-void __trigger_all_cpu_backtrace(void);
-#define trigger_all_cpu_backtrace() __trigger_all_cpu_backtrace()
-
-static inline void localise_nmi_watchdog(void)
-{
-	if (nmi_watchdog == NMI_IO_APIC)
-		nmi_watchdog = NMI_LOCAL_APIC;
-}
-
-/* check if nmi_watchdog is active (ie was specified at boot) */
-static inline int nmi_watchdog_active(void)
-{
-	/*
-	 * actually it should be:
-	 * 	return (nmi_watchdog == NMI_LOCAL_APIC ||
-	 * 		nmi_watchdog == NMI_IO_APIC)
-	 * but since they are power of two we could use a
-	 * cheaper way --cvg
-	 */
-	return nmi_watchdog & 0x3;
-}
-#endif
-
-void lapic_watchdog_stop(void);
-int lapic_watchdog_init(unsigned nmi_hz);
-int lapic_wd_event(unsigned nmi_hz);
-unsigned lapic_adjust_nmi_hz(unsigned hz);
-int lapic_watchdog_ok(void);
-void disable_lapic_nmi_watchdog(void);
-void enable_lapic_nmi_watchdog(void);
-void stop_nmi(void);
-void restart_nmi(void);
-
-#endif /* ASM_X86__NMI_H */
diff --git a/include/asm-x86/nops.h b/include/asm-x86/nops.h
deleted file mode 100644
index ae742721ae73..000000000000
--- a/include/asm-x86/nops.h
+++ /dev/null
@@ -1,118 +0,0 @@
-#ifndef ASM_X86__NOPS_H
-#define ASM_X86__NOPS_H
-
-/* Define nops for use with alternative() */
-
-/* generic versions from gas
-   1: nop
-   the following instructions are NOT nops in 64-bit mode,
-   for 64-bit mode use K8 or P6 nops instead
-   2: movl %esi,%esi
-   3: leal 0x00(%esi),%esi
-   4: leal 0x00(,%esi,1),%esi
-   6: leal 0x00000000(%esi),%esi
-   7: leal 0x00000000(,%esi,1),%esi
-*/
-#define GENERIC_NOP1 ".byte 0x90\n"
-#define GENERIC_NOP2 ".byte 0x89,0xf6\n"
-#define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
-#define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
-#define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
-#define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
-#define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
-#define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
-
-/* Opteron 64bit nops
-   1: nop
-   2: osp nop
-   3: osp osp nop
-   4: osp osp osp nop
-*/
-#define K8_NOP1 GENERIC_NOP1
-#define K8_NOP2	".byte 0x66,0x90\n"
-#define K8_NOP3	".byte 0x66,0x66,0x90\n"
-#define K8_NOP4	".byte 0x66,0x66,0x66,0x90\n"
-#define K8_NOP5	K8_NOP3 K8_NOP2
-#define K8_NOP6	K8_NOP3 K8_NOP3
-#define K8_NOP7	K8_NOP4 K8_NOP3
-#define K8_NOP8	K8_NOP4 K8_NOP4
-
-/* K7 nops
-   uses eax dependencies (arbitary choice)
-   1: nop
-   2: movl %eax,%eax
-   3: leal (,%eax,1),%eax
-   4: leal 0x00(,%eax,1),%eax
-   6: leal 0x00000000(%eax),%eax
-   7: leal 0x00000000(,%eax,1),%eax
-*/
-#define K7_NOP1	GENERIC_NOP1
-#define K7_NOP2	".byte 0x8b,0xc0\n"
-#define K7_NOP3	".byte 0x8d,0x04,0x20\n"
-#define K7_NOP4	".byte 0x8d,0x44,0x20,0x00\n"
-#define K7_NOP5	K7_NOP4 ASM_NOP1
-#define K7_NOP6	".byte 0x8d,0x80,0,0,0,0\n"
-#define K7_NOP7	".byte 0x8D,0x04,0x05,0,0,0,0\n"
-#define K7_NOP8	K7_NOP7 ASM_NOP1
-
-/* P6 nops
-   uses eax dependencies (Intel-recommended choice)
-   1: nop
-   2: osp nop
-   3: nopl (%eax)
-   4: nopl 0x00(%eax)
-   5: nopl 0x00(%eax,%eax,1)
-   6: osp nopl 0x00(%eax,%eax,1)
-   7: nopl 0x00000000(%eax)
-   8: nopl 0x00000000(%eax,%eax,1)
-*/
-#define P6_NOP1	GENERIC_NOP1
-#define P6_NOP2	".byte 0x66,0x90\n"
-#define P6_NOP3	".byte 0x0f,0x1f,0x00\n"
-#define P6_NOP4	".byte 0x0f,0x1f,0x40,0\n"
-#define P6_NOP5	".byte 0x0f,0x1f,0x44,0x00,0\n"
-#define P6_NOP6	".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
-#define P6_NOP7	".byte 0x0f,0x1f,0x80,0,0,0,0\n"
-#define P6_NOP8	".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
-
-#if defined(CONFIG_MK7)
-#define ASM_NOP1 K7_NOP1
-#define ASM_NOP2 K7_NOP2
-#define ASM_NOP3 K7_NOP3
-#define ASM_NOP4 K7_NOP4
-#define ASM_NOP5 K7_NOP5
-#define ASM_NOP6 K7_NOP6
-#define ASM_NOP7 K7_NOP7
-#define ASM_NOP8 K7_NOP8
-#elif defined(CONFIG_X86_P6_NOP)
-#define ASM_NOP1 P6_NOP1
-#define ASM_NOP2 P6_NOP2
-#define ASM_NOP3 P6_NOP3
-#define ASM_NOP4 P6_NOP4
-#define ASM_NOP5 P6_NOP5
-#define ASM_NOP6 P6_NOP6
-#define ASM_NOP7 P6_NOP7
-#define ASM_NOP8 P6_NOP8
-#elif defined(CONFIG_X86_64)
-#define ASM_NOP1 K8_NOP1
-#define ASM_NOP2 K8_NOP2
-#define ASM_NOP3 K8_NOP3
-#define ASM_NOP4 K8_NOP4
-#define ASM_NOP5 K8_NOP5
-#define ASM_NOP6 K8_NOP6
-#define ASM_NOP7 K8_NOP7
-#define ASM_NOP8 K8_NOP8
-#else
-#define ASM_NOP1 GENERIC_NOP1
-#define ASM_NOP2 GENERIC_NOP2
-#define ASM_NOP3 GENERIC_NOP3
-#define ASM_NOP4 GENERIC_NOP4
-#define ASM_NOP5 GENERIC_NOP5
-#define ASM_NOP6 GENERIC_NOP6
-#define ASM_NOP7 GENERIC_NOP7
-#define ASM_NOP8 GENERIC_NOP8
-#endif
-
-#define ASM_NOP_MAX 8
-
-#endif /* ASM_X86__NOPS_H */
diff --git a/include/asm-x86/numa.h b/include/asm-x86/numa.h
deleted file mode 100644
index 27da400d3138..000000000000
--- a/include/asm-x86/numa.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifdef CONFIG_X86_32
-# include "numa_32.h"
-#else
-# include "numa_64.h"
-#endif
diff --git a/include/asm-x86/numa_32.h b/include/asm-x86/numa_32.h
deleted file mode 100644
index 44cb07855c5b..000000000000
--- a/include/asm-x86/numa_32.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef ASM_X86__NUMA_32_H
-#define ASM_X86__NUMA_32_H
-
-extern int pxm_to_nid(int pxm);
-extern void numa_remove_cpu(int cpu);
-
-#ifdef CONFIG_NUMA
-extern void set_highmem_pages_init(void);
-#endif
-
-#endif /* ASM_X86__NUMA_32_H */
diff --git a/include/asm-x86/numa_64.h b/include/asm-x86/numa_64.h
deleted file mode 100644
index 15c990395b02..000000000000
--- a/include/asm-x86/numa_64.h
+++ /dev/null
@@ -1,43 +0,0 @@
-#ifndef ASM_X86__NUMA_64_H
-#define ASM_X86__NUMA_64_H
-
-#include <linux/nodemask.h>
-#include <asm/apicdef.h>
-
-struct bootnode {
-	u64 start;
-	u64 end;
-};
-
-extern int compute_hash_shift(struct bootnode *nodes, int numblks,
-			      int *nodeids);
-
-#define ZONE_ALIGN (1UL << (MAX_ORDER+PAGE_SHIFT))
-
-extern void numa_init_array(void);
-extern int numa_off;
-
-extern void srat_reserve_add_area(int nodeid);
-extern int hotadd_percent;
-
-extern s16 apicid_to_node[MAX_LOCAL_APIC];
-
-extern unsigned long numa_free_all_bootmem(void);
-extern void setup_node_bootmem(int nodeid, unsigned long start,
-			       unsigned long end);
-
-#ifdef CONFIG_NUMA
-extern void __init init_cpu_to_node(void);
-extern void __cpuinit numa_set_node(int cpu, int node);
-extern void __cpuinit numa_clear_node(int cpu);
-extern void __cpuinit numa_add_cpu(int cpu);
-extern void __cpuinit numa_remove_cpu(int cpu);
-#else
-static inline void init_cpu_to_node(void)		{ }
-static inline void numa_set_node(int cpu, int node)	{ }
-static inline void numa_clear_node(int cpu)		{ }
-static inline void numa_add_cpu(int cpu, int node)	{ }
-static inline void numa_remove_cpu(int cpu)		{ }
-#endif
-
-#endif /* ASM_X86__NUMA_64_H */
diff --git a/include/asm-x86/numaq.h b/include/asm-x86/numaq.h
deleted file mode 100644
index 124bf7d4b70a..000000000000
--- a/include/asm-x86/numaq.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Written by: Patricia Gaughen, IBM Corporation
- *
- * Copyright (C) 2002, IBM Corp.
- *
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Send feedback to <gone@us.ibm.com>
- */
-
-#ifndef ASM_X86__NUMAQ_H
-#define ASM_X86__NUMAQ_H
-
-#ifdef CONFIG_X86_NUMAQ
-
-extern int found_numaq;
-extern int get_memcfg_numaq(void);
-
-/*
- * SYS_CFG_DATA_PRIV_ADDR, struct eachquadmem, and struct sys_cfg_data are the
- */
-#define SYS_CFG_DATA_PRIV_ADDR		0x0009d000 /* place for scd in private
-						      quad space */
-
-/*
- * Communication area for each processor on lynxer-processor tests.
- *
- * NOTE: If you change the size of this eachproc structure you need
- *       to change the definition for EACH_QUAD_SIZE.
- */
-struct eachquadmem {
-	unsigned int	priv_mem_start;		/* Starting address of this */
-						/* quad's private memory. */
-						/* This is always 0. */
-						/* In MB. */
-	unsigned int	priv_mem_size;		/* Size of this quad's */
-						/* private memory. */
-						/* In MB. */
-	unsigned int	low_shrd_mem_strp_start;/* Starting address of this */
-						/* quad's low shared block */
-						/* (untranslated). */
-						/* In MB. */
-	unsigned int	low_shrd_mem_start;	/* Starting address of this */
-						/* quad's low shared memory */
-						/* (untranslated). */
-						/* In MB. */
-	unsigned int	low_shrd_mem_size;	/* Size of this quad's low */
-						/* shared memory. */
-						/* In MB. */
-	unsigned int	lmmio_copb_start;	/* Starting address of this */
-						/* quad's local memory */
-						/* mapped I/O in the */
-						/* compatibility OPB. */
-						/* In MB. */
-	unsigned int	lmmio_copb_size;	/* Size of this quad's local */
-						/* memory mapped I/O in the */
-						/* compatibility OPB. */
-						/* In MB. */
-	unsigned int	lmmio_nopb_start;	/* Starting address of this */
-						/* quad's local memory */
-						/* mapped I/O in the */
-						/* non-compatibility OPB. */
-						/* In MB. */
-	unsigned int	lmmio_nopb_size;	/* Size of this quad's local */
-						/* memory mapped I/O in the */
-						/* non-compatibility OPB. */
-						/* In MB. */
-	unsigned int	io_apic_0_start;	/* Starting address of I/O */
-						/* APIC 0. */
-	unsigned int	io_apic_0_sz;		/* Size I/O APIC 0. */
-	unsigned int	io_apic_1_start;	/* Starting address of I/O */
-						/* APIC 1. */
-	unsigned int	io_apic_1_sz;		/* Size I/O APIC 1. */
-	unsigned int	hi_shrd_mem_start;	/* Starting address of this */
-						/* quad's high shared memory.*/
-						/* In MB. */
-	unsigned int	hi_shrd_mem_size;	/* Size of this quad's high */
-						/* shared memory. */
-						/* In MB. */
-	unsigned int	mps_table_addr;		/* Address of this quad's */
-						/* MPS tables from BIOS, */
-						/* in system space.*/
-	unsigned int	lcl_MDC_pio_addr;	/* Port-I/O address for */
-						/* local access of MDC. */
-	unsigned int	rmt_MDC_mmpio_addr;	/* MM-Port-I/O address for */
-						/* remote access of MDC. */
-	unsigned int	mm_port_io_start;	/* Starting address of this */
-						/* quad's memory mapped Port */
-						/* I/O space. */
-	unsigned int	mm_port_io_size;	/* Size of this quad's memory*/
-						/* mapped Port I/O space. */
-	unsigned int	mm_rmt_io_apic_start;	/* Starting address of this */
-						/* quad's memory mapped */
-						/* remote I/O APIC space. */
-	unsigned int	mm_rmt_io_apic_size;	/* Size of this quad's memory*/
-						/* mapped remote I/O APIC */
-						/* space. */
-	unsigned int	mm_isa_start;		/* Starting address of this */
-						/* quad's memory mapped ISA */
-						/* space (contains MDC */
-						/* memory space). */
-	unsigned int	mm_isa_size;		/* Size of this quad's memory*/
-						/* mapped ISA space (contains*/
-						/* MDC memory space). */
-	unsigned int	rmt_qmi_addr;		/* Remote addr to access QMI.*/
-	unsigned int	lcl_qmi_addr;		/* Local addr to access QMI. */
-};
-
-/*
- * Note: This structure must be NOT be changed unless the multiproc and
- * OS are changed to reflect the new structure.
- */
-struct sys_cfg_data {
-	unsigned int	quad_id;
-	unsigned int	bsp_proc_id; /* Boot Strap Processor in this quad. */
-	unsigned int	scd_version; /* Version number of this table. */
-	unsigned int	first_quad_id;
-	unsigned int	quads_present31_0; /* 1 bit for each quad */
-	unsigned int	quads_present63_32; /* 1 bit for each quad */
-	unsigned int	config_flags;
-	unsigned int	boot_flags;
-	unsigned int	csr_start_addr; /* Absolute value (not in MB) */
-	unsigned int	csr_size; /* Absolute value (not in MB) */
-	unsigned int	lcl_apic_start_addr; /* Absolute value (not in MB) */
-	unsigned int	lcl_apic_size; /* Absolute value (not in MB) */
-	unsigned int	low_shrd_mem_base; /* 0 or 512MB or 1GB */
-	unsigned int	low_shrd_mem_quad_offset; /* 0,128M,256M,512M,1G */
-					/* may not be totally populated */
-	unsigned int	split_mem_enbl; /* 0 for no low shared memory */
-	unsigned int	mmio_sz; /* Size of total system memory mapped I/O */
-				 /* (in MB). */
-	unsigned int	quad_spin_lock; /* Spare location used for quad */
-					/* bringup. */
-	unsigned int	nonzero55; /* For checksumming. */
-	unsigned int	nonzeroaa; /* For checksumming. */
-	unsigned int	scd_magic_number;
-	unsigned int	system_type;
-	unsigned int	checksum;
-	/*
-	 *	memory configuration area for each quad
-	 */
-	struct		eachquadmem eq[MAX_NUMNODES];	/* indexed by quad id */
-};
-
-void numaq_tsc_disable(void);
-
-#else
-static inline int get_memcfg_numaq(void)
-{
-	return 0;
-}
-#endif /* CONFIG_X86_NUMAQ */
-#endif /* ASM_X86__NUMAQ_H */
-
diff --git a/include/asm-x86/numaq/apic.h b/include/asm-x86/numaq/apic.h
deleted file mode 100644
index a8344ba6ea15..000000000000
--- a/include/asm-x86/numaq/apic.h
+++ /dev/null
@@ -1,138 +0,0 @@
-#ifndef __ASM_NUMAQ_APIC_H
-#define __ASM_NUMAQ_APIC_H
-
-#include <asm/io.h>
-#include <linux/mmzone.h>
-#include <linux/nodemask.h>
-
-#define APIC_DFR_VALUE	(APIC_DFR_CLUSTER)
-
-static inline cpumask_t target_cpus(void)
-{
-	return CPU_MASK_ALL;
-}
-
-#define TARGET_CPUS (target_cpus())
-
-#define NO_BALANCE_IRQ (1)
-#define esr_disable (1)
-
-#define INT_DELIVERY_MODE dest_LowestPrio
-#define INT_DEST_MODE 0     /* physical delivery on LOCAL quad */
- 
-static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
-{
-	return physid_isset(apicid, bitmap);
-}
-static inline unsigned long check_apicid_present(int bit)
-{
-	return physid_isset(bit, phys_cpu_present_map);
-}
-#define apicid_cluster(apicid) (apicid & 0xF0)
-
-static inline int apic_id_registered(void)
-{
-	return 1;
-}
-
-static inline void init_apic_ldr(void)
-{
-	/* Already done in NUMA-Q firmware */
-}
-
-static inline void setup_apic_routing(void)
-{
-	printk("Enabling APIC mode:  %s.  Using %d I/O APICs\n",
-		"NUMA-Q", nr_ioapics);
-}
-
-/*
- * Skip adding the timer int on secondary nodes, which causes
- * a small but painful rift in the time-space continuum.
- */
-static inline int multi_timer_check(int apic, int irq)
-{
-	return apic != 0 && irq == 0;
-}
-
-static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
-{
-	/* We don't have a good way to do this yet - hack */
-	return physids_promote(0xFUL);
-}
-
-/* Mapping from cpu number to logical apicid */
-extern u8 cpu_2_logical_apicid[];
-static inline int cpu_to_logical_apicid(int cpu)
-{
-       if (cpu >= NR_CPUS)
-	       return BAD_APICID;
-	return (int)cpu_2_logical_apicid[cpu];
-}
-
-/*
- * Supporting over 60 cpus on NUMA-Q requires a locality-dependent
- * cpu to APIC ID relation to properly interact with the intelligent
- * mode of the cluster controller.
- */
-static inline int cpu_present_to_apicid(int mps_cpu)
-{
-	if (mps_cpu < 60)
-		return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
-	else
-		return BAD_APICID;
-}
-
-static inline int apicid_to_node(int logical_apicid) 
-{
-	return logical_apicid >> 4;
-}
-
-static inline physid_mask_t apicid_to_cpu_present(int logical_apicid)
-{
-	int node = apicid_to_node(logical_apicid);
-	int cpu = __ffs(logical_apicid & 0xf);
-
-	return physid_mask_of_physid(cpu + 4*node);
-}
-
-extern void *xquad_portio;
-
-static inline void setup_portio_remap(void)
-{
-	int num_quads = num_online_nodes();
-
-	if (num_quads <= 1)
-       		return;
-
-	printk("Remapping cross-quad port I/O for %d quads\n", num_quads);
-	xquad_portio = ioremap(XQUAD_PORTIO_BASE, num_quads*XQUAD_PORTIO_QUAD);
-	printk("xquad_portio vaddr 0x%08lx, len %08lx\n",
-		(u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD);
-}
-
-static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
-{
-	return (1);
-}
-
-static inline void enable_apic_mode(void)
-{
-}
-
-/*
- * We use physical apicids here, not logical, so just return the default
- * physical broadcast to stop people from breaking us
- */
-static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
-{
-	return (int) 0xF;
-}
-
-/* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
-static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
-{
-	return cpuid_apic >> index_msb;
-}
-
-#endif /* __ASM_NUMAQ_APIC_H */
diff --git a/include/asm-x86/numaq/apicdef.h b/include/asm-x86/numaq/apicdef.h
deleted file mode 100644
index e012a46cc22a..000000000000
--- a/include/asm-x86/numaq/apicdef.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef __ASM_NUMAQ_APICDEF_H
-#define __ASM_NUMAQ_APICDEF_H
-
-
-#define APIC_ID_MASK (0xF<<24)
-
-static inline unsigned get_apic_id(unsigned long x)
-{
-	        return (((x)>>24)&0x0F);
-}
-
-#define         GET_APIC_ID(x)  get_apic_id(x)
-
-#endif
diff --git a/include/asm-x86/numaq/ipi.h b/include/asm-x86/numaq/ipi.h
deleted file mode 100644
index 935588d286cf..000000000000
--- a/include/asm-x86/numaq/ipi.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef __ASM_NUMAQ_IPI_H
-#define __ASM_NUMAQ_IPI_H
-
-void send_IPI_mask_sequence(cpumask_t, int vector);
-
-static inline void send_IPI_mask(cpumask_t mask, int vector)
-{
-	send_IPI_mask_sequence(mask, vector);
-}
-
-static inline void send_IPI_allbutself(int vector)
-{
-	cpumask_t mask = cpu_online_map;
-	cpu_clear(smp_processor_id(), mask);
-
-	if (!cpus_empty(mask))
-		send_IPI_mask(mask, vector);
-}
-
-static inline void send_IPI_all(int vector)
-{
-	send_IPI_mask(cpu_online_map, vector);
-}
-
-#endif /* __ASM_NUMAQ_IPI_H */
diff --git a/include/asm-x86/numaq/mpparse.h b/include/asm-x86/numaq/mpparse.h
deleted file mode 100644
index 252292e077b6..000000000000
--- a/include/asm-x86/numaq/mpparse.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_NUMAQ_MPPARSE_H
-#define __ASM_NUMAQ_MPPARSE_H
-
-extern void numaq_mps_oem_check(struct mp_config_table *mpc, char *oem,
-				char *productid);
-
-#endif /* __ASM_NUMAQ_MPPARSE_H */
diff --git a/include/asm-x86/numaq/wakecpu.h b/include/asm-x86/numaq/wakecpu.h
deleted file mode 100644
index c577bda5b1c5..000000000000
--- a/include/asm-x86/numaq/wakecpu.h
+++ /dev/null
@@ -1,43 +0,0 @@
-#ifndef __ASM_NUMAQ_WAKECPU_H
-#define __ASM_NUMAQ_WAKECPU_H
-
-/* This file copes with machines that wakeup secondary CPUs by NMIs */
-
-#define WAKE_SECONDARY_VIA_NMI
-
-#define TRAMPOLINE_LOW phys_to_virt(0x8)
-#define TRAMPOLINE_HIGH phys_to_virt(0xa)
-
-#define boot_cpu_apicid boot_cpu_logical_apicid
-
-/* We don't do anything here because we use NMI's to boot instead */
-static inline void wait_for_init_deassert(atomic_t *deassert)
-{
-}
-
-/*
- * Because we use NMIs rather than the INIT-STARTUP sequence to
- * bootstrap the CPUs, the APIC may be in a weird state. Kick it.
- */
-static inline void smp_callin_clear_local_apic(void)
-{
-	clear_local_APIC();
-}
-
-static inline void store_NMI_vector(unsigned short *high, unsigned short *low)
-{
-	printk("Storing NMI vector\n");
-	*high = *((volatile unsigned short *) TRAMPOLINE_HIGH);
-	*low = *((volatile unsigned short *) TRAMPOLINE_LOW);
-}
-
-static inline void restore_NMI_vector(unsigned short *high, unsigned short *low)
-{
-	printk("Restoring NMI vector\n");
-	*((volatile unsigned short *) TRAMPOLINE_HIGH) = *high;
-	*((volatile unsigned short *) TRAMPOLINE_LOW) = *low;
-}
-
-#define inquire_remote_apic(apicid) {}
-
-#endif /* __ASM_NUMAQ_WAKECPU_H */
diff --git a/include/asm-x86/olpc.h b/include/asm-x86/olpc.h
deleted file mode 100644
index d7328b1a05c1..000000000000
--- a/include/asm-x86/olpc.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* OLPC machine specific definitions */
-
-#ifndef ASM_X86__OLPC_H
-#define ASM_X86__OLPC_H
-
-#include <asm/geode.h>
-
-struct olpc_platform_t {
-	int flags;
-	uint32_t boardrev;
-	int ecver;
-};
-
-#define OLPC_F_PRESENT		0x01
-#define OLPC_F_DCON		0x02
-#define OLPC_F_VSA		0x04
-
-#ifdef CONFIG_OLPC
-
-extern struct olpc_platform_t olpc_platform_info;
-
-/*
- * OLPC board IDs contain the major build number within the mask 0x0ff0,
- * and the minor build number withing 0x000f.  Pre-builds have a minor
- * number less than 8, and normal builds start at 8.  For example, 0x0B10
- * is a PreB1, and 0x0C18 is a C1.
- */
-
-static inline uint32_t olpc_board(uint8_t id)
-{
-	return (id << 4) | 0x8;
-}
-
-static inline uint32_t olpc_board_pre(uint8_t id)
-{
-	return id << 4;
-}
-
-static inline int machine_is_olpc(void)
-{
-	return (olpc_platform_info.flags & OLPC_F_PRESENT) ? 1 : 0;
-}
-
-/*
- * The DCON is OLPC's Display Controller.  It has a number of unique
- * features that we might want to take advantage of..
- */
-static inline int olpc_has_dcon(void)
-{
-	return (olpc_platform_info.flags & OLPC_F_DCON) ? 1 : 0;
-}
-
-/*
- * The VSA is software from AMD that typical Geode bioses will include.
- * It is used to emulate the PCI bus, VGA, etc.  OLPC's Open Firmware does
- * not include the VSA; instead, PCI is emulated by the kernel.
- *
- * The VSA is described further in arch/x86/pci/olpc.c.
- */
-static inline int olpc_has_vsa(void)
-{
-	return (olpc_platform_info.flags & OLPC_F_VSA) ? 1 : 0;
-}
-
-/*
- * The "Mass Production" version of OLPC's XO is identified as being model
- * C2.  During the prototype phase, the following models (in chronological
- * order) were created: A1, B1, B2, B3, B4, C1.  The A1 through B2 models
- * were based on Geode GX CPUs, and models after that were based upon
- * Geode LX CPUs.  There were also some hand-assembled models floating
- * around, referred to as PreB1, PreB2, etc.
- */
-static inline int olpc_board_at_least(uint32_t rev)
-{
-	return olpc_platform_info.boardrev >= rev;
-}
-
-#else
-
-static inline int machine_is_olpc(void)
-{
-	return 0;
-}
-
-static inline int olpc_has_dcon(void)
-{
-	return 0;
-}
-
-static inline int olpc_has_vsa(void)
-{
-	return 0;
-}
-
-#endif
-
-/* EC related functions */
-
-extern int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen,
-		unsigned char *outbuf, size_t outlen);
-
-extern int olpc_ec_mask_set(uint8_t bits);
-extern int olpc_ec_mask_unset(uint8_t bits);
-
-/* EC commands */
-
-#define EC_FIRMWARE_REV		0x08
-
-/* SCI source values */
-
-#define EC_SCI_SRC_EMPTY	0x00
-#define EC_SCI_SRC_GAME		0x01
-#define EC_SCI_SRC_BATTERY	0x02
-#define EC_SCI_SRC_BATSOC	0x04
-#define EC_SCI_SRC_BATERR	0x08
-#define EC_SCI_SRC_EBOOK	0x10
-#define EC_SCI_SRC_WLAN		0x20
-#define EC_SCI_SRC_ACPWR	0x40
-#define EC_SCI_SRC_ALL		0x7F
-
-/* GPIO assignments */
-
-#define OLPC_GPIO_MIC_AC	geode_gpio(1)
-#define OLPC_GPIO_DCON_IRQ	geode_gpio(7)
-#define OLPC_GPIO_THRM_ALRM	geode_gpio(10)
-#define OLPC_GPIO_SMB_CLK	geode_gpio(14)
-#define OLPC_GPIO_SMB_DATA	geode_gpio(15)
-#define OLPC_GPIO_WORKAUX	geode_gpio(24)
-#define OLPC_GPIO_LID		geode_gpio(26)
-#define OLPC_GPIO_ECSCI		geode_gpio(27)
-
-#endif /* ASM_X86__OLPC_H */
diff --git a/include/asm-x86/page.h b/include/asm-x86/page.h
deleted file mode 100644
index d4f1d5791fc1..000000000000
--- a/include/asm-x86/page.h
+++ /dev/null
@@ -1,209 +0,0 @@
-#ifndef ASM_X86__PAGE_H
-#define ASM_X86__PAGE_H
-
-#include <linux/const.h>
-
-/* PAGE_SHIFT determines the page size */
-#define PAGE_SHIFT	12
-#define PAGE_SIZE	(_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK	(~(PAGE_SIZE-1))
-
-#ifdef __KERNEL__
-
-#define __PHYSICAL_MASK		((phys_addr_t)(1ULL << __PHYSICAL_MASK_SHIFT) - 1)
-#define __VIRTUAL_MASK		((1UL << __VIRTUAL_MASK_SHIFT) - 1)
-
-/* Cast PAGE_MASK to a signed type so that it is sign-extended if
-   virtual addresses are 32-bits but physical addresses are larger
-   (ie, 32-bit PAE). */
-#define PHYSICAL_PAGE_MASK	(((signed long)PAGE_MASK) & __PHYSICAL_MASK)
-
-/* PTE_PFN_MASK extracts the PFN from a (pte|pmd|pud|pgd)val_t */
-#define PTE_PFN_MASK		((pteval_t)PHYSICAL_PAGE_MASK)
-
-/* PTE_FLAGS_MASK extracts the flags from a (pte|pmd|pud|pgd)val_t */
-#define PTE_FLAGS_MASK		(~PTE_PFN_MASK)
-
-#define PMD_PAGE_SIZE		(_AC(1, UL) << PMD_SHIFT)
-#define PMD_PAGE_MASK		(~(PMD_PAGE_SIZE-1))
-
-#define HPAGE_SHIFT		PMD_SHIFT
-#define HPAGE_SIZE		(_AC(1,UL) << HPAGE_SHIFT)
-#define HPAGE_MASK		(~(HPAGE_SIZE - 1))
-#define HUGETLB_PAGE_ORDER	(HPAGE_SHIFT - PAGE_SHIFT)
-
-#define HUGE_MAX_HSTATE 2
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#endif
-
-#ifdef CONFIG_X86_64
-#include <asm/page_64.h>
-#else
-#include <asm/page_32.h>
-#endif	/* CONFIG_X86_64 */
-
-#define PAGE_OFFSET		((unsigned long)__PAGE_OFFSET)
-
-#define VM_DATA_DEFAULT_FLAGS \
-	(((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
-	 VM_READ | VM_WRITE | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-
-#ifndef __ASSEMBLY__
-
-typedef struct { pgdval_t pgd; } pgd_t;
-typedef struct { pgprotval_t pgprot; } pgprot_t;
-
-extern int page_is_ram(unsigned long pagenr);
-extern int pagerange_is_ram(unsigned long start, unsigned long end);
-extern int devmem_is_allowed(unsigned long pagenr);
-extern void map_devmem(unsigned long pfn, unsigned long size,
-		       pgprot_t vma_prot);
-extern void unmap_devmem(unsigned long pfn, unsigned long size,
-			 pgprot_t vma_prot);
-
-extern unsigned long max_low_pfn_mapped;
-extern unsigned long max_pfn_mapped;
-
-struct page;
-
-static inline void clear_user_page(void *page, unsigned long vaddr,
-				struct page *pg)
-{
-	clear_page(page);
-}
-
-static inline void copy_user_page(void *to, void *from, unsigned long vaddr,
-				struct page *topage)
-{
-	copy_page(to, from);
-}
-
-#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \
-	alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr)
-#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
-
-static inline pgd_t native_make_pgd(pgdval_t val)
-{
-	return (pgd_t) { val };
-}
-
-static inline pgdval_t native_pgd_val(pgd_t pgd)
-{
-	return pgd.pgd;
-}
-
-#if PAGETABLE_LEVELS >= 3
-#if PAGETABLE_LEVELS == 4
-typedef struct { pudval_t pud; } pud_t;
-
-static inline pud_t native_make_pud(pmdval_t val)
-{
-	return (pud_t) { val };
-}
-
-static inline pudval_t native_pud_val(pud_t pud)
-{
-	return pud.pud;
-}
-#else	/* PAGETABLE_LEVELS == 3 */
-#include <asm-generic/pgtable-nopud.h>
-
-static inline pudval_t native_pud_val(pud_t pud)
-{
-	return native_pgd_val(pud.pgd);
-}
-#endif	/* PAGETABLE_LEVELS == 4 */
-
-typedef struct { pmdval_t pmd; } pmd_t;
-
-static inline pmd_t native_make_pmd(pmdval_t val)
-{
-	return (pmd_t) { val };
-}
-
-static inline pmdval_t native_pmd_val(pmd_t pmd)
-{
-	return pmd.pmd;
-}
-#else  /* PAGETABLE_LEVELS == 2 */
-#include <asm-generic/pgtable-nopmd.h>
-
-static inline pmdval_t native_pmd_val(pmd_t pmd)
-{
-	return native_pgd_val(pmd.pud.pgd);
-}
-#endif	/* PAGETABLE_LEVELS >= 3 */
-
-static inline pte_t native_make_pte(pteval_t val)
-{
-	return (pte_t) { .pte = val };
-}
-
-static inline pteval_t native_pte_val(pte_t pte)
-{
-	return pte.pte;
-}
-
-static inline pteval_t native_pte_flags(pte_t pte)
-{
-	return native_pte_val(pte) & PTE_FLAGS_MASK;
-}
-
-#define pgprot_val(x)	((x).pgprot)
-#define __pgprot(x)	((pgprot_t) { (x) } )
-
-#ifdef CONFIG_PARAVIRT
-#include <asm/paravirt.h>
-#else  /* !CONFIG_PARAVIRT */
-
-#define pgd_val(x)	native_pgd_val(x)
-#define __pgd(x)	native_make_pgd(x)
-
-#ifndef __PAGETABLE_PUD_FOLDED
-#define pud_val(x)	native_pud_val(x)
-#define __pud(x)	native_make_pud(x)
-#endif
-
-#ifndef __PAGETABLE_PMD_FOLDED
-#define pmd_val(x)	native_pmd_val(x)
-#define __pmd(x)	native_make_pmd(x)
-#endif
-
-#define pte_val(x)	native_pte_val(x)
-#define pte_flags(x)	native_pte_flags(x)
-#define __pte(x)	native_make_pte(x)
-
-#endif	/* CONFIG_PARAVIRT */
-
-#define __pa(x)		__phys_addr((unsigned long)(x))
-#define __pa_nodebug(x)	__phys_addr_nodebug((unsigned long)(x))
-/* __pa_symbol should be used for C visible symbols.
-   This seems to be the official gcc blessed way to do such arithmetic. */
-#define __pa_symbol(x)	__pa(__phys_reloc_hide((unsigned long)(x)))
-
-#define __va(x)			((void *)((unsigned long)(x)+PAGE_OFFSET))
-
-#define __boot_va(x)		__va(x)
-#define __boot_pa(x)		__pa(x)
-
-/*
- * virt_to_page(kaddr) returns a valid pointer if and only if
- * virt_addr_valid(kaddr) returns true.
- */
-#define virt_to_page(kaddr)	pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
-#define pfn_to_kaddr(pfn)      __va((pfn) << PAGE_SHIFT)
-extern bool __virt_addr_valid(unsigned long kaddr);
-#define virt_addr_valid(kaddr)	__virt_addr_valid((unsigned long) (kaddr))
-
-#endif	/* __ASSEMBLY__ */
-
-#include <asm-generic/memory_model.h>
-#include <asm-generic/page.h>
-
-#define __HAVE_ARCH_GATE_AREA 1
-
-#endif	/* __KERNEL__ */
-#endif /* ASM_X86__PAGE_H */
diff --git a/include/asm-x86/page_32.h b/include/asm-x86/page_32.h
deleted file mode 100644
index e8d80d1de237..000000000000
--- a/include/asm-x86/page_32.h
+++ /dev/null
@@ -1,138 +0,0 @@
-#ifndef ASM_X86__PAGE_32_H
-#define ASM_X86__PAGE_32_H
-
-/*
- * This handles the memory map.
- *
- * A __PAGE_OFFSET of 0xC0000000 means that the kernel has
- * a virtual address space of one gigabyte, which limits the
- * amount of physical memory you can use to about 950MB.
- *
- * If you want more physical memory than this then see the CONFIG_HIGHMEM4G
- * and CONFIG_HIGHMEM64G options in the kernel configuration.
- */
-#define __PAGE_OFFSET		_AC(CONFIG_PAGE_OFFSET, UL)
-
-#ifdef CONFIG_4KSTACKS
-#define THREAD_ORDER	0
-#else
-#define THREAD_ORDER	1
-#endif
-#define THREAD_SIZE 	(PAGE_SIZE << THREAD_ORDER)
-
-#define STACKFAULT_STACK 0
-#define DOUBLEFAULT_STACK 1
-#define NMI_STACK 0
-#define DEBUG_STACK 0
-#define MCE_STACK 0
-#define N_EXCEPTION_STACKS 1
-
-#ifdef CONFIG_X86_PAE
-/* 44=32+12, the limit we can fit into an unsigned long pfn */
-#define __PHYSICAL_MASK_SHIFT	44
-#define __VIRTUAL_MASK_SHIFT	32
-#define PAGETABLE_LEVELS	3
-
-#ifndef __ASSEMBLY__
-typedef u64	pteval_t;
-typedef u64	pmdval_t;
-typedef u64	pudval_t;
-typedef u64	pgdval_t;
-typedef u64	pgprotval_t;
-typedef u64	phys_addr_t;
-
-typedef union {
-	struct {
-		unsigned long pte_low, pte_high;
-	};
-	pteval_t pte;
-} pte_t;
-#endif	/* __ASSEMBLY__
- */
-#else  /* !CONFIG_X86_PAE */
-#define __PHYSICAL_MASK_SHIFT	32
-#define __VIRTUAL_MASK_SHIFT	32
-#define PAGETABLE_LEVELS	2
-
-#ifndef __ASSEMBLY__
-typedef unsigned long	pteval_t;
-typedef unsigned long	pmdval_t;
-typedef unsigned long	pudval_t;
-typedef unsigned long	pgdval_t;
-typedef unsigned long	pgprotval_t;
-typedef unsigned long	phys_addr_t;
-
-typedef union {
-	pteval_t pte;
-	pteval_t pte_low;
-} pte_t;
-
-#endif	/* __ASSEMBLY__ */
-#endif	/* CONFIG_X86_PAE */
-
-#ifndef __ASSEMBLY__
-typedef struct page *pgtable_t;
-#endif
-
-#ifdef CONFIG_HUGETLB_PAGE
-#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
-#endif
-
-#ifndef __ASSEMBLY__
-#define __phys_addr_nodebug(x)	((x) - PAGE_OFFSET)
-#ifdef CONFIG_DEBUG_VIRTUAL
-extern unsigned long __phys_addr(unsigned long);
-#else
-#define __phys_addr(x)		__phys_addr_nodebug(x)
-#endif
-#define __phys_reloc_hide(x)	RELOC_HIDE((x), 0)
-
-#ifdef CONFIG_FLATMEM
-#define pfn_valid(pfn)		((pfn) < max_mapnr)
-#endif /* CONFIG_FLATMEM */
-
-extern int nx_enabled;
-
-/*
- * This much address space is reserved for vmalloc() and iomap()
- * as well as fixmap mappings.
- */
-extern unsigned int __VMALLOC_RESERVE;
-extern int sysctl_legacy_va_layout;
-
-extern void find_low_pfn_range(void);
-extern unsigned long init_memory_mapping(unsigned long start,
-					 unsigned long end);
-extern void initmem_init(unsigned long, unsigned long);
-extern void free_initmem(void);
-extern void setup_bootmem_allocator(void);
-
-
-#ifdef CONFIG_X86_USE_3DNOW
-#include <asm/mmx.h>
-
-static inline void clear_page(void *page)
-{
-	mmx_clear_page(page);
-}
-
-static inline void copy_page(void *to, void *from)
-{
-	mmx_copy_page(to, from);
-}
-#else  /* !CONFIG_X86_USE_3DNOW */
-#include <linux/string.h>
-
-static inline void clear_page(void *page)
-{
-	memset(page, 0, PAGE_SIZE);
-}
-
-static inline void copy_page(void *to, void *from)
-{
-	memcpy(to, from, PAGE_SIZE);
-}
-#endif	/* CONFIG_X86_3DNOW */
-#endif	/* !__ASSEMBLY__ */
-
-#endif /* ASM_X86__PAGE_32_H */
diff --git a/include/asm-x86/page_64.h b/include/asm-x86/page_64.h
deleted file mode 100644
index 5e64acfed0a4..000000000000
--- a/include/asm-x86/page_64.h
+++ /dev/null
@@ -1,106 +0,0 @@
-#ifndef ASM_X86__PAGE_64_H
-#define ASM_X86__PAGE_64_H
-
-#define PAGETABLE_LEVELS	4
-
-#define THREAD_ORDER	1
-#define THREAD_SIZE  (PAGE_SIZE << THREAD_ORDER)
-#define CURRENT_MASK (~(THREAD_SIZE - 1))
-
-#define EXCEPTION_STACK_ORDER 0
-#define EXCEPTION_STKSZ (PAGE_SIZE << EXCEPTION_STACK_ORDER)
-
-#define DEBUG_STACK_ORDER (EXCEPTION_STACK_ORDER + 1)
-#define DEBUG_STKSZ (PAGE_SIZE << DEBUG_STACK_ORDER)
-
-#define IRQSTACK_ORDER 2
-#define IRQSTACKSIZE (PAGE_SIZE << IRQSTACK_ORDER)
-
-#define STACKFAULT_STACK 1
-#define DOUBLEFAULT_STACK 2
-#define NMI_STACK 3
-#define DEBUG_STACK 4
-#define MCE_STACK 5
-#define N_EXCEPTION_STACKS 5  /* hw limit: 7 */
-
-#define PUD_PAGE_SIZE		(_AC(1, UL) << PUD_SHIFT)
-#define PUD_PAGE_MASK		(~(PUD_PAGE_SIZE-1))
-
-/*
- * Set __PAGE_OFFSET to the most negative possible address +
- * PGDIR_SIZE*16 (pgd slot 272).  The gap is to allow a space for a
- * hypervisor to fit.  Choosing 16 slots here is arbitrary, but it's
- * what Xen requires.
- */
-#define __PAGE_OFFSET           _AC(0xffff880000000000, UL)
-
-#define __PHYSICAL_START	CONFIG_PHYSICAL_START
-#define __KERNEL_ALIGN		0x200000
-
-/*
- * Make sure kernel is aligned to 2MB address. Catching it at compile
- * time is better. Change your config file and compile the kernel
- * for a 2MB aligned address (CONFIG_PHYSICAL_START)
- */
-#if (CONFIG_PHYSICAL_START % __KERNEL_ALIGN) != 0
-#error "CONFIG_PHYSICAL_START must be a multiple of 2MB"
-#endif
-
-#define __START_KERNEL		(__START_KERNEL_map + __PHYSICAL_START)
-#define __START_KERNEL_map	_AC(0xffffffff80000000, UL)
-
-/* See Documentation/x86_64/mm.txt for a description of the memory map. */
-#define __PHYSICAL_MASK_SHIFT	46
-#define __VIRTUAL_MASK_SHIFT	48
-
-/*
- * Kernel image size is limited to 512 MB (see level2_kernel_pgt in
- * arch/x86/kernel/head_64.S), and it is mapped here:
- */
-#define KERNEL_IMAGE_SIZE	(512 * 1024 * 1024)
-#define KERNEL_IMAGE_START	_AC(0xffffffff80000000, UL)
-
-#ifndef __ASSEMBLY__
-void clear_page(void *page);
-void copy_page(void *to, void *from);
-
-/* duplicated to the one in bootmem.h */
-extern unsigned long max_pfn;
-extern unsigned long phys_base;
-
-extern unsigned long __phys_addr(unsigned long);
-#define __phys_reloc_hide(x)	(x)
-
-/*
- * These are used to make use of C type-checking..
- */
-typedef unsigned long	pteval_t;
-typedef unsigned long	pmdval_t;
-typedef unsigned long	pudval_t;
-typedef unsigned long	pgdval_t;
-typedef unsigned long	pgprotval_t;
-typedef unsigned long	phys_addr_t;
-
-typedef struct page *pgtable_t;
-
-typedef struct { pteval_t pte; } pte_t;
-
-#define vmemmap ((struct page *)VMEMMAP_START)
-
-extern unsigned long init_memory_mapping(unsigned long start,
-					 unsigned long end);
-
-extern void initmem_init(unsigned long start_pfn, unsigned long end_pfn);
-extern void free_initmem(void);
-
-extern void init_extra_mapping_uc(unsigned long phys, unsigned long size);
-extern void init_extra_mapping_wb(unsigned long phys, unsigned long size);
-
-#endif	/* !__ASSEMBLY__ */
-
-#ifdef CONFIG_FLATMEM
-#define pfn_valid(pfn)          ((pfn) < max_pfn)
-#endif
-
-
-#endif /* ASM_X86__PAGE_64_H */
diff --git a/include/asm-x86/param.h b/include/asm-x86/param.h
deleted file mode 100644
index 0009cfb11a5f..000000000000
--- a/include/asm-x86/param.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef ASM_X86__PARAM_H
-#define ASM_X86__PARAM_H
-
-#ifdef __KERNEL__
-# define HZ		CONFIG_HZ	/* Internal kernel timer frequency */
-# define USER_HZ	100		/* some user interfaces are */
-# define CLOCKS_PER_SEC	(USER_HZ)       /* in "ticks" like times() */
-#endif
-
-#ifndef HZ
-#define HZ 100
-#endif
-
-#define EXEC_PAGESIZE	4096
-
-#ifndef NOGROUP
-#define NOGROUP		(-1)
-#endif
-
-#define MAXHOSTNAMELEN	64	/* max length of hostname */
-
-#endif /* ASM_X86__PARAM_H */
diff --git a/include/asm-x86/paravirt.h b/include/asm-x86/paravirt.h
deleted file mode 100644
index 8d6ae2f760d0..000000000000
--- a/include/asm-x86/paravirt.h
+++ /dev/null
@@ -1,1650 +0,0 @@
-#ifndef ASM_X86__PARAVIRT_H
-#define ASM_X86__PARAVIRT_H
-/* Various instructions on x86 need to be replaced for
- * para-virtualization: those hooks are defined here. */
-
-#ifdef CONFIG_PARAVIRT
-#include <asm/page.h>
-#include <asm/asm.h>
-
-/* Bitmask of what can be clobbered: usually at least eax. */
-#define CLBR_NONE 0
-#define CLBR_EAX  (1 << 0)
-#define CLBR_ECX  (1 << 1)
-#define CLBR_EDX  (1 << 2)
-
-#ifdef CONFIG_X86_64
-#define CLBR_RSI  (1 << 3)
-#define CLBR_RDI  (1 << 4)
-#define CLBR_R8   (1 << 5)
-#define CLBR_R9   (1 << 6)
-#define CLBR_R10  (1 << 7)
-#define CLBR_R11  (1 << 8)
-#define CLBR_ANY  ((1 << 9) - 1)
-#include <asm/desc_defs.h>
-#else
-/* CLBR_ANY should match all regs platform has. For i386, that's just it */
-#define CLBR_ANY  ((1 << 3) - 1)
-#endif /* X86_64 */
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#include <linux/cpumask.h>
-#include <asm/kmap_types.h>
-#include <asm/desc_defs.h>
-
-struct page;
-struct thread_struct;
-struct desc_ptr;
-struct tss_struct;
-struct mm_struct;
-struct desc_struct;
-
-/* general info */
-struct pv_info {
-	unsigned int kernel_rpl;
-	int shared_kernel_pmd;
-	int paravirt_enabled;
-	const char *name;
-};
-
-struct pv_init_ops {
-	/*
-	 * Patch may replace one of the defined code sequences with
-	 * arbitrary code, subject to the same register constraints.
-	 * This generally means the code is not free to clobber any
-	 * registers other than EAX.  The patch function should return
-	 * the number of bytes of code generated, as we nop pad the
-	 * rest in generic code.
-	 */
-	unsigned (*patch)(u8 type, u16 clobber, void *insnbuf,
-			  unsigned long addr, unsigned len);
-
-	/* Basic arch-specific setup */
-	void (*arch_setup)(void);
-	char *(*memory_setup)(void);
-	void (*post_allocator_init)(void);
-
-	/* Print a banner to identify the environment */
-	void (*banner)(void);
-};
-
-
-struct pv_lazy_ops {
-	/* Set deferred update mode, used for batching operations. */
-	void (*enter)(void);
-	void (*leave)(void);
-};
-
-struct pv_time_ops {
-	void (*time_init)(void);
-
-	/* Set and set time of day */
-	unsigned long (*get_wallclock)(void);
-	int (*set_wallclock)(unsigned long);
-
-	unsigned long long (*sched_clock)(void);
-	unsigned long (*get_tsc_khz)(void);
-};
-
-struct pv_cpu_ops {
-	/* hooks for various privileged instructions */
-	unsigned long (*get_debugreg)(int regno);
-	void (*set_debugreg)(int regno, unsigned long value);
-
-	void (*clts)(void);
-
-	unsigned long (*read_cr0)(void);
-	void (*write_cr0)(unsigned long);
-
-	unsigned long (*read_cr4_safe)(void);
-	unsigned long (*read_cr4)(void);
-	void (*write_cr4)(unsigned long);
-
-#ifdef CONFIG_X86_64
-	unsigned long (*read_cr8)(void);
-	void (*write_cr8)(unsigned long);
-#endif
-
-	/* Segment descriptor handling */
-	void (*load_tr_desc)(void);
-	void (*load_gdt)(const struct desc_ptr *);
-	void (*load_idt)(const struct desc_ptr *);
-	void (*store_gdt)(struct desc_ptr *);
-	void (*store_idt)(struct desc_ptr *);
-	void (*set_ldt)(const void *desc, unsigned entries);
-	unsigned long (*store_tr)(void);
-	void (*load_tls)(struct thread_struct *t, unsigned int cpu);
-#ifdef CONFIG_X86_64
-	void (*load_gs_index)(unsigned int idx);
-#endif
-	void (*write_ldt_entry)(struct desc_struct *ldt, int entrynum,
-				const void *desc);
-	void (*write_gdt_entry)(struct desc_struct *,
-				int entrynum, const void *desc, int size);
-	void (*write_idt_entry)(gate_desc *,
-				int entrynum, const gate_desc *gate);
-	void (*alloc_ldt)(struct desc_struct *ldt, unsigned entries);
-	void (*free_ldt)(struct desc_struct *ldt, unsigned entries);
-
-	void (*load_sp0)(struct tss_struct *tss, struct thread_struct *t);
-
-	void (*set_iopl_mask)(unsigned mask);
-
-	void (*wbinvd)(void);
-	void (*io_delay)(void);
-
-	/* cpuid emulation, mostly so that caps bits can be disabled */
-	void (*cpuid)(unsigned int *eax, unsigned int *ebx,
-		      unsigned int *ecx, unsigned int *edx);
-
-	/* MSR, PMC and TSR operations.
-	   err = 0/-EFAULT.  wrmsr returns 0/-EFAULT. */
-	u64 (*read_msr_amd)(unsigned int msr, int *err);
-	u64 (*read_msr)(unsigned int msr, int *err);
-	int (*write_msr)(unsigned int msr, unsigned low, unsigned high);
-
-	u64 (*read_tsc)(void);
-	u64 (*read_pmc)(int counter);
-	unsigned long long (*read_tscp)(unsigned int *aux);
-
-	/*
-	 * Atomically enable interrupts and return to userspace.  This
-	 * is only ever used to return to 32-bit processes; in a
-	 * 64-bit kernel, it's used for 32-on-64 compat processes, but
-	 * never native 64-bit processes.  (Jump, not call.)
-	 */
-	void (*irq_enable_sysexit)(void);
-
-	/*
-	 * Switch to usermode gs and return to 64-bit usermode using
-	 * sysret.  Only used in 64-bit kernels to return to 64-bit
-	 * processes.  Usermode register state, including %rsp, must
-	 * already be restored.
-	 */
-	void (*usergs_sysret64)(void);
-
-	/*
-	 * Switch to usermode gs and return to 32-bit usermode using
-	 * sysret.  Used to return to 32-on-64 compat processes.
-	 * Other usermode register state, including %esp, must already
-	 * be restored.
-	 */
-	void (*usergs_sysret32)(void);
-
-	/* Normal iret.  Jump to this with the standard iret stack
-	   frame set up. */
-	void (*iret)(void);
-
-	void (*swapgs)(void);
-
-	struct pv_lazy_ops lazy_mode;
-};
-
-struct pv_irq_ops {
-	void (*init_IRQ)(void);
-
-	/*
-	 * Get/set interrupt state.  save_fl and restore_fl are only
-	 * expected to use X86_EFLAGS_IF; all other bits
-	 * returned from save_fl are undefined, and may be ignored by
-	 * restore_fl.
-	 */
-	unsigned long (*save_fl)(void);
-	void (*restore_fl)(unsigned long);
-	void (*irq_disable)(void);
-	void (*irq_enable)(void);
-	void (*safe_halt)(void);
-	void (*halt)(void);
-
-#ifdef CONFIG_X86_64
-	void (*adjust_exception_frame)(void);
-#endif
-};
-
-struct pv_apic_ops {
-#ifdef CONFIG_X86_LOCAL_APIC
-	void (*setup_boot_clock)(void);
-	void (*setup_secondary_clock)(void);
-
-	void (*startup_ipi_hook)(int phys_apicid,
-				 unsigned long start_eip,
-				 unsigned long start_esp);
-#endif
-};
-
-struct pv_mmu_ops {
-	/*
-	 * Called before/after init_mm pagetable setup. setup_start
-	 * may reset %cr3, and may pre-install parts of the pagetable;
-	 * pagetable setup is expected to preserve any existing
-	 * mapping.
-	 */
-	void (*pagetable_setup_start)(pgd_t *pgd_base);
-	void (*pagetable_setup_done)(pgd_t *pgd_base);
-
-	unsigned long (*read_cr2)(void);
-	void (*write_cr2)(unsigned long);
-
-	unsigned long (*read_cr3)(void);
-	void (*write_cr3)(unsigned long);
-
-	/*
-	 * Hooks for intercepting the creation/use/destruction of an
-	 * mm_struct.
-	 */
-	void (*activate_mm)(struct mm_struct *prev,
-			    struct mm_struct *next);
-	void (*dup_mmap)(struct mm_struct *oldmm,
-			 struct mm_struct *mm);
-	void (*exit_mmap)(struct mm_struct *mm);
-
-
-	/* TLB operations */
-	void (*flush_tlb_user)(void);
-	void (*flush_tlb_kernel)(void);
-	void (*flush_tlb_single)(unsigned long addr);
-	void (*flush_tlb_others)(const cpumask_t *cpus, struct mm_struct *mm,
-				 unsigned long va);
-
-	/* Hooks for allocating and freeing a pagetable top-level */
-	int  (*pgd_alloc)(struct mm_struct *mm);
-	void (*pgd_free)(struct mm_struct *mm, pgd_t *pgd);
-
-	/*
-	 * Hooks for allocating/releasing pagetable pages when they're
-	 * attached to a pagetable
-	 */
-	void (*alloc_pte)(struct mm_struct *mm, unsigned long pfn);
-	void (*alloc_pmd)(struct mm_struct *mm, unsigned long pfn);
-	void (*alloc_pmd_clone)(unsigned long pfn, unsigned long clonepfn, unsigned long start, unsigned long count);
-	void (*alloc_pud)(struct mm_struct *mm, unsigned long pfn);
-	void (*release_pte)(unsigned long pfn);
-	void (*release_pmd)(unsigned long pfn);
-	void (*release_pud)(unsigned long pfn);
-
-	/* Pagetable manipulation functions */
-	void (*set_pte)(pte_t *ptep, pte_t pteval);
-	void (*set_pte_at)(struct mm_struct *mm, unsigned long addr,
-			   pte_t *ptep, pte_t pteval);
-	void (*set_pmd)(pmd_t *pmdp, pmd_t pmdval);
-	void (*pte_update)(struct mm_struct *mm, unsigned long addr,
-			   pte_t *ptep);
-	void (*pte_update_defer)(struct mm_struct *mm,
-				 unsigned long addr, pte_t *ptep);
-
-	pte_t (*ptep_modify_prot_start)(struct mm_struct *mm, unsigned long addr,
-					pte_t *ptep);
-	void (*ptep_modify_prot_commit)(struct mm_struct *mm, unsigned long addr,
-					pte_t *ptep, pte_t pte);
-
-	pteval_t (*pte_val)(pte_t);
-	pteval_t (*pte_flags)(pte_t);
-	pte_t (*make_pte)(pteval_t pte);
-
-	pgdval_t (*pgd_val)(pgd_t);
-	pgd_t (*make_pgd)(pgdval_t pgd);
-
-#if PAGETABLE_LEVELS >= 3
-#ifdef CONFIG_X86_PAE
-	void (*set_pte_atomic)(pte_t *ptep, pte_t pteval);
-	void (*set_pte_present)(struct mm_struct *mm, unsigned long addr,
-				pte_t *ptep, pte_t pte);
-	void (*pte_clear)(struct mm_struct *mm, unsigned long addr,
-			  pte_t *ptep);
-	void (*pmd_clear)(pmd_t *pmdp);
-
-#endif	/* CONFIG_X86_PAE */
-
-	void (*set_pud)(pud_t *pudp, pud_t pudval);
-
-	pmdval_t (*pmd_val)(pmd_t);
-	pmd_t (*make_pmd)(pmdval_t pmd);
-
-#if PAGETABLE_LEVELS == 4
-	pudval_t (*pud_val)(pud_t);
-	pud_t (*make_pud)(pudval_t pud);
-
-	void (*set_pgd)(pgd_t *pudp, pgd_t pgdval);
-#endif	/* PAGETABLE_LEVELS == 4 */
-#endif	/* PAGETABLE_LEVELS >= 3 */
-
-#ifdef CONFIG_HIGHPTE
-	void *(*kmap_atomic_pte)(struct page *page, enum km_type type);
-#endif
-
-	struct pv_lazy_ops lazy_mode;
-
-	/* dom0 ops */
-
-	/* Sometimes the physical address is a pfn, and sometimes its
-	   an mfn.  We can tell which is which from the index. */
-	void (*set_fixmap)(unsigned /* enum fixed_addresses */ idx,
-			   unsigned long phys, pgprot_t flags);
-};
-
-struct raw_spinlock;
-struct pv_lock_ops {
-	int (*spin_is_locked)(struct raw_spinlock *lock);
-	int (*spin_is_contended)(struct raw_spinlock *lock);
-	void (*spin_lock)(struct raw_spinlock *lock);
-	void (*spin_lock_flags)(struct raw_spinlock *lock, unsigned long flags);
-	int (*spin_trylock)(struct raw_spinlock *lock);
-	void (*spin_unlock)(struct raw_spinlock *lock);
-};
-
-/* This contains all the paravirt structures: we get a convenient
- * number for each function using the offset which we use to indicate
- * what to patch. */
-struct paravirt_patch_template {
-	struct pv_init_ops pv_init_ops;
-	struct pv_time_ops pv_time_ops;
-	struct pv_cpu_ops pv_cpu_ops;
-	struct pv_irq_ops pv_irq_ops;
-	struct pv_apic_ops pv_apic_ops;
-	struct pv_mmu_ops pv_mmu_ops;
-	struct pv_lock_ops pv_lock_ops;
-};
-
-extern struct pv_info pv_info;
-extern struct pv_init_ops pv_init_ops;
-extern struct pv_time_ops pv_time_ops;
-extern struct pv_cpu_ops pv_cpu_ops;
-extern struct pv_irq_ops pv_irq_ops;
-extern struct pv_apic_ops pv_apic_ops;
-extern struct pv_mmu_ops pv_mmu_ops;
-extern struct pv_lock_ops pv_lock_ops;
-
-#define PARAVIRT_PATCH(x)					\
-	(offsetof(struct paravirt_patch_template, x) / sizeof(void *))
-
-#define paravirt_type(op)				\
-	[paravirt_typenum] "i" (PARAVIRT_PATCH(op)),	\
-	[paravirt_opptr] "m" (op)
-#define paravirt_clobber(clobber)		\
-	[paravirt_clobber] "i" (clobber)
-
-/*
- * Generate some code, and mark it as patchable by the
- * apply_paravirt() alternate instruction patcher.
- */
-#define _paravirt_alt(insn_string, type, clobber)	\
-	"771:\n\t" insn_string "\n" "772:\n"		\
-	".pushsection .parainstructions,\"a\"\n"	\
-	_ASM_ALIGN "\n"					\
-	_ASM_PTR " 771b\n"				\
-	"  .byte " type "\n"				\
-	"  .byte 772b-771b\n"				\
-	"  .short " clobber "\n"			\
-	".popsection\n"
-
-/* Generate patchable code, with the default asm parameters. */
-#define paravirt_alt(insn_string)					\
-	_paravirt_alt(insn_string, "%c[paravirt_typenum]", "%c[paravirt_clobber]")
-
-/* Simple instruction patching code. */
-#define DEF_NATIVE(ops, name, code) 					\
-	extern const char start_##ops##_##name[], end_##ops##_##name[];	\
-	asm("start_" #ops "_" #name ": " code "; end_" #ops "_" #name ":")
-
-unsigned paravirt_patch_nop(void);
-unsigned paravirt_patch_ignore(unsigned len);
-unsigned paravirt_patch_call(void *insnbuf,
-			     const void *target, u16 tgt_clobbers,
-			     unsigned long addr, u16 site_clobbers,
-			     unsigned len);
-unsigned paravirt_patch_jmp(void *insnbuf, const void *target,
-			    unsigned long addr, unsigned len);
-unsigned paravirt_patch_default(u8 type, u16 clobbers, void *insnbuf,
-				unsigned long addr, unsigned len);
-
-unsigned paravirt_patch_insns(void *insnbuf, unsigned len,
-			      const char *start, const char *end);
-
-unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
-		      unsigned long addr, unsigned len);
-
-int paravirt_disable_iospace(void);
-
-/*
- * This generates an indirect call based on the operation type number.
- * The type number, computed in PARAVIRT_PATCH, is derived from the
- * offset into the paravirt_patch_template structure, and can therefore be
- * freely converted back into a structure offset.
- */
-#define PARAVIRT_CALL	"call *%[paravirt_opptr];"
-
-/*
- * These macros are intended to wrap calls through one of the paravirt
- * ops structs, so that they can be later identified and patched at
- * runtime.
- *
- * Normally, a call to a pv_op function is a simple indirect call:
- * (pv_op_struct.operations)(args...).
- *
- * Unfortunately, this is a relatively slow operation for modern CPUs,
- * because it cannot necessarily determine what the destination
- * address is.  In this case, the address is a runtime constant, so at
- * the very least we can patch the call to e a simple direct call, or
- * ideally, patch an inline implementation into the callsite.  (Direct
- * calls are essentially free, because the call and return addresses
- * are completely predictable.)
- *
- * For i386, these macros rely on the standard gcc "regparm(3)" calling
- * convention, in which the first three arguments are placed in %eax,
- * %edx, %ecx (in that order), and the remaining arguments are placed
- * on the stack.  All caller-save registers (eax,edx,ecx) are expected
- * to be modified (either clobbered or used for return values).
- * X86_64, on the other hand, already specifies a register-based calling
- * conventions, returning at %rax, with parameteres going on %rdi, %rsi,
- * %rdx, and %rcx. Note that for this reason, x86_64 does not need any
- * special handling for dealing with 4 arguments, unlike i386.
- * However, x86_64 also have to clobber all caller saved registers, which
- * unfortunately, are quite a bit (r8 - r11)
- *
- * The call instruction itself is marked by placing its start address
- * and size into the .parainstructions section, so that
- * apply_paravirt() in arch/i386/kernel/alternative.c can do the
- * appropriate patching under the control of the backend pv_init_ops
- * implementation.
- *
- * Unfortunately there's no way to get gcc to generate the args setup
- * for the call, and then allow the call itself to be generated by an
- * inline asm.  Because of this, we must do the complete arg setup and
- * return value handling from within these macros.  This is fairly
- * cumbersome.
- *
- * There are 5 sets of PVOP_* macros for dealing with 0-4 arguments.
- * It could be extended to more arguments, but there would be little
- * to be gained from that.  For each number of arguments, there are
- * the two VCALL and CALL variants for void and non-void functions.
- *
- * When there is a return value, the invoker of the macro must specify
- * the return type.  The macro then uses sizeof() on that type to
- * determine whether its a 32 or 64 bit value, and places the return
- * in the right register(s) (just %eax for 32-bit, and %edx:%eax for
- * 64-bit). For x86_64 machines, it just returns at %rax regardless of
- * the return value size.
- *
- * 64-bit arguments are passed as a pair of adjacent 32-bit arguments
- * i386 also passes 64-bit arguments as a pair of adjacent 32-bit arguments
- * in low,high order
- *
- * Small structures are passed and returned in registers.  The macro
- * calling convention can't directly deal with this, so the wrapper
- * functions must do this.
- *
- * These PVOP_* macros are only defined within this header.  This
- * means that all uses must be wrapped in inline functions.  This also
- * makes sure the incoming and outgoing types are always correct.
- */
-#ifdef CONFIG_X86_32
-#define PVOP_VCALL_ARGS			unsigned long __eax, __edx, __ecx
-#define PVOP_CALL_ARGS			PVOP_VCALL_ARGS
-#define PVOP_VCALL_CLOBBERS		"=a" (__eax), "=d" (__edx),	\
-					"=c" (__ecx)
-#define PVOP_CALL_CLOBBERS		PVOP_VCALL_CLOBBERS
-#define EXTRA_CLOBBERS
-#define VEXTRA_CLOBBERS
-#else
-#define PVOP_VCALL_ARGS		unsigned long __edi, __esi, __edx, __ecx
-#define PVOP_CALL_ARGS		PVOP_VCALL_ARGS, __eax
-#define PVOP_VCALL_CLOBBERS	"=D" (__edi),				\
-				"=S" (__esi), "=d" (__edx),		\
-				"=c" (__ecx)
-
-#define PVOP_CALL_CLOBBERS	PVOP_VCALL_CLOBBERS, "=a" (__eax)
-
-#define EXTRA_CLOBBERS	 , "r8", "r9", "r10", "r11"
-#define VEXTRA_CLOBBERS	 , "rax", "r8", "r9", "r10", "r11"
-#endif
-
-#ifdef CONFIG_PARAVIRT_DEBUG
-#define PVOP_TEST_NULL(op)	BUG_ON(op == NULL)
-#else
-#define PVOP_TEST_NULL(op)	((void)op)
-#endif
-
-#define __PVOP_CALL(rettype, op, pre, post, ...)			\
-	({								\
-		rettype __ret;						\
-		PVOP_CALL_ARGS;					\
-		PVOP_TEST_NULL(op);					\
-		/* This is 32-bit specific, but is okay in 64-bit */	\
-		/* since this condition will never hold */		\
-		if (sizeof(rettype) > sizeof(unsigned long)) {		\
-			asm volatile(pre				\
-				     paravirt_alt(PARAVIRT_CALL)	\
-				     post				\
-				     : PVOP_CALL_CLOBBERS		\
-				     : paravirt_type(op),		\
-				       paravirt_clobber(CLBR_ANY),	\
-				       ##__VA_ARGS__			\
-				     : "memory", "cc" EXTRA_CLOBBERS);	\
-			__ret = (rettype)((((u64)__edx) << 32) | __eax); \
-		} else {						\
-			asm volatile(pre				\
-				     paravirt_alt(PARAVIRT_CALL)	\
-				     post				\
-				     : PVOP_CALL_CLOBBERS		\
-				     : paravirt_type(op),		\
-				       paravirt_clobber(CLBR_ANY),	\
-				       ##__VA_ARGS__			\
-				     : "memory", "cc" EXTRA_CLOBBERS);	\
-			__ret = (rettype)__eax;				\
-		}							\
-		__ret;							\
-	})
-#define __PVOP_VCALL(op, pre, post, ...)				\
-	({								\
-		PVOP_VCALL_ARGS;					\
-		PVOP_TEST_NULL(op);					\
-		asm volatile(pre					\
-			     paravirt_alt(PARAVIRT_CALL)		\
-			     post					\
-			     : PVOP_VCALL_CLOBBERS			\
-			     : paravirt_type(op),			\
-			       paravirt_clobber(CLBR_ANY),		\
-			       ##__VA_ARGS__				\
-			     : "memory", "cc" VEXTRA_CLOBBERS);		\
-	})
-
-#define PVOP_CALL0(rettype, op)						\
-	__PVOP_CALL(rettype, op, "", "")
-#define PVOP_VCALL0(op)							\
-	__PVOP_VCALL(op, "", "")
-
-#define PVOP_CALL1(rettype, op, arg1)					\
-	__PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)))
-#define PVOP_VCALL1(op, arg1)						\
-	__PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)))
-
-#define PVOP_CALL2(rettype, op, arg1, arg2)				\
-	__PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), 	\
-	"1" ((unsigned long)(arg2)))
-#define PVOP_VCALL2(op, arg1, arg2)					\
-	__PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), 		\
-	"1" ((unsigned long)(arg2)))
-
-#define PVOP_CALL3(rettype, op, arg1, arg2, arg3)			\
-	__PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)),	\
-	"1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)))
-#define PVOP_VCALL3(op, arg1, arg2, arg3)				\
-	__PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)),		\
-	"1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)))
-
-/* This is the only difference in x86_64. We can make it much simpler */
-#ifdef CONFIG_X86_32
-#define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4)			\
-	__PVOP_CALL(rettype, op,					\
-		    "push %[_arg4];", "lea 4(%%esp),%%esp;",		\
-		    "0" ((u32)(arg1)), "1" ((u32)(arg2)),		\
-		    "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
-#define PVOP_VCALL4(op, arg1, arg2, arg3, arg4)				\
-	__PVOP_VCALL(op,						\
-		    "push %[_arg4];", "lea 4(%%esp),%%esp;",		\
-		    "0" ((u32)(arg1)), "1" ((u32)(arg2)),		\
-		    "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
-#else
-#define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4)			\
-	__PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)),	\
-	"1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)),		\
-	"3"((unsigned long)(arg4)))
-#define PVOP_VCALL4(op, arg1, arg2, arg3, arg4)				\
-	__PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)),		\
-	"1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)),		\
-	"3"((unsigned long)(arg4)))
-#endif
-
-static inline int paravirt_enabled(void)
-{
-	return pv_info.paravirt_enabled;
-}
-
-static inline void load_sp0(struct tss_struct *tss,
-			     struct thread_struct *thread)
-{
-	PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread);
-}
-
-#define ARCH_SETUP			pv_init_ops.arch_setup();
-static inline unsigned long get_wallclock(void)
-{
-	return PVOP_CALL0(unsigned long, pv_time_ops.get_wallclock);
-}
-
-static inline int set_wallclock(unsigned long nowtime)
-{
-	return PVOP_CALL1(int, pv_time_ops.set_wallclock, nowtime);
-}
-
-static inline void (*choose_time_init(void))(void)
-{
-	return pv_time_ops.time_init;
-}
-
-/* The paravirtualized CPUID instruction. */
-static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
-			   unsigned int *ecx, unsigned int *edx)
-{
-	PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx);
-}
-
-/*
- * These special macros can be used to get or set a debugging register
- */
-static inline unsigned long paravirt_get_debugreg(int reg)
-{
-	return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg);
-}
-#define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
-static inline void set_debugreg(unsigned long val, int reg)
-{
-	PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val);
-}
-
-static inline void clts(void)
-{
-	PVOP_VCALL0(pv_cpu_ops.clts);
-}
-
-static inline unsigned long read_cr0(void)
-{
-	return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0);
-}
-
-static inline void write_cr0(unsigned long x)
-{
-	PVOP_VCALL1(pv_cpu_ops.write_cr0, x);
-}
-
-static inline unsigned long read_cr2(void)
-{
-	return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2);
-}
-
-static inline void write_cr2(unsigned long x)
-{
-	PVOP_VCALL1(pv_mmu_ops.write_cr2, x);
-}
-
-static inline unsigned long read_cr3(void)
-{
-	return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3);
-}
-
-static inline void write_cr3(unsigned long x)
-{
-	PVOP_VCALL1(pv_mmu_ops.write_cr3, x);
-}
-
-static inline unsigned long read_cr4(void)
-{
-	return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4);
-}
-static inline unsigned long read_cr4_safe(void)
-{
-	return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe);
-}
-
-static inline void write_cr4(unsigned long x)
-{
-	PVOP_VCALL1(pv_cpu_ops.write_cr4, x);
-}
-
-#ifdef CONFIG_X86_64
-static inline unsigned long read_cr8(void)
-{
-	return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8);
-}
-
-static inline void write_cr8(unsigned long x)
-{
-	PVOP_VCALL1(pv_cpu_ops.write_cr8, x);
-}
-#endif
-
-static inline void raw_safe_halt(void)
-{
-	PVOP_VCALL0(pv_irq_ops.safe_halt);
-}
-
-static inline void halt(void)
-{
-	PVOP_VCALL0(pv_irq_ops.safe_halt);
-}
-
-static inline void wbinvd(void)
-{
-	PVOP_VCALL0(pv_cpu_ops.wbinvd);
-}
-
-#define get_kernel_rpl()  (pv_info.kernel_rpl)
-
-static inline u64 paravirt_read_msr(unsigned msr, int *err)
-{
-	return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err);
-}
-static inline u64 paravirt_read_msr_amd(unsigned msr, int *err)
-{
-	return PVOP_CALL2(u64, pv_cpu_ops.read_msr_amd, msr, err);
-}
-static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
-{
-	return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high);
-}
-
-/* These should all do BUG_ON(_err), but our headers are too tangled. */
-#define rdmsr(msr, val1, val2)			\
-do {						\
-	int _err;				\
-	u64 _l = paravirt_read_msr(msr, &_err);	\
-	val1 = (u32)_l;				\
-	val2 = _l >> 32;			\
-} while (0)
-
-#define wrmsr(msr, val1, val2)			\
-do {						\
-	paravirt_write_msr(msr, val1, val2);	\
-} while (0)
-
-#define rdmsrl(msr, val)			\
-do {						\
-	int _err;				\
-	val = paravirt_read_msr(msr, &_err);	\
-} while (0)
-
-#define wrmsrl(msr, val)	wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32)
-#define wrmsr_safe(msr, a, b)	paravirt_write_msr(msr, a, b)
-
-/* rdmsr with exception handling */
-#define rdmsr_safe(msr, a, b)			\
-({						\
-	int _err;				\
-	u64 _l = paravirt_read_msr(msr, &_err);	\
-	(*a) = (u32)_l;				\
-	(*b) = _l >> 32;			\
-	_err;					\
-})
-
-static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
-{
-	int err;
-
-	*p = paravirt_read_msr(msr, &err);
-	return err;
-}
-static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
-{
-	int err;
-
-	*p = paravirt_read_msr_amd(msr, &err);
-	return err;
-}
-
-static inline u64 paravirt_read_tsc(void)
-{
-	return PVOP_CALL0(u64, pv_cpu_ops.read_tsc);
-}
-
-#define rdtscl(low)				\
-do {						\
-	u64 _l = paravirt_read_tsc();		\
-	low = (int)_l;				\
-} while (0)
-
-#define rdtscll(val) (val = paravirt_read_tsc())
-
-static inline unsigned long long paravirt_sched_clock(void)
-{
-	return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock);
-}
-#define calibrate_tsc() (pv_time_ops.get_tsc_khz())
-
-static inline unsigned long long paravirt_read_pmc(int counter)
-{
-	return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter);
-}
-
-#define rdpmc(counter, low, high)		\
-do {						\
-	u64 _l = paravirt_read_pmc(counter);	\
-	low = (u32)_l;				\
-	high = _l >> 32;			\
-} while (0)
-
-static inline unsigned long long paravirt_rdtscp(unsigned int *aux)
-{
-	return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux);
-}
-
-#define rdtscp(low, high, aux)				\
-do {							\
-	int __aux;					\
-	unsigned long __val = paravirt_rdtscp(&__aux);	\
-	(low) = (u32)__val;				\
-	(high) = (u32)(__val >> 32);			\
-	(aux) = __aux;					\
-} while (0)
-
-#define rdtscpll(val, aux)				\
-do {							\
-	unsigned long __aux; 				\
-	val = paravirt_rdtscp(&__aux);			\
-	(aux) = __aux;					\
-} while (0)
-
-static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
-{
-	PVOP_VCALL2(pv_cpu_ops.alloc_ldt, ldt, entries);
-}
-
-static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
-{
-	PVOP_VCALL2(pv_cpu_ops.free_ldt, ldt, entries);
-}
-
-static inline void load_TR_desc(void)
-{
-	PVOP_VCALL0(pv_cpu_ops.load_tr_desc);
-}
-static inline void load_gdt(const struct desc_ptr *dtr)
-{
-	PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr);
-}
-static inline void load_idt(const struct desc_ptr *dtr)
-{
-	PVOP_VCALL1(pv_cpu_ops.load_idt, dtr);
-}
-static inline void set_ldt(const void *addr, unsigned entries)
-{
-	PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries);
-}
-static inline void store_gdt(struct desc_ptr *dtr)
-{
-	PVOP_VCALL1(pv_cpu_ops.store_gdt, dtr);
-}
-static inline void store_idt(struct desc_ptr *dtr)
-{
-	PVOP_VCALL1(pv_cpu_ops.store_idt, dtr);
-}
-static inline unsigned long paravirt_store_tr(void)
-{
-	return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr);
-}
-#define store_tr(tr)	((tr) = paravirt_store_tr())
-static inline void load_TLS(struct thread_struct *t, unsigned cpu)
-{
-	PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu);
-}
-
-#ifdef CONFIG_X86_64
-static inline void load_gs_index(unsigned int gs)
-{
-	PVOP_VCALL1(pv_cpu_ops.load_gs_index, gs);
-}
-#endif
-
-static inline void write_ldt_entry(struct desc_struct *dt, int entry,
-				   const void *desc)
-{
-	PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc);
-}
-
-static inline void write_gdt_entry(struct desc_struct *dt, int entry,
-				   void *desc, int type)
-{
-	PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type);
-}
-
-static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g)
-{
-	PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g);
-}
-static inline void set_iopl_mask(unsigned mask)
-{
-	PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask);
-}
-
-/* The paravirtualized I/O functions */
-static inline void slow_down_io(void)
-{
-	pv_cpu_ops.io_delay();
-#ifdef REALLY_SLOW_IO
-	pv_cpu_ops.io_delay();
-	pv_cpu_ops.io_delay();
-	pv_cpu_ops.io_delay();
-#endif
-}
-
-#ifdef CONFIG_X86_LOCAL_APIC
-static inline void setup_boot_clock(void)
-{
-	PVOP_VCALL0(pv_apic_ops.setup_boot_clock);
-}
-
-static inline void setup_secondary_clock(void)
-{
-	PVOP_VCALL0(pv_apic_ops.setup_secondary_clock);
-}
-#endif
-
-static inline void paravirt_post_allocator_init(void)
-{
-	if (pv_init_ops.post_allocator_init)
-		(*pv_init_ops.post_allocator_init)();
-}
-
-static inline void paravirt_pagetable_setup_start(pgd_t *base)
-{
-	(*pv_mmu_ops.pagetable_setup_start)(base);
-}
-
-static inline void paravirt_pagetable_setup_done(pgd_t *base)
-{
-	(*pv_mmu_ops.pagetable_setup_done)(base);
-}
-
-#ifdef CONFIG_SMP
-static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip,
-				    unsigned long start_esp)
-{
-	PVOP_VCALL3(pv_apic_ops.startup_ipi_hook,
-		    phys_apicid, start_eip, start_esp);
-}
-#endif
-
-static inline void paravirt_activate_mm(struct mm_struct *prev,
-					struct mm_struct *next)
-{
-	PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next);
-}
-
-static inline void arch_dup_mmap(struct mm_struct *oldmm,
-				 struct mm_struct *mm)
-{
-	PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm);
-}
-
-static inline void arch_exit_mmap(struct mm_struct *mm)
-{
-	PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm);
-}
-
-static inline void __flush_tlb(void)
-{
-	PVOP_VCALL0(pv_mmu_ops.flush_tlb_user);
-}
-static inline void __flush_tlb_global(void)
-{
-	PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel);
-}
-static inline void __flush_tlb_single(unsigned long addr)
-{
-	PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr);
-}
-
-static inline void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
-				    unsigned long va)
-{
-	PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, &cpumask, mm, va);
-}
-
-static inline int paravirt_pgd_alloc(struct mm_struct *mm)
-{
-	return PVOP_CALL1(int, pv_mmu_ops.pgd_alloc, mm);
-}
-
-static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
-	PVOP_VCALL2(pv_mmu_ops.pgd_free, mm, pgd);
-}
-
-static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn)
-{
-	PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn);
-}
-static inline void paravirt_release_pte(unsigned long pfn)
-{
-	PVOP_VCALL1(pv_mmu_ops.release_pte, pfn);
-}
-
-static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn)
-{
-	PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn);
-}
-
-static inline void paravirt_alloc_pmd_clone(unsigned long pfn, unsigned long clonepfn,
-					    unsigned long start, unsigned long count)
-{
-	PVOP_VCALL4(pv_mmu_ops.alloc_pmd_clone, pfn, clonepfn, start, count);
-}
-static inline void paravirt_release_pmd(unsigned long pfn)
-{
-	PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn);
-}
-
-static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn)
-{
-	PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn);
-}
-static inline void paravirt_release_pud(unsigned long pfn)
-{
-	PVOP_VCALL1(pv_mmu_ops.release_pud, pfn);
-}
-
-#ifdef CONFIG_HIGHPTE
-static inline void *kmap_atomic_pte(struct page *page, enum km_type type)
-{
-	unsigned long ret;
-	ret = PVOP_CALL2(unsigned long, pv_mmu_ops.kmap_atomic_pte, page, type);
-	return (void *)ret;
-}
-#endif
-
-static inline void pte_update(struct mm_struct *mm, unsigned long addr,
-			      pte_t *ptep)
-{
-	PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep);
-}
-
-static inline void pte_update_defer(struct mm_struct *mm, unsigned long addr,
-				    pte_t *ptep)
-{
-	PVOP_VCALL3(pv_mmu_ops.pte_update_defer, mm, addr, ptep);
-}
-
-static inline pte_t __pte(pteval_t val)
-{
-	pteval_t ret;
-
-	if (sizeof(pteval_t) > sizeof(long))
-		ret = PVOP_CALL2(pteval_t,
-				 pv_mmu_ops.make_pte,
-				 val, (u64)val >> 32);
-	else
-		ret = PVOP_CALL1(pteval_t,
-				 pv_mmu_ops.make_pte,
-				 val);
-
-	return (pte_t) { .pte = ret };
-}
-
-static inline pteval_t pte_val(pte_t pte)
-{
-	pteval_t ret;
-
-	if (sizeof(pteval_t) > sizeof(long))
-		ret = PVOP_CALL2(pteval_t, pv_mmu_ops.pte_val,
-				 pte.pte, (u64)pte.pte >> 32);
-	else
-		ret = PVOP_CALL1(pteval_t, pv_mmu_ops.pte_val,
-				 pte.pte);
-
-	return ret;
-}
-
-static inline pteval_t pte_flags(pte_t pte)
-{
-	pteval_t ret;
-
-	if (sizeof(pteval_t) > sizeof(long))
-		ret = PVOP_CALL2(pteval_t, pv_mmu_ops.pte_flags,
-				 pte.pte, (u64)pte.pte >> 32);
-	else
-		ret = PVOP_CALL1(pteval_t, pv_mmu_ops.pte_flags,
-				 pte.pte);
-
-#ifdef CONFIG_PARAVIRT_DEBUG
-	BUG_ON(ret & PTE_PFN_MASK);
-#endif
-	return ret;
-}
-
-static inline pgd_t __pgd(pgdval_t val)
-{
-	pgdval_t ret;
-
-	if (sizeof(pgdval_t) > sizeof(long))
-		ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.make_pgd,
-				 val, (u64)val >> 32);
-	else
-		ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.make_pgd,
-				 val);
-
-	return (pgd_t) { ret };
-}
-
-static inline pgdval_t pgd_val(pgd_t pgd)
-{
-	pgdval_t ret;
-
-	if (sizeof(pgdval_t) > sizeof(long))
-		ret =  PVOP_CALL2(pgdval_t, pv_mmu_ops.pgd_val,
-				  pgd.pgd, (u64)pgd.pgd >> 32);
-	else
-		ret =  PVOP_CALL1(pgdval_t, pv_mmu_ops.pgd_val,
-				  pgd.pgd);
-
-	return ret;
-}
-
-#define  __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
-static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr,
-					   pte_t *ptep)
-{
-	pteval_t ret;
-
-	ret = PVOP_CALL3(pteval_t, pv_mmu_ops.ptep_modify_prot_start,
-			 mm, addr, ptep);
-
-	return (pte_t) { .pte = ret };
-}
-
-static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
-					   pte_t *ptep, pte_t pte)
-{
-	if (sizeof(pteval_t) > sizeof(long))
-		/* 5 arg words */
-		pv_mmu_ops.ptep_modify_prot_commit(mm, addr, ptep, pte);
-	else
-		PVOP_VCALL4(pv_mmu_ops.ptep_modify_prot_commit,
-			    mm, addr, ptep, pte.pte);
-}
-
-static inline void set_pte(pte_t *ptep, pte_t pte)
-{
-	if (sizeof(pteval_t) > sizeof(long))
-		PVOP_VCALL3(pv_mmu_ops.set_pte, ptep,
-			    pte.pte, (u64)pte.pte >> 32);
-	else
-		PVOP_VCALL2(pv_mmu_ops.set_pte, ptep,
-			    pte.pte);
-}
-
-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
-			      pte_t *ptep, pte_t pte)
-{
-	if (sizeof(pteval_t) > sizeof(long))
-		/* 5 arg words */
-		pv_mmu_ops.set_pte_at(mm, addr, ptep, pte);
-	else
-		PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte);
-}
-
-static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
-{
-	pmdval_t val = native_pmd_val(pmd);
-
-	if (sizeof(pmdval_t) > sizeof(long))
-		PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32);
-	else
-		PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val);
-}
-
-#if PAGETABLE_LEVELS >= 3
-static inline pmd_t __pmd(pmdval_t val)
-{
-	pmdval_t ret;
-
-	if (sizeof(pmdval_t) > sizeof(long))
-		ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.make_pmd,
-				 val, (u64)val >> 32);
-	else
-		ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.make_pmd,
-				 val);
-
-	return (pmd_t) { ret };
-}
-
-static inline pmdval_t pmd_val(pmd_t pmd)
-{
-	pmdval_t ret;
-
-	if (sizeof(pmdval_t) > sizeof(long))
-		ret =  PVOP_CALL2(pmdval_t, pv_mmu_ops.pmd_val,
-				  pmd.pmd, (u64)pmd.pmd >> 32);
-	else
-		ret =  PVOP_CALL1(pmdval_t, pv_mmu_ops.pmd_val,
-				  pmd.pmd);
-
-	return ret;
-}
-
-static inline void set_pud(pud_t *pudp, pud_t pud)
-{
-	pudval_t val = native_pud_val(pud);
-
-	if (sizeof(pudval_t) > sizeof(long))
-		PVOP_VCALL3(pv_mmu_ops.set_pud, pudp,
-			    val, (u64)val >> 32);
-	else
-		PVOP_VCALL2(pv_mmu_ops.set_pud, pudp,
-			    val);
-}
-#if PAGETABLE_LEVELS == 4
-static inline pud_t __pud(pudval_t val)
-{
-	pudval_t ret;
-
-	if (sizeof(pudval_t) > sizeof(long))
-		ret = PVOP_CALL2(pudval_t, pv_mmu_ops.make_pud,
-				 val, (u64)val >> 32);
-	else
-		ret = PVOP_CALL1(pudval_t, pv_mmu_ops.make_pud,
-				 val);
-
-	return (pud_t) { ret };
-}
-
-static inline pudval_t pud_val(pud_t pud)
-{
-	pudval_t ret;
-
-	if (sizeof(pudval_t) > sizeof(long))
-		ret =  PVOP_CALL2(pudval_t, pv_mmu_ops.pud_val,
-				  pud.pud, (u64)pud.pud >> 32);
-	else
-		ret =  PVOP_CALL1(pudval_t, pv_mmu_ops.pud_val,
-				  pud.pud);
-
-	return ret;
-}
-
-static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
-{
-	pgdval_t val = native_pgd_val(pgd);
-
-	if (sizeof(pgdval_t) > sizeof(long))
-		PVOP_VCALL3(pv_mmu_ops.set_pgd, pgdp,
-			    val, (u64)val >> 32);
-	else
-		PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp,
-			    val);
-}
-
-static inline void pgd_clear(pgd_t *pgdp)
-{
-	set_pgd(pgdp, __pgd(0));
-}
-
-static inline void pud_clear(pud_t *pudp)
-{
-	set_pud(pudp, __pud(0));
-}
-
-#endif	/* PAGETABLE_LEVELS == 4 */
-
-#endif	/* PAGETABLE_LEVELS >= 3 */
-
-#ifdef CONFIG_X86_PAE
-/* Special-case pte-setting operations for PAE, which can't update a
-   64-bit pte atomically */
-static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
-{
-	PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep,
-		    pte.pte, pte.pte >> 32);
-}
-
-static inline void set_pte_present(struct mm_struct *mm, unsigned long addr,
-				   pte_t *ptep, pte_t pte)
-{
-	/* 5 arg words */
-	pv_mmu_ops.set_pte_present(mm, addr, ptep, pte);
-}
-
-static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
-			     pte_t *ptep)
-{
-	PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep);
-}
-
-static inline void pmd_clear(pmd_t *pmdp)
-{
-	PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp);
-}
-#else  /* !CONFIG_X86_PAE */
-static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
-{
-	set_pte(ptep, pte);
-}
-
-static inline void set_pte_present(struct mm_struct *mm, unsigned long addr,
-				   pte_t *ptep, pte_t pte)
-{
-	set_pte(ptep, pte);
-}
-
-static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
-			     pte_t *ptep)
-{
-	set_pte_at(mm, addr, ptep, __pte(0));
-}
-
-static inline void pmd_clear(pmd_t *pmdp)
-{
-	set_pmd(pmdp, __pmd(0));
-}
-#endif	/* CONFIG_X86_PAE */
-
-/* Lazy mode for batching updates / context switch */
-enum paravirt_lazy_mode {
-	PARAVIRT_LAZY_NONE,
-	PARAVIRT_LAZY_MMU,
-	PARAVIRT_LAZY_CPU,
-};
-
-enum paravirt_lazy_mode paravirt_get_lazy_mode(void);
-void paravirt_enter_lazy_cpu(void);
-void paravirt_leave_lazy_cpu(void);
-void paravirt_enter_lazy_mmu(void);
-void paravirt_leave_lazy_mmu(void);
-void paravirt_leave_lazy(enum paravirt_lazy_mode mode);
-
-#define  __HAVE_ARCH_ENTER_LAZY_CPU_MODE
-static inline void arch_enter_lazy_cpu_mode(void)
-{
-	PVOP_VCALL0(pv_cpu_ops.lazy_mode.enter);
-}
-
-static inline void arch_leave_lazy_cpu_mode(void)
-{
-	PVOP_VCALL0(pv_cpu_ops.lazy_mode.leave);
-}
-
-static inline void arch_flush_lazy_cpu_mode(void)
-{
-	if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU)) {
-		arch_leave_lazy_cpu_mode();
-		arch_enter_lazy_cpu_mode();
-	}
-}
-
-
-#define  __HAVE_ARCH_ENTER_LAZY_MMU_MODE
-static inline void arch_enter_lazy_mmu_mode(void)
-{
-	PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter);
-}
-
-static inline void arch_leave_lazy_mmu_mode(void)
-{
-	PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave);
-}
-
-static inline void arch_flush_lazy_mmu_mode(void)
-{
-	if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU)) {
-		arch_leave_lazy_mmu_mode();
-		arch_enter_lazy_mmu_mode();
-	}
-}
-
-static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx,
-				unsigned long phys, pgprot_t flags)
-{
-	pv_mmu_ops.set_fixmap(idx, phys, flags);
-}
-
-void _paravirt_nop(void);
-#define paravirt_nop	((void *)_paravirt_nop)
-
-void paravirt_use_bytelocks(void);
-
-#ifdef CONFIG_SMP
-
-static inline int __raw_spin_is_locked(struct raw_spinlock *lock)
-{
-	return PVOP_CALL1(int, pv_lock_ops.spin_is_locked, lock);
-}
-
-static inline int __raw_spin_is_contended(struct raw_spinlock *lock)
-{
-	return PVOP_CALL1(int, pv_lock_ops.spin_is_contended, lock);
-}
-
-static __always_inline void __raw_spin_lock(struct raw_spinlock *lock)
-{
-	PVOP_VCALL1(pv_lock_ops.spin_lock, lock);
-}
-
-static __always_inline void __raw_spin_lock_flags(struct raw_spinlock *lock,
-						  unsigned long flags)
-{
-	PVOP_VCALL2(pv_lock_ops.spin_lock_flags, lock, flags);
-}
-
-static __always_inline int __raw_spin_trylock(struct raw_spinlock *lock)
-{
-	return PVOP_CALL1(int, pv_lock_ops.spin_trylock, lock);
-}
-
-static __always_inline void __raw_spin_unlock(struct raw_spinlock *lock)
-{
-	PVOP_VCALL1(pv_lock_ops.spin_unlock, lock);
-}
-
-#endif
-
-/* These all sit in the .parainstructions section to tell us what to patch. */
-struct paravirt_patch_site {
-	u8 *instr; 		/* original instructions */
-	u8 instrtype;		/* type of this instruction */
-	u8 len;			/* length of original instruction */
-	u16 clobbers;		/* what registers you may clobber */
-};
-
-extern struct paravirt_patch_site __parainstructions[],
-	__parainstructions_end[];
-
-#ifdef CONFIG_X86_32
-#define PV_SAVE_REGS "pushl %%ecx; pushl %%edx;"
-#define PV_RESTORE_REGS "popl %%edx; popl %%ecx"
-#define PV_FLAGS_ARG "0"
-#define PV_EXTRA_CLOBBERS
-#define PV_VEXTRA_CLOBBERS
-#else
-/* We save some registers, but all of them, that's too much. We clobber all
- * caller saved registers but the argument parameter */
-#define PV_SAVE_REGS "pushq %%rdi;"
-#define PV_RESTORE_REGS "popq %%rdi;"
-#define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx", "rsi"
-#define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx", "rsi"
-#define PV_FLAGS_ARG "D"
-#endif
-
-static inline unsigned long __raw_local_save_flags(void)
-{
-	unsigned long f;
-
-	asm volatile(paravirt_alt(PV_SAVE_REGS
-				  PARAVIRT_CALL
-				  PV_RESTORE_REGS)
-		     : "=a"(f)
-		     : paravirt_type(pv_irq_ops.save_fl),
-		       paravirt_clobber(CLBR_EAX)
-		     : "memory", "cc" PV_VEXTRA_CLOBBERS);
-	return f;
-}
-
-static inline void raw_local_irq_restore(unsigned long f)
-{
-	asm volatile(paravirt_alt(PV_SAVE_REGS
-				  PARAVIRT_CALL
-				  PV_RESTORE_REGS)
-		     : "=a"(f)
-		     : PV_FLAGS_ARG(f),
-		       paravirt_type(pv_irq_ops.restore_fl),
-		       paravirt_clobber(CLBR_EAX)
-		     : "memory", "cc" PV_EXTRA_CLOBBERS);
-}
-
-static inline void raw_local_irq_disable(void)
-{
-	asm volatile(paravirt_alt(PV_SAVE_REGS
-				  PARAVIRT_CALL
-				  PV_RESTORE_REGS)
-		     :
-		     : paravirt_type(pv_irq_ops.irq_disable),
-		       paravirt_clobber(CLBR_EAX)
-		     : "memory", "eax", "cc" PV_EXTRA_CLOBBERS);
-}
-
-static inline void raw_local_irq_enable(void)
-{
-	asm volatile(paravirt_alt(PV_SAVE_REGS
-				  PARAVIRT_CALL
-				  PV_RESTORE_REGS)
-		     :
-		     : paravirt_type(pv_irq_ops.irq_enable),
-		       paravirt_clobber(CLBR_EAX)
-		     : "memory", "eax", "cc" PV_EXTRA_CLOBBERS);
-}
-
-static inline unsigned long __raw_local_irq_save(void)
-{
-	unsigned long f;
-
-	f = __raw_local_save_flags();
-	raw_local_irq_disable();
-	return f;
-}
-
-
-/* Make sure as little as possible of this mess escapes. */
-#undef PARAVIRT_CALL
-#undef __PVOP_CALL
-#undef __PVOP_VCALL
-#undef PVOP_VCALL0
-#undef PVOP_CALL0
-#undef PVOP_VCALL1
-#undef PVOP_CALL1
-#undef PVOP_VCALL2
-#undef PVOP_CALL2
-#undef PVOP_VCALL3
-#undef PVOP_CALL3
-#undef PVOP_VCALL4
-#undef PVOP_CALL4
-
-#else  /* __ASSEMBLY__ */
-
-#define _PVSITE(ptype, clobbers, ops, word, algn)	\
-771:;						\
-	ops;					\
-772:;						\
-	.pushsection .parainstructions,"a";	\
-	 .align	algn;				\
-	 word 771b;				\
-	 .byte ptype;				\
-	 .byte 772b-771b;			\
-	 .short clobbers;			\
-	.popsection
-
-
-#ifdef CONFIG_X86_64
-#define PV_SAVE_REGS				\
-	push %rax;				\
-	push %rcx;				\
-	push %rdx;				\
-	push %rsi;				\
-	push %rdi;				\
-	push %r8;				\
-	push %r9;				\
-	push %r10;				\
-	push %r11
-#define PV_RESTORE_REGS				\
-	pop %r11;				\
-	pop %r10;				\
-	pop %r9;				\
-	pop %r8;				\
-	pop %rdi;				\
-	pop %rsi;				\
-	pop %rdx;				\
-	pop %rcx;				\
-	pop %rax
-#define PARA_PATCH(struct, off)        ((PARAVIRT_PATCH_##struct + (off)) / 8)
-#define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8)
-#define PARA_INDIRECT(addr)	*addr(%rip)
-#else
-#define PV_SAVE_REGS   pushl %eax; pushl %edi; pushl %ecx; pushl %edx
-#define PV_RESTORE_REGS popl %edx; popl %ecx; popl %edi; popl %eax
-#define PARA_PATCH(struct, off)        ((PARAVIRT_PATCH_##struct + (off)) / 4)
-#define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4)
-#define PARA_INDIRECT(addr)	*%cs:addr
-#endif
-
-#define INTERRUPT_RETURN						\
-	PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE,	\
-		  jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret))
-
-#define DISABLE_INTERRUPTS(clobbers)					\
-	PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \
-		  PV_SAVE_REGS;						\
-		  call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_disable);	\
-		  PV_RESTORE_REGS;)			\
-
-#define ENABLE_INTERRUPTS(clobbers)					\
-	PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers,	\
-		  PV_SAVE_REGS;						\
-		  call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_enable);	\
-		  PV_RESTORE_REGS;)
-
-#define USERGS_SYSRET32							\
-	PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret32),	\
-		  CLBR_NONE,						\
-		  jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret32))
-
-#ifdef CONFIG_X86_32
-#define GET_CR0_INTO_EAX				\
-	push %ecx; push %edx;				\
-	call PARA_INDIRECT(pv_cpu_ops+PV_CPU_read_cr0);	\
-	pop %edx; pop %ecx
-
-#define ENABLE_INTERRUPTS_SYSEXIT					\
-	PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_sysexit),	\
-		  CLBR_NONE,						\
-		  jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_irq_enable_sysexit))
-
-
-#else	/* !CONFIG_X86_32 */
-
-/*
- * If swapgs is used while the userspace stack is still current,
- * there's no way to call a pvop.  The PV replacement *must* be
- * inlined, or the swapgs instruction must be trapped and emulated.
- */
-#define SWAPGS_UNSAFE_STACK						\
-	PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE,	\
-		  swapgs)
-
-#define SWAPGS								\
-	PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE,	\
-		  PV_SAVE_REGS;						\
-		  call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs);		\
-		  PV_RESTORE_REGS					\
-		 )
-
-#define GET_CR2_INTO_RCX				\
-	call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2);	\
-	movq %rax, %rcx;				\
-	xorq %rax, %rax;
-
-#define PARAVIRT_ADJUST_EXCEPTION_FRAME					\
-	PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_adjust_exception_frame), \
-		  CLBR_NONE,						\
-		  call PARA_INDIRECT(pv_irq_ops+PV_IRQ_adjust_exception_frame))
-
-#define USERGS_SYSRET64							\
-	PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret64),	\
-		  CLBR_NONE,						\
-		  jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64))
-
-#define ENABLE_INTERRUPTS_SYSEXIT32					\
-	PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_sysexit),	\
-		  CLBR_NONE,						\
-		  jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_irq_enable_sysexit))
-#endif	/* CONFIG_X86_32 */
-
-#endif /* __ASSEMBLY__ */
-#endif /* CONFIG_PARAVIRT */
-#endif /* ASM_X86__PARAVIRT_H */
diff --git a/include/asm-x86/parport.h b/include/asm-x86/parport.h
deleted file mode 100644
index 2e3dda4dc3d9..000000000000
--- a/include/asm-x86/parport.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef ASM_X86__PARPORT_H
-#define ASM_X86__PARPORT_H
-
-static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma);
-static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
-{
-	return parport_pc_find_isa_ports(autoirq, autodma);
-}
-
-#endif /* ASM_X86__PARPORT_H */
diff --git a/include/asm-x86/pat.h b/include/asm-x86/pat.h
deleted file mode 100644
index 482c3e3f9879..000000000000
--- a/include/asm-x86/pat.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef ASM_X86__PAT_H
-#define ASM_X86__PAT_H
-
-#include <linux/types.h>
-
-#ifdef CONFIG_X86_PAT
-extern int pat_enabled;
-extern void validate_pat_support(struct cpuinfo_x86 *c);
-#else
-static const int pat_enabled;
-static inline void validate_pat_support(struct cpuinfo_x86 *c) { }
-#endif
-
-extern void pat_init(void);
-
-extern int reserve_memtype(u64 start, u64 end,
-		unsigned long req_type, unsigned long *ret_type);
-extern int free_memtype(u64 start, u64 end);
-
-extern void pat_disable(char *reason);
-
-#endif /* ASM_X86__PAT_H */
diff --git a/include/asm-x86/pci-direct.h b/include/asm-x86/pci-direct.h
deleted file mode 100644
index da42be07b690..000000000000
--- a/include/asm-x86/pci-direct.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef ASM_X86__PCI_DIRECT_H
-#define ASM_X86__PCI_DIRECT_H
-
-#include <linux/types.h>
-
-/* Direct PCI access. This is used for PCI accesses in early boot before
-   the PCI subsystem works. */
-
-extern u32 read_pci_config(u8 bus, u8 slot, u8 func, u8 offset);
-extern u8 read_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset);
-extern u16 read_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset);
-extern void write_pci_config(u8 bus, u8 slot, u8 func, u8 offset, u32 val);
-extern void write_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset, u8 val);
-extern void write_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset, u16 val);
-
-extern int early_pci_allowed(void);
-
-extern unsigned int pci_early_dump_regs;
-extern void early_dump_pci_device(u8 bus, u8 slot, u8 func);
-extern void early_dump_pci_devices(void);
-#endif /* ASM_X86__PCI_DIRECT_H */
diff --git a/include/asm-x86/pci.h b/include/asm-x86/pci.h
deleted file mode 100644
index 602583192991..000000000000
--- a/include/asm-x86/pci.h
+++ /dev/null
@@ -1,114 +0,0 @@
-#ifndef ASM_X86__PCI_H
-#define ASM_X86__PCI_H
-
-#include <linux/mm.h> /* for struct page */
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <asm/scatterlist.h>
-#include <asm/io.h>
-
-#ifdef __KERNEL__
-
-struct pci_sysdata {
-	int		domain;		/* PCI domain */
-	int		node;		/* NUMA node */
-#ifdef CONFIG_X86_64
-	void		*iommu;		/* IOMMU private data */
-#endif
-};
-
-extern int pci_routeirq;
-
-/* scan a bus after allocating a pci_sysdata for it */
-extern struct pci_bus *pci_scan_bus_on_node(int busno, struct pci_ops *ops,
-					    int node);
-extern struct pci_bus *pci_scan_bus_with_sysdata(int busno);
-
-static inline int pci_domain_nr(struct pci_bus *bus)
-{
-	struct pci_sysdata *sd = bus->sysdata;
-	return sd->domain;
-}
-
-static inline int pci_proc_domain(struct pci_bus *bus)
-{
-	return pci_domain_nr(bus);
-}
-
-
-/* Can be used to override the logic in pci_scan_bus for skipping
-   already-configured bus numbers - to be used for buggy BIOSes
-   or architectures with incomplete PCI setup by the loader */
-
-#ifdef CONFIG_PCI
-extern unsigned int pcibios_assign_all_busses(void);
-#else
-#define pcibios_assign_all_busses()	0
-#endif
-#define pcibios_scan_all_fns(a, b)	0
-
-extern unsigned long pci_mem_start;
-#define PCIBIOS_MIN_IO		0x1000
-#define PCIBIOS_MIN_MEM		(pci_mem_start)
-
-#define PCIBIOS_MIN_CARDBUS_IO	0x4000
-
-void pcibios_config_init(void);
-struct pci_bus *pcibios_scan_root(int bus);
-
-void pcibios_set_master(struct pci_dev *dev);
-void pcibios_penalize_isa_irq(int irq, int active);
-struct irq_routing_table *pcibios_get_irq_routing_table(void);
-int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
-
-
-#define HAVE_PCI_MMAP
-extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
-			       enum pci_mmap_state mmap_state,
-			       int write_combine);
-
-
-#ifdef CONFIG_PCI
-extern void early_quirks(void);
-static inline void pci_dma_burst_advice(struct pci_dev *pdev,
-					enum pci_dma_burst_strategy *strat,
-					unsigned long *strategy_parameter)
-{
-	*strat = PCI_DMA_BURST_INFINITY;
-	*strategy_parameter = ~0UL;
-}
-#else
-static inline void early_quirks(void) { }
-#endif
-
-#endif  /* __KERNEL__ */
-
-#ifdef CONFIG_X86_32
-# include "pci_32.h"
-#else
-# include "pci_64.h"
-#endif
-
-/* implement the pci_ DMA API in terms of the generic device dma_ one */
-#include <asm-generic/pci-dma-compat.h>
-
-/* generic pci stuff */
-#include <asm-generic/pci.h>
-
-#ifdef CONFIG_NUMA
-/* Returns the node based on pci bus */
-static inline int __pcibus_to_node(struct pci_bus *bus)
-{
-	struct pci_sysdata *sd = bus->sysdata;
-
-	return sd->node;
-}
-
-static inline cpumask_t __pcibus_to_cpumask(struct pci_bus *bus)
-{
-	return node_to_cpumask(__pcibus_to_node(bus));
-}
-#endif
-
-#endif /* ASM_X86__PCI_H */
diff --git a/include/asm-x86/pci_32.h b/include/asm-x86/pci_32.h
deleted file mode 100644
index 3f2288207c0c..000000000000
--- a/include/asm-x86/pci_32.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef ASM_X86__PCI_32_H
-#define ASM_X86__PCI_32_H
-
-
-#ifdef __KERNEL__
-
-
-/* Dynamic DMA mapping stuff.
- * i386 has everything mapped statically.
- */
-
-struct pci_dev;
-
-/* The PCI address space does equal the physical memory
- * address space.  The networking and block device layers use
- * this boolean for bounce buffer decisions.
- */
-#define PCI_DMA_BUS_IS_PHYS	(1)
-
-/* pci_unmap_{page,single} is a nop so... */
-#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)	dma_addr_t ADDR_NAME[0];
-#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)	unsigned LEN_NAME[0];
-#define pci_unmap_addr(PTR, ADDR_NAME)	sizeof((PTR)->ADDR_NAME)
-#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
-	do { break; } while (pci_unmap_addr(PTR, ADDR_NAME))
-#define pci_unmap_len(PTR, LEN_NAME)		sizeof((PTR)->LEN_NAME)
-#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
-	do { break; } while (pci_unmap_len(PTR, LEN_NAME))
-
-
-#endif /* __KERNEL__ */
-
-
-#endif /* ASM_X86__PCI_32_H */
diff --git a/include/asm-x86/pci_64.h b/include/asm-x86/pci_64.h
deleted file mode 100644
index f72e12d5770e..000000000000
--- a/include/asm-x86/pci_64.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifndef ASM_X86__PCI_64_H
-#define ASM_X86__PCI_64_H
-
-#ifdef __KERNEL__
-
-#ifdef CONFIG_CALGARY_IOMMU
-static inline void *pci_iommu(struct pci_bus *bus)
-{
-	struct pci_sysdata *sd = bus->sysdata;
-	return sd->iommu;
-}
-
-static inline void set_pci_iommu(struct pci_bus *bus, void *val)
-{
-	struct pci_sysdata *sd = bus->sysdata;
-	sd->iommu = val;
-}
-#endif /* CONFIG_CALGARY_IOMMU */
-
-extern int (*pci_config_read)(int seg, int bus, int dev, int fn,
-			      int reg, int len, u32 *value);
-extern int (*pci_config_write)(int seg, int bus, int dev, int fn,
-			       int reg, int len, u32 value);
-
-extern void dma32_reserve_bootmem(void);
-extern void pci_iommu_alloc(void);
-
-/* The PCI address space does equal the physical memory
- * address space.  The networking and block device layers use
- * this boolean for bounce buffer decisions
- *
- * On AMD64 it mostly equals, but we set it to zero if a hardware
- * IOMMU (gart) of sotware IOMMU (swiotlb) is available.
- */
-#define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
-
-#if defined(CONFIG_GART_IOMMU) || defined(CONFIG_CALGARY_IOMMU)
-
-#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)	\
-	dma_addr_t ADDR_NAME;
-#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)		\
-	__u32 LEN_NAME;
-#define pci_unmap_addr(PTR, ADDR_NAME)			\
-	((PTR)->ADDR_NAME)
-#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)		\
-	(((PTR)->ADDR_NAME) = (VAL))
-#define pci_unmap_len(PTR, LEN_NAME)			\
-	((PTR)->LEN_NAME)
-#define pci_unmap_len_set(PTR, LEN_NAME, VAL)		\
-	(((PTR)->LEN_NAME) = (VAL))
-
-#else
-/* No IOMMU */
-
-#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
-#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
-#define pci_unmap_addr(PTR, ADDR_NAME)		(0)
-#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)	do { } while (0)
-#define pci_unmap_len(PTR, LEN_NAME)		(0)
-#define pci_unmap_len_set(PTR, LEN_NAME, VAL)	do { } while (0)
-
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif /* ASM_X86__PCI_64_H */
diff --git a/include/asm-x86/pda.h b/include/asm-x86/pda.h
deleted file mode 100644
index 45fd2aee8d6a..000000000000
--- a/include/asm-x86/pda.h
+++ /dev/null
@@ -1,137 +0,0 @@
-#ifndef ASM_X86__PDA_H
-#define ASM_X86__PDA_H
-
-#ifndef __ASSEMBLY__
-#include <linux/stddef.h>
-#include <linux/types.h>
-#include <linux/cache.h>
-#include <asm/page.h>
-
-/* Per processor datastructure. %gs points to it while the kernel runs */
-struct x8664_pda {
-	struct task_struct *pcurrent;	/* 0  Current process */
-	unsigned long data_offset;	/* 8 Per cpu data offset from linker
-					   address */
-	unsigned long kernelstack;	/* 16 top of kernel stack for current */
-	unsigned long oldrsp;		/* 24 user rsp for system call */
-	int irqcount;			/* 32 Irq nesting counter. Starts -1 */
-	unsigned int cpunumber;		/* 36 Logical CPU number */
-	unsigned long stack_canary;	/* 40 stack canary value */
-					/* gcc-ABI: this canary MUST be at
-					   offset 40!!! */
-	char *irqstackptr;
-	short nodenumber;		/* number of current node (32k max) */
-	short in_bootmem;		/* pda lives in bootmem */
-	unsigned int __softirq_pending;
-	unsigned int __nmi_count;	/* number of NMI on this CPUs */
-	short mmu_state;
-	short isidle;
-	struct mm_struct *active_mm;
-	unsigned apic_timer_irqs;
-	unsigned irq0_irqs;
-	unsigned irq_resched_count;
-	unsigned irq_call_count;
-	unsigned irq_tlb_count;
-	unsigned irq_thermal_count;
-	unsigned irq_threshold_count;
-	unsigned irq_spurious_count;
-} ____cacheline_aligned_in_smp;
-
-extern struct x8664_pda **_cpu_pda;
-extern void pda_init(int);
-
-#define cpu_pda(i) (_cpu_pda[i])
-
-/*
- * There is no fast way to get the base address of the PDA, all the accesses
- * have to mention %fs/%gs.  So it needs to be done this Torvaldian way.
- */
-extern void __bad_pda_field(void) __attribute__((noreturn));
-
-/*
- * proxy_pda doesn't actually exist, but tell gcc it is accessed for
- * all PDA accesses so it gets read/write dependencies right.
- */
-extern struct x8664_pda _proxy_pda;
-
-#define pda_offset(field) offsetof(struct x8664_pda, field)
-
-#define pda_to_op(op, field, val)					\
-do {									\
-	typedef typeof(_proxy_pda.field) T__;				\
-	if (0) { T__ tmp__; tmp__ = (val); }	/* type checking */	\
-	switch (sizeof(_proxy_pda.field)) {				\
-	case 2:								\
-		asm(op "w %1,%%gs:%c2" :				\
-		    "+m" (_proxy_pda.field) :				\
-		    "ri" ((T__)val),					\
-		    "i"(pda_offset(field)));				\
-		break;							\
-	case 4:								\
-		asm(op "l %1,%%gs:%c2" :				\
-		    "+m" (_proxy_pda.field) :				\
-		    "ri" ((T__)val),					\
-		    "i" (pda_offset(field)));				\
-		break;							\
-	case 8:								\
-		asm(op "q %1,%%gs:%c2":					\
-		    "+m" (_proxy_pda.field) :				\
-		    "ri" ((T__)val),					\
-		    "i"(pda_offset(field)));				\
-		break;							\
-	default:							\
-		__bad_pda_field();					\
-	}								\
-} while (0)
-
-#define pda_from_op(op, field)			\
-({						\
-	typeof(_proxy_pda.field) ret__;		\
-	switch (sizeof(_proxy_pda.field)) {	\
-	case 2:					\
-		asm(op "w %%gs:%c1,%0" :	\
-		    "=r" (ret__) :		\
-		    "i" (pda_offset(field)),	\
-		    "m" (_proxy_pda.field));	\
-		break;				\
-	case 4:					\
-		asm(op "l %%gs:%c1,%0":		\
-		    "=r" (ret__):		\
-		    "i" (pda_offset(field)),	\
-		    "m" (_proxy_pda.field));	\
-		break;				\
-	case 8:					\
-		asm(op "q %%gs:%c1,%0":		\
-		    "=r" (ret__) :		\
-		    "i" (pda_offset(field)),	\
-		    "m" (_proxy_pda.field));	\
-		break;				\
-	default:				\
-		__bad_pda_field();		\
-	}					\
-	ret__;					\
-})
-
-#define read_pda(field)		pda_from_op("mov", field)
-#define write_pda(field, val)	pda_to_op("mov", field, val)
-#define add_pda(field, val)	pda_to_op("add", field, val)
-#define sub_pda(field, val)	pda_to_op("sub", field, val)
-#define or_pda(field, val)	pda_to_op("or", field, val)
-
-/* This is not atomic against other CPUs -- CPU preemption needs to be off */
-#define test_and_clear_bit_pda(bit, field)				\
-({									\
-	int old__;							\
-	asm volatile("btr %2,%%gs:%c3\n\tsbbl %0,%0"			\
-		     : "=r" (old__), "+m" (_proxy_pda.field)		\
-		     : "dIr" (bit), "i" (pda_offset(field)) : "memory");\
-	old__;								\
-})
-
-#endif
-
-#define PDA_STACKOFFSET (5*8)
-
-#define refresh_stack_canary() write_pda(stack_canary, current->stack_canary)
-
-#endif /* ASM_X86__PDA_H */
diff --git a/include/asm-x86/percpu.h b/include/asm-x86/percpu.h
deleted file mode 100644
index e10a1d0678cf..000000000000
--- a/include/asm-x86/percpu.h
+++ /dev/null
@@ -1,218 +0,0 @@
-#ifndef ASM_X86__PERCPU_H
-#define ASM_X86__PERCPU_H
-
-#ifdef CONFIG_X86_64
-#include <linux/compiler.h>
-
-/* Same as asm-generic/percpu.h, except that we store the per cpu offset
-   in the PDA. Longer term the PDA and every per cpu variable
-   should be just put into a single section and referenced directly
-   from %gs */
-
-#ifdef CONFIG_SMP
-#include <asm/pda.h>
-
-#define __per_cpu_offset(cpu) (cpu_pda(cpu)->data_offset)
-#define __my_cpu_offset read_pda(data_offset)
-
-#define per_cpu_offset(x) (__per_cpu_offset(x))
-
-#endif
-#include <asm-generic/percpu.h>
-
-DECLARE_PER_CPU(struct x8664_pda, pda);
-
-/*
- * These are supposed to be implemented as a single instruction which
- * operates on the per-cpu data base segment.  x86-64 doesn't have
- * that yet, so this is a fairly inefficient workaround for the
- * meantime.  The single instruction is atomic with respect to
- * preemption and interrupts, so we need to explicitly disable
- * interrupts here to achieve the same effect.  However, because it
- * can be used from within interrupt-disable/enable, we can't actually
- * disable interrupts; disabling preemption is enough.
- */
-#define x86_read_percpu(var)						\
-	({								\
-		typeof(per_cpu_var(var)) __tmp;				\
-		preempt_disable();					\
-		__tmp = __get_cpu_var(var);				\
-		preempt_enable();					\
-		__tmp;							\
-	})
-
-#define x86_write_percpu(var, val)					\
-	do {								\
-		preempt_disable();					\
-		__get_cpu_var(var) = (val);				\
-		preempt_enable();					\
-	} while(0)
-
-#else /* CONFIG_X86_64 */
-
-#ifdef __ASSEMBLY__
-
-/*
- * PER_CPU finds an address of a per-cpu variable.
- *
- * Args:
- *    var - variable name
- *    reg - 32bit register
- *
- * The resulting address is stored in the "reg" argument.
- *
- * Example:
- *    PER_CPU(cpu_gdt_descr, %ebx)
- */
-#ifdef CONFIG_SMP
-#define PER_CPU(var, reg)				\
-	movl %fs:per_cpu__##this_cpu_off, reg;		\
-	lea per_cpu__##var(reg), reg
-#define PER_CPU_VAR(var)	%fs:per_cpu__##var
-#else /* ! SMP */
-#define PER_CPU(var, reg)			\
-	movl $per_cpu__##var, reg
-#define PER_CPU_VAR(var)	per_cpu__##var
-#endif	/* SMP */
-
-#else /* ...!ASSEMBLY */
-
-/*
- * PER_CPU finds an address of a per-cpu variable.
- *
- * Args:
- *    var - variable name
- *    cpu - 32bit register containing the current CPU number
- *
- * The resulting address is stored in the "cpu" argument.
- *
- * Example:
- *    PER_CPU(cpu_gdt_descr, %ebx)
- */
-#ifdef CONFIG_SMP
-
-#define __my_cpu_offset x86_read_percpu(this_cpu_off)
-
-/* fs segment starts at (positive) offset == __per_cpu_offset[cpu] */
-#define __percpu_seg "%%fs:"
-
-#else  /* !SMP */
-
-#define __percpu_seg ""
-
-#endif	/* SMP */
-
-#include <asm-generic/percpu.h>
-
-/* We can use this directly for local CPU (faster). */
-DECLARE_PER_CPU(unsigned long, this_cpu_off);
-
-/* For arch-specific code, we can use direct single-insn ops (they
- * don't give an lvalue though). */
-extern void __bad_percpu_size(void);
-
-#define percpu_to_op(op, var, val)			\
-do {							\
-	typedef typeof(var) T__;			\
-	if (0) {					\
-		T__ tmp__;				\
-		tmp__ = (val);				\
-	}						\
-	switch (sizeof(var)) {				\
-	case 1:						\
-		asm(op "b %1,"__percpu_seg"%0"		\
-		    : "+m" (var)			\
-		    : "ri" ((T__)val));			\
-		break;					\
-	case 2:						\
-		asm(op "w %1,"__percpu_seg"%0"		\
-		    : "+m" (var)			\
-		    : "ri" ((T__)val));			\
-		break;					\
-	case 4:						\
-		asm(op "l %1,"__percpu_seg"%0"		\
-		    : "+m" (var)			\
-		    : "ri" ((T__)val));			\
-		break;					\
-	default: __bad_percpu_size();			\
-	}						\
-} while (0)
-
-#define percpu_from_op(op, var)				\
-({							\
-	typeof(var) ret__;				\
-	switch (sizeof(var)) {				\
-	case 1:						\
-		asm(op "b "__percpu_seg"%1,%0"		\
-		    : "=r" (ret__)			\
-		    : "m" (var));			\
-		break;					\
-	case 2:						\
-		asm(op "w "__percpu_seg"%1,%0"		\
-		    : "=r" (ret__)			\
-		    : "m" (var));			\
-		break;					\
-	case 4:						\
-		asm(op "l "__percpu_seg"%1,%0"		\
-		    : "=r" (ret__)			\
-		    : "m" (var));			\
-		break;					\
-	default: __bad_percpu_size();			\
-	}						\
-	ret__;						\
-})
-
-#define x86_read_percpu(var) percpu_from_op("mov", per_cpu__##var)
-#define x86_write_percpu(var, val) percpu_to_op("mov", per_cpu__##var, val)
-#define x86_add_percpu(var, val) percpu_to_op("add", per_cpu__##var, val)
-#define x86_sub_percpu(var, val) percpu_to_op("sub", per_cpu__##var, val)
-#define x86_or_percpu(var, val) percpu_to_op("or", per_cpu__##var, val)
-#endif /* !__ASSEMBLY__ */
-#endif /* !CONFIG_X86_64 */
-
-#ifdef CONFIG_SMP
-
-/*
- * Define the "EARLY_PER_CPU" macros.  These are used for some per_cpu
- * variables that are initialized and accessed before there are per_cpu
- * areas allocated.
- */
-
-#define	DEFINE_EARLY_PER_CPU(_type, _name, _initvalue)			\
-	DEFINE_PER_CPU(_type, _name) = _initvalue;			\
-	__typeof__(_type) _name##_early_map[NR_CPUS] __initdata =	\
-				{ [0 ... NR_CPUS-1] = _initvalue };	\
-	__typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map
-
-#define EXPORT_EARLY_PER_CPU_SYMBOL(_name)			\
-	EXPORT_PER_CPU_SYMBOL(_name)
-
-#define DECLARE_EARLY_PER_CPU(_type, _name)			\
-	DECLARE_PER_CPU(_type, _name);				\
-	extern __typeof__(_type) *_name##_early_ptr;		\
-	extern __typeof__(_type)  _name##_early_map[]
-
-#define	early_per_cpu_ptr(_name) (_name##_early_ptr)
-#define	early_per_cpu_map(_name, _idx) (_name##_early_map[_idx])
-#define	early_per_cpu(_name, _cpu) 				\
-	(early_per_cpu_ptr(_name) ?				\
-		early_per_cpu_ptr(_name)[_cpu] :		\
-		per_cpu(_name, _cpu))
-
-#else	/* !CONFIG_SMP */
-#define	DEFINE_EARLY_PER_CPU(_type, _name, _initvalue)		\
-	DEFINE_PER_CPU(_type, _name) = _initvalue
-
-#define EXPORT_EARLY_PER_CPU_SYMBOL(_name)			\
-	EXPORT_PER_CPU_SYMBOL(_name)
-
-#define DECLARE_EARLY_PER_CPU(_type, _name)			\
-	DECLARE_PER_CPU(_type, _name)
-
-#define	early_per_cpu(_name, _cpu) per_cpu(_name, _cpu)
-#define	early_per_cpu_ptr(_name) NULL
-/* no early_per_cpu_map() */
-
-#endif	/* !CONFIG_SMP */
-
-#endif /* ASM_X86__PERCPU_H */
diff --git a/include/asm-x86/pgalloc.h b/include/asm-x86/pgalloc.h
deleted file mode 100644
index 3cd23adedae8..000000000000
--- a/include/asm-x86/pgalloc.h
+++ /dev/null
@@ -1,114 +0,0 @@
-#ifndef ASM_X86__PGALLOC_H
-#define ASM_X86__PGALLOC_H
-
-#include <linux/threads.h>
-#include <linux/mm.h>		/* for struct page */
-#include <linux/pagemap.h>
-
-static inline int  __paravirt_pgd_alloc(struct mm_struct *mm) { return 0; }
-
-#ifdef CONFIG_PARAVIRT
-#include <asm/paravirt.h>
-#else
-#define paravirt_pgd_alloc(mm)	__paravirt_pgd_alloc(mm)
-static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd) {}
-static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn)	{}
-static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn)	{}
-static inline void paravirt_alloc_pmd_clone(unsigned long pfn, unsigned long clonepfn,
-					    unsigned long start, unsigned long count) {}
-static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn)	{}
-static inline void paravirt_release_pte(unsigned long pfn) {}
-static inline void paravirt_release_pmd(unsigned long pfn) {}
-static inline void paravirt_release_pud(unsigned long pfn) {}
-#endif
-
-/*
- * Allocate and free page tables.
- */
-extern pgd_t *pgd_alloc(struct mm_struct *);
-extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
-
-extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long);
-extern pgtable_t pte_alloc_one(struct mm_struct *, unsigned long);
-
-/* Should really implement gc for free page table pages. This could be
-   done with a reference count in struct page. */
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
-	BUG_ON((unsigned long)pte & (PAGE_SIZE-1));
-	free_page((unsigned long)pte);
-}
-
-static inline void pte_free(struct mm_struct *mm, struct page *pte)
-{
-	__free_page(pte);
-}
-
-extern void __pte_free_tlb(struct mmu_gather *tlb, struct page *pte);
-
-static inline void pmd_populate_kernel(struct mm_struct *mm,
-				       pmd_t *pmd, pte_t *pte)
-{
-	paravirt_alloc_pte(mm, __pa(pte) >> PAGE_SHIFT);
-	set_pmd(pmd, __pmd(__pa(pte) | _PAGE_TABLE));
-}
-
-static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
-				struct page *pte)
-{
-	unsigned long pfn = page_to_pfn(pte);
-
-	paravirt_alloc_pte(mm, pfn);
-	set_pmd(pmd, __pmd(((pteval_t)pfn << PAGE_SHIFT) | _PAGE_TABLE));
-}
-
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-#if PAGETABLE_LEVELS > 2
-static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
-{
-	return (pmd_t *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT);
-}
-
-static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
-{
-	BUG_ON((unsigned long)pmd & (PAGE_SIZE-1));
-	free_page((unsigned long)pmd);
-}
-
-extern void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd);
-
-#ifdef CONFIG_X86_PAE
-extern void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd);
-#else	/* !CONFIG_X86_PAE */
-static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
-{
-	paravirt_alloc_pmd(mm, __pa(pmd) >> PAGE_SHIFT);
-	set_pud(pud, __pud(_PAGE_TABLE | __pa(pmd)));
-}
-#endif	/* CONFIG_X86_PAE */
-
-#if PAGETABLE_LEVELS > 3
-static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
-{
-	paravirt_alloc_pud(mm, __pa(pud) >> PAGE_SHIFT);
-	set_pgd(pgd, __pgd(_PAGE_TABLE | __pa(pud)));
-}
-
-static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
-{
-	return (pud_t *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT);
-}
-
-static inline void pud_free(struct mm_struct *mm, pud_t *pud)
-{
-	BUG_ON((unsigned long)pud & (PAGE_SIZE-1));
-	free_page((unsigned long)pud);
-}
-
-extern void __pud_free_tlb(struct mmu_gather *tlb, pud_t *pud);
-#endif	/* PAGETABLE_LEVELS > 3 */
-#endif	/* PAGETABLE_LEVELS > 2 */
-
-#endif /* ASM_X86__PGALLOC_H */
diff --git a/include/asm-x86/pgtable-2level-defs.h b/include/asm-x86/pgtable-2level-defs.h
deleted file mode 100644
index 7ec48f4e5347..000000000000
--- a/include/asm-x86/pgtable-2level-defs.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef ASM_X86__PGTABLE_2LEVEL_DEFS_H
-#define ASM_X86__PGTABLE_2LEVEL_DEFS_H
-
-#define SHARED_KERNEL_PMD	0
-
-/*
- * traditional i386 two-level paging structure:
- */
-
-#define PGDIR_SHIFT	22
-#define PTRS_PER_PGD	1024
-
-/*
- * the i386 is two-level, so we don't really have any
- * PMD directory physically.
- */
-
-#define PTRS_PER_PTE	1024
-
-#endif /* ASM_X86__PGTABLE_2LEVEL_DEFS_H */
diff --git a/include/asm-x86/pgtable-2level.h b/include/asm-x86/pgtable-2level.h
deleted file mode 100644
index 81762081dcd8..000000000000
--- a/include/asm-x86/pgtable-2level.h
+++ /dev/null
@@ -1,79 +0,0 @@
-#ifndef ASM_X86__PGTABLE_2LEVEL_H
-#define ASM_X86__PGTABLE_2LEVEL_H
-
-#define pte_ERROR(e) \
-	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, (e).pte_low)
-#define pgd_ERROR(e) \
-	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
-
-/*
- * Certain architectures need to do special things when PTEs
- * within a page table are directly modified.  Thus, the following
- * hook is made available.
- */
-static inline void native_set_pte(pte_t *ptep , pte_t pte)
-{
-	*ptep = pte;
-}
-
-static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
-{
-	*pmdp = pmd;
-}
-
-static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
-{
-	native_set_pte(ptep, pte);
-}
-
-static inline void native_set_pte_present(struct mm_struct *mm,
-					  unsigned long addr,
-					  pte_t *ptep, pte_t pte)
-{
-	native_set_pte(ptep, pte);
-}
-
-static inline void native_pmd_clear(pmd_t *pmdp)
-{
-	native_set_pmd(pmdp, __pmd(0));
-}
-
-static inline void native_pte_clear(struct mm_struct *mm,
-				    unsigned long addr, pte_t *xp)
-{
-	*xp = native_make_pte(0);
-}
-
-#ifdef CONFIG_SMP
-static inline pte_t native_ptep_get_and_clear(pte_t *xp)
-{
-	return __pte(xchg(&xp->pte_low, 0));
-}
-#else
-#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
-#endif
-
-#define pte_none(x)		(!(x).pte_low)
-
-/*
- * Bits 0, 6 and 7 are taken, split up the 29 bits of offset
- * into this range:
- */
-#define PTE_FILE_MAX_BITS	29
-
-#define pte_to_pgoff(pte)						\
-	((((pte).pte_low >> 1) & 0x1f) + (((pte).pte_low >> 8) << 5))
-
-#define pgoff_to_pte(off)						\
-	((pte_t) { .pte_low = (((off) & 0x1f) << 1) +			\
-			(((off) >> 5) << 8) + _PAGE_FILE })
-
-/* Encode and de-code a swap entry */
-#define __swp_type(x)			(((x).val >> 1) & 0x1f)
-#define __swp_offset(x)			((x).val >> 8)
-#define __swp_entry(type, offset)				\
-	((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
-#define __pte_to_swp_entry(pte)		((swp_entry_t) { (pte).pte_low })
-#define __swp_entry_to_pte(x)		((pte_t) { .pte = (x).val })
-
-#endif /* ASM_X86__PGTABLE_2LEVEL_H */
diff --git a/include/asm-x86/pgtable-3level-defs.h b/include/asm-x86/pgtable-3level-defs.h
deleted file mode 100644
index c05fe6ff3720..000000000000
--- a/include/asm-x86/pgtable-3level-defs.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef ASM_X86__PGTABLE_3LEVEL_DEFS_H
-#define ASM_X86__PGTABLE_3LEVEL_DEFS_H
-
-#ifdef CONFIG_PARAVIRT
-#define SHARED_KERNEL_PMD	(pv_info.shared_kernel_pmd)
-#else
-#define SHARED_KERNEL_PMD	1
-#endif
-
-/*
- * PGDIR_SHIFT determines what a top-level page table entry can map
- */
-#define PGDIR_SHIFT	30
-#define PTRS_PER_PGD	4
-
-/*
- * PMD_SHIFT determines the size of the area a middle-level
- * page table can map
- */
-#define PMD_SHIFT	21
-#define PTRS_PER_PMD	512
-
-/*
- * entries per page directory level
- */
-#define PTRS_PER_PTE	512
-
-#endif /* ASM_X86__PGTABLE_3LEVEL_DEFS_H */
diff --git a/include/asm-x86/pgtable-3level.h b/include/asm-x86/pgtable-3level.h
deleted file mode 100644
index 75f4276b5ddb..000000000000
--- a/include/asm-x86/pgtable-3level.h
+++ /dev/null
@@ -1,175 +0,0 @@
-#ifndef ASM_X86__PGTABLE_3LEVEL_H
-#define ASM_X86__PGTABLE_3LEVEL_H
-
-/*
- * Intel Physical Address Extension (PAE) Mode - three-level page
- * tables on PPro+ CPUs.
- *
- * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
- */
-
-#define pte_ERROR(e)							\
-	printk("%s:%d: bad pte %p(%08lx%08lx).\n",			\
-	       __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
-#define pmd_ERROR(e)							\
-	printk("%s:%d: bad pmd %p(%016Lx).\n",				\
-	       __FILE__, __LINE__, &(e), pmd_val(e))
-#define pgd_ERROR(e)							\
-	printk("%s:%d: bad pgd %p(%016Lx).\n",				\
-	       __FILE__, __LINE__, &(e), pgd_val(e))
-
-static inline int pud_none(pud_t pud)
-{
-	return pud_val(pud) == 0;
-}
-
-static inline int pud_bad(pud_t pud)
-{
-	return (pud_val(pud) & ~(PTE_PFN_MASK | _KERNPG_TABLE | _PAGE_USER)) != 0;
-}
-
-static inline int pud_present(pud_t pud)
-{
-	return pud_val(pud) & _PAGE_PRESENT;
-}
-
-/* Rules for using set_pte: the pte being assigned *must* be
- * either not present or in a state where the hardware will
- * not attempt to update the pte.  In places where this is
- * not possible, use pte_get_and_clear to obtain the old pte
- * value and then use set_pte to update it.  -ben
- */
-static inline void native_set_pte(pte_t *ptep, pte_t pte)
-{
-	ptep->pte_high = pte.pte_high;
-	smp_wmb();
-	ptep->pte_low = pte.pte_low;
-}
-
-/*
- * Since this is only called on user PTEs, and the page fault handler
- * must handle the already racy situation of simultaneous page faults,
- * we are justified in merely clearing the PTE present bit, followed
- * by a set.  The ordering here is important.
- */
-static inline void native_set_pte_present(struct mm_struct *mm,
-					  unsigned long addr,
-					  pte_t *ptep, pte_t pte)
-{
-	ptep->pte_low = 0;
-	smp_wmb();
-	ptep->pte_high = pte.pte_high;
-	smp_wmb();
-	ptep->pte_low = pte.pte_low;
-}
-
-static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
-{
-	set_64bit((unsigned long long *)(ptep), native_pte_val(pte));
-}
-
-static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
-{
-	set_64bit((unsigned long long *)(pmdp), native_pmd_val(pmd));
-}
-
-static inline void native_set_pud(pud_t *pudp, pud_t pud)
-{
-	set_64bit((unsigned long long *)(pudp), native_pud_val(pud));
-}
-
-/*
- * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
- * entry, so clear the bottom half first and enforce ordering with a compiler
- * barrier.
- */
-static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
-				    pte_t *ptep)
-{
-	ptep->pte_low = 0;
-	smp_wmb();
-	ptep->pte_high = 0;
-}
-
-static inline void native_pmd_clear(pmd_t *pmd)
-{
-	u32 *tmp = (u32 *)pmd;
-	*tmp = 0;
-	smp_wmb();
-	*(tmp + 1) = 0;
-}
-
-static inline void pud_clear(pud_t *pudp)
-{
-	unsigned long pgd;
-
-	set_pud(pudp, __pud(0));
-
-	/*
-	 * According to Intel App note "TLBs, Paging-Structure Caches,
-	 * and Their Invalidation", April 2007, document 317080-001,
-	 * section 8.1: in PAE mode we explicitly have to flush the
-	 * TLB via cr3 if the top-level pgd is changed...
-	 *
-	 * Make sure the pud entry we're updating is within the
-	 * current pgd to avoid unnecessary TLB flushes.
-	 */
-	pgd = read_cr3();
-	if (__pa(pudp) >= pgd && __pa(pudp) <
-	    (pgd + sizeof(pgd_t)*PTRS_PER_PGD))
-		write_cr3(pgd);
-}
-
-#define pud_page(pud) ((struct page *) __va(pud_val(pud) & PTE_PFN_MASK))
-
-#define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & PTE_PFN_MASK))
-
-
-/* Find an entry in the second-level page table.. */
-#define pmd_offset(pud, address) ((pmd_t *)pud_page(*(pud)) +	\
-				  pmd_index(address))
-
-#ifdef CONFIG_SMP
-static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
-{
-	pte_t res;
-
-	/* xchg acts as a barrier before the setting of the high bits */
-	res.pte_low = xchg(&ptep->pte_low, 0);
-	res.pte_high = ptep->pte_high;
-	ptep->pte_high = 0;
-
-	return res;
-}
-#else
-#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
-#endif
-
-#define __HAVE_ARCH_PTE_SAME
-static inline int pte_same(pte_t a, pte_t b)
-{
-	return a.pte_low == b.pte_low && a.pte_high == b.pte_high;
-}
-
-static inline int pte_none(pte_t pte)
-{
-	return !pte.pte_low && !pte.pte_high;
-}
-
-/*
- * Bits 0, 6 and 7 are taken in the low part of the pte,
- * put the 32 bits of offset into the high part.
- */
-#define pte_to_pgoff(pte) ((pte).pte_high)
-#define pgoff_to_pte(off)						\
-	((pte_t) { { .pte_low = _PAGE_FILE, .pte_high = (off) } })
-#define PTE_FILE_MAX_BITS       32
-
-/* Encode and de-code a swap entry */
-#define __swp_type(x)			(((x).val) & 0x1f)
-#define __swp_offset(x)			((x).val >> 5)
-#define __swp_entry(type, offset)	((swp_entry_t){(type) | (offset) << 5})
-#define __pte_to_swp_entry(pte)		((swp_entry_t){ (pte).pte_high })
-#define __swp_entry_to_pte(x)		((pte_t){ { .pte_high = (x).val } })
-
-#endif /* ASM_X86__PGTABLE_3LEVEL_H */
diff --git a/include/asm-x86/pgtable.h b/include/asm-x86/pgtable.h
deleted file mode 100644
index 182f9d4c570f..000000000000
--- a/include/asm-x86/pgtable.h
+++ /dev/null
@@ -1,556 +0,0 @@
-#ifndef ASM_X86__PGTABLE_H
-#define ASM_X86__PGTABLE_H
-
-#define FIRST_USER_ADDRESS	0
-
-#define _PAGE_BIT_PRESENT	0	/* is present */
-#define _PAGE_BIT_RW		1	/* writeable */
-#define _PAGE_BIT_USER		2	/* userspace addressable */
-#define _PAGE_BIT_PWT		3	/* page write through */
-#define _PAGE_BIT_PCD		4	/* page cache disabled */
-#define _PAGE_BIT_ACCESSED	5	/* was accessed (raised by CPU) */
-#define _PAGE_BIT_DIRTY		6	/* was written to (raised by CPU) */
-#define _PAGE_BIT_FILE		6
-#define _PAGE_BIT_PSE		7	/* 4 MB (or 2MB) page */
-#define _PAGE_BIT_PAT		7	/* on 4KB pages */
-#define _PAGE_BIT_GLOBAL	8	/* Global TLB entry PPro+ */
-#define _PAGE_BIT_UNUSED1	9	/* available for programmer */
-#define _PAGE_BIT_IOMAP		10	/* flag used to indicate IO mapping */
-#define _PAGE_BIT_UNUSED3	11
-#define _PAGE_BIT_PAT_LARGE	12	/* On 2MB or 1GB pages */
-#define _PAGE_BIT_SPECIAL	_PAGE_BIT_UNUSED1
-#define _PAGE_BIT_CPA_TEST	_PAGE_BIT_UNUSED1
-#define _PAGE_BIT_NX           63       /* No execute: only valid after cpuid check */
-
-#define _PAGE_PRESENT	(_AT(pteval_t, 1) << _PAGE_BIT_PRESENT)
-#define _PAGE_RW	(_AT(pteval_t, 1) << _PAGE_BIT_RW)
-#define _PAGE_USER	(_AT(pteval_t, 1) << _PAGE_BIT_USER)
-#define _PAGE_PWT	(_AT(pteval_t, 1) << _PAGE_BIT_PWT)
-#define _PAGE_PCD	(_AT(pteval_t, 1) << _PAGE_BIT_PCD)
-#define _PAGE_ACCESSED	(_AT(pteval_t, 1) << _PAGE_BIT_ACCESSED)
-#define _PAGE_DIRTY	(_AT(pteval_t, 1) << _PAGE_BIT_DIRTY)
-#define _PAGE_PSE	(_AT(pteval_t, 1) << _PAGE_BIT_PSE)
-#define _PAGE_GLOBAL	(_AT(pteval_t, 1) << _PAGE_BIT_GLOBAL)
-#define _PAGE_UNUSED1	(_AT(pteval_t, 1) << _PAGE_BIT_UNUSED1)
-#define _PAGE_IOMAP	(_AT(pteval_t, 1) << _PAGE_BIT_IOMAP)
-#define _PAGE_UNUSED3	(_AT(pteval_t, 1) << _PAGE_BIT_UNUSED3)
-#define _PAGE_PAT	(_AT(pteval_t, 1) << _PAGE_BIT_PAT)
-#define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE)
-#define _PAGE_SPECIAL	(_AT(pteval_t, 1) << _PAGE_BIT_SPECIAL)
-#define _PAGE_CPA_TEST	(_AT(pteval_t, 1) << _PAGE_BIT_CPA_TEST)
-#define __HAVE_ARCH_PTE_SPECIAL
-
-#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
-#define _PAGE_NX	(_AT(pteval_t, 1) << _PAGE_BIT_NX)
-#else
-#define _PAGE_NX	(_AT(pteval_t, 0))
-#endif
-
-/* If _PAGE_PRESENT is clear, we use these: */
-#define _PAGE_FILE	_PAGE_DIRTY	/* nonlinear file mapping,
-					 * saved PTE; unset:swap */
-#define _PAGE_PROTNONE	_PAGE_PSE	/* if the user mapped it with PROT_NONE;
-					   pte_present gives true */
-
-#define _PAGE_TABLE	(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |	\
-			 _PAGE_ACCESSED | _PAGE_DIRTY)
-#define _KERNPG_TABLE	(_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED |	\
-			 _PAGE_DIRTY)
-
-/* Set of bits not changed in pte_modify */
-#define _PAGE_CHG_MASK	(PTE_PFN_MASK | _PAGE_PCD | _PAGE_PWT |		\
-			 _PAGE_SPECIAL | _PAGE_ACCESSED | _PAGE_DIRTY)
-
-#define _PAGE_CACHE_MASK	(_PAGE_PCD | _PAGE_PWT)
-#define _PAGE_CACHE_WB		(0)
-#define _PAGE_CACHE_WC		(_PAGE_PWT)
-#define _PAGE_CACHE_UC_MINUS	(_PAGE_PCD)
-#define _PAGE_CACHE_UC		(_PAGE_PCD | _PAGE_PWT)
-
-#define PAGE_NONE	__pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
-#define PAGE_SHARED	__pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
-				 _PAGE_ACCESSED | _PAGE_NX)
-
-#define PAGE_SHARED_EXEC	__pgprot(_PAGE_PRESENT | _PAGE_RW |	\
-					 _PAGE_USER | _PAGE_ACCESSED)
-#define PAGE_COPY_NOEXEC	__pgprot(_PAGE_PRESENT | _PAGE_USER |	\
-					 _PAGE_ACCESSED | _PAGE_NX)
-#define PAGE_COPY_EXEC		__pgprot(_PAGE_PRESENT | _PAGE_USER |	\
-					 _PAGE_ACCESSED)
-#define PAGE_COPY		PAGE_COPY_NOEXEC
-#define PAGE_READONLY		__pgprot(_PAGE_PRESENT | _PAGE_USER |	\
-					 _PAGE_ACCESSED | _PAGE_NX)
-#define PAGE_READONLY_EXEC	__pgprot(_PAGE_PRESENT | _PAGE_USER |	\
-					 _PAGE_ACCESSED)
-
-#define __PAGE_KERNEL_EXEC						\
-	(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_GLOBAL)
-#define __PAGE_KERNEL		(__PAGE_KERNEL_EXEC | _PAGE_NX)
-
-#define __PAGE_KERNEL_RO		(__PAGE_KERNEL & ~_PAGE_RW)
-#define __PAGE_KERNEL_RX		(__PAGE_KERNEL_EXEC & ~_PAGE_RW)
-#define __PAGE_KERNEL_EXEC_NOCACHE	(__PAGE_KERNEL_EXEC | _PAGE_PCD | _PAGE_PWT)
-#define __PAGE_KERNEL_WC		(__PAGE_KERNEL | _PAGE_CACHE_WC)
-#define __PAGE_KERNEL_NOCACHE		(__PAGE_KERNEL | _PAGE_PCD | _PAGE_PWT)
-#define __PAGE_KERNEL_UC_MINUS		(__PAGE_KERNEL | _PAGE_PCD)
-#define __PAGE_KERNEL_VSYSCALL		(__PAGE_KERNEL_RX | _PAGE_USER)
-#define __PAGE_KERNEL_VSYSCALL_NOCACHE	(__PAGE_KERNEL_VSYSCALL | _PAGE_PCD | _PAGE_PWT)
-#define __PAGE_KERNEL_LARGE		(__PAGE_KERNEL | _PAGE_PSE)
-#define __PAGE_KERNEL_LARGE_NOCACHE	(__PAGE_KERNEL | _PAGE_CACHE_UC | _PAGE_PSE)
-#define __PAGE_KERNEL_LARGE_EXEC	(__PAGE_KERNEL_EXEC | _PAGE_PSE)
-
-#define __PAGE_KERNEL_IO		(__PAGE_KERNEL | _PAGE_IOMAP)
-#define __PAGE_KERNEL_IO_NOCACHE	(__PAGE_KERNEL_NOCACHE | _PAGE_IOMAP)
-#define __PAGE_KERNEL_IO_UC_MINUS	(__PAGE_KERNEL_UC_MINUS | _PAGE_IOMAP)
-#define __PAGE_KERNEL_IO_WC		(__PAGE_KERNEL_WC | _PAGE_IOMAP)
-
-#define PAGE_KERNEL			__pgprot(__PAGE_KERNEL)
-#define PAGE_KERNEL_RO			__pgprot(__PAGE_KERNEL_RO)
-#define PAGE_KERNEL_EXEC		__pgprot(__PAGE_KERNEL_EXEC)
-#define PAGE_KERNEL_RX			__pgprot(__PAGE_KERNEL_RX)
-#define PAGE_KERNEL_WC			__pgprot(__PAGE_KERNEL_WC)
-#define PAGE_KERNEL_NOCACHE		__pgprot(__PAGE_KERNEL_NOCACHE)
-#define PAGE_KERNEL_UC_MINUS		__pgprot(__PAGE_KERNEL_UC_MINUS)
-#define PAGE_KERNEL_EXEC_NOCACHE	__pgprot(__PAGE_KERNEL_EXEC_NOCACHE)
-#define PAGE_KERNEL_LARGE		__pgprot(__PAGE_KERNEL_LARGE)
-#define PAGE_KERNEL_LARGE_NOCACHE	__pgprot(__PAGE_KERNEL_LARGE_NOCACHE)
-#define PAGE_KERNEL_LARGE_EXEC		__pgprot(__PAGE_KERNEL_LARGE_EXEC)
-#define PAGE_KERNEL_VSYSCALL		__pgprot(__PAGE_KERNEL_VSYSCALL)
-#define PAGE_KERNEL_VSYSCALL_NOCACHE	__pgprot(__PAGE_KERNEL_VSYSCALL_NOCACHE)
-
-#define PAGE_KERNEL_IO			__pgprot(__PAGE_KERNEL_IO)
-#define PAGE_KERNEL_IO_NOCACHE		__pgprot(__PAGE_KERNEL_IO_NOCACHE)
-#define PAGE_KERNEL_IO_UC_MINUS		__pgprot(__PAGE_KERNEL_IO_UC_MINUS)
-#define PAGE_KERNEL_IO_WC		__pgprot(__PAGE_KERNEL_IO_WC)
-
-/*         xwr */
-#define __P000	PAGE_NONE
-#define __P001	PAGE_READONLY
-#define __P010	PAGE_COPY
-#define __P011	PAGE_COPY
-#define __P100	PAGE_READONLY_EXEC
-#define __P101	PAGE_READONLY_EXEC
-#define __P110	PAGE_COPY_EXEC
-#define __P111	PAGE_COPY_EXEC
-
-#define __S000	PAGE_NONE
-#define __S001	PAGE_READONLY
-#define __S010	PAGE_SHARED
-#define __S011	PAGE_SHARED
-#define __S100	PAGE_READONLY_EXEC
-#define __S101	PAGE_READONLY_EXEC
-#define __S110	PAGE_SHARED_EXEC
-#define __S111	PAGE_SHARED_EXEC
-
-/*
- * early identity mapping  pte attrib macros.
- */
-#ifdef CONFIG_X86_64
-#define __PAGE_KERNEL_IDENT_LARGE_EXEC	__PAGE_KERNEL_LARGE_EXEC
-#else
-#define PTE_IDENT_ATTR	 0x003		/* PRESENT+RW */
-#define PDE_IDENT_ATTR	 0x063		/* PRESENT+RW+DIRTY+ACCESSED */
-#define PGD_IDENT_ATTR	 0x001		/* PRESENT (no other attributes) */
-#endif
-
-#ifndef __ASSEMBLY__
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
-#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
-
-extern spinlock_t pgd_lock;
-extern struct list_head pgd_list;
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-static inline int pte_dirty(pte_t pte)
-{
-	return pte_flags(pte) & _PAGE_DIRTY;
-}
-
-static inline int pte_young(pte_t pte)
-{
-	return pte_flags(pte) & _PAGE_ACCESSED;
-}
-
-static inline int pte_write(pte_t pte)
-{
-	return pte_flags(pte) & _PAGE_RW;
-}
-
-static inline int pte_file(pte_t pte)
-{
-	return pte_flags(pte) & _PAGE_FILE;
-}
-
-static inline int pte_huge(pte_t pte)
-{
-	return pte_flags(pte) & _PAGE_PSE;
-}
-
-static inline int pte_global(pte_t pte)
-{
-	return pte_flags(pte) & _PAGE_GLOBAL;
-}
-
-static inline int pte_exec(pte_t pte)
-{
-	return !(pte_flags(pte) & _PAGE_NX);
-}
-
-static inline int pte_special(pte_t pte)
-{
-	return pte_flags(pte) & _PAGE_SPECIAL;
-}
-
-static inline unsigned long pte_pfn(pte_t pte)
-{
-	return (pte_val(pte) & PTE_PFN_MASK) >> PAGE_SHIFT;
-}
-
-#define pte_page(pte)	pfn_to_page(pte_pfn(pte))
-
-static inline int pmd_large(pmd_t pte)
-{
-	return (pmd_val(pte) & (_PAGE_PSE | _PAGE_PRESENT)) ==
-		(_PAGE_PSE | _PAGE_PRESENT);
-}
-
-static inline pte_t pte_mkclean(pte_t pte)
-{
-	return __pte(pte_val(pte) & ~_PAGE_DIRTY);
-}
-
-static inline pte_t pte_mkold(pte_t pte)
-{
-	return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
-}
-
-static inline pte_t pte_wrprotect(pte_t pte)
-{
-	return __pte(pte_val(pte) & ~_PAGE_RW);
-}
-
-static inline pte_t pte_mkexec(pte_t pte)
-{
-	return __pte(pte_val(pte) & ~_PAGE_NX);
-}
-
-static inline pte_t pte_mkdirty(pte_t pte)
-{
-	return __pte(pte_val(pte) | _PAGE_DIRTY);
-}
-
-static inline pte_t pte_mkyoung(pte_t pte)
-{
-	return __pte(pte_val(pte) | _PAGE_ACCESSED);
-}
-
-static inline pte_t pte_mkwrite(pte_t pte)
-{
-	return __pte(pte_val(pte) | _PAGE_RW);
-}
-
-static inline pte_t pte_mkhuge(pte_t pte)
-{
-	return __pte(pte_val(pte) | _PAGE_PSE);
-}
-
-static inline pte_t pte_clrhuge(pte_t pte)
-{
-	return __pte(pte_val(pte) & ~_PAGE_PSE);
-}
-
-static inline pte_t pte_mkglobal(pte_t pte)
-{
-	return __pte(pte_val(pte) | _PAGE_GLOBAL);
-}
-
-static inline pte_t pte_clrglobal(pte_t pte)
-{
-	return __pte(pte_val(pte) & ~_PAGE_GLOBAL);
-}
-
-static inline pte_t pte_mkspecial(pte_t pte)
-{
-	return __pte(pte_val(pte) | _PAGE_SPECIAL);
-}
-
-extern pteval_t __supported_pte_mask;
-
-static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
-{
-	return __pte((((phys_addr_t)page_nr << PAGE_SHIFT) |
-		      pgprot_val(pgprot)) & __supported_pte_mask);
-}
-
-static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
-{
-	return __pmd((((phys_addr_t)page_nr << PAGE_SHIFT) |
-		      pgprot_val(pgprot)) & __supported_pte_mask);
-}
-
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{
-	pteval_t val = pte_val(pte);
-
-	/*
-	 * Chop off the NX bit (if present), and add the NX portion of
-	 * the newprot (if present):
-	 */
-	val &= _PAGE_CHG_MASK;
-	val |= pgprot_val(newprot) & (~_PAGE_CHG_MASK) & __supported_pte_mask;
-
-	return __pte(val);
-}
-
-/* mprotect needs to preserve PAT bits when updating vm_page_prot */
-#define pgprot_modify pgprot_modify
-static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
-{
-	pgprotval_t preservebits = pgprot_val(oldprot) & _PAGE_CHG_MASK;
-	pgprotval_t addbits = pgprot_val(newprot);
-	return __pgprot(preservebits | addbits);
-}
-
-#define pte_pgprot(x) __pgprot(pte_flags(x) & PTE_FLAGS_MASK)
-
-#define canon_pgprot(p) __pgprot(pgprot_val(p) & __supported_pte_mask)
-
-#ifndef __ASSEMBLY__
-#define __HAVE_PHYS_MEM_ACCESS_PROT
-struct file;
-pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
-                              unsigned long size, pgprot_t vma_prot);
-int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
-                              unsigned long size, pgprot_t *vma_prot);
-#endif
-
-/* Install a pte for a particular vaddr in kernel space. */
-void set_pte_vaddr(unsigned long vaddr, pte_t pte);
-
-#ifdef CONFIG_X86_32
-extern void native_pagetable_setup_start(pgd_t *base);
-extern void native_pagetable_setup_done(pgd_t *base);
-#else
-static inline void native_pagetable_setup_start(pgd_t *base) {}
-static inline void native_pagetable_setup_done(pgd_t *base) {}
-#endif
-
-extern int arch_report_meminfo(char *page);
-
-#ifdef CONFIG_PARAVIRT
-#include <asm/paravirt.h>
-#else  /* !CONFIG_PARAVIRT */
-#define set_pte(ptep, pte)		native_set_pte(ptep, pte)
-#define set_pte_at(mm, addr, ptep, pte)	native_set_pte_at(mm, addr, ptep, pte)
-
-#define set_pte_present(mm, addr, ptep, pte)				\
-	native_set_pte_present(mm, addr, ptep, pte)
-#define set_pte_atomic(ptep, pte)					\
-	native_set_pte_atomic(ptep, pte)
-
-#define set_pmd(pmdp, pmd)		native_set_pmd(pmdp, pmd)
-
-#ifndef __PAGETABLE_PUD_FOLDED
-#define set_pgd(pgdp, pgd)		native_set_pgd(pgdp, pgd)
-#define pgd_clear(pgd)			native_pgd_clear(pgd)
-#endif
-
-#ifndef set_pud
-# define set_pud(pudp, pud)		native_set_pud(pudp, pud)
-#endif
-
-#ifndef __PAGETABLE_PMD_FOLDED
-#define pud_clear(pud)			native_pud_clear(pud)
-#endif
-
-#define pte_clear(mm, addr, ptep)	native_pte_clear(mm, addr, ptep)
-#define pmd_clear(pmd)			native_pmd_clear(pmd)
-
-#define pte_update(mm, addr, ptep)              do { } while (0)
-#define pte_update_defer(mm, addr, ptep)        do { } while (0)
-
-static inline void __init paravirt_pagetable_setup_start(pgd_t *base)
-{
-	native_pagetable_setup_start(base);
-}
-
-static inline void __init paravirt_pagetable_setup_done(pgd_t *base)
-{
-	native_pagetable_setup_done(base);
-}
-#endif	/* CONFIG_PARAVIRT */
-
-#endif	/* __ASSEMBLY__ */
-
-#ifdef CONFIG_X86_32
-# include "pgtable_32.h"
-#else
-# include "pgtable_64.h"
-#endif
-
-/*
- * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
- *
- * this macro returns the index of the entry in the pgd page which would
- * control the given virtual address
- */
-#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
-
-/*
- * pgd_offset() returns a (pgd_t *)
- * pgd_index() is used get the offset into the pgd page's array of pgd_t's;
- */
-#define pgd_offset(mm, address) ((mm)->pgd + pgd_index((address)))
-/*
- * a shortcut which implies the use of the kernel's pgd, instead
- * of a process's
- */
-#define pgd_offset_k(address) pgd_offset(&init_mm, (address))
-
-
-#define KERNEL_PGD_BOUNDARY	pgd_index(PAGE_OFFSET)
-#define KERNEL_PGD_PTRS		(PTRS_PER_PGD - KERNEL_PGD_BOUNDARY)
-
-#ifndef __ASSEMBLY__
-
-enum {
-	PG_LEVEL_NONE,
-	PG_LEVEL_4K,
-	PG_LEVEL_2M,
-	PG_LEVEL_1G,
-	PG_LEVEL_NUM
-};
-
-#ifdef CONFIG_PROC_FS
-extern void update_page_count(int level, unsigned long pages);
-#else
-static inline void update_page_count(int level, unsigned long pages) { }
-#endif
-
-/*
- * Helper function that returns the kernel pagetable entry controlling
- * the virtual address 'address'. NULL means no pagetable entry present.
- * NOTE: the return type is pte_t but if the pmd is PSE then we return it
- * as a pte too.
- */
-extern pte_t *lookup_address(unsigned long address, unsigned int *level);
-
-/* local pte updates need not use xchg for locking */
-static inline pte_t native_local_ptep_get_and_clear(pte_t *ptep)
-{
-	pte_t res = *ptep;
-
-	/* Pure native function needs no input for mm, addr */
-	native_pte_clear(NULL, 0, ptep);
-	return res;
-}
-
-static inline void native_set_pte_at(struct mm_struct *mm, unsigned long addr,
-				     pte_t *ptep , pte_t pte)
-{
-	native_set_pte(ptep, pte);
-}
-
-#ifndef CONFIG_PARAVIRT
-/*
- * Rules for using pte_update - it must be called after any PTE update which
- * has not been done using the set_pte / clear_pte interfaces.  It is used by
- * shadow mode hypervisors to resynchronize the shadow page tables.  Kernel PTE
- * updates should either be sets, clears, or set_pte_atomic for P->P
- * transitions, which means this hook should only be called for user PTEs.
- * This hook implies a P->P protection or access change has taken place, which
- * requires a subsequent TLB flush.  The notification can optionally be delayed
- * until the TLB flush event by using the pte_update_defer form of the
- * interface, but care must be taken to assure that the flush happens while
- * still holding the same page table lock so that the shadow and primary pages
- * do not become out of sync on SMP.
- */
-#define pte_update(mm, addr, ptep)		do { } while (0)
-#define pte_update_defer(mm, addr, ptep)	do { } while (0)
-#endif
-
-/*
- * We only update the dirty/accessed state if we set
- * the dirty bit by hand in the kernel, since the hardware
- * will do the accessed bit for us, and we don't want to
- * race with other CPU's that might be updating the dirty
- * bit at the same time.
- */
-struct vm_area_struct;
-
-#define  __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
-extern int ptep_set_access_flags(struct vm_area_struct *vma,
-				 unsigned long address, pte_t *ptep,
-				 pte_t entry, int dirty);
-
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
-extern int ptep_test_and_clear_young(struct vm_area_struct *vma,
-				     unsigned long addr, pte_t *ptep);
-
-#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
-extern int ptep_clear_flush_young(struct vm_area_struct *vma,
-				  unsigned long address, pte_t *ptep);
-
-#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
-static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
-				       pte_t *ptep)
-{
-	pte_t pte = native_ptep_get_and_clear(ptep);
-	pte_update(mm, addr, ptep);
-	return pte;
-}
-
-#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
-static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
-					    unsigned long addr, pte_t *ptep,
-					    int full)
-{
-	pte_t pte;
-	if (full) {
-		/*
-		 * Full address destruction in progress; paravirt does not
-		 * care about updates and native needs no locking
-		 */
-		pte = native_local_ptep_get_and_clear(ptep);
-	} else {
-		pte = ptep_get_and_clear(mm, addr, ptep);
-	}
-	return pte;
-}
-
-#define __HAVE_ARCH_PTEP_SET_WRPROTECT
-static inline void ptep_set_wrprotect(struct mm_struct *mm,
-				      unsigned long addr, pte_t *ptep)
-{
-	clear_bit(_PAGE_BIT_RW, (unsigned long *)&ptep->pte);
-	pte_update(mm, addr, ptep);
-}
-
-/*
- * clone_pgd_range(pgd_t *dst, pgd_t *src, int count);
- *
- *  dst - pointer to pgd range anwhere on a pgd page
- *  src - ""
- *  count - the number of pgds to copy.
- *
- * dst and src can be on the same page, but the range must not overlap,
- * and must not cross a page boundary.
- */
-static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count)
-{
-       memcpy(dst, src, count * sizeof(pgd_t));
-}
-
-
-#include <asm-generic/pgtable.h>
-#endif	/* __ASSEMBLY__ */
-
-#endif /* ASM_X86__PGTABLE_H */
diff --git a/include/asm-x86/pgtable_32.h b/include/asm-x86/pgtable_32.h
deleted file mode 100644
index 8de702dc7d62..000000000000
--- a/include/asm-x86/pgtable_32.h
+++ /dev/null
@@ -1,191 +0,0 @@
-#ifndef ASM_X86__PGTABLE_32_H
-#define ASM_X86__PGTABLE_32_H
-
-
-/*
- * The Linux memory management assumes a three-level page table setup. On
- * the i386, we use that, but "fold" the mid level into the top-level page
- * table, so that we physically have the same two-level page table as the
- * i386 mmu expects.
- *
- * This file contains the functions and defines necessary to modify and use
- * the i386 page table tree.
- */
-#ifndef __ASSEMBLY__
-#include <asm/processor.h>
-#include <asm/fixmap.h>
-#include <linux/threads.h>
-#include <asm/paravirt.h>
-
-#include <linux/bitops.h>
-#include <linux/slab.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-
-struct mm_struct;
-struct vm_area_struct;
-
-extern pgd_t swapper_pg_dir[1024];
-
-static inline void pgtable_cache_init(void) { }
-static inline void check_pgt_cache(void) { }
-void paging_init(void);
-
-extern void set_pmd_pfn(unsigned long, unsigned long, pgprot_t);
-
-/*
- * The Linux x86 paging architecture is 'compile-time dual-mode', it
- * implements both the traditional 2-level x86 page tables and the
- * newer 3-level PAE-mode page tables.
- */
-#ifdef CONFIG_X86_PAE
-# include <asm/pgtable-3level-defs.h>
-# define PMD_SIZE	(1UL << PMD_SHIFT)
-# define PMD_MASK	(~(PMD_SIZE - 1))
-#else
-# include <asm/pgtable-2level-defs.h>
-#endif
-
-#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
-#define PGDIR_MASK	(~(PGDIR_SIZE - 1))
-
-/* Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 8MB value just means that there will be a 8MB "hole" after the
- * physical memory until the kernel virtual memory starts.  That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- */
-#define VMALLOC_OFFSET	(8 * 1024 * 1024)
-#define VMALLOC_START	((unsigned long)high_memory + VMALLOC_OFFSET)
-#ifdef CONFIG_X86_PAE
-#define LAST_PKMAP 512
-#else
-#define LAST_PKMAP 1024
-#endif
-
-#define PKMAP_BASE ((FIXADDR_BOOT_START - PAGE_SIZE * (LAST_PKMAP + 1))	\
-		    & PMD_MASK)
-
-#ifdef CONFIG_HIGHMEM
-# define VMALLOC_END	(PKMAP_BASE - 2 * PAGE_SIZE)
-#else
-# define VMALLOC_END	(FIXADDR_START - 2 * PAGE_SIZE)
-#endif
-
-#define MAXMEM	(VMALLOC_END - PAGE_OFFSET - __VMALLOC_RESERVE)
-
-/*
- * Define this if things work differently on an i386 and an i486:
- * it will (on an i486) warn about kernel memory accesses that are
- * done without a 'access_ok(VERIFY_WRITE,..)'
- */
-#undef TEST_ACCESS_OK
-
-/* The boot page tables (all created as a single array) */
-extern unsigned long pg0[];
-
-#define pte_present(x)	((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
-
-/* To avoid harmful races, pmd_none(x) should check only the lower when PAE */
-#define pmd_none(x)	(!(unsigned long)pmd_val((x)))
-#define pmd_present(x)	(pmd_val((x)) & _PAGE_PRESENT)
-#define pmd_bad(x) ((pmd_val(x) & (PTE_FLAGS_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
-
-#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
-
-#ifdef CONFIG_X86_PAE
-# include <asm/pgtable-3level.h>
-#else
-# include <asm/pgtable-2level.h>
-#endif
-
-/*
- * Macro to mark a page protection value as "uncacheable".
- * On processors which do not support it, this is a no-op.
- */
-#define pgprot_noncached(prot)					\
-	((boot_cpu_data.x86 > 3)				\
-	 ? (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT))	\
-	 : (prot))
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-#define mk_pte(page, pgprot)	pfn_pte(page_to_pfn(page), (pgprot))
-
-
-static inline int pud_large(pud_t pud) { return 0; }
-
-/*
- * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD]
- *
- * this macro returns the index of the entry in the pmd page which would
- * control the given virtual address
- */
-#define pmd_index(address)				\
-	(((address) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
-
-/*
- * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
- *
- * this macro returns the index of the entry in the pte page which would
- * control the given virtual address
- */
-#define pte_index(address)					\
-	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#define pte_offset_kernel(dir, address)				\
-	((pte_t *)pmd_page_vaddr(*(dir)) +  pte_index((address)))
-
-#define pmd_page(pmd) (pfn_to_page(pmd_val((pmd)) >> PAGE_SHIFT))
-
-#define pmd_page_vaddr(pmd)					\
-	((unsigned long)__va(pmd_val((pmd)) & PTE_PFN_MASK))
-
-#if defined(CONFIG_HIGHPTE)
-#define pte_offset_map(dir, address)					\
-	((pte_t *)kmap_atomic_pte(pmd_page(*(dir)), KM_PTE0) +		\
-	 pte_index((address)))
-#define pte_offset_map_nested(dir, address)				\
-	((pte_t *)kmap_atomic_pte(pmd_page(*(dir)), KM_PTE1) +		\
-	 pte_index((address)))
-#define pte_unmap(pte) kunmap_atomic((pte), KM_PTE0)
-#define pte_unmap_nested(pte) kunmap_atomic((pte), KM_PTE1)
-#else
-#define pte_offset_map(dir, address)					\
-	((pte_t *)page_address(pmd_page(*(dir))) + pte_index((address)))
-#define pte_offset_map_nested(dir, address) pte_offset_map((dir), (address))
-#define pte_unmap(pte) do { } while (0)
-#define pte_unmap_nested(pte) do { } while (0)
-#endif
-
-/* Clear a kernel PTE and flush it from the TLB */
-#define kpte_clear_flush(ptep, vaddr)		\
-do {						\
-	pte_clear(&init_mm, (vaddr), (ptep));	\
-	__flush_tlb_one((vaddr));		\
-} while (0)
-
-/*
- * The i386 doesn't have any external MMU info: the kernel page
- * tables contain all the necessary information.
- */
-#define update_mmu_cache(vma, address, pte) do { } while (0)
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * kern_addr_valid() is (1) for FLATMEM and (0) for
- * SPARSEMEM and DISCONTIGMEM
- */
-#ifdef CONFIG_FLATMEM
-#define kern_addr_valid(addr)	(1)
-#else
-#define kern_addr_valid(kaddr)	(0)
-#endif
-
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)	\
-	remap_pfn_range(vma, vaddr, pfn, size, prot)
-
-#endif /* ASM_X86__PGTABLE_32_H */
diff --git a/include/asm-x86/pgtable_64.h b/include/asm-x86/pgtable_64.h
deleted file mode 100644
index fde9770e53d1..000000000000
--- a/include/asm-x86/pgtable_64.h
+++ /dev/null
@@ -1,285 +0,0 @@
-#ifndef ASM_X86__PGTABLE_64_H
-#define ASM_X86__PGTABLE_64_H
-
-#include <linux/const.h>
-#ifndef __ASSEMBLY__
-
-/*
- * This file contains the functions and defines necessary to modify and use
- * the x86-64 page table tree.
- */
-#include <asm/processor.h>
-#include <linux/bitops.h>
-#include <linux/threads.h>
-#include <asm/pda.h>
-
-extern pud_t level3_kernel_pgt[512];
-extern pud_t level3_ident_pgt[512];
-extern pmd_t level2_kernel_pgt[512];
-extern pmd_t level2_fixmap_pgt[512];
-extern pmd_t level2_ident_pgt[512];
-extern pgd_t init_level4_pgt[];
-
-#define swapper_pg_dir init_level4_pgt
-
-extern void paging_init(void);
-
-#endif /* !__ASSEMBLY__ */
-
-#define SHARED_KERNEL_PMD	0
-
-/*
- * PGDIR_SHIFT determines what a top-level page table entry can map
- */
-#define PGDIR_SHIFT	39
-#define PTRS_PER_PGD	512
-
-/*
- * 3rd level page
- */
-#define PUD_SHIFT	30
-#define PTRS_PER_PUD	512
-
-/*
- * PMD_SHIFT determines the size of the area a middle-level
- * page table can map
- */
-#define PMD_SHIFT	21
-#define PTRS_PER_PMD	512
-
-/*
- * entries per page directory level
- */
-#define PTRS_PER_PTE	512
-
-#ifndef __ASSEMBLY__
-
-#define pte_ERROR(e)					\
-	printk("%s:%d: bad pte %p(%016lx).\n",		\
-	       __FILE__, __LINE__, &(e), pte_val(e))
-#define pmd_ERROR(e)					\
-	printk("%s:%d: bad pmd %p(%016lx).\n",		\
-	       __FILE__, __LINE__, &(e), pmd_val(e))
-#define pud_ERROR(e)					\
-	printk("%s:%d: bad pud %p(%016lx).\n",		\
-	       __FILE__, __LINE__, &(e), pud_val(e))
-#define pgd_ERROR(e)					\
-	printk("%s:%d: bad pgd %p(%016lx).\n",		\
-	       __FILE__, __LINE__, &(e), pgd_val(e))
-
-#define pgd_none(x)	(!pgd_val(x))
-#define pud_none(x)	(!pud_val(x))
-
-struct mm_struct;
-
-void set_pte_vaddr_pud(pud_t *pud_page, unsigned long vaddr, pte_t new_pte);
-
-
-static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
-				    pte_t *ptep)
-{
-	*ptep = native_make_pte(0);
-}
-
-static inline void native_set_pte(pte_t *ptep, pte_t pte)
-{
-	*ptep = pte;
-}
-
-static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
-{
-	native_set_pte(ptep, pte);
-}
-
-static inline pte_t native_ptep_get_and_clear(pte_t *xp)
-{
-#ifdef CONFIG_SMP
-	return native_make_pte(xchg(&xp->pte, 0));
-#else
-	/* native_local_ptep_get_and_clear,
-	   but duplicated because of cyclic dependency */
-	pte_t ret = *xp;
-	native_pte_clear(NULL, 0, xp);
-	return ret;
-#endif
-}
-
-static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
-{
-	*pmdp = pmd;
-}
-
-static inline void native_pmd_clear(pmd_t *pmd)
-{
-	native_set_pmd(pmd, native_make_pmd(0));
-}
-
-static inline void native_set_pud(pud_t *pudp, pud_t pud)
-{
-	*pudp = pud;
-}
-
-static inline void native_pud_clear(pud_t *pud)
-{
-	native_set_pud(pud, native_make_pud(0));
-}
-
-static inline void native_set_pgd(pgd_t *pgdp, pgd_t pgd)
-{
-	*pgdp = pgd;
-}
-
-static inline void native_pgd_clear(pgd_t *pgd)
-{
-	native_set_pgd(pgd, native_make_pgd(0));
-}
-
-#define pte_same(a, b)		((a).pte == (b).pte)
-
-#endif /* !__ASSEMBLY__ */
-
-#define PMD_SIZE	(_AC(1, UL) << PMD_SHIFT)
-#define PMD_MASK	(~(PMD_SIZE - 1))
-#define PUD_SIZE	(_AC(1, UL) << PUD_SHIFT)
-#define PUD_MASK	(~(PUD_SIZE - 1))
-#define PGDIR_SIZE	(_AC(1, UL) << PGDIR_SHIFT)
-#define PGDIR_MASK	(~(PGDIR_SIZE - 1))
-
-
-#define MAXMEM		 _AC(0x00003fffffffffff, UL)
-#define VMALLOC_START    _AC(0xffffc20000000000, UL)
-#define VMALLOC_END      _AC(0xffffe1ffffffffff, UL)
-#define VMEMMAP_START	 _AC(0xffffe20000000000, UL)
-#define MODULES_VADDR    _AC(0xffffffffa0000000, UL)
-#define MODULES_END      _AC(0xffffffffff000000, UL)
-#define MODULES_LEN   (MODULES_END - MODULES_VADDR)
-
-#ifndef __ASSEMBLY__
-
-static inline int pgd_bad(pgd_t pgd)
-{
-	return (pgd_val(pgd) & ~(PTE_PFN_MASK | _PAGE_USER)) != _KERNPG_TABLE;
-}
-
-static inline int pud_bad(pud_t pud)
-{
-	return (pud_val(pud) & ~(PTE_PFN_MASK | _PAGE_USER)) != _KERNPG_TABLE;
-}
-
-static inline int pmd_bad(pmd_t pmd)
-{
-	return (pmd_val(pmd) & ~(PTE_PFN_MASK | _PAGE_USER)) != _KERNPG_TABLE;
-}
-
-#define pte_none(x)	(!pte_val((x)))
-#define pte_present(x)	(pte_val((x)) & (_PAGE_PRESENT | _PAGE_PROTNONE))
-
-#define pages_to_mb(x)	((x) >> (20 - PAGE_SHIFT))   /* FIXME: is this right? */
-
-/*
- * Macro to mark a page protection value as "uncacheable".
- */
-#define pgprot_noncached(prot)					\
-	(__pgprot(pgprot_val((prot)) | _PAGE_PCD | _PAGE_PWT))
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-
-/*
- * Level 4 access.
- */
-#define pgd_page_vaddr(pgd)						\
-	((unsigned long)__va((unsigned long)pgd_val((pgd)) & PTE_PFN_MASK))
-#define pgd_page(pgd)		(pfn_to_page(pgd_val((pgd)) >> PAGE_SHIFT))
-#define pgd_present(pgd) (pgd_val(pgd) & _PAGE_PRESENT)
-static inline int pgd_large(pgd_t pgd) { return 0; }
-#define mk_kernel_pgd(address) __pgd((address) | _KERNPG_TABLE)
-
-/* PUD - Level3 access */
-/* to find an entry in a page-table-directory. */
-#define pud_page_vaddr(pud)						\
-	((unsigned long)__va(pud_val((pud)) & PHYSICAL_PAGE_MASK))
-#define pud_page(pud)	(pfn_to_page(pud_val((pud)) >> PAGE_SHIFT))
-#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
-#define pud_offset(pgd, address)					\
-	((pud_t *)pgd_page_vaddr(*(pgd)) + pud_index((address)))
-#define pud_present(pud) (pud_val((pud)) & _PAGE_PRESENT)
-
-static inline int pud_large(pud_t pte)
-{
-	return (pud_val(pte) & (_PAGE_PSE | _PAGE_PRESENT)) ==
-		(_PAGE_PSE | _PAGE_PRESENT);
-}
-
-/* PMD  - Level 2 access */
-#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val((pmd)) & PTE_PFN_MASK))
-#define pmd_page(pmd)		(pfn_to_page(pmd_val((pmd)) >> PAGE_SHIFT))
-
-#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
-#define pmd_offset(dir, address) ((pmd_t *)pud_page_vaddr(*(dir)) + \
-				  pmd_index(address))
-#define pmd_none(x)	(!pmd_val((x)))
-#define pmd_present(x)	(pmd_val((x)) & _PAGE_PRESENT)
-#define pfn_pmd(nr, prot) (__pmd(((nr) << PAGE_SHIFT) | pgprot_val((prot))))
-#define pmd_pfn(x)  ((pmd_val((x)) & __PHYSICAL_MASK) >> PAGE_SHIFT)
-
-#define pte_to_pgoff(pte) ((pte_val((pte)) & PHYSICAL_PAGE_MASK) >> PAGE_SHIFT)
-#define pgoff_to_pte(off) ((pte_t) { .pte = ((off) << PAGE_SHIFT) |	\
-					    _PAGE_FILE })
-#define PTE_FILE_MAX_BITS __PHYSICAL_MASK_SHIFT
-
-/* PTE - Level 1 access. */
-
-/* page, protection -> pte */
-#define mk_pte(page, pgprot)	pfn_pte(page_to_pfn((page)), (pgprot))
-
-#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#define pte_offset_kernel(dir, address) ((pte_t *) pmd_page_vaddr(*(dir)) + \
-					 pte_index((address)))
-
-/* x86-64 always has all page tables mapped. */
-#define pte_offset_map(dir, address) pte_offset_kernel((dir), (address))
-#define pte_offset_map_nested(dir, address) pte_offset_kernel((dir), (address))
-#define pte_unmap(pte) /* NOP */
-#define pte_unmap_nested(pte) /* NOP */
-
-#define update_mmu_cache(vma, address, pte) do { } while (0)
-
-extern int direct_gbpages;
-
-/* Encode and de-code a swap entry */
-#define __swp_type(x)			(((x).val >> 1) & 0x3f)
-#define __swp_offset(x)			((x).val >> 8)
-#define __swp_entry(type, offset)	((swp_entry_t) { ((type) << 1) | \
-							 ((offset) << 8) })
-#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val((pte)) })
-#define __swp_entry_to_pte(x)		((pte_t) { .pte = (x).val })
-
-extern int kern_addr_valid(unsigned long addr);
-extern void cleanup_highmap(void);
-
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)	\
-	remap_pfn_range(vma, vaddr, pfn, size, prot)
-
-#define HAVE_ARCH_UNMAPPED_AREA
-#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
-
-#define pgtable_cache_init()   do { } while (0)
-#define check_pgt_cache()      do { } while (0)
-
-#define PAGE_AGP    PAGE_KERNEL_NOCACHE
-#define HAVE_PAGE_AGP 1
-
-/* fs/proc/kcore.c */
-#define	kc_vaddr_to_offset(v) ((v) & __VIRTUAL_MASK)
-#define	kc_offset_to_vaddr(o)				\
-	(((o) & (1UL << (__VIRTUAL_MASK_SHIFT - 1)))	\
-	 ? ((o) | ~__VIRTUAL_MASK)			\
-	 : (o))
-
-#define __HAVE_ARCH_PTE_SAME
-#endif /* !__ASSEMBLY__ */
-
-#endif /* ASM_X86__PGTABLE_64_H */
diff --git a/include/asm-x86/poll.h b/include/asm-x86/poll.h
deleted file mode 100644
index c98509d3149e..000000000000
--- a/include/asm-x86/poll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/poll.h>
diff --git a/include/asm-x86/posix_types.h b/include/asm-x86/posix_types.h
deleted file mode 100644
index bb7133dc155d..000000000000
--- a/include/asm-x86/posix_types.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifdef __KERNEL__
-# ifdef CONFIG_X86_32
-#  include "posix_types_32.h"
-# else
-#  include "posix_types_64.h"
-# endif
-#else
-# ifdef __i386__
-#  include "posix_types_32.h"
-# else
-#  include "posix_types_64.h"
-# endif
-#endif
diff --git a/include/asm-x86/posix_types_32.h b/include/asm-x86/posix_types_32.h
deleted file mode 100644
index 70cf2bb05939..000000000000
--- a/include/asm-x86/posix_types_32.h
+++ /dev/null
@@ -1,85 +0,0 @@
-#ifndef ASM_X86__POSIX_TYPES_32_H
-#define ASM_X86__POSIX_TYPES_32_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned long	__kernel_ino_t;
-typedef unsigned short	__kernel_mode_t;
-typedef unsigned short	__kernel_nlink_t;
-typedef long		__kernel_off_t;
-typedef int		__kernel_pid_t;
-typedef unsigned short	__kernel_ipc_pid_t;
-typedef unsigned short	__kernel_uid_t;
-typedef unsigned short	__kernel_gid_t;
-typedef unsigned int	__kernel_size_t;
-typedef int		__kernel_ssize_t;
-typedef int		__kernel_ptrdiff_t;
-typedef long		__kernel_time_t;
-typedef long		__kernel_suseconds_t;
-typedef long		__kernel_clock_t;
-typedef int		__kernel_timer_t;
-typedef int		__kernel_clockid_t;
-typedef int		__kernel_daddr_t;
-typedef char *		__kernel_caddr_t;
-typedef unsigned short	__kernel_uid16_t;
-typedef unsigned short	__kernel_gid16_t;
-typedef unsigned int	__kernel_uid32_t;
-typedef unsigned int	__kernel_gid32_t;
-
-typedef unsigned short	__kernel_old_uid_t;
-typedef unsigned short	__kernel_old_gid_t;
-typedef unsigned short	__kernel_old_dev_t;
-
-#ifdef __GNUC__
-typedef long long	__kernel_loff_t;
-#endif
-
-typedef struct {
-	int	val[2];
-} __kernel_fsid_t;
-
-#if defined(__KERNEL__)
-
-#undef	__FD_SET
-#define __FD_SET(fd,fdsetp)					\
-	asm volatile("btsl %1,%0":				\
-		     "+m" (*(__kernel_fd_set *)(fdsetp))	\
-		     : "r" ((int)(fd)))
-
-#undef	__FD_CLR
-#define __FD_CLR(fd,fdsetp)					\
-	asm volatile("btrl %1,%0":				\
-		     "+m" (*(__kernel_fd_set *)(fdsetp))	\
-		     : "r" ((int) (fd)))
-
-#undef	__FD_ISSET
-#define __FD_ISSET(fd,fdsetp)					\
-	(__extension__						\
-	 ({							\
-	 unsigned char __result;				\
-	 asm volatile("btl %1,%2 ; setb %0"			\
-		      : "=q" (__result)				\
-		      : "r" ((int)(fd)),			\
-			"m" (*(__kernel_fd_set *)(fdsetp)));	\
-	 __result;						\
-}))
-
-#undef	__FD_ZERO
-#define __FD_ZERO(fdsetp)					\
-do {								\
-	int __d0, __d1;						\
-	asm volatile("cld ; rep ; stosl"			\
-		     : "=m" (*(__kernel_fd_set *)(fdsetp)),	\
-		       "=&c" (__d0), "=&D" (__d1)		\
-		     : "a" (0), "1" (__FDSET_LONGS),		\
-		       "2" ((__kernel_fd_set *)(fdsetp))	\
-		     : "memory");				\
-} while (0)
-
-#endif /* defined(__KERNEL__) */
-
-#endif /* ASM_X86__POSIX_TYPES_32_H */
diff --git a/include/asm-x86/posix_types_64.h b/include/asm-x86/posix_types_64.h
deleted file mode 100644
index 388b4e7f4a44..000000000000
--- a/include/asm-x86/posix_types_64.h
+++ /dev/null
@@ -1,119 +0,0 @@
-#ifndef ASM_X86__POSIX_TYPES_64_H
-#define ASM_X86__POSIX_TYPES_64_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned long	__kernel_ino_t;
-typedef unsigned int	__kernel_mode_t;
-typedef unsigned long	__kernel_nlink_t;
-typedef long		__kernel_off_t;
-typedef int		__kernel_pid_t;
-typedef int		__kernel_ipc_pid_t;
-typedef unsigned int	__kernel_uid_t;
-typedef unsigned int	__kernel_gid_t;
-typedef unsigned long	__kernel_size_t;
-typedef long		__kernel_ssize_t;
-typedef long		__kernel_ptrdiff_t;
-typedef long		__kernel_time_t;
-typedef long		__kernel_suseconds_t;
-typedef long		__kernel_clock_t;
-typedef int		__kernel_timer_t;
-typedef int		__kernel_clockid_t;
-typedef int		__kernel_daddr_t;
-typedef char *		__kernel_caddr_t;
-typedef unsigned short	__kernel_uid16_t;
-typedef unsigned short	__kernel_gid16_t;
-
-#ifdef __GNUC__
-typedef long long	__kernel_loff_t;
-#endif
-
-typedef struct {
-	int	val[2];
-} __kernel_fsid_t;
-
-typedef unsigned short __kernel_old_uid_t;
-typedef unsigned short __kernel_old_gid_t;
-typedef __kernel_uid_t __kernel_uid32_t;
-typedef __kernel_gid_t __kernel_gid32_t;
-
-typedef unsigned long	__kernel_old_dev_t;
-
-#ifdef __KERNEL__
-
-#undef __FD_SET
-static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
-{
-	unsigned long _tmp = fd / __NFDBITS;
-	unsigned long _rem = fd % __NFDBITS;
-	fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
-}
-
-#undef __FD_CLR
-static inline void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
-{
-	unsigned long _tmp = fd / __NFDBITS;
-	unsigned long _rem = fd % __NFDBITS;
-	fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
-}
-
-#undef __FD_ISSET
-static inline int __FD_ISSET(unsigned long fd, __const__ __kernel_fd_set *p)
-{
-	unsigned long _tmp = fd / __NFDBITS;
-	unsigned long _rem = fd % __NFDBITS;
-	return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
-}
-
-/*
- * This will unroll the loop for the normal constant cases (8 or 32 longs,
- * for 256 and 1024-bit fd_sets respectively)
- */
-#undef __FD_ZERO
-static inline void __FD_ZERO(__kernel_fd_set *p)
-{
-	unsigned long *tmp = p->fds_bits;
-	int i;
-
-	if (__builtin_constant_p(__FDSET_LONGS)) {
-		switch (__FDSET_LONGS) {
-		case 32:
-			tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
-			tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
-			tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
-			tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
-			tmp[16] = 0; tmp[17] = 0; tmp[18] = 0; tmp[19] = 0;
-			tmp[20] = 0; tmp[21] = 0; tmp[22] = 0; tmp[23] = 0;
-			tmp[24] = 0; tmp[25] = 0; tmp[26] = 0; tmp[27] = 0;
-			tmp[28] = 0; tmp[29] = 0; tmp[30] = 0; tmp[31] = 0;
-			return;
-		case 16:
-			tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
-			tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
-			tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
-			tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
-			return;
-		case 8:
-			tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
-			tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
-			return;
-		case 4:
-			tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
-			return;
-		}
-	}
-	i = __FDSET_LONGS;
-	while (i) {
-		i--;
-		*tmp = 0;
-		tmp++;
-	}
-}
-
-#endif /* defined(__KERNEL__) */
-
-#endif /* ASM_X86__POSIX_TYPES_64_H */
diff --git a/include/asm-x86/prctl.h b/include/asm-x86/prctl.h
deleted file mode 100644
index e7ae34eb4103..000000000000
--- a/include/asm-x86/prctl.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef ASM_X86__PRCTL_H
-#define ASM_X86__PRCTL_H
-
-#define ARCH_SET_GS 0x1001
-#define ARCH_SET_FS 0x1002
-#define ARCH_GET_FS 0x1003
-#define ARCH_GET_GS 0x1004
-
-
-#endif /* ASM_X86__PRCTL_H */
diff --git a/include/asm-x86/processor-cyrix.h b/include/asm-x86/processor-cyrix.h
deleted file mode 100644
index 1198f2a0e42c..000000000000
--- a/include/asm-x86/processor-cyrix.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * NSC/Cyrix CPU indexed register access. Must be inlined instead of
- * macros to ensure correct access ordering
- * Access order is always 0x22 (=offset), 0x23 (=value)
- *
- * When using the old macros a line like
- *   setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);
- * gets expanded to:
- *  do {
- *    outb((CX86_CCR2), 0x22);
- *    outb((({
- *        outb((CX86_CCR2), 0x22);
- *        inb(0x23);
- *    }) | 0x88), 0x23);
- *  } while (0);
- *
- * which in fact violates the access order (= 0x22, 0x22, 0x23, 0x23).
- */
-
-static inline u8 getCx86(u8 reg)
-{
-	outb(reg, 0x22);
-	return inb(0x23);
-}
-
-static inline void setCx86(u8 reg, u8 data)
-{
-	outb(reg, 0x22);
-	outb(data, 0x23);
-}
-
-#define getCx86_old(reg) ({ outb((reg), 0x22); inb(0x23); })
-
-#define setCx86_old(reg, data) do { \
-	outb((reg), 0x22); \
-	outb((data), 0x23); \
-} while (0)
-
diff --git a/include/asm-x86/processor-flags.h b/include/asm-x86/processor-flags.h
deleted file mode 100644
index dc5f0712f9fa..000000000000
--- a/include/asm-x86/processor-flags.h
+++ /dev/null
@@ -1,100 +0,0 @@
-#ifndef ASM_X86__PROCESSOR_FLAGS_H
-#define ASM_X86__PROCESSOR_FLAGS_H
-/* Various flags defined: can be included from assembler. */
-
-/*
- * EFLAGS bits
- */
-#define X86_EFLAGS_CF	0x00000001 /* Carry Flag */
-#define X86_EFLAGS_PF	0x00000004 /* Parity Flag */
-#define X86_EFLAGS_AF	0x00000010 /* Auxillary carry Flag */
-#define X86_EFLAGS_ZF	0x00000040 /* Zero Flag */
-#define X86_EFLAGS_SF	0x00000080 /* Sign Flag */
-#define X86_EFLAGS_TF	0x00000100 /* Trap Flag */
-#define X86_EFLAGS_IF	0x00000200 /* Interrupt Flag */
-#define X86_EFLAGS_DF	0x00000400 /* Direction Flag */
-#define X86_EFLAGS_OF	0x00000800 /* Overflow Flag */
-#define X86_EFLAGS_IOPL	0x00003000 /* IOPL mask */
-#define X86_EFLAGS_NT	0x00004000 /* Nested Task */
-#define X86_EFLAGS_RF	0x00010000 /* Resume Flag */
-#define X86_EFLAGS_VM	0x00020000 /* Virtual Mode */
-#define X86_EFLAGS_AC	0x00040000 /* Alignment Check */
-#define X86_EFLAGS_VIF	0x00080000 /* Virtual Interrupt Flag */
-#define X86_EFLAGS_VIP	0x00100000 /* Virtual Interrupt Pending */
-#define X86_EFLAGS_ID	0x00200000 /* CPUID detection flag */
-
-/*
- * Basic CPU control in CR0
- */
-#define X86_CR0_PE	0x00000001 /* Protection Enable */
-#define X86_CR0_MP	0x00000002 /* Monitor Coprocessor */
-#define X86_CR0_EM	0x00000004 /* Emulation */
-#define X86_CR0_TS	0x00000008 /* Task Switched */
-#define X86_CR0_ET	0x00000010 /* Extension Type */
-#define X86_CR0_NE	0x00000020 /* Numeric Error */
-#define X86_CR0_WP	0x00010000 /* Write Protect */
-#define X86_CR0_AM	0x00040000 /* Alignment Mask */
-#define X86_CR0_NW	0x20000000 /* Not Write-through */
-#define X86_CR0_CD	0x40000000 /* Cache Disable */
-#define X86_CR0_PG	0x80000000 /* Paging */
-
-/*
- * Paging options in CR3
- */
-#define X86_CR3_PWT	0x00000008 /* Page Write Through */
-#define X86_CR3_PCD	0x00000010 /* Page Cache Disable */
-
-/*
- * Intel CPU features in CR4
- */
-#define X86_CR4_VME	0x00000001 /* enable vm86 extensions */
-#define X86_CR4_PVI	0x00000002 /* virtual interrupts flag enable */
-#define X86_CR4_TSD	0x00000004 /* disable time stamp at ipl 3 */
-#define X86_CR4_DE	0x00000008 /* enable debugging extensions */
-#define X86_CR4_PSE	0x00000010 /* enable page size extensions */
-#define X86_CR4_PAE	0x00000020 /* enable physical address extensions */
-#define X86_CR4_MCE	0x00000040 /* Machine check enable */
-#define X86_CR4_PGE	0x00000080 /* enable global pages */
-#define X86_CR4_PCE	0x00000100 /* enable performance counters at ipl 3 */
-#define X86_CR4_OSFXSR	0x00000200 /* enable fast FPU save and restore */
-#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
-#define X86_CR4_VMXE	0x00002000 /* enable VMX virtualization */
-#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
-
-/*
- * x86-64 Task Priority Register, CR8
- */
-#define X86_CR8_TPR	0x0000000F /* task priority register */
-
-/*
- * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
- */
-
-/*
- *      NSC/Cyrix CPU configuration register indexes
- */
-#define CX86_PCR0	0x20
-#define CX86_GCR	0xb8
-#define CX86_CCR0	0xc0
-#define CX86_CCR1	0xc1
-#define CX86_CCR2	0xc2
-#define CX86_CCR3	0xc3
-#define CX86_CCR4	0xe8
-#define CX86_CCR5	0xe9
-#define CX86_CCR6	0xea
-#define CX86_CCR7	0xeb
-#define CX86_PCR1	0xf0
-#define CX86_DIR0	0xfe
-#define CX86_DIR1	0xff
-#define CX86_ARR_BASE	0xc4
-#define CX86_RCR_BASE	0xdc
-
-#ifdef __KERNEL__
-#ifdef CONFIG_VM86
-#define X86_VM_MASK	X86_EFLAGS_VM
-#else
-#define X86_VM_MASK	0 /* No VM86 support */
-#endif
-#endif
-
-#endif /* ASM_X86__PROCESSOR_FLAGS_H */
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h
deleted file mode 100644
index ee7cbb30773a..000000000000
--- a/include/asm-x86/processor.h
+++ /dev/null
@@ -1,936 +0,0 @@
-#ifndef ASM_X86__PROCESSOR_H
-#define ASM_X86__PROCESSOR_H
-
-#include <asm/processor-flags.h>
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-struct mm_struct;
-
-#include <asm/vm86.h>
-#include <asm/math_emu.h>
-#include <asm/segment.h>
-#include <asm/types.h>
-#include <asm/sigcontext.h>
-#include <asm/current.h>
-#include <asm/cpufeature.h>
-#include <asm/system.h>
-#include <asm/page.h>
-#include <asm/percpu.h>
-#include <asm/msr.h>
-#include <asm/desc_defs.h>
-#include <asm/nops.h>
-#include <asm/ds.h>
-
-#include <linux/personality.h>
-#include <linux/cpumask.h>
-#include <linux/cache.h>
-#include <linux/threads.h>
-#include <linux/init.h>
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-static inline void *current_text_addr(void)
-{
-	void *pc;
-
-	asm volatile("mov $1f, %0; 1:":"=r" (pc));
-
-	return pc;
-}
-
-#ifdef CONFIG_X86_VSMP
-# define ARCH_MIN_TASKALIGN		(1 << INTERNODE_CACHE_SHIFT)
-# define ARCH_MIN_MMSTRUCT_ALIGN	(1 << INTERNODE_CACHE_SHIFT)
-#else
-# define ARCH_MIN_TASKALIGN		16
-# define ARCH_MIN_MMSTRUCT_ALIGN	0
-#endif
-
-/*
- *  CPU type and hardware bug flags. Kept separately for each CPU.
- *  Members of this structure are referenced in head.S, so think twice
- *  before touching them. [mj]
- */
-
-struct cpuinfo_x86 {
-	__u8			x86;		/* CPU family */
-	__u8			x86_vendor;	/* CPU vendor */
-	__u8			x86_model;
-	__u8			x86_mask;
-#ifdef CONFIG_X86_32
-	char			wp_works_ok;	/* It doesn't on 386's */
-
-	/* Problems on some 486Dx4's and old 386's: */
-	char			hlt_works_ok;
-	char			hard_math;
-	char			rfu;
-	char			fdiv_bug;
-	char			f00f_bug;
-	char			coma_bug;
-	char			pad0;
-#else
-	/* Number of 4K pages in DTLB/ITLB combined(in pages): */
-	int			 x86_tlbsize;
-	__u8			x86_virt_bits;
-	__u8			x86_phys_bits;
-#endif
-	/* CPUID returned core id bits: */
-	__u8			x86_coreid_bits;
-	/* Max extended CPUID function supported: */
-	__u32			extended_cpuid_level;
-	/* Maximum supported CPUID level, -1=no CPUID: */
-	int			cpuid_level;
-	__u32			x86_capability[NCAPINTS];
-	char			x86_vendor_id[16];
-	char			x86_model_id[64];
-	/* in KB - valid for CPUS which support this call: */
-	int			x86_cache_size;
-	int			x86_cache_alignment;	/* In bytes */
-	int			x86_power;
-	unsigned long		loops_per_jiffy;
-#ifdef CONFIG_SMP
-	/* cpus sharing the last level cache: */
-	cpumask_t		llc_shared_map;
-#endif
-	/* cpuid returned max cores value: */
-	u16			 x86_max_cores;
-	u16			apicid;
-	u16			initial_apicid;
-	u16			x86_clflush_size;
-#ifdef CONFIG_SMP
-	/* number of cores as seen by the OS: */
-	u16			booted_cores;
-	/* Physical processor id: */
-	u16			phys_proc_id;
-	/* Core id: */
-	u16			cpu_core_id;
-	/* Index into per_cpu list: */
-	u16			cpu_index;
-#endif
-} __attribute__((__aligned__(SMP_CACHE_BYTES)));
-
-#define X86_VENDOR_INTEL	0
-#define X86_VENDOR_CYRIX	1
-#define X86_VENDOR_AMD		2
-#define X86_VENDOR_UMC		3
-#define X86_VENDOR_CENTAUR	5
-#define X86_VENDOR_TRANSMETA	7
-#define X86_VENDOR_NSC		8
-#define X86_VENDOR_NUM		9
-
-#define X86_VENDOR_UNKNOWN	0xff
-
-/*
- * capabilities of CPUs
- */
-extern struct cpuinfo_x86	boot_cpu_data;
-extern struct cpuinfo_x86	new_cpu_data;
-
-extern struct tss_struct	doublefault_tss;
-extern __u32			cleared_cpu_caps[NCAPINTS];
-
-#ifdef CONFIG_SMP
-DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
-#define cpu_data(cpu)		per_cpu(cpu_info, cpu)
-#define current_cpu_data	__get_cpu_var(cpu_info)
-#else
-#define cpu_data(cpu)		boot_cpu_data
-#define current_cpu_data	boot_cpu_data
-#endif
-
-extern const struct seq_operations cpuinfo_op;
-
-static inline int hlt_works(int cpu)
-{
-#ifdef CONFIG_X86_32
-	return cpu_data(cpu).hlt_works_ok;
-#else
-	return 1;
-#endif
-}
-
-#define cache_line_size()	(boot_cpu_data.x86_cache_alignment)
-
-extern void cpu_detect(struct cpuinfo_x86 *c);
-
-extern struct pt_regs *idle_regs(struct pt_regs *);
-
-extern void early_cpu_init(void);
-extern void identify_boot_cpu(void);
-extern void identify_secondary_cpu(struct cpuinfo_x86 *);
-extern void print_cpu_info(struct cpuinfo_x86 *);
-extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
-extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
-extern unsigned short num_cache_leaves;
-
-extern void detect_extended_topology(struct cpuinfo_x86 *c);
-extern void detect_ht(struct cpuinfo_x86 *c);
-
-static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
-				unsigned int *ecx, unsigned int *edx)
-{
-	/* ecx is often an input as well as an output. */
-	asm("cpuid"
-	    : "=a" (*eax),
-	      "=b" (*ebx),
-	      "=c" (*ecx),
-	      "=d" (*edx)
-	    : "0" (*eax), "2" (*ecx));
-}
-
-static inline void load_cr3(pgd_t *pgdir)
-{
-	write_cr3(__pa(pgdir));
-}
-
-#ifdef CONFIG_X86_32
-/* This is the TSS defined by the hardware. */
-struct x86_hw_tss {
-	unsigned short		back_link, __blh;
-	unsigned long		sp0;
-	unsigned short		ss0, __ss0h;
-	unsigned long		sp1;
-	/* ss1 caches MSR_IA32_SYSENTER_CS: */
-	unsigned short		ss1, __ss1h;
-	unsigned long		sp2;
-	unsigned short		ss2, __ss2h;
-	unsigned long		__cr3;
-	unsigned long		ip;
-	unsigned long		flags;
-	unsigned long		ax;
-	unsigned long		cx;
-	unsigned long		dx;
-	unsigned long		bx;
-	unsigned long		sp;
-	unsigned long		bp;
-	unsigned long		si;
-	unsigned long		di;
-	unsigned short		es, __esh;
-	unsigned short		cs, __csh;
-	unsigned short		ss, __ssh;
-	unsigned short		ds, __dsh;
-	unsigned short		fs, __fsh;
-	unsigned short		gs, __gsh;
-	unsigned short		ldt, __ldth;
-	unsigned short		trace;
-	unsigned short		io_bitmap_base;
-
-} __attribute__((packed));
-#else
-struct x86_hw_tss {
-	u32			reserved1;
-	u64			sp0;
-	u64			sp1;
-	u64			sp2;
-	u64			reserved2;
-	u64			ist[7];
-	u32			reserved3;
-	u32			reserved4;
-	u16			reserved5;
-	u16			io_bitmap_base;
-
-} __attribute__((packed)) ____cacheline_aligned;
-#endif
-
-/*
- * IO-bitmap sizes:
- */
-#define IO_BITMAP_BITS			65536
-#define IO_BITMAP_BYTES			(IO_BITMAP_BITS/8)
-#define IO_BITMAP_LONGS			(IO_BITMAP_BYTES/sizeof(long))
-#define IO_BITMAP_OFFSET		offsetof(struct tss_struct, io_bitmap)
-#define INVALID_IO_BITMAP_OFFSET	0x8000
-#define INVALID_IO_BITMAP_OFFSET_LAZY	0x9000
-
-struct tss_struct {
-	/*
-	 * The hardware state:
-	 */
-	struct x86_hw_tss	x86_tss;
-
-	/*
-	 * The extra 1 is there because the CPU will access an
-	 * additional byte beyond the end of the IO permission
-	 * bitmap. The extra byte must be all 1 bits, and must
-	 * be within the limit.
-	 */
-	unsigned long		io_bitmap[IO_BITMAP_LONGS + 1];
-	/*
-	 * Cache the current maximum and the last task that used the bitmap:
-	 */
-	unsigned long		io_bitmap_max;
-	struct thread_struct	*io_bitmap_owner;
-
-	/*
-	 * .. and then another 0x100 bytes for the emergency kernel stack:
-	 */
-	unsigned long		stack[64];
-
-} ____cacheline_aligned;
-
-DECLARE_PER_CPU(struct tss_struct, init_tss);
-
-/*
- * Save the original ist values for checking stack pointers during debugging
- */
-struct orig_ist {
-	unsigned long		ist[7];
-};
-
-#define	MXCSR_DEFAULT		0x1f80
-
-struct i387_fsave_struct {
-	u32			cwd;	/* FPU Control Word		*/
-	u32			swd;	/* FPU Status Word		*/
-	u32			twd;	/* FPU Tag Word			*/
-	u32			fip;	/* FPU IP Offset		*/
-	u32			fcs;	/* FPU IP Selector		*/
-	u32			foo;	/* FPU Operand Pointer Offset	*/
-	u32			fos;	/* FPU Operand Pointer Selector	*/
-
-	/* 8*10 bytes for each FP-reg = 80 bytes:			*/
-	u32			st_space[20];
-
-	/* Software status information [not touched by FSAVE ]:		*/
-	u32			status;
-};
-
-struct i387_fxsave_struct {
-	u16			cwd; /* Control Word			*/
-	u16			swd; /* Status Word			*/
-	u16			twd; /* Tag Word			*/
-	u16			fop; /* Last Instruction Opcode		*/
-	union {
-		struct {
-			u64	rip; /* Instruction Pointer		*/
-			u64	rdp; /* Data Pointer			*/
-		};
-		struct {
-			u32	fip; /* FPU IP Offset			*/
-			u32	fcs; /* FPU IP Selector			*/
-			u32	foo; /* FPU Operand Offset		*/
-			u32	fos; /* FPU Operand Selector		*/
-		};
-	};
-	u32			mxcsr;		/* MXCSR Register State */
-	u32			mxcsr_mask;	/* MXCSR Mask		*/
-
-	/* 8*16 bytes for each FP-reg = 128 bytes:			*/
-	u32			st_space[32];
-
-	/* 16*16 bytes for each XMM-reg = 256 bytes:			*/
-	u32			xmm_space[64];
-
-	u32			padding[12];
-
-	union {
-		u32		padding1[12];
-		u32		sw_reserved[12];
-	};
-
-} __attribute__((aligned(16)));
-
-struct i387_soft_struct {
-	u32			cwd;
-	u32			swd;
-	u32			twd;
-	u32			fip;
-	u32			fcs;
-	u32			foo;
-	u32			fos;
-	/* 8*10 bytes for each FP-reg = 80 bytes: */
-	u32			st_space[20];
-	u8			ftop;
-	u8			changed;
-	u8			lookahead;
-	u8			no_update;
-	u8			rm;
-	u8			alimit;
-	struct info		*info;
-	u32			entry_eip;
-};
-
-struct xsave_hdr_struct {
-	u64 xstate_bv;
-	u64 reserved1[2];
-	u64 reserved2[5];
-} __attribute__((packed));
-
-struct xsave_struct {
-	struct i387_fxsave_struct i387;
-	struct xsave_hdr_struct xsave_hdr;
-	/* new processor state extensions will go here */
-} __attribute__ ((packed, aligned (64)));
-
-union thread_xstate {
-	struct i387_fsave_struct	fsave;
-	struct i387_fxsave_struct	fxsave;
-	struct i387_soft_struct		soft;
-	struct xsave_struct		xsave;
-};
-
-#ifdef CONFIG_X86_64
-DECLARE_PER_CPU(struct orig_ist, orig_ist);
-#endif
-
-extern void print_cpu_info(struct cpuinfo_x86 *);
-extern unsigned int xstate_size;
-extern void free_thread_xstate(struct task_struct *);
-extern struct kmem_cache *task_xstate_cachep;
-extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
-extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
-extern unsigned short num_cache_leaves;
-
-struct thread_struct {
-	/* Cached TLS descriptors: */
-	struct desc_struct	tls_array[GDT_ENTRY_TLS_ENTRIES];
-	unsigned long		sp0;
-	unsigned long		sp;
-#ifdef CONFIG_X86_32
-	unsigned long		sysenter_cs;
-#else
-	unsigned long		usersp;	/* Copy from PDA */
-	unsigned short		es;
-	unsigned short		ds;
-	unsigned short		fsindex;
-	unsigned short		gsindex;
-#endif
-	unsigned long		ip;
-	unsigned long		fs;
-	unsigned long		gs;
-	/* Hardware debugging registers: */
-	unsigned long		debugreg0;
-	unsigned long		debugreg1;
-	unsigned long		debugreg2;
-	unsigned long		debugreg3;
-	unsigned long		debugreg6;
-	unsigned long		debugreg7;
-	/* Fault info: */
-	unsigned long		cr2;
-	unsigned long		trap_no;
-	unsigned long		error_code;
-	/* floating point and extended processor state */
-	union thread_xstate	*xstate;
-#ifdef CONFIG_X86_32
-	/* Virtual 86 mode info */
-	struct vm86_struct __user *vm86_info;
-	unsigned long		screen_bitmap;
-	unsigned long		v86flags;
-	unsigned long		v86mask;
-	unsigned long		saved_sp0;
-	unsigned int		saved_fs;
-	unsigned int		saved_gs;
-#endif
-	/* IO permissions: */
-	unsigned long		*io_bitmap_ptr;
-	unsigned long		iopl;
-	/* Max allowed port in the bitmap, in bytes: */
-	unsigned		io_bitmap_max;
-/* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set.  */
-	unsigned long	debugctlmsr;
-#ifdef CONFIG_X86_DS
-/* Debug Store context; see include/asm-x86/ds.h; goes into MSR_IA32_DS_AREA */
-	struct ds_context	*ds_ctx;
-#endif /* CONFIG_X86_DS */
-#ifdef CONFIG_X86_PTRACE_BTS
-/* the signal to send on a bts buffer overflow */
-	unsigned int	bts_ovfl_signal;
-#endif /* CONFIG_X86_PTRACE_BTS */
-};
-
-static inline unsigned long native_get_debugreg(int regno)
-{
-	unsigned long val = 0;	/* Damn you, gcc! */
-
-	switch (regno) {
-	case 0:
-		asm("mov %%db0, %0" :"=r" (val));
-		break;
-	case 1:
-		asm("mov %%db1, %0" :"=r" (val));
-		break;
-	case 2:
-		asm("mov %%db2, %0" :"=r" (val));
-		break;
-	case 3:
-		asm("mov %%db3, %0" :"=r" (val));
-		break;
-	case 6:
-		asm("mov %%db6, %0" :"=r" (val));
-		break;
-	case 7:
-		asm("mov %%db7, %0" :"=r" (val));
-		break;
-	default:
-		BUG();
-	}
-	return val;
-}
-
-static inline void native_set_debugreg(int regno, unsigned long value)
-{
-	switch (regno) {
-	case 0:
-		asm("mov %0, %%db0"	::"r" (value));
-		break;
-	case 1:
-		asm("mov %0, %%db1"	::"r" (value));
-		break;
-	case 2:
-		asm("mov %0, %%db2"	::"r" (value));
-		break;
-	case 3:
-		asm("mov %0, %%db3"	::"r" (value));
-		break;
-	case 6:
-		asm("mov %0, %%db6"	::"r" (value));
-		break;
-	case 7:
-		asm("mov %0, %%db7"	::"r" (value));
-		break;
-	default:
-		BUG();
-	}
-}
-
-/*
- * Set IOPL bits in EFLAGS from given mask
- */
-static inline void native_set_iopl_mask(unsigned mask)
-{
-#ifdef CONFIG_X86_32
-	unsigned int reg;
-
-	asm volatile ("pushfl;"
-		      "popl %0;"
-		      "andl %1, %0;"
-		      "orl %2, %0;"
-		      "pushl %0;"
-		      "popfl"
-		      : "=&r" (reg)
-		      : "i" (~X86_EFLAGS_IOPL), "r" (mask));
-#endif
-}
-
-static inline void
-native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
-{
-	tss->x86_tss.sp0 = thread->sp0;
-#ifdef CONFIG_X86_32
-	/* Only happens when SEP is enabled, no need to test "SEP"arately: */
-	if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
-		tss->x86_tss.ss1 = thread->sysenter_cs;
-		wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
-	}
-#endif
-}
-
-static inline void native_swapgs(void)
-{
-#ifdef CONFIG_X86_64
-	asm volatile("swapgs" ::: "memory");
-#endif
-}
-
-#ifdef CONFIG_PARAVIRT
-#include <asm/paravirt.h>
-#else
-#define __cpuid			native_cpuid
-#define paravirt_enabled()	0
-
-/*
- * These special macros can be used to get or set a debugging register
- */
-#define get_debugreg(var, register)				\
-	(var) = native_get_debugreg(register)
-#define set_debugreg(value, register)				\
-	native_set_debugreg(register, value)
-
-static inline void load_sp0(struct tss_struct *tss,
-			    struct thread_struct *thread)
-{
-	native_load_sp0(tss, thread);
-}
-
-#define set_iopl_mask native_set_iopl_mask
-#endif /* CONFIG_PARAVIRT */
-
-/*
- * Save the cr4 feature set we're using (ie
- * Pentium 4MB enable and PPro Global page
- * enable), so that any CPU's that boot up
- * after us can get the correct flags.
- */
-extern unsigned long		mmu_cr4_features;
-
-static inline void set_in_cr4(unsigned long mask)
-{
-	unsigned cr4;
-
-	mmu_cr4_features |= mask;
-	cr4 = read_cr4();
-	cr4 |= mask;
-	write_cr4(cr4);
-}
-
-static inline void clear_in_cr4(unsigned long mask)
-{
-	unsigned cr4;
-
-	mmu_cr4_features &= ~mask;
-	cr4 = read_cr4();
-	cr4 &= ~mask;
-	write_cr4(cr4);
-}
-
-typedef struct {
-	unsigned long		seg;
-} mm_segment_t;
-
-
-/*
- * create a kernel thread without removing it from tasklists
- */
-extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
-
-/* Free all resources held by a thread. */
-extern void release_thread(struct task_struct *);
-
-/* Prepare to copy thread state - unlazy all lazy state */
-extern void prepare_to_copy(struct task_struct *tsk);
-
-unsigned long get_wchan(struct task_struct *p);
-
-/*
- * Generic CPUID function
- * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
- * resulting in stale register contents being returned.
- */
-static inline void cpuid(unsigned int op,
-			 unsigned int *eax, unsigned int *ebx,
-			 unsigned int *ecx, unsigned int *edx)
-{
-	*eax = op;
-	*ecx = 0;
-	__cpuid(eax, ebx, ecx, edx);
-}
-
-/* Some CPUID calls want 'count' to be placed in ecx */
-static inline void cpuid_count(unsigned int op, int count,
-			       unsigned int *eax, unsigned int *ebx,
-			       unsigned int *ecx, unsigned int *edx)
-{
-	*eax = op;
-	*ecx = count;
-	__cpuid(eax, ebx, ecx, edx);
-}
-
-/*
- * CPUID functions returning a single datum
- */
-static inline unsigned int cpuid_eax(unsigned int op)
-{
-	unsigned int eax, ebx, ecx, edx;
-
-	cpuid(op, &eax, &ebx, &ecx, &edx);
-
-	return eax;
-}
-
-static inline unsigned int cpuid_ebx(unsigned int op)
-{
-	unsigned int eax, ebx, ecx, edx;
-
-	cpuid(op, &eax, &ebx, &ecx, &edx);
-
-	return ebx;
-}
-
-static inline unsigned int cpuid_ecx(unsigned int op)
-{
-	unsigned int eax, ebx, ecx, edx;
-
-	cpuid(op, &eax, &ebx, &ecx, &edx);
-
-	return ecx;
-}
-
-static inline unsigned int cpuid_edx(unsigned int op)
-{
-	unsigned int eax, ebx, ecx, edx;
-
-	cpuid(op, &eax, &ebx, &ecx, &edx);
-
-	return edx;
-}
-
-/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
-static inline void rep_nop(void)
-{
-	asm volatile("rep; nop" ::: "memory");
-}
-
-static inline void cpu_relax(void)
-{
-	rep_nop();
-}
-
-/* Stop speculative execution: */
-static inline void sync_core(void)
-{
-	int tmp;
-
-	asm volatile("cpuid" : "=a" (tmp) : "0" (1)
-		     : "ebx", "ecx", "edx", "memory");
-}
-
-static inline void __monitor(const void *eax, unsigned long ecx,
-			     unsigned long edx)
-{
-	/* "monitor %eax, %ecx, %edx;" */
-	asm volatile(".byte 0x0f, 0x01, 0xc8;"
-		     :: "a" (eax), "c" (ecx), "d"(edx));
-}
-
-static inline void __mwait(unsigned long eax, unsigned long ecx)
-{
-	/* "mwait %eax, %ecx;" */
-	asm volatile(".byte 0x0f, 0x01, 0xc9;"
-		     :: "a" (eax), "c" (ecx));
-}
-
-static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
-{
-	trace_hardirqs_on();
-	/* "mwait %eax, %ecx;" */
-	asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
-		     :: "a" (eax), "c" (ecx));
-}
-
-extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
-
-extern void select_idle_routine(const struct cpuinfo_x86 *c);
-
-extern unsigned long		boot_option_idle_override;
-extern unsigned long		idle_halt;
-extern unsigned long		idle_nomwait;
-
-/*
- * on systems with caches, caches must be flashed as the absolute
- * last instruction before going into a suspended halt.  Otherwise,
- * dirty data can linger in the cache and become stale on resume,
- * leading to strange errors.
- *
- * perform a variety of operations to guarantee that the compiler
- * will not reorder instructions.  wbinvd itself is serializing
- * so the processor will not reorder.
- *
- * Systems without cache can just go into halt.
- */
-static inline void wbinvd_halt(void)
-{
-	mb();
-	/* check for clflush to determine if wbinvd is legal */
-	if (cpu_has_clflush)
-		asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
-	else
-		while (1)
-			halt();
-}
-
-extern void enable_sep_cpu(void);
-extern int sysenter_setup(void);
-
-/* Defined in head.S */
-extern struct desc_ptr		early_gdt_descr;
-
-extern void cpu_set_gdt(int);
-extern void switch_to_new_gdt(void);
-extern void cpu_init(void);
-extern void init_gdt(int cpu);
-
-static inline void update_debugctlmsr(unsigned long debugctlmsr)
-{
-#ifndef CONFIG_X86_DEBUGCTLMSR
-	if (boot_cpu_data.x86 < 6)
-		return;
-#endif
-	wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
-}
-
-/*
- * from system description table in BIOS. Mostly for MCA use, but
- * others may find it useful:
- */
-extern unsigned int		machine_id;
-extern unsigned int		machine_submodel_id;
-extern unsigned int		BIOS_revision;
-
-/* Boot loader type from the setup header: */
-extern int			bootloader_type;
-
-extern char			ignore_fpu_irq;
-
-#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
-#define ARCH_HAS_PREFETCHW
-#define ARCH_HAS_SPINLOCK_PREFETCH
-
-#ifdef CONFIG_X86_32
-# define BASE_PREFETCH		ASM_NOP4
-# define ARCH_HAS_PREFETCH
-#else
-# define BASE_PREFETCH		"prefetcht0 (%1)"
-#endif
-
-/*
- * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
- *
- * It's not worth to care about 3dnow prefetches for the K6
- * because they are microcoded there and very slow.
- */
-static inline void prefetch(const void *x)
-{
-	alternative_input(BASE_PREFETCH,
-			  "prefetchnta (%1)",
-			  X86_FEATURE_XMM,
-			  "r" (x));
-}
-
-/*
- * 3dnow prefetch to get an exclusive cache line.
- * Useful for spinlocks to avoid one state transition in the
- * cache coherency protocol:
- */
-static inline void prefetchw(const void *x)
-{
-	alternative_input(BASE_PREFETCH,
-			  "prefetchw (%1)",
-			  X86_FEATURE_3DNOW,
-			  "r" (x));
-}
-
-static inline void spin_lock_prefetch(const void *x)
-{
-	prefetchw(x);
-}
-
-#ifdef CONFIG_X86_32
-/*
- * User space process size: 3GB (default).
- */
-#define TASK_SIZE		PAGE_OFFSET
-#define STACK_TOP		TASK_SIZE
-#define STACK_TOP_MAX		STACK_TOP
-
-#define INIT_THREAD  {							  \
-	.sp0			= sizeof(init_stack) + (long)&init_stack, \
-	.vm86_info		= NULL,					  \
-	.sysenter_cs		= __KERNEL_CS,				  \
-	.io_bitmap_ptr		= NULL,					  \
-	.fs			= __KERNEL_PERCPU,			  \
-}
-
-/*
- * Note that the .io_bitmap member must be extra-big. This is because
- * the CPU will access an additional byte beyond the end of the IO
- * permission bitmap. The extra byte must be all 1 bits, and must
- * be within the limit.
- */
-#define INIT_TSS  {							  \
-	.x86_tss = {							  \
-		.sp0		= sizeof(init_stack) + (long)&init_stack, \
-		.ss0		= __KERNEL_DS,				  \
-		.ss1		= __KERNEL_CS,				  \
-		.io_bitmap_base	= INVALID_IO_BITMAP_OFFSET,		  \
-	 },								  \
-	.io_bitmap		= { [0 ... IO_BITMAP_LONGS] = ~0 },	  \
-}
-
-extern unsigned long thread_saved_pc(struct task_struct *tsk);
-
-#define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
-#define KSTK_TOP(info)                                                 \
-({                                                                     \
-       unsigned long *__ptr = (unsigned long *)(info);                 \
-       (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
-})
-
-/*
- * The below -8 is to reserve 8 bytes on top of the ring0 stack.
- * This is necessary to guarantee that the entire "struct pt_regs"
- * is accessable even if the CPU haven't stored the SS/ESP registers
- * on the stack (interrupt gate does not save these registers
- * when switching to the same priv ring).
- * Therefore beware: accessing the ss/esp fields of the
- * "struct pt_regs" is possible, but they may contain the
- * completely wrong values.
- */
-#define task_pt_regs(task)                                             \
-({                                                                     \
-       struct pt_regs *__regs__;                                       \
-       __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
-       __regs__ - 1;                                                   \
-})
-
-#define KSTK_ESP(task)		(task_pt_regs(task)->sp)
-
-#else
-/*
- * User space process size. 47bits minus one guard page.
- */
-#define TASK_SIZE64	((1UL << 47) - PAGE_SIZE)
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define IA32_PAGE_OFFSET	((current->personality & ADDR_LIMIT_3GB) ? \
-					0xc0000000 : 0xFFFFe000)
-
-#define TASK_SIZE		(test_thread_flag(TIF_IA32) ? \
-					IA32_PAGE_OFFSET : TASK_SIZE64)
-#define TASK_SIZE_OF(child)	((test_tsk_thread_flag(child, TIF_IA32)) ? \
-					IA32_PAGE_OFFSET : TASK_SIZE64)
-
-#define STACK_TOP		TASK_SIZE
-#define STACK_TOP_MAX		TASK_SIZE64
-
-#define INIT_THREAD  { \
-	.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
-}
-
-#define INIT_TSS  { \
-	.x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
-}
-
-/*
- * Return saved PC of a blocked thread.
- * What is this good for? it will be always the scheduler or ret_from_fork.
- */
-#define thread_saved_pc(t)	(*(unsigned long *)((t)->thread.sp - 8))
-
-#define task_pt_regs(tsk)	((struct pt_regs *)(tsk)->thread.sp0 - 1)
-#define KSTK_ESP(tsk)		-1 /* sorry. doesn't work for syscall. */
-#endif /* CONFIG_X86_64 */
-
-extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
-					       unsigned long new_sp);
-
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE	(PAGE_ALIGN(TASK_SIZE / 3))
-
-#define KSTK_EIP(task)		(task_pt_regs(task)->ip)
-
-/* Get/set a process' ability to use the timestamp counter instruction */
-#define GET_TSC_CTL(adr)	get_tsc_mode((adr))
-#define SET_TSC_CTL(val)	set_tsc_mode((val))
-
-extern int get_tsc_mode(unsigned long adr);
-extern int set_tsc_mode(unsigned int val);
-
-#endif /* ASM_X86__PROCESSOR_H */
diff --git a/include/asm-x86/proto.h b/include/asm-x86/proto.h
deleted file mode 100644
index 6e89e8b4de0e..000000000000
--- a/include/asm-x86/proto.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef ASM_X86__PROTO_H
-#define ASM_X86__PROTO_H
-
-#include <asm/ldt.h>
-
-/* misc architecture specific prototypes */
-
-extern void early_idt_handler(void);
-
-extern void system_call(void);
-extern void syscall_init(void);
-
-extern void ia32_syscall(void);
-extern void ia32_cstar_target(void);
-extern void ia32_sysenter_target(void);
-
-extern void syscall32_cpu_init(void);
-
-extern void check_efer(void);
-
-#ifdef CONFIG_X86_BIOS_REBOOT
-extern int reboot_force;
-#else
-static const int reboot_force = 0;
-#endif
-
-long do_arch_prctl(struct task_struct *task, int code, unsigned long addr);
-
-#define round_up(x, y) (((x) + (y) - 1) & ~((y) - 1))
-#define round_down(x, y) ((x) & ~((y) - 1))
-
-#endif /* ASM_X86__PROTO_H */
diff --git a/include/asm-x86/ptrace-abi.h b/include/asm-x86/ptrace-abi.h
deleted file mode 100644
index 4298b8882a78..000000000000
--- a/include/asm-x86/ptrace-abi.h
+++ /dev/null
@@ -1,145 +0,0 @@
-#ifndef ASM_X86__PTRACE_ABI_H
-#define ASM_X86__PTRACE_ABI_H
-
-#ifdef __i386__
-
-#define EBX 0
-#define ECX 1
-#define EDX 2
-#define ESI 3
-#define EDI 4
-#define EBP 5
-#define EAX 6
-#define DS 7
-#define ES 8
-#define FS 9
-#define GS 10
-#define ORIG_EAX 11
-#define EIP 12
-#define CS  13
-#define EFL 14
-#define UESP 15
-#define SS   16
-#define FRAME_SIZE 17
-
-#else /* __i386__ */
-
-#if defined(__ASSEMBLY__) || defined(__FRAME_OFFSETS)
-#define R15 0
-#define R14 8
-#define R13 16
-#define R12 24
-#define RBP 32
-#define RBX 40
-/* arguments: interrupts/non tracing syscalls only save upto here*/
-#define R11 48
-#define R10 56
-#define R9 64
-#define R8 72
-#define RAX 80
-#define RCX 88
-#define RDX 96
-#define RSI 104
-#define RDI 112
-#define ORIG_RAX 120       /* = ERROR */
-/* end of arguments */
-/* cpu exception frame or undefined in case of fast syscall. */
-#define RIP 128
-#define CS 136
-#define EFLAGS 144
-#define RSP 152
-#define SS 160
-#define ARGOFFSET R11
-#endif /* __ASSEMBLY__ */
-
-/* top of stack page */
-#define FRAME_SIZE 168
-
-#endif /* !__i386__ */
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS            12
-#define PTRACE_SETREGS            13
-#define PTRACE_GETFPREGS          14
-#define PTRACE_SETFPREGS          15
-#define PTRACE_GETFPXREGS         18
-#define PTRACE_SETFPXREGS         19
-
-#define PTRACE_OLDSETOPTIONS      21
-
-/* only useful for access 32bit programs / kernels */
-#define PTRACE_GET_THREAD_AREA    25
-#define PTRACE_SET_THREAD_AREA    26
-
-#ifdef __x86_64__
-# define PTRACE_ARCH_PRCTL	  30
-#endif
-
-#define PTRACE_SYSEMU		  31
-#define PTRACE_SYSEMU_SINGLESTEP  32
-
-#define PTRACE_SINGLEBLOCK	33	/* resume execution until next branch */
-
-#ifdef CONFIG_X86_PTRACE_BTS
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-
-/* configuration/status structure used in PTRACE_BTS_CONFIG and
-   PTRACE_BTS_STATUS commands.
-*/
-struct ptrace_bts_config {
-	/* requested or actual size of BTS buffer in bytes */
-	__u32 size;
-	/* bitmask of below flags */
-	__u32 flags;
-	/* buffer overflow signal */
-	__u32 signal;
-	/* actual size of bts_struct in bytes */
-	__u32 bts_size;
-};
-#endif /* __ASSEMBLY__ */
-
-#define PTRACE_BTS_O_TRACE	0x1 /* branch trace */
-#define PTRACE_BTS_O_SCHED	0x2 /* scheduling events w/ jiffies */
-#define PTRACE_BTS_O_SIGNAL     0x4 /* send SIG<signal> on buffer overflow
-				       instead of wrapping around */
-#define PTRACE_BTS_O_ALLOC	0x8 /* (re)allocate buffer */
-
-#define PTRACE_BTS_CONFIG	40
-/* Configure branch trace recording.
-   ADDR points to a struct ptrace_bts_config.
-   DATA gives the size of that buffer.
-   A new buffer is allocated, if requested in the flags.
-   An overflow signal may only be requested for new buffers.
-   Returns the number of bytes read.
-*/
-#define PTRACE_BTS_STATUS	41
-/* Return the current configuration in a struct ptrace_bts_config
-   pointed to by ADDR; DATA gives the size of that buffer.
-   Returns the number of bytes written.
-*/
-#define PTRACE_BTS_SIZE		42
-/* Return the number of available BTS records for draining.
-   DATA and ADDR are ignored.
-*/
-#define PTRACE_BTS_GET		43
-/* Get a single BTS record.
-   DATA defines the index into the BTS array, where 0 is the newest
-   entry, and higher indices refer to older entries.
-   ADDR is pointing to struct bts_struct (see asm/ds.h).
-*/
-#define PTRACE_BTS_CLEAR	44
-/* Clear the BTS buffer.
-   DATA and ADDR are ignored.
-*/
-#define PTRACE_BTS_DRAIN	45
-/* Read all available BTS records and clear the buffer.
-   ADDR points to an array of struct bts_struct.
-   DATA gives the size of that buffer.
-   BTS records are read from oldest to newest.
-   Returns number of BTS records drained.
-*/
-#endif /* CONFIG_X86_PTRACE_BTS */
-
-#endif /* ASM_X86__PTRACE_ABI_H */
diff --git a/include/asm-x86/ptrace.h b/include/asm-x86/ptrace.h
deleted file mode 100644
index a2025525a15a..000000000000
--- a/include/asm-x86/ptrace.h
+++ /dev/null
@@ -1,280 +0,0 @@
-#ifndef ASM_X86__PTRACE_H
-#define ASM_X86__PTRACE_H
-
-#include <linux/compiler.h>	/* For __user */
-#include <asm/ptrace-abi.h>
-#include <asm/processor-flags.h>
-
-#ifdef __KERNEL__
-#include <asm/ds.h>		/* the DS BTS struct is used for ptrace too */
-#include <asm/segment.h>
-#endif
-
-#ifndef __ASSEMBLY__
-
-#ifdef __i386__
-/* this struct defines the way the registers are stored on the
-   stack during a system call. */
-
-#ifndef __KERNEL__
-
-struct pt_regs {
-	long ebx;
-	long ecx;
-	long edx;
-	long esi;
-	long edi;
-	long ebp;
-	long eax;
-	int  xds;
-	int  xes;
-	int  xfs;
-	/* int  gs; */
-	long orig_eax;
-	long eip;
-	int  xcs;
-	long eflags;
-	long esp;
-	int  xss;
-};
-
-#else /* __KERNEL__ */
-
-struct pt_regs {
-	unsigned long bx;
-	unsigned long cx;
-	unsigned long dx;
-	unsigned long si;
-	unsigned long di;
-	unsigned long bp;
-	unsigned long ax;
-	unsigned long ds;
-	unsigned long es;
-	unsigned long fs;
-	/* int  gs; */
-	unsigned long orig_ax;
-	unsigned long ip;
-	unsigned long cs;
-	unsigned long flags;
-	unsigned long sp;
-	unsigned long ss;
-};
-
-#endif /* __KERNEL__ */
-
-#else /* __i386__ */
-
-#ifndef __KERNEL__
-
-struct pt_regs {
-	unsigned long r15;
-	unsigned long r14;
-	unsigned long r13;
-	unsigned long r12;
-	unsigned long rbp;
-	unsigned long rbx;
-/* arguments: non interrupts/non tracing syscalls only save upto here*/
-	unsigned long r11;
-	unsigned long r10;
-	unsigned long r9;
-	unsigned long r8;
-	unsigned long rax;
-	unsigned long rcx;
-	unsigned long rdx;
-	unsigned long rsi;
-	unsigned long rdi;
-	unsigned long orig_rax;
-/* end of arguments */
-/* cpu exception frame or undefined */
-	unsigned long rip;
-	unsigned long cs;
-	unsigned long eflags;
-	unsigned long rsp;
-	unsigned long ss;
-/* top of stack page */
-};
-
-#else /* __KERNEL__ */
-
-struct pt_regs {
-	unsigned long r15;
-	unsigned long r14;
-	unsigned long r13;
-	unsigned long r12;
-	unsigned long bp;
-	unsigned long bx;
-/* arguments: non interrupts/non tracing syscalls only save upto here*/
-	unsigned long r11;
-	unsigned long r10;
-	unsigned long r9;
-	unsigned long r8;
-	unsigned long ax;
-	unsigned long cx;
-	unsigned long dx;
-	unsigned long si;
-	unsigned long di;
-	unsigned long orig_ax;
-/* end of arguments */
-/* cpu exception frame or undefined */
-	unsigned long ip;
-	unsigned long cs;
-	unsigned long flags;
-	unsigned long sp;
-	unsigned long ss;
-/* top of stack page */
-};
-
-#endif /* __KERNEL__ */
-#endif /* !__i386__ */
-
-
-#ifdef CONFIG_X86_PTRACE_BTS
-/* a branch trace record entry
- *
- * In order to unify the interface between various processor versions,
- * we use the below data structure for all processors.
- */
-enum bts_qualifier {
-	BTS_INVALID = 0,
-	BTS_BRANCH,
-	BTS_TASK_ARRIVES,
-	BTS_TASK_DEPARTS
-};
-
-struct bts_struct {
-	__u64 qualifier;
-	union {
-		/* BTS_BRANCH */
-		struct {
-			__u64 from_ip;
-			__u64 to_ip;
-		} lbr;
-		/* BTS_TASK_ARRIVES or
-		   BTS_TASK_DEPARTS */
-		__u64 jiffies;
-	} variant;
-};
-#endif /* CONFIG_X86_PTRACE_BTS */
-
-#ifdef __KERNEL__
-
-#include <linux/init.h>
-
-struct cpuinfo_x86;
-struct task_struct;
-
-#ifdef CONFIG_X86_PTRACE_BTS
-extern void __cpuinit ptrace_bts_init_intel(struct cpuinfo_x86 *);
-extern void ptrace_bts_take_timestamp(struct task_struct *, enum bts_qualifier);
-#else
-#define ptrace_bts_init_intel(config) do {} while (0)
-#endif /* CONFIG_X86_PTRACE_BTS */
-
-extern unsigned long profile_pc(struct pt_regs *regs);
-
-extern unsigned long
-convert_ip_to_linear(struct task_struct *child, struct pt_regs *regs);
-extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs,
-			 int error_code, int si_code);
-void signal_fault(struct pt_regs *regs, void __user *frame, char *where);
-
-extern long syscall_trace_enter(struct pt_regs *);
-extern void syscall_trace_leave(struct pt_regs *);
-
-static inline unsigned long regs_return_value(struct pt_regs *regs)
-{
-	return regs->ax;
-}
-
-/*
- * user_mode_vm(regs) determines whether a register set came from user mode.
- * This is true if V8086 mode was enabled OR if the register set was from
- * protected mode with RPL-3 CS value.  This tricky test checks that with
- * one comparison.  Many places in the kernel can bypass this full check
- * if they have already ruled out V8086 mode, so user_mode(regs) can be used.
- */
-static inline int user_mode(struct pt_regs *regs)
-{
-#ifdef CONFIG_X86_32
-	return (regs->cs & SEGMENT_RPL_MASK) == USER_RPL;
-#else
-	return !!(regs->cs & 3);
-#endif
-}
-
-static inline int user_mode_vm(struct pt_regs *regs)
-{
-#ifdef CONFIG_X86_32
-	return ((regs->cs & SEGMENT_RPL_MASK) | (regs->flags & X86_VM_MASK)) >=
-		USER_RPL;
-#else
-	return user_mode(regs);
-#endif
-}
-
-static inline int v8086_mode(struct pt_regs *regs)
-{
-#ifdef CONFIG_X86_32
-	return (regs->flags & X86_VM_MASK);
-#else
-	return 0;	/* No V86 mode support in long mode */
-#endif
-}
-
-/*
- * X86_32 CPUs don't save ss and esp if the CPU is already in kernel mode
- * when it traps.  So regs will be the current sp.
- *
- * This is valid only for kernel mode traps.
- */
-static inline unsigned long kernel_trap_sp(struct pt_regs *regs)
-{
-#ifdef CONFIG_X86_32
-	return (unsigned long)regs;
-#else
-	return regs->sp;
-#endif
-}
-
-static inline unsigned long instruction_pointer(struct pt_regs *regs)
-{
-	return regs->ip;
-}
-
-static inline unsigned long frame_pointer(struct pt_regs *regs)
-{
-	return regs->bp;
-}
-
-static inline unsigned long user_stack_pointer(struct pt_regs *regs)
-{
-	return regs->sp;
-}
-
-/*
- * These are defined as per linux/ptrace.h, which see.
- */
-#define arch_has_single_step()	(1)
-extern void user_enable_single_step(struct task_struct *);
-extern void user_disable_single_step(struct task_struct *);
-
-extern void user_enable_block_step(struct task_struct *);
-#ifdef CONFIG_X86_DEBUGCTLMSR
-#define arch_has_block_step()	(1)
-#else
-#define arch_has_block_step()	(boot_cpu_data.x86 >= 6)
-#endif
-
-struct user_desc;
-extern int do_get_thread_area(struct task_struct *p, int idx,
-			      struct user_desc __user *info);
-extern int do_set_thread_area(struct task_struct *p, int idx,
-			      struct user_desc __user *info, int can_allocate);
-
-#define __ARCH_WANT_COMPAT_SYS_PTRACE
-
-#endif /* __KERNEL__ */
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* ASM_X86__PTRACE_H */
diff --git a/include/asm-x86/pvclock-abi.h b/include/asm-x86/pvclock-abi.h
deleted file mode 100644
index edb3b4ecfc81..000000000000
--- a/include/asm-x86/pvclock-abi.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef ASM_X86__PVCLOCK_ABI_H
-#define ASM_X86__PVCLOCK_ABI_H
-#ifndef __ASSEMBLY__
-
-/*
- * These structs MUST NOT be changed.
- * They are the ABI between hypervisor and guest OS.
- * Both Xen and KVM are using this.
- *
- * pvclock_vcpu_time_info holds the system time and the tsc timestamp
- * of the last update. So the guest can use the tsc delta to get a
- * more precise system time.  There is one per virtual cpu.
- *
- * pvclock_wall_clock references the point in time when the system
- * time was zero (usually boot time), thus the guest calculates the
- * current wall clock by adding the system time.
- *
- * Protocol for the "version" fields is: hypervisor raises it (making
- * it uneven) before it starts updating the fields and raises it again
- * (making it even) when it is done.  Thus the guest can make sure the
- * time values it got are consistent by checking the version before
- * and after reading them.
- */
-
-struct pvclock_vcpu_time_info {
-	u32   version;
-	u32   pad0;
-	u64   tsc_timestamp;
-	u64   system_time;
-	u32   tsc_to_system_mul;
-	s8    tsc_shift;
-	u8    pad[3];
-} __attribute__((__packed__)); /* 32 bytes */
-
-struct pvclock_wall_clock {
-	u32   version;
-	u32   sec;
-	u32   nsec;
-} __attribute__((__packed__));
-
-#endif /* __ASSEMBLY__ */
-#endif /* ASM_X86__PVCLOCK_ABI_H */
diff --git a/include/asm-x86/pvclock.h b/include/asm-x86/pvclock.h
deleted file mode 100644
index 1a38f6834800..000000000000
--- a/include/asm-x86/pvclock.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef ASM_X86__PVCLOCK_H
-#define ASM_X86__PVCLOCK_H
-
-#include <linux/clocksource.h>
-#include <asm/pvclock-abi.h>
-
-/* some helper functions for xen and kvm pv clock sources */
-cycle_t pvclock_clocksource_read(struct pvclock_vcpu_time_info *src);
-void pvclock_read_wallclock(struct pvclock_wall_clock *wall,
-			    struct pvclock_vcpu_time_info *vcpu,
-			    struct timespec *ts);
-
-#endif /* ASM_X86__PVCLOCK_H */
diff --git a/include/asm-x86/reboot.h b/include/asm-x86/reboot.h
deleted file mode 100644
index 1c2f0ce9e31e..000000000000
--- a/include/asm-x86/reboot.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef ASM_X86__REBOOT_H
-#define ASM_X86__REBOOT_H
-
-struct pt_regs;
-
-struct machine_ops {
-	void (*restart)(char *cmd);
-	void (*halt)(void);
-	void (*power_off)(void);
-	void (*shutdown)(void);
-	void (*crash_shutdown)(struct pt_regs *);
-	void (*emergency_restart)(void);
-};
-
-extern struct machine_ops machine_ops;
-
-void native_machine_crash_shutdown(struct pt_regs *regs);
-void native_machine_shutdown(void);
-void machine_real_restart(const unsigned char *code, int length);
-
-#endif /* ASM_X86__REBOOT_H */
diff --git a/include/asm-x86/reboot_fixups.h b/include/asm-x86/reboot_fixups.h
deleted file mode 100644
index 2c2987d97570..000000000000
--- a/include/asm-x86/reboot_fixups.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef ASM_X86__REBOOT_FIXUPS_H
-#define ASM_X86__REBOOT_FIXUPS_H
-
-extern void mach_reboot_fixups(void);
-
-#endif /* ASM_X86__REBOOT_FIXUPS_H */
diff --git a/include/asm-x86/required-features.h b/include/asm-x86/required-features.h
deleted file mode 100644
index a01c4e376331..000000000000
--- a/include/asm-x86/required-features.h
+++ /dev/null
@@ -1,82 +0,0 @@
-#ifndef ASM_X86__REQUIRED_FEATURES_H
-#define ASM_X86__REQUIRED_FEATURES_H
-
-/* Define minimum CPUID feature set for kernel These bits are checked
-   really early to actually display a visible error message before the
-   kernel dies.  Make sure to assign features to the proper mask!
-
-   Some requirements that are not in CPUID yet are also in the
-   CONFIG_X86_MINIMUM_CPU_FAMILY which is checked too.
-
-   The real information is in arch/x86/Kconfig.cpu, this just converts
-   the CONFIGs into a bitmask */
-
-#ifndef CONFIG_MATH_EMULATION
-# define NEED_FPU	(1<<(X86_FEATURE_FPU & 31))
-#else
-# define NEED_FPU	0
-#endif
-
-#if defined(CONFIG_X86_PAE) || defined(CONFIG_X86_64)
-# define NEED_PAE	(1<<(X86_FEATURE_PAE & 31))
-#else
-# define NEED_PAE	0
-#endif
-
-#ifdef CONFIG_X86_CMPXCHG64
-# define NEED_CX8	(1<<(X86_FEATURE_CX8 & 31))
-#else
-# define NEED_CX8	0
-#endif
-
-#if defined(CONFIG_X86_CMOV) || defined(CONFIG_X86_64)
-# define NEED_CMOV	(1<<(X86_FEATURE_CMOV & 31))
-#else
-# define NEED_CMOV	0
-#endif
-
-#ifdef CONFIG_X86_USE_3DNOW
-# define NEED_3DNOW	(1<<(X86_FEATURE_3DNOW & 31))
-#else
-# define NEED_3DNOW	0
-#endif
-
-#if defined(CONFIG_X86_P6_NOP) || defined(CONFIG_X86_64)
-# define NEED_NOPL	(1<<(X86_FEATURE_NOPL & 31))
-#else
-# define NEED_NOPL	0
-#endif
-
-#ifdef CONFIG_X86_64
-#define NEED_PSE	0
-#define NEED_MSR	(1<<(X86_FEATURE_MSR & 31))
-#define NEED_PGE	(1<<(X86_FEATURE_PGE & 31))
-#define NEED_FXSR	(1<<(X86_FEATURE_FXSR & 31))
-#define NEED_XMM	(1<<(X86_FEATURE_XMM & 31))
-#define NEED_XMM2	(1<<(X86_FEATURE_XMM2 & 31))
-#define NEED_LM		(1<<(X86_FEATURE_LM & 31))
-#else
-#define NEED_PSE	0
-#define NEED_MSR	0
-#define NEED_PGE	0
-#define NEED_FXSR	0
-#define NEED_XMM	0
-#define NEED_XMM2	0
-#define NEED_LM		0
-#endif
-
-#define REQUIRED_MASK0	(NEED_FPU|NEED_PSE|NEED_MSR|NEED_PAE|\
-			 NEED_CX8|NEED_PGE|NEED_FXSR|NEED_CMOV|\
-			 NEED_XMM|NEED_XMM2)
-#define SSE_MASK	(NEED_XMM|NEED_XMM2)
-
-#define REQUIRED_MASK1	(NEED_LM|NEED_3DNOW)
-
-#define REQUIRED_MASK2	0
-#define REQUIRED_MASK3	(NEED_NOPL)
-#define REQUIRED_MASK4	0
-#define REQUIRED_MASK5	0
-#define REQUIRED_MASK6	0
-#define REQUIRED_MASK7	0
-
-#endif /* ASM_X86__REQUIRED_FEATURES_H */
diff --git a/include/asm-x86/resource.h b/include/asm-x86/resource.h
deleted file mode 100644
index 04bc4db8921b..000000000000
--- a/include/asm-x86/resource.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/resource.h>
diff --git a/include/asm-x86/resume-trace.h b/include/asm-x86/resume-trace.h
deleted file mode 100644
index e39376d7de50..000000000000
--- a/include/asm-x86/resume-trace.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef ASM_X86__RESUME_TRACE_H
-#define ASM_X86__RESUME_TRACE_H
-
-#include <asm/asm.h>
-
-#define TRACE_RESUME(user)					\
-do {								\
-	if (pm_trace_enabled) {					\
-		const void *tracedata;				\
-		asm volatile(_ASM_MOV " $1f,%0\n"		\
-			     ".section .tracedata,\"a\"\n"	\
-			     "1:\t.word %c1\n\t"		\
-			     _ASM_PTR " %c2\n"			\
-			     ".previous"			\
-			     :"=r" (tracedata)			\
-			     : "i" (__LINE__), "i" (__FILE__));	\
-		generate_resume_trace(tracedata, user);		\
-	}							\
-} while (0)
-
-#endif /* ASM_X86__RESUME_TRACE_H */
diff --git a/include/asm-x86/rio.h b/include/asm-x86/rio.h
deleted file mode 100644
index 5e1256bdee83..000000000000
--- a/include/asm-x86/rio.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Derived from include/asm-x86/mach-summit/mach_mpparse.h
- *          and include/asm-x86/mach-default/bios_ebda.h
- *
- * Author: Laurent Vivier <Laurent.Vivier@bull.net>
- */
-
-#ifndef ASM_X86__RIO_H
-#define ASM_X86__RIO_H
-
-#define RIO_TABLE_VERSION	3
-
-struct rio_table_hdr {
-	u8 version;		/* Version number of this data structure  */
-	u8 num_scal_dev;	/* # of Scalability devices               */
-	u8 num_rio_dev;		/* # of RIO I/O devices                   */
-} __attribute__((packed));
-
-struct scal_detail {
-	u8 node_id;		/* Scalability Node ID                    */
-	u32 CBAR;		/* Address of 1MB register space          */
-	u8 port0node;		/* Node ID port connected to: 0xFF=None   */
-	u8 port0port;		/* Port num port connected to: 0,1,2, or  */
-				/* 0xFF=None                              */
-	u8 port1node;		/* Node ID port connected to: 0xFF = None */
-	u8 port1port;		/* Port num port connected to: 0,1,2, or  */
-				/* 0xFF=None                              */
-	u8 port2node;		/* Node ID port connected to: 0xFF = None */
-	u8 port2port;		/* Port num port connected to: 0,1,2, or  */
-				/* 0xFF=None                              */
-	u8 chassis_num;		/* 1 based Chassis number (1 = boot node) */
-} __attribute__((packed));
-
-struct rio_detail {
-	u8 node_id;		/* RIO Node ID                            */
-	u32 BBAR;		/* Address of 1MB register space          */
-	u8 type;		/* Type of device                         */
-	u8 owner_id;		/* Node ID of Hurricane that owns this    */
-				/* node                                   */
-	u8 port0node;		/* Node ID port connected to: 0xFF=None   */
-	u8 port0port;		/* Port num port connected to: 0,1,2, or  */
-				/* 0xFF=None                              */
-	u8 port1node;		/* Node ID port connected to: 0xFF=None   */
-	u8 port1port;		/* Port num port connected to: 0,1,2, or  */
-				/* 0xFF=None                              */
-	u8 first_slot;		/* Lowest slot number below this Calgary  */
-	u8 status;		/* Bit 0 = 1 : the XAPIC is used          */
-				/*       = 0 : the XAPIC is not used, ie: */
-				/*            ints fwded to another XAPIC */
-				/*           Bits1:7 Reserved             */
-	u8 WP_index;		/* instance index - lower ones have       */
-				/*     lower slot numbers/PCI bus numbers */
-	u8 chassis_num;		/* 1 based Chassis number                 */
-} __attribute__((packed));
-
-enum {
-	HURR_SCALABILTY	= 0,	/* Hurricane Scalability info */
-	HURR_RIOIB	= 2,	/* Hurricane RIOIB info       */
-	COMPAT_CALGARY	= 4,	/* Compatibility Calgary      */
-	ALT_CALGARY	= 5,	/* Second Planar Calgary      */
-};
-
-#endif /* ASM_X86__RIO_H */
diff --git a/include/asm-x86/rtc.h b/include/asm-x86/rtc.h
deleted file mode 100644
index f71c3b0ed360..000000000000
--- a/include/asm-x86/rtc.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/rtc.h>
diff --git a/include/asm-x86/rwlock.h b/include/asm-x86/rwlock.h
deleted file mode 100644
index 48a3109e1a7d..000000000000
--- a/include/asm-x86/rwlock.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef ASM_X86__RWLOCK_H
-#define ASM_X86__RWLOCK_H
-
-#define RW_LOCK_BIAS		 0x01000000
-
-/* Actual code is in asm/spinlock.h or in arch/x86/lib/rwlock.S */
-
-#endif /* ASM_X86__RWLOCK_H */
diff --git a/include/asm-x86/rwsem.h b/include/asm-x86/rwsem.h
deleted file mode 100644
index 3ff3015b71a8..000000000000
--- a/include/asm-x86/rwsem.h
+++ /dev/null
@@ -1,265 +0,0 @@
-/* rwsem.h: R/W semaphores implemented using XADD/CMPXCHG for i486+
- *
- * Written by David Howells (dhowells@redhat.com).
- *
- * Derived from asm-x86/semaphore.h
- *
- *
- * The MSW of the count is the negated number of active writers and waiting
- * lockers, and the LSW is the total number of active locks
- *
- * The lock count is initialized to 0 (no active and no waiting lockers).
- *
- * When a writer subtracts WRITE_BIAS, it'll get 0xffff0001 for the case of an
- * uncontended lock. This can be determined because XADD returns the old value.
- * Readers increment by 1 and see a positive value when uncontended, negative
- * if there are writers (and maybe) readers waiting (in which case it goes to
- * sleep).
- *
- * The value of WAITING_BIAS supports up to 32766 waiting processes. This can
- * be extended to 65534 by manually checking the whole MSW rather than relying
- * on the S flag.
- *
- * The value of ACTIVE_BIAS supports up to 65535 active processes.
- *
- * This should be totally fair - if anything is waiting, a process that wants a
- * lock will go to the back of the queue. When the currently active lock is
- * released, if there's a writer at the front of the queue, then that and only
- * that will be woken up; if there's a bunch of consequtive readers at the
- * front, then they'll all be woken up, but no other readers will be.
- */
-
-#ifndef ASM_X86__RWSEM_H
-#define ASM_X86__RWSEM_H
-
-#ifndef _LINUX_RWSEM_H
-#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
-#endif
-
-#ifdef __KERNEL__
-
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <linux/lockdep.h>
-
-struct rwsem_waiter;
-
-extern asmregparm struct rw_semaphore *
- rwsem_down_read_failed(struct rw_semaphore *sem);
-extern asmregparm struct rw_semaphore *
- rwsem_down_write_failed(struct rw_semaphore *sem);
-extern asmregparm struct rw_semaphore *
- rwsem_wake(struct rw_semaphore *);
-extern asmregparm struct rw_semaphore *
- rwsem_downgrade_wake(struct rw_semaphore *sem);
-
-/*
- * the semaphore definition
- */
-
-#define RWSEM_UNLOCKED_VALUE		0x00000000
-#define RWSEM_ACTIVE_BIAS		0x00000001
-#define RWSEM_ACTIVE_MASK		0x0000ffff
-#define RWSEM_WAITING_BIAS		(-0x00010000)
-#define RWSEM_ACTIVE_READ_BIAS		RWSEM_ACTIVE_BIAS
-#define RWSEM_ACTIVE_WRITE_BIAS		(RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
-
-struct rw_semaphore {
-	signed long		count;
-	spinlock_t		wait_lock;
-	struct list_head	wait_list;
-#ifdef CONFIG_DEBUG_LOCK_ALLOC
-	struct lockdep_map dep_map;
-#endif
-};
-
-#ifdef CONFIG_DEBUG_LOCK_ALLOC
-# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
-#else
-# define __RWSEM_DEP_MAP_INIT(lockname)
-#endif
-
-
-#define __RWSEM_INITIALIZER(name)				\
-{								\
-	RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait_lock), \
-	LIST_HEAD_INIT((name).wait_list) __RWSEM_DEP_MAP_INIT(name) \
-}
-
-#define DECLARE_RWSEM(name)					\
-	struct rw_semaphore name = __RWSEM_INITIALIZER(name)
-
-extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
-			 struct lock_class_key *key);
-
-#define init_rwsem(sem)						\
-do {								\
-	static struct lock_class_key __key;			\
-								\
-	__init_rwsem((sem), #sem, &__key);			\
-} while (0)
-
-/*
- * lock for reading
- */
-static inline void __down_read(struct rw_semaphore *sem)
-{
-	asm volatile("# beginning down_read\n\t"
-		     LOCK_PREFIX "  incl      (%%eax)\n\t"
-		     /* adds 0x00000001, returns the old value */
-		     "  jns        1f\n"
-		     "  call call_rwsem_down_read_failed\n"
-		     "1:\n\t"
-		     "# ending down_read\n\t"
-		     : "+m" (sem->count)
-		     : "a" (sem)
-		     : "memory", "cc");
-}
-
-/*
- * trylock for reading -- returns 1 if successful, 0 if contention
- */
-static inline int __down_read_trylock(struct rw_semaphore *sem)
-{
-	__s32 result, tmp;
-	asm volatile("# beginning __down_read_trylock\n\t"
-		     "  movl      %0,%1\n\t"
-		     "1:\n\t"
-		     "  movl	     %1,%2\n\t"
-		     "  addl      %3,%2\n\t"
-		     "  jle	     2f\n\t"
-		     LOCK_PREFIX "  cmpxchgl  %2,%0\n\t"
-		     "  jnz	     1b\n\t"
-		     "2:\n\t"
-		     "# ending __down_read_trylock\n\t"
-		     : "+m" (sem->count), "=&a" (result), "=&r" (tmp)
-		     : "i" (RWSEM_ACTIVE_READ_BIAS)
-		     : "memory", "cc");
-	return result >= 0 ? 1 : 0;
-}
-
-/*
- * lock for writing
- */
-static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
-{
-	int tmp;
-
-	tmp = RWSEM_ACTIVE_WRITE_BIAS;
-	asm volatile("# beginning down_write\n\t"
-		     LOCK_PREFIX "  xadd      %%edx,(%%eax)\n\t"
-		     /* subtract 0x0000ffff, returns the old value */
-		     "  testl     %%edx,%%edx\n\t"
-		     /* was the count 0 before? */
-		     "  jz        1f\n"
-		     "  call call_rwsem_down_write_failed\n"
-		     "1:\n"
-		     "# ending down_write"
-		     : "+m" (sem->count), "=d" (tmp)
-		     : "a" (sem), "1" (tmp)
-		     : "memory", "cc");
-}
-
-static inline void __down_write(struct rw_semaphore *sem)
-{
-	__down_write_nested(sem, 0);
-}
-
-/*
- * trylock for writing -- returns 1 if successful, 0 if contention
- */
-static inline int __down_write_trylock(struct rw_semaphore *sem)
-{
-	signed long ret = cmpxchg(&sem->count,
-				  RWSEM_UNLOCKED_VALUE,
-				  RWSEM_ACTIVE_WRITE_BIAS);
-	if (ret == RWSEM_UNLOCKED_VALUE)
-		return 1;
-	return 0;
-}
-
-/*
- * unlock after reading
- */
-static inline void __up_read(struct rw_semaphore *sem)
-{
-	__s32 tmp = -RWSEM_ACTIVE_READ_BIAS;
-	asm volatile("# beginning __up_read\n\t"
-		     LOCK_PREFIX "  xadd      %%edx,(%%eax)\n\t"
-		     /* subtracts 1, returns the old value */
-		     "  jns        1f\n\t"
-		     "  call call_rwsem_wake\n"
-		     "1:\n"
-		     "# ending __up_read\n"
-		     : "+m" (sem->count), "=d" (tmp)
-		     : "a" (sem), "1" (tmp)
-		     : "memory", "cc");
-}
-
-/*
- * unlock after writing
- */
-static inline void __up_write(struct rw_semaphore *sem)
-{
-	asm volatile("# beginning __up_write\n\t"
-		     "  movl      %2,%%edx\n\t"
-		     LOCK_PREFIX "  xaddl     %%edx,(%%eax)\n\t"
-		     /* tries to transition
-			0xffff0001 -> 0x00000000 */
-		     "  jz       1f\n"
-		     "  call call_rwsem_wake\n"
-		     "1:\n\t"
-		     "# ending __up_write\n"
-		     : "+m" (sem->count)
-		     : "a" (sem), "i" (-RWSEM_ACTIVE_WRITE_BIAS)
-		     : "memory", "cc", "edx");
-}
-
-/*
- * downgrade write lock to read lock
- */
-static inline void __downgrade_write(struct rw_semaphore *sem)
-{
-	asm volatile("# beginning __downgrade_write\n\t"
-		     LOCK_PREFIX "  addl      %2,(%%eax)\n\t"
-		     /* transitions 0xZZZZ0001 -> 0xYYYY0001 */
-		     "  jns       1f\n\t"
-		     "  call call_rwsem_downgrade_wake\n"
-		     "1:\n\t"
-		     "# ending __downgrade_write\n"
-		     : "+m" (sem->count)
-		     : "a" (sem), "i" (-RWSEM_WAITING_BIAS)
-		     : "memory", "cc");
-}
-
-/*
- * implement atomic add functionality
- */
-static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
-{
-	asm volatile(LOCK_PREFIX "addl %1,%0"
-		     : "+m" (sem->count)
-		     : "ir" (delta));
-}
-
-/*
- * implement exchange and add functionality
- */
-static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
-{
-	int tmp = delta;
-
-	asm volatile(LOCK_PREFIX "xadd %0,%1"
-		     : "+r" (tmp), "+m" (sem->count)
-		     : : "memory");
-
-	return tmp + delta;
-}
-
-static inline int rwsem_is_locked(struct rw_semaphore *sem)
-{
-	return (sem->count != 0);
-}
-
-#endif /* __KERNEL__ */
-#endif /* ASM_X86__RWSEM_H */
diff --git a/include/asm-x86/scatterlist.h b/include/asm-x86/scatterlist.h
deleted file mode 100644
index ee48f880005d..000000000000
--- a/include/asm-x86/scatterlist.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef ASM_X86__SCATTERLIST_H
-#define ASM_X86__SCATTERLIST_H
-
-#include <asm/types.h>
-
-struct scatterlist {
-#ifdef CONFIG_DEBUG_SG
-	unsigned long	sg_magic;
-#endif
-	unsigned long	page_link;
-	unsigned int	offset;
-	unsigned int	length;
-	dma_addr_t	dma_address;
-	unsigned int	dma_length;
-};
-
-#define ARCH_HAS_SG_CHAIN
-#define ISA_DMA_THRESHOLD (0x00ffffff)
-
-/*
- * These macros should be used after a pci_map_sg call has been done
- * to get bus addresses of each of the SG entries and their lengths.
- * You should only work with the number of sg entries pci_map_sg
- * returns.
- */
-#define sg_dma_address(sg)	((sg)->dma_address)
-#ifdef CONFIG_X86_32
-# define sg_dma_len(sg)		((sg)->length)
-#else
-# define sg_dma_len(sg)		((sg)->dma_length)
-#endif
-
-#endif /* ASM_X86__SCATTERLIST_H */
diff --git a/include/asm-x86/seccomp.h b/include/asm-x86/seccomp.h
deleted file mode 100644
index c62e58a5a90d..000000000000
--- a/include/asm-x86/seccomp.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifdef CONFIG_X86_32
-# include "seccomp_32.h"
-#else
-# include "seccomp_64.h"
-#endif
diff --git a/include/asm-x86/seccomp_32.h b/include/asm-x86/seccomp_32.h
deleted file mode 100644
index cf9ab2dbcef1..000000000000
--- a/include/asm-x86/seccomp_32.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef ASM_X86__SECCOMP_32_H
-#define ASM_X86__SECCOMP_32_H
-
-#include <linux/thread_info.h>
-
-#ifdef TIF_32BIT
-#error "unexpected TIF_32BIT on i386"
-#endif
-
-#include <linux/unistd.h>
-
-#define __NR_seccomp_read __NR_read
-#define __NR_seccomp_write __NR_write
-#define __NR_seccomp_exit __NR_exit
-#define __NR_seccomp_sigreturn __NR_sigreturn
-
-#endif /* ASM_X86__SECCOMP_32_H */
diff --git a/include/asm-x86/seccomp_64.h b/include/asm-x86/seccomp_64.h
deleted file mode 100644
index 03274cea751f..000000000000
--- a/include/asm-x86/seccomp_64.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef ASM_X86__SECCOMP_64_H
-#define ASM_X86__SECCOMP_64_H
-
-#include <linux/thread_info.h>
-
-#ifdef TIF_32BIT
-#error "unexpected TIF_32BIT on x86_64"
-#else
-#define TIF_32BIT TIF_IA32
-#endif
-
-#include <linux/unistd.h>
-#include <asm/ia32_unistd.h>
-
-#define __NR_seccomp_read __NR_read
-#define __NR_seccomp_write __NR_write
-#define __NR_seccomp_exit __NR_exit
-#define __NR_seccomp_sigreturn __NR_rt_sigreturn
-
-#define __NR_seccomp_read_32 __NR_ia32_read
-#define __NR_seccomp_write_32 __NR_ia32_write
-#define __NR_seccomp_exit_32 __NR_ia32_exit
-#define __NR_seccomp_sigreturn_32 __NR_ia32_sigreturn
-
-#endif /* ASM_X86__SECCOMP_64_H */
diff --git a/include/asm-x86/sections.h b/include/asm-x86/sections.h
deleted file mode 100644
index 2b8c5160388f..000000000000
--- a/include/asm-x86/sections.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/sections.h>
diff --git a/include/asm-x86/segment.h b/include/asm-x86/segment.h
deleted file mode 100644
index 5d6e69454891..000000000000
--- a/include/asm-x86/segment.h
+++ /dev/null
@@ -1,209 +0,0 @@
-#ifndef ASM_X86__SEGMENT_H
-#define ASM_X86__SEGMENT_H
-
-/* Constructor for a conventional segment GDT (or LDT) entry */
-/* This is a macro so it can be used in initializers */
-#define GDT_ENTRY(flags, base, limit)			\
-	((((base)  & 0xff000000ULL) << (56-24)) |	\
-	 (((flags) & 0x0000f0ffULL) << 40) |		\
-	 (((limit) & 0x000f0000ULL) << (48-16)) |	\
-	 (((base)  & 0x00ffffffULL) << 16) |		\
-	 (((limit) & 0x0000ffffULL)))
-
-/* Simple and small GDT entries for booting only */
-
-#define GDT_ENTRY_BOOT_CS	2
-#define __BOOT_CS		(GDT_ENTRY_BOOT_CS * 8)
-
-#define GDT_ENTRY_BOOT_DS	(GDT_ENTRY_BOOT_CS + 1)
-#define __BOOT_DS		(GDT_ENTRY_BOOT_DS * 8)
-
-#define GDT_ENTRY_BOOT_TSS	(GDT_ENTRY_BOOT_CS + 2)
-#define __BOOT_TSS		(GDT_ENTRY_BOOT_TSS * 8)
-
-#ifdef CONFIG_X86_32
-/*
- * The layout of the per-CPU GDT under Linux:
- *
- *   0 - null
- *   1 - reserved
- *   2 - reserved
- *   3 - reserved
- *
- *   4 - unused			<==== new cacheline
- *   5 - unused
- *
- *  ------- start of TLS (Thread-Local Storage) segments:
- *
- *   6 - TLS segment #1			[ glibc's TLS segment ]
- *   7 - TLS segment #2			[ Wine's %fs Win32 segment ]
- *   8 - TLS segment #3
- *   9 - reserved
- *  10 - reserved
- *  11 - reserved
- *
- *  ------- start of kernel segments:
- *
- *  12 - kernel code segment		<==== new cacheline
- *  13 - kernel data segment
- *  14 - default user CS
- *  15 - default user DS
- *  16 - TSS
- *  17 - LDT
- *  18 - PNPBIOS support (16->32 gate)
- *  19 - PNPBIOS support
- *  20 - PNPBIOS support
- *  21 - PNPBIOS support
- *  22 - PNPBIOS support
- *  23 - APM BIOS support
- *  24 - APM BIOS support
- *  25 - APM BIOS support
- *
- *  26 - ESPFIX small SS
- *  27 - per-cpu			[ offset to per-cpu data area ]
- *  28 - unused
- *  29 - unused
- *  30 - unused
- *  31 - TSS for double fault handler
- */
-#define GDT_ENTRY_TLS_MIN	6
-#define GDT_ENTRY_TLS_MAX 	(GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
-
-#define GDT_ENTRY_DEFAULT_USER_CS	14
-
-#define GDT_ENTRY_DEFAULT_USER_DS	15
-
-#define GDT_ENTRY_KERNEL_BASE	12
-
-#define GDT_ENTRY_KERNEL_CS		(GDT_ENTRY_KERNEL_BASE + 0)
-
-#define GDT_ENTRY_KERNEL_DS		(GDT_ENTRY_KERNEL_BASE + 1)
-
-#define GDT_ENTRY_TSS			(GDT_ENTRY_KERNEL_BASE + 4)
-#define GDT_ENTRY_LDT			(GDT_ENTRY_KERNEL_BASE + 5)
-
-#define GDT_ENTRY_PNPBIOS_BASE		(GDT_ENTRY_KERNEL_BASE + 6)
-#define GDT_ENTRY_APMBIOS_BASE		(GDT_ENTRY_KERNEL_BASE + 11)
-
-#define GDT_ENTRY_ESPFIX_SS		(GDT_ENTRY_KERNEL_BASE + 14)
-#define __ESPFIX_SS (GDT_ENTRY_ESPFIX_SS * 8)
-
-#define GDT_ENTRY_PERCPU			(GDT_ENTRY_KERNEL_BASE + 15)
-#ifdef CONFIG_SMP
-#define __KERNEL_PERCPU (GDT_ENTRY_PERCPU * 8)
-#else
-#define __KERNEL_PERCPU 0
-#endif
-
-#define GDT_ENTRY_DOUBLEFAULT_TSS	31
-
-/*
- * The GDT has 32 entries
- */
-#define GDT_ENTRIES 32
-
-/* The PnP BIOS entries in the GDT */
-#define GDT_ENTRY_PNPBIOS_CS32		(GDT_ENTRY_PNPBIOS_BASE + 0)
-#define GDT_ENTRY_PNPBIOS_CS16		(GDT_ENTRY_PNPBIOS_BASE + 1)
-#define GDT_ENTRY_PNPBIOS_DS		(GDT_ENTRY_PNPBIOS_BASE + 2)
-#define GDT_ENTRY_PNPBIOS_TS1		(GDT_ENTRY_PNPBIOS_BASE + 3)
-#define GDT_ENTRY_PNPBIOS_TS2		(GDT_ENTRY_PNPBIOS_BASE + 4)
-
-/* The PnP BIOS selectors */
-#define PNP_CS32   (GDT_ENTRY_PNPBIOS_CS32 * 8)	/* segment for calling fn */
-#define PNP_CS16   (GDT_ENTRY_PNPBIOS_CS16 * 8)	/* code segment for BIOS */
-#define PNP_DS     (GDT_ENTRY_PNPBIOS_DS * 8)	/* data segment for BIOS */
-#define PNP_TS1    (GDT_ENTRY_PNPBIOS_TS1 * 8)	/* transfer data segment */
-#define PNP_TS2    (GDT_ENTRY_PNPBIOS_TS2 * 8)	/* another data segment */
-
-/* Bottom two bits of selector give the ring privilege level */
-#define SEGMENT_RPL_MASK	0x3
-/* Bit 2 is table indicator (LDT/GDT) */
-#define SEGMENT_TI_MASK		0x4
-
-/* User mode is privilege level 3 */
-#define USER_RPL		0x3
-/* LDT segment has TI set, GDT has it cleared */
-#define SEGMENT_LDT		0x4
-#define SEGMENT_GDT		0x0
-
-/*
- * Matching rules for certain types of segments.
- */
-
-/* Matches PNP_CS32 and PNP_CS16 (they must be consecutive) */
-#define SEGMENT_IS_PNP_CODE(x)   (((x) & 0xf4) == GDT_ENTRY_PNPBIOS_BASE * 8)
-
-
-#else
-#include <asm/cache.h>
-
-#define GDT_ENTRY_KERNEL32_CS 1
-#define GDT_ENTRY_KERNEL_CS 2
-#define GDT_ENTRY_KERNEL_DS 3
-
-#define __KERNEL32_CS   (GDT_ENTRY_KERNEL32_CS * 8)
-
-/*
- * we cannot use the same code segment descriptor for user and kernel
- * -- not even in the long flat mode, because of different DPL /kkeil
- * The segment offset needs to contain a RPL. Grr. -AK
- * GDT layout to get 64bit syscall right (sysret hardcodes gdt offsets)
- */
-#define GDT_ENTRY_DEFAULT_USER32_CS 4
-#define GDT_ENTRY_DEFAULT_USER_DS 5
-#define GDT_ENTRY_DEFAULT_USER_CS 6
-#define __USER32_CS   (GDT_ENTRY_DEFAULT_USER32_CS * 8 + 3)
-#define __USER32_DS	__USER_DS
-
-#define GDT_ENTRY_TSS 8	/* needs two entries */
-#define GDT_ENTRY_LDT 10 /* needs two entries */
-#define GDT_ENTRY_TLS_MIN 12
-#define GDT_ENTRY_TLS_MAX 14
-
-#define GDT_ENTRY_PER_CPU 15	/* Abused to load per CPU data from limit */
-#define __PER_CPU_SEG	(GDT_ENTRY_PER_CPU * 8 + 3)
-
-/* TLS indexes for 64bit - hardcoded in arch_prctl */
-#define FS_TLS 0
-#define GS_TLS 1
-
-#define GS_TLS_SEL ((GDT_ENTRY_TLS_MIN+GS_TLS)*8 + 3)
-#define FS_TLS_SEL ((GDT_ENTRY_TLS_MIN+FS_TLS)*8 + 3)
-
-#define GDT_ENTRIES 16
-
-#endif
-
-#define __KERNEL_CS	(GDT_ENTRY_KERNEL_CS * 8)
-#define __KERNEL_DS	(GDT_ENTRY_KERNEL_DS * 8)
-#define __USER_DS     (GDT_ENTRY_DEFAULT_USER_DS* 8 + 3)
-#define __USER_CS     (GDT_ENTRY_DEFAULT_USER_CS* 8 + 3)
-#ifndef CONFIG_PARAVIRT
-#define get_kernel_rpl()  0
-#endif
-
-/* User mode is privilege level 3 */
-#define USER_RPL		0x3
-/* LDT segment has TI set, GDT has it cleared */
-#define SEGMENT_LDT		0x4
-#define SEGMENT_GDT		0x0
-
-/* Bottom two bits of selector give the ring privilege level */
-#define SEGMENT_RPL_MASK	0x3
-/* Bit 2 is table indicator (LDT/GDT) */
-#define SEGMENT_TI_MASK		0x4
-
-#define IDT_ENTRIES 256
-#define NUM_EXCEPTION_VECTORS 32
-#define GDT_SIZE (GDT_ENTRIES * 8)
-#define GDT_ENTRY_TLS_ENTRIES 3
-#define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
-
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-extern const char early_idt_handlers[NUM_EXCEPTION_VECTORS][10];
-#endif
-#endif
-
-#endif /* ASM_X86__SEGMENT_H */
diff --git a/include/asm-x86/sembuf.h b/include/asm-x86/sembuf.h
deleted file mode 100644
index 81f06b7e5a3f..000000000000
--- a/include/asm-x86/sembuf.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef ASM_X86__SEMBUF_H
-#define ASM_X86__SEMBUF_H
-
-/*
- * The semid64_ds structure for x86 architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-struct semid64_ds {
-	struct ipc64_perm sem_perm;	/* permissions .. see ipc.h */
-	__kernel_time_t	sem_otime;	/* last semop time */
-	unsigned long	__unused1;
-	__kernel_time_t	sem_ctime;	/* last change time */
-	unsigned long	__unused2;
-	unsigned long	sem_nsems;	/* no. of semaphores in array */
-	unsigned long	__unused3;
-	unsigned long	__unused4;
-};
-
-#endif /* ASM_X86__SEMBUF_H */
diff --git a/include/asm-x86/serial.h b/include/asm-x86/serial.h
deleted file mode 100644
index 303660b671e5..000000000000
--- a/include/asm-x86/serial.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef ASM_X86__SERIAL_H
-#define ASM_X86__SERIAL_H
-
-/*
- * This assumes you have a 1.8432 MHz clock for your UART.
- *
- * It'd be nice if someone built a serial card with a 24.576 MHz
- * clock, since the 16550A is capable of handling a top speed of 1.5
- * megabits/second; but this requires the faster clock.
- */
-#define BASE_BAUD ( 1843200 / 16 )
-
-/* Standard COM flags (except for COM4, because of the 8514 problem) */
-#ifdef CONFIG_SERIAL_DETECT_IRQ
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
-#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
-#else
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
-#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
-#endif
-
-#define SERIAL_PORT_DFNS			\
-	/* UART CLK   PORT IRQ     FLAGS        */			\
-	{ 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },	/* ttyS0 */	\
-	{ 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },	/* ttyS1 */	\
-	{ 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },	/* ttyS2 */	\
-	{ 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },	/* ttyS3 */
-
-#endif /* ASM_X86__SERIAL_H */
diff --git a/include/asm-x86/setup.h b/include/asm-x86/setup.h
deleted file mode 100644
index 11b6cc14b289..000000000000
--- a/include/asm-x86/setup.h
+++ /dev/null
@@ -1,105 +0,0 @@
-#ifndef ASM_X86__SETUP_H
-#define ASM_X86__SETUP_H
-
-#define COMMAND_LINE_SIZE 2048
-
-#ifndef __ASSEMBLY__
-
-/* Interrupt control for vSMPowered x86_64 systems */
-void vsmp_init(void);
-
-#ifdef CONFIG_X86_VISWS
-extern void visws_early_detect(void);
-extern int is_visws_box(void);
-#else
-static inline void visws_early_detect(void) { }
-static inline int is_visws_box(void) { return 0; }
-#endif
-
-/*
- * Any setup quirks to be performed?
- */
-struct mpc_config_processor;
-struct mpc_config_bus;
-struct mp_config_oemtable;
-struct x86_quirks {
-	int (*arch_pre_time_init)(void);
-	int (*arch_time_init)(void);
-	int (*arch_pre_intr_init)(void);
-	int (*arch_intr_init)(void);
-	int (*arch_trap_init)(void);
-	char * (*arch_memory_setup)(void);
-	int (*mach_get_smp_config)(unsigned int early);
-	int (*mach_find_smp_config)(unsigned int reserve);
-
-	int *mpc_record;
-	int (*mpc_apic_id)(struct mpc_config_processor *m);
-	void (*mpc_oem_bus_info)(struct mpc_config_bus *m, char *name);
-	void (*mpc_oem_pci_bus)(struct mpc_config_bus *m);
-	void (*smp_read_mpc_oem)(struct mp_config_oemtable *oemtable,
-                                    unsigned short oemsize);
-	int (*setup_ioapic_ids)(void);
-};
-
-extern struct x86_quirks *x86_quirks;
-extern unsigned long saved_video_mode;
-
-#ifndef CONFIG_PARAVIRT
-#define paravirt_post_allocator_init()	do {} while (0)
-#endif
-#endif /* __ASSEMBLY__ */
-
-#ifdef __KERNEL__
-
-#ifdef __i386__
-
-#include <linux/pfn.h>
-/*
- * Reserved space for vmalloc and iomap - defined in asm/page.h
- */
-#define MAXMEM_PFN	PFN_DOWN(MAXMEM)
-#define MAX_NONPAE_PFN	(1 << 20)
-
-#endif /* __i386__ */
-
-#define PARAM_SIZE 4096		/* sizeof(struct boot_params) */
-
-#define OLD_CL_MAGIC		0xA33F
-#define OLD_CL_ADDRESS		0x020	/* Relative to real mode data */
-#define NEW_CL_POINTER		0x228	/* Relative to real mode data */
-
-#ifndef __ASSEMBLY__
-#include <asm/bootparam.h>
-
-#ifndef _SETUP
-
-/*
- * This is set up by the setup-routine at boot-time
- */
-extern struct boot_params boot_params;
-
-/*
- * Do NOT EVER look at the BIOS memory size location.
- * It does not work on many machines.
- */
-#define LOWMEMSIZE()	(0x9f000)
-
-#ifdef __i386__
-
-void __init i386_start_kernel(void);
-extern void probe_roms(void);
-
-extern unsigned long init_pg_tables_start;
-extern unsigned long init_pg_tables_end;
-
-#else
-void __init x86_64_init_pda(void);
-void __init x86_64_start_kernel(char *real_mode);
-void __init x86_64_start_reservations(char *real_mode_data);
-
-#endif /* __i386__ */
-#endif /* _SETUP */
-#endif /* __ASSEMBLY__ */
-#endif  /*  __KERNEL__  */
-
-#endif /* ASM_X86__SETUP_H */
diff --git a/include/asm-x86/shmbuf.h b/include/asm-x86/shmbuf.h
deleted file mode 100644
index f51aec2298e9..000000000000
--- a/include/asm-x86/shmbuf.h
+++ /dev/null
@@ -1,51 +0,0 @@
-#ifndef ASM_X86__SHMBUF_H
-#define ASM_X86__SHMBUF_H
-
-/*
- * The shmid64_ds structure for x86 architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space on 32 bit is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- *
- * Pad space on 64 bit is left for:
- * - 2 miscellaneous 64-bit values
- */
-
-struct shmid64_ds {
-	struct ipc64_perm	shm_perm;	/* operation perms */
-	size_t			shm_segsz;	/* size of segment (bytes) */
-	__kernel_time_t		shm_atime;	/* last attach time */
-#ifdef __i386__
-	unsigned long		__unused1;
-#endif
-	__kernel_time_t		shm_dtime;	/* last detach time */
-#ifdef __i386__
-	unsigned long		__unused2;
-#endif
-	__kernel_time_t		shm_ctime;	/* last change time */
-#ifdef __i386__
-	unsigned long		__unused3;
-#endif
-	__kernel_pid_t		shm_cpid;	/* pid of creator */
-	__kernel_pid_t		shm_lpid;	/* pid of last operator */
-	unsigned long		shm_nattch;	/* no. of current attaches */
-	unsigned long		__unused4;
-	unsigned long		__unused5;
-};
-
-struct shminfo64 {
-	unsigned long	shmmax;
-	unsigned long	shmmin;
-	unsigned long	shmmni;
-	unsigned long	shmseg;
-	unsigned long	shmall;
-	unsigned long	__unused1;
-	unsigned long	__unused2;
-	unsigned long	__unused3;
-	unsigned long	__unused4;
-};
-
-#endif /* ASM_X86__SHMBUF_H */
diff --git a/include/asm-x86/shmparam.h b/include/asm-x86/shmparam.h
deleted file mode 100644
index a83a1fd96a0e..000000000000
--- a/include/asm-x86/shmparam.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef ASM_X86__SHMPARAM_H
-#define ASM_X86__SHMPARAM_H
-
-#define SHMLBA PAGE_SIZE	 /* attach addr a multiple of this */
-
-#endif /* ASM_X86__SHMPARAM_H */
diff --git a/include/asm-x86/sigcontext.h b/include/asm-x86/sigcontext.h
deleted file mode 100644
index ee813f4fe5d5..000000000000
--- a/include/asm-x86/sigcontext.h
+++ /dev/null
@@ -1,284 +0,0 @@
-#ifndef ASM_X86__SIGCONTEXT_H
-#define ASM_X86__SIGCONTEXT_H
-
-#include <linux/compiler.h>
-#include <asm/types.h>
-
-#define FP_XSTATE_MAGIC1	0x46505853U
-#define FP_XSTATE_MAGIC2	0x46505845U
-#define FP_XSTATE_MAGIC2_SIZE	sizeof(FP_XSTATE_MAGIC2)
-
-/*
- * bytes 464..511 in the current 512byte layout of fxsave/fxrstor frame
- * are reserved for SW usage. On cpu's supporting xsave/xrstor, these bytes
- * are used to extended the fpstate pointer in the sigcontext, which now
- * includes the extended state information along with fpstate information.
- *
- * Presence of FP_XSTATE_MAGIC1 at the beginning of this SW reserved
- * area and FP_XSTATE_MAGIC2 at the end of memory layout
- * (extended_size - FP_XSTATE_MAGIC2_SIZE) indicates the presence of the
- * extended state information in the memory layout pointed by the fpstate
- * pointer in sigcontext.
- */
-struct _fpx_sw_bytes {
-	__u32 magic1;		/* FP_XSTATE_MAGIC1 */
-	__u32 extended_size;	/* total size of the layout referred by
-				 * fpstate pointer in the sigcontext.
-				 */
-	__u64 xstate_bv;
-				/* feature bit mask (including fp/sse/extended
-				 * state) that is present in the memory
-				 * layout.
-				 */
-	__u32 xstate_size;	/* actual xsave state size, based on the
-				 * features saved in the layout.
-				 * 'extended_size' will be greater than
-				 * 'xstate_size'.
-				 */
-	__u32 padding[7];	/*  for future use. */
-};
-
-#ifdef __i386__
-/*
- * As documented in the iBCS2 standard..
- *
- * The first part of "struct _fpstate" is just the normal i387
- * hardware setup, the extra "status" word is used to save the
- * coprocessor status word before entering the handler.
- *
- * Pentium III FXSR, SSE support
- *	Gareth Hughes <gareth@valinux.com>, May 2000
- *
- * The FPU state data structure has had to grow to accommodate the
- * extended FPU state required by the Streaming SIMD Extensions.
- * There is no documented standard to accomplish this at the moment.
- */
-struct _fpreg {
-	unsigned short significand[4];
-	unsigned short exponent;
-};
-
-struct _fpxreg {
-	unsigned short significand[4];
-	unsigned short exponent;
-	unsigned short padding[3];
-};
-
-struct _xmmreg {
-	unsigned long element[4];
-};
-
-struct _fpstate {
-	/* Regular FPU environment */
-	unsigned long	cw;
-	unsigned long	sw;
-	unsigned long	tag;
-	unsigned long	ipoff;
-	unsigned long	cssel;
-	unsigned long	dataoff;
-	unsigned long	datasel;
-	struct _fpreg	_st[8];
-	unsigned short	status;
-	unsigned short	magic;		/* 0xffff = regular FPU data only */
-
-	/* FXSR FPU environment */
-	unsigned long	_fxsr_env[6];	/* FXSR FPU env is ignored */
-	unsigned long	mxcsr;
-	unsigned long	reserved;
-	struct _fpxreg	_fxsr_st[8];	/* FXSR FPU reg data is ignored */
-	struct _xmmreg	_xmm[8];
-	unsigned long	padding1[44];
-
-	union {
-		unsigned long	padding2[12];
-		struct _fpx_sw_bytes sw_reserved; /* represents the extended
-						   * state info */
-	};
-};
-
-#define X86_FXSR_MAGIC		0x0000
-
-#ifdef __KERNEL__
-struct sigcontext {
-	unsigned short gs, __gsh;
-	unsigned short fs, __fsh;
-	unsigned short es, __esh;
-	unsigned short ds, __dsh;
-	unsigned long di;
-	unsigned long si;
-	unsigned long bp;
-	unsigned long sp;
-	unsigned long bx;
-	unsigned long dx;
-	unsigned long cx;
-	unsigned long ax;
-	unsigned long trapno;
-	unsigned long err;
-	unsigned long ip;
-	unsigned short cs, __csh;
-	unsigned long flags;
-	unsigned long sp_at_signal;
-	unsigned short ss, __ssh;
-
-	/*
-	 * fpstate is really (struct _fpstate *) or (struct _xstate *)
-	 * depending on the FP_XSTATE_MAGIC1 encoded in the SW reserved
-	 * bytes of (struct _fpstate) and FP_XSTATE_MAGIC2 present at the end
-	 * of extended memory layout. See comments at the defintion of
-	 * (struct _fpx_sw_bytes)
-	 */
-	void __user *fpstate;		/* zero when no FPU/extended context */
-	unsigned long oldmask;
-	unsigned long cr2;
-};
-#else /* __KERNEL__ */
-/*
- * User-space might still rely on the old definition:
- */
-struct sigcontext {
-	unsigned short gs, __gsh;
-	unsigned short fs, __fsh;
-	unsigned short es, __esh;
-	unsigned short ds, __dsh;
-	unsigned long edi;
-	unsigned long esi;
-	unsigned long ebp;
-	unsigned long esp;
-	unsigned long ebx;
-	unsigned long edx;
-	unsigned long ecx;
-	unsigned long eax;
-	unsigned long trapno;
-	unsigned long err;
-	unsigned long eip;
-	unsigned short cs, __csh;
-	unsigned long eflags;
-	unsigned long esp_at_signal;
-	unsigned short ss, __ssh;
-	struct _fpstate __user *fpstate;
-	unsigned long oldmask;
-	unsigned long cr2;
-};
-#endif /* !__KERNEL__ */
-
-#else /* __i386__ */
-
-/* FXSAVE frame */
-/* Note: reserved1/2 may someday contain valuable data. Always save/restore
-   them when you change signal frames. */
-struct _fpstate {
-	__u16	cwd;
-	__u16	swd;
-	__u16	twd;		/* Note this is not the same as the
-				   32bit/x87/FSAVE twd */
-	__u16	fop;
-	__u64	rip;
-	__u64	rdp;
-	__u32	mxcsr;
-	__u32	mxcsr_mask;
-	__u32	st_space[32];	/* 8*16 bytes for each FP-reg */
-	__u32	xmm_space[64];	/* 16*16 bytes for each XMM-reg  */
-	__u32	reserved2[12];
-	union {
-		__u32	reserved3[12];
-		struct _fpx_sw_bytes sw_reserved; /* represents the extended
-						   * state information */
-	};
-};
-
-#ifdef __KERNEL__
-struct sigcontext {
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long r11;
-	unsigned long r12;
-	unsigned long r13;
-	unsigned long r14;
-	unsigned long r15;
-	unsigned long di;
-	unsigned long si;
-	unsigned long bp;
-	unsigned long bx;
-	unsigned long dx;
-	unsigned long ax;
-	unsigned long cx;
-	unsigned long sp;
-	unsigned long ip;
-	unsigned long flags;
-	unsigned short cs;
-	unsigned short gs;
-	unsigned short fs;
-	unsigned short __pad0;
-	unsigned long err;
-	unsigned long trapno;
-	unsigned long oldmask;
-	unsigned long cr2;
-
-	/*
-	 * fpstate is really (struct _fpstate *) or (struct _xstate *)
-	 * depending on the FP_XSTATE_MAGIC1 encoded in the SW reserved
-	 * bytes of (struct _fpstate) and FP_XSTATE_MAGIC2 present at the end
-	 * of extended memory layout. See comments at the defintion of
-	 * (struct _fpx_sw_bytes)
-	 */
-	void __user *fpstate;		/* zero when no FPU/extended context */
-	unsigned long reserved1[8];
-};
-#else /* __KERNEL__ */
-/*
- * User-space might still rely on the old definition:
- */
-struct sigcontext {
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long r11;
-	unsigned long r12;
-	unsigned long r13;
-	unsigned long r14;
-	unsigned long r15;
-	unsigned long rdi;
-	unsigned long rsi;
-	unsigned long rbp;
-	unsigned long rbx;
-	unsigned long rdx;
-	unsigned long rax;
-	unsigned long rcx;
-	unsigned long rsp;
-	unsigned long rip;
-	unsigned long eflags;		/* RFLAGS */
-	unsigned short cs;
-	unsigned short gs;
-	unsigned short fs;
-	unsigned short __pad0;
-	unsigned long err;
-	unsigned long trapno;
-	unsigned long oldmask;
-	unsigned long cr2;
-	struct _fpstate __user *fpstate;	/* zero when no FPU context */
-	unsigned long reserved1[8];
-};
-#endif /* !__KERNEL__ */
-
-#endif /* !__i386__ */
-
-struct _xsave_hdr {
-	__u64 xstate_bv;
-	__u64 reserved1[2];
-	__u64 reserved2[5];
-};
-
-/*
- * Extended state pointed by the fpstate pointer in the sigcontext.
- * In addition to the fpstate, information encoded in the xstate_hdr
- * indicates the presence of other extended state information
- * supported by the processor and OS.
- */
-struct _xstate {
-	struct _fpstate fpstate;
-	struct _xsave_hdr xstate_hdr;
-	/* new processor state extensions go here */
-};
-
-#endif /* ASM_X86__SIGCONTEXT_H */
diff --git a/include/asm-x86/sigcontext32.h b/include/asm-x86/sigcontext32.h
deleted file mode 100644
index 8c347032c2f2..000000000000
--- a/include/asm-x86/sigcontext32.h
+++ /dev/null
@@ -1,75 +0,0 @@
-#ifndef ASM_X86__SIGCONTEXT32_H
-#define ASM_X86__SIGCONTEXT32_H
-
-/* signal context for 32bit programs. */
-
-#define X86_FXSR_MAGIC		0x0000
-
-struct _fpreg {
-	unsigned short significand[4];
-	unsigned short exponent;
-};
-
-struct _fpxreg {
-	unsigned short significand[4];
-	unsigned short exponent;
-	unsigned short padding[3];
-};
-
-struct _xmmreg {
-	__u32	element[4];
-};
-
-/* FSAVE frame with extensions */
-struct _fpstate_ia32 {
-	/* Regular FPU environment */
-	__u32 	cw;
-	__u32	sw;
-	__u32	tag;	/* not compatible to 64bit twd */
-	__u32	ipoff;
-	__u32	cssel;
-	__u32	dataoff;
-	__u32	datasel;
-	struct _fpreg	_st[8];
-	unsigned short	status;
-	unsigned short	magic;		/* 0xffff = regular FPU data only */
-
-	/* FXSR FPU environment */
-	__u32	_fxsr_env[6];
-	__u32	mxcsr;
-	__u32	reserved;
-	struct _fpxreg	_fxsr_st[8];
-	struct _xmmreg	_xmm[8];	/* It's actually 16 */
-	__u32	padding[44];
-	union {
-		__u32 padding2[12];
-		struct _fpx_sw_bytes sw_reserved;
-	};
-};
-
-struct sigcontext_ia32 {
-       unsigned short gs, __gsh;
-       unsigned short fs, __fsh;
-       unsigned short es, __esh;
-       unsigned short ds, __dsh;
-       unsigned int di;
-       unsigned int si;
-       unsigned int bp;
-       unsigned int sp;
-       unsigned int bx;
-       unsigned int dx;
-       unsigned int cx;
-       unsigned int ax;
-       unsigned int trapno;
-       unsigned int err;
-       unsigned int ip;
-       unsigned short cs, __csh;
-       unsigned int flags;
-       unsigned int sp_at_signal;
-       unsigned short ss, __ssh;
-       unsigned int fpstate;		/* really (struct _fpstate_ia32 *) */
-       unsigned int oldmask;
-       unsigned int cr2;
-};
-
-#endif /* ASM_X86__SIGCONTEXT32_H */
diff --git a/include/asm-x86/siginfo.h b/include/asm-x86/siginfo.h
deleted file mode 100644
index 808bdfb2958c..000000000000
--- a/include/asm-x86/siginfo.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef ASM_X86__SIGINFO_H
-#define ASM_X86__SIGINFO_H
-
-#ifdef __x86_64__
-# define __ARCH_SI_PREAMBLE_SIZE	(4 * sizeof(int))
-#endif
-
-#include <asm-generic/siginfo.h>
-
-#endif /* ASM_X86__SIGINFO_H */
diff --git a/include/asm-x86/signal.h b/include/asm-x86/signal.h
deleted file mode 100644
index 65acc82d267a..000000000000
--- a/include/asm-x86/signal.h
+++ /dev/null
@@ -1,262 +0,0 @@
-#ifndef ASM_X86__SIGNAL_H
-#define ASM_X86__SIGNAL_H
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#include <linux/time.h>
-#include <linux/compiler.h>
-
-/* Avoid too many header ordering problems.  */
-struct siginfo;
-
-#ifdef __KERNEL__
-#include <linux/linkage.h>
-
-/* Most things should be clean enough to redefine this at will, if care
-   is taken to make libc match.  */
-
-#define _NSIG		64
-
-#ifdef __i386__
-# define _NSIG_BPW	32
-#else
-# define _NSIG_BPW	64
-#endif
-
-#define _NSIG_WORDS	(_NSIG / _NSIG_BPW)
-
-typedef unsigned long old_sigset_t;		/* at least 32 bits */
-
-typedef struct {
-	unsigned long sig[_NSIG_WORDS];
-} sigset_t;
-
-#else
-/* Here we must cater to libcs that poke about in kernel headers.  */
-
-#define NSIG		32
-typedef unsigned long sigset_t;
-
-#endif /* __KERNEL__ */
-#endif /* __ASSEMBLY__ */
-
-#define SIGHUP		 1
-#define SIGINT		 2
-#define SIGQUIT		 3
-#define SIGILL		 4
-#define SIGTRAP		 5
-#define SIGABRT		 6
-#define SIGIOT		 6
-#define SIGBUS		 7
-#define SIGFPE		 8
-#define SIGKILL		 9
-#define SIGUSR1		10
-#define SIGSEGV		11
-#define SIGUSR2		12
-#define SIGPIPE		13
-#define SIGALRM		14
-#define SIGTERM		15
-#define SIGSTKFLT	16
-#define SIGCHLD		17
-#define SIGCONT		18
-#define SIGSTOP		19
-#define SIGTSTP		20
-#define SIGTTIN		21
-#define SIGTTOU		22
-#define SIGURG		23
-#define SIGXCPU		24
-#define SIGXFSZ		25
-#define SIGVTALRM	26
-#define SIGPROF		27
-#define SIGWINCH	28
-#define SIGIO		29
-#define SIGPOLL		SIGIO
-/*
-#define SIGLOST		29
-*/
-#define SIGPWR		30
-#define SIGSYS		31
-#define	SIGUNUSED	31
-
-/* These should not be considered constants from userland.  */
-#define SIGRTMIN	32
-#define SIGRTMAX	_NSIG
-
-/*
- * SA_FLAGS values:
- *
- * SA_ONSTACK indicates that a registered stack_t will be used.
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
- * SA_RESETHAND clears the handler when the signal is delivered.
- * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
- * SA_NODEFER prevents the current signal from being masked in the handler.
- *
- * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
- * Unix names RESETHAND and NODEFER respectively.
- */
-#define SA_NOCLDSTOP	0x00000001u
-#define SA_NOCLDWAIT	0x00000002u
-#define SA_SIGINFO	0x00000004u
-#define SA_ONSTACK	0x08000000u
-#define SA_RESTART	0x10000000u
-#define SA_NODEFER	0x40000000u
-#define SA_RESETHAND	0x80000000u
-
-#define SA_NOMASK	SA_NODEFER
-#define SA_ONESHOT	SA_RESETHAND
-
-#define SA_RESTORER	0x04000000
-
-/*
- * sigaltstack controls
- */
-#define SS_ONSTACK	1
-#define SS_DISABLE	2
-
-#define MINSIGSTKSZ	2048
-#define SIGSTKSZ	8192
-
-#include <asm-generic/signal.h>
-
-#ifndef __ASSEMBLY__
-
-#ifdef __i386__
-# ifdef __KERNEL__
-struct old_sigaction {
-	__sighandler_t sa_handler;
-	old_sigset_t sa_mask;
-	unsigned long sa_flags;
-	__sigrestore_t sa_restorer;
-};
-
-struct sigaction {
-	__sighandler_t sa_handler;
-	unsigned long sa_flags;
-	__sigrestore_t sa_restorer;
-	sigset_t sa_mask;		/* mask last for extensibility */
-};
-
-struct k_sigaction {
-	struct sigaction sa;
-};
-
-extern void do_notify_resume(struct pt_regs *, void *, __u32);
-
-# else /* __KERNEL__ */
-/* Here we must cater to libcs that poke about in kernel headers.  */
-
-struct sigaction {
-	union {
-	  __sighandler_t _sa_handler;
-	  void (*_sa_sigaction)(int, struct siginfo *, void *);
-	} _u;
-	sigset_t sa_mask;
-	unsigned long sa_flags;
-	void (*sa_restorer)(void);
-};
-
-#define sa_handler	_u._sa_handler
-#define sa_sigaction	_u._sa_sigaction
-
-# endif /* ! __KERNEL__ */
-#else /* __i386__ */
-
-struct sigaction {
-	__sighandler_t sa_handler;
-	unsigned long sa_flags;
-	__sigrestore_t sa_restorer;
-	sigset_t sa_mask;		/* mask last for extensibility */
-};
-
-struct k_sigaction {
-	struct sigaction sa;
-};
-
-#endif /* !__i386__ */
-
-typedef struct sigaltstack {
-	void __user *ss_sp;
-	int ss_flags;
-	size_t ss_size;
-} stack_t;
-
-#ifdef __KERNEL__
-#include <asm/sigcontext.h>
-
-#ifdef __i386__
-
-#define __HAVE_ARCH_SIG_BITOPS
-
-#define sigaddset(set,sig)		    \
-	(__builtin_constant_p(sig)	    \
-	 ? __const_sigaddset((set), (sig))  \
-	 : __gen_sigaddset((set), (sig)))
-
-static inline void __gen_sigaddset(sigset_t *set, int _sig)
-{
-	asm("btsl %1,%0" : "+m"(*set) : "Ir"(_sig - 1) : "cc");
-}
-
-static inline void __const_sigaddset(sigset_t *set, int _sig)
-{
-	unsigned long sig = _sig - 1;
-	set->sig[sig / _NSIG_BPW] |= 1 << (sig % _NSIG_BPW);
-}
-
-#define sigdelset(set, sig)		    \
-	(__builtin_constant_p(sig)	    \
-	 ? __const_sigdelset((set), (sig))  \
-	 : __gen_sigdelset((set), (sig)))
-
-
-static inline void __gen_sigdelset(sigset_t *set, int _sig)
-{
-	asm("btrl %1,%0" : "+m"(*set) : "Ir"(_sig - 1) : "cc");
-}
-
-static inline void __const_sigdelset(sigset_t *set, int _sig)
-{
-	unsigned long sig = _sig - 1;
-	set->sig[sig / _NSIG_BPW] &= ~(1 << (sig % _NSIG_BPW));
-}
-
-static inline int __const_sigismember(sigset_t *set, int _sig)
-{
-	unsigned long sig = _sig - 1;
-	return 1 & (set->sig[sig / _NSIG_BPW] >> (sig % _NSIG_BPW));
-}
-
-static inline int __gen_sigismember(sigset_t *set, int _sig)
-{
-	int ret;
-	asm("btl %2,%1\n\tsbbl %0,%0"
-	    : "=r"(ret) : "m"(*set), "Ir"(_sig-1) : "cc");
-	return ret;
-}
-
-#define sigismember(set, sig)			\
-	(__builtin_constant_p(sig)		\
-	 ? __const_sigismember((set), (sig))	\
-	 : __gen_sigismember((set), (sig)))
-
-static inline int sigfindinword(unsigned long word)
-{
-	asm("bsfl %1,%0" : "=r"(word) : "rm"(word) : "cc");
-	return word;
-}
-
-struct pt_regs;
-
-#else /* __i386__ */
-
-#undef __HAVE_ARCH_SIG_BITOPS
-
-#endif /* !__i386__ */
-
-#define ptrace_signal_deliver(regs, cookie) do { } while (0)
-
-#endif /* __KERNEL__ */
-#endif /* __ASSEMBLY__ */
-
-#endif /* ASM_X86__SIGNAL_H */
diff --git a/include/asm-x86/smp.h b/include/asm-x86/smp.h
deleted file mode 100644
index a6afc29f2dd9..000000000000
--- a/include/asm-x86/smp.h
+++ /dev/null
@@ -1,229 +0,0 @@
-#ifndef ASM_X86__SMP_H
-#define ASM_X86__SMP_H
-#ifndef __ASSEMBLY__
-#include <linux/cpumask.h>
-#include <linux/init.h>
-#include <asm/percpu.h>
-
-/*
- * We need the APIC definitions automatically as part of 'smp.h'
- */
-#ifdef CONFIG_X86_LOCAL_APIC
-# include <asm/mpspec.h>
-# include <asm/apic.h>
-# ifdef CONFIG_X86_IO_APIC
-#  include <asm/io_apic.h>
-# endif
-#endif
-#include <asm/pda.h>
-#include <asm/thread_info.h>
-
-extern cpumask_t cpu_callout_map;
-extern cpumask_t cpu_initialized;
-extern cpumask_t cpu_callin_map;
-
-extern void (*mtrr_hook)(void);
-extern void zap_low_mappings(void);
-
-extern int __cpuinit get_local_pda(int cpu);
-
-extern int smp_num_siblings;
-extern unsigned int num_processors;
-extern cpumask_t cpu_initialized;
-
-DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
-DECLARE_PER_CPU(cpumask_t, cpu_core_map);
-DECLARE_PER_CPU(u16, cpu_llc_id);
-#ifdef CONFIG_X86_32
-DECLARE_PER_CPU(int, cpu_number);
-#endif
-
-DECLARE_EARLY_PER_CPU(u16, x86_cpu_to_apicid);
-DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
-
-/* Static state in head.S used to set up a CPU */
-extern struct {
-	void *sp;
-	unsigned short ss;
-} stack_start;
-
-struct smp_ops {
-	void (*smp_prepare_boot_cpu)(void);
-	void (*smp_prepare_cpus)(unsigned max_cpus);
-	void (*smp_cpus_done)(unsigned max_cpus);
-
-	void (*smp_send_stop)(void);
-	void (*smp_send_reschedule)(int cpu);
-
-	int (*cpu_up)(unsigned cpu);
-	int (*cpu_disable)(void);
-	void (*cpu_die)(unsigned int cpu);
-	void (*play_dead)(void);
-
-	void (*send_call_func_ipi)(cpumask_t mask);
-	void (*send_call_func_single_ipi)(int cpu);
-};
-
-/* Globals due to paravirt */
-extern void set_cpu_sibling_map(int cpu);
-
-#ifdef CONFIG_SMP
-#ifndef CONFIG_PARAVIRT
-#define startup_ipi_hook(phys_apicid, start_eip, start_esp) do { } while (0)
-#endif
-extern struct smp_ops smp_ops;
-
-static inline void smp_send_stop(void)
-{
-	smp_ops.smp_send_stop();
-}
-
-static inline void smp_prepare_boot_cpu(void)
-{
-	smp_ops.smp_prepare_boot_cpu();
-}
-
-static inline void smp_prepare_cpus(unsigned int max_cpus)
-{
-	smp_ops.smp_prepare_cpus(max_cpus);
-}
-
-static inline void smp_cpus_done(unsigned int max_cpus)
-{
-	smp_ops.smp_cpus_done(max_cpus);
-}
-
-static inline int __cpu_up(unsigned int cpu)
-{
-	return smp_ops.cpu_up(cpu);
-}
-
-static inline int __cpu_disable(void)
-{
-	return smp_ops.cpu_disable();
-}
-
-static inline void __cpu_die(unsigned int cpu)
-{
-	smp_ops.cpu_die(cpu);
-}
-
-static inline void play_dead(void)
-{
-	smp_ops.play_dead();
-}
-
-static inline void smp_send_reschedule(int cpu)
-{
-	smp_ops.smp_send_reschedule(cpu);
-}
-
-static inline void arch_send_call_function_single_ipi(int cpu)
-{
-	smp_ops.send_call_func_single_ipi(cpu);
-}
-
-static inline void arch_send_call_function_ipi(cpumask_t mask)
-{
-	smp_ops.send_call_func_ipi(mask);
-}
-
-void cpu_disable_common(void);
-void native_smp_prepare_boot_cpu(void);
-void native_smp_prepare_cpus(unsigned int max_cpus);
-void native_smp_cpus_done(unsigned int max_cpus);
-int native_cpu_up(unsigned int cpunum);
-int native_cpu_disable(void);
-void native_cpu_die(unsigned int cpu);
-void native_play_dead(void);
-void play_dead_common(void);
-
-void native_send_call_func_ipi(cpumask_t mask);
-void native_send_call_func_single_ipi(int cpu);
-
-extern void prefill_possible_map(void);
-
-void smp_store_cpu_info(int id);
-#define cpu_physical_id(cpu)	per_cpu(x86_cpu_to_apicid, cpu)
-
-/* We don't mark CPUs online until __cpu_up(), so we need another measure */
-static inline int num_booting_cpus(void)
-{
-	return cpus_weight(cpu_callout_map);
-}
-#else
-static inline void prefill_possible_map(void)
-{
-}
-#endif /* CONFIG_SMP */
-
-extern unsigned disabled_cpus __cpuinitdata;
-
-#ifdef CONFIG_X86_32_SMP
-/*
- * This function is needed by all SMP systems. It must _always_ be valid
- * from the initial startup. We map APIC_BASE very early in page_setup(),
- * so this is correct in the x86 case.
- */
-#define raw_smp_processor_id() (x86_read_percpu(cpu_number))
-extern int safe_smp_processor_id(void);
-
-#elif defined(CONFIG_X86_64_SMP)
-#define raw_smp_processor_id()	read_pda(cpunumber)
-
-#define stack_smp_processor_id()					\
-({								\
-	struct thread_info *ti;						\
-	__asm__("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK));	\
-	ti->cpu;							\
-})
-#define safe_smp_processor_id()		smp_processor_id()
-
-#else /* !CONFIG_X86_32_SMP && !CONFIG_X86_64_SMP */
-#define cpu_physical_id(cpu)		boot_cpu_physical_apicid
-#define safe_smp_processor_id()		0
-#define stack_smp_processor_id() 	0
-#endif
-
-#ifdef CONFIG_X86_LOCAL_APIC
-
-#ifndef CONFIG_X86_64
-static inline int logical_smp_processor_id(void)
-{
-	/* we don't want to mark this access volatile - bad code generation */
-	return GET_APIC_LOGICAL_ID(*(u32 *)(APIC_BASE + APIC_LDR));
-}
-
-#include <mach_apicdef.h>
-static inline unsigned int read_apic_id(void)
-{
-	unsigned int reg;
-
-	reg = *(u32 *)(APIC_BASE + APIC_ID);
-
-	return GET_APIC_ID(reg);
-}
-#endif
-
-
-# if defined(APIC_DEFINITION) || defined(CONFIG_X86_64)
-extern int hard_smp_processor_id(void);
-# else
-#include <mach_apicdef.h>
-static inline int hard_smp_processor_id(void)
-{
-	/* we don't want to mark this access volatile - bad code generation */
-	return read_apic_id();
-}
-# endif /* APIC_DEFINITION */
-
-#else /* CONFIG_X86_LOCAL_APIC */
-
-# ifndef CONFIG_SMP
-#  define hard_smp_processor_id()	0
-# endif
-
-#endif /* CONFIG_X86_LOCAL_APIC */
-
-#endif /* __ASSEMBLY__ */
-#endif /* ASM_X86__SMP_H */
diff --git a/include/asm-x86/socket.h b/include/asm-x86/socket.h
deleted file mode 100644
index db73274c83c3..000000000000
--- a/include/asm-x86/socket.h
+++ /dev/null
@@ -1,57 +0,0 @@
-#ifndef ASM_X86__SOCKET_H
-#define ASM_X86__SOCKET_H
-
-#include <asm/sockios.h>
-
-/* For setsockopt(2) */
-#define SOL_SOCKET	1
-
-#define SO_DEBUG	1
-#define SO_REUSEADDR	2
-#define SO_TYPE		3
-#define SO_ERROR	4
-#define SO_DONTROUTE	5
-#define SO_BROADCAST	6
-#define SO_SNDBUF	7
-#define SO_RCVBUF	8
-#define SO_SNDBUFFORCE	32
-#define SO_RCVBUFFORCE	33
-#define SO_KEEPALIVE	9
-#define SO_OOBINLINE	10
-#define SO_NO_CHECK	11
-#define SO_PRIORITY	12
-#define SO_LINGER	13
-#define SO_BSDCOMPAT	14
-/* To add :#define SO_REUSEPORT 15 */
-#define SO_PASSCRED	16
-#define SO_PEERCRED	17
-#define SO_RCVLOWAT	18
-#define SO_SNDLOWAT	19
-#define SO_RCVTIMEO	20
-#define SO_SNDTIMEO	21
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION		22
-#define SO_SECURITY_ENCRYPTION_TRANSPORT	23
-#define SO_SECURITY_ENCRYPTION_NETWORK		24
-
-#define SO_BINDTODEVICE	25
-
-/* Socket filtering */
-#define SO_ATTACH_FILTER        26
-#define SO_DETACH_FILTER        27
-
-#define SO_PEERNAME		28
-#define SO_TIMESTAMP		29
-#define SCM_TIMESTAMP		SO_TIMESTAMP
-
-#define SO_ACCEPTCONN		30
-
-#define SO_PEERSEC		31
-#define SO_PASSSEC		34
-#define SO_TIMESTAMPNS		35
-#define SCM_TIMESTAMPNS		SO_TIMESTAMPNS
-
-#define SO_MARK			36
-
-#endif /* ASM_X86__SOCKET_H */
diff --git a/include/asm-x86/sockios.h b/include/asm-x86/sockios.h
deleted file mode 100644
index a006704fdc84..000000000000
--- a/include/asm-x86/sockios.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef ASM_X86__SOCKIOS_H
-#define ASM_X86__SOCKIOS_H
-
-/* Socket-level I/O control calls. */
-#define FIOSETOWN	0x8901
-#define SIOCSPGRP	0x8902
-#define FIOGETOWN	0x8903
-#define SIOCGPGRP	0x8904
-#define SIOCATMARK	0x8905
-#define SIOCGSTAMP	0x8906		/* Get stamp (timeval) */
-#define SIOCGSTAMPNS	0x8907		/* Get stamp (timespec) */
-
-#endif /* ASM_X86__SOCKIOS_H */
diff --git a/include/asm-x86/sparsemem.h b/include/asm-x86/sparsemem.h
deleted file mode 100644
index 38f8e6bc3186..000000000000
--- a/include/asm-x86/sparsemem.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef ASM_X86__SPARSEMEM_H
-#define ASM_X86__SPARSEMEM_H
-
-#ifdef CONFIG_SPARSEMEM
-/*
- * generic non-linear memory support:
- *
- * 1) we will not split memory into more chunks than will fit into the flags
- *    field of the struct page
- *
- * SECTION_SIZE_BITS		2^n: size of each section
- * MAX_PHYSADDR_BITS		2^n: max size of physical address space
- * MAX_PHYSMEM_BITS		2^n: how much memory we can have in that space
- *
- */
-
-#ifdef CONFIG_X86_32
-# ifdef CONFIG_X86_PAE
-#  define SECTION_SIZE_BITS	29
-#  define MAX_PHYSADDR_BITS	36
-#  define MAX_PHYSMEM_BITS	36
-# else
-#  define SECTION_SIZE_BITS	26
-#  define MAX_PHYSADDR_BITS	32
-#  define MAX_PHYSMEM_BITS	32
-# endif
-#else /* CONFIG_X86_32 */
-# define SECTION_SIZE_BITS	27 /* matt - 128 is convenient right now */
-# define MAX_PHYSADDR_BITS	44
-# define MAX_PHYSMEM_BITS	44
-#endif
-
-#endif /* CONFIG_SPARSEMEM */
-#endif /* ASM_X86__SPARSEMEM_H */
diff --git a/include/asm-x86/spinlock.h b/include/asm-x86/spinlock.h
deleted file mode 100644
index 157ff7fab97a..000000000000
--- a/include/asm-x86/spinlock.h
+++ /dev/null
@@ -1,364 +0,0 @@
-#ifndef ASM_X86__SPINLOCK_H
-#define ASM_X86__SPINLOCK_H
-
-#include <asm/atomic.h>
-#include <asm/rwlock.h>
-#include <asm/page.h>
-#include <asm/processor.h>
-#include <linux/compiler.h>
-#include <asm/paravirt.h>
-/*
- * Your basic SMP spinlocks, allowing only a single CPU anywhere
- *
- * Simple spin lock operations.  There are two variants, one clears IRQ's
- * on the local processor, one does not.
- *
- * These are fair FIFO ticket locks, which are currently limited to 256
- * CPUs.
- *
- * (the type definitions are in asm/spinlock_types.h)
- */
-
-#ifdef CONFIG_X86_32
-# define LOCK_PTR_REG "a"
-# define REG_PTR_MODE "k"
-#else
-# define LOCK_PTR_REG "D"
-# define REG_PTR_MODE "q"
-#endif
-
-#if defined(CONFIG_X86_32) && \
-	(defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE))
-/*
- * On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock
- * (PPro errata 66, 92)
- */
-# define UNLOCK_LOCK_PREFIX LOCK_PREFIX
-#else
-# define UNLOCK_LOCK_PREFIX
-#endif
-
-/*
- * Ticket locks are conceptually two parts, one indicating the current head of
- * the queue, and the other indicating the current tail. The lock is acquired
- * by atomically noting the tail and incrementing it by one (thus adding
- * ourself to the queue and noting our position), then waiting until the head
- * becomes equal to the the initial value of the tail.
- *
- * We use an xadd covering *both* parts of the lock, to increment the tail and
- * also load the position of the head, which takes care of memory ordering
- * issues and should be optimal for the uncontended case. Note the tail must be
- * in the high part, because a wide xadd increment of the low part would carry
- * up and contaminate the high part.
- *
- * With fewer than 2^8 possible CPUs, we can use x86's partial registers to
- * save some instructions and make the code more elegant. There really isn't
- * much between them in performance though, especially as locks are out of line.
- */
-#if (NR_CPUS < 256)
-#define TICKET_SHIFT 8
-
-static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
-{
-	short inc = 0x0100;
-
-	asm volatile (
-		LOCK_PREFIX "xaddw %w0, %1\n"
-		"1:\t"
-		"cmpb %h0, %b0\n\t"
-		"je 2f\n\t"
-		"rep ; nop\n\t"
-		"movb %1, %b0\n\t"
-		/* don't need lfence here, because loads are in-order */
-		"jmp 1b\n"
-		"2:"
-		: "+Q" (inc), "+m" (lock->slock)
-		:
-		: "memory", "cc");
-}
-
-static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
-{
-	int tmp, new;
-
-	asm volatile("movzwl %2, %0\n\t"
-		     "cmpb %h0,%b0\n\t"
-		     "leal 0x100(%" REG_PTR_MODE "0), %1\n\t"
-		     "jne 1f\n\t"
-		     LOCK_PREFIX "cmpxchgw %w1,%2\n\t"
-		     "1:"
-		     "sete %b1\n\t"
-		     "movzbl %b1,%0\n\t"
-		     : "=&a" (tmp), "=&q" (new), "+m" (lock->slock)
-		     :
-		     : "memory", "cc");
-
-	return tmp;
-}
-
-static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
-{
-	asm volatile(UNLOCK_LOCK_PREFIX "incb %0"
-		     : "+m" (lock->slock)
-		     :
-		     : "memory", "cc");
-}
-#else
-#define TICKET_SHIFT 16
-
-static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
-{
-	int inc = 0x00010000;
-	int tmp;
-
-	asm volatile(LOCK_PREFIX "xaddl %0, %1\n"
-		     "movzwl %w0, %2\n\t"
-		     "shrl $16, %0\n\t"
-		     "1:\t"
-		     "cmpl %0, %2\n\t"
-		     "je 2f\n\t"
-		     "rep ; nop\n\t"
-		     "movzwl %1, %2\n\t"
-		     /* don't need lfence here, because loads are in-order */
-		     "jmp 1b\n"
-		     "2:"
-		     : "+r" (inc), "+m" (lock->slock), "=&r" (tmp)
-		     :
-		     : "memory", "cc");
-}
-
-static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
-{
-	int tmp;
-	int new;
-
-	asm volatile("movl %2,%0\n\t"
-		     "movl %0,%1\n\t"
-		     "roll $16, %0\n\t"
-		     "cmpl %0,%1\n\t"
-		     "leal 0x00010000(%" REG_PTR_MODE "0), %1\n\t"
-		     "jne 1f\n\t"
-		     LOCK_PREFIX "cmpxchgl %1,%2\n\t"
-		     "1:"
-		     "sete %b1\n\t"
-		     "movzbl %b1,%0\n\t"
-		     : "=&a" (tmp), "=&q" (new), "+m" (lock->slock)
-		     :
-		     : "memory", "cc");
-
-	return tmp;
-}
-
-static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
-{
-	asm volatile(UNLOCK_LOCK_PREFIX "incw %0"
-		     : "+m" (lock->slock)
-		     :
-		     : "memory", "cc");
-}
-#endif
-
-static inline int __ticket_spin_is_locked(raw_spinlock_t *lock)
-{
-	int tmp = ACCESS_ONCE(lock->slock);
-
-	return !!(((tmp >> TICKET_SHIFT) ^ tmp) & ((1 << TICKET_SHIFT) - 1));
-}
-
-static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
-{
-	int tmp = ACCESS_ONCE(lock->slock);
-
-	return (((tmp >> TICKET_SHIFT) - tmp) & ((1 << TICKET_SHIFT) - 1)) > 1;
-}
-
-#ifdef CONFIG_PARAVIRT
-/*
- * Define virtualization-friendly old-style lock byte lock, for use in
- * pv_lock_ops if desired.
- *
- * This differs from the pre-2.6.24 spinlock by always using xchgb
- * rather than decb to take the lock; this allows it to use a
- * zero-initialized lock structure.  It also maintains a 1-byte
- * contention counter, so that we can implement
- * __byte_spin_is_contended.
- */
-struct __byte_spinlock {
-	s8 lock;
-	s8 spinners;
-};
-
-static inline int __byte_spin_is_locked(raw_spinlock_t *lock)
-{
-	struct __byte_spinlock *bl = (struct __byte_spinlock *)lock;
-	return bl->lock != 0;
-}
-
-static inline int __byte_spin_is_contended(raw_spinlock_t *lock)
-{
-	struct __byte_spinlock *bl = (struct __byte_spinlock *)lock;
-	return bl->spinners != 0;
-}
-
-static inline void __byte_spin_lock(raw_spinlock_t *lock)
-{
-	struct __byte_spinlock *bl = (struct __byte_spinlock *)lock;
-	s8 val = 1;
-
-	asm("1: xchgb %1, %0\n"
-	    "   test %1,%1\n"
-	    "   jz 3f\n"
-	    "   " LOCK_PREFIX "incb %2\n"
-	    "2: rep;nop\n"
-	    "   cmpb $1, %0\n"
-	    "   je 2b\n"
-	    "   " LOCK_PREFIX "decb %2\n"
-	    "   jmp 1b\n"
-	    "3:"
-	    : "+m" (bl->lock), "+q" (val), "+m" (bl->spinners): : "memory");
-}
-
-static inline int __byte_spin_trylock(raw_spinlock_t *lock)
-{
-	struct __byte_spinlock *bl = (struct __byte_spinlock *)lock;
-	u8 old = 1;
-
-	asm("xchgb %1,%0"
-	    : "+m" (bl->lock), "+q" (old) : : "memory");
-
-	return old == 0;
-}
-
-static inline void __byte_spin_unlock(raw_spinlock_t *lock)
-{
-	struct __byte_spinlock *bl = (struct __byte_spinlock *)lock;
-	smp_wmb();
-	bl->lock = 0;
-}
-#else  /* !CONFIG_PARAVIRT */
-static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
-{
-	return __ticket_spin_is_locked(lock);
-}
-
-static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
-{
-	return __ticket_spin_is_contended(lock);
-}
-
-static __always_inline void __raw_spin_lock(raw_spinlock_t *lock)
-{
-	__ticket_spin_lock(lock);
-}
-
-static __always_inline int __raw_spin_trylock(raw_spinlock_t *lock)
-{
-	return __ticket_spin_trylock(lock);
-}
-
-static __always_inline void __raw_spin_unlock(raw_spinlock_t *lock)
-{
-	__ticket_spin_unlock(lock);
-}
-
-static __always_inline void __raw_spin_lock_flags(raw_spinlock_t *lock,
-						  unsigned long flags)
-{
-	__raw_spin_lock(lock);
-}
-
-#endif	/* CONFIG_PARAVIRT */
-
-static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
-{
-	while (__raw_spin_is_locked(lock))
-		cpu_relax();
-}
-
-/*
- * Read-write spinlocks, allowing multiple readers
- * but only one writer.
- *
- * NOTE! it is quite common to have readers in interrupts
- * but no interrupt writers. For those circumstances we
- * can "mix" irq-safe locks - any writer needs to get a
- * irq-safe write-lock, but readers can get non-irqsafe
- * read-locks.
- *
- * On x86, we implement read-write locks as a 32-bit counter
- * with the high bit (sign) being the "contended" bit.
- */
-
-/**
- * read_can_lock - would read_trylock() succeed?
- * @lock: the rwlock in question.
- */
-static inline int __raw_read_can_lock(raw_rwlock_t *lock)
-{
-	return (int)(lock)->lock > 0;
-}
-
-/**
- * write_can_lock - would write_trylock() succeed?
- * @lock: the rwlock in question.
- */
-static inline int __raw_write_can_lock(raw_rwlock_t *lock)
-{
-	return (lock)->lock == RW_LOCK_BIAS;
-}
-
-static inline void __raw_read_lock(raw_rwlock_t *rw)
-{
-	asm volatile(LOCK_PREFIX " subl $1,(%0)\n\t"
-		     "jns 1f\n"
-		     "call __read_lock_failed\n\t"
-		     "1:\n"
-		     ::LOCK_PTR_REG (rw) : "memory");
-}
-
-static inline void __raw_write_lock(raw_rwlock_t *rw)
-{
-	asm volatile(LOCK_PREFIX " subl %1,(%0)\n\t"
-		     "jz 1f\n"
-		     "call __write_lock_failed\n\t"
-		     "1:\n"
-		     ::LOCK_PTR_REG (rw), "i" (RW_LOCK_BIAS) : "memory");
-}
-
-static inline int __raw_read_trylock(raw_rwlock_t *lock)
-{
-	atomic_t *count = (atomic_t *)lock;
-
-	atomic_dec(count);
-	if (atomic_read(count) >= 0)
-		return 1;
-	atomic_inc(count);
-	return 0;
-}
-
-static inline int __raw_write_trylock(raw_rwlock_t *lock)
-{
-	atomic_t *count = (atomic_t *)lock;
-
-	if (atomic_sub_and_test(RW_LOCK_BIAS, count))
-		return 1;
-	atomic_add(RW_LOCK_BIAS, count);
-	return 0;
-}
-
-static inline void __raw_read_unlock(raw_rwlock_t *rw)
-{
-	asm volatile(LOCK_PREFIX "incl %0" :"+m" (rw->lock) : : "memory");
-}
-
-static inline void __raw_write_unlock(raw_rwlock_t *rw)
-{
-	asm volatile(LOCK_PREFIX "addl %1, %0"
-		     : "+m" (rw->lock) : "i" (RW_LOCK_BIAS) : "memory");
-}
-
-#define _raw_spin_relax(lock)	cpu_relax()
-#define _raw_read_relax(lock)	cpu_relax()
-#define _raw_write_relax(lock)	cpu_relax()
-
-#endif /* ASM_X86__SPINLOCK_H */
diff --git a/include/asm-x86/spinlock_types.h b/include/asm-x86/spinlock_types.h
deleted file mode 100644
index 6aa9b562c508..000000000000
--- a/include/asm-x86/spinlock_types.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef ASM_X86__SPINLOCK_TYPES_H
-#define ASM_X86__SPINLOCK_TYPES_H
-
-#ifndef __LINUX_SPINLOCK_TYPES_H
-# error "please don't include this file directly"
-#endif
-
-typedef struct raw_spinlock {
-	unsigned int slock;
-} raw_spinlock_t;
-
-#define __RAW_SPIN_LOCK_UNLOCKED	{ 0 }
-
-typedef struct {
-	unsigned int lock;
-} raw_rwlock_t;
-
-#define __RAW_RW_LOCK_UNLOCKED		{ RW_LOCK_BIAS }
-
-#endif /* ASM_X86__SPINLOCK_TYPES_H */
diff --git a/include/asm-x86/srat.h b/include/asm-x86/srat.h
deleted file mode 100644
index 5363e4f7e1cd..000000000000
--- a/include/asm-x86/srat.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Some of the code in this file has been gleaned from the 64 bit
- * discontigmem support code base.
- *
- * Copyright (C) 2002, IBM Corp.
- *
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Send feedback to Pat Gaughen <gone@us.ibm.com>
- */
-
-#ifndef ASM_X86__SRAT_H
-#define ASM_X86__SRAT_H
-
-#ifdef CONFIG_ACPI_NUMA
-extern int get_memcfg_from_srat(void);
-#else
-static inline int get_memcfg_from_srat(void)
-{
-	return 0;
-}
-#endif
-
-#endif /* ASM_X86__SRAT_H */
diff --git a/include/asm-x86/stacktrace.h b/include/asm-x86/stacktrace.h
deleted file mode 100644
index f43517e28532..000000000000
--- a/include/asm-x86/stacktrace.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef ASM_X86__STACKTRACE_H
-#define ASM_X86__STACKTRACE_H
-
-extern int kstack_depth_to_print;
-
-/* Generic stack tracer with callbacks */
-
-struct stacktrace_ops {
-	void (*warning)(void *data, char *msg);
-	/* msg must contain %s for the symbol */
-	void (*warning_symbol)(void *data, char *msg, unsigned long symbol);
-	void (*address)(void *data, unsigned long address, int reliable);
-	/* On negative return stop dumping */
-	int (*stack)(void *data, char *name);
-};
-
-void dump_trace(struct task_struct *tsk, struct pt_regs *regs,
-		unsigned long *stack, unsigned long bp,
-		const struct stacktrace_ops *ops, void *data);
-
-#endif /* ASM_X86__STACKTRACE_H */
diff --git a/include/asm-x86/stat.h b/include/asm-x86/stat.h
deleted file mode 100644
index 1e120f628905..000000000000
--- a/include/asm-x86/stat.h
+++ /dev/null
@@ -1,114 +0,0 @@
-#ifndef ASM_X86__STAT_H
-#define ASM_X86__STAT_H
-
-#define STAT_HAVE_NSEC 1
-
-#ifdef __i386__
-struct stat {
-	unsigned long  st_dev;
-	unsigned long  st_ino;
-	unsigned short st_mode;
-	unsigned short st_nlink;
-	unsigned short st_uid;
-	unsigned short st_gid;
-	unsigned long  st_rdev;
-	unsigned long  st_size;
-	unsigned long  st_blksize;
-	unsigned long  st_blocks;
-	unsigned long  st_atime;
-	unsigned long  st_atime_nsec;
-	unsigned long  st_mtime;
-	unsigned long  st_mtime_nsec;
-	unsigned long  st_ctime;
-	unsigned long  st_ctime_nsec;
-	unsigned long  __unused4;
-	unsigned long  __unused5;
-};
-
-#define STAT64_HAS_BROKEN_ST_INO	1
-
-/* This matches struct stat64 in glibc2.1, hence the absolutely
- * insane amounts of padding around dev_t's.
- */
-struct stat64 {
-	unsigned long long	st_dev;
-	unsigned char	__pad0[4];
-
-	unsigned long	__st_ino;
-
-	unsigned int	st_mode;
-	unsigned int	st_nlink;
-
-	unsigned long	st_uid;
-	unsigned long	st_gid;
-
-	unsigned long long	st_rdev;
-	unsigned char	__pad3[4];
-
-	long long	st_size;
-	unsigned long	st_blksize;
-
-	/* Number 512-byte blocks allocated. */
-	unsigned long long	st_blocks;
-
-	unsigned long	st_atime;
-	unsigned long	st_atime_nsec;
-
-	unsigned long	st_mtime;
-	unsigned int	st_mtime_nsec;
-
-	unsigned long	st_ctime;
-	unsigned long	st_ctime_nsec;
-
-	unsigned long long	st_ino;
-};
-
-#else /* __i386__ */
-
-struct stat {
-	unsigned long	st_dev;
-	unsigned long	st_ino;
-	unsigned long	st_nlink;
-
-	unsigned int	st_mode;
-	unsigned int	st_uid;
-	unsigned int	st_gid;
-	unsigned int	__pad0;
-	unsigned long	st_rdev;
-	long		st_size;
-	long		st_blksize;
-	long		st_blocks;	/* Number 512-byte blocks allocated. */
-
-	unsigned long	st_atime;
-	unsigned long	st_atime_nsec;
-	unsigned long	st_mtime;
-	unsigned long	st_mtime_nsec;
-	unsigned long	st_ctime;
-	unsigned long   st_ctime_nsec;
-	long		__unused[3];
-};
-#endif
-
-/* for 32bit emulation and 32 bit kernels */
-struct __old_kernel_stat {
-	unsigned short st_dev;
-	unsigned short st_ino;
-	unsigned short st_mode;
-	unsigned short st_nlink;
-	unsigned short st_uid;
-	unsigned short st_gid;
-	unsigned short st_rdev;
-#ifdef __i386__
-	unsigned long  st_size;
-	unsigned long  st_atime;
-	unsigned long  st_mtime;
-	unsigned long  st_ctime;
-#else
-	unsigned int  st_size;
-	unsigned int  st_atime;
-	unsigned int  st_mtime;
-	unsigned int  st_ctime;
-#endif
-};
-
-#endif /* ASM_X86__STAT_H */
diff --git a/include/asm-x86/statfs.h b/include/asm-x86/statfs.h
deleted file mode 100644
index ca5dc19dd461..000000000000
--- a/include/asm-x86/statfs.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef ASM_X86__STATFS_H
-#define ASM_X86__STATFS_H
-
-/*
- * We need compat_statfs64 to be packed, because the i386 ABI won't
- * add padding at the end to bring it to a multiple of 8 bytes, but
- * the x86_64 ABI will.
- */
-#define ARCH_PACK_COMPAT_STATFS64 __attribute__((packed,aligned(4)))
-
-#include <asm-generic/statfs.h>
-#endif /* ASM_X86__STATFS_H */
diff --git a/include/asm-x86/string.h b/include/asm-x86/string.h
deleted file mode 100644
index 6dfd6d9373a0..000000000000
--- a/include/asm-x86/string.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifdef CONFIG_X86_32
-# include "string_32.h"
-#else
-# include "string_64.h"
-#endif
diff --git a/include/asm-x86/string_32.h b/include/asm-x86/string_32.h
deleted file mode 100644
index 487843ed245a..000000000000
--- a/include/asm-x86/string_32.h
+++ /dev/null
@@ -1,326 +0,0 @@
-#ifndef ASM_X86__STRING_32_H
-#define ASM_X86__STRING_32_H
-
-#ifdef __KERNEL__
-
-/* Let gcc decide whether to inline or use the out of line functions */
-
-#define __HAVE_ARCH_STRCPY
-extern char *strcpy(char *dest, const char *src);
-
-#define __HAVE_ARCH_STRNCPY
-extern char *strncpy(char *dest, const char *src, size_t count);
-
-#define __HAVE_ARCH_STRCAT
-extern char *strcat(char *dest, const char *src);
-
-#define __HAVE_ARCH_STRNCAT
-extern char *strncat(char *dest, const char *src, size_t count);
-
-#define __HAVE_ARCH_STRCMP
-extern int strcmp(const char *cs, const char *ct);
-
-#define __HAVE_ARCH_STRNCMP
-extern int strncmp(const char *cs, const char *ct, size_t count);
-
-#define __HAVE_ARCH_STRCHR
-extern char *strchr(const char *s, int c);
-
-#define __HAVE_ARCH_STRLEN
-extern size_t strlen(const char *s);
-
-static __always_inline void *__memcpy(void *to, const void *from, size_t n)
-{
-	int d0, d1, d2;
-	asm volatile("rep ; movsl\n\t"
-		     "movl %4,%%ecx\n\t"
-		     "andl $3,%%ecx\n\t"
-		     "jz 1f\n\t"
-		     "rep ; movsb\n\t"
-		     "1:"
-		     : "=&c" (d0), "=&D" (d1), "=&S" (d2)
-		     : "0" (n / 4), "g" (n), "1" ((long)to), "2" ((long)from)
-		     : "memory");
-	return to;
-}
-
-/*
- * This looks ugly, but the compiler can optimize it totally,
- * as the count is constant.
- */
-static __always_inline void *__constant_memcpy(void *to, const void *from,
-					       size_t n)
-{
-	long esi, edi;
-	if (!n)
-		return to;
-
-	switch (n) {
-	case 1:
-		*(char *)to = *(char *)from;
-		return to;
-	case 2:
-		*(short *)to = *(short *)from;
-		return to;
-	case 4:
-		*(int *)to = *(int *)from;
-		return to;
-
-	case 3:
-		*(short *)to = *(short *)from;
-		*((char *)to + 2) = *((char *)from + 2);
-		return to;
-	case 5:
-		*(int *)to = *(int *)from;
-		*((char *)to + 4) = *((char *)from + 4);
-		return to;
-	case 6:
-		*(int *)to = *(int *)from;
-		*((short *)to + 2) = *((short *)from + 2);
-		return to;
-	case 8:
-		*(int *)to = *(int *)from;
-		*((int *)to + 1) = *((int *)from + 1);
-		return to;
-	}
-
-	esi = (long)from;
-	edi = (long)to;
-	if (n >= 5 * 4) {
-		/* large block: use rep prefix */
-		int ecx;
-		asm volatile("rep ; movsl"
-			     : "=&c" (ecx), "=&D" (edi), "=&S" (esi)
-			     : "0" (n / 4), "1" (edi), "2" (esi)
-			     : "memory"
-		);
-	} else {
-		/* small block: don't clobber ecx + smaller code */
-		if (n >= 4 * 4)
-			asm volatile("movsl"
-				     : "=&D"(edi), "=&S"(esi)
-				     : "0"(edi), "1"(esi)
-				     : "memory");
-		if (n >= 3 * 4)
-			asm volatile("movsl"
-				     : "=&D"(edi), "=&S"(esi)
-				     : "0"(edi), "1"(esi)
-				     : "memory");
-		if (n >= 2 * 4)
-			asm volatile("movsl"
-				     : "=&D"(edi), "=&S"(esi)
-				     : "0"(edi), "1"(esi)
-				     : "memory");
-		if (n >= 1 * 4)
-			asm volatile("movsl"
-				     : "=&D"(edi), "=&S"(esi)
-				     : "0"(edi), "1"(esi)
-				     : "memory");
-	}
-	switch (n % 4) {
-		/* tail */
-	case 0:
-		return to;
-	case 1:
-		asm volatile("movsb"
-			     : "=&D"(edi), "=&S"(esi)
-			     : "0"(edi), "1"(esi)
-			     : "memory");
-		return to;
-	case 2:
-		asm volatile("movsw"
-			     : "=&D"(edi), "=&S"(esi)
-			     : "0"(edi), "1"(esi)
-			     : "memory");
-		return to;
-	default:
-		asm volatile("movsw\n\tmovsb"
-			     : "=&D"(edi), "=&S"(esi)
-			     : "0"(edi), "1"(esi)
-			     : "memory");
-		return to;
-	}
-}
-
-#define __HAVE_ARCH_MEMCPY
-
-#ifdef CONFIG_X86_USE_3DNOW
-
-#include <asm/mmx.h>
-
-/*
- *	This CPU favours 3DNow strongly (eg AMD Athlon)
- */
-
-static inline void *__constant_memcpy3d(void *to, const void *from, size_t len)
-{
-	if (len < 512)
-		return __constant_memcpy(to, from, len);
-	return _mmx_memcpy(to, from, len);
-}
-
-static inline void *__memcpy3d(void *to, const void *from, size_t len)
-{
-	if (len < 512)
-		return __memcpy(to, from, len);
-	return _mmx_memcpy(to, from, len);
-}
-
-#define memcpy(t, f, n)				\
-	(__builtin_constant_p((n))		\
-	 ? __constant_memcpy3d((t), (f), (n))	\
-	 : __memcpy3d((t), (f), (n)))
-
-#else
-
-/*
- *	No 3D Now!
- */
-
-#define memcpy(t, f, n)				\
-	(__builtin_constant_p((n))		\
-	 ? __constant_memcpy((t), (f), (n))	\
-	 : __memcpy((t), (f), (n)))
-
-#endif
-
-#define __HAVE_ARCH_MEMMOVE
-void *memmove(void *dest, const void *src, size_t n);
-
-#define memcmp __builtin_memcmp
-
-#define __HAVE_ARCH_MEMCHR
-extern void *memchr(const void *cs, int c, size_t count);
-
-static inline void *__memset_generic(void *s, char c, size_t count)
-{
-	int d0, d1;
-	asm volatile("rep\n\t"
-		     "stosb"
-		     : "=&c" (d0), "=&D" (d1)
-		     : "a" (c), "1" (s), "0" (count)
-		     : "memory");
-	return s;
-}
-
-/* we might want to write optimized versions of these later */
-#define __constant_count_memset(s, c, count) __memset_generic((s), (c), (count))
-
-/*
- * memset(x, 0, y) is a reasonably common thing to do, so we want to fill
- * things 32 bits at a time even when we don't know the size of the
- * area at compile-time..
- */
-static __always_inline
-void *__constant_c_memset(void *s, unsigned long c, size_t count)
-{
-	int d0, d1;
-	asm volatile("rep ; stosl\n\t"
-		     "testb $2,%b3\n\t"
-		     "je 1f\n\t"
-		     "stosw\n"
-		     "1:\ttestb $1,%b3\n\t"
-		     "je 2f\n\t"
-		     "stosb\n"
-		     "2:"
-		     : "=&c" (d0), "=&D" (d1)
-		     : "a" (c), "q" (count), "0" (count/4), "1" ((long)s)
-		     : "memory");
-	return s;
-}
-
-/* Added by Gertjan van Wingerde to make minix and sysv module work */
-#define __HAVE_ARCH_STRNLEN
-extern size_t strnlen(const char *s, size_t count);
-/* end of additional stuff */
-
-#define __HAVE_ARCH_STRSTR
-extern char *strstr(const char *cs, const char *ct);
-
-/*
- * This looks horribly ugly, but the compiler can optimize it totally,
- * as we by now know that both pattern and count is constant..
- */
-static __always_inline
-void *__constant_c_and_count_memset(void *s, unsigned long pattern,
-				    size_t count)
-{
-	switch (count) {
-	case 0:
-		return s;
-	case 1:
-		*(unsigned char *)s = pattern & 0xff;
-		return s;
-	case 2:
-		*(unsigned short *)s = pattern & 0xffff;
-		return s;
-	case 3:
-		*(unsigned short *)s = pattern & 0xffff;
-		*((unsigned char *)s + 2) = pattern & 0xff;
-		return s;
-	case 4:
-		*(unsigned long *)s = pattern;
-		return s;
-	}
-
-#define COMMON(x)							\
-	asm volatile("rep ; stosl"					\
-		     x							\
-		     : "=&c" (d0), "=&D" (d1)				\
-		     : "a" (eax), "0" (count/4), "1" ((long)s)	\
-		     : "memory")
-
-	{
-		int d0, d1;
-#if __GNUC__ == 4 && __GNUC_MINOR__ == 0
-		/* Workaround for broken gcc 4.0 */
-		register unsigned long eax asm("%eax") = pattern;
-#else
-		unsigned long eax = pattern;
-#endif
-
-		switch (count % 4) {
-		case 0:
-			COMMON("");
-			return s;
-		case 1:
-			COMMON("\n\tstosb");
-			return s;
-		case 2:
-			COMMON("\n\tstosw");
-			return s;
-		default:
-			COMMON("\n\tstosw\n\tstosb");
-			return s;
-		}
-	}
-
-#undef COMMON
-}
-
-#define __constant_c_x_memset(s, c, count)			\
-	(__builtin_constant_p(count)				\
-	 ? __constant_c_and_count_memset((s), (c), (count))	\
-	 : __constant_c_memset((s), (c), (count)))
-
-#define __memset(s, c, count)				\
-	(__builtin_constant_p(count)			\
-	 ? __constant_count_memset((s), (c), (count))	\
-	 : __memset_generic((s), (c), (count)))
-
-#define __HAVE_ARCH_MEMSET
-#define memset(s, c, count)						\
-	(__builtin_constant_p(c)					\
-	 ? __constant_c_x_memset((s), (0x01010101UL * (unsigned char)(c)), \
-				 (count))				\
-	 : __memset((s), (c), (count)))
-
-/*
- * find the first occurrence of byte 'c', or 1 past the area if none
- */
-#define __HAVE_ARCH_MEMSCAN
-extern void *memscan(void *addr, int c, size_t size);
-
-#endif /* __KERNEL__ */
-
-#endif /* ASM_X86__STRING_32_H */
diff --git a/include/asm-x86/string_64.h b/include/asm-x86/string_64.h
deleted file mode 100644
index a2add11d3b66..000000000000
--- a/include/asm-x86/string_64.h
+++ /dev/null
@@ -1,60 +0,0 @@
-#ifndef ASM_X86__STRING_64_H
-#define ASM_X86__STRING_64_H
-
-#ifdef __KERNEL__
-
-/* Written 2002 by Andi Kleen */
-
-/* Only used for special circumstances. Stolen from i386/string.h */
-static __always_inline void *__inline_memcpy(void *to, const void *from, size_t n)
-{
-	unsigned long d0, d1, d2;
-	asm volatile("rep ; movsl\n\t"
-		     "testb $2,%b4\n\t"
-		     "je 1f\n\t"
-		     "movsw\n"
-		     "1:\ttestb $1,%b4\n\t"
-		     "je 2f\n\t"
-		     "movsb\n"
-		     "2:"
-		     : "=&c" (d0), "=&D" (d1), "=&S" (d2)
-		     : "0" (n / 4), "q" (n), "1" ((long)to), "2" ((long)from)
-		     : "memory");
-	return to;
-}
-
-/* Even with __builtin_ the compiler may decide to use the out of line
-   function. */
-
-#define __HAVE_ARCH_MEMCPY 1
-#if (__GNUC__ == 4 && __GNUC_MINOR__ >= 3) || __GNUC__ > 4
-extern void *memcpy(void *to, const void *from, size_t len);
-#else
-extern void *__memcpy(void *to, const void *from, size_t len);
-#define memcpy(dst, src, len)					\
-({								\
-	size_t __len = (len);					\
-	void *__ret;						\
-	if (__builtin_constant_p(len) && __len >= 64)		\
-		__ret = __memcpy((dst), (src), __len);		\
-	else							\
-		__ret = __builtin_memcpy((dst), (src), __len);	\
-	__ret;							\
-})
-#endif
-
-#define __HAVE_ARCH_MEMSET
-void *memset(void *s, int c, size_t n);
-
-#define __HAVE_ARCH_MEMMOVE
-void *memmove(void *dest, const void *src, size_t count);
-
-int memcmp(const void *cs, const void *ct, size_t count);
-size_t strlen(const char *s);
-char *strcpy(char *dest, const char *src);
-char *strcat(char *dest, const char *src);
-int strcmp(const char *cs, const char *ct);
-
-#endif /* __KERNEL__ */
-
-#endif /* ASM_X86__STRING_64_H */
diff --git a/include/asm-x86/summit/apic.h b/include/asm-x86/summit/apic.h
deleted file mode 100644
index c5b2e4b10358..000000000000
--- a/include/asm-x86/summit/apic.h
+++ /dev/null
@@ -1,185 +0,0 @@
-#ifndef __ASM_SUMMIT_APIC_H
-#define __ASM_SUMMIT_APIC_H
-
-#include <asm/smp.h>
-
-#define esr_disable (1)
-#define NO_BALANCE_IRQ (0)
-
-/* In clustered mode, the high nibble of APIC ID is a cluster number.
- * The low nibble is a 4-bit bitmap. */
-#define XAPIC_DEST_CPUS_SHIFT	4
-#define XAPIC_DEST_CPUS_MASK	((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
-#define XAPIC_DEST_CLUSTER_MASK	(XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
-
-#define APIC_DFR_VALUE	(APIC_DFR_CLUSTER)
-
-static inline cpumask_t target_cpus(void)
-{
-	/* CPU_MASK_ALL (0xff) has undefined behaviour with
-	 * dest_LowestPrio mode logical clustered apic interrupt routing
-	 * Just start on cpu 0.  IRQ balancing will spread load
-	 */
-	return cpumask_of_cpu(0);
-}
-#define TARGET_CPUS	(target_cpus())
-
-#define INT_DELIVERY_MODE (dest_LowestPrio)
-#define INT_DEST_MODE 1     /* logical delivery broadcast to all procs */
-
-static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
-{
-	return 0;
-}
-
-/* we don't use the phys_cpu_present_map to indicate apicid presence */
-static inline unsigned long check_apicid_present(int bit)
-{
-	return 1;
-}
-
-#define apicid_cluster(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
-
-extern u8 cpu_2_logical_apicid[];
-
-static inline void init_apic_ldr(void)
-{
-	unsigned long val, id;
-	int count = 0;
-	u8 my_id = (u8)hard_smp_processor_id();
-	u8 my_cluster = (u8)apicid_cluster(my_id);
-#ifdef CONFIG_SMP
-	u8 lid;
-	int i;
-
-	/* Create logical APIC IDs by counting CPUs already in cluster. */
-	for (count = 0, i = NR_CPUS; --i >= 0; ) {
-		lid = cpu_2_logical_apicid[i];
-		if (lid != BAD_APICID && apicid_cluster(lid) == my_cluster)
-			++count;
-	}
-#endif
-	/* We only have a 4 wide bitmap in cluster mode.  If a deranged
-	 * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */
-	BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT);
-	id = my_cluster | (1UL << count);
-	apic_write(APIC_DFR, APIC_DFR_VALUE);
-	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
-	val |= SET_APIC_LOGICAL_ID(id);
-	apic_write(APIC_LDR, val);
-}
-
-static inline int multi_timer_check(int apic, int irq)
-{
-	return 0;
-}
-
-static inline int apic_id_registered(void)
-{
-	return 1;
-}
-
-static inline void setup_apic_routing(void)
-{
-	printk("Enabling APIC mode:  Summit.  Using %d I/O APICs\n",
-						nr_ioapics);
-}
-
-static inline int apicid_to_node(int logical_apicid)
-{
-#ifdef CONFIG_SMP
-	return apicid_2_node[hard_smp_processor_id()];
-#else
-	return 0;
-#endif
-}
-
-/* Mapping from cpu number to logical apicid */
-static inline int cpu_to_logical_apicid(int cpu)
-{
-#ifdef CONFIG_SMP
-       if (cpu >= NR_CPUS)
-	       return BAD_APICID;
-	return (int)cpu_2_logical_apicid[cpu];
-#else
-	return logical_smp_processor_id();
-#endif
-}
-
-static inline int cpu_present_to_apicid(int mps_cpu)
-{
-	if (mps_cpu < NR_CPUS)
-		return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
-	else
-		return BAD_APICID;
-}
-
-static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_id_map)
-{
-	/* For clustered we don't have a good way to do this yet - hack */
-	return physids_promote(0x0F);
-}
-
-static inline physid_mask_t apicid_to_cpu_present(int apicid)
-{
-	return physid_mask_of_physid(0);
-}
-
-static inline void setup_portio_remap(void)
-{
-}
-
-static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
-{
-	return 1;
-}
-
-static inline void enable_apic_mode(void)
-{
-}
-
-static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
-{
-	int num_bits_set;
-	int cpus_found = 0;
-	int cpu;
-	int apicid;
-
-	num_bits_set = cpus_weight(cpumask);
-	/* Return id to all */
-	if (num_bits_set == NR_CPUS)
-		return (int) 0xFF;
-	/*
-	 * The cpus in the mask must all be on the apic cluster.  If are not
-	 * on the same apicid cluster return default value of TARGET_CPUS.
-	 */
-	cpu = first_cpu(cpumask);
-	apicid = cpu_to_logical_apicid(cpu);
-	while (cpus_found < num_bits_set) {
-		if (cpu_isset(cpu, cpumask)) {
-			int new_apicid = cpu_to_logical_apicid(cpu);
-			if (apicid_cluster(apicid) !=
-					apicid_cluster(new_apicid)){
-				printk ("%s: Not a valid mask!\n",__FUNCTION__);
-				return 0xFF;
-			}
-			apicid = apicid | new_apicid;
-			cpus_found++;
-		}
-		cpu++;
-	}
-	return apicid;
-}
-
-/* cpuid returns the value latched in the HW at reset, not the APIC ID
- * register's value.  For any box whose BIOS changes APIC IDs, like
- * clustered APIC systems, we must use hard_smp_processor_id.
- *
- * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
- */
-static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
-{
-	return hard_smp_processor_id() >> index_msb;
-}
-
-#endif /* __ASM_SUMMIT_APIC_H */
diff --git a/include/asm-x86/summit/apicdef.h b/include/asm-x86/summit/apicdef.h
deleted file mode 100644
index f3fbca1f61c1..000000000000
--- a/include/asm-x86/summit/apicdef.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ASM_SUMMIT_APICDEF_H
-#define __ASM_SUMMIT_APICDEF_H
-
-#define		APIC_ID_MASK		(0xFF<<24)
-
-static inline unsigned get_apic_id(unsigned long x)
-{
-	return (x>>24)&0xFF;
-}
-
-#define		GET_APIC_ID(x)	get_apic_id(x)
-
-#endif
diff --git a/include/asm-x86/summit/ipi.h b/include/asm-x86/summit/ipi.h
deleted file mode 100644
index 53bd1e7bd7b4..000000000000
--- a/include/asm-x86/summit/ipi.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef __ASM_SUMMIT_IPI_H
-#define __ASM_SUMMIT_IPI_H
-
-void send_IPI_mask_sequence(cpumask_t mask, int vector);
-
-static inline void send_IPI_mask(cpumask_t mask, int vector)
-{
-	send_IPI_mask_sequence(mask, vector);
-}
-
-static inline void send_IPI_allbutself(int vector)
-{
-	cpumask_t mask = cpu_online_map;
-	cpu_clear(smp_processor_id(), mask);
-
-	if (!cpus_empty(mask))
-		send_IPI_mask(mask, vector);
-}
-
-static inline void send_IPI_all(int vector)
-{
-	send_IPI_mask(cpu_online_map, vector);
-}
-
-#endif /* __ASM_SUMMIT_IPI_H */
diff --git a/include/asm-x86/summit/irq_vectors_limits.h b/include/asm-x86/summit/irq_vectors_limits.h
deleted file mode 100644
index 890ce3f5e09a..000000000000
--- a/include/asm-x86/summit/irq_vectors_limits.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef _ASM_IRQ_VECTORS_LIMITS_H
-#define _ASM_IRQ_VECTORS_LIMITS_H
-
-/*
- * For Summit or generic (i.e. installer) kernels, we have lots of I/O APICs,
- * even with uni-proc kernels, so use a big array.
- *
- * This value should be the same in both the generic and summit subarches.
- * Change one, change 'em both.
- */
-#define NR_IRQS	224
-#define NR_IRQ_VECTORS	1024
-
-#endif /* _ASM_IRQ_VECTORS_LIMITS_H */
diff --git a/include/asm-x86/summit/mpparse.h b/include/asm-x86/summit/mpparse.h
deleted file mode 100644
index 013ce6fab2d5..000000000000
--- a/include/asm-x86/summit/mpparse.h
+++ /dev/null
@@ -1,109 +0,0 @@
-#ifndef __ASM_SUMMIT_MPPARSE_H
-#define __ASM_SUMMIT_MPPARSE_H
-
-#include <asm/tsc.h>
-
-extern int use_cyclone;
-
-#ifdef CONFIG_X86_SUMMIT_NUMA
-extern void setup_summit(void);
-#else
-#define setup_summit()	{}
-#endif
-
-static inline int mps_oem_check(struct mp_config_table *mpc, char *oem,
-		char *productid)
-{
-	if (!strncmp(oem, "IBM ENSW", 8) &&
-			(!strncmp(productid, "VIGIL SMP", 9)
-			 || !strncmp(productid, "EXA", 3)
-			 || !strncmp(productid, "RUTHLESS SMP", 12))){
-		mark_tsc_unstable("Summit based system");
-		use_cyclone = 1; /*enable cyclone-timer*/
-		setup_summit();
-		return 1;
-	}
-	return 0;
-}
-
-/* Hook from generic ACPI tables.c */
-static inline int acpi_madt_oem_check(char *oem_id, char *oem_table_id)
-{
-	if (!strncmp(oem_id, "IBM", 3) &&
-	    (!strncmp(oem_table_id, "SERVIGIL", 8)
-	     || !strncmp(oem_table_id, "EXA", 3))){
-		mark_tsc_unstable("Summit based system");
-		use_cyclone = 1; /*enable cyclone-timer*/
-		setup_summit();
-		return 1;
-	}
-	return 0;
-}
-
-struct rio_table_hdr {
-	unsigned char version;      /* Version number of this data structure           */
-	                            /* Version 3 adds chassis_num & WP_index           */
-	unsigned char num_scal_dev; /* # of Scalability devices (Twisters for Vigil)   */
-	unsigned char num_rio_dev;  /* # of RIO I/O devices (Cyclones and Winnipegs)   */
-} __attribute__((packed));
-
-struct scal_detail {
-	unsigned char node_id;      /* Scalability Node ID                             */
-	unsigned long CBAR;         /* Address of 1MB register space                   */
-	unsigned char port0node;    /* Node ID port connected to: 0xFF=None            */
-	unsigned char port0port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
-	unsigned char port1node;    /* Node ID port connected to: 0xFF = None          */
-	unsigned char port1port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
-	unsigned char port2node;    /* Node ID port connected to: 0xFF = None          */
-	unsigned char port2port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
-	unsigned char chassis_num;  /* 1 based Chassis number (1 = boot node)          */
-} __attribute__((packed));
-
-struct rio_detail {
-	unsigned char node_id;      /* RIO Node ID                                     */
-	unsigned long BBAR;         /* Address of 1MB register space                   */
-	unsigned char type;         /* Type of device                                  */
-	unsigned char owner_id;     /* For WPEG: Node ID of Cyclone that owns this WPEG*/
-	                            /* For CYC:  Node ID of Twister that owns this CYC */
-	unsigned char port0node;    /* Node ID port connected to: 0xFF=None            */
-	unsigned char port0port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
-	unsigned char port1node;    /* Node ID port connected to: 0xFF=None            */
-	unsigned char port1port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
-	unsigned char first_slot;   /* For WPEG: Lowest slot number below this WPEG    */
-	                            /* For CYC:  0                                     */
-	unsigned char status;       /* For WPEG: Bit 0 = 1 : the XAPIC is used         */
-	                            /*                 = 0 : the XAPIC is not used, ie:*/
-	                            /*                     ints fwded to another XAPIC */
-	                            /*           Bits1:7 Reserved                      */
-	                            /* For CYC:  Bits0:7 Reserved                      */
-	unsigned char WP_index;     /* For WPEG: WPEG instance index - lower ones have */
-	                            /*           lower slot numbers/PCI bus numbers    */
-	                            /* For CYC:  No meaning                            */
-	unsigned char chassis_num;  /* 1 based Chassis number                          */
-	                            /* For LookOut WPEGs this field indicates the      */
-	                            /* Expansion Chassis #, enumerated from Boot       */
-	                            /* Node WPEG external port, then Boot Node CYC     */
-	                            /* external port, then Next Vigil chassis WPEG     */
-	                            /* external port, etc.                             */
-	                            /* Shared Lookouts have only 1 chassis number (the */
-	                            /* first one assigned)                             */
-} __attribute__((packed));
-
-
-typedef enum {
-	CompatTwister = 0,  /* Compatibility Twister               */
-	AltTwister    = 1,  /* Alternate Twister of internal 8-way */
-	CompatCyclone = 2,  /* Compatibility Cyclone               */
-	AltCyclone    = 3,  /* Alternate Cyclone of internal 8-way */
-	CompatWPEG    = 4,  /* Compatibility WPEG                  */
-	AltWPEG       = 5,  /* Second Planar WPEG                  */
-	LookOutAWPEG  = 6,  /* LookOut WPEG                        */
-	LookOutBWPEG  = 7,  /* LookOut WPEG                        */
-} node_type;
-
-static inline int is_WPEG(struct rio_detail *rio){
-	return (rio->type == CompatWPEG || rio->type == AltWPEG ||
-		rio->type == LookOutAWPEG || rio->type == LookOutBWPEG);
-}
-
-#endif /* __ASM_SUMMIT_MPPARSE_H */
diff --git a/include/asm-x86/suspend.h b/include/asm-x86/suspend.h
deleted file mode 100644
index 9bd521fe4570..000000000000
--- a/include/asm-x86/suspend.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifdef CONFIG_X86_32
-# include "suspend_32.h"
-#else
-# include "suspend_64.h"
-#endif
diff --git a/include/asm-x86/suspend_32.h b/include/asm-x86/suspend_32.h
deleted file mode 100644
index acb6d4d491f4..000000000000
--- a/include/asm-x86/suspend_32.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright 2001-2002 Pavel Machek <pavel@suse.cz>
- * Based on code
- * Copyright 2001 Patrick Mochel <mochel@osdl.org>
- */
-#ifndef ASM_X86__SUSPEND_32_H
-#define ASM_X86__SUSPEND_32_H
-
-#include <asm/desc.h>
-#include <asm/i387.h>
-
-static inline int arch_prepare_suspend(void) { return 0; }
-
-/* image of the saved processor state */
-struct saved_context {
-	u16 es, fs, gs, ss;
-	unsigned long cr0, cr2, cr3, cr4;
-	struct desc_ptr gdt;
-	struct desc_ptr idt;
-	u16 ldt;
-	u16 tss;
-	unsigned long tr;
-	unsigned long safety;
-	unsigned long return_address;
-} __attribute__((packed));
-
-#ifdef CONFIG_ACPI
-extern unsigned long saved_eip;
-extern unsigned long saved_esp;
-extern unsigned long saved_ebp;
-extern unsigned long saved_ebx;
-extern unsigned long saved_esi;
-extern unsigned long saved_edi;
-
-static inline void acpi_save_register_state(unsigned long return_point)
-{
-	saved_eip = return_point;
-	asm volatile("movl %%esp,%0" : "=m" (saved_esp));
-	asm volatile("movl %%ebp,%0" : "=m" (saved_ebp));
-	asm volatile("movl %%ebx,%0" : "=m" (saved_ebx));
-	asm volatile("movl %%edi,%0" : "=m" (saved_edi));
-	asm volatile("movl %%esi,%0" : "=m" (saved_esi));
-}
-
-#define acpi_restore_register_state()  do {} while (0)
-
-/* routines for saving/restoring kernel state */
-extern int acpi_save_state_mem(void);
-#endif
-
-#endif /* ASM_X86__SUSPEND_32_H */
diff --git a/include/asm-x86/suspend_64.h b/include/asm-x86/suspend_64.h
deleted file mode 100644
index cf821dd310e8..000000000000
--- a/include/asm-x86/suspend_64.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2001-2003 Pavel Machek <pavel@suse.cz>
- * Based on code
- * Copyright 2001 Patrick Mochel <mochel@osdl.org>
- */
-#ifndef ASM_X86__SUSPEND_64_H
-#define ASM_X86__SUSPEND_64_H
-
-#include <asm/desc.h>
-#include <asm/i387.h>
-
-static inline int arch_prepare_suspend(void)
-{
-	return 0;
-}
-
-/*
- * Image of the saved processor state, used by the low level ACPI suspend to
- * RAM code and by the low level hibernation code.
- *
- * If you modify it, fix arch/x86/kernel/acpi/wakeup_64.S and make sure that
- * __save/__restore_processor_state(), defined in arch/x86/kernel/suspend_64.c,
- * still work as required.
- */
-struct saved_context {
-	struct pt_regs regs;
-	u16 ds, es, fs, gs, ss;
-	unsigned long gs_base, gs_kernel_base, fs_base;
-	unsigned long cr0, cr2, cr3, cr4, cr8;
-	unsigned long efer;
-	u16 gdt_pad;
-	u16 gdt_limit;
-	unsigned long gdt_base;
-	u16 idt_pad;
-	u16 idt_limit;
-	unsigned long idt_base;
-	u16 ldt;
-	u16 tss;
-	unsigned long tr;
-	unsigned long safety;
-	unsigned long return_address;
-} __attribute__((packed));
-
-#define loaddebug(thread,register) \
-	set_debugreg((thread)->debugreg##register, register)
-
-/* routines for saving/restoring kernel state */
-extern int acpi_save_state_mem(void);
-extern char core_restore_code;
-extern char restore_registers;
-
-#endif /* ASM_X86__SUSPEND_64_H */
diff --git a/include/asm-x86/swiotlb.h b/include/asm-x86/swiotlb.h
deleted file mode 100644
index 1e20adbcad4b..000000000000
--- a/include/asm-x86/swiotlb.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef ASM_X86__SWIOTLB_H
-#define ASM_X86__SWIOTLB_H
-
-#include <asm/dma-mapping.h>
-
-/* SWIOTLB interface */
-
-extern dma_addr_t swiotlb_map_single(struct device *hwdev, void *ptr,
-				     size_t size, int dir);
-extern void *swiotlb_alloc_coherent(struct device *hwdev, size_t size,
-				    dma_addr_t *dma_handle, gfp_t flags);
-extern void swiotlb_unmap_single(struct device *hwdev, dma_addr_t dev_addr,
-				 size_t size, int dir);
-extern void swiotlb_sync_single_for_cpu(struct device *hwdev,
-					dma_addr_t dev_addr,
-					size_t size, int dir);
-extern void swiotlb_sync_single_for_device(struct device *hwdev,
-					   dma_addr_t dev_addr,
-					   size_t size, int dir);
-extern void swiotlb_sync_single_range_for_cpu(struct device *hwdev,
-					      dma_addr_t dev_addr,
-					      unsigned long offset,
-					      size_t size, int dir);
-extern void swiotlb_sync_single_range_for_device(struct device *hwdev,
-						 dma_addr_t dev_addr,
-						 unsigned long offset,
-						 size_t size, int dir);
-extern void swiotlb_sync_sg_for_cpu(struct device *hwdev,
-				    struct scatterlist *sg, int nelems,
-				    int dir);
-extern void swiotlb_sync_sg_for_device(struct device *hwdev,
-				       struct scatterlist *sg, int nelems,
-				       int dir);
-extern int swiotlb_map_sg(struct device *hwdev, struct scatterlist *sg,
-			  int nents, int direction);
-extern void swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sg,
-			     int nents, int direction);
-extern int swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t dma_addr);
-extern void swiotlb_free_coherent(struct device *hwdev, size_t size,
-				  void *vaddr, dma_addr_t dma_handle);
-extern int swiotlb_dma_supported(struct device *hwdev, u64 mask);
-extern void swiotlb_init(void);
-
-extern int swiotlb_force;
-
-#ifdef CONFIG_SWIOTLB
-extern int swiotlb;
-extern void pci_swiotlb_init(void);
-#else
-#define swiotlb 0
-static inline void pci_swiotlb_init(void)
-{
-}
-#endif
-
-static inline void dma_mark_clean(void *addr, size_t size) {}
-
-#endif /* ASM_X86__SWIOTLB_H */
diff --git a/include/asm-x86/sync_bitops.h b/include/asm-x86/sync_bitops.h
deleted file mode 100644
index b689bee71104..000000000000
--- a/include/asm-x86/sync_bitops.h
+++ /dev/null
@@ -1,130 +0,0 @@
-#ifndef ASM_X86__SYNC_BITOPS_H
-#define ASM_X86__SYNC_BITOPS_H
-
-/*
- * Copyright 1992, Linus Torvalds.
- */
-
-/*
- * These have to be done with inline assembly: that way the bit-setting
- * is guaranteed to be atomic. All bit operations return 0 if the bit
- * was cleared before the operation and != 0 if it was not.
- *
- * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
- */
-
-#define ADDR (*(volatile long *)addr)
-
-/**
- * sync_set_bit - Atomically set a bit in memory
- * @nr: the bit to set
- * @addr: the address to start counting from
- *
- * This function is atomic and may not be reordered.  See __set_bit()
- * if you do not require the atomic guarantees.
- *
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static inline void sync_set_bit(int nr, volatile unsigned long *addr)
-{
-	asm volatile("lock; btsl %1,%0"
-		     : "+m" (ADDR)
-		     : "Ir" (nr)
-		     : "memory");
-}
-
-/**
- * sync_clear_bit - Clears a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * sync_clear_bit() is atomic and may not be reordered.  However, it does
- * not contain a memory barrier, so if it is used for locking purposes,
- * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
- * in order to ensure changes are visible on other processors.
- */
-static inline void sync_clear_bit(int nr, volatile unsigned long *addr)
-{
-	asm volatile("lock; btrl %1,%0"
-		     : "+m" (ADDR)
-		     : "Ir" (nr)
-		     : "memory");
-}
-
-/**
- * sync_change_bit - Toggle a bit in memory
- * @nr: Bit to change
- * @addr: Address to start counting from
- *
- * sync_change_bit() is atomic and may not be reordered.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static inline void sync_change_bit(int nr, volatile unsigned long *addr)
-{
-	asm volatile("lock; btcl %1,%0"
-		     : "+m" (ADDR)
-		     : "Ir" (nr)
-		     : "memory");
-}
-
-/**
- * sync_test_and_set_bit - Set a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int sync_test_and_set_bit(int nr, volatile unsigned long *addr)
-{
-	int oldbit;
-
-	asm volatile("lock; btsl %2,%1\n\tsbbl %0,%0"
-		     : "=r" (oldbit), "+m" (ADDR)
-		     : "Ir" (nr) : "memory");
-	return oldbit;
-}
-
-/**
- * sync_test_and_clear_bit - Clear a bit and return its old value
- * @nr: Bit to clear
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int sync_test_and_clear_bit(int nr, volatile unsigned long *addr)
-{
-	int oldbit;
-
-	asm volatile("lock; btrl %2,%1\n\tsbbl %0,%0"
-		     : "=r" (oldbit), "+m" (ADDR)
-		     : "Ir" (nr) : "memory");
-	return oldbit;
-}
-
-/**
- * sync_test_and_change_bit - Change a bit and return its old value
- * @nr: Bit to change
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int sync_test_and_change_bit(int nr, volatile unsigned long *addr)
-{
-	int oldbit;
-
-	asm volatile("lock; btcl %2,%1\n\tsbbl %0,%0"
-		     : "=r" (oldbit), "+m" (ADDR)
-		     : "Ir" (nr) : "memory");
-	return oldbit;
-}
-
-#define sync_test_bit(nr, addr) test_bit(nr, addr)
-
-#undef ADDR
-
-#endif /* ASM_X86__SYNC_BITOPS_H */
diff --git a/include/asm-x86/syscall.h b/include/asm-x86/syscall.h
deleted file mode 100644
index 04c47dc5597c..000000000000
--- a/include/asm-x86/syscall.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * Access to user system call parameters and results
- *
- * Copyright (C) 2008 Red Hat, Inc.  All rights reserved.
- *
- * This copyrighted material is made available to anyone wishing to use,
- * modify, copy, or redistribute it subject to the terms and conditions
- * of the GNU General Public License v.2.
- *
- * See asm-generic/syscall.h for descriptions of what we must do here.
- */
-
-#ifndef _ASM_SYSCALL_H
-#define _ASM_SYSCALL_H	1
-
-#include <linux/sched.h>
-#include <linux/err.h>
-
-static inline long syscall_get_nr(struct task_struct *task,
-				  struct pt_regs *regs)
-{
-	/*
-	 * We always sign-extend a -1 value being set here,
-	 * so this is always either -1L or a syscall number.
-	 */
-	return regs->orig_ax;
-}
-
-static inline void syscall_rollback(struct task_struct *task,
-				    struct pt_regs *regs)
-{
-	regs->ax = regs->orig_ax;
-}
-
-static inline long syscall_get_error(struct task_struct *task,
-				     struct pt_regs *regs)
-{
-	unsigned long error = regs->ax;
-#ifdef CONFIG_IA32_EMULATION
-	/*
-	 * TS_COMPAT is set for 32-bit syscall entries and then
-	 * remains set until we return to user mode.
-	 */
-	if (task_thread_info(task)->status & TS_COMPAT)
-		/*
-		 * Sign-extend the value so (int)-EFOO becomes (long)-EFOO
-		 * and will match correctly in comparisons.
-		 */
-		error = (long) (int) error;
-#endif
-	return IS_ERR_VALUE(error) ? error : 0;
-}
-
-static inline long syscall_get_return_value(struct task_struct *task,
-					    struct pt_regs *regs)
-{
-	return regs->ax;
-}
-
-static inline void syscall_set_return_value(struct task_struct *task,
-					    struct pt_regs *regs,
-					    int error, long val)
-{
-	regs->ax = (long) error ?: val;
-}
-
-#ifdef CONFIG_X86_32
-
-static inline void syscall_get_arguments(struct task_struct *task,
-					 struct pt_regs *regs,
-					 unsigned int i, unsigned int n,
-					 unsigned long *args)
-{
-	BUG_ON(i + n > 6);
-	memcpy(args, &regs->bx + i, n * sizeof(args[0]));
-}
-
-static inline void syscall_set_arguments(struct task_struct *task,
-					 struct pt_regs *regs,
-					 unsigned int i, unsigned int n,
-					 const unsigned long *args)
-{
-	BUG_ON(i + n > 6);
-	memcpy(&regs->bx + i, args, n * sizeof(args[0]));
-}
-
-#else	 /* CONFIG_X86_64 */
-
-static inline void syscall_get_arguments(struct task_struct *task,
-					 struct pt_regs *regs,
-					 unsigned int i, unsigned int n,
-					 unsigned long *args)
-{
-# ifdef CONFIG_IA32_EMULATION
-	if (task_thread_info(task)->status & TS_COMPAT)
-		switch (i + n) {
-		case 6:
-			if (!n--) break;
-			*args++ = regs->bp;
-		case 5:
-			if (!n--) break;
-			*args++ = regs->di;
-		case 4:
-			if (!n--) break;
-			*args++ = regs->si;
-		case 3:
-			if (!n--) break;
-			*args++ = regs->dx;
-		case 2:
-			if (!n--) break;
-			*args++ = regs->cx;
-		case 1:
-			if (!n--) break;
-			*args++ = regs->bx;
-		case 0:
-			if (!n--) break;
-		default:
-			BUG();
-			break;
-		}
-	else
-# endif
-		switch (i + n) {
-		case 6:
-			if (!n--) break;
-			*args++ = regs->r9;
-		case 5:
-			if (!n--) break;
-			*args++ = regs->r8;
-		case 4:
-			if (!n--) break;
-			*args++ = regs->r10;
-		case 3:
-			if (!n--) break;
-			*args++ = regs->dx;
-		case 2:
-			if (!n--) break;
-			*args++ = regs->si;
-		case 1:
-			if (!n--) break;
-			*args++ = regs->di;
-		case 0:
-			if (!n--) break;
-		default:
-			BUG();
-			break;
-		}
-}
-
-static inline void syscall_set_arguments(struct task_struct *task,
-					 struct pt_regs *regs,
-					 unsigned int i, unsigned int n,
-					 const unsigned long *args)
-{
-# ifdef CONFIG_IA32_EMULATION
-	if (task_thread_info(task)->status & TS_COMPAT)
-		switch (i + n) {
-		case 6:
-			if (!n--) break;
-			regs->bp = *args++;
-		case 5:
-			if (!n--) break;
-			regs->di = *args++;
-		case 4:
-			if (!n--) break;
-			regs->si = *args++;
-		case 3:
-			if (!n--) break;
-			regs->dx = *args++;
-		case 2:
-			if (!n--) break;
-			regs->cx = *args++;
-		case 1:
-			if (!n--) break;
-			regs->bx = *args++;
-		case 0:
-			if (!n--) break;
-		default:
-			BUG();
-		}
-	else
-# endif
-		switch (i + n) {
-		case 6:
-			if (!n--) break;
-			regs->r9 = *args++;
-		case 5:
-			if (!n--) break;
-			regs->r8 = *args++;
-		case 4:
-			if (!n--) break;
-			regs->r10 = *args++;
-		case 3:
-			if (!n--) break;
-			regs->dx = *args++;
-		case 2:
-			if (!n--) break;
-			regs->si = *args++;
-		case 1:
-			if (!n--) break;
-			regs->di = *args++;
-		case 0:
-			if (!n--) break;
-		default:
-			BUG();
-		}
-}
-
-#endif	/* CONFIG_X86_32 */
-
-#endif	/* _ASM_SYSCALL_H */
diff --git a/include/asm-x86/syscalls.h b/include/asm-x86/syscalls.h
deleted file mode 100644
index 87803da44010..000000000000
--- a/include/asm-x86/syscalls.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * syscalls.h - Linux syscall interfaces (arch-specific)
- *
- * Copyright (c) 2008 Jaswinder Singh
- *
- * This file is released under the GPLv2.
- * See the file COPYING for more details.
- */
-
-#ifndef _ASM_X86_SYSCALLS_H
-#define _ASM_X86_SYSCALLS_H
-
-#include <linux/compiler.h>
-#include <linux/linkage.h>
-#include <linux/types.h>
-#include <linux/signal.h>
-
-/* Common in X86_32 and X86_64 */
-/* kernel/ioport.c */
-asmlinkage long sys_ioperm(unsigned long, unsigned long, int);
-
-/* X86_32 only */
-#ifdef CONFIG_X86_32
-/* kernel/process_32.c */
-asmlinkage int sys_fork(struct pt_regs);
-asmlinkage int sys_clone(struct pt_regs);
-asmlinkage int sys_vfork(struct pt_regs);
-asmlinkage int sys_execve(struct pt_regs);
-
-/* kernel/signal_32.c */
-asmlinkage int sys_sigsuspend(int, int, old_sigset_t);
-asmlinkage int sys_sigaction(int, const struct old_sigaction __user *,
-			     struct old_sigaction __user *);
-asmlinkage int sys_sigaltstack(unsigned long);
-asmlinkage unsigned long sys_sigreturn(unsigned long);
-asmlinkage int sys_rt_sigreturn(unsigned long);
-
-/* kernel/ioport.c */
-asmlinkage long sys_iopl(unsigned long);
-
-/* kernel/ldt.c */
-asmlinkage int sys_modify_ldt(int, void __user *, unsigned long);
-
-/* kernel/sys_i386_32.c */
-asmlinkage long sys_mmap2(unsigned long, unsigned long, unsigned long,
-			  unsigned long, unsigned long, unsigned long);
-struct mmap_arg_struct;
-asmlinkage int old_mmap(struct mmap_arg_struct __user *);
-struct sel_arg_struct;
-asmlinkage int old_select(struct sel_arg_struct __user *);
-asmlinkage int sys_ipc(uint, int, int, int, void __user *, long);
-struct old_utsname;
-asmlinkage int sys_uname(struct old_utsname __user *);
-struct oldold_utsname;
-asmlinkage int sys_olduname(struct oldold_utsname __user *);
-
-/* kernel/tls.c */
-asmlinkage int sys_set_thread_area(struct user_desc __user *);
-asmlinkage int sys_get_thread_area(struct user_desc __user *);
-
-/* kernel/vm86_32.c */
-asmlinkage int sys_vm86old(struct pt_regs);
-asmlinkage int sys_vm86(struct pt_regs);
-
-#else /* CONFIG_X86_32 */
-
-/* X86_64 only */
-/* kernel/process_64.c */
-asmlinkage long sys_fork(struct pt_regs *);
-asmlinkage long sys_clone(unsigned long, unsigned long,
-			  void __user *, void __user *,
-			  struct pt_regs *);
-asmlinkage long sys_vfork(struct pt_regs *);
-asmlinkage long sys_execve(char __user *, char __user * __user *,
-			   char __user * __user *,
-			   struct pt_regs *);
-
-/* kernel/ioport.c */
-asmlinkage long sys_iopl(unsigned int, struct pt_regs *);
-
-/* kernel/signal_64.c */
-asmlinkage long sys_sigaltstack(const stack_t __user *, stack_t __user *,
-				struct pt_regs *);
-asmlinkage long sys_rt_sigreturn(struct pt_regs *);
-
-/* kernel/sys_x86_64.c */
-asmlinkage long sys_mmap(unsigned long, unsigned long, unsigned long,
-			 unsigned long, unsigned long, unsigned long);
-struct new_utsname;
-asmlinkage long sys_uname(struct new_utsname __user *);
-
-#endif /* CONFIG_X86_32 */
-#endif /* _ASM_X86_SYSCALLS_H */
diff --git a/include/asm-x86/system.h b/include/asm-x86/system.h
deleted file mode 100644
index d79fa4a9ee64..000000000000
--- a/include/asm-x86/system.h
+++ /dev/null
@@ -1,429 +0,0 @@
-#ifndef ASM_X86__SYSTEM_H
-#define ASM_X86__SYSTEM_H
-
-#include <asm/asm.h>
-#include <asm/segment.h>
-#include <asm/cpufeature.h>
-#include <asm/cmpxchg.h>
-#include <asm/nops.h>
-
-#include <linux/kernel.h>
-#include <linux/irqflags.h>
-
-/* entries in ARCH_DLINFO: */
-#ifdef CONFIG_IA32_EMULATION
-# define AT_VECTOR_SIZE_ARCH 2
-#else
-# define AT_VECTOR_SIZE_ARCH 1
-#endif
-
-#ifdef CONFIG_X86_32
-
-struct task_struct; /* one of the stranger aspects of C forward declarations */
-struct task_struct *__switch_to(struct task_struct *prev,
-				struct task_struct *next);
-
-/*
- * Saving eflags is important. It switches not only IOPL between tasks,
- * it also protects other tasks from NT leaking through sysenter etc.
- */
-#define switch_to(prev, next, last)					\
-do {									\
-	/*								\
-	 * Context-switching clobbers all registers, so we clobber	\
-	 * them explicitly, via unused output variables.		\
-	 * (EAX and EBP is not listed because EBP is saved/restored	\
-	 * explicitly for wchan access and EAX is the return value of	\
-	 * __switch_to())						\
-	 */								\
-	unsigned long ebx, ecx, edx, esi, edi;				\
-									\
-	asm volatile("pushfl\n\t"		/* save    flags */	\
-		     "pushl %%ebp\n\t"		/* save    EBP   */	\
-		     "movl %%esp,%[prev_sp]\n\t"	/* save    ESP   */ \
-		     "movl %[next_sp],%%esp\n\t"	/* restore ESP   */ \
-		     "movl $1f,%[prev_ip]\n\t"	/* save    EIP   */	\
-		     "pushl %[next_ip]\n\t"	/* restore EIP   */	\
-		     "jmp __switch_to\n"	/* regparm call  */	\
-		     "1:\t"						\
-		     "popl %%ebp\n\t"		/* restore EBP   */	\
-		     "popfl\n"			/* restore flags */	\
-									\
-		     /* output parameters */				\
-		     : [prev_sp] "=m" (prev->thread.sp),		\
-		       [prev_ip] "=m" (prev->thread.ip),		\
-		       "=a" (last),					\
-									\
-		       /* clobbered output registers: */		\
-		       "=b" (ebx), "=c" (ecx), "=d" (edx),		\
-		       "=S" (esi), "=D" (edi)				\
-		       							\
-		       /* input parameters: */				\
-		     : [next_sp]  "m" (next->thread.sp),		\
-		       [next_ip]  "m" (next->thread.ip),		\
-		       							\
-		       /* regparm parameters for __switch_to(): */	\
-		       [prev]     "a" (prev),				\
-		       [next]     "d" (next)				\
-									\
-		     : /* reloaded segment registers */			\
-			"memory");					\
-} while (0)
-
-/*
- * disable hlt during certain critical i/o operations
- */
-#define HAVE_DISABLE_HLT
-#else
-#define __SAVE(reg, offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
-#define __RESTORE(reg, offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
-
-/* frame pointer must be last for get_wchan */
-#define SAVE_CONTEXT    "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
-#define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
-
-#define __EXTRA_CLOBBER  \
-	, "rcx", "rbx", "rdx", "r8", "r9", "r10", "r11", \
-	  "r12", "r13", "r14", "r15"
-
-/* Save restore flags to clear handle leaking NT */
-#define switch_to(prev, next, last) \
-	asm volatile(SAVE_CONTEXT						    \
-	     "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */	  \
-	     "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */	  \
-	     "call __switch_to\n\t"					  \
-	     ".globl thread_return\n"					  \
-	     "thread_return:\n\t"					  \
-	     "movq %%gs:%P[pda_pcurrent],%%rsi\n\t"			  \
-	     "movq %P[task_canary](%%rsi),%%r8\n\t"			  \
-	     "movq %%r8,%%gs:%P[pda_canary]\n\t"			  \
-	     "movq %P[thread_info](%%rsi),%%r8\n\t"			  \
-	     LOCK_PREFIX "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"	  \
-	     "movq %%rax,%%rdi\n\t" 					  \
-	     "jc   ret_from_fork\n\t"					  \
-	     RESTORE_CONTEXT						  \
-	     : "=a" (last)					  	  \
-	     : [next] "S" (next), [prev] "D" (prev),			  \
-	       [threadrsp] "i" (offsetof(struct task_struct, thread.sp)), \
-	       [ti_flags] "i" (offsetof(struct thread_info, flags)),	  \
-	       [tif_fork] "i" (TIF_FORK),			  	  \
-	       [thread_info] "i" (offsetof(struct task_struct, stack)),   \
-	       [task_canary] "i" (offsetof(struct task_struct, stack_canary)),\
-	       [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)), \
-	       [pda_canary] "i" (offsetof(struct x8664_pda, stack_canary))\
-	     : "memory", "cc" __EXTRA_CLOBBER)
-#endif
-
-#ifdef __KERNEL__
-#define _set_base(addr, base) do { unsigned long __pr; \
-__asm__ __volatile__ ("movw %%dx,%1\n\t" \
-	"rorl $16,%%edx\n\t" \
-	"movb %%dl,%2\n\t" \
-	"movb %%dh,%3" \
-	:"=&d" (__pr) \
-	:"m" (*((addr)+2)), \
-	 "m" (*((addr)+4)), \
-	 "m" (*((addr)+7)), \
-	 "0" (base) \
-	); } while (0)
-
-#define _set_limit(addr, limit) do { unsigned long __lr; \
-__asm__ __volatile__ ("movw %%dx,%1\n\t" \
-	"rorl $16,%%edx\n\t" \
-	"movb %2,%%dh\n\t" \
-	"andb $0xf0,%%dh\n\t" \
-	"orb %%dh,%%dl\n\t" \
-	"movb %%dl,%2" \
-	:"=&d" (__lr) \
-	:"m" (*(addr)), \
-	 "m" (*((addr)+6)), \
-	 "0" (limit) \
-	); } while (0)
-
-#define set_base(ldt, base) _set_base(((char *)&(ldt)) , (base))
-#define set_limit(ldt, limit) _set_limit(((char *)&(ldt)) , ((limit)-1))
-
-extern void native_load_gs_index(unsigned);
-
-/*
- * Load a segment. Fall back on loading the zero
- * segment if something goes wrong..
- */
-#define loadsegment(seg, value)			\
-	asm volatile("\n"			\
-		     "1:\t"			\
-		     "movl %k0,%%" #seg "\n"	\
-		     "2:\n"			\
-		     ".section .fixup,\"ax\"\n"	\
-		     "3:\t"			\
-		     "movl %k1, %%" #seg "\n\t"	\
-		     "jmp 2b\n"			\
-		     ".previous\n"		\
-		     _ASM_EXTABLE(1b,3b)	\
-		     : :"r" (value), "r" (0) : "memory")
-
-
-/*
- * Save a segment register away
- */
-#define savesegment(seg, value)				\
-	asm("mov %%" #seg ",%0":"=r" (value) : : "memory")
-
-static inline unsigned long get_limit(unsigned long segment)
-{
-	unsigned long __limit;
-	asm("lsll %1,%0" : "=r" (__limit) : "r" (segment));
-	return __limit + 1;
-}
-
-static inline void native_clts(void)
-{
-	asm volatile("clts");
-}
-
-/*
- * Volatile isn't enough to prevent the compiler from reordering the
- * read/write functions for the control registers and messing everything up.
- * A memory clobber would solve the problem, but would prevent reordering of
- * all loads stores around it, which can hurt performance. Solution is to
- * use a variable and mimic reads and writes to it to enforce serialization
- */
-static unsigned long __force_order;
-
-static inline unsigned long native_read_cr0(void)
-{
-	unsigned long val;
-	asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
-	return val;
-}
-
-static inline void native_write_cr0(unsigned long val)
-{
-	asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order));
-}
-
-static inline unsigned long native_read_cr2(void)
-{
-	unsigned long val;
-	asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
-	return val;
-}
-
-static inline void native_write_cr2(unsigned long val)
-{
-	asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order));
-}
-
-static inline unsigned long native_read_cr3(void)
-{
-	unsigned long val;
-	asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
-	return val;
-}
-
-static inline void native_write_cr3(unsigned long val)
-{
-	asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order));
-}
-
-static inline unsigned long native_read_cr4(void)
-{
-	unsigned long val;
-	asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
-	return val;
-}
-
-static inline unsigned long native_read_cr4_safe(void)
-{
-	unsigned long val;
-	/* This could fault if %cr4 does not exist. In x86_64, a cr4 always
-	 * exists, so it will never fail. */
-#ifdef CONFIG_X86_32
-	asm volatile("1: mov %%cr4, %0\n"
-		     "2:\n"
-		     _ASM_EXTABLE(1b, 2b)
-		     : "=r" (val), "=m" (__force_order) : "0" (0));
-#else
-	val = native_read_cr4();
-#endif
-	return val;
-}
-
-static inline void native_write_cr4(unsigned long val)
-{
-	asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order));
-}
-
-#ifdef CONFIG_X86_64
-static inline unsigned long native_read_cr8(void)
-{
-	unsigned long cr8;
-	asm volatile("movq %%cr8,%0" : "=r" (cr8));
-	return cr8;
-}
-
-static inline void native_write_cr8(unsigned long val)
-{
-	asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
-}
-#endif
-
-static inline void native_wbinvd(void)
-{
-	asm volatile("wbinvd": : :"memory");
-}
-
-#ifdef CONFIG_PARAVIRT
-#include <asm/paravirt.h>
-#else
-#define read_cr0()	(native_read_cr0())
-#define write_cr0(x)	(native_write_cr0(x))
-#define read_cr2()	(native_read_cr2())
-#define write_cr2(x)	(native_write_cr2(x))
-#define read_cr3()	(native_read_cr3())
-#define write_cr3(x)	(native_write_cr3(x))
-#define read_cr4()	(native_read_cr4())
-#define read_cr4_safe()	(native_read_cr4_safe())
-#define write_cr4(x)	(native_write_cr4(x))
-#define wbinvd()	(native_wbinvd())
-#ifdef CONFIG_X86_64
-#define read_cr8()	(native_read_cr8())
-#define write_cr8(x)	(native_write_cr8(x))
-#define load_gs_index   native_load_gs_index
-#endif
-
-/* Clear the 'TS' bit */
-#define clts()		(native_clts())
-
-#endif/* CONFIG_PARAVIRT */
-
-#define stts() write_cr0(read_cr0() | X86_CR0_TS)
-
-#endif /* __KERNEL__ */
-
-static inline void clflush(volatile void *__p)
-{
-	asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
-}
-
-#define nop() asm volatile ("nop")
-
-void disable_hlt(void);
-void enable_hlt(void);
-
-void cpu_idle_wait(void);
-
-extern unsigned long arch_align_stack(unsigned long sp);
-extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
-
-void default_idle(void);
-
-/*
- * Force strict CPU ordering.
- * And yes, this is required on UP too when we're talking
- * to devices.
- */
-#ifdef CONFIG_X86_32
-/*
- * Some non-Intel clones support out of order store. wmb() ceases to be a
- * nop for these.
- */
-#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
-#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
-#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
-#else
-#define mb() 	asm volatile("mfence":::"memory")
-#define rmb()	asm volatile("lfence":::"memory")
-#define wmb()	asm volatile("sfence" ::: "memory")
-#endif
-
-/**
- * read_barrier_depends - Flush all pending reads that subsequents reads
- * depend on.
- *
- * No data-dependent reads from memory-like regions are ever reordered
- * over this barrier.  All reads preceding this primitive are guaranteed
- * to access memory (but not necessarily other CPUs' caches) before any
- * reads following this primitive that depend on the data return by
- * any of the preceding reads.  This primitive is much lighter weight than
- * rmb() on most CPUs, and is never heavier weight than is
- * rmb().
- *
- * These ordering constraints are respected by both the local CPU
- * and the compiler.
- *
- * Ordering is not guaranteed by anything other than these primitives,
- * not even by data dependencies.  See the documentation for
- * memory_barrier() for examples and URLs to more information.
- *
- * For example, the following code would force ordering (the initial
- * value of "a" is zero, "b" is one, and "p" is "&a"):
- *
- * <programlisting>
- *	CPU 0				CPU 1
- *
- *	b = 2;
- *	memory_barrier();
- *	p = &b;				q = p;
- *					read_barrier_depends();
- *					d = *q;
- * </programlisting>
- *
- * because the read of "*q" depends on the read of "p" and these
- * two reads are separated by a read_barrier_depends().  However,
- * the following code, with the same initial values for "a" and "b":
- *
- * <programlisting>
- *	CPU 0				CPU 1
- *
- *	a = 2;
- *	memory_barrier();
- *	b = 3;				y = b;
- *					read_barrier_depends();
- *					x = a;
- * </programlisting>
- *
- * does not enforce ordering, since there is no data dependency between
- * the read of "a" and the read of "b".  Therefore, on some CPUs, such
- * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
- * in cases like this where there are no data dependencies.
- **/
-
-#define read_barrier_depends()	do { } while (0)
-
-#ifdef CONFIG_SMP
-#define smp_mb()	mb()
-#ifdef CONFIG_X86_PPRO_FENCE
-# define smp_rmb()	rmb()
-#else
-# define smp_rmb()	barrier()
-#endif
-#ifdef CONFIG_X86_OOSTORE
-# define smp_wmb() 	wmb()
-#else
-# define smp_wmb()	barrier()
-#endif
-#define smp_read_barrier_depends()	read_barrier_depends()
-#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
-#else
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#define smp_read_barrier_depends()	do { } while (0)
-#define set_mb(var, value) do { var = value; barrier(); } while (0)
-#endif
-
-/*
- * Stop RDTSC speculation. This is needed when you need to use RDTSC
- * (or get_cycles or vread that possibly accesses the TSC) in a defined
- * code region.
- *
- * (Could use an alternative three way for this if there was one.)
- */
-static inline void rdtsc_barrier(void)
-{
-	alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
-	alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
-}
-
-#endif /* ASM_X86__SYSTEM_H */
diff --git a/include/asm-x86/system_64.h b/include/asm-x86/system_64.h
deleted file mode 100644
index 5aedb8bffc5a..000000000000
--- a/include/asm-x86/system_64.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef ASM_X86__SYSTEM_64_H
-#define ASM_X86__SYSTEM_64_H
-
-#include <asm/segment.h>
-#include <asm/cmpxchg.h>
-
-
-static inline unsigned long read_cr8(void)
-{
-	unsigned long cr8;
-	asm volatile("movq %%cr8,%0" : "=r" (cr8));
-	return cr8;
-}
-
-static inline void write_cr8(unsigned long val)
-{
-	asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
-}
-
-#include <linux/irqflags.h>
-
-#endif /* ASM_X86__SYSTEM_64_H */
diff --git a/include/asm-x86/tce.h b/include/asm-x86/tce.h
deleted file mode 100644
index e7932d7fbbab..000000000000
--- a/include/asm-x86/tce.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is derived from asm-powerpc/tce.h.
- *
- * Copyright (C) IBM Corporation, 2006
- *
- * Author: Muli Ben-Yehuda <muli@il.ibm.com>
- * Author: Jon Mason <jdmason@us.ibm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef ASM_X86__TCE_H
-#define ASM_X86__TCE_H
-
-extern unsigned int specified_table_size;
-struct iommu_table;
-
-#define TCE_ENTRY_SIZE   8   /* in bytes */
-
-#define TCE_READ_SHIFT   0
-#define TCE_WRITE_SHIFT  1
-#define TCE_HUBID_SHIFT  2   /* unused */
-#define TCE_RSVD_SHIFT   8   /* unused */
-#define TCE_RPN_SHIFT    12
-#define TCE_UNUSED_SHIFT 48  /* unused */
-
-#define TCE_RPN_MASK     0x0000fffffffff000ULL
-
-extern void tce_build(struct iommu_table *tbl, unsigned long index,
-		      unsigned int npages, unsigned long uaddr, int direction);
-extern void tce_free(struct iommu_table *tbl, long index, unsigned int npages);
-extern void * __init alloc_tce_table(void);
-extern void __init free_tce_table(void *tbl);
-extern int __init build_tce_table(struct pci_dev *dev, void __iomem *bbar);
-
-#endif /* ASM_X86__TCE_H */
diff --git a/include/asm-x86/termbits.h b/include/asm-x86/termbits.h
deleted file mode 100644
index 3d00dc5e0c71..000000000000
--- a/include/asm-x86/termbits.h
+++ /dev/null
@@ -1,198 +0,0 @@
-#ifndef ASM_X86__TERMBITS_H
-#define ASM_X86__TERMBITS_H
-
-#include <linux/posix_types.h>
-
-typedef unsigned char	cc_t;
-typedef unsigned int	speed_t;
-typedef unsigned int	tcflag_t;
-
-#define NCCS 19
-struct termios {
-	tcflag_t c_iflag;		/* input mode flags */
-	tcflag_t c_oflag;		/* output mode flags */
-	tcflag_t c_cflag;		/* control mode flags */
-	tcflag_t c_lflag;		/* local mode flags */
-	cc_t c_line;			/* line discipline */
-	cc_t c_cc[NCCS];		/* control characters */
-};
-
-struct termios2 {
-	tcflag_t c_iflag;		/* input mode flags */
-	tcflag_t c_oflag;		/* output mode flags */
-	tcflag_t c_cflag;		/* control mode flags */
-	tcflag_t c_lflag;		/* local mode flags */
-	cc_t c_line;			/* line discipline */
-	cc_t c_cc[NCCS];		/* control characters */
-	speed_t c_ispeed;		/* input speed */
-	speed_t c_ospeed;		/* output speed */
-};
-
-struct ktermios {
-	tcflag_t c_iflag;		/* input mode flags */
-	tcflag_t c_oflag;		/* output mode flags */
-	tcflag_t c_cflag;		/* control mode flags */
-	tcflag_t c_lflag;		/* local mode flags */
-	cc_t c_line;			/* line discipline */
-	cc_t c_cc[NCCS];		/* control characters */
-	speed_t c_ispeed;		/* input speed */
-	speed_t c_ospeed;		/* output speed */
-};
-
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-
-/* c_iflag bits */
-#define IGNBRK	0000001
-#define BRKINT	0000002
-#define IGNPAR	0000004
-#define PARMRK	0000010
-#define INPCK	0000020
-#define ISTRIP	0000040
-#define INLCR	0000100
-#define IGNCR	0000200
-#define ICRNL	0000400
-#define IUCLC	0001000
-#define IXON	0002000
-#define IXANY	0004000
-#define IXOFF	0010000
-#define IMAXBEL	0020000
-#define IUTF8	0040000
-
-/* c_oflag bits */
-#define OPOST	0000001
-#define OLCUC	0000002
-#define ONLCR	0000004
-#define OCRNL	0000010
-#define ONOCR	0000020
-#define ONLRET	0000040
-#define OFILL	0000100
-#define OFDEL	0000200
-#define NLDLY	0000400
-#define   NL0	0000000
-#define   NL1	0000400
-#define CRDLY	0003000
-#define   CR0	0000000
-#define   CR1	0001000
-#define   CR2	0002000
-#define   CR3	0003000
-#define TABDLY	0014000
-#define   TAB0	0000000
-#define   TAB1	0004000
-#define   TAB2	0010000
-#define   TAB3	0014000
-#define   XTABS	0014000
-#define BSDLY	0020000
-#define   BS0	0000000
-#define   BS1	0020000
-#define VTDLY	0040000
-#define   VT0	0000000
-#define   VT1	0040000
-#define FFDLY	0100000
-#define   FF0	0000000
-#define   FF1	0100000
-
-/* c_cflag bit meaning */
-#define CBAUD	0010017
-#define  B0	0000000		/* hang up */
-#define  B50	0000001
-#define  B75	0000002
-#define  B110	0000003
-#define  B134	0000004
-#define  B150	0000005
-#define  B200	0000006
-#define  B300	0000007
-#define  B600	0000010
-#define  B1200	0000011
-#define  B1800	0000012
-#define  B2400	0000013
-#define  B4800	0000014
-#define  B9600	0000015
-#define  B19200	0000016
-#define  B38400	0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE	0000060
-#define   CS5	0000000
-#define   CS6	0000020
-#define   CS7	0000040
-#define   CS8	0000060
-#define CSTOPB	0000100
-#define CREAD	0000200
-#define PARENB	0000400
-#define PARODD	0001000
-#define HUPCL	0002000
-#define CLOCAL	0004000
-#define CBAUDEX 0010000
-#define	   BOTHER 0010000		/* non standard rate */
-#define    B57600 0010001
-#define   B115200 0010002
-#define   B230400 0010003
-#define   B460800 0010004
-#define   B500000 0010005
-#define   B576000 0010006
-#define   B921600 0010007
-#define  B1000000 0010010
-#define  B1152000 0010011
-#define  B1500000 0010012
-#define  B2000000 0010013
-#define  B2500000 0010014
-#define  B3000000 0010015
-#define  B3500000 0010016
-#define  B4000000 0010017
-#define CIBAUD	  002003600000	/* input baud rate */
-#define CMSPAR	  010000000000	/* mark or space (stick) parity */
-#define CRTSCTS	  020000000000	/* flow control */
-
-#define IBSHIFT	  16		/* Shift from CBAUD to CIBAUD */
-
-/* c_lflag bits */
-#define ISIG	0000001
-#define ICANON	0000002
-#define XCASE	0000004
-#define ECHO	0000010
-#define ECHOE	0000020
-#define ECHOK	0000040
-#define ECHONL	0000100
-#define NOFLSH	0000200
-#define TOSTOP	0000400
-#define ECHOCTL	0001000
-#define ECHOPRT	0002000
-#define ECHOKE	0004000
-#define FLUSHO	0010000
-#define PENDIN	0040000
-#define IEXTEN	0100000
-
-/* tcflow() and TCXONC use these */
-#define	TCOOFF		0
-#define	TCOON		1
-#define	TCIOFF		2
-#define	TCION		3
-
-/* tcflush() and TCFLSH use these */
-#define	TCIFLUSH	0
-#define	TCOFLUSH	1
-#define	TCIOFLUSH	2
-
-/* tcsetattr uses these */
-#define	TCSANOW		0
-#define	TCSADRAIN	1
-#define	TCSAFLUSH	2
-
-#endif /* ASM_X86__TERMBITS_H */
diff --git a/include/asm-x86/termios.h b/include/asm-x86/termios.h
deleted file mode 100644
index e235db248071..000000000000
--- a/include/asm-x86/termios.h
+++ /dev/null
@@ -1,113 +0,0 @@
-#ifndef ASM_X86__TERMIOS_H
-#define ASM_X86__TERMIOS_H
-
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-
-struct winsize {
-	unsigned short ws_row;
-	unsigned short ws_col;
-	unsigned short ws_xpixel;
-	unsigned short ws_ypixel;
-};
-
-#define NCC 8
-struct termio {
-	unsigned short c_iflag;		/* input mode flags */
-	unsigned short c_oflag;		/* output mode flags */
-	unsigned short c_cflag;		/* control mode flags */
-	unsigned short c_lflag;		/* local mode flags */
-	unsigned char c_line;		/* line discipline */
-	unsigned char c_cc[NCC];	/* control characters */
-};
-
-/* modem lines */
-#define TIOCM_LE	0x001
-#define TIOCM_DTR	0x002
-#define TIOCM_RTS	0x004
-#define TIOCM_ST	0x008
-#define TIOCM_SR	0x010
-#define TIOCM_CTS	0x020
-#define TIOCM_CAR	0x040
-#define TIOCM_RNG	0x080
-#define TIOCM_DSR	0x100
-#define TIOCM_CD	TIOCM_CAR
-#define TIOCM_RI	TIOCM_RNG
-#define TIOCM_OUT1	0x2000
-#define TIOCM_OUT2	0x4000
-#define TIOCM_LOOP	0x8000
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-
-#ifdef __KERNEL__
-
-#include <asm/uaccess.h>
-
-/*	intr=^C		quit=^\		erase=del	kill=^U
-	eof=^D		vtime=\0	vmin=\1		sxtc=\0
-	start=^Q	stop=^S		susp=^Z		eol=\0
-	reprint=^R	discard=^U	werase=^W	lnext=^V
-	eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
-	unsigned short __tmp; \
-	get_user(__tmp,&(termio)->x); \
-	*(unsigned short *) &(termios)->x = __tmp; \
-}
-
-static inline int user_termio_to_kernel_termios(struct ktermios *termios,
-						struct termio __user *termio)
-{
-	SET_LOW_TERMIOS_BITS(termios, termio, c_iflag);
-	SET_LOW_TERMIOS_BITS(termios, termio, c_oflag);
-	SET_LOW_TERMIOS_BITS(termios, termio, c_cflag);
-	SET_LOW_TERMIOS_BITS(termios, termio, c_lflag);
-	return copy_from_user(termios->c_cc, termio->c_cc, NCC);
-}
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-static inline int kernel_termios_to_user_termio(struct termio __user *termio,
-					    struct ktermios *termios)
-{
-	put_user((termios)->c_iflag, &(termio)->c_iflag);
-	put_user((termios)->c_oflag, &(termio)->c_oflag);
-	put_user((termios)->c_cflag, &(termio)->c_cflag);
-	put_user((termios)->c_lflag, &(termio)->c_lflag);
-	put_user((termios)->c_line,  &(termio)->c_line);
-	return copy_to_user((termio)->c_cc, (termios)->c_cc, NCC);
-}
-
-static inline int user_termios_to_kernel_termios(struct ktermios *k,
-						 struct termios2 __user *u)
-{
-	return copy_from_user(k, u, sizeof(struct termios2));
-}
-
-static inline int kernel_termios_to_user_termios(struct termios2 __user *u,
-						 struct ktermios *k)
-{
-	return copy_to_user(u, k, sizeof(struct termios2));
-}
-
-static inline int user_termios_to_kernel_termios_1(struct ktermios *k,
-						   struct termios __user *u)
-{
-	return copy_from_user(k, u, sizeof(struct termios));
-}
-
-static inline int kernel_termios_to_user_termios_1(struct termios __user *u,
-						   struct ktermios *k)
-{
-	return copy_to_user(u, k, sizeof(struct termios));
-}
-
-#endif	/* __KERNEL__ */
-
-#endif /* ASM_X86__TERMIOS_H */
diff --git a/include/asm-x86/therm_throt.h b/include/asm-x86/therm_throt.h
deleted file mode 100644
index 1c7f57b6b66e..000000000000
--- a/include/asm-x86/therm_throt.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef ASM_X86__THERM_THROT_H
-#define ASM_X86__THERM_THROT_H
-
-#include <asm/atomic.h>
-
-extern atomic_t therm_throt_en;
-int therm_throt_process(int curr);
-
-#endif /* ASM_X86__THERM_THROT_H */
diff --git a/include/asm-x86/thread_info.h b/include/asm-x86/thread_info.h
deleted file mode 100644
index 3f4e52bb77f5..000000000000
--- a/include/asm-x86/thread_info.h
+++ /dev/null
@@ -1,264 +0,0 @@
-/* thread_info.h: low-level thread information
- *
- * Copyright (C) 2002  David Howells (dhowells@redhat.com)
- * - Incorporating suggestions made by Linus Torvalds and Dave Miller
- */
-
-#ifndef ASM_X86__THREAD_INFO_H
-#define ASM_X86__THREAD_INFO_H
-
-#include <linux/compiler.h>
-#include <asm/page.h>
-#include <asm/types.h>
-
-/*
- * low level task data that entry.S needs immediate access to
- * - this struct should fit entirely inside of one cache line
- * - this struct shares the supervisor stack pages
- */
-#ifndef __ASSEMBLY__
-struct task_struct;
-struct exec_domain;
-#include <asm/processor.h>
-
-struct thread_info {
-	struct task_struct	*task;		/* main task structure */
-	struct exec_domain	*exec_domain;	/* execution domain */
-	unsigned long		flags;		/* low level flags */
-	__u32			status;		/* thread synchronous flags */
-	__u32			cpu;		/* current CPU */
-	int			preempt_count;	/* 0 => preemptable,
-						   <0 => BUG */
-	mm_segment_t		addr_limit;
-	struct restart_block    restart_block;
-	void __user		*sysenter_return;
-#ifdef CONFIG_X86_32
-	unsigned long           previous_esp;   /* ESP of the previous stack in
-						   case of nested (IRQ) stacks
-						*/
-	__u8			supervisor_stack[0];
-#endif
-};
-
-#define INIT_THREAD_INFO(tsk)			\
-{						\
-	.task		= &tsk,			\
-	.exec_domain	= &default_exec_domain,	\
-	.flags		= 0,			\
-	.cpu		= 0,			\
-	.preempt_count	= 1,			\
-	.addr_limit	= KERNEL_DS,		\
-	.restart_block = {			\
-		.fn = do_no_restart_syscall,	\
-	},					\
-}
-
-#define init_thread_info	(init_thread_union.thread_info)
-#define init_stack		(init_thread_union.stack)
-
-#else /* !__ASSEMBLY__ */
-
-#include <asm/asm-offsets.h>
-
-#endif
-
-/*
- * thread information flags
- * - these are process state flags that various assembly files
- *   may need to access
- * - pending work-to-be-done flags are in LSW
- * - other flags in MSW
- * Warning: layout of LSW is hardcoded in entry.S
- */
-#define TIF_SYSCALL_TRACE	0	/* syscall trace active */
-#define TIF_NOTIFY_RESUME	1	/* callback before returning to user */
-#define TIF_SIGPENDING		2	/* signal pending */
-#define TIF_NEED_RESCHED	3	/* rescheduling necessary */
-#define TIF_SINGLESTEP		4	/* reenable singlestep on user return*/
-#define TIF_IRET		5	/* force IRET */
-#define TIF_SYSCALL_EMU		6	/* syscall emulation active */
-#define TIF_SYSCALL_AUDIT	7	/* syscall auditing active */
-#define TIF_SECCOMP		8	/* secure computing */
-#define TIF_MCE_NOTIFY		10	/* notify userspace of an MCE */
-#define TIF_NOTSC		16	/* TSC is not accessible in userland */
-#define TIF_IA32		17	/* 32bit process */
-#define TIF_FORK		18	/* ret_from_fork */
-#define TIF_ABI_PENDING		19
-#define TIF_MEMDIE		20
-#define TIF_DEBUG		21	/* uses debug registers */
-#define TIF_IO_BITMAP		22	/* uses I/O bitmap */
-#define TIF_FREEZE		23	/* is freezing for suspend */
-#define TIF_FORCED_TF		24	/* true if TF in eflags artificially */
-#define TIF_DEBUGCTLMSR		25	/* uses thread_struct.debugctlmsr */
-#define TIF_DS_AREA_MSR		26      /* uses thread_struct.ds_area_msr */
-#define TIF_BTS_TRACE_TS	27      /* record scheduling event timestamps */
-
-#define _TIF_SYSCALL_TRACE	(1 << TIF_SYSCALL_TRACE)
-#define _TIF_NOTIFY_RESUME	(1 << TIF_NOTIFY_RESUME)
-#define _TIF_SIGPENDING		(1 << TIF_SIGPENDING)
-#define _TIF_SINGLESTEP		(1 << TIF_SINGLESTEP)
-#define _TIF_NEED_RESCHED	(1 << TIF_NEED_RESCHED)
-#define _TIF_IRET		(1 << TIF_IRET)
-#define _TIF_SYSCALL_EMU	(1 << TIF_SYSCALL_EMU)
-#define _TIF_SYSCALL_AUDIT	(1 << TIF_SYSCALL_AUDIT)
-#define _TIF_SECCOMP		(1 << TIF_SECCOMP)
-#define _TIF_MCE_NOTIFY		(1 << TIF_MCE_NOTIFY)
-#define _TIF_NOTSC		(1 << TIF_NOTSC)
-#define _TIF_IA32		(1 << TIF_IA32)
-#define _TIF_FORK		(1 << TIF_FORK)
-#define _TIF_ABI_PENDING	(1 << TIF_ABI_PENDING)
-#define _TIF_DEBUG		(1 << TIF_DEBUG)
-#define _TIF_IO_BITMAP		(1 << TIF_IO_BITMAP)
-#define _TIF_FREEZE		(1 << TIF_FREEZE)
-#define _TIF_FORCED_TF		(1 << TIF_FORCED_TF)
-#define _TIF_DEBUGCTLMSR	(1 << TIF_DEBUGCTLMSR)
-#define _TIF_DS_AREA_MSR	(1 << TIF_DS_AREA_MSR)
-#define _TIF_BTS_TRACE_TS	(1 << TIF_BTS_TRACE_TS)
-
-/* work to do in syscall_trace_enter() */
-#define _TIF_WORK_SYSCALL_ENTRY	\
-	(_TIF_SYSCALL_TRACE | _TIF_SYSCALL_EMU | \
-	 _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | _TIF_SINGLESTEP)
-
-/* work to do in syscall_trace_leave() */
-#define _TIF_WORK_SYSCALL_EXIT	\
-	(_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SINGLESTEP)
-
-/* work to do on interrupt/exception return */
-#define _TIF_WORK_MASK							\
-	(0x0000FFFF &							\
-	 ~(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|			\
-	   _TIF_SINGLESTEP|_TIF_SECCOMP|_TIF_SYSCALL_EMU))
-
-/* work to do on any return to user space */
-#define _TIF_ALLWORK_MASK (0x0000FFFF & ~_TIF_SECCOMP)
-
-/* Only used for 64 bit */
-#define _TIF_DO_NOTIFY_MASK						\
-	(_TIF_SIGPENDING|_TIF_MCE_NOTIFY|_TIF_NOTIFY_RESUME)
-
-/* flags to check in __switch_to() */
-#define _TIF_WORK_CTXSW							\
-	(_TIF_IO_BITMAP|_TIF_DEBUGCTLMSR|_TIF_DS_AREA_MSR|_TIF_BTS_TRACE_TS| \
-								_TIF_NOTSC)
-
-#define _TIF_WORK_CTXSW_PREV _TIF_WORK_CTXSW
-#define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW|_TIF_DEBUG)
-
-#define PREEMPT_ACTIVE		0x10000000
-
-/* thread information allocation */
-#ifdef CONFIG_DEBUG_STACK_USAGE
-#define THREAD_FLAGS (GFP_KERNEL | __GFP_ZERO)
-#else
-#define THREAD_FLAGS GFP_KERNEL
-#endif
-
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
-
-#define alloc_thread_info(tsk)						\
-	((struct thread_info *)__get_free_pages(THREAD_FLAGS, THREAD_ORDER))
-
-#ifdef CONFIG_X86_32
-
-#define STACK_WARN	(THREAD_SIZE/8)
-/*
- * macros/functions for gaining access to the thread information structure
- *
- * preempt_count needs to be 1 initially, until the scheduler is functional.
- */
-#ifndef __ASSEMBLY__
-
-
-/* how to get the current stack pointer from C */
-register unsigned long current_stack_pointer asm("esp") __used;
-
-/* how to get the thread information struct from C */
-static inline struct thread_info *current_thread_info(void)
-{
-	return (struct thread_info *)
-		(current_stack_pointer & ~(THREAD_SIZE - 1));
-}
-
-#else /* !__ASSEMBLY__ */
-
-/* how to get the thread information struct from ASM */
-#define GET_THREAD_INFO(reg)	 \
-	movl $-THREAD_SIZE, reg; \
-	andl %esp, reg
-
-/* use this one if reg already contains %esp */
-#define GET_THREAD_INFO_WITH_ESP(reg) \
-	andl $-THREAD_SIZE, reg
-
-#endif
-
-#else /* X86_32 */
-
-#include <asm/pda.h>
-
-/*
- * macros/functions for gaining access to the thread information structure
- * preempt_count needs to be 1 initially, until the scheduler is functional.
- */
-#ifndef __ASSEMBLY__
-static inline struct thread_info *current_thread_info(void)
-{
-	struct thread_info *ti;
-	ti = (void *)(read_pda(kernelstack) + PDA_STACKOFFSET - THREAD_SIZE);
-	return ti;
-}
-
-/* do not use in interrupt context */
-static inline struct thread_info *stack_thread_info(void)
-{
-	struct thread_info *ti;
-	asm("andq %%rsp,%0; " : "=r" (ti) : "0" (~(THREAD_SIZE - 1)));
-	return ti;
-}
-
-#else /* !__ASSEMBLY__ */
-
-/* how to get the thread information struct from ASM */
-#define GET_THREAD_INFO(reg) \
-	movq %gs:pda_kernelstack,reg ; \
-	subq $(THREAD_SIZE-PDA_STACKOFFSET),reg
-
-#endif
-
-#endif /* !X86_32 */
-
-/*
- * Thread-synchronous status.
- *
- * This is different from the flags in that nobody else
- * ever touches our thread-synchronous status, so we don't
- * have to worry about atomic accesses.
- */
-#define TS_USEDFPU		0x0001	/* FPU was used by this task
-					   this quantum (SMP) */
-#define TS_COMPAT		0x0002	/* 32bit syscall active (64BIT)*/
-#define TS_POLLING		0x0004	/* true if in idle loop
-					   and not sleeping */
-#define TS_RESTORE_SIGMASK	0x0008	/* restore signal mask in do_signal() */
-#define TS_XSAVE		0x0010	/* Use xsave/xrstor */
-
-#define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING)
-
-#ifndef __ASSEMBLY__
-#define HAVE_SET_RESTORE_SIGMASK	1
-static inline void set_restore_sigmask(void)
-{
-	struct thread_info *ti = current_thread_info();
-	ti->status |= TS_RESTORE_SIGMASK;
-	set_bit(TIF_SIGPENDING, (unsigned long *)&ti->flags);
-}
-#endif	/* !__ASSEMBLY__ */
-
-#ifndef __ASSEMBLY__
-extern void arch_task_cache_init(void);
-extern void free_thread_info(struct thread_info *ti);
-extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
-#define arch_task_cache_init arch_task_cache_init
-#endif
-#endif /* ASM_X86__THREAD_INFO_H */
diff --git a/include/asm-x86/time.h b/include/asm-x86/time.h
deleted file mode 100644
index 3e724eef7ac4..000000000000
--- a/include/asm-x86/time.h
+++ /dev/null
@@ -1,63 +0,0 @@
-#ifndef ASM_X86__TIME_H
-#define ASM_X86__TIME_H
-
-extern void hpet_time_init(void);
-
-#include <asm/mc146818rtc.h>
-#ifdef CONFIG_X86_32
-#include <linux/efi.h>
-
-static inline unsigned long native_get_wallclock(void)
-{
-	unsigned long retval;
-
-	if (efi_enabled)
-		retval = efi_get_time();
-	else
-		retval = mach_get_cmos_time();
-
-	return retval;
-}
-
-static inline int native_set_wallclock(unsigned long nowtime)
-{
-	int retval;
-
-	if (efi_enabled)
-		retval = efi_set_rtc_mmss(nowtime);
-	else
-		retval = mach_set_rtc_mmss(nowtime);
-
-	return retval;
-}
-
-#else
-extern void native_time_init_hook(void);
-
-static inline unsigned long native_get_wallclock(void)
-{
-	return mach_get_cmos_time();
-}
-
-static inline int native_set_wallclock(unsigned long nowtime)
-{
-	return mach_set_rtc_mmss(nowtime);
-}
-
-#endif
-
-extern void time_init(void);
-
-#ifdef CONFIG_PARAVIRT
-#include <asm/paravirt.h>
-#else /* !CONFIG_PARAVIRT */
-
-#define get_wallclock() native_get_wallclock()
-#define set_wallclock(x) native_set_wallclock(x)
-#define choose_time_init() hpet_time_init
-
-#endif /* CONFIG_PARAVIRT */
-
-extern unsigned long __init calibrate_cpu(void);
-
-#endif /* ASM_X86__TIME_H */
diff --git a/include/asm-x86/timer.h b/include/asm-x86/timer.h
deleted file mode 100644
index d0babce4b47a..000000000000
--- a/include/asm-x86/timer.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifndef ASM_X86__TIMER_H
-#define ASM_X86__TIMER_H
-#include <linux/init.h>
-#include <linux/pm.h>
-#include <linux/percpu.h>
-
-#define TICK_SIZE (tick_nsec / 1000)
-
-unsigned long long native_sched_clock(void);
-unsigned long native_calibrate_tsc(void);
-
-#ifdef CONFIG_X86_32
-extern int timer_ack;
-extern int recalibrate_cpu_khz(void);
-#endif /* CONFIG_X86_32 */
-
-extern int no_timer_check;
-
-#ifndef CONFIG_PARAVIRT
-#define calibrate_tsc() native_calibrate_tsc()
-#endif
-
-/* Accelerators for sched_clock()
- * convert from cycles(64bits) => nanoseconds (64bits)
- *  basic equation:
- *		ns = cycles / (freq / ns_per_sec)
- *		ns = cycles * (ns_per_sec / freq)
- *		ns = cycles * (10^9 / (cpu_khz * 10^3))
- *		ns = cycles * (10^6 / cpu_khz)
- *
- *	Then we use scaling math (suggested by george@mvista.com) to get:
- *		ns = cycles * (10^6 * SC / cpu_khz) / SC
- *		ns = cycles * cyc2ns_scale / SC
- *
- *	And since SC is a constant power of two, we can convert the div
- *  into a shift.
- *
- *  We can use khz divisor instead of mhz to keep a better precision, since
- *  cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
- *  (mathieu.desnoyers@polymtl.ca)
- *
- *			-johnstul@us.ibm.com "math is hard, lets go shopping!"
- */
-
-DECLARE_PER_CPU(unsigned long, cyc2ns);
-
-#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
-
-static inline unsigned long long __cycles_2_ns(unsigned long long cyc)
-{
-	return cyc * per_cpu(cyc2ns, smp_processor_id()) >> CYC2NS_SCALE_FACTOR;
-}
-
-static inline unsigned long long cycles_2_ns(unsigned long long cyc)
-{
-	unsigned long long ns;
-	unsigned long flags;
-
-	local_irq_save(flags);
-	ns = __cycles_2_ns(cyc);
-	local_irq_restore(flags);
-
-	return ns;
-}
-
-#endif /* ASM_X86__TIMER_H */
diff --git a/include/asm-x86/timex.h b/include/asm-x86/timex.h
deleted file mode 100644
index d1ce2416a5da..000000000000
--- a/include/asm-x86/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* x86 architecture timex specifications */
-#ifndef ASM_X86__TIMEX_H
-#define ASM_X86__TIMEX_H
-
-#include <asm/processor.h>
-#include <asm/tsc.h>
-
-#ifdef CONFIG_X86_ELAN
-#  define PIT_TICK_RATE 1189200 /* AMD Elan has different frequency! */
-#elif defined(CONFIG_X86_RDC321X)
-#  define PIT_TICK_RATE 1041667 /* Underlying HZ for R8610 */
-#else
-#  define PIT_TICK_RATE 1193182 /* Underlying HZ */
-#endif
-#define CLOCK_TICK_RATE	PIT_TICK_RATE
-
-#define ARCH_HAS_READ_CURRENT_TIMER
-
-#endif /* ASM_X86__TIMEX_H */
diff --git a/include/asm-x86/tlb.h b/include/asm-x86/tlb.h
deleted file mode 100644
index db36e9e89e87..000000000000
--- a/include/asm-x86/tlb.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef ASM_X86__TLB_H
-#define ASM_X86__TLB_H
-
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-
-#include <asm-generic/tlb.h>
-
-#endif /* ASM_X86__TLB_H */
diff --git a/include/asm-x86/tlbflush.h b/include/asm-x86/tlbflush.h
deleted file mode 100644
index 3cdd08b5bdb7..000000000000
--- a/include/asm-x86/tlbflush.h
+++ /dev/null
@@ -1,178 +0,0 @@
-#ifndef ASM_X86__TLBFLUSH_H
-#define ASM_X86__TLBFLUSH_H
-
-#include <linux/mm.h>
-#include <linux/sched.h>
-
-#include <asm/processor.h>
-#include <asm/system.h>
-
-#ifdef CONFIG_PARAVIRT
-#include <asm/paravirt.h>
-#else
-#define __flush_tlb() __native_flush_tlb()
-#define __flush_tlb_global() __native_flush_tlb_global()
-#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
-#endif
-
-static inline void __native_flush_tlb(void)
-{
-	write_cr3(read_cr3());
-}
-
-static inline void __native_flush_tlb_global(void)
-{
-	unsigned long flags;
-	unsigned long cr4;
-
-	/*
-	 * Read-modify-write to CR4 - protect it from preemption and
-	 * from interrupts. (Use the raw variant because this code can
-	 * be called from deep inside debugging code.)
-	 */
-	raw_local_irq_save(flags);
-
-	cr4 = read_cr4();
-	/* clear PGE */
-	write_cr4(cr4 & ~X86_CR4_PGE);
-	/* write old PGE again and flush TLBs */
-	write_cr4(cr4);
-
-	raw_local_irq_restore(flags);
-}
-
-static inline void __native_flush_tlb_single(unsigned long addr)
-{
-	asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
-}
-
-static inline void __flush_tlb_all(void)
-{
-	if (cpu_has_pge)
-		__flush_tlb_global();
-	else
-		__flush_tlb();
-}
-
-static inline void __flush_tlb_one(unsigned long addr)
-{
-	if (cpu_has_invlpg)
-		__flush_tlb_single(addr);
-	else
-		__flush_tlb();
-}
-
-#ifdef CONFIG_X86_32
-# define TLB_FLUSH_ALL	0xffffffff
-#else
-# define TLB_FLUSH_ALL	-1ULL
-#endif
-
-/*
- * TLB flushing:
- *
- *  - flush_tlb() flushes the current mm struct TLBs
- *  - flush_tlb_all() flushes all processes TLBs
- *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
- *  - flush_tlb_page(vma, vmaddr) flushes one page
- *  - flush_tlb_range(vma, start, end) flushes a range of pages
- *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
- *  - flush_tlb_others(cpumask, mm, va) flushes TLBs on other cpus
- *
- * ..but the i386 has somewhat limited tlb flushing capabilities,
- * and page-granular flushes are available only on i486 and up.
- *
- * x86-64 can only flush individual pages or full VMs. For a range flush
- * we always do the full VM. Might be worth trying if for a small
- * range a few INVLPGs in a row are a win.
- */
-
-#ifndef CONFIG_SMP
-
-#define flush_tlb() __flush_tlb()
-#define flush_tlb_all() __flush_tlb_all()
-#define local_flush_tlb() __flush_tlb()
-
-static inline void flush_tlb_mm(struct mm_struct *mm)
-{
-	if (mm == current->active_mm)
-		__flush_tlb();
-}
-
-static inline void flush_tlb_page(struct vm_area_struct *vma,
-				  unsigned long addr)
-{
-	if (vma->vm_mm == current->active_mm)
-		__flush_tlb_one(addr);
-}
-
-static inline void flush_tlb_range(struct vm_area_struct *vma,
-				   unsigned long start, unsigned long end)
-{
-	if (vma->vm_mm == current->active_mm)
-		__flush_tlb();
-}
-
-static inline void native_flush_tlb_others(const cpumask_t *cpumask,
-					   struct mm_struct *mm,
-					   unsigned long va)
-{
-}
-
-static inline void reset_lazy_tlbstate(void)
-{
-}
-
-#else  /* SMP */
-
-#include <asm/smp.h>
-
-#define local_flush_tlb() __flush_tlb()
-
-extern void flush_tlb_all(void);
-extern void flush_tlb_current_task(void);
-extern void flush_tlb_mm(struct mm_struct *);
-extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
-
-#define flush_tlb()	flush_tlb_current_task()
-
-static inline void flush_tlb_range(struct vm_area_struct *vma,
-				   unsigned long start, unsigned long end)
-{
-	flush_tlb_mm(vma->vm_mm);
-}
-
-void native_flush_tlb_others(const cpumask_t *cpumask, struct mm_struct *mm,
-			     unsigned long va);
-
-#define TLBSTATE_OK	1
-#define TLBSTATE_LAZY	2
-
-#ifdef CONFIG_X86_32
-struct tlb_state {
-	struct mm_struct *active_mm;
-	int state;
-	char __cacheline_padding[L1_CACHE_BYTES-8];
-};
-DECLARE_PER_CPU(struct tlb_state, cpu_tlbstate);
-
-void reset_lazy_tlbstate(void);
-#else
-static inline void reset_lazy_tlbstate(void)
-{
-}
-#endif
-
-#endif	/* SMP */
-
-#ifndef CONFIG_PARAVIRT
-#define flush_tlb_others(mask, mm, va)	native_flush_tlb_others(&mask, mm, va)
-#endif
-
-static inline void flush_tlb_kernel_range(unsigned long start,
-					  unsigned long end)
-{
-	flush_tlb_all();
-}
-
-#endif /* ASM_X86__TLBFLUSH_H */
diff --git a/include/asm-x86/topology.h b/include/asm-x86/topology.h
deleted file mode 100644
index 7eca9bc022b2..000000000000
--- a/include/asm-x86/topology.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * Written by: Matthew Dobson, IBM Corporation
- *
- * Copyright (C) 2002, IBM Corp.
- *
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Send feedback to <colpatch@us.ibm.com>
- */
-#ifndef ASM_X86__TOPOLOGY_H
-#define ASM_X86__TOPOLOGY_H
-
-#ifdef CONFIG_X86_32
-# ifdef CONFIG_X86_HT
-#  define ENABLE_TOPO_DEFINES
-# endif
-#else
-# ifdef CONFIG_SMP
-#  define ENABLE_TOPO_DEFINES
-# endif
-#endif
-
-/* Node not present */
-#define NUMA_NO_NODE	(-1)
-
-#ifdef CONFIG_NUMA
-#include <linux/cpumask.h>
-#include <asm/mpspec.h>
-
-#ifdef CONFIG_X86_32
-
-/* Mappings between node number and cpus on that node. */
-extern cpumask_t node_to_cpumask_map[];
-
-/* Mappings between logical cpu number and node number */
-extern int cpu_to_node_map[];
-
-/* Returns the number of the node containing CPU 'cpu' */
-static inline int cpu_to_node(int cpu)
-{
-	return cpu_to_node_map[cpu];
-}
-#define early_cpu_to_node(cpu)	cpu_to_node(cpu)
-
-/* Returns a bitmask of CPUs on Node 'node'.
- *
- * Side note: this function creates the returned cpumask on the stack
- * so with a high NR_CPUS count, excessive stack space is used.  The
- * node_to_cpumask_ptr function should be used whenever possible.
- */
-static inline cpumask_t node_to_cpumask(int node)
-{
-	return node_to_cpumask_map[node];
-}
-
-#else /* CONFIG_X86_64 */
-
-/* Mappings between node number and cpus on that node. */
-extern cpumask_t *node_to_cpumask_map;
-
-/* Mappings between logical cpu number and node number */
-DECLARE_EARLY_PER_CPU(int, x86_cpu_to_node_map);
-
-/* Returns the number of the current Node. */
-#define numa_node_id()		read_pda(nodenumber)
-
-#ifdef CONFIG_DEBUG_PER_CPU_MAPS
-extern int cpu_to_node(int cpu);
-extern int early_cpu_to_node(int cpu);
-extern const cpumask_t *_node_to_cpumask_ptr(int node);
-extern cpumask_t node_to_cpumask(int node);
-
-#else	/* !CONFIG_DEBUG_PER_CPU_MAPS */
-
-/* Returns the number of the node containing CPU 'cpu' */
-static inline int cpu_to_node(int cpu)
-{
-	return per_cpu(x86_cpu_to_node_map, cpu);
-}
-
-/* Same function but used if called before per_cpu areas are setup */
-static inline int early_cpu_to_node(int cpu)
-{
-	if (early_per_cpu_ptr(x86_cpu_to_node_map))
-		return early_per_cpu_ptr(x86_cpu_to_node_map)[cpu];
-
-	return per_cpu(x86_cpu_to_node_map, cpu);
-}
-
-/* Returns a pointer to the cpumask of CPUs on Node 'node'. */
-static inline const cpumask_t *_node_to_cpumask_ptr(int node)
-{
-	return &node_to_cpumask_map[node];
-}
-
-/* Returns a bitmask of CPUs on Node 'node'. */
-static inline cpumask_t node_to_cpumask(int node)
-{
-	return node_to_cpumask_map[node];
-}
-
-#endif /* !CONFIG_DEBUG_PER_CPU_MAPS */
-
-/* Replace default node_to_cpumask_ptr with optimized version */
-#define node_to_cpumask_ptr(v, node)		\
-		const cpumask_t *v = _node_to_cpumask_ptr(node)
-
-#define node_to_cpumask_ptr_next(v, node)	\
-			   v = _node_to_cpumask_ptr(node)
-
-#endif /* CONFIG_X86_64 */
-
-/*
- * Returns the number of the node containing Node 'node'. This
- * architecture is flat, so it is a pretty simple function!
- */
-#define parent_node(node) (node)
-
-#define pcibus_to_node(bus) __pcibus_to_node(bus)
-#define pcibus_to_cpumask(bus) __pcibus_to_cpumask(bus)
-
-#ifdef CONFIG_X86_32
-extern unsigned long node_start_pfn[];
-extern unsigned long node_end_pfn[];
-extern unsigned long node_remap_size[];
-#define node_has_online_mem(nid) (node_start_pfn[nid] != node_end_pfn[nid])
-
-# define SD_CACHE_NICE_TRIES	1
-# define SD_IDLE_IDX		1
-# define SD_NEWIDLE_IDX		2
-# define SD_FORKEXEC_IDX	0
-
-#else
-
-# define SD_CACHE_NICE_TRIES	2
-# define SD_IDLE_IDX		2
-# define SD_NEWIDLE_IDX		2
-# define SD_FORKEXEC_IDX	1
-
-#endif
-
-/* sched_domains SD_NODE_INIT for NUMAQ machines */
-#define SD_NODE_INIT (struct sched_domain) {		\
-	.min_interval		= 8,			\
-	.max_interval		= 32,			\
-	.busy_factor		= 32,			\
-	.imbalance_pct		= 125,			\
-	.cache_nice_tries	= SD_CACHE_NICE_TRIES,	\
-	.busy_idx		= 3,			\
-	.idle_idx		= SD_IDLE_IDX,		\
-	.newidle_idx		= SD_NEWIDLE_IDX,	\
-	.wake_idx		= 1,			\
-	.forkexec_idx		= SD_FORKEXEC_IDX,	\
-	.flags			= SD_LOAD_BALANCE	\
-				| SD_BALANCE_EXEC	\
-				| SD_BALANCE_FORK	\
-				| SD_SERIALIZE		\
-				| SD_WAKE_BALANCE,	\
-	.last_balance		= jiffies,		\
-	.balance_interval	= 1,			\
-}
-
-#ifdef CONFIG_X86_64_ACPI_NUMA
-extern int __node_distance(int, int);
-#define node_distance(a, b) __node_distance(a, b)
-#endif
-
-#else /* !CONFIG_NUMA */
-
-#define numa_node_id()		0
-#define	cpu_to_node(cpu)	0
-#define	early_cpu_to_node(cpu)	0
-
-static inline const cpumask_t *_node_to_cpumask_ptr(int node)
-{
-	return &cpu_online_map;
-}
-static inline cpumask_t node_to_cpumask(int node)
-{
-	return cpu_online_map;
-}
-static inline int node_to_first_cpu(int node)
-{
-	return first_cpu(cpu_online_map);
-}
-
-/* Replace default node_to_cpumask_ptr with optimized version */
-#define node_to_cpumask_ptr(v, node)		\
-		const cpumask_t *v = _node_to_cpumask_ptr(node)
-
-#define node_to_cpumask_ptr_next(v, node)	\
-			   v = _node_to_cpumask_ptr(node)
-#endif
-
-#include <asm-generic/topology.h>
-
-#ifdef CONFIG_NUMA
-/* Returns the number of the first CPU on Node 'node'. */
-static inline int node_to_first_cpu(int node)
-{
-	node_to_cpumask_ptr(mask, node);
-	return first_cpu(*mask);
-}
-#endif
-
-extern cpumask_t cpu_coregroup_map(int cpu);
-
-#ifdef ENABLE_TOPO_DEFINES
-#define topology_physical_package_id(cpu)	(cpu_data(cpu).phys_proc_id)
-#define topology_core_id(cpu)			(cpu_data(cpu).cpu_core_id)
-#define topology_core_siblings(cpu)		(per_cpu(cpu_core_map, cpu))
-#define topology_thread_siblings(cpu)		(per_cpu(cpu_sibling_map, cpu))
-
-/* indicates that pointers to the topology cpumask_t maps are valid */
-#define arch_provides_topology_pointers		yes
-#endif
-
-static inline void arch_fix_phys_package_id(int num, u32 slot)
-{
-}
-
-struct pci_bus;
-void set_pci_bus_resources_arch_default(struct pci_bus *b);
-
-#ifdef CONFIG_SMP
-#define mc_capable()			(boot_cpu_data.x86_max_cores > 1)
-#define smt_capable()			(smp_num_siblings > 1)
-#endif
-
-#ifdef CONFIG_NUMA
-extern int get_mp_bus_to_node(int busnum);
-extern void set_mp_bus_to_node(int busnum, int node);
-#else
-static inline int get_mp_bus_to_node(int busnum)
-{
-	return 0;
-}
-static inline void set_mp_bus_to_node(int busnum, int node)
-{
-}
-#endif
-
-#endif /* ASM_X86__TOPOLOGY_H */
diff --git a/include/asm-x86/trampoline.h b/include/asm-x86/trampoline.h
deleted file mode 100644
index 0406bbd898a9..000000000000
--- a/include/asm-x86/trampoline.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef ASM_X86__TRAMPOLINE_H
-#define ASM_X86__TRAMPOLINE_H
-
-#ifndef __ASSEMBLY__
-
-/*
- * Trampoline 80x86 program as an array.
- */
-extern const unsigned char trampoline_data [];
-extern const unsigned char trampoline_end  [];
-extern unsigned char *trampoline_base;
-
-extern unsigned long init_rsp;
-extern unsigned long initial_code;
-
-#define TRAMPOLINE_BASE 0x6000
-extern unsigned long setup_trampoline(void);
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* ASM_X86__TRAMPOLINE_H */
diff --git a/include/asm-x86/traps.h b/include/asm-x86/traps.h
deleted file mode 100644
index 6c3dc2c65751..000000000000
--- a/include/asm-x86/traps.h
+++ /dev/null
@@ -1,81 +0,0 @@
-#ifndef ASM_X86__TRAPS_H
-#define ASM_X86__TRAPS_H
-
-#include <asm/debugreg.h>
-
-#ifdef CONFIG_X86_32
-#define dotraplinkage
-#else
-#define dotraplinkage asmlinkage
-#endif
-
-asmlinkage void divide_error(void);
-asmlinkage void debug(void);
-asmlinkage void nmi(void);
-asmlinkage void int3(void);
-asmlinkage void overflow(void);
-asmlinkage void bounds(void);
-asmlinkage void invalid_op(void);
-asmlinkage void device_not_available(void);
-#ifdef CONFIG_X86_64
-asmlinkage void double_fault(void);
-#endif
-asmlinkage void coprocessor_segment_overrun(void);
-asmlinkage void invalid_TSS(void);
-asmlinkage void segment_not_present(void);
-asmlinkage void stack_segment(void);
-asmlinkage void general_protection(void);
-asmlinkage void page_fault(void);
-asmlinkage void spurious_interrupt_bug(void);
-asmlinkage void coprocessor_error(void);
-asmlinkage void alignment_check(void);
-#ifdef CONFIG_X86_MCE
-asmlinkage void machine_check(void);
-#endif /* CONFIG_X86_MCE */
-asmlinkage void simd_coprocessor_error(void);
-
-dotraplinkage void do_divide_error(struct pt_regs *, long);
-dotraplinkage void do_debug(struct pt_regs *, long);
-dotraplinkage void do_nmi(struct pt_regs *, long);
-dotraplinkage void do_int3(struct pt_regs *, long);
-dotraplinkage void do_overflow(struct pt_regs *, long);
-dotraplinkage void do_bounds(struct pt_regs *, long);
-dotraplinkage void do_invalid_op(struct pt_regs *, long);
-dotraplinkage void do_device_not_available(struct pt_regs *, long);
-dotraplinkage void do_coprocessor_segment_overrun(struct pt_regs *, long);
-dotraplinkage void do_invalid_TSS(struct pt_regs *, long);
-dotraplinkage void do_segment_not_present(struct pt_regs *, long);
-dotraplinkage void do_stack_segment(struct pt_regs *, long);
-dotraplinkage void do_general_protection(struct pt_regs *, long);
-dotraplinkage void do_page_fault(struct pt_regs *, unsigned long);
-dotraplinkage void do_spurious_interrupt_bug(struct pt_regs *, long);
-dotraplinkage void do_coprocessor_error(struct pt_regs *, long);
-dotraplinkage void do_alignment_check(struct pt_regs *, long);
-#ifdef CONFIG_X86_MCE
-dotraplinkage void do_machine_check(struct pt_regs *, long);
-#endif
-dotraplinkage void do_simd_coprocessor_error(struct pt_regs *, long);
-#ifdef CONFIG_X86_32
-dotraplinkage void do_iret_error(struct pt_regs *, long);
-#endif
-
-static inline int get_si_code(unsigned long condition)
-{
-	if (condition & DR_STEP)
-		return TRAP_TRACE;
-	else if (condition & (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3))
-		return TRAP_HWBKPT;
-	else
-		return TRAP_BRKPT;
-}
-
-extern int panic_on_unrecovered_nmi;
-extern int kstack_depth_to_print;
-
-#ifdef CONFIG_X86_32
-void math_error(void __user *);
-unsigned long patch_espfix_desc(unsigned long, unsigned long);
-asmlinkage void math_emulate(long);
-#endif
-
-#endif /* ASM_X86__TRAPS_H */
diff --git a/include/asm-x86/tsc.h b/include/asm-x86/tsc.h
deleted file mode 100644
index ad0f5c41e78c..000000000000
--- a/include/asm-x86/tsc.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * x86 TSC related functions
- */
-#ifndef ASM_X86__TSC_H
-#define ASM_X86__TSC_H
-
-#include <asm/processor.h>
-
-#define NS_SCALE	10 /* 2^10, carefully chosen */
-#define US_SCALE	32 /* 2^32, arbitralrily chosen */
-
-/*
- * Standard way to access the cycle counter.
- */
-typedef unsigned long long cycles_t;
-
-extern unsigned int cpu_khz;
-extern unsigned int tsc_khz;
-
-extern void disable_TSC(void);
-
-static inline cycles_t get_cycles(void)
-{
-	unsigned long long ret = 0;
-
-#ifndef CONFIG_X86_TSC
-	if (!cpu_has_tsc)
-		return 0;
-#endif
-	rdtscll(ret);
-
-	return ret;
-}
-
-static __always_inline cycles_t vget_cycles(void)
-{
-	/*
-	 * We only do VDSOs on TSC capable CPUs, so this shouldnt
-	 * access boot_cpu_data (which is not VDSO-safe):
-	 */
-#ifndef CONFIG_X86_TSC
-	if (!cpu_has_tsc)
-		return 0;
-#endif
-	return (cycles_t)__native_read_tsc();
-}
-
-extern void tsc_init(void);
-extern void mark_tsc_unstable(char *reason);
-extern int unsynchronized_tsc(void);
-int check_tsc_unstable(void);
-
-/*
- * Boot-time check whether the TSCs are synchronized across
- * all CPUs/cores:
- */
-extern void check_tsc_sync_source(int cpu);
-extern void check_tsc_sync_target(void);
-
-extern int notsc_setup(char *);
-
-#endif /* ASM_X86__TSC_H */
diff --git a/include/asm-x86/types.h b/include/asm-x86/types.h
deleted file mode 100644
index e78b52e17444..000000000000
--- a/include/asm-x86/types.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef ASM_X86__TYPES_H
-#define ASM_X86__TYPES_H
-
-#include <asm-generic/int-ll64.h>
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned short umode_t;
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-#ifdef CONFIG_X86_32
-# define BITS_PER_LONG 32
-#else
-# define BITS_PER_LONG 64
-#endif
-
-#ifndef __ASSEMBLY__
-
-typedef u64 dma64_addr_t;
-#if defined(CONFIG_X86_64) || defined(CONFIG_HIGHMEM64G)
-/* DMA addresses come in 32-bit and 64-bit flavours. */
-typedef u64 dma_addr_t;
-#else
-typedef u32 dma_addr_t;
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL__ */
-
-#endif /* ASM_X86__TYPES_H */
diff --git a/include/asm-x86/uaccess.h b/include/asm-x86/uaccess.h
deleted file mode 100644
index 48ebc0ad40ec..000000000000
--- a/include/asm-x86/uaccess.h
+++ /dev/null
@@ -1,454 +0,0 @@
-#ifndef ASM_X86__UACCESS_H
-#define ASM_X86__UACCESS_H
-/*
- * User space memory access functions
- */
-#include <linux/errno.h>
-#include <linux/compiler.h>
-#include <linux/thread_info.h>
-#include <linux/prefetch.h>
-#include <linux/string.h>
-#include <asm/asm.h>
-#include <asm/page.h>
-
-#define VERIFY_READ 0
-#define VERIFY_WRITE 1
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not.  If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- *
- * For historical reasons, these macros are grossly misnamed.
- */
-
-#define MAKE_MM_SEG(s)	((mm_segment_t) { (s) })
-
-#define KERNEL_DS	MAKE_MM_SEG(-1UL)
-#define USER_DS		MAKE_MM_SEG(PAGE_OFFSET)
-
-#define get_ds()	(KERNEL_DS)
-#define get_fs()	(current_thread_info()->addr_limit)
-#define set_fs(x)	(current_thread_info()->addr_limit = (x))
-
-#define segment_eq(a, b)	((a).seg == (b).seg)
-
-#define __addr_ok(addr)					\
-	((unsigned long __force)(addr) <		\
-	 (current_thread_info()->addr_limit.seg))
-
-/*
- * Test whether a block of memory is a valid user space address.
- * Returns 0 if the range is valid, nonzero otherwise.
- *
- * This is equivalent to the following test:
- * (u33)addr + (u33)size >= (u33)current->addr_limit.seg (u65 for x86_64)
- *
- * This needs 33-bit (65-bit for x86_64) arithmetic. We have a carry...
- */
-
-#define __range_not_ok(addr, size)					\
-({									\
-	unsigned long flag, roksum;					\
-	__chk_user_ptr(addr);						\
-	asm("add %3,%1 ; sbb %0,%0 ; cmp %1,%4 ; sbb $0,%0"		\
-	    : "=&r" (flag), "=r" (roksum)				\
-	    : "1" (addr), "g" ((long)(size)),				\
-	      "rm" (current_thread_info()->addr_limit.seg));		\
-	flag;								\
-})
-
-/**
- * access_ok: - Checks if a user space pointer is valid
- * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE.  Note that
- *        %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe
- *        to write to a block, it is always safe to read from it.
- * @addr: User space pointer to start of block to check
- * @size: Size of block to check
- *
- * Context: User context only.  This function may sleep.
- *
- * Checks if a pointer to a block of memory in user space is valid.
- *
- * Returns true (nonzero) if the memory block may be valid, false (zero)
- * if it is definitely invalid.
- *
- * Note that, depending on architecture, this function probably just
- * checks that the pointer is in the user space range - after calling
- * this function, memory access functions may still return -EFAULT.
- */
-#define access_ok(type, addr, size) (likely(__range_not_ok(addr, size) == 0))
-
-/*
- * The exception table consists of pairs of addresses: the first is the
- * address of an instruction that is allowed to fault, and the second is
- * the address at which the program should continue.  No registers are
- * modified, so it is entirely up to the continuation code to figure out
- * what to do.
- *
- * All the routines below use bits of fixup code that are out of line
- * with the main instruction path.  This means when everything is well,
- * we don't even have to jump over them.  Further, they do not intrude
- * on our cache or tlb entries.
- */
-
-struct exception_table_entry {
-	unsigned long insn, fixup;
-};
-
-extern int fixup_exception(struct pt_regs *regs);
-
-/*
- * These are the main single-value transfer routines.  They automatically
- * use the right size if we just have the right pointer type.
- *
- * This gets kind of ugly. We want to return _two_ values in "get_user()"
- * and yet we don't want to do any pointers, because that is too much
- * of a performance impact. Thus we have a few rather ugly macros here,
- * and hide all the ugliness from the user.
- *
- * The "__xxx" versions of the user access functions are versions that
- * do not verify the address space, that must have been done previously
- * with a separate "access_ok()" call (this is used when we do multiple
- * accesses to the same area of user memory).
- */
-
-extern int __get_user_1(void);
-extern int __get_user_2(void);
-extern int __get_user_4(void);
-extern int __get_user_8(void);
-extern int __get_user_bad(void);
-
-#define __get_user_x(size, ret, x, ptr)		      \
-	asm volatile("call __get_user_" #size	      \
-		     : "=a" (ret),"=d" (x)	      \
-		     : "0" (ptr))		      \
-
-/* Careful: we have to cast the result to the type of the pointer
- * for sign reasons */
-
-/**
- * get_user: - Get a simple variable from user space.
- * @x:   Variable to store result.
- * @ptr: Source address, in user space.
- *
- * Context: User context only.  This function may sleep.
- *
- * This macro copies a single simple variable from user space to kernel
- * space.  It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and the result of
- * dereferencing @ptr must be assignable to @x without a cast.
- *
- * Returns zero on success, or -EFAULT on error.
- * On error, the variable @x is set to zero.
- */
-#ifdef CONFIG_X86_32
-#define __get_user_8(__ret_gu, __val_gu, ptr)				\
-		__get_user_x(X, __ret_gu, __val_gu, ptr)
-#else
-#define __get_user_8(__ret_gu, __val_gu, ptr)				\
-		__get_user_x(8, __ret_gu, __val_gu, ptr)
-#endif
-
-#define get_user(x, ptr)						\
-({									\
-	int __ret_gu;							\
-	unsigned long __val_gu;						\
-	__chk_user_ptr(ptr);						\
-	switch (sizeof(*(ptr))) {					\
-	case 1:								\
-		__get_user_x(1, __ret_gu, __val_gu, ptr);		\
-		break;							\
-	case 2:								\
-		__get_user_x(2, __ret_gu, __val_gu, ptr);		\
-		break;							\
-	case 4:								\
-		__get_user_x(4, __ret_gu, __val_gu, ptr);		\
-		break;							\
-	case 8:								\
-		__get_user_8(__ret_gu, __val_gu, ptr);			\
-		break;							\
-	default:							\
-		__get_user_x(X, __ret_gu, __val_gu, ptr);		\
-		break;							\
-	}								\
-	(x) = (__typeof__(*(ptr)))__val_gu;				\
-	__ret_gu;							\
-})
-
-#define __put_user_x(size, x, ptr, __ret_pu)			\
-	asm volatile("call __put_user_" #size : "=a" (__ret_pu)	\
-		     :"0" ((typeof(*(ptr)))(x)), "c" (ptr) : "ebx")
-
-
-
-#ifdef CONFIG_X86_32
-#define __put_user_u64(x, addr, err)					\
-	asm volatile("1:	movl %%eax,0(%2)\n"			\
-		     "2:	movl %%edx,4(%2)\n"			\
-		     "3:\n"						\
-		     ".section .fixup,\"ax\"\n"				\
-		     "4:	movl %3,%0\n"				\
-		     "	jmp 3b\n"					\
-		     ".previous\n"					\
-		     _ASM_EXTABLE(1b, 4b)				\
-		     _ASM_EXTABLE(2b, 4b)				\
-		     : "=r" (err)					\
-		     : "A" (x), "r" (addr), "i" (-EFAULT), "0" (err))
-
-#define __put_user_x8(x, ptr, __ret_pu)				\
-	asm volatile("call __put_user_8" : "=a" (__ret_pu)	\
-		     : "A" ((typeof(*(ptr)))(x)), "c" (ptr) : "ebx")
-#else
-#define __put_user_u64(x, ptr, retval) \
-	__put_user_asm(x, ptr, retval, "q", "", "Zr", -EFAULT)
-#define __put_user_x8(x, ptr, __ret_pu) __put_user_x(8, x, ptr, __ret_pu)
-#endif
-
-extern void __put_user_bad(void);
-
-/*
- * Strange magic calling convention: pointer in %ecx,
- * value in %eax(:%edx), return value in %eax. clobbers %rbx
- */
-extern void __put_user_1(void);
-extern void __put_user_2(void);
-extern void __put_user_4(void);
-extern void __put_user_8(void);
-
-#ifdef CONFIG_X86_WP_WORKS_OK
-
-/**
- * put_user: - Write a simple value into user space.
- * @x:   Value to copy to user space.
- * @ptr: Destination address, in user space.
- *
- * Context: User context only.  This function may sleep.
- *
- * This macro copies a single simple value from kernel space to user
- * space.  It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and @x must be assignable
- * to the result of dereferencing @ptr.
- *
- * Returns zero on success, or -EFAULT on error.
- */
-#define put_user(x, ptr)					\
-({								\
-	int __ret_pu;						\
-	__typeof__(*(ptr)) __pu_val;				\
-	__chk_user_ptr(ptr);					\
-	__pu_val = x;						\
-	switch (sizeof(*(ptr))) {				\
-	case 1:							\
-		__put_user_x(1, __pu_val, ptr, __ret_pu);	\
-		break;						\
-	case 2:							\
-		__put_user_x(2, __pu_val, ptr, __ret_pu);	\
-		break;						\
-	case 4:							\
-		__put_user_x(4, __pu_val, ptr, __ret_pu);	\
-		break;						\
-	case 8:							\
-		__put_user_x8(__pu_val, ptr, __ret_pu);		\
-		break;						\
-	default:						\
-		__put_user_x(X, __pu_val, ptr, __ret_pu);	\
-		break;						\
-	}							\
-	__ret_pu;						\
-})
-
-#define __put_user_size(x, ptr, size, retval, errret)			\
-do {									\
-	retval = 0;							\
-	__chk_user_ptr(ptr);						\
-	switch (size) {							\
-	case 1:								\
-		__put_user_asm(x, ptr, retval, "b", "b", "iq", errret);	\
-		break;							\
-	case 2:								\
-		__put_user_asm(x, ptr, retval, "w", "w", "ir", errret);	\
-		break;							\
-	case 4:								\
-		__put_user_asm(x, ptr, retval, "l", "k",  "ir", errret);\
-		break;							\
-	case 8:								\
-		__put_user_u64((__typeof__(*ptr))(x), ptr, retval);	\
-		break;							\
-	default:							\
-		__put_user_bad();					\
-	}								\
-} while (0)
-
-#else
-
-#define __put_user_size(x, ptr, size, retval, errret)			\
-do {									\
-	__typeof__(*(ptr))__pus_tmp = x;				\
-	retval = 0;							\
-									\
-	if (unlikely(__copy_to_user_ll(ptr, &__pus_tmp, size) != 0))	\
-		retval = errret;					\
-} while (0)
-
-#define put_user(x, ptr)					\
-({								\
-	int __ret_pu;						\
-	__typeof__(*(ptr))__pus_tmp = x;			\
-	__ret_pu = 0;						\
-	if (unlikely(__copy_to_user_ll(ptr, &__pus_tmp,		\
-				       sizeof(*(ptr))) != 0))	\
-		__ret_pu = -EFAULT;				\
-	__ret_pu;						\
-})
-#endif
-
-#ifdef CONFIG_X86_32
-#define __get_user_asm_u64(x, ptr, retval, errret)	(x) = __get_user_bad()
-#else
-#define __get_user_asm_u64(x, ptr, retval, errret) \
-	 __get_user_asm(x, ptr, retval, "q", "", "=r", errret)
-#endif
-
-#define __get_user_size(x, ptr, size, retval, errret)			\
-do {									\
-	retval = 0;							\
-	__chk_user_ptr(ptr);						\
-	switch (size) {							\
-	case 1:								\
-		__get_user_asm(x, ptr, retval, "b", "b", "=q", errret);	\
-		break;							\
-	case 2:								\
-		__get_user_asm(x, ptr, retval, "w", "w", "=r", errret);	\
-		break;							\
-	case 4:								\
-		__get_user_asm(x, ptr, retval, "l", "k", "=r", errret);	\
-		break;							\
-	case 8:								\
-		__get_user_asm_u64(x, ptr, retval, errret);		\
-		break;							\
-	default:							\
-		(x) = __get_user_bad();					\
-	}								\
-} while (0)
-
-#define __get_user_asm(x, addr, err, itype, rtype, ltype, errret)	\
-	asm volatile("1:	mov"itype" %2,%"rtype"1\n"		\
-		     "2:\n"						\
-		     ".section .fixup,\"ax\"\n"				\
-		     "3:	mov %3,%0\n"				\
-		     "	xor"itype" %"rtype"1,%"rtype"1\n"		\
-		     "	jmp 2b\n"					\
-		     ".previous\n"					\
-		     _ASM_EXTABLE(1b, 3b)				\
-		     : "=r" (err), ltype(x)				\
-		     : "m" (__m(addr)), "i" (errret), "0" (err))
-
-#define __put_user_nocheck(x, ptr, size)			\
-({								\
-	long __pu_err;						\
-	__put_user_size((x), (ptr), (size), __pu_err, -EFAULT);	\
-	__pu_err;						\
-})
-
-#define __get_user_nocheck(x, ptr, size)				\
-({									\
-	long __gu_err;							\
-	unsigned long __gu_val;						\
-	__get_user_size(__gu_val, (ptr), (size), __gu_err, -EFAULT);	\
-	(x) = (__force __typeof__(*(ptr)))__gu_val;			\
-	__gu_err;							\
-})
-
-/* FIXME: this hack is definitely wrong -AK */
-struct __large_struct { unsigned long buf[100]; };
-#define __m(x) (*(struct __large_struct __user *)(x))
-
-/*
- * Tell gcc we read from memory instead of writing: this is because
- * we do not write to any memory gcc knows about, so there are no
- * aliasing issues.
- */
-#define __put_user_asm(x, addr, err, itype, rtype, ltype, errret)	\
-	asm volatile("1:	mov"itype" %"rtype"1,%2\n"		\
-		     "2:\n"						\
-		     ".section .fixup,\"ax\"\n"				\
-		     "3:	mov %3,%0\n"				\
-		     "	jmp 2b\n"					\
-		     ".previous\n"					\
-		     _ASM_EXTABLE(1b, 3b)				\
-		     : "=r"(err)					\
-		     : ltype(x), "m" (__m(addr)), "i" (errret), "0" (err))
-/**
- * __get_user: - Get a simple variable from user space, with less checking.
- * @x:   Variable to store result.
- * @ptr: Source address, in user space.
- *
- * Context: User context only.  This function may sleep.
- *
- * This macro copies a single simple variable from user space to kernel
- * space.  It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and the result of
- * dereferencing @ptr must be assignable to @x without a cast.
- *
- * Caller must check the pointer with access_ok() before calling this
- * function.
- *
- * Returns zero on success, or -EFAULT on error.
- * On error, the variable @x is set to zero.
- */
-
-#define __get_user(x, ptr)						\
-	__get_user_nocheck((x), (ptr), sizeof(*(ptr)))
-/**
- * __put_user: - Write a simple value into user space, with less checking.
- * @x:   Value to copy to user space.
- * @ptr: Destination address, in user space.
- *
- * Context: User context only.  This function may sleep.
- *
- * This macro copies a single simple value from kernel space to user
- * space.  It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and @x must be assignable
- * to the result of dereferencing @ptr.
- *
- * Caller must check the pointer with access_ok() before calling this
- * function.
- *
- * Returns zero on success, or -EFAULT on error.
- */
-
-#define __put_user(x, ptr)						\
-	__put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
-
-#define __get_user_unaligned __get_user
-#define __put_user_unaligned __put_user
-
-/*
- * movsl can be slow when source and dest are not both 8-byte aligned
- */
-#ifdef CONFIG_X86_INTEL_USERCOPY
-extern struct movsl_mask {
-	int mask;
-} ____cacheline_aligned_in_smp movsl_mask;
-#endif
-
-#define ARCH_HAS_NOCACHE_UACCESS 1
-
-#ifdef CONFIG_X86_32
-# include "uaccess_32.h"
-#else
-# define ARCH_HAS_SEARCH_EXTABLE
-# include "uaccess_64.h"
-#endif
-
-#endif /* ASM_X86__UACCESS_H */
-
diff --git a/include/asm-x86/uaccess_32.h b/include/asm-x86/uaccess_32.h
deleted file mode 100644
index 6b5b57d9c6d1..000000000000
--- a/include/asm-x86/uaccess_32.h
+++ /dev/null
@@ -1,218 +0,0 @@
-#ifndef ASM_X86__UACCESS_32_H
-#define ASM_X86__UACCESS_32_H
-
-/*
- * User space memory access functions
- */
-#include <linux/errno.h>
-#include <linux/thread_info.h>
-#include <linux/prefetch.h>
-#include <linux/string.h>
-#include <asm/asm.h>
-#include <asm/page.h>
-
-unsigned long __must_check __copy_to_user_ll
-		(void __user *to, const void *from, unsigned long n);
-unsigned long __must_check __copy_from_user_ll
-		(void *to, const void __user *from, unsigned long n);
-unsigned long __must_check __copy_from_user_ll_nozero
-		(void *to, const void __user *from, unsigned long n);
-unsigned long __must_check __copy_from_user_ll_nocache
-		(void *to, const void __user *from, unsigned long n);
-unsigned long __must_check __copy_from_user_ll_nocache_nozero
-		(void *to, const void __user *from, unsigned long n);
-
-/**
- * __copy_to_user_inatomic: - Copy a block of data into user space, with less checking.
- * @to:   Destination address, in user space.
- * @from: Source address, in kernel space.
- * @n:    Number of bytes to copy.
- *
- * Context: User context only.
- *
- * Copy data from kernel space to user space.  Caller must check
- * the specified block with access_ok() before calling this function.
- * The caller should also make sure he pins the user space address
- * so that the we don't result in page fault and sleep.
- *
- * Here we special-case 1, 2 and 4-byte copy_*_user invocations.  On a fault
- * we return the initial request size (1, 2 or 4), as copy_*_user should do.
- * If a store crosses a page boundary and gets a fault, the x86 will not write
- * anything, so this is accurate.
- */
-
-static __always_inline unsigned long __must_check
-__copy_to_user_inatomic(void __user *to, const void *from, unsigned long n)
-{
-	if (__builtin_constant_p(n)) {
-		unsigned long ret;
-
-		switch (n) {
-		case 1:
-			__put_user_size(*(u8 *)from, (u8 __user *)to,
-					1, ret, 1);
-			return ret;
-		case 2:
-			__put_user_size(*(u16 *)from, (u16 __user *)to,
-					2, ret, 2);
-			return ret;
-		case 4:
-			__put_user_size(*(u32 *)from, (u32 __user *)to,
-					4, ret, 4);
-			return ret;
-		}
-	}
-	return __copy_to_user_ll(to, from, n);
-}
-
-/**
- * __copy_to_user: - Copy a block of data into user space, with less checking.
- * @to:   Destination address, in user space.
- * @from: Source address, in kernel space.
- * @n:    Number of bytes to copy.
- *
- * Context: User context only.  This function may sleep.
- *
- * Copy data from kernel space to user space.  Caller must check
- * the specified block with access_ok() before calling this function.
- *
- * Returns number of bytes that could not be copied.
- * On success, this will be zero.
- */
-static __always_inline unsigned long __must_check
-__copy_to_user(void __user *to, const void *from, unsigned long n)
-{
-       might_sleep();
-       return __copy_to_user_inatomic(to, from, n);
-}
-
-static __always_inline unsigned long
-__copy_from_user_inatomic(void *to, const void __user *from, unsigned long n)
-{
-	/* Avoid zeroing the tail if the copy fails..
-	 * If 'n' is constant and 1, 2, or 4, we do still zero on a failure,
-	 * but as the zeroing behaviour is only significant when n is not
-	 * constant, that shouldn't be a problem.
-	 */
-	if (__builtin_constant_p(n)) {
-		unsigned long ret;
-
-		switch (n) {
-		case 1:
-			__get_user_size(*(u8 *)to, from, 1, ret, 1);
-			return ret;
-		case 2:
-			__get_user_size(*(u16 *)to, from, 2, ret, 2);
-			return ret;
-		case 4:
-			__get_user_size(*(u32 *)to, from, 4, ret, 4);
-			return ret;
-		}
-	}
-	return __copy_from_user_ll_nozero(to, from, n);
-}
-
-/**
- * __copy_from_user: - Copy a block of data from user space, with less checking.
- * @to:   Destination address, in kernel space.
- * @from: Source address, in user space.
- * @n:    Number of bytes to copy.
- *
- * Context: User context only.  This function may sleep.
- *
- * Copy data from user space to kernel space.  Caller must check
- * the specified block with access_ok() before calling this function.
- *
- * Returns number of bytes that could not be copied.
- * On success, this will be zero.
- *
- * If some data could not be copied, this function will pad the copied
- * data to the requested size using zero bytes.
- *
- * An alternate version - __copy_from_user_inatomic() - may be called from
- * atomic context and will fail rather than sleep.  In this case the
- * uncopied bytes will *NOT* be padded with zeros.  See fs/filemap.h
- * for explanation of why this is needed.
- */
-static __always_inline unsigned long
-__copy_from_user(void *to, const void __user *from, unsigned long n)
-{
-	might_sleep();
-	if (__builtin_constant_p(n)) {
-		unsigned long ret;
-
-		switch (n) {
-		case 1:
-			__get_user_size(*(u8 *)to, from, 1, ret, 1);
-			return ret;
-		case 2:
-			__get_user_size(*(u16 *)to, from, 2, ret, 2);
-			return ret;
-		case 4:
-			__get_user_size(*(u32 *)to, from, 4, ret, 4);
-			return ret;
-		}
-	}
-	return __copy_from_user_ll(to, from, n);
-}
-
-static __always_inline unsigned long __copy_from_user_nocache(void *to,
-				const void __user *from, unsigned long n)
-{
-	might_sleep();
-	if (__builtin_constant_p(n)) {
-		unsigned long ret;
-
-		switch (n) {
-		case 1:
-			__get_user_size(*(u8 *)to, from, 1, ret, 1);
-			return ret;
-		case 2:
-			__get_user_size(*(u16 *)to, from, 2, ret, 2);
-			return ret;
-		case 4:
-			__get_user_size(*(u32 *)to, from, 4, ret, 4);
-			return ret;
-		}
-	}
-	return __copy_from_user_ll_nocache(to, from, n);
-}
-
-static __always_inline unsigned long
-__copy_from_user_inatomic_nocache(void *to, const void __user *from,
-				  unsigned long n)
-{
-       return __copy_from_user_ll_nocache_nozero(to, from, n);
-}
-
-unsigned long __must_check copy_to_user(void __user *to,
-					const void *from, unsigned long n);
-unsigned long __must_check copy_from_user(void *to,
-					  const void __user *from,
-					  unsigned long n);
-long __must_check strncpy_from_user(char *dst, const char __user *src,
-				    long count);
-long __must_check __strncpy_from_user(char *dst,
-				      const char __user *src, long count);
-
-/**
- * strlen_user: - Get the size of a string in user space.
- * @str: The string to measure.
- *
- * Context: User context only.  This function may sleep.
- *
- * Get the size of a NUL-terminated string in user space.
- *
- * Returns the size of the string INCLUDING the terminating NUL.
- * On exception, returns 0.
- *
- * If there is a limit on the length of a valid string, you may wish to
- * consider using strnlen_user() instead.
- */
-#define strlen_user(str) strnlen_user(str, LONG_MAX)
-
-long strnlen_user(const char __user *str, long n);
-unsigned long __must_check clear_user(void __user *mem, unsigned long len);
-unsigned long __must_check __clear_user(void __user *mem, unsigned long len);
-
-#endif /* ASM_X86__UACCESS_32_H */
diff --git a/include/asm-x86/uaccess_64.h b/include/asm-x86/uaccess_64.h
deleted file mode 100644
index c96c1f5d07a2..000000000000
--- a/include/asm-x86/uaccess_64.h
+++ /dev/null
@@ -1,202 +0,0 @@
-#ifndef ASM_X86__UACCESS_64_H
-#define ASM_X86__UACCESS_64_H
-
-/*
- * User space memory access functions
- */
-#include <linux/compiler.h>
-#include <linux/errno.h>
-#include <linux/prefetch.h>
-#include <linux/lockdep.h>
-#include <asm/page.h>
-
-/*
- * Copy To/From Userspace
- */
-
-/* Handles exceptions in both to and from, but doesn't do access_ok */
-__must_check unsigned long
-copy_user_generic(void *to, const void *from, unsigned len);
-
-__must_check unsigned long
-copy_to_user(void __user *to, const void *from, unsigned len);
-__must_check unsigned long
-copy_from_user(void *to, const void __user *from, unsigned len);
-__must_check unsigned long
-copy_in_user(void __user *to, const void __user *from, unsigned len);
-
-static __always_inline __must_check
-int __copy_from_user(void *dst, const void __user *src, unsigned size)
-{
-	int ret = 0;
-	if (!__builtin_constant_p(size))
-		return copy_user_generic(dst, (__force void *)src, size);
-	switch (size) {
-	case 1:__get_user_asm(*(u8 *)dst, (u8 __user *)src,
-			      ret, "b", "b", "=q", 1);
-		return ret;
-	case 2:__get_user_asm(*(u16 *)dst, (u16 __user *)src,
-			      ret, "w", "w", "=r", 2);
-		return ret;
-	case 4:__get_user_asm(*(u32 *)dst, (u32 __user *)src,
-			      ret, "l", "k", "=r", 4);
-		return ret;
-	case 8:__get_user_asm(*(u64 *)dst, (u64 __user *)src,
-			      ret, "q", "", "=r", 8);
-		return ret;
-	case 10:
-		__get_user_asm(*(u64 *)dst, (u64 __user *)src,
-			       ret, "q", "", "=r", 16);
-		if (unlikely(ret))
-			return ret;
-		__get_user_asm(*(u16 *)(8 + (char *)dst),
-			       (u16 __user *)(8 + (char __user *)src),
-			       ret, "w", "w", "=r", 2);
-		return ret;
-	case 16:
-		__get_user_asm(*(u64 *)dst, (u64 __user *)src,
-			       ret, "q", "", "=r", 16);
-		if (unlikely(ret))
-			return ret;
-		__get_user_asm(*(u64 *)(8 + (char *)dst),
-			       (u64 __user *)(8 + (char __user *)src),
-			       ret, "q", "", "=r", 8);
-		return ret;
-	default:
-		return copy_user_generic(dst, (__force void *)src, size);
-	}
-}
-
-static __always_inline __must_check
-int __copy_to_user(void __user *dst, const void *src, unsigned size)
-{
-	int ret = 0;
-	if (!__builtin_constant_p(size))
-		return copy_user_generic((__force void *)dst, src, size);
-	switch (size) {
-	case 1:__put_user_asm(*(u8 *)src, (u8 __user *)dst,
-			      ret, "b", "b", "iq", 1);
-		return ret;
-	case 2:__put_user_asm(*(u16 *)src, (u16 __user *)dst,
-			      ret, "w", "w", "ir", 2);
-		return ret;
-	case 4:__put_user_asm(*(u32 *)src, (u32 __user *)dst,
-			      ret, "l", "k", "ir", 4);
-		return ret;
-	case 8:__put_user_asm(*(u64 *)src, (u64 __user *)dst,
-			      ret, "q", "", "ir", 8);
-		return ret;
-	case 10:
-		__put_user_asm(*(u64 *)src, (u64 __user *)dst,
-			       ret, "q", "", "ir", 10);
-		if (unlikely(ret))
-			return ret;
-		asm("":::"memory");
-		__put_user_asm(4[(u16 *)src], 4 + (u16 __user *)dst,
-			       ret, "w", "w", "ir", 2);
-		return ret;
-	case 16:
-		__put_user_asm(*(u64 *)src, (u64 __user *)dst,
-			       ret, "q", "", "ir", 16);
-		if (unlikely(ret))
-			return ret;
-		asm("":::"memory");
-		__put_user_asm(1[(u64 *)src], 1 + (u64 __user *)dst,
-			       ret, "q", "", "ir", 8);
-		return ret;
-	default:
-		return copy_user_generic((__force void *)dst, src, size);
-	}
-}
-
-static __always_inline __must_check
-int __copy_in_user(void __user *dst, const void __user *src, unsigned size)
-{
-	int ret = 0;
-	if (!__builtin_constant_p(size))
-		return copy_user_generic((__force void *)dst,
-					 (__force void *)src, size);
-	switch (size) {
-	case 1: {
-		u8 tmp;
-		__get_user_asm(tmp, (u8 __user *)src,
-			       ret, "b", "b", "=q", 1);
-		if (likely(!ret))
-			__put_user_asm(tmp, (u8 __user *)dst,
-				       ret, "b", "b", "iq", 1);
-		return ret;
-	}
-	case 2: {
-		u16 tmp;
-		__get_user_asm(tmp, (u16 __user *)src,
-			       ret, "w", "w", "=r", 2);
-		if (likely(!ret))
-			__put_user_asm(tmp, (u16 __user *)dst,
-				       ret, "w", "w", "ir", 2);
-		return ret;
-	}
-
-	case 4: {
-		u32 tmp;
-		__get_user_asm(tmp, (u32 __user *)src,
-			       ret, "l", "k", "=r", 4);
-		if (likely(!ret))
-			__put_user_asm(tmp, (u32 __user *)dst,
-				       ret, "l", "k", "ir", 4);
-		return ret;
-	}
-	case 8: {
-		u64 tmp;
-		__get_user_asm(tmp, (u64 __user *)src,
-			       ret, "q", "", "=r", 8);
-		if (likely(!ret))
-			__put_user_asm(tmp, (u64 __user *)dst,
-				       ret, "q", "", "ir", 8);
-		return ret;
-	}
-	default:
-		return copy_user_generic((__force void *)dst,
-					 (__force void *)src, size);
-	}
-}
-
-__must_check long
-strncpy_from_user(char *dst, const char __user *src, long count);
-__must_check long
-__strncpy_from_user(char *dst, const char __user *src, long count);
-__must_check long strnlen_user(const char __user *str, long n);
-__must_check long __strnlen_user(const char __user *str, long n);
-__must_check long strlen_user(const char __user *str);
-__must_check unsigned long clear_user(void __user *mem, unsigned long len);
-__must_check unsigned long __clear_user(void __user *mem, unsigned long len);
-
-__must_check long __copy_from_user_inatomic(void *dst, const void __user *src,
-					    unsigned size);
-
-static __must_check __always_inline int
-__copy_to_user_inatomic(void __user *dst, const void *src, unsigned size)
-{
-	return copy_user_generic((__force void *)dst, src, size);
-}
-
-extern long __copy_user_nocache(void *dst, const void __user *src,
-				unsigned size, int zerorest);
-
-static inline int __copy_from_user_nocache(void *dst, const void __user *src,
-					   unsigned size)
-{
-	might_sleep();
-	return __copy_user_nocache(dst, src, size, 1);
-}
-
-static inline int __copy_from_user_inatomic_nocache(void *dst,
-						    const void __user *src,
-						    unsigned size)
-{
-	return __copy_user_nocache(dst, src, size, 0);
-}
-
-unsigned long
-copy_user_handle_tail(char *to, char *from, unsigned len, unsigned zerorest);
-
-#endif /* ASM_X86__UACCESS_64_H */
diff --git a/include/asm-x86/ucontext.h b/include/asm-x86/ucontext.h
deleted file mode 100644
index 89eaa5456a7e..000000000000
--- a/include/asm-x86/ucontext.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef ASM_X86__UCONTEXT_H
-#define ASM_X86__UCONTEXT_H
-
-#define UC_FP_XSTATE	0x1	/* indicates the presence of extended state
-				 * information in the memory layout pointed
-				 * by the fpstate pointer in the ucontext's
-				 * sigcontext struct (uc_mcontext).
-				 */
-
-struct ucontext {
-	unsigned long	  uc_flags;
-	struct ucontext  *uc_link;
-	stack_t		  uc_stack;
-	struct sigcontext uc_mcontext;
-	sigset_t	  uc_sigmask;	/* mask last for extensibility */
-};
-
-#endif /* ASM_X86__UCONTEXT_H */
diff --git a/include/asm-x86/unaligned.h b/include/asm-x86/unaligned.h
deleted file mode 100644
index 59dcdec37160..000000000000
--- a/include/asm-x86/unaligned.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef ASM_X86__UNALIGNED_H
-#define ASM_X86__UNALIGNED_H
-
-/*
- * The x86 can do unaligned accesses itself.
- */
-
-#include <linux/unaligned/access_ok.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned __get_unaligned_le
-#define put_unaligned __put_unaligned_le
-
-#endif /* ASM_X86__UNALIGNED_H */
diff --git a/include/asm-x86/unistd.h b/include/asm-x86/unistd.h
deleted file mode 100644
index 2a58ed3e51d8..000000000000
--- a/include/asm-x86/unistd.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifdef __KERNEL__
-# ifdef CONFIG_X86_32
-#  include "unistd_32.h"
-# else
-#  include "unistd_64.h"
-# endif
-#else
-# ifdef __i386__
-#  include "unistd_32.h"
-# else
-#  include "unistd_64.h"
-# endif
-#endif
diff --git a/include/asm-x86/unistd_32.h b/include/asm-x86/unistd_32.h
deleted file mode 100644
index 017f4a87c913..000000000000
--- a/include/asm-x86/unistd_32.h
+++ /dev/null
@@ -1,379 +0,0 @@
-#ifndef ASM_X86__UNISTD_32_H
-#define ASM_X86__UNISTD_32_H
-
-/*
- * This file contains the system call numbers.
- */
-
-#define __NR_restart_syscall      0
-#define __NR_exit		  1
-#define __NR_fork		  2
-#define __NR_read		  3
-#define __NR_write		  4
-#define __NR_open		  5
-#define __NR_close		  6
-#define __NR_waitpid		  7
-#define __NR_creat		  8
-#define __NR_link		  9
-#define __NR_unlink		 10
-#define __NR_execve		 11
-#define __NR_chdir		 12
-#define __NR_time		 13
-#define __NR_mknod		 14
-#define __NR_chmod		 15
-#define __NR_lchown		 16
-#define __NR_break		 17
-#define __NR_oldstat		 18
-#define __NR_lseek		 19
-#define __NR_getpid		 20
-#define __NR_mount		 21
-#define __NR_umount		 22
-#define __NR_setuid		 23
-#define __NR_getuid		 24
-#define __NR_stime		 25
-#define __NR_ptrace		 26
-#define __NR_alarm		 27
-#define __NR_oldfstat		 28
-#define __NR_pause		 29
-#define __NR_utime		 30
-#define __NR_stty		 31
-#define __NR_gtty		 32
-#define __NR_access		 33
-#define __NR_nice		 34
-#define __NR_ftime		 35
-#define __NR_sync		 36
-#define __NR_kill		 37
-#define __NR_rename		 38
-#define __NR_mkdir		 39
-#define __NR_rmdir		 40
-#define __NR_dup		 41
-#define __NR_pipe		 42
-#define __NR_times		 43
-#define __NR_prof		 44
-#define __NR_brk		 45
-#define __NR_setgid		 46
-#define __NR_getgid		 47
-#define __NR_signal		 48
-#define __NR_geteuid		 49
-#define __NR_getegid		 50
-#define __NR_acct		 51
-#define __NR_umount2		 52
-#define __NR_lock		 53
-#define __NR_ioctl		 54
-#define __NR_fcntl		 55
-#define __NR_mpx		 56
-#define __NR_setpgid		 57
-#define __NR_ulimit		 58
-#define __NR_oldolduname	 59
-#define __NR_umask		 60
-#define __NR_chroot		 61
-#define __NR_ustat		 62
-#define __NR_dup2		 63
-#define __NR_getppid		 64
-#define __NR_getpgrp		 65
-#define __NR_setsid		 66
-#define __NR_sigaction		 67
-#define __NR_sgetmask		 68
-#define __NR_ssetmask		 69
-#define __NR_setreuid		 70
-#define __NR_setregid		 71
-#define __NR_sigsuspend		 72
-#define __NR_sigpending		 73
-#define __NR_sethostname	 74
-#define __NR_setrlimit		 75
-#define __NR_getrlimit		 76   /* Back compatible 2Gig limited rlimit */
-#define __NR_getrusage		 77
-#define __NR_gettimeofday	 78
-#define __NR_settimeofday	 79
-#define __NR_getgroups		 80
-#define __NR_setgroups		 81
-#define __NR_select		 82
-#define __NR_symlink		 83
-#define __NR_oldlstat		 84
-#define __NR_readlink		 85
-#define __NR_uselib		 86
-#define __NR_swapon		 87
-#define __NR_reboot		 88
-#define __NR_readdir		 89
-#define __NR_mmap		 90
-#define __NR_munmap		 91
-#define __NR_truncate		 92
-#define __NR_ftruncate		 93
-#define __NR_fchmod		 94
-#define __NR_fchown		 95
-#define __NR_getpriority	 96
-#define __NR_setpriority	 97
-#define __NR_profil		 98
-#define __NR_statfs		 99
-#define __NR_fstatfs		100
-#define __NR_ioperm		101
-#define __NR_socketcall		102
-#define __NR_syslog		103
-#define __NR_setitimer		104
-#define __NR_getitimer		105
-#define __NR_stat		106
-#define __NR_lstat		107
-#define __NR_fstat		108
-#define __NR_olduname		109
-#define __NR_iopl		110
-#define __NR_vhangup		111
-#define __NR_idle		112
-#define __NR_vm86old		113
-#define __NR_wait4		114
-#define __NR_swapoff		115
-#define __NR_sysinfo		116
-#define __NR_ipc		117
-#define __NR_fsync		118
-#define __NR_sigreturn		119
-#define __NR_clone		120
-#define __NR_setdomainname	121
-#define __NR_uname		122
-#define __NR_modify_ldt		123
-#define __NR_adjtimex		124
-#define __NR_mprotect		125
-#define __NR_sigprocmask	126
-#define __NR_create_module	127
-#define __NR_init_module	128
-#define __NR_delete_module	129
-#define __NR_get_kernel_syms	130
-#define __NR_quotactl		131
-#define __NR_getpgid		132
-#define __NR_fchdir		133
-#define __NR_bdflush		134
-#define __NR_sysfs		135
-#define __NR_personality	136
-#define __NR_afs_syscall	137 /* Syscall for Andrew File System */
-#define __NR_setfsuid		138
-#define __NR_setfsgid		139
-#define __NR__llseek		140
-#define __NR_getdents		141
-#define __NR__newselect		142
-#define __NR_flock		143
-#define __NR_msync		144
-#define __NR_readv		145
-#define __NR_writev		146
-#define __NR_getsid		147
-#define __NR_fdatasync		148
-#define __NR__sysctl		149
-#define __NR_mlock		150
-#define __NR_munlock		151
-#define __NR_mlockall		152
-#define __NR_munlockall		153
-#define __NR_sched_setparam		154
-#define __NR_sched_getparam		155
-#define __NR_sched_setscheduler		156
-#define __NR_sched_getscheduler		157
-#define __NR_sched_yield		158
-#define __NR_sched_get_priority_max	159
-#define __NR_sched_get_priority_min	160
-#define __NR_sched_rr_get_interval	161
-#define __NR_nanosleep		162
-#define __NR_mremap		163
-#define __NR_setresuid		164
-#define __NR_getresuid		165
-#define __NR_vm86		166
-#define __NR_query_module	167
-#define __NR_poll		168
-#define __NR_nfsservctl		169
-#define __NR_setresgid		170
-#define __NR_getresgid		171
-#define __NR_prctl              172
-#define __NR_rt_sigreturn	173
-#define __NR_rt_sigaction	174
-#define __NR_rt_sigprocmask	175
-#define __NR_rt_sigpending	176
-#define __NR_rt_sigtimedwait	177
-#define __NR_rt_sigqueueinfo	178
-#define __NR_rt_sigsuspend	179
-#define __NR_pread64		180
-#define __NR_pwrite64		181
-#define __NR_chown		182
-#define __NR_getcwd		183
-#define __NR_capget		184
-#define __NR_capset		185
-#define __NR_sigaltstack	186
-#define __NR_sendfile		187
-#define __NR_getpmsg		188	/* some people actually want streams */
-#define __NR_putpmsg		189	/* some people actually want streams */
-#define __NR_vfork		190
-#define __NR_ugetrlimit		191	/* SuS compliant getrlimit */
-#define __NR_mmap2		192
-#define __NR_truncate64		193
-#define __NR_ftruncate64	194
-#define __NR_stat64		195
-#define __NR_lstat64		196
-#define __NR_fstat64		197
-#define __NR_lchown32		198
-#define __NR_getuid32		199
-#define __NR_getgid32		200
-#define __NR_geteuid32		201
-#define __NR_getegid32		202
-#define __NR_setreuid32		203
-#define __NR_setregid32		204
-#define __NR_getgroups32	205
-#define __NR_setgroups32	206
-#define __NR_fchown32		207
-#define __NR_setresuid32	208
-#define __NR_getresuid32	209
-#define __NR_setresgid32	210
-#define __NR_getresgid32	211
-#define __NR_chown32		212
-#define __NR_setuid32		213
-#define __NR_setgid32		214
-#define __NR_setfsuid32		215
-#define __NR_setfsgid32		216
-#define __NR_pivot_root		217
-#define __NR_mincore		218
-#define __NR_madvise		219
-#define __NR_madvise1		219	/* delete when C lib stub is removed */
-#define __NR_getdents64		220
-#define __NR_fcntl64		221
-/* 223 is unused */
-#define __NR_gettid		224
-#define __NR_readahead		225
-#define __NR_setxattr		226
-#define __NR_lsetxattr		227
-#define __NR_fsetxattr		228
-#define __NR_getxattr		229
-#define __NR_lgetxattr		230
-#define __NR_fgetxattr		231
-#define __NR_listxattr		232
-#define __NR_llistxattr		233
-#define __NR_flistxattr		234
-#define __NR_removexattr	235
-#define __NR_lremovexattr	236
-#define __NR_fremovexattr	237
-#define __NR_tkill		238
-#define __NR_sendfile64		239
-#define __NR_futex		240
-#define __NR_sched_setaffinity	241
-#define __NR_sched_getaffinity	242
-#define __NR_set_thread_area	243
-#define __NR_get_thread_area	244
-#define __NR_io_setup		245
-#define __NR_io_destroy		246
-#define __NR_io_getevents	247
-#define __NR_io_submit		248
-#define __NR_io_cancel		249
-#define __NR_fadvise64		250
-/* 251 is available for reuse (was briefly sys_set_zone_reclaim) */
-#define __NR_exit_group		252
-#define __NR_lookup_dcookie	253
-#define __NR_epoll_create	254
-#define __NR_epoll_ctl		255
-#define __NR_epoll_wait		256
-#define __NR_remap_file_pages	257
-#define __NR_set_tid_address	258
-#define __NR_timer_create	259
-#define __NR_timer_settime	(__NR_timer_create+1)
-#define __NR_timer_gettime	(__NR_timer_create+2)
-#define __NR_timer_getoverrun	(__NR_timer_create+3)
-#define __NR_timer_delete	(__NR_timer_create+4)
-#define __NR_clock_settime	(__NR_timer_create+5)
-#define __NR_clock_gettime	(__NR_timer_create+6)
-#define __NR_clock_getres	(__NR_timer_create+7)
-#define __NR_clock_nanosleep	(__NR_timer_create+8)
-#define __NR_statfs64		268
-#define __NR_fstatfs64		269
-#define __NR_tgkill		270
-#define __NR_utimes		271
-#define __NR_fadvise64_64	272
-#define __NR_vserver		273
-#define __NR_mbind		274
-#define __NR_get_mempolicy	275
-#define __NR_set_mempolicy	276
-#define __NR_mq_open 		277
-#define __NR_mq_unlink		(__NR_mq_open+1)
-#define __NR_mq_timedsend	(__NR_mq_open+2)
-#define __NR_mq_timedreceive	(__NR_mq_open+3)
-#define __NR_mq_notify		(__NR_mq_open+4)
-#define __NR_mq_getsetattr	(__NR_mq_open+5)
-#define __NR_kexec_load		283
-#define __NR_waitid		284
-/* #define __NR_sys_setaltroot	285 */
-#define __NR_add_key		286
-#define __NR_request_key	287
-#define __NR_keyctl		288
-#define __NR_ioprio_set		289
-#define __NR_ioprio_get		290
-#define __NR_inotify_init	291
-#define __NR_inotify_add_watch	292
-#define __NR_inotify_rm_watch	293
-#define __NR_migrate_pages	294
-#define __NR_openat		295
-#define __NR_mkdirat		296
-#define __NR_mknodat		297
-#define __NR_fchownat		298
-#define __NR_futimesat		299
-#define __NR_fstatat64		300
-#define __NR_unlinkat		301
-#define __NR_renameat		302
-#define __NR_linkat		303
-#define __NR_symlinkat		304
-#define __NR_readlinkat		305
-#define __NR_fchmodat		306
-#define __NR_faccessat		307
-#define __NR_pselect6		308
-#define __NR_ppoll		309
-#define __NR_unshare		310
-#define __NR_set_robust_list	311
-#define __NR_get_robust_list	312
-#define __NR_splice		313
-#define __NR_sync_file_range	314
-#define __NR_tee		315
-#define __NR_vmsplice		316
-#define __NR_move_pages		317
-#define __NR_getcpu		318
-#define __NR_epoll_pwait	319
-#define __NR_utimensat		320
-#define __NR_signalfd		321
-#define __NR_timerfd_create	322
-#define __NR_eventfd		323
-#define __NR_fallocate		324
-#define __NR_timerfd_settime	325
-#define __NR_timerfd_gettime	326
-#define __NR_signalfd4		327
-#define __NR_eventfd2		328
-#define __NR_epoll_create1	329
-#define __NR_dup3		330
-#define __NR_pipe2		331
-#define __NR_inotify_init1	332
-
-#ifdef __KERNEL__
-
-#define __ARCH_WANT_IPC_PARSE_VERSION
-#define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_OLD_STAT
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SGETMASK
-#define __ARCH_WANT_SYS_SIGNAL
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_OLD_GETRLIMIT
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_SIGPENDING
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_RT_SIGACTION
-#define __ARCH_WANT_SYS_RT_SIGSUSPEND
-
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#ifndef cond_syscall
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-#endif
-
-#endif /* __KERNEL__ */
-#endif /* ASM_X86__UNISTD_32_H */
diff --git a/include/asm-x86/unistd_64.h b/include/asm-x86/unistd_64.h
deleted file mode 100644
index ace83f1f6787..000000000000
--- a/include/asm-x86/unistd_64.h
+++ /dev/null
@@ -1,693 +0,0 @@
-#ifndef ASM_X86__UNISTD_64_H
-#define ASM_X86__UNISTD_64_H
-
-#ifndef __SYSCALL
-#define __SYSCALL(a, b)
-#endif
-
-/*
- * This file contains the system call numbers.
- *
- * Note: holes are not allowed.
- */
-
-/* at least 8 syscall per cacheline */
-#define __NR_read				0
-__SYSCALL(__NR_read, sys_read)
-#define __NR_write				1
-__SYSCALL(__NR_write, sys_write)
-#define __NR_open				2
-__SYSCALL(__NR_open, sys_open)
-#define __NR_close				3
-__SYSCALL(__NR_close, sys_close)
-#define __NR_stat				4
-__SYSCALL(__NR_stat, sys_newstat)
-#define __NR_fstat				5
-__SYSCALL(__NR_fstat, sys_newfstat)
-#define __NR_lstat				6
-__SYSCALL(__NR_lstat, sys_newlstat)
-#define __NR_poll				7
-__SYSCALL(__NR_poll, sys_poll)
-
-#define __NR_lseek				8
-__SYSCALL(__NR_lseek, sys_lseek)
-#define __NR_mmap				9
-__SYSCALL(__NR_mmap, sys_mmap)
-#define __NR_mprotect				10
-__SYSCALL(__NR_mprotect, sys_mprotect)
-#define __NR_munmap				11
-__SYSCALL(__NR_munmap, sys_munmap)
-#define __NR_brk				12
-__SYSCALL(__NR_brk, sys_brk)
-#define __NR_rt_sigaction			13
-__SYSCALL(__NR_rt_sigaction, sys_rt_sigaction)
-#define __NR_rt_sigprocmask			14
-__SYSCALL(__NR_rt_sigprocmask, sys_rt_sigprocmask)
-#define __NR_rt_sigreturn			15
-__SYSCALL(__NR_rt_sigreturn, stub_rt_sigreturn)
-
-#define __NR_ioctl				16
-__SYSCALL(__NR_ioctl, sys_ioctl)
-#define __NR_pread64				17
-__SYSCALL(__NR_pread64, sys_pread64)
-#define __NR_pwrite64				18
-__SYSCALL(__NR_pwrite64, sys_pwrite64)
-#define __NR_readv				19
-__SYSCALL(__NR_readv, sys_readv)
-#define __NR_writev				20
-__SYSCALL(__NR_writev, sys_writev)
-#define __NR_access				21
-__SYSCALL(__NR_access, sys_access)
-#define __NR_pipe				22
-__SYSCALL(__NR_pipe, sys_pipe)
-#define __NR_select				23
-__SYSCALL(__NR_select, sys_select)
-
-#define __NR_sched_yield			24
-__SYSCALL(__NR_sched_yield, sys_sched_yield)
-#define __NR_mremap				25
-__SYSCALL(__NR_mremap, sys_mremap)
-#define __NR_msync				26
-__SYSCALL(__NR_msync, sys_msync)
-#define __NR_mincore				27
-__SYSCALL(__NR_mincore, sys_mincore)
-#define __NR_madvise				28
-__SYSCALL(__NR_madvise, sys_madvise)
-#define __NR_shmget				29
-__SYSCALL(__NR_shmget, sys_shmget)
-#define __NR_shmat				30
-__SYSCALL(__NR_shmat, sys_shmat)
-#define __NR_shmctl				31
-__SYSCALL(__NR_shmctl, sys_shmctl)
-
-#define __NR_dup				32
-__SYSCALL(__NR_dup, sys_dup)
-#define __NR_dup2				33
-__SYSCALL(__NR_dup2, sys_dup2)
-#define __NR_pause				34
-__SYSCALL(__NR_pause, sys_pause)
-#define __NR_nanosleep				35
-__SYSCALL(__NR_nanosleep, sys_nanosleep)
-#define __NR_getitimer				36
-__SYSCALL(__NR_getitimer, sys_getitimer)
-#define __NR_alarm				37
-__SYSCALL(__NR_alarm, sys_alarm)
-#define __NR_setitimer				38
-__SYSCALL(__NR_setitimer, sys_setitimer)
-#define __NR_getpid				39
-__SYSCALL(__NR_getpid, sys_getpid)
-
-#define __NR_sendfile				40
-__SYSCALL(__NR_sendfile, sys_sendfile64)
-#define __NR_socket				41
-__SYSCALL(__NR_socket, sys_socket)
-#define __NR_connect				42
-__SYSCALL(__NR_connect, sys_connect)
-#define __NR_accept				43
-__SYSCALL(__NR_accept, sys_accept)
-#define __NR_sendto				44
-__SYSCALL(__NR_sendto, sys_sendto)
-#define __NR_recvfrom				45
-__SYSCALL(__NR_recvfrom, sys_recvfrom)
-#define __NR_sendmsg				46
-__SYSCALL(__NR_sendmsg, sys_sendmsg)
-#define __NR_recvmsg				47
-__SYSCALL(__NR_recvmsg, sys_recvmsg)
-
-#define __NR_shutdown				48
-__SYSCALL(__NR_shutdown, sys_shutdown)
-#define __NR_bind				49
-__SYSCALL(__NR_bind, sys_bind)
-#define __NR_listen				50
-__SYSCALL(__NR_listen, sys_listen)
-#define __NR_getsockname			51
-__SYSCALL(__NR_getsockname, sys_getsockname)
-#define __NR_getpeername			52
-__SYSCALL(__NR_getpeername, sys_getpeername)
-#define __NR_socketpair				53
-__SYSCALL(__NR_socketpair, sys_socketpair)
-#define __NR_setsockopt				54
-__SYSCALL(__NR_setsockopt, sys_setsockopt)
-#define __NR_getsockopt				55
-__SYSCALL(__NR_getsockopt, sys_getsockopt)
-
-#define __NR_clone				56
-__SYSCALL(__NR_clone, stub_clone)
-#define __NR_fork				57
-__SYSCALL(__NR_fork, stub_fork)
-#define __NR_vfork				58
-__SYSCALL(__NR_vfork, stub_vfork)
-#define __NR_execve				59
-__SYSCALL(__NR_execve, stub_execve)
-#define __NR_exit				60
-__SYSCALL(__NR_exit, sys_exit)
-#define __NR_wait4				61
-__SYSCALL(__NR_wait4, sys_wait4)
-#define __NR_kill				62
-__SYSCALL(__NR_kill, sys_kill)
-#define __NR_uname				63
-__SYSCALL(__NR_uname, sys_uname)
-
-#define __NR_semget				64
-__SYSCALL(__NR_semget, sys_semget)
-#define __NR_semop				65
-__SYSCALL(__NR_semop, sys_semop)
-#define __NR_semctl				66
-__SYSCALL(__NR_semctl, sys_semctl)
-#define __NR_shmdt				67
-__SYSCALL(__NR_shmdt, sys_shmdt)
-#define __NR_msgget				68
-__SYSCALL(__NR_msgget, sys_msgget)
-#define __NR_msgsnd				69
-__SYSCALL(__NR_msgsnd, sys_msgsnd)
-#define __NR_msgrcv				70
-__SYSCALL(__NR_msgrcv, sys_msgrcv)
-#define __NR_msgctl				71
-__SYSCALL(__NR_msgctl, sys_msgctl)
-
-#define __NR_fcntl				72
-__SYSCALL(__NR_fcntl, sys_fcntl)
-#define __NR_flock				73
-__SYSCALL(__NR_flock, sys_flock)
-#define __NR_fsync				74
-__SYSCALL(__NR_fsync, sys_fsync)
-#define __NR_fdatasync				75
-__SYSCALL(__NR_fdatasync, sys_fdatasync)
-#define __NR_truncate				76
-__SYSCALL(__NR_truncate, sys_truncate)
-#define __NR_ftruncate				77
-__SYSCALL(__NR_ftruncate, sys_ftruncate)
-#define __NR_getdents				78
-__SYSCALL(__NR_getdents, sys_getdents)
-#define __NR_getcwd				79
-__SYSCALL(__NR_getcwd, sys_getcwd)
-
-#define __NR_chdir				80
-__SYSCALL(__NR_chdir, sys_chdir)
-#define __NR_fchdir				81
-__SYSCALL(__NR_fchdir, sys_fchdir)
-#define __NR_rename				82
-__SYSCALL(__NR_rename, sys_rename)
-#define __NR_mkdir				83
-__SYSCALL(__NR_mkdir, sys_mkdir)
-#define __NR_rmdir				84
-__SYSCALL(__NR_rmdir, sys_rmdir)
-#define __NR_creat				85
-__SYSCALL(__NR_creat, sys_creat)
-#define __NR_link				86
-__SYSCALL(__NR_link, sys_link)
-#define __NR_unlink				87
-__SYSCALL(__NR_unlink, sys_unlink)
-
-#define __NR_symlink				88
-__SYSCALL(__NR_symlink, sys_symlink)
-#define __NR_readlink				89
-__SYSCALL(__NR_readlink, sys_readlink)
-#define __NR_chmod				90
-__SYSCALL(__NR_chmod, sys_chmod)
-#define __NR_fchmod				91
-__SYSCALL(__NR_fchmod, sys_fchmod)
-#define __NR_chown				92
-__SYSCALL(__NR_chown, sys_chown)
-#define __NR_fchown				93
-__SYSCALL(__NR_fchown, sys_fchown)
-#define __NR_lchown				94
-__SYSCALL(__NR_lchown, sys_lchown)
-#define __NR_umask				95
-__SYSCALL(__NR_umask, sys_umask)
-
-#define __NR_gettimeofday			96
-__SYSCALL(__NR_gettimeofday, sys_gettimeofday)
-#define __NR_getrlimit				97
-__SYSCALL(__NR_getrlimit, sys_getrlimit)
-#define __NR_getrusage				98
-__SYSCALL(__NR_getrusage, sys_getrusage)
-#define __NR_sysinfo				99
-__SYSCALL(__NR_sysinfo, sys_sysinfo)
-#define __NR_times				100
-__SYSCALL(__NR_times, sys_times)
-#define __NR_ptrace				101
-__SYSCALL(__NR_ptrace, sys_ptrace)
-#define __NR_getuid				102
-__SYSCALL(__NR_getuid, sys_getuid)
-#define __NR_syslog				103
-__SYSCALL(__NR_syslog, sys_syslog)
-
-/* at the very end the stuff that never runs during the benchmarks */
-#define __NR_getgid				104
-__SYSCALL(__NR_getgid, sys_getgid)
-#define __NR_setuid				105
-__SYSCALL(__NR_setuid, sys_setuid)
-#define __NR_setgid				106
-__SYSCALL(__NR_setgid, sys_setgid)
-#define __NR_geteuid				107
-__SYSCALL(__NR_geteuid, sys_geteuid)
-#define __NR_getegid				108
-__SYSCALL(__NR_getegid, sys_getegid)
-#define __NR_setpgid				109
-__SYSCALL(__NR_setpgid, sys_setpgid)
-#define __NR_getppid				110
-__SYSCALL(__NR_getppid, sys_getppid)
-#define __NR_getpgrp				111
-__SYSCALL(__NR_getpgrp, sys_getpgrp)
-
-#define __NR_setsid				112
-__SYSCALL(__NR_setsid, sys_setsid)
-#define __NR_setreuid				113
-__SYSCALL(__NR_setreuid, sys_setreuid)
-#define __NR_setregid				114
-__SYSCALL(__NR_setregid, sys_setregid)
-#define __NR_getgroups				115
-__SYSCALL(__NR_getgroups, sys_getgroups)
-#define __NR_setgroups				116
-__SYSCALL(__NR_setgroups, sys_setgroups)
-#define __NR_setresuid				117
-__SYSCALL(__NR_setresuid, sys_setresuid)
-#define __NR_getresuid				118
-__SYSCALL(__NR_getresuid, sys_getresuid)
-#define __NR_setresgid				119
-__SYSCALL(__NR_setresgid, sys_setresgid)
-
-#define __NR_getresgid				120
-__SYSCALL(__NR_getresgid, sys_getresgid)
-#define __NR_getpgid				121
-__SYSCALL(__NR_getpgid, sys_getpgid)
-#define __NR_setfsuid				122
-__SYSCALL(__NR_setfsuid, sys_setfsuid)
-#define __NR_setfsgid				123
-__SYSCALL(__NR_setfsgid, sys_setfsgid)
-#define __NR_getsid				124
-__SYSCALL(__NR_getsid, sys_getsid)
-#define __NR_capget				125
-__SYSCALL(__NR_capget, sys_capget)
-#define __NR_capset				126
-__SYSCALL(__NR_capset, sys_capset)
-
-#define __NR_rt_sigpending			127
-__SYSCALL(__NR_rt_sigpending, sys_rt_sigpending)
-#define __NR_rt_sigtimedwait			128
-__SYSCALL(__NR_rt_sigtimedwait, sys_rt_sigtimedwait)
-#define __NR_rt_sigqueueinfo			129
-__SYSCALL(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo)
-#define __NR_rt_sigsuspend			130
-__SYSCALL(__NR_rt_sigsuspend, sys_rt_sigsuspend)
-#define __NR_sigaltstack			131
-__SYSCALL(__NR_sigaltstack, stub_sigaltstack)
-#define __NR_utime				132
-__SYSCALL(__NR_utime, sys_utime)
-#define __NR_mknod				133
-__SYSCALL(__NR_mknod, sys_mknod)
-
-/* Only needed for a.out */
-#define __NR_uselib				134
-__SYSCALL(__NR_uselib, sys_ni_syscall)
-#define __NR_personality			135
-__SYSCALL(__NR_personality, sys_personality)
-
-#define __NR_ustat				136
-__SYSCALL(__NR_ustat, sys_ustat)
-#define __NR_statfs				137
-__SYSCALL(__NR_statfs, sys_statfs)
-#define __NR_fstatfs				138
-__SYSCALL(__NR_fstatfs, sys_fstatfs)
-#define __NR_sysfs				139
-__SYSCALL(__NR_sysfs, sys_sysfs)
-
-#define __NR_getpriority			140
-__SYSCALL(__NR_getpriority, sys_getpriority)
-#define __NR_setpriority			141
-__SYSCALL(__NR_setpriority, sys_setpriority)
-#define __NR_sched_setparam			142
-__SYSCALL(__NR_sched_setparam, sys_sched_setparam)
-#define __NR_sched_getparam			143
-__SYSCALL(__NR_sched_getparam, sys_sched_getparam)
-#define __NR_sched_setscheduler			144
-__SYSCALL(__NR_sched_setscheduler, sys_sched_setscheduler)
-#define __NR_sched_getscheduler			145
-__SYSCALL(__NR_sched_getscheduler, sys_sched_getscheduler)
-#define __NR_sched_get_priority_max		146
-__SYSCALL(__NR_sched_get_priority_max, sys_sched_get_priority_max)
-#define __NR_sched_get_priority_min		147
-__SYSCALL(__NR_sched_get_priority_min, sys_sched_get_priority_min)
-#define __NR_sched_rr_get_interval		148
-__SYSCALL(__NR_sched_rr_get_interval, sys_sched_rr_get_interval)
-
-#define __NR_mlock				149
-__SYSCALL(__NR_mlock, sys_mlock)
-#define __NR_munlock				150
-__SYSCALL(__NR_munlock, sys_munlock)
-#define __NR_mlockall				151
-__SYSCALL(__NR_mlockall, sys_mlockall)
-#define __NR_munlockall				152
-__SYSCALL(__NR_munlockall, sys_munlockall)
-
-#define __NR_vhangup				153
-__SYSCALL(__NR_vhangup, sys_vhangup)
-
-#define __NR_modify_ldt				154
-__SYSCALL(__NR_modify_ldt, sys_modify_ldt)
-
-#define __NR_pivot_root				155
-__SYSCALL(__NR_pivot_root, sys_pivot_root)
-
-#define __NR__sysctl				156
-__SYSCALL(__NR__sysctl, sys_sysctl)
-
-#define __NR_prctl				157
-__SYSCALL(__NR_prctl, sys_prctl)
-#define __NR_arch_prctl				158
-__SYSCALL(__NR_arch_prctl, sys_arch_prctl)
-
-#define __NR_adjtimex				159
-__SYSCALL(__NR_adjtimex, sys_adjtimex)
-
-#define __NR_setrlimit				160
-__SYSCALL(__NR_setrlimit, sys_setrlimit)
-
-#define __NR_chroot				161
-__SYSCALL(__NR_chroot, sys_chroot)
-
-#define __NR_sync				162
-__SYSCALL(__NR_sync, sys_sync)
-
-#define __NR_acct				163
-__SYSCALL(__NR_acct, sys_acct)
-
-#define __NR_settimeofday			164
-__SYSCALL(__NR_settimeofday, sys_settimeofday)
-
-#define __NR_mount				165
-__SYSCALL(__NR_mount, sys_mount)
-#define __NR_umount2				166
-__SYSCALL(__NR_umount2, sys_umount)
-
-#define __NR_swapon				167
-__SYSCALL(__NR_swapon, sys_swapon)
-#define __NR_swapoff				168
-__SYSCALL(__NR_swapoff, sys_swapoff)
-
-#define __NR_reboot				169
-__SYSCALL(__NR_reboot, sys_reboot)
-
-#define __NR_sethostname			170
-__SYSCALL(__NR_sethostname, sys_sethostname)
-#define __NR_setdomainname			171
-__SYSCALL(__NR_setdomainname, sys_setdomainname)
-
-#define __NR_iopl				172
-__SYSCALL(__NR_iopl, stub_iopl)
-#define __NR_ioperm				173
-__SYSCALL(__NR_ioperm, sys_ioperm)
-
-#define __NR_create_module			174
-__SYSCALL(__NR_create_module, sys_ni_syscall)
-#define __NR_init_module			175
-__SYSCALL(__NR_init_module, sys_init_module)
-#define __NR_delete_module			176
-__SYSCALL(__NR_delete_module, sys_delete_module)
-#define __NR_get_kernel_syms			177
-__SYSCALL(__NR_get_kernel_syms, sys_ni_syscall)
-#define __NR_query_module			178
-__SYSCALL(__NR_query_module, sys_ni_syscall)
-
-#define __NR_quotactl				179
-__SYSCALL(__NR_quotactl, sys_quotactl)
-
-#define __NR_nfsservctl				180
-__SYSCALL(__NR_nfsservctl, sys_nfsservctl)
-
-/* reserved for LiS/STREAMS */
-#define __NR_getpmsg				181
-__SYSCALL(__NR_getpmsg, sys_ni_syscall)
-#define __NR_putpmsg				182
-__SYSCALL(__NR_putpmsg, sys_ni_syscall)
-
-/* reserved for AFS */
-#define __NR_afs_syscall			183
-__SYSCALL(__NR_afs_syscall, sys_ni_syscall)
-
-/* reserved for tux */
-#define __NR_tuxcall				184
-__SYSCALL(__NR_tuxcall, sys_ni_syscall)
-
-#define __NR_security				185
-__SYSCALL(__NR_security, sys_ni_syscall)
-
-#define __NR_gettid				186
-__SYSCALL(__NR_gettid, sys_gettid)
-
-#define __NR_readahead				187
-__SYSCALL(__NR_readahead, sys_readahead)
-#define __NR_setxattr				188
-__SYSCALL(__NR_setxattr, sys_setxattr)
-#define __NR_lsetxattr				189
-__SYSCALL(__NR_lsetxattr, sys_lsetxattr)
-#define __NR_fsetxattr				190
-__SYSCALL(__NR_fsetxattr, sys_fsetxattr)
-#define __NR_getxattr				191
-__SYSCALL(__NR_getxattr, sys_getxattr)
-#define __NR_lgetxattr				192
-__SYSCALL(__NR_lgetxattr, sys_lgetxattr)
-#define __NR_fgetxattr				193
-__SYSCALL(__NR_fgetxattr, sys_fgetxattr)
-#define __NR_listxattr				194
-__SYSCALL(__NR_listxattr, sys_listxattr)
-#define __NR_llistxattr				195
-__SYSCALL(__NR_llistxattr, sys_llistxattr)
-#define __NR_flistxattr				196
-__SYSCALL(__NR_flistxattr, sys_flistxattr)
-#define __NR_removexattr			197
-__SYSCALL(__NR_removexattr, sys_removexattr)
-#define __NR_lremovexattr			198
-__SYSCALL(__NR_lremovexattr, sys_lremovexattr)
-#define __NR_fremovexattr			199
-__SYSCALL(__NR_fremovexattr, sys_fremovexattr)
-#define __NR_tkill				200
-__SYSCALL(__NR_tkill, sys_tkill)
-#define __NR_time				201
-__SYSCALL(__NR_time, sys_time)
-#define __NR_futex				202
-__SYSCALL(__NR_futex, sys_futex)
-#define __NR_sched_setaffinity			203
-__SYSCALL(__NR_sched_setaffinity, sys_sched_setaffinity)
-#define __NR_sched_getaffinity			204
-__SYSCALL(__NR_sched_getaffinity, sys_sched_getaffinity)
-#define __NR_set_thread_area			205
-__SYSCALL(__NR_set_thread_area, sys_ni_syscall)	/* use arch_prctl */
-#define __NR_io_setup				206
-__SYSCALL(__NR_io_setup, sys_io_setup)
-#define __NR_io_destroy				207
-__SYSCALL(__NR_io_destroy, sys_io_destroy)
-#define __NR_io_getevents			208
-__SYSCALL(__NR_io_getevents, sys_io_getevents)
-#define __NR_io_submit				209
-__SYSCALL(__NR_io_submit, sys_io_submit)
-#define __NR_io_cancel				210
-__SYSCALL(__NR_io_cancel, sys_io_cancel)
-#define __NR_get_thread_area			211
-__SYSCALL(__NR_get_thread_area, sys_ni_syscall)	/* use arch_prctl */
-#define __NR_lookup_dcookie			212
-__SYSCALL(__NR_lookup_dcookie, sys_lookup_dcookie)
-#define __NR_epoll_create			213
-__SYSCALL(__NR_epoll_create, sys_epoll_create)
-#define __NR_epoll_ctl_old			214
-__SYSCALL(__NR_epoll_ctl_old, sys_ni_syscall)
-#define __NR_epoll_wait_old			215
-__SYSCALL(__NR_epoll_wait_old, sys_ni_syscall)
-#define __NR_remap_file_pages			216
-__SYSCALL(__NR_remap_file_pages, sys_remap_file_pages)
-#define __NR_getdents64				217
-__SYSCALL(__NR_getdents64, sys_getdents64)
-#define __NR_set_tid_address			218
-__SYSCALL(__NR_set_tid_address, sys_set_tid_address)
-#define __NR_restart_syscall			219
-__SYSCALL(__NR_restart_syscall, sys_restart_syscall)
-#define __NR_semtimedop				220
-__SYSCALL(__NR_semtimedop, sys_semtimedop)
-#define __NR_fadvise64				221
-__SYSCALL(__NR_fadvise64, sys_fadvise64)
-#define __NR_timer_create			222
-__SYSCALL(__NR_timer_create, sys_timer_create)
-#define __NR_timer_settime			223
-__SYSCALL(__NR_timer_settime, sys_timer_settime)
-#define __NR_timer_gettime			224
-__SYSCALL(__NR_timer_gettime, sys_timer_gettime)
-#define __NR_timer_getoverrun			225
-__SYSCALL(__NR_timer_getoverrun, sys_timer_getoverrun)
-#define __NR_timer_delete			226
-__SYSCALL(__NR_timer_delete, sys_timer_delete)
-#define __NR_clock_settime			227
-__SYSCALL(__NR_clock_settime, sys_clock_settime)
-#define __NR_clock_gettime			228
-__SYSCALL(__NR_clock_gettime, sys_clock_gettime)
-#define __NR_clock_getres			229
-__SYSCALL(__NR_clock_getres, sys_clock_getres)
-#define __NR_clock_nanosleep			230
-__SYSCALL(__NR_clock_nanosleep, sys_clock_nanosleep)
-#define __NR_exit_group				231
-__SYSCALL(__NR_exit_group, sys_exit_group)
-#define __NR_epoll_wait				232
-__SYSCALL(__NR_epoll_wait, sys_epoll_wait)
-#define __NR_epoll_ctl				233
-__SYSCALL(__NR_epoll_ctl, sys_epoll_ctl)
-#define __NR_tgkill				234
-__SYSCALL(__NR_tgkill, sys_tgkill)
-#define __NR_utimes				235
-__SYSCALL(__NR_utimes, sys_utimes)
-#define __NR_vserver				236
-__SYSCALL(__NR_vserver, sys_ni_syscall)
-#define __NR_mbind				237
-__SYSCALL(__NR_mbind, sys_mbind)
-#define __NR_set_mempolicy			238
-__SYSCALL(__NR_set_mempolicy, sys_set_mempolicy)
-#define __NR_get_mempolicy			239
-__SYSCALL(__NR_get_mempolicy, sys_get_mempolicy)
-#define __NR_mq_open				240
-__SYSCALL(__NR_mq_open, sys_mq_open)
-#define __NR_mq_unlink				241
-__SYSCALL(__NR_mq_unlink, sys_mq_unlink)
-#define __NR_mq_timedsend			242
-__SYSCALL(__NR_mq_timedsend, sys_mq_timedsend)
-#define __NR_mq_timedreceive			243
-__SYSCALL(__NR_mq_timedreceive, sys_mq_timedreceive)
-#define __NR_mq_notify				244
-__SYSCALL(__NR_mq_notify, sys_mq_notify)
-#define __NR_mq_getsetattr			245
-__SYSCALL(__NR_mq_getsetattr, sys_mq_getsetattr)
-#define __NR_kexec_load				246
-__SYSCALL(__NR_kexec_load, sys_kexec_load)
-#define __NR_waitid				247
-__SYSCALL(__NR_waitid, sys_waitid)
-#define __NR_add_key				248
-__SYSCALL(__NR_add_key, sys_add_key)
-#define __NR_request_key			249
-__SYSCALL(__NR_request_key, sys_request_key)
-#define __NR_keyctl				250
-__SYSCALL(__NR_keyctl, sys_keyctl)
-#define __NR_ioprio_set				251
-__SYSCALL(__NR_ioprio_set, sys_ioprio_set)
-#define __NR_ioprio_get				252
-__SYSCALL(__NR_ioprio_get, sys_ioprio_get)
-#define __NR_inotify_init			253
-__SYSCALL(__NR_inotify_init, sys_inotify_init)
-#define __NR_inotify_add_watch			254
-__SYSCALL(__NR_inotify_add_watch, sys_inotify_add_watch)
-#define __NR_inotify_rm_watch			255
-__SYSCALL(__NR_inotify_rm_watch, sys_inotify_rm_watch)
-#define __NR_migrate_pages			256
-__SYSCALL(__NR_migrate_pages, sys_migrate_pages)
-#define __NR_openat				257
-__SYSCALL(__NR_openat, sys_openat)
-#define __NR_mkdirat				258
-__SYSCALL(__NR_mkdirat, sys_mkdirat)
-#define __NR_mknodat				259
-__SYSCALL(__NR_mknodat, sys_mknodat)
-#define __NR_fchownat				260
-__SYSCALL(__NR_fchownat, sys_fchownat)
-#define __NR_futimesat				261
-__SYSCALL(__NR_futimesat, sys_futimesat)
-#define __NR_newfstatat				262
-__SYSCALL(__NR_newfstatat, sys_newfstatat)
-#define __NR_unlinkat				263
-__SYSCALL(__NR_unlinkat, sys_unlinkat)
-#define __NR_renameat				264
-__SYSCALL(__NR_renameat, sys_renameat)
-#define __NR_linkat				265
-__SYSCALL(__NR_linkat, sys_linkat)
-#define __NR_symlinkat				266
-__SYSCALL(__NR_symlinkat, sys_symlinkat)
-#define __NR_readlinkat				267
-__SYSCALL(__NR_readlinkat, sys_readlinkat)
-#define __NR_fchmodat				268
-__SYSCALL(__NR_fchmodat, sys_fchmodat)
-#define __NR_faccessat				269
-__SYSCALL(__NR_faccessat, sys_faccessat)
-#define __NR_pselect6				270
-__SYSCALL(__NR_pselect6, sys_pselect6)
-#define __NR_ppoll				271
-__SYSCALL(__NR_ppoll,	sys_ppoll)
-#define __NR_unshare				272
-__SYSCALL(__NR_unshare,	sys_unshare)
-#define __NR_set_robust_list			273
-__SYSCALL(__NR_set_robust_list, sys_set_robust_list)
-#define __NR_get_robust_list			274
-__SYSCALL(__NR_get_robust_list, sys_get_robust_list)
-#define __NR_splice				275
-__SYSCALL(__NR_splice, sys_splice)
-#define __NR_tee				276
-__SYSCALL(__NR_tee, sys_tee)
-#define __NR_sync_file_range			277
-__SYSCALL(__NR_sync_file_range, sys_sync_file_range)
-#define __NR_vmsplice				278
-__SYSCALL(__NR_vmsplice, sys_vmsplice)
-#define __NR_move_pages				279
-__SYSCALL(__NR_move_pages, sys_move_pages)
-#define __NR_utimensat				280
-__SYSCALL(__NR_utimensat, sys_utimensat)
-#define __IGNORE_getcpu		/* implemented as a vsyscall */
-#define __NR_epoll_pwait			281
-__SYSCALL(__NR_epoll_pwait, sys_epoll_pwait)
-#define __NR_signalfd				282
-__SYSCALL(__NR_signalfd, sys_signalfd)
-#define __NR_timerfd_create			283
-__SYSCALL(__NR_timerfd_create, sys_timerfd_create)
-#define __NR_eventfd				284
-__SYSCALL(__NR_eventfd, sys_eventfd)
-#define __NR_fallocate				285
-__SYSCALL(__NR_fallocate, sys_fallocate)
-#define __NR_timerfd_settime			286
-__SYSCALL(__NR_timerfd_settime, sys_timerfd_settime)
-#define __NR_timerfd_gettime			287
-__SYSCALL(__NR_timerfd_gettime, sys_timerfd_gettime)
-#define __NR_paccept				288
-__SYSCALL(__NR_paccept, sys_paccept)
-#define __NR_signalfd4				289
-__SYSCALL(__NR_signalfd4, sys_signalfd4)
-#define __NR_eventfd2				290
-__SYSCALL(__NR_eventfd2, sys_eventfd2)
-#define __NR_epoll_create1			291
-__SYSCALL(__NR_epoll_create1, sys_epoll_create1)
-#define __NR_dup3				292
-__SYSCALL(__NR_dup3, sys_dup3)
-#define __NR_pipe2				293
-__SYSCALL(__NR_pipe2, sys_pipe2)
-#define __NR_inotify_init1			294
-__SYSCALL(__NR_inotify_init1, sys_inotify_init1)
-
-
-#ifndef __NO_STUBS
-#define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_OLD_STAT
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SGETMASK
-#define __ARCH_WANT_SYS_SIGNAL
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_OLD_GETRLIMIT
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_SIGPENDING
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_RT_SIGACTION
-#define __ARCH_WANT_SYS_RT_SIGSUSPEND
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_COMPAT_SYS_TIME
-#endif	/* __NO_STUBS */
-
-#ifdef __KERNEL__
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-#endif	/* __KERNEL__ */
-
-#endif /* ASM_X86__UNISTD_64_H */
diff --git a/include/asm-x86/unwind.h b/include/asm-x86/unwind.h
deleted file mode 100644
index a2151567db44..000000000000
--- a/include/asm-x86/unwind.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef ASM_X86__UNWIND_H
-#define ASM_X86__UNWIND_H
-
-#define UNW_PC(frame) ((void)(frame), 0UL)
-#define UNW_SP(frame) ((void)(frame), 0UL)
-#define UNW_FP(frame) ((void)(frame), 0UL)
-
-static inline int arch_unw_user_mode(const void *info)
-{
-	return 0;
-}
-
-#endif /* ASM_X86__UNWIND_H */
diff --git a/include/asm-x86/user.h b/include/asm-x86/user.h
deleted file mode 100644
index 999873b22e7f..000000000000
--- a/include/asm-x86/user.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifdef CONFIG_X86_32
-# include "user_32.h"
-#else
-# include "user_64.h"
-#endif
diff --git a/include/asm-x86/user32.h b/include/asm-x86/user32.h
deleted file mode 100644
index aa66c1857f06..000000000000
--- a/include/asm-x86/user32.h
+++ /dev/null
@@ -1,70 +0,0 @@
-#ifndef ASM_X86__USER32_H
-#define ASM_X86__USER32_H
-
-/* IA32 compatible user structures for ptrace.
- * These should be used for 32bit coredumps too. */
-
-struct user_i387_ia32_struct {
-	u32	cwd;
-	u32	swd;
-	u32	twd;
-	u32	fip;
-	u32	fcs;
-	u32	foo;
-	u32	fos;
-	u32	st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
-};
-
-/* FSAVE frame with extensions */
-struct user32_fxsr_struct {
-	unsigned short	cwd;
-	unsigned short	swd;
-	unsigned short	twd;	/* not compatible to 64bit twd */
-	unsigned short	fop;
-	int	fip;
-	int	fcs;
-	int	foo;
-	int	fos;
-	int	mxcsr;
-	int	reserved;
-	int	st_space[32];	/* 8*16 bytes for each FP-reg = 128 bytes */
-	int	xmm_space[32];	/* 8*16 bytes for each XMM-reg = 128 bytes */
-	int	padding[56];
-};
-
-struct user_regs_struct32 {
-	__u32 ebx, ecx, edx, esi, edi, ebp, eax;
-	unsigned short ds, __ds, es, __es;
-	unsigned short fs, __fs, gs, __gs;
-	__u32 orig_eax, eip;
-	unsigned short cs, __cs;
-	__u32 eflags, esp;
-	unsigned short ss, __ss;
-};
-
-struct user32 {
-  struct user_regs_struct32 regs; /* Where the registers are actually stored */
-  int u_fpvalid;		/* True if math co-processor being used. */
-				/* for this mess. Not yet used. */
-  struct user_i387_ia32_struct i387;	/* Math Co-processor registers. */
-/* The rest of this junk is to help gdb figure out what goes where */
-  __u32 u_tsize;	/* Text segment size (pages). */
-  __u32 u_dsize;	/* Data segment size (pages). */
-  __u32 u_ssize;	/* Stack segment size (pages). */
-  __u32 start_code;     /* Starting virtual address of text. */
-  __u32 start_stack;	/* Starting virtual address of stack area.
-				   This is actually the bottom of the stack,
-				   the top of the stack is always found in the
-				   esp register.  */
-  __u32 signal;     		/* Signal that caused the core dump. */
-  int reserved;			/* No __u32er used */
-  __u32 u_ar0;	/* Used by gdb to help find the values for */
-				/* the registers. */
-  __u32 u_fpstate;	/* Math Co-processor pointer. */
-  __u32 magic;		/* To uniquely identify a core file */
-  char u_comm[32];		/* User command that was responsible */
-  int u_debugreg[8];
-};
-
-
-#endif /* ASM_X86__USER32_H */
diff --git a/include/asm-x86/user_32.h b/include/asm-x86/user_32.h
deleted file mode 100644
index e0fe2f55f1a6..000000000000
--- a/include/asm-x86/user_32.h
+++ /dev/null
@@ -1,131 +0,0 @@
-#ifndef ASM_X86__USER_32_H
-#define ASM_X86__USER_32_H
-
-#include <asm/page.h>
-/* Core file format: The core file is written in such a way that gdb
-   can understand it and provide useful information to the user (under
-   linux we use the 'trad-core' bfd).  There are quite a number of
-   obstacles to being able to view the contents of the floating point
-   registers, and until these are solved you will not be able to view the
-   contents of them.  Actually, you can read in the core file and look at
-   the contents of the user struct to find out what the floating point
-   registers contain.
-   The actual file contents are as follows:
-   UPAGE: 1 page consisting of a user struct that tells gdb what is present
-   in the file.  Directly after this is a copy of the task_struct, which
-   is currently not used by gdb, but it may come in useful at some point.
-   All of the registers are stored as part of the upage.  The upage should
-   always be only one page.
-   DATA: The data area is stored.  We use current->end_text to
-   current->brk to pick up all of the user variables, plus any memory
-   that may have been malloced.  No attempt is made to determine if a page
-   is demand-zero or if a page is totally unused, we just cover the entire
-   range.  All of the addresses are rounded in such a way that an integral
-   number of pages is written.
-   STACK: We need the stack information in order to get a meaningful
-   backtrace.  We need to write the data from (esp) to
-   current->start_stack, so we round each of these off in order to be able
-   to write an integer number of pages.
-   The minimum core file size is 3 pages, or 12288 bytes.
-*/
-
-/*
- * Pentium III FXSR, SSE support
- *	Gareth Hughes <gareth@valinux.com>, May 2000
- *
- * Provide support for the GDB 5.0+ PTRACE_{GET|SET}FPXREGS requests for
- * interacting with the FXSR-format floating point environment.  Floating
- * point data can be accessed in the regular format in the usual manner,
- * and both the standard and SIMD floating point data can be accessed via
- * the new ptrace requests.  In either case, changes to the FPU environment
- * will be reflected in the task's state as expected.
- */
-
-struct user_i387_struct {
-	long	cwd;
-	long	swd;
-	long	twd;
-	long	fip;
-	long	fcs;
-	long	foo;
-	long	fos;
-	long	st_space[20];	/* 8*10 bytes for each FP-reg = 80 bytes */
-};
-
-struct user_fxsr_struct {
-	unsigned short	cwd;
-	unsigned short	swd;
-	unsigned short	twd;
-	unsigned short	fop;
-	long	fip;
-	long	fcs;
-	long	foo;
-	long	fos;
-	long	mxcsr;
-	long	reserved;
-	long	st_space[32];	/* 8*16 bytes for each FP-reg = 128 bytes */
-	long	xmm_space[32];	/* 8*16 bytes for each XMM-reg = 128 bytes */
-	long	padding[56];
-};
-
-/*
- * This is the old layout of "struct pt_regs", and
- * is still the layout used by user mode (the new
- * pt_regs doesn't have all registers as the kernel
- * doesn't use the extra segment registers)
- */
-struct user_regs_struct {
-	unsigned long	bx;
-	unsigned long	cx;
-	unsigned long	dx;
-	unsigned long	si;
-	unsigned long	di;
-	unsigned long	bp;
-	unsigned long	ax;
-	unsigned long	ds;
-	unsigned long	es;
-	unsigned long	fs;
-	unsigned long	gs;
-	unsigned long	orig_ax;
-	unsigned long	ip;
-	unsigned long	cs;
-	unsigned long	flags;
-	unsigned long	sp;
-	unsigned long	ss;
-};
-
-/* When the kernel dumps core, it starts by dumping the user struct -
-   this will be used by gdb to figure out where the data and stack segments
-   are within the file, and what virtual addresses to use. */
-struct user{
-/* We start with the registers, to mimic the way that "memory" is returned
-   from the ptrace(3,...) function.  */
-  struct user_regs_struct regs;	/* Where the registers are actually stored */
-/* ptrace does not yet supply these.  Someday.... */
-  int u_fpvalid;		/* True if math co-processor being used. */
-				/* for this mess. Not yet used. */
-  struct user_i387_struct i387;	/* Math Co-processor registers. */
-/* The rest of this junk is to help gdb figure out what goes where */
-  unsigned long int u_tsize;	/* Text segment size (pages). */
-  unsigned long int u_dsize;	/* Data segment size (pages). */
-  unsigned long int u_ssize;	/* Stack segment size (pages). */
-  unsigned long start_code;     /* Starting virtual address of text. */
-  unsigned long start_stack;	/* Starting virtual address of stack area.
-				   This is actually the bottom of the stack,
-				   the top of the stack is always found in the
-				   esp register.  */
-  long int signal;     		/* Signal that caused the core dump. */
-  int reserved;			/* No longer used */
-  unsigned long u_ar0;		/* Used by gdb to help find the values for */
-				/* the registers. */
-  struct user_i387_struct *u_fpstate;	/* Math Co-processor pointer. */
-  unsigned long magic;		/* To uniquely identify a core file */
-  char u_comm[32];		/* User command that was responsible */
-  int u_debugreg[8];
-};
-#define NBPG PAGE_SIZE
-#define UPAGES 1
-#define HOST_TEXT_START_ADDR (u.start_code)
-#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
-
-#endif /* ASM_X86__USER_32_H */
diff --git a/include/asm-x86/user_64.h b/include/asm-x86/user_64.h
deleted file mode 100644
index 38b5799863b4..000000000000
--- a/include/asm-x86/user_64.h
+++ /dev/null
@@ -1,137 +0,0 @@
-#ifndef ASM_X86__USER_64_H
-#define ASM_X86__USER_64_H
-
-#include <asm/types.h>
-#include <asm/page.h>
-/* Core file format: The core file is written in such a way that gdb
-   can understand it and provide useful information to the user.
-   There are quite a number of obstacles to being able to view the
-   contents of the floating point registers, and until these are
-   solved you will not be able to view the contents of them.
-   Actually, you can read in the core file and look at the contents of
-   the user struct to find out what the floating point registers
-   contain.
-
-   The actual file contents are as follows:
-   UPAGE: 1 page consisting of a user struct that tells gdb what is present
-   in the file.  Directly after this is a copy of the task_struct, which
-   is currently not used by gdb, but it may come in useful at some point.
-   All of the registers are stored as part of the upage.  The upage should
-   always be only one page.
-   DATA: The data area is stored.  We use current->end_text to
-   current->brk to pick up all of the user variables, plus any memory
-   that may have been malloced.  No attempt is made to determine if a page
-   is demand-zero or if a page is totally unused, we just cover the entire
-   range.  All of the addresses are rounded in such a way that an integral
-   number of pages is written.
-   STACK: We need the stack information in order to get a meaningful
-   backtrace.  We need to write the data from (esp) to
-   current->start_stack, so we round each of these off in order to be able
-   to write an integer number of pages.
-   The minimum core file size is 3 pages, or 12288 bytes.  */
-
-/*
- * Pentium III FXSR, SSE support
- *	Gareth Hughes <gareth@valinux.com>, May 2000
- *
- * Provide support for the GDB 5.0+ PTRACE_{GET|SET}FPXREGS requests for
- * interacting with the FXSR-format floating point environment.  Floating
- * point data can be accessed in the regular format in the usual manner,
- * and both the standard and SIMD floating point data can be accessed via
- * the new ptrace requests.  In either case, changes to the FPU environment
- * will be reflected in the task's state as expected.
- *
- * x86-64 support by Andi Kleen.
- */
-
-/* This matches the 64bit FXSAVE format as defined by AMD. It is the same
-   as the 32bit format defined by Intel, except that the selector:offset pairs
-   for data and eip are replaced with flat 64bit pointers. */
-struct user_i387_struct {
-	unsigned short	cwd;
-	unsigned short	swd;
-	unsigned short	twd;	/* Note this is not the same as
-				   the 32bit/x87/FSAVE twd */
-	unsigned short	fop;
-	__u64	rip;
-	__u64	rdp;
-	__u32	mxcsr;
-	__u32	mxcsr_mask;
-	__u32	st_space[32];	/* 8*16 bytes for each FP-reg = 128 bytes */
-	__u32	xmm_space[64];	/* 16*16 bytes for each XMM-reg = 256 bytes */
-	__u32	padding[24];
-};
-
-/*
- * Segment register layout in coredumps.
- */
-struct user_regs_struct {
-	unsigned long	r15;
-	unsigned long	r14;
-	unsigned long	r13;
-	unsigned long	r12;
-	unsigned long	bp;
-	unsigned long	bx;
-	unsigned long	r11;
-	unsigned long	r10;
-	unsigned long	r9;
-	unsigned long	r8;
-	unsigned long	ax;
-	unsigned long	cx;
-	unsigned long	dx;
-	unsigned long	si;
-	unsigned long	di;
-	unsigned long	orig_ax;
-	unsigned long	ip;
-	unsigned long	cs;
-	unsigned long	flags;
-	unsigned long	sp;
-	unsigned long	ss;
-	unsigned long	fs_base;
-	unsigned long	gs_base;
-	unsigned long	ds;
-	unsigned long	es;
-	unsigned long	fs;
-	unsigned long	gs;
-};
-
-/* When the kernel dumps core, it starts by dumping the user struct -
-   this will be used by gdb to figure out where the data and stack segments
-   are within the file, and what virtual addresses to use. */
-
-struct user {
-/* We start with the registers, to mimic the way that "memory" is returned
-   from the ptrace(3,...) function.  */
-  struct user_regs_struct regs;	/* Where the registers are actually stored */
-/* ptrace does not yet supply these.  Someday.... */
-  int u_fpvalid;		/* True if math co-processor being used. */
-				/* for this mess. Not yet used. */
-  int pad0;
-  struct user_i387_struct i387;	/* Math Co-processor registers. */
-/* The rest of this junk is to help gdb figure out what goes where */
-  unsigned long int u_tsize;	/* Text segment size (pages). */
-  unsigned long int u_dsize;	/* Data segment size (pages). */
-  unsigned long int u_ssize;	/* Stack segment size (pages). */
-  unsigned long start_code;     /* Starting virtual address of text. */
-  unsigned long start_stack;	/* Starting virtual address of stack area.
-				   This is actually the bottom of the stack,
-				   the top of the stack is always found in the
-				   esp register.  */
-  long int signal;		/* Signal that caused the core dump. */
-  int reserved;			/* No longer used */
-  int pad1;
-  unsigned long u_ar0;		/* Used by gdb to help find the values for */
-				/* the registers. */
-  struct user_i387_struct *u_fpstate;	/* Math Co-processor pointer. */
-  unsigned long magic;		/* To uniquely identify a core file */
-  char u_comm[32];		/* User command that was responsible */
-  unsigned long u_debugreg[8];
-  unsigned long error_code; /* CPU error code or 0 */
-  unsigned long fault_address; /* CR3 or 0 */
-};
-#define NBPG PAGE_SIZE
-#define UPAGES 1
-#define HOST_TEXT_START_ADDR (u.start_code)
-#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
-
-#endif /* ASM_X86__USER_64_H */
diff --git a/include/asm-x86/uv/bios.h b/include/asm-x86/uv/bios.h
deleted file mode 100644
index 7cd6d7ec1308..000000000000
--- a/include/asm-x86/uv/bios.h
+++ /dev/null
@@ -1,68 +0,0 @@
-#ifndef ASM_X86__UV__BIOS_H
-#define ASM_X86__UV__BIOS_H
-
-/*
- * BIOS layer definitions.
- *
- *  Copyright (c) 2008 Silicon Graphics, Inc.  All Rights Reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#include <linux/rtc.h>
-
-#define BIOS_FREQ_BASE			0x01000001
-
-enum {
-	BIOS_FREQ_BASE_PLATFORM = 0,
-	BIOS_FREQ_BASE_INTERVAL_TIMER = 1,
-	BIOS_FREQ_BASE_REALTIME_CLOCK = 2
-};
-
-# define BIOS_CALL(result, a0, a1, a2, a3, a4, a5, a6, a7)		\
-	do {								\
-		/* XXX - the real call goes here */			\
-		result.status = BIOS_STATUS_UNIMPLEMENTED;		\
-		isrv.v0 = 0;						\
-		isrv.v1 = 0;						\
-	} while (0)
-
-enum {
-	BIOS_STATUS_SUCCESS		=  0,
-	BIOS_STATUS_UNIMPLEMENTED	= -1,
-	BIOS_STATUS_EINVAL		= -2,
-	BIOS_STATUS_ERROR		= -3
-};
-
-struct uv_bios_retval {
-	/*
-	 * A zero status value indicates call completed without error.
-	 * A negative status value indicates reason of call failure.
-	 * A positive status value indicates success but an
-	 * informational value should be printed (e.g., "reboot for
-	 * change to take effect").
-	 */
-	s64 status;
-	u64 v0;
-	u64 v1;
-	u64 v2;
-};
-
-extern long
-x86_bios_freq_base(unsigned long which, unsigned long *ticks_per_second,
-		   unsigned long *drift_info);
-extern const char *x86_bios_strerror(long status);
-
-#endif /* ASM_X86__UV__BIOS_H */
diff --git a/include/asm-x86/uv/uv_bau.h b/include/asm-x86/uv/uv_bau.h
deleted file mode 100644
index 77153fb18f5e..000000000000
--- a/include/asm-x86/uv/uv_bau.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * SGI UV Broadcast Assist Unit definitions
- *
- * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef ASM_X86__UV__UV_BAU_H
-#define ASM_X86__UV__UV_BAU_H
-
-#include <linux/bitmap.h>
-#define BITSPERBYTE 8
-
-/*
- * Broadcast Assist Unit messaging structures
- *
- * Selective Broadcast activations are induced by software action
- * specifying a particular 8-descriptor "set" via a 6-bit index written
- * to an MMR.
- * Thus there are 64 unique 512-byte sets of SB descriptors - one set for
- * each 6-bit index value. These descriptor sets are mapped in sequence
- * starting with set 0 located at the address specified in the
- * BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
- * set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
- *
- * We will use 31 sets, one for sending BAU messages from each of the 32
- * cpu's on the node.
- *
- * TLB shootdown will use the first of the 8 descriptors of each set.
- * Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
- */
-
-#define UV_ITEMS_PER_DESCRIPTOR		8
-#define UV_CPUS_PER_ACT_STATUS		32
-#define UV_ACT_STATUS_MASK		0x3
-#define UV_ACT_STATUS_SIZE		2
-#define UV_ACTIVATION_DESCRIPTOR_SIZE	32
-#define UV_DISTRIBUTION_SIZE		256
-#define UV_SW_ACK_NPENDING		8
-#define UV_NET_ENDPOINT_INTD		0x38
-#define UV_DESC_BASE_PNODE_SHIFT	49
-#define UV_PAYLOADQ_PNODE_SHIFT		49
-#define UV_PTC_BASENAME			"sgi_uv/ptc_statistics"
-#define uv_physnodeaddr(x)		((__pa((unsigned long)(x)) & uv_mmask))
-
-/*
- * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
- */
-#define DESC_STATUS_IDLE		0
-#define DESC_STATUS_ACTIVE		1
-#define DESC_STATUS_DESTINATION_TIMEOUT	2
-#define DESC_STATUS_SOURCE_TIMEOUT	3
-
-/*
- * source side threshholds at which message retries print a warning
- */
-#define SOURCE_TIMEOUT_LIMIT		20
-#define DESTINATION_TIMEOUT_LIMIT	20
-
-/*
- * number of entries in the destination side payload queue
- */
-#define DEST_Q_SIZE			17
-/*
- * number of destination side software ack resources
- */
-#define DEST_NUM_RESOURCES		8
-#define MAX_CPUS_PER_NODE		32
-/*
- * completion statuses for sending a TLB flush message
- */
-#define	FLUSH_RETRY			1
-#define	FLUSH_GIVEUP			2
-#define	FLUSH_COMPLETE			3
-
-/*
- * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
- * If the 'multilevel' flag in the header portion of the descriptor
- * has been set to 0, then endpoint multi-unicast mode is selected.
- * The distribution specification (32 bytes) is interpreted as a 256-bit
- * distribution vector. Adjacent bits correspond to consecutive even numbered
- * nodeIDs. The result of adding the index of a given bit to the 15-bit
- * 'base_dest_nodeid' field of the header corresponds to the
- * destination nodeID associated with that specified bit.
- */
-struct bau_target_nodemask {
-	unsigned long bits[BITS_TO_LONGS(256)];
-};
-
-/*
- * mask of cpu's on a node
- * (during initialization we need to check that unsigned long has
- *  enough bits for max. cpu's per node)
- */
-struct bau_local_cpumask {
-	unsigned long bits;
-};
-
-/*
- * Payload: 16 bytes (128 bits) (bytes 0x20-0x2f of descriptor)
- * only 12 bytes (96 bits) of the payload area are usable.
- * An additional 3 bytes (bits 27:4) of the header address are carried
- * to the next bytes of the destination payload queue.
- * And an additional 2 bytes of the header Suppl_A field are also
- * carried to the destination payload queue.
- * But the first byte of the Suppl_A becomes bits 127:120 (the 16th byte)
- * of the destination payload queue, which is written by the hardware
- * with the s/w ack resource bit vector.
- * [ effective message contents (16 bytes (128 bits) maximum), not counting
- *   the s/w ack bit vector  ]
- */
-
-/*
- * The payload is software-defined for INTD transactions
- */
-struct bau_msg_payload {
-	unsigned long address;		/* signifies a page or all TLB's
-						of the cpu */
-	/* 64 bits */
-	unsigned short sending_cpu;	/* filled in by sender */
-	/* 16 bits */
-	unsigned short acknowledge_count;/* filled in by destination */
-	/* 16 bits */
-	unsigned int reserved1:32;	/* not usable */
-};
-
-
-/*
- * Message header:  16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
- * see table 4.2.3.0.1 in broacast_assist spec.
- */
-struct bau_msg_header {
-	int dest_subnodeid:6;	/* must be zero */
-	/* bits 5:0 */
-	int base_dest_nodeid:15; /* nasid>>1 (pnode) of first bit in node_map */
-	/* bits 20:6 */
-	int command:8;		/* message type */
-	/* bits 28:21 */
-				/* 0x38: SN3net EndPoint Message */
-	int rsvd_1:3;		/* must be zero */
-	/* bits 31:29 */
-				/* int will align on 32 bits */
-	int rsvd_2:9;		/* must be zero */
-	/* bits 40:32 */
-				/* Suppl_A is 56-41 */
-	int payload_2a:8;	/* becomes byte 16 of msg */
-	/* bits 48:41 */	/* not currently using */
-	int payload_2b:8;	/* becomes byte 17 of msg */
-	/* bits 56:49 */	/* not currently using */
-				/* Address field (96:57) is never used as an
-				   address (these are address bits 42:3) */
-	int rsvd_3:1;		/* must be zero */
-	/* bit 57 */
-				/* address bits 27:4 are payload */
-				/* these 24 bits become bytes 12-14 of msg */
-	int replied_to:1;	/* sent as 0 by the source to byte 12 */
-	/* bit 58 */
-
-	int payload_1a:5;	/* not currently used */
-	/* bits 63:59 */
-	int payload_1b:8;	/* not currently used */
-	/* bits 71:64 */
-	int payload_1c:8;	/* not currently used */
-	/* bits 79:72 */
-	int payload_1d:2;	/* not currently used */
-	/* bits 81:80 */
-
-	int rsvd_4:7;		/* must be zero */
-	/* bits 88:82 */
-	int sw_ack_flag:1;	/* software acknowledge flag */
-	/* bit 89 */
-				/* INTD trasactions at destination are to
-				   wait for software acknowledge */
-	int rsvd_5:6;		/* must be zero */
-	/* bits 95:90 */
-	int rsvd_6:5;		/* must be zero */
-	/* bits 100:96 */
-	int int_both:1;		/* if 1, interrupt both sockets on the blade */
-	/* bit 101*/
-	int fairness:3;		/* usually zero */
-	/* bits 104:102 */
-	int multilevel:1;	/* multi-level multicast format */
-	/* bit 105 */
-				/* 0 for TLB: endpoint multi-unicast messages */
-	int chaining:1;		/* next descriptor is part of this activation*/
-	/* bit 106 */
-	int rsvd_7:21;		/* must be zero */
-	/* bits 127:107 */
-};
-
-/*
- * The activation descriptor:
- * The format of the message to send, plus all accompanying control
- * Should be 64 bytes
- */
-struct bau_desc {
-	struct bau_target_nodemask distribution;
-	/*
-	 * message template, consisting of header and payload:
-	 */
-	struct bau_msg_header header;
-	struct bau_msg_payload payload;
-};
-/*
- *   -payload--    ---------header------
- *   bytes 0-11    bits 41-56  bits 58-81
- *       A           B  (2)      C (3)
- *
- *            A/B/C are moved to:
- *       A            C          B
- *   bytes 0-11  bytes 12-14  bytes 16-17  (byte 15 filled in by hw as vector)
- *   ------------payload queue-----------
- */
-
-/*
- * The payload queue on the destination side is an array of these.
- * With BAU_MISC_CONTROL set for software acknowledge mode, the messages
- * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
- * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
- * (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from
- *  sw_ack_vector and payload_2)
- * "Enabling Software Acknowledgment mode (see Section 4.3.3 Software
- *  Acknowledge Processing) also selects 32 byte (17 bytes usable) payload
- *  operation."
- */
-struct bau_payload_queue_entry {
-	unsigned long address;		/* signifies a page or all TLB's
-						of the cpu */
-	/* 64 bits, bytes 0-7 */
-
-	unsigned short sending_cpu;	/* cpu that sent the message */
-	/* 16 bits, bytes 8-9 */
-
-	unsigned short acknowledge_count; /* filled in by destination */
-	/* 16 bits, bytes 10-11 */
-
-	unsigned short replied_to:1;	/* sent as 0 by the source */
-	/* 1 bit */
-	unsigned short unused1:7;       /* not currently using */
-	/* 7 bits: byte 12) */
-
-	unsigned char unused2[2];	/* not currently using */
-	/* bytes 13-14 */
-
-	unsigned char sw_ack_vector;	/* filled in by the hardware */
-	/* byte 15 (bits 127:120) */
-
-	unsigned char unused4[3];	/* not currently using bytes 17-19 */
-	/* bytes 17-19 */
-
-	int number_of_cpus;		/* filled in at destination */
-	/* 32 bits, bytes 20-23 (aligned) */
-
-	unsigned char unused5[8];       /* not using */
-	/* bytes 24-31 */
-};
-
-/*
- * one for every slot in the destination payload queue
- */
-struct bau_msg_status {
-	struct bau_local_cpumask seen_by;	/* map of cpu's */
-};
-
-/*
- * one for every slot in the destination software ack resources
- */
-struct bau_sw_ack_status {
-	struct bau_payload_queue_entry *msg;	/* associated message */
-	int watcher;				/* cpu monitoring, or -1 */
-};
-
-/*
- * one on every node and per-cpu; to locate the software tables
- */
-struct bau_control {
-	struct bau_desc *descriptor_base;
-	struct bau_payload_queue_entry *bau_msg_head;
-	struct bau_payload_queue_entry *va_queue_first;
-	struct bau_payload_queue_entry *va_queue_last;
-	struct bau_msg_status *msg_statuses;
-	int *watching; /* pointer to array */
-};
-
-/*
- * This structure is allocated per_cpu for UV TLB shootdown statistics.
- */
-struct ptc_stats {
-	unsigned long ptc_i;	/* number of IPI-style flushes */
-	unsigned long requestor;	/* number of nodes this cpu sent to */
-	unsigned long requestee;	/* times cpu was remotely requested */
-	unsigned long alltlb;	/* times all tlb's on this cpu were flushed */
-	unsigned long onetlb;	/* times just one tlb on this cpu was flushed */
-	unsigned long s_retry;	/* retries on source side timeouts */
-	unsigned long d_retry;	/* retries on destination side timeouts */
-	unsigned long sflush;	/* cycles spent in uv_flush_tlb_others */
-	unsigned long dflush;	/* cycles spent on destination side */
-	unsigned long retriesok; /* successes on retries */
-	unsigned long nomsg;	/* interrupts with no message */
-	unsigned long multmsg;	/* interrupts with multiple messages */
-	unsigned long ntargeted;/* nodes targeted */
-};
-
-static inline int bau_node_isset(int node, struct bau_target_nodemask *dstp)
-{
-	return constant_test_bit(node, &dstp->bits[0]);
-}
-static inline void bau_node_set(int node, struct bau_target_nodemask *dstp)
-{
-	__set_bit(node, &dstp->bits[0]);
-}
-static inline void bau_nodes_clear(struct bau_target_nodemask *dstp, int nbits)
-{
-	bitmap_zero(&dstp->bits[0], nbits);
-}
-
-static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
-{
-	bitmap_zero(&dstp->bits, nbits);
-}
-
-#define cpubit_isset(cpu, bau_local_cpumask) \
-	test_bit((cpu), (bau_local_cpumask).bits)
-
-extern int uv_flush_tlb_others(cpumask_t *, struct mm_struct *, unsigned long);
-extern void uv_bau_message_intr1(void);
-extern void uv_bau_timeout_intr1(void);
-
-#endif /* ASM_X86__UV__UV_BAU_H */
diff --git a/include/asm-x86/uv/uv_hub.h b/include/asm-x86/uv/uv_hub.h
deleted file mode 100644
index bdb5b01afbf5..000000000000
--- a/include/asm-x86/uv/uv_hub.h
+++ /dev/null
@@ -1,354 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * SGI UV architectural definitions
- *
- * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef ASM_X86__UV__UV_HUB_H
-#define ASM_X86__UV__UV_HUB_H
-
-#include <linux/numa.h>
-#include <linux/percpu.h>
-#include <asm/types.h>
-#include <asm/percpu.h>
-
-
-/*
- * Addressing Terminology
- *
- *	M       - The low M bits of a physical address represent the offset
- *		  into the blade local memory. RAM memory on a blade is physically
- *		  contiguous (although various IO spaces may punch holes in
- *		  it)..
- *
- * 	N	- Number of bits in the node portion of a socket physical
- * 		  address.
- *
- * 	NASID   - network ID of a router, Mbrick or Cbrick. Nasid values of
- * 	 	  routers always have low bit of 1, C/MBricks have low bit
- * 		  equal to 0. Most addressing macros that target UV hub chips
- * 		  right shift the NASID by 1 to exclude the always-zero bit.
- * 		  NASIDs contain up to 15 bits.
- *
- *	GNODE   - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
- *		  of nasids.
- *
- * 	PNODE   - the low N bits of the GNODE. The PNODE is the most useful variant
- * 		  of the nasid for socket usage.
- *
- *
- *  NumaLink Global Physical Address Format:
- *  +--------------------------------+---------------------+
- *  |00..000|      GNODE             |      NodeOffset     |
- *  +--------------------------------+---------------------+
- *          |<-------53 - M bits --->|<--------M bits ----->
- *
- *	M - number of node offset bits (35 .. 40)
- *
- *
- *  Memory/UV-HUB Processor Socket Address Format:
- *  +----------------+---------------+---------------------+
- *  |00..000000000000|   PNODE       |      NodeOffset     |
- *  +----------------+---------------+---------------------+
- *                   <--- N bits --->|<--------M bits ----->
- *
- *	M - number of node offset bits (35 .. 40)
- *	N - number of PNODE bits (0 .. 10)
- *
- *		Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
- *		The actual values are configuration dependent and are set at
- *		boot time. M & N values are set by the hardware/BIOS at boot.
- *
- *
- * APICID format
- * 	NOTE!!!!!! This is the current format of the APICID. However, code
- * 	should assume that this will change in the future. Use functions
- * 	in this file for all APICID bit manipulations and conversion.
- *
- * 		1111110000000000
- * 		5432109876543210
- *		pppppppppplc0cch
- *		sssssssssss
- *
- *			p  = pnode bits
- *			l =  socket number on board
- *			c  = core
- *			h  = hyperthread
- *			s  = bits that are in the SOCKET_ID CSR
- *
- *	Note: Processor only supports 12 bits in the APICID register. The ACPI
- *	      tables hold all 16 bits. Software needs to be aware of this.
- *
- * 	      Unless otherwise specified, all references to APICID refer to
- * 	      the FULL value contained in ACPI tables, not the subset in the
- * 	      processor APICID register.
- */
-
-
-/*
- * Maximum number of bricks in all partitions and in all coherency domains.
- * This is the total number of bricks accessible in the numalink fabric. It
- * includes all C & M bricks. Routers are NOT included.
- *
- * This value is also the value of the maximum number of non-router NASIDs
- * in the numalink fabric.
- *
- * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
- */
-#define UV_MAX_NUMALINK_BLADES	16384
-
-/*
- * Maximum number of C/Mbricks within a software SSI (hardware may support
- * more).
- */
-#define UV_MAX_SSI_BLADES	256
-
-/*
- * The largest possible NASID of a C or M brick (+ 2)
- */
-#define UV_MAX_NASID_VALUE	(UV_MAX_NUMALINK_NODES * 2)
-
-/*
- * The following defines attributes of the HUB chip. These attributes are
- * frequently referenced and are kept in the per-cpu data areas of each cpu.
- * They are kept together in a struct to minimize cache misses.
- */
-struct uv_hub_info_s {
-	unsigned long	global_mmr_base;
-	unsigned long	gpa_mask;
-	unsigned long	gnode_upper;
-	unsigned long	lowmem_remap_top;
-	unsigned long	lowmem_remap_base;
-	unsigned short	pnode;
-	unsigned short	pnode_mask;
-	unsigned short	coherency_domain_number;
-	unsigned short	numa_blade_id;
-	unsigned char	blade_processor_id;
-	unsigned char	m_val;
-	unsigned char	n_val;
-};
-DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
-#define uv_hub_info 		(&__get_cpu_var(__uv_hub_info))
-#define uv_cpu_hub_info(cpu)	(&per_cpu(__uv_hub_info, cpu))
-
-/*
- * Local & Global MMR space macros.
- * 	Note: macros are intended to be used ONLY by inline functions
- * 	in this file - not by other kernel code.
- * 		n -  NASID (full 15-bit global nasid)
- * 		g -  GNODE (full 15-bit global nasid, right shifted 1)
- * 		p -  PNODE (local part of nsids, right shifted 1)
- */
-#define UV_NASID_TO_PNODE(n)		(((n) >> 1) & uv_hub_info->pnode_mask)
-#define UV_PNODE_TO_NASID(p)		(((p) << 1) | uv_hub_info->gnode_upper)
-
-#define UV_LOCAL_MMR_BASE		0xf4000000UL
-#define UV_GLOBAL_MMR32_BASE		0xf8000000UL
-#define UV_GLOBAL_MMR64_BASE		(uv_hub_info->global_mmr_base)
-#define UV_LOCAL_MMR_SIZE		(64UL * 1024 * 1024)
-#define UV_GLOBAL_MMR32_SIZE		(64UL * 1024 * 1024)
-
-#define UV_GLOBAL_MMR32_PNODE_SHIFT	15
-#define UV_GLOBAL_MMR64_PNODE_SHIFT	26
-
-#define UV_GLOBAL_MMR32_PNODE_BITS(p)	((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
-
-#define UV_GLOBAL_MMR64_PNODE_BITS(p)					\
-	((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)
-
-#define UV_APIC_PNODE_SHIFT	6
-
-/*
- * Macros for converting between kernel virtual addresses, socket local physical
- * addresses, and UV global physical addresses.
- * 	Note: use the standard __pa() & __va() macros for converting
- * 	      between socket virtual and socket physical addresses.
- */
-
-/* socket phys RAM --> UV global physical address */
-static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
-{
-	if (paddr < uv_hub_info->lowmem_remap_top)
-		paddr += uv_hub_info->lowmem_remap_base;
-	return paddr | uv_hub_info->gnode_upper;
-}
-
-
-/* socket virtual --> UV global physical address */
-static inline unsigned long uv_gpa(void *v)
-{
-	return __pa(v) | uv_hub_info->gnode_upper;
-}
-
-/* socket virtual --> UV global physical address */
-static inline void *uv_vgpa(void *v)
-{
-	return (void *)uv_gpa(v);
-}
-
-/* UV global physical address --> socket virtual */
-static inline void *uv_va(unsigned long gpa)
-{
-	return __va(gpa & uv_hub_info->gpa_mask);
-}
-
-/* pnode, offset --> socket virtual */
-static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
-{
-	return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
-}
-
-
-/*
- * Extract a PNODE from an APICID (full apicid, not processor subset)
- */
-static inline int uv_apicid_to_pnode(int apicid)
-{
-	return (apicid >> UV_APIC_PNODE_SHIFT);
-}
-
-/*
- * Access global MMRs using the low memory MMR32 space. This region supports
- * faster MMR access but not all MMRs are accessible in this space.
- */
-static inline unsigned long *uv_global_mmr32_address(int pnode,
-				unsigned long offset)
-{
-	return __va(UV_GLOBAL_MMR32_BASE |
-		       UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
-}
-
-static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
-				 unsigned long val)
-{
-	*uv_global_mmr32_address(pnode, offset) = val;
-}
-
-static inline unsigned long uv_read_global_mmr32(int pnode,
-						 unsigned long offset)
-{
-	return *uv_global_mmr32_address(pnode, offset);
-}
-
-/*
- * Access Global MMR space using the MMR space located at the top of physical
- * memory.
- */
-static inline unsigned long *uv_global_mmr64_address(int pnode,
-				unsigned long offset)
-{
-	return __va(UV_GLOBAL_MMR64_BASE |
-		    UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
-}
-
-static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
-				unsigned long val)
-{
-	*uv_global_mmr64_address(pnode, offset) = val;
-}
-
-static inline unsigned long uv_read_global_mmr64(int pnode,
-						 unsigned long offset)
-{
-	return *uv_global_mmr64_address(pnode, offset);
-}
-
-/*
- * Access hub local MMRs. Faster than using global space but only local MMRs
- * are accessible.
- */
-static inline unsigned long *uv_local_mmr_address(unsigned long offset)
-{
-	return __va(UV_LOCAL_MMR_BASE | offset);
-}
-
-static inline unsigned long uv_read_local_mmr(unsigned long offset)
-{
-	return *uv_local_mmr_address(offset);
-}
-
-static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
-{
-	*uv_local_mmr_address(offset) = val;
-}
-
-/*
- * Structures and definitions for converting between cpu, node, pnode, and blade
- * numbers.
- */
-struct uv_blade_info {
-	unsigned short	nr_possible_cpus;
-	unsigned short	nr_online_cpus;
-	unsigned short	pnode;
-};
-extern struct uv_blade_info *uv_blade_info;
-extern short *uv_node_to_blade;
-extern short *uv_cpu_to_blade;
-extern short uv_possible_blades;
-
-/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
-static inline int uv_blade_processor_id(void)
-{
-	return uv_hub_info->blade_processor_id;
-}
-
-/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
-static inline int uv_numa_blade_id(void)
-{
-	return uv_hub_info->numa_blade_id;
-}
-
-/* Convert a cpu number to the the UV blade number */
-static inline int uv_cpu_to_blade_id(int cpu)
-{
-	return uv_cpu_to_blade[cpu];
-}
-
-/* Convert linux node number to the UV blade number */
-static inline int uv_node_to_blade_id(int nid)
-{
-	return uv_node_to_blade[nid];
-}
-
-/* Convert a blade id to the PNODE of the blade */
-static inline int uv_blade_to_pnode(int bid)
-{
-	return uv_blade_info[bid].pnode;
-}
-
-/* Determine the number of possible cpus on a blade */
-static inline int uv_blade_nr_possible_cpus(int bid)
-{
-	return uv_blade_info[bid].nr_possible_cpus;
-}
-
-/* Determine the number of online cpus on a blade */
-static inline int uv_blade_nr_online_cpus(int bid)
-{
-	return uv_blade_info[bid].nr_online_cpus;
-}
-
-/* Convert a cpu id to the PNODE of the blade containing the cpu */
-static inline int uv_cpu_to_pnode(int cpu)
-{
-	return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
-}
-
-/* Convert a linux node number to the PNODE of the blade */
-static inline int uv_node_to_pnode(int nid)
-{
-	return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
-}
-
-/* Maximum possible number of blades */
-static inline int uv_num_possible_blades(void)
-{
-	return uv_possible_blades;
-}
-
-#endif /* ASM_X86__UV__UV_HUB_H */
-
diff --git a/include/asm-x86/uv/uv_mmrs.h b/include/asm-x86/uv/uv_mmrs.h
deleted file mode 100644
index 8b03d89d2459..000000000000
--- a/include/asm-x86/uv/uv_mmrs.h
+++ /dev/null
@@ -1,1295 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * SGI UV MMR definitions
- *
- * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef ASM_X86__UV__UV_MMRS_H
-#define ASM_X86__UV__UV_MMRS_H
-
-#define UV_MMR_ENABLE		(1UL << 63)
-
-/* ========================================================================= */
-/*                           UVH_BAU_DATA_CONFIG                             */
-/* ========================================================================= */
-#define UVH_BAU_DATA_CONFIG 0x61680UL
-#define UVH_BAU_DATA_CONFIG_32 0x0438
-
-#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
-#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UVH_BAU_DATA_CONFIG_DM_SHFT 8
-#define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
-#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
-#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12
-#define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UVH_BAU_DATA_CONFIG_P_SHFT 13
-#define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
-#define UVH_BAU_DATA_CONFIG_T_SHFT 15
-#define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
-#define UVH_BAU_DATA_CONFIG_M_SHFT 16
-#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
-#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
-#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
-
-union uvh_bau_data_config_u {
-    unsigned long	v;
-    struct uvh_bau_data_config_s {
-	unsigned long	vector_  :  8;  /* RW */
-	unsigned long	dm       :  3;  /* RW */
-	unsigned long	destmode :  1;  /* RW */
-	unsigned long	status   :  1;  /* RO */
-	unsigned long	p        :  1;  /* RO */
-	unsigned long	rsvd_14  :  1;  /*    */
-	unsigned long	t        :  1;  /* RO */
-	unsigned long	m        :  1;  /* RW */
-	unsigned long	rsvd_17_31: 15;  /*    */
-	unsigned long	apic_id  : 32;  /* RW */
-    } s;
-};
-
-/* ========================================================================= */
-/*                           UVH_EVENT_OCCURRED0                             */
-/* ========================================================================= */
-#define UVH_EVENT_OCCURRED0 0x70000UL
-#define UVH_EVENT_OCCURRED0_32 0x005e8
-
-#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0
-#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
-#define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
-#define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
-#define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
-#define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
-#define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3
-#define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
-#define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4
-#define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
-#define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5
-#define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
-#define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6
-#define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
-#define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
-#define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
-#define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
-#define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
-#define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
-#define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
-#define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
-#define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
-#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
-#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
-#define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
-#define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
-#define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
-#define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
-#define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
-#define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
-#define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
-#define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
-#define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
-#define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
-#define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
-#define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
-#define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
-#define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
-#define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
-#define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
-#define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
-#define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
-#define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
-#define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
-#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
-#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
-#define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
-#define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
-#define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
-#define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
-#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
-#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
-#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
-#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
-#define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43
-#define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
-#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
-#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
-#define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45
-#define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
-#define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
-#define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
-#define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
-#define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
-#define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
-#define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
-#define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
-#define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
-#define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
-#define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
-#define UVH_EVENT_OCCURRED0_RTC0_SHFT 51
-#define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
-#define UVH_EVENT_OCCURRED0_RTC1_SHFT 52
-#define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
-#define UVH_EVENT_OCCURRED0_RTC2_SHFT 53
-#define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
-#define UVH_EVENT_OCCURRED0_RTC3_SHFT 54
-#define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
-#define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55
-#define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
-#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
-#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
-union uvh_event_occurred0_u {
-    unsigned long	v;
-    struct uvh_event_occurred0_s {
-	unsigned long	lb_hcerr             :  1;  /* RW, W1C */
-	unsigned long	gr0_hcerr            :  1;  /* RW, W1C */
-	unsigned long	gr1_hcerr            :  1;  /* RW, W1C */
-	unsigned long	lh_hcerr             :  1;  /* RW, W1C */
-	unsigned long	rh_hcerr             :  1;  /* RW, W1C */
-	unsigned long	xn_hcerr             :  1;  /* RW, W1C */
-	unsigned long	si_hcerr             :  1;  /* RW, W1C */
-	unsigned long	lb_aoerr0            :  1;  /* RW, W1C */
-	unsigned long	gr0_aoerr0           :  1;  /* RW, W1C */
-	unsigned long	gr1_aoerr0           :  1;  /* RW, W1C */
-	unsigned long	lh_aoerr0            :  1;  /* RW, W1C */
-	unsigned long	rh_aoerr0            :  1;  /* RW, W1C */
-	unsigned long	xn_aoerr0            :  1;  /* RW, W1C */
-	unsigned long	si_aoerr0            :  1;  /* RW, W1C */
-	unsigned long	lb_aoerr1            :  1;  /* RW, W1C */
-	unsigned long	gr0_aoerr1           :  1;  /* RW, W1C */
-	unsigned long	gr1_aoerr1           :  1;  /* RW, W1C */
-	unsigned long	lh_aoerr1            :  1;  /* RW, W1C */
-	unsigned long	rh_aoerr1            :  1;  /* RW, W1C */
-	unsigned long	xn_aoerr1            :  1;  /* RW, W1C */
-	unsigned long	si_aoerr1            :  1;  /* RW, W1C */
-	unsigned long	rh_vpi_int           :  1;  /* RW, W1C */
-	unsigned long	system_shutdown_int  :  1;  /* RW, W1C */
-	unsigned long	lb_irq_int_0         :  1;  /* RW, W1C */
-	unsigned long	lb_irq_int_1         :  1;  /* RW, W1C */
-	unsigned long	lb_irq_int_2         :  1;  /* RW, W1C */
-	unsigned long	lb_irq_int_3         :  1;  /* RW, W1C */
-	unsigned long	lb_irq_int_4         :  1;  /* RW, W1C */
-	unsigned long	lb_irq_int_5         :  1;  /* RW, W1C */
-	unsigned long	lb_irq_int_6         :  1;  /* RW, W1C */
-	unsigned long	lb_irq_int_7         :  1;  /* RW, W1C */
-	unsigned long	lb_irq_int_8         :  1;  /* RW, W1C */
-	unsigned long	lb_irq_int_9         :  1;  /* RW, W1C */
-	unsigned long	lb_irq_int_10        :  1;  /* RW, W1C */
-	unsigned long	lb_irq_int_11        :  1;  /* RW, W1C */
-	unsigned long	lb_irq_int_12        :  1;  /* RW, W1C */
-	unsigned long	lb_irq_int_13        :  1;  /* RW, W1C */
-	unsigned long	lb_irq_int_14        :  1;  /* RW, W1C */
-	unsigned long	lb_irq_int_15        :  1;  /* RW, W1C */
-	unsigned long	l1_nmi_int           :  1;  /* RW, W1C */
-	unsigned long	stop_clock           :  1;  /* RW, W1C */
-	unsigned long	asic_to_l1           :  1;  /* RW, W1C */
-	unsigned long	l1_to_asic           :  1;  /* RW, W1C */
-	unsigned long	ltc_int              :  1;  /* RW, W1C */
-	unsigned long	la_seq_trigger       :  1;  /* RW, W1C */
-	unsigned long	ipi_int              :  1;  /* RW, W1C */
-	unsigned long	extio_int0           :  1;  /* RW, W1C */
-	unsigned long	extio_int1           :  1;  /* RW, W1C */
-	unsigned long	extio_int2           :  1;  /* RW, W1C */
-	unsigned long	extio_int3           :  1;  /* RW, W1C */
-	unsigned long	profile_int          :  1;  /* RW, W1C */
-	unsigned long	rtc0                 :  1;  /* RW, W1C */
-	unsigned long	rtc1                 :  1;  /* RW, W1C */
-	unsigned long	rtc2                 :  1;  /* RW, W1C */
-	unsigned long	rtc3                 :  1;  /* RW, W1C */
-	unsigned long	bau_data             :  1;  /* RW, W1C */
-	unsigned long	power_management_req :  1;  /* RW, W1C */
-	unsigned long	rsvd_57_63           :  7;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                        UVH_EVENT_OCCURRED0_ALIAS                          */
-/* ========================================================================= */
-#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
-#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0
-
-/* ========================================================================= */
-/*                               UVH_INT_CMPB                                */
-/* ========================================================================= */
-#define UVH_INT_CMPB 0x22080UL
-
-#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
-#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
-
-union uvh_int_cmpb_u {
-    unsigned long	v;
-    struct uvh_int_cmpb_s {
-	unsigned long	real_time_cmpb : 56;  /* RW */
-	unsigned long	rsvd_56_63     :  8;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                               UVH_INT_CMPC                                */
-/* ========================================================================= */
-#define UVH_INT_CMPC 0x22100UL
-
-#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
-#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL
-
-union uvh_int_cmpc_u {
-    unsigned long	v;
-    struct uvh_int_cmpc_s {
-	unsigned long	real_time_cmpc : 56;  /* RW */
-	unsigned long	rsvd_56_63     :  8;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                               UVH_INT_CMPD                                */
-/* ========================================================================= */
-#define UVH_INT_CMPD 0x22180UL
-
-#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
-#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL
-
-union uvh_int_cmpd_u {
-    unsigned long	v;
-    struct uvh_int_cmpd_s {
-	unsigned long	real_time_cmpd : 56;  /* RW */
-	unsigned long	rsvd_56_63     :  8;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                               UVH_IPI_INT                                 */
-/* ========================================================================= */
-#define UVH_IPI_INT 0x60500UL
-#define UVH_IPI_INT_32 0x0348
-
-#define UVH_IPI_INT_VECTOR_SHFT 0
-#define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
-#define UVH_IPI_INT_DELIVERY_MODE_SHFT 8
-#define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL
-#define UVH_IPI_INT_DESTMODE_SHFT 11
-#define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL
-#define UVH_IPI_INT_APIC_ID_SHFT 16
-#define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
-#define UVH_IPI_INT_SEND_SHFT 63
-#define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL
-
-union uvh_ipi_int_u {
-    unsigned long	v;
-    struct uvh_ipi_int_s {
-	unsigned long	vector_       :  8;  /* RW */
-	unsigned long	delivery_mode :  3;  /* RW */
-	unsigned long	destmode      :  1;  /* RW */
-	unsigned long	rsvd_12_15    :  4;  /*    */
-	unsigned long	apic_id       : 32;  /* RW */
-	unsigned long	rsvd_48_62    : 15;  /*    */
-	unsigned long	send          :  1;  /* WP */
-    } s;
-};
-
-/* ========================================================================= */
-/*                   UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST                     */
-/* ========================================================================= */
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x009c0
-
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
-
-union uvh_lb_bau_intd_payload_queue_first_u {
-    unsigned long	v;
-    struct uvh_lb_bau_intd_payload_queue_first_s {
-	unsigned long	rsvd_0_3:  4;  /*    */
-	unsigned long	address : 39;  /* RW */
-	unsigned long	rsvd_43_48:  6;  /*    */
-	unsigned long	node_id : 14;  /* RW */
-	unsigned long	rsvd_63 :  1;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST                     */
-/* ========================================================================= */
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x009c8
-
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
-
-union uvh_lb_bau_intd_payload_queue_last_u {
-    unsigned long	v;
-    struct uvh_lb_bau_intd_payload_queue_last_s {
-	unsigned long	rsvd_0_3:  4;  /*    */
-	unsigned long	address : 39;  /* RW */
-	unsigned long	rsvd_43_63: 21;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL                     */
-/* ========================================================================= */
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x009d0
-
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
-
-union uvh_lb_bau_intd_payload_queue_tail_u {
-    unsigned long	v;
-    struct uvh_lb_bau_intd_payload_queue_tail_s {
-	unsigned long	rsvd_0_3:  4;  /*    */
-	unsigned long	address : 39;  /* RW */
-	unsigned long	rsvd_43_63: 21;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                   UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE                    */
-/* ========================================================================= */
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x0a68
-
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
-union uvh_lb_bau_intd_software_acknowledge_u {
-    unsigned long	v;
-    struct uvh_lb_bau_intd_software_acknowledge_s {
-	unsigned long	pending_0 :  1;  /* RW, W1C */
-	unsigned long	pending_1 :  1;  /* RW, W1C */
-	unsigned long	pending_2 :  1;  /* RW, W1C */
-	unsigned long	pending_3 :  1;  /* RW, W1C */
-	unsigned long	pending_4 :  1;  /* RW, W1C */
-	unsigned long	pending_5 :  1;  /* RW, W1C */
-	unsigned long	pending_6 :  1;  /* RW, W1C */
-	unsigned long	pending_7 :  1;  /* RW, W1C */
-	unsigned long	timeout_0 :  1;  /* RW, W1C */
-	unsigned long	timeout_1 :  1;  /* RW, W1C */
-	unsigned long	timeout_2 :  1;  /* RW, W1C */
-	unsigned long	timeout_3 :  1;  /* RW, W1C */
-	unsigned long	timeout_4 :  1;  /* RW, W1C */
-	unsigned long	timeout_5 :  1;  /* RW, W1C */
-	unsigned long	timeout_6 :  1;  /* RW, W1C */
-	unsigned long	timeout_7 :  1;  /* RW, W1C */
-	unsigned long	rsvd_16_63: 48;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS                 */
-/* ========================================================================= */
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0a70
-
-/* ========================================================================= */
-/*                     UVH_LB_BAU_SB_ACTIVATION_CONTROL                      */
-/* ========================================================================= */
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x009a8
-
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL
-
-union uvh_lb_bau_sb_activation_control_u {
-    unsigned long	v;
-    struct uvh_lb_bau_sb_activation_control_s {
-	unsigned long	index :  6;  /* RW */
-	unsigned long	rsvd_6_61: 56;  /*    */
-	unsigned long	push  :  1;  /* WP */
-	unsigned long	init  :  1;  /* WP */
-    } s;
-};
-
-/* ========================================================================= */
-/*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_0                      */
-/* ========================================================================= */
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x009b0
-
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
-
-union uvh_lb_bau_sb_activation_status_0_u {
-    unsigned long	v;
-    struct uvh_lb_bau_sb_activation_status_0_s {
-	unsigned long	status : 64;  /* RW */
-    } s;
-};
-
-/* ========================================================================= */
-/*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_1                      */
-/* ========================================================================= */
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x009b8
-
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
-
-union uvh_lb_bau_sb_activation_status_1_u {
-    unsigned long	v;
-    struct uvh_lb_bau_sb_activation_status_1_s {
-	unsigned long	status : 64;  /* RW */
-    } s;
-};
-
-/* ========================================================================= */
-/*                      UVH_LB_BAU_SB_DESCRIPTOR_BASE                        */
-/* ========================================================================= */
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x009a0
-
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL
-
-union uvh_lb_bau_sb_descriptor_base_u {
-    unsigned long	v;
-    struct uvh_lb_bau_sb_descriptor_base_s {
-	unsigned long	rsvd_0_11    : 12;  /*    */
-	unsigned long	page_address : 31;  /* RW */
-	unsigned long	rsvd_43_48   :  6;  /*    */
-	unsigned long	node_id      : 14;  /* RW */
-	unsigned long	rsvd_63      :  1;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                      UVH_LB_MCAST_AOERR0_RPT_ENABLE                       */
-/* ========================================================================= */
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE 0x50b20UL
-
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_SHFT 0
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_MASK 0x0000000000000001UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_SHFT 1
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_MASK 0x0000000000000002UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_SHFT 2
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_MASK 0x0000000000000004UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_SHFT 3
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_MASK 0x0000000000000008UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_SHFT 4
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_MASK 0x0000000000000010UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_SHFT 5
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_MASK 0x0000000000000020UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_SHFT 6
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_MASK 0x0000000000000040UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_SHFT 7
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_MASK 0x0000000000000080UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_SHFT 8
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_MASK 0x0000000000000100UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_SHFT 9
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_MASK 0x0000000000000200UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_SHFT 10
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_MASK 0x0000000000000400UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_SHFT 11
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_MASK 0x0000000000000800UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_SHFT 12
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_MASK 0x0000000000001000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_SHFT 13
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_MASK 0x0000000000002000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_SHFT 14
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_MASK 0x0000000000004000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_SHFT 15
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_MASK 0x0000000000008000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_SHFT 16
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_MASK 0x0000000000010000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_SHFT 17
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_MASK 0x0000000000020000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_SHFT 18
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_MASK 0x0000000000040000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_SHFT 19
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_MASK 0x0000000000080000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_SHFT 20
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_MASK 0x0000000000100000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_SHFT 21
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_MASK 0x0000000000200000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_AMO_TIMEOUT_SHFT 22
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_AMO_TIMEOUT_MASK 0x0000000000400000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_PUT_TIMEOUT_SHFT 23
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_PUT_TIMEOUT_MASK 0x0000000000800000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_SHFT 24
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_MASK 0x0000000001000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_SHFT 25
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_MASK 0x0000000002000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_SHFT 26
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_MASK 0x0000000004000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_SHFT 27
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_MASK 0x0000000008000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_SHFT 28
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_MASK 0x0000000010000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_SHFT 29
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_MASK 0x0000000020000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_SHFT 30
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_MASK 0x0000000040000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_SHFT 31
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_MASK 0x0000000080000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_SHFT 32
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_MASK 0x0000000100000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_SHFT 33
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_MASK 0x0000000200000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_SHFT 34
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_MASK 0x0000000400000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_SHFT 35
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_MASK 0x0000000800000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_SHFT 36
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_MASK 0x0000001000000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_SHFT 37
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_MASK 0x0000002000000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_SHFT 38
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_MASK 0x0000004000000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_SHFT 39
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_MASK 0x0000008000000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_SHFT 40
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_MASK 0x0000010000000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_SHFT 41
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_MASK 0x0000020000000000UL
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_SHFT 42
-#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_MASK 0x0000040000000000UL
-
-union uvh_lb_mcast_aoerr0_rpt_enable_u {
-    unsigned long	v;
-    struct uvh_lb_mcast_aoerr0_rpt_enable_s {
-	unsigned long	mcast_obese_msg                         :  1;  /* RW */
-	unsigned long	mcast_data_sb_err                       :  1;  /* RW */
-	unsigned long	mcast_nack_buff_parity                  :  1;  /* RW */
-	unsigned long	mcast_timeout                           :  1;  /* RW */
-	unsigned long	mcast_inactive_reply                    :  1;  /* RW */
-	unsigned long	mcast_upgrade_error                     :  1;  /* RW */
-	unsigned long	mcast_reg_count_underflow               :  1;  /* RW */
-	unsigned long	mcast_rep_obese_msg                     :  1;  /* RW */
-	unsigned long	ucache_req_runt_msg                     :  1;  /* RW */
-	unsigned long	ucache_req_obese_msg                    :  1;  /* RW */
-	unsigned long	ucache_req_data_sb_err                  :  1;  /* RW */
-	unsigned long	ucache_rep_runt_msg                     :  1;  /* RW */
-	unsigned long	ucache_rep_obese_msg                    :  1;  /* RW */
-	unsigned long	ucache_rep_data_sb_err                  :  1;  /* RW */
-	unsigned long	ucache_rep_command_err                  :  1;  /* RW */
-	unsigned long	ucache_pend_timeout                     :  1;  /* RW */
-	unsigned long	macc_req_runt_msg                       :  1;  /* RW */
-	unsigned long	macc_req_obese_msg                      :  1;  /* RW */
-	unsigned long	macc_req_data_sb_err                    :  1;  /* RW */
-	unsigned long	macc_rep_runt_msg                       :  1;  /* RW */
-	unsigned long	macc_rep_obese_msg                      :  1;  /* RW */
-	unsigned long	macc_rep_data_sb_err                    :  1;  /* RW */
-	unsigned long	macc_amo_timeout                        :  1;  /* RW */
-	unsigned long	macc_put_timeout                        :  1;  /* RW */
-	unsigned long	macc_spurious_event                     :  1;  /* RW */
-	unsigned long	ioh_destination_table_parity            :  1;  /* RW */
-	unsigned long	get_had_error_reply                     :  1;  /* RW */
-	unsigned long	get_timeout                             :  1;  /* RW */
-	unsigned long	lock_manager_had_error_reply            :  1;  /* RW */
-	unsigned long	put_had_error_reply                     :  1;  /* RW */
-	unsigned long	put_timeout                             :  1;  /* RW */
-	unsigned long	sb_activation_overrun                   :  1;  /* RW */
-	unsigned long	completed_gb_activation_had_error_reply :  1;  /* RW */
-	unsigned long	completed_gb_activation_timeout         :  1;  /* RW */
-	unsigned long	descriptor_buffer_0_parity              :  1;  /* RW */
-	unsigned long	descriptor_buffer_1_parity              :  1;  /* RW */
-	unsigned long	socket_destination_table_parity         :  1;  /* RW */
-	unsigned long	bau_reply_payload_corruption            :  1;  /* RW */
-	unsigned long	io_port_destination_table_parity        :  1;  /* RW */
-	unsigned long	intd_soft_ack_timeout                   :  1;  /* RW */
-	unsigned long	int_rep_obese_msg                       :  1;  /* RW */
-	unsigned long	int_rep_command_err                     :  1;  /* RW */
-	unsigned long	int_timeout                             :  1;  /* RW */
-	unsigned long	rsvd_43_63                              : 21;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                          UVH_LOCAL_INT0_CONFIG                            */
-/* ========================================================================= */
-#define UVH_LOCAL_INT0_CONFIG 0x61000UL
-
-#define UVH_LOCAL_INT0_CONFIG_VECTOR_SHFT 0
-#define UVH_LOCAL_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UVH_LOCAL_INT0_CONFIG_DM_SHFT 8
-#define UVH_LOCAL_INT0_CONFIG_DM_MASK 0x0000000000000700UL
-#define UVH_LOCAL_INT0_CONFIG_DESTMODE_SHFT 11
-#define UVH_LOCAL_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UVH_LOCAL_INT0_CONFIG_STATUS_SHFT 12
-#define UVH_LOCAL_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UVH_LOCAL_INT0_CONFIG_P_SHFT 13
-#define UVH_LOCAL_INT0_CONFIG_P_MASK 0x0000000000002000UL
-#define UVH_LOCAL_INT0_CONFIG_T_SHFT 15
-#define UVH_LOCAL_INT0_CONFIG_T_MASK 0x0000000000008000UL
-#define UVH_LOCAL_INT0_CONFIG_M_SHFT 16
-#define UVH_LOCAL_INT0_CONFIG_M_MASK 0x0000000000010000UL
-#define UVH_LOCAL_INT0_CONFIG_APIC_ID_SHFT 32
-#define UVH_LOCAL_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
-
-union uvh_local_int0_config_u {
-    unsigned long	v;
-    struct uvh_local_int0_config_s {
-	unsigned long	vector_  :  8;  /* RW */
-	unsigned long	dm       :  3;  /* RW */
-	unsigned long	destmode :  1;  /* RW */
-	unsigned long	status   :  1;  /* RO */
-	unsigned long	p        :  1;  /* RO */
-	unsigned long	rsvd_14  :  1;  /*    */
-	unsigned long	t        :  1;  /* RO */
-	unsigned long	m        :  1;  /* RW */
-	unsigned long	rsvd_17_31: 15;  /*    */
-	unsigned long	apic_id  : 32;  /* RW */
-    } s;
-};
-
-/* ========================================================================= */
-/*                          UVH_LOCAL_INT0_ENABLE                            */
-/* ========================================================================= */
-#define UVH_LOCAL_INT0_ENABLE 0x65000UL
-
-#define UVH_LOCAL_INT0_ENABLE_LB_HCERR_SHFT 0
-#define UVH_LOCAL_INT0_ENABLE_LB_HCERR_MASK 0x0000000000000001UL
-#define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_SHFT 1
-#define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_MASK 0x0000000000000002UL
-#define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_SHFT 2
-#define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_MASK 0x0000000000000004UL
-#define UVH_LOCAL_INT0_ENABLE_LH_HCERR_SHFT 3
-#define UVH_LOCAL_INT0_ENABLE_LH_HCERR_MASK 0x0000000000000008UL
-#define UVH_LOCAL_INT0_ENABLE_RH_HCERR_SHFT 4
-#define UVH_LOCAL_INT0_ENABLE_RH_HCERR_MASK 0x0000000000000010UL
-#define UVH_LOCAL_INT0_ENABLE_XN_HCERR_SHFT 5
-#define UVH_LOCAL_INT0_ENABLE_XN_HCERR_MASK 0x0000000000000020UL
-#define UVH_LOCAL_INT0_ENABLE_SI_HCERR_SHFT 6
-#define UVH_LOCAL_INT0_ENABLE_SI_HCERR_MASK 0x0000000000000040UL
-#define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_SHFT 7
-#define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_MASK 0x0000000000000080UL
-#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_SHFT 8
-#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_MASK 0x0000000000000100UL
-#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_SHFT 9
-#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_MASK 0x0000000000000200UL
-#define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_SHFT 10
-#define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_MASK 0x0000000000000400UL
-#define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_SHFT 11
-#define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_MASK 0x0000000000000800UL
-#define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_SHFT 12
-#define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_MASK 0x0000000000001000UL
-#define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_SHFT 13
-#define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_MASK 0x0000000000002000UL
-#define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_SHFT 14
-#define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_MASK 0x0000000000004000UL
-#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_SHFT 15
-#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_MASK 0x0000000000008000UL
-#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_SHFT 16
-#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_MASK 0x0000000000010000UL
-#define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_SHFT 17
-#define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_MASK 0x0000000000020000UL
-#define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_SHFT 18
-#define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_MASK 0x0000000000040000UL
-#define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_SHFT 19
-#define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_MASK 0x0000000000080000UL
-#define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_SHFT 20
-#define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_MASK 0x0000000000100000UL
-#define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_SHFT 21
-#define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_MASK 0x0000000000200000UL
-#define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 22
-#define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_SHFT 23
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_MASK 0x0000000000800000UL
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_SHFT 24
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_MASK 0x0000000001000000UL
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_SHFT 25
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_MASK 0x0000000002000000UL
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_SHFT 26
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_MASK 0x0000000004000000UL
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_SHFT 27
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_MASK 0x0000000008000000UL
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_SHFT 28
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_MASK 0x0000000010000000UL
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_SHFT 29
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_MASK 0x0000000020000000UL
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_SHFT 30
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_MASK 0x0000000040000000UL
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_SHFT 31
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_MASK 0x0000000080000000UL
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_SHFT 32
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_MASK 0x0000000100000000UL
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_SHFT 33
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_MASK 0x0000000200000000UL
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_SHFT 34
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_MASK 0x0000000400000000UL
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_SHFT 35
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_MASK 0x0000000800000000UL
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_SHFT 36
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_MASK 0x0000001000000000UL
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_SHFT 37
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_MASK 0x0000002000000000UL
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_SHFT 38
-#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_MASK 0x0000004000000000UL
-#define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_SHFT 39
-#define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_MASK 0x0000008000000000UL
-#define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_SHFT 40
-#define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_MASK 0x0000010000000000UL
-#define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_SHFT 41
-#define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_MASK 0x0000020000000000UL
-#define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_SHFT 42
-#define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_MASK 0x0000040000000000UL
-#define UVH_LOCAL_INT0_ENABLE_LTC_INT_SHFT 43
-#define UVH_LOCAL_INT0_ENABLE_LTC_INT_MASK 0x0000080000000000UL
-#define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_SHFT 44
-#define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
-
-union uvh_local_int0_enable_u {
-    unsigned long	v;
-    struct uvh_local_int0_enable_s {
-	unsigned long	lb_hcerr            :  1;  /* RW */
-	unsigned long	gr0_hcerr           :  1;  /* RW */
-	unsigned long	gr1_hcerr           :  1;  /* RW */
-	unsigned long	lh_hcerr            :  1;  /* RW */
-	unsigned long	rh_hcerr            :  1;  /* RW */
-	unsigned long	xn_hcerr            :  1;  /* RW */
-	unsigned long	si_hcerr            :  1;  /* RW */
-	unsigned long	lb_aoerr0           :  1;  /* RW */
-	unsigned long	gr0_aoerr0          :  1;  /* RW */
-	unsigned long	gr1_aoerr0          :  1;  /* RW */
-	unsigned long	lh_aoerr0           :  1;  /* RW */
-	unsigned long	rh_aoerr0           :  1;  /* RW */
-	unsigned long	xn_aoerr0           :  1;  /* RW */
-	unsigned long	si_aoerr0           :  1;  /* RW */
-	unsigned long	lb_aoerr1           :  1;  /* RW */
-	unsigned long	gr0_aoerr1          :  1;  /* RW */
-	unsigned long	gr1_aoerr1          :  1;  /* RW */
-	unsigned long	lh_aoerr1           :  1;  /* RW */
-	unsigned long	rh_aoerr1           :  1;  /* RW */
-	unsigned long	xn_aoerr1           :  1;  /* RW */
-	unsigned long	si_aoerr1           :  1;  /* RW */
-	unsigned long	rh_vpi_int          :  1;  /* RW */
-	unsigned long	system_shutdown_int :  1;  /* RW */
-	unsigned long	lb_irq_int_0        :  1;  /* RW */
-	unsigned long	lb_irq_int_1        :  1;  /* RW */
-	unsigned long	lb_irq_int_2        :  1;  /* RW */
-	unsigned long	lb_irq_int_3        :  1;  /* RW */
-	unsigned long	lb_irq_int_4        :  1;  /* RW */
-	unsigned long	lb_irq_int_5        :  1;  /* RW */
-	unsigned long	lb_irq_int_6        :  1;  /* RW */
-	unsigned long	lb_irq_int_7        :  1;  /* RW */
-	unsigned long	lb_irq_int_8        :  1;  /* RW */
-	unsigned long	lb_irq_int_9        :  1;  /* RW */
-	unsigned long	lb_irq_int_10       :  1;  /* RW */
-	unsigned long	lb_irq_int_11       :  1;  /* RW */
-	unsigned long	lb_irq_int_12       :  1;  /* RW */
-	unsigned long	lb_irq_int_13       :  1;  /* RW */
-	unsigned long	lb_irq_int_14       :  1;  /* RW */
-	unsigned long	lb_irq_int_15       :  1;  /* RW */
-	unsigned long	l1_nmi_int          :  1;  /* RW */
-	unsigned long	stop_clock          :  1;  /* RW */
-	unsigned long	asic_to_l1          :  1;  /* RW */
-	unsigned long	l1_to_asic          :  1;  /* RW */
-	unsigned long	ltc_int             :  1;  /* RW */
-	unsigned long	la_seq_trigger      :  1;  /* RW */
-	unsigned long	rsvd_45_63          : 19;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                               UVH_NODE_ID                                 */
-/* ========================================================================= */
-#define UVH_NODE_ID 0x0UL
-
-#define UVH_NODE_ID_FORCE1_SHFT 0
-#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
-#define UVH_NODE_ID_MANUFACTURER_SHFT 1
-#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
-#define UVH_NODE_ID_PART_NUMBER_SHFT 12
-#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
-#define UVH_NODE_ID_REVISION_SHFT 28
-#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
-#define UVH_NODE_ID_NODE_ID_SHFT 32
-#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
-#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
-#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
-#define UVH_NODE_ID_NI_PORT_SHFT 56
-#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
-
-union uvh_node_id_u {
-    unsigned long	v;
-    struct uvh_node_id_s {
-	unsigned long	force1        :  1;  /* RO */
-	unsigned long	manufacturer  : 11;  /* RO */
-	unsigned long	part_number   : 16;  /* RO */
-	unsigned long	revision      :  4;  /* RO */
-	unsigned long	node_id       : 15;  /* RW */
-	unsigned long	rsvd_47       :  1;  /*    */
-	unsigned long	nodes_per_bit :  7;  /* RW */
-	unsigned long	rsvd_55       :  1;  /*    */
-	unsigned long	ni_port       :  4;  /* RO */
-	unsigned long	rsvd_60_63    :  4;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                          UVH_NODE_PRESENT_TABLE                           */
-/* ========================================================================= */
-#define UVH_NODE_PRESENT_TABLE 0x1400UL
-#define UVH_NODE_PRESENT_TABLE_DEPTH 16
-
-#define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0
-#define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL
-
-union uvh_node_present_table_u {
-    unsigned long	v;
-    struct uvh_node_present_table_s {
-	unsigned long	nodes : 64;  /* RW */
-    } s;
-};
-
-/* ========================================================================= */
-/*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR                  */
-/* ========================================================================= */
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
-
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
-
-union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
-    unsigned long	v;
-    struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
-	unsigned long	rsvd_0_23 : 24;  /*    */
-	unsigned long	dest_base : 22;  /* RW */
-	unsigned long	rsvd_46_63: 18;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR                  */
-/* ========================================================================= */
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
-
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
-
-union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
-    unsigned long	v;
-    struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
-	unsigned long	rsvd_0_23 : 24;  /*    */
-	unsigned long	dest_base : 22;  /* RW */
-	unsigned long	rsvd_46_63: 18;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR                  */
-/* ========================================================================= */
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
-
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
-
-union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
-    unsigned long	v;
-    struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
-	unsigned long	rsvd_0_23 : 24;  /*    */
-	unsigned long	dest_base : 22;  /* RW */
-	unsigned long	rsvd_46_63: 18;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                    UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR                      */
-/* ========================================================================= */
-#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR 0x1600020UL
-
-#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT 26
-#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
-#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
-#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
-
-union uvh_rh_gam_cfg_overlay_config_mmr_u {
-    unsigned long	v;
-    struct uvh_rh_gam_cfg_overlay_config_mmr_s {
-	unsigned long	rsvd_0_25: 26;  /*    */
-	unsigned long	base   : 20;  /* RW */
-	unsigned long	rsvd_46_62: 17;  /*    */
-	unsigned long	enable :  1;  /* RW */
-    } s;
-};
-
-/* ========================================================================= */
-/*                    UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR                      */
-/* ========================================================================= */
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
-
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
-
-union uvh_rh_gam_gru_overlay_config_mmr_u {
-    unsigned long	v;
-    struct uvh_rh_gam_gru_overlay_config_mmr_s {
-	unsigned long	rsvd_0_27: 28;  /*    */
-	unsigned long	base   : 18;  /* RW */
-	unsigned long	rsvd_46_47:  2;  /*    */
-	unsigned long	gr4    :  1;  /* RW */
-	unsigned long	rsvd_49_51:  3;  /*    */
-	unsigned long	n_gru  :  4;  /* RW */
-	unsigned long	rsvd_56_62:  7;  /*    */
-	unsigned long	enable :  1;  /* RW */
-    } s;
-};
-
-/* ========================================================================= */
-/*                   UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR                     */
-/* ========================================================================= */
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
-
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
-
-union uvh_rh_gam_mmioh_overlay_config_mmr_u {
-    unsigned long	v;
-    struct uvh_rh_gam_mmioh_overlay_config_mmr_s {
-	unsigned long	rsvd_0_29: 30;  /*    */
-	unsigned long	base   : 16;  /* RW */
-	unsigned long	m_io   :  6;  /* RW */
-	unsigned long	n_io   :  4;  /* RW */
-	unsigned long	rsvd_56_62:  7;  /*    */
-	unsigned long	enable :  1;  /* RW */
-    } s;
-};
-
-/* ========================================================================= */
-/*                    UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR                      */
-/* ========================================================================= */
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
-
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
-
-union uvh_rh_gam_mmr_overlay_config_mmr_u {
-    unsigned long	v;
-    struct uvh_rh_gam_mmr_overlay_config_mmr_s {
-	unsigned long	rsvd_0_25: 26;  /*    */
-	unsigned long	base     : 20;  /* RW */
-	unsigned long	dual_hub :  1;  /* RW */
-	unsigned long	rsvd_47_62: 16;  /*    */
-	unsigned long	enable   :  1;  /* RW */
-    } s;
-};
-
-/* ========================================================================= */
-/*                                 UVH_RTC                                   */
-/* ========================================================================= */
-#define UVH_RTC 0x340000UL
-
-#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
-#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
-
-union uvh_rtc_u {
-    unsigned long	v;
-    struct uvh_rtc_s {
-	unsigned long	real_time_clock : 56;  /* RW */
-	unsigned long	rsvd_56_63      :  8;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                           UVH_RTC1_INT_CONFIG                             */
-/* ========================================================================= */
-#define UVH_RTC1_INT_CONFIG 0x615c0UL
-
-#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
-#define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UVH_RTC1_INT_CONFIG_DM_SHFT 8
-#define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
-#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11
-#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12
-#define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UVH_RTC1_INT_CONFIG_P_SHFT 13
-#define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
-#define UVH_RTC1_INT_CONFIG_T_SHFT 15
-#define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
-#define UVH_RTC1_INT_CONFIG_M_SHFT 16
-#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
-#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32
-#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
-
-union uvh_rtc1_int_config_u {
-    unsigned long	v;
-    struct uvh_rtc1_int_config_s {
-	unsigned long	vector_  :  8;  /* RW */
-	unsigned long	dm       :  3;  /* RW */
-	unsigned long	destmode :  1;  /* RW */
-	unsigned long	status   :  1;  /* RO */
-	unsigned long	p        :  1;  /* RO */
-	unsigned long	rsvd_14  :  1;  /*    */
-	unsigned long	t        :  1;  /* RO */
-	unsigned long	m        :  1;  /* RW */
-	unsigned long	rsvd_17_31: 15;  /*    */
-	unsigned long	apic_id  : 32;  /* RW */
-    } s;
-};
-
-/* ========================================================================= */
-/*                           UVH_RTC2_INT_CONFIG                             */
-/* ========================================================================= */
-#define UVH_RTC2_INT_CONFIG 0x61600UL
-
-#define UVH_RTC2_INT_CONFIG_VECTOR_SHFT 0
-#define UVH_RTC2_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UVH_RTC2_INT_CONFIG_DM_SHFT 8
-#define UVH_RTC2_INT_CONFIG_DM_MASK 0x0000000000000700UL
-#define UVH_RTC2_INT_CONFIG_DESTMODE_SHFT 11
-#define UVH_RTC2_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UVH_RTC2_INT_CONFIG_STATUS_SHFT 12
-#define UVH_RTC2_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UVH_RTC2_INT_CONFIG_P_SHFT 13
-#define UVH_RTC2_INT_CONFIG_P_MASK 0x0000000000002000UL
-#define UVH_RTC2_INT_CONFIG_T_SHFT 15
-#define UVH_RTC2_INT_CONFIG_T_MASK 0x0000000000008000UL
-#define UVH_RTC2_INT_CONFIG_M_SHFT 16
-#define UVH_RTC2_INT_CONFIG_M_MASK 0x0000000000010000UL
-#define UVH_RTC2_INT_CONFIG_APIC_ID_SHFT 32
-#define UVH_RTC2_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
-
-union uvh_rtc2_int_config_u {
-    unsigned long	v;
-    struct uvh_rtc2_int_config_s {
-	unsigned long	vector_  :  8;  /* RW */
-	unsigned long	dm       :  3;  /* RW */
-	unsigned long	destmode :  1;  /* RW */
-	unsigned long	status   :  1;  /* RO */
-	unsigned long	p        :  1;  /* RO */
-	unsigned long	rsvd_14  :  1;  /*    */
-	unsigned long	t        :  1;  /* RO */
-	unsigned long	m        :  1;  /* RW */
-	unsigned long	rsvd_17_31: 15;  /*    */
-	unsigned long	apic_id  : 32;  /* RW */
-    } s;
-};
-
-/* ========================================================================= */
-/*                           UVH_RTC3_INT_CONFIG                             */
-/* ========================================================================= */
-#define UVH_RTC3_INT_CONFIG 0x61640UL
-
-#define UVH_RTC3_INT_CONFIG_VECTOR_SHFT 0
-#define UVH_RTC3_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UVH_RTC3_INT_CONFIG_DM_SHFT 8
-#define UVH_RTC3_INT_CONFIG_DM_MASK 0x0000000000000700UL
-#define UVH_RTC3_INT_CONFIG_DESTMODE_SHFT 11
-#define UVH_RTC3_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UVH_RTC3_INT_CONFIG_STATUS_SHFT 12
-#define UVH_RTC3_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UVH_RTC3_INT_CONFIG_P_SHFT 13
-#define UVH_RTC3_INT_CONFIG_P_MASK 0x0000000000002000UL
-#define UVH_RTC3_INT_CONFIG_T_SHFT 15
-#define UVH_RTC3_INT_CONFIG_T_MASK 0x0000000000008000UL
-#define UVH_RTC3_INT_CONFIG_M_SHFT 16
-#define UVH_RTC3_INT_CONFIG_M_MASK 0x0000000000010000UL
-#define UVH_RTC3_INT_CONFIG_APIC_ID_SHFT 32
-#define UVH_RTC3_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
-
-union uvh_rtc3_int_config_u {
-    unsigned long	v;
-    struct uvh_rtc3_int_config_s {
-	unsigned long	vector_  :  8;  /* RW */
-	unsigned long	dm       :  3;  /* RW */
-	unsigned long	destmode :  1;  /* RW */
-	unsigned long	status   :  1;  /* RO */
-	unsigned long	p        :  1;  /* RO */
-	unsigned long	rsvd_14  :  1;  /*    */
-	unsigned long	t        :  1;  /* RO */
-	unsigned long	m        :  1;  /* RW */
-	unsigned long	rsvd_17_31: 15;  /*    */
-	unsigned long	apic_id  : 32;  /* RW */
-    } s;
-};
-
-/* ========================================================================= */
-/*                            UVH_RTC_INC_RATIO                              */
-/* ========================================================================= */
-#define UVH_RTC_INC_RATIO 0x350000UL
-
-#define UVH_RTC_INC_RATIO_FRACTION_SHFT 0
-#define UVH_RTC_INC_RATIO_FRACTION_MASK 0x00000000000fffffUL
-#define UVH_RTC_INC_RATIO_RATIO_SHFT 20
-#define UVH_RTC_INC_RATIO_RATIO_MASK 0x0000000000700000UL
-
-union uvh_rtc_inc_ratio_u {
-    unsigned long	v;
-    struct uvh_rtc_inc_ratio_s {
-	unsigned long	fraction : 20;  /* RW */
-	unsigned long	ratio    :  3;  /* RW */
-	unsigned long	rsvd_23_63: 41;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                          UVH_SI_ADDR_MAP_CONFIG                           */
-/* ========================================================================= */
-#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
-
-#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
-#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
-#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
-#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
-
-union uvh_si_addr_map_config_u {
-    unsigned long	v;
-    struct uvh_si_addr_map_config_s {
-	unsigned long	m_skt :  6;  /* RW */
-	unsigned long	rsvd_6_7:  2;  /*    */
-	unsigned long	n_skt :  4;  /* RW */
-	unsigned long	rsvd_12_63: 52;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                       UVH_SI_ALIAS0_OVERLAY_CONFIG                        */
-/* ========================================================================= */
-#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
-
-#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
-#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
-#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
-#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
-#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
-#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
-
-union uvh_si_alias0_overlay_config_u {
-    unsigned long	v;
-    struct uvh_si_alias0_overlay_config_s {
-	unsigned long	rsvd_0_23: 24;  /*    */
-	unsigned long	base    :  8;  /* RW */
-	unsigned long	rsvd_32_47: 16;  /*    */
-	unsigned long	m_alias :  5;  /* RW */
-	unsigned long	rsvd_53_62: 10;  /*    */
-	unsigned long	enable  :  1;  /* RW */
-    } s;
-};
-
-/* ========================================================================= */
-/*                       UVH_SI_ALIAS1_OVERLAY_CONFIG                        */
-/* ========================================================================= */
-#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
-
-#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
-#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
-#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
-#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
-#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
-#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
-
-union uvh_si_alias1_overlay_config_u {
-    unsigned long	v;
-    struct uvh_si_alias1_overlay_config_s {
-	unsigned long	rsvd_0_23: 24;  /*    */
-	unsigned long	base    :  8;  /* RW */
-	unsigned long	rsvd_32_47: 16;  /*    */
-	unsigned long	m_alias :  5;  /* RW */
-	unsigned long	rsvd_53_62: 10;  /*    */
-	unsigned long	enable  :  1;  /* RW */
-    } s;
-};
-
-/* ========================================================================= */
-/*                       UVH_SI_ALIAS2_OVERLAY_CONFIG                        */
-/* ========================================================================= */
-#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
-
-#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
-#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
-#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
-#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
-#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
-#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
-
-union uvh_si_alias2_overlay_config_u {
-    unsigned long	v;
-    struct uvh_si_alias2_overlay_config_s {
-	unsigned long	rsvd_0_23: 24;  /*    */
-	unsigned long	base    :  8;  /* RW */
-	unsigned long	rsvd_32_47: 16;  /*    */
-	unsigned long	m_alias :  5;  /* RW */
-	unsigned long	rsvd_53_62: 10;  /*    */
-	unsigned long	enable  :  1;  /* RW */
-    } s;
-};
-
-
-#endif /* ASM_X86__UV__UV_MMRS_H */
diff --git a/include/asm-x86/vdso.h b/include/asm-x86/vdso.h
deleted file mode 100644
index 4ab320913ea3..000000000000
--- a/include/asm-x86/vdso.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef ASM_X86__VDSO_H
-#define ASM_X86__VDSO_H
-
-#ifdef CONFIG_X86_64
-extern const char VDSO64_PRELINK[];
-
-/*
- * Given a pointer to the vDSO image, find the pointer to VDSO64_name
- * as that symbol is defined in the vDSO sources or linker script.
- */
-#define VDSO64_SYMBOL(base, name)					\
-({									\
-	extern const char VDSO64_##name[];				\
-	(void *)(VDSO64_##name - VDSO64_PRELINK + (unsigned long)(base)); \
-})
-#endif
-
-#if defined CONFIG_X86_32 || defined CONFIG_COMPAT
-extern const char VDSO32_PRELINK[];
-
-/*
- * Given a pointer to the vDSO image, find the pointer to VDSO32_name
- * as that symbol is defined in the vDSO sources or linker script.
- */
-#define VDSO32_SYMBOL(base, name)					\
-({									\
-	extern const char VDSO32_##name[];				\
-	(void *)(VDSO32_##name - VDSO32_PRELINK + (unsigned long)(base)); \
-})
-#endif
-
-/*
- * These symbols are defined with the addresses in the vsyscall page.
- * See vsyscall-sigreturn.S.
- */
-extern void __user __kernel_sigreturn;
-extern void __user __kernel_rt_sigreturn;
-
-/*
- * These symbols are defined by vdso32.S to mark the bounds
- * of the ELF DSO images included therein.
- */
-extern const char vdso32_int80_start, vdso32_int80_end;
-extern const char vdso32_syscall_start, vdso32_syscall_end;
-extern const char vdso32_sysenter_start, vdso32_sysenter_end;
-
-#endif /* ASM_X86__VDSO_H */
diff --git a/include/asm-x86/vga.h b/include/asm-x86/vga.h
deleted file mode 100644
index b9e493d07d07..000000000000
--- a/include/asm-x86/vga.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *	Access to VGA videoram
- *
- *	(c) 1998 Martin Mares <mj@ucw.cz>
- */
-
-#ifndef ASM_X86__VGA_H
-#define ASM_X86__VGA_H
-
-/*
- *	On the PC, we can just recalculate addresses and then
- *	access the videoram directly without any black magic.
- */
-
-#define VGA_MAP_MEM(x, s) (unsigned long)phys_to_virt(x)
-
-#define vga_readb(x) (*(x))
-#define vga_writeb(x, y) (*(y) = (x))
-
-#endif /* ASM_X86__VGA_H */
diff --git a/include/asm-x86/vgtod.h b/include/asm-x86/vgtod.h
deleted file mode 100644
index 38fd13364021..000000000000
--- a/include/asm-x86/vgtod.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef ASM_X86__VGTOD_H
-#define ASM_X86__VGTOD_H
-
-#include <asm/vsyscall.h>
-#include <linux/clocksource.h>
-
-struct vsyscall_gtod_data {
-	seqlock_t	lock;
-
-	/* open coded 'struct timespec' */
-	time_t		wall_time_sec;
-	u32		wall_time_nsec;
-
-	int		sysctl_enabled;
-	struct timezone sys_tz;
-	struct { /* extract of a clocksource struct */
-		cycle_t (*vread)(void);
-		cycle_t	cycle_last;
-		cycle_t	mask;
-		u32	mult;
-		u32	shift;
-	} clock;
-	struct timespec wall_to_monotonic;
-};
-extern struct vsyscall_gtod_data __vsyscall_gtod_data
-__section_vsyscall_gtod_data;
-extern struct vsyscall_gtod_data vsyscall_gtod_data;
-
-#endif /* ASM_X86__VGTOD_H */
diff --git a/include/asm-x86/vic.h b/include/asm-x86/vic.h
deleted file mode 100644
index 53100f353612..000000000000
--- a/include/asm-x86/vic.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright (C) 1999,2001
- *
- * Author: J.E.J.Bottomley@HansenPartnership.com
- *
- * Standard include definitions for the NCR Voyager Interrupt Controller */
-
-/* The eight CPI vectors.  To activate a CPI, you write a bit mask
- * corresponding to the processor set to be interrupted into the
- * relevant register.  That set of CPUs will then be interrupted with
- * the CPI */
-static const int VIC_CPI_Registers[] =
-	{0xFC00, 0xFC01, 0xFC08, 0xFC09,
-	 0xFC10, 0xFC11, 0xFC18, 0xFC19 };
-
-#define VIC_PROC_WHO_AM_I		0xfc29
-#	define	QUAD_IDENTIFIER		0xC0
-#	define  EIGHT_SLOT_IDENTIFIER	0xE0
-#define QIC_EXTENDED_PROCESSOR_SELECT	0xFC72
-#define VIC_CPI_BASE_REGISTER		0xFC41
-#define VIC_PROCESSOR_ID		0xFC21
-#	define VIC_CPU_MASQUERADE_ENABLE 0x8
-
-#define VIC_CLAIM_REGISTER_0		0xFC38
-#define VIC_CLAIM_REGISTER_1		0xFC39
-#define VIC_REDIRECT_REGISTER_0		0xFC60
-#define VIC_REDIRECT_REGISTER_1		0xFC61
-#define VIC_PRIORITY_REGISTER		0xFC20
-
-#define VIC_PRIMARY_MC_BASE		0xFC48
-#define VIC_SECONDARY_MC_BASE		0xFC49
-
-#define QIC_PROCESSOR_ID		0xFC71
-#	define	QIC_CPUID_ENABLE	0x08
-
-#define QIC_VIC_CPI_BASE_REGISTER	0xFC79
-#define QIC_CPI_BASE_REGISTER		0xFC7A
-
-#define QIC_MASK_REGISTER0		0xFC80
-/* NOTE: these are masked high, enabled low */
-#	define QIC_PERF_TIMER		0x01
-#	define QIC_LPE			0x02
-#	define QIC_SYS_INT		0x04
-#	define QIC_CMN_INT		0x08
-/* at the moment, just enable CMN_INT, disable SYS_INT */
-#	define QIC_DEFAULT_MASK0	(~(QIC_CMN_INT /* | VIC_SYS_INT */))
-#define QIC_MASK_REGISTER1		0xFC81
-#	define QIC_BOOT_CPI_MASK	0xFE
-/* Enable CPI's 1-6 inclusive */
-#	define QIC_CPI_ENABLE		0x81
-
-#define QIC_INTERRUPT_CLEAR0		0xFC8A
-#define QIC_INTERRUPT_CLEAR1		0xFC8B
-
-/* this is where we place the CPI vectors */
-#define VIC_DEFAULT_CPI_BASE		0xC0
-/* this is where we place the QIC CPI vectors */
-#define QIC_DEFAULT_CPI_BASE		0xD0
-
-#define VIC_BOOT_INTERRUPT_MASK		0xfe
-
-extern void smp_vic_timer_interrupt(void);
diff --git a/include/asm-x86/visws/cobalt.h b/include/asm-x86/visws/cobalt.h
deleted file mode 100644
index 9627a8fe84e9..000000000000
--- a/include/asm-x86/visws/cobalt.h
+++ /dev/null
@@ -1,125 +0,0 @@
-#ifndef ASM_X86__VISWS__COBALT_H
-#define ASM_X86__VISWS__COBALT_H
-
-#include <asm/fixmap.h>
-
-/*
- * Cobalt SGI Visual Workstation system ASIC
- */ 
-
-#define CO_CPU_NUM_PHYS 0x1e00
-#define CO_CPU_TAB_PHYS (CO_CPU_NUM_PHYS + 2)
-
-#define CO_CPU_MAX 4
-
-#define	CO_CPU_PHYS		0xc2000000
-#define	CO_APIC_PHYS		0xc4000000
-
-/* see set_fixmap() and asm/fixmap.h */
-#define	CO_CPU_VADDR		(fix_to_virt(FIX_CO_CPU))
-#define	CO_APIC_VADDR		(fix_to_virt(FIX_CO_APIC))
-
-/* Cobalt CPU registers -- relative to CO_CPU_VADDR, use co_cpu_*() */
-#define	CO_CPU_REV		0x08
-#define	CO_CPU_CTRL		0x10
-#define	CO_CPU_STAT		0x20
-#define	CO_CPU_TIMEVAL		0x30
-
-/* CO_CPU_CTRL bits */
-#define	CO_CTRL_TIMERUN		0x04		/* 0 == disabled */
-#define	CO_CTRL_TIMEMASK	0x08		/* 0 == unmasked */
-
-/* CO_CPU_STATUS bits */
-#define	CO_STAT_TIMEINTR	0x02	/* (r) 1 == int pend, (w) 0 == clear */
-
-/* CO_CPU_TIMEVAL value */
-#define	CO_TIME_HZ		100000000	/* Cobalt core rate */
-
-/* Cobalt APIC registers -- relative to CO_APIC_VADDR, use co_apic_*() */
-#define	CO_APIC_HI(n)		(((n) * 0x10) + 4)
-#define	CO_APIC_LO(n)		((n) * 0x10)
-#define	CO_APIC_ID		0x0ffc
-
-/* CO_APIC_ID bits */
-#define	CO_APIC_ENABLE		0x00000100
-
-/* CO_APIC_LO bits */
-#define	CO_APIC_MASK		0x00010000	/* 0 = enabled */
-#define	CO_APIC_LEVEL		0x00008000	/* 0 = edge */
-
-/*
- * Where things are physically wired to Cobalt
- * #defines with no board _<type>_<rev>_ are common to all (thus far)
- */
-#define	CO_APIC_IDE0		4
-#define CO_APIC_IDE1		2		/* Only on 320 */
-
-#define	CO_APIC_8259		12		/* serial, floppy, par-l-l */
-
-/* Lithium PCI Bridge A -- "the one with 82557 Ethernet" */
-#define	CO_APIC_PCIA_BASE0	0 /* and 1 */	/* slot 0, line 0 */
-#define	CO_APIC_PCIA_BASE123	5 /* and 6 */	/* slot 0, line 1 */
-
-#define	CO_APIC_PIIX4_USB	7		/* this one is weird */
-
-/* Lithium PCI Bridge B -- "the one with PIIX4" */
-#define	CO_APIC_PCIB_BASE0	8 /* and 9-12 *//* slot 0, line 0 */
-#define	CO_APIC_PCIB_BASE123	13 /* 14.15 */	/* slot 0, line 1 */
-
-#define	CO_APIC_VIDOUT0		16
-#define	CO_APIC_VIDOUT1		17
-#define	CO_APIC_VIDIN0		18
-#define	CO_APIC_VIDIN1		19
-
-#define	CO_APIC_LI_AUDIO	22
-
-#define	CO_APIC_AS		24
-#define	CO_APIC_RE		25
-
-#define CO_APIC_CPU		28		/* Timer and Cache interrupt */
-#define	CO_APIC_NMI		29
-#define	CO_APIC_LAST		CO_APIC_NMI
-
-/*
- * This is how irqs are assigned on the Visual Workstation.
- * Legacy devices get irq's 1-15 (system clock is 0 and is CO_APIC_CPU).
- * All other devices (including PCI) go to Cobalt and are irq's 16 on up.
- */
-#define	CO_IRQ_APIC0	16			/* irq of apic entry 0 */
-#define	IS_CO_APIC(irq)	((irq) >= CO_IRQ_APIC0)
-#define	CO_IRQ(apic)	(CO_IRQ_APIC0 + (apic))	/* apic ent to irq */
-#define	CO_APIC(irq)	((irq) - CO_IRQ_APIC0)	/* irq to apic ent */
-#define CO_IRQ_IDE0	14			/* knowledge of... */
-#define CO_IRQ_IDE1	15			/* ... ide driver defaults! */
-#define	CO_IRQ_8259	CO_IRQ(CO_APIC_8259)
-
-#ifdef CONFIG_X86_VISWS_APIC
-static inline void co_cpu_write(unsigned long reg, unsigned long v)
-{
-	*((volatile unsigned long *)(CO_CPU_VADDR+reg))=v;
-}
-
-static inline unsigned long co_cpu_read(unsigned long reg)
-{
-	return *((volatile unsigned long *)(CO_CPU_VADDR+reg));
-}            
-             
-static inline void co_apic_write(unsigned long reg, unsigned long v)
-{
-	*((volatile unsigned long *)(CO_APIC_VADDR+reg))=v;
-}            
-             
-static inline unsigned long co_apic_read(unsigned long reg)
-{
-	return *((volatile unsigned long *)(CO_APIC_VADDR+reg));
-}
-#endif
-
-extern char visws_board_type;
-
-#define	VISWS_320	0
-#define	VISWS_540	1
-
-extern char visws_board_rev;
-
-#endif /* ASM_X86__VISWS__COBALT_H */
diff --git a/include/asm-x86/visws/lithium.h b/include/asm-x86/visws/lithium.h
deleted file mode 100644
index b36d3b378c63..000000000000
--- a/include/asm-x86/visws/lithium.h
+++ /dev/null
@@ -1,53 +0,0 @@
-#ifndef ASM_X86__VISWS__LITHIUM_H
-#define ASM_X86__VISWS__LITHIUM_H
-
-#include <asm/fixmap.h>
-
-/*
- * Lithium is the SGI Visual Workstation I/O ASIC
- */
-
-#define	LI_PCI_A_PHYS		0xfc000000	/* Enet is dev 3 */
-#define	LI_PCI_B_PHYS		0xfd000000	/* PIIX4 is here */
-
-/* see set_fixmap() and asm/fixmap.h */
-#define LI_PCIA_VADDR   (fix_to_virt(FIX_LI_PCIA))
-#define LI_PCIB_VADDR   (fix_to_virt(FIX_LI_PCIB))
-
-/* Not a standard PCI? (not in linux/pci.h) */
-#define	LI_PCI_BUSNUM	0x44			/* lo8: primary, hi8: sub */
-#define LI_PCI_INTEN    0x46
-
-/* LI_PCI_INTENT bits */
-#define	LI_INTA_0	0x0001
-#define	LI_INTA_1	0x0002
-#define	LI_INTA_2	0x0004
-#define	LI_INTA_3	0x0008
-#define	LI_INTA_4	0x0010
-#define	LI_INTB		0x0020
-#define	LI_INTC		0x0040
-#define	LI_INTD		0x0080
-
-/* More special purpose macros... */
-static inline void li_pcia_write16(unsigned long reg, unsigned short v)
-{
-	*((volatile unsigned short *)(LI_PCIA_VADDR+reg))=v;
-}
-
-static inline unsigned short li_pcia_read16(unsigned long reg)
-{
-	 return *((volatile unsigned short *)(LI_PCIA_VADDR+reg));
-}
-
-static inline void li_pcib_write16(unsigned long reg, unsigned short v)
-{
-	*((volatile unsigned short *)(LI_PCIB_VADDR+reg))=v;
-}
-
-static inline unsigned short li_pcib_read16(unsigned long reg)
-{
-	return *((volatile unsigned short *)(LI_PCIB_VADDR+reg));
-}
-
-#endif /* ASM_X86__VISWS__LITHIUM_H */
-
diff --git a/include/asm-x86/visws/piix4.h b/include/asm-x86/visws/piix4.h
deleted file mode 100644
index 61c938045ec9..000000000000
--- a/include/asm-x86/visws/piix4.h
+++ /dev/null
@@ -1,107 +0,0 @@
-#ifndef ASM_X86__VISWS__PIIX4_H
-#define ASM_X86__VISWS__PIIX4_H
-
-/*
- * PIIX4 as used on SGI Visual Workstations
- */
-
-#define	PIIX_PM_START		0x0F80
-
-#define	SIO_GPIO_START		0x0FC0
-
-#define	SIO_PM_START		0x0FC8
-
-#define	PMBASE			PIIX_PM_START
-#define	GPIREG0			(PMBASE+0x30)
-#define	GPIREG(x)		(GPIREG0+((x)/8))
-#define	GPIBIT(x)		(1 << ((x)%8))
-
-#define	PIIX_GPI_BD_ID1		18
-#define	PIIX_GPI_BD_ID2		19
-#define	PIIX_GPI_BD_ID3		20
-#define	PIIX_GPI_BD_ID4		21
-#define	PIIX_GPI_BD_REG		GPIREG(PIIX_GPI_BD_ID1)
-#define	PIIX_GPI_BD_MASK	(GPIBIT(PIIX_GPI_BD_ID1) | \
-				GPIBIT(PIIX_GPI_BD_ID2) | \
-				GPIBIT(PIIX_GPI_BD_ID3) | \
-				GPIBIT(PIIX_GPI_BD_ID4) )
-
-#define	PIIX_GPI_BD_SHIFT	(PIIX_GPI_BD_ID1 % 8)
-
-#define	SIO_INDEX		0x2e
-#define	SIO_DATA		0x2f
-
-#define	SIO_DEV_SEL		0x7
-#define	SIO_DEV_ENB		0x30
-#define	SIO_DEV_MSB		0x60
-#define	SIO_DEV_LSB		0x61
-
-#define	SIO_GP_DEV		0x7
-
-#define	SIO_GP_BASE		SIO_GPIO_START
-#define	SIO_GP_MSB		(SIO_GP_BASE>>8)
-#define	SIO_GP_LSB		(SIO_GP_BASE&0xff)
-
-#define	SIO_GP_DATA1		(SIO_GP_BASE+0)
-
-#define	SIO_PM_DEV		0x8
-
-#define	SIO_PM_BASE		SIO_PM_START
-#define	SIO_PM_MSB		(SIO_PM_BASE>>8)
-#define	SIO_PM_LSB		(SIO_PM_BASE&0xff)
-#define	SIO_PM_INDEX		(SIO_PM_BASE+0)
-#define	SIO_PM_DATA		(SIO_PM_BASE+1)
-
-#define	SIO_PM_FER2		0x1
-
-#define	SIO_PM_GP_EN		0x80
-
-
-
-/*
- * This is the dev/reg where generating a config cycle will
- * result in a PCI special cycle.
- */
-#define SPECIAL_DEV		0xff
-#define SPECIAL_REG		0x00
-
-/*
- * PIIX4 needs to see a special cycle with the following data
- * to be convinced the processor has gone into the stop grant
- * state.  PIIX4 insists on seeing this before it will power
- * down a system.
- */
-#define PIIX_SPECIAL_STOP		0x00120002
-
-#define PIIX4_RESET_PORT	0xcf9
-#define PIIX4_RESET_VAL		0x6
-
-#define PMSTS_PORT		0xf80	// 2 bytes	PM Status
-#define PMEN_PORT		0xf82	// 2 bytes	PM Enable
-#define	PMCNTRL_PORT		0xf84	// 2 bytes	PM Control
-
-#define PM_SUSPEND_ENABLE	0x2000	// start sequence to suspend state
-
-/*
- * PMSTS and PMEN I/O bit definitions.
- * (Bits are the same in both registers)
- */
-#define PM_STS_RSM		(1<<15)	// Resume Status
-#define PM_STS_PWRBTNOR		(1<<11)	// Power Button Override
-#define PM_STS_RTC		(1<<10)	// RTC status
-#define PM_STS_PWRBTN		(1<<8)	// Power Button Pressed?
-#define PM_STS_GBL		(1<<5)	// Global Status
-#define PM_STS_BM		(1<<4)	// Bus Master Status
-#define PM_STS_TMROF		(1<<0)	// Timer Overflow Status.
-
-/*
- * Stop clock GPI register
- */
-#define PIIX_GPIREG0			(0xf80 + 0x30)
-
-/*
- * Stop clock GPI bit in GPIREG0
- */
-#define	PIIX_GPI_STPCLK		0x4	// STPCLK signal routed back in
-
-#endif /* ASM_X86__VISWS__PIIX4_H */
diff --git a/include/asm-x86/visws/sgivw.h b/include/asm-x86/visws/sgivw.h
deleted file mode 100644
index 5fbf63e1003c..000000000000
--- a/include/asm-x86/visws/sgivw.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * Frame buffer position and size:
- */
-extern unsigned long sgivwfb_mem_phys;
-extern unsigned long sgivwfb_mem_size;
diff --git a/include/asm-x86/vm86.h b/include/asm-x86/vm86.h
deleted file mode 100644
index 998bd18eb737..000000000000
--- a/include/asm-x86/vm86.h
+++ /dev/null
@@ -1,208 +0,0 @@
-#ifndef ASM_X86__VM86_H
-#define ASM_X86__VM86_H
-
-/*
- * I'm guessing at the VIF/VIP flag usage, but hope that this is how
- * the Pentium uses them. Linux will return from vm86 mode when both
- * VIF and VIP is set.
- *
- * On a Pentium, we could probably optimize the virtual flags directly
- * in the eflags register instead of doing it "by hand" in vflags...
- *
- * Linus
- */
-
-#include <asm/processor-flags.h>
-
-#define BIOSSEG		0x0f000
-
-#define CPU_086		0
-#define CPU_186		1
-#define CPU_286		2
-#define CPU_386		3
-#define CPU_486		4
-#define CPU_586		5
-
-/*
- * Return values for the 'vm86()' system call
- */
-#define VM86_TYPE(retval)	((retval) & 0xff)
-#define VM86_ARG(retval)	((retval) >> 8)
-
-#define VM86_SIGNAL	0	/* return due to signal */
-#define VM86_UNKNOWN	1	/* unhandled GP fault
-				   - IO-instruction or similar */
-#define VM86_INTx	2	/* int3/int x instruction (ARG = x) */
-#define VM86_STI	3	/* sti/popf/iret instruction enabled
-				   virtual interrupts */
-
-/*
- * Additional return values when invoking new vm86()
- */
-#define VM86_PICRETURN	4	/* return due to pending PIC request */
-#define VM86_TRAP	6	/* return due to DOS-debugger request */
-
-/*
- * function codes when invoking new vm86()
- */
-#define VM86_PLUS_INSTALL_CHECK	0
-#define VM86_ENTER		1
-#define VM86_ENTER_NO_BYPASS	2
-#define	VM86_REQUEST_IRQ	3
-#define VM86_FREE_IRQ		4
-#define VM86_GET_IRQ_BITS	5
-#define VM86_GET_AND_RESET_IRQ	6
-
-/*
- * This is the stack-layout seen by the user space program when we have
- * done a translation of "SAVE_ALL" from vm86 mode. The real kernel layout
- * is 'kernel_vm86_regs' (see below).
- */
-
-struct vm86_regs {
-/*
- * normal regs, with special meaning for the segment descriptors..
- */
-	long ebx;
-	long ecx;
-	long edx;
-	long esi;
-	long edi;
-	long ebp;
-	long eax;
-	long __null_ds;
-	long __null_es;
-	long __null_fs;
-	long __null_gs;
-	long orig_eax;
-	long eip;
-	unsigned short cs, __csh;
-	long eflags;
-	long esp;
-	unsigned short ss, __ssh;
-/*
- * these are specific to v86 mode:
- */
-	unsigned short es, __esh;
-	unsigned short ds, __dsh;
-	unsigned short fs, __fsh;
-	unsigned short gs, __gsh;
-};
-
-struct revectored_struct {
-	unsigned long __map[8];			/* 256 bits */
-};
-
-struct vm86_struct {
-	struct vm86_regs regs;
-	unsigned long flags;
-	unsigned long screen_bitmap;
-	unsigned long cpu_type;
-	struct revectored_struct int_revectored;
-	struct revectored_struct int21_revectored;
-};
-
-/*
- * flags masks
- */
-#define VM86_SCREEN_BITMAP	0x0001
-
-struct vm86plus_info_struct {
-	unsigned long force_return_for_pic:1;
-	unsigned long vm86dbg_active:1;       /* for debugger */
-	unsigned long vm86dbg_TFpendig:1;     /* for debugger */
-	unsigned long unused:28;
-	unsigned long is_vm86pus:1;	      /* for vm86 internal use */
-	unsigned char vm86dbg_intxxtab[32];   /* for debugger */
-};
-struct vm86plus_struct {
-	struct vm86_regs regs;
-	unsigned long flags;
-	unsigned long screen_bitmap;
-	unsigned long cpu_type;
-	struct revectored_struct int_revectored;
-	struct revectored_struct int21_revectored;
-	struct vm86plus_info_struct vm86plus;
-};
-
-#ifdef __KERNEL__
-
-#include <asm/ptrace.h>
-
-/*
- * This is the (kernel) stack-layout when we have done a "SAVE_ALL" from vm86
- * mode - the main change is that the old segment descriptors aren't
- * useful any more and are forced to be zero by the kernel (and the
- * hardware when a trap occurs), and the real segment descriptors are
- * at the end of the structure. Look at ptrace.h to see the "normal"
- * setup. For user space layout see 'struct vm86_regs' above.
- */
-
-struct kernel_vm86_regs {
-/*
- * normal regs, with special meaning for the segment descriptors..
- */
-	struct pt_regs pt;
-/*
- * these are specific to v86 mode:
- */
-	unsigned short es, __esh;
-	unsigned short ds, __dsh;
-	unsigned short fs, __fsh;
-	unsigned short gs, __gsh;
-};
-
-struct kernel_vm86_struct {
-	struct kernel_vm86_regs regs;
-/*
- * the below part remains on the kernel stack while we are in VM86 mode.
- * 'tss.esp0' then contains the address of VM86_TSS_ESP0 below, and when we
- * get forced back from VM86, the CPU and "SAVE_ALL" will restore the above
- * 'struct kernel_vm86_regs' with the then actual values.
- * Therefore, pt_regs in fact points to a complete 'kernel_vm86_struct'
- * in kernelspace, hence we need not reget the data from userspace.
- */
-#define VM86_TSS_ESP0 flags
-	unsigned long flags;
-	unsigned long screen_bitmap;
-	unsigned long cpu_type;
-	struct revectored_struct int_revectored;
-	struct revectored_struct int21_revectored;
-	struct vm86plus_info_struct vm86plus;
-	struct pt_regs *regs32;   /* here we save the pointer to the old regs */
-/*
- * The below is not part of the structure, but the stack layout continues
- * this way. In front of 'return-eip' may be some data, depending on
- * compilation, so we don't rely on this and save the pointer to 'oldregs'
- * in 'regs32' above.
- * However, with GCC-2.7.2 and the current CFLAGS you see exactly this:
-
-	long return-eip;        from call to vm86()
-	struct pt_regs oldregs;  user space registers as saved by syscall
- */
-};
-
-#ifdef CONFIG_VM86
-
-void handle_vm86_fault(struct kernel_vm86_regs *, long);
-int handle_vm86_trap(struct kernel_vm86_regs *, long, int);
-struct pt_regs *save_v86_state(struct kernel_vm86_regs *);
-
-struct task_struct;
-void release_vm86_irqs(struct task_struct *);
-
-#else
-
-#define handle_vm86_fault(a, b)
-#define release_vm86_irqs(a)
-
-static inline int handle_vm86_trap(struct kernel_vm86_regs *a, long b, int c)
-{
-	return 0;
-}
-
-#endif /* CONFIG_VM86 */
-
-#endif /* __KERNEL__ */
-
-#endif /* ASM_X86__VM86_H */
diff --git a/include/asm-x86/vmi.h b/include/asm-x86/vmi.h
deleted file mode 100644
index b7c0dea119fe..000000000000
--- a/include/asm-x86/vmi.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * VMI interface definition
- *
- * Copyright (C) 2005, VMware, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Maintained by: Zachary Amsden zach@vmware.com
- *
- */
-#include <linux/types.h>
-
-/*
- *---------------------------------------------------------------------
- *
- *  VMI Option ROM API
- *
- *---------------------------------------------------------------------
- */
-#define VMI_SIGNATURE 0x696d5663   /* "cVmi" */
-
-#define PCI_VENDOR_ID_VMWARE            0x15AD
-#define PCI_DEVICE_ID_VMWARE_VMI        0x0801
-
-/*
- * We use two version numbers for compatibility, with the major
- * number signifying interface breakages, and the minor number
- * interface extensions.
- */
-#define VMI_API_REV_MAJOR       3
-#define VMI_API_REV_MINOR       0
-
-#define VMI_CALL_CPUID			0
-#define VMI_CALL_WRMSR			1
-#define VMI_CALL_RDMSR			2
-#define VMI_CALL_SetGDT			3
-#define VMI_CALL_SetLDT			4
-#define VMI_CALL_SetIDT			5
-#define VMI_CALL_SetTR			6
-#define VMI_CALL_GetGDT			7
-#define VMI_CALL_GetLDT			8
-#define VMI_CALL_GetIDT			9
-#define VMI_CALL_GetTR			10
-#define VMI_CALL_WriteGDTEntry		11
-#define VMI_CALL_WriteLDTEntry		12
-#define VMI_CALL_WriteIDTEntry		13
-#define VMI_CALL_UpdateKernelStack	14
-#define VMI_CALL_SetCR0			15
-#define VMI_CALL_SetCR2			16
-#define VMI_CALL_SetCR3			17
-#define VMI_CALL_SetCR4			18
-#define VMI_CALL_GetCR0			19
-#define VMI_CALL_GetCR2			20
-#define VMI_CALL_GetCR3			21
-#define VMI_CALL_GetCR4			22
-#define VMI_CALL_WBINVD			23
-#define VMI_CALL_SetDR			24
-#define VMI_CALL_GetDR			25
-#define VMI_CALL_RDPMC			26
-#define VMI_CALL_RDTSC			27
-#define VMI_CALL_CLTS			28
-#define VMI_CALL_EnableInterrupts	29
-#define VMI_CALL_DisableInterrupts	30
-#define VMI_CALL_GetInterruptMask	31
-#define VMI_CALL_SetInterruptMask	32
-#define VMI_CALL_IRET			33
-#define VMI_CALL_SYSEXIT		34
-#define VMI_CALL_Halt			35
-#define VMI_CALL_Reboot			36
-#define VMI_CALL_Shutdown		37
-#define VMI_CALL_SetPxE			38
-#define VMI_CALL_SetPxELong		39
-#define VMI_CALL_UpdatePxE		40
-#define VMI_CALL_UpdatePxELong		41
-#define VMI_CALL_MachineToPhysical	42
-#define VMI_CALL_PhysicalToMachine	43
-#define VMI_CALL_AllocatePage		44
-#define VMI_CALL_ReleasePage		45
-#define VMI_CALL_InvalPage		46
-#define VMI_CALL_FlushTLB		47
-#define VMI_CALL_SetLinearMapping	48
-
-#define VMI_CALL_SetIOPLMask		61
-#define VMI_CALL_SetInitialAPState	62
-#define VMI_CALL_APICWrite		63
-#define VMI_CALL_APICRead		64
-#define VMI_CALL_IODelay		65
-#define VMI_CALL_SetLazyMode		73
-
-/*
- *---------------------------------------------------------------------
- *
- * MMU operation flags
- *
- *---------------------------------------------------------------------
- */
-
-/* Flags used by VMI_{Allocate|Release}Page call */
-#define VMI_PAGE_PAE             0x10  /* Allocate PAE shadow */
-#define VMI_PAGE_CLONE           0x20  /* Clone from another shadow */
-#define VMI_PAGE_ZEROED          0x40  /* Page is pre-zeroed */
-
-
-/* Flags shared by Allocate|Release Page and PTE updates */
-#define VMI_PAGE_PT              0x01
-#define VMI_PAGE_PD              0x02
-#define VMI_PAGE_PDP             0x04
-#define VMI_PAGE_PML4            0x08
-
-#define VMI_PAGE_NORMAL          0x00 /* for debugging */
-
-/* Flags used by PTE updates */
-#define VMI_PAGE_CURRENT_AS      0x10 /* implies VMI_PAGE_VA_MASK is valid */
-#define VMI_PAGE_DEFER           0x20 /* may queue update until TLB inval */
-#define VMI_PAGE_VA_MASK         0xfffff000
-
-#ifdef CONFIG_X86_PAE
-#define VMI_PAGE_L1		(VMI_PAGE_PT | VMI_PAGE_PAE | VMI_PAGE_ZEROED)
-#define VMI_PAGE_L2		(VMI_PAGE_PD | VMI_PAGE_PAE | VMI_PAGE_ZEROED)
-#else
-#define VMI_PAGE_L1		(VMI_PAGE_PT | VMI_PAGE_ZEROED)
-#define VMI_PAGE_L2		(VMI_PAGE_PD | VMI_PAGE_ZEROED)
-#endif
-
-/* Flags used by VMI_FlushTLB call */
-#define VMI_FLUSH_TLB            0x01
-#define VMI_FLUSH_GLOBAL         0x02
-
-/*
- *---------------------------------------------------------------------
- *
- *  VMI relocation definitions for ROM call get_reloc
- *
- *---------------------------------------------------------------------
- */
-
-/* VMI Relocation types */
-#define VMI_RELOCATION_NONE     0
-#define VMI_RELOCATION_CALL_REL 1
-#define VMI_RELOCATION_JUMP_REL 2
-#define VMI_RELOCATION_NOP	3
-
-#ifndef __ASSEMBLY__
-struct vmi_relocation_info {
-	unsigned char           *eip;
-	unsigned char           type;
-	unsigned char           reserved[3];
-};
-#endif
-
-
-/*
- *---------------------------------------------------------------------
- *
- *  Generic ROM structures and definitions
- *
- *---------------------------------------------------------------------
- */
-
-#ifndef __ASSEMBLY__
-
-struct vrom_header {
-	u16     rom_signature;  /* option ROM signature */
-	u8      rom_length;     /* ROM length in 512 byte chunks */
-	u8      rom_entry[4];   /* 16-bit code entry point */
-	u8      rom_pad0;       /* 4-byte align pad */
-	u32     vrom_signature; /* VROM identification signature */
-	u8      api_version_min;/* Minor version of API */
-	u8      api_version_maj;/* Major version of API */
-	u8      jump_slots;     /* Number of jump slots */
-	u8      reserved1;      /* Reserved for expansion */
-	u32     virtual_top;    /* Hypervisor virtual address start */
-	u16     reserved2;      /* Reserved for expansion */
-	u16	license_offs;	/* Offset to License string */
-	u16     pci_header_offs;/* Offset to PCI OPROM header */
-	u16     pnp_header_offs;/* Offset to PnP OPROM header */
-	u32     rom_pad3;       /* PnP reserverd / VMI reserved */
-	u8      reserved[96];   /* Reserved for headers */
-	char    vmi_init[8];    /* VMI_Init jump point */
-	char    get_reloc[8];   /* VMI_GetRelocationInfo jump point */
-} __attribute__((packed));
-
-struct pnp_header {
-	char sig[4];
-	char rev;
-	char size;
-	short next;
-	short res;
-	long devID;
-	unsigned short manufacturer_offset;
-	unsigned short product_offset;
-} __attribute__((packed));
-
-struct pci_header {
-	char sig[4];
-	short vendorID;
-	short deviceID;
-	short vpdData;
-	short size;
-	char rev;
-	char class;
-	char subclass;
-	char interface;
-	short chunks;
-	char rom_version_min;
-	char rom_version_maj;
-	char codetype;
-	char lastRom;
-	short reserved;
-} __attribute__((packed));
-
-/* Function prototypes for bootstrapping */
-extern void vmi_init(void);
-extern void vmi_bringup(void);
-extern void vmi_apply_boot_page_allocations(void);
-
-/* State needed to start an application processor in an SMP system. */
-struct vmi_ap_state {
-	u32 cr0;
-	u32 cr2;
-	u32 cr3;
-	u32 cr4;
-
-	u64 efer;
-
-	u32 eip;
-	u32 eflags;
-	u32 eax;
-	u32 ebx;
-	u32 ecx;
-	u32 edx;
-	u32 esp;
-	u32 ebp;
-	u32 esi;
-	u32 edi;
-	u16 cs;
-	u16 ss;
-	u16 ds;
-	u16 es;
-	u16 fs;
-	u16 gs;
-	u16 ldtr;
-
-	u16 gdtr_limit;
-	u32 gdtr_base;
-	u32 idtr_base;
-	u16 idtr_limit;
-};
-
-#endif
diff --git a/include/asm-x86/vmi_time.h b/include/asm-x86/vmi_time.h
deleted file mode 100644
index b2d39e6a08b7..000000000000
--- a/include/asm-x86/vmi_time.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * VMI Time wrappers
- *
- * Copyright (C) 2006, VMware, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Send feedback to dhecht@vmware.com
- *
- */
-
-#ifndef ASM_X86__VMI_TIME_H
-#define ASM_X86__VMI_TIME_H
-
-/*
- * Raw VMI call indices for timer functions
- */
-#define VMI_CALL_GetCycleFrequency	66
-#define VMI_CALL_GetCycleCounter	67
-#define VMI_CALL_SetAlarm		68
-#define VMI_CALL_CancelAlarm		69
-#define VMI_CALL_GetWallclockTime	70
-#define VMI_CALL_WallclockUpdated	71
-
-/* Cached VMI timer operations */
-extern struct vmi_timer_ops {
-	u64 (*get_cycle_frequency)(void);
-	u64 (*get_cycle_counter)(int);
-	u64 (*get_wallclock)(void);
-	int (*wallclock_updated)(void);
-	void (*set_alarm)(u32 flags, u64 expiry, u64 period);
-	void (*cancel_alarm)(u32 flags);
-} vmi_timer_ops;
-
-/* Prototypes */
-extern void __init vmi_time_init(void);
-extern unsigned long vmi_get_wallclock(void);
-extern int vmi_set_wallclock(unsigned long now);
-extern unsigned long long vmi_sched_clock(void);
-extern unsigned long vmi_tsc_khz(void);
-
-#ifdef CONFIG_X86_LOCAL_APIC
-extern void __devinit vmi_time_bsp_init(void);
-extern void __devinit vmi_time_ap_init(void);
-#endif
-
-/*
- * When run under a hypervisor, a vcpu is always in one of three states:
- * running, halted, or ready.  The vcpu is in the 'running' state if it
- * is executing.  When the vcpu executes the halt interface, the vcpu
- * enters the 'halted' state and remains halted until there is some work
- * pending for the vcpu (e.g. an alarm expires, host I/O completes on
- * behalf of virtual I/O).  At this point, the vcpu enters the 'ready'
- * state (waiting for the hypervisor to reschedule it).  Finally, at any
- * time when the vcpu is not in the 'running' state nor the 'halted'
- * state, it is in the 'ready' state.
- *
- * Real time is advances while the vcpu is 'running', 'ready', or
- * 'halted'.  Stolen time is the time in which the vcpu is in the
- * 'ready' state.  Available time is the remaining time -- the vcpu is
- * either 'running' or 'halted'.
- *
- * All three views of time are accessible through the VMI cycle
- * counters.
- */
-
-/* The cycle counters. */
-#define VMI_CYCLES_REAL         0
-#define VMI_CYCLES_AVAILABLE    1
-#define VMI_CYCLES_STOLEN       2
-
-/* The alarm interface 'flags' bits */
-#define VMI_ALARM_COUNTERS      2
-
-#define VMI_ALARM_COUNTER_MASK  0x000000ff
-
-#define VMI_ALARM_WIRED_IRQ0    0x00000000
-#define VMI_ALARM_WIRED_LVTT    0x00010000
-
-#define VMI_ALARM_IS_ONESHOT    0x00000000
-#define VMI_ALARM_IS_PERIODIC   0x00000100
-
-#define CONFIG_VMI_ALARM_HZ	100
-
-#endif /* ASM_X86__VMI_TIME_H */
diff --git a/include/asm-x86/voyager.h b/include/asm-x86/voyager.h
deleted file mode 100644
index 9c811d2e6f91..000000000000
--- a/include/asm-x86/voyager.h
+++ /dev/null
@@ -1,528 +0,0 @@
-/* Copyright (C) 1999,2001
- *
- * Author: J.E.J.Bottomley@HansenPartnership.com
- *
- * Standard include definitions for the NCR Voyager system */
-
-#undef	VOYAGER_DEBUG
-#undef	VOYAGER_CAT_DEBUG
-
-#ifdef VOYAGER_DEBUG
-#define VDEBUG(x)	printk x
-#else
-#define VDEBUG(x)
-#endif
-
-/* There are three levels of voyager machine: 3,4 and 5. The rule is
- * if it's less than 3435 it's a Level 3 except for a 3360 which is
- * a level 4.  A 3435 or above is a Level 5 */
-#define VOYAGER_LEVEL5_AND_ABOVE	0x3435
-#define VOYAGER_LEVEL4			0x3360
-
-/* The L4 DINO ASIC */
-#define VOYAGER_DINO			0x43
-
-/* voyager ports in standard I/O space */
-#define VOYAGER_MC_SETUP	0x96
-
-
-#define	VOYAGER_CAT_CONFIG_PORT			0x97
-#	define VOYAGER_CAT_DESELECT		0xff
-#define VOYAGER_SSPB_RELOCATION_PORT		0x98
-
-/* Valid CAT controller commands */
-/* start instruction register cycle */
-#define VOYAGER_CAT_IRCYC			0x01
-/* start data register cycle */
-#define VOYAGER_CAT_DRCYC			0x02
-/* move to execute state */
-#define VOYAGER_CAT_RUN				0x0F
-/* end operation */
-#define VOYAGER_CAT_END				0x80
-/* hold in idle state */
-#define VOYAGER_CAT_HOLD			0x90
-/* single step an "intest" vector */
-#define VOYAGER_CAT_STEP			0xE0
-/* return cat controller to CLEMSON mode */
-#define VOYAGER_CAT_CLEMSON			0xFF
-
-/* the default cat command header */
-#define VOYAGER_CAT_HEADER			0x7F
-
-/* the range of possible CAT module ids in the system */
-#define VOYAGER_MIN_MODULE			0x10
-#define VOYAGER_MAX_MODULE			0x1f
-
-/* The voyager registers per asic */
-#define VOYAGER_ASIC_ID_REG			0x00
-#define VOYAGER_ASIC_TYPE_REG			0x01
-/* the sub address registers can be made auto incrementing on reads */
-#define VOYAGER_AUTO_INC_REG			0x02
-#	define VOYAGER_AUTO_INC			0x04
-#	define VOYAGER_NO_AUTO_INC		0xfb
-#define VOYAGER_SUBADDRDATA			0x03
-#define VOYAGER_SCANPATH			0x05
-#	define VOYAGER_CONNECT_ASIC		0x01
-#	define VOYAGER_DISCONNECT_ASIC		0xfe
-#define VOYAGER_SUBADDRLO			0x06
-#define VOYAGER_SUBADDRHI			0x07
-#define VOYAGER_SUBMODSELECT			0x08
-#define VOYAGER_SUBMODPRESENT			0x09
-
-#define VOYAGER_SUBADDR_LO			0xff
-#define VOYAGER_SUBADDR_HI			0xffff
-
-/* the maximum size of a scan path -- used to form instructions */
-#define VOYAGER_MAX_SCAN_PATH			0x100
-/* the biggest possible register size (in bytes) */
-#define VOYAGER_MAX_REG_SIZE			4
-
-/* Total number of possible modules (including submodules) */
-#define VOYAGER_MAX_MODULES			16
-/* Largest number of asics per module */
-#define VOYAGER_MAX_ASICS_PER_MODULE		7
-
-/* the CAT asic of each module is always the first one */
-#define VOYAGER_CAT_ID				0
-#define VOYAGER_PSI				0x1a
-
-/* voyager instruction operations and registers */
-#define VOYAGER_READ_CONFIG			0x1
-#define VOYAGER_WRITE_CONFIG			0x2
-#define VOYAGER_BYPASS				0xff
-
-typedef struct voyager_asic {
-	__u8	asic_addr;	/* ASIC address; Level 4 */
-	__u8	asic_type;      /* ASIC type */
-	__u8	asic_id;	/* ASIC id */
-	__u8	jtag_id[4];	/* JTAG id */
-	__u8	asic_location;	/* Location within scan path; start w/ 0 */
-	__u8	bit_location;	/* Location within bit stream; start w/ 0 */
-	__u8	ireg_length;	/* Instruction register length */
-	__u16	subaddr;	/* Amount of sub address space */
-	struct voyager_asic *next;	/* Next asic in linked list */
-} voyager_asic_t;
-
-typedef struct voyager_module {
-	__u8	module_addr;		/* Module address */
-	__u8	scan_path_connected;	/* Scan path connected */
-	__u16   ee_size;		/* Size of the EEPROM */
-	__u16   num_asics;		/* Number of Asics */
-	__u16   inst_bits;		/* Instruction bits in the scan path */
-	__u16   largest_reg;		/* Largest register in the scan path */
-	__u16   smallest_reg;		/* Smallest register in the scan path */
-	voyager_asic_t   *asic;		/* First ASIC in scan path (CAT_I) */
-	struct   voyager_module *submodule;	/* Submodule pointer */
-	struct   voyager_module *next;		/* Next module in linked list */
-} voyager_module_t;
-
-typedef struct voyager_eeprom_hdr {
-	 __u8  module_id[4];
-	 __u8  version_id;
-	 __u8  config_id;
-	 __u16 boundry_id;	/* boundary scan id */
-	 __u16 ee_size;		/* size of EEPROM */
-	 __u8  assembly[11];	/* assembly # */
-	 __u8  assembly_rev;	/* assembly rev */
-	 __u8  tracer[4];	/* tracer number */
-	 __u16 assembly_cksum;	/* asm checksum */
-	 __u16 power_consump;	/* pwr requirements */
-	 __u16 num_asics;	/* number of asics */
-	 __u16 bist_time;	/* min. bist time */
-	 __u16 err_log_offset;	/* error log offset */
-	 __u16 scan_path_offset;/* scan path offset */
-	 __u16 cct_offset;
-	 __u16 log_length;	/* length of err log */
-	 __u16 xsum_end;	/* offset to end of
-				   checksum */
-	 __u8  reserved[4];
-	 __u8  sflag;		/* starting sentinal */
-	 __u8  part_number[13];	/* prom part number */
-	 __u8  version[10];	/* version number */
-	 __u8  signature[8];
-	 __u16 eeprom_chksum;
-	 __u32  data_stamp_offset;
-	 __u8  eflag ;		 /* ending sentinal */
-} __attribute__((packed)) voyager_eprom_hdr_t;
-
-
-
-#define VOYAGER_EPROM_SIZE_OFFSET				\
-	((__u16)(&(((voyager_eprom_hdr_t *)0)->ee_size)))
-#define VOYAGER_XSUM_END_OFFSET		0x2a
-
-/* the following three definitions are for internal table layouts
- * in the module EPROMs.  We really only care about the IDs and
- * offsets */
-typedef struct voyager_sp_table {
-	__u8 asic_id;
-	__u8 bypass_flag;
-	__u16 asic_data_offset;
-	__u16 config_data_offset;
-} __attribute__((packed)) voyager_sp_table_t;
-
-typedef struct voyager_jtag_table {
-	__u8 icode[4];
-	__u8 runbist[4];
-	__u8 intest[4];
-	__u8 samp_preld[4];
-	__u8 ireg_len;
-} __attribute__((packed)) voyager_jtt_t;
-
-typedef struct voyager_asic_data_table {
-	__u8 jtag_id[4];
-	__u16 length_bsr;
-	__u16 length_bist_reg;
-	__u32 bist_clk;
-	__u16 subaddr_bits;
-	__u16 seed_bits;
-	__u16 sig_bits;
-	__u16 jtag_offset;
-} __attribute__((packed)) voyager_at_t;
-
-/* Voyager Interrupt Controller (VIC) registers */
-
-/* Base to add to Cross Processor Interrupts (CPIs) when triggering
- * the CPU IRQ line */
-/* register defines for the WCBICs (one per processor) */
-#define VOYAGER_WCBIC0	0x41		/* bus A node P1 processor 0 */
-#define VOYAGER_WCBIC1	0x49		/* bus A node P1 processor 1 */
-#define VOYAGER_WCBIC2	0x51		/* bus A node P2 processor 0 */
-#define VOYAGER_WCBIC3	0x59		/* bus A node P2 processor 1 */
-#define VOYAGER_WCBIC4	0x61		/* bus B node P1 processor 0 */
-#define VOYAGER_WCBIC5	0x69		/* bus B node P1 processor 1 */
-#define VOYAGER_WCBIC6	0x71		/* bus B node P2 processor 0 */
-#define VOYAGER_WCBIC7	0x79		/* bus B node P2 processor 1 */
-
-
-/* top of memory registers */
-#define VOYAGER_WCBIC_TOM_L	0x4
-#define VOYAGER_WCBIC_TOM_H	0x5
-
-/* register defines for Voyager Memory Contol (VMC)
- * these are present on L4 machines only */
-#define	VOYAGER_VMC1		0x81
-#define VOYAGER_VMC2		0x91
-#define VOYAGER_VMC3		0xa1
-#define VOYAGER_VMC4		0xb1
-
-/* VMC Ports */
-#define VOYAGER_VMC_MEMORY_SETUP	0x9
-#	define VMC_Interleaving		0x01
-#	define VMC_4Way			0x02
-#	define VMC_EvenCacheLines	0x04
-#	define VMC_HighLine		0x08
-#	define VMC_Start0_Enable	0x20
-#	define VMC_Start1_Enable	0x40
-#	define VMC_Vremap		0x80
-#define VOYAGER_VMC_BANK_DENSITY	0xa
-#	define	VMC_BANK_EMPTY		0
-#	define	VMC_BANK_4MB		1
-#	define	VMC_BANK_16MB		2
-#	define	VMC_BANK_64MB		3
-#	define	VMC_BANK0_MASK		0x03
-#	define	VMC_BANK1_MASK		0x0C
-#	define	VMC_BANK2_MASK		0x30
-#	define	VMC_BANK3_MASK		0xC0
-
-/* Magellan Memory Controller (MMC) defines - present on L5 */
-#define VOYAGER_MMC_ASIC_ID		1
-/* the two memory modules corresponding to memory cards in the system */
-#define VOYAGER_MMC_MEMORY0_MODULE	0x14
-#define VOYAGER_MMC_MEMORY1_MODULE	0x15
-/* the Magellan Memory Address (MMA) defines */
-#define VOYAGER_MMA_ASIC_ID		2
-
-/* Submodule number for the Quad Baseboard */
-#define VOYAGER_QUAD_BASEBOARD		1
-
-/* ASIC defines for the Quad Baseboard */
-#define VOYAGER_QUAD_QDATA0		1
-#define VOYAGER_QUAD_QDATA1		2
-#define VOYAGER_QUAD_QABC		3
-
-/* Useful areas in extended CMOS */
-#define VOYAGER_PROCESSOR_PRESENT_MASK	0x88a
-#define VOYAGER_MEMORY_CLICKMAP		0xa23
-#define VOYAGER_DUMP_LOCATION		0xb1a
-
-/* SUS In Control bit - used to tell SUS that we don't need to be
- * babysat anymore */
-#define VOYAGER_SUS_IN_CONTROL_PORT	0x3ff
-#	define VOYAGER_IN_CONTROL_FLAG	0x80
-
-/* Voyager PSI defines */
-#define VOYAGER_PSI_STATUS_REG		0x08
-#	define PSI_DC_FAIL		0x01
-#	define PSI_MON			0x02
-#	define PSI_FAULT		0x04
-#	define PSI_ALARM		0x08
-#	define PSI_CURRENT		0x10
-#	define PSI_DVM			0x20
-#	define PSI_PSCFAULT		0x40
-#	define PSI_STAT_CHG		0x80
-
-#define VOYAGER_PSI_SUPPLY_REG		0x8000
-	/* read */
-#	define PSI_FAIL_DC		0x01
-#	define PSI_FAIL_AC		0x02
-#	define PSI_MON_INT		0x04
-#	define PSI_SWITCH_OFF		0x08
-#	define PSI_HX_OFF		0x10
-#	define PSI_SECURITY		0x20
-#	define PSI_CMOS_BATT_LOW	0x40
-#	define PSI_CMOS_BATT_FAIL	0x80
-	/* write */
-#	define PSI_CLR_SWITCH_OFF	0x13
-#	define PSI_CLR_HX_OFF		0x14
-#	define PSI_CLR_CMOS_BATT_FAIL	0x17
-
-#define VOYAGER_PSI_MASK		0x8001
-#	define PSI_MASK_MASK		0x10
-
-#define VOYAGER_PSI_AC_FAIL_REG		0x8004
-#define	AC_FAIL_STAT_CHANGE		0x80
-
-#define VOYAGER_PSI_GENERAL_REG		0x8007
-	/* read */
-#	define PSI_SWITCH_ON		0x01
-#	define PSI_SWITCH_ENABLED	0x02
-#	define PSI_ALARM_ENABLED	0x08
-#	define PSI_SECURE_ENABLED	0x10
-#	define PSI_COLD_RESET		0x20
-#	define PSI_COLD_START		0x80
-	/* write */
-#	define PSI_POWER_DOWN		0x10
-#	define PSI_SWITCH_DISABLE	0x01
-#	define PSI_SWITCH_ENABLE	0x11
-#	define PSI_CLEAR		0x12
-#	define PSI_ALARM_DISABLE	0x03
-#	define PSI_ALARM_ENABLE		0x13
-#	define PSI_CLEAR_COLD_RESET	0x05
-#	define PSI_SET_COLD_RESET	0x15
-#	define PSI_CLEAR_COLD_START	0x07
-#	define PSI_SET_COLD_START	0x17
-
-
-
-struct voyager_bios_info {
-	__u8	len;
-	__u8	major;
-	__u8	minor;
-	__u8	debug;
-	__u8	num_classes;
-	__u8	class_1;
-	__u8	class_2;
-};
-
-/* The following structures and definitions are for the Kernel/SUS
- * interface these are needed to find out how SUS initialised any Quad
- * boards in the system */
-
-#define	NUMBER_OF_MC_BUSSES	2
-#define SLOTS_PER_MC_BUS	8
-#define MAX_CPUS                16      /* 16 way CPU system */
-#define MAX_PROCESSOR_BOARDS	4	/* 4 processor slot system */
-#define MAX_CACHE_LEVELS	4	/* # of cache levels supported */
-#define MAX_SHARED_CPUS		4	/* # of CPUs that can share a LARC */
-#define NUMBER_OF_POS_REGS	8
-
-typedef struct {
-	__u8	MC_Slot;
-	__u8	POS_Values[NUMBER_OF_POS_REGS];
-} __attribute__((packed)) MC_SlotInformation_t;
-
-struct QuadDescription {
-	__u8  Type;	/* for type 0 (DYADIC or MONADIC) all fields
-			 * will be zero except for slot */
-	__u8 StructureVersion;
-	__u32 CPI_BaseAddress;
-	__u32  LARC_BankSize;
-	__u32 LocalMemoryStateBits;
-	__u8  Slot; /* Processor slots 1 - 4 */
-} __attribute__((packed));
-
-struct ProcBoardInfo {
-	__u8 Type;
-	__u8 StructureVersion;
-	__u8 NumberOfBoards;
-	struct QuadDescription QuadData[MAX_PROCESSOR_BOARDS];
-} __attribute__((packed));
-
-struct CacheDescription {
-	__u8 Level;
-	__u32 TotalSize;
-	__u16 LineSize;
-	__u8  Associativity;
-	__u8  CacheType;
-	__u8  WriteType;
-	__u8  Number_CPUs_SharedBy;
-	__u8  Shared_CPUs_Hardware_IDs[MAX_SHARED_CPUS];
-
-} __attribute__((packed));
-
-struct CPU_Description {
-	__u8 CPU_HardwareId;
-	char *FRU_String;
-	__u8 NumberOfCacheLevels;
-	struct CacheDescription CacheLevelData[MAX_CACHE_LEVELS];
-} __attribute__((packed));
-
-struct CPU_Info {
-	__u8 Type;
-	__u8 StructureVersion;
-	__u8 NumberOf_CPUs;
-	struct CPU_Description CPU_Data[MAX_CPUS];
-} __attribute__((packed));
-
-
-/*
- * This structure will be used by SUS and the OS.
- * The assumption about this structure is that no blank space is
- * packed in it by our friend the compiler.
- */
-typedef struct {
-	__u8	Mailbox_SUS;		/* Written to by SUS to give
-					   commands/response to the OS */
-	__u8	Mailbox_OS;		/* Written to by the OS to give
-					   commands/response to SUS */
-	__u8	SUS_MailboxVersion;	/* Tells the OS which iteration of the
-					   interface SUS supports */
-	__u8	OS_MailboxVersion;	/* Tells SUS which iteration of the
-					   interface the OS supports */
-	__u32	OS_Flags;		/* Flags set by the OS as info for
-					   SUS */
-	__u32	SUS_Flags;		/* Flags set by SUS as info
-					   for the OS */
-	__u32	WatchDogPeriod;		/* Watchdog period (in seconds) which
-					   the DP uses to see if the OS
-					   is dead */
-	__u32	WatchDogCount;		/* Updated by the OS on every tic. */
-	__u32	MemoryFor_SUS_ErrorLog;	/* Flat 32 bit address which tells SUS
-					   where to stuff the SUS error log
-					   on a dump */
-	MC_SlotInformation_t MC_SlotInfo[NUMBER_OF_MC_BUSSES*SLOTS_PER_MC_BUS];
-					/* Storage for MCA POS data */
-	/* All new SECOND_PASS_INTERFACE fields added from this point */
-	struct ProcBoardInfo    *BoardData;
-	struct CPU_Info         *CPU_Data;
-	/* All new fields must be added from this point */
-} Voyager_KernelSUS_Mbox_t;
-
-/* structure for finding the right memory address to send a QIC CPI to */
-struct voyager_qic_cpi {
-	/* Each cache line (32 bytes) can trigger a cpi.  The cpi
-	 * read/write may occur anywhere in the cache line---pick the
-	 * middle to be safe */
-	struct  {
-		__u32 pad1[3];
-		__u32 cpi;
-		__u32 pad2[4];
-	} qic_cpi[8];
-};
-
-struct voyager_status {
-	__u32	power_fail:1;
-	__u32	switch_off:1;
-	__u32	request_from_kernel:1;
-};
-
-struct voyager_psi_regs {
-	__u8 cat_id;
-	__u8 cat_dev;
-	__u8 cat_control;
-	__u8 subaddr;
-	__u8 dummy4;
-	__u8 checkbit;
-	__u8 subaddr_low;
-	__u8 subaddr_high;
-	__u8 intstatus;
-	__u8 stat1;
-	__u8 stat3;
-	__u8 fault;
-	__u8 tms;
-	__u8 gen;
-	__u8 sysconf;
-	__u8 dummy15;
-};
-
-struct voyager_psi_subregs {
-	__u8 supply;
-	__u8 mask;
-	__u8 present;
-	__u8 DCfail;
-	__u8 ACfail;
-	__u8 fail;
-	__u8 UPSfail;
-	__u8 genstatus;
-};
-
-struct voyager_psi {
-	struct voyager_psi_regs regs;
-	struct voyager_psi_subregs subregs;
-};
-
-struct voyager_SUS {
-#define	VOYAGER_DUMP_BUTTON_NMI		0x1
-#define VOYAGER_SUS_VALID		0x2
-#define VOYAGER_SYSINT_COMPLETE		0x3
-	__u8	SUS_mbox;
-#define VOYAGER_NO_COMMAND		0x0
-#define VOYAGER_IGNORE_DUMP		0x1
-#define VOYAGER_DO_DUMP			0x2
-#define VOYAGER_SYSINT_HANDSHAKE	0x3
-#define VOYAGER_DO_MEM_DUMP		0x4
-#define VOYAGER_SYSINT_WAS_RECOVERED	0x5
-	__u8	kernel_mbox;
-#define	VOYAGER_MAILBOX_VERSION		0x10
-	__u8	SUS_version;
-	__u8	kernel_version;
-#define VOYAGER_OS_HAS_SYSINT		0x1
-#define VOYAGER_OS_IN_PROGRESS		0x2
-#define VOYAGER_UPDATING_WDPERIOD	0x4
-	__u32	kernel_flags;
-#define VOYAGER_SUS_BOOTING		0x1
-#define VOYAGER_SUS_IN_PROGRESS		0x2
-	__u32	SUS_flags;
-	__u32	watchdog_period;
-	__u32	watchdog_count;
-	__u32	SUS_errorlog;
-	/* lots of system configuration stuff under here */
-};
-
-/* Variables exported by voyager_smp */
-extern __u32 voyager_extended_vic_processors;
-extern __u32 voyager_allowed_boot_processors;
-extern __u32 voyager_quad_processors;
-extern struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS];
-extern struct voyager_SUS *voyager_SUS;
-
-/* variables exported always */
-extern struct task_struct *voyager_thread;
-extern int voyager_level;
-extern struct voyager_status voyager_status;
-
-/* functions exported by the voyager and voyager_smp modules */
-extern int voyager_cat_readb(__u8 module, __u8 asic, int reg);
-extern void voyager_cat_init(void);
-extern void voyager_detect(struct voyager_bios_info *);
-extern void voyager_trap_init(void);
-extern void voyager_setup_irqs(void);
-extern int voyager_memory_detect(int region, __u32 *addr, __u32 *length);
-extern void voyager_smp_intr_init(void);
-extern __u8 voyager_extended_cmos_read(__u16 cmos_address);
-extern void voyager_smp_dump(void);
-extern void voyager_timer_interrupt(void);
-extern void smp_local_timer_interrupt(void);
-extern void voyager_power_off(void);
-extern void smp_voyager_power_off(void *dummy);
-extern void voyager_restart(void);
-extern void voyager_cat_power_off(void);
-extern void voyager_cat_do_common_interrupt(void);
-extern void voyager_handle_nmi(void);
-/* Commands for the following are */
-#define	VOYAGER_PSI_READ	0
-#define VOYAGER_PSI_WRITE	1
-#define VOYAGER_PSI_SUBREAD	2
-#define VOYAGER_PSI_SUBWRITE	3
-extern void voyager_cat_psi(__u8, __u16, __u8 *);
diff --git a/include/asm-x86/vsyscall.h b/include/asm-x86/vsyscall.h
deleted file mode 100644
index dcd4682413de..000000000000
--- a/include/asm-x86/vsyscall.h
+++ /dev/null
@@ -1,44 +0,0 @@
-#ifndef ASM_X86__VSYSCALL_H
-#define ASM_X86__VSYSCALL_H
-
-enum vsyscall_num {
-	__NR_vgettimeofday,
-	__NR_vtime,
-	__NR_vgetcpu,
-};
-
-#define VSYSCALL_START (-10UL << 20)
-#define VSYSCALL_SIZE 1024
-#define VSYSCALL_END (-2UL << 20)
-#define VSYSCALL_MAPPED_PAGES 1
-#define VSYSCALL_ADDR(vsyscall_nr) (VSYSCALL_START+VSYSCALL_SIZE*(vsyscall_nr))
-
-#ifdef __KERNEL__
-#include <linux/seqlock.h>
-
-#define __section_vgetcpu_mode __attribute__ ((unused, __section__ (".vgetcpu_mode"), aligned(16)))
-#define __section_jiffies __attribute__ ((unused, __section__ (".jiffies"), aligned(16)))
-
-/* Definitions for CONFIG_GENERIC_TIME definitions */
-#define __section_vsyscall_gtod_data __attribute__ \
-	((unused, __section__ (".vsyscall_gtod_data"),aligned(16)))
-#define __section_vsyscall_clock __attribute__ \
-	((unused, __section__ (".vsyscall_clock"),aligned(16)))
-#define __vsyscall_fn \
-	__attribute__ ((unused, __section__(".vsyscall_fn"))) notrace
-
-#define VGETCPU_RDTSCP	1
-#define VGETCPU_LSL	2
-
-extern int __vgetcpu_mode;
-extern volatile unsigned long __jiffies;
-
-/* kernel space (writeable) */
-extern int vgetcpu_mode;
-extern struct timezone sys_tz;
-
-extern void map_vsyscall(void);
-
-#endif /* __KERNEL__ */
-
-#endif /* ASM_X86__VSYSCALL_H */
diff --git a/include/asm-x86/xcr.h b/include/asm-x86/xcr.h
deleted file mode 100644
index f2cba4e79a23..000000000000
--- a/include/asm-x86/xcr.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* -*- linux-c -*- ------------------------------------------------------- *
- *
- *   Copyright 2008 rPath, Inc. - All Rights Reserved
- *
- *   This file is part of the Linux kernel, and is made available under
- *   the terms of the GNU General Public License version 2 or (at your
- *   option) any later version; incorporated herein by reference.
- *
- * ----------------------------------------------------------------------- */
-
-/*
- * asm-x86/xcr.h
- *
- * Definitions for the eXtended Control Register instructions
- */
-
-#ifndef _ASM_X86_XCR_H
-#define _ASM_X86_XCR_H
-
-#define XCR_XFEATURE_ENABLED_MASK	0x00000000
-
-#ifdef __KERNEL__
-# ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-static inline u64 xgetbv(u32 index)
-{
-	u32 eax, edx;
-
-	asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */
-		     : "=a" (eax), "=d" (edx)
-		     : "c" (index));
-	return eax + ((u64)edx << 32);
-}
-
-static inline void xsetbv(u32 index, u64 value)
-{
-	u32 eax = value;
-	u32 edx = value >> 32;
-
-	asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */
-		     : : "a" (eax), "d" (edx), "c" (index));
-}
-
-# endif /* __ASSEMBLY__ */
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_X86_XCR_H */
diff --git a/include/asm-x86/xen/events.h b/include/asm-x86/xen/events.h
deleted file mode 100644
index 8151f5b8b6cb..000000000000
--- a/include/asm-x86/xen/events.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef ASM_X86__XEN__EVENTS_H
-#define ASM_X86__XEN__EVENTS_H
-
-enum ipi_vector {
-	XEN_RESCHEDULE_VECTOR,
-	XEN_CALL_FUNCTION_VECTOR,
-	XEN_CALL_FUNCTION_SINGLE_VECTOR,
-	XEN_SPIN_UNLOCK_VECTOR,
-
-	XEN_NR_IPIS,
-};
-
-static inline int xen_irqs_disabled(struct pt_regs *regs)
-{
-	return raw_irqs_disabled_flags(regs->flags);
-}
-
-static inline void xen_do_IRQ(int irq, struct pt_regs *regs)
-{
-	regs->orig_ax = ~irq;
-	do_IRQ(regs);
-}
-
-#endif /* ASM_X86__XEN__EVENTS_H */
diff --git a/include/asm-x86/xen/grant_table.h b/include/asm-x86/xen/grant_table.h
deleted file mode 100644
index c4baab4d2b68..000000000000
--- a/include/asm-x86/xen/grant_table.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef ASM_X86__XEN__GRANT_TABLE_H
-#define ASM_X86__XEN__GRANT_TABLE_H
-
-#define xen_alloc_vm_area(size)	alloc_vm_area(size)
-#define xen_free_vm_area(area)	free_vm_area(area)
-
-#endif /* ASM_X86__XEN__GRANT_TABLE_H */
diff --git a/include/asm-x86/xen/hypercall.h b/include/asm-x86/xen/hypercall.h
deleted file mode 100644
index 44f4259bee3f..000000000000
--- a/include/asm-x86/xen/hypercall.h
+++ /dev/null
@@ -1,527 +0,0 @@
-/******************************************************************************
- * hypercall.h
- *
- * Linux-specific hypervisor handling.
- *
- * Copyright (c) 2002-2004, K A Fraser
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation; or, when distributed
- * separately from the Linux kernel or incorporated into other
- * software packages, subject to the following license:
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this source file (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy, modify,
- * merge, publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#ifndef ASM_X86__XEN__HYPERCALL_H
-#define ASM_X86__XEN__HYPERCALL_H
-
-#include <linux/errno.h>
-#include <linux/string.h>
-
-#include <xen/interface/xen.h>
-#include <xen/interface/sched.h>
-#include <xen/interface/physdev.h>
-
-/*
- * The hypercall asms have to meet several constraints:
- * - Work on 32- and 64-bit.
- *    The two architectures put their arguments in different sets of
- *    registers.
- *
- * - Work around asm syntax quirks
- *    It isn't possible to specify one of the rNN registers in a
- *    constraint, so we use explicit register variables to get the
- *    args into the right place.
- *
- * - Mark all registers as potentially clobbered
- *    Even unused parameters can be clobbered by the hypervisor, so we
- *    need to make sure gcc knows it.
- *
- * - Avoid compiler bugs.
- *    This is the tricky part.  Because x86_32 has such a constrained
- *    register set, gcc versions below 4.3 have trouble generating
- *    code when all the arg registers and memory are trashed by the
- *    asm.  There are syntactically simpler ways of achieving the
- *    semantics below, but they cause the compiler to crash.
- *
- *    The only combination I found which works is:
- *     - assign the __argX variables first
- *     - list all actually used parameters as "+r" (__argX)
- *     - clobber the rest
- *
- * The result certainly isn't pretty, and it really shows up cpp's
- * weakness as as macro language.  Sorry.  (But let's just give thanks
- * there aren't more than 5 arguments...)
- */
-
-extern struct { char _entry[32]; } hypercall_page[];
-
-#define __HYPERCALL		"call hypercall_page+%c[offset]"
-#define __HYPERCALL_ENTRY(x)						\
-	[offset] "i" (__HYPERVISOR_##x * sizeof(hypercall_page[0]))
-
-#ifdef CONFIG_X86_32
-#define __HYPERCALL_RETREG	"eax"
-#define __HYPERCALL_ARG1REG	"ebx"
-#define __HYPERCALL_ARG2REG	"ecx"
-#define __HYPERCALL_ARG3REG	"edx"
-#define __HYPERCALL_ARG4REG	"esi"
-#define __HYPERCALL_ARG5REG	"edi"
-#else
-#define __HYPERCALL_RETREG	"rax"
-#define __HYPERCALL_ARG1REG	"rdi"
-#define __HYPERCALL_ARG2REG	"rsi"
-#define __HYPERCALL_ARG3REG	"rdx"
-#define __HYPERCALL_ARG4REG	"r10"
-#define __HYPERCALL_ARG5REG	"r8"
-#endif
-
-#define __HYPERCALL_DECLS						\
-	register unsigned long __res  asm(__HYPERCALL_RETREG);		\
-	register unsigned long __arg1 asm(__HYPERCALL_ARG1REG) = __arg1; \
-	register unsigned long __arg2 asm(__HYPERCALL_ARG2REG) = __arg2; \
-	register unsigned long __arg3 asm(__HYPERCALL_ARG3REG) = __arg3; \
-	register unsigned long __arg4 asm(__HYPERCALL_ARG4REG) = __arg4; \
-	register unsigned long __arg5 asm(__HYPERCALL_ARG5REG) = __arg5;
-
-#define __HYPERCALL_0PARAM	"=r" (__res)
-#define __HYPERCALL_1PARAM	__HYPERCALL_0PARAM, "+r" (__arg1)
-#define __HYPERCALL_2PARAM	__HYPERCALL_1PARAM, "+r" (__arg2)
-#define __HYPERCALL_3PARAM	__HYPERCALL_2PARAM, "+r" (__arg3)
-#define __HYPERCALL_4PARAM	__HYPERCALL_3PARAM, "+r" (__arg4)
-#define __HYPERCALL_5PARAM	__HYPERCALL_4PARAM, "+r" (__arg5)
-
-#define __HYPERCALL_0ARG()
-#define __HYPERCALL_1ARG(a1)						\
-	__HYPERCALL_0ARG()		__arg1 = (unsigned long)(a1);
-#define __HYPERCALL_2ARG(a1,a2)						\
-	__HYPERCALL_1ARG(a1)		__arg2 = (unsigned long)(a2);
-#define __HYPERCALL_3ARG(a1,a2,a3)					\
-	__HYPERCALL_2ARG(a1,a2)		__arg3 = (unsigned long)(a3);
-#define __HYPERCALL_4ARG(a1,a2,a3,a4)					\
-	__HYPERCALL_3ARG(a1,a2,a3)	__arg4 = (unsigned long)(a4);
-#define __HYPERCALL_5ARG(a1,a2,a3,a4,a5)				\
-	__HYPERCALL_4ARG(a1,a2,a3,a4)	__arg5 = (unsigned long)(a5);
-
-#define __HYPERCALL_CLOBBER5	"memory"
-#define __HYPERCALL_CLOBBER4	__HYPERCALL_CLOBBER5, __HYPERCALL_ARG5REG
-#define __HYPERCALL_CLOBBER3	__HYPERCALL_CLOBBER4, __HYPERCALL_ARG4REG
-#define __HYPERCALL_CLOBBER2	__HYPERCALL_CLOBBER3, __HYPERCALL_ARG3REG
-#define __HYPERCALL_CLOBBER1	__HYPERCALL_CLOBBER2, __HYPERCALL_ARG2REG
-#define __HYPERCALL_CLOBBER0	__HYPERCALL_CLOBBER1, __HYPERCALL_ARG1REG
-
-#define _hypercall0(type, name)						\
-({									\
-	__HYPERCALL_DECLS;						\
-	__HYPERCALL_0ARG();						\
-	asm volatile (__HYPERCALL					\
-		      : __HYPERCALL_0PARAM				\
-		      : __HYPERCALL_ENTRY(name)				\
-		      : __HYPERCALL_CLOBBER0);				\
-	(type)__res;							\
-})
-
-#define _hypercall1(type, name, a1)					\
-({									\
-	__HYPERCALL_DECLS;						\
-	__HYPERCALL_1ARG(a1);						\
-	asm volatile (__HYPERCALL					\
-		      : __HYPERCALL_1PARAM				\
-		      : __HYPERCALL_ENTRY(name)				\
-		      : __HYPERCALL_CLOBBER1);				\
-	(type)__res;							\
-})
-
-#define _hypercall2(type, name, a1, a2)					\
-({									\
-	__HYPERCALL_DECLS;						\
-	__HYPERCALL_2ARG(a1, a2);					\
-	asm volatile (__HYPERCALL					\
-		      : __HYPERCALL_2PARAM				\
-		      : __HYPERCALL_ENTRY(name)				\
-		      : __HYPERCALL_CLOBBER2);				\
-	(type)__res;							\
-})
-
-#define _hypercall3(type, name, a1, a2, a3)				\
-({									\
-	__HYPERCALL_DECLS;						\
-	__HYPERCALL_3ARG(a1, a2, a3);					\
-	asm volatile (__HYPERCALL					\
-		      : __HYPERCALL_3PARAM				\
-		      : __HYPERCALL_ENTRY(name)				\
-		      : __HYPERCALL_CLOBBER3);				\
-	(type)__res;							\
-})
-
-#define _hypercall4(type, name, a1, a2, a3, a4)				\
-({									\
-	__HYPERCALL_DECLS;						\
-	__HYPERCALL_4ARG(a1, a2, a3, a4);				\
-	asm volatile (__HYPERCALL					\
-		      : __HYPERCALL_4PARAM				\
-		      : __HYPERCALL_ENTRY(name)				\
-		      : __HYPERCALL_CLOBBER4);				\
-	(type)__res;							\
-})
-
-#define _hypercall5(type, name, a1, a2, a3, a4, a5)			\
-({									\
-	__HYPERCALL_DECLS;						\
-	__HYPERCALL_5ARG(a1, a2, a3, a4, a5);				\
-	asm volatile (__HYPERCALL					\
-		      : __HYPERCALL_5PARAM				\
-		      : __HYPERCALL_ENTRY(name)				\
-		      : __HYPERCALL_CLOBBER5);				\
-	(type)__res;							\
-})
-
-static inline int
-HYPERVISOR_set_trap_table(struct trap_info *table)
-{
-	return _hypercall1(int, set_trap_table, table);
-}
-
-static inline int
-HYPERVISOR_mmu_update(struct mmu_update *req, int count,
-		      int *success_count, domid_t domid)
-{
-	return _hypercall4(int, mmu_update, req, count, success_count, domid);
-}
-
-static inline int
-HYPERVISOR_mmuext_op(struct mmuext_op *op, int count,
-		     int *success_count, domid_t domid)
-{
-	return _hypercall4(int, mmuext_op, op, count, success_count, domid);
-}
-
-static inline int
-HYPERVISOR_set_gdt(unsigned long *frame_list, int entries)
-{
-	return _hypercall2(int, set_gdt, frame_list, entries);
-}
-
-static inline int
-HYPERVISOR_stack_switch(unsigned long ss, unsigned long esp)
-{
-	return _hypercall2(int, stack_switch, ss, esp);
-}
-
-#ifdef CONFIG_X86_32
-static inline int
-HYPERVISOR_set_callbacks(unsigned long event_selector,
-			 unsigned long event_address,
-			 unsigned long failsafe_selector,
-			 unsigned long failsafe_address)
-{
-	return _hypercall4(int, set_callbacks,
-			   event_selector, event_address,
-			   failsafe_selector, failsafe_address);
-}
-#else  /* CONFIG_X86_64 */
-static inline int
-HYPERVISOR_set_callbacks(unsigned long event_address,
-			unsigned long failsafe_address,
-			unsigned long syscall_address)
-{
-	return _hypercall3(int, set_callbacks,
-			   event_address, failsafe_address,
-			   syscall_address);
-}
-#endif  /* CONFIG_X86_{32,64} */
-
-static inline int
-HYPERVISOR_callback_op(int cmd, void *arg)
-{
-	return _hypercall2(int, callback_op, cmd, arg);
-}
-
-static inline int
-HYPERVISOR_fpu_taskswitch(int set)
-{
-	return _hypercall1(int, fpu_taskswitch, set);
-}
-
-static inline int
-HYPERVISOR_sched_op(int cmd, void *arg)
-{
-	return _hypercall2(int, sched_op_new, cmd, arg);
-}
-
-static inline long
-HYPERVISOR_set_timer_op(u64 timeout)
-{
-	unsigned long timeout_hi = (unsigned long)(timeout>>32);
-	unsigned long timeout_lo = (unsigned long)timeout;
-	return _hypercall2(long, set_timer_op, timeout_lo, timeout_hi);
-}
-
-static inline int
-HYPERVISOR_set_debugreg(int reg, unsigned long value)
-{
-	return _hypercall2(int, set_debugreg, reg, value);
-}
-
-static inline unsigned long
-HYPERVISOR_get_debugreg(int reg)
-{
-	return _hypercall1(unsigned long, get_debugreg, reg);
-}
-
-static inline int
-HYPERVISOR_update_descriptor(u64 ma, u64 desc)
-{
-	return _hypercall4(int, update_descriptor, ma, ma>>32, desc, desc>>32);
-}
-
-static inline int
-HYPERVISOR_memory_op(unsigned int cmd, void *arg)
-{
-	return _hypercall2(int, memory_op, cmd, arg);
-}
-
-static inline int
-HYPERVISOR_multicall(void *call_list, int nr_calls)
-{
-	return _hypercall2(int, multicall, call_list, nr_calls);
-}
-
-static inline int
-HYPERVISOR_update_va_mapping(unsigned long va, pte_t new_val,
-			     unsigned long flags)
-{
-	if (sizeof(new_val) == sizeof(long))
-		return _hypercall3(int, update_va_mapping, va,
-				   new_val.pte, flags);
-	else
-		return _hypercall4(int, update_va_mapping, va,
-				   new_val.pte, new_val.pte >> 32, flags);
-}
-
-static inline int
-HYPERVISOR_event_channel_op(int cmd, void *arg)
-{
-	int rc = _hypercall2(int, event_channel_op, cmd, arg);
-	if (unlikely(rc == -ENOSYS)) {
-		struct evtchn_op op;
-		op.cmd = cmd;
-		memcpy(&op.u, arg, sizeof(op.u));
-		rc = _hypercall1(int, event_channel_op_compat, &op);
-		memcpy(arg, &op.u, sizeof(op.u));
-	}
-	return rc;
-}
-
-static inline int
-HYPERVISOR_xen_version(int cmd, void *arg)
-{
-	return _hypercall2(int, xen_version, cmd, arg);
-}
-
-static inline int
-HYPERVISOR_console_io(int cmd, int count, char *str)
-{
-	return _hypercall3(int, console_io, cmd, count, str);
-}
-
-static inline int
-HYPERVISOR_physdev_op(int cmd, void *arg)
-{
-	int rc = _hypercall2(int, physdev_op, cmd, arg);
-	if (unlikely(rc == -ENOSYS)) {
-		struct physdev_op op;
-		op.cmd = cmd;
-		memcpy(&op.u, arg, sizeof(op.u));
-		rc = _hypercall1(int, physdev_op_compat, &op);
-		memcpy(arg, &op.u, sizeof(op.u));
-	}
-	return rc;
-}
-
-static inline int
-HYPERVISOR_grant_table_op(unsigned int cmd, void *uop, unsigned int count)
-{
-	return _hypercall3(int, grant_table_op, cmd, uop, count);
-}
-
-static inline int
-HYPERVISOR_update_va_mapping_otherdomain(unsigned long va, pte_t new_val,
-					 unsigned long flags, domid_t domid)
-{
-	if (sizeof(new_val) == sizeof(long))
-		return _hypercall4(int, update_va_mapping_otherdomain, va,
-				   new_val.pte, flags, domid);
-	else
-		return _hypercall5(int, update_va_mapping_otherdomain, va,
-				   new_val.pte, new_val.pte >> 32,
-				   flags, domid);
-}
-
-static inline int
-HYPERVISOR_vm_assist(unsigned int cmd, unsigned int type)
-{
-	return _hypercall2(int, vm_assist, cmd, type);
-}
-
-static inline int
-HYPERVISOR_vcpu_op(int cmd, int vcpuid, void *extra_args)
-{
-	return _hypercall3(int, vcpu_op, cmd, vcpuid, extra_args);
-}
-
-#ifdef CONFIG_X86_64
-static inline int
-HYPERVISOR_set_segment_base(int reg, unsigned long value)
-{
-	return _hypercall2(int, set_segment_base, reg, value);
-}
-#endif
-
-static inline int
-HYPERVISOR_suspend(unsigned long srec)
-{
-	return _hypercall3(int, sched_op, SCHEDOP_shutdown,
-			   SHUTDOWN_suspend, srec);
-}
-
-static inline int
-HYPERVISOR_nmi_op(unsigned long op, unsigned long arg)
-{
-	return _hypercall2(int, nmi_op, op, arg);
-}
-
-static inline void
-MULTI_fpu_taskswitch(struct multicall_entry *mcl, int set)
-{
-	mcl->op = __HYPERVISOR_fpu_taskswitch;
-	mcl->args[0] = set;
-}
-
-static inline void
-MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va,
-			pte_t new_val, unsigned long flags)
-{
-	mcl->op = __HYPERVISOR_update_va_mapping;
-	mcl->args[0] = va;
-	if (sizeof(new_val) == sizeof(long)) {
-		mcl->args[1] = new_val.pte;
-		mcl->args[2] = flags;
-	} else {
-		mcl->args[1] = new_val.pte;
-		mcl->args[2] = new_val.pte >> 32;
-		mcl->args[3] = flags;
-	}
-}
-
-static inline void
-MULTI_grant_table_op(struct multicall_entry *mcl, unsigned int cmd,
-		     void *uop, unsigned int count)
-{
-	mcl->op = __HYPERVISOR_grant_table_op;
-	mcl->args[0] = cmd;
-	mcl->args[1] = (unsigned long)uop;
-	mcl->args[2] = count;
-}
-
-static inline void
-MULTI_update_va_mapping_otherdomain(struct multicall_entry *mcl, unsigned long va,
-				    pte_t new_val, unsigned long flags,
-				    domid_t domid)
-{
-	mcl->op = __HYPERVISOR_update_va_mapping_otherdomain;
-	mcl->args[0] = va;
-	if (sizeof(new_val) == sizeof(long)) {
-		mcl->args[1] = new_val.pte;
-		mcl->args[2] = flags;
-		mcl->args[3] = domid;
-	} else {
-		mcl->args[1] = new_val.pte;
-		mcl->args[2] = new_val.pte >> 32;
-		mcl->args[3] = flags;
-		mcl->args[4] = domid;
-	}
-}
-
-static inline void
-MULTI_update_descriptor(struct multicall_entry *mcl, u64 maddr,
-			struct desc_struct desc)
-{
-	mcl->op = __HYPERVISOR_update_descriptor;
-	if (sizeof(maddr) == sizeof(long)) {
-		mcl->args[0] = maddr;
-		mcl->args[1] = *(unsigned long *)&desc;
-	} else {
-		mcl->args[0] = maddr;
-		mcl->args[1] = maddr >> 32;
-		mcl->args[2] = desc.a;
-		mcl->args[3] = desc.b;
-	}
-}
-
-static inline void
-MULTI_memory_op(struct multicall_entry *mcl, unsigned int cmd, void *arg)
-{
-	mcl->op = __HYPERVISOR_memory_op;
-	mcl->args[0] = cmd;
-	mcl->args[1] = (unsigned long)arg;
-}
-
-static inline void
-MULTI_mmu_update(struct multicall_entry *mcl, struct mmu_update *req,
-		 int count, int *success_count, domid_t domid)
-{
-	mcl->op = __HYPERVISOR_mmu_update;
-	mcl->args[0] = (unsigned long)req;
-	mcl->args[1] = count;
-	mcl->args[2] = (unsigned long)success_count;
-	mcl->args[3] = domid;
-}
-
-static inline void
-MULTI_mmuext_op(struct multicall_entry *mcl, struct mmuext_op *op, int count,
-		int *success_count, domid_t domid)
-{
-	mcl->op = __HYPERVISOR_mmuext_op;
-	mcl->args[0] = (unsigned long)op;
-	mcl->args[1] = count;
-	mcl->args[2] = (unsigned long)success_count;
-	mcl->args[3] = domid;
-}
-
-static inline void
-MULTI_set_gdt(struct multicall_entry *mcl, unsigned long *frames, int entries)
-{
-	mcl->op = __HYPERVISOR_set_gdt;
-	mcl->args[0] = (unsigned long)frames;
-	mcl->args[1] = entries;
-}
-
-static inline void
-MULTI_stack_switch(struct multicall_entry *mcl,
-		   unsigned long ss, unsigned long esp)
-{
-	mcl->op = __HYPERVISOR_stack_switch;
-	mcl->args[0] = ss;
-	mcl->args[1] = esp;
-}
-
-#endif /* ASM_X86__XEN__HYPERCALL_H */
diff --git a/include/asm-x86/xen/hypervisor.h b/include/asm-x86/xen/hypervisor.h
deleted file mode 100644
index 445a24759560..000000000000
--- a/include/asm-x86/xen/hypervisor.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/******************************************************************************
- * hypervisor.h
- *
- * Linux-specific hypervisor handling.
- *
- * Copyright (c) 2002-2004, K A Fraser
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation; or, when distributed
- * separately from the Linux kernel or incorporated into other
- * software packages, subject to the following license:
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this source file (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy, modify,
- * merge, publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#ifndef ASM_X86__XEN__HYPERVISOR_H
-#define ASM_X86__XEN__HYPERVISOR_H
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-
-#include <xen/interface/xen.h>
-#include <xen/interface/version.h>
-
-#include <asm/ptrace.h>
-#include <asm/page.h>
-#include <asm/desc.h>
-#if defined(__i386__)
-#  ifdef CONFIG_X86_PAE
-#   include <asm-generic/pgtable-nopud.h>
-#  else
-#   include <asm-generic/pgtable-nopmd.h>
-#  endif
-#endif
-#include <asm/xen/hypercall.h>
-
-/* arch/i386/kernel/setup.c */
-extern struct shared_info *HYPERVISOR_shared_info;
-extern struct start_info *xen_start_info;
-
-/* arch/i386/mach-xen/evtchn.c */
-/* Force a proper event-channel callback from Xen. */
-extern void force_evtchn_callback(void);
-
-/* Turn jiffies into Xen system time. */
-u64 jiffies_to_st(unsigned long jiffies);
-
-
-#define MULTI_UVMFLAGS_INDEX 3
-#define MULTI_UVMDOMID_INDEX 4
-
-enum xen_domain_type {
-	XEN_NATIVE,
-	XEN_PV_DOMAIN,
-	XEN_HVM_DOMAIN,
-};
-
-extern enum xen_domain_type xen_domain_type;
-
-#define xen_domain()		(xen_domain_type != XEN_NATIVE)
-#define xen_pv_domain()		(xen_domain_type == XEN_PV_DOMAIN)
-#define xen_initial_domain()	(xen_pv_domain() && xen_start_info->flags & SIF_INITDOMAIN)
-#define xen_hvm_domain()	(xen_domain_type == XEN_HVM_DOMAIN)
-
-#endif /* ASM_X86__XEN__HYPERVISOR_H */
diff --git a/include/asm-x86/xen/interface.h b/include/asm-x86/xen/interface.h
deleted file mode 100644
index d077bba96da9..000000000000
--- a/include/asm-x86/xen/interface.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/******************************************************************************
- * arch-x86_32.h
- *
- * Guest OS interface to x86 Xen.
- *
- * Copyright (c) 2004, K A Fraser
- */
-
-#ifndef ASM_X86__XEN__INTERFACE_H
-#define ASM_X86__XEN__INTERFACE_H
-
-#ifdef __XEN__
-#define __DEFINE_GUEST_HANDLE(name, type) \
-    typedef struct { type *p; } __guest_handle_ ## name
-#else
-#define __DEFINE_GUEST_HANDLE(name, type) \
-    typedef type * __guest_handle_ ## name
-#endif
-
-#define DEFINE_GUEST_HANDLE_STRUCT(name) \
-	__DEFINE_GUEST_HANDLE(name, struct name)
-#define DEFINE_GUEST_HANDLE(name) __DEFINE_GUEST_HANDLE(name, name)
-#define GUEST_HANDLE(name)        __guest_handle_ ## name
-
-#ifdef __XEN__
-#if defined(__i386__)
-#define set_xen_guest_handle(hnd, val)			\
-	do {						\
-		if (sizeof(hnd) == 8)			\
-			*(uint64_t *)&(hnd) = 0;	\
-		(hnd).p = val;				\
-	} while (0)
-#elif defined(__x86_64__)
-#define set_xen_guest_handle(hnd, val)	do { (hnd).p = val; } while (0)
-#endif
-#else
-#if defined(__i386__)
-#define set_xen_guest_handle(hnd, val)			\
-	do {						\
-		if (sizeof(hnd) == 8)			\
-			*(uint64_t *)&(hnd) = 0;	\
-		(hnd) = val;				\
-	} while (0)
-#elif defined(__x86_64__)
-#define set_xen_guest_handle(hnd, val)	do { (hnd) = val; } while (0)
-#endif
-#endif
-
-#ifndef __ASSEMBLY__
-/* Guest handles for primitive C types. */
-__DEFINE_GUEST_HANDLE(uchar, unsigned char);
-__DEFINE_GUEST_HANDLE(uint,  unsigned int);
-__DEFINE_GUEST_HANDLE(ulong, unsigned long);
-DEFINE_GUEST_HANDLE(char);
-DEFINE_GUEST_HANDLE(int);
-DEFINE_GUEST_HANDLE(long);
-DEFINE_GUEST_HANDLE(void);
-#endif
-
-#ifndef HYPERVISOR_VIRT_START
-#define HYPERVISOR_VIRT_START mk_unsigned_long(__HYPERVISOR_VIRT_START)
-#endif
-
-#ifndef machine_to_phys_mapping
-#define machine_to_phys_mapping ((unsigned long *)HYPERVISOR_VIRT_START)
-#endif
-
-/* Maximum number of virtual CPUs in multi-processor guests. */
-#define MAX_VIRT_CPUS 32
-
-/*
- * SEGMENT DESCRIPTOR TABLES
- */
-/*
- * A number of GDT entries are reserved by Xen. These are not situated at the
- * start of the GDT because some stupid OSes export hard-coded selector values
- * in their ABI. These hard-coded values are always near the start of the GDT,
- * so Xen places itself out of the way, at the far end of the GDT.
- */
-#define FIRST_RESERVED_GDT_PAGE  14
-#define FIRST_RESERVED_GDT_BYTE  (FIRST_RESERVED_GDT_PAGE * 4096)
-#define FIRST_RESERVED_GDT_ENTRY (FIRST_RESERVED_GDT_BYTE / 8)
-
-/*
- * Send an array of these to HYPERVISOR_set_trap_table()
- * The privilege level specifies which modes may enter a trap via a software
- * interrupt. On x86/64, since rings 1 and 2 are unavailable, we allocate
- * privilege levels as follows:
- *  Level == 0: Noone may enter
- *  Level == 1: Kernel may enter
- *  Level == 2: Kernel may enter
- *  Level == 3: Everyone may enter
- */
-#define TI_GET_DPL(_ti)		((_ti)->flags & 3)
-#define TI_GET_IF(_ti)		((_ti)->flags & 4)
-#define TI_SET_DPL(_ti, _dpl)	((_ti)->flags |= (_dpl))
-#define TI_SET_IF(_ti, _if)	((_ti)->flags |= ((!!(_if))<<2))
-
-#ifndef __ASSEMBLY__
-struct trap_info {
-    uint8_t       vector;  /* exception vector                              */
-    uint8_t       flags;   /* 0-3: privilege level; 4: clear event enable?  */
-    uint16_t      cs;      /* code selector                                 */
-    unsigned long address; /* code offset                                   */
-};
-DEFINE_GUEST_HANDLE_STRUCT(trap_info);
-
-struct arch_shared_info {
-    unsigned long max_pfn;                  /* max pfn that appears in table */
-    /* Frame containing list of mfns containing list of mfns containing p2m. */
-    unsigned long pfn_to_mfn_frame_list_list;
-    unsigned long nmi_reason;
-};
-#endif	/* !__ASSEMBLY__ */
-
-#ifdef CONFIG_X86_32
-#include "interface_32.h"
-#else
-#include "interface_64.h"
-#endif
-
-#ifndef __ASSEMBLY__
-/*
- * The following is all CPU context. Note that the fpu_ctxt block is filled
- * in by FXSAVE if the CPU has feature FXSR; otherwise FSAVE is used.
- */
-struct vcpu_guest_context {
-    /* FPU registers come first so they can be aligned for FXSAVE/FXRSTOR. */
-    struct { char x[512]; } fpu_ctxt;       /* User-level FPU registers     */
-#define VGCF_I387_VALID (1<<0)
-#define VGCF_HVM_GUEST  (1<<1)
-#define VGCF_IN_KERNEL  (1<<2)
-    unsigned long flags;                    /* VGCF_* flags                 */
-    struct cpu_user_regs user_regs;         /* User-level CPU registers     */
-    struct trap_info trap_ctxt[256];        /* Virtual IDT                  */
-    unsigned long ldt_base, ldt_ents;       /* LDT (linear address, # ents) */
-    unsigned long gdt_frames[16], gdt_ents; /* GDT (machine frames, # ents) */
-    unsigned long kernel_ss, kernel_sp;     /* Virtual TSS (only SS1/SP1)   */
-    /* NB. User pagetable on x86/64 is placed in ctrlreg[1]. */
-    unsigned long ctrlreg[8];               /* CR0-CR7 (control registers)  */
-    unsigned long debugreg[8];              /* DB0-DB7 (debug registers)    */
-#ifdef __i386__
-    unsigned long event_callback_cs;        /* CS:EIP of event callback     */
-    unsigned long event_callback_eip;
-    unsigned long failsafe_callback_cs;     /* CS:EIP of failsafe callback  */
-    unsigned long failsafe_callback_eip;
-#else
-    unsigned long event_callback_eip;
-    unsigned long failsafe_callback_eip;
-    unsigned long syscall_callback_eip;
-#endif
-    unsigned long vm_assist;                /* VMASST_TYPE_* bitmap */
-#ifdef __x86_64__
-    /* Segment base addresses. */
-    uint64_t      fs_base;
-    uint64_t      gs_base_kernel;
-    uint64_t      gs_base_user;
-#endif
-};
-DEFINE_GUEST_HANDLE_STRUCT(vcpu_guest_context);
-#endif	/* !__ASSEMBLY__ */
-
-/*
- * Prefix forces emulation of some non-trapping instructions.
- * Currently only CPUID.
- */
-#ifdef __ASSEMBLY__
-#define XEN_EMULATE_PREFIX .byte 0x0f,0x0b,0x78,0x65,0x6e ;
-#define XEN_CPUID          XEN_EMULATE_PREFIX cpuid
-#else
-#define XEN_EMULATE_PREFIX ".byte 0x0f,0x0b,0x78,0x65,0x6e ; "
-#define XEN_CPUID          XEN_EMULATE_PREFIX "cpuid"
-#endif
-
-#endif /* ASM_X86__XEN__INTERFACE_H */
diff --git a/include/asm-x86/xen/interface_32.h b/include/asm-x86/xen/interface_32.h
deleted file mode 100644
index 08167e19fc66..000000000000
--- a/include/asm-x86/xen/interface_32.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/******************************************************************************
- * arch-x86_32.h
- *
- * Guest OS interface to x86 32-bit Xen.
- *
- * Copyright (c) 2004, K A Fraser
- */
-
-#ifndef ASM_X86__XEN__INTERFACE_32_H
-#define ASM_X86__XEN__INTERFACE_32_H
-
-
-/*
- * These flat segments are in the Xen-private section of every GDT. Since these
- * are also present in the initial GDT, many OSes will be able to avoid
- * installing their own GDT.
- */
-#define FLAT_RING1_CS 0xe019    /* GDT index 259 */
-#define FLAT_RING1_DS 0xe021    /* GDT index 260 */
-#define FLAT_RING1_SS 0xe021    /* GDT index 260 */
-#define FLAT_RING3_CS 0xe02b    /* GDT index 261 */
-#define FLAT_RING3_DS 0xe033    /* GDT index 262 */
-#define FLAT_RING3_SS 0xe033    /* GDT index 262 */
-
-#define FLAT_KERNEL_CS FLAT_RING1_CS
-#define FLAT_KERNEL_DS FLAT_RING1_DS
-#define FLAT_KERNEL_SS FLAT_RING1_SS
-#define FLAT_USER_CS    FLAT_RING3_CS
-#define FLAT_USER_DS    FLAT_RING3_DS
-#define FLAT_USER_SS    FLAT_RING3_SS
-
-/* And the trap vector is... */
-#define TRAP_INSTR "int $0x82"
-
-/*
- * Virtual addresses beyond this are not modifiable by guest OSes. The
- * machine->physical mapping table starts at this address, read-only.
- */
-#define __HYPERVISOR_VIRT_START 0xF5800000
-
-#ifndef __ASSEMBLY__
-
-struct cpu_user_regs {
-    uint32_t ebx;
-    uint32_t ecx;
-    uint32_t edx;
-    uint32_t esi;
-    uint32_t edi;
-    uint32_t ebp;
-    uint32_t eax;
-    uint16_t error_code;    /* private */
-    uint16_t entry_vector;  /* private */
-    uint32_t eip;
-    uint16_t cs;
-    uint8_t  saved_upcall_mask;
-    uint8_t  _pad0;
-    uint32_t eflags;        /* eflags.IF == !saved_upcall_mask */
-    uint32_t esp;
-    uint16_t ss, _pad1;
-    uint16_t es, _pad2;
-    uint16_t ds, _pad3;
-    uint16_t fs, _pad4;
-    uint16_t gs, _pad5;
-};
-DEFINE_GUEST_HANDLE_STRUCT(cpu_user_regs);
-
-typedef uint64_t tsc_timestamp_t; /* RDTSC timestamp */
-
-struct arch_vcpu_info {
-    unsigned long cr2;
-    unsigned long pad[5]; /* sizeof(struct vcpu_info) == 64 */
-};
-
-struct xen_callback {
-	unsigned long cs;
-	unsigned long eip;
-};
-typedef struct xen_callback xen_callback_t;
-
-#define XEN_CALLBACK(__cs, __eip)				\
-	((struct xen_callback){ .cs = (__cs), .eip = (unsigned long)(__eip) })
-#endif /* !__ASSEMBLY__ */
-
-
-/*
- * Page-directory addresses above 4GB do not fit into architectural %cr3.
- * When accessing %cr3, or equivalent field in vcpu_guest_context, guests
- * must use the following accessor macros to pack/unpack valid MFNs.
- *
- * Note that Xen is using the fact that the pagetable base is always
- * page-aligned, and putting the 12 MSB of the address into the 12 LSB
- * of cr3.
- */
-#define xen_pfn_to_cr3(pfn) (((unsigned)(pfn) << 12) | ((unsigned)(pfn) >> 20))
-#define xen_cr3_to_pfn(cr3) (((unsigned)(cr3) >> 12) | ((unsigned)(cr3) << 20))
-
-#endif /* ASM_X86__XEN__INTERFACE_32_H */
diff --git a/include/asm-x86/xen/interface_64.h b/include/asm-x86/xen/interface_64.h
deleted file mode 100644
index 046c0f1e01d4..000000000000
--- a/include/asm-x86/xen/interface_64.h
+++ /dev/null
@@ -1,159 +0,0 @@
-#ifndef ASM_X86__XEN__INTERFACE_64_H
-#define ASM_X86__XEN__INTERFACE_64_H
-
-/*
- * 64-bit segment selectors
- * These flat segments are in the Xen-private section of every GDT. Since these
- * are also present in the initial GDT, many OSes will be able to avoid
- * installing their own GDT.
- */
-
-#define FLAT_RING3_CS32 0xe023  /* GDT index 260 */
-#define FLAT_RING3_CS64 0xe033  /* GDT index 261 */
-#define FLAT_RING3_DS32 0xe02b  /* GDT index 262 */
-#define FLAT_RING3_DS64 0x0000  /* NULL selector */
-#define FLAT_RING3_SS32 0xe02b  /* GDT index 262 */
-#define FLAT_RING3_SS64 0xe02b  /* GDT index 262 */
-
-#define FLAT_KERNEL_DS64 FLAT_RING3_DS64
-#define FLAT_KERNEL_DS32 FLAT_RING3_DS32
-#define FLAT_KERNEL_DS   FLAT_KERNEL_DS64
-#define FLAT_KERNEL_CS64 FLAT_RING3_CS64
-#define FLAT_KERNEL_CS32 FLAT_RING3_CS32
-#define FLAT_KERNEL_CS   FLAT_KERNEL_CS64
-#define FLAT_KERNEL_SS64 FLAT_RING3_SS64
-#define FLAT_KERNEL_SS32 FLAT_RING3_SS32
-#define FLAT_KERNEL_SS   FLAT_KERNEL_SS64
-
-#define FLAT_USER_DS64 FLAT_RING3_DS64
-#define FLAT_USER_DS32 FLAT_RING3_DS32
-#define FLAT_USER_DS   FLAT_USER_DS64
-#define FLAT_USER_CS64 FLAT_RING3_CS64
-#define FLAT_USER_CS32 FLAT_RING3_CS32
-#define FLAT_USER_CS   FLAT_USER_CS64
-#define FLAT_USER_SS64 FLAT_RING3_SS64
-#define FLAT_USER_SS32 FLAT_RING3_SS32
-#define FLAT_USER_SS   FLAT_USER_SS64
-
-#define __HYPERVISOR_VIRT_START 0xFFFF800000000000
-#define __HYPERVISOR_VIRT_END   0xFFFF880000000000
-#define __MACH2PHYS_VIRT_START  0xFFFF800000000000
-#define __MACH2PHYS_VIRT_END    0xFFFF804000000000
-
-#ifndef HYPERVISOR_VIRT_START
-#define HYPERVISOR_VIRT_START mk_unsigned_long(__HYPERVISOR_VIRT_START)
-#define HYPERVISOR_VIRT_END   mk_unsigned_long(__HYPERVISOR_VIRT_END)
-#endif
-
-#define MACH2PHYS_VIRT_START  mk_unsigned_long(__MACH2PHYS_VIRT_START)
-#define MACH2PHYS_VIRT_END    mk_unsigned_long(__MACH2PHYS_VIRT_END)
-#define MACH2PHYS_NR_ENTRIES  ((MACH2PHYS_VIRT_END-MACH2PHYS_VIRT_START)>>3)
-#ifndef machine_to_phys_mapping
-#define machine_to_phys_mapping ((unsigned long *)HYPERVISOR_VIRT_START)
-#endif
-
-/*
- * int HYPERVISOR_set_segment_base(unsigned int which, unsigned long base)
- *  @which == SEGBASE_*  ;  @base == 64-bit base address
- * Returns 0 on success.
- */
-#define SEGBASE_FS          0
-#define SEGBASE_GS_USER     1
-#define SEGBASE_GS_KERNEL   2
-#define SEGBASE_GS_USER_SEL 3 /* Set user %gs specified in base[15:0] */
-
-/*
- * int HYPERVISOR_iret(void)
- * All arguments are on the kernel stack, in the following format.
- * Never returns if successful. Current kernel context is lost.
- * The saved CS is mapped as follows:
- *   RING0 -> RING3 kernel mode.
- *   RING1 -> RING3 kernel mode.
- *   RING2 -> RING3 kernel mode.
- *   RING3 -> RING3 user mode.
- * However RING0 indicates that the guest kernel should return to iteself
- * directly with
- *      orb   $3,1*8(%rsp)
- *      iretq
- * If flags contains VGCF_in_syscall:
- *   Restore RAX, RIP, RFLAGS, RSP.
- *   Discard R11, RCX, CS, SS.
- * Otherwise:
- *   Restore RAX, R11, RCX, CS:RIP, RFLAGS, SS:RSP.
- * All other registers are saved on hypercall entry and restored to user.
- */
-/* Guest exited in SYSCALL context? Return to guest with SYSRET? */
-#define _VGCF_in_syscall 8
-#define VGCF_in_syscall  (1<<_VGCF_in_syscall)
-#define VGCF_IN_SYSCALL  VGCF_in_syscall
-
-#ifndef __ASSEMBLY__
-
-struct iret_context {
-    /* Top of stack (%rsp at point of hypercall). */
-    uint64_t rax, r11, rcx, flags, rip, cs, rflags, rsp, ss;
-    /* Bottom of iret stack frame. */
-};
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-/* Anonymous union includes both 32- and 64-bit names (e.g., eax/rax). */
-#define __DECL_REG(name) union { \
-    uint64_t r ## name, e ## name; \
-    uint32_t _e ## name; \
-}
-#else
-/* Non-gcc sources must always use the proper 64-bit name (e.g., rax). */
-#define __DECL_REG(name) uint64_t r ## name
-#endif
-
-struct cpu_user_regs {
-    uint64_t r15;
-    uint64_t r14;
-    uint64_t r13;
-    uint64_t r12;
-    __DECL_REG(bp);
-    __DECL_REG(bx);
-    uint64_t r11;
-    uint64_t r10;
-    uint64_t r9;
-    uint64_t r8;
-    __DECL_REG(ax);
-    __DECL_REG(cx);
-    __DECL_REG(dx);
-    __DECL_REG(si);
-    __DECL_REG(di);
-    uint32_t error_code;    /* private */
-    uint32_t entry_vector;  /* private */
-    __DECL_REG(ip);
-    uint16_t cs, _pad0[1];
-    uint8_t  saved_upcall_mask;
-    uint8_t  _pad1[3];
-    __DECL_REG(flags);      /* rflags.IF == !saved_upcall_mask */
-    __DECL_REG(sp);
-    uint16_t ss, _pad2[3];
-    uint16_t es, _pad3[3];
-    uint16_t ds, _pad4[3];
-    uint16_t fs, _pad5[3]; /* Non-zero => takes precedence over fs_base.     */
-    uint16_t gs, _pad6[3]; /* Non-zero => takes precedence over gs_base_usr. */
-};
-DEFINE_GUEST_HANDLE_STRUCT(cpu_user_regs);
-
-#undef __DECL_REG
-
-#define xen_pfn_to_cr3(pfn) ((unsigned long)(pfn) << 12)
-#define xen_cr3_to_pfn(cr3) ((unsigned long)(cr3) >> 12)
-
-struct arch_vcpu_info {
-    unsigned long cr2;
-    unsigned long pad; /* sizeof(vcpu_info_t) == 64 */
-};
-
-typedef unsigned long xen_callback_t;
-
-#define XEN_CALLBACK(__cs, __rip)				\
-	((unsigned long)(__rip))
-
-#endif /* !__ASSEMBLY__ */
-
-
-#endif /* ASM_X86__XEN__INTERFACE_64_H */
diff --git a/include/asm-x86/xen/page.h b/include/asm-x86/xen/page.h
deleted file mode 100644
index c50185dccec1..000000000000
--- a/include/asm-x86/xen/page.h
+++ /dev/null
@@ -1,165 +0,0 @@
-#ifndef ASM_X86__XEN__PAGE_H
-#define ASM_X86__XEN__PAGE_H
-
-#include <linux/pfn.h>
-
-#include <asm/uaccess.h>
-#include <asm/pgtable.h>
-
-#include <xen/features.h>
-
-/* Xen machine address */
-typedef struct xmaddr {
-	phys_addr_t maddr;
-} xmaddr_t;
-
-/* Xen pseudo-physical address */
-typedef struct xpaddr {
-	phys_addr_t paddr;
-} xpaddr_t;
-
-#define XMADDR(x)	((xmaddr_t) { .maddr = (x) })
-#define XPADDR(x)	((xpaddr_t) { .paddr = (x) })
-
-/**** MACHINE <-> PHYSICAL CONVERSION MACROS ****/
-#define INVALID_P2M_ENTRY	(~0UL)
-#define FOREIGN_FRAME_BIT	(1UL<<31)
-#define FOREIGN_FRAME(m)	((m) | FOREIGN_FRAME_BIT)
-
-/* Maximum amount of memory we can handle in a domain in pages */
-#define MAX_DOMAIN_PAGES						\
-    ((unsigned long)((u64)CONFIG_XEN_MAX_DOMAIN_MEMORY * 1024 * 1024 * 1024 / PAGE_SIZE))
-
-
-extern unsigned long get_phys_to_machine(unsigned long pfn);
-extern void set_phys_to_machine(unsigned long pfn, unsigned long mfn);
-
-static inline unsigned long pfn_to_mfn(unsigned long pfn)
-{
-	if (xen_feature(XENFEAT_auto_translated_physmap))
-		return pfn;
-
-	return get_phys_to_machine(pfn) & ~FOREIGN_FRAME_BIT;
-}
-
-static inline int phys_to_machine_mapping_valid(unsigned long pfn)
-{
-	if (xen_feature(XENFEAT_auto_translated_physmap))
-		return 1;
-
-	return get_phys_to_machine(pfn) != INVALID_P2M_ENTRY;
-}
-
-static inline unsigned long mfn_to_pfn(unsigned long mfn)
-{
-	unsigned long pfn;
-
-	if (xen_feature(XENFEAT_auto_translated_physmap))
-		return mfn;
-
-#if 0
-	if (unlikely((mfn >> machine_to_phys_order) != 0))
-		return max_mapnr;
-#endif
-
-	pfn = 0;
-	/*
-	 * The array access can fail (e.g., device space beyond end of RAM).
-	 * In such cases it doesn't matter what we return (we return garbage),
-	 * but we must handle the fault without crashing!
-	 */
-	__get_user(pfn, &machine_to_phys_mapping[mfn]);
-
-	return pfn;
-}
-
-static inline xmaddr_t phys_to_machine(xpaddr_t phys)
-{
-	unsigned offset = phys.paddr & ~PAGE_MASK;
-	return XMADDR(PFN_PHYS((u64)pfn_to_mfn(PFN_DOWN(phys.paddr))) | offset);
-}
-
-static inline xpaddr_t machine_to_phys(xmaddr_t machine)
-{
-	unsigned offset = machine.maddr & ~PAGE_MASK;
-	return XPADDR(PFN_PHYS((u64)mfn_to_pfn(PFN_DOWN(machine.maddr))) | offset);
-}
-
-/*
- * We detect special mappings in one of two ways:
- *  1. If the MFN is an I/O page then Xen will set the m2p entry
- *     to be outside our maximum possible pseudophys range.
- *  2. If the MFN belongs to a different domain then we will certainly
- *     not have MFN in our p2m table. Conversely, if the page is ours,
- *     then we'll have p2m(m2p(MFN))==MFN.
- * If we detect a special mapping then it doesn't have a 'struct page'.
- * We force !pfn_valid() by returning an out-of-range pointer.
- *
- * NB. These checks require that, for any MFN that is not in our reservation,
- * there is no PFN such that p2m(PFN) == MFN. Otherwise we can get confused if
- * we are foreign-mapping the MFN, and the other domain as m2p(MFN) == PFN.
- * Yikes! Various places must poke in INVALID_P2M_ENTRY for safety.
- *
- * NB2. When deliberately mapping foreign pages into the p2m table, you *must*
- *      use FOREIGN_FRAME(). This will cause pte_pfn() to choke on it, as we
- *      require. In all the cases we care about, the FOREIGN_FRAME bit is
- *      masked (e.g., pfn_to_mfn()) so behaviour there is correct.
- */
-static inline unsigned long mfn_to_local_pfn(unsigned long mfn)
-{
-	extern unsigned long max_mapnr;
-	unsigned long pfn = mfn_to_pfn(mfn);
-	if ((pfn < max_mapnr)
-	    && !xen_feature(XENFEAT_auto_translated_physmap)
-	    && (get_phys_to_machine(pfn) != mfn))
-		return max_mapnr; /* force !pfn_valid() */
-	/* XXX fixme; not true with sparsemem */
-	return pfn;
-}
-
-/* VIRT <-> MACHINE conversion */
-#define virt_to_machine(v)	(phys_to_machine(XPADDR(__pa(v))))
-#define virt_to_mfn(v)		(pfn_to_mfn(PFN_DOWN(__pa(v))))
-#define mfn_to_virt(m)		(__va(mfn_to_pfn(m) << PAGE_SHIFT))
-
-static inline unsigned long pte_mfn(pte_t pte)
-{
-	return (pte.pte & PTE_PFN_MASK) >> PAGE_SHIFT;
-}
-
-static inline pte_t mfn_pte(unsigned long page_nr, pgprot_t pgprot)
-{
-	pte_t pte;
-
-	pte.pte = ((phys_addr_t)page_nr << PAGE_SHIFT) |
-		(pgprot_val(pgprot) & __supported_pte_mask);
-
-	return pte;
-}
-
-static inline pteval_t pte_val_ma(pte_t pte)
-{
-	return pte.pte;
-}
-
-static inline pte_t __pte_ma(pteval_t x)
-{
-	return (pte_t) { .pte = x };
-}
-
-#define pmd_val_ma(v) ((v).pmd)
-#ifdef __PAGETABLE_PUD_FOLDED
-#define pud_val_ma(v) ((v).pgd.pgd)
-#else
-#define pud_val_ma(v) ((v).pud)
-#endif
-#define __pmd_ma(x)	((pmd_t) { (x) } )
-
-#define pgd_val_ma(x)	((x).pgd)
-
-
-xmaddr_t arbitrary_virt_to_machine(void *address);
-void make_lowmem_page_readonly(void *vaddr);
-void make_lowmem_page_readwrite(void *vaddr);
-
-#endif /* ASM_X86__XEN__PAGE_H */
diff --git a/include/asm-x86/xor.h b/include/asm-x86/xor.h
deleted file mode 100644
index 11b3bb86e17b..000000000000
--- a/include/asm-x86/xor.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifdef CONFIG_X86_32
-# include "xor_32.h"
-#else
-# include "xor_64.h"
-#endif
diff --git a/include/asm-x86/xor_32.h b/include/asm-x86/xor_32.h
deleted file mode 100644
index 921b45840449..000000000000
--- a/include/asm-x86/xor_32.h
+++ /dev/null
@@ -1,888 +0,0 @@
-#ifndef ASM_X86__XOR_32_H
-#define ASM_X86__XOR_32_H
-
-/*
- * Optimized RAID-5 checksumming functions for MMX and SSE.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * You should have received a copy of the GNU General Public License
- * (for example /usr/src/linux/COPYING); if not, write to the Free
- * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * High-speed RAID5 checksumming functions utilizing MMX instructions.
- * Copyright (C) 1998 Ingo Molnar.
- */
-
-#define LD(x, y)	"       movq   8*("#x")(%1), %%mm"#y"   ;\n"
-#define ST(x, y)	"       movq %%mm"#y",   8*("#x")(%1)   ;\n"
-#define XO1(x, y)	"       pxor   8*("#x")(%2), %%mm"#y"   ;\n"
-#define XO2(x, y)	"       pxor   8*("#x")(%3), %%mm"#y"   ;\n"
-#define XO3(x, y)	"       pxor   8*("#x")(%4), %%mm"#y"   ;\n"
-#define XO4(x, y)	"       pxor   8*("#x")(%5), %%mm"#y"   ;\n"
-
-#include <asm/i387.h>
-
-static void
-xor_pII_mmx_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
-{
-	unsigned long lines = bytes >> 7;
-
-	kernel_fpu_begin();
-
-	asm volatile(
-#undef BLOCK
-#define BLOCK(i)				\
-	LD(i, 0)				\
-		LD(i + 1, 1)			\
-			LD(i + 2, 2)		\
-				LD(i + 3, 3)	\
-	XO1(i, 0)				\
-	ST(i, 0)				\
-		XO1(i+1, 1)			\
-		ST(i+1, 1)			\
-			XO1(i + 2, 2)		\
-			ST(i + 2, 2)		\
-				XO1(i + 3, 3)	\
-				ST(i + 3, 3)
-
-	" .align 32			;\n"
-	" 1:                            ;\n"
-
-	BLOCK(0)
-	BLOCK(4)
-	BLOCK(8)
-	BLOCK(12)
-
-	"       addl $128, %1         ;\n"
-	"       addl $128, %2         ;\n"
-	"       decl %0               ;\n"
-	"       jnz 1b                ;\n"
-	: "+r" (lines),
-	  "+r" (p1), "+r" (p2)
-	:
-	: "memory");
-
-	kernel_fpu_end();
-}
-
-static void
-xor_pII_mmx_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-	      unsigned long *p3)
-{
-	unsigned long lines = bytes >> 7;
-
-	kernel_fpu_begin();
-
-	asm volatile(
-#undef BLOCK
-#define BLOCK(i)				\
-	LD(i, 0)				\
-		LD(i + 1, 1)			\
-			LD(i + 2, 2)		\
-				LD(i + 3, 3)	\
-	XO1(i, 0)				\
-		XO1(i + 1, 1)			\
-			XO1(i + 2, 2)		\
-				XO1(i + 3, 3)	\
-	XO2(i, 0)				\
-	ST(i, 0)				\
-		XO2(i + 1, 1)			\
-		ST(i + 1, 1)			\
-			XO2(i + 2, 2)		\
-			ST(i + 2, 2)		\
-				XO2(i + 3, 3)	\
-				ST(i + 3, 3)
-
-	" .align 32			;\n"
-	" 1:                            ;\n"
-
-	BLOCK(0)
-	BLOCK(4)
-	BLOCK(8)
-	BLOCK(12)
-
-	"       addl $128, %1         ;\n"
-	"       addl $128, %2         ;\n"
-	"       addl $128, %3         ;\n"
-	"       decl %0               ;\n"
-	"       jnz 1b                ;\n"
-	: "+r" (lines),
-	  "+r" (p1), "+r" (p2), "+r" (p3)
-	:
-	: "memory");
-
-	kernel_fpu_end();
-}
-
-static void
-xor_pII_mmx_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-	      unsigned long *p3, unsigned long *p4)
-{
-	unsigned long lines = bytes >> 7;
-
-	kernel_fpu_begin();
-
-	asm volatile(
-#undef BLOCK
-#define BLOCK(i)				\
-	LD(i, 0)				\
-		LD(i + 1, 1)			\
-			LD(i + 2, 2)		\
-				LD(i + 3, 3)	\
-	XO1(i, 0)				\
-		XO1(i + 1, 1)			\
-			XO1(i + 2, 2)		\
-				XO1(i + 3, 3)	\
-	XO2(i, 0)				\
-		XO2(i + 1, 1)			\
-			XO2(i + 2, 2)		\
-				XO2(i + 3, 3)	\
-	XO3(i, 0)				\
-	ST(i, 0)				\
-		XO3(i + 1, 1)			\
-		ST(i + 1, 1)			\
-			XO3(i + 2, 2)		\
-			ST(i + 2, 2)		\
-				XO3(i + 3, 3)	\
-				ST(i + 3, 3)
-
-	" .align 32			;\n"
-	" 1:                            ;\n"
-
-	BLOCK(0)
-	BLOCK(4)
-	BLOCK(8)
-	BLOCK(12)
-
-	"       addl $128, %1         ;\n"
-	"       addl $128, %2         ;\n"
-	"       addl $128, %3         ;\n"
-	"       addl $128, %4         ;\n"
-	"       decl %0               ;\n"
-	"       jnz 1b                ;\n"
-	: "+r" (lines),
-	  "+r" (p1), "+r" (p2), "+r" (p3), "+r" (p4)
-	:
-	: "memory");
-
-	kernel_fpu_end();
-}
-
-
-static void
-xor_pII_mmx_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-	      unsigned long *p3, unsigned long *p4, unsigned long *p5)
-{
-	unsigned long lines = bytes >> 7;
-
-	kernel_fpu_begin();
-
-	/* Make sure GCC forgets anything it knows about p4 or p5,
-	   such that it won't pass to the asm volatile below a
-	   register that is shared with any other variable.  That's
-	   because we modify p4 and p5 there, but we can't mark them
-	   as read/write, otherwise we'd overflow the 10-asm-operands
-	   limit of GCC < 3.1.  */
-	asm("" : "+r" (p4), "+r" (p5));
-
-	asm volatile(
-#undef BLOCK
-#define BLOCK(i)				\
-	LD(i, 0)				\
-		LD(i + 1, 1)			\
-			LD(i + 2, 2)		\
-				LD(i + 3, 3)	\
-	XO1(i, 0)				\
-		XO1(i + 1, 1)			\
-			XO1(i + 2, 2)		\
-				XO1(i + 3, 3)	\
-	XO2(i, 0)				\
-		XO2(i + 1, 1)			\
-			XO2(i + 2, 2)		\
-				XO2(i + 3, 3)	\
-	XO3(i, 0)				\
-		XO3(i + 1, 1)			\
-			XO3(i + 2, 2)		\
-				XO3(i + 3, 3)	\
-	XO4(i, 0)				\
-	ST(i, 0)				\
-		XO4(i + 1, 1)			\
-		ST(i + 1, 1)			\
-			XO4(i + 2, 2)		\
-			ST(i + 2, 2)		\
-				XO4(i + 3, 3)	\
-				ST(i + 3, 3)
-
-	" .align 32			;\n"
-	" 1:                            ;\n"
-
-	BLOCK(0)
-	BLOCK(4)
-	BLOCK(8)
-	BLOCK(12)
-
-	"       addl $128, %1         ;\n"
-	"       addl $128, %2         ;\n"
-	"       addl $128, %3         ;\n"
-	"       addl $128, %4         ;\n"
-	"       addl $128, %5         ;\n"
-	"       decl %0               ;\n"
-	"       jnz 1b                ;\n"
-	: "+r" (lines),
-	  "+r" (p1), "+r" (p2), "+r" (p3)
-	: "r" (p4), "r" (p5)
-	: "memory");
-
-	/* p4 and p5 were modified, and now the variables are dead.
-	   Clobber them just to be sure nobody does something stupid
-	   like assuming they have some legal value.  */
-	asm("" : "=r" (p4), "=r" (p5));
-
-	kernel_fpu_end();
-}
-
-#undef LD
-#undef XO1
-#undef XO2
-#undef XO3
-#undef XO4
-#undef ST
-#undef BLOCK
-
-static void
-xor_p5_mmx_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
-{
-	unsigned long lines = bytes >> 6;
-
-	kernel_fpu_begin();
-
-	asm volatile(
-	" .align 32	             ;\n"
-	" 1:                         ;\n"
-	"       movq   (%1), %%mm0   ;\n"
-	"       movq  8(%1), %%mm1   ;\n"
-	"       pxor   (%2), %%mm0   ;\n"
-	"       movq 16(%1), %%mm2   ;\n"
-	"       movq %%mm0,   (%1)   ;\n"
-	"       pxor  8(%2), %%mm1   ;\n"
-	"       movq 24(%1), %%mm3   ;\n"
-	"       movq %%mm1,  8(%1)   ;\n"
-	"       pxor 16(%2), %%mm2   ;\n"
-	"       movq 32(%1), %%mm4   ;\n"
-	"       movq %%mm2, 16(%1)   ;\n"
-	"       pxor 24(%2), %%mm3   ;\n"
-	"       movq 40(%1), %%mm5   ;\n"
-	"       movq %%mm3, 24(%1)   ;\n"
-	"       pxor 32(%2), %%mm4   ;\n"
-	"       movq 48(%1), %%mm6   ;\n"
-	"       movq %%mm4, 32(%1)   ;\n"
-	"       pxor 40(%2), %%mm5   ;\n"
-	"       movq 56(%1), %%mm7   ;\n"
-	"       movq %%mm5, 40(%1)   ;\n"
-	"       pxor 48(%2), %%mm6   ;\n"
-	"       pxor 56(%2), %%mm7   ;\n"
-	"       movq %%mm6, 48(%1)   ;\n"
-	"       movq %%mm7, 56(%1)   ;\n"
-
-	"       addl $64, %1         ;\n"
-	"       addl $64, %2         ;\n"
-	"       decl %0              ;\n"
-	"       jnz 1b               ;\n"
-	: "+r" (lines),
-	  "+r" (p1), "+r" (p2)
-	:
-	: "memory");
-
-	kernel_fpu_end();
-}
-
-static void
-xor_p5_mmx_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-	     unsigned long *p3)
-{
-	unsigned long lines = bytes >> 6;
-
-	kernel_fpu_begin();
-
-	asm volatile(
-	" .align 32,0x90             ;\n"
-	" 1:                         ;\n"
-	"       movq   (%1), %%mm0   ;\n"
-	"       movq  8(%1), %%mm1   ;\n"
-	"       pxor   (%2), %%mm0   ;\n"
-	"       movq 16(%1), %%mm2   ;\n"
-	"       pxor  8(%2), %%mm1   ;\n"
-	"       pxor   (%3), %%mm0   ;\n"
-	"       pxor 16(%2), %%mm2   ;\n"
-	"       movq %%mm0,   (%1)   ;\n"
-	"       pxor  8(%3), %%mm1   ;\n"
-	"       pxor 16(%3), %%mm2   ;\n"
-	"       movq 24(%1), %%mm3   ;\n"
-	"       movq %%mm1,  8(%1)   ;\n"
-	"       movq 32(%1), %%mm4   ;\n"
-	"       movq 40(%1), %%mm5   ;\n"
-	"       pxor 24(%2), %%mm3   ;\n"
-	"       movq %%mm2, 16(%1)   ;\n"
-	"       pxor 32(%2), %%mm4   ;\n"
-	"       pxor 24(%3), %%mm3   ;\n"
-	"       pxor 40(%2), %%mm5   ;\n"
-	"       movq %%mm3, 24(%1)   ;\n"
-	"       pxor 32(%3), %%mm4   ;\n"
-	"       pxor 40(%3), %%mm5   ;\n"
-	"       movq 48(%1), %%mm6   ;\n"
-	"       movq %%mm4, 32(%1)   ;\n"
-	"       movq 56(%1), %%mm7   ;\n"
-	"       pxor 48(%2), %%mm6   ;\n"
-	"       movq %%mm5, 40(%1)   ;\n"
-	"       pxor 56(%2), %%mm7   ;\n"
-	"       pxor 48(%3), %%mm6   ;\n"
-	"       pxor 56(%3), %%mm7   ;\n"
-	"       movq %%mm6, 48(%1)   ;\n"
-	"       movq %%mm7, 56(%1)   ;\n"
-
-	"       addl $64, %1         ;\n"
-	"       addl $64, %2         ;\n"
-	"       addl $64, %3         ;\n"
-	"       decl %0              ;\n"
-	"       jnz 1b               ;\n"
-	: "+r" (lines),
-	  "+r" (p1), "+r" (p2), "+r" (p3)
-	:
-	: "memory" );
-
-	kernel_fpu_end();
-}
-
-static void
-xor_p5_mmx_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-	     unsigned long *p3, unsigned long *p4)
-{
-	unsigned long lines = bytes >> 6;
-
-	kernel_fpu_begin();
-
-	asm volatile(
-	" .align 32,0x90             ;\n"
-	" 1:                         ;\n"
-	"       movq   (%1), %%mm0   ;\n"
-	"       movq  8(%1), %%mm1   ;\n"
-	"       pxor   (%2), %%mm0   ;\n"
-	"       movq 16(%1), %%mm2   ;\n"
-	"       pxor  8(%2), %%mm1   ;\n"
-	"       pxor   (%3), %%mm0   ;\n"
-	"       pxor 16(%2), %%mm2   ;\n"
-	"       pxor  8(%3), %%mm1   ;\n"
-	"       pxor   (%4), %%mm0   ;\n"
-	"       movq 24(%1), %%mm3   ;\n"
-	"       pxor 16(%3), %%mm2   ;\n"
-	"       pxor  8(%4), %%mm1   ;\n"
-	"       movq %%mm0,   (%1)   ;\n"
-	"       movq 32(%1), %%mm4   ;\n"
-	"       pxor 24(%2), %%mm3   ;\n"
-	"       pxor 16(%4), %%mm2   ;\n"
-	"       movq %%mm1,  8(%1)   ;\n"
-	"       movq 40(%1), %%mm5   ;\n"
-	"       pxor 32(%2), %%mm4   ;\n"
-	"       pxor 24(%3), %%mm3   ;\n"
-	"       movq %%mm2, 16(%1)   ;\n"
-	"       pxor 40(%2), %%mm5   ;\n"
-	"       pxor 32(%3), %%mm4   ;\n"
-	"       pxor 24(%4), %%mm3   ;\n"
-	"       movq %%mm3, 24(%1)   ;\n"
-	"       movq 56(%1), %%mm7   ;\n"
-	"       movq 48(%1), %%mm6   ;\n"
-	"       pxor 40(%3), %%mm5   ;\n"
-	"       pxor 32(%4), %%mm4   ;\n"
-	"       pxor 48(%2), %%mm6   ;\n"
-	"       movq %%mm4, 32(%1)   ;\n"
-	"       pxor 56(%2), %%mm7   ;\n"
-	"       pxor 40(%4), %%mm5   ;\n"
-	"       pxor 48(%3), %%mm6   ;\n"
-	"       pxor 56(%3), %%mm7   ;\n"
-	"       movq %%mm5, 40(%1)   ;\n"
-	"       pxor 48(%4), %%mm6   ;\n"
-	"       pxor 56(%4), %%mm7   ;\n"
-	"       movq %%mm6, 48(%1)   ;\n"
-	"       movq %%mm7, 56(%1)   ;\n"
-
-	"       addl $64, %1         ;\n"
-	"       addl $64, %2         ;\n"
-	"       addl $64, %3         ;\n"
-	"       addl $64, %4         ;\n"
-	"       decl %0              ;\n"
-	"       jnz 1b               ;\n"
-	: "+r" (lines),
-	  "+r" (p1), "+r" (p2), "+r" (p3), "+r" (p4)
-	:
-	: "memory");
-
-	kernel_fpu_end();
-}
-
-static void
-xor_p5_mmx_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-	     unsigned long *p3, unsigned long *p4, unsigned long *p5)
-{
-	unsigned long lines = bytes >> 6;
-
-	kernel_fpu_begin();
-
-	/* Make sure GCC forgets anything it knows about p4 or p5,
-	   such that it won't pass to the asm volatile below a
-	   register that is shared with any other variable.  That's
-	   because we modify p4 and p5 there, but we can't mark them
-	   as read/write, otherwise we'd overflow the 10-asm-operands
-	   limit of GCC < 3.1.  */
-	asm("" : "+r" (p4), "+r" (p5));
-
-	asm volatile(
-	" .align 32,0x90             ;\n"
-	" 1:                         ;\n"
-	"       movq   (%1), %%mm0   ;\n"
-	"       movq  8(%1), %%mm1   ;\n"
-	"       pxor   (%2), %%mm0   ;\n"
-	"       pxor  8(%2), %%mm1   ;\n"
-	"       movq 16(%1), %%mm2   ;\n"
-	"       pxor   (%3), %%mm0   ;\n"
-	"       pxor  8(%3), %%mm1   ;\n"
-	"       pxor 16(%2), %%mm2   ;\n"
-	"       pxor   (%4), %%mm0   ;\n"
-	"       pxor  8(%4), %%mm1   ;\n"
-	"       pxor 16(%3), %%mm2   ;\n"
-	"       movq 24(%1), %%mm3   ;\n"
-	"       pxor   (%5), %%mm0   ;\n"
-	"       pxor  8(%5), %%mm1   ;\n"
-	"       movq %%mm0,   (%1)   ;\n"
-	"       pxor 16(%4), %%mm2   ;\n"
-	"       pxor 24(%2), %%mm3   ;\n"
-	"       movq %%mm1,  8(%1)   ;\n"
-	"       pxor 16(%5), %%mm2   ;\n"
-	"       pxor 24(%3), %%mm3   ;\n"
-	"       movq 32(%1), %%mm4   ;\n"
-	"       movq %%mm2, 16(%1)   ;\n"
-	"       pxor 24(%4), %%mm3   ;\n"
-	"       pxor 32(%2), %%mm4   ;\n"
-	"       movq 40(%1), %%mm5   ;\n"
-	"       pxor 24(%5), %%mm3   ;\n"
-	"       pxor 32(%3), %%mm4   ;\n"
-	"       pxor 40(%2), %%mm5   ;\n"
-	"       movq %%mm3, 24(%1)   ;\n"
-	"       pxor 32(%4), %%mm4   ;\n"
-	"       pxor 40(%3), %%mm5   ;\n"
-	"       movq 48(%1), %%mm6   ;\n"
-	"       movq 56(%1), %%mm7   ;\n"
-	"       pxor 32(%5), %%mm4   ;\n"
-	"       pxor 40(%4), %%mm5   ;\n"
-	"       pxor 48(%2), %%mm6   ;\n"
-	"       pxor 56(%2), %%mm7   ;\n"
-	"       movq %%mm4, 32(%1)   ;\n"
-	"       pxor 48(%3), %%mm6   ;\n"
-	"       pxor 56(%3), %%mm7   ;\n"
-	"       pxor 40(%5), %%mm5   ;\n"
-	"       pxor 48(%4), %%mm6   ;\n"
-	"       pxor 56(%4), %%mm7   ;\n"
-	"       movq %%mm5, 40(%1)   ;\n"
-	"       pxor 48(%5), %%mm6   ;\n"
-	"       pxor 56(%5), %%mm7   ;\n"
-	"       movq %%mm6, 48(%1)   ;\n"
-	"       movq %%mm7, 56(%1)   ;\n"
-
-	"       addl $64, %1         ;\n"
-	"       addl $64, %2         ;\n"
-	"       addl $64, %3         ;\n"
-	"       addl $64, %4         ;\n"
-	"       addl $64, %5         ;\n"
-	"       decl %0              ;\n"
-	"       jnz 1b               ;\n"
-	: "+r" (lines),
-	  "+r" (p1), "+r" (p2), "+r" (p3)
-	: "r" (p4), "r" (p5)
-	: "memory");
-
-	/* p4 and p5 were modified, and now the variables are dead.
-	   Clobber them just to be sure nobody does something stupid
-	   like assuming they have some legal value.  */
-	asm("" : "=r" (p4), "=r" (p5));
-
-	kernel_fpu_end();
-}
-
-static struct xor_block_template xor_block_pII_mmx = {
-	.name = "pII_mmx",
-	.do_2 = xor_pII_mmx_2,
-	.do_3 = xor_pII_mmx_3,
-	.do_4 = xor_pII_mmx_4,
-	.do_5 = xor_pII_mmx_5,
-};
-
-static struct xor_block_template xor_block_p5_mmx = {
-	.name = "p5_mmx",
-	.do_2 = xor_p5_mmx_2,
-	.do_3 = xor_p5_mmx_3,
-	.do_4 = xor_p5_mmx_4,
-	.do_5 = xor_p5_mmx_5,
-};
-
-/*
- * Cache avoiding checksumming functions utilizing KNI instructions
- * Copyright (C) 1999 Zach Brown (with obvious credit due Ingo)
- */
-
-#define XMMS_SAVE				\
-do {						\
-	preempt_disable();			\
-	cr0 = read_cr0();			\
-	clts();					\
-	asm volatile(				\
-		"movups %%xmm0,(%0)	;\n\t"	\
-		"movups %%xmm1,0x10(%0)	;\n\t"	\
-		"movups %%xmm2,0x20(%0)	;\n\t"	\
-		"movups %%xmm3,0x30(%0)	;\n\t"	\
-		:				\
-		: "r" (xmm_save) 		\
-		: "memory");			\
-} while (0)
-
-#define XMMS_RESTORE				\
-do {						\
-	asm volatile(				\
-		"sfence			;\n\t"	\
-		"movups (%0),%%xmm0	;\n\t"	\
-		"movups 0x10(%0),%%xmm1	;\n\t"	\
-		"movups 0x20(%0),%%xmm2	;\n\t"	\
-		"movups 0x30(%0),%%xmm3	;\n\t"	\
-		:				\
-		: "r" (xmm_save)		\
-		: "memory");			\
-	write_cr0(cr0);				\
-	preempt_enable();			\
-} while (0)
-
-#define ALIGN16 __attribute__((aligned(16)))
-
-#define OFFS(x)		"16*("#x")"
-#define PF_OFFS(x)	"256+16*("#x")"
-#define	PF0(x)		"	prefetchnta "PF_OFFS(x)"(%1)		;\n"
-#define LD(x, y)	"       movaps   "OFFS(x)"(%1), %%xmm"#y"	;\n"
-#define ST(x, y)	"       movaps %%xmm"#y",   "OFFS(x)"(%1)	;\n"
-#define PF1(x)		"	prefetchnta "PF_OFFS(x)"(%2)		;\n"
-#define PF2(x)		"	prefetchnta "PF_OFFS(x)"(%3)		;\n"
-#define PF3(x)		"	prefetchnta "PF_OFFS(x)"(%4)		;\n"
-#define PF4(x)		"	prefetchnta "PF_OFFS(x)"(%5)		;\n"
-#define PF5(x)		"	prefetchnta "PF_OFFS(x)"(%6)		;\n"
-#define XO1(x, y)	"       xorps   "OFFS(x)"(%2), %%xmm"#y"	;\n"
-#define XO2(x, y)	"       xorps   "OFFS(x)"(%3), %%xmm"#y"	;\n"
-#define XO3(x, y)	"       xorps   "OFFS(x)"(%4), %%xmm"#y"	;\n"
-#define XO4(x, y)	"       xorps   "OFFS(x)"(%5), %%xmm"#y"	;\n"
-#define XO5(x, y)	"       xorps   "OFFS(x)"(%6), %%xmm"#y"	;\n"
-
-
-static void
-xor_sse_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
-{
-	unsigned long lines = bytes >> 8;
-	char xmm_save[16*4] ALIGN16;
-	int cr0;
-
-	XMMS_SAVE;
-
-	asm volatile(
-#undef BLOCK
-#define BLOCK(i)					\
-		LD(i, 0)				\
-			LD(i + 1, 1)			\
-		PF1(i)					\
-				PF1(i + 2)		\
-				LD(i + 2, 2)		\
-					LD(i + 3, 3)	\
-		PF0(i + 4)				\
-				PF0(i + 6)		\
-		XO1(i, 0)				\
-			XO1(i + 1, 1)			\
-				XO1(i + 2, 2)		\
-					XO1(i + 3, 3)	\
-		ST(i, 0)				\
-			ST(i + 1, 1)			\
-				ST(i + 2, 2)		\
-					ST(i + 3, 3)	\
-
-
-		PF0(0)
-				PF0(2)
-
-	" .align 32			;\n"
-	" 1:                            ;\n"
-
-		BLOCK(0)
-		BLOCK(4)
-		BLOCK(8)
-		BLOCK(12)
-
-	"       addl $256, %1           ;\n"
-	"       addl $256, %2           ;\n"
-	"       decl %0                 ;\n"
-	"       jnz 1b                  ;\n"
-	: "+r" (lines),
-	  "+r" (p1), "+r" (p2)
-	:
-	: "memory");
-
-	XMMS_RESTORE;
-}
-
-static void
-xor_sse_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-	  unsigned long *p3)
-{
-	unsigned long lines = bytes >> 8;
-	char xmm_save[16*4] ALIGN16;
-	int cr0;
-
-	XMMS_SAVE;
-
-	asm volatile(
-#undef BLOCK
-#define BLOCK(i) \
-		PF1(i)					\
-				PF1(i + 2)		\
-		LD(i,0)					\
-			LD(i + 1, 1)			\
-				LD(i + 2, 2)		\
-					LD(i + 3, 3)	\
-		PF2(i)					\
-				PF2(i + 2)		\
-		PF0(i + 4)				\
-				PF0(i + 6)		\
-		XO1(i,0)				\
-			XO1(i + 1, 1)			\
-				XO1(i + 2, 2)		\
-					XO1(i + 3, 3)	\
-		XO2(i,0)				\
-			XO2(i + 1, 1)			\
-				XO2(i + 2, 2)		\
-					XO2(i + 3, 3)	\
-		ST(i,0)					\
-			ST(i + 1, 1)			\
-				ST(i + 2, 2)		\
-					ST(i + 3, 3)	\
-
-
-		PF0(0)
-				PF0(2)
-
-	" .align 32			;\n"
-	" 1:                            ;\n"
-
-		BLOCK(0)
-		BLOCK(4)
-		BLOCK(8)
-		BLOCK(12)
-
-	"       addl $256, %1           ;\n"
-	"       addl $256, %2           ;\n"
-	"       addl $256, %3           ;\n"
-	"       decl %0                 ;\n"
-	"       jnz 1b                  ;\n"
-	: "+r" (lines),
-	  "+r" (p1), "+r"(p2), "+r"(p3)
-	:
-	: "memory" );
-
-	XMMS_RESTORE;
-}
-
-static void
-xor_sse_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-	  unsigned long *p3, unsigned long *p4)
-{
-	unsigned long lines = bytes >> 8;
-	char xmm_save[16*4] ALIGN16;
-	int cr0;
-
-	XMMS_SAVE;
-
-	asm volatile(
-#undef BLOCK
-#define BLOCK(i) \
-		PF1(i)					\
-				PF1(i + 2)		\
-		LD(i,0)					\
-			LD(i + 1, 1)			\
-				LD(i + 2, 2)		\
-					LD(i + 3, 3)	\
-		PF2(i)					\
-				PF2(i + 2)		\
-		XO1(i,0)				\
-			XO1(i + 1, 1)			\
-				XO1(i + 2, 2)		\
-					XO1(i + 3, 3)	\
-		PF3(i)					\
-				PF3(i + 2)		\
-		PF0(i + 4)				\
-				PF0(i + 6)		\
-		XO2(i,0)				\
-			XO2(i + 1, 1)			\
-				XO2(i + 2, 2)		\
-					XO2(i + 3, 3)	\
-		XO3(i,0)				\
-			XO3(i + 1, 1)			\
-				XO3(i + 2, 2)		\
-					XO3(i + 3, 3)	\
-		ST(i,0)					\
-			ST(i + 1, 1)			\
-				ST(i + 2, 2)		\
-					ST(i + 3, 3)	\
-
-
-		PF0(0)
-				PF0(2)
-
-	" .align 32			;\n"
-	" 1:                            ;\n"
-
-		BLOCK(0)
-		BLOCK(4)
-		BLOCK(8)
-		BLOCK(12)
-
-	"       addl $256, %1           ;\n"
-	"       addl $256, %2           ;\n"
-	"       addl $256, %3           ;\n"
-	"       addl $256, %4           ;\n"
-	"       decl %0                 ;\n"
-	"       jnz 1b                  ;\n"
-	: "+r" (lines),
-	  "+r" (p1), "+r" (p2), "+r" (p3), "+r" (p4)
-	:
-	: "memory" );
-
-	XMMS_RESTORE;
-}
-
-static void
-xor_sse_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-	  unsigned long *p3, unsigned long *p4, unsigned long *p5)
-{
-	unsigned long lines = bytes >> 8;
-	char xmm_save[16*4] ALIGN16;
-	int cr0;
-
-	XMMS_SAVE;
-
-	/* Make sure GCC forgets anything it knows about p4 or p5,
-	   such that it won't pass to the asm volatile below a
-	   register that is shared with any other variable.  That's
-	   because we modify p4 and p5 there, but we can't mark them
-	   as read/write, otherwise we'd overflow the 10-asm-operands
-	   limit of GCC < 3.1.  */
-	asm("" : "+r" (p4), "+r" (p5));
-
-	asm volatile(
-#undef BLOCK
-#define BLOCK(i) \
-		PF1(i)					\
-				PF1(i + 2)		\
-		LD(i,0)					\
-			LD(i + 1, 1)			\
-				LD(i + 2, 2)		\
-					LD(i + 3, 3)	\
-		PF2(i)					\
-				PF2(i + 2)		\
-		XO1(i,0)				\
-			XO1(i + 1, 1)			\
-				XO1(i + 2, 2)		\
-					XO1(i + 3, 3)	\
-		PF3(i)					\
-				PF3(i + 2)		\
-		XO2(i,0)				\
-			XO2(i + 1, 1)			\
-				XO2(i + 2, 2)		\
-					XO2(i + 3, 3)	\
-		PF4(i)					\
-				PF4(i + 2)		\
-		PF0(i + 4)				\
-				PF0(i + 6)		\
-		XO3(i,0)				\
-			XO3(i + 1, 1)			\
-				XO3(i + 2, 2)		\
-					XO3(i + 3, 3)	\
-		XO4(i,0)				\
-			XO4(i + 1, 1)			\
-				XO4(i + 2, 2)		\
-					XO4(i + 3, 3)	\
-		ST(i,0)					\
-			ST(i + 1, 1)			\
-				ST(i + 2, 2)		\
-					ST(i + 3, 3)	\
-
-
-		PF0(0)
-				PF0(2)
-
-	" .align 32			;\n"
-	" 1:                            ;\n"
-
-		BLOCK(0)
-		BLOCK(4)
-		BLOCK(8)
-		BLOCK(12)
-
-	"       addl $256, %1           ;\n"
-	"       addl $256, %2           ;\n"
-	"       addl $256, %3           ;\n"
-	"       addl $256, %4           ;\n"
-	"       addl $256, %5           ;\n"
-	"       decl %0                 ;\n"
-	"       jnz 1b                  ;\n"
-	: "+r" (lines),
-	  "+r" (p1), "+r" (p2), "+r" (p3)
-	: "r" (p4), "r" (p5)
-	: "memory");
-
-	/* p4 and p5 were modified, and now the variables are dead.
-	   Clobber them just to be sure nobody does something stupid
-	   like assuming they have some legal value.  */
-	asm("" : "=r" (p4), "=r" (p5));
-
-	XMMS_RESTORE;
-}
-
-static struct xor_block_template xor_block_pIII_sse = {
-	.name = "pIII_sse",
-	.do_2 = xor_sse_2,
-	.do_3 = xor_sse_3,
-	.do_4 = xor_sse_4,
-	.do_5 = xor_sse_5,
-};
-
-/* Also try the generic routines.  */
-#include <asm-generic/xor.h>
-
-#undef XOR_TRY_TEMPLATES
-#define XOR_TRY_TEMPLATES				\
-do {							\
-	xor_speed(&xor_block_8regs);			\
-	xor_speed(&xor_block_8regs_p);			\
-	xor_speed(&xor_block_32regs);			\
-	xor_speed(&xor_block_32regs_p);			\
-	if (cpu_has_xmm)				\
-		xor_speed(&xor_block_pIII_sse);		\
-	if (cpu_has_mmx) {				\
-		xor_speed(&xor_block_pII_mmx);		\
-		xor_speed(&xor_block_p5_mmx);		\
-	}						\
-} while (0)
-
-/* We force the use of the SSE xor block because it can write around L2.
-   We may also be able to load into the L1 only depending on how the cpu
-   deals with a load to a line that is being prefetched.  */
-#define XOR_SELECT_TEMPLATE(FASTEST)			\
-	(cpu_has_xmm ? &xor_block_pIII_sse : FASTEST)
-
-#endif /* ASM_X86__XOR_32_H */
diff --git a/include/asm-x86/xor_64.h b/include/asm-x86/xor_64.h
deleted file mode 100644
index 2d3a18de295b..000000000000
--- a/include/asm-x86/xor_64.h
+++ /dev/null
@@ -1,361 +0,0 @@
-#ifndef ASM_X86__XOR_64_H
-#define ASM_X86__XOR_64_H
-
-/*
- * Optimized RAID-5 checksumming functions for MMX and SSE.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * You should have received a copy of the GNU General Public License
- * (for example /usr/src/linux/COPYING); if not, write to the Free
- * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-
-/*
- * Cache avoiding checksumming functions utilizing KNI instructions
- * Copyright (C) 1999 Zach Brown (with obvious credit due Ingo)
- */
-
-/*
- * Based on
- * High-speed RAID5 checksumming functions utilizing SSE instructions.
- * Copyright (C) 1998 Ingo Molnar.
- */
-
-/*
- * x86-64 changes / gcc fixes from Andi Kleen.
- * Copyright 2002 Andi Kleen, SuSE Labs.
- *
- * This hasn't been optimized for the hammer yet, but there are likely
- * no advantages to be gotten from x86-64 here anyways.
- */
-
-typedef struct {
-	unsigned long a, b;
-} __attribute__((aligned(16))) xmm_store_t;
-
-/* Doesn't use gcc to save the XMM registers, because there is no easy way to
-   tell it to do a clts before the register saving. */
-#define XMMS_SAVE				\
-do {						\
-	preempt_disable();			\
-	asm volatile(				\
-		"movq %%cr0,%0		;\n\t"	\
-		"clts			;\n\t"	\
-		"movups %%xmm0,(%1)	;\n\t"	\
-		"movups %%xmm1,0x10(%1)	;\n\t"	\
-		"movups %%xmm2,0x20(%1)	;\n\t"	\
-		"movups %%xmm3,0x30(%1)	;\n\t"	\
-		: "=&r" (cr0)			\
-		: "r" (xmm_save) 		\
-		: "memory");			\
-} while (0)
-
-#define XMMS_RESTORE				\
-do {						\
-	asm volatile(				\
-		"sfence			;\n\t"	\
-		"movups (%1),%%xmm0	;\n\t"	\
-		"movups 0x10(%1),%%xmm1	;\n\t"	\
-		"movups 0x20(%1),%%xmm2	;\n\t"	\
-		"movups 0x30(%1),%%xmm3	;\n\t"	\
-		"movq 	%0,%%cr0	;\n\t"	\
-		:				\
-		: "r" (cr0), "r" (xmm_save)	\
-		: "memory");			\
-	preempt_enable();			\
-} while (0)
-
-#define OFFS(x)		"16*("#x")"
-#define PF_OFFS(x)	"256+16*("#x")"
-#define	PF0(x)		"	prefetchnta "PF_OFFS(x)"(%[p1])		;\n"
-#define LD(x, y)	"       movaps   "OFFS(x)"(%[p1]), %%xmm"#y"	;\n"
-#define ST(x, y)	"       movaps %%xmm"#y",   "OFFS(x)"(%[p1])	;\n"
-#define PF1(x)		"	prefetchnta "PF_OFFS(x)"(%[p2])		;\n"
-#define PF2(x)		"	prefetchnta "PF_OFFS(x)"(%[p3])		;\n"
-#define PF3(x)		"	prefetchnta "PF_OFFS(x)"(%[p4])		;\n"
-#define PF4(x)		"	prefetchnta "PF_OFFS(x)"(%[p5])		;\n"
-#define PF5(x)		"	prefetchnta "PF_OFFS(x)"(%[p6])		;\n"
-#define XO1(x, y)	"       xorps   "OFFS(x)"(%[p2]), %%xmm"#y"	;\n"
-#define XO2(x, y)	"       xorps   "OFFS(x)"(%[p3]), %%xmm"#y"	;\n"
-#define XO3(x, y)	"       xorps   "OFFS(x)"(%[p4]), %%xmm"#y"	;\n"
-#define XO4(x, y)	"       xorps   "OFFS(x)"(%[p5]), %%xmm"#y"	;\n"
-#define XO5(x, y)	"       xorps   "OFFS(x)"(%[p6]), %%xmm"#y"	;\n"
-
-
-static void
-xor_sse_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
-{
-	unsigned int lines = bytes >> 8;
-	unsigned long cr0;
-	xmm_store_t xmm_save[4];
-
-	XMMS_SAVE;
-
-	asm volatile(
-#undef BLOCK
-#define BLOCK(i) \
-		LD(i, 0)				\
-			LD(i + 1, 1)			\
-		PF1(i)					\
-				PF1(i + 2)		\
-				LD(i + 2, 2)		\
-					LD(i + 3, 3)	\
-		PF0(i + 4)				\
-				PF0(i + 6)		\
-		XO1(i, 0)				\
-			XO1(i + 1, 1)			\
-				XO1(i + 2, 2)		\
-					XO1(i + 3, 3)	\
-		ST(i, 0)				\
-			ST(i + 1, 1)			\
-				ST(i + 2, 2)		\
-					ST(i + 3, 3)	\
-
-
-		PF0(0)
-				PF0(2)
-
-	" .align 32			;\n"
-	" 1:                            ;\n"
-
-		BLOCK(0)
-		BLOCK(4)
-		BLOCK(8)
-		BLOCK(12)
-
-	"       addq %[inc], %[p1]           ;\n"
-	"       addq %[inc], %[p2]           ;\n"
-		"		decl %[cnt] ; jnz 1b"
-	: [p1] "+r" (p1), [p2] "+r" (p2), [cnt] "+r" (lines)
-	: [inc] "r" (256UL)
-	: "memory");
-
-	XMMS_RESTORE;
-}
-
-static void
-xor_sse_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-	  unsigned long *p3)
-{
-	unsigned int lines = bytes >> 8;
-	xmm_store_t xmm_save[4];
-	unsigned long cr0;
-
-	XMMS_SAVE;
-
-	asm volatile(
-#undef BLOCK
-#define BLOCK(i) \
-		PF1(i)					\
-				PF1(i + 2)		\
-		LD(i, 0)					\
-			LD(i + 1, 1)			\
-				LD(i + 2, 2)		\
-					LD(i + 3, 3)	\
-		PF2(i)					\
-				PF2(i + 2)		\
-		PF0(i + 4)				\
-				PF0(i + 6)		\
-		XO1(i, 0)				\
-			XO1(i + 1, 1)			\
-				XO1(i + 2, 2)		\
-					XO1(i + 3, 3)	\
-		XO2(i, 0)				\
-			XO2(i + 1, 1)			\
-				XO2(i + 2, 2)		\
-					XO2(i + 3, 3)	\
-		ST(i, 0)				\
-			ST(i + 1, 1)			\
-				ST(i + 2, 2)		\
-					ST(i + 3, 3)	\
-
-
-		PF0(0)
-				PF0(2)
-
-	" .align 32			;\n"
-	" 1:                            ;\n"
-
-		BLOCK(0)
-		BLOCK(4)
-		BLOCK(8)
-		BLOCK(12)
-
-	"       addq %[inc], %[p1]           ;\n"
-	"       addq %[inc], %[p2]          ;\n"
-	"       addq %[inc], %[p3]           ;\n"
-		"		decl %[cnt] ; jnz 1b"
-	: [cnt] "+r" (lines),
-	  [p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3)
-	: [inc] "r" (256UL)
-	: "memory");
-	XMMS_RESTORE;
-}
-
-static void
-xor_sse_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-	  unsigned long *p3, unsigned long *p4)
-{
-	unsigned int lines = bytes >> 8;
-	xmm_store_t xmm_save[4];
-	unsigned long cr0;
-
-	XMMS_SAVE;
-
-	asm volatile(
-#undef BLOCK
-#define BLOCK(i) \
-		PF1(i)					\
-				PF1(i + 2)		\
-		LD(i, 0)				\
-			LD(i + 1, 1)			\
-				LD(i + 2, 2)		\
-					LD(i + 3, 3)	\
-		PF2(i)					\
-				PF2(i + 2)		\
-		XO1(i, 0)				\
-			XO1(i + 1, 1)			\
-				XO1(i + 2, 2)		\
-					XO1(i + 3, 3)	\
-		PF3(i)					\
-				PF3(i + 2)		\
-		PF0(i + 4)				\
-				PF0(i + 6)		\
-		XO2(i, 0)				\
-			XO2(i + 1, 1)			\
-				XO2(i + 2, 2)		\
-					XO2(i + 3, 3)	\
-		XO3(i, 0)				\
-			XO3(i + 1, 1)			\
-				XO3(i + 2, 2)		\
-					XO3(i + 3, 3)	\
-		ST(i, 0)				\
-			ST(i + 1, 1)			\
-				ST(i + 2, 2)		\
-					ST(i + 3, 3)	\
-
-
-		PF0(0)
-				PF0(2)
-
-	" .align 32			;\n"
-	" 1:                            ;\n"
-
-		BLOCK(0)
-		BLOCK(4)
-		BLOCK(8)
-		BLOCK(12)
-
-	"       addq %[inc], %[p1]           ;\n"
-	"       addq %[inc], %[p2]           ;\n"
-	"       addq %[inc], %[p3]           ;\n"
-	"       addq %[inc], %[p4]           ;\n"
-	"	decl %[cnt] ; jnz 1b"
-	: [cnt] "+c" (lines),
-	  [p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3), [p4] "+r" (p4)
-	: [inc] "r" (256UL)
-	: "memory" );
-
-	XMMS_RESTORE;
-}
-
-static void
-xor_sse_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-	  unsigned long *p3, unsigned long *p4, unsigned long *p5)
-{
-	unsigned int lines = bytes >> 8;
-	xmm_store_t xmm_save[4];
-	unsigned long cr0;
-
-	XMMS_SAVE;
-
-	asm volatile(
-#undef BLOCK
-#define BLOCK(i) \
-		PF1(i)					\
-				PF1(i + 2)		\
-		LD(i, 0)				\
-			LD(i + 1, 1)			\
-				LD(i + 2, 2)		\
-					LD(i + 3, 3)	\
-		PF2(i)					\
-				PF2(i + 2)		\
-		XO1(i, 0)				\
-			XO1(i + 1, 1)			\
-				XO1(i + 2, 2)		\
-					XO1(i + 3, 3)	\
-		PF3(i)					\
-				PF3(i + 2)		\
-		XO2(i, 0)				\
-			XO2(i + 1, 1)			\
-				XO2(i + 2, 2)		\
-					XO2(i + 3, 3)	\
-		PF4(i)					\
-				PF4(i + 2)		\
-		PF0(i + 4)				\
-				PF0(i + 6)		\
-		XO3(i, 0)				\
-			XO3(i + 1, 1)			\
-				XO3(i + 2, 2)		\
-					XO3(i + 3, 3)	\
-		XO4(i, 0)				\
-			XO4(i + 1, 1)			\
-				XO4(i + 2, 2)		\
-					XO4(i + 3, 3)	\
-		ST(i, 0)				\
-			ST(i + 1, 1)			\
-				ST(i + 2, 2)		\
-					ST(i + 3, 3)	\
-
-
-		PF0(0)
-				PF0(2)
-
-	" .align 32			;\n"
-	" 1:                            ;\n"
-
-		BLOCK(0)
-		BLOCK(4)
-		BLOCK(8)
-		BLOCK(12)
-
-	"       addq %[inc], %[p1]           ;\n"
-	"       addq %[inc], %[p2]           ;\n"
-	"       addq %[inc], %[p3]           ;\n"
-	"       addq %[inc], %[p4]           ;\n"
-	"       addq %[inc], %[p5]           ;\n"
-	"	decl %[cnt] ; jnz 1b"
-	: [cnt] "+c" (lines),
-	  [p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3), [p4] "+r" (p4),
-	  [p5] "+r" (p5)
-	: [inc] "r" (256UL)
-	: "memory");
-
-	XMMS_RESTORE;
-}
-
-static struct xor_block_template xor_block_sse = {
-	.name = "generic_sse",
-	.do_2 = xor_sse_2,
-	.do_3 = xor_sse_3,
-	.do_4 = xor_sse_4,
-	.do_5 = xor_sse_5,
-};
-
-#undef XOR_TRY_TEMPLATES
-#define XOR_TRY_TEMPLATES			\
-do {						\
-	xor_speed(&xor_block_sse);		\
-} while (0)
-
-/* We force the use of the SSE xor block because it can write around L2.
-   We may also be able to load into the L1 only depending on how the cpu
-   deals with a load to a line that is being prefetched.  */
-#define XOR_SELECT_TEMPLATE(FASTEST) (&xor_block_sse)
-
-#endif /* ASM_X86__XOR_64_H */
diff --git a/include/asm-x86/xsave.h b/include/asm-x86/xsave.h
deleted file mode 100644
index 08e9a1ac07a9..000000000000
--- a/include/asm-x86/xsave.h
+++ /dev/null
@@ -1,118 +0,0 @@
-#ifndef __ASM_X86_XSAVE_H
-#define __ASM_X86_XSAVE_H
-
-#include <linux/types.h>
-#include <asm/processor.h>
-#include <asm/i387.h>
-
-#define XSTATE_FP	0x1
-#define XSTATE_SSE	0x2
-
-#define XSTATE_FPSSE	(XSTATE_FP | XSTATE_SSE)
-
-#define FXSAVE_SIZE	512
-
-/*
- * These are the features that the OS can handle currently.
- */
-#define XCNTXT_MASK	(XSTATE_FP | XSTATE_SSE)
-
-#ifdef CONFIG_X86_64
-#define REX_PREFIX	"0x48, "
-#else
-#define REX_PREFIX
-#endif
-
-extern unsigned int xstate_size;
-extern u64 pcntxt_mask;
-extern struct xsave_struct *init_xstate_buf;
-
-extern void xsave_cntxt_init(void);
-extern void xsave_init(void);
-extern int init_fpu(struct task_struct *child);
-extern int check_for_xstate(struct i387_fxsave_struct __user *buf,
-			    void __user *fpstate,
-			    struct _fpx_sw_bytes *sw);
-
-static inline int xrstor_checking(struct xsave_struct *fx)
-{
-	int err;
-
-	asm volatile("1: .byte " REX_PREFIX "0x0f,0xae,0x2f\n\t"
-		     "2:\n"
-		     ".section .fixup,\"ax\"\n"
-		     "3:  movl $-1,%[err]\n"
-		     "    jmp  2b\n"
-		     ".previous\n"
-		     _ASM_EXTABLE(1b, 3b)
-		     : [err] "=r" (err)
-		     : "D" (fx), "m" (*fx), "a" (-1), "d" (-1), "0" (0)
-		     : "memory");
-
-	return err;
-}
-
-static inline int xsave_user(struct xsave_struct __user *buf)
-{
-	int err;
-	__asm__ __volatile__("1: .byte " REX_PREFIX "0x0f,0xae,0x27\n"
-			     "2:\n"
-			     ".section .fixup,\"ax\"\n"
-			     "3:  movl $-1,%[err]\n"
-			     "    jmp  2b\n"
-			     ".previous\n"
-			     ".section __ex_table,\"a\"\n"
-			     _ASM_ALIGN "\n"
-			     _ASM_PTR "1b,3b\n"
-			     ".previous"
-			     : [err] "=r" (err)
-			     : "D" (buf), "a" (-1), "d" (-1), "0" (0)
-			     : "memory");
-	if (unlikely(err) && __clear_user(buf, xstate_size))
-		err = -EFAULT;
-	/* No need to clear here because the caller clears USED_MATH */
-	return err;
-}
-
-static inline int xrestore_user(struct xsave_struct __user *buf, u64 mask)
-{
-	int err;
-	struct xsave_struct *xstate = ((__force struct xsave_struct *)buf);
-	u32 lmask = mask;
-	u32 hmask = mask >> 32;
-
-	__asm__ __volatile__("1: .byte " REX_PREFIX "0x0f,0xae,0x2f\n"
-			     "2:\n"
-			     ".section .fixup,\"ax\"\n"
-			     "3:  movl $-1,%[err]\n"
-			     "    jmp  2b\n"
-			     ".previous\n"
-			     ".section __ex_table,\"a\"\n"
-			     _ASM_ALIGN "\n"
-			     _ASM_PTR "1b,3b\n"
-			     ".previous"
-			     : [err] "=r" (err)
-			     : "D" (xstate), "a" (lmask), "d" (hmask), "0" (0)
-			     : "memory");	/* memory required? */
-	return err;
-}
-
-static inline void xrstor_state(struct xsave_struct *fx, u64 mask)
-{
-	u32 lmask = mask;
-	u32 hmask = mask >> 32;
-
-	asm volatile(".byte " REX_PREFIX "0x0f,0xae,0x2f\n\t"
-		     : : "D" (fx), "m" (*fx), "a" (lmask), "d" (hmask)
-		     :   "memory");
-}
-
-static inline void xsave(struct task_struct *tsk)
-{
-	/* This, however, we can work around by forcing the compiler to select
-	   an addressing mode that doesn't require extended registers. */
-	__asm__ __volatile__(".byte " REX_PREFIX "0x0f,0xae,0x27"
-			     : : "D" (&(tsk->thread.xstate->xsave)),
-				 "a" (-1), "d"(-1) : "memory");
-}
-#endif
diff --git a/include/asm-xtensa/elf.h b/include/asm-xtensa/elf.h
index ca6e5101a2cb..c3f53e755ca5 100644
--- a/include/asm-xtensa/elf.h
+++ b/include/asm-xtensa/elf.h
@@ -189,7 +189,7 @@ typedef struct {
 #endif
 } elf_xtregs_t;
 
-#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT)
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX_32BIT)
 
 struct task_struct;
 
diff --git a/include/asm-xtensa/io.h b/include/asm-xtensa/io.h
index 47c3616ea9ac..07b7299dab20 100644
--- a/include/asm-xtensa/io.h
+++ b/include/asm-xtensa/io.h
@@ -18,10 +18,12 @@
 
 #include <linux/types.h>
 
-#define XCHAL_KIO_CACHED_VADDR	0xf0000000
-#define XCHAL_KIO_BYPASS_VADDR	0xf8000000
+#define XCHAL_KIO_CACHED_VADDR	0xe0000000
+#define XCHAL_KIO_BYPASS_VADDR	0xf0000000
 #define XCHAL_KIO_PADDR		0xf0000000
-#define XCHAL_KIO_SIZE		0x08000000
+#define XCHAL_KIO_SIZE		0x10000000
+
+#define IOADDR(x)		(XCHAL_KIO_BYPASS_VADDR + (x))
 
 /*
  * swap functions to change byte order from little-endian to big-endian and
diff --git a/include/asm-xtensa/rwsem.h b/include/asm-xtensa/rwsem.h
index 0aad3a587551..e39edf5c86f2 100644
--- a/include/asm-xtensa/rwsem.h
+++ b/include/asm-xtensa/rwsem.h
@@ -13,6 +13,10 @@
 #ifndef _XTENSA_RWSEM_H
 #define _XTENSA_RWSEM_H
 
+#ifndef _LINUX_RWSEM_H
+#error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead."
+#endif
+
 #include <linux/list.h>
 #include <linux/spinlock.h>
 #include <asm/atomic.h>
diff --git a/include/asm-xtensa/thread_info.h b/include/asm-xtensa/thread_info.h
index 7e4131dd546c..0f4fe1faf9ba 100644
--- a/include/asm-xtensa/thread_info.h
+++ b/include/asm-xtensa/thread_info.h
@@ -134,6 +134,7 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_MEMDIE		5
 #define TIF_RESTORE_SIGMASK	6	/* restore signal mask in do_signal() */
 #define TIF_POLLING_NRFLAG	16	/* true if poll_idle() is polling TIF_NEED_RESCHED */
+#define TIF_FREEZE		17	/* is freezing for suspend */
 
 #define _TIF_SYSCALL_TRACE	(1<<TIF_SYSCALL_TRACE)
 #define _TIF_SIGPENDING		(1<<TIF_SIGPENDING)
@@ -142,6 +143,7 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_IRET		(1<<TIF_IRET)
 #define _TIF_POLLING_NRFLAG	(1<<TIF_POLLING_NRFLAG)
 #define _TIF_RESTORE_SIGMASK	(1<<TIF_RESTORE_SIGMASK)
+#define _TIF_FREEZE		(1<<TIF_FREEZE)
 
 #define _TIF_WORK_MASK		0x0000FFFE	/* work to do on interrupt/exception return */
 #define _TIF_ALLWORK_MASK	0x0000FFFF	/* work to do on any return to u-space */
diff --git a/include/asm-xtensa/variant-dc232b/core.h b/include/asm-xtensa/variant-dc232b/core.h
new file mode 100644
index 000000000000..525bd3d90154
--- /dev/null
+++ b/include/asm-xtensa/variant-dc232b/core.h
@@ -0,0 +1,424 @@
+/*
+ * Xtensa processor core configuration information.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1999-2007 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_CORE_CONFIGURATION_H
+#define _XTENSA_CORE_CONFIGURATION_H
+
+
+/****************************************************************************
+	    Parameters Useful for Any Code, USER or PRIVILEGED
+ ****************************************************************************/
+
+/*
+ *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
+ *  configured, and a value of 0 otherwise.  These macros are always defined.
+ */
+
+
+/*----------------------------------------------------------------------
+				ISA
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
+#define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
+#define XCHAL_NUM_AREGS			32	/* num of physical addr regs */
+#define XCHAL_NUM_AREGS_LOG2		5	/* log2(XCHAL_NUM_AREGS) */
+#define XCHAL_MAX_INSTRUCTION_SIZE	3	/* max instr bytes (3..8) */
+#define XCHAL_HAVE_DEBUG		1	/* debug option */
+#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
+#define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
+#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
+#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
+#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
+#define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
+#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
+#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
+#define XCHAL_HAVE_MUL32_HIGH		0	/* MULUH/MULSH instructions */
+#define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
+#define XCHAL_HAVE_L32R			1	/* L32R instruction */
+#define XCHAL_HAVE_ABSOLUTE_LITERALS	1	/* non-PC-rel (extended) L32R */
+#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
+#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
+#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
+#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
+#define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
+#define XCHAL_HAVE_ABS			1	/* ABS instruction */
+/*#define XCHAL_HAVE_POPC		0*/	/* POPC instruction */
+/*#define XCHAL_HAVE_CRC		0*/	/* CRC instruction */
+#define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
+#define XCHAL_HAVE_S32C1I		1	/* S32C1I instruction */
+#define XCHAL_HAVE_SPECULATION		0	/* speculation */
+#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
+#define XCHAL_NUM_CONTEXTS		1	/* */
+#define XCHAL_NUM_MISC_REGS		2	/* num of scratch regs (0..4) */
+#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
+#define XCHAL_HAVE_PRID			1	/* processor ID register */
+#define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
+#define XCHAL_HAVE_BOOLEANS		0	/* boolean registers */
+#define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
+#define XCHAL_CP_MAXCFG			8	/* max allowed cp id plus one */
+#define XCHAL_HAVE_MAC16		1	/* MAC16 package */
+#define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
+#define XCHAL_HAVE_FP			0	/* floating point pkg */
+#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
+#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
+#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
+
+
+/*----------------------------------------------------------------------
+				MISC
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_WRITEBUFFER_ENTRIES	8	/* size of write buffer */
+#define XCHAL_INST_FETCH_WIDTH		4	/* instr-fetch width in bytes */
+#define XCHAL_DATA_WIDTH		4	/* data width in bytes */
+/*  In T1050, applies to selected core load and store instructions (see ISA): */
+#define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
+#define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
+
+#define XCHAL_SW_VERSION		701001	/* sw version of this header */
+
+#define XCHAL_CORE_ID			"dc232b"	/* alphanum core name
+						   (CoreID) set in the Xtensa
+						   Processor Generator */
+
+#define XCHAL_CORE_DESCRIPTION		"Diamond 232L Standard Core Rev.B (LE)"
+#define XCHAL_BUILD_UNIQUE_ID		0x0000BEEF	/* 22-bit sw build ID */
+
+/*
+ *  These definitions describe the hardware targeted by this software.
+ */
+#define XCHAL_HW_CONFIGID0		0xC56307FE	/* ConfigID hi 32 bits*/
+#define XCHAL_HW_CONFIGID1		0x0D40BEEF	/* ConfigID lo 32 bits*/
+#define XCHAL_HW_VERSION_NAME		"LX2.1.1"	/* full version name */
+#define XCHAL_HW_VERSION_MAJOR		2210	/* major ver# of targeted hw */
+#define XCHAL_HW_VERSION_MINOR		1	/* minor ver# of targeted hw */
+#define XCHAL_HW_VERSION		221001	/* major*100+minor */
+#define XCHAL_HW_REL_LX2		1
+#define XCHAL_HW_REL_LX2_1		1
+#define XCHAL_HW_REL_LX2_1_1		1
+#define XCHAL_HW_CONFIGID_RELIABLE	1
+/*  If software targets a *range* of hardware versions, these are the bounds: */
+#define XCHAL_HW_MIN_VERSION_MAJOR	2210	/* major v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION_MINOR	1	/* minor v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION		221001	/* earliest targeted hw */
+#define XCHAL_HW_MAX_VERSION_MAJOR	2210	/* major v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION_MINOR	1	/* minor v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION		221001	/* latest targeted hw */
+
+
+/*----------------------------------------------------------------------
+				CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_ICACHE_LINESIZE		32	/* I-cache line size in bytes */
+#define XCHAL_DCACHE_LINESIZE		32	/* D-cache line size in bytes */
+#define XCHAL_ICACHE_LINEWIDTH		5	/* log2(I line size in bytes) */
+#define XCHAL_DCACHE_LINEWIDTH		5	/* log2(D line size in bytes) */
+
+#define XCHAL_ICACHE_SIZE		16384	/* I-cache size in bytes or 0 */
+#define XCHAL_DCACHE_SIZE		16384	/* D-cache size in bytes or 0 */
+
+#define XCHAL_DCACHE_IS_WRITEBACK	1	/* writeback feature */
+
+
+
+
+/****************************************************************************
+    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
+ ****************************************************************************/
+
+
+#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
+
+/*----------------------------------------------------------------------
+				CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_PIF			1	/* any outbound PIF present */
+
+/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
+
+/*  Number of cache sets in log2(lines per way):  */
+#define XCHAL_ICACHE_SETWIDTH		7
+#define XCHAL_DCACHE_SETWIDTH		7
+
+/*  Cache set associativity (number of ways):  */
+#define XCHAL_ICACHE_WAYS		4
+#define XCHAL_DCACHE_WAYS		4
+
+/*  Cache features:  */
+#define XCHAL_ICACHE_LINE_LOCKABLE	1
+#define XCHAL_DCACHE_LINE_LOCKABLE	1
+#define XCHAL_ICACHE_ECC_PARITY		0
+#define XCHAL_DCACHE_ECC_PARITY		0
+
+/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
+#define XCHAL_CA_BITS			4
+
+
+/*----------------------------------------------------------------------
+			INTERNAL I/D RAM/ROMs and XLMI
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_INSTROM		0	/* number of core instr. ROMs */
+#define XCHAL_NUM_INSTRAM		0	/* number of core instr. RAMs */
+#define XCHAL_NUM_DATAROM		0	/* number of core data ROMs */
+#define XCHAL_NUM_DATARAM		0	/* number of core data RAMs */
+#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
+#define XCHAL_NUM_XLMI			0	/* number of core XLMI ports */
+
+
+/*----------------------------------------------------------------------
+			INTERRUPTS and TIMERS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
+#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1	/* med/high-pri. interrupts */
+#define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
+#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
+#define XCHAL_NUM_TIMERS		3	/* number of CCOMPAREn regs */
+#define XCHAL_NUM_INTERRUPTS		22	/* number of interrupts */
+#define XCHAL_NUM_INTERRUPTS_LOG2	5	/* ceil(log2(NUM_INTERRUPTS)) */
+#define XCHAL_NUM_EXTINTERRUPTS		17	/* num of external interrupts */
+#define XCHAL_NUM_INTLEVELS		6	/* number of interrupt levels
+						   (not including level zero) */
+#define XCHAL_EXCM_LEVEL		3	/* level masked by PS.EXCM */
+	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
+
+/*  Masks of interrupts at each interrupt level:  */
+#define XCHAL_INTLEVEL1_MASK		0x001F80FF
+#define XCHAL_INTLEVEL2_MASK		0x00000100
+#define XCHAL_INTLEVEL3_MASK		0x00200E00
+#define XCHAL_INTLEVEL4_MASK		0x00001000
+#define XCHAL_INTLEVEL5_MASK		0x00002000
+#define XCHAL_INTLEVEL6_MASK		0x00000000
+#define XCHAL_INTLEVEL7_MASK		0x00004000
+
+/*  Masks of interrupts at each range 1..n of interrupt levels:  */
+#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x001F80FF
+#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x001F81FF
+#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x003F8FFF
+#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x003F9FFF
+#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0x003FBFFF
+#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0x003FBFFF
+#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0x003FFFFF
+
+/*  Level of each interrupt:  */
+#define XCHAL_INT0_LEVEL		1
+#define XCHAL_INT1_LEVEL		1
+#define XCHAL_INT2_LEVEL		1
+#define XCHAL_INT3_LEVEL		1
+#define XCHAL_INT4_LEVEL		1
+#define XCHAL_INT5_LEVEL		1
+#define XCHAL_INT6_LEVEL		1
+#define XCHAL_INT7_LEVEL		1
+#define XCHAL_INT8_LEVEL		2
+#define XCHAL_INT9_LEVEL		3
+#define XCHAL_INT10_LEVEL		3
+#define XCHAL_INT11_LEVEL		3
+#define XCHAL_INT12_LEVEL		4
+#define XCHAL_INT13_LEVEL		5
+#define XCHAL_INT14_LEVEL		7
+#define XCHAL_INT15_LEVEL		1
+#define XCHAL_INT16_LEVEL		1
+#define XCHAL_INT17_LEVEL		1
+#define XCHAL_INT18_LEVEL		1
+#define XCHAL_INT19_LEVEL		1
+#define XCHAL_INT20_LEVEL		1
+#define XCHAL_INT21_LEVEL		3
+#define XCHAL_DEBUGLEVEL		6	/* debug interrupt level */
+#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
+#define XCHAL_NMILEVEL			7	/* NMI "level" (for use with
+						   EXCSAVE/EPS/EPC_n, RFI n) */
+
+/*  Type of each interrupt:  */
+#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+
+/*  Masks of interrupts for each type of interrupt:  */
+#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFFC00000
+#define XCHAL_INTTYPE_MASK_SOFTWARE	0x00000880
+#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x003F8000
+#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x0000133F
+#define XCHAL_INTTYPE_MASK_TIMER	0x00002440
+#define XCHAL_INTTYPE_MASK_NMI		0x00004000
+#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000000
+
+/*  Interrupt numbers assigned to specific interrupt sources:  */
+#define XCHAL_TIMER0_INTERRUPT		6	/* CCOMPARE0 */
+#define XCHAL_TIMER1_INTERRUPT		10	/* CCOMPARE1 */
+#define XCHAL_TIMER2_INTERRUPT		13	/* CCOMPARE2 */
+#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
+#define XCHAL_NMI_INTERRUPT		14	/* non-maskable interrupt */
+
+/*  Interrupt numbers for levels at which only one interrupt is configured:  */
+#define XCHAL_INTLEVEL2_NUM		8
+#define XCHAL_INTLEVEL4_NUM		12
+#define XCHAL_INTLEVEL5_NUM		13
+#define XCHAL_INTLEVEL7_NUM		14
+/*  (There are many interrupts each at level(s) 1, 3.)  */
+
+
+/*
+ *  External interrupt vectors/levels.
+ *  These macros describe how Xtensa processor interrupt numbers
+ *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
+ *  map to external BInterrupt<n> pins, for those interrupts
+ *  configured as external (level-triggered, edge-triggered, or NMI).
+ *  See the Xtensa processor databook for more details.
+ */
+
+/*  Core interrupt numbers mapped to each EXTERNAL interrupt number:  */
+#define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
+#define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
+#define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
+#define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
+#define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
+#define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
+#define XCHAL_EXTINT6_NUM		8	/* (intlevel 2) */
+#define XCHAL_EXTINT7_NUM		9	/* (intlevel 3) */
+#define XCHAL_EXTINT8_NUM		12	/* (intlevel 4) */
+#define XCHAL_EXTINT9_NUM		14	/* (intlevel 7) */
+#define XCHAL_EXTINT10_NUM		15	/* (intlevel 1) */
+#define XCHAL_EXTINT11_NUM		16	/* (intlevel 1) */
+#define XCHAL_EXTINT12_NUM		17	/* (intlevel 1) */
+#define XCHAL_EXTINT13_NUM		18	/* (intlevel 1) */
+#define XCHAL_EXTINT14_NUM		19	/* (intlevel 1) */
+#define XCHAL_EXTINT15_NUM		20	/* (intlevel 1) */
+#define XCHAL_EXTINT16_NUM		21	/* (intlevel 3) */
+
+
+/*----------------------------------------------------------------------
+			EXCEPTIONS and VECTORS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
+						   number: 1 == XEA1 (old)
+							   2 == XEA2 (new)
+							   0 == XEAX (extern) */
+#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
+#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
+#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
+#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
+#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
+#define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
+#define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
+#define XCHAL_VECBASE_RESET_VADDR	0xD0000000  /* VECBASE reset value */
+#define XCHAL_VECBASE_RESET_PADDR	0x00000000
+#define XCHAL_RESET_VECBASE_OVERLAP	0
+
+#define XCHAL_RESET_VECTOR0_VADDR	0xFE000000
+#define XCHAL_RESET_VECTOR0_PADDR	0xFE000000
+#define XCHAL_RESET_VECTOR1_VADDR	0xD8000500
+#define XCHAL_RESET_VECTOR1_PADDR	0x00000500
+#define XCHAL_RESET_VECTOR_VADDR	0xFE000000
+#define XCHAL_RESET_VECTOR_PADDR	0xFE000000
+#define XCHAL_USER_VECOFS		0x00000340
+#define XCHAL_USER_VECTOR_VADDR		0xD0000340
+#define XCHAL_USER_VECTOR_PADDR		0x00000340
+#define XCHAL_KERNEL_VECOFS		0x00000300
+#define XCHAL_KERNEL_VECTOR_VADDR	0xD0000300
+#define XCHAL_KERNEL_VECTOR_PADDR	0x00000300
+#define XCHAL_DOUBLEEXC_VECOFS		0x000003C0
+#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0xD00003C0
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x000003C0
+#define XCHAL_WINDOW_OF4_VECOFS		0x00000000
+#define XCHAL_WINDOW_UF4_VECOFS		0x00000040
+#define XCHAL_WINDOW_OF8_VECOFS		0x00000080
+#define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
+#define XCHAL_WINDOW_OF12_VECOFS	0x00000100
+#define XCHAL_WINDOW_UF12_VECOFS	0x00000140
+#define XCHAL_WINDOW_VECTORS_VADDR	0xD0000000
+#define XCHAL_WINDOW_VECTORS_PADDR	0x00000000
+#define XCHAL_INTLEVEL2_VECOFS		0x00000180
+#define XCHAL_INTLEVEL2_VECTOR_VADDR	0xD0000180
+#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x00000180
+#define XCHAL_INTLEVEL3_VECOFS		0x000001C0
+#define XCHAL_INTLEVEL3_VECTOR_VADDR	0xD00001C0
+#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x000001C0
+#define XCHAL_INTLEVEL4_VECOFS		0x00000200
+#define XCHAL_INTLEVEL4_VECTOR_VADDR	0xD0000200
+#define XCHAL_INTLEVEL4_VECTOR_PADDR	0x00000200
+#define XCHAL_INTLEVEL5_VECOFS		0x00000240
+#define XCHAL_INTLEVEL5_VECTOR_VADDR	0xD0000240
+#define XCHAL_INTLEVEL5_VECTOR_PADDR	0x00000240
+#define XCHAL_INTLEVEL6_VECOFS		0x00000280
+#define XCHAL_INTLEVEL6_VECTOR_VADDR	0xD0000280
+#define XCHAL_INTLEVEL6_VECTOR_PADDR	0x00000280
+#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL6_VECOFS
+#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL6_VECTOR_VADDR
+#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL6_VECTOR_PADDR
+#define XCHAL_NMI_VECOFS		0x000002C0
+#define XCHAL_NMI_VECTOR_VADDR		0xD00002C0
+#define XCHAL_NMI_VECTOR_PADDR		0x000002C0
+#define XCHAL_INTLEVEL7_VECOFS		XCHAL_NMI_VECOFS
+#define XCHAL_INTLEVEL7_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
+#define XCHAL_INTLEVEL7_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
+
+
+/*----------------------------------------------------------------------
+				DEBUG
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
+#define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
+#define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
+#define XCHAL_HAVE_OCD_DIR_ARRAY	1	/* faster OCD option */
+
+
+/*----------------------------------------------------------------------
+				MMU
+  ----------------------------------------------------------------------*/
+
+/*  See core-matmap.h header file for more details.  */
+
+#define XCHAL_HAVE_TLBS			1	/* inverse of HAVE_CACHEATTR */
+#define XCHAL_HAVE_SPANNING_WAY		0	/* one way maps I+D 4GB vaddr */
+#define XCHAL_HAVE_IDENTITY_MAP		0	/* vaddr == paddr always */
+#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
+#define XCHAL_HAVE_MIMIC_CACHEATTR	0	/* region protection */
+#define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
+#define XCHAL_HAVE_PTP_MMU		1	/* full MMU (with page table
+						   [autorefill] and protection)
+						   usable for an MMU-based OS */
+/*  If none of the above last 4 are set, it's a custom TLB configuration.  */
+#define XCHAL_ITLB_ARF_ENTRIES_LOG2	2	/* log2(autorefill way size) */
+#define XCHAL_DTLB_ARF_ENTRIES_LOG2	2	/* log2(autorefill way size) */
+
+#define XCHAL_MMU_ASID_BITS		8	/* number of bits in ASIDs */
+#define XCHAL_MMU_RINGS			4	/* number of rings (1..4) */
+#define XCHAL_MMU_RING_BITS		2	/* num of bits in RING field */
+
+#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
+
+
+#endif /* _XTENSA_CORE_CONFIGURATION_H */
+
diff --git a/include/asm-xtensa/variant-dc232b/tie-asm.h b/include/asm-xtensa/variant-dc232b/tie-asm.h
new file mode 100644
index 000000000000..ed4f53f529db
--- /dev/null
+++ b/include/asm-xtensa/variant-dc232b/tie-asm.h
@@ -0,0 +1,122 @@
+/*
+ * This header file contains assembly-language definitions (assembly
+ * macros, etc.) for this specific Xtensa processor's TIE extensions
+ * and options.  It is customized to this Xtensa processor configuration.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999-2007 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_CORE_TIE_ASM_H
+#define _XTENSA_CORE_TIE_ASM_H
+
+/*  Selection parameter values for save-area save/restore macros:  */
+/*  Option vs. TIE:  */
+#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
+#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
+/*  Whether used automatically by compiler:  */
+#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
+#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
+/*  ABI handling across function calls:  */
+#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
+#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
+#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
+/*  Misc  */
+#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
+
+
+
+/* Macro to save all non-coprocessor (extra) custom TIE and optional state
+ * (not including zero-overhead loop registers).
+ * Save area ptr (clobbered):  ptr  (1 byte aligned)
+ * Scratch regs  (clobbered):  at1..at4  (only first XCHAL_NCP_NUM_ATMPS needed)
+ */
+	.macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL
+	xchal_sa_start	\continue, \ofs
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
+	xchal_sa_align	\ptr, 0, 1024-8, 4, 4
+	rsr	\at1, ACCLO		// MAC16 accumulator
+	rsr	\at2, ACCHI
+	s32i	\at1, \ptr, .Lxchal_ofs_ + 0
+	s32i	\at2, \ptr, .Lxchal_ofs_ + 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
+	.endif
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
+	xchal_sa_align	\ptr, 0, 1024-16, 4, 4
+	rsr	\at1, M0		// MAC16 registers
+	rsr	\at2, M1
+	s32i	\at1, \ptr, .Lxchal_ofs_ + 0
+	s32i	\at2, \ptr, .Lxchal_ofs_ + 4
+	rsr	\at1, M2
+	rsr	\at2, M3
+	s32i	\at1, \ptr, .Lxchal_ofs_ + 8
+	s32i	\at2, \ptr, .Lxchal_ofs_ + 12
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 16
+	.endif
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
+	xchal_sa_align	\ptr, 0, 1024-4, 4, 4
+	rsr	\at1, SCOMPARE1		// conditional store option
+	s32i	\at1, \ptr, .Lxchal_ofs_ + 0
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.endif
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
+	xchal_sa_align	\ptr, 0, 1024-4, 4, 4
+	rur	\at1, THREADPTR		// threadptr option
+	s32i	\at1, \ptr, .Lxchal_ofs_ + 0
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.endif
+	.endm	// xchal_ncp_store
+
+/* Macro to save all non-coprocessor (extra) custom TIE and optional state
+ * (not including zero-overhead loop registers).
+ * Save area ptr (clobbered):  ptr  (1 byte aligned)
+ * Scratch regs  (clobbered):  at1..at4  (only first XCHAL_NCP_NUM_ATMPS needed)
+ */
+	.macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL
+	xchal_sa_start	\continue, \ofs
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
+	xchal_sa_align	\ptr, 0, 1024-8, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_ + 0
+	l32i	\at2, \ptr, .Lxchal_ofs_ + 4
+	wsr	\at1, ACCLO		// MAC16 accumulator
+	wsr	\at2, ACCHI
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
+	.endif
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
+	xchal_sa_align	\ptr, 0, 1024-16, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_ + 0
+	l32i	\at2, \ptr, .Lxchal_ofs_ + 4
+	wsr	\at1, M0		// MAC16 registers
+	wsr	\at2, M1
+	l32i	\at1, \ptr, .Lxchal_ofs_ + 8
+	l32i	\at2, \ptr, .Lxchal_ofs_ + 12
+	wsr	\at1, M2
+	wsr	\at2, M3
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 16
+	.endif
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
+	xchal_sa_align	\ptr, 0, 1024-4, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_ + 0
+	wsr	\at1, SCOMPARE1		// conditional store option
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.endif
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
+	xchal_sa_align	\ptr, 0, 1024-4, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_ + 0
+	wur	\at1, THREADPTR		// threadptr option
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.endif
+	.endm	// xchal_ncp_load
+
+
+
+#define XCHAL_NCP_NUM_ATMPS	2
+
+
+#define XCHAL_SA_NUM_ATMPS	2
+
+#endif /*_XTENSA_CORE_TIE_ASM_H*/
+
diff --git a/include/asm-xtensa/variant-dc232b/tie.h b/include/asm-xtensa/variant-dc232b/tie.h
new file mode 100644
index 000000000000..018e81af4393
--- /dev/null
+++ b/include/asm-xtensa/variant-dc232b/tie.h
@@ -0,0 +1,131 @@
+/*
+ * This header file describes this specific Xtensa processor's TIE extensions
+ * that extend basic Xtensa core functionality.  It is customized to this
+ * Xtensa processor configuration.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999-2007 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_CORE_TIE_H
+#define _XTENSA_CORE_TIE_H
+
+#define XCHAL_CP_NUM			1	/* number of coprocessors */
+#define XCHAL_CP_MAX			8	/* max CP ID + 1 (0 if none) */
+#define XCHAL_CP_MASK			0x80	/* bitmask of all CPs by ID */
+#define XCHAL_CP_PORT_MASK		0x80	/* bitmask of only port CPs */
+
+/*  Basic parameters of each coprocessor:  */
+#define XCHAL_CP7_NAME			"XTIOP"
+#define XCHAL_CP7_IDENT			XTIOP
+#define XCHAL_CP7_SA_SIZE		0	/* size of state save area */
+#define XCHAL_CP7_SA_ALIGN		1	/* min alignment of save area */
+#define XCHAL_CP_ID_XTIOP		7	/* coprocessor ID (0..7) */
+
+/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
+#define XCHAL_CP0_SA_SIZE		0
+#define XCHAL_CP0_SA_ALIGN		1
+#define XCHAL_CP1_SA_SIZE		0
+#define XCHAL_CP1_SA_ALIGN		1
+#define XCHAL_CP2_SA_SIZE		0
+#define XCHAL_CP2_SA_ALIGN		1
+#define XCHAL_CP3_SA_SIZE		0
+#define XCHAL_CP3_SA_ALIGN		1
+#define XCHAL_CP4_SA_SIZE		0
+#define XCHAL_CP4_SA_ALIGN		1
+#define XCHAL_CP5_SA_SIZE		0
+#define XCHAL_CP5_SA_ALIGN		1
+#define XCHAL_CP6_SA_SIZE		0
+#define XCHAL_CP6_SA_ALIGN		1
+
+/*  Save area for non-coprocessor optional and custom (TIE) state:  */
+#define XCHAL_NCP_SA_SIZE		32
+#define XCHAL_NCP_SA_ALIGN		4
+
+/*  Total save area for optional and custom state (NCP + CPn):  */
+#define XCHAL_TOTAL_SA_SIZE		32	/* with 16-byte align padding */
+#define XCHAL_TOTAL_SA_ALIGN		4	/* actual minimum alignment */
+
+/*
+ * Detailed contents of save areas.
+ * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
+ * before expanding the XCHAL_xxx_SA_LIST() macros.
+ *
+ * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
+ *		dbnum,base,regnum,bitsz,gapsz,reset,x...)
+ *
+ *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
+ *	ccused = set if used by compiler without special options or code
+ *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
+ *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
+ *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
+ *	name = lowercase reg name (no quotes)
+ *	galign = group byte alignment (power of 2) (galign >= align)
+ *	align = register byte alignment (power of 2)
+ *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
+ *	  (not including any pad bytes required to galign this or next reg)
+ *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
+ *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)
+ *	regnum = reg index in regfile, or special/TIE-user reg number
+ *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
+ *	gapsz = intervening bits, if bitsz bits not stored contiguously
+ *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
+ *	reset = register reset value (or 0 if undefined at reset)
+ *	x = reserved for future use (0 until then)
+ *
+ *  To filter out certain registers, e.g. to expand only the non-global
+ *  registers used by the compiler, you can do something like this:
+ *
+ *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)
+ *  #define SELCC0(p...)
+ *  #define SELCC1(abikind,p...)	SELAK##abikind(p)
+ *  #define SELAK0(p...)		REG(p)
+ *  #define SELAK1(p...)		REG(p)
+ *  #define SELAK2(p...)
+ *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
+ *		...what you want to expand...
+ */
+
+#define XCHAL_NCP_SA_NUM	8
+#define XCHAL_NCP_SA_LIST(s)	\
+ XCHAL_SA_REG(s,1,0,0,1,          acclo, 4, 4, 4,0x0210,  sr,16 , 32,0,0,0) \
+ XCHAL_SA_REG(s,1,0,0,1,          acchi, 4, 4, 4,0x0211,  sr,17 ,  8,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m0, 4, 4, 4,0x0220,  sr,32 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m1, 4, 4, 4,0x0221,  sr,33 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m2, 4, 4, 4,0x0222,  sr,34 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m3, 4, 4, 4,0x0223,  sr,35 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,      scompare1, 4, 4, 4,0x020C,  sr,12 , 32,0,0,0) \
+ XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0)
+
+#define XCHAL_CP0_SA_NUM	0
+#define XCHAL_CP0_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP1_SA_NUM	0
+#define XCHAL_CP1_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP2_SA_NUM	0
+#define XCHAL_CP2_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP3_SA_NUM	0
+#define XCHAL_CP3_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP4_SA_NUM	0
+#define XCHAL_CP4_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP5_SA_NUM	0
+#define XCHAL_CP5_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP6_SA_NUM	0
+#define XCHAL_CP6_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP7_SA_NUM	0
+#define XCHAL_CP7_SA_LIST(s)	/* empty */
+
+/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
+#define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
+
+#endif /*_XTENSA_CORE_TIE_H*/
+
diff --git a/include/crypto/aes.h b/include/crypto/aes.h
index 40008d67ee3d..656a4c66a568 100644
--- a/include/crypto/aes.h
+++ b/include/crypto/aes.h
@@ -23,10 +23,10 @@ struct crypto_aes_ctx {
 	u32 key_dec[AES_MAX_KEYLENGTH_U32];
 };
 
-extern u32 crypto_ft_tab[4][256];
-extern u32 crypto_fl_tab[4][256];
-extern u32 crypto_it_tab[4][256];
-extern u32 crypto_il_tab[4][256];
+extern const u32 crypto_ft_tab[4][256];
+extern const u32 crypto_fl_tab[4][256];
+extern const u32 crypto_it_tab[4][256];
+extern const u32 crypto_il_tab[4][256];
 
 int crypto_aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
 		unsigned int key_len);
diff --git a/include/crypto/algapi.h b/include/crypto/algapi.h
index 60d06e784be3..010545436efa 100644
--- a/include/crypto/algapi.h
+++ b/include/crypto/algapi.h
@@ -22,9 +22,18 @@ struct seq_file;
 
 struct crypto_type {
 	unsigned int (*ctxsize)(struct crypto_alg *alg, u32 type, u32 mask);
+	unsigned int (*extsize)(struct crypto_alg *alg,
+				const struct crypto_type *frontend);
 	int (*init)(struct crypto_tfm *tfm, u32 type, u32 mask);
-	void (*exit)(struct crypto_tfm *tfm);
+	int (*init_tfm)(struct crypto_tfm *tfm,
+		        const struct crypto_type *frontend);
 	void (*show)(struct seq_file *m, struct crypto_alg *alg);
+	struct crypto_alg *(*lookup)(const char *name, u32 type, u32 mask);
+
+	unsigned int type;
+	unsigned int maskclear;
+	unsigned int maskset;
+	unsigned int tfmsize;
 };
 
 struct crypto_instance {
@@ -239,6 +248,11 @@ static inline struct crypto_hash *crypto_spawn_hash(struct crypto_spawn *spawn)
 	return __crypto_hash_cast(crypto_spawn_tfm(spawn, type, mask));
 }
 
+static inline void *crypto_hash_ctx(struct crypto_hash *tfm)
+{
+	return crypto_tfm_ctx(&tfm->base);
+}
+
 static inline void *crypto_hash_ctx_aligned(struct crypto_hash *tfm)
 {
 	return crypto_tfm_ctx_aligned(&tfm->base);
diff --git a/include/crypto/hash.h b/include/crypto/hash.h
index ee48ef8fb2ea..cd16d6e668ce 100644
--- a/include/crypto/hash.h
+++ b/include/crypto/hash.h
@@ -15,10 +15,40 @@
 
 #include <linux/crypto.h>
 
+struct shash_desc {
+	struct crypto_shash *tfm;
+	u32 flags;
+
+	void *__ctx[] CRYPTO_MINALIGN_ATTR;
+};
+
+struct shash_alg {
+	int (*init)(struct shash_desc *desc);
+	int (*reinit)(struct shash_desc *desc);
+	int (*update)(struct shash_desc *desc, const u8 *data,
+		      unsigned int len);
+	int (*final)(struct shash_desc *desc, u8 *out);
+	int (*finup)(struct shash_desc *desc, const u8 *data,
+		     unsigned int len, u8 *out);
+	int (*digest)(struct shash_desc *desc, const u8 *data,
+		      unsigned int len, u8 *out);
+	int (*setkey)(struct crypto_shash *tfm, const u8 *key,
+		      unsigned int keylen);
+
+	unsigned int descsize;
+	unsigned int digestsize;
+
+	struct crypto_alg base;
+};
+
 struct crypto_ahash {
 	struct crypto_tfm base;
 };
 
+struct crypto_shash {
+	struct crypto_tfm base;
+};
+
 static inline struct crypto_ahash *__crypto_ahash_cast(struct crypto_tfm *tfm)
 {
 	return (struct crypto_ahash *)tfm;
@@ -87,6 +117,11 @@ static inline unsigned int crypto_ahash_reqsize(struct crypto_ahash *tfm)
 	return crypto_ahash_crt(tfm)->reqsize;
 }
 
+static inline void *ahash_request_ctx(struct ahash_request *req)
+{
+	return req->__ctx;
+}
+
 static inline int crypto_ahash_setkey(struct crypto_ahash *tfm,
 				      const u8 *key, unsigned int keylen)
 {
@@ -101,6 +136,14 @@ static inline int crypto_ahash_digest(struct ahash_request *req)
 	return crt->digest(req);
 }
 
+static inline void crypto_ahash_export(struct ahash_request *req, u8 *out)
+{
+	memcpy(out, ahash_request_ctx(req),
+	       crypto_ahash_reqsize(crypto_ahash_reqtfm(req)));
+}
+
+int crypto_ahash_import(struct ahash_request *req, const u8 *in);
+
 static inline int crypto_ahash_init(struct ahash_request *req)
 {
 	struct ahash_tfm *crt = crypto_ahash_crt(crypto_ahash_reqtfm(req));
@@ -169,4 +212,86 @@ static inline void ahash_request_set_crypt(struct ahash_request *req,
 	req->result = result;
 }
 
+struct crypto_shash *crypto_alloc_shash(const char *alg_name, u32 type,
+					u32 mask);
+
+static inline struct crypto_tfm *crypto_shash_tfm(struct crypto_shash *tfm)
+{
+	return &tfm->base;
+}
+
+static inline void crypto_free_shash(struct crypto_shash *tfm)
+{
+	crypto_free_tfm(crypto_shash_tfm(tfm));
+}
+
+static inline unsigned int crypto_shash_alignmask(
+	struct crypto_shash *tfm)
+{
+	return crypto_tfm_alg_alignmask(crypto_shash_tfm(tfm));
+}
+
+static inline struct shash_alg *__crypto_shash_alg(struct crypto_alg *alg)
+{
+	return container_of(alg, struct shash_alg, base);
+}
+
+static inline struct shash_alg *crypto_shash_alg(struct crypto_shash *tfm)
+{
+	return __crypto_shash_alg(crypto_shash_tfm(tfm)->__crt_alg);
+}
+
+static inline unsigned int crypto_shash_digestsize(struct crypto_shash *tfm)
+{
+	return crypto_shash_alg(tfm)->digestsize;
+}
+
+static inline u32 crypto_shash_get_flags(struct crypto_shash *tfm)
+{
+	return crypto_tfm_get_flags(crypto_shash_tfm(tfm));
+}
+
+static inline void crypto_shash_set_flags(struct crypto_shash *tfm, u32 flags)
+{
+	crypto_tfm_set_flags(crypto_shash_tfm(tfm), flags);
+}
+
+static inline void crypto_shash_clear_flags(struct crypto_shash *tfm, u32 flags)
+{
+	crypto_tfm_clear_flags(crypto_shash_tfm(tfm), flags);
+}
+
+static inline unsigned int crypto_shash_descsize(struct crypto_shash *tfm)
+{
+	return crypto_shash_alg(tfm)->descsize;
+}
+
+static inline void *shash_desc_ctx(struct shash_desc *desc)
+{
+	return desc->__ctx;
+}
+
+int crypto_shash_setkey(struct crypto_shash *tfm, const u8 *key,
+			unsigned int keylen);
+int crypto_shash_digest(struct shash_desc *desc, const u8 *data,
+			unsigned int len, u8 *out);
+
+static inline void crypto_shash_export(struct shash_desc *desc, u8 *out)
+{
+	memcpy(out, shash_desc_ctx(desc), crypto_shash_descsize(desc->tfm));
+}
+
+int crypto_shash_import(struct shash_desc *desc, const u8 *in);
+
+static inline int crypto_shash_init(struct shash_desc *desc)
+{
+	return crypto_shash_alg(desc->tfm)->init(desc);
+}
+
+int crypto_shash_update(struct shash_desc *desc, const u8 *data,
+			unsigned int len);
+int crypto_shash_final(struct shash_desc *desc, u8 *out);
+int crypto_shash_finup(struct shash_desc *desc, const u8 *data,
+		       unsigned int len, u8 *out);
+
 #endif	/* _CRYPTO_HASH_H */
diff --git a/include/crypto/internal/hash.h b/include/crypto/internal/hash.h
index 917ae57bad4a..82b70564bcab 100644
--- a/include/crypto/internal/hash.h
+++ b/include/crypto/internal/hash.h
@@ -39,6 +39,12 @@ extern const struct crypto_type crypto_ahash_type;
 int crypto_hash_walk_done(struct crypto_hash_walk *walk, int err);
 int crypto_hash_walk_first(struct ahash_request *req,
 			   struct crypto_hash_walk *walk);
+int crypto_hash_walk_first_compat(struct hash_desc *hdesc,
+				  struct crypto_hash_walk *walk,
+				  struct scatterlist *sg, unsigned int len);
+
+int crypto_register_shash(struct shash_alg *alg);
+int crypto_unregister_shash(struct shash_alg *alg);
 
 static inline void *crypto_ahash_ctx(struct crypto_ahash *tfm)
 {
@@ -63,16 +69,16 @@ static inline struct ahash_request *ahash_dequeue_request(
 	return ahash_request_cast(crypto_dequeue_request(queue));
 }
 
-static inline void *ahash_request_ctx(struct ahash_request *req)
-{
-	return req->__ctx;
-}
-
 static inline int ahash_tfm_in_queue(struct crypto_queue *queue,
 					  struct crypto_ahash *tfm)
 {
 	return crypto_tfm_in_queue(queue, crypto_ahash_tfm(tfm));
 }
 
+static inline void *crypto_shash_ctx(struct crypto_shash *tfm)
+{
+	return crypto_tfm_ctx(&tfm->base);
+}
+
 #endif	/* _CRYPTO_INTERNAL_HASH_H */
 
diff --git a/include/drm/Kbuild b/include/drm/Kbuild
index 82b6983b7fbb..b940fdfa3b25 100644
--- a/include/drm/Kbuild
+++ b/include/drm/Kbuild
@@ -1,4 +1,4 @@
-unifdef-y += drm.h drm_sarea.h
+unifdef-y += drm.h drm_sarea.h drm_mode.h
 unifdef-y += i810_drm.h
 unifdef-y += i830_drm.h
 unifdef-y += i915_drm.h
diff --git a/include/drm/drm.h b/include/drm/drm.h
index 38d3c6b8276a..32e5096554e9 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -36,7 +36,6 @@
 #ifndef _DRM_H_
 #define _DRM_H_
 
-#if defined(__linux__)
 #if defined(__KERNEL__)
 #endif
 #include <asm/ioctl.h>		/* For _IO* macros */
@@ -46,22 +45,6 @@
 #define DRM_IOC_WRITE		_IOC_WRITE
 #define DRM_IOC_READWRITE	_IOC_READ|_IOC_WRITE
 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
-#elif defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)
-#if defined(__FreeBSD__) && defined(IN_MODULE)
-/* Prevent name collision when including sys/ioccom.h */
-#undef ioctl
-#include <sys/ioccom.h>
-#define ioctl(a,b,c)		xf86ioctl(a,b,c)
-#else
-#include <sys/ioccom.h>
-#endif				/* __FreeBSD__ && xf86ioctl */
-#define DRM_IOCTL_NR(n)		((n) & 0xff)
-#define DRM_IOC_VOID		IOC_VOID
-#define DRM_IOC_READ		IOC_OUT
-#define DRM_IOC_WRITE		IOC_IN
-#define DRM_IOC_READWRITE	IOC_INOUT
-#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
-#endif
 
 #define DRM_MAJOR       226
 #define DRM_MAX_MINOR   15
@@ -190,6 +173,7 @@ enum drm_map_type {
 	_DRM_AGP = 3,		  /**< AGP/GART */
 	_DRM_SCATTER_GATHER = 4,  /**< Scatter/gather memory for PCI DMA */
 	_DRM_CONSISTENT = 5,	  /**< Consistent memory for PCI DMA */
+	_DRM_GEM = 6,		  /**< GEM object */
 };
 
 /**
@@ -471,6 +455,7 @@ struct drm_irq_busid {
 enum drm_vblank_seq_type {
 	_DRM_VBLANK_ABSOLUTE = 0x0,	/**< Wait for specific vblank sequence number */
 	_DRM_VBLANK_RELATIVE = 0x1,	/**< Wait for given number of vblanks */
+	_DRM_VBLANK_FLIP = 0x8000000,   /**< Scheduled buffer swap should flip */
 	_DRM_VBLANK_NEXTONMISS = 0x10000000,	/**< If missed, wait for next vblank */
 	_DRM_VBLANK_SECONDARY = 0x20000000,	/**< Secondary display controller */
 	_DRM_VBLANK_SIGNAL = 0x40000000	/**< Send signal instead of blocking */
@@ -503,6 +488,19 @@ union drm_wait_vblank {
 	struct drm_wait_vblank_reply reply;
 };
 
+#define _DRM_PRE_MODESET 1
+#define _DRM_POST_MODESET 2
+
+/**
+ * DRM_IOCTL_MODESET_CTL ioctl argument type
+ *
+ * \sa drmModesetCtl().
+ */
+struct drm_modeset_ctl {
+	uint32_t crtc;
+	uint32_t cmd;
+};
+
 /**
  * DRM_IOCTL_AGP_ENABLE ioctl argument type.
  *
@@ -573,6 +571,36 @@ struct drm_set_version {
 	int drm_dd_minor;
 };
 
+/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
+struct drm_gem_close {
+	/** Handle of the object to be closed. */
+	uint32_t handle;
+	uint32_t pad;
+};
+
+/** DRM_IOCTL_GEM_FLINK ioctl argument type */
+struct drm_gem_flink {
+	/** Handle for the object being named */
+	uint32_t handle;
+
+	/** Returned global name */
+	uint32_t name;
+};
+
+/** DRM_IOCTL_GEM_OPEN ioctl argument type */
+struct drm_gem_open {
+	/** Name of object being opened */
+	uint32_t name;
+
+	/** Returned handle for the object */
+	uint32_t handle;
+
+	/** Returned size of the object */
+	uint64_t size;
+};
+
+#include "drm_mode.h"
+
 #define DRM_IOCTL_BASE			'd'
 #define DRM_IO(nr)			_IO(DRM_IOCTL_BASE,nr)
 #define DRM_IOR(nr,type)		_IOR(DRM_IOCTL_BASE,nr,type)
@@ -587,6 +615,10 @@ struct drm_set_version {
 #define DRM_IOCTL_GET_CLIENT            DRM_IOWR(0x05, struct drm_client)
 #define DRM_IOCTL_GET_STATS             DRM_IOR( 0x06, struct drm_stats)
 #define DRM_IOCTL_SET_VERSION		DRM_IOWR(0x07, struct drm_set_version)
+#define DRM_IOCTL_MODESET_CTL           DRM_IOW(0x08, struct drm_modeset_ctl)
+#define DRM_IOCTL_GEM_CLOSE		DRM_IOW (0x09, struct drm_gem_close)
+#define DRM_IOCTL_GEM_FLINK		DRM_IOWR(0x0a, struct drm_gem_flink)
+#define DRM_IOCTL_GEM_OPEN		DRM_IOWR(0x0b, struct drm_gem_open)
 
 #define DRM_IOCTL_SET_UNIQUE		DRM_IOW( 0x10, struct drm_unique)
 #define DRM_IOCTL_AUTH_MAGIC		DRM_IOW( 0x11, struct drm_auth)
@@ -605,6 +637,9 @@ struct drm_set_version {
 #define DRM_IOCTL_SET_SAREA_CTX		DRM_IOW( 0x1c, struct drm_ctx_priv_map)
 #define DRM_IOCTL_GET_SAREA_CTX 	DRM_IOWR(0x1d, struct drm_ctx_priv_map)
 
+#define DRM_IOCTL_SET_MASTER            DRM_IO(0x1e)
+#define DRM_IOCTL_DROP_MASTER           DRM_IO(0x1f)
+
 #define DRM_IOCTL_ADD_CTX		DRM_IOWR(0x20, struct drm_ctx)
 #define DRM_IOCTL_RM_CTX		DRM_IOWR(0x21, struct drm_ctx)
 #define DRM_IOCTL_MOD_CTX		DRM_IOW( 0x22, struct drm_ctx)
@@ -635,6 +670,24 @@ struct drm_set_version {
 
 #define DRM_IOCTL_UPDATE_DRAW		DRM_IOW(0x3f, struct drm_update_draw)
 
+#define DRM_IOCTL_MODE_GETRESOURCES	DRM_IOWR(0xA0, struct drm_mode_card_res)
+#define DRM_IOCTL_MODE_GETCRTC		DRM_IOWR(0xA1, struct drm_mode_crtc)
+#define DRM_IOCTL_MODE_SETCRTC		DRM_IOWR(0xA2, struct drm_mode_crtc)
+#define DRM_IOCTL_MODE_CURSOR		DRM_IOWR(0xA3, struct drm_mode_cursor)
+#define DRM_IOCTL_MODE_GETGAMMA		DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
+#define DRM_IOCTL_MODE_SETGAMMA		DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
+#define DRM_IOCTL_MODE_GETENCODER	DRM_IOWR(0xA6, struct drm_mode_get_encoder)
+#define DRM_IOCTL_MODE_GETCONNECTOR	DRM_IOWR(0xA7, struct drm_mode_get_connector)
+#define DRM_IOCTL_MODE_ATTACHMODE	DRM_IOWR(0xA8, struct drm_mode_mode_cmd)
+#define DRM_IOCTL_MODE_DETACHMODE	DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
+
+#define DRM_IOCTL_MODE_GETPROPERTY	DRM_IOWR(0xAA, struct drm_mode_get_property)
+#define DRM_IOCTL_MODE_SETPROPERTY	DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
+#define DRM_IOCTL_MODE_GETPROPBLOB	DRM_IOWR(0xAC, struct drm_mode_get_blob)
+#define DRM_IOCTL_MODE_GETFB		DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
+#define DRM_IOCTL_MODE_ADDFB		DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
+#define DRM_IOCTL_MODE_RMFB		DRM_IOWR(0xAF, unsigned int)
+
 /**
  * Device specific ioctls should only be in their respective headers
  * The device specific ioctl range is from 0x40 to 0x99.
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 1c1b13e29223..afb7858c068d 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -104,6 +104,8 @@ struct drm_device;
 #define DRIVER_DMA_QUEUE   0x200
 #define DRIVER_FB_DMA      0x400
 #define DRIVER_IRQ_VBL2    0x800
+#define DRIVER_GEM         0x1000
+#define DRIVER_MODESET     0x2000
 
 /***********************************************************************/
 /** \name Begin the DRM... */
@@ -237,11 +239,11 @@ struct drm_device;
  */
 #define LOCK_TEST_WITH_RETURN( dev, file_priv )				\
 do {									\
-	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||		\
-	     dev->lock.file_priv != file_priv )	{			\
+	if (!_DRM_LOCK_IS_HELD(file_priv->master->lock.hw_lock->lock) ||		\
+	    file_priv->master->lock.file_priv != file_priv)	{			\
 		DRM_ERROR( "%s called without lock held, held  %d owner %p %p\n",\
-			   __func__, _DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ),\
-			   dev->lock.file_priv, file_priv );		\
+			   __func__, _DRM_LOCK_IS_HELD(file_priv->master->lock.hw_lock->lock),\
+			   file_priv->master->lock.file_priv, file_priv);		\
 		return -EINVAL;						\
 	}								\
 } while (0)
@@ -275,6 +277,7 @@ typedef int drm_ioctl_compat_t(struct file *filp, unsigned int cmd,
 #define DRM_AUTH	0x1
 #define	DRM_MASTER	0x2
 #define DRM_ROOT_ONLY	0x4
+#define DRM_CONTROL_ALLOW 0x8
 
 struct drm_ioctl_desc {
 	unsigned int cmd;
@@ -378,17 +381,26 @@ struct drm_buf_entry {
 /** File private data */
 struct drm_file {
 	int authenticated;
-	int master;
 	pid_t pid;
 	uid_t uid;
 	drm_magic_t magic;
 	unsigned long ioctl_count;
 	struct list_head lhead;
 	struct drm_minor *minor;
-	int remove_auth_on_close;
 	unsigned long lock_count;
+
+	/** Mapping of mm object handles to object pointers. */
+	struct idr object_idr;
+	/** Lock for synchronization of access to object_idr. */
+	spinlock_t table_lock;
+
 	struct file *filp;
 	void *driver_priv;
+
+	int is_master; /* this file private is a master for a minor */
+	struct drm_master *master; /* master this node is currently associated with
+				      N.B. not always minor->master */
+	struct list_head fbs;
 };
 
 /** Wait queue */
@@ -518,6 +530,8 @@ struct drm_map_list {
 	struct drm_hash_item hash;
 	struct drm_map *map;			/**< mapping */
 	uint64_t user_token;
+	struct drm_master *master;
+	struct drm_mm_node *file_offset_node;	/**< fake offset */
 };
 
 typedef struct drm_map drm_local_map_t;
@@ -558,6 +572,94 @@ struct drm_ati_pcigart_info {
 };
 
 /**
+ * GEM specific mm private for tracking GEM objects
+ */
+struct drm_gem_mm {
+	struct drm_mm offset_manager;	/**< Offset mgmt for buffer objects */
+	struct drm_open_hash offset_hash; /**< User token hash table for maps */
+};
+
+/**
+ * This structure defines the drm_mm memory object, which will be used by the
+ * DRM for its buffer objects.
+ */
+struct drm_gem_object {
+	/** Reference count of this object */
+	struct kref refcount;
+
+	/** Handle count of this object. Each handle also holds a reference */
+	struct kref handlecount;
+
+	/** Related drm device */
+	struct drm_device *dev;
+
+	/** File representing the shmem storage */
+	struct file *filp;
+
+	/* Mapping info for this object */
+	struct drm_map_list map_list;
+
+	/**
+	 * Size of the object, in bytes.  Immutable over the object's
+	 * lifetime.
+	 */
+	size_t size;
+
+	/**
+	 * Global name for this object, starts at 1. 0 means unnamed.
+	 * Access is covered by the object_name_lock in the related drm_device
+	 */
+	int name;
+
+	/**
+	 * Memory domains. These monitor which caches contain read/write data
+	 * related to the object. When transitioning from one set of domains
+	 * to another, the driver is called to ensure that caches are suitably
+	 * flushed and invalidated
+	 */
+	uint32_t read_domains;
+	uint32_t write_domain;
+
+	/**
+	 * While validating an exec operation, the
+	 * new read/write domain values are computed here.
+	 * They will be transferred to the above values
+	 * at the point that any cache flushing occurs
+	 */
+	uint32_t pending_read_domains;
+	uint32_t pending_write_domain;
+
+	void *driver_private;
+};
+
+#include "drm_crtc.h"
+
+/* per-master structure */
+struct drm_master {
+
+	struct kref refcount; /* refcount for this master */
+
+	struct list_head head; /**< each minor contains a list of masters */
+	struct drm_minor *minor; /**< link back to minor we are a master for */
+
+	char *unique;			/**< Unique identifier: e.g., busid */
+	int unique_len;			/**< Length of unique field */
+	int unique_size;		/**< amount allocated */
+
+	int blocked;			/**< Blocked due to VC switch? */
+
+	/** \name Authentication */
+	/*@{ */
+	struct drm_open_hash magiclist;
+	struct list_head magicfree;
+	/*@} */
+
+	struct drm_lock_data lock;	/**< Information on hardware lock */
+
+	void *driver_priv; /**< Private structure for driver to use */
+};
+
+/**
  * DRM driver structure. This structure represent the common code for
  * a family of cards. There will one drm_device for each card present
  * in this family
@@ -580,11 +682,54 @@ struct drm_driver {
 	int (*kernel_context_switch) (struct drm_device *dev, int old,
 				      int new);
 	void (*kernel_context_switch_unlock) (struct drm_device *dev);
-	int (*vblank_wait) (struct drm_device *dev, unsigned int *sequence);
-	int (*vblank_wait2) (struct drm_device *dev, unsigned int *sequence);
 	int (*dri_library_name) (struct drm_device *dev, char *buf);
 
 	/**
+	 * get_vblank_counter - get raw hardware vblank counter
+	 * @dev: DRM device
+	 * @crtc: counter to fetch
+	 *
+	 * Driver callback for fetching a raw hardware vblank counter
+	 * for @crtc.  If a device doesn't have a hardware counter, the
+	 * driver can simply return the value of drm_vblank_count and
+	 * make the enable_vblank() and disable_vblank() hooks into no-ops,
+	 * leaving interrupts enabled at all times.
+	 *
+	 * Wraparound handling and loss of events due to modesetting is dealt
+	 * with in the DRM core code.
+	 *
+	 * RETURNS
+	 * Raw vblank counter value.
+	 */
+	u32 (*get_vblank_counter) (struct drm_device *dev, int crtc);
+
+	/**
+	 * enable_vblank - enable vblank interrupt events
+	 * @dev: DRM device
+	 * @crtc: which irq to enable
+	 *
+	 * Enable vblank interrupts for @crtc.  If the device doesn't have
+	 * a hardware vblank counter, this routine should be a no-op, since
+	 * interrupts will have to stay on to keep the count accurate.
+	 *
+	 * RETURNS
+	 * Zero on success, appropriate errno if the given @crtc's vblank
+	 * interrupt cannot be enabled.
+	 */
+	int (*enable_vblank) (struct drm_device *dev, int crtc);
+
+	/**
+	 * disable_vblank - disable vblank interrupt events
+	 * @dev: DRM device
+	 * @crtc: which irq to enable
+	 *
+	 * Disable vblank interrupts for @crtc.  If the device doesn't have
+	 * a hardware vblank counter, this routine should be a no-op, since
+	 * interrupts will have to stay on to keep the count accurate.
+	 */
+	void (*disable_vblank) (struct drm_device *dev, int crtc);
+
+	/**
 	 * Called by \c drm_device_is_agp.  Typically used to determine if a
 	 * card is really attached to AGP or not.
 	 *
@@ -601,7 +746,7 @@ struct drm_driver {
 
 	irqreturn_t(*irq_handler) (DRM_IRQ_ARGS);
 	void (*irq_preinstall) (struct drm_device *dev);
-	void (*irq_postinstall) (struct drm_device *dev);
+	int (*irq_postinstall) (struct drm_device *dev);
 	void (*irq_uninstall) (struct drm_device *dev);
 	void (*reclaim_buffers) (struct drm_device *dev,
 				 struct drm_file * file_priv);
@@ -614,6 +759,25 @@ struct drm_driver {
 	void (*set_version) (struct drm_device *dev,
 			     struct drm_set_version *sv);
 
+	/* Master routines */
+	int (*master_create)(struct drm_device *dev, struct drm_master *master);
+	void (*master_destroy)(struct drm_device *dev, struct drm_master *master);
+
+	int (*proc_init)(struct drm_minor *minor);
+	void (*proc_cleanup)(struct drm_minor *minor);
+
+	/**
+	 * Driver-specific constructor for drm_gem_objects, to set up
+	 * obj->driver_private.
+	 *
+	 * Returns 0 on success.
+	 */
+	int (*gem_init_object) (struct drm_gem_object *obj);
+	void (*gem_free_object) (struct drm_gem_object *obj);
+
+	/* Driver private ops for this object */
+	struct vm_operations_struct *gem_vm_ops;
+
 	int major;
 	int minor;
 	int patchlevel;
@@ -627,10 +791,14 @@ struct drm_driver {
 	int num_ioctls;
 	struct file_operations fops;
 	struct pci_driver pci_driver;
+	/* List of devices hanging off this driver */
+	struct list_head device_list;
 };
 
 #define DRM_MINOR_UNASSIGNED 0
 #define DRM_MINOR_LEGACY 1
+#define DRM_MINOR_CONTROL 2
+#define DRM_MINOR_RENDER 3
 
 /**
  * DRM minor structure. This structure represents a drm minor number.
@@ -642,6 +810,9 @@ struct drm_minor {
 	struct device kdev;		/**< Linux device */
 	struct drm_device *dev;
 	struct proc_dir_entry *dev_root;  /**< proc directory entry */
+	struct drm_master *master; /* currently active master for this node */
+	struct list_head master_list;
+	struct drm_mode_group mode_group;
 };
 
 /**
@@ -649,13 +820,10 @@ struct drm_minor {
  * may contain multiple heads.
  */
 struct drm_device {
-	char *unique;			/**< Unique identifier: e.g., busid */
-	int unique_len;			/**< Length of unique field */
+	struct list_head driver_item;	/**< list of devices per driver */
 	char *devname;			/**< For /proc/interrupts */
 	int if_version;			/**< Highest interface version set */
 
-	int blocked;			/**< Blocked due to VC switch? */
-
 	/** \name Locks */
 	/*@{ */
 	spinlock_t count_lock;		/**< For inuse, drm_device::open_count, drm_device::buf_use */
@@ -678,12 +846,7 @@ struct drm_device {
 	atomic_t counts[15];
 	/*@} */
 
-	/** \name Authentication */
-	/*@{ */
 	struct list_head filelist;
-	struct drm_open_hash magiclist;	/**< magic hash table */
-	struct list_head magicfree;
-	/*@} */
 
 	/** \name Memory management */
 	/*@{ */
@@ -700,7 +863,7 @@ struct drm_device {
 	struct idr ctx_idr;
 
 	struct list_head vmalist;	/**< List of vmas (for debugging) */
-	struct drm_lock_data lock;	/**< Information on hardware lock */
+
 	/*@} */
 
 	/** \name DMA queues (contexts) */
@@ -714,7 +877,6 @@ struct drm_device {
 
 	/** \name Context support */
 	/*@{ */
-	int irq;			/**< Interrupt used by board */
 	int irq_enabled;		/**< True if irq handler is enabled */
 	__volatile__ long context_flag;	/**< Context swapping flag */
 	__volatile__ long interrupt_flag; /**< Interruption handler flag */
@@ -730,15 +892,29 @@ struct drm_device {
 	/** \name VBLANK IRQ support */
 	/*@{ */
 
-	wait_queue_head_t vbl_queue;	/**< VBLANK wait queue */
-	atomic_t vbl_received;
-	atomic_t vbl_received2;		/**< number of secondary VBLANK interrupts */
+	/*
+	 * At load time, disabling the vblank interrupt won't be allowed since
+	 * old clients may not call the modeset ioctl and therefore misbehave.
+	 * Once the modeset ioctl *has* been called though, we can safely
+	 * disable them when unused.
+	 */
+	int vblank_disable_allowed;
+
+	wait_queue_head_t *vbl_queue;   /**< VBLANK wait queue */
+	atomic_t *_vblank_count;        /**< number of VBLANK interrupts (driver must alloc the right number of counters) */
 	spinlock_t vbl_lock;
-	struct list_head vbl_sigs;		/**< signal list to send on VBLANK */
-	struct list_head vbl_sigs2;	/**< signals to send on secondary VBLANK */
-	unsigned int vbl_pending;
-	spinlock_t tasklet_lock;	/**< For drm_locked_tasklet */
-	void (*locked_tasklet_func)(struct drm_device *dev);
+	struct list_head *vbl_sigs;	/**< signal list to send on VBLANK */
+	atomic_t vbl_signal_pending;    /* number of signals pending on all crtcs*/
+	atomic_t *vblank_refcount;      /* number of users of vblank interruptsper crtc */
+	u32 *last_vblank;               /* protected by dev->vbl_lock, used */
+					/* for wraparound handling */
+	int *vblank_enabled;            /* so we don't call enable more than
+					   once per disable */
+	int *vblank_inmodeset;          /* Display driver is setting mode */
+	u32 *last_vblank_wait;		/* Last vblank seqno waited per CRTC */
+	struct timer_list vblank_disable_timer;
+
+	u32 max_vblank_count;           /**< size of vblank counter register */
 
 	/*@} */
 	cycles_t ctx_start;
@@ -757,13 +933,17 @@ struct drm_device {
 	struct pci_controller *hose;
 #endif
 	struct drm_sg_mem *sg;	/**< Scatter gather memory */
+	int num_crtcs;                  /**< Number of CRTCs on this device */
 	void *dev_private;		/**< device private data */
+	void *mm_private;
+	struct address_space *dev_mapping;
 	struct drm_sigdata sigdata;	   /**< For block_all_signals */
 	sigset_t sigmask;
 
 	struct drm_driver *driver;
 	drm_local_map_t *agp_buffer_map;
 	unsigned int agp_buffer_token;
+	struct drm_minor *control;		/**< Control node for card */
 	struct drm_minor *primary;		/**< render type primary screen head */
 
 	/** \name Drawable information */
@@ -771,8 +951,31 @@ struct drm_device {
 	spinlock_t drw_lock;
 	struct idr drw_idr;
 	/*@} */
+
+        struct drm_mode_config mode_config;	/**< Current mode config */
+
+	/** \name GEM information */
+	/*@{ */
+	spinlock_t object_name_lock;
+	struct idr object_name_idr;
+	atomic_t object_count;
+	atomic_t object_memory;
+	atomic_t pin_count;
+	atomic_t pin_memory;
+	atomic_t gtt_count;
+	atomic_t gtt_memory;
+	uint32_t gtt_total;
+	uint32_t invalidate_domains;    /* domains pending invalidation */
+	uint32_t flush_domains;         /* domains pending flush */
+	/*@} */
+
 };
 
+static inline int drm_dev_to_irq(struct drm_device *dev)
+{
+	return dev->pdev->irq;
+}
+
 static __inline__ int drm_core_check_feature(struct drm_device *dev,
 					     int feature)
 {
@@ -853,6 +1056,8 @@ extern int drm_release(struct inode *inode, struct file *filp);
 
 				/* Mapping support (drm_vm.h) */
 extern int drm_mmap(struct file *filp, struct vm_area_struct *vma);
+extern int drm_mmap_locked(struct file *filp, struct vm_area_struct *vma);
+extern void drm_vm_open_locked(struct vm_area_struct *vma);
 extern unsigned long drm_core_get_map_ofs(struct drm_map * map);
 extern unsigned long drm_core_get_reg_ofs(struct drm_device *dev);
 extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait);
@@ -867,6 +1072,11 @@ extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area);
 extern DRM_AGP_MEM *drm_alloc_agp(struct drm_device *dev, int pages, u32 type);
 extern int drm_free_agp(DRM_AGP_MEM * handle, int pages);
 extern int drm_bind_agp(DRM_AGP_MEM * handle, unsigned int start);
+extern DRM_AGP_MEM *drm_agp_bind_pages(struct drm_device *dev,
+				       struct page **pages,
+				       unsigned long num_pages,
+				       uint32_t gtt_offset,
+				       uint32_t type);
 extern int drm_unbind_agp(DRM_AGP_MEM * handle);
 
 				/* Misc. IOCTL support (drm_ioctl.h) */
@@ -929,6 +1139,9 @@ extern int drm_getmagic(struct drm_device *dev, void *data,
 extern int drm_authmagic(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv);
 
+/* Cache management (drm_cache.c) */
+void drm_clflush_pages(struct page *pages[], unsigned long num_pages);
+
 				/* Locking IOCTL support (drm_lock.h) */
 extern int drm_lock(struct drm_device *dev, void *data,
 		    struct drm_file *file_priv);
@@ -985,16 +1198,26 @@ extern void drm_core_reclaim_buffers(struct drm_device *dev,
 extern int drm_control(struct drm_device *dev, void *data,
 		       struct drm_file *file_priv);
 extern irqreturn_t drm_irq_handler(DRM_IRQ_ARGS);
+extern int drm_irq_install(struct drm_device *dev);
 extern int drm_irq_uninstall(struct drm_device *dev);
 extern void drm_driver_irq_preinstall(struct drm_device *dev);
 extern void drm_driver_irq_postinstall(struct drm_device *dev);
 extern void drm_driver_irq_uninstall(struct drm_device *dev);
 
+extern int drm_vblank_init(struct drm_device *dev, int num_crtcs);
 extern int drm_wait_vblank(struct drm_device *dev, void *data,
-			   struct drm_file *file_priv);
+			   struct drm_file *filp);
 extern int drm_vblank_wait(struct drm_device *dev, unsigned int *vbl_seq);
-extern void drm_vbl_send_signals(struct drm_device *dev);
-extern void drm_locked_tasklet(struct drm_device *dev, void(*func)(struct drm_device*));
+extern u32 drm_vblank_count(struct drm_device *dev, int crtc);
+extern void drm_handle_vblank(struct drm_device *dev, int crtc);
+extern int drm_vblank_get(struct drm_device *dev, int crtc);
+extern void drm_vblank_put(struct drm_device *dev, int crtc);
+extern void drm_vblank_cleanup(struct drm_device *dev);
+/* Modesetting support */
+extern void drm_vblank_pre_modeset(struct drm_device *dev, int crtc);
+extern void drm_vblank_post_modeset(struct drm_device *dev, int crtc);
+extern int drm_modeset_ctl(struct drm_device *dev, void *data,
+			   struct drm_file *file_priv);
 
 				/* AGP/GART support (drm_agpsupport.h) */
 extern struct drm_agp_head *drm_agp_init(struct drm_device *dev);
@@ -1026,8 +1249,16 @@ extern DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data *bridge, size
 extern int drm_agp_free_memory(DRM_AGP_MEM * handle);
 extern int drm_agp_bind_memory(DRM_AGP_MEM * handle, off_t start);
 extern int drm_agp_unbind_memory(DRM_AGP_MEM * handle);
+extern void drm_agp_chipset_flush(struct drm_device *dev);
 
 				/* Stub support (drm_stub.h) */
+extern int drm_setmaster_ioctl(struct drm_device *dev, void *data,
+			       struct drm_file *file_priv);
+extern int drm_dropmaster_ioctl(struct drm_device *dev, void *data,
+				struct drm_file *file_priv);
+struct drm_master *drm_master_create(struct drm_minor *minor);
+extern struct drm_master *drm_master_get(struct drm_master *master);
+extern void drm_master_put(struct drm_master **master);
 extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
 		       struct drm_driver *driver);
 extern int drm_put_dev(struct drm_device *dev);
@@ -1070,7 +1301,11 @@ struct drm_sysfs_class;
 extern struct class *drm_sysfs_create(struct module *owner, char *name);
 extern void drm_sysfs_destroy(void);
 extern int drm_sysfs_device_add(struct drm_minor *minor);
+extern void drm_sysfs_hotplug_event(struct drm_device *dev);
 extern void drm_sysfs_device_remove(struct drm_minor *minor);
+extern char *drm_get_connector_status_name(enum drm_connector_status status);
+extern int drm_sysfs_connector_add(struct drm_connector *connector);
+extern void drm_sysfs_connector_remove(struct drm_connector *connector);
 
 /*
  * Basic memory manager support (drm_mm.c)
@@ -1088,6 +1323,68 @@ extern unsigned long drm_mm_tail_space(struct drm_mm *mm);
 extern int drm_mm_remove_space_from_tail(struct drm_mm *mm, unsigned long size);
 extern int drm_mm_add_space_to_tail(struct drm_mm *mm, unsigned long size);
 
+/* Graphics Execution Manager library functions (drm_gem.c) */
+int drm_gem_init(struct drm_device *dev);
+void drm_gem_destroy(struct drm_device *dev);
+void drm_gem_object_free(struct kref *kref);
+struct drm_gem_object *drm_gem_object_alloc(struct drm_device *dev,
+					    size_t size);
+void drm_gem_object_handle_free(struct kref *kref);
+int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
+
+static inline void
+drm_gem_object_reference(struct drm_gem_object *obj)
+{
+	kref_get(&obj->refcount);
+}
+
+static inline void
+drm_gem_object_unreference(struct drm_gem_object *obj)
+{
+	if (obj == NULL)
+		return;
+
+	kref_put(&obj->refcount, drm_gem_object_free);
+}
+
+int drm_gem_handle_create(struct drm_file *file_priv,
+			  struct drm_gem_object *obj,
+			  int *handlep);
+
+static inline void
+drm_gem_object_handle_reference(struct drm_gem_object *obj)
+{
+	drm_gem_object_reference(obj);
+	kref_get(&obj->handlecount);
+}
+
+static inline void
+drm_gem_object_handle_unreference(struct drm_gem_object *obj)
+{
+	if (obj == NULL)
+		return;
+
+	/*
+	 * Must bump handle count first as this may be the last
+	 * ref, in which case the object would disappear before we
+	 * checked for a name
+	 */
+	kref_put(&obj->handlecount, drm_gem_object_handle_free);
+	drm_gem_object_unreference(obj);
+}
+
+struct drm_gem_object *drm_gem_object_lookup(struct drm_device *dev,
+					     struct drm_file *filp,
+					     int handle);
+int drm_gem_close_ioctl(struct drm_device *dev, void *data,
+			struct drm_file *file_priv);
+int drm_gem_flink_ioctl(struct drm_device *dev, void *data,
+			struct drm_file *file_priv);
+int drm_gem_open_ioctl(struct drm_device *dev, void *data,
+		       struct drm_file *file_priv);
+void drm_gem_open(struct drm_device *dev, struct drm_file *file_private);
+void drm_gem_release(struct drm_device *dev, struct drm_file *file_private);
+
 extern void drm_core_ioremap(struct drm_map *map, struct drm_device *dev);
 extern void drm_core_ioremap_wc(struct drm_map *map, struct drm_device *dev);
 extern void drm_core_ioremapfree(struct drm_map *map, struct drm_device *dev);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
new file mode 100644
index 000000000000..0acb07f31fa4
--- /dev/null
+++ b/include/drm/drm_crtc.h
@@ -0,0 +1,733 @@
+/*
+ * Copyright © 2006 Keith Packard
+ * Copyright © 2007-2008 Dave Airlie
+ * Copyright © 2007-2008 Intel Corporation
+ *   Jesse Barnes <jesse.barnes@intel.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __DRM_CRTC_H__
+#define __DRM_CRTC_H__
+
+#include <linux/i2c.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/idr.h>
+
+#include <linux/fb.h>
+
+struct drm_device;
+struct drm_mode_set;
+struct drm_framebuffer;
+
+
+#define DRM_MODE_OBJECT_CRTC 0xcccccccc
+#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
+#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0
+#define DRM_MODE_OBJECT_MODE 0xdededede
+#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
+#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
+#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
+
+struct drm_mode_object {
+	uint32_t id;
+	uint32_t type;
+};
+
+/*
+ * Note on terminology:  here, for brevity and convenience, we refer to connector
+ * control chips as 'CRTCs'.  They can control any type of connector, VGA, LVDS,
+ * DVI, etc.  And 'screen' refers to the whole of the visible display, which
+ * may span multiple monitors (and therefore multiple CRTC and connector
+ * structures).
+ */
+
+enum drm_mode_status {
+    MODE_OK	= 0,	/* Mode OK */
+    MODE_HSYNC,		/* hsync out of range */
+    MODE_VSYNC,		/* vsync out of range */
+    MODE_H_ILLEGAL,	/* mode has illegal horizontal timings */
+    MODE_V_ILLEGAL,	/* mode has illegal horizontal timings */
+    MODE_BAD_WIDTH,	/* requires an unsupported linepitch */
+    MODE_NOMODE,	/* no mode with a maching name */
+    MODE_NO_INTERLACE,	/* interlaced mode not supported */
+    MODE_NO_DBLESCAN,	/* doublescan mode not supported */
+    MODE_NO_VSCAN,	/* multiscan mode not supported */
+    MODE_MEM,		/* insufficient video memory */
+    MODE_VIRTUAL_X,	/* mode width too large for specified virtual size */
+    MODE_VIRTUAL_Y,	/* mode height too large for specified virtual size */
+    MODE_MEM_VIRT,	/* insufficient video memory given virtual size */
+    MODE_NOCLOCK,	/* no fixed clock available */
+    MODE_CLOCK_HIGH,	/* clock required is too high */
+    MODE_CLOCK_LOW,	/* clock required is too low */
+    MODE_CLOCK_RANGE,	/* clock/mode isn't in a ClockRange */
+    MODE_BAD_HVALUE,	/* horizontal timing was out of range */
+    MODE_BAD_VVALUE,	/* vertical timing was out of range */
+    MODE_BAD_VSCAN,	/* VScan value out of range */
+    MODE_HSYNC_NARROW,	/* horizontal sync too narrow */
+    MODE_HSYNC_WIDE,	/* horizontal sync too wide */
+    MODE_HBLANK_NARROW,	/* horizontal blanking too narrow */
+    MODE_HBLANK_WIDE,	/* horizontal blanking too wide */
+    MODE_VSYNC_NARROW,	/* vertical sync too narrow */
+    MODE_VSYNC_WIDE,	/* vertical sync too wide */
+    MODE_VBLANK_NARROW,	/* vertical blanking too narrow */
+    MODE_VBLANK_WIDE,	/* vertical blanking too wide */
+    MODE_PANEL,         /* exceeds panel dimensions */
+    MODE_INTERLACE_WIDTH, /* width too large for interlaced mode */
+    MODE_ONE_WIDTH,     /* only one width is supported */
+    MODE_ONE_HEIGHT,    /* only one height is supported */
+    MODE_ONE_SIZE,      /* only one resolution is supported */
+    MODE_NO_REDUCED,    /* monitor doesn't accept reduced blanking */
+    MODE_UNVERIFIED = -3, /* mode needs to reverified */
+    MODE_BAD = -2,	/* unspecified reason */
+    MODE_ERROR	= -1	/* error condition */
+};
+
+#define DRM_MODE_TYPE_CLOCK_CRTC_C (DRM_MODE_TYPE_CLOCK_C | \
+				    DRM_MODE_TYPE_CRTC_C)
+
+#define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f) \
+	.name = nm, .status = 0, .type = (t), .clock = (c), \
+	.hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \
+	.htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \
+	.vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \
+	.vscan = (vs), .flags = (f), .vrefresh = 0
+
+#define CRTC_INTERLACE_HALVE_V 0x1 /* halve V values for interlacing */
+
+struct drm_display_mode {
+	/* Header */
+	struct list_head head;
+	struct drm_mode_object base;
+
+	char name[DRM_DISPLAY_MODE_LEN];
+
+	int connector_count;
+	enum drm_mode_status status;
+	int type;
+
+	/* Proposed mode values */
+	int clock;
+	int hdisplay;
+	int hsync_start;
+	int hsync_end;
+	int htotal;
+	int hskew;
+	int vdisplay;
+	int vsync_start;
+	int vsync_end;
+	int vtotal;
+	int vscan;
+	unsigned int flags;
+
+	/* Addressable image size (may be 0 for projectors, etc.) */
+	int width_mm;
+	int height_mm;
+
+	/* Actual mode we give to hw */
+	int clock_index;
+	int synth_clock;
+	int crtc_hdisplay;
+	int crtc_hblank_start;
+	int crtc_hblank_end;
+	int crtc_hsync_start;
+	int crtc_hsync_end;
+	int crtc_htotal;
+	int crtc_hskew;
+	int crtc_vdisplay;
+	int crtc_vblank_start;
+	int crtc_vblank_end;
+	int crtc_vsync_start;
+	int crtc_vsync_end;
+	int crtc_vtotal;
+	int crtc_hadjusted;
+	int crtc_vadjusted;
+
+	/* Driver private mode info */
+	int private_size;
+	int *private;
+	int private_flags;
+
+	int vrefresh;
+	float hsync;
+};
+
+enum drm_connector_status {
+	connector_status_connected = 1,
+	connector_status_disconnected = 2,
+	connector_status_unknown = 3,
+};
+
+enum subpixel_order {
+	SubPixelUnknown = 0,
+	SubPixelHorizontalRGB,
+	SubPixelHorizontalBGR,
+	SubPixelVerticalRGB,
+	SubPixelVerticalBGR,
+	SubPixelNone,
+};
+
+
+/*
+ * Describes a given display (e.g. CRT or flat panel) and its limitations.
+ */
+struct drm_display_info {
+	char name[DRM_DISPLAY_INFO_LEN];
+	/* Input info */
+	bool serration_vsync;
+	bool sync_on_green;
+	bool composite_sync;
+	bool separate_syncs;
+	bool blank_to_black;
+	unsigned char video_level;
+	bool digital;
+	/* Physical size */
+        unsigned int width_mm;
+	unsigned int height_mm;
+
+	/* Display parameters */
+	unsigned char gamma; /* FIXME: storage format */
+	bool gtf_supported;
+	bool standard_color;
+	enum {
+		monochrome = 0,
+		rgb,
+		other,
+		unknown,
+	} display_type;
+	bool active_off_supported;
+	bool suspend_supported;
+	bool standby_supported;
+
+	/* Color info FIXME: storage format */
+	unsigned short redx, redy;
+	unsigned short greenx, greeny;
+	unsigned short bluex, bluey;
+	unsigned short whitex, whitey;
+
+	/* Clock limits FIXME: storage format */
+	unsigned int min_vfreq, max_vfreq;
+	unsigned int min_hfreq, max_hfreq;
+	unsigned int pixel_clock;
+
+	/* White point indices FIXME: storage format */
+	unsigned int wpx1, wpy1;
+	unsigned int wpgamma1;
+	unsigned int wpx2, wpy2;
+	unsigned int wpgamma2;
+
+	enum subpixel_order subpixel_order;
+
+	char *raw_edid; /* if any */
+};
+
+struct drm_framebuffer_funcs {
+	void (*destroy)(struct drm_framebuffer *framebuffer);
+	int (*create_handle)(struct drm_framebuffer *fb,
+			     struct drm_file *file_priv,
+			     unsigned int *handle);
+};
+
+struct drm_framebuffer {
+	struct drm_device *dev;
+	struct list_head head;
+	struct drm_mode_object base;
+	const struct drm_framebuffer_funcs *funcs;
+	unsigned int pitch;
+	unsigned int width;
+	unsigned int height;
+	/* depth can be 15 or 16 */
+	unsigned int depth;
+	int bits_per_pixel;
+	int flags;
+	void *fbdev;
+	u32 pseudo_palette[17];
+	struct list_head filp_head;
+};
+
+struct drm_property_blob {
+	struct drm_mode_object base;
+	struct list_head head;
+	unsigned int length;
+	void *data;
+};
+
+struct drm_property_enum {
+	uint64_t value;
+	struct list_head head;
+	char name[DRM_PROP_NAME_LEN];
+};
+
+struct drm_property {
+	struct list_head head;
+	struct drm_mode_object base;
+	uint32_t flags;
+	char name[DRM_PROP_NAME_LEN];
+	uint32_t num_values;
+	uint64_t *values;
+
+	struct list_head enum_blob_list;
+};
+
+struct drm_crtc;
+struct drm_connector;
+struct drm_encoder;
+
+/**
+ * drm_crtc_funcs - control CRTCs for a given device
+ * @dpms: control display power levels
+ * @save: save CRTC state
+ * @resore: restore CRTC state
+ * @lock: lock the CRTC
+ * @unlock: unlock the CRTC
+ * @shadow_allocate: allocate shadow pixmap
+ * @shadow_create: create shadow pixmap for rotation support
+ * @shadow_destroy: free shadow pixmap
+ * @mode_fixup: fixup proposed mode
+ * @mode_set: set the desired mode on the CRTC
+ * @gamma_set: specify color ramp for CRTC
+ * @destroy: deinit and free object.
+ *
+ * The drm_crtc_funcs structure is the central CRTC management structure
+ * in the DRM.  Each CRTC controls one or more connectors (note that the name
+ * CRTC is simply historical, a CRTC may control LVDS, VGA, DVI, TV out, etc.
+ * connectors, not just CRTs).
+ *
+ * Each driver is responsible for filling out this structure at startup time,
+ * in addition to providing other modesetting features, like i2c and DDC
+ * bus accessors.
+ */
+struct drm_crtc_funcs {
+	/* Save CRTC state */
+	void (*save)(struct drm_crtc *crtc); /* suspend? */
+	/* Restore CRTC state */
+	void (*restore)(struct drm_crtc *crtc); /* resume? */
+
+	/* cursor controls */
+	int (*cursor_set)(struct drm_crtc *crtc, struct drm_file *file_priv,
+			  uint32_t handle, uint32_t width, uint32_t height);
+	int (*cursor_move)(struct drm_crtc *crtc, int x, int y);
+
+	/* Set gamma on the CRTC */
+	void (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
+			  uint32_t size);
+	/* Object destroy routine */
+	void (*destroy)(struct drm_crtc *crtc);
+
+	int (*set_config)(struct drm_mode_set *set);
+};
+
+/**
+ * drm_crtc - central CRTC control structure
+ * @enabled: is this CRTC enabled?
+ * @x: x position on screen
+ * @y: y position on screen
+ * @desired_mode: new desired mode
+ * @desired_x: desired x for desired_mode
+ * @desired_y: desired y for desired_mode
+ * @funcs: CRTC control functions
+ *
+ * Each CRTC may have one or more connectors associated with it.  This structure
+ * allows the CRTC to be controlled.
+ */
+struct drm_crtc {
+	struct drm_device *dev;
+	struct list_head head;
+
+	struct drm_mode_object base;
+
+	/* framebuffer the connector is currently bound to */
+	struct drm_framebuffer *fb;
+
+	bool enabled;
+
+	struct drm_display_mode mode;
+
+	int x, y;
+	struct drm_display_mode *desired_mode;
+	int desired_x, desired_y;
+	const struct drm_crtc_funcs *funcs;
+
+	/* CRTC gamma size for reporting to userspace */
+	uint32_t gamma_size;
+	uint16_t *gamma_store;
+
+	/* if you are using the helper */
+	void *helper_private;
+};
+
+
+/**
+ * drm_connector_funcs - control connectors on a given device
+ * @dpms: set power state (see drm_crtc_funcs above)
+ * @save: save connector state
+ * @restore: restore connector state
+ * @mode_valid: is this mode valid on the given connector?
+ * @mode_fixup: try to fixup proposed mode for this connector
+ * @mode_set: set this mode
+ * @detect: is this connector active?
+ * @get_modes: get mode list for this connector
+ * @set_property: property for this connector may need update
+ * @destroy: make object go away
+ *
+ * Each CRTC may have one or more connectors attached to it.  The functions
+ * below allow the core DRM code to control connectors, enumerate available modes,
+ * etc.
+ */
+struct drm_connector_funcs {
+	void (*dpms)(struct drm_connector *connector, int mode);
+	void (*save)(struct drm_connector *connector);
+	void (*restore)(struct drm_connector *connector);
+	enum drm_connector_status (*detect)(struct drm_connector *connector);
+	void (*fill_modes)(struct drm_connector *connector, uint32_t max_width, uint32_t max_height);
+	int (*set_property)(struct drm_connector *connector, struct drm_property *property,
+			     uint64_t val);
+	void (*destroy)(struct drm_connector *connector);
+};
+
+struct drm_encoder_funcs {
+	void (*destroy)(struct drm_encoder *encoder);
+};
+
+#define DRM_CONNECTOR_MAX_UMODES 16
+#define DRM_CONNECTOR_MAX_PROPERTY 16
+#define DRM_CONNECTOR_LEN 32
+#define DRM_CONNECTOR_MAX_ENCODER 2
+
+/**
+ * drm_encoder - central DRM encoder structure
+ */
+struct drm_encoder {
+	struct drm_device *dev;
+	struct list_head head;
+
+	struct drm_mode_object base;
+	int encoder_type;
+	uint32_t possible_crtcs;
+	uint32_t possible_clones;
+
+	struct drm_crtc *crtc;
+	const struct drm_encoder_funcs *funcs;
+	void *helper_private;
+};
+
+/**
+ * drm_connector - central DRM connector control structure
+ * @crtc: CRTC this connector is currently connected to, NULL if none
+ * @interlace_allowed: can this connector handle interlaced modes?
+ * @doublescan_allowed: can this connector handle doublescan?
+ * @available_modes: modes available on this connector (from get_modes() + user)
+ * @initial_x: initial x position for this connector
+ * @initial_y: initial y position for this connector
+ * @status: connector connected?
+ * @funcs: connector control functions
+ *
+ * Each connector may be connected to one or more CRTCs, or may be clonable by
+ * another connector if they can share a CRTC.  Each connector also has a specific
+ * position in the broader display (referred to as a 'screen' though it could
+ * span multiple monitors).
+ */
+struct drm_connector {
+	struct drm_device *dev;
+	struct device kdev;
+	struct device_attribute *attr;
+	struct list_head head;
+
+	struct drm_mode_object base;
+
+	int connector_type;
+	int connector_type_id;
+	bool interlace_allowed;
+	bool doublescan_allowed;
+	struct list_head modes; /* list of modes on this connector */
+
+	int initial_x, initial_y;
+	enum drm_connector_status status;
+
+	/* these are modes added by probing with DDC or the BIOS */
+	struct list_head probed_modes;
+
+	struct drm_display_info display_info;
+	const struct drm_connector_funcs *funcs;
+
+	struct list_head user_modes;
+	struct drm_property_blob *edid_blob_ptr;
+	u32 property_ids[DRM_CONNECTOR_MAX_PROPERTY];
+	uint64_t property_values[DRM_CONNECTOR_MAX_PROPERTY];
+
+	void *helper_private;
+
+	uint32_t encoder_ids[DRM_CONNECTOR_MAX_ENCODER];
+	uint32_t force_encoder_id;
+	struct drm_encoder *encoder; /* currently active encoder */
+};
+
+/**
+ * struct drm_mode_set
+ *
+ * Represents a single crtc the connectors that it drives with what mode
+ * and from which framebuffer it scans out from.
+ *
+ * This is used to set modes.
+ */
+struct drm_mode_set {
+	struct list_head head;
+
+	struct drm_framebuffer *fb;
+	struct drm_crtc *crtc;
+	struct drm_display_mode *mode;
+
+	uint32_t x;
+	uint32_t y;
+
+	struct drm_connector **connectors;
+	size_t num_connectors;
+};
+
+/**
+ * struct drm_mode_config_funcs - configure CRTCs for a given screen layout
+ * @resize: adjust CRTCs as necessary for the proposed layout
+ *
+ * Currently only a resize hook is available.  DRM will call back into the
+ * driver with a new screen width and height.  If the driver can't support
+ * the proposed size, it can return false.  Otherwise it should adjust
+ * the CRTC<->connector mappings as needed and update its view of the screen.
+ */
+struct drm_mode_config_funcs {
+	struct drm_framebuffer *(*fb_create)(struct drm_device *dev, struct drm_file *file_priv, struct drm_mode_fb_cmd *mode_cmd);
+	int (*fb_changed)(struct drm_device *dev);
+};
+
+struct drm_mode_group {
+	uint32_t num_crtcs;
+	uint32_t num_encoders;
+	uint32_t num_connectors;
+
+	/* list of object IDs for this group */
+	uint32_t *id_list;
+};
+
+/**
+ * drm_mode_config - Mode configuration control structure
+ *
+ */
+struct drm_mode_config {
+	struct mutex mutex; /* protects configuration and IDR */
+	struct idr crtc_idr; /* use this idr for all IDs, fb, crtc, connector, modes - just makes life easier */
+	/* this is limited to one for now */
+	int num_fb;
+	struct list_head fb_list;
+	int num_connector;
+	struct list_head connector_list;
+	int num_encoder;
+	struct list_head encoder_list;
+
+	int num_crtc;
+	struct list_head crtc_list;
+
+	struct list_head property_list;
+
+	/* in-kernel framebuffers - hung of filp_head in drm_framebuffer */
+	struct list_head fb_kernel_list;
+
+	int min_width, min_height;
+	int max_width, max_height;
+	struct drm_mode_config_funcs *funcs;
+	unsigned long fb_base;
+
+	/* pointers to standard properties */
+	struct list_head property_blob_list;
+	struct drm_property *edid_property;
+	struct drm_property *dpms_property;
+
+	/* DVI-I properties */
+	struct drm_property *dvi_i_subconnector_property;
+	struct drm_property *dvi_i_select_subconnector_property;
+
+	/* TV properties */
+	struct drm_property *tv_subconnector_property;
+	struct drm_property *tv_select_subconnector_property;
+	struct drm_property *tv_mode_property;
+	struct drm_property *tv_left_margin_property;
+	struct drm_property *tv_right_margin_property;
+	struct drm_property *tv_top_margin_property;
+	struct drm_property *tv_bottom_margin_property;
+
+	/* Optional properties */
+	struct drm_property *scaling_mode_property;
+	struct drm_property *dithering_mode_property;
+};
+
+#define obj_to_crtc(x) container_of(x, struct drm_crtc, base)
+#define obj_to_connector(x) container_of(x, struct drm_connector, base)
+#define obj_to_encoder(x) container_of(x, struct drm_encoder, base)
+#define obj_to_mode(x) container_of(x, struct drm_display_mode, base)
+#define obj_to_fb(x) container_of(x, struct drm_framebuffer, base)
+#define obj_to_property(x) container_of(x, struct drm_property, base)
+#define obj_to_blob(x) container_of(x, struct drm_property_blob, base)
+
+
+extern void drm_crtc_init(struct drm_device *dev,
+			  struct drm_crtc *crtc,
+			  const struct drm_crtc_funcs *funcs);
+extern void drm_crtc_cleanup(struct drm_crtc *crtc);
+
+extern void drm_connector_init(struct drm_device *dev,
+			    struct drm_connector *connector,
+			    const struct drm_connector_funcs *funcs,
+			    int connector_type);
+
+extern void drm_connector_cleanup(struct drm_connector *connector);
+
+extern void drm_encoder_init(struct drm_device *dev,
+			     struct drm_encoder *encoder,
+			     const struct drm_encoder_funcs *funcs,
+			     int encoder_type);
+
+extern void drm_encoder_cleanup(struct drm_encoder *encoder);
+
+extern char *drm_get_connector_name(struct drm_connector *connector);
+extern char *drm_get_dpms_name(int val);
+extern char *drm_get_dvi_i_subconnector_name(int val);
+extern char *drm_get_dvi_i_select_name(int val);
+extern char *drm_get_tv_subconnector_name(int val);
+extern char *drm_get_tv_select_name(int val);
+extern void drm_fb_release(struct file *filp);
+extern int drm_mode_group_init_legacy_group(struct drm_device *dev, struct drm_mode_group *group);
+extern struct edid *drm_get_edid(struct drm_connector *connector,
+				 struct i2c_adapter *adapter);
+extern unsigned char *drm_do_probe_ddc_edid(struct i2c_adapter *adapter);
+extern int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid);
+extern void drm_mode_probed_add(struct drm_connector *connector, struct drm_display_mode *mode);
+extern void drm_mode_remove(struct drm_connector *connector, struct drm_display_mode *mode);
+extern struct drm_display_mode *drm_mode_duplicate(struct drm_device *dev,
+						   struct drm_display_mode *mode);
+extern void drm_mode_debug_printmodeline(struct drm_display_mode *mode);
+extern void drm_mode_config_init(struct drm_device *dev);
+extern void drm_mode_config_cleanup(struct drm_device *dev);
+extern void drm_mode_set_name(struct drm_display_mode *mode);
+extern bool drm_mode_equal(struct drm_display_mode *mode1, struct drm_display_mode *mode2);
+extern int drm_mode_width(struct drm_display_mode *mode);
+extern int drm_mode_height(struct drm_display_mode *mode);
+
+/* for us by fb module */
+extern int drm_mode_attachmode_crtc(struct drm_device *dev,
+				    struct drm_crtc *crtc,
+				    struct drm_display_mode *mode);
+extern int drm_mode_detachmode_crtc(struct drm_device *dev, struct drm_display_mode *mode);
+
+extern struct drm_display_mode *drm_mode_create(struct drm_device *dev);
+extern void drm_mode_destroy(struct drm_device *dev, struct drm_display_mode *mode);
+extern void drm_mode_list_concat(struct list_head *head,
+				 struct list_head *new);
+extern void drm_mode_validate_size(struct drm_device *dev,
+				   struct list_head *mode_list,
+				   int maxX, int maxY, int maxPitch);
+extern void drm_mode_prune_invalid(struct drm_device *dev,
+				   struct list_head *mode_list, bool verbose);
+extern void drm_mode_sort(struct list_head *mode_list);
+extern int drm_mode_vrefresh(struct drm_display_mode *mode);
+extern void drm_mode_set_crtcinfo(struct drm_display_mode *p,
+				  int adjust_flags);
+extern void drm_mode_connector_list_update(struct drm_connector *connector);
+extern int drm_mode_connector_update_edid_property(struct drm_connector *connector,
+						struct edid *edid);
+extern int drm_connector_property_set_value(struct drm_connector *connector,
+					 struct drm_property *property,
+					 uint64_t value);
+extern int drm_connector_property_get_value(struct drm_connector *connector,
+					 struct drm_property *property,
+					 uint64_t *value);
+extern struct drm_display_mode *drm_crtc_mode_create(struct drm_device *dev);
+extern void drm_framebuffer_set_object(struct drm_device *dev,
+				       unsigned long handle);
+extern int drm_framebuffer_init(struct drm_device *dev,
+				struct drm_framebuffer *fb,
+				const struct drm_framebuffer_funcs *funcs);
+extern void drm_framebuffer_cleanup(struct drm_framebuffer *fb);
+extern int drmfb_probe(struct drm_device *dev, struct drm_crtc *crtc);
+extern int drmfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
+extern void drm_crtc_probe_connector_modes(struct drm_device *dev, int maxX, int maxY);
+extern bool drm_crtc_in_use(struct drm_crtc *crtc);
+
+extern int drm_connector_attach_property(struct drm_connector *connector,
+				      struct drm_property *property, uint64_t init_val);
+extern struct drm_property *drm_property_create(struct drm_device *dev, int flags,
+						const char *name, int num_values);
+extern void drm_property_destroy(struct drm_device *dev, struct drm_property *property);
+extern int drm_property_add_enum(struct drm_property *property, int index,
+				 uint64_t value, const char *name);
+extern int drm_mode_create_dvi_i_properties(struct drm_device *dev);
+extern int drm_mode_create_tv_properties(struct drm_device *dev, int num_formats,
+				     char *formats[]);
+extern int drm_mode_create_scaling_mode_property(struct drm_device *dev);
+extern int drm_mode_create_dithering_property(struct drm_device *dev);
+extern char *drm_get_encoder_name(struct drm_encoder *encoder);
+
+extern int drm_mode_connector_attach_encoder(struct drm_connector *connector,
+					     struct drm_encoder *encoder);
+extern void drm_mode_connector_detach_encoder(struct drm_connector *connector,
+					   struct drm_encoder *encoder);
+extern bool drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc,
+					 int gamma_size);
+extern void *drm_mode_object_find(struct drm_device *dev, uint32_t id, uint32_t type);
+/* IOCTLs */
+extern int drm_mode_getresources(struct drm_device *dev,
+				 void *data, struct drm_file *file_priv);
+
+extern int drm_mode_getcrtc(struct drm_device *dev,
+			    void *data, struct drm_file *file_priv);
+extern int drm_mode_getconnector(struct drm_device *dev,
+			      void *data, struct drm_file *file_priv);
+extern int drm_mode_setcrtc(struct drm_device *dev,
+			    void *data, struct drm_file *file_priv);
+extern int drm_mode_cursor_ioctl(struct drm_device *dev,
+				void *data, struct drm_file *file_priv);
+extern int drm_mode_addfb(struct drm_device *dev,
+			  void *data, struct drm_file *file_priv);
+extern int drm_mode_rmfb(struct drm_device *dev,
+			 void *data, struct drm_file *file_priv);
+extern int drm_mode_getfb(struct drm_device *dev,
+			  void *data, struct drm_file *file_priv);
+extern int drm_mode_addmode_ioctl(struct drm_device *dev,
+				  void *data, struct drm_file *file_priv);
+extern int drm_mode_rmmode_ioctl(struct drm_device *dev,
+				 void *data, struct drm_file *file_priv);
+extern int drm_mode_attachmode_ioctl(struct drm_device *dev,
+				     void *data, struct drm_file *file_priv);
+extern int drm_mode_detachmode_ioctl(struct drm_device *dev,
+				     void *data, struct drm_file *file_priv);
+
+extern int drm_mode_getproperty_ioctl(struct drm_device *dev,
+				      void *data, struct drm_file *file_priv);
+extern int drm_mode_getblob_ioctl(struct drm_device *dev,
+				  void *data, struct drm_file *file_priv);
+extern int drm_mode_connector_property_set_ioctl(struct drm_device *dev,
+					      void *data, struct drm_file *file_priv);
+extern int drm_mode_hotplug_ioctl(struct drm_device *dev,
+				  void *data, struct drm_file *file_priv);
+extern int drm_mode_replacefb(struct drm_device *dev,
+			      void *data, struct drm_file *file_priv);
+extern int drm_mode_getencoder(struct drm_device *dev,
+			       void *data, struct drm_file *file_priv);
+extern int drm_mode_gamma_get_ioctl(struct drm_device *dev,
+				    void *data, struct drm_file *file_priv);
+extern int drm_mode_gamma_set_ioctl(struct drm_device *dev,
+				    void *data, struct drm_file *file_priv);
+#endif /* __DRM_CRTC_H__ */
diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h
new file mode 100644
index 000000000000..4bc04cf460a7
--- /dev/null
+++ b/include/drm/drm_crtc_helper.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright © 2006 Keith Packard
+ * Copyright © 2007-2008 Dave Airlie
+ * Copyright © 2007-2008 Intel Corporation
+ *   Jesse Barnes <jesse.barnes@intel.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * The DRM mode setting helper functions are common code for drivers to use if
+ * they wish.  Drivers are not forced to use this code in their
+ * implementations but it would be useful if they code they do use at least
+ * provides a consistent interface and operation to userspace
+ */
+
+#ifndef __DRM_CRTC_HELPER_H__
+#define __DRM_CRTC_HELPER_H__
+
+#include <linux/i2c.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/idr.h>
+
+#include <linux/fb.h>
+
+struct drm_crtc_helper_funcs {
+	/*
+	 * Control power levels on the CRTC.  If the mode passed in is
+	 * unsupported, the provider must use the next lowest power level.
+	 */
+	void (*dpms)(struct drm_crtc *crtc, int mode);
+	void (*prepare)(struct drm_crtc *crtc);
+	void (*commit)(struct drm_crtc *crtc);
+
+	/* Provider can fixup or change mode timings before modeset occurs */
+	bool (*mode_fixup)(struct drm_crtc *crtc,
+			   struct drm_display_mode *mode,
+			   struct drm_display_mode *adjusted_mode);
+	/* Actually set the mode */
+	void (*mode_set)(struct drm_crtc *crtc, struct drm_display_mode *mode,
+			 struct drm_display_mode *adjusted_mode, int x, int y,
+			 struct drm_framebuffer *old_fb);
+
+	/* Move the crtc on the current fb to the given position *optional* */
+	void (*mode_set_base)(struct drm_crtc *crtc, int x, int y,
+			      struct drm_framebuffer *old_fb);
+};
+
+struct drm_encoder_helper_funcs {
+	void (*dpms)(struct drm_encoder *encoder, int mode);
+	void (*save)(struct drm_encoder *encoder);
+	void (*restore)(struct drm_encoder *encoder);
+
+	bool (*mode_fixup)(struct drm_encoder *encoder,
+			   struct drm_display_mode *mode,
+			   struct drm_display_mode *adjusted_mode);
+	void (*prepare)(struct drm_encoder *encoder);
+	void (*commit)(struct drm_encoder *encoder);
+	void (*mode_set)(struct drm_encoder *encoder,
+			 struct drm_display_mode *mode,
+			 struct drm_display_mode *adjusted_mode);
+	/* detect for DAC style encoders */
+	enum drm_connector_status (*detect)(struct drm_encoder *encoder,
+					    struct drm_connector *connector);
+};
+
+struct drm_connector_helper_funcs {
+	int (*get_modes)(struct drm_connector *connector);
+	int (*mode_valid)(struct drm_connector *connector,
+			  struct drm_display_mode *mode);
+	struct drm_encoder *(*best_encoder)(struct drm_connector *connector);
+};
+
+extern void drm_helper_probe_single_connector_modes(struct drm_connector *connector, uint32_t maxX, uint32_t maxY);
+extern void drm_helper_disable_unused_functions(struct drm_device *dev);
+extern int drm_helper_hotplug_stage_two(struct drm_device *dev);
+extern bool drm_helper_initial_config(struct drm_device *dev, bool can_grow);
+extern int drm_crtc_helper_set_config(struct drm_mode_set *set);
+extern bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
+				     struct drm_display_mode *mode,
+				     int x, int y,
+				     struct drm_framebuffer *old_fb);
+extern bool drm_helper_crtc_in_use(struct drm_crtc *crtc);
+
+extern int drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb,
+					  struct drm_mode_fb_cmd *mode_cmd);
+
+static inline void drm_crtc_helper_add(struct drm_crtc *crtc,
+				       const struct drm_crtc_helper_funcs *funcs)
+{
+	crtc->helper_private = (void *)funcs;
+}
+
+static inline void drm_encoder_helper_add(struct drm_encoder *encoder,
+					  const struct drm_encoder_helper_funcs *funcs)
+{
+	encoder->helper_private = (void *)funcs;
+}
+
+static inline void drm_connector_helper_add(struct drm_connector *connector,
+					    const struct drm_connector_helper_funcs *funcs)
+{
+	connector->helper_private = (void *)funcs;
+}
+
+extern int drm_helper_resume_force_mode(struct drm_device *dev);
+#endif
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
new file mode 100644
index 000000000000..c707c15f5164
--- /dev/null
+++ b/include/drm/drm_edid.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright © 2007-2008 Intel Corporation
+ *   Jesse Barnes <jesse.barnes@intel.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __DRM_EDID_H__
+#define __DRM_EDID_H__
+
+#include <linux/types.h>
+
+#define EDID_LENGTH 128
+#define DDC_ADDR 0x50
+
+#ifdef BIG_ENDIAN
+#error "EDID structure is little endian, need big endian versions"
+#else
+
+struct est_timings {
+	u8 t1;
+	u8 t2;
+	u8 mfg_rsvd;
+} __attribute__((packed));
+
+struct std_timing {
+	u8 hsize; /* need to multiply by 8 then add 248 */
+	u8 vfreq:6; /* need to add 60 */
+	u8 aspect_ratio:2; /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
+} __attribute__((packed));
+
+/* If detailed data is pixel timing */
+struct detailed_pixel_timing {
+	u8 hactive_lo;
+	u8 hblank_lo;
+	u8 hblank_hi:4;
+	u8 hactive_hi:4;
+	u8 vactive_lo;
+	u8 vblank_lo;
+	u8 vblank_hi:4;
+	u8 vactive_hi:4;
+	u8 hsync_offset_lo;
+	u8 hsync_pulse_width_lo;
+	u8 vsync_pulse_width_lo:4;
+	u8 vsync_offset_lo:4;
+	u8 hsync_pulse_width_hi:2;
+	u8 hsync_offset_hi:2;
+	u8 vsync_pulse_width_hi:2;
+	u8 vsync_offset_hi:2;
+	u8 width_mm_lo;
+	u8 height_mm_lo;
+	u8 height_mm_hi:4;
+	u8 width_mm_hi:4;
+	u8 hborder;
+	u8 vborder;
+	u8 unknown0:1;
+	u8 vsync_positive:1;
+	u8 hsync_positive:1;
+	u8 separate_sync:2;
+	u8 stereo:1;
+	u8 unknown6:1;
+	u8 interlaced:1;
+} __attribute__((packed));
+
+/* If it's not pixel timing, it'll be one of the below */
+struct detailed_data_string {
+	u8 str[13];
+} __attribute__((packed));
+
+struct detailed_data_monitor_range {
+	u8 min_vfreq;
+	u8 max_vfreq;
+	u8 min_hfreq_khz;
+	u8 max_hfreq_khz;
+	u8 pixel_clock_mhz; /* need to multiply by 10 */
+	u16 sec_gtf_toggle; /* A000=use above, 20=use below */ /* FIXME: byte order */
+	u8 hfreq_start_khz; /* need to multiply by 2 */
+	u8 c; /* need to divide by 2 */
+	u16 m; /* FIXME: byte order */
+	u8 k;
+	u8 j; /* need to divide by 2 */
+} __attribute__((packed));
+
+struct detailed_data_wpindex {
+	u8 white_y_lo:2;
+	u8 white_x_lo:2;
+	u8 pad:4;
+	u8 white_x_hi;
+	u8 white_y_hi;
+	u8 gamma; /* need to divide by 100 then add 1 */
+} __attribute__((packed));
+
+struct detailed_data_color_point {
+	u8 windex1;
+	u8 wpindex1[3];
+	u8 windex2;
+	u8 wpindex2[3];
+} __attribute__((packed));
+
+struct detailed_non_pixel {
+	u8 pad1;
+	u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
+		    fb=color point data, fa=standard timing data,
+		    f9=undefined, f8=mfg. reserved */
+	u8 pad2;
+	union {
+		struct detailed_data_string str;
+		struct detailed_data_monitor_range range;
+		struct detailed_data_wpindex color;
+		struct std_timing timings[5];
+	} data;
+} __attribute__((packed));
+
+#define EDID_DETAIL_STD_MODES 0xfa
+#define EDID_DETAIL_MONITOR_CPDATA 0xfb
+#define EDID_DETAIL_MONITOR_NAME 0xfc
+#define EDID_DETAIL_MONITOR_RANGE 0xfd
+#define EDID_DETAIL_MONITOR_STRING 0xfe
+#define EDID_DETAIL_MONITOR_SERIAL 0xff
+
+struct detailed_timing {
+	u16 pixel_clock; /* need to multiply by 10 KHz */ /* FIXME: byte order */
+	union {
+		struct detailed_pixel_timing pixel_data;
+		struct detailed_non_pixel other_data;
+	} data;
+} __attribute__((packed));
+
+struct edid {
+	u8 header[8];
+	/* Vendor & product info */
+	u8 mfg_id[2];
+	u8 prod_code[2];
+	u32 serial; /* FIXME: byte order */
+	u8 mfg_week;
+	u8 mfg_year;
+	/* EDID version */
+	u8 version;
+	u8 revision;
+	/* Display info: */
+	/*   input definition */
+	u8 serration_vsync:1;
+	u8 sync_on_green:1;
+	u8 composite_sync:1;
+	u8 separate_syncs:1;
+	u8 blank_to_black:1;
+	u8 video_level:2;
+	u8 digital:1; /* bits below must be zero if set */
+	u8 width_cm;
+	u8 height_cm;
+	u8 gamma;
+	/*   feature support */
+	u8 default_gtf:1;
+	u8 preferred_timing:1;
+	u8 standard_color:1;
+	u8 display_type:2; /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
+	u8 pm_active_off:1;
+	u8 pm_suspend:1;
+	u8 pm_standby:1;
+	/* Color characteristics */
+	u8 red_green_lo;
+	u8 black_white_lo;
+	u8 red_x;
+	u8 red_y;
+	u8 green_x;
+	u8 green_y;
+	u8 blue_x;
+	u8 blue_y;
+	u8 white_x;
+	u8 white_y;
+	/* Est. timings and mfg rsvd timings*/
+	struct est_timings established_timings;
+	/* Standard timings 1-8*/
+	struct std_timing standard_timings[8];
+	/* Detailing timings 1-4 */
+	struct detailed_timing detailed_timings[4];
+	/* Number of 128 byte ext. blocks */
+	u8 extensions;
+	/* Checksum */
+	u8 checksum;
+} __attribute__((packed));
+
+#endif /* little endian structs */
+
+#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
+
+#endif /* __DRM_EDID_H__ */
diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h
new file mode 100644
index 000000000000..601d2bd839f6
--- /dev/null
+++ b/include/drm/drm_mode.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
+ * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
+ * Copyright (c) 2008 Red Hat Inc.
+ * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
+ * Copyright (c) 2007-2008 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef _DRM_MODE_H
+#define _DRM_MODE_H
+
+#if !defined(__KERNEL__) && !defined(_KERNEL)
+#include <stdint.h>
+#else
+#include <linux/kernel.h>
+#endif
+
+#define DRM_DISPLAY_INFO_LEN	32
+#define DRM_CONNECTOR_NAME_LEN	32
+#define DRM_DISPLAY_MODE_LEN	32
+#define DRM_PROP_NAME_LEN	32
+
+#define DRM_MODE_TYPE_BUILTIN	(1<<0)
+#define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN)
+#define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN)
+#define DRM_MODE_TYPE_PREFERRED	(1<<3)
+#define DRM_MODE_TYPE_DEFAULT	(1<<4)
+#define DRM_MODE_TYPE_USERDEF	(1<<5)
+#define DRM_MODE_TYPE_DRIVER	(1<<6)
+
+/* Video mode flags */
+/* bit compatible with the xorg definitions. */
+#define DRM_MODE_FLAG_PHSYNC	(1<<0)
+#define DRM_MODE_FLAG_NHSYNC	(1<<1)
+#define DRM_MODE_FLAG_PVSYNC	(1<<2)
+#define DRM_MODE_FLAG_NVSYNC	(1<<3)
+#define DRM_MODE_FLAG_INTERLACE	(1<<4)
+#define DRM_MODE_FLAG_DBLSCAN	(1<<5)
+#define DRM_MODE_FLAG_CSYNC	(1<<6)
+#define DRM_MODE_FLAG_PCSYNC	(1<<7)
+#define DRM_MODE_FLAG_NCSYNC	(1<<8)
+#define DRM_MODE_FLAG_HSKEW	(1<<9) /* hskew provided */
+#define DRM_MODE_FLAG_BCAST	(1<<10)
+#define DRM_MODE_FLAG_PIXMUX	(1<<11)
+#define DRM_MODE_FLAG_DBLCLK	(1<<12)
+#define DRM_MODE_FLAG_CLKDIV2	(1<<13)
+
+/* DPMS flags */
+/* bit compatible with the xorg definitions. */
+#define DRM_MODE_DPMS_ON	0
+#define DRM_MODE_DPMS_STANDBY	1
+#define DRM_MODE_DPMS_SUSPEND	2
+#define DRM_MODE_DPMS_OFF	3
+
+/* Scaling mode options */
+#define DRM_MODE_SCALE_NON_GPU		0
+#define DRM_MODE_SCALE_FULLSCREEN	1
+#define DRM_MODE_SCALE_NO_SCALE		2
+#define DRM_MODE_SCALE_ASPECT		3
+
+/* Dithering mode options */
+#define DRM_MODE_DITHERING_OFF	0
+#define DRM_MODE_DITHERING_ON	1
+
+struct drm_mode_modeinfo {
+	uint32_t clock;
+	uint16_t hdisplay, hsync_start, hsync_end, htotal, hskew;
+	uint16_t vdisplay, vsync_start, vsync_end, vtotal, vscan;
+
+	uint32_t vrefresh; /* vertical refresh * 1000 */
+
+	uint32_t flags;
+	uint32_t type;
+	char name[DRM_DISPLAY_MODE_LEN];
+};
+
+struct drm_mode_card_res {
+	uint64_t fb_id_ptr;
+	uint64_t crtc_id_ptr;
+	uint64_t connector_id_ptr;
+	uint64_t encoder_id_ptr;
+	uint32_t count_fbs;
+	uint32_t count_crtcs;
+	uint32_t count_connectors;
+	uint32_t count_encoders;
+	uint32_t min_width, max_width;
+	uint32_t min_height, max_height;
+};
+
+struct drm_mode_crtc {
+	uint64_t set_connectors_ptr;
+	uint32_t count_connectors;
+
+	uint32_t crtc_id; /**< Id */
+	uint32_t fb_id; /**< Id of framebuffer */
+
+	uint32_t x, y; /**< Position on the frameuffer */
+
+	uint32_t gamma_size;
+	uint32_t mode_valid;
+	struct drm_mode_modeinfo mode;
+};
+
+#define DRM_MODE_ENCODER_NONE	0
+#define DRM_MODE_ENCODER_DAC	1
+#define DRM_MODE_ENCODER_TMDS	2
+#define DRM_MODE_ENCODER_LVDS	3
+#define DRM_MODE_ENCODER_TVDAC	4
+
+struct drm_mode_get_encoder {
+	uint32_t encoder_id;
+	uint32_t encoder_type;
+
+	uint32_t crtc_id; /**< Id of crtc */
+
+	uint32_t possible_crtcs;
+	uint32_t possible_clones;
+};
+
+/* This is for connectors with multiple signal types. */
+/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
+#define DRM_MODE_SUBCONNECTOR_Automatic	0
+#define DRM_MODE_SUBCONNECTOR_Unknown	0
+#define DRM_MODE_SUBCONNECTOR_DVID	3
+#define DRM_MODE_SUBCONNECTOR_DVIA	4
+#define DRM_MODE_SUBCONNECTOR_Composite	5
+#define DRM_MODE_SUBCONNECTOR_SVIDEO	6
+#define DRM_MODE_SUBCONNECTOR_Component	8
+
+#define DRM_MODE_CONNECTOR_Unknown	0
+#define DRM_MODE_CONNECTOR_VGA		1
+#define DRM_MODE_CONNECTOR_DVII		2
+#define DRM_MODE_CONNECTOR_DVID		3
+#define DRM_MODE_CONNECTOR_DVIA		4
+#define DRM_MODE_CONNECTOR_Composite	5
+#define DRM_MODE_CONNECTOR_SVIDEO	6
+#define DRM_MODE_CONNECTOR_LVDS		7
+#define DRM_MODE_CONNECTOR_Component	8
+#define DRM_MODE_CONNECTOR_9PinDIN	9
+#define DRM_MODE_CONNECTOR_DisplayPort	10
+#define DRM_MODE_CONNECTOR_HDMIA	11
+#define DRM_MODE_CONNECTOR_HDMIB	12
+
+struct drm_mode_get_connector {
+
+	uint64_t encoders_ptr;
+	uint64_t modes_ptr;
+	uint64_t props_ptr;
+	uint64_t prop_values_ptr;
+
+	uint32_t count_modes;
+	uint32_t count_props;
+	uint32_t count_encoders;
+
+	uint32_t encoder_id; /**< Current Encoder */
+	uint32_t connector_id; /**< Id */
+	uint32_t connector_type;
+	uint32_t connector_type_id;
+
+	uint32_t connection;
+	uint32_t mm_width, mm_height; /**< HxW in millimeters */
+	uint32_t subpixel;
+};
+
+#define DRM_MODE_PROP_PENDING	(1<<0)
+#define DRM_MODE_PROP_RANGE	(1<<1)
+#define DRM_MODE_PROP_IMMUTABLE	(1<<2)
+#define DRM_MODE_PROP_ENUM	(1<<3) /* enumerated type with text strings */
+#define DRM_MODE_PROP_BLOB	(1<<4)
+
+struct drm_mode_property_enum {
+	uint64_t value;
+	char name[DRM_PROP_NAME_LEN];
+};
+
+struct drm_mode_get_property {
+	uint64_t values_ptr; /* values and blob lengths */
+	uint64_t enum_blob_ptr; /* enum and blob id ptrs */
+
+	uint32_t prop_id;
+	uint32_t flags;
+	char name[DRM_PROP_NAME_LEN];
+
+	uint32_t count_values;
+	uint32_t count_enum_blobs;
+};
+
+struct drm_mode_connector_set_property {
+	uint64_t value;
+	uint32_t prop_id;
+	uint32_t connector_id;
+};
+
+struct drm_mode_get_blob {
+	uint32_t blob_id;
+	uint32_t length;
+	uint64_t data;
+};
+
+struct drm_mode_fb_cmd {
+	uint32_t fb_id;
+	uint32_t width, height;
+	uint32_t pitch;
+	uint32_t bpp;
+	uint32_t depth;
+	/* driver specific handle */
+	uint32_t handle;
+};
+
+struct drm_mode_mode_cmd {
+	uint32_t connector_id;
+	struct drm_mode_modeinfo mode;
+};
+
+#define DRM_MODE_CURSOR_BO	(1<<0)
+#define DRM_MODE_CURSOR_MOVE	(1<<1)
+
+/*
+ * depending on the value in flags diffrent members are used.
+ *
+ * CURSOR_BO uses
+ *    crtc
+ *    width
+ *    height
+ *    handle - if 0 turns the cursor of
+ *
+ * CURSOR_MOVE uses
+ *    crtc
+ *    x
+ *    y
+ */
+struct drm_mode_cursor {
+	uint32_t flags;
+	uint32_t crtc_id;
+	int32_t x;
+	int32_t y;
+	uint32_t width;
+	uint32_t height;
+	/* driver specific handle */
+	uint32_t handle;
+};
+
+struct drm_mode_crtc_lut {
+	uint32_t crtc_id;
+	uint32_t gamma_size;
+
+	/* pointers to arrays */
+	uint64_t red;
+	uint64_t green;
+	uint64_t blue;
+};
+
+#endif
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index 135bd19499fc..5165f240aa68 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -84,18 +84,18 @@
 	{0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
 	{0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
 	{0x1002, 0x5657, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
 	{0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
 	{0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
 	{0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
@@ -113,8 +113,10 @@
 	{0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
 	{0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
 	{0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
-	{0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
-	{0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+	{0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \
+	{0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+	{0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \
+	{0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
 	{0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
 	{0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
 	{0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
@@ -122,16 +124,16 @@
 	{0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
 	{0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
 	{0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
-	{0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-	{0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+	{0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
 	{0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
 	{0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
 	{0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
@@ -237,6 +239,10 @@
 	{0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
 	{0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
 	{0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
+	{0x1002, 0x796c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
+	{0x1002, 0x796d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
+	{0x1002, 0x796e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
+	{0x1002, 0x796f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
 	{0, 0, 0}
 
 #define r128_PCI_IDS \
@@ -389,27 +395,27 @@
 	{0, 0, 0}
 
 #define i915_PCI_IDS \
-	{0x8086, 0x3577, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x2562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x3582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x2572, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x2582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x258a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x2592, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x2772, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x27a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x27ae, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x2972, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x2982, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x2992, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x29a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x29b2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x29c2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x29d2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
-	{0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+	{0x8086, 0x3577, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x2562, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x3582, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x2572, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x2582, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x258a, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x2592, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x2772, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x27a2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x27ae, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x2972, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x2982, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x2992, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x29a2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x29b2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x29c2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x29d2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+	{0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
 	{0, 0, 0}
diff --git a/include/drm/drm_sarea.h b/include/drm/drm_sarea.h
index 480037331e4e..ee5389d22c64 100644
--- a/include/drm/drm_sarea.h
+++ b/include/drm/drm_sarea.h
@@ -36,12 +36,12 @@
 
 /* SAREA area needs to be at least a page */
 #if defined(__alpha__)
-#define SAREA_MAX                       0x2000
+#define SAREA_MAX                       0x2000U
 #elif defined(__ia64__)
-#define SAREA_MAX                       0x10000	/* 64kB */
+#define SAREA_MAX                       0x10000U	/* 64kB */
 #else
 /* Intel 830M driver needs at least 8k SAREA */
-#define SAREA_MAX                       0x2000
+#define SAREA_MAX                       0x2000U
 #endif
 
 /** Maximum number of drawables in the SAREA */
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 05c66cf03a9e..b3bcf72dc656 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -113,8 +113,31 @@ typedef struct _drm_i915_sarea {
 	int pipeB_y;
 	int pipeB_w;
 	int pipeB_h;
+
+	/* fill out some space for old userspace triple buffer */
+	drm_handle_t unused_handle;
+	uint32_t unused1, unused2, unused3;
+
+	/* buffer object handles for static buffers. May change
+	 * over the lifetime of the client.
+	 */
+	uint32_t front_bo_handle;
+	uint32_t back_bo_handle;
+	uint32_t unused_bo_handle;
+	uint32_t depth_bo_handle;
+
 } drm_i915_sarea_t;
 
+/* due to userspace building against these headers we need some compat here */
+#define planeA_x pipeA_x
+#define planeA_y pipeA_y
+#define planeA_w pipeA_w
+#define planeA_h pipeA_h
+#define planeB_x pipeB_x
+#define planeB_y pipeB_y
+#define planeB_w pipeB_w
+#define planeB_h pipeB_h
+
 /* Flags for perf_boxes
  */
 #define I915_BOX_RING_EMPTY    0x1
@@ -143,6 +166,24 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_GET_VBLANK_PIPE	0x0e
 #define DRM_I915_VBLANK_SWAP	0x0f
 #define DRM_I915_HWS_ADDR	0x11
+#define DRM_I915_GEM_INIT	0x13
+#define DRM_I915_GEM_EXECBUFFER	0x14
+#define DRM_I915_GEM_PIN	0x15
+#define DRM_I915_GEM_UNPIN	0x16
+#define DRM_I915_GEM_BUSY	0x17
+#define DRM_I915_GEM_THROTTLE	0x18
+#define DRM_I915_GEM_ENTERVT	0x19
+#define DRM_I915_GEM_LEAVEVT	0x1a
+#define DRM_I915_GEM_CREATE	0x1b
+#define DRM_I915_GEM_PREAD	0x1c
+#define DRM_I915_GEM_PWRITE	0x1d
+#define DRM_I915_GEM_MMAP	0x1e
+#define DRM_I915_GEM_SET_DOMAIN	0x1f
+#define DRM_I915_GEM_SW_FINISH	0x20
+#define DRM_I915_GEM_SET_TILING	0x21
+#define DRM_I915_GEM_GET_TILING	0x22
+#define DRM_I915_GEM_GET_APERTURE 0x23
+#define DRM_I915_GEM_MMAP_GTT	0x24
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -160,11 +201,29 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_SET_VBLANK_PIPE	DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 #define DRM_IOCTL_I915_GET_VBLANK_PIPE	DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 #define DRM_IOCTL_I915_VBLANK_SWAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
+#define DRM_IOCTL_I915_GEM_INIT		DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
+#define DRM_IOCTL_I915_GEM_EXECBUFFER	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
+#define DRM_IOCTL_I915_GEM_PIN		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
+#define DRM_IOCTL_I915_GEM_UNPIN	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
+#define DRM_IOCTL_I915_GEM_BUSY		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
+#define DRM_IOCTL_I915_GEM_THROTTLE	DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
+#define DRM_IOCTL_I915_GEM_ENTERVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
+#define DRM_IOCTL_I915_GEM_LEAVEVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
+#define DRM_IOCTL_I915_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_PREAD	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
+#define DRM_IOCTL_I915_GEM_PWRITE	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
+#define DRM_IOCTL_I915_GEM_MMAP		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
+#define DRM_IOCTL_I915_GEM_MMAP_GTT	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
+#define DRM_IOCTL_I915_GEM_SET_DOMAIN	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
+#define DRM_IOCTL_I915_GEM_SW_FINISH	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
+#define DRM_IOCTL_I915_GEM_SET_TILING	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
+#define DRM_IOCTL_I915_GEM_GET_TILING	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
+#define DRM_IOCTL_I915_GEM_GET_APERTURE	DRM_IOR  (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
  */
-typedef struct _drm_i915_batchbuffer {
+typedef struct drm_i915_batchbuffer {
 	int start;		/* agp offset */
 	int used;		/* nr bytes in use */
 	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
@@ -200,6 +259,8 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_IRQ_ACTIVE            1
 #define I915_PARAM_ALLOW_BATCHBUFFER     2
 #define I915_PARAM_LAST_DISPATCH         3
+#define I915_PARAM_CHIPSET_ID            4
+#define I915_PARAM_HAS_GEM               5
 
 typedef struct drm_i915_getparam {
 	int param;
@@ -267,4 +328,328 @@ typedef struct drm_i915_hws_addr {
 	uint64_t addr;
 } drm_i915_hws_addr_t;
 
+struct drm_i915_gem_init {
+	/**
+	 * Beginning offset in the GTT to be managed by the DRM memory
+	 * manager.
+	 */
+	uint64_t gtt_start;
+	/**
+	 * Ending offset in the GTT to be managed by the DRM memory
+	 * manager.
+	 */
+	uint64_t gtt_end;
+};
+
+struct drm_i915_gem_create {
+	/**
+	 * Requested size for the object.
+	 *
+	 * The (page-aligned) allocated size for the object will be returned.
+	 */
+	uint64_t size;
+	/**
+	 * Returned handle for the object.
+	 *
+	 * Object handles are nonzero.
+	 */
+	uint32_t handle;
+	uint32_t pad;
+};
+
+struct drm_i915_gem_pread {
+	/** Handle for the object being read. */
+	uint32_t handle;
+	uint32_t pad;
+	/** Offset into the object to read from */
+	uint64_t offset;
+	/** Length of data to read */
+	uint64_t size;
+	/**
+	 * Pointer to write the data into.
+	 *
+	 * This is a fixed-size type for 32/64 compatibility.
+	 */
+	uint64_t data_ptr;
+};
+
+struct drm_i915_gem_pwrite {
+	/** Handle for the object being written to. */
+	uint32_t handle;
+	uint32_t pad;
+	/** Offset into the object to write to */
+	uint64_t offset;
+	/** Length of data to write */
+	uint64_t size;
+	/**
+	 * Pointer to read the data from.
+	 *
+	 * This is a fixed-size type for 32/64 compatibility.
+	 */
+	uint64_t data_ptr;
+};
+
+struct drm_i915_gem_mmap {
+	/** Handle for the object being mapped. */
+	uint32_t handle;
+	uint32_t pad;
+	/** Offset in the object to map. */
+	uint64_t offset;
+	/**
+	 * Length of data to map.
+	 *
+	 * The value will be page-aligned.
+	 */
+	uint64_t size;
+	/**
+	 * Returned pointer the data was mapped at.
+	 *
+	 * This is a fixed-size type for 32/64 compatibility.
+	 */
+	uint64_t addr_ptr;
+};
+
+struct drm_i915_gem_mmap_gtt {
+	/** Handle for the object being mapped. */
+	uint32_t handle;
+	uint32_t pad;
+	/**
+	 * Fake offset to use for subsequent mmap call
+	 *
+	 * This is a fixed-size type for 32/64 compatibility.
+	 */
+	uint64_t offset;
+};
+
+struct drm_i915_gem_set_domain {
+	/** Handle for the object */
+	uint32_t handle;
+
+	/** New read domains */
+	uint32_t read_domains;
+
+	/** New write domain */
+	uint32_t write_domain;
+};
+
+struct drm_i915_gem_sw_finish {
+	/** Handle for the object */
+	uint32_t handle;
+};
+
+struct drm_i915_gem_relocation_entry {
+	/**
+	 * Handle of the buffer being pointed to by this relocation entry.
+	 *
+	 * It's appealing to make this be an index into the mm_validate_entry
+	 * list to refer to the buffer, but this allows the driver to create
+	 * a relocation list for state buffers and not re-write it per
+	 * exec using the buffer.
+	 */
+	uint32_t target_handle;
+
+	/**
+	 * Value to be added to the offset of the target buffer to make up
+	 * the relocation entry.
+	 */
+	uint32_t delta;
+
+	/** Offset in the buffer the relocation entry will be written into */
+	uint64_t offset;
+
+	/**
+	 * Offset value of the target buffer that the relocation entry was last
+	 * written as.
+	 *
+	 * If the buffer has the same offset as last time, we can skip syncing
+	 * and writing the relocation.  This value is written back out by
+	 * the execbuffer ioctl when the relocation is written.
+	 */
+	uint64_t presumed_offset;
+
+	/**
+	 * Target memory domains read by this operation.
+	 */
+	uint32_t read_domains;
+
+	/**
+	 * Target memory domains written by this operation.
+	 *
+	 * Note that only one domain may be written by the whole
+	 * execbuffer operation, so that where there are conflicts,
+	 * the application will get -EINVAL back.
+	 */
+	uint32_t write_domain;
+};
+
+/** @{
+ * Intel memory domains
+ *
+ * Most of these just align with the various caches in
+ * the system and are used to flush and invalidate as
+ * objects end up cached in different domains.
+ */
+/** CPU cache */
+#define I915_GEM_DOMAIN_CPU		0x00000001
+/** Render cache, used by 2D and 3D drawing */
+#define I915_GEM_DOMAIN_RENDER		0x00000002
+/** Sampler cache, used by texture engine */
+#define I915_GEM_DOMAIN_SAMPLER		0x00000004
+/** Command queue, used to load batch buffers */
+#define I915_GEM_DOMAIN_COMMAND		0x00000008
+/** Instruction cache, used by shader programs */
+#define I915_GEM_DOMAIN_INSTRUCTION	0x00000010
+/** Vertex address cache */
+#define I915_GEM_DOMAIN_VERTEX		0x00000020
+/** GTT domain - aperture and scanout */
+#define I915_GEM_DOMAIN_GTT		0x00000040
+/** @} */
+
+struct drm_i915_gem_exec_object {
+	/**
+	 * User's handle for a buffer to be bound into the GTT for this
+	 * operation.
+	 */
+	uint32_t handle;
+
+	/** Number of relocations to be performed on this buffer */
+	uint32_t relocation_count;
+	/**
+	 * Pointer to array of struct drm_i915_gem_relocation_entry containing
+	 * the relocations to be performed in this buffer.
+	 */
+	uint64_t relocs_ptr;
+
+	/** Required alignment in graphics aperture */
+	uint64_t alignment;
+
+	/**
+	 * Returned value of the updated offset of the object, for future
+	 * presumed_offset writes.
+	 */
+	uint64_t offset;
+};
+
+struct drm_i915_gem_execbuffer {
+	/**
+	 * List of buffers to be validated with their relocations to be
+	 * performend on them.
+	 *
+	 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
+	 *
+	 * These buffers must be listed in an order such that all relocations
+	 * a buffer is performing refer to buffers that have already appeared
+	 * in the validate list.
+	 */
+	uint64_t buffers_ptr;
+	uint32_t buffer_count;
+
+	/** Offset in the batchbuffer to start execution from. */
+	uint32_t batch_start_offset;
+	/** Bytes used in batchbuffer from batch_start_offset */
+	uint32_t batch_len;
+	uint32_t DR1;
+	uint32_t DR4;
+	uint32_t num_cliprects;
+	/** This is a struct drm_clip_rect *cliprects */
+	uint64_t cliprects_ptr;
+};
+
+struct drm_i915_gem_pin {
+	/** Handle of the buffer to be pinned. */
+	uint32_t handle;
+	uint32_t pad;
+
+	/** alignment required within the aperture */
+	uint64_t alignment;
+
+	/** Returned GTT offset of the buffer. */
+	uint64_t offset;
+};
+
+struct drm_i915_gem_unpin {
+	/** Handle of the buffer to be unpinned. */
+	uint32_t handle;
+	uint32_t pad;
+};
+
+struct drm_i915_gem_busy {
+	/** Handle of the buffer to check for busy */
+	uint32_t handle;
+
+	/** Return busy status (1 if busy, 0 if idle) */
+	uint32_t busy;
+};
+
+#define I915_TILING_NONE	0
+#define I915_TILING_X		1
+#define I915_TILING_Y		2
+
+#define I915_BIT_6_SWIZZLE_NONE		0
+#define I915_BIT_6_SWIZZLE_9		1
+#define I915_BIT_6_SWIZZLE_9_10		2
+#define I915_BIT_6_SWIZZLE_9_11		3
+#define I915_BIT_6_SWIZZLE_9_10_11	4
+/* Not seen by userland */
+#define I915_BIT_6_SWIZZLE_UNKNOWN	5
+
+struct drm_i915_gem_set_tiling {
+	/** Handle of the buffer to have its tiling state updated */
+	uint32_t handle;
+
+	/**
+	 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
+	 * I915_TILING_Y).
+	 *
+	 * This value is to be set on request, and will be updated by the
+	 * kernel on successful return with the actual chosen tiling layout.
+	 *
+	 * The tiling mode may be demoted to I915_TILING_NONE when the system
+	 * has bit 6 swizzling that can't be managed correctly by GEM.
+	 *
+	 * Buffer contents become undefined when changing tiling_mode.
+	 */
+	uint32_t tiling_mode;
+
+	/**
+	 * Stride in bytes for the object when in I915_TILING_X or
+	 * I915_TILING_Y.
+	 */
+	uint32_t stride;
+
+	/**
+	 * Returned address bit 6 swizzling required for CPU access through
+	 * mmap mapping.
+	 */
+	uint32_t swizzle_mode;
+};
+
+struct drm_i915_gem_get_tiling {
+	/** Handle of the buffer to get tiling state for. */
+	uint32_t handle;
+
+	/**
+	 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
+	 * I915_TILING_Y).
+	 */
+	uint32_t tiling_mode;
+
+	/**
+	 * Returned address bit 6 swizzling required for CPU access through
+	 * mmap mapping.
+	 */
+	uint32_t swizzle_mode;
+};
+
+struct drm_i915_gem_get_aperture {
+	/** Total size of the aperture used by i915_gem_execbuffer, in bytes */
+	uint64_t aper_size;
+
+	/**
+	 * Available space in the aperture used by i915_gem_execbuffer, in
+	 * bytes
+	 */
+	uint64_t aper_available_size;
+};
+
 #endif				/* _I915_DRM_H_ */
diff --git a/include/keys/keyring-type.h b/include/keys/keyring-type.h
new file mode 100644
index 000000000000..843f872a4b63
--- /dev/null
+++ b/include/keys/keyring-type.h
@@ -0,0 +1,31 @@
+/* Keyring key type
+ *
+ * Copyright (C) 2008 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _KEYS_KEYRING_TYPE_H
+#define _KEYS_KEYRING_TYPE_H
+
+#include <linux/key.h>
+#include <linux/rcupdate.h>
+
+/*
+ * the keyring payload contains a list of the keys to which the keyring is
+ * subscribed
+ */
+struct keyring_list {
+	struct rcu_head	rcu;		/* RCU deletion hook */
+	unsigned short	maxkeys;	/* max keys this list can hold */
+	unsigned short	nkeys;		/* number of keys currently held */
+	unsigned short	delkey;		/* key to be unlinked by RCU */
+	struct key	*keys[0];
+};
+
+
+#endif /* _KEYS_KEYRING_TYPE_H */
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index 282a504bd1db..95ac82340c3b 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -107,6 +107,7 @@ header-y += keyctl.h
 header-y += limits.h
 header-y += magic.h
 header-y += major.h
+header-y += map_to_7segment.h
 header-y += matroxfb.h
 header-y += meye.h
 header-y += minix_fs.h
@@ -182,6 +183,7 @@ unifdef-y += auto_fs.h
 unifdef-y += auxvec.h
 unifdef-y += binfmts.h
 unifdef-y += blktrace_api.h
+unifdef-y += byteorder.h
 unifdef-y += capability.h
 unifdef-y += capi.h
 unifdef-y += cciss_ioctl.h
@@ -311,6 +313,7 @@ unifdef-y += ptrace.h
 unifdef-y += qnx4_fs.h
 unifdef-y += quota.h
 unifdef-y += random.h
+unifdef-y += irqnr.h
 unifdef-y += reboot.h
 unifdef-y += reiserfs_fs.h
 unifdef-y += reiserfs_xattr.h
@@ -339,6 +342,7 @@ unifdef-y += soundcard.h
 unifdef-y += stat.h
 unifdef-y += stddef.h
 unifdef-y += string.h
+unifdef-y += swab.h
 unifdef-y += synclink.h
 unifdef-y += sysctl.h
 unifdef-y += tcp.h
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 702f79dad16a..fba8051fb297 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -94,18 +94,10 @@ int acpi_parse_mcfg (struct acpi_table_header *header);
 void acpi_table_print_madt_entry (struct acpi_subtable_header *madt);
 
 /* the following four functions are architecture-dependent */
-#ifdef CONFIG_HAVE_ARCH_PARSE_SRAT
-#define NR_NODE_MEMBLKS MAX_NUMNODES
-#define acpi_numa_slit_init(slit) do {} while (0)
-#define acpi_numa_processor_affinity_init(pa) do {} while (0)
-#define acpi_numa_memory_affinity_init(ma) do {} while (0)
-#define acpi_numa_arch_fixup() do {} while (0)
-#else
 void acpi_numa_slit_init (struct acpi_table_slit *slit);
 void acpi_numa_processor_affinity_init (struct acpi_srat_cpu_affinity *pa);
 void acpi_numa_memory_affinity_init (struct acpi_srat_mem_affinity *ma);
 void acpi_numa_arch_fixup(void);
-#endif
 
 #ifdef CONFIG_ACPI_HOTPLUG_CPU
 /* Arch dependent functions for cpu hotplug support */
@@ -171,8 +163,6 @@ struct acpi_pci_driver {
 int acpi_pci_register_driver(struct acpi_pci_driver *driver);
 void acpi_pci_unregister_driver(struct acpi_pci_driver *driver);
 
-#ifdef CONFIG_ACPI_EC
-
 extern int ec_read(u8 addr, u8 *val);
 extern int ec_write(u8 addr, u8 val);
 extern int ec_transaction(u8 command,
@@ -180,8 +170,6 @@ extern int ec_transaction(u8 command,
                           u8 *rdata, unsigned rdata_len,
 			  int force_poll);
 
-#endif /*CONFIG_ACPI_EC*/
-
 #if defined(CONFIG_ACPI_WMI) || defined(CONFIG_ACPI_WMI_MODULE)
 
 typedef void (*wmi_notify_handler) (u32 value, void *context);
@@ -202,6 +190,50 @@ extern bool wmi_has_guid(const char *guid);
 
 #endif	/* CONFIG_ACPI_WMI */
 
+#define ACPI_VIDEO_OUTPUT_SWITCHING			0x0001
+#define ACPI_VIDEO_DEVICE_POSTING			0x0002
+#define ACPI_VIDEO_ROM_AVAILABLE			0x0004
+#define ACPI_VIDEO_BACKLIGHT				0x0008
+#define ACPI_VIDEO_BACKLIGHT_FORCE_VENDOR		0x0010
+#define ACPI_VIDEO_BACKLIGHT_FORCE_VIDEO		0x0020
+#define ACPI_VIDEO_OUTPUT_SWITCHING_FORCE_VENDOR	0x0040
+#define ACPI_VIDEO_OUTPUT_SWITCHING_FORCE_VIDEO		0x0080
+#define ACPI_VIDEO_BACKLIGHT_DMI_VENDOR			0x0100
+#define ACPI_VIDEO_BACKLIGHT_DMI_VIDEO			0x0200
+#define ACPI_VIDEO_OUTPUT_SWITCHING_DMI_VENDOR		0x0400
+#define ACPI_VIDEO_OUTPUT_SWITCHING_DMI_VIDEO		0x0800
+
+#if defined(CONFIG_ACPI_VIDEO) || defined(CONFIG_ACPI_VIDEO_MODULE)
+
+extern long acpi_video_get_capabilities(acpi_handle graphics_dev_handle);
+extern long acpi_is_video_device(struct acpi_device *device);
+extern int acpi_video_backlight_support(void);
+extern int acpi_video_display_switch_support(void);
+
+#else
+
+static inline long acpi_video_get_capabilities(acpi_handle graphics_dev_handle)
+{
+	return 0;
+}
+
+static inline long acpi_is_video_device(struct acpi_device *device)
+{
+	return 0;
+}
+
+static inline int acpi_video_backlight_support(void)
+{
+	return 0;
+}
+
+static inline int acpi_video_display_switch_support(void)
+{
+	return 0;
+}
+
+#endif /* defined(CONFIG_ACPI_VIDEO) || defined(CONFIG_ACPI_VIDEO_MODULE) */
+
 extern int acpi_blacklisted(void);
 #ifdef CONFIG_DMI
 extern void acpi_dmi_osi_linux(int enable, const struct dmi_system_id *d);
diff --git a/include/linux/aer.h b/include/linux/aer.h
index f2518141de88..f7df1eefc107 100644
--- a/include/linux/aer.h
+++ b/include/linux/aer.h
@@ -10,7 +10,6 @@
 #if defined(CONFIG_PCIEAER)
 /* pci-e port driver needs this function to enable aer */
 extern int pci_enable_pcie_error_reporting(struct pci_dev *dev);
-extern int pci_find_aer_capability(struct pci_dev *dev);
 extern int pci_disable_pcie_error_reporting(struct pci_dev *dev);
 extern int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev);
 #else
@@ -18,10 +17,6 @@ static inline int pci_enable_pcie_error_reporting(struct pci_dev *dev)
 {
 	return -EINVAL;
 }
-static inline int pci_find_aer_capability(struct pci_dev *dev)
-{
-	return 0;
-}
 static inline int pci_disable_pcie_error_reporting(struct pci_dev *dev)
 {
 	return -EINVAL;
diff --git a/include/linux/aio.h b/include/linux/aio.h
index 09b276c35227..b16a957030f8 100644
--- a/include/linux/aio.h
+++ b/include/linux/aio.h
@@ -5,6 +5,7 @@
 #include <linux/workqueue.h>
 #include <linux/aio_abi.h>
 #include <linux/uio.h>
+#include <linux/rcupdate.h>
 
 #include <asm/atomic.h>
 
@@ -183,7 +184,7 @@ struct kioctx {
 
 	/* This needs improving */
 	unsigned long		user_id;
-	struct kioctx		*next;
+	struct hlist_node	list;
 
 	wait_queue_head_t	wait;
 
@@ -199,17 +200,28 @@ struct kioctx {
 	struct aio_ring_info	ring_info;
 
 	struct delayed_work	wq;
+
+	struct rcu_head		rcu_head;
 };
 
 /* prototypes */
 extern unsigned aio_max_size;
 
+#ifdef CONFIG_AIO
 extern ssize_t wait_on_sync_kiocb(struct kiocb *iocb);
 extern int aio_put_req(struct kiocb *iocb);
 extern void kick_iocb(struct kiocb *iocb);
 extern int aio_complete(struct kiocb *iocb, long res, long res2);
 struct mm_struct;
 extern void exit_aio(struct mm_struct *mm);
+#else
+static inline ssize_t wait_on_sync_kiocb(struct kiocb *iocb) { return 0; }
+static inline int aio_put_req(struct kiocb *iocb) { return 0; }
+static inline void kick_iocb(struct kiocb *iocb) { }
+static inline int aio_complete(struct kiocb *iocb, long res, long res2) { return 0; }
+struct mm_struct;
+static inline void exit_aio(struct mm_struct *mm) { }
+#endif /* CONFIG_AIO */
 
 #define io_wait_to_kiocb(wait) container_of(wait, struct kiocb, ki_wait)
 
diff --git a/include/linux/atm.h b/include/linux/atm.h
index c791ddd96939..d3b292174aeb 100644
--- a/include/linux/atm.h
+++ b/include/linux/atm.h
@@ -231,10 +231,21 @@ static __inline__ int atmpvc_addr_in_use(struct sockaddr_atmpvc addr)
  */
 
 struct atmif_sioc {
-    int number;
-    int length;
-    void __user *arg;
+	int number;
+	int length;
+	void __user *arg;
 };
 
+#ifdef __KERNEL__
+#ifdef CONFIG_COMPAT
+#include <linux/compat.h>
+struct compat_atmif_sioc {
+	int number;
+	int length;
+	compat_uptr_t arg;
+};
+#endif
+#endif
+
 typedef unsigned short atm_backend_t;
 #endif
diff --git a/include/linux/atmdev.h b/include/linux/atmdev.h
index a3d07c29d16c..086e5c362d3a 100644
--- a/include/linux/atmdev.h
+++ b/include/linux/atmdev.h
@@ -100,6 +100,10 @@ struct atm_dev_stats {
 					/* use backend to make new if */
 #define ATM_ADDPARTY  	_IOW('a', ATMIOC_SPECIAL+4,struct atm_iobuf)
  					/* add party to p2mp call */
+#ifdef CONFIG_COMPAT
+/* It actually takes struct sockaddr_atmsvc, not struct atm_iobuf */
+#define COMPAT_ATM_ADDPARTY  	_IOW('a', ATMIOC_SPECIAL+4,struct compat_atm_iobuf)
+#endif
 #define ATM_DROPPARTY 	_IOW('a', ATMIOC_SPECIAL+5,int)
 					/* drop party from p2mp call */
 
@@ -224,6 +228,13 @@ struct atm_cirange {
 extern struct proc_dir_entry *atm_proc_root;
 #endif
 
+#ifdef CONFIG_COMPAT
+#include <linux/compat.h>
+struct compat_atm_iobuf {
+	int length;
+	compat_uptr_t buffer;
+};
+#endif
 
 struct k_atm_aal_stats {
 #define __HANDLE_ITEM(i) atomic_t i
@@ -379,6 +390,10 @@ struct atmdev_ops { /* only send is required */
 	int (*open)(struct atm_vcc *vcc);
 	void (*close)(struct atm_vcc *vcc);
 	int (*ioctl)(struct atm_dev *dev,unsigned int cmd,void __user *arg);
+#ifdef CONFIG_COMPAT
+	int (*compat_ioctl)(struct atm_dev *dev,unsigned int cmd,
+			    void __user *arg);
+#endif
 	int (*getsockopt)(struct atm_vcc *vcc,int level,int optname,
 	    void __user *optval,int optlen);
 	int (*setsockopt)(struct atm_vcc *vcc,int level,int optname,
diff --git a/include/linux/audit.h b/include/linux/audit.h
index 6272a395d43c..26c4f6f65a46 100644
--- a/include/linux/audit.h
+++ b/include/linux/audit.h
@@ -99,6 +99,8 @@
 #define AUDIT_OBJ_PID		1318	/* ptrace target */
 #define AUDIT_TTY		1319	/* Input on an administrative TTY */
 #define AUDIT_EOE		1320	/* End of multi-record event */
+#define AUDIT_BPRM_FCAPS	1321	/* Information about fcaps increasing perms */
+#define AUDIT_CAPSET		1322	/* Record showing argument to sys_capset */
 
 #define AUDIT_AVC		1400	/* SE Linux avc denial or grant */
 #define AUDIT_SELINUX_ERR	1401	/* Internal SE Linux Errors */
@@ -391,6 +393,7 @@ extern int audit_classify_arch(int arch);
 #ifdef CONFIG_AUDITSYSCALL
 /* These are defined in auditsc.c */
 				/* Public API */
+extern void audit_finish_fork(struct task_struct *child);
 extern int  audit_alloc(struct task_struct *task);
 extern void audit_free(struct task_struct *task);
 extern void audit_syscall_entry(int arch,
@@ -434,7 +437,7 @@ static inline void audit_ptrace(struct task_struct *t)
 
 				/* Private API (for audit.c only) */
 extern unsigned int audit_serial(void);
-extern void auditsc_get_stamp(struct audit_context *ctx,
+extern int auditsc_get_stamp(struct audit_context *ctx,
 			      struct timespec *t, unsigned int *serial);
 extern int  audit_set_loginuid(struct task_struct *task, uid_t loginuid);
 #define audit_get_loginuid(t) ((t)->loginuid)
@@ -452,6 +455,10 @@ extern int __audit_mq_timedsend(mqd_t mqdes, size_t msg_len, unsigned int msg_pr
 extern int __audit_mq_timedreceive(mqd_t mqdes, size_t msg_len, unsigned int __user *u_msg_prio, const struct timespec __user *u_abs_timeout);
 extern int __audit_mq_notify(mqd_t mqdes, const struct sigevent __user *u_notification);
 extern int __audit_mq_getsetattr(mqd_t mqdes, struct mq_attr *mqstat);
+extern int __audit_log_bprm_fcaps(struct linux_binprm *bprm,
+				  const struct cred *new,
+				  const struct cred *old);
+extern int __audit_log_capset(pid_t pid, const struct cred *new, const struct cred *old);
 
 static inline int audit_ipc_obj(struct kern_ipc_perm *ipcp)
 {
@@ -501,9 +508,28 @@ static inline int audit_mq_getsetattr(mqd_t mqdes, struct mq_attr *mqstat)
 		return __audit_mq_getsetattr(mqdes, mqstat);
 	return 0;
 }
+
+static inline int audit_log_bprm_fcaps(struct linux_binprm *bprm,
+				       const struct cred *new,
+				       const struct cred *old)
+{
+	if (unlikely(!audit_dummy_context()))
+		return __audit_log_bprm_fcaps(bprm, new, old);
+	return 0;
+}
+
+static inline int audit_log_capset(pid_t pid, const struct cred *new,
+				   const struct cred *old)
+{
+	if (unlikely(!audit_dummy_context()))
+		return __audit_log_capset(pid, new, old);
+	return 0;
+}
+
 extern int audit_n_rules;
 extern int audit_signals;
 #else
+#define audit_finish_fork(t)
 #define audit_alloc(t) ({ 0; })
 #define audit_free(t) do { ; } while (0)
 #define audit_syscall_entry(ta,a,b,c,d,e) do { ; } while (0)
@@ -516,7 +542,7 @@ extern int audit_signals;
 #define audit_inode(n,d) do { ; } while (0)
 #define audit_inode_child(d,i,p) do { ; } while (0)
 #define audit_core_dumps(i) do { ; } while (0)
-#define auditsc_get_stamp(c,t,s) do { BUG(); } while (0)
+#define auditsc_get_stamp(c,t,s) (0)
 #define audit_get_loginuid(t) (-1)
 #define audit_get_sessionid(t) (-1)
 #define audit_log_task_context(b) do { ; } while (0)
@@ -532,6 +558,8 @@ extern int audit_signals;
 #define audit_mq_timedreceive(d,l,p,t) ({ 0; })
 #define audit_mq_notify(d,n) ({ 0; })
 #define audit_mq_getsetattr(d,s) ({ 0; })
+#define audit_log_bprm_fcaps(b, ncr, ocr) ({ 0; })
+#define audit_log_capset(pid, ncr, ocr) ({ 0; })
 #define audit_ptrace(t) ((void)0)
 #define audit_n_rules 0
 #define audit_signals 0
diff --git a/include/linux/auto_dev-ioctl.h b/include/linux/auto_dev-ioctl.h
new file mode 100644
index 000000000000..f4d05ccd731f
--- /dev/null
+++ b/include/linux/auto_dev-ioctl.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2008 Red Hat, Inc. All rights reserved.
+ * Copyright 2008 Ian Kent <raven@themaw.net>
+ *
+ * This file is part of the Linux kernel and is made available under
+ * the terms of the GNU General Public License, version 2, or at your
+ * option, any later version, incorporated herein by reference.
+ */
+
+#ifndef _LINUX_AUTO_DEV_IOCTL_H
+#define _LINUX_AUTO_DEV_IOCTL_H
+
+#include <linux/types.h>
+
+#define AUTOFS_DEVICE_NAME		"autofs"
+
+#define AUTOFS_DEV_IOCTL_VERSION_MAJOR	1
+#define AUTOFS_DEV_IOCTL_VERSION_MINOR	0
+
+#define AUTOFS_DEVID_LEN		16
+
+#define AUTOFS_DEV_IOCTL_SIZE		sizeof(struct autofs_dev_ioctl)
+
+/*
+ * An ioctl interface for autofs mount point control.
+ */
+
+/*
+ * All the ioctls use this structure.
+ * When sending a path size must account for the total length
+ * of the chunk of memory otherwise is is the size of the
+ * structure.
+ */
+
+struct autofs_dev_ioctl {
+	__u32 ver_major;
+	__u32 ver_minor;
+	__u32 size;		/* total size of data passed in
+				 * including this struct */
+	__s32 ioctlfd;		/* automount command fd */
+
+	__u32 arg1;		/* Command parameters */
+	__u32 arg2;
+
+	char path[0];
+};
+
+static inline void init_autofs_dev_ioctl(struct autofs_dev_ioctl *in)
+{
+	in->ver_major = AUTOFS_DEV_IOCTL_VERSION_MAJOR;
+	in->ver_minor = AUTOFS_DEV_IOCTL_VERSION_MINOR;
+	in->size = sizeof(struct autofs_dev_ioctl);
+	in->ioctlfd = -1;
+	in->arg1 = 0;
+	in->arg2 = 0;
+	return;
+}
+
+/*
+ * If you change this make sure you make the corresponding change
+ * to autofs-dev-ioctl.c:lookup_ioctl()
+ */
+enum {
+	/* Get various version info */
+	AUTOFS_DEV_IOCTL_VERSION_CMD = 0x71,
+	AUTOFS_DEV_IOCTL_PROTOVER_CMD,
+	AUTOFS_DEV_IOCTL_PROTOSUBVER_CMD,
+
+	/* Open mount ioctl fd */
+	AUTOFS_DEV_IOCTL_OPENMOUNT_CMD,
+
+	/* Close mount ioctl fd */
+	AUTOFS_DEV_IOCTL_CLOSEMOUNT_CMD,
+
+	/* Mount/expire status returns */
+	AUTOFS_DEV_IOCTL_READY_CMD,
+	AUTOFS_DEV_IOCTL_FAIL_CMD,
+
+	/* Activate/deactivate autofs mount */
+	AUTOFS_DEV_IOCTL_SETPIPEFD_CMD,
+	AUTOFS_DEV_IOCTL_CATATONIC_CMD,
+
+	/* Expiry timeout */
+	AUTOFS_DEV_IOCTL_TIMEOUT_CMD,
+
+	/* Get mount last requesting uid and gid */
+	AUTOFS_DEV_IOCTL_REQUESTER_CMD,
+
+	/* Check for eligible expire candidates */
+	AUTOFS_DEV_IOCTL_EXPIRE_CMD,
+
+	/* Request busy status */
+	AUTOFS_DEV_IOCTL_ASKUMOUNT_CMD,
+
+	/* Check if path is a mountpoint */
+	AUTOFS_DEV_IOCTL_ISMOUNTPOINT_CMD,
+};
+
+#define AUTOFS_IOCTL 0x93
+
+#define AUTOFS_DEV_IOCTL_VERSION \
+	_IOWR(AUTOFS_IOCTL, \
+	      AUTOFS_DEV_IOCTL_VERSION_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_PROTOVER \
+	_IOWR(AUTOFS_IOCTL, \
+	      AUTOFS_DEV_IOCTL_PROTOVER_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_PROTOSUBVER \
+	_IOWR(AUTOFS_IOCTL, \
+	      AUTOFS_DEV_IOCTL_PROTOSUBVER_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_OPENMOUNT \
+	_IOWR(AUTOFS_IOCTL, \
+	      AUTOFS_DEV_IOCTL_OPENMOUNT_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_CLOSEMOUNT \
+	_IOWR(AUTOFS_IOCTL, \
+	      AUTOFS_DEV_IOCTL_CLOSEMOUNT_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_READY \
+	_IOWR(AUTOFS_IOCTL, \
+	      AUTOFS_DEV_IOCTL_READY_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_FAIL \
+	_IOWR(AUTOFS_IOCTL, \
+	      AUTOFS_DEV_IOCTL_FAIL_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_SETPIPEFD \
+	_IOWR(AUTOFS_IOCTL, \
+	      AUTOFS_DEV_IOCTL_SETPIPEFD_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_CATATONIC \
+	_IOWR(AUTOFS_IOCTL, \
+	      AUTOFS_DEV_IOCTL_CATATONIC_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_TIMEOUT \
+	_IOWR(AUTOFS_IOCTL, \
+	      AUTOFS_DEV_IOCTL_TIMEOUT_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_REQUESTER \
+	_IOWR(AUTOFS_IOCTL, \
+	      AUTOFS_DEV_IOCTL_REQUESTER_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_EXPIRE \
+	_IOWR(AUTOFS_IOCTL, \
+	      AUTOFS_DEV_IOCTL_EXPIRE_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_ASKUMOUNT \
+	_IOWR(AUTOFS_IOCTL, \
+	      AUTOFS_DEV_IOCTL_ASKUMOUNT_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_ISMOUNTPOINT \
+	_IOWR(AUTOFS_IOCTL, \
+	      AUTOFS_DEV_IOCTL_ISMOUNTPOINT_CMD, struct autofs_dev_ioctl)
+
+#endif	/* _LINUX_AUTO_DEV_IOCTL_H */
diff --git a/include/linux/auto_fs4.h b/include/linux/auto_fs4.h
index b785c6f8644d..2253716d4b92 100644
--- a/include/linux/auto_fs4.h
+++ b/include/linux/auto_fs4.h
@@ -23,12 +23,17 @@
 #define AUTOFS_MIN_PROTO_VERSION	3
 #define AUTOFS_MAX_PROTO_VERSION	5
 
-#define AUTOFS_PROTO_SUBVERSION		0
+#define AUTOFS_PROTO_SUBVERSION		1
 
 /* Mask for expire behaviour */
 #define AUTOFS_EXP_IMMEDIATE		1
 #define AUTOFS_EXP_LEAVES		2
 
+#define AUTOFS_TYPE_ANY			0x0000
+#define AUTOFS_TYPE_INDIRECT		0x0001
+#define AUTOFS_TYPE_DIRECT		0x0002
+#define AUTOFS_TYPE_OFFSET		0x0004
+
 /* Daemon notification packet types */
 enum autofs_notify {
 	NFY_NONE,
diff --git a/include/linux/backing-dev.h b/include/linux/backing-dev.h
index 0a24d5550eb3..bee52abb8a4d 100644
--- a/include/linux/backing-dev.h
+++ b/include/linux/backing-dev.h
@@ -175,6 +175,8 @@ int bdi_set_max_ratio(struct backing_dev_info *bdi, unsigned int max_ratio);
  * BDI_CAP_READ_MAP:       Can be mapped for reading
  * BDI_CAP_WRITE_MAP:      Can be mapped for writing
  * BDI_CAP_EXEC_MAP:       Can be mapped for execution
+ *
+ * BDI_CAP_SWAP_BACKED:    Count shmem/tmpfs objects as swap-backed.
  */
 #define BDI_CAP_NO_ACCT_DIRTY	0x00000001
 #define BDI_CAP_NO_WRITEBACK	0x00000002
@@ -184,6 +186,7 @@ int bdi_set_max_ratio(struct backing_dev_info *bdi, unsigned int max_ratio);
 #define BDI_CAP_WRITE_MAP	0x00000020
 #define BDI_CAP_EXEC_MAP	0x00000040
 #define BDI_CAP_NO_ACCT_WB	0x00000080
+#define BDI_CAP_SWAP_BACKED	0x00000100
 
 #define BDI_CAP_VMFLAGS \
 	(BDI_CAP_READ_MAP | BDI_CAP_WRITE_MAP | BDI_CAP_EXEC_MAP)
@@ -248,6 +251,11 @@ static inline bool bdi_cap_account_writeback(struct backing_dev_info *bdi)
 				      BDI_CAP_NO_WRITEBACK));
 }
 
+static inline bool bdi_cap_swap_backed(struct backing_dev_info *bdi)
+{
+	return bdi->capabilities & BDI_CAP_SWAP_BACKED;
+}
+
 static inline bool mapping_cap_writeback_dirty(struct address_space *mapping)
 {
 	return bdi_cap_writeback_dirty(mapping->backing_dev_info);
@@ -258,4 +266,9 @@ static inline bool mapping_cap_account_dirty(struct address_space *mapping)
 	return bdi_cap_account_dirty(mapping->backing_dev_info);
 }
 
+static inline bool mapping_cap_swap_backed(struct address_space *mapping)
+{
+	return bdi_cap_swap_backed(mapping->backing_dev_info);
+}
+
 #endif		/* _LINUX_BACKING_DEV_H */
diff --git a/include/linux/bcd.h b/include/linux/bcd.h
index 7ac518e3c152..22ea563ba3eb 100644
--- a/include/linux/bcd.h
+++ b/include/linux/bcd.h
@@ -1,12 +1,3 @@
-/* Permission is hereby granted to copy, modify and redistribute this code
- * in terms of the GNU Library General Public License, Version 2 or later,
- * at your option.
- */
-
-/* macros to translate to/from binary and binary-coded decimal (frequently
- * found in RTC chips).
- */
-
 #ifndef _BCD_H
 #define _BCD_H
 
@@ -15,11 +6,4 @@
 unsigned bcd2bin(unsigned char val) __attribute_const__;
 unsigned char bin2bcd(unsigned val) __attribute_const__;
 
-#define BCD2BIN(val)	bcd2bin(val)
-#define BIN2BCD(val)	bin2bcd(val)
-
-/* backwards compat */
-#define BCD_TO_BIN(val) ((val)=BCD2BIN(val))
-#define BIN_TO_BCD(val) ((val)=BIN2BCD(val))
-
 #endif /* _BCD_H */
diff --git a/include/linux/binfmts.h b/include/linux/binfmts.h
index 826f62350805..6cbfbe297180 100644
--- a/include/linux/binfmts.h
+++ b/include/linux/binfmts.h
@@ -35,12 +35,20 @@ struct linux_binprm{
 	struct mm_struct *mm;
 	unsigned long p; /* current top of mem */
 	unsigned int sh_bang:1,
-		     misc_bang:1;
+		misc_bang:1,
+		cred_prepared:1,/* true if creds already prepared (multiple
+				 * preps happen for interpreters) */
+		cap_effective:1;/* true if has elevated effective capabilities,
+				 * false if not; except for init which inherits
+				 * its parent's caps anyway */
+#ifdef __alpha__
+	unsigned int taso:1;
+#endif
+	unsigned int recursion_depth;
 	struct file * file;
-	int e_uid, e_gid;
-	kernel_cap_t cap_post_exec_permitted;
-	bool cap_effective;
-	void *security;
+	struct cred *cred;	/* new credentials */
+	int unsafe;		/* how unsafe this exec is (mask of LSM_UNSAFE_*) */
+	unsigned int per_clear;	/* bits to clear in current->personality */
 	int argc, envc;
 	char * filename;	/* Name of binary as seen by procps */
 	char * interp;		/* Name of the binary really executed. Most
@@ -58,6 +66,7 @@ struct linux_binprm{
 #define BINPRM_FLAGS_EXECFD_BIT 1
 #define BINPRM_FLAGS_EXECFD (1 << BINPRM_FLAGS_EXECFD_BIT)
 
+#define BINPRM_MAX_RECURSION 4
 
 /*
  * This structure defines the functions that are used to load the binary formats that
@@ -96,7 +105,7 @@ extern int setup_arg_pages(struct linux_binprm * bprm,
 			   int executable_stack);
 extern int bprm_mm_init(struct linux_binprm *bprm);
 extern int copy_strings_kernel(int argc,char ** argv,struct linux_binprm *bprm);
-extern void compute_creds(struct linux_binprm *binprm);
+extern void install_exec_creds(struct linux_binprm *bprm);
 extern int do_coredump(long signr, int exit_code, struct pt_regs * regs);
 extern int set_binfmt(struct linux_binfmt *new);
 extern void free_bprm(struct linux_binprm *);
diff --git a/include/linux/bio.h b/include/linux/bio.h
index ff5b4cf9e2da..18462c5b8fff 100644
--- a/include/linux/bio.h
+++ b/include/linux/bio.h
@@ -79,14 +79,22 @@ struct bio {
 
 	unsigned int		bi_size;	/* residual I/O count */
 
+	/*
+	 * To keep track of the max segment size, we account for the
+	 * sizes of the first and last mergeable segments in this bio.
+	 */
+	unsigned int		bi_seg_front_size;
+	unsigned int		bi_seg_back_size;
+
 	unsigned int		bi_max_vecs;	/* max bvl_vecs we can hold */
 
 	unsigned int		bi_comp_cpu;	/* completion CPU */
 
+	atomic_t		bi_cnt;		/* pin count */
+
 	struct bio_vec		*bi_io_vec;	/* the actual vec list */
 
 	bio_end_io_t		*bi_end_io;
-	atomic_t		bi_cnt;		/* pin count */
 
 	void			*bi_private;
 #if defined(CONFIG_BLK_DEV_INTEGRITY)
@@ -94,6 +102,13 @@ struct bio {
 #endif
 
 	bio_destructor_t	*bi_destructor;	/* destructor */
+
+	/*
+	 * We can inline a number of vecs at the end of the bio, to avoid
+	 * double allocations for a small number of bio_vecs. This member
+	 * MUST obviously be kept at the very end of the bio.
+	 */
+	struct bio_vec		bi_inline_vecs[0];
 };
 
 /*
@@ -110,6 +125,7 @@ struct bio {
 #define BIO_CPU_AFFINE	8	/* complete bio on same CPU as submitted */
 #define BIO_NULL_MAPPED 9	/* contains invalid user pages */
 #define BIO_FS_INTEGRITY 10	/* fs owns integrity data, not block layer */
+#define BIO_QUIET	11	/* Make BIO Quiet */
 #define bio_flagged(bio, flag)	((bio)->bi_flags & (1 << (flag)))
 
 /*
@@ -129,25 +145,30 @@ struct bio {
  * bit 2 -- barrier
  *	Insert a serialization point in the IO queue, forcing previously
  *	submitted IO to be completed before this oen is issued.
- * bit 3 -- fail fast, don't want low level driver retries
- * bit 4 -- synchronous I/O hint: the block layer will unplug immediately
+ * bit 3 -- synchronous I/O hint: the block layer will unplug immediately
  *	Note that this does NOT indicate that the IO itself is sync, just
  *	that the block layer will not postpone issue of this IO by plugging.
- * bit 5 -- metadata request
+ * bit 4 -- metadata request
  *	Used for tracing to differentiate metadata and data IO. May also
  *	get some preferential treatment in the IO scheduler
- * bit 6 -- discard sectors
+ * bit 5 -- discard sectors
  *	Informs the lower level device that this range of sectors is no longer
  *	used by the file system and may thus be freed by the device. Used
  *	for flash based storage.
+ * bit 6 -- fail fast device errors
+ * bit 7 -- fail fast transport errors
+ * bit 8 -- fail fast driver errors
+ *	Don't want driver retries for any fast fail whatever the reason.
  */
 #define BIO_RW		0	/* Must match RW in req flags (blkdev.h) */
 #define BIO_RW_AHEAD	1	/* Must match FAILFAST in req flags */
 #define BIO_RW_BARRIER	2
-#define BIO_RW_FAILFAST	3
-#define BIO_RW_SYNC	4
-#define BIO_RW_META	5
-#define BIO_RW_DISCARD	6
+#define BIO_RW_SYNC	3
+#define BIO_RW_META	4
+#define BIO_RW_DISCARD	5
+#define BIO_RW_FAILFAST_DEV		6
+#define BIO_RW_FAILFAST_TRANSPORT	7
+#define BIO_RW_FAILFAST_DRIVER		8
 
 /*
  * upper 16 bits of bi_rw define the io priority of this bio
@@ -174,7 +195,10 @@ struct bio {
 #define bio_sectors(bio)	((bio)->bi_size >> 9)
 #define bio_barrier(bio)	((bio)->bi_rw & (1 << BIO_RW_BARRIER))
 #define bio_sync(bio)		((bio)->bi_rw & (1 << BIO_RW_SYNC))
-#define bio_failfast(bio)	((bio)->bi_rw & (1 << BIO_RW_FAILFAST))
+#define bio_failfast_dev(bio)	((bio)->bi_rw &	(1 << BIO_RW_FAILFAST_DEV))
+#define bio_failfast_transport(bio)	\
+	((bio)->bi_rw & (1 << BIO_RW_FAILFAST_TRANSPORT))
+#define bio_failfast_driver(bio) ((bio)->bi_rw & (1 << BIO_RW_FAILFAST_DRIVER))
 #define bio_rw_ahead(bio)	((bio)->bi_rw & (1 << BIO_RW_AHEAD))
 #define bio_rw_meta(bio)	((bio)->bi_rw & (1 << BIO_RW_META))
 #define bio_discard(bio)	((bio)->bi_rw & (1 << BIO_RW_DISCARD))
@@ -196,6 +220,11 @@ static inline void *bio_data(struct bio *bio)
 	return NULL;
 }
 
+static inline int bio_has_allocated_vec(struct bio *bio)
+{
+	return bio->bi_io_vec && bio->bi_io_vec != bio->bi_inline_vecs;
+}
+
 /*
  * will die
  */
@@ -221,12 +250,16 @@ static inline void *bio_data(struct bio *bio)
 #define __BVEC_END(bio)		bio_iovec_idx((bio), (bio)->bi_vcnt - 1)
 #define __BVEC_START(bio)	bio_iovec_idx((bio), (bio)->bi_idx)
 
+/* Default implementation of BIOVEC_PHYS_MERGEABLE */
+#define __BIOVEC_PHYS_MERGEABLE(vec1, vec2)	\
+	((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
+
 /*
  * allow arch override, for eg virtualized architectures (put in asm/io.h)
  */
 #ifndef BIOVEC_PHYS_MERGEABLE
 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2)	\
-	((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
+	__BIOVEC_PHYS_MERGEABLE(vec1, vec2)
 #endif
 
 #define __BIO_SEG_BOUNDARY(addr1, addr2, mask) \
@@ -313,7 +346,7 @@ struct bio_pair {
 extern struct bio_pair *bio_split(struct bio *bi, int first_sectors);
 extern void bio_pair_release(struct bio_pair *dbio);
 
-extern struct bio_set *bioset_create(int, int);
+extern struct bio_set *bioset_create(unsigned int, unsigned int);
 extern void bioset_free(struct bio_set *);
 
 extern struct bio *bio_alloc(gfp_t, int);
@@ -358,6 +391,7 @@ extern struct bio *bio_copy_user_iov(struct request_queue *,
 extern int bio_uncopy_user(struct bio *);
 void zero_fill_bio(struct bio *bio);
 extern struct bio_vec *bvec_alloc_bs(gfp_t, int, unsigned long *, struct bio_set *);
+extern void bvec_free_bs(struct bio_set *, struct bio_vec *, unsigned int);
 extern unsigned int bvec_nr_vecs(unsigned short idx);
 
 /*
@@ -376,13 +410,17 @@ static inline void bio_set_completion_cpu(struct bio *bio, unsigned int cpu)
  */
 #define BIO_POOL_SIZE 2
 #define BIOVEC_NR_POOLS 6
+#define BIOVEC_MAX_IDX	(BIOVEC_NR_POOLS - 1)
 
 struct bio_set {
+	struct kmem_cache *bio_slab;
+	unsigned int front_pad;
+
 	mempool_t *bio_pool;
 #if defined(CONFIG_BLK_DEV_INTEGRITY)
 	mempool_t *bio_integrity_pool;
 #endif
-	mempool_t *bvec_pools[BIOVEC_NR_POOLS];
+	mempool_t *bvec_pool;
 };
 
 struct biovec_slab {
@@ -392,6 +430,7 @@ struct biovec_slab {
 };
 
 extern struct bio_set *fs_bio_set;
+extern struct biovec_slab bvec_slabs[BIOVEC_NR_POOLS] __read_mostly;
 
 /*
  * a small number of entries is fine, not going to be performance critical.
diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h
index 89781fd48859..a08c33a26ca9 100644
--- a/include/linux/bitmap.h
+++ b/include/linux/bitmap.h
@@ -110,7 +110,6 @@ extern int __bitmap_weight(const unsigned long *bitmap, int bits);
 
 extern int bitmap_scnprintf(char *buf, unsigned int len,
 			const unsigned long *src, int nbits);
-extern int bitmap_scnprintf_len(unsigned int nr_bits);
 extern int __bitmap_parse(const char *buf, unsigned int buflen, int is_user,
 			unsigned long *dst, int nbits);
 extern int bitmap_parse_user(const char __user *ubuf, unsigned int ulen,
@@ -130,6 +129,7 @@ extern void bitmap_fold(unsigned long *dst, const unsigned long *orig,
 extern int bitmap_find_free_region(unsigned long *bitmap, int bits, int order);
 extern void bitmap_release_region(unsigned long *bitmap, int pos, int order);
 extern int bitmap_allocate_region(unsigned long *bitmap, int pos, int order);
+extern void bitmap_copy_le(void *dst, const unsigned long *src, int nbits);
 
 #define BITMAP_LAST_WORD_MASK(nbits)					\
 (									\
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index a92d9e4ea96e..7035cec583b6 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -26,7 +26,6 @@ struct scsi_ioctl_command;
 
 struct request_queue;
 struct elevator_queue;
-typedef struct elevator_queue elevator_t;
 struct request_pm_state;
 struct blk_trace;
 struct request;
@@ -87,7 +86,9 @@ enum {
  */
 enum rq_flag_bits {
 	__REQ_RW,		/* not set, read. set, write */
-	__REQ_FAILFAST,		/* no low level driver retries */
+	__REQ_FAILFAST_DEV,	/* no driver retries of device errors */
+	__REQ_FAILFAST_TRANSPORT, /* no driver retries of transport errors */
+	__REQ_FAILFAST_DRIVER,	/* no driver retries of driver errors */
 	__REQ_DISCARD,		/* request to discard sectors */
 	__REQ_SORTED,		/* elevator knows about this request */
 	__REQ_SOFTBARRIER,	/* may not be passed by ioscheduler */
@@ -111,8 +112,10 @@ enum rq_flag_bits {
 };
 
 #define REQ_RW		(1 << __REQ_RW)
+#define REQ_FAILFAST_DEV	(1 << __REQ_FAILFAST_DEV)
+#define REQ_FAILFAST_TRANSPORT	(1 << __REQ_FAILFAST_TRANSPORT)
+#define REQ_FAILFAST_DRIVER	(1 << __REQ_FAILFAST_DRIVER)
 #define REQ_DISCARD	(1 << __REQ_DISCARD)
-#define REQ_FAILFAST	(1 << __REQ_FAILFAST)
 #define REQ_SORTED	(1 << __REQ_SORTED)
 #define REQ_SOFTBARRIER	(1 << __REQ_SOFTBARRIER)
 #define REQ_HARDBARRIER	(1 << __REQ_HARDBARRIER)
@@ -309,7 +312,7 @@ struct request_queue
 	 */
 	struct list_head	queue_head;
 	struct request		*last_merge;
-	elevator_t		*elevator;
+	struct elevator_queue	*elevator;
 
 	/*
 	 * the queue request freelist, one for reads and one for writes
@@ -445,6 +448,7 @@ struct request_queue
 #define QUEUE_FLAG_FAIL_IO     12	/* fake timeout */
 #define QUEUE_FLAG_STACKABLE   13	/* supports request stacking */
 #define QUEUE_FLAG_NONROT      14	/* non-rotational device (SSD) */
+#define QUEUE_FLAG_VIRT        QUEUE_FLAG_NONROT /* paravirt device */
 
 static inline int queue_is_locked(struct request_queue *q)
 {
@@ -518,22 +522,32 @@ enum {
 	 * TAG_FLUSH	: ordering by tag w/ pre and post flushes
 	 * TAG_FUA	: ordering by tag w/ pre flush and FUA write
 	 */
-	QUEUE_ORDERED_NONE	= 0x00,
-	QUEUE_ORDERED_DRAIN	= 0x01,
-	QUEUE_ORDERED_TAG	= 0x02,
-
-	QUEUE_ORDERED_PREFLUSH	= 0x10,
-	QUEUE_ORDERED_POSTFLUSH	= 0x20,
-	QUEUE_ORDERED_FUA	= 0x40,
-
-	QUEUE_ORDERED_DRAIN_FLUSH = QUEUE_ORDERED_DRAIN |
-			QUEUE_ORDERED_PREFLUSH | QUEUE_ORDERED_POSTFLUSH,
-	QUEUE_ORDERED_DRAIN_FUA	= QUEUE_ORDERED_DRAIN |
-			QUEUE_ORDERED_PREFLUSH | QUEUE_ORDERED_FUA,
-	QUEUE_ORDERED_TAG_FLUSH	= QUEUE_ORDERED_TAG |
-			QUEUE_ORDERED_PREFLUSH | QUEUE_ORDERED_POSTFLUSH,
-	QUEUE_ORDERED_TAG_FUA	= QUEUE_ORDERED_TAG |
-			QUEUE_ORDERED_PREFLUSH | QUEUE_ORDERED_FUA,
+	QUEUE_ORDERED_BY_DRAIN		= 0x01,
+	QUEUE_ORDERED_BY_TAG		= 0x02,
+	QUEUE_ORDERED_DO_PREFLUSH	= 0x10,
+	QUEUE_ORDERED_DO_BAR		= 0x20,
+	QUEUE_ORDERED_DO_POSTFLUSH	= 0x40,
+	QUEUE_ORDERED_DO_FUA		= 0x80,
+
+	QUEUE_ORDERED_NONE		= 0x00,
+
+	QUEUE_ORDERED_DRAIN		= QUEUE_ORDERED_BY_DRAIN |
+					  QUEUE_ORDERED_DO_BAR,
+	QUEUE_ORDERED_DRAIN_FLUSH	= QUEUE_ORDERED_DRAIN |
+					  QUEUE_ORDERED_DO_PREFLUSH |
+					  QUEUE_ORDERED_DO_POSTFLUSH,
+	QUEUE_ORDERED_DRAIN_FUA		= QUEUE_ORDERED_DRAIN |
+					  QUEUE_ORDERED_DO_PREFLUSH |
+					  QUEUE_ORDERED_DO_FUA,
+
+	QUEUE_ORDERED_TAG		= QUEUE_ORDERED_BY_TAG |
+					  QUEUE_ORDERED_DO_BAR,
+	QUEUE_ORDERED_TAG_FLUSH		= QUEUE_ORDERED_TAG |
+					  QUEUE_ORDERED_DO_PREFLUSH |
+					  QUEUE_ORDERED_DO_POSTFLUSH,
+	QUEUE_ORDERED_TAG_FUA		= QUEUE_ORDERED_TAG |
+					  QUEUE_ORDERED_DO_PREFLUSH |
+					  QUEUE_ORDERED_DO_FUA,
 
 	/*
 	 * Ordered operation sequence
@@ -560,7 +574,12 @@ enum {
 #define blk_special_request(rq)	((rq)->cmd_type == REQ_TYPE_SPECIAL)
 #define blk_sense_request(rq)	((rq)->cmd_type == REQ_TYPE_SENSE)
 
-#define blk_noretry_request(rq)	((rq)->cmd_flags & REQ_FAILFAST)
+#define blk_failfast_dev(rq)	((rq)->cmd_flags & REQ_FAILFAST_DEV)
+#define blk_failfast_transport(rq) ((rq)->cmd_flags & REQ_FAILFAST_TRANSPORT)
+#define blk_failfast_driver(rq)	((rq)->cmd_flags & REQ_FAILFAST_DRIVER)
+#define blk_noretry_request(rq)	(blk_failfast_dev(rq) ||	\
+				 blk_failfast_transport(rq) ||	\
+				 blk_failfast_driver(rq))
 #define blk_rq_started(rq)	((rq)->cmd_flags & REQ_STARTED)
 
 #define blk_account_rq(rq)	(blk_rq_started(rq) && (blk_fs_request(rq) || blk_discard_rq(rq))) 
@@ -576,7 +595,6 @@ enum {
 #define blk_fua_rq(rq)		((rq)->cmd_flags & REQ_FUA)
 #define blk_discard_rq(rq)	((rq)->cmd_flags & REQ_DISCARD)
 #define blk_bidi_rq(rq)		((rq)->next_rq != NULL)
-#define blk_empty_barrier(rq)	(blk_barrier_rq(rq) && blk_fs_request(rq) && !(rq)->hard_nr_sectors)
 /* rq->queuelist of dequeued request must be list_empty() */
 #define blk_queued_rq(rq)	(!list_empty(&(rq)->queuelist))
 
@@ -653,6 +671,7 @@ extern unsigned long blk_max_low_pfn, blk_max_pfn;
  * default timeout for SG_IO if none specified
  */
 #define BLK_DEFAULT_SG_TIMEOUT	(60 * HZ)
+#define BLK_MIN_SG_TIMEOUT	(7 * HZ)
 
 #ifdef CONFIG_BOUNCE
 extern int init_emergency_isa_pool(void);
@@ -708,10 +727,10 @@ extern void blk_plug_device(struct request_queue *);
 extern void blk_plug_device_unlocked(struct request_queue *);
 extern int blk_remove_plug(struct request_queue *);
 extern void blk_recount_segments(struct request_queue *, struct bio *);
-extern int scsi_cmd_ioctl(struct file *, struct request_queue *,
-			  struct gendisk *, unsigned int, void __user *);
-extern int sg_scsi_ioctl(struct file *, struct request_queue *,
-		struct gendisk *, struct scsi_ioctl_command __user *);
+extern int scsi_cmd_ioctl(struct request_queue *, struct gendisk *, fmode_t,
+			  unsigned int, void __user *);
+extern int sg_scsi_ioctl(struct request_queue *, struct gendisk *, fmode_t,
+			 struct scsi_ioctl_command __user *);
 
 /*
  * Temporary export, until SCSI gets fixed up.
@@ -777,6 +796,8 @@ static inline void blk_run_address_space(struct address_space *mapping)
 		blk_run_backing_dev(mapping->backing_dev_info, NULL);
 }
 
+extern void blkdev_dequeue_request(struct request *req);
+
 /*
  * blk_end_request() and friends.
  * __blk_end_request() and end_request() must be called with
@@ -811,11 +832,6 @@ extern void blk_update_request(struct request *rq, int error,
 extern unsigned int blk_rq_bytes(struct request *rq);
 extern unsigned int blk_rq_cur_bytes(struct request *rq);
 
-static inline void blkdev_dequeue_request(struct request *req)
-{
-	elv_dequeue_request(req->q, req);
-}
-
 /*
  * Access functions for manipulating queue properties
  */
@@ -848,15 +864,14 @@ extern void blk_queue_rq_timed_out(struct request_queue *, rq_timed_out_fn *);
 extern void blk_queue_rq_timeout(struct request_queue *, unsigned int);
 extern struct backing_dev_info *blk_get_backing_dev_info(struct block_device *bdev);
 extern int blk_queue_ordered(struct request_queue *, unsigned, prepare_flush_fn *);
-extern int blk_do_ordered(struct request_queue *, struct request **);
+extern bool blk_do_ordered(struct request_queue *, struct request **);
 extern unsigned blk_ordered_cur_seq(struct request_queue *);
 extern unsigned blk_ordered_req_seq(struct request *);
-extern void blk_ordered_complete_seq(struct request_queue *, unsigned, int);
+extern bool blk_ordered_complete_seq(struct request_queue *, unsigned, int);
 
 extern int blk_rq_map_sg(struct request_queue *, struct request *, struct scatterlist *);
 extern void blk_dump_rq_flags(struct request *, char *);
 extern void generic_unplug_device(struct request_queue *);
-extern void __generic_unplug_device(struct request_queue *);
 extern long nr_blockdev_pages(void);
 
 int blk_get_queue(struct request_queue *);
@@ -902,7 +917,8 @@ static inline int sb_issue_discard(struct super_block *sb,
 * command filter functions
 */
 extern int blk_verify_command(struct blk_cmd_filter *filter,
-			      unsigned char *cmd, int has_write_perm);
+			      unsigned char *cmd, fmode_t has_write_perm);
+extern void blk_unregister_filter(struct gendisk *disk);
 extern void blk_set_cmd_filter_defaults(struct blk_cmd_filter *filter);
 
 #define MAX_PHYS_SEGMENTS 128
@@ -912,6 +928,8 @@ extern void blk_set_cmd_filter_defaults(struct blk_cmd_filter *filter);
 
 #define MAX_SEGMENT_SIZE	65536
 
+#define BLK_SEG_BOUNDARY_MASK	0xFFFFFFFFUL
+
 #define blkdev_entry_to_request(entry) list_entry((entry), struct request, queuelist)
 
 static inline int queue_hardsect_size(struct request_queue *q)
@@ -968,7 +986,6 @@ static inline void put_dev_sector(Sector p)
 
 struct work_struct;
 int kblockd_schedule_work(struct request_queue *q, struct work_struct *work);
-void kblockd_flush_work(struct work_struct *work);
 
 #define MODULE_ALIAS_BLOCKDEV(major,minor) \
 	MODULE_ALIAS("block-major-" __stringify(major) "-" __stringify(minor))
@@ -1048,6 +1065,22 @@ static inline int blk_integrity_rq(struct request *rq)
 
 #endif /* CONFIG_BLK_DEV_INTEGRITY */
 
+struct block_device_operations {
+	int (*open) (struct block_device *, fmode_t);
+	int (*release) (struct gendisk *, fmode_t);
+	int (*locked_ioctl) (struct block_device *, fmode_t, unsigned, unsigned long);
+	int (*ioctl) (struct block_device *, fmode_t, unsigned, unsigned long);
+	int (*compat_ioctl) (struct block_device *, fmode_t, unsigned, unsigned long);
+	int (*direct_access) (struct block_device *, sector_t,
+						void **, unsigned long *);
+	int (*media_changed) (struct gendisk *);
+	int (*revalidate_disk) (struct gendisk *);
+	int (*getgeo)(struct block_device *, struct hd_geometry *);
+	struct module *owner;
+};
+
+extern int __blkdev_driver_ioctl(struct block_device *, fmode_t, unsigned int,
+				 unsigned long);
 #else /* CONFIG_BLOCK */
 /*
  * stubs for when the block layer is configured out
diff --git a/include/linux/blktrace_api.h b/include/linux/blktrace_api.h
index 3a31eb506164..1dba3493d520 100644
--- a/include/linux/blktrace_api.h
+++ b/include/linux/blktrace_api.h
@@ -24,6 +24,7 @@ enum blktrace_cat {
 	BLK_TC_AHEAD	= 1 << 11,	/* readahead */
 	BLK_TC_META	= 1 << 12,	/* metadata */
 	BLK_TC_DISCARD	= 1 << 13,	/* discard requests */
+	BLK_TC_DRV_DATA	= 1 << 14,	/* binary per-driver data */
 
 	BLK_TC_END	= 1 << 15,	/* only 16-bits, reminder */
 };
@@ -51,6 +52,7 @@ enum blktrace_act {
 	__BLK_TA_BOUNCE,		/* bio was bounced */
 	__BLK_TA_REMAP,			/* bio was remapped */
 	__BLK_TA_ABORT,			/* request aborted */
+	__BLK_TA_DRV_DATA,		/* driver-specific binary data */
 };
 
 /*
@@ -82,6 +84,7 @@ enum blktrace_notify {
 #define BLK_TA_BOUNCE		(__BLK_TA_BOUNCE)
 #define BLK_TA_REMAP		(__BLK_TA_REMAP | BLK_TC_ACT(BLK_TC_QUEUE))
 #define BLK_TA_ABORT		(__BLK_TA_ABORT | BLK_TC_ACT(BLK_TC_QUEUE))
+#define BLK_TA_DRV_DATA	(__BLK_TA_DRV_DATA | BLK_TC_ACT(BLK_TC_DRV_DATA))
 
 #define BLK_TN_PROCESS		(__BLK_TN_PROCESS | BLK_TC_ACT(BLK_TC_NOTIFY))
 #define BLK_TN_TIMESTAMP	(__BLK_TN_TIMESTAMP | BLK_TC_ACT(BLK_TC_NOTIFY))
@@ -157,7 +160,6 @@ struct blk_trace {
 
 extern int blk_trace_ioctl(struct block_device *, unsigned, char __user *);
 extern void blk_trace_shutdown(struct request_queue *);
-extern void __blk_add_trace(struct blk_trace *, sector_t, int, int, u32, int, int, void *);
 extern int do_blk_trace_setup(struct request_queue *q,
 	char *name, dev_t dev, struct blk_user_trace_setup *buts);
 extern void __trace_note_message(struct blk_trace *, const char *fmt, ...);
@@ -183,140 +185,8 @@ extern void __trace_note_message(struct blk_trace *, const char *fmt, ...);
 	} while (0)
 #define BLK_TN_MAX_MSG		128
 
-/**
- * blk_add_trace_rq - Add a trace for a request oriented action
- * @q:		queue the io is for
- * @rq:		the source request
- * @what:	the action
- *
- * Description:
- *     Records an action against a request. Will log the bio offset + size.
- *
- **/
-static inline void blk_add_trace_rq(struct request_queue *q, struct request *rq,
-				    u32 what)
-{
-	struct blk_trace *bt = q->blk_trace;
-	int rw = rq->cmd_flags & 0x03;
-
-	if (likely(!bt))
-		return;
-
-	if (blk_discard_rq(rq))
-		rw |= (1 << BIO_RW_DISCARD);
-
-	if (blk_pc_request(rq)) {
-		what |= BLK_TC_ACT(BLK_TC_PC);
-		__blk_add_trace(bt, 0, rq->data_len, rw, what, rq->errors, sizeof(rq->cmd), rq->cmd);
-	} else  {
-		what |= BLK_TC_ACT(BLK_TC_FS);
-		__blk_add_trace(bt, rq->hard_sector, rq->hard_nr_sectors << 9, rw, what, rq->errors, 0, NULL);
-	}
-}
-
-/**
- * blk_add_trace_bio - Add a trace for a bio oriented action
- * @q:		queue the io is for
- * @bio:	the source bio
- * @what:	the action
- *
- * Description:
- *     Records an action against a bio. Will log the bio offset + size.
- *
- **/
-static inline void blk_add_trace_bio(struct request_queue *q, struct bio *bio,
-				     u32 what)
-{
-	struct blk_trace *bt = q->blk_trace;
-
-	if (likely(!bt))
-		return;
-
-	__blk_add_trace(bt, bio->bi_sector, bio->bi_size, bio->bi_rw, what, !bio_flagged(bio, BIO_UPTODATE), 0, NULL);
-}
-
-/**
- * blk_add_trace_generic - Add a trace for a generic action
- * @q:		queue the io is for
- * @bio:	the source bio
- * @rw:		the data direction
- * @what:	the action
- *
- * Description:
- *     Records a simple trace
- *
- **/
-static inline void blk_add_trace_generic(struct request_queue *q,
-					 struct bio *bio, int rw, u32 what)
-{
-	struct blk_trace *bt = q->blk_trace;
-
-	if (likely(!bt))
-		return;
-
-	if (bio)
-		blk_add_trace_bio(q, bio, what);
-	else
-		__blk_add_trace(bt, 0, 0, rw, what, 0, 0, NULL);
-}
-
-/**
- * blk_add_trace_pdu_int - Add a trace for a bio with an integer payload
- * @q:		queue the io is for
- * @what:	the action
- * @bio:	the source bio
- * @pdu:	the integer payload
- *
- * Description:
- *     Adds a trace with some integer payload. This might be an unplug
- *     option given as the action, with the depth at unplug time given
- *     as the payload
- *
- **/
-static inline void blk_add_trace_pdu_int(struct request_queue *q, u32 what,
-					 struct bio *bio, unsigned int pdu)
-{
-	struct blk_trace *bt = q->blk_trace;
-	__be64 rpdu = cpu_to_be64(pdu);
-
-	if (likely(!bt))
-		return;
-
-	if (bio)
-		__blk_add_trace(bt, bio->bi_sector, bio->bi_size, bio->bi_rw, what, !bio_flagged(bio, BIO_UPTODATE), sizeof(rpdu), &rpdu);
-	else
-		__blk_add_trace(bt, 0, 0, 0, what, 0, sizeof(rpdu), &rpdu);
-}
-
-/**
- * blk_add_trace_remap - Add a trace for a remap operation
- * @q:		queue the io is for
- * @bio:	the source bio
- * @dev:	target device
- * @from:	source sector
- * @to:		target sector
- *
- * Description:
- *     Device mapper or raid target sometimes need to split a bio because
- *     it spans a stripe (or similar). Add a trace for that action.
- *
- **/
-static inline void blk_add_trace_remap(struct request_queue *q, struct bio *bio,
-				       dev_t dev, sector_t from, sector_t to)
-{
-	struct blk_trace *bt = q->blk_trace;
-	struct blk_io_trace_remap r;
-
-	if (likely(!bt))
-		return;
-
-	r.device = cpu_to_be32(dev);
-	r.device_from = cpu_to_be32(bio->bi_bdev->bd_dev);
-	r.sector = cpu_to_be64(to);
-
-	__blk_add_trace(bt, from, bio->bi_size, bio->bi_rw, BLK_TA_REMAP, !bio_flagged(bio, BIO_UPTODATE), sizeof(r), &r);
-}
-
+extern void blk_add_driver_data(struct request_queue *q, struct request *rq,
+				void *data, size_t len);
 extern int blk_trace_setup(struct request_queue *q, char *name, dev_t dev,
 			   char __user *arg);
 extern int blk_trace_startstop(struct request_queue *q, int start);
@@ -325,12 +195,8 @@ extern int blk_trace_remove(struct request_queue *q);
 #else /* !CONFIG_BLK_DEV_IO_TRACE */
 #define blk_trace_ioctl(bdev, cmd, arg)		(-ENOTTY)
 #define blk_trace_shutdown(q)			do { } while (0)
-#define blk_add_trace_rq(q, rq, what)		do { } while (0)
-#define blk_add_trace_bio(q, rq, what)		do { } while (0)
-#define blk_add_trace_generic(q, rq, rw, what)	do { } while (0)
-#define blk_add_trace_pdu_int(q, what, bio, pdu)	do { } while (0)
-#define blk_add_trace_remap(q, bio, dev, f, t)	do {} while (0)
 #define do_blk_trace_setup(q, name, dev, buts)	(-ENOTTY)
+#define blk_add_driver_data(q, rq, data, len)	do {} while (0)
 #define blk_trace_setup(q, name, dev, arg)	(-ENOTTY)
 #define blk_trace_startstop(q, start)		(-ENOTTY)
 #define blk_trace_remove(q)			(-ENOTTY)
diff --git a/include/linux/bottom_half.h b/include/linux/bottom_half.h
index 777dbf695d44..27b1bcffe408 100644
--- a/include/linux/bottom_half.h
+++ b/include/linux/bottom_half.h
@@ -2,7 +2,6 @@
 #define _LINUX_BH_H
 
 extern void local_bh_disable(void);
-extern void __local_bh_enable(void);
 extern void _local_bh_enable(void);
 extern void local_bh_enable(void);
 extern void local_bh_enable_ip(unsigned long ip);
diff --git a/include/linux/buffer_head.h b/include/linux/buffer_head.h
index eadaab44015f..8605f8a74df9 100644
--- a/include/linux/buffer_head.h
+++ b/include/linux/buffer_head.h
@@ -35,6 +35,7 @@ enum bh_state_bits {
 	BH_Ordered,	/* ordered write */
 	BH_Eopnotsupp,	/* operation not supported (barrier) */
 	BH_Unwritten,	/* Buffer is allocated on disk but not written */
+	BH_Quiet,	/* Buffer Error Prinks to be quiet */
 
 	BH_PrivateStart,/* not a state bit, but the first bit available
 			 * for private allocation by other entities
@@ -322,7 +323,7 @@ static inline void wait_on_buffer(struct buffer_head *bh)
 
 static inline int trylock_buffer(struct buffer_head *bh)
 {
-	return likely(!test_and_set_bit(BH_Lock, &bh->b_state));
+	return likely(!test_and_set_bit_lock(BH_Lock, &bh->b_state));
 }
 
 static inline void lock_buffer(struct buffer_head *bh)
diff --git a/include/linux/byteorder/Kbuild b/include/linux/byteorder/Kbuild
index 1133d5f9d818..fbaa7f9cee32 100644
--- a/include/linux/byteorder/Kbuild
+++ b/include/linux/byteorder/Kbuild
@@ -1,3 +1,4 @@
 unifdef-y += big_endian.h
 unifdef-y += little_endian.h
 unifdef-y += swab.h
+unifdef-y += swabb.h
diff --git a/include/linux/byteorder/big_endian.h b/include/linux/byteorder/big_endian.h
index 44f95b92393b..1cba3f3efe5f 100644
--- a/include/linux/byteorder/big_endian.h
+++ b/include/linux/byteorder/big_endian.h
@@ -10,6 +10,7 @@
 
 #include <linux/types.h>
 #include <linux/byteorder/swab.h>
+#include <linux/byteorder/swabb.h>
 
 #define __constant_htonl(x) ((__force __be32)(__u32)(x))
 #define __constant_ntohl(x) ((__force __u32)(__be32)(x))
diff --git a/include/linux/byteorder/little_endian.h b/include/linux/byteorder/little_endian.h
index 4cc170a31762..cedc1b5a289c 100644
--- a/include/linux/byteorder/little_endian.h
+++ b/include/linux/byteorder/little_endian.h
@@ -10,6 +10,7 @@
 
 #include <linux/types.h>
 #include <linux/byteorder/swab.h>
+#include <linux/byteorder/swabb.h>
 
 #define __constant_htonl(x) ((__force __be32)___constant_swab32((x)))
 #define __constant_ntohl(x) ___constant_swab32((__force __be32)(x))
diff --git a/include/linux/c2port.h b/include/linux/c2port.h
new file mode 100644
index 000000000000..7b5a2388ba67
--- /dev/null
+++ b/include/linux/c2port.h
@@ -0,0 +1,65 @@
+/*
+ *  Silicon Labs C2 port Linux support
+ *
+ *  Copyright (c) 2007 Rodolfo Giometti <giometti@linux.it>
+ *  Copyright (c) 2007 Eurotech S.p.A. <info@eurotech.it>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation
+ */
+
+#include <linux/device.h>
+
+#define C2PORT_NAME_LEN			32
+
+/*
+ * C2 port basic structs
+ */
+
+/* Main struct */
+struct c2port_ops;
+struct c2port_device {
+	unsigned int access:1;
+	unsigned int flash_access:1;
+
+	int id;
+	char name[C2PORT_NAME_LEN];
+	struct c2port_ops *ops;
+	struct mutex mutex;		/* prevent races during read/write */
+
+	struct device *dev;
+
+	void *private_data;
+};
+
+/* Basic operations */
+struct c2port_ops {
+	/* Flash layout */
+	unsigned short block_size;	/* flash block size in bytes */
+	unsigned short blocks_num;	/* flash blocks number */
+
+	/* Enable or disable the access to C2 port */
+	void (*access)(struct c2port_device *dev, int status);
+
+	/* Set C2D data line as input/output */
+	void (*c2d_dir)(struct c2port_device *dev, int dir);
+
+	/* Read/write C2D data line */
+	int (*c2d_get)(struct c2port_device *dev);
+	void (*c2d_set)(struct c2port_device *dev, int status);
+
+	/* Write C2CK clock line */
+	void (*c2ck_set)(struct c2port_device *dev, int status);
+};
+
+/*
+ * Exported functions
+ */
+
+#define to_class_dev(obj) container_of((obj), struct class_device, kobj)
+#define to_c2port_device(obj) container_of((obj), struct c2port_device, class)
+
+extern struct c2port_device *c2port_device_register(char *name,
+					struct c2port_ops *ops, void *devdata);
+extern void c2port_device_unregister(struct c2port_device *dev);
diff --git a/include/linux/can/core.h b/include/linux/can/core.h
index e9ca210ffa5b..f50785ad4781 100644
--- a/include/linux/can/core.h
+++ b/include/linux/can/core.h
@@ -19,7 +19,7 @@
 #include <linux/skbuff.h>
 #include <linux/netdevice.h>
 
-#define CAN_VERSION "20071116"
+#define CAN_VERSION "20081130"
 
 /* increment this number each time you change some user-space interface */
 #define CAN_ABI_VERSION "8"
diff --git a/include/linux/capability.h b/include/linux/capability.h
index 9d1fe30b6f6c..e22f48c2a46f 100644
--- a/include/linux/capability.h
+++ b/include/linux/capability.h
@@ -53,6 +53,7 @@ typedef struct __user_cap_data_struct {
 #define XATTR_NAME_CAPS XATTR_SECURITY_PREFIX XATTR_CAPS_SUFFIX
 
 #define VFS_CAP_REVISION_MASK	0xFF000000
+#define VFS_CAP_REVISION_SHIFT	24
 #define VFS_CAP_FLAGS_MASK	~VFS_CAP_REVISION_MASK
 #define VFS_CAP_FLAGS_EFFECTIVE	0x000001
 
@@ -68,6 +69,9 @@ typedef struct __user_cap_data_struct {
 #define VFS_CAP_U32             VFS_CAP_U32_2
 #define VFS_CAP_REVISION	VFS_CAP_REVISION_2
 
+#ifdef CONFIG_SECURITY_FILE_CAPABILITIES
+extern int file_caps_enabled;
+#endif
 
 struct vfs_cap_data {
 	__le32 magic_etc;            /* Little endian */
@@ -96,6 +100,13 @@ typedef struct kernel_cap_struct {
 	__u32 cap[_KERNEL_CAPABILITY_U32S];
 } kernel_cap_t;
 
+/* exact same as vfs_cap_data but in cpu endian and always filled completely */
+struct cpu_vfs_cap_data {
+	__u32 magic_etc;
+	kernel_cap_t permitted;
+	kernel_cap_t inheritable;
+};
+
 #define _USER_CAP_HEADER_SIZE  (sizeof(struct __user_cap_header_struct))
 #define _KERNEL_CAP_T_SIZE     (sizeof(kernel_cap_t))
 
@@ -454,6 +465,13 @@ static inline int cap_isclear(const kernel_cap_t a)
 	return 1;
 }
 
+/*
+ * Check if "a" is a subset of "set".
+ * return 1 if ALL of the capabilities in "a" are also in "set"
+ *	cap_issubset(0101, 1111) will return 1
+ * return 0 if ANY of the capabilities in "a" are not in "set"
+ *	cap_issubset(1111, 0101) will return 0
+ */
 static inline int cap_issubset(const kernel_cap_t a, const kernel_cap_t set)
 {
 	kernel_cap_t dest;
@@ -501,8 +519,6 @@ extern const kernel_cap_t __cap_empty_set;
 extern const kernel_cap_t __cap_full_set;
 extern const kernel_cap_t __cap_init_eff_set;
 
-kernel_cap_t cap_set_effective(const kernel_cap_t pE_new);
-
 /**
  * has_capability - Determine if a task has a superior capability available
  * @t: The task in question
@@ -514,9 +530,14 @@ kernel_cap_t cap_set_effective(const kernel_cap_t pE_new);
  * Note that this does not set PF_SUPERPRIV on the task.
  */
 #define has_capability(t, cap) (security_capable((t), (cap)) == 0)
+#define has_capability_noaudit(t, cap) (security_capable_noaudit((t), (cap)) == 0)
 
 extern int capable(int cap);
 
+/* audit system wants to get cap info from files as well */
+struct dentry;
+extern int get_vfs_caps_from_disk(const struct dentry *dentry, struct cpu_vfs_cap_data *cpu_caps);
+
 #endif /* __KERNEL__ */
 
 #endif /* !_LINUX_CAPABILITY_H */
diff --git a/include/linux/cdrom.h b/include/linux/cdrom.h
index 5db265ea60f6..0b49e08d3cb0 100644
--- a/include/linux/cdrom.h
+++ b/include/linux/cdrom.h
@@ -987,11 +987,11 @@ struct cdrom_device_ops {
 };
 
 /* the general block_device operations structure: */
-extern int cdrom_open(struct cdrom_device_info *cdi, struct inode *ip,
-			struct file *fp);
-extern int cdrom_release(struct cdrom_device_info *cdi, struct file *fp);
-extern int cdrom_ioctl(struct file *file, struct cdrom_device_info *cdi,
-		struct inode *ip, unsigned int cmd, unsigned long arg);
+extern int cdrom_open(struct cdrom_device_info *cdi, struct block_device *bdev,
+			fmode_t mode);
+extern void cdrom_release(struct cdrom_device_info *cdi, fmode_t mode);
+extern int cdrom_ioctl(struct cdrom_device_info *cdi, struct block_device *bdev,
+		       fmode_t mode, unsigned int cmd, unsigned long arg);
 extern int cdrom_media_changed(struct cdrom_device_info *);
 
 extern int register_cdrom(struct cdrom_device_info *cdi);
diff --git a/include/linux/cgroup.h b/include/linux/cgroup.h
index c98dd7cb7076..1164963c3a85 100644
--- a/include/linux/cgroup.h
+++ b/include/linux/cgroup.h
@@ -9,12 +9,12 @@
  */
 
 #include <linux/sched.h>
-#include <linux/kref.h>
 #include <linux/cpumask.h>
 #include <linux/nodemask.h>
 #include <linux/rcupdate.h>
 #include <linux/cgroupstats.h>
 #include <linux/prio_heap.h>
+#include <linux/rwsem.h>
 
 #ifdef CONFIG_CGROUPS
 
@@ -25,7 +25,6 @@ struct cgroup;
 
 extern int cgroup_init_early(void);
 extern int cgroup_init(void);
-extern void cgroup_init_smp(void);
 extern void cgroup_lock(void);
 extern bool cgroup_lock_live_group(struct cgroup *cgrp);
 extern void cgroup_unlock(void);
@@ -137,6 +136,15 @@ struct cgroup {
 	 * release_list_lock
 	 */
 	struct list_head release_list;
+
+	/* pids_mutex protects the fields below */
+	struct rw_semaphore pids_mutex;
+	/* Array of process ids in the cgroup */
+	pid_t *tasks_pids;
+	/* How many files are using the current tasks_pids array */
+	int pids_use_count;
+	/* Length of the current tasks_pids array */
+	int pids_length;
 };
 
 /* A css_set is a structure holding pointers to a set of
@@ -149,7 +157,7 @@ struct cgroup {
 struct css_set {
 
 	/* Reference count */
-	struct kref ref;
+	atomic_t refcount;
 
 	/*
 	 * List running through all cgroup groups in the same hash
@@ -326,7 +334,8 @@ struct cgroup_subsys {
 	 */
 	void (*mm_owner_changed)(struct cgroup_subsys *ss,
 					struct cgroup *old,
-					struct cgroup *new);
+					struct cgroup *new,
+					struct task_struct *p);
 	int subsys_id;
 	int active;
 	int disabled;
@@ -338,8 +347,6 @@ struct cgroup_subsys {
 	struct cgroupfs_root *root;
 
 	struct list_head sibling;
-
-	void *private;
 };
 
 #define SUBSYS(_x) extern struct cgroup_subsys _x ## _subsys;
@@ -393,11 +400,13 @@ void cgroup_iter_end(struct cgroup *cgrp, struct cgroup_iter *it);
 int cgroup_scan_tasks(struct cgroup_scanner *scan);
 int cgroup_attach_task(struct cgroup *, struct task_struct *);
 
+void cgroup_mm_owner_callbacks(struct task_struct *old,
+			       struct task_struct *new);
+
 #else /* !CONFIG_CGROUPS */
 
 static inline int cgroup_init_early(void) { return 0; }
 static inline int cgroup_init(void) { return 0; }
-static inline void cgroup_init_smp(void) {}
 static inline void cgroup_fork(struct task_struct *p) {}
 static inline void cgroup_fork_callbacks(struct task_struct *p) {}
 static inline void cgroup_post_fork(struct task_struct *p) {}
@@ -411,15 +420,9 @@ static inline int cgroupstats_build(struct cgroupstats *stats,
 	return -EINVAL;
 }
 
+static inline void cgroup_mm_owner_callbacks(struct task_struct *old,
+					     struct task_struct *new) {}
+
 #endif /* !CONFIG_CGROUPS */
 
-#ifdef CONFIG_MM_OWNER
-extern void
-cgroup_mm_owner_callbacks(struct task_struct *old, struct task_struct *new);
-#else /* !CONFIG_MM_OWNER */
-static inline void
-cgroup_mm_owner_callbacks(struct task_struct *old, struct task_struct *new)
-{
-}
-#endif /* CONFIG_MM_OWNER */
 #endif /* _LINUX_CGROUP_H */
diff --git a/include/linux/cgroup_subsys.h b/include/linux/cgroup_subsys.h
index e2877454ec82..9c8d31bacf46 100644
--- a/include/linux/cgroup_subsys.h
+++ b/include/linux/cgroup_subsys.h
@@ -48,3 +48,15 @@ SUBSYS(devices)
 #endif
 
 /* */
+
+#ifdef CONFIG_CGROUP_FREEZER
+SUBSYS(freezer)
+#endif
+
+/* */
+
+#ifdef CONFIG_NET_CLS_CGROUP
+SUBSYS(net_cls)
+#endif
+
+/* */
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 5ca8c6fddb56..778777316ea4 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -35,6 +35,8 @@ struct clk;
  * clk_get may return different clock producers depending on @dev.)
  *
  * Drivers must assume that the clock source is not enabled.
+ *
+ * clk_get should not be called from within interrupt context.
  */
 struct clk *clk_get(struct device *dev, const char *id);
 
@@ -76,6 +78,8 @@ unsigned long clk_get_rate(struct clk *clk);
  * Note: drivers must ensure that all clk_enable calls made on this
  * clock source are balanced by clk_disable calls prior to calling
  * this function.
+ *
+ * clk_put should not be called from within interrupt context.
  */
 void clk_put(struct clk *clk);
 
diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h
index 55e434feec99..f88d32f8ff7c 100644
--- a/include/linux/clocksource.h
+++ b/include/linux/clocksource.h
@@ -45,7 +45,8 @@ struct clocksource;
  * @read:		returns a cycle value
  * @mask:		bitmask for two's complement
  *			subtraction of non 64 bit counters
- * @mult:		cycle to nanosecond multiplier
+ * @mult:		cycle to nanosecond multiplier (adjusted by NTP)
+ * @mult_orig:		cycle to nanosecond multiplier (unadjusted by NTP)
  * @shift:		cycle to nanosecond divisor (power of two)
  * @flags:		flags describing special properties
  * @vread:		vsyscall based read
@@ -63,6 +64,7 @@ struct clocksource {
 	cycle_t (*read)(void);
 	cycle_t mask;
 	u32 mult;
+	u32 mult_orig;
 	u32 shift;
 	unsigned long flags;
 	cycle_t (*vread)(void);
@@ -77,6 +79,7 @@ struct clocksource {
 	/* timekeeping specific data, ignore */
 	cycle_t cycle_interval;
 	u64	xtime_interval;
+	u32	raw_interval;
 	/*
 	 * Second part is written at each timer interrupt
 	 * Keep it in a different cache line to dirty no
@@ -85,6 +88,7 @@ struct clocksource {
 	cycle_t cycle_last ____cacheline_aligned_in_smp;
 	u64 xtime_nsec;
 	s64 error;
+	struct timespec raw_time;
 
 #ifdef CONFIG_CLOCKSOURCE_WATCHDOG
 	/* Watchdog related data, used by the framework */
@@ -201,17 +205,19 @@ static inline void clocksource_calculate_interval(struct clocksource *c,
 {
 	u64 tmp;
 
-	/* XXX - All of this could use a whole lot of optimization */
+	/* Do the ns -> cycle conversion first, using original mult */
 	tmp = length_nsec;
 	tmp <<= c->shift;
-	tmp += c->mult/2;
-	do_div(tmp, c->mult);
+	tmp += c->mult_orig/2;
+	do_div(tmp, c->mult_orig);
 
 	c->cycle_interval = (cycle_t)tmp;
 	if (c->cycle_interval == 0)
 		c->cycle_interval = 1;
 
+	/* Go back from cycles -> shifted ns, this time use ntp adjused mult */
 	c->xtime_interval = (u64)c->cycle_interval * c->mult;
+	c->raw_interval = ((u64)c->cycle_interval * c->mult_orig) >> c->shift;
 }
 
 
diff --git a/include/linux/cnt32_to_63.h b/include/linux/cnt32_to_63.h
index 8c0f9505b48c..7605fdd1eb65 100644
--- a/include/linux/cnt32_to_63.h
+++ b/include/linux/cnt32_to_63.h
@@ -16,6 +16,7 @@
 #include <linux/compiler.h>
 #include <linux/types.h>
 #include <asm/byteorder.h>
+#include <asm/system.h>
 
 /* this is used only to give gcc a clue about good code generation */
 union cnt32_to_63 {
@@ -53,11 +54,19 @@ union cnt32_to_63 {
  * needed increment.  And any race in updating the value in memory is harmless
  * as the same value would simply be stored more than once.
  *
- * The only restriction for the algorithm to work properly is that this
- * code must be executed at least once per each half period of the 32-bit
- * counter to properly update the state bit in memory. This is usually not a
- * problem in practice, but if it is then a kernel timer could be scheduled
- * to manage for this code to be executed often enough.
+ * The restrictions for the algorithm to work properly are:
+ *
+ * 1) this code must be called at least once per each half period of the
+ *    32-bit counter;
+ *
+ * 2) this code must not be preempted for a duration longer than the
+ *    32-bit counter half period minus the longest period between two
+ *    calls to this code.
+ *
+ * Those requirements ensure proper update to the state bit in memory.
+ * This is usually not a problem in practice, but if it is then a kernel
+ * timer should be scheduled to manage for this code to be executed often
+ * enough.
  *
  * Note that the top bit (bit 63) in the returned value should be considered
  * as garbage.  It is not cleared here because callers are likely to use a
@@ -68,9 +77,10 @@ union cnt32_to_63 {
  */
 #define cnt32_to_63(cnt_lo) \
 ({ \
-	static volatile u32 __m_cnt_hi; \
+	static u32 __m_cnt_hi; \
 	union cnt32_to_63 __x; \
 	__x.hi = __m_cnt_hi; \
+ 	smp_rmb(); \
 	__x.lo = (cnt_lo); \
 	if (unlikely((s32)(__x.hi ^ __x.lo) < 0)) \
 		__m_cnt_hi = __x.hi = (__x.hi ^ 0x80000000) + (__x.hi >> 31); \
diff --git a/include/linux/compat.h b/include/linux/compat.h
index cf8d11cad5ae..e88f3ecf38b4 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -78,7 +78,6 @@ typedef struct {
 	compat_sigset_word	sig[_COMPAT_NSIG_WORDS];
 } compat_sigset_t;
 
-extern int cp_compat_stat(struct kstat *, struct compat_stat __user *);
 extern int get_compat_timespec(struct timespec *, const struct compat_timespec __user *);
 extern int put_compat_timespec(const struct timespec *, struct compat_timespec __user *);
 
@@ -235,6 +234,11 @@ extern int get_compat_itimerspec(struct itimerspec *dst,
 extern int put_compat_itimerspec(struct compat_itimerspec __user *dst,
 				 const struct itimerspec *src);
 
+asmlinkage long compat_sys_gettimeofday(struct compat_timeval __user *tv,
+		struct timezone __user *tz);
+asmlinkage long compat_sys_settimeofday(struct compat_timeval __user *tv,
+		struct timezone __user *tz);
+
 asmlinkage long compat_sys_adjtimex(struct compat_timex __user *utp);
 
 extern int compat_printk(const char *fmt, ...);
@@ -248,12 +252,10 @@ extern int compat_ptrace_request(struct task_struct *child,
 				 compat_long_t request,
 				 compat_ulong_t addr, compat_ulong_t data);
 
-#ifdef __ARCH_WANT_COMPAT_SYS_PTRACE
 extern long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
 			       compat_ulong_t addr, compat_ulong_t data);
 asmlinkage long compat_sys_ptrace(compat_long_t request, compat_long_t pid,
 				  compat_long_t addr, compat_long_t data);
-#endif	/* __ARCH_WANT_COMPAT_SYS_PTRACE */
 
 /*
  * epoll (fs/eventpoll.c) compat bits follow ...
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
index 8322141ee480..ea7c6be354b7 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -44,6 +44,8 @@ extern void __chk_io_ptr(const volatile void __iomem *);
 # error Sorry, your compiler is too old/not recognized.
 #endif
 
+#define notrace __attribute__((no_instrument_function))
+
 /* Intel compiler defines __GNUC__. So we will overwrite implementations
  * coming from above header files here
  */
@@ -57,8 +59,88 @@ extern void __chk_io_ptr(const volatile void __iomem *);
  * specific implementations come from the above header files
  */
 
-#define likely(x)	__builtin_expect(!!(x), 1)
-#define unlikely(x)	__builtin_expect(!!(x), 0)
+struct ftrace_branch_data {
+	const char *func;
+	const char *file;
+	unsigned line;
+	union {
+		struct {
+			unsigned long correct;
+			unsigned long incorrect;
+		};
+		struct {
+			unsigned long miss;
+			unsigned long hit;
+		};
+	};
+};
+
+/*
+ * Note: DISABLE_BRANCH_PROFILING can be used by special lowlevel code
+ * to disable branch tracing on a per file basis.
+ */
+#if defined(CONFIG_TRACE_BRANCH_PROFILING) && !defined(DISABLE_BRANCH_PROFILING)
+void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
+
+#define likely_notrace(x)	__builtin_expect(!!(x), 1)
+#define unlikely_notrace(x)	__builtin_expect(!!(x), 0)
+
+#define __branch_check__(x, expect) ({					\
+			int ______r;					\
+			static struct ftrace_branch_data		\
+				__attribute__((__aligned__(4)))		\
+				__attribute__((section("_ftrace_annotated_branch"))) \
+				______f = {				\
+				.func = __func__,			\
+				.file = __FILE__,			\
+				.line = __LINE__,			\
+			};						\
+			______r = likely_notrace(x);			\
+			ftrace_likely_update(&______f, ______r, expect); \
+			______r;					\
+		})
+
+/*
+ * Using __builtin_constant_p(x) to ignore cases where the return
+ * value is always the same.  This idea is taken from a similar patch
+ * written by Daniel Walker.
+ */
+# ifndef likely
+#  define likely(x)	(__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 1))
+# endif
+# ifndef unlikely
+#  define unlikely(x)	(__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 0))
+# endif
+
+#ifdef CONFIG_PROFILE_ALL_BRANCHES
+/*
+ * "Define 'is'", Bill Clinton
+ * "Define 'if'", Steven Rostedt
+ */
+#define if(cond) if (__builtin_constant_p((cond)) ? !!(cond) :		\
+	({								\
+		int ______r;						\
+		static struct ftrace_branch_data			\
+			__attribute__((__aligned__(4)))			\
+			__attribute__((section("_ftrace_branch")))	\
+			______f = {					\
+				.func = __func__,			\
+				.file = __FILE__,			\
+				.line = __LINE__,			\
+			};						\
+		______r = !!(cond);					\
+		if (______r)						\
+			______f.hit++;					\
+		else							\
+			______f.miss++;					\
+		______r;						\
+	}))
+#endif /* CONFIG_PROFILE_ALL_BRANCHES */
+
+#else
+# define likely(x)	__builtin_expect(!!(x), 1)
+# define unlikely(x)	__builtin_expect(!!(x), 0)
+#endif
 
 /* Optimization barrier */
 #ifndef barrier
diff --git a/include/linux/console.h b/include/linux/console.h
index 248e6e3b9b73..a67a90cf8268 100644
--- a/include/linux/console.h
+++ b/include/linux/console.h
@@ -153,4 +153,8 @@ void vcs_remove_sysfs(struct tty_struct *tty);
 #define VESA_HSYNC_SUSPEND      2
 #define VESA_POWERDOWN          3
 
+#ifdef CONFIG_VGA_CONSOLE
+extern bool vgacon_text_force(void);
+#endif
+
 #endif /* _LINUX_CONSOLE_H */
diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h
index d3219d73f8e6..21e1dd43e52a 100644
--- a/include/linux/cpumask.h
+++ b/include/linux/cpumask.h
@@ -5,6 +5,9 @@
  * Cpumasks provide a bitmap suitable for representing the
  * set of CPU's in a system, one bit position per CPU number.
  *
+ * The new cpumask_ ops take a "struct cpumask *"; the old ones
+ * use cpumask_t.
+ *
  * See detailed comments in the file linux/bitmap.h describing the
  * data type on which these cpumasks are based.
  *
@@ -31,7 +34,7 @@
  *       will span the entire range of NR_CPUS.
  * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  *
- * The available cpumask operations are:
+ * The obsolescent cpumask operations are:
  *
  * void cpu_set(cpu, mask)		turn on bit 'cpu' in mask
  * void cpu_clear(cpu, mask)		turn off bit 'cpu' in mask
@@ -138,7 +141,7 @@
 #include <linux/threads.h>
 #include <linux/bitmap.h>
 
-typedef struct { DECLARE_BITMAP(bits, NR_CPUS); } cpumask_t;
+typedef struct cpumask { DECLARE_BITMAP(bits, NR_CPUS); } cpumask_t;
 extern cpumask_t _unused_cpumask_arg_;
 
 #define cpu_set(cpu, dst) __cpu_set((cpu), &(dst))
@@ -527,4 +530,556 @@ extern cpumask_t cpu_active_map;
 #define for_each_online_cpu(cpu)   for_each_cpu_mask_nr((cpu), cpu_online_map)
 #define for_each_present_cpu(cpu)  for_each_cpu_mask_nr((cpu), cpu_present_map)
 
+/* These are the new versions of the cpumask operators: passed by pointer.
+ * The older versions will be implemented in terms of these, then deleted. */
+#define cpumask_bits(maskp) ((maskp)->bits)
+
+#if NR_CPUS <= BITS_PER_LONG
+#define CPU_BITS_ALL						\
+{								\
+	[BITS_TO_LONGS(NR_CPUS)-1] = CPU_MASK_LAST_WORD	\
+}
+
+/* This produces more efficient code. */
+#define nr_cpumask_bits	NR_CPUS
+
+#else /* NR_CPUS > BITS_PER_LONG */
+
+#define CPU_BITS_ALL						\
+{								\
+	[0 ... BITS_TO_LONGS(NR_CPUS)-2] = ~0UL,		\
+	[BITS_TO_LONGS(NR_CPUS)-1] = CPU_MASK_LAST_WORD		\
+}
+
+#define nr_cpumask_bits	nr_cpu_ids
+#endif /* NR_CPUS > BITS_PER_LONG */
+
+/* verify cpu argument to cpumask_* operators */
+static inline unsigned int cpumask_check(unsigned int cpu)
+{
+#ifdef CONFIG_DEBUG_PER_CPU_MAPS
+	WARN_ON_ONCE(cpu >= nr_cpumask_bits);
+#endif /* CONFIG_DEBUG_PER_CPU_MAPS */
+	return cpu;
+}
+
+#if NR_CPUS == 1
+/* Uniprocessor.  Assume all masks are "1". */
+static inline unsigned int cpumask_first(const struct cpumask *srcp)
+{
+	return 0;
+}
+
+/* Valid inputs for n are -1 and 0. */
+static inline unsigned int cpumask_next(int n, const struct cpumask *srcp)
+{
+	return n+1;
+}
+
+static inline unsigned int cpumask_next_zero(int n, const struct cpumask *srcp)
+{
+	return n+1;
+}
+
+static inline unsigned int cpumask_next_and(int n,
+					    const struct cpumask *srcp,
+					    const struct cpumask *andp)
+{
+	return n+1;
+}
+
+/* cpu must be a valid cpu, ie 0, so there's no other choice. */
+static inline unsigned int cpumask_any_but(const struct cpumask *mask,
+					   unsigned int cpu)
+{
+	return 1;
+}
+
+#define for_each_cpu(cpu, mask)			\
+	for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask)
+#define for_each_cpu_and(cpu, mask, and)	\
+	for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask, (void)and)
+#else
+/**
+ * cpumask_first - get the first cpu in a cpumask
+ * @srcp: the cpumask pointer
+ *
+ * Returns >= nr_cpu_ids if no cpus set.
+ */
+static inline unsigned int cpumask_first(const struct cpumask *srcp)
+{
+	return find_first_bit(cpumask_bits(srcp), nr_cpumask_bits);
+}
+
+/**
+ * cpumask_next - get the next cpu in a cpumask
+ * @n: the cpu prior to the place to search (ie. return will be > @n)
+ * @srcp: the cpumask pointer
+ *
+ * Returns >= nr_cpu_ids if no further cpus set.
+ */
+static inline unsigned int cpumask_next(int n, const struct cpumask *srcp)
+{
+	/* -1 is a legal arg here. */
+	if (n != -1)
+		cpumask_check(n);
+	return find_next_bit(cpumask_bits(srcp), nr_cpumask_bits, n+1);
+}
+
+/**
+ * cpumask_next_zero - get the next unset cpu in a cpumask
+ * @n: the cpu prior to the place to search (ie. return will be > @n)
+ * @srcp: the cpumask pointer
+ *
+ * Returns >= nr_cpu_ids if no further cpus unset.
+ */
+static inline unsigned int cpumask_next_zero(int n, const struct cpumask *srcp)
+{
+	/* -1 is a legal arg here. */
+	if (n != -1)
+		cpumask_check(n);
+	return find_next_zero_bit(cpumask_bits(srcp), nr_cpumask_bits, n+1);
+}
+
+int cpumask_next_and(int n, const struct cpumask *, const struct cpumask *);
+int cpumask_any_but(const struct cpumask *mask, unsigned int cpu);
+
+/**
+ * for_each_cpu - iterate over every cpu in a mask
+ * @cpu: the (optionally unsigned) integer iterator
+ * @mask: the cpumask pointer
+ *
+ * After the loop, cpu is >= nr_cpu_ids.
+ */
+#define for_each_cpu(cpu, mask)				\
+	for ((cpu) = -1;				\
+		(cpu) = cpumask_next((cpu), (mask)),	\
+		(cpu) < nr_cpu_ids;)
+
+/**
+ * for_each_cpu_and - iterate over every cpu in both masks
+ * @cpu: the (optionally unsigned) integer iterator
+ * @mask: the first cpumask pointer
+ * @and: the second cpumask pointer
+ *
+ * This saves a temporary CPU mask in many places.  It is equivalent to:
+ *	struct cpumask tmp;
+ *	cpumask_and(&tmp, &mask, &and);
+ *	for_each_cpu(cpu, &tmp)
+ *		...
+ *
+ * After the loop, cpu is >= nr_cpu_ids.
+ */
+#define for_each_cpu_and(cpu, mask, and)				\
+	for ((cpu) = -1;						\
+		(cpu) = cpumask_next_and((cpu), (mask), (and)),		\
+		(cpu) < nr_cpu_ids;)
+#endif /* SMP */
+
+#define CPU_BITS_NONE						\
+{								\
+	[0 ... BITS_TO_LONGS(NR_CPUS)-1] = 0UL			\
+}
+
+#define CPU_BITS_CPU0						\
+{								\
+	[0] =  1UL						\
+}
+
+/**
+ * cpumask_set_cpu - set a cpu in a cpumask
+ * @cpu: cpu number (< nr_cpu_ids)
+ * @dstp: the cpumask pointer
+ */
+static inline void cpumask_set_cpu(unsigned int cpu, struct cpumask *dstp)
+{
+	set_bit(cpumask_check(cpu), cpumask_bits(dstp));
+}
+
+/**
+ * cpumask_clear_cpu - clear a cpu in a cpumask
+ * @cpu: cpu number (< nr_cpu_ids)
+ * @dstp: the cpumask pointer
+ */
+static inline void cpumask_clear_cpu(int cpu, struct cpumask *dstp)
+{
+	clear_bit(cpumask_check(cpu), cpumask_bits(dstp));
+}
+
+/**
+ * cpumask_test_cpu - test for a cpu in a cpumask
+ * @cpu: cpu number (< nr_cpu_ids)
+ * @cpumask: the cpumask pointer
+ *
+ * No static inline type checking - see Subtlety (1) above.
+ */
+#define cpumask_test_cpu(cpu, cpumask) \
+	test_bit(cpumask_check(cpu), (cpumask)->bits)
+
+/**
+ * cpumask_test_and_set_cpu - atomically test and set a cpu in a cpumask
+ * @cpu: cpu number (< nr_cpu_ids)
+ * @cpumask: the cpumask pointer
+ *
+ * test_and_set_bit wrapper for cpumasks.
+ */
+static inline int cpumask_test_and_set_cpu(int cpu, struct cpumask *cpumask)
+{
+	return test_and_set_bit(cpumask_check(cpu), cpumask_bits(cpumask));
+}
+
+/**
+ * cpumask_setall - set all cpus (< nr_cpu_ids) in a cpumask
+ * @dstp: the cpumask pointer
+ */
+static inline void cpumask_setall(struct cpumask *dstp)
+{
+	bitmap_fill(cpumask_bits(dstp), nr_cpumask_bits);
+}
+
+/**
+ * cpumask_clear - clear all cpus (< nr_cpu_ids) in a cpumask
+ * @dstp: the cpumask pointer
+ */
+static inline void cpumask_clear(struct cpumask *dstp)
+{
+	bitmap_zero(cpumask_bits(dstp), nr_cpumask_bits);
+}
+
+/**
+ * cpumask_and - *dstp = *src1p & *src2p
+ * @dstp: the cpumask result
+ * @src1p: the first input
+ * @src2p: the second input
+ */
+static inline void cpumask_and(struct cpumask *dstp,
+			       const struct cpumask *src1p,
+			       const struct cpumask *src2p)
+{
+	bitmap_and(cpumask_bits(dstp), cpumask_bits(src1p),
+				       cpumask_bits(src2p), nr_cpumask_bits);
+}
+
+/**
+ * cpumask_or - *dstp = *src1p | *src2p
+ * @dstp: the cpumask result
+ * @src1p: the first input
+ * @src2p: the second input
+ */
+static inline void cpumask_or(struct cpumask *dstp, const struct cpumask *src1p,
+			      const struct cpumask *src2p)
+{
+	bitmap_or(cpumask_bits(dstp), cpumask_bits(src1p),
+				      cpumask_bits(src2p), nr_cpumask_bits);
+}
+
+/**
+ * cpumask_xor - *dstp = *src1p ^ *src2p
+ * @dstp: the cpumask result
+ * @src1p: the first input
+ * @src2p: the second input
+ */
+static inline void cpumask_xor(struct cpumask *dstp,
+			       const struct cpumask *src1p,
+			       const struct cpumask *src2p)
+{
+	bitmap_xor(cpumask_bits(dstp), cpumask_bits(src1p),
+				       cpumask_bits(src2p), nr_cpumask_bits);
+}
+
+/**
+ * cpumask_andnot - *dstp = *src1p & ~*src2p
+ * @dstp: the cpumask result
+ * @src1p: the first input
+ * @src2p: the second input
+ */
+static inline void cpumask_andnot(struct cpumask *dstp,
+				  const struct cpumask *src1p,
+				  const struct cpumask *src2p)
+{
+	bitmap_andnot(cpumask_bits(dstp), cpumask_bits(src1p),
+					  cpumask_bits(src2p), nr_cpumask_bits);
+}
+
+/**
+ * cpumask_complement - *dstp = ~*srcp
+ * @dstp: the cpumask result
+ * @srcp: the input to invert
+ */
+static inline void cpumask_complement(struct cpumask *dstp,
+				      const struct cpumask *srcp)
+{
+	bitmap_complement(cpumask_bits(dstp), cpumask_bits(srcp),
+					      nr_cpumask_bits);
+}
+
+/**
+ * cpumask_equal - *src1p == *src2p
+ * @src1p: the first input
+ * @src2p: the second input
+ */
+static inline bool cpumask_equal(const struct cpumask *src1p,
+				const struct cpumask *src2p)
+{
+	return bitmap_equal(cpumask_bits(src1p), cpumask_bits(src2p),
+						 nr_cpumask_bits);
+}
+
+/**
+ * cpumask_intersects - (*src1p & *src2p) != 0
+ * @src1p: the first input
+ * @src2p: the second input
+ */
+static inline bool cpumask_intersects(const struct cpumask *src1p,
+				     const struct cpumask *src2p)
+{
+	return bitmap_intersects(cpumask_bits(src1p), cpumask_bits(src2p),
+						      nr_cpumask_bits);
+}
+
+/**
+ * cpumask_subset - (*src1p & ~*src2p) == 0
+ * @src1p: the first input
+ * @src2p: the second input
+ */
+static inline int cpumask_subset(const struct cpumask *src1p,
+				 const struct cpumask *src2p)
+{
+	return bitmap_subset(cpumask_bits(src1p), cpumask_bits(src2p),
+						  nr_cpumask_bits);
+}
+
+/**
+ * cpumask_empty - *srcp == 0
+ * @srcp: the cpumask to that all cpus < nr_cpu_ids are clear.
+ */
+static inline bool cpumask_empty(const struct cpumask *srcp)
+{
+	return bitmap_empty(cpumask_bits(srcp), nr_cpumask_bits);
+}
+
+/**
+ * cpumask_full - *srcp == 0xFFFFFFFF...
+ * @srcp: the cpumask to that all cpus < nr_cpu_ids are set.
+ */
+static inline bool cpumask_full(const struct cpumask *srcp)
+{
+	return bitmap_full(cpumask_bits(srcp), nr_cpumask_bits);
+}
+
+/**
+ * cpumask_weight - Count of bits in *srcp
+ * @srcp: the cpumask to count bits (< nr_cpu_ids) in.
+ */
+static inline unsigned int cpumask_weight(const struct cpumask *srcp)
+{
+	return bitmap_weight(cpumask_bits(srcp), nr_cpumask_bits);
+}
+
+/**
+ * cpumask_shift_right - *dstp = *srcp >> n
+ * @dstp: the cpumask result
+ * @srcp: the input to shift
+ * @n: the number of bits to shift by
+ */
+static inline void cpumask_shift_right(struct cpumask *dstp,
+				       const struct cpumask *srcp, int n)
+{
+	bitmap_shift_right(cpumask_bits(dstp), cpumask_bits(srcp), n,
+					       nr_cpumask_bits);
+}
+
+/**
+ * cpumask_shift_left - *dstp = *srcp << n
+ * @dstp: the cpumask result
+ * @srcp: the input to shift
+ * @n: the number of bits to shift by
+ */
+static inline void cpumask_shift_left(struct cpumask *dstp,
+				      const struct cpumask *srcp, int n)
+{
+	bitmap_shift_left(cpumask_bits(dstp), cpumask_bits(srcp), n,
+					      nr_cpumask_bits);
+}
+
+/**
+ * cpumask_copy - *dstp = *srcp
+ * @dstp: the result
+ * @srcp: the input cpumask
+ */
+static inline void cpumask_copy(struct cpumask *dstp,
+				const struct cpumask *srcp)
+{
+	bitmap_copy(cpumask_bits(dstp), cpumask_bits(srcp), nr_cpumask_bits);
+}
+
+/**
+ * cpumask_any - pick a "random" cpu from *srcp
+ * @srcp: the input cpumask
+ *
+ * Returns >= nr_cpu_ids if no cpus set.
+ */
+#define cpumask_any(srcp) cpumask_first(srcp)
+
+/**
+ * cpumask_first_and - return the first cpu from *srcp1 & *srcp2
+ * @src1p: the first input
+ * @src2p: the second input
+ *
+ * Returns >= nr_cpu_ids if no cpus set in both.  See also cpumask_next_and().
+ */
+#define cpumask_first_and(src1p, src2p) cpumask_next_and(-1, (src1p), (src2p))
+
+/**
+ * cpumask_any_and - pick a "random" cpu from *mask1 & *mask2
+ * @mask1: the first input cpumask
+ * @mask2: the second input cpumask
+ *
+ * Returns >= nr_cpu_ids if no cpus set.
+ */
+#define cpumask_any_and(mask1, mask2) cpumask_first_and((mask1), (mask2))
+
+/**
+ * cpumask_of - the cpumask containing just a given cpu
+ * @cpu: the cpu (<= nr_cpu_ids)
+ */
+#define cpumask_of(cpu) (get_cpu_mask(cpu))
+
+/**
+ * to_cpumask - convert an NR_CPUS bitmap to a struct cpumask *
+ * @bitmap: the bitmap
+ *
+ * There are a few places where cpumask_var_t isn't appropriate and
+ * static cpumasks must be used (eg. very early boot), yet we don't
+ * expose the definition of 'struct cpumask'.
+ *
+ * This does the conversion, and can be used as a constant initializer.
+ */
+#define to_cpumask(bitmap)						\
+	((struct cpumask *)(1 ? (bitmap)				\
+			    : (void *)sizeof(__check_is_bitmap(bitmap))))
+
+static inline int __check_is_bitmap(const unsigned long *bitmap)
+{
+	return 1;
+}
+
+/**
+ * cpumask_size - size to allocate for a 'struct cpumask' in bytes
+ *
+ * This will eventually be a runtime variable, depending on nr_cpu_ids.
+ */
+static inline size_t cpumask_size(void)
+{
+	/* FIXME: Once all cpumask assignments are eliminated, this
+	 * can be nr_cpumask_bits */
+	return BITS_TO_LONGS(NR_CPUS) * sizeof(long);
+}
+
+/*
+ * cpumask_var_t: struct cpumask for stack usage.
+ *
+ * Oh, the wicked games we play!  In order to make kernel coding a
+ * little more difficult, we typedef cpumask_var_t to an array or a
+ * pointer: doing &mask on an array is a noop, so it still works.
+ *
+ * ie.
+ *	cpumask_var_t tmpmask;
+ *	if (!alloc_cpumask_var(&tmpmask, GFP_KERNEL))
+ *		return -ENOMEM;
+ *
+ *	  ... use 'tmpmask' like a normal struct cpumask * ...
+ *
+ *	free_cpumask_var(tmpmask);
+ */
+#ifdef CONFIG_CPUMASK_OFFSTACK
+typedef struct cpumask *cpumask_var_t;
+
+bool alloc_cpumask_var(cpumask_var_t *mask, gfp_t flags);
+void alloc_bootmem_cpumask_var(cpumask_var_t *mask);
+void free_cpumask_var(cpumask_var_t mask);
+void free_bootmem_cpumask_var(cpumask_var_t mask);
+
+#else
+typedef struct cpumask cpumask_var_t[1];
+
+static inline bool alloc_cpumask_var(cpumask_var_t *mask, gfp_t flags)
+{
+	return true;
+}
+
+static inline void alloc_bootmem_cpumask_var(cpumask_var_t *mask)
+{
+}
+
+static inline void free_cpumask_var(cpumask_var_t mask)
+{
+}
+
+static inline void free_bootmem_cpumask_var(cpumask_var_t mask)
+{
+}
+#endif /* CONFIG_CPUMASK_OFFSTACK */
+
+/* The pointer versions of the maps, these will become the primary versions. */
+#define cpu_possible_mask ((const struct cpumask *)&cpu_possible_map)
+#define cpu_online_mask ((const struct cpumask *)&cpu_online_map)
+#define cpu_present_mask ((const struct cpumask *)&cpu_present_map)
+#define cpu_active_mask ((const struct cpumask *)&cpu_active_map)
+
+/* It's common to want to use cpu_all_mask in struct member initializers,
+ * so it has to refer to an address rather than a pointer. */
+extern const DECLARE_BITMAP(cpu_all_bits, NR_CPUS);
+#define cpu_all_mask to_cpumask(cpu_all_bits)
+
+/* First bits of cpu_bit_bitmap are in fact unset. */
+#define cpu_none_mask to_cpumask(cpu_bit_bitmap[0])
+
+/* Wrappers for arch boot code to manipulate normally-constant masks */
+static inline void set_cpu_possible(unsigned int cpu, bool possible)
+{
+	if (possible)
+		cpumask_set_cpu(cpu, &cpu_possible_map);
+	else
+		cpumask_clear_cpu(cpu, &cpu_possible_map);
+}
+
+static inline void set_cpu_present(unsigned int cpu, bool present)
+{
+	if (present)
+		cpumask_set_cpu(cpu, &cpu_present_map);
+	else
+		cpumask_clear_cpu(cpu, &cpu_present_map);
+}
+
+static inline void set_cpu_online(unsigned int cpu, bool online)
+{
+	if (online)
+		cpumask_set_cpu(cpu, &cpu_online_map);
+	else
+		cpumask_clear_cpu(cpu, &cpu_online_map);
+}
+
+static inline void set_cpu_active(unsigned int cpu, bool active)
+{
+	if (active)
+		cpumask_set_cpu(cpu, &cpu_active_map);
+	else
+		cpumask_clear_cpu(cpu, &cpu_active_map);
+}
+
+static inline void init_cpu_present(const struct cpumask *src)
+{
+	cpumask_copy(&cpu_present_map, src);
+}
+
+static inline void init_cpu_possible(const struct cpumask *src)
+{
+	cpumask_copy(&cpu_possible_map, src);
+}
+
+static inline void init_cpu_online(const struct cpumask *src)
+{
+	cpumask_copy(&cpu_online_map, src);
+}
 #endif /* __LINUX_CPUMASK_H */
diff --git a/include/linux/cpuset.h b/include/linux/cpuset.h
index 2691926fb506..8e540d32c9fe 100644
--- a/include/linux/cpuset.h
+++ b/include/linux/cpuset.h
@@ -74,8 +74,6 @@ static inline int cpuset_do_slab_mem_spread(void)
 	return current->flags & PF_SPREAD_SLAB;
 }
 
-extern void cpuset_track_online_nodes(void);
-
 extern int current_cpuset_is_being_rebound(void);
 
 extern void rebuild_sched_domains(void);
@@ -151,8 +149,6 @@ static inline int cpuset_do_slab_mem_spread(void)
 	return 0;
 }
 
-static inline void cpuset_track_online_nodes(void) {}
-
 static inline int current_cpuset_is_being_rebound(void)
 {
 	return 0;
diff --git a/include/linux/crash_dump.h b/include/linux/crash_dump.h
index 025e4f575103..2dac064d8359 100644
--- a/include/linux/crash_dump.h
+++ b/include/linux/crash_dump.h
@@ -8,17 +8,12 @@
 #include <linux/proc_fs.h>
 
 #define ELFCORE_ADDR_MAX	(-1ULL)
+#define ELFCORE_ADDR_ERR	(-2ULL)
 
-#ifdef CONFIG_PROC_VMCORE
 extern unsigned long long elfcorehdr_addr;
-#else
-static const unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX;
-#endif
 
 extern ssize_t copy_oldmem_page(unsigned long, char *, size_t,
 						unsigned long, int);
-extern const struct file_operations proc_vmcore_operations;
-extern struct proc_dir_entry *proc_vmcore;
 
 /* Architecture code defines this if there are other possible ELF
  * machine types, e.g. on bi-arch capable hardware. */
@@ -28,10 +23,43 @@ extern struct proc_dir_entry *proc_vmcore;
 
 #define vmcore_elf_check_arch(x) (elf_check_arch(x) || vmcore_elf_check_arch_cross(x))
 
+/*
+ * is_kdump_kernel() checks whether this kernel is booting after a panic of
+ * previous kernel or not. This is determined by checking if previous kernel
+ * has passed the elf core header address on command line.
+ *
+ * This is not just a test if CONFIG_CRASH_DUMP is enabled or not. It will
+ * return 1 if CONFIG_CRASH_DUMP=y and if kernel is booting after a panic of
+ * previous kernel.
+ */
+
 static inline int is_kdump_kernel(void)
 {
 	return (elfcorehdr_addr != ELFCORE_ADDR_MAX) ? 1 : 0;
 }
+
+/* is_vmcore_usable() checks if the kernel is booting after a panic and
+ * the vmcore region is usable.
+ *
+ * This makes use of the fact that due to alignment -2ULL is not
+ * a valid pointer, much in the vain of IS_ERR(), except
+ * dealing directly with an unsigned long long rather than a pointer.
+ */
+
+static inline int is_vmcore_usable(void)
+{
+	return is_kdump_kernel() && elfcorehdr_addr != ELFCORE_ADDR_ERR ? 1 : 0;
+}
+
+/* vmcore_unusable() marks the vmcore as unusable,
+ * without disturbing the logic of is_kdump_kernel()
+ */
+
+static inline void vmcore_unusable(void)
+{
+	if (is_kdump_kernel())
+		elfcorehdr_addr = ELFCORE_ADDR_ERR;
+}
 #else /* !CONFIG_CRASH_DUMP */
 static inline int is_kdump_kernel(void) { return 0; }
 #endif /* CONFIG_CRASH_DUMP */
diff --git a/include/linux/crc32c.h b/include/linux/crc32c.h
index 508f512e5a2f..bd8b44d96bdc 100644
--- a/include/linux/crc32c.h
+++ b/include/linux/crc32c.h
@@ -3,9 +3,9 @@
 
 #include <linux/types.h>
 
-extern u32 crc32c_le(u32 crc, unsigned char const *address, size_t length);
-extern u32 crc32c_be(u32 crc, unsigned char const *address, size_t length);
+extern u32 crc32c(u32 crc, const void *address, unsigned int length);
 
-#define crc32c(seed, data, length)  crc32c_le(seed, (unsigned char const *)data, length)
+/* This macro exists for backwards-compatibility. */
+#define crc32c_le crc32c
 
 #endif	/* _LINUX_CRC32C_H */
diff --git a/include/linux/cred.h b/include/linux/cred.h
index b69222cc1fd2..3282ee4318e7 100644
--- a/include/linux/cred.h
+++ b/include/linux/cred.h
@@ -1,4 +1,4 @@
-/* Credentials management
+/* Credentials management - see Documentation/credentials.txt
  *
  * Copyright (C) 2008 Red Hat, Inc. All Rights Reserved.
  * Written by David Howells (dhowells@redhat.com)
@@ -12,39 +12,335 @@
 #ifndef _LINUX_CRED_H
 #define _LINUX_CRED_H
 
-#define get_current_user()	(get_uid(current->user))
+#include <linux/capability.h>
+#include <linux/key.h>
+#include <asm/atomic.h>
 
-#define task_uid(task)		((task)->uid)
-#define task_gid(task)		((task)->gid)
-#define task_euid(task)		((task)->euid)
-#define task_egid(task)		((task)->egid)
+struct user_struct;
+struct cred;
+struct inode;
 
-#define current_uid()		(current->uid)
-#define current_gid()		(current->gid)
-#define current_euid()		(current->euid)
-#define current_egid()		(current->egid)
-#define current_suid()		(current->suid)
-#define current_sgid()		(current->sgid)
-#define current_fsuid()		(current->fsuid)
-#define current_fsgid()		(current->fsgid)
-#define current_cap()		(current->cap_effective)
+/*
+ * COW Supplementary groups list
+ */
+#define NGROUPS_SMALL		32
+#define NGROUPS_PER_BLOCK	((unsigned int)(PAGE_SIZE / sizeof(gid_t)))
+
+struct group_info {
+	atomic_t	usage;
+	int		ngroups;
+	int		nblocks;
+	gid_t		small_block[NGROUPS_SMALL];
+	gid_t		*blocks[0];
+};
+
+/**
+ * get_group_info - Get a reference to a group info structure
+ * @group_info: The group info to reference
+ *
+ * This gets a reference to a set of supplementary groups.
+ *
+ * If the caller is accessing a task's credentials, they must hold the RCU read
+ * lock when reading.
+ */
+static inline struct group_info *get_group_info(struct group_info *gi)
+{
+	atomic_inc(&gi->usage);
+	return gi;
+}
+
+/**
+ * put_group_info - Release a reference to a group info structure
+ * @group_info: The group info to release
+ */
+#define put_group_info(group_info)			\
+do {							\
+	if (atomic_dec_and_test(&(group_info)->usage))	\
+		groups_free(group_info);		\
+} while (0)
+
+extern struct group_info *groups_alloc(int);
+extern struct group_info init_groups;
+extern void groups_free(struct group_info *);
+extern int set_current_groups(struct group_info *);
+extern int set_groups(struct cred *, struct group_info *);
+extern int groups_search(const struct group_info *, gid_t);
+
+/* access the groups "array" with this macro */
+#define GROUP_AT(gi, i) \
+	((gi)->blocks[(i) / NGROUPS_PER_BLOCK][(i) % NGROUPS_PER_BLOCK])
+
+extern int in_group_p(gid_t);
+extern int in_egroup_p(gid_t);
+
+/*
+ * The common credentials for a thread group
+ * - shared by CLONE_THREAD
+ */
+#ifdef CONFIG_KEYS
+struct thread_group_cred {
+	atomic_t	usage;
+	pid_t		tgid;			/* thread group process ID */
+	spinlock_t	lock;
+	struct key	*session_keyring;	/* keyring inherited over fork */
+	struct key	*process_keyring;	/* keyring private to this process */
+	struct rcu_head	rcu;			/* RCU deletion hook */
+};
+#endif
+
+/*
+ * The security context of a task
+ *
+ * The parts of the context break down into two categories:
+ *
+ *  (1) The objective context of a task.  These parts are used when some other
+ *	task is attempting to affect this one.
+ *
+ *  (2) The subjective context.  These details are used when the task is acting
+ *	upon another object, be that a file, a task, a key or whatever.
+ *
+ * Note that some members of this structure belong to both categories - the
+ * LSM security pointer for instance.
+ *
+ * A task has two security pointers.  task->real_cred points to the objective
+ * context that defines that task's actual details.  The objective part of this
+ * context is used whenever that task is acted upon.
+ *
+ * task->cred points to the subjective context that defines the details of how
+ * that task is going to act upon another object.  This may be overridden
+ * temporarily to point to another security context, but normally points to the
+ * same context as task->real_cred.
+ */
+struct cred {
+	atomic_t	usage;
+	uid_t		uid;		/* real UID of the task */
+	gid_t		gid;		/* real GID of the task */
+	uid_t		suid;		/* saved UID of the task */
+	gid_t		sgid;		/* saved GID of the task */
+	uid_t		euid;		/* effective UID of the task */
+	gid_t		egid;		/* effective GID of the task */
+	uid_t		fsuid;		/* UID for VFS ops */
+	gid_t		fsgid;		/* GID for VFS ops */
+	unsigned	securebits;	/* SUID-less security management */
+	kernel_cap_t	cap_inheritable; /* caps our children can inherit */
+	kernel_cap_t	cap_permitted;	/* caps we're permitted */
+	kernel_cap_t	cap_effective;	/* caps we can actually use */
+	kernel_cap_t	cap_bset;	/* capability bounding set */
+#ifdef CONFIG_KEYS
+	unsigned char	jit_keyring;	/* default keyring to attach requested
+					 * keys to */
+	struct key	*thread_keyring; /* keyring private to this thread */
+	struct key	*request_key_auth; /* assumed request_key authority */
+	struct thread_group_cred *tgcred; /* thread-group shared credentials */
+#endif
+#ifdef CONFIG_SECURITY
+	void		*security;	/* subjective LSM security */
+#endif
+	struct user_struct *user;	/* real user ID subscription */
+	struct group_info *group_info;	/* supplementary groups for euid/fsgid */
+	struct rcu_head	rcu;		/* RCU deletion hook */
+};
+
+extern void __put_cred(struct cred *);
+extern int copy_creds(struct task_struct *, unsigned long);
+extern struct cred *prepare_creds(void);
+extern struct cred *prepare_exec_creds(void);
+extern struct cred *prepare_usermodehelper_creds(void);
+extern int commit_creds(struct cred *);
+extern void abort_creds(struct cred *);
+extern const struct cred *override_creds(const struct cred *);
+extern void revert_creds(const struct cred *);
+extern struct cred *prepare_kernel_cred(struct task_struct *);
+extern int change_create_files_as(struct cred *, struct inode *);
+extern int set_security_override(struct cred *, u32);
+extern int set_security_override_from_ctx(struct cred *, const char *);
+extern int set_create_files_as(struct cred *, struct inode *);
+extern void __init cred_init(void);
+
+/**
+ * get_new_cred - Get a reference on a new set of credentials
+ * @cred: The new credentials to reference
+ *
+ * Get a reference on the specified set of new credentials.  The caller must
+ * release the reference.
+ */
+static inline struct cred *get_new_cred(struct cred *cred)
+{
+	atomic_inc(&cred->usage);
+	return cred;
+}
+
+/**
+ * get_cred - Get a reference on a set of credentials
+ * @cred: The credentials to reference
+ *
+ * Get a reference on the specified set of credentials.  The caller must
+ * release the reference.
+ *
+ * This is used to deal with a committed set of credentials.  Although the
+ * pointer is const, this will temporarily discard the const and increment the
+ * usage count.  The purpose of this is to attempt to catch at compile time the
+ * accidental alteration of a set of credentials that should be considered
+ * immutable.
+ */
+static inline const struct cred *get_cred(const struct cred *cred)
+{
+	return get_new_cred((struct cred *) cred);
+}
+
+/**
+ * put_cred - Release a reference to a set of credentials
+ * @cred: The credentials to release
+ *
+ * Release a reference to a set of credentials, deleting them when the last ref
+ * is released.
+ *
+ * This takes a const pointer to a set of credentials because the credentials
+ * on task_struct are attached by const pointers to prevent accidental
+ * alteration of otherwise immutable credential sets.
+ */
+static inline void put_cred(const struct cred *_cred)
+{
+	struct cred *cred = (struct cred *) _cred;
+
+	BUG_ON(atomic_read(&(cred)->usage) <= 0);
+	if (atomic_dec_and_test(&(cred)->usage))
+		__put_cred(cred);
+}
+
+/**
+ * current_cred - Access the current task's subjective credentials
+ *
+ * Access the subjective credentials of the current task.
+ */
+#define current_cred() \
+	(current->cred)
+
+/**
+ * __task_cred - Access a task's objective credentials
+ * @task: The task to query
+ *
+ * Access the objective credentials of a task.  The caller must hold the RCU
+ * readlock.
+ *
+ * The caller must make sure task doesn't go away, either by holding a ref on
+ * task or by holding tasklist_lock to prevent it from being unlinked.
+ */
+#define __task_cred(task) \
+	((const struct cred *)(rcu_dereference((task)->real_cred)))
+
+/**
+ * get_task_cred - Get another task's objective credentials
+ * @task: The task to query
+ *
+ * Get the objective credentials of a task, pinning them so that they can't go
+ * away.  Accessing a task's credentials directly is not permitted.
+ *
+ * The caller must make sure task doesn't go away, either by holding a ref on
+ * task or by holding tasklist_lock to prevent it from being unlinked.
+ */
+#define get_task_cred(task)				\
+({							\
+	struct cred *__cred;				\
+	rcu_read_lock();				\
+	__cred = (struct cred *) __task_cred((task));	\
+	get_cred(__cred);				\
+	rcu_read_unlock();				\
+	__cred;						\
+})
+
+/**
+ * get_current_cred - Get the current task's subjective credentials
+ *
+ * Get the subjective credentials of the current task, pinning them so that
+ * they can't go away.  Accessing the current task's credentials directly is
+ * not permitted.
+ */
+#define get_current_cred()				\
+	(get_cred(current_cred()))
+
+/**
+ * get_current_user - Get the current task's user_struct
+ *
+ * Get the user record of the current task, pinning it so that it can't go
+ * away.
+ */
+#define get_current_user()				\
+({							\
+	struct user_struct *__u;			\
+	struct cred *__cred;				\
+	__cred = (struct cred *) current_cred();	\
+	__u = get_uid(__cred->user);			\
+	__u;						\
+})
+
+/**
+ * get_current_groups - Get the current task's supplementary group list
+ *
+ * Get the supplementary group list of the current task, pinning it so that it
+ * can't go away.
+ */
+#define get_current_groups()				\
+({							\
+	struct group_info *__groups;			\
+	struct cred *__cred;				\
+	__cred = (struct cred *) current_cred();	\
+	__groups = get_group_info(__cred->group_info);	\
+	__groups;					\
+})
+
+#define task_cred_xxx(task, xxx)			\
+({							\
+	__typeof__(((struct cred *)NULL)->xxx) ___val;	\
+	rcu_read_lock();				\
+	___val = __task_cred((task))->xxx;		\
+	rcu_read_unlock();				\
+	___val;						\
+})
+
+#define task_uid(task)		(task_cred_xxx((task), uid))
+#define task_euid(task)		(task_cred_xxx((task), euid))
+
+#define current_cred_xxx(xxx)			\
+({						\
+	current->cred->xxx;			\
+})
+
+#define current_uid()		(current_cred_xxx(uid))
+#define current_gid()		(current_cred_xxx(gid))
+#define current_euid()		(current_cred_xxx(euid))
+#define current_egid()		(current_cred_xxx(egid))
+#define current_suid()		(current_cred_xxx(suid))
+#define current_sgid()		(current_cred_xxx(sgid))
+#define current_fsuid() 	(current_cred_xxx(fsuid))
+#define current_fsgid() 	(current_cred_xxx(fsgid))
+#define current_cap()		(current_cred_xxx(cap_effective))
+#define current_user()		(current_cred_xxx(user))
+#define current_user_ns()	(current_cred_xxx(user)->user_ns)
+#define current_security()	(current_cred_xxx(security))
 
 #define current_uid_gid(_uid, _gid)		\
 do {						\
-	*(_uid) = current->uid;			\
-	*(_gid) = current->gid;			\
+	const struct cred *__cred;		\
+	__cred = current_cred();		\
+	*(_uid) = __cred->uid;			\
+	*(_gid) = __cred->gid;			\
 } while(0)
 
-#define current_euid_egid(_uid, _gid)		\
+#define current_euid_egid(_euid, _egid)		\
 do {						\
-	*(_uid) = current->euid;		\
-	*(_gid) = current->egid;		\
+	const struct cred *__cred;		\
+	__cred = current_cred();		\
+	*(_euid) = __cred->euid;		\
+	*(_egid) = __cred->egid;		\
 } while(0)
 
-#define current_fsuid_fsgid(_uid, _gid)		\
+#define current_fsuid_fsgid(_fsuid, _fsgid)	\
 do {						\
-	*(_uid) = current->fsuid;		\
-	*(_gid) = current->fsgid;		\
+	const struct cred *__cred;		\
+	__cred = current_cred();		\
+	*(_fsuid) = __cred->fsuid;		\
+	*(_fsgid) = __cred->fsgid;		\
 } while(0)
 
 #endif /* _LINUX_CRED_H */
diff --git a/include/linux/crypto.h b/include/linux/crypto.h
index 3d2317e4af2e..3bacd71509fb 100644
--- a/include/linux/crypto.h
+++ b/include/linux/crypto.h
@@ -36,7 +36,8 @@
 #define CRYPTO_ALG_TYPE_ABLKCIPHER	0x00000005
 #define CRYPTO_ALG_TYPE_GIVCIPHER	0x00000006
 #define CRYPTO_ALG_TYPE_DIGEST		0x00000008
-#define CRYPTO_ALG_TYPE_HASH		0x00000009
+#define CRYPTO_ALG_TYPE_HASH		0x00000008
+#define CRYPTO_ALG_TYPE_SHASH		0x00000009
 #define CRYPTO_ALG_TYPE_AHASH		0x0000000a
 #define CRYPTO_ALG_TYPE_RNG		0x0000000c
 
@@ -220,6 +221,7 @@ struct ablkcipher_alg {
 
 struct ahash_alg {
 	int (*init)(struct ahash_request *req);
+	int (*reinit)(struct ahash_request *req);
 	int (*update)(struct ahash_request *req);
 	int (*final)(struct ahash_request *req);
 	int (*digest)(struct ahash_request *req);
@@ -480,6 +482,8 @@ struct crypto_tfm {
 		struct compress_tfm compress;
 		struct rng_tfm rng;
 	} crt_u;
+
+	void (*exit)(struct crypto_tfm *tfm);
 	
 	struct crypto_alg *__crt_alg;
 
@@ -544,7 +548,9 @@ struct crypto_attr_u32 {
  * Transform user interface.
  */
  
-struct crypto_tfm *crypto_alloc_tfm(const char *alg_name, u32 tfm_flags);
+struct crypto_tfm *crypto_alloc_tfm(const char *alg_name,
+				    const struct crypto_type *frontend,
+				    u32 type, u32 mask);
 struct crypto_tfm *crypto_alloc_base(const char *alg_name, u32 type, u32 mask);
 void crypto_free_tfm(struct crypto_tfm *tfm);
 
diff --git a/include/linux/dcache.h b/include/linux/dcache.h
index efba1de629ac..a37359d0bad1 100644
--- a/include/linux/dcache.h
+++ b/include/linux/dcache.h
@@ -228,9 +228,9 @@ extern void d_delete(struct dentry *);
 
 /* allocate/de-allocate */
 extern struct dentry * d_alloc(struct dentry *, const struct qstr *);
-extern struct dentry * d_alloc_anon(struct inode *);
 extern struct dentry * d_splice_alias(struct inode *, struct dentry *);
 extern struct dentry * d_add_ci(struct dentry *, struct inode *, struct qstr *);
+extern struct dentry * d_obtain_alias(struct inode *);
 extern void shrink_dcache_sb(struct super_block *);
 extern void shrink_dcache_parent(struct dentry *);
 extern void shrink_dcache_for_umount(struct super_block *);
@@ -287,6 +287,7 @@ static inline struct dentry *d_add_unique(struct dentry *entry, struct inode *in
 
 /* used for rename() and baskets */
 extern void d_move(struct dentry *, struct dentry *);
+extern struct dentry *d_ancestor(struct dentry *, struct dentry *);
 
 /* appendix may either be NULL or be used for transname suffixes */
 extern struct dentry * d_lookup(struct dentry *, struct qstr *);
diff --git a/include/linux/dcbnl.h b/include/linux/dcbnl.h
new file mode 100644
index 000000000000..b0ef274e0031
--- /dev/null
+++ b/include/linux/dcbnl.h
@@ -0,0 +1,340 @@
+/*
+ * Copyright (c) 2008, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * Author: Lucy Liu <lucy.liu@intel.com>
+ */
+
+#ifndef __LINUX_DCBNL_H__
+#define __LINUX_DCBNL_H__
+
+#define DCB_PROTO_VERSION 1
+
+struct dcbmsg {
+	unsigned char      dcb_family;
+	__u8               cmd;
+	__u16              dcb_pad;
+};
+
+/**
+ * enum dcbnl_commands - supported DCB commands
+ *
+ * @DCB_CMD_UNDEFINED: unspecified command to catch errors
+ * @DCB_CMD_GSTATE: request the state of DCB in the device
+ * @DCB_CMD_SSTATE: set the state of DCB in the device
+ * @DCB_CMD_PGTX_GCFG: request the priority group configuration for Tx
+ * @DCB_CMD_PGTX_SCFG: set the priority group configuration for Tx
+ * @DCB_CMD_PGRX_GCFG: request the priority group configuration for Rx
+ * @DCB_CMD_PGRX_SCFG: set the priority group configuration for Rx
+ * @DCB_CMD_PFC_GCFG: request the priority flow control configuration
+ * @DCB_CMD_PFC_SCFG: set the priority flow control configuration
+ * @DCB_CMD_SET_ALL: apply all changes to the underlying device
+ * @DCB_CMD_GPERM_HWADDR: get the permanent MAC address of the underlying
+ *                        device.  Only useful when using bonding.
+ * @DCB_CMD_GCAP: request the DCB capabilities of the device
+ * @DCB_CMD_GNUMTCS: get the number of traffic classes currently supported
+ * @DCB_CMD_SNUMTCS: set the number of traffic classes
+ * @DCB_CMD_GBCN: set backward congestion notification configuration
+ * @DCB_CMD_SBCN: get backward congestion notification configration.
+ */
+enum dcbnl_commands {
+	DCB_CMD_UNDEFINED,
+
+	DCB_CMD_GSTATE,
+	DCB_CMD_SSTATE,
+
+	DCB_CMD_PGTX_GCFG,
+	DCB_CMD_PGTX_SCFG,
+	DCB_CMD_PGRX_GCFG,
+	DCB_CMD_PGRX_SCFG,
+
+	DCB_CMD_PFC_GCFG,
+	DCB_CMD_PFC_SCFG,
+
+	DCB_CMD_SET_ALL,
+
+	DCB_CMD_GPERM_HWADDR,
+
+	DCB_CMD_GCAP,
+
+	DCB_CMD_GNUMTCS,
+	DCB_CMD_SNUMTCS,
+
+	DCB_CMD_PFC_GSTATE,
+	DCB_CMD_PFC_SSTATE,
+
+	DCB_CMD_BCN_GCFG,
+	DCB_CMD_BCN_SCFG,
+
+	__DCB_CMD_ENUM_MAX,
+	DCB_CMD_MAX = __DCB_CMD_ENUM_MAX - 1,
+};
+
+/**
+ * enum dcbnl_attrs - DCB top-level netlink attributes
+ *
+ * @DCB_ATTR_UNDEFINED: unspecified attribute to catch errors
+ * @DCB_ATTR_IFNAME: interface name of the underlying device (NLA_STRING)
+ * @DCB_ATTR_STATE: enable state of DCB in the device (NLA_U8)
+ * @DCB_ATTR_PFC_STATE: enable state of PFC in the device (NLA_U8)
+ * @DCB_ATTR_PFC_CFG: priority flow control configuration (NLA_NESTED)
+ * @DCB_ATTR_NUM_TC: number of traffic classes supported in the device (NLA_U8)
+ * @DCB_ATTR_PG_CFG: priority group configuration (NLA_NESTED)
+ * @DCB_ATTR_SET_ALL: bool to commit changes to hardware or not (NLA_U8)
+ * @DCB_ATTR_PERM_HWADDR: MAC address of the physical device (NLA_NESTED)
+ * @DCB_ATTR_CAP: DCB capabilities of the device (NLA_NESTED)
+ * @DCB_ATTR_NUMTCS: number of traffic classes supported (NLA_NESTED)
+ * @DCB_ATTR_BCN: backward congestion notification configuration (NLA_NESTED)
+ */
+enum dcbnl_attrs {
+	DCB_ATTR_UNDEFINED,
+
+	DCB_ATTR_IFNAME,
+	DCB_ATTR_STATE,
+	DCB_ATTR_PFC_STATE,
+	DCB_ATTR_PFC_CFG,
+	DCB_ATTR_NUM_TC,
+	DCB_ATTR_PG_CFG,
+	DCB_ATTR_SET_ALL,
+	DCB_ATTR_PERM_HWADDR,
+	DCB_ATTR_CAP,
+	DCB_ATTR_NUMTCS,
+	DCB_ATTR_BCN,
+
+	__DCB_ATTR_ENUM_MAX,
+	DCB_ATTR_MAX = __DCB_ATTR_ENUM_MAX - 1,
+};
+
+/**
+ * enum dcbnl_pfc_attrs - DCB Priority Flow Control user priority nested attrs
+ *
+ * @DCB_PFC_UP_ATTR_UNDEFINED: unspecified attribute to catch errors
+ * @DCB_PFC_UP_ATTR_0: Priority Flow Control value for User Priority 0 (NLA_U8)
+ * @DCB_PFC_UP_ATTR_1: Priority Flow Control value for User Priority 1 (NLA_U8)
+ * @DCB_PFC_UP_ATTR_2: Priority Flow Control value for User Priority 2 (NLA_U8)
+ * @DCB_PFC_UP_ATTR_3: Priority Flow Control value for User Priority 3 (NLA_U8)
+ * @DCB_PFC_UP_ATTR_4: Priority Flow Control value for User Priority 4 (NLA_U8)
+ * @DCB_PFC_UP_ATTR_5: Priority Flow Control value for User Priority 5 (NLA_U8)
+ * @DCB_PFC_UP_ATTR_6: Priority Flow Control value for User Priority 6 (NLA_U8)
+ * @DCB_PFC_UP_ATTR_7: Priority Flow Control value for User Priority 7 (NLA_U8)
+ * @DCB_PFC_UP_ATTR_MAX: highest attribute number currently defined
+ * @DCB_PFC_UP_ATTR_ALL: apply to all priority flow control attrs (NLA_FLAG)
+ *
+ */
+enum dcbnl_pfc_up_attrs {
+	DCB_PFC_UP_ATTR_UNDEFINED,
+
+	DCB_PFC_UP_ATTR_0,
+	DCB_PFC_UP_ATTR_1,
+	DCB_PFC_UP_ATTR_2,
+	DCB_PFC_UP_ATTR_3,
+	DCB_PFC_UP_ATTR_4,
+	DCB_PFC_UP_ATTR_5,
+	DCB_PFC_UP_ATTR_6,
+	DCB_PFC_UP_ATTR_7,
+	DCB_PFC_UP_ATTR_ALL,
+
+	__DCB_PFC_UP_ATTR_ENUM_MAX,
+	DCB_PFC_UP_ATTR_MAX = __DCB_PFC_UP_ATTR_ENUM_MAX - 1,
+};
+
+/**
+ * enum dcbnl_pg_attrs - DCB Priority Group attributes
+ *
+ * @DCB_PG_ATTR_UNDEFINED: unspecified attribute to catch errors
+ * @DCB_PG_ATTR_TC_0: Priority Group Traffic Class 0 configuration (NLA_NESTED)
+ * @DCB_PG_ATTR_TC_1: Priority Group Traffic Class 1 configuration (NLA_NESTED)
+ * @DCB_PG_ATTR_TC_2: Priority Group Traffic Class 2 configuration (NLA_NESTED)
+ * @DCB_PG_ATTR_TC_3: Priority Group Traffic Class 3 configuration (NLA_NESTED)
+ * @DCB_PG_ATTR_TC_4: Priority Group Traffic Class 4 configuration (NLA_NESTED)
+ * @DCB_PG_ATTR_TC_5: Priority Group Traffic Class 5 configuration (NLA_NESTED)
+ * @DCB_PG_ATTR_TC_6: Priority Group Traffic Class 6 configuration (NLA_NESTED)
+ * @DCB_PG_ATTR_TC_7: Priority Group Traffic Class 7 configuration (NLA_NESTED)
+ * @DCB_PG_ATTR_TC_MAX: highest attribute number currently defined
+ * @DCB_PG_ATTR_TC_ALL: apply to all traffic classes (NLA_NESTED)
+ * @DCB_PG_ATTR_BW_ID_0: Percent of link bandwidth for Priority Group 0 (NLA_U8)
+ * @DCB_PG_ATTR_BW_ID_1: Percent of link bandwidth for Priority Group 1 (NLA_U8)
+ * @DCB_PG_ATTR_BW_ID_2: Percent of link bandwidth for Priority Group 2 (NLA_U8)
+ * @DCB_PG_ATTR_BW_ID_3: Percent of link bandwidth for Priority Group 3 (NLA_U8)
+ * @DCB_PG_ATTR_BW_ID_4: Percent of link bandwidth for Priority Group 4 (NLA_U8)
+ * @DCB_PG_ATTR_BW_ID_5: Percent of link bandwidth for Priority Group 5 (NLA_U8)
+ * @DCB_PG_ATTR_BW_ID_6: Percent of link bandwidth for Priority Group 6 (NLA_U8)
+ * @DCB_PG_ATTR_BW_ID_7: Percent of link bandwidth for Priority Group 7 (NLA_U8)
+ * @DCB_PG_ATTR_BW_ID_MAX: highest attribute number currently defined
+ * @DCB_PG_ATTR_BW_ID_ALL: apply to all priority groups (NLA_FLAG)
+ *
+ */
+enum dcbnl_pg_attrs {
+	DCB_PG_ATTR_UNDEFINED,
+
+	DCB_PG_ATTR_TC_0,
+	DCB_PG_ATTR_TC_1,
+	DCB_PG_ATTR_TC_2,
+	DCB_PG_ATTR_TC_3,
+	DCB_PG_ATTR_TC_4,
+	DCB_PG_ATTR_TC_5,
+	DCB_PG_ATTR_TC_6,
+	DCB_PG_ATTR_TC_7,
+	DCB_PG_ATTR_TC_MAX,
+	DCB_PG_ATTR_TC_ALL,
+
+	DCB_PG_ATTR_BW_ID_0,
+	DCB_PG_ATTR_BW_ID_1,
+	DCB_PG_ATTR_BW_ID_2,
+	DCB_PG_ATTR_BW_ID_3,
+	DCB_PG_ATTR_BW_ID_4,
+	DCB_PG_ATTR_BW_ID_5,
+	DCB_PG_ATTR_BW_ID_6,
+	DCB_PG_ATTR_BW_ID_7,
+	DCB_PG_ATTR_BW_ID_MAX,
+	DCB_PG_ATTR_BW_ID_ALL,
+
+	__DCB_PG_ATTR_ENUM_MAX,
+	DCB_PG_ATTR_MAX = __DCB_PG_ATTR_ENUM_MAX - 1,
+};
+
+/**
+ * enum dcbnl_tc_attrs - DCB Traffic Class attributes
+ *
+ * @DCB_TC_ATTR_PARAM_UNDEFINED: unspecified attribute to catch errors
+ * @DCB_TC_ATTR_PARAM_PGID: (NLA_U8) Priority group the traffic class belongs to
+ *                          Valid values are:  0-7
+ * @DCB_TC_ATTR_PARAM_UP_MAPPING: (NLA_U8) Traffic class to user priority map
+ *                                Some devices may not support changing the
+ *                                user priority map of a TC.
+ * @DCB_TC_ATTR_PARAM_STRICT_PRIO: (NLA_U8) Strict priority setting
+ *                                 0 - none
+ *                                 1 - group strict
+ *                                 2 - link strict
+ * @DCB_TC_ATTR_PARAM_BW_PCT: optional - (NLA_U8) If supported by the device and
+ *                            not configured to use link strict priority,
+ *                            this is the percentage of bandwidth of the
+ *                            priority group this traffic class belongs to
+ * @DCB_TC_ATTR_PARAM_ALL: (NLA_FLAG) all traffic class parameters
+ *
+ */
+enum dcbnl_tc_attrs {
+	DCB_TC_ATTR_PARAM_UNDEFINED,
+
+	DCB_TC_ATTR_PARAM_PGID,
+	DCB_TC_ATTR_PARAM_UP_MAPPING,
+	DCB_TC_ATTR_PARAM_STRICT_PRIO,
+	DCB_TC_ATTR_PARAM_BW_PCT,
+	DCB_TC_ATTR_PARAM_ALL,
+
+	__DCB_TC_ATTR_PARAM_ENUM_MAX,
+	DCB_TC_ATTR_PARAM_MAX = __DCB_TC_ATTR_PARAM_ENUM_MAX - 1,
+};
+
+/**
+ * enum dcbnl_cap_attrs - DCB Capability attributes
+ *
+ * @DCB_CAP_ATTR_UNDEFINED: unspecified attribute to catch errors
+ * @DCB_CAP_ATTR_ALL: (NLA_FLAG) all capability parameters
+ * @DCB_CAP_ATTR_PG: (NLA_U8) device supports Priority Groups
+ * @DCB_CAP_ATTR_PFC: (NLA_U8) device supports Priority Flow Control
+ * @DCB_CAP_ATTR_UP2TC: (NLA_U8) device supports user priority to
+ *                               traffic class mapping
+ * @DCB_CAP_ATTR_PG_TCS: (NLA_U8) bitmap where each bit represents a
+ *                                number of traffic classes the device
+ *                                can be configured to use for Priority Groups
+ * @DCB_CAP_ATTR_PFC_TCS: (NLA_U8) bitmap where each bit represents a
+ *                                 number of traffic classes the device can be
+ *                                 configured to use for Priority Flow Control
+ * @DCB_CAP_ATTR_GSP: (NLA_U8) device supports group strict priority
+ * @DCB_CAP_ATTR_BCN: (NLA_U8) device supports Backwards Congestion
+ *                             Notification
+ */
+enum dcbnl_cap_attrs {
+	DCB_CAP_ATTR_UNDEFINED,
+	DCB_CAP_ATTR_ALL,
+	DCB_CAP_ATTR_PG,
+	DCB_CAP_ATTR_PFC,
+	DCB_CAP_ATTR_UP2TC,
+	DCB_CAP_ATTR_PG_TCS,
+	DCB_CAP_ATTR_PFC_TCS,
+	DCB_CAP_ATTR_GSP,
+	DCB_CAP_ATTR_BCN,
+
+	__DCB_CAP_ATTR_ENUM_MAX,
+	DCB_CAP_ATTR_MAX = __DCB_CAP_ATTR_ENUM_MAX - 1,
+};
+
+/**
+ * enum dcbnl_numtcs_attrs - number of traffic classes
+ *
+ * @DCB_NUMTCS_ATTR_UNDEFINED: unspecified attribute to catch errors
+ * @DCB_NUMTCS_ATTR_ALL: (NLA_FLAG) all traffic class attributes
+ * @DCB_NUMTCS_ATTR_PG: (NLA_U8) number of traffic classes used for
+ *                               priority groups
+ * @DCB_NUMTCS_ATTR_PFC: (NLA_U8) number of traffic classes which can
+ *                                support priority flow control
+ */
+enum dcbnl_numtcs_attrs {
+	DCB_NUMTCS_ATTR_UNDEFINED,
+	DCB_NUMTCS_ATTR_ALL,
+	DCB_NUMTCS_ATTR_PG,
+	DCB_NUMTCS_ATTR_PFC,
+
+	__DCB_NUMTCS_ATTR_ENUM_MAX,
+	DCB_NUMTCS_ATTR_MAX = __DCB_NUMTCS_ATTR_ENUM_MAX - 1,
+};
+
+enum dcbnl_bcn_attrs{
+	DCB_BCN_ATTR_UNDEFINED = 0,
+
+	DCB_BCN_ATTR_RP_0,
+	DCB_BCN_ATTR_RP_1,
+	DCB_BCN_ATTR_RP_2,
+	DCB_BCN_ATTR_RP_3,
+	DCB_BCN_ATTR_RP_4,
+	DCB_BCN_ATTR_RP_5,
+	DCB_BCN_ATTR_RP_6,
+	DCB_BCN_ATTR_RP_7,
+	DCB_BCN_ATTR_RP_ALL,
+
+	DCB_BCN_ATTR_BCNA_0,
+	DCB_BCN_ATTR_BCNA_1,
+	DCB_BCN_ATTR_ALPHA,
+	DCB_BCN_ATTR_BETA,
+	DCB_BCN_ATTR_GD,
+	DCB_BCN_ATTR_GI,
+	DCB_BCN_ATTR_TMAX,
+	DCB_BCN_ATTR_TD,
+	DCB_BCN_ATTR_RMIN,
+	DCB_BCN_ATTR_W,
+	DCB_BCN_ATTR_RD,
+	DCB_BCN_ATTR_RU,
+	DCB_BCN_ATTR_WRTT,
+	DCB_BCN_ATTR_RI,
+	DCB_BCN_ATTR_C,
+	DCB_BCN_ATTR_ALL,
+
+	__DCB_BCN_ATTR_ENUM_MAX,
+	DCB_BCN_ATTR_MAX = __DCB_BCN_ATTR_ENUM_MAX - 1,
+};
+
+/**
+ * enum dcb_general_attr_values - general DCB attribute values
+ *
+ * @DCB_ATTR_UNDEFINED: value used to indicate an attribute is not supported
+ *
+ */
+enum dcb_general_attr_values {
+	DCB_ATTR_VALUE_UNDEFINED = 0xff
+};
+
+
+#endif /* __LINUX_DCBNL_H__ */
diff --git a/include/linux/dccp.h b/include/linux/dccp.h
index 6080449fbec9..61734e27abb7 100644
--- a/include/linux/dccp.h
+++ b/include/linux/dccp.h
@@ -168,6 +168,8 @@ enum {
 	DCCPO_MIN_CCID_SPECIFIC = 128,
 	DCCPO_MAX_CCID_SPECIFIC = 255,
 };
+/* maximum size of a single TLV-encoded DCCP option (sans type/len bytes) */
+#define DCCP_SINGLE_OPT_MAXLEN	253
 
 /* DCCP CCIDS */
 enum {
@@ -176,29 +178,23 @@ enum {
 };
 
 /* DCCP features (RFC 4340 section 6.4) */
-enum {
+enum dccp_feature_numbers {
 	DCCPF_RESERVED = 0,
 	DCCPF_CCID = 1,
-	DCCPF_SHORT_SEQNOS = 2,		/* XXX: not yet implemented */
+	DCCPF_SHORT_SEQNOS = 2,
 	DCCPF_SEQUENCE_WINDOW = 3,
-	DCCPF_ECN_INCAPABLE = 4,	/* XXX: not yet implemented */
+	DCCPF_ECN_INCAPABLE = 4,
 	DCCPF_ACK_RATIO = 5,
 	DCCPF_SEND_ACK_VECTOR = 6,
 	DCCPF_SEND_NDP_COUNT = 7,
 	DCCPF_MIN_CSUM_COVER = 8,
-	DCCPF_DATA_CHECKSUM = 9,	/* XXX: not yet implemented */
+	DCCPF_DATA_CHECKSUM = 9,
 	/* 10-127 reserved */
 	DCCPF_MIN_CCID_SPECIFIC = 128,
+	DCCPF_SEND_LEV_RATE = 192,	/* RFC 4342, sec. 8.4 */
 	DCCPF_MAX_CCID_SPECIFIC = 255,
 };
 
-/* this structure is argument to DCCP_SOCKOPT_CHANGE_X */
-struct dccp_so_feat {
-	__u8 dccpsf_feat;
-	__u8 __user *dccpsf_val;
-	__u8 dccpsf_len;
-};
-
 /* DCCP socket options */
 #define DCCP_SOCKOPT_PACKET_SIZE	1 /* XXX deprecated, without effect */
 #define DCCP_SOCKOPT_SERVICE		2
@@ -208,6 +204,10 @@ struct dccp_so_feat {
 #define DCCP_SOCKOPT_SERVER_TIMEWAIT	6
 #define DCCP_SOCKOPT_SEND_CSCOV		10
 #define DCCP_SOCKOPT_RECV_CSCOV		11
+#define DCCP_SOCKOPT_AVAILABLE_CCIDS	12
+#define DCCP_SOCKOPT_CCID		13
+#define DCCP_SOCKOPT_TX_CCID		14
+#define DCCP_SOCKOPT_RX_CCID		15
 #define DCCP_SOCKOPT_CCID_RX_INFO	128
 #define DCCP_SOCKOPT_CCID_TX_INFO	192
 
@@ -360,7 +360,6 @@ static inline unsigned int dccp_hdr_len(const struct sk_buff *skb)
 #define DCCPF_INITIAL_SEQUENCE_WINDOW		100
 #define DCCPF_INITIAL_ACK_RATIO			2
 #define DCCPF_INITIAL_CCID			DCCPC_CCID2
-#define DCCPF_INITIAL_SEND_ACK_VECTOR		1
 /* FIXME: for now we're default to 1 but it should really be 0 */
 #define DCCPF_INITIAL_SEND_NDP_COUNT		1
 
@@ -370,20 +369,11 @@ static inline unsigned int dccp_hdr_len(const struct sk_buff *skb)
   * Will be used to pass the state from dccp_request_sock to dccp_sock.
   *
   * @dccpms_sequence_window - Sequence Window Feature (section 7.5.2)
-  * @dccpms_ccid - Congestion Control Id (CCID) (section 10)
-  * @dccpms_send_ack_vector - Send Ack Vector Feature (section 11.5)
-  * @dccpms_send_ndp_count - Send NDP Count Feature (7.7.2)
-  * @dccpms_ack_ratio - Ack Ratio Feature (section 11.3)
   * @dccpms_pending - List of features being negotiated
   * @dccpms_conf -
   */
 struct dccp_minisock {
 	__u64			dccpms_sequence_window;
-	__u8			dccpms_rx_ccid;
-	__u8			dccpms_tx_ccid;
-	__u8			dccpms_send_ack_vector;
-	__u8			dccpms_send_ndp_count;
-	__u8			dccpms_ack_ratio;
 	struct list_head	dccpms_pending;
 	struct list_head	dccpms_conf;
 };
@@ -411,6 +401,7 @@ extern void dccp_minisock_init(struct dccp_minisock *dmsk);
  * @dreq_iss: initial sequence number sent on the Response (RFC 4340, 7.1)
  * @dreq_isr: initial sequence number received on the Request
  * @dreq_service: service code present on the Request (there is just one)
+ * @dreq_featneg: feature negotiation options for this connection
  * The following two fields are analogous to the ones in dccp_sock:
  * @dreq_timestamp_echo: last received timestamp to echo (13.1)
  * @dreq_timestamp_echo: the time of receiving the last @dreq_timestamp_echo
@@ -420,6 +411,7 @@ struct dccp_request_sock {
 	__u64			 dreq_iss;
 	__u64			 dreq_isr;
 	__be32			 dreq_service;
+	struct list_head	 dreq_featneg;
 	__u32			 dreq_timestamp_echo;
 	__u32			 dreq_timestamp_time;
 };
@@ -493,10 +485,12 @@ struct dccp_ackvec;
  * @dccps_r_ack_ratio - feature-remote Ack Ratio
  * @dccps_pcslen - sender   partial checksum coverage (via sockopt)
  * @dccps_pcrlen - receiver partial checksum coverage (via sockopt)
+ * @dccps_send_ndp_count - local Send NDP Count feature (7.7.2)
  * @dccps_ndp_count - number of Non Data Packets since last data packet
  * @dccps_mss_cache - current value of MSS (path MTU minus header sizes)
  * @dccps_rate_last - timestamp for rate-limiting DCCP-Sync (RFC 4340, 7.5.4)
  * @dccps_minisock - associated minisock (accessed via dccp_msk)
+ * @dccps_featneg - tracks feature-negotiation state (mostly during handshake)
  * @dccps_hc_rx_ackvec - rx half connection ack vector
  * @dccps_hc_rx_ccid - CCID used for the receiver (or receiving half-connection)
  * @dccps_hc_tx_ccid - CCID used for the sender (or sending half-connection)
@@ -529,11 +523,13 @@ struct dccp_sock {
 	__u32				dccps_timestamp_time;
 	__u16				dccps_l_ack_ratio;
 	__u16				dccps_r_ack_ratio;
-	__u16				dccps_pcslen;
-	__u16				dccps_pcrlen;
+	__u8				dccps_pcslen:4;
+	__u8				dccps_pcrlen:4;
+	__u8				dccps_send_ndp_count:1;
 	__u64				dccps_ndp_count:48;
 	unsigned long			dccps_rate_last;
 	struct dccp_minisock		dccps_minisock;
+	struct list_head		dccps_featneg;
 	struct dccp_ackvec		*dccps_hc_rx_ackvec;
 	struct ccid			*dccps_hc_rx_ccid;
 	struct ccid			*dccps_hc_tx_ccid;
diff --git a/include/linux/debug_locks.h b/include/linux/debug_locks.h
index 4aaa4afb1cb9..096476f1fb35 100644
--- a/include/linux/debug_locks.h
+++ b/include/linux/debug_locks.h
@@ -17,7 +17,7 @@ extern int debug_locks_off(void);
 ({									\
 	int __ret = 0;							\
 									\
-	if (unlikely(c)) {						\
+	if (!oops_in_progress && unlikely(c)) {				\
 		if (debug_locks_off() && !debug_locks_silent)		\
 			WARN_ON(1);					\
 		__ret = 1;						\
diff --git a/include/linux/device-mapper.h b/include/linux/device-mapper.h
index 08d783592b73..c17fd334e574 100644
--- a/include/linux/device-mapper.h
+++ b/include/linux/device-mapper.h
@@ -69,8 +69,7 @@ typedef int (*dm_status_fn) (struct dm_target *ti, status_type_t status_type,
 
 typedef int (*dm_message_fn) (struct dm_target *ti, unsigned argc, char **argv);
 
-typedef int (*dm_ioctl_fn) (struct dm_target *ti, struct inode *inode,
-			    struct file *filp, unsigned int cmd,
+typedef int (*dm_ioctl_fn) (struct dm_target *ti, unsigned int cmd,
 			    unsigned long arg);
 
 typedef int (*dm_merge_fn) (struct dm_target *ti, struct bvec_merge_data *bvm,
@@ -85,7 +84,7 @@ void dm_set_device_limits(struct dm_target *ti, struct block_device *bdev);
 
 struct dm_dev {
 	struct block_device *bdev;
-	int mode;
+	fmode_t mode;
 	char name[16];
 };
 
@@ -95,7 +94,7 @@ struct dm_dev {
  * FIXME: too many arguments.
  */
 int dm_get_device(struct dm_target *ti, const char *path, sector_t start,
-		  sector_t len, int mode, struct dm_dev **result);
+		  sector_t len, fmode_t mode, struct dm_dev **result);
 void dm_put_device(struct dm_target *ti, struct dm_dev *d);
 
 /*
@@ -223,7 +222,7 @@ int dm_set_geometry(struct mapped_device *md, struct hd_geometry *geo);
 /*
  * First create an empty table.
  */
-int dm_table_create(struct dm_table **result, int mode,
+int dm_table_create(struct dm_table **result, fmode_t mode,
 		    unsigned num_targets, struct mapped_device *md);
 
 /*
@@ -254,7 +253,7 @@ void dm_table_put(struct dm_table *t);
  */
 sector_t dm_table_get_size(struct dm_table *t);
 unsigned int dm_table_get_num_targets(struct dm_table *t);
-int dm_table_get_mode(struct dm_table *t);
+fmode_t dm_table_get_mode(struct dm_table *t);
 struct mapped_device *dm_table_get_md(struct dm_table *t);
 
 /*
@@ -354,6 +353,9 @@ void *dm_vcalloc(unsigned long nmemb, unsigned long elem_size);
  */
 #define dm_round_up(n, sz) (dm_div_up((n), (sz)) * (sz))
 
+#define dm_array_too_big(fixed, obj, num) \
+	((num) > (UINT_MAX - (fixed)) / (obj))
+
 static inline sector_t to_sector(unsigned long n)
 {
 	return (n >> SECTOR_SHIFT);
diff --git a/include/linux/device.h b/include/linux/device.h
index 246937c9cbc7..1a3686d15f98 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -90,6 +90,9 @@ int __must_check bus_for_each_drv(struct bus_type *bus,
 				  struct device_driver *start, void *data,
 				  int (*fn)(struct device_driver *, void *));
 
+void bus_sort_breadthfirst(struct bus_type *bus,
+			   int (*compare)(const struct device *a,
+					  const struct device *b));
 /*
  * Bus notifiers: Get notified of addition/removal of devices
  * and binding/unbinding of drivers to devices.
@@ -447,7 +450,7 @@ static inline void set_dev_node(struct device *dev, int node)
 }
 #endif
 
-static inline void *dev_get_drvdata(struct device *dev)
+static inline void *dev_get_drvdata(const struct device *dev)
 {
 	return dev->driver_data;
 }
@@ -502,7 +505,6 @@ extern struct device *device_create(struct class *cls, struct device *parent,
 				    dev_t devt, void *drvdata,
 				    const char *fmt, ...)
 				    __attribute__((format(printf, 5, 6)));
-#define device_create_drvdata	device_create
 extern void device_destroy(struct class *cls, dev_t devt);
 
 /*
@@ -551,7 +553,11 @@ extern const char *dev_driver_string(const struct device *dev);
 #define dev_info(dev, format, arg...)		\
 	dev_printk(KERN_INFO , dev , format , ## arg)
 
-#ifdef DEBUG
+#if defined(CONFIG_DYNAMIC_PRINTK_DEBUG)
+#define dev_dbg(dev, format, ...) do { \
+	dynamic_dev_dbg(dev, format, ##__VA_ARGS__); \
+	} while (0)
+#elif defined(DEBUG)
 #define dev_dbg(dev, format, arg...)		\
 	dev_printk(KERN_DEBUG , dev , format , ## arg)
 #else
@@ -567,6 +573,14 @@ extern const char *dev_driver_string(const struct device *dev);
 	({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
 #endif
 
+/*
+ * dev_WARN() acts like dev_printk(), but with the key difference
+ * of using a WARN/WARN_ON to get the message out, including the
+ * file/line information and a backtrace.
+ */
+#define dev_WARN(dev, format, arg...) \
+	WARN(1, "Device: %s\n" format, dev_driver_string(dev), ## arg);
+
 /* Create alias, so I can be autoloaded. */
 #define MODULE_ALIAS_CHARDEV(major,minor) \
 	MODULE_ALIAS("char-major-" __stringify(major) "-" __stringify(minor))
diff --git a/include/linux/dm-region-hash.h b/include/linux/dm-region-hash.h
new file mode 100644
index 000000000000..a9e652a41373
--- /dev/null
+++ b/include/linux/dm-region-hash.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2003 Sistina Software Limited.
+ * Copyright (C) 2004-2008 Red Hat, Inc. All rights reserved.
+ *
+ * Device-Mapper dirty region hash interface.
+ *
+ * This file is released under the GPL.
+ */
+
+#ifndef DM_REGION_HASH_H
+#define DM_REGION_HASH_H
+
+#include <linux/dm-dirty-log.h>
+
+/*-----------------------------------------------------------------
+ * Region hash
+ *----------------------------------------------------------------*/
+struct dm_region_hash;
+struct dm_region;
+
+/*
+ * States a region can have.
+ */
+enum dm_rh_region_states {
+	DM_RH_CLEAN	 = 0x01,	/* No writes in flight. */
+	DM_RH_DIRTY	 = 0x02,	/* Writes in flight. */
+	DM_RH_NOSYNC	 = 0x04,	/* Out of sync. */
+	DM_RH_RECOVERING = 0x08,	/* Under resynchronization. */
+};
+
+/*
+ * Region hash create/destroy.
+ */
+struct bio_list;
+struct dm_region_hash *dm_region_hash_create(
+		void *context, void (*dispatch_bios)(void *context,
+						     struct bio_list *bios),
+		void (*wakeup_workers)(void *context),
+		void (*wakeup_all_recovery_waiters)(void *context),
+		sector_t target_begin, unsigned max_recovery,
+		struct dm_dirty_log *log, uint32_t region_size,
+		region_t nr_regions);
+void dm_region_hash_destroy(struct dm_region_hash *rh);
+
+struct dm_dirty_log *dm_rh_dirty_log(struct dm_region_hash *rh);
+
+/*
+ * Conversion functions.
+ */
+region_t dm_rh_bio_to_region(struct dm_region_hash *rh, struct bio *bio);
+sector_t dm_rh_region_to_sector(struct dm_region_hash *rh, region_t region);
+void *dm_rh_region_context(struct dm_region *reg);
+
+/*
+ * Get region size and key (ie. number of the region).
+ */
+sector_t dm_rh_get_region_size(struct dm_region_hash *rh);
+region_t dm_rh_get_region_key(struct dm_region *reg);
+
+/*
+ * Get/set/update region state (and dirty log).
+ *
+ */
+int dm_rh_get_state(struct dm_region_hash *rh, region_t region, int may_block);
+void dm_rh_set_state(struct dm_region_hash *rh, region_t region,
+		     enum dm_rh_region_states state, int may_block);
+
+/* Non-zero errors_handled leaves the state of the region NOSYNC */
+void dm_rh_update_states(struct dm_region_hash *rh, int errors_handled);
+
+/* Flush the region hash and dirty log. */
+int dm_rh_flush(struct dm_region_hash *rh);
+
+/* Inc/dec pending count on regions. */
+void dm_rh_inc_pending(struct dm_region_hash *rh, struct bio_list *bios);
+void dm_rh_dec(struct dm_region_hash *rh, region_t region);
+
+/* Delay bios on regions. */
+void dm_rh_delay(struct dm_region_hash *rh, struct bio *bio);
+
+void dm_rh_mark_nosync(struct dm_region_hash *rh,
+		       struct bio *bio, unsigned done, int error);
+
+/*
+ * Region recovery control.
+ */
+
+/* Prepare some regions for recovery by starting to quiesce them. */
+void dm_rh_recovery_prepare(struct dm_region_hash *rh);
+
+/* Try fetching a quiesced region for recovery. */
+struct dm_region *dm_rh_recovery_start(struct dm_region_hash *rh);
+
+/* Report recovery end on a region. */
+void dm_rh_recovery_end(struct dm_region *reg, int error);
+
+/* Returns number of regions with recovery work outstanding. */
+int dm_rh_recovery_in_flight(struct dm_region_hash *rh);
+
+/* Start/stop recovery. */
+void dm_rh_start_recovery(struct dm_region_hash *rh);
+void dm_rh_stop_recovery(struct dm_region_hash *rh);
+
+#endif /* DM_REGION_HASH_H */
diff --git a/include/linux/dma_remapping.h b/include/linux/dma_remapping.h
new file mode 100644
index 000000000000..952df39c989d
--- /dev/null
+++ b/include/linux/dma_remapping.h
@@ -0,0 +1,156 @@
+#ifndef _DMA_REMAPPING_H
+#define _DMA_REMAPPING_H
+
+/*
+ * VT-d hardware uses 4KiB page size regardless of host page size.
+ */
+#define VTD_PAGE_SHIFT		(12)
+#define VTD_PAGE_SIZE		(1UL << VTD_PAGE_SHIFT)
+#define VTD_PAGE_MASK		(((u64)-1) << VTD_PAGE_SHIFT)
+#define VTD_PAGE_ALIGN(addr)	(((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK)
+
+#define IOVA_PFN(addr)		((addr) >> PAGE_SHIFT)
+#define DMA_32BIT_PFN		IOVA_PFN(DMA_32BIT_MASK)
+#define DMA_64BIT_PFN		IOVA_PFN(DMA_64BIT_MASK)
+
+
+/*
+ * 0: Present
+ * 1-11: Reserved
+ * 12-63: Context Ptr (12 - (haw-1))
+ * 64-127: Reserved
+ */
+struct root_entry {
+	u64	val;
+	u64	rsvd1;
+};
+#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
+static inline bool root_present(struct root_entry *root)
+{
+	return (root->val & 1);
+}
+static inline void set_root_present(struct root_entry *root)
+{
+	root->val |= 1;
+}
+static inline void set_root_value(struct root_entry *root, unsigned long value)
+{
+	root->val |= value & VTD_PAGE_MASK;
+}
+
+struct context_entry;
+static inline struct context_entry *
+get_context_addr_from_root(struct root_entry *root)
+{
+	return (struct context_entry *)
+		(root_present(root)?phys_to_virt(
+		root->val & VTD_PAGE_MASK) :
+		NULL);
+}
+
+/*
+ * low 64 bits:
+ * 0: present
+ * 1: fault processing disable
+ * 2-3: translation type
+ * 12-63: address space root
+ * high 64 bits:
+ * 0-2: address width
+ * 3-6: aval
+ * 8-23: domain id
+ */
+struct context_entry {
+	u64 lo;
+	u64 hi;
+};
+#define context_present(c) ((c).lo & 1)
+#define context_fault_disable(c) (((c).lo >> 1) & 1)
+#define context_translation_type(c) (((c).lo >> 2) & 3)
+#define context_address_root(c) ((c).lo & VTD_PAGE_MASK)
+#define context_address_width(c) ((c).hi &  7)
+#define context_domain_id(c) (((c).hi >> 8) & ((1 << 16) - 1))
+
+#define context_set_present(c) do {(c).lo |= 1;} while (0)
+#define context_set_fault_enable(c) \
+	do {(c).lo &= (((u64)-1) << 2) | 1;} while (0)
+#define context_set_translation_type(c, val) \
+	do { \
+		(c).lo &= (((u64)-1) << 4) | 3; \
+		(c).lo |= ((val) & 3) << 2; \
+	} while (0)
+#define CONTEXT_TT_MULTI_LEVEL 0
+#define context_set_address_root(c, val) \
+	do {(c).lo |= (val) & VTD_PAGE_MASK; } while (0)
+#define context_set_address_width(c, val) do {(c).hi |= (val) & 7;} while (0)
+#define context_set_domain_id(c, val) \
+	do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0)
+#define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0)
+
+/*
+ * 0: readable
+ * 1: writable
+ * 2-6: reserved
+ * 7: super page
+ * 8-11: available
+ * 12-63: Host physcial address
+ */
+struct dma_pte {
+	u64 val;
+};
+#define dma_clear_pte(p)	do {(p).val = 0;} while (0)
+
+#define DMA_PTE_READ (1)
+#define DMA_PTE_WRITE (2)
+
+#define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0)
+#define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0)
+#define dma_set_pte_prot(p, prot) \
+		do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0)
+#define dma_pte_addr(p) ((p).val & VTD_PAGE_MASK)
+#define dma_set_pte_addr(p, addr) do {\
+		(p).val |= ((addr) & VTD_PAGE_MASK); } while (0)
+#define dma_pte_present(p) (((p).val & 3) != 0)
+
+struct intel_iommu;
+
+struct dmar_domain {
+	int	id;			/* domain id */
+	struct intel_iommu *iommu;	/* back pointer to owning iommu */
+
+	struct list_head devices; 	/* all devices' list */
+	struct iova_domain iovad;	/* iova's that belong to this domain */
+
+	struct dma_pte	*pgd;		/* virtual address */
+	spinlock_t	mapping_lock;	/* page table lock */
+	int		gaw;		/* max guest address width */
+
+	/* adjusted guest address width, 0 is level 2 30-bit */
+	int		agaw;
+
+#define DOMAIN_FLAG_MULTIPLE_DEVICES 1
+	int		flags;
+};
+
+/* PCI domain-device relationship */
+struct device_domain_info {
+	struct list_head link;	/* link to domain siblings */
+	struct list_head global; /* link to global list */
+	u8 bus;			/* PCI bus numer */
+	u8 devfn;		/* PCI devfn number */
+	struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
+	struct dmar_domain *domain; /* pointer to domain */
+};
+
+extern int init_dmars(void);
+extern void free_dmar_iommu(struct intel_iommu *iommu);
+
+extern int dmar_disabled;
+
+#ifndef CONFIG_DMAR_GFX_WA
+static inline void iommu_prepare_gfx_mapping(void)
+{
+	return;
+}
+#endif /* !CONFIG_DMAR_GFX_WA */
+
+#endif
diff --git a/include/linux/dmar.h b/include/linux/dmar.h
index c360c558e59e..f1984fc3e06d 100644
--- a/include/linux/dmar.h
+++ b/include/linux/dmar.h
@@ -45,7 +45,6 @@ extern struct list_head dmar_drhd_units;
 	list_for_each_entry(drhd, &dmar_drhd_units, list)
 
 extern int dmar_table_init(void);
-extern int early_dmar_detect(void);
 extern int dmar_dev_scope_init(void);
 
 /* Intel IOMMU detection */
diff --git a/include/linux/dmi.h b/include/linux/dmi.h
index e5084eb5943a..34161907b2f8 100644
--- a/include/linux/dmi.h
+++ b/include/linux/dmi.h
@@ -44,8 +44,10 @@ extern const struct dmi_device * dmi_find_device(int type, const char *name,
 extern void dmi_scan_machine(void);
 extern int dmi_get_year(int field);
 extern int dmi_name_in_vendors(const char *str);
+extern int dmi_name_in_serial(const char *str);
 extern int dmi_available;
 extern int dmi_walk(void (*decode)(const struct dmi_header *));
+extern bool dmi_match(enum dmi_field f, const char *str);
 
 #else
 
@@ -56,9 +58,12 @@ static inline const struct dmi_device * dmi_find_device(int type, const char *na
 static inline void dmi_scan_machine(void) { return; }
 static inline int dmi_get_year(int year) { return 0; }
 static inline int dmi_name_in_vendors(const char *s) { return 0; }
+static inline int dmi_name_in_serial(const char *s) { return 0; }
 #define dmi_available 0
 static inline int dmi_walk(void (*decode)(const struct dmi_header *))
 	{ return -1; }
+static inline bool dmi_match(enum dmi_field f, const char *str)
+	{ return false; }
 
 #endif
 
diff --git a/include/linux/ds1286.h b/include/linux/ds1286.h
index d8989860e4ce..45ea0aa0aeb9 100644
--- a/include/linux/ds1286.h
+++ b/include/linux/ds1286.h
@@ -8,8 +8,6 @@
 #ifndef __LINUX_DS1286_H
 #define __LINUX_DS1286_H
 
-#include <asm/ds1286.h>
-
 /**********************************************************************
  * register summary
  **********************************************************************/
diff --git a/include/linux/dvb/frontend.h b/include/linux/dvb/frontend.h
index 6e4ace270276..79a8ed8e6a7d 100644
--- a/include/linux/dvb/frontend.h
+++ b/include/linux/dvb/frontend.h
@@ -166,6 +166,7 @@ typedef enum fe_modulation {
 	VSB_16,
 	PSK_8,
 	APSK_16,
+	APSK_32,
 	DQPSK,
 } fe_modulation_t;
 
@@ -295,6 +296,7 @@ typedef enum fe_delivery_system {
 	SYS_DVBC_ANNEX_AC,
 	SYS_DVBC_ANNEX_B,
 	SYS_DVBT,
+	SYS_DSS,
 	SYS_DVBS,
 	SYS_DVBS2,
 	SYS_DVBH,
diff --git a/include/linux/dynamic_printk.h b/include/linux/dynamic_printk.h
new file mode 100644
index 000000000000..2d528d009074
--- /dev/null
+++ b/include/linux/dynamic_printk.h
@@ -0,0 +1,93 @@
+#ifndef _DYNAMIC_PRINTK_H
+#define _DYNAMIC_PRINTK_H
+
+#define DYNAMIC_DEBUG_HASH_BITS 6
+#define DEBUG_HASH_TABLE_SIZE (1 << DYNAMIC_DEBUG_HASH_BITS)
+
+#define TYPE_BOOLEAN 1
+
+#define DYNAMIC_ENABLED_ALL 0
+#define DYNAMIC_ENABLED_NONE 1
+#define DYNAMIC_ENABLED_SOME 2
+
+extern int dynamic_enabled;
+
+/* dynamic_printk_enabled, and dynamic_printk_enabled2 are bitmasks in which
+ * bit n is set to 1 if any modname hashes into the bucket n, 0 otherwise. They
+ * use independent hash functions, to reduce the chance of false positives.
+ */
+extern long long dynamic_printk_enabled;
+extern long long dynamic_printk_enabled2;
+
+struct mod_debug {
+	char *modname;
+	char *logical_modname;
+	char *flag_names;
+	int type;
+	int hash;
+	int hash2;
+} __attribute__((aligned(8)));
+
+int register_dynamic_debug_module(char *mod_name, int type, char *share_name,
+					char *flags, int hash, int hash2);
+
+#if defined(CONFIG_DYNAMIC_PRINTK_DEBUG)
+extern int unregister_dynamic_debug_module(char *mod_name);
+extern int __dynamic_dbg_enabled_helper(char *modname, int type,
+					int value, int hash);
+
+#define __dynamic_dbg_enabled(module, type, value, level, hash)  ({	     \
+	int __ret = 0;							     \
+	if (unlikely((dynamic_printk_enabled & (1LL << DEBUG_HASH)) &&	     \
+			(dynamic_printk_enabled2 & (1LL << DEBUG_HASH2))))   \
+			__ret = __dynamic_dbg_enabled_helper(module, type,   \
+								value, hash);\
+	__ret; })
+
+#define dynamic_pr_debug(fmt, ...) do {					    \
+	static char mod_name[]						    \
+	__attribute__((section("__verbose_strings")))			    \
+	 = KBUILD_MODNAME;						    \
+	static struct mod_debug descriptor				    \
+	__used								    \
+	__attribute__((section("__verbose"), aligned(8))) =		    \
+	{ mod_name, mod_name, NULL, TYPE_BOOLEAN, DEBUG_HASH, DEBUG_HASH2 };\
+	if (__dynamic_dbg_enabled(KBUILD_MODNAME, TYPE_BOOLEAN,		    \
+						0, 0, DEBUG_HASH))	    \
+		printk(KERN_DEBUG KBUILD_MODNAME ":" fmt,		    \
+				##__VA_ARGS__);				    \
+	} while (0)
+
+#define dynamic_dev_dbg(dev, format, ...) do {				    \
+	static char mod_name[]						    \
+	__attribute__((section("__verbose_strings")))			    \
+	 = KBUILD_MODNAME;						    \
+	static struct mod_debug descriptor				    \
+	__used								    \
+	__attribute__((section("__verbose"), aligned(8))) =		    \
+	{ mod_name, mod_name, NULL, TYPE_BOOLEAN, DEBUG_HASH, DEBUG_HASH2 };\
+	if (__dynamic_dbg_enabled(KBUILD_MODNAME, TYPE_BOOLEAN,		    \
+						0, 0, DEBUG_HASH))	    \
+			dev_printk(KERN_DEBUG, dev,			    \
+					KBUILD_MODNAME ": " format,	    \
+					##__VA_ARGS__);			    \
+	} while (0)
+
+#else
+
+static inline int unregister_dynamic_debug_module(const char *mod_name)
+{
+	return 0;
+}
+static inline int __dynamic_dbg_enabled_helper(char *modname, int type,
+						int value, int hash)
+{
+	return 0;
+}
+
+#define __dynamic_dbg_enabled(module, type, value, level, hash)  ({ 0; })
+#define dynamic_pr_debug(fmt, ...)  do { } while (0)
+#define dynamic_dev_dbg(dev, format, ...)  do { } while (0)
+#endif
+
+#endif
diff --git a/include/linux/efi.h b/include/linux/efi.h
index 807373d467f7..bb66feb164bd 100644
--- a/include/linux/efi.h
+++ b/include/linux/efi.h
@@ -208,6 +208,9 @@ typedef efi_status_t efi_set_virtual_address_map_t (unsigned long memory_map_siz
 #define EFI_GLOBAL_VARIABLE_GUID \
     EFI_GUID(  0x8be4df61, 0x93ca, 0x11d2, 0xaa, 0x0d, 0x00, 0xe0, 0x98, 0x03, 0x2b, 0x8c )
 
+#define UV_SYSTEM_TABLE_GUID \
+    EFI_GUID(  0x3b13a7d4, 0x633e, 0x11dd, 0x93, 0xec, 0xda, 0x25, 0x56, 0xd8, 0x95, 0x93 )
+
 typedef struct {
 	efi_guid_t guid;
 	unsigned long table;
@@ -255,6 +258,7 @@ extern struct efi {
 	unsigned long boot_info;	/* boot info table */
 	unsigned long hcdp;		/* HCDP table */
 	unsigned long uga;		/* UGA table */
+	unsigned long uv_systab;	/* UV system table */
 	efi_get_time_t *get_time;
 	efi_set_time_t *set_time;
 	efi_get_wakeup_time_t *get_wakeup_time;
diff --git a/include/linux/elevator.h b/include/linux/elevator.h
index 92f6f634e3e6..7a204256b155 100644
--- a/include/linux/elevator.h
+++ b/include/linux/elevator.h
@@ -28,7 +28,7 @@ typedef void (elevator_activate_req_fn) (struct request_queue *, struct request
 typedef void (elevator_deactivate_req_fn) (struct request_queue *, struct request *);
 
 typedef void *(elevator_init_fn) (struct request_queue *);
-typedef void (elevator_exit_fn) (elevator_t *);
+typedef void (elevator_exit_fn) (struct elevator_queue *);
 
 struct elevator_ops
 {
@@ -62,8 +62,8 @@ struct elevator_ops
 
 struct elv_fs_entry {
 	struct attribute attr;
-	ssize_t (*show)(elevator_t *, char *);
-	ssize_t (*store)(elevator_t *, const char *, size_t);
+	ssize_t (*show)(struct elevator_queue *, char *);
+	ssize_t (*store)(struct elevator_queue *, const char *, size_t);
 };
 
 /*
@@ -130,7 +130,7 @@ extern ssize_t elv_iosched_show(struct request_queue *, char *);
 extern ssize_t elv_iosched_store(struct request_queue *, const char *, size_t);
 
 extern int elevator_init(struct request_queue *, char *);
-extern void elevator_exit(elevator_t *);
+extern void elevator_exit(struct elevator_queue *);
 extern int elv_rq_merge_ok(struct request *, struct bio *);
 
 /*
diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h
index 25d62e6e3290..1cb0f0b90926 100644
--- a/include/linux/etherdevice.h
+++ b/include/linux/etherdevice.h
@@ -27,6 +27,7 @@
 #include <linux/if_ether.h>
 #include <linux/netdevice.h>
 #include <linux/random.h>
+#include <asm/unaligned.h>
 
 #ifdef __KERNEL__
 extern __be16		eth_type_trans(struct sk_buff *skb, struct net_device *dev);
@@ -41,6 +42,10 @@ extern int eth_header_cache(const struct neighbour *neigh, struct hh_cache *hh);
 extern void eth_header_cache_update(struct hh_cache *hh,
 				    const struct net_device *dev,
 				    const unsigned char *haddr);
+extern int eth_mac_addr(struct net_device *dev, void *p);
+extern int eth_change_mtu(struct net_device *dev, int new_mtu);
+extern int eth_validate_addr(struct net_device *dev);
+
 
 
 extern struct net_device *alloc_etherdev_mq(int sizeof_priv, unsigned int queue_count);
@@ -136,6 +141,47 @@ static inline unsigned compare_ether_addr(const u8 *addr1, const u8 *addr2)
 	BUILD_BUG_ON(ETH_ALEN != 6);
 	return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) != 0;
 }
+
+static inline unsigned long zap_last_2bytes(unsigned long value)
+{
+#ifdef __BIG_ENDIAN
+	return value >> 16;
+#else
+	return value << 16;
+#endif
+}
+
+/**
+ * compare_ether_addr_64bits - Compare two Ethernet addresses
+ * @addr1: Pointer to an array of 8 bytes
+ * @addr2: Pointer to an other array of 8 bytes
+ *
+ * Compare two ethernet addresses, returns 0 if equal.
+ * Same result than "memcmp(addr1, addr2, ETH_ALEN)" but without conditional
+ * branches, and possibly long word memory accesses on CPU allowing cheap
+ * unaligned memory reads.
+ * arrays = { byte1, byte2, byte3, byte4, byte6, byte7, pad1, pad2}
+ *
+ * Please note that alignment of addr1 & addr2 is only guaranted to be 16 bits.
+ */
+
+static inline unsigned compare_ether_addr_64bits(const u8 addr1[6+2],
+						 const u8 addr2[6+2])
+{
+#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
+	unsigned long fold = ((*(unsigned long *)addr1) ^
+			      (*(unsigned long *)addr2));
+
+	if (sizeof(fold) == 8)
+		return zap_last_2bytes(fold) != 0;
+
+	fold |= zap_last_2bytes((*(unsigned long *)(addr1 + 4)) ^
+				(*(unsigned long *)(addr2 + 4)));
+	return fold != 0;
+#else
+	return compare_ether_addr(addr1, addr2);
+#endif
+}
 #endif	/* __KERNEL__ */
 
 #endif	/* _LINUX_ETHERDEVICE_H */
diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
index b4b038b89ee6..27c67a542235 100644
--- a/include/linux/ethtool.h
+++ b/include/linux/ethtool.h
@@ -467,6 +467,8 @@ struct ethtool_ops {
 
 #define	ETHTOOL_GRXFH		0x00000029 /* Get RX flow hash configuration */
 #define	ETHTOOL_SRXFH		0x0000002a /* Set RX flow hash configuration */
+#define ETHTOOL_GGRO		0x0000002b /* Get GRO enable (ethtool_value) */
+#define ETHTOOL_SGRO		0x0000002c /* Set GRO enable (ethtool_value) */
 
 /* compatibility with older code */
 #define SPARC_ETH_GSET		ETHTOOL_GSET
diff --git a/include/linux/ext2_fs.h b/include/linux/ext2_fs.h
index 2efe7b863cff..78c775a83f7c 100644
--- a/include/linux/ext2_fs.h
+++ b/include/linux/ext2_fs.h
@@ -47,7 +47,7 @@
 #ifdef EXT2FS_DEBUG
 #	define ext2_debug(f, a...)	{ \
 					printk ("EXT2-fs DEBUG (%s, %d): %s:", \
-						__FILE__, __LINE__, __FUNCTION__); \
+						__FILE__, __LINE__, __func__); \
 				  	printk (f, ## a); \
 					}
 #else
diff --git a/include/linux/ext3_fs.h b/include/linux/ext3_fs.h
index 8120fa1bc235..d14f02918483 100644
--- a/include/linux/ext3_fs.h
+++ b/include/linux/ext3_fs.h
@@ -43,7 +43,7 @@
 #define ext3_debug(f, a...)						\
 	do {								\
 		printk (KERN_DEBUG "EXT3-fs DEBUG (%s, %d): %s:",	\
-			__FILE__, __LINE__, __FUNCTION__);		\
+			__FILE__, __LINE__, __func__);		\
 		printk (KERN_DEBUG f, ## a);				\
 	} while (0)
 #else
@@ -380,6 +380,8 @@ struct ext3_inode {
 #define EXT3_MOUNT_QUOTA		0x80000 /* Some quota option set */
 #define EXT3_MOUNT_USRQUOTA		0x100000 /* "old" user quota */
 #define EXT3_MOUNT_GRPQUOTA		0x200000 /* "old" group quota */
+#define EXT3_MOUNT_DATA_ERR_ABORT	0x400000 /* Abort on file data write
+						  * error in ordered mode */
 
 /* Compatibility, for having both ext2_fs.h and ext3_fs.h included at once */
 #ifndef _LINUX_EXT2_FS_H
@@ -871,7 +873,7 @@ extern void ext3_update_dynamic_rev (struct super_block *sb);
 #define ext3_std_error(sb, errno)				\
 do {								\
 	if ((errno))						\
-		__ext3_std_error((sb), __FUNCTION__, (errno));	\
+		__ext3_std_error((sb), __func__, (errno));	\
 } while (0)
 
 /*
diff --git a/include/linux/ext3_jbd.h b/include/linux/ext3_jbd.h
index 8c43b13a02fe..cf82d519be40 100644
--- a/include/linux/ext3_jbd.h
+++ b/include/linux/ext3_jbd.h
@@ -137,17 +137,17 @@ int __ext3_journal_dirty_metadata(const char *where,
 				handle_t *handle, struct buffer_head *bh);
 
 #define ext3_journal_get_undo_access(handle, bh) \
-	__ext3_journal_get_undo_access(__FUNCTION__, (handle), (bh))
+	__ext3_journal_get_undo_access(__func__, (handle), (bh))
 #define ext3_journal_get_write_access(handle, bh) \
-	__ext3_journal_get_write_access(__FUNCTION__, (handle), (bh))
+	__ext3_journal_get_write_access(__func__, (handle), (bh))
 #define ext3_journal_revoke(handle, blocknr, bh) \
-	__ext3_journal_revoke(__FUNCTION__, (handle), (blocknr), (bh))
+	__ext3_journal_revoke(__func__, (handle), (blocknr), (bh))
 #define ext3_journal_get_create_access(handle, bh) \
-	__ext3_journal_get_create_access(__FUNCTION__, (handle), (bh))
+	__ext3_journal_get_create_access(__func__, (handle), (bh))
 #define ext3_journal_dirty_metadata(handle, bh) \
-	__ext3_journal_dirty_metadata(__FUNCTION__, (handle), (bh))
+	__ext3_journal_dirty_metadata(__func__, (handle), (bh))
 #define ext3_journal_forget(handle, bh) \
-	__ext3_journal_forget(__FUNCTION__, (handle), (bh))
+	__ext3_journal_forget(__func__, (handle), (bh))
 
 int ext3_journal_dirty_data(handle_t *handle, struct buffer_head *bh);
 
@@ -160,7 +160,7 @@ static inline handle_t *ext3_journal_start(struct inode *inode, int nblocks)
 }
 
 #define ext3_journal_stop(handle) \
-	__ext3_journal_stop(__FUNCTION__, (handle))
+	__ext3_journal_stop(__func__, (handle))
 
 static inline handle_t *ext3_journal_current_handle(void)
 {
diff --git a/include/linux/fault-inject.h b/include/linux/fault-inject.h
index 32368c4f0326..06ca9b21dad2 100644
--- a/include/linux/fault-inject.h
+++ b/include/linux/fault-inject.h
@@ -81,4 +81,13 @@ static inline void cleanup_fault_attr_dentries(struct fault_attr *attr)
 
 #endif /* CONFIG_FAULT_INJECTION */
 
+#ifdef CONFIG_FAILSLAB
+extern bool should_failslab(size_t size, gfp_t gfpflags);
+#else
+static inline bool should_failslab(size_t size, gfp_t gfpflags)
+{
+	return false;
+}
+#endif /* CONFIG_FAILSLAB */
+
 #endif /* _LINUX_FAULT_INJECT_H */
diff --git a/include/linux/fb.h b/include/linux/fb.h
index 531ccd5f5960..1ee63df5be92 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -808,6 +808,7 @@ struct fb_tile_ops {
 struct fb_info {
 	int node;
 	int flags;
+	struct mutex lock;		/* Lock for open/release/ioctl funcs */
 	struct fb_var_screeninfo var;	/* Current var */
 	struct fb_fix_screeninfo fix;	/* Current fix */
 	struct fb_monspecs monspecs;	/* Current Monitor specs */
@@ -887,7 +888,7 @@ struct fb_info {
 #define fb_writeq sbus_writeq
 #define fb_memset sbus_memset_io
 
-#elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || defined(__hppa__) || (defined(__sh__) && !defined(__SH5__)) || defined(__powerpc__) || defined(__avr32__)
+#elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || defined(__hppa__) || defined(__sh__) || defined(__powerpc__) || defined(__avr32__)
 
 #define fb_readb __raw_readb
 #define fb_readw __raw_readw
diff --git a/include/linux/fddidevice.h b/include/linux/fddidevice.h
index e61e42dfd317..155bafd9e886 100644
--- a/include/linux/fddidevice.h
+++ b/include/linux/fddidevice.h
@@ -27,6 +27,7 @@
 #ifdef __KERNEL__
 extern __be16	fddi_type_trans(struct sk_buff *skb,
 				struct net_device *dev);
+extern int fddi_change_mtu(struct net_device *dev, int new_mtu);
 extern struct net_device *alloc_fddidev(int sizeof_priv);
 #endif
 
diff --git a/include/linux/file.h b/include/linux/file.h
index a20259e248a5..335a0a5c316e 100644
--- a/include/linux/file.h
+++ b/include/linux/file.h
@@ -19,10 +19,10 @@ struct file_operations;
 struct vfsmount;
 struct dentry;
 extern int init_file(struct file *, struct vfsmount *mnt,
-		struct dentry *dentry, mode_t mode,
+		struct dentry *dentry, fmode_t mode,
 		const struct file_operations *fop);
 extern struct file *alloc_file(struct vfsmount *, struct dentry *dentry,
-		mode_t mode, const struct file_operations *fop);
+		fmode_t mode, const struct file_operations *fop);
 
 static inline void fput_light(struct file *file, int fput_needed)
 {
diff --git a/include/linux/filter.h b/include/linux/filter.h
index b6ea9aa9e853..1354aaf6abbe 100644
--- a/include/linux/filter.h
+++ b/include/linux/filter.h
@@ -122,7 +122,8 @@ struct sock_fprog	/* Required for SO_ATTACH_FILTER. */
 #define SKF_AD_PKTTYPE 	4
 #define SKF_AD_IFINDEX 	8
 #define SKF_AD_NLATTR	12
-#define SKF_AD_MAX 	16
+#define SKF_AD_NLATTR_NEST	16
+#define SKF_AD_MAX	20
 #define SKF_NET_OFF   (-0x100000)
 #define SKF_LL_OFF    (-0x200000)
 
diff --git a/include/linux/firewire-cdev.h b/include/linux/firewire-cdev.h
index 0f0e271f97fa..4d078e99c017 100644
--- a/include/linux/firewire-cdev.h
+++ b/include/linux/firewire-cdev.h
@@ -154,8 +154,13 @@ struct fw_cdev_event_iso_interrupt {
  * @request:       Valid if @common.type == %FW_CDEV_EVENT_REQUEST
  * @iso_interrupt: Valid if @common.type == %FW_CDEV_EVENT_ISO_INTERRUPT
  *
- * Convenience union for userspace use.  Events could be read(2) into a char
- * buffer and then cast to this union for further processing.
+ * Convenience union for userspace use.  Events could be read(2) into an
+ * appropriately aligned char buffer and then cast to this union for further
+ * processing.  Note that for a request, response or iso_interrupt event,
+ * the data[] or header[] may make the size of the full event larger than
+ * sizeof(union fw_cdev_event).  Also note that if you attempt to read(2)
+ * an event into a buffer that is not large enough for it, the data that does
+ * not fit will be discarded so that the next read(2) will return a new event.
  */
 union fw_cdev_event {
 	struct fw_cdev_event_common common;
diff --git a/include/linux/freezer.h b/include/linux/freezer.h
index deddeedf3257..5a361f85cfec 100644
--- a/include/linux/freezer.h
+++ b/include/linux/freezer.h
@@ -6,7 +6,7 @@
 #include <linux/sched.h>
 #include <linux/wait.h>
 
-#ifdef CONFIG_PM_SLEEP
+#ifdef CONFIG_FREEZER
 /*
  * Check if a process has been frozen
  */
@@ -39,29 +39,14 @@ static inline void clear_freeze_flag(struct task_struct *p)
 	clear_tsk_thread_flag(p, TIF_FREEZE);
 }
 
-/*
- * Wake up a frozen process
- *
- * task_lock() is taken to prevent the race with refrigerator() which may
- * occur if the freezing of tasks fails.  Namely, without the lock, if the
- * freezing of tasks failed, thaw_tasks() might have run before a task in
- * refrigerator() could call frozen_process(), in which case the task would be
- * frozen and no one would thaw it.
- */
-static inline int thaw_process(struct task_struct *p)
+static inline bool should_send_signal(struct task_struct *p)
 {
-	task_lock(p);
-	if (frozen(p)) {
-		p->flags &= ~PF_FROZEN;
-		task_unlock(p);
-		wake_up_process(p);
-		return 1;
-	}
-	clear_freeze_flag(p);
-	task_unlock(p);
-	return 0;
+	return !(p->flags & PF_FREEZER_NOSIG);
 }
 
+/* Takes and releases task alloc lock using task_lock() */
+extern int thaw_process(struct task_struct *p);
+
 extern void refrigerator(void);
 extern int freeze_processes(void);
 extern void thaw_processes(void);
@@ -75,6 +60,15 @@ static inline int try_to_freeze(void)
 		return 0;
 }
 
+extern bool freeze_task(struct task_struct *p, bool sig_only);
+extern void cancel_freezing(struct task_struct *p);
+
+#ifdef CONFIG_CGROUP_FREEZER
+extern int cgroup_frozen(struct task_struct *task);
+#else /* !CONFIG_CGROUP_FREEZER */
+static inline int cgroup_frozen(struct task_struct *task) { return 0; }
+#endif /* !CONFIG_CGROUP_FREEZER */
+
 /*
  * The PF_FREEZER_SKIP flag should be set by a vfork parent right before it
  * calls wait_for_completion(&vfork) and reset right after it returns from this
@@ -166,7 +160,7 @@ static inline void set_freezable_with_signal(void)
 	} while (try_to_freeze());					\
 	__retval;							\
 })
-#else /* !CONFIG_PM_SLEEP */
+#else /* !CONFIG_FREEZER */
 static inline int frozen(struct task_struct *p) { return 0; }
 static inline int freezing(struct task_struct *p) { return 0; }
 static inline void set_freeze_flag(struct task_struct *p) {}
@@ -191,6 +185,6 @@ static inline void set_freezable_with_signal(void) {}
 #define wait_event_freezable_timeout(wq, condition, timeout)		\
 		wait_event_interruptible_timeout(wq, condition, timeout)
 
-#endif /* !CONFIG_PM_SLEEP */
+#endif /* !CONFIG_FREEZER */
 
 #endif	/* FREEZER_H_INCLUDED */
diff --git a/include/linux/fs.h b/include/linux/fs.h
index a6a625be13fc..001ded4845b4 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -63,18 +63,32 @@ extern int dir_notify_enable;
 #define MAY_ACCESS 16
 #define MAY_OPEN 32
 
-#define FMODE_READ 1
-#define FMODE_WRITE 2
+/* file is open for reading */
+#define FMODE_READ		((__force fmode_t)1)
+/* file is open for writing */
+#define FMODE_WRITE		((__force fmode_t)2)
+/* file is seekable */
+#define FMODE_LSEEK		((__force fmode_t)4)
+/* file can be accessed using pread/pwrite */
+#define FMODE_PREAD		((__force fmode_t)8)
+#define FMODE_PWRITE		FMODE_PREAD	/* These go hand in hand */
+/* File is opened for execution with sys_execve / sys_uselib */
+#define FMODE_EXEC		((__force fmode_t)16)
+/* File is opened with O_NDELAY (only set for block devices) */
+#define FMODE_NDELAY		((__force fmode_t)32)
+/* File is opened with O_EXCL (only set for block devices) */
+#define FMODE_EXCL		((__force fmode_t)64)
+/* File is opened using open(.., 3, ..) and is writeable only for ioctls
+   (specialy hack for floppy.c) */
+#define FMODE_WRITE_IOCTL	((__force fmode_t)128)
 
-/* Internal kernel extensions */
-#define FMODE_LSEEK	4
-#define FMODE_PREAD	8
-#define FMODE_PWRITE	FMODE_PREAD	/* These go hand in hand */
-
-/* File is being opened for execution. Primary users of this flag are
-   distributed filesystems that can use it to achieve correct ETXTBUSY
-   behavior for cross-node execution/opening_for_writing of files */
-#define FMODE_EXEC	16
+/*
+ * Don't update ctime and mtime.
+ *
+ * Currently a special hack for the XFS open_by_handle ioctl, but we'll
+ * hopefully graduate it to a proper O_CMTIME flag supported by open(2) soon.
+ */
+#define FMODE_NOCMTIME		((__force fmode_t)2048)
 
 #define RW_MASK		1
 #define RWA_MASK	2
@@ -136,7 +150,7 @@ extern int dir_notify_enable;
 /*
  * Superblock flags that can be altered by MS_REMOUNT
  */
-#define MS_RMT_MASK	(MS_RDONLY|MS_SYNCHRONOUS|MS_MANDLOCK)
+#define MS_RMT_MASK	(MS_RDONLY|MS_SYNCHRONOUS|MS_MANDLOCK|MS_I_VERSION)
 
 /*
  * Old magic mount flag and mask
@@ -310,6 +324,7 @@ struct poll_table_struct;
 struct kstatfs;
 struct vm_area_struct;
 struct vfsmount;
+struct cred;
 
 extern void __init inode_init(void);
 extern void __init inode_init_early(void);
@@ -484,13 +499,6 @@ struct address_space_operations {
 	int (*readpages)(struct file *filp, struct address_space *mapping,
 			struct list_head *pages, unsigned nr_pages);
 
-	/*
-	 * ext3 requires that a successful prepare_write() call be followed
-	 * by a commit_write() call - they must be balanced
-	 */
-	int (*prepare_write)(struct file *, struct page *, unsigned, unsigned);
-	int (*commit_write)(struct file *, struct page *, unsigned, unsigned);
-
 	int (*write_begin)(struct file *, struct address_space *mapping,
 				loff_t pos, unsigned len, unsigned flags,
 				struct page **pagep, void **fsdata);
@@ -825,10 +833,10 @@ struct file {
 	const struct file_operations	*f_op;
 	atomic_long_t		f_count;
 	unsigned int 		f_flags;
-	mode_t			f_mode;
+	fmode_t			f_mode;
 	loff_t			f_pos;
 	struct fown_struct	f_owner;
-	unsigned int		f_uid, f_gid;
+	const struct cred	*f_cred;
 	struct file_ra_state	f_ra;
 
 	u64			f_version;
@@ -1037,7 +1045,6 @@ extern int vfs_setlease(struct file *, long, struct file_lock **);
 extern int lease_modify(struct file_lock **, int);
 extern int lock_may_read(struct inode *, loff_t start, unsigned long count);
 extern int lock_may_write(struct inode *, loff_t start, unsigned long count);
-extern struct seq_operations locks_seq_operations;
 #else /* !CONFIG_FILE_LOCKING */
 #define fcntl_getlk(a, b) ({ -EINVAL; })
 #define fcntl_setlk(a, b, c, d) ({ -EACCES; })
@@ -1152,6 +1159,7 @@ struct super_block {
 	char s_id[32];				/* Informational name */
 
 	void 			*s_fs_info;	/* Filesystem private info */
+	fmode_t			s_mode;
 
 	/*
 	 * The next field is for VFS *only*. No filesystems have any business
@@ -1195,7 +1203,7 @@ enum {
 #define has_fs_excl() atomic_read(&current->fs_excl)
 
 #define is_owner_or_cap(inode)	\
-	((current->fsuid == (inode)->i_uid) || capable(CAP_FOWNER))
+	((current_fsuid() == (inode)->i_uid) || capable(CAP_FOWNER))
 
 /* not quite ready to be deprecated, but... */
 extern void lock_super(struct super_block *);
@@ -1266,20 +1274,7 @@ int generic_osync_inode(struct inode *, struct address_space *, int);
  * to have different dirent layouts depending on the binary type.
  */
 typedef int (*filldir_t)(void *, const char *, int, loff_t, u64, unsigned);
-
-struct block_device_operations {
-	int (*open) (struct inode *, struct file *);
-	int (*release) (struct inode *, struct file *);
-	int (*ioctl) (struct inode *, struct file *, unsigned, unsigned long);
-	long (*unlocked_ioctl) (struct file *, unsigned, unsigned long);
-	long (*compat_ioctl) (struct file *, unsigned, unsigned long);
-	int (*direct_access) (struct block_device *, sector_t,
-						void **, unsigned long *);
-	int (*media_changed) (struct gendisk *);
-	int (*revalidate_disk) (struct gendisk *);
-	int (*getgeo)(struct block_device *, struct hd_geometry *);
-	struct module *owner;
-};
+struct block_device_operations;
 
 /* These macros are for out of kernel modules to test that
  * the kernel supports the unlocked_ioctl and compat_ioctl
@@ -1593,7 +1588,6 @@ extern int get_sb_pseudo(struct file_system_type *, char *,
 	struct vfsmount *mnt);
 extern int simple_set_mnt(struct vfsmount *mnt, struct super_block *sb);
 int __put_super_and_need_restart(struct super_block *sb);
-void unnamed_dev_init(void);
 
 /* Alas, no aliases. Too much hassle with bringing module.h everywhere */
 #define fops_get(fops) \
@@ -1689,7 +1683,8 @@ extern int do_truncate(struct dentry *, loff_t start, unsigned int time_attrs,
 extern long do_sys_open(int dfd, const char __user *filename, int flags,
 			int mode);
 extern struct file *filp_open(const char *, int, int);
-extern struct file * dentry_open(struct dentry *, struct vfsmount *, int);
+extern struct file * dentry_open(struct dentry *, struct vfsmount *, int,
+				 const struct cred *);
 extern int filp_close(struct file *, fl_owner_t id);
 extern char * getname(const char __user *);
 
@@ -1714,7 +1709,7 @@ extern struct block_device *bdget(dev_t);
 extern void bd_set_size(struct block_device *, loff_t size);
 extern void bd_forget(struct inode *inode);
 extern void bdput(struct block_device *);
-extern struct block_device *open_by_devnum(dev_t, unsigned);
+extern struct block_device *open_by_devnum(dev_t, fmode_t);
 #else
 static inline void bd_forget(struct inode *inode) {}
 #endif
@@ -1724,13 +1719,10 @@ extern const struct file_operations bad_sock_fops;
 extern const struct file_operations def_fifo_fops;
 #ifdef CONFIG_BLOCK
 extern int ioctl_by_bdev(struct block_device *, unsigned, unsigned long);
-extern int blkdev_ioctl(struct inode *, struct file *, unsigned, unsigned long);
-extern int blkdev_driver_ioctl(struct inode *inode, struct file *file,
-			       struct gendisk *disk, unsigned cmd,
-			       unsigned long arg);
+extern int blkdev_ioctl(struct block_device *, fmode_t, unsigned, unsigned long);
 extern long compat_blkdev_ioctl(struct file *, unsigned, unsigned long);
-extern int blkdev_get(struct block_device *, mode_t, unsigned);
-extern int blkdev_put(struct block_device *);
+extern int blkdev_get(struct block_device *, fmode_t);
+extern int blkdev_put(struct block_device *, fmode_t);
 extern int bd_claim(struct block_device *, void *);
 extern void bd_release(struct block_device *);
 #ifdef CONFIG_SYSFS
@@ -1761,9 +1753,10 @@ extern void chrdev_show(struct seq_file *,off_t);
 extern const char *__bdevname(dev_t, char *buffer);
 extern const char *bdevname(struct block_device *bdev, char *buffer);
 extern struct block_device *lookup_bdev(const char *);
-extern struct block_device *open_bdev_excl(const char *, int, void *);
-extern void close_bdev_excl(struct block_device *);
+extern struct block_device *open_bdev_exclusive(const char *, fmode_t, void *);
+extern void close_bdev_exclusive(struct block_device *, fmode_t);
 extern void blkdev_show(struct seq_file *,off_t);
+
 #else
 #define BLKDEV_MAJOR_HASH_SIZE	0
 #endif
@@ -1852,6 +1845,11 @@ extern int inode_permission(struct inode *, int);
 extern int generic_permission(struct inode *, int,
 		int (*check_acl)(struct inode *, int));
 
+static inline bool execute_ok(struct inode *inode)
+{
+	return (inode->i_mode & S_IXUGO) || S_ISDIR(inode->i_mode);
+}
+
 extern int get_write_access(struct inode *);
 extern int deny_write_access(struct file *);
 static inline void put_write_access(struct inode * inode)
@@ -1887,7 +1885,9 @@ extern loff_t default_llseek(struct file *file, loff_t offset, int origin);
 
 extern loff_t vfs_llseek(struct file *file, loff_t offset, int origin);
 
+extern struct inode * inode_init_always(struct super_block *, struct inode *);
 extern void inode_init_once(struct inode *);
+extern void inode_add_to_lists(struct super_block *, struct inode *);
 extern void iput(struct inode *);
 extern struct inode * igrab(struct inode *);
 extern ino_t iunique(struct super_block *, ino_t);
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 4e625e0094c8..d9051d717d27 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -47,11 +47,7 @@
 struct gianfar_platform_data {
 	/* device specific information */
 	u32	device_flags;
-	/* board specific information */
-	u32	board_flags;
-	char	bus_id[MII_BUS_ID_SIZE];
-	u32	phy_id;
-	u8	mac_addr[6];
+	char	bus_id[BUS_ID_SIZE];
 	phy_interface_t interface;
 };
 
@@ -60,17 +56,6 @@ struct gianfar_mdio_data {
 	int	irq[32];
 };
 
-/* Flags related to gianfar device features */
-#define FSL_GIANFAR_DEV_HAS_GIGABIT		0x00000001
-#define FSL_GIANFAR_DEV_HAS_COALESCE		0x00000002
-#define FSL_GIANFAR_DEV_HAS_RMON		0x00000004
-#define FSL_GIANFAR_DEV_HAS_MULTI_INTR		0x00000008
-#define FSL_GIANFAR_DEV_HAS_CSUM		0x00000010
-#define FSL_GIANFAR_DEV_HAS_VLAN		0x00000020
-#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH	0x00000040
-#define FSL_GIANFAR_DEV_HAS_PADDING		0x00000080
-#define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET	0x00000100
-
 /* Flags in gianfar_platform_data */
 #define FSL_GIANFAR_BRD_HAS_PHY_INTR	0x00000001 /* set or use a timer */
 #define FSL_GIANFAR_BRD_IS_REDUCED	0x00000002 /* Set if RGMII, RMII */
diff --git a/include/linux/fsnotify.h b/include/linux/fsnotify.h
index a89513188ce7..00fbd5b245c9 100644
--- a/include/linux/fsnotify.h
+++ b/include/linux/fsnotify.h
@@ -188,7 +188,7 @@ static inline void fsnotify_close(struct file *file)
 	struct dentry *dentry = file->f_path.dentry;
 	struct inode *inode = dentry->d_inode;
 	const char *name = dentry->d_name.name;
-	mode_t mode = file->f_mode;
+	fmode_t mode = file->f_mode;
 	u32 mask = (mode & FMODE_WRITE) ? IN_CLOSE_WRITE : IN_CLOSE_NOWRITE;
 
 	if (S_ISDIR(inode->i_mode))
diff --git a/include/linux/ftrace.h b/include/linux/ftrace.h
index bb384068272e..677432b9cb7e 100644
--- a/include/linux/ftrace.h
+++ b/include/linux/ftrace.h
@@ -1,10 +1,17 @@
 #ifndef _LINUX_FTRACE_H
 #define _LINUX_FTRACE_H
 
-#ifdef CONFIG_FTRACE
-
 #include <linux/linkage.h>
 #include <linux/fs.h>
+#include <linux/ktime.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/kallsyms.h>
+#include <linux/bitops.h>
+#include <linux/sched.h>
+
+#ifdef CONFIG_FUNCTION_TRACER
 
 extern int ftrace_enabled;
 extern int
@@ -19,6 +26,45 @@ struct ftrace_ops {
 	struct ftrace_ops *next;
 };
 
+extern int function_trace_stop;
+
+/*
+ * Type of the current tracing.
+ */
+enum ftrace_tracing_type_t {
+	FTRACE_TYPE_ENTER = 0, /* Hook the call of the function */
+	FTRACE_TYPE_RETURN,	/* Hook the return of the function */
+};
+
+/* Current tracing type, default is FTRACE_TYPE_ENTER */
+extern enum ftrace_tracing_type_t ftrace_tracing_type;
+
+/**
+ * ftrace_stop - stop function tracer.
+ *
+ * A quick way to stop the function tracer. Note this an on off switch,
+ * it is not something that is recursive like preempt_disable.
+ * This does not disable the calling of mcount, it only stops the
+ * calling of functions from mcount.
+ */
+static inline void ftrace_stop(void)
+{
+	function_trace_stop = 1;
+}
+
+/**
+ * ftrace_start - start the function tracer.
+ *
+ * This function is the inverse of ftrace_stop. This does not enable
+ * the function tracing if the function tracer is disabled. This only
+ * sets the function tracer flag to continue calling the functions
+ * from mcount.
+ */
+static inline void ftrace_start(void)
+{
+	function_trace_stop = 0;
+}
+
 /*
  * The ftrace_ops must be a static and should also
  * be read_mostly.  These functions do modify read_mostly variables
@@ -32,15 +78,26 @@ void clear_ftrace_function(void);
 
 extern void ftrace_stub(unsigned long a0, unsigned long a1);
 
-#else /* !CONFIG_FTRACE */
+#else /* !CONFIG_FUNCTION_TRACER */
 # define register_ftrace_function(ops) do { } while (0)
 # define unregister_ftrace_function(ops) do { } while (0)
 # define clear_ftrace_function(ops) do { } while (0)
-#endif /* CONFIG_FTRACE */
+static inline void ftrace_kill(void) { }
+static inline void ftrace_stop(void) { }
+static inline void ftrace_start(void) { }
+#endif /* CONFIG_FUNCTION_TRACER */
+
+#ifdef CONFIG_STACK_TRACER
+extern int stack_tracer_enabled;
+int
+stack_trace_sysctl(struct ctl_table *table, int write,
+		   struct file *file, void __user *buffer, size_t *lenp,
+		   loff_t *ppos);
+#endif
 
 #ifdef CONFIG_DYNAMIC_FTRACE
-# define FTRACE_HASHBITS	10
-# define FTRACE_HASHSIZE	(1<<FTRACE_HASHBITS)
+/* asm/ftrace.h must be defined for archs supporting dynamic ftrace */
+#include <asm/ftrace.h>
 
 enum {
 	FTRACE_FL_FREE		= (1 << 0),
@@ -53,9 +110,10 @@ enum {
 };
 
 struct dyn_ftrace {
-	struct hlist_node node;
-	unsigned long	  ip; /* address of mcount call-site */
-	unsigned long	  flags;
+	struct list_head	list;
+	unsigned long		ip; /* address of mcount call-site */
+	unsigned long		flags;
+	struct dyn_arch_ftrace	arch;
 };
 
 int ftrace_force_update(void);
@@ -63,47 +121,103 @@ void ftrace_set_filter(unsigned char *buf, int len, int reset);
 
 /* defined in arch */
 extern int ftrace_ip_converted(unsigned long ip);
-extern unsigned char *ftrace_nop_replace(void);
-extern unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr);
 extern int ftrace_dyn_arch_init(void *data);
-extern int ftrace_mcount_set(unsigned long *data);
-extern int ftrace_modify_code(unsigned long ip, unsigned char *old_code,
-			      unsigned char *new_code);
 extern int ftrace_update_ftrace_func(ftrace_func_t func);
 extern void ftrace_caller(void);
 extern void ftrace_call(void);
 extern void mcount_call(void);
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+extern void ftrace_graph_caller(void);
+extern int ftrace_enable_ftrace_graph_caller(void);
+extern int ftrace_disable_ftrace_graph_caller(void);
+#else
+static inline int ftrace_enable_ftrace_graph_caller(void) { return 0; }
+static inline int ftrace_disable_ftrace_graph_caller(void) { return 0; }
+#endif
+
+/**
+ * ftrace_make_nop - convert code into top
+ * @mod: module structure if called by module load initialization
+ * @rec: the mcount call site record
+ * @addr: the address that the call site should be calling
+ *
+ * This is a very sensitive operation and great care needs
+ * to be taken by the arch.  The operation should carefully
+ * read the location, check to see if what is read is indeed
+ * what we expect it to be, and then on success of the compare,
+ * it should write to the location.
+ *
+ * The code segment at @rec->ip should be a caller to @addr
+ *
+ * Return must be:
+ *  0 on success
+ *  -EFAULT on error reading the location
+ *  -EINVAL on a failed compare of the contents
+ *  -EPERM  on error writing to the location
+ * Any other value will be considered a failure.
+ */
+extern int ftrace_make_nop(struct module *mod,
+			   struct dyn_ftrace *rec, unsigned long addr);
+
+/**
+ * ftrace_make_call - convert a nop call site into a call to addr
+ * @rec: the mcount call site record
+ * @addr: the address that the call site should call
+ *
+ * This is a very sensitive operation and great care needs
+ * to be taken by the arch.  The operation should carefully
+ * read the location, check to see if what is read is indeed
+ * what we expect it to be, and then on success of the compare,
+ * it should write to the location.
+ *
+ * The code segment at @rec->ip should be a nop
+ *
+ * Return must be:
+ *  0 on success
+ *  -EFAULT on error reading the location
+ *  -EINVAL on a failed compare of the contents
+ *  -EPERM  on error writing to the location
+ * Any other value will be considered a failure.
+ */
+extern int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr);
+
+
+/* May be defined in arch */
+extern int ftrace_arch_read_dyn_info(char *buf, int size);
 
 extern int skip_trace(unsigned long ip);
 
-void ftrace_disable_daemon(void);
-void ftrace_enable_daemon(void);
+extern void ftrace_release(void *start, unsigned long size);
 
+extern void ftrace_disable_daemon(void);
+extern void ftrace_enable_daemon(void);
 #else
 # define skip_trace(ip)				({ 0; })
 # define ftrace_force_update()			({ 0; })
 # define ftrace_set_filter(buf, len, reset)	do { } while (0)
 # define ftrace_disable_daemon()		do { } while (0)
 # define ftrace_enable_daemon()			do { } while (0)
+static inline void ftrace_release(void *start, unsigned long size) { }
 #endif /* CONFIG_DYNAMIC_FTRACE */
 
 /* totally disable ftrace - can not re-enable after this */
 void ftrace_kill(void);
-void ftrace_kill_atomic(void);
 
 static inline void tracer_disable(void)
 {
-#ifdef CONFIG_FTRACE
+#ifdef CONFIG_FUNCTION_TRACER
 	ftrace_enabled = 0;
 #endif
 }
 
-/* Ftrace disable/restore without lock. Some synchronization mechanism
+/*
+ * Ftrace disable/restore without lock. Some synchronization mechanism
  * must be used to prevent ftrace_enabled to be changed between
- * disable/restore. */
+ * disable/restore.
+ */
 static inline int __ftrace_enabled_save(void)
 {
-#ifdef CONFIG_FTRACE
+#ifdef CONFIG_FUNCTION_TRACER
 	int saved_ftrace_enabled = ftrace_enabled;
 	ftrace_enabled = 0;
 	return saved_ftrace_enabled;
@@ -114,7 +228,7 @@ static inline int __ftrace_enabled_save(void)
 
 static inline void __ftrace_enabled_restore(int enabled)
 {
-#ifdef CONFIG_FTRACE
+#ifdef CONFIG_FUNCTION_TRACER
 	ftrace_enabled = enabled;
 #endif
 }
@@ -155,11 +269,227 @@ static inline void __ftrace_enabled_restore(int enabled)
 #endif
 
 #ifdef CONFIG_TRACING
+extern int ftrace_dump_on_oops;
+
+extern void tracing_start(void);
+extern void tracing_stop(void);
+extern void ftrace_off_permanent(void);
+
 extern void
 ftrace_special(unsigned long arg1, unsigned long arg2, unsigned long arg3);
+
+/**
+ * ftrace_printk - printf formatting in the ftrace buffer
+ * @fmt: the printf format for printing
+ *
+ * Note: __ftrace_printk is an internal function for ftrace_printk and
+ *       the @ip is passed in via the ftrace_printk macro.
+ *
+ * This function allows a kernel developer to debug fast path sections
+ * that printk is not appropriate for. By scattering in various
+ * printk like tracing in the code, a developer can quickly see
+ * where problems are occurring.
+ *
+ * This is intended as a debugging tool for the developer only.
+ * Please refrain from leaving ftrace_printks scattered around in
+ * your code.
+ */
+# define ftrace_printk(fmt...) __ftrace_printk(_THIS_IP_, fmt)
+extern int
+__ftrace_printk(unsigned long ip, const char *fmt, ...)
+	__attribute__ ((format (printf, 2, 3)));
+extern void ftrace_dump(void);
 #else
 static inline void
 ftrace_special(unsigned long arg1, unsigned long arg2, unsigned long arg3) { }
+static inline int
+ftrace_printk(const char *fmt, ...) __attribute__ ((format (printf, 1, 2)));
+
+static inline void tracing_start(void) { }
+static inline void tracing_stop(void) { }
+static inline void ftrace_off_permanent(void) { }
+static inline int
+ftrace_printk(const char *fmt, ...)
+{
+	return 0;
+}
+static inline void ftrace_dump(void) { }
+#endif
+
+#ifdef CONFIG_FTRACE_MCOUNT_RECORD
+extern void ftrace_init(void);
+extern void ftrace_init_module(struct module *mod,
+			       unsigned long *start, unsigned long *end);
+#else
+static inline void ftrace_init(void) { }
+static inline void
+ftrace_init_module(struct module *mod,
+		   unsigned long *start, unsigned long *end) { }
+#endif
+
+enum {
+	POWER_NONE = 0,
+	POWER_CSTATE = 1,
+	POWER_PSTATE = 2,
+};
+
+struct power_trace {
+#ifdef CONFIG_POWER_TRACER
+	ktime_t			stamp;
+	ktime_t			end;
+	int			type;
+	int			state;
+#endif
+};
+
+#ifdef CONFIG_POWER_TRACER
+extern void trace_power_start(struct power_trace *it, unsigned int type,
+					unsigned int state);
+extern void trace_power_mark(struct power_trace *it, unsigned int type,
+					unsigned int state);
+extern void trace_power_end(struct power_trace *it);
+#else
+static inline void trace_power_start(struct power_trace *it, unsigned int type,
+					unsigned int state) { }
+static inline void trace_power_mark(struct power_trace *it, unsigned int type,
+					unsigned int state) { }
+static inline void trace_power_end(struct power_trace *it) { }
+#endif
+
+
+/*
+ * Structure that defines an entry function trace.
+ */
+struct ftrace_graph_ent {
+	unsigned long func; /* Current function */
+	int depth;
+};
+
+/*
+ * Structure that defines a return function trace.
+ */
+struct ftrace_graph_ret {
+	unsigned long func; /* Current function */
+	unsigned long long calltime;
+	unsigned long long rettime;
+	/* Number of functions that overran the depth limit for current task */
+	unsigned long overrun;
+	int depth;
+};
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+
+/*
+ * Sometimes we don't want to trace a function with the function
+ * graph tracer but we want them to keep traced by the usual function
+ * tracer if the function graph tracer is not configured.
+ */
+#define __notrace_funcgraph		notrace
+
+/*
+ * We want to which function is an entrypoint of a hardirq.
+ * That will help us to put a signal on output.
+ */
+#define __irq_entry		 __attribute__((__section__(".irqentry.text")))
+
+/* Limits of hardirq entrypoints */
+extern char __irqentry_text_start[];
+extern char __irqentry_text_end[];
+
+#define FTRACE_RETFUNC_DEPTH 50
+#define FTRACE_RETSTACK_ALLOC_SIZE 32
+/* Type of the callback handlers for tracing function graph*/
+typedef void (*trace_func_graph_ret_t)(struct ftrace_graph_ret *); /* return */
+typedef int (*trace_func_graph_ent_t)(struct ftrace_graph_ent *); /* entry */
+
+extern int register_ftrace_graph(trace_func_graph_ret_t retfunc,
+				trace_func_graph_ent_t entryfunc);
+
+extern void ftrace_graph_stop(void);
+
+/* The current handlers in use */
+extern trace_func_graph_ret_t ftrace_graph_return;
+extern trace_func_graph_ent_t ftrace_graph_entry;
+
+extern void unregister_ftrace_graph(void);
+
+extern void ftrace_graph_init_task(struct task_struct *t);
+extern void ftrace_graph_exit_task(struct task_struct *t);
+
+static inline int task_curr_ret_stack(struct task_struct *t)
+{
+	return t->curr_ret_stack;
+}
+
+static inline void pause_graph_tracing(void)
+{
+	atomic_inc(&current->tracing_graph_pause);
+}
+
+static inline void unpause_graph_tracing(void)
+{
+	atomic_dec(&current->tracing_graph_pause);
+}
+#else
+
+#define __notrace_funcgraph
+#define __irq_entry
+
+static inline void ftrace_graph_init_task(struct task_struct *t) { }
+static inline void ftrace_graph_exit_task(struct task_struct *t) { }
+
+static inline int task_curr_ret_stack(struct task_struct *tsk)
+{
+	return -1;
+}
+
+static inline void pause_graph_tracing(void) { }
+static inline void unpause_graph_tracing(void) { }
 #endif
 
+#ifdef CONFIG_TRACING
+#include <linux/sched.h>
+
+/* flags for current->trace */
+enum {
+	TSK_TRACE_FL_TRACE_BIT	= 0,
+	TSK_TRACE_FL_GRAPH_BIT	= 1,
+};
+enum {
+	TSK_TRACE_FL_TRACE	= 1 << TSK_TRACE_FL_TRACE_BIT,
+	TSK_TRACE_FL_GRAPH	= 1 << TSK_TRACE_FL_GRAPH_BIT,
+};
+
+static inline void set_tsk_trace_trace(struct task_struct *tsk)
+{
+	set_bit(TSK_TRACE_FL_TRACE_BIT, &tsk->trace);
+}
+
+static inline void clear_tsk_trace_trace(struct task_struct *tsk)
+{
+	clear_bit(TSK_TRACE_FL_TRACE_BIT, &tsk->trace);
+}
+
+static inline int test_tsk_trace_trace(struct task_struct *tsk)
+{
+	return tsk->trace & TSK_TRACE_FL_TRACE;
+}
+
+static inline void set_tsk_trace_graph(struct task_struct *tsk)
+{
+	set_bit(TSK_TRACE_FL_GRAPH_BIT, &tsk->trace);
+}
+
+static inline void clear_tsk_trace_graph(struct task_struct *tsk)
+{
+	clear_bit(TSK_TRACE_FL_GRAPH_BIT, &tsk->trace);
+}
+
+static inline int test_tsk_trace_graph(struct task_struct *tsk)
+{
+	return tsk->trace & TSK_TRACE_FL_GRAPH;
+}
+
+#endif /* CONFIG_TRACING */
+
 #endif /* _LINUX_FTRACE_H */
diff --git a/include/linux/ftrace_irq.h b/include/linux/ftrace_irq.h
new file mode 100644
index 000000000000..366a054d0b05
--- /dev/null
+++ b/include/linux/ftrace_irq.h
@@ -0,0 +1,13 @@
+#ifndef _LINUX_FTRACE_IRQ_H
+#define _LINUX_FTRACE_IRQ_H
+
+
+#if defined(CONFIG_DYNAMIC_FTRACE) || defined(CONFIG_FUNCTION_GRAPH_TRACER)
+extern void ftrace_nmi_enter(void);
+extern void ftrace_nmi_exit(void);
+#else
+static inline void ftrace_nmi_enter(void) { }
+static inline void ftrace_nmi_exit(void) { }
+#endif
+
+#endif /* _LINUX_FTRACE_IRQ_H */
diff --git a/include/linux/fuse.h b/include/linux/fuse.h
index 265635dc9908..350fe9767bbc 100644
--- a/include/linux/fuse.h
+++ b/include/linux/fuse.h
@@ -17,8 +17,14 @@
  *  - add lock_owner field to fuse_setattr_in, fuse_read_in and fuse_write_in
  *  - add blksize field to fuse_attr
  *  - add file flags field to fuse_read_in and fuse_write_in
+ *
+ * 7.10
+ *  - add nonseekable open flag
  */
 
+#ifndef _LINUX_FUSE_H
+#define _LINUX_FUSE_H
+
 #include <asm/types.h>
 #include <linux/major.h>
 
@@ -26,7 +32,7 @@
 #define FUSE_KERNEL_VERSION 7
 
 /** Minor version number of this interface */
-#define FUSE_KERNEL_MINOR_VERSION 9
+#define FUSE_KERNEL_MINOR_VERSION 10
 
 /** The node ID of the root inode */
 #define FUSE_ROOT_ID 1
@@ -98,9 +104,11 @@ struct fuse_file_lock {
  *
  * FOPEN_DIRECT_IO: bypass page cache for this open file
  * FOPEN_KEEP_CACHE: don't invalidate the data cache on open
+ * FOPEN_NONSEEKABLE: the file is not seekable
  */
 #define FOPEN_DIRECT_IO		(1 << 0)
 #define FOPEN_KEEP_CACHE	(1 << 1)
+#define FOPEN_NONSEEKABLE	(1 << 2)
 
 /**
  * INIT request/reply flags
@@ -409,3 +417,5 @@ struct fuse_dirent {
 #define FUSE_DIRENT_ALIGN(x) (((x) + sizeof(__u64) - 1) & ~(sizeof(__u64) - 1))
 #define FUSE_DIRENT_SIZE(d) \
 	FUSE_DIRENT_ALIGN(FUSE_NAME_OFFSET + (d)->namelen)
+
+#endif /* _LINUX_FUSE_H */
diff --git a/include/linux/futex.h b/include/linux/futex.h
index 586ab56a3ec3..3bf5bb5a34f9 100644
--- a/include/linux/futex.h
+++ b/include/linux/futex.h
@@ -25,7 +25,8 @@ union ktime;
 #define FUTEX_WAKE_BITSET	10
 
 #define FUTEX_PRIVATE_FLAG	128
-#define FUTEX_CMD_MASK		~FUTEX_PRIVATE_FLAG
+#define FUTEX_CLOCK_REALTIME	256
+#define FUTEX_CMD_MASK		~(FUTEX_PRIVATE_FLAG | FUTEX_CLOCK_REALTIME)
 
 #define FUTEX_WAIT_PRIVATE	(FUTEX_WAIT | FUTEX_PRIVATE_FLAG)
 #define FUTEX_WAKE_PRIVATE	(FUTEX_WAKE | FUTEX_PRIVATE_FLAG)
@@ -164,6 +165,8 @@ union futex_key {
 	} both;
 };
 
+#define FUTEX_KEY_INIT (union futex_key) { .both = { .ptr = NULL } }
+
 #ifdef CONFIG_FUTEX
 extern void exit_robust_list(struct task_struct *curr);
 extern void exit_pi_state_list(struct task_struct *curr);
diff --git a/include/linux/gameport.h b/include/linux/gameport.h
index f64e29c0ef3f..0cd825f7363a 100644
--- a/include/linux/gameport.h
+++ b/include/linux/gameport.h
@@ -146,10 +146,11 @@ static inline void gameport_unpin_driver(struct gameport *gameport)
 	mutex_unlock(&gameport->drv_mutex);
 }
 
-void __gameport_register_driver(struct gameport_driver *drv, struct module *owner);
-static inline void gameport_register_driver(struct gameport_driver *drv)
+int __gameport_register_driver(struct gameport_driver *drv,
+				struct module *owner, const char *mod_name);
+static inline int __must_check gameport_register_driver(struct gameport_driver *drv)
 {
-	__gameport_register_driver(drv, THIS_MODULE);
+	return __gameport_register_driver(drv, THIS_MODULE, KBUILD_MODNAME);
 }
 
 void gameport_unregister_driver(struct gameport_driver *drv);
diff --git a/include/linux/genhd.h b/include/linux/genhd.h
index 206cdf96c3a7..16948eaecae3 100644
--- a/include/linux/genhd.h
+++ b/include/linux/genhd.h
@@ -25,9 +25,6 @@ extern struct device_type part_type;
 extern struct kobject *block_depr;
 extern struct class block_class;
 
-extern const struct seq_operations partitions_op;
-extern const struct seq_operations diskstats_op;
-
 enum {
 /* These three have identical behaviour; use the second one if DOS FDISK gets
    confused about extended/logical partitions starting past cylinder 1023. */
@@ -129,6 +126,7 @@ struct blk_scsi_cmd_filter {
 struct disk_part_tbl {
 	struct rcu_head rcu_head;
 	int len;
+	struct hd_struct *last_lookup;
 	struct hd_struct *part[];
 };
 
@@ -525,7 +523,9 @@ extern char *disk_name (struct gendisk *hd, int partno, char *buf);
 
 extern int disk_expand_part_tbl(struct gendisk *disk, int target);
 extern int rescan_partitions(struct gendisk *disk, struct block_device *bdev);
-extern int __must_check add_partition(struct gendisk *, int, sector_t, sector_t, int);
+extern struct hd_struct * __must_check add_partition(struct gendisk *disk,
+						     int partno, sector_t start,
+						     sector_t len, int flags);
 extern void delete_partition(struct gendisk *, int);
 extern void printk_all_partitions(void);
 
diff --git a/include/linux/gpio.h b/include/linux/gpio.h
index 730a20b83576..e10c49a5b96e 100644
--- a/include/linux/gpio.h
+++ b/include/linux/gpio.h
@@ -8,6 +8,7 @@
 
 #else
 
+#include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/errno.h>
 
@@ -32,6 +33,8 @@ static inline int gpio_request(unsigned gpio, const char *label)
 
 static inline void gpio_free(unsigned gpio)
 {
+	might_sleep();
+
 	/* GPIO can never have been requested */
 	WARN_ON(1);
 }
diff --git a/include/linux/hardirq.h b/include/linux/hardirq.h
index 181006cc94a0..f83288347dda 100644
--- a/include/linux/hardirq.h
+++ b/include/linux/hardirq.h
@@ -4,6 +4,7 @@
 #include <linux/preempt.h>
 #include <linux/smp_lock.h>
 #include <linux/lockdep.h>
+#include <linux/ftrace_irq.h>
 #include <asm/hardirq.h>
 #include <asm/system.h>
 
@@ -118,13 +119,17 @@ static inline void account_system_vtime(struct task_struct *tsk)
 }
 #endif
 
-#if defined(CONFIG_PREEMPT_RCU) && defined(CONFIG_NO_HZ)
+#if defined(CONFIG_NO_HZ) && !defined(CONFIG_CLASSIC_RCU)
 extern void rcu_irq_enter(void);
 extern void rcu_irq_exit(void);
+extern void rcu_nmi_enter(void);
+extern void rcu_nmi_exit(void);
 #else
 # define rcu_irq_enter() do { } while (0)
 # define rcu_irq_exit() do { } while (0)
-#endif /* CONFIG_PREEMPT_RCU */
+# define rcu_nmi_enter() do { } while (0)
+# define rcu_nmi_exit() do { } while (0)
+#endif /* #if defined(CONFIG_NO_HZ) && !defined(CONFIG_CLASSIC_RCU) */
 
 /*
  * It is safe to do non-atomic ops on ->hardirq_context,
@@ -134,7 +139,6 @@ extern void rcu_irq_exit(void);
  */
 #define __irq_enter()					\
 	do {						\
-		rcu_irq_enter();			\
 		account_system_vtime(current);		\
 		add_preempt_count(HARDIRQ_OFFSET);	\
 		trace_hardirq_enter();			\
@@ -153,7 +157,6 @@ extern void irq_enter(void);
 		trace_hardirq_exit();			\
 		account_system_vtime(current);		\
 		sub_preempt_count(HARDIRQ_OFFSET);	\
-		rcu_irq_exit();				\
 	} while (0)
 
 /*
@@ -161,7 +164,20 @@ extern void irq_enter(void);
  */
 extern void irq_exit(void);
 
-#define nmi_enter()		do { lockdep_off(); __irq_enter(); } while (0)
-#define nmi_exit()		do { __irq_exit(); lockdep_on(); } while (0)
+#define nmi_enter()				\
+	do {					\
+		ftrace_nmi_enter();		\
+		lockdep_off();			\
+		rcu_nmi_enter();		\
+		__irq_enter();			\
+	} while (0)
+
+#define nmi_exit()				\
+	do {					\
+		__irq_exit();			\
+		rcu_nmi_exit();			\
+		lockdep_on();			\
+		ftrace_nmi_exit();		\
+	} while (0)
 
 #endif /* LINUX_HARDIRQ_H */
diff --git a/include/linux/hdlc.h b/include/linux/hdlc.h
index c59769693bee..fd47a151665e 100644
--- a/include/linux/hdlc.h
+++ b/include/linux/hdlc.h
@@ -43,7 +43,7 @@ struct hdlc_proto {
 };
 
 
-/* Pointed to by dev->priv */
+/* Pointed to by netdev_priv(dev) */
 typedef struct hdlc_device {
 	/* used by HDLC layer to take control over HDLC device from hw driver*/
 	int (*attach)(struct net_device *dev,
@@ -80,7 +80,7 @@ struct net_device *alloc_hdlcdev(void *priv);
 
 static inline struct hdlc_device* dev_to_hdlc(struct net_device *dev)
 {
-	return dev->priv;
+	return netdev_priv(dev);
 }
 
 static __inline__ void debug_frame(const struct sk_buff *skb)
diff --git a/include/linux/hid.h b/include/linux/hid.h
index f13bca2dd53b..e5780f8c934a 100644
--- a/include/linux/hid.h
+++ b/include/linux/hid.h
@@ -410,6 +410,7 @@ struct hid_output_fifo {
 #define HID_SUSPENDED		5
 #define HID_CLEAR_HALT		6
 #define HID_DISCONNECTED	7
+#define HID_STARTED		8
 
 struct hid_input {
 	struct list_head list;
@@ -417,6 +418,11 @@ struct hid_input {
 	struct input_dev *input;
 };
 
+enum hid_type {
+	HID_TYPE_OTHER = 0,
+	HID_TYPE_USBMOUSE
+};
+
 struct hid_driver;
 struct hid_ll_driver;
 
@@ -431,6 +437,7 @@ struct hid_device {							/* device report descriptor */
 	__u32 vendor;							/* Vendor ID */
 	__u32 product;							/* Product ID */
 	__u32 version;							/* HID version */
+	enum hid_type type;						/* device type (mouse, kbd, ...) */
 	unsigned country;						/* HID country */
 	struct hid_report_enum report_enum[HID_REPORT_TYPES];
 
diff --git a/include/linux/highmem.h b/include/linux/highmem.h
index 7dcbc82f3b7b..13875ce9112a 100644
--- a/include/linux/highmem.h
+++ b/include/linux/highmem.h
@@ -63,12 +63,14 @@ static inline void *kmap_atomic(struct page *page, enum km_type idx)
 #endif /* CONFIG_HIGHMEM */
 
 /* when CONFIG_HIGHMEM is not set these will be plain clear/copy_page */
+#ifndef clear_user_highpage
 static inline void clear_user_highpage(struct page *page, unsigned long vaddr)
 {
 	void *addr = kmap_atomic(page, KM_USER0);
 	clear_user_page(addr, vaddr, page);
 	kunmap_atomic(addr, KM_USER0);
 }
+#endif
 
 #ifndef __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
 /**
diff --git a/include/linux/hippidevice.h b/include/linux/hippidevice.h
index bab303dafd6e..f148e4908410 100644
--- a/include/linux/hippidevice.h
+++ b/include/linux/hippidevice.h
@@ -32,7 +32,9 @@ struct hippi_cb {
 };
 
 extern __be16 hippi_type_trans(struct sk_buff *skb, struct net_device *dev);
-
+extern int hippi_change_mtu(struct net_device *dev, int new_mtu);
+extern int hippi_mac_addr(struct net_device *dev, void *p);
+extern int hippi_neigh_setup_dev(struct net_device *dev, struct neigh_parms *p);
 extern struct net_device *alloc_hippi_dev(int sizeof_priv);
 #endif
 
diff --git a/include/linux/hrtimer.h b/include/linux/hrtimer.h
index 2f245fe63bda..bd37078c2d7d 100644
--- a/include/linux/hrtimer.h
+++ b/include/linux/hrtimer.h
@@ -20,6 +20,8 @@
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/wait.h>
+#include <linux/percpu.h>
+
 
 struct hrtimer_clock_base;
 struct hrtimer_cpu_base;
@@ -41,31 +43,6 @@ enum hrtimer_restart {
 };
 
 /*
- * hrtimer callback modes:
- *
- *	HRTIMER_CB_SOFTIRQ:		Callback must run in softirq context
- *	HRTIMER_CB_IRQSAFE:		Callback may run in hardirq context
- *	HRTIMER_CB_IRQSAFE_NO_RESTART:	Callback may run in hardirq context and
- *					does not restart the timer
- *	HRTIMER_CB_IRQSAFE_PERCPU:	Callback must run in hardirq context
- *					Special mode for tick emulation and
- *					scheduler timer. Such timers are per
- *					cpu and not allowed to be migrated on
- *					cpu unplug.
- *	HRTIMER_CB_IRQSAFE_UNLOCKED:	Callback should run in hardirq context
- *					with timer->base lock unlocked
- *					used for timers which call wakeup to
- *					avoid lock order problems with rq->lock
- */
-enum hrtimer_cb_mode {
-	HRTIMER_CB_SOFTIRQ,
-	HRTIMER_CB_IRQSAFE,
-	HRTIMER_CB_IRQSAFE_NO_RESTART,
-	HRTIMER_CB_IRQSAFE_PERCPU,
-	HRTIMER_CB_IRQSAFE_UNLOCKED,
-};
-
-/*
  * Values to track state of the timer
  *
  * Possible states:
@@ -73,7 +50,6 @@ enum hrtimer_cb_mode {
  * 0x00		inactive
  * 0x01		enqueued into rbtree
  * 0x02		callback function running
- * 0x04		callback pending (high resolution mode)
  *
  * Special cases:
  * 0x03		callback function running and enqueued
@@ -95,20 +71,22 @@ enum hrtimer_cb_mode {
 #define HRTIMER_STATE_INACTIVE	0x00
 #define HRTIMER_STATE_ENQUEUED	0x01
 #define HRTIMER_STATE_CALLBACK	0x02
-#define HRTIMER_STATE_PENDING	0x04
-#define HRTIMER_STATE_MIGRATE	0x08
+#define HRTIMER_STATE_MIGRATE	0x04
 
 /**
  * struct hrtimer - the basic hrtimer structure
  * @node:	red black tree node for time ordered insertion
- * @expires:	the absolute expiry time in the hrtimers internal
+ * @_expires:	the absolute expiry time in the hrtimers internal
  *		representation. The time is related to the clock on
- *		which the timer is based.
+ *		which the timer is based. Is setup by adding
+ *		slack to the _softexpires value. For non range timers
+ *		identical to _softexpires.
+ * @_softexpires: the absolute earliest expiry time of the hrtimer.
+ *		The time which was given as expiry time when the timer
+ *		was armed.
  * @function:	timer expiry callback function
  * @base:	pointer to the timer base (per cpu and per clock)
  * @state:	state information (See bit values above)
- * @cb_mode:	high resolution timer feature to select the callback execution
- *		 mode
  * @cb_entry:	list head to enqueue an expired timer into the callback list
  * @start_site:	timer statistics field to store the site where the timer
  *		was started
@@ -121,16 +99,16 @@ enum hrtimer_cb_mode {
  */
 struct hrtimer {
 	struct rb_node			node;
-	ktime_t				expires;
+	ktime_t				_expires;
+	ktime_t				_softexpires;
 	enum hrtimer_restart		(*function)(struct hrtimer *);
 	struct hrtimer_clock_base	*base;
 	unsigned long			state;
-	enum hrtimer_cb_mode		cb_mode;
 	struct list_head		cb_entry;
 #ifdef CONFIG_TIMER_STATS
+	int				start_pid;
 	void				*start_site;
 	char				start_comm[16];
-	int				start_pid;
 #endif
 };
 
@@ -155,10 +133,8 @@ struct hrtimer_sleeper {
  * @first:		pointer to the timer node which expires first
  * @resolution:		the resolution of the clock, in nanoseconds
  * @get_time:		function to retrieve the current time of the clock
- * @get_softirq_time:	function to retrieve the current time from the softirq
  * @softirq_time:	the time when running the hrtimer queue in the softirq
  * @offset:		offset of this clock to the monotonic base
- * @reprogram:		function to reprogram the timer event
  */
 struct hrtimer_clock_base {
 	struct hrtimer_cpu_base	*cpu_base;
@@ -167,13 +143,9 @@ struct hrtimer_clock_base {
 	struct rb_node		*first;
 	ktime_t			resolution;
 	ktime_t			(*get_time)(void);
-	ktime_t			(*get_softirq_time)(void);
 	ktime_t			softirq_time;
 #ifdef CONFIG_HIGH_RES_TIMERS
 	ktime_t			offset;
-	int			(*reprogram)(struct hrtimer *t,
-					     struct hrtimer_clock_base *b,
-					     ktime_t n);
 #endif
 };
 
@@ -191,15 +163,11 @@ struct hrtimer_clock_base {
  * @check_clocks:	Indictator, when set evaluate time source and clock
  *			event devices whether high resolution mode can be
  *			activated.
- * @cb_pending:		Expired timers are moved from the rbtree to this
- *			list in the timer interrupt. The list is processed
- *			in the softirq.
  * @nr_events:		Total number of timer interrupt events
  */
 struct hrtimer_cpu_base {
 	spinlock_t			lock;
 	struct hrtimer_clock_base	clock_base[HRTIMER_MAX_CLOCK_BASES];
-	struct list_head		cb_pending;
 #ifdef CONFIG_HIGH_RES_TIMERS
 	ktime_t				expires_next;
 	int				hres_active;
@@ -207,6 +175,71 @@ struct hrtimer_cpu_base {
 #endif
 };
 
+static inline void hrtimer_set_expires(struct hrtimer *timer, ktime_t time)
+{
+	timer->_expires = time;
+	timer->_softexpires = time;
+}
+
+static inline void hrtimer_set_expires_range(struct hrtimer *timer, ktime_t time, ktime_t delta)
+{
+	timer->_softexpires = time;
+	timer->_expires = ktime_add_safe(time, delta);
+}
+
+static inline void hrtimer_set_expires_range_ns(struct hrtimer *timer, ktime_t time, unsigned long delta)
+{
+	timer->_softexpires = time;
+	timer->_expires = ktime_add_safe(time, ns_to_ktime(delta));
+}
+
+static inline void hrtimer_set_expires_tv64(struct hrtimer *timer, s64 tv64)
+{
+	timer->_expires.tv64 = tv64;
+	timer->_softexpires.tv64 = tv64;
+}
+
+static inline void hrtimer_add_expires(struct hrtimer *timer, ktime_t time)
+{
+	timer->_expires = ktime_add_safe(timer->_expires, time);
+	timer->_softexpires = ktime_add_safe(timer->_softexpires, time);
+}
+
+static inline void hrtimer_add_expires_ns(struct hrtimer *timer, u64 ns)
+{
+	timer->_expires = ktime_add_ns(timer->_expires, ns);
+	timer->_softexpires = ktime_add_ns(timer->_softexpires, ns);
+}
+
+static inline ktime_t hrtimer_get_expires(const struct hrtimer *timer)
+{
+	return timer->_expires;
+}
+
+static inline ktime_t hrtimer_get_softexpires(const struct hrtimer *timer)
+{
+	return timer->_softexpires;
+}
+
+static inline s64 hrtimer_get_expires_tv64(const struct hrtimer *timer)
+{
+	return timer->_expires.tv64;
+}
+static inline s64 hrtimer_get_softexpires_tv64(const struct hrtimer *timer)
+{
+	return timer->_softexpires.tv64;
+}
+
+static inline s64 hrtimer_get_expires_ns(const struct hrtimer *timer)
+{
+	return ktime_to_ns(timer->_expires);
+}
+
+static inline ktime_t hrtimer_expires_remaining(const struct hrtimer *timer)
+{
+    return ktime_sub(timer->_expires, timer->base->get_time());
+}
+
 #ifdef CONFIG_HIGH_RES_TIMERS
 struct clock_event_device;
 
@@ -227,6 +260,8 @@ static inline int hrtimer_is_hres_active(struct hrtimer *timer)
 	return timer->base->cpu_base->hres_active;
 }
 
+extern void hrtimer_peek_ahead_timers(void);
+
 /*
  * The resolution of the clocks. The resolution value is returned in
  * the clock_getres() system call to give application programmers an
@@ -249,6 +284,7 @@ static inline int hrtimer_is_hres_active(struct hrtimer *timer)
  * is expired in the next softirq when the clock was advanced.
  */
 static inline void clock_was_set(void) { }
+static inline void hrtimer_peek_ahead_timers(void) { }
 
 static inline void hres_timers_resume(void) { }
 
@@ -270,6 +306,10 @@ static inline int hrtimer_is_hres_active(struct hrtimer *timer)
 extern ktime_t ktime_get(void);
 extern ktime_t ktime_get_real(void);
 
+
+DECLARE_PER_CPU(struct tick_device, tick_cpu_device);
+
+
 /* Exported timer functions: */
 
 /* Initialize timers: */
@@ -294,12 +334,25 @@ static inline void destroy_hrtimer_on_stack(struct hrtimer *timer) { }
 /* Basic timer operations: */
 extern int hrtimer_start(struct hrtimer *timer, ktime_t tim,
 			 const enum hrtimer_mode mode);
+extern int hrtimer_start_range_ns(struct hrtimer *timer, ktime_t tim,
+			unsigned long range_ns, const enum hrtimer_mode mode);
 extern int hrtimer_cancel(struct hrtimer *timer);
 extern int hrtimer_try_to_cancel(struct hrtimer *timer);
 
+static inline int hrtimer_start_expires(struct hrtimer *timer,
+						enum hrtimer_mode mode)
+{
+	unsigned long delta;
+	ktime_t soft, hard;
+	soft = hrtimer_get_softexpires(timer);
+	hard = hrtimer_get_expires(timer);
+	delta = ktime_to_ns(ktime_sub(hard, soft));
+	return hrtimer_start_range_ns(timer, soft, delta, mode);
+}
+
 static inline int hrtimer_restart(struct hrtimer *timer)
 {
-	return hrtimer_start(timer, timer->expires, HRTIMER_MODE_ABS);
+	return hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
 }
 
 /* Query timers: */
@@ -322,8 +375,7 @@ static inline int hrtimer_active(const struct hrtimer *timer)
  */
 static inline int hrtimer_is_queued(struct hrtimer *timer)
 {
-	return timer->state &
-		(HRTIMER_STATE_ENQUEUED | HRTIMER_STATE_PENDING);
+	return timer->state & HRTIMER_STATE_ENQUEUED;
 }
 
 /*
@@ -356,6 +408,10 @@ extern long hrtimer_nanosleep_restart(struct restart_block *restart_block);
 extern void hrtimer_init_sleeper(struct hrtimer_sleeper *sl,
 				 struct task_struct *tsk);
 
+extern int schedule_hrtimeout_range(ktime_t *expires, unsigned long delta,
+						const enum hrtimer_mode mode);
+extern int schedule_hrtimeout(ktime_t *expires, const enum hrtimer_mode mode);
+
 /* Soft interrupt function to run the hrtimer queues: */
 extern void hrtimer_run_queues(void);
 extern void hrtimer_run_pending(void);
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index 32e0ef0f6e1f..e1c8afc002c0 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -27,7 +27,7 @@ void unmap_hugepage_range(struct vm_area_struct *,
 void __unmap_hugepage_range(struct vm_area_struct *,
 			unsigned long, unsigned long, struct page *);
 int hugetlb_prefault(struct address_space *, struct vm_area_struct *);
-int hugetlb_report_meminfo(char *);
+void hugetlb_report_meminfo(struct seq_file *);
 int hugetlb_report_node_meminfo(int, char *);
 unsigned long hugetlb_total_pages(void);
 int hugetlb_fault(struct mm_struct *mm, struct vm_area_struct *vma,
@@ -79,7 +79,9 @@ static inline unsigned long hugetlb_total_pages(void)
 #define copy_hugetlb_page_range(src, dst, vma)	({ BUG(); 0; })
 #define hugetlb_prefault(mapping, vma)		({ BUG(); 0; })
 #define unmap_hugepage_range(vma, start, end, page)	BUG()
-#define hugetlb_report_meminfo(buf)		0
+static inline void hugetlb_report_meminfo(struct seq_file *m)
+{
+}
 #define hugetlb_report_node_meminfo(n, buf)	0
 #define follow_huge_pmd(mm, addr, pmd, write)	NULL
 #define follow_huge_pud(mm, addr, pud, write)	NULL
diff --git a/include/linux/i2c-algo-pcf.h b/include/linux/i2c-algo-pcf.h
index 0177d280f733..0f91a957a690 100644
--- a/include/linux/i2c-algo-pcf.h
+++ b/include/linux/i2c-algo-pcf.h
@@ -31,7 +31,10 @@ struct i2c_algo_pcf_data {
 	int  (*getpcf) (void *data, int ctl);
 	int  (*getown) (void *data);
 	int  (*getclock) (void *data);
-	void (*waitforpin) (void);
+	void (*waitforpin) (void *data);
+
+	void (*xfer_begin) (void *data);
+	void (*xfer_end) (void *data);
 
 	/* Multi-master lost arbitration back-off delay (msecs)
 	 * This should be set by the bus adapter or knowledgable client
diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h
index 493435bcdbe5..01d67ba9e985 100644
--- a/include/linux/i2c-id.h
+++ b/include/linux/i2c-id.h
@@ -60,7 +60,7 @@
 #define I2C_DRIVERID_WM8775	69	/* wm8775 audio processor	*/
 #define I2C_DRIVERID_CS53L32A	70	/* cs53l32a audio processor	*/
 #define I2C_DRIVERID_CX25840	71	/* cx2584x video encoder	*/
-#define I2C_DRIVERID_SAA7127	72	/* saa7124 video encoder	*/
+#define I2C_DRIVERID_SAA7127	72	/* saa7127 video encoder	*/
 #define I2C_DRIVERID_SAA711X	73	/* saa711x video encoders	*/
 #define I2C_DRIVERID_AKITAIOEXP	74	/* IO Expander on Sharp SL-C1000 */
 #define I2C_DRIVERID_INFRARED	75	/* I2C InfraRed on Video boards */
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 06115128047f..33a5992d4936 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -53,45 +53,44 @@ struct i2c_board_info;
  * transmit one message at a time, a more complex version can be used to
  * transmit an arbitrary number of messages without interruption.
  */
-extern int i2c_master_send(struct i2c_client *,const char* ,int);
-extern int i2c_master_recv(struct i2c_client *,char* ,int);
+extern int i2c_master_send(struct i2c_client *client, const char *buf,
+			   int count);
+extern int i2c_master_recv(struct i2c_client *client, char *buf, int count);
 
 /* Transfer num messages.
  */
-extern int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num);
-
+extern int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
+			int num);
 
 /* This is the very generalized SMBus access routine. You probably do not
    want to use this, though; one of the functions below may be much easier,
    and probably just as fast.
    Note that we use i2c_adapter here, because you do not need a specific
    smbus adapter to call this function. */
-extern s32 i2c_smbus_xfer (struct i2c_adapter * adapter, u16 addr,
-                           unsigned short flags,
-                           char read_write, u8 command, int size,
-                           union i2c_smbus_data * data);
+extern s32 i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
+			  unsigned short flags, char read_write, u8 command,
+			  int size, union i2c_smbus_data *data);
 
 /* Now follow the 'nice' access routines. These also document the calling
    conventions of i2c_smbus_xfer. */
 
-extern s32 i2c_smbus_read_byte(struct i2c_client * client);
-extern s32 i2c_smbus_write_byte(struct i2c_client * client, u8 value);
-extern s32 i2c_smbus_read_byte_data(struct i2c_client * client, u8 command);
-extern s32 i2c_smbus_write_byte_data(struct i2c_client * client,
-                                     u8 command, u8 value);
-extern s32 i2c_smbus_read_word_data(struct i2c_client * client, u8 command);
-extern s32 i2c_smbus_write_word_data(struct i2c_client * client,
-                                     u8 command, u16 value);
+extern s32 i2c_smbus_read_byte(struct i2c_client *client);
+extern s32 i2c_smbus_write_byte(struct i2c_client *client, u8 value);
+extern s32 i2c_smbus_read_byte_data(struct i2c_client *client, u8 command);
+extern s32 i2c_smbus_write_byte_data(struct i2c_client *client,
+				     u8 command, u8 value);
+extern s32 i2c_smbus_read_word_data(struct i2c_client *client, u8 command);
+extern s32 i2c_smbus_write_word_data(struct i2c_client *client,
+				     u8 command, u16 value);
 /* Returns the number of read bytes */
 extern s32 i2c_smbus_read_block_data(struct i2c_client *client,
 				     u8 command, u8 *values);
-extern s32 i2c_smbus_write_block_data(struct i2c_client * client,
-				      u8 command, u8 length,
-				      const u8 *values);
+extern s32 i2c_smbus_write_block_data(struct i2c_client *client,
+				      u8 command, u8 length, const u8 *values);
 /* Returns the number of read bytes */
-extern s32 i2c_smbus_read_i2c_block_data(struct i2c_client * client,
+extern s32 i2c_smbus_read_i2c_block_data(struct i2c_client *client,
 					 u8 command, u8 length, u8 *values);
-extern s32 i2c_smbus_write_i2c_block_data(struct i2c_client * client,
+extern s32 i2c_smbus_write_i2c_block_data(struct i2c_client *client,
 					  u8 command, u8 length,
 					  const u8 *values);
 
@@ -169,7 +168,7 @@ struct i2c_driver {
 	/* a ioctl like command that can be used to perform specific functions
 	 * with the device.
 	 */
-	int (*command)(struct i2c_client *client,unsigned int cmd, void *arg);
+	int (*command)(struct i2c_client *client, unsigned int cmd, void *arg);
 
 	struct device_driver driver;
 	const struct i2c_device_id *id_table;
@@ -224,14 +223,14 @@ static inline struct i2c_client *kobj_to_i2c_client(struct kobject *kobj)
 	return to_i2c_client(dev);
 }
 
-static inline void *i2c_get_clientdata (struct i2c_client *dev)
+static inline void *i2c_get_clientdata(const struct i2c_client *dev)
 {
-	return dev_get_drvdata (&dev->dev);
+	return dev_get_drvdata(&dev->dev);
 }
 
-static inline void i2c_set_clientdata (struct i2c_client *dev, void *data)
+static inline void i2c_set_clientdata(struct i2c_client *dev, void *data)
 {
-	dev_set_drvdata (&dev->dev, data);
+	dev_set_drvdata(&dev->dev, data);
 }
 
 /**
@@ -240,6 +239,7 @@ static inline void i2c_set_clientdata (struct i2c_client *dev, void *data)
  * @flags: to initialize i2c_client.flags
  * @addr: stored in i2c_client.addr
  * @platform_data: stored in i2c_client.dev.platform_data
+ * @archdata: copied into i2c_client.dev.archdata
  * @irq: stored in i2c_client.irq
  *
  * I2C doesn't actually support hardware probing, although controllers and
@@ -259,6 +259,7 @@ struct i2c_board_info {
 	unsigned short	flags;
 	unsigned short	addr;
 	void		*platform_data;
+	struct dev_archdata	*archdata;
 	int		irq;
 };
 
@@ -272,7 +273,7 @@ struct i2c_board_info {
  * fields (such as associated irq, or device-specific platform_data)
  * are provided using conventional syntax.
  */
-#define I2C_BOARD_INFO(dev_type,dev_addr) \
+#define I2C_BOARD_INFO(dev_type, dev_addr) \
 	.type = (dev_type), .addr = (dev_addr)
 
 
@@ -306,10 +307,12 @@ extern void i2c_unregister_device(struct i2c_client *);
  */
 #ifdef CONFIG_I2C_BOARDINFO
 extern int
-i2c_register_board_info(int busnum, struct i2c_board_info const *info, unsigned n);
+i2c_register_board_info(int busnum, struct i2c_board_info const *info,
+			unsigned n);
 #else
 static inline int
-i2c_register_board_info(int busnum, struct i2c_board_info const *info, unsigned n)
+i2c_register_board_info(int busnum, struct i2c_board_info const *info,
+			unsigned n)
 {
 	return 0;
 }
@@ -328,11 +331,11 @@ struct i2c_algorithm {
 	   using common I2C messages */
 	/* master_xfer should return the number of messages successfully
 	   processed, or a negative value on error */
-	int (*master_xfer)(struct i2c_adapter *adap,struct i2c_msg *msgs,
-	                   int num);
+	int (*master_xfer)(struct i2c_adapter *adap, struct i2c_msg *msgs,
+			   int num);
 	int (*smbus_xfer) (struct i2c_adapter *adap, u16 addr,
-	                   unsigned short flags, char read_write,
-	                   u8 command, int size, union i2c_smbus_data * data);
+			   unsigned short flags, char read_write,
+			   u8 command, int size, union i2c_smbus_data *data);
 
 	/* To determine what the adapter supports */
 	u32 (*functionality) (struct i2c_adapter *);
@@ -345,7 +348,7 @@ struct i2c_algorithm {
 struct i2c_adapter {
 	struct module *owner;
 	unsigned int id;
-	unsigned int class;
+	unsigned int class;		  /* classes to allow probing for */
 	const struct i2c_algorithm *algo; /* the algorithm to access the bus */
 	void *algo_data;
 
@@ -369,14 +372,14 @@ struct i2c_adapter {
 };
 #define to_i2c_adapter(d) container_of(d, struct i2c_adapter, dev)
 
-static inline void *i2c_get_adapdata (struct i2c_adapter *dev)
+static inline void *i2c_get_adapdata(const struct i2c_adapter *dev)
 {
-	return dev_get_drvdata (&dev->dev);
+	return dev_get_drvdata(&dev->dev);
 }
 
-static inline void i2c_set_adapdata (struct i2c_adapter *dev, void *data)
+static inline void i2c_set_adapdata(struct i2c_adapter *dev, void *data)
 {
-	dev_set_drvdata (&dev->dev, data);
+	dev_set_drvdata(&dev->dev, data);
 }
 
 /*flags for the client struct: */
@@ -449,7 +452,7 @@ extern int i2c_probe(struct i2c_adapter *adapter,
 		const struct i2c_client_address_data *address_data,
 		int (*found_proc) (struct i2c_adapter *, int, int));
 
-extern struct i2c_adapter* i2c_get_adapter(int id);
+extern struct i2c_adapter *i2c_get_adapter(int id);
 extern void i2c_put_adapter(struct i2c_adapter *adap);
 
 
@@ -465,7 +468,7 @@ static inline int i2c_check_functionality(struct i2c_adapter *adap, u32 func)
 	return (func & i2c_get_functionality(adap)) == func;
 }
 
-/* Return id number for a specific adapter */
+/* Return the adapter number for a specific adapter */
 static inline int i2c_adapter_id(struct i2c_adapter *adap)
 {
 	return adap->nr;
@@ -526,7 +529,7 @@ struct i2c_msg {
 
 #define I2C_FUNC_I2C			0x00000001
 #define I2C_FUNC_10BIT_ADDR		0x00000002
-#define I2C_FUNC_PROTOCOL_MANGLING	0x00000004 /* I2C_M_{REV_DIR_ADDR,NOSTART,..} */
+#define I2C_FUNC_PROTOCOL_MANGLING	0x00000004 /* I2C_M_NOSTART etc. */
 #define I2C_FUNC_SMBUS_PEC		0x00000008
 #define I2C_FUNC_SMBUS_BLOCK_PROC_CALL	0x00008000 /* SMBus 2.0 */
 #define I2C_FUNC_SMBUS_QUICK		0x00010000
@@ -541,30 +544,26 @@ struct i2c_msg {
 #define I2C_FUNC_SMBUS_WRITE_BLOCK_DATA 0x02000000
 #define I2C_FUNC_SMBUS_READ_I2C_BLOCK	0x04000000 /* I2C-like block xfer  */
 #define I2C_FUNC_SMBUS_WRITE_I2C_BLOCK	0x08000000 /* w/ 1-byte reg. addr. */
-#define I2C_FUNC_SMBUS_READ_I2C_BLOCK_2	 0x10000000 /* I2C-like block xfer  */
-#define I2C_FUNC_SMBUS_WRITE_I2C_BLOCK_2 0x20000000 /* w/ 2-byte reg. addr. */
-
-#define I2C_FUNC_SMBUS_BYTE (I2C_FUNC_SMBUS_READ_BYTE | \
-                             I2C_FUNC_SMBUS_WRITE_BYTE)
-#define I2C_FUNC_SMBUS_BYTE_DATA (I2C_FUNC_SMBUS_READ_BYTE_DATA | \
-                                  I2C_FUNC_SMBUS_WRITE_BYTE_DATA)
-#define I2C_FUNC_SMBUS_WORD_DATA (I2C_FUNC_SMBUS_READ_WORD_DATA | \
-                                  I2C_FUNC_SMBUS_WRITE_WORD_DATA)
-#define I2C_FUNC_SMBUS_BLOCK_DATA (I2C_FUNC_SMBUS_READ_BLOCK_DATA | \
-                                   I2C_FUNC_SMBUS_WRITE_BLOCK_DATA)
-#define I2C_FUNC_SMBUS_I2C_BLOCK (I2C_FUNC_SMBUS_READ_I2C_BLOCK | \
-                                  I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)
-#define I2C_FUNC_SMBUS_I2C_BLOCK_2 (I2C_FUNC_SMBUS_READ_I2C_BLOCK_2 | \
-                                    I2C_FUNC_SMBUS_WRITE_I2C_BLOCK_2)
-
-#define I2C_FUNC_SMBUS_EMUL (I2C_FUNC_SMBUS_QUICK | \
-                             I2C_FUNC_SMBUS_BYTE | \
-                             I2C_FUNC_SMBUS_BYTE_DATA | \
-                             I2C_FUNC_SMBUS_WORD_DATA | \
-                             I2C_FUNC_SMBUS_PROC_CALL | \
-                             I2C_FUNC_SMBUS_WRITE_BLOCK_DATA | \
-			     I2C_FUNC_SMBUS_I2C_BLOCK | \
-			     I2C_FUNC_SMBUS_PEC)
+
+#define I2C_FUNC_SMBUS_BYTE		(I2C_FUNC_SMBUS_READ_BYTE | \
+					 I2C_FUNC_SMBUS_WRITE_BYTE)
+#define I2C_FUNC_SMBUS_BYTE_DATA	(I2C_FUNC_SMBUS_READ_BYTE_DATA | \
+					 I2C_FUNC_SMBUS_WRITE_BYTE_DATA)
+#define I2C_FUNC_SMBUS_WORD_DATA	(I2C_FUNC_SMBUS_READ_WORD_DATA | \
+					 I2C_FUNC_SMBUS_WRITE_WORD_DATA)
+#define I2C_FUNC_SMBUS_BLOCK_DATA	(I2C_FUNC_SMBUS_READ_BLOCK_DATA | \
+					 I2C_FUNC_SMBUS_WRITE_BLOCK_DATA)
+#define I2C_FUNC_SMBUS_I2C_BLOCK	(I2C_FUNC_SMBUS_READ_I2C_BLOCK | \
+					 I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)
+
+#define I2C_FUNC_SMBUS_EMUL		(I2C_FUNC_SMBUS_QUICK | \
+					 I2C_FUNC_SMBUS_BYTE | \
+					 I2C_FUNC_SMBUS_BYTE_DATA | \
+					 I2C_FUNC_SMBUS_WORD_DATA | \
+					 I2C_FUNC_SMBUS_PROC_CALL | \
+					 I2C_FUNC_SMBUS_WRITE_BLOCK_DATA | \
+					 I2C_FUNC_SMBUS_I2C_BLOCK | \
+					 I2C_FUNC_SMBUS_PEC)
 
 /*
  * Data for SMBus Messages
@@ -574,7 +573,7 @@ union i2c_smbus_data {
 	__u8 byte;
 	__u16 word;
 	__u8 block[I2C_SMBUS_BLOCK_MAX + 2]; /* block[0] is used for length */
-	                       /* and one more for user-space compatibility */
+			       /* and one more for user-space compatibility */
 };
 
 /* i2c_smbus_xfer read or write markers */
@@ -602,21 +601,21 @@ union i2c_smbus_data {
 
 /* Default fill of many variables */
 #define I2C_CLIENT_DEFAULTS {I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
-                          I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
-                          I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
-                          I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
-                          I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
-                          I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
-                          I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
-                          I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
-                          I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
-                          I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
-                          I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
-                          I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
-                          I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
-                          I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
-                          I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
-                          I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END}
+			     I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
+			     I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
+			     I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
+			     I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
+			     I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
+			     I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
+			     I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
+			     I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
+			     I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
+			     I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
+			     I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
+			     I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
+			     I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
+			     I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END, \
+			     I2C_CLIENT_END, I2C_CLIENT_END, I2C_CLIENT_END}
 
 /* I2C_CLIENT_MODULE_PARM creates a module parameter, and puts it in the
    module header */
@@ -625,7 +624,7 @@ union i2c_smbus_data {
   static unsigned short var[I2C_CLIENT_MAX_OPTS] = I2C_CLIENT_DEFAULTS; \
   static unsigned int var##_num; \
   module_param_array(var, short, &var##_num, 0); \
-  MODULE_PARM_DESC(var,desc)
+  MODULE_PARM_DESC(var, desc)
 
 #define I2C_CLIENT_MODULE_PARM_FORCE(name)				\
 I2C_CLIENT_MODULE_PARM(force_##name,					\
diff --git a/include/linux/i2c/twl4030.h b/include/linux/i2c/twl4030.h
new file mode 100644
index 000000000000..fb604dcd38f1
--- /dev/null
+++ b/include/linux/i2c/twl4030.h
@@ -0,0 +1,343 @@
+/*
+ * twl4030.h - header for TWL4030 PM and audio CODEC device
+ *
+ * Copyright (C) 2005-2006 Texas Instruments, Inc.
+ *
+ * Based on tlv320aic23.c:
+ * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#ifndef __TWL4030_H_
+#define __TWL4030_H_
+
+/*
+ * Using the twl4030 core we address registers using a pair
+ *	{ module id, relative register offset }
+ * which that core then maps to the relevant
+ *	{ i2c slave, absolute register address }
+ *
+ * The module IDs are meaningful only to the twl4030 core code,
+ * which uses them as array indices to look up the first register
+ * address each module uses within a given i2c slave.
+ */
+
+/* Slave 0 (i2c address 0x48) */
+#define TWL4030_MODULE_USB		0x00
+
+/* Slave 1 (i2c address 0x49) */
+#define TWL4030_MODULE_AUDIO_VOICE	0x01
+#define TWL4030_MODULE_GPIO		0x02
+#define TWL4030_MODULE_INTBR		0x03
+#define TWL4030_MODULE_PIH		0x04
+#define TWL4030_MODULE_TEST		0x05
+
+/* Slave 2 (i2c address 0x4a) */
+#define TWL4030_MODULE_KEYPAD		0x06
+#define TWL4030_MODULE_MADC		0x07
+#define TWL4030_MODULE_INTERRUPTS	0x08
+#define TWL4030_MODULE_LED		0x09
+#define TWL4030_MODULE_MAIN_CHARGE	0x0A
+#define TWL4030_MODULE_PRECHARGE	0x0B
+#define TWL4030_MODULE_PWM0		0x0C
+#define TWL4030_MODULE_PWM1		0x0D
+#define TWL4030_MODULE_PWMA		0x0E
+#define TWL4030_MODULE_PWMB		0x0F
+
+/* Slave 3 (i2c address 0x4b) */
+#define TWL4030_MODULE_BACKUP		0x10
+#define TWL4030_MODULE_INT		0x11
+#define TWL4030_MODULE_PM_MASTER	0x12
+#define TWL4030_MODULE_PM_RECEIVER	0x13
+#define TWL4030_MODULE_RTC		0x14
+#define TWL4030_MODULE_SECURED_REG	0x15
+
+/*
+ * Read and write single 8-bit registers
+ */
+int twl4030_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
+int twl4030_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);
+
+/*
+ * Read and write several 8-bit registers at once.
+ *
+ * IMPORTANT:  For twl4030_i2c_write(), allocate num_bytes + 1
+ * for the value, and populate your data starting at offset 1.
+ */
+int twl4030_i2c_write(u8 mod_no, u8 *value, u8 reg, u8 num_bytes);
+int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, u8 num_bytes);
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * NOTE:  at up to 1024 registers, this is a big chip.
+ *
+ * Avoid putting register declarations in this file, instead of into
+ * a driver-private file, unless some of the registers in a block
+ * need to be shared with other drivers.  One example is blocks that
+ * have Secondary IRQ Handler (SIH) registers.
+ */
+
+#define TWL4030_SIH_CTRL_EXCLEN_MASK	BIT(0)
+#define TWL4030_SIH_CTRL_PENDDIS_MASK	BIT(1)
+#define TWL4030_SIH_CTRL_COR_MASK	BIT(2)
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * GPIO Block Register offsets (use TWL4030_MODULE_GPIO)
+ */
+
+#define REG_GPIODATAIN1			0x0
+#define REG_GPIODATAIN2			0x1
+#define REG_GPIODATAIN3			0x2
+#define REG_GPIODATADIR1		0x3
+#define REG_GPIODATADIR2		0x4
+#define REG_GPIODATADIR3		0x5
+#define REG_GPIODATAOUT1		0x6
+#define REG_GPIODATAOUT2		0x7
+#define REG_GPIODATAOUT3		0x8
+#define REG_CLEARGPIODATAOUT1		0x9
+#define REG_CLEARGPIODATAOUT2		0xA
+#define REG_CLEARGPIODATAOUT3		0xB
+#define REG_SETGPIODATAOUT1		0xC
+#define REG_SETGPIODATAOUT2		0xD
+#define REG_SETGPIODATAOUT3		0xE
+#define REG_GPIO_DEBEN1			0xF
+#define REG_GPIO_DEBEN2			0x10
+#define REG_GPIO_DEBEN3			0x11
+#define REG_GPIO_CTRL			0x12
+#define REG_GPIOPUPDCTR1		0x13
+#define REG_GPIOPUPDCTR2		0x14
+#define REG_GPIOPUPDCTR3		0x15
+#define REG_GPIOPUPDCTR4		0x16
+#define REG_GPIOPUPDCTR5		0x17
+#define REG_GPIO_ISR1A			0x19
+#define REG_GPIO_ISR2A			0x1A
+#define REG_GPIO_ISR3A			0x1B
+#define REG_GPIO_IMR1A			0x1C
+#define REG_GPIO_IMR2A			0x1D
+#define REG_GPIO_IMR3A			0x1E
+#define REG_GPIO_ISR1B			0x1F
+#define REG_GPIO_ISR2B			0x20
+#define REG_GPIO_ISR3B			0x21
+#define REG_GPIO_IMR1B			0x22
+#define REG_GPIO_IMR2B			0x23
+#define REG_GPIO_IMR3B			0x24
+#define REG_GPIO_EDR1			0x28
+#define REG_GPIO_EDR2			0x29
+#define REG_GPIO_EDR3			0x2A
+#define REG_GPIO_EDR4			0x2B
+#define REG_GPIO_EDR5			0x2C
+#define REG_GPIO_SIH_CTRL		0x2D
+
+/* Up to 18 signals are available as GPIOs, when their
+ * pins are not assigned to another use (such as ULPI/USB).
+ */
+#define TWL4030_GPIO_MAX		18
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * Keypad register offsets (use TWL4030_MODULE_KEYPAD)
+ * ... SIH/interrupt only
+ */
+
+#define TWL4030_KEYPAD_KEYP_ISR1	0x11
+#define TWL4030_KEYPAD_KEYP_IMR1	0x12
+#define TWL4030_KEYPAD_KEYP_ISR2	0x13
+#define TWL4030_KEYPAD_KEYP_IMR2	0x14
+#define TWL4030_KEYPAD_KEYP_SIR		0x15	/* test register */
+#define TWL4030_KEYPAD_KEYP_EDR		0x16
+#define TWL4030_KEYPAD_KEYP_SIH_CTRL	0x17
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * Multichannel ADC register offsets (use TWL4030_MODULE_MADC)
+ * ... SIH/interrupt only
+ */
+
+#define TWL4030_MADC_ISR1		0x61
+#define TWL4030_MADC_IMR1		0x62
+#define TWL4030_MADC_ISR2		0x63
+#define TWL4030_MADC_IMR2		0x64
+#define TWL4030_MADC_SIR		0x65	/* test register */
+#define TWL4030_MADC_EDR		0x66
+#define TWL4030_MADC_SIH_CTRL		0x67
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS)
+ */
+
+#define TWL4030_INTERRUPTS_BCIISR1A	0x0
+#define TWL4030_INTERRUPTS_BCIISR2A	0x1
+#define TWL4030_INTERRUPTS_BCIIMR1A	0x2
+#define TWL4030_INTERRUPTS_BCIIMR2A	0x3
+#define TWL4030_INTERRUPTS_BCIISR1B	0x4
+#define TWL4030_INTERRUPTS_BCIISR2B	0x5
+#define TWL4030_INTERRUPTS_BCIIMR1B	0x6
+#define TWL4030_INTERRUPTS_BCIIMR2B	0x7
+#define TWL4030_INTERRUPTS_BCISIR1	0x8	/* test register */
+#define TWL4030_INTERRUPTS_BCISIR2	0x9	/* test register */
+#define TWL4030_INTERRUPTS_BCIEDR1	0xa
+#define TWL4030_INTERRUPTS_BCIEDR2	0xb
+#define TWL4030_INTERRUPTS_BCIEDR3	0xc
+#define TWL4030_INTERRUPTS_BCISIHCTRL	0xd
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * Power Interrupt block register offsets (use TWL4030_MODULE_INT)
+ */
+
+#define TWL4030_INT_PWR_ISR1		0x0
+#define TWL4030_INT_PWR_IMR1		0x1
+#define TWL4030_INT_PWR_ISR2		0x2
+#define TWL4030_INT_PWR_IMR2		0x3
+#define TWL4030_INT_PWR_SIR		0x4	/* test register */
+#define TWL4030_INT_PWR_EDR1		0x5
+#define TWL4030_INT_PWR_EDR2		0x6
+#define TWL4030_INT_PWR_SIH_CTRL	0x7
+
+/*----------------------------------------------------------------------*/
+
+struct twl4030_bci_platform_data {
+	int *battery_tmp_tbl;
+	unsigned int tblsize;
+};
+
+/* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
+struct twl4030_gpio_platform_data {
+	int		gpio_base;
+	unsigned	irq_base, irq_end;
+
+	/* package the two LED signals as output-only GPIOs? */
+	bool		use_leds;
+
+	/* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */
+	u8		mmc_cd;
+
+	/* For gpio-N, bit (1 << N) in "pullups" is set if that pullup
+	 * should be enabled.  Else, if that bit is set in "pulldowns",
+	 * that pulldown is enabled.  Don't waste power by letting any
+	 * digital inputs float...
+	 */
+	u32		pullups;
+	u32		pulldowns;
+
+	int		(*setup)(struct device *dev,
+				unsigned gpio, unsigned ngpio);
+	int		(*teardown)(struct device *dev,
+				unsigned gpio, unsigned ngpio);
+};
+
+struct twl4030_madc_platform_data {
+	int		irq_line;
+};
+
+struct twl4030_keypad_data {
+	int rows;
+	int cols;
+	int *keymap;
+	int irq;
+	unsigned int keymapsize;
+	unsigned int rep:1;
+};
+
+enum twl4030_usb_mode {
+	T2_USB_MODE_ULPI = 1,
+	T2_USB_MODE_CEA2011_3PIN = 2,
+};
+
+struct twl4030_usb_data {
+	enum twl4030_usb_mode	usb_mode;
+};
+
+struct twl4030_platform_data {
+	unsigned				irq_base, irq_end;
+	struct twl4030_bci_platform_data	*bci;
+	struct twl4030_gpio_platform_data	*gpio;
+	struct twl4030_madc_platform_data	*madc;
+	struct twl4030_keypad_data		*keypad;
+	struct twl4030_usb_data			*usb;
+
+	/* REVISIT more to come ... _nothing_ should be hard-wired */
+};
+
+/*----------------------------------------------------------------------*/
+
+int twl4030_sih_setup(int module);
+
+/*
+ * FIXME completely stop using TWL4030_IRQ_BASE ... instead, pass the
+ * IRQ data to subsidiary devices using platform device resources.
+ */
+
+/* IRQ information-need base */
+#include <mach/irqs.h>
+/* TWL4030 interrupts */
+
+/* #define TWL4030_MODIRQ_GPIO		(TWL4030_IRQ_BASE + 0) */
+#define TWL4030_MODIRQ_KEYPAD		(TWL4030_IRQ_BASE + 1)
+#define TWL4030_MODIRQ_BCI		(TWL4030_IRQ_BASE + 2)
+#define TWL4030_MODIRQ_MADC		(TWL4030_IRQ_BASE + 3)
+/* #define TWL4030_MODIRQ_USB		(TWL4030_IRQ_BASE + 4) */
+/* #define TWL4030_MODIRQ_PWR		(TWL4030_IRQ_BASE + 5) */
+
+#define TWL4030_PWRIRQ_PWRBTN		(TWL4030_PWR_IRQ_BASE + 0)
+/* #define TWL4030_PWRIRQ_CHG_PRES		(TWL4030_PWR_IRQ_BASE + 1) */
+/* #define TWL4030_PWRIRQ_USB_PRES		(TWL4030_PWR_IRQ_BASE + 2) */
+/* #define TWL4030_PWRIRQ_RTC		(TWL4030_PWR_IRQ_BASE + 3) */
+/* #define TWL4030_PWRIRQ_HOT_DIE		(TWL4030_PWR_IRQ_BASE + 4) */
+/* #define TWL4030_PWRIRQ_PWROK_TIMEOUT	(TWL4030_PWR_IRQ_BASE + 5) */
+/* #define TWL4030_PWRIRQ_MBCHG		(TWL4030_PWR_IRQ_BASE + 6) */
+/* #define TWL4030_PWRIRQ_SC_DETECT	(TWL4030_PWR_IRQ_BASE + 7) */
+
+/* Rest are unsued currently*/
+
+/* Offsets to Power Registers */
+#define TWL4030_VDAC_DEV_GRP		0x3B
+#define TWL4030_VDAC_DEDICATED		0x3E
+#define TWL4030_VAUX1_DEV_GRP		0x17
+#define TWL4030_VAUX1_DEDICATED		0x1A
+#define TWL4030_VAUX2_DEV_GRP		0x1B
+#define TWL4030_VAUX2_DEDICATED		0x1E
+#define TWL4030_VAUX3_DEV_GRP		0x1F
+#define TWL4030_VAUX3_DEDICATED		0x22
+
+/* TWL4030 GPIO interrupt definitions */
+
+#define TWL4030_GPIO_IRQ_NO(n)		(TWL4030_GPIO_IRQ_BASE + (n))
+
+/*
+ * Exported TWL4030 GPIO APIs
+ *
+ * WARNING -- use standard GPIO and IRQ calls instead; these will vanish.
+ */
+int twl4030_set_gpio_debounce(int gpio, int enable);
+
+#if defined(CONFIG_TWL4030_BCI_BATTERY) || \
+	defined(CONFIG_TWL4030_BCI_BATTERY_MODULE)
+	extern int twl4030charger_usb_en(int enable);
+#else
+	static inline int twl4030charger_usb_en(int enable) { return 0; }
+#endif
+
+#endif /* End of __TWL4030_H */
diff --git a/include/linux/i2o.h b/include/linux/i2o.h
index 75ae6d8aba4f..4c4e57d1f19d 100644
--- a/include/linux/i2o.h
+++ b/include/linux/i2o.h
@@ -570,7 +570,6 @@ struct i2o_controller {
 #endif
 	spinlock_t lock;	/* lock for controller
 				   configuration */
-
 	void *driver_data[I2O_MAX_DRIVERS];	/* storage for drivers */
 };
 
@@ -691,289 +690,22 @@ static inline u32 i2o_dma_high(dma_addr_t dma_addr)
 };
 #endif
 
-/**
- *	i2o_sg_tablesize - Calculate the maximum number of elements in a SGL
- *	@c: I2O controller for which the calculation should be done
- *	@body_size: maximum body size used for message in 32-bit words.
- *
- *	Return the maximum number of SG elements in a SG list.
- */
-static inline u16 i2o_sg_tablesize(struct i2o_controller *c, u16 body_size)
-{
-	i2o_status_block *sb = c->status_block.virt;
-	u16 sg_count =
-	    (sb->inbound_frame_size - sizeof(struct i2o_message) / 4) -
-	    body_size;
-
-	if (c->pae_support) {
-		/*
-		 * for 64-bit a SG attribute element must be added and each
-		 * SG element needs 12 bytes instead of 8.
-		 */
-		sg_count -= 2;
-		sg_count /= 3;
-	} else
-		sg_count /= 2;
-
-	if (c->short_req && (sg_count > 8))
-		sg_count = 8;
-
-	return sg_count;
-};
-
-/**
- *	i2o_dma_map_single - Map pointer to controller and fill in I2O message.
- *	@c: I2O controller
- *	@ptr: pointer to the data which should be mapped
- *	@size: size of data in bytes
- *	@direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
- *	@sg_ptr: pointer to the SG list inside the I2O message
- *
- *	This function does all necessary DMA handling and also writes the I2O
- *	SGL elements into the I2O message. For details on DMA handling see also
- *	dma_map_single(). The pointer sg_ptr will only be set to the end of the
- *	SG list if the allocation was successful.
- *
- *	Returns DMA address which must be checked for failures using
- *	dma_mapping_error().
- */
-static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
+extern u16 i2o_sg_tablesize(struct i2o_controller *c, u16 body_size);
+extern dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
 					    size_t size,
 					    enum dma_data_direction direction,
-					    u32 ** sg_ptr)
-{
-	u32 sg_flags;
-	u32 *mptr = *sg_ptr;
-	dma_addr_t dma_addr;
-
-	switch (direction) {
-	case DMA_TO_DEVICE:
-		sg_flags = 0xd4000000;
-		break;
-	case DMA_FROM_DEVICE:
-		sg_flags = 0xd0000000;
-		break;
-	default:
-		return 0;
-	}
-
-	dma_addr = dma_map_single(&c->pdev->dev, ptr, size, direction);
-	if (!dma_mapping_error(&c->pdev->dev, dma_addr)) {
-#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
-		if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
-			*mptr++ = cpu_to_le32(0x7C020002);
-			*mptr++ = cpu_to_le32(PAGE_SIZE);
-		}
-#endif
-
-		*mptr++ = cpu_to_le32(sg_flags | size);
-		*mptr++ = cpu_to_le32(i2o_dma_low(dma_addr));
-#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
-		if ((sizeof(dma_addr_t) > 4) && c->pae_support)
-			*mptr++ = cpu_to_le32(i2o_dma_high(dma_addr));
-#endif
-		*sg_ptr = mptr;
-	}
-	return dma_addr;
-};
-
-/**
- *	i2o_dma_map_sg - Map a SG List to controller and fill in I2O message.
- *	@c: I2O controller
- *	@sg: SG list to be mapped
- *	@sg_count: number of elements in the SG list
- *	@direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
- *	@sg_ptr: pointer to the SG list inside the I2O message
- *
- *	This function does all necessary DMA handling and also writes the I2O
- *	SGL elements into the I2O message. For details on DMA handling see also
- *	dma_map_sg(). The pointer sg_ptr will only be set to the end of the SG
- *	list if the allocation was successful.
- *
- *	Returns 0 on failure or 1 on success.
- */
-static inline int i2o_dma_map_sg(struct i2o_controller *c,
+					    u32 ** sg_ptr);
+extern int i2o_dma_map_sg(struct i2o_controller *c,
 				 struct scatterlist *sg, int sg_count,
 				 enum dma_data_direction direction,
-				 u32 ** sg_ptr)
-{
-	u32 sg_flags;
-	u32 *mptr = *sg_ptr;
-
-	switch (direction) {
-	case DMA_TO_DEVICE:
-		sg_flags = 0x14000000;
-		break;
-	case DMA_FROM_DEVICE:
-		sg_flags = 0x10000000;
-		break;
-	default:
-		return 0;
-	}
-
-	sg_count = dma_map_sg(&c->pdev->dev, sg, sg_count, direction);
-	if (!sg_count)
-		return 0;
-
-#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
-	if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
-		*mptr++ = cpu_to_le32(0x7C020002);
-		*mptr++ = cpu_to_le32(PAGE_SIZE);
-	}
-#endif
-
-	while (sg_count-- > 0) {
-		if (!sg_count)
-			sg_flags |= 0xC0000000;
-		*mptr++ = cpu_to_le32(sg_flags | sg_dma_len(sg));
-		*mptr++ = cpu_to_le32(i2o_dma_low(sg_dma_address(sg)));
-#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
-		if ((sizeof(dma_addr_t) > 4) && c->pae_support)
-			*mptr++ = cpu_to_le32(i2o_dma_high(sg_dma_address(sg)));
-#endif
-		sg = sg_next(sg);
-	}
-	*sg_ptr = mptr;
-
-	return 1;
-};
-
-/**
- *	i2o_dma_alloc - Allocate DMA memory
- *	@dev: struct device pointer to the PCI device of the I2O controller
- *	@addr: i2o_dma struct which should get the DMA buffer
- *	@len: length of the new DMA memory
- *	@gfp_mask: GFP mask
- *
- *	Allocate a coherent DMA memory and write the pointers into addr.
- *
- *	Returns 0 on success or -ENOMEM on failure.
- */
-static inline int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr,
-				size_t len, gfp_t gfp_mask)
-{
-	struct pci_dev *pdev = to_pci_dev(dev);
-	int dma_64 = 0;
-
-	if ((sizeof(dma_addr_t) > 4) && (pdev->dma_mask == DMA_64BIT_MASK)) {
-		dma_64 = 1;
-		if (pci_set_dma_mask(pdev, DMA_32BIT_MASK))
-			return -ENOMEM;
-	}
-
-	addr->virt = dma_alloc_coherent(dev, len, &addr->phys, gfp_mask);
-
-	if ((sizeof(dma_addr_t) > 4) && dma_64)
-		if (pci_set_dma_mask(pdev, DMA_64BIT_MASK))
-			printk(KERN_WARNING "i2o: unable to set 64-bit DMA");
-
-	if (!addr->virt)
-		return -ENOMEM;
-
-	memset(addr->virt, 0, len);
-	addr->len = len;
-
-	return 0;
-};
-
-/**
- *	i2o_dma_free - Free DMA memory
- *	@dev: struct device pointer to the PCI device of the I2O controller
- *	@addr: i2o_dma struct which contains the DMA buffer
- *
- *	Free a coherent DMA memory and set virtual address of addr to NULL.
- */
-static inline void i2o_dma_free(struct device *dev, struct i2o_dma *addr)
-{
-	if (addr->virt) {
-		if (addr->phys)
-			dma_free_coherent(dev, addr->len, addr->virt,
-					  addr->phys);
-		else
-			kfree(addr->virt);
-		addr->virt = NULL;
-	}
-};
-
-/**
- *	i2o_dma_realloc - Realloc DMA memory
- *	@dev: struct device pointer to the PCI device of the I2O controller
- *	@addr: pointer to a i2o_dma struct DMA buffer
- *	@len: new length of memory
- *	@gfp_mask: GFP mask
- *
- *	If there was something allocated in the addr, free it first. If len > 0
- *	than try to allocate it and write the addresses back to the addr
- *	structure. If len == 0 set the virtual address to NULL.
- *
- *	Returns the 0 on success or negative error code on failure.
- */
-static inline int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr,
-				  size_t len, gfp_t gfp_mask)
-{
-	i2o_dma_free(dev, addr);
-
-	if (len)
-		return i2o_dma_alloc(dev, addr, len, gfp_mask);
-
-	return 0;
-};
-
-/*
- *	i2o_pool_alloc - Allocate an slab cache and mempool
- *	@mempool: pointer to struct i2o_pool to write data into.
- *	@name: name which is used to identify cache
- *	@size: size of each object
- *	@min_nr: minimum number of objects
- *
- *	First allocates a slab cache with name and size. Then allocates a
- *	mempool which uses the slab cache for allocation and freeing.
- *
- *	Returns 0 on success or negative error code on failure.
- */
-static inline int i2o_pool_alloc(struct i2o_pool *pool, const char *name,
-				 size_t size, int min_nr)
-{
-	pool->name = kmalloc(strlen(name) + 1, GFP_KERNEL);
-	if (!pool->name)
-		goto exit;
-	strcpy(pool->name, name);
-
-	pool->slab =
-	    kmem_cache_create(pool->name, size, 0, SLAB_HWCACHE_ALIGN, NULL);
-	if (!pool->slab)
-		goto free_name;
-
-	pool->mempool = mempool_create_slab_pool(min_nr, pool->slab);
-	if (!pool->mempool)
-		goto free_slab;
-
-	return 0;
-
-      free_slab:
-	kmem_cache_destroy(pool->slab);
-
-      free_name:
-	kfree(pool->name);
-
-      exit:
-	return -ENOMEM;
-};
-
-/*
- *	i2o_pool_free - Free slab cache and mempool again
- *	@mempool: pointer to struct i2o_pool which should be freed
- *
- *	Note that you have to return all objects to the mempool again before
- *	calling i2o_pool_free().
- */
-static inline void i2o_pool_free(struct i2o_pool *pool)
-{
-	mempool_destroy(pool->mempool);
-	kmem_cache_destroy(pool->slab);
-	kfree(pool->name);
-};
-
+				 u32 ** sg_ptr);
+extern int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr, size_t len);
+extern void i2o_dma_free(struct device *dev, struct i2o_dma *addr);
+extern int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr,
+								size_t len);
+extern int i2o_pool_alloc(struct i2o_pool *pool, const char *name,
+				 size_t size, int min_nr);
+extern void i2o_pool_free(struct i2o_pool *pool);
 /* I2O driver (OSM) functions */
 extern int i2o_driver_register(struct i2o_driver *);
 extern void i2o_driver_unregister(struct i2o_driver *);
diff --git a/include/linux/i7300_idle.h b/include/linux/i7300_idle.h
new file mode 100644
index 000000000000..05a80c44513c
--- /dev/null
+++ b/include/linux/i7300_idle.h
@@ -0,0 +1,83 @@
+
+#ifndef I7300_IDLE_H
+#define I7300_IDLE_H
+
+#include <linux/pci.h>
+
+/*
+ * I/O AT controls (PCI bus 0 device 8 function 0)
+ * DIMM controls (PCI bus 0 device 16 function 1)
+ */
+#define IOAT_BUS 0
+#define IOAT_DEVFN PCI_DEVFN(8, 0)
+#define MEMCTL_BUS 0
+#define MEMCTL_DEVFN PCI_DEVFN(16, 1)
+
+struct fbd_ioat {
+	unsigned int vendor;
+	unsigned int ioat_dev;
+};
+
+/*
+ * The i5000 chip-set has the same hooks as the i7300
+ * but support is disabled by default because this driver
+ * has not been validated on that platform.
+ */
+#define SUPPORT_I5000 0
+
+static const struct fbd_ioat fbd_ioat_list[] = {
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_CNB},
+#if SUPPORT_I5000
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT},
+#endif
+	{0, 0}
+};
+
+/* table of devices that work with this driver */
+static const struct pci_device_id pci_tbl[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_FBD_CNB) },
+#if SUPPORT_I5000
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5000_ERR) },
+#endif
+	{ } /* Terminating entry */
+};
+
+/* Check for known platforms with I/O-AT */
+static inline int i7300_idle_platform_probe(struct pci_dev **fbd_dev,
+						struct pci_dev **ioat_dev)
+{
+	int i;
+	struct pci_dev *memdev, *dmadev;
+
+	memdev = pci_get_bus_and_slot(MEMCTL_BUS, MEMCTL_DEVFN);
+	if (!memdev)
+		return -ENODEV;
+
+	for (i = 0; pci_tbl[i].vendor != 0; i++) {
+		if (memdev->vendor == pci_tbl[i].vendor &&
+		    memdev->device == pci_tbl[i].device) {
+			break;
+		}
+	}
+	if (pci_tbl[i].vendor == 0)
+		return -ENODEV;
+
+	dmadev = pci_get_bus_and_slot(IOAT_BUS, IOAT_DEVFN);
+	if (!dmadev)
+		return -ENODEV;
+
+	for (i = 0; fbd_ioat_list[i].vendor != 0; i++) {
+		if (dmadev->vendor == fbd_ioat_list[i].vendor &&
+		    dmadev->device == fbd_ioat_list[i].ioat_dev) {
+			if (fbd_dev)
+				*fbd_dev = memdev;
+			if (ioat_dev)
+				*ioat_dev = dmadev;
+
+			return 0;
+		}
+	}
+	return -ENODEV;
+}
+
+#endif
diff --git a/include/linux/icmpv6.h b/include/linux/icmpv6.h
index 03067443198a..a93a8dd33118 100644
--- a/include/linux/icmpv6.h
+++ b/include/linux/icmpv6.h
@@ -40,16 +40,18 @@ struct icmp6hdr {
                 struct icmpv6_nd_ra {
 			__u8		hop_limit;
 #if defined(__LITTLE_ENDIAN_BITFIELD)
-			__u8		reserved:4,
+			__u8		reserved:3,
 					router_pref:2,
+					home_agent:1,
 					other:1,
 					managed:1;
 
 #elif defined(__BIG_ENDIAN_BITFIELD)
 			__u8		managed:1,
 					other:1,
+					home_agent:1,
 					router_pref:2,
-					reserved:4;
+					reserved:3;
 #else
 #error	"Please fix <asm/byteorder.h>"
 #endif
diff --git a/include/linux/ide.h b/include/linux/ide.h
index c47e371554c1..e99c56de7f56 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -122,8 +122,6 @@ struct ide_io_ports {
 #define MAX_DRIVES	2	/* per interface; 2 assumed by lots of code */
 #define SECTOR_SIZE	512
 
-#define IDE_LARGE_SEEK(b1,b2,t)	(((b1) > (b2) + (t)) || ((b2) > (b1) + (t)))
-
 /*
  * Timeouts for various operations:
  */
@@ -172,9 +170,7 @@ typedef int (ide_ack_intr_t)(struct hwif_s *);
 enum {		ide_unknown,	ide_generic,	ide_pci,
 		ide_cmd640,	ide_dtc2278,	ide_ali14xx,
 		ide_qd65xx,	ide_umc8672,	ide_ht6560b,
-		ide_rz1000,	ide_trm290,
-		ide_cmd646,	ide_cy82c693,	ide_4drives,
-		ide_pmac,	ide_acorn,
+		ide_4drives,	ide_pmac,	ide_acorn,
 		ide_au1xxx,	ide_palm3710
 };
 
@@ -461,12 +457,26 @@ struct ide_acpi_drive_link;
 struct ide_acpi_hwif_link;
 #endif
 
+struct ide_drive_s;
+
+struct ide_disk_ops {
+	int		(*check)(struct ide_drive_s *, const char *);
+	int		(*get_capacity)(struct ide_drive_s *);
+	void		(*setup)(struct ide_drive_s *);
+	void		(*flush)(struct ide_drive_s *);
+	int		(*init_media)(struct ide_drive_s *, struct gendisk *);
+	int		(*set_doorlock)(struct ide_drive_s *, struct gendisk *,
+					int);
+	ide_startstop_t	(*do_request)(struct ide_drive_s *, struct request *,
+				      sector_t);
+	int		(*end_request)(struct ide_drive_s *, int, int);
+	int		(*ioctl)(struct ide_drive_s *, struct block_device *,
+				 fmode_t, unsigned int, unsigned long);
+};
+
 /* ATAPI device flags */
 enum {
 	IDE_AFLAG_DRQ_INTERRUPT		= (1 << 0),
-	IDE_AFLAG_MEDIA_CHANGED		= (1 << 1),
-	/* Drive cannot lock the door. */
-	IDE_AFLAG_NO_DOORLOCK		= (1 << 2),
 
 	/* ide-cd */
 	/* Drive cannot eject the disc. */
@@ -482,8 +492,6 @@ enum {
 	 * when more than one interrupt is needed.
 	 */
 	IDE_AFLAG_LIMIT_NFRAMES		= (1 << 7),
-	/* Seeking in progress. */
-	IDE_AFLAG_SEEKING		= (1 << 8),
 	/* Saved TOC information is current. */
 	IDE_AFLAG_TOC_VALID		= (1 << 9),
 	/* We think that the drive door is locked. */
@@ -498,14 +506,10 @@ enum {
 	IDE_AFLAG_LE_SPEED_FIELDS	= (1 << 17),
 
 	/* ide-floppy */
-	/* Format in progress */
-	IDE_AFLAG_FORMAT_IN_PROGRESS	= (1 << 18),
 	/* Avoid commands not supported in Clik drive */
 	IDE_AFLAG_CLIK_DRIVE		= (1 << 19),
 	/* Requires BH algorithm for packets */
 	IDE_AFLAG_ZIP_DRIVE		= (1 << 20),
-	/* Write protect */
-	IDE_AFLAG_WP			= (1 << 21),
 	/* Supports format progress report */
 	IDE_AFLAG_SRFP			= (1 << 22),
 
@@ -578,7 +582,11 @@ enum {
 	/* don't unload heads */
 	IDE_DFLAG_NO_UNLOAD		= (1 << 27),
 	/* heads unloaded, please don't reset port */
-	IDE_DFLAG_PARKED		= (1 << 28)
+	IDE_DFLAG_PARKED		= (1 << 28),
+	IDE_DFLAG_MEDIA_CHANGED		= (1 << 29),
+	/* write protect */
+	IDE_DFLAG_WP			= (1 << 30),
+	IDE_DFLAG_FORMAT_IN_PROGRESS	= (1 << 31),
 };
 
 struct ide_drive_s {
@@ -597,6 +605,8 @@ struct ide_drive_s {
 #endif
 	struct hwif_s		*hwif;	/* actually (ide_hwif_t *) */
 
+	const struct ide_disk_ops *disk_ops;
+
 	unsigned long dev_flags;
 
 	unsigned long sleep;		/* sleep until this time */
@@ -829,8 +839,6 @@ typedef struct hwif_s {
 	unsigned	extra_ports;	/* number of extra dma ports */
 
 	unsigned	present    : 1;	/* this interface exists */
-	unsigned	serialized : 1;	/* serialized all channel operation */
-	unsigned	sharing_irq: 1;	/* 1 = sharing irq with another hwif */
 	unsigned	sg_mapped  : 1;	/* sg_table and sg_nents are ready */
 
 	struct device		gendev;
@@ -893,6 +901,8 @@ typedef struct hwgroup_s {
 
 	int req_gen;
 	int req_gen_timer;
+
+	spinlock_t lock;
 } ide_hwgroup_t;
 
 typedef struct ide_driver_s ide_driver_t;
@@ -1106,6 +1116,14 @@ enum {
 	IDE_PM_COMPLETED,
 };
 
+int generic_ide_suspend(struct device *, pm_message_t);
+int generic_ide_resume(struct device *);
+
+void ide_complete_power_step(ide_drive_t *, struct request *);
+ide_startstop_t ide_start_power_step(ide_drive_t *, struct request *);
+void ide_complete_pm_request(ide_drive_t *, struct request *);
+void ide_check_pm_state(ide_drive_t *, struct request *);
+
 /*
  * Subdrivers support.
  *
@@ -1123,8 +1141,8 @@ struct ide_driver_s {
 	void		(*resume)(ide_drive_t *);
 	void		(*shutdown)(ide_drive_t *);
 #ifdef CONFIG_IDE_PROC_FS
-	ide_proc_entry_t		*proc;
-	const struct ide_proc_devset	*settings;
+	ide_proc_entry_t *		(*proc_entries)(ide_drive_t *);
+	const struct ide_proc_devset *	(*proc_devsets)(ide_drive_t *);
 #endif
 };
 
@@ -1142,8 +1160,7 @@ struct ide_ioctl_devset {
 int ide_setting_ioctl(ide_drive_t *, struct block_device *, unsigned int,
 		      unsigned long, const struct ide_ioctl_devset *);
 
-int generic_ide_ioctl(ide_drive_t *, struct file *, struct block_device *,
-		      unsigned, unsigned long);
+int generic_ide_ioctl(ide_drive_t *, struct block_device *, unsigned, unsigned long);
 
 extern int ide_vlb_clk;
 extern int ide_pci_clk;
@@ -1281,6 +1298,13 @@ extern int __ide_pci_register_driver(struct pci_driver *driver, struct module *o
 #define ide_pci_register_driver(d) pci_register_driver(d)
 #endif
 
+static inline int ide_pci_is_in_compatibility_mode(struct pci_dev *dev)
+{
+	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 5) != 5)
+		return 1;
+	return 0;
+}
+
 void ide_pci_setup_ports(struct pci_dev *, const struct ide_port_info *, int,
 			 hw_regs_t *, hw_regs_t **);
 void ide_setup_pci_noise(struct pci_dev *, const struct ide_port_info *);
@@ -1354,12 +1378,13 @@ enum {
 	IDE_HFLAG_LEGACY_IRQS		= (1 << 21),
 	/* force use of legacy IRQs */
 	IDE_HFLAG_FORCE_LEGACY_IRQS	= (1 << 22),
-	/* limit LBA48 requests to 256 sectors */
-	IDE_HFLAG_RQSIZE_256		= (1 << 23),
+	/* host is TRM290 */
+	IDE_HFLAG_TRM290		= (1 << 23),
 	/* use 32-bit I/O ops */
 	IDE_HFLAG_IO_32BIT		= (1 << 24),
 	/* unmask IRQs */
 	IDE_HFLAG_UNMASK_IRQS		= (1 << 25),
+	IDE_HFLAG_BROKEN_ALTSTATUS	= (1 << 26),
 	/* serialize ports if DMA is possible (for sl82c105) */
 	IDE_HFLAG_SERIALIZE_DMA		= (1 << 27),
 	/* force host out of "simplex" mode */
@@ -1392,6 +1417,9 @@ struct ide_port_info {
 
 	ide_pci_enablebit_t	enablebits[2];
 	hwif_chipset_t		chipset;
+
+	u16			max_sectors;	/* if < than the default one */
+
 	u32			host_flags;
 	u8			pio_mask;
 	u8			swdma_mask;
@@ -1587,13 +1615,13 @@ extern struct mutex ide_cfg_mtx;
 /*
  * Structure locking:
  *
- * ide_cfg_mtx and ide_lock together protect changes to
- * ide_hwif_t->{next,hwgroup}
+ * ide_cfg_mtx and hwgroup->lock together protect changes to
+ * ide_hwif_t->next
  * ide_drive_t->next
  *
- * ide_hwgroup_t->busy: ide_lock
- * ide_hwgroup_t->hwif: ide_lock
- * ide_hwif_t->mate: constant, no locking
+ * ide_hwgroup_t->busy: hwgroup->lock
+ * ide_hwgroup_t->hwif: hwgroup->lock
+ * ide_hwif_t->{hwgroup,mate}: constant, no locking
  * ide_drive_t->hwif: constant, no locking
  */
 
diff --git a/include/linux/idr.h b/include/linux/idr.h
index fa035f96f2a3..dd846df8cd32 100644
--- a/include/linux/idr.h
+++ b/include/linux/idr.h
@@ -52,13 +52,14 @@ struct idr_layer {
 	unsigned long		 bitmap; /* A zero bit means "space here" */
 	struct idr_layer	*ary[1<<IDR_BITS];
 	int			 count;	 /* When zero, we can release it */
+	int			 layer;	 /* distance from leaf */
 	struct rcu_head		 rcu_head;
 };
 
 struct idr {
 	struct idr_layer *top;
 	struct idr_layer *id_free;
-	int		  layers;
+	int		  layers; /* only valid without concurrent changes */
 	int		  id_free_cnt;
 	spinlock_t	  lock;
 };
diff --git a/include/linux/ieee80211.h b/include/linux/ieee80211.h
index 14126bc36641..c4e6ca1a6306 100644
--- a/include/linux/ieee80211.h
+++ b/include/linux/ieee80211.h
@@ -12,8 +12,8 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef IEEE80211_H
-#define IEEE80211_H
+#ifndef LINUX_IEEE80211_H
+#define LINUX_IEEE80211_H
 
 #include <linux/types.h>
 #include <asm/byteorder.h>
@@ -97,7 +97,10 @@
 #define IEEE80211_MAX_FRAME_LEN		2352
 
 #define IEEE80211_MAX_SSID_LEN		32
+
 #define IEEE80211_MAX_MESH_ID_LEN	32
+#define IEEE80211_MESH_CONFIG_LEN	19
+
 #define IEEE80211_QOS_CTL_LEN		2
 #define IEEE80211_QOS_CTL_TID_MASK	0x000F
 #define IEEE80211_QOS_CTL_TAG1D_MASK	0x0007
@@ -666,6 +669,13 @@ struct ieee80211_cts {
 	u8 ra[6];
 } __attribute__ ((packed));
 
+struct ieee80211_pspoll {
+	__le16 frame_control;
+	__le16 aid;
+	u8 bssid[6];
+	u8 ta[6];
+} __attribute__ ((packed));
+
 /**
  * struct ieee80211_bar - HT Block Ack Request
  *
@@ -685,28 +695,88 @@ struct ieee80211_bar {
 #define IEEE80211_BAR_CTRL_ACK_POLICY_NORMAL     0x0000
 #define IEEE80211_BAR_CTRL_CBMTID_COMPRESSED_BA  0x0004
 
+
+#define IEEE80211_HT_MCS_MASK_LEN		10
+
+/**
+ * struct ieee80211_mcs_info - MCS information
+ * @rx_mask: RX mask
+ * @rx_highest: highest supported RX rate
+ * @tx_params: TX parameters
+ */
+struct ieee80211_mcs_info {
+	u8 rx_mask[IEEE80211_HT_MCS_MASK_LEN];
+	__le16 rx_highest;
+	u8 tx_params;
+	u8 reserved[3];
+} __attribute__((packed));
+
+/* 802.11n HT capability MSC set */
+#define IEEE80211_HT_MCS_RX_HIGHEST_MASK	0x3ff
+#define IEEE80211_HT_MCS_TX_DEFINED		0x01
+#define IEEE80211_HT_MCS_TX_RX_DIFF		0x02
+/* value 0 == 1 stream etc */
+#define IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK	0x0C
+#define IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT	2
+#define		IEEE80211_HT_MCS_TX_MAX_STREAMS	4
+#define IEEE80211_HT_MCS_TX_UNEQUAL_MODULATION	0x10
+
+/*
+ * 802.11n D5.0 20.3.5 / 20.6 says:
+ * - indices 0 to 7 and 32 are single spatial stream
+ * - 8 to 31 are multiple spatial streams using equal modulation
+ *   [8..15 for two streams, 16..23 for three and 24..31 for four]
+ * - remainder are multiple spatial streams using unequal modulation
+ */
+#define IEEE80211_HT_MCS_UNEQUAL_MODULATION_START 33
+#define IEEE80211_HT_MCS_UNEQUAL_MODULATION_START_BYTE \
+	(IEEE80211_HT_MCS_UNEQUAL_MODULATION_START / 8)
+
 /**
  * struct ieee80211_ht_cap - HT capabilities
  *
- * This structure refers to "HT capabilities element" as
- * described in 802.11n draft section 7.3.2.52
+ * This structure is the "HT capabilities element" as
+ * described in 802.11n D5.0 7.3.2.57
  */
 struct ieee80211_ht_cap {
 	__le16 cap_info;
 	u8 ampdu_params_info;
-	u8 supp_mcs_set[16];
+
+	/* 16 bytes MCS information */
+	struct ieee80211_mcs_info mcs;
+
 	__le16 extended_ht_cap_info;
 	__le32 tx_BF_cap_info;
 	u8 antenna_selection_info;
 } __attribute__ ((packed));
 
+/* 802.11n HT capabilities masks (for cap_info) */
+#define IEEE80211_HT_CAP_LDPC_CODING		0x0001
+#define IEEE80211_HT_CAP_SUP_WIDTH_20_40	0x0002
+#define IEEE80211_HT_CAP_SM_PS			0x000C
+#define IEEE80211_HT_CAP_GRN_FLD		0x0010
+#define IEEE80211_HT_CAP_SGI_20			0x0020
+#define IEEE80211_HT_CAP_SGI_40			0x0040
+#define IEEE80211_HT_CAP_TX_STBC		0x0080
+#define IEEE80211_HT_CAP_RX_STBC		0x0300
+#define IEEE80211_HT_CAP_DELAY_BA		0x0400
+#define IEEE80211_HT_CAP_MAX_AMSDU		0x0800
+#define IEEE80211_HT_CAP_DSSSCCK40		0x1000
+#define IEEE80211_HT_CAP_PSMP_SUPPORT		0x2000
+#define IEEE80211_HT_CAP_40MHZ_INTOLERANT	0x4000
+#define IEEE80211_HT_CAP_LSIG_TXOP_PROT		0x8000
+
+/* 802.11n HT capability AMPDU settings (for ampdu_params_info) */
+#define IEEE80211_HT_AMPDU_PARM_FACTOR		0x03
+#define IEEE80211_HT_AMPDU_PARM_DENSITY		0x1C
+
 /**
- * struct ieee80211_ht_cap - HT additional information
+ * struct ieee80211_ht_info - HT information
  *
- * This structure refers to "HT information element" as
- * described in 802.11n draft section 7.3.2.53
+ * This structure is the "HT information element" as
+ * described in 802.11n D5.0 7.3.2.58
  */
-struct ieee80211_ht_addt_info {
+struct ieee80211_ht_info {
 	u8 control_chan;
 	u8 ht_param;
 	__le16 operation_mode;
@@ -714,36 +784,33 @@ struct ieee80211_ht_addt_info {
 	u8 basic_set[16];
 } __attribute__ ((packed));
 
-/* 802.11n HT capabilities masks */
-#define IEEE80211_HT_CAP_SUP_WIDTH		0x0002
-#define IEEE80211_HT_CAP_SM_PS			0x000C
-#define IEEE80211_HT_CAP_GRN_FLD		0x0010
-#define IEEE80211_HT_CAP_SGI_20			0x0020
-#define IEEE80211_HT_CAP_SGI_40			0x0040
-#define IEEE80211_HT_CAP_DELAY_BA		0x0400
-#define IEEE80211_HT_CAP_MAX_AMSDU		0x0800
-#define IEEE80211_HT_CAP_DSSSCCK40		0x1000
-/* 802.11n HT capability AMPDU settings */
-#define IEEE80211_HT_CAP_AMPDU_FACTOR		0x03
-#define IEEE80211_HT_CAP_AMPDU_DENSITY		0x1C
-/* 802.11n HT capability MSC set */
-#define IEEE80211_SUPP_MCS_SET_UEQM		4
-#define IEEE80211_HT_CAP_MAX_STREAMS		4
-#define IEEE80211_SUPP_MCS_SET_LEN		10
-/* maximum streams the spec allows */
-#define IEEE80211_HT_CAP_MCS_TX_DEFINED		0x01
-#define IEEE80211_HT_CAP_MCS_TX_RX_DIFF		0x02
-#define IEEE80211_HT_CAP_MCS_TX_STREAMS		0x0C
-#define IEEE80211_HT_CAP_MCS_TX_UEQM		0x10
-/* 802.11n HT IE masks */
-#define IEEE80211_HT_IE_CHA_SEC_OFFSET		0x03
-#define IEEE80211_HT_IE_CHA_SEC_NONE	 	0x00
-#define IEEE80211_HT_IE_CHA_SEC_ABOVE 		0x01
-#define IEEE80211_HT_IE_CHA_SEC_BELOW 		0x03
-#define IEEE80211_HT_IE_CHA_WIDTH		0x04
-#define IEEE80211_HT_IE_HT_PROTECTION		0x0003
-#define IEEE80211_HT_IE_NON_GF_STA_PRSNT	0x0004
-#define IEEE80211_HT_IE_NON_HT_STA_PRSNT	0x0010
+/* for ht_param */
+#define IEEE80211_HT_PARAM_CHA_SEC_OFFSET		0x03
+#define		IEEE80211_HT_PARAM_CHA_SEC_NONE		0x00
+#define		IEEE80211_HT_PARAM_CHA_SEC_ABOVE	0x01
+#define		IEEE80211_HT_PARAM_CHA_SEC_BELOW	0x03
+#define IEEE80211_HT_PARAM_CHAN_WIDTH_ANY		0x04
+#define IEEE80211_HT_PARAM_RIFS_MODE			0x08
+#define IEEE80211_HT_PARAM_SPSMP_SUPPORT		0x10
+#define IEEE80211_HT_PARAM_SERV_INTERVAL_GRAN		0xE0
+
+/* for operation_mode */
+#define IEEE80211_HT_OP_MODE_PROTECTION			0x0003
+#define		IEEE80211_HT_OP_MODE_PROTECTION_NONE		0
+#define		IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER	1
+#define		IEEE80211_HT_OP_MODE_PROTECTION_20MHZ		2
+#define		IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED	3
+#define IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT		0x0004
+#define IEEE80211_HT_OP_MODE_NON_HT_STA_PRSNT		0x0010
+
+/* for stbc_param */
+#define IEEE80211_HT_STBC_PARAM_DUAL_BEACON		0x0040
+#define IEEE80211_HT_STBC_PARAM_DUAL_CTS_PROT		0x0080
+#define IEEE80211_HT_STBC_PARAM_STBC_BEACON		0x0100
+#define IEEE80211_HT_STBC_PARAM_LSIG_TXOP_FULLPROT	0x0200
+#define IEEE80211_HT_STBC_PARAM_PCO_ACTIVE		0x0400
+#define IEEE80211_HT_STBC_PARAM_PCO_PHASE		0x0800
+
 
 /* block-ack parameters */
 #define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002
@@ -769,7 +836,6 @@ struct ieee80211_ht_addt_info {
 /* Authentication algorithms */
 #define WLAN_AUTH_OPEN 0
 #define WLAN_AUTH_SHARED_KEY 1
-#define WLAN_AUTH_FAST_BSS_TRANSITION 2
 #define WLAN_AUTH_LEAP 128
 
 #define WLAN_AUTH_CHALLENGE_LEN 128
@@ -949,7 +1015,7 @@ enum ieee80211_eid {
 	WLAN_EID_EXT_SUPP_RATES = 50,
 	/* 802.11n */
 	WLAN_EID_HT_CAPABILITY = 45,
-	WLAN_EID_HT_EXTRA_INFO = 61,
+	WLAN_EID_HT_INFORMATION = 61,
 	/* 802.11i */
 	WLAN_EID_RSN = 48,
 	WLAN_EID_WPA = 221,
@@ -976,6 +1042,68 @@ enum ieee80211_spectrum_mgmt_actioncode {
 	WLAN_ACTION_SPCT_CHL_SWITCH = 4,
 };
 
+/*
+ * IEEE 802.11-2007 7.3.2.9 Country information element
+ *
+ * Minimum length is 8 octets, ie len must be evenly
+ * divisible by 2
+ */
+
+/* Although the spec says 8 I'm seeing 6 in practice */
+#define IEEE80211_COUNTRY_IE_MIN_LEN	6
+
+/*
+ * For regulatory extension stuff see IEEE 802.11-2007
+ * Annex I (page 1141) and Annex J (page 1147). Also
+ * review 7.3.2.9.
+ *
+ * When dot11RegulatoryClassesRequired is true and the
+ * first_channel/reg_extension_id is >= 201 then the IE
+ * compromises of the 'ext' struct represented below:
+ *
+ *  - Regulatory extension ID - when generating IE this just needs
+ *    to be monotonically increasing for each triplet passed in
+ *    the IE
+ *  - Regulatory class - index into set of rules
+ *  - Coverage class - index into air propagation time (Table 7-27),
+ *    in microseconds, you can compute the air propagation time from
+ *    the index by multiplying by 3, so index 10 yields a propagation
+ *    of 10 us. Valid values are 0-31, values 32-255 are not defined
+ *    yet. A value of 0 inicates air propagation of <= 1 us.
+ *
+ *  See also Table I.2 for Emission limit sets and table
+ *  I.3 for Behavior limit sets. Table J.1 indicates how to map
+ *  a reg_class to an emission limit set and behavior limit set.
+ */
+#define IEEE80211_COUNTRY_EXTENSION_ID 201
+
+/*
+ *  Channels numbers in the IE must be monotonically increasing
+ *  if dot11RegulatoryClassesRequired is not true.
+ *
+ *  If dot11RegulatoryClassesRequired is true consecutive
+ *  subband triplets following a regulatory triplet shall
+ *  have monotonically increasing first_channel number fields.
+ *
+ *  Channel numbers shall not overlap.
+ *
+ *  Note that max_power is signed.
+ */
+struct ieee80211_country_ie_triplet {
+	union {
+		struct {
+			u8 first_channel;
+			u8 num_channels;
+			s8 max_power;
+		} __attribute__ ((packed)) chans;
+		struct {
+			u8 reg_extension_id;
+			u8 reg_class;
+			u8 coverage_class;
+		} __attribute__ ((packed)) ext;
+	};
+} __attribute__ ((packed));
+
 /* BACK action code */
 enum ieee80211_back_actioncode {
 	WLAN_ACTION_ADDBA_REQ = 0,
@@ -1057,4 +1185,4 @@ static inline u8 *ieee80211_get_DA(struct ieee80211_hdr *hdr)
 		return hdr->addr1;
 }
 
-#endif /* IEEE80211_H */
+#endif /* LINUX_IEEE80211_H */
diff --git a/include/linux/if.h b/include/linux/if.h
index 65246846c844..2a6e29620a96 100644
--- a/include/linux/if.h
+++ b/include/linux/if.h
@@ -65,6 +65,7 @@
 #define IFF_BONDING	0x20		/* bonding master or slave	*/
 #define IFF_SLAVE_NEEDARP 0x40		/* need ARPs for validation	*/
 #define IFF_ISATAP	0x80		/* ISATAP interface (RFC4214)	*/
+#define IFF_MASTER_ARPMON 0x100		/* bonding master, ARP mon in use */
 
 #define IF_GET_IFACE	0x0001		/* for querying only */
 #define IF_GET_PROTO	0x0002
diff --git a/include/linux/if_arp.h b/include/linux/if_arp.h
index 4d3401812e6c..5ff89809a581 100644
--- a/include/linux/if_arp.h
+++ b/include/linux/if_arp.h
@@ -87,6 +87,9 @@
 #define ARPHRD_IEEE80211_PRISM 802	/* IEEE 802.11 + Prism2 header  */
 #define ARPHRD_IEEE80211_RADIOTAP 803	/* IEEE 802.11 + radiotap header */
 
+#define ARPHRD_PHONET	820		/* PhoNet media type		*/
+#define ARPHRD_PHONET_PIPE 821		/* PhoNet pipe header		*/
+
 #define ARPHRD_VOID	  0xFFFF	/* Void type, nothing is known */
 #define ARPHRD_NONE	  0xFFFE	/* zero header length */
 
diff --git a/include/linux/if_vlan.h b/include/linux/if_vlan.h
index 9e7b49b8062d..a5cb0c3f6dcf 100644
--- a/include/linux/if_vlan.h
+++ b/include/linux/if_vlan.h
@@ -114,6 +114,8 @@ extern u16 vlan_dev_vlan_id(const struct net_device *dev);
 
 extern int __vlan_hwaccel_rx(struct sk_buff *skb, struct vlan_group *grp,
 			     u16 vlan_tci, int polling);
+extern int vlan_hwaccel_do_receive(struct sk_buff *skb);
+
 #else
 static inline struct net_device *vlan_dev_real_dev(const struct net_device *dev)
 {
@@ -133,6 +135,11 @@ static inline int __vlan_hwaccel_rx(struct sk_buff *skb, struct vlan_group *grp,
 	BUG();
 	return NET_XMIT_SUCCESS;
 }
+
+static inline int vlan_hwaccel_do_receive(struct sk_buff *skb)
+{
+	return 0;
+}
 #endif
 
 /**
diff --git a/include/linux/in.h b/include/linux/in.h
index db458beef19d..d60122a3a088 100644
--- a/include/linux/in.h
+++ b/include/linux/in.h
@@ -80,6 +80,10 @@ struct in_addr {
 /* BSD compatibility */
 #define IP_RECVRETOPTS	IP_RETOPTS
 
+/* TProxy original addresses */
+#define IP_ORIGDSTADDR       20
+#define IP_RECVORIGDSTADDR   IP_ORIGDSTADDR
+
 /* IP_MTU_DISCOVER values */
 #define IP_PMTUDISC_DONT		0	/* Never send DF frames */
 #define IP_PMTUDISC_WANT		1	/* Use per route hints	*/
diff --git a/include/linux/init.h b/include/linux/init.h
index 93538b696e3d..68cb0265d009 100644
--- a/include/linux/init.h
+++ b/include/linux/init.h
@@ -40,7 +40,7 @@
 
 /* These are for everybody (although not all archs will actually
    discard it in modules) */
-#define __init		__section(.init.text) __cold
+#define __init		__section(.init.text) __cold notrace
 #define __initdata	__section(.init.data)
 #define __initconst	__section(.init.rodata)
 #define __exitdata	__section(.exit.data)
@@ -112,21 +112,25 @@
 #define __FINIT		.previous
 
 #define __INITDATA	.section	".init.data","aw"
+#define __INITRODATA	.section	".init.rodata","a"
 #define __FINITDATA	.previous
 
 #define __DEVINIT        .section	".devinit.text", "ax"
 #define __DEVINITDATA    .section	".devinit.data", "aw"
+#define __DEVINITRODATA  .section	".devinit.rodata", "a"
 
 #define __CPUINIT        .section	".cpuinit.text", "ax"
 #define __CPUINITDATA    .section	".cpuinit.data", "aw"
+#define __CPUINITRODATA  .section	".cpuinit.rodata", "a"
 
 #define __MEMINIT        .section	".meminit.text", "ax"
 #define __MEMINITDATA    .section	".meminit.data", "aw"
+#define __MEMINITRODATA  .section	".meminit.rodata", "a"
 
 /* silence warnings when references are OK */
 #define __REF            .section       ".ref.text", "ax"
 #define __REFDATA        .section       ".ref.data", "aw"
-#define __REFCONST       .section       ".ref.rodata", "aw"
+#define __REFCONST       .section       ".ref.rodata", "a"
 
 #ifndef __ASSEMBLY__
 /*
@@ -233,9 +237,6 @@ struct obs_kernel_param {
 		__attribute__((aligned((sizeof(long)))))	\
 		= { __setup_str_##unique_id, fn, early }
 
-#define __setup_null_param(str, unique_id)			\
-	__setup_param(str, unique_id, NULL, 0)
-
 #define __setup(str, fn)					\
 	__setup_param(str, fn, fn, 0)
 
@@ -296,7 +297,6 @@ void __init parse_early_param(void);
 	void cleanup_module(void) __attribute__((alias(#exitfn)));
 
 #define __setup_param(str, unique_id, fn)	/* nothing */
-#define __setup_null_param(str, unique_id) 	/* nothing */
 #define __setup(str, func) 			/* nothing */
 #endif
 
diff --git a/include/linux/init_task.h b/include/linux/init_task.h
index 021d8e720c79..959f5522d10a 100644
--- a/include/linux/init_task.h
+++ b/include/linux/init_task.h
@@ -57,7 +57,6 @@ extern struct nsproxy init_nsproxy;
 	.mnt_ns		= NULL,						\
 	INIT_NET_NS(net_ns)                                             \
 	INIT_IPC_NS(ipc_ns)						\
-	.user_ns	= &init_user_ns,				\
 }
 
 #define INIT_SIGHAND(sighand) {						\
@@ -113,6 +112,8 @@ extern struct group_info init_groups;
 # define CAP_INIT_BSET  CAP_INIT_EFF_SET
 #endif
 
+extern struct cred init_cred;
+
 /*
  *  INIT_TASK is used to set up the first task table, touch at
  * your own risk!. Base=0, limit=0x1fffff (=2MB)
@@ -147,13 +148,10 @@ extern struct group_info init_groups;
 	.children	= LIST_HEAD_INIT(tsk.children),			\
 	.sibling	= LIST_HEAD_INIT(tsk.sibling),			\
 	.group_leader	= &tsk,						\
-	.group_info	= &init_groups,					\
-	.cap_effective	= CAP_INIT_EFF_SET,				\
-	.cap_inheritable = CAP_INIT_INH_SET,				\
-	.cap_permitted	= CAP_FULL_SET,					\
-	.cap_bset 	= CAP_INIT_BSET,				\
-	.securebits     = SECUREBITS_DEFAULT,				\
-	.user		= INIT_USER,					\
+	.real_cred	= &init_cred,					\
+	.cred		= &init_cred,					\
+	.cred_exec_mutex =						\
+		 __MUTEX_INITIALIZER(tsk.cred_exec_mutex),		\
 	.comm		= "swapper",					\
 	.thread		= INIT_THREAD,					\
 	.fs		= &init_fs,					\
@@ -170,6 +168,7 @@ extern struct group_info init_groups;
 	.cpu_timers	= INIT_CPU_TIMERS(tsk.cpu_timers),		\
 	.fs_excl	= ATOMIC_INIT(0),				\
 	.pi_lock	= __SPIN_LOCK_UNLOCKED(tsk.pi_lock),		\
+	.timer_slack_ns = 50000, /* 50 usec default slack */		\
 	.pids = {							\
 		[PIDTYPE_PID]  = INIT_PID_LINK(PIDTYPE_PID),		\
 		[PIDTYPE_PGID] = INIT_PID_LINK(PIDTYPE_PGID),		\
diff --git a/include/linux/inotify.h b/include/linux/inotify.h
index bd578578a8b9..37ea2894b3c0 100644
--- a/include/linux/inotify.h
+++ b/include/linux/inotify.h
@@ -134,6 +134,8 @@ extern void inotify_remove_watch_locked(struct inotify_handle *,
 					struct inotify_watch *);
 extern void get_inotify_watch(struct inotify_watch *);
 extern void put_inotify_watch(struct inotify_watch *);
+extern int pin_inotify_watch(struct inotify_watch *);
+extern void unpin_inotify_watch(struct inotify_watch *);
 
 #else
 
@@ -228,6 +230,15 @@ static inline void put_inotify_watch(struct inotify_watch *watch)
 {
 }
 
+extern inline int pin_inotify_watch(struct inotify_watch *watch)
+{
+	return 0;
+}
+
+extern inline void unpin_inotify_watch(struct inotify_watch *watch)
+{
+}
+
 #endif	/* CONFIG_INOTIFY */
 
 #endif	/* __KERNEL __ */
diff --git a/include/linux/input.h b/include/linux/input.h
index a5802c9c81a4..9a6355f74db2 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -238,6 +238,7 @@ struct input_absinfo {
 #define KEY_KPEQUAL		117
 #define KEY_KPPLUSMINUS		118
 #define KEY_PAUSE		119
+#define KEY_SCALE		120	/* AL Compiz Scale (Expose) */
 
 #define KEY_KPCOMMA		121
 #define KEY_HANGEUL		122
@@ -322,6 +323,7 @@ struct input_absinfo {
 #define KEY_PAUSECD		201
 #define KEY_PROG3		202
 #define KEY_PROG4		203
+#define KEY_DASHBOARD		204	/* AL Dashboard */
 #define KEY_SUSPEND		205
 #define KEY_CLOSE		206	/* AC Close */
 #define KEY_PLAY		207
@@ -577,9 +579,22 @@ struct input_absinfo {
 #define KEY_BRL_DOT9		0x1f9
 #define KEY_BRL_DOT10		0x1fa
 
+#define KEY_NUMERIC_0		0x200	/* used by phones, remote controls, */
+#define KEY_NUMERIC_1		0x201	/* and other keypads */
+#define KEY_NUMERIC_2		0x202
+#define KEY_NUMERIC_3		0x203
+#define KEY_NUMERIC_4		0x204
+#define KEY_NUMERIC_5		0x205
+#define KEY_NUMERIC_6		0x206
+#define KEY_NUMERIC_7		0x207
+#define KEY_NUMERIC_8		0x208
+#define KEY_NUMERIC_9		0x209
+#define KEY_NUMERIC_STAR	0x20a
+#define KEY_NUMERIC_POUND	0x20b
+
 /* We avoid low common keys in module aliases so they don't get huge. */
 #define KEY_MIN_INTERESTING	KEY_MUTE
-#define KEY_MAX			0x1ff
+#define KEY_MAX			0x2ff
 #define KEY_CNT			(KEY_MAX+1)
 
 /*
@@ -644,6 +659,8 @@ struct input_absinfo {
 #define SW_RADIO		SW_RFKILL_ALL	/* deprecated */
 #define SW_MICROPHONE_INSERT	0x04  /* set = inserted */
 #define SW_DOCK			0x05  /* set = plugged into dock */
+#define SW_LINEOUT_INSERT	0x06  /* set = inserted */
+#define SW_JACK_PHYSICAL_INSERT 0x07  /* set = mechanical switch set */
 #define SW_MAX			0x0f
 #define SW_CNT			(SW_MAX+1)
 
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
new file mode 100644
index 000000000000..3d017cfd245b
--- /dev/null
+++ b/include/linux/intel-iommu.h
@@ -0,0 +1,363 @@
+/*
+ * Copyright (c) 2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * Copyright (C) 2006-2008 Intel Corporation
+ * Author: Ashok Raj <ashok.raj@intel.com>
+ * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
+ */
+
+#ifndef _INTEL_IOMMU_H_
+#define _INTEL_IOMMU_H_
+
+#include <linux/types.h>
+#include <linux/msi.h>
+#include <linux/sysdev.h>
+#include <linux/iova.h>
+#include <linux/io.h>
+#include <linux/dma_remapping.h>
+#include <asm/cacheflush.h>
+#include <asm/iommu.h>
+
+/*
+ * Intel IOMMU register specification per version 1.0 public spec.
+ */
+
+#define	DMAR_VER_REG	0x0	/* Arch version supported by this IOMMU */
+#define	DMAR_CAP_REG	0x8	/* Hardware supported capabilities */
+#define	DMAR_ECAP_REG	0x10	/* Extended capabilities supported */
+#define	DMAR_GCMD_REG	0x18	/* Global command register */
+#define	DMAR_GSTS_REG	0x1c	/* Global status register */
+#define	DMAR_RTADDR_REG	0x20	/* Root entry table */
+#define	DMAR_CCMD_REG	0x28	/* Context command reg */
+#define	DMAR_FSTS_REG	0x34	/* Fault Status register */
+#define	DMAR_FECTL_REG	0x38	/* Fault control register */
+#define	DMAR_FEDATA_REG	0x3c	/* Fault event interrupt data register */
+#define	DMAR_FEADDR_REG	0x40	/* Fault event interrupt addr register */
+#define	DMAR_FEUADDR_REG 0x44	/* Upper address register */
+#define	DMAR_AFLOG_REG	0x58	/* Advanced Fault control */
+#define	DMAR_PMEN_REG	0x64	/* Enable Protected Memory Region */
+#define	DMAR_PLMBASE_REG 0x68	/* PMRR Low addr */
+#define	DMAR_PLMLIMIT_REG 0x6c	/* PMRR low limit */
+#define	DMAR_PHMBASE_REG 0x70	/* pmrr high base addr */
+#define	DMAR_PHMLIMIT_REG 0x78	/* pmrr high limit */
+#define DMAR_IQH_REG	0x80	/* Invalidation queue head register */
+#define DMAR_IQT_REG	0x88	/* Invalidation queue tail register */
+#define DMAR_IQA_REG	0x90	/* Invalidation queue addr register */
+#define DMAR_ICS_REG	0x98	/* Invalidation complete status register */
+#define DMAR_IRTA_REG	0xb8    /* Interrupt remapping table addr register */
+
+#define OFFSET_STRIDE		(9)
+/*
+#define dmar_readl(dmar, reg) readl(dmar + reg)
+#define dmar_readq(dmar, reg) ({ \
+		u32 lo, hi; \
+		lo = readl(dmar + reg); \
+		hi = readl(dmar + reg + 4); \
+		(((u64) hi) << 32) + lo; })
+*/
+static inline u64 dmar_readq(void __iomem *addr)
+{
+	u32 lo, hi;
+	lo = readl(addr);
+	hi = readl(addr + 4);
+	return (((u64) hi) << 32) + lo;
+}
+
+static inline void dmar_writeq(void __iomem *addr, u64 val)
+{
+	writel((u32)val, addr);
+	writel((u32)(val >> 32), addr + 4);
+}
+
+#define DMAR_VER_MAJOR(v)		(((v) & 0xf0) >> 4)
+#define DMAR_VER_MINOR(v)		((v) & 0x0f)
+
+/*
+ * Decoding Capability Register
+ */
+#define cap_read_drain(c)	(((c) >> 55) & 1)
+#define cap_write_drain(c)	(((c) >> 54) & 1)
+#define cap_max_amask_val(c)	(((c) >> 48) & 0x3f)
+#define cap_num_fault_regs(c)	((((c) >> 40) & 0xff) + 1)
+#define cap_pgsel_inv(c)	(((c) >> 39) & 1)
+
+#define cap_super_page_val(c)	(((c) >> 34) & 0xf)
+#define cap_super_offset(c)	(((find_first_bit(&cap_super_page_val(c), 4)) \
+					* OFFSET_STRIDE) + 21)
+
+#define cap_fault_reg_offset(c)	((((c) >> 24) & 0x3ff) * 16)
+#define cap_max_fault_reg_offset(c) \
+	(cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
+
+#define cap_zlr(c)		(((c) >> 22) & 1)
+#define cap_isoch(c)		(((c) >> 23) & 1)
+#define cap_mgaw(c)		((((c) >> 16) & 0x3f) + 1)
+#define cap_sagaw(c)		(((c) >> 8) & 0x1f)
+#define cap_caching_mode(c)	(((c) >> 7) & 1)
+#define cap_phmr(c)		(((c) >> 6) & 1)
+#define cap_plmr(c)		(((c) >> 5) & 1)
+#define cap_rwbf(c)		(((c) >> 4) & 1)
+#define cap_afl(c)		(((c) >> 3) & 1)
+#define cap_ndoms(c)		(((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
+/*
+ * Extended Capability Register
+ */
+
+#define ecap_niotlb_iunits(e)	((((e) >> 24) & 0xff) + 1)
+#define ecap_iotlb_offset(e) 	((((e) >> 8) & 0x3ff) * 16)
+#define ecap_max_iotlb_offset(e) \
+	(ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16)
+#define ecap_coherent(e)	((e) & 0x1)
+#define ecap_qis(e)		((e) & 0x2)
+#define ecap_eim_support(e)	((e >> 4) & 0x1)
+#define ecap_ir_support(e)	((e >> 3) & 0x1)
+#define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
+
+
+/* IOTLB_REG */
+#define DMA_TLB_FLUSH_GRANU_OFFSET  60
+#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
+#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
+#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
+#define DMA_TLB_IIRG(type) ((type >> 60) & 7)
+#define DMA_TLB_IAIG(val) (((val) >> 57) & 7)
+#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
+#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
+#define DMA_TLB_DID(id)	(((u64)((id) & 0xffff)) << 32)
+#define DMA_TLB_IVT (((u64)1) << 63)
+#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
+#define DMA_TLB_MAX_SIZE (0x3f)
+
+/* INVALID_DESC */
+#define DMA_CCMD_INVL_GRANU_OFFSET  61
+#define DMA_ID_TLB_GLOBAL_FLUSH	(((u64)1) << 3)
+#define DMA_ID_TLB_DSI_FLUSH	(((u64)2) << 3)
+#define DMA_ID_TLB_PSI_FLUSH	(((u64)3) << 3)
+#define DMA_ID_TLB_READ_DRAIN	(((u64)1) << 7)
+#define DMA_ID_TLB_WRITE_DRAIN	(((u64)1) << 6)
+#define DMA_ID_TLB_DID(id)	(((u64)((id & 0xffff) << 16)))
+#define DMA_ID_TLB_IH_NONLEAF	(((u64)1) << 6)
+#define DMA_ID_TLB_ADDR(addr)	(addr)
+#define DMA_ID_TLB_ADDR_MASK(mask)	(mask)
+
+/* PMEN_REG */
+#define DMA_PMEN_EPM (((u32)1)<<31)
+#define DMA_PMEN_PRS (((u32)1)<<0)
+
+/* GCMD_REG */
+#define DMA_GCMD_TE (((u32)1) << 31)
+#define DMA_GCMD_SRTP (((u32)1) << 30)
+#define DMA_GCMD_SFL (((u32)1) << 29)
+#define DMA_GCMD_EAFL (((u32)1) << 28)
+#define DMA_GCMD_WBF (((u32)1) << 27)
+#define DMA_GCMD_QIE (((u32)1) << 26)
+#define DMA_GCMD_SIRTP (((u32)1) << 24)
+#define DMA_GCMD_IRE (((u32) 1) << 25)
+
+/* GSTS_REG */
+#define DMA_GSTS_TES (((u32)1) << 31)
+#define DMA_GSTS_RTPS (((u32)1) << 30)
+#define DMA_GSTS_FLS (((u32)1) << 29)
+#define DMA_GSTS_AFLS (((u32)1) << 28)
+#define DMA_GSTS_WBFS (((u32)1) << 27)
+#define DMA_GSTS_QIES (((u32)1) << 26)
+#define DMA_GSTS_IRTPS (((u32)1) << 24)
+#define DMA_GSTS_IRES (((u32)1) << 25)
+
+/* CCMD_REG */
+#define DMA_CCMD_ICC (((u64)1) << 63)
+#define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
+#define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
+#define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
+#define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
+#define DMA_CCMD_MASK_NOBIT 0
+#define DMA_CCMD_MASK_1BIT 1
+#define DMA_CCMD_MASK_2BIT 2
+#define DMA_CCMD_MASK_3BIT 3
+#define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
+#define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
+
+/* FECTL_REG */
+#define DMA_FECTL_IM (((u32)1) << 31)
+
+/* FSTS_REG */
+#define DMA_FSTS_PPF ((u32)2)
+#define DMA_FSTS_PFO ((u32)1)
+#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
+
+/* FRCD_REG, 32 bits access */
+#define DMA_FRCD_F (((u32)1) << 31)
+#define dma_frcd_type(d) ((d >> 30) & 1)
+#define dma_frcd_fault_reason(c) (c & 0xff)
+#define dma_frcd_source_id(c) (c & 0xffff)
+/* low 64 bit */
+#define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
+
+#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts)			\
+do {									\
+	cycles_t start_time = get_cycles();				\
+	while (1) {							\
+		sts = op(iommu->reg + offset);				\
+		if (cond)						\
+			break;						\
+		if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
+			panic("DMAR hardware is malfunctioning\n");	\
+		cpu_relax();						\
+	}								\
+} while (0)
+
+#define QI_LENGTH	256	/* queue length */
+
+enum {
+	QI_FREE,
+	QI_IN_USE,
+	QI_DONE
+};
+
+#define QI_CC_TYPE		0x1
+#define QI_IOTLB_TYPE		0x2
+#define QI_DIOTLB_TYPE		0x3
+#define QI_IEC_TYPE		0x4
+#define QI_IWD_TYPE		0x5
+
+#define QI_IEC_SELECTIVE	(((u64)1) << 4)
+#define QI_IEC_IIDEX(idx)	(((u64)(idx & 0xffff) << 32))
+#define QI_IEC_IM(m)		(((u64)(m & 0x1f) << 27))
+
+#define QI_IWD_STATUS_DATA(d)	(((u64)d) << 32)
+#define QI_IWD_STATUS_WRITE	(((u64)1) << 5)
+
+#define QI_IOTLB_DID(did) 	(((u64)did) << 16)
+#define QI_IOTLB_DR(dr) 	(((u64)dr) << 7)
+#define QI_IOTLB_DW(dw) 	(((u64)dw) << 6)
+#define QI_IOTLB_GRAN(gran) 	(((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
+#define QI_IOTLB_ADDR(addr)	(((u64)addr) & VTD_PAGE_MASK)
+#define QI_IOTLB_IH(ih)		(((u64)ih) << 6)
+#define QI_IOTLB_AM(am)		(((u8)am))
+
+#define QI_CC_FM(fm)		(((u64)fm) << 48)
+#define QI_CC_SID(sid)		(((u64)sid) << 32)
+#define QI_CC_DID(did)		(((u64)did) << 16)
+#define QI_CC_GRAN(gran)	(((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
+
+struct qi_desc {
+	u64 low, high;
+};
+
+struct q_inval {
+	spinlock_t      q_lock;
+	struct qi_desc  *desc;          /* invalidation queue */
+	int             *desc_status;   /* desc status */
+	int             free_head;      /* first free entry */
+	int             free_tail;      /* last free entry */
+	int             free_cnt;
+};
+
+#ifdef CONFIG_INTR_REMAP
+/* 1MB - maximum possible interrupt remapping table size */
+#define INTR_REMAP_PAGE_ORDER	8
+#define INTR_REMAP_TABLE_REG_SIZE	0xf
+
+#define INTR_REMAP_TABLE_ENTRIES	65536
+
+struct ir_table {
+	struct irte *base;
+};
+#endif
+
+struct iommu_flush {
+	int (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
+		u64 type, int non_present_entry_flush);
+	int (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
+		unsigned int size_order, u64 type, int non_present_entry_flush);
+};
+
+struct intel_iommu {
+	void __iomem	*reg; /* Pointer to hardware regs, virtual addr */
+	u64		cap;
+	u64		ecap;
+	int		seg;
+	u32		gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
+	spinlock_t	register_lock; /* protect register handling */
+	int		seq_id;	/* sequence id of the iommu */
+
+#ifdef CONFIG_DMAR
+	unsigned long 	*domain_ids; /* bitmap of domains */
+	struct dmar_domain **domains; /* ptr to domains */
+	spinlock_t	lock; /* protect context, domain ids */
+	struct root_entry *root_entry; /* virtual address */
+
+	unsigned int irq;
+	unsigned char name[7];    /* Device Name */
+	struct msi_msg saved_msg;
+	struct sys_device sysdev;
+	struct iommu_flush flush;
+#endif
+	struct q_inval  *qi;            /* Queued invalidation info */
+#ifdef CONFIG_INTR_REMAP
+	struct ir_table *ir_table;	/* Interrupt remapping info */
+#endif
+};
+
+static inline void __iommu_flush_cache(
+	struct intel_iommu *iommu, void *addr, int size)
+{
+	if (!ecap_coherent(iommu->ecap))
+		clflush_cache_range(addr, size);
+}
+
+extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
+
+extern int alloc_iommu(struct dmar_drhd_unit *drhd);
+extern void free_iommu(struct intel_iommu *iommu);
+extern int dmar_enable_qi(struct intel_iommu *iommu);
+extern void qi_global_iec(struct intel_iommu *iommu);
+
+extern int qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
+			        u8 fm, u64 type, int non_present_entry_flush);
+extern int qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
+			  unsigned int size_order, u64 type,
+			  int non_present_entry_flush);
+
+extern void qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
+
+void intel_iommu_domain_exit(struct dmar_domain *domain);
+struct dmar_domain *intel_iommu_domain_alloc(struct pci_dev *pdev);
+int intel_iommu_context_mapping(struct dmar_domain *domain,
+				struct pci_dev *pdev);
+int intel_iommu_page_mapping(struct dmar_domain *domain, dma_addr_t iova,
+			     u64 hpa, size_t size, int prot);
+void intel_iommu_detach_dev(struct dmar_domain *domain, u8 bus, u8 devfn);
+struct dmar_domain *intel_iommu_find_domain(struct pci_dev *pdev);
+u64 intel_iommu_iova_to_pfn(struct dmar_domain *domain, u64 iova);
+
+#ifdef CONFIG_DMAR
+int intel_iommu_found(void);
+#else /* CONFIG_DMAR */
+static inline int intel_iommu_found(void)
+{
+	return 0;
+}
+#endif /* CONFIG_DMAR */
+
+extern void *intel_alloc_coherent(struct device *, size_t, dma_addr_t *, gfp_t);
+extern void intel_free_coherent(struct device *, size_t, void *, dma_addr_t);
+extern dma_addr_t intel_map_single(struct device *, phys_addr_t, size_t, int);
+extern void intel_unmap_single(struct device *, dma_addr_t, size_t, int);
+extern int intel_map_sg(struct device *, struct scatterlist *, int, int);
+extern void intel_unmap_sg(struct device *, struct scatterlist *, int, int);
+
+#endif
diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h
index 58ff4e74b2f3..be3c484b5242 100644
--- a/include/linux/interrupt.h
+++ b/include/linux/interrupt.h
@@ -8,9 +8,14 @@
 #include <linux/preempt.h>
 #include <linux/cpumask.h>
 #include <linux/irqreturn.h>
+#include <linux/irqnr.h>
 #include <linux/hardirq.h>
 #include <linux/sched.h>
 #include <linux/irqflags.h>
+#include <linux/smp.h>
+#include <linux/percpu.h>
+#include <linux/irqnr.h>
+
 #include <asm/atomic.h>
 #include <asm/ptrace.h>
 #include <asm/system.h>
@@ -248,10 +253,9 @@ enum
 	BLOCK_SOFTIRQ,
 	TASKLET_SOFTIRQ,
 	SCHED_SOFTIRQ,
-#ifdef CONFIG_HIGH_RES_TIMERS
-	HRTIMER_SOFTIRQ,
-#endif
 	RCU_SOFTIRQ, 	/* Preferable RCU should always be the last softirq */
+
+	NR_SOFTIRQS
 };
 
 /* softirq mask and active fields moved to irq_cpustat_t in
@@ -271,6 +275,25 @@ extern void softirq_init(void);
 extern void raise_softirq_irqoff(unsigned int nr);
 extern void raise_softirq(unsigned int nr);
 
+/* This is the worklist that queues up per-cpu softirq work.
+ *
+ * send_remote_sendirq() adds work to these lists, and
+ * the softirq handler itself dequeues from them.  The queues
+ * are protected by disabling local cpu interrupts and they must
+ * only be accessed by the local cpu that they are for.
+ */
+DECLARE_PER_CPU(struct list_head [NR_SOFTIRQS], softirq_work_list);
+
+/* Try to send a softirq to a remote cpu.  If this cannot be done, the
+ * work will be queued to the local cpu.
+ */
+extern void send_remote_softirq(struct call_single_data *cp, int cpu, int softirq);
+
+/* Like send_remote_softirq(), but the caller must disable local cpu interrupts
+ * and compute the current cpu, passed in as 'this_cpu'.
+ */
+extern void __send_remote_softirq(struct call_single_data *cp, int cpu,
+				  int this_cpu, int softirq);
 
 /* Tasklets --- multithreaded analogue of BHs.
 
diff --git a/include/linux/io-mapping.h b/include/linux/io-mapping.h
new file mode 100644
index 000000000000..82df31726a54
--- /dev/null
+++ b/include/linux/io-mapping.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright © 2008 Keith Packard <keithp@keithp.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#ifndef _LINUX_IO_MAPPING_H
+#define _LINUX_IO_MAPPING_H
+
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/page.h>
+#include <asm/iomap.h>
+
+/*
+ * The io_mapping mechanism provides an abstraction for mapping
+ * individual pages from an io device to the CPU in an efficient fashion.
+ *
+ * See Documentation/io_mapping.txt
+ */
+
+/* this struct isn't actually defined anywhere */
+struct io_mapping;
+
+#ifdef CONFIG_HAVE_ATOMIC_IOMAP
+
+/*
+ * For small address space machines, mapping large objects
+ * into the kernel virtual space isn't practical. Where
+ * available, use fixmap support to dynamically map pages
+ * of the object at run time.
+ */
+
+static inline struct io_mapping *
+io_mapping_create_wc(unsigned long base, unsigned long size)
+{
+	return (struct io_mapping *) base;
+}
+
+static inline void
+io_mapping_free(struct io_mapping *mapping)
+{
+}
+
+/* Atomic map/unmap */
+static inline void *
+io_mapping_map_atomic_wc(struct io_mapping *mapping, unsigned long offset)
+{
+	offset += (unsigned long) mapping;
+	return iomap_atomic_prot_pfn(offset >> PAGE_SHIFT, KM_USER0,
+				     __pgprot(__PAGE_KERNEL_WC));
+}
+
+static inline void
+io_mapping_unmap_atomic(void *vaddr)
+{
+	iounmap_atomic(vaddr, KM_USER0);
+}
+
+static inline void *
+io_mapping_map_wc(struct io_mapping *mapping, unsigned long offset)
+{
+	offset += (unsigned long) mapping;
+	return ioremap_wc(offset, PAGE_SIZE);
+}
+
+static inline void
+io_mapping_unmap(void *vaddr)
+{
+	iounmap(vaddr);
+}
+
+#else
+
+/* Create the io_mapping object*/
+static inline struct io_mapping *
+io_mapping_create_wc(unsigned long base, unsigned long size)
+{
+	return (struct io_mapping *) ioremap_wc(base, size);
+}
+
+static inline void
+io_mapping_free(struct io_mapping *mapping)
+{
+	iounmap(mapping);
+}
+
+/* Atomic map/unmap */
+static inline void *
+io_mapping_map_atomic_wc(struct io_mapping *mapping, unsigned long offset)
+{
+	return ((char *) mapping) + offset;
+}
+
+static inline void
+io_mapping_unmap_atomic(void *vaddr)
+{
+}
+
+/* Non-atomic map/unmap */
+static inline void *
+io_mapping_map_wc(struct io_mapping *mapping, unsigned long offset)
+{
+	return ((char *) mapping) + offset;
+}
+
+static inline void
+io_mapping_unmap(void *vaddr)
+{
+}
+
+#endif /* HAVE_ATOMIC_IOMAP */
+
+#endif /* _LINUX_IO_MAPPING_H */
diff --git a/include/linux/iommu-helper.h b/include/linux/iommu-helper.h
index a6d0586e2bf7..3b068e5b5671 100644
--- a/include/linux/iommu-helper.h
+++ b/include/linux/iommu-helper.h
@@ -23,4 +23,7 @@ extern unsigned long iommu_area_alloc(unsigned long *map, unsigned long size,
 extern void iommu_area_free(unsigned long *map, unsigned long start,
 			    unsigned int nr);
 
+extern unsigned long iommu_num_pages(unsigned long addr, unsigned long len,
+				     unsigned long io_page_size);
+
 #endif
diff --git a/include/linux/ioport.h b/include/linux/ioport.h
index ee9bcc6f32b6..041e95aac2bf 100644
--- a/include/linux/ioport.h
+++ b/include/linux/ioport.h
@@ -34,7 +34,8 @@ struct resource_list {
  */
 #define IORESOURCE_BITS		0x000000ff	/* Bus-specific bits */
 
-#define IORESOURCE_IO		0x00000100	/* Resource type */
+#define IORESOURCE_TYPE_BITS	0x00000f00	/* Resource type */
+#define IORESOURCE_IO		0x00000100
 #define IORESOURCE_MEM		0x00000200
 #define IORESOURCE_IRQ		0x00000400
 #define IORESOURCE_DMA		0x00000800
@@ -126,6 +127,10 @@ static inline resource_size_t resource_size(struct resource *res)
 {
 	return res->end - res->start + 1;
 }
+static inline unsigned long resource_type(struct resource *res)
+{
+	return res->flags & IORESOURCE_TYPE_BITS;
+}
 
 /* Convenience shorthand with allocation */
 #define request_region(start,n,name)	__request_region(&ioport_resource, (start), (n), (name))
@@ -169,6 +174,7 @@ extern struct resource * __devm_request_region(struct device *dev,
 
 extern void __devm_release_region(struct device *dev, struct resource *parent,
 				  resource_size_t start, resource_size_t n);
+extern int iomem_map_sanity_check(resource_size_t addr, unsigned long size);
 
 #endif /* __ASSEMBLY__ */
 #endif	/* _LINUX_IOPORT_H */
diff --git a/include/linux/iova.h b/include/linux/iova.h
new file mode 100644
index 000000000000..228f6c94b69c
--- /dev/null
+++ b/include/linux/iova.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2006, Intel Corporation.
+ *
+ * This file is released under the GPLv2.
+ *
+ * Copyright (C) 2006-2008 Intel Corporation
+ * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
+ *
+ */
+
+#ifndef _IOVA_H_
+#define _IOVA_H_
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/rbtree.h>
+#include <linux/dma-mapping.h>
+
+/* IO virtual address start page frame number */
+#define IOVA_START_PFN		(1)
+
+/* iova structure */
+struct iova {
+	struct rb_node	node;
+	unsigned long	pfn_hi; /* IOMMU dish out addr hi */
+	unsigned long	pfn_lo; /* IOMMU dish out addr lo */
+};
+
+/* holds all the iova translations for a domain */
+struct iova_domain {
+	spinlock_t	iova_alloc_lock;/* Lock to protect iova  allocation */
+	spinlock_t	iova_rbtree_lock; /* Lock to protect update of rbtree */
+	struct rb_root	rbroot;		/* iova domain rbtree root */
+	struct rb_node	*cached32_node; /* Save last alloced node */
+	unsigned long	dma_32bit_pfn;
+};
+
+struct iova *alloc_iova_mem(void);
+void free_iova_mem(struct iova *iova);
+void free_iova(struct iova_domain *iovad, unsigned long pfn);
+void __free_iova(struct iova_domain *iovad, struct iova *iova);
+struct iova *alloc_iova(struct iova_domain *iovad, unsigned long size,
+	unsigned long limit_pfn,
+	bool size_aligned);
+struct iova *reserve_iova(struct iova_domain *iovad, unsigned long pfn_lo,
+	unsigned long pfn_hi);
+void copy_reserved_iova(struct iova_domain *from, struct iova_domain *to);
+void init_iova_domain(struct iova_domain *iovad, unsigned long pfn_32bit);
+struct iova *find_iova(struct iova_domain *iovad, unsigned long pfn);
+void put_iova_domain(struct iova_domain *iovad);
+
+#endif
diff --git a/include/linux/ipv6.h b/include/linux/ipv6.h
index 641e026eee8f..0b816cae533e 100644
--- a/include/linux/ipv6.h
+++ b/include/linux/ipv6.h
@@ -278,6 +278,7 @@ struct ipv6_pinfo {
 	struct in6_addr 	saddr;
 	struct in6_addr 	rcv_saddr;
 	struct in6_addr		daddr;
+	struct in6_pktinfo	sticky_pktinfo;
 	struct in6_addr		*daddr_cache;
 #ifdef CONFIG_IPV6_SUBTREES
 	struct in6_addr		*saddr_cache;
diff --git a/include/linux/irq.h b/include/linux/irq.h
index 8d9411bc60f6..98564dc64476 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -18,6 +18,7 @@
 #include <linux/spinlock.h>
 #include <linux/cpumask.h>
 #include <linux/irqreturn.h>
+#include <linux/irqnr.h>
 #include <linux/errno.h>
 
 #include <asm/irq.h>
@@ -62,7 +63,8 @@ typedef	void (*irq_flow_handler_t)(unsigned int irq,
 #define IRQ_MOVE_PENDING	0x00200000	/* need to re-target IRQ destination */
 #define IRQ_NO_BALANCING	0x00400000	/* IRQ is excluded from balancing */
 #define IRQ_SPURIOUS_DISABLED	0x00800000	/* IRQ was disabled by the spurious trap */
-#define IRQ_MOVE_PCNTXT	0x01000000	/* IRQ migration from process context */
+#define IRQ_MOVE_PCNTXT		0x01000000	/* IRQ migration from process context */
+#define IRQ_AFFINITY_SET	0x02000000	/* IRQ affinity was set from userspace*/
 
 #ifdef CONFIG_IRQ_PER_CPU
 # define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
@@ -127,9 +129,14 @@ struct irq_chip {
 	const char	*typename;
 };
 
+struct timer_rand_state;
+struct irq_2_iommu;
 /**
  * struct irq_desc - interrupt descriptor
- *
+ * @irq:		interrupt number for this descriptor
+ * @timer_rand_state:	pointer to timer rand state struct
+ * @kstat_irqs:		irq stats per cpu
+ * @irq_2_iommu:	iommu with this irq
  * @handle_irq:		highlevel irq-events handler [if NULL, __do_IRQ()]
  * @chip:		low level interrupt hardware access
  * @msi_desc:		MSI descriptor
@@ -141,17 +148,24 @@ struct irq_chip {
  * @depth:		disable-depth, for nested irq_disable() calls
  * @wake_depth:		enable depth, for multiple set_irq_wake() callers
  * @irq_count:		stats field to detect stalled irqs
- * @irqs_unhandled:	stats field for spurious unhandled interrupts
  * @last_unhandled:	aging timer for unhandled count
+ * @irqs_unhandled:	stats field for spurious unhandled interrupts
  * @lock:		locking for SMP
  * @affinity:		IRQ affinity on SMP
  * @cpu:		cpu index useful for balancing
  * @pending_mask:	pending rebalanced interrupts
  * @dir:		/proc/irq/ procfs entry
- * @affinity_entry:	/proc/irq/smp_affinity procfs entry on SMP
  * @name:		flow handler name for /proc/interrupts output
  */
 struct irq_desc {
+	unsigned int		irq;
+#ifdef CONFIG_SPARSE_IRQ
+	struct timer_rand_state *timer_rand_state;
+	unsigned int            *kstat_irqs;
+# ifdef CONFIG_INTR_REMAP
+	struct irq_2_iommu      *irq_2_iommu;
+# endif
+#endif
 	irq_flow_handler_t	handle_irq;
 	struct irq_chip		*chip;
 	struct msi_desc		*msi_desc;
@@ -163,14 +177,14 @@ struct irq_desc {
 	unsigned int		depth;		/* nested irq disables */
 	unsigned int		wake_depth;	/* nested wake enables */
 	unsigned int		irq_count;	/* For detecting broken IRQs */
-	unsigned int		irqs_unhandled;
 	unsigned long		last_unhandled;	/* Aging timer for unhandled count */
+	unsigned int		irqs_unhandled;
 	spinlock_t		lock;
 #ifdef CONFIG_SMP
 	cpumask_t		affinity;
 	unsigned int		cpu;
 #endif
-#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
+#ifdef CONFIG_GENERIC_PENDING_IRQ
 	cpumask_t		pending_mask;
 #endif
 #ifdef CONFIG_PROC_FS
@@ -179,8 +193,53 @@ struct irq_desc {
 	const char		*name;
 } ____cacheline_internodealigned_in_smp;
 
+extern void early_irq_init(void);
+extern void arch_early_irq_init(void);
+extern void arch_init_chip_data(struct irq_desc *desc, int cpu);
+extern void arch_init_copy_chip_data(struct irq_desc *old_desc,
+					struct irq_desc *desc, int cpu);
+extern void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc);
+
+#ifndef CONFIG_SPARSE_IRQ
 extern struct irq_desc irq_desc[NR_IRQS];
 
+static inline struct irq_desc *irq_to_desc(unsigned int irq)
+{
+	return (irq < NR_IRQS) ? irq_desc + irq : NULL;
+}
+static inline struct irq_desc *irq_to_desc_alloc_cpu(unsigned int irq, int cpu)
+{
+	return irq_to_desc(irq);
+}
+
+#else
+
+extern struct irq_desc *irq_to_desc(unsigned int irq);
+extern struct irq_desc *irq_to_desc_alloc_cpu(unsigned int irq, int cpu);
+extern struct irq_desc *move_irq_desc(struct irq_desc *old_desc, int cpu);
+
+# define for_each_irq_desc(irq, desc)		\
+	for (irq = 0, desc = irq_to_desc(irq); irq < nr_irqs; irq++, desc = irq_to_desc(irq))
+# define for_each_irq_desc_reverse(irq, desc)                          \
+	for (irq = nr_irqs - 1, desc = irq_to_desc(irq); irq >= 0; irq--, desc = irq_to_desc(irq))
+
+#define kstat_irqs_this_cpu(DESC) \
+	((DESC)->kstat_irqs[smp_processor_id()])
+#define kstat_incr_irqs_this_cpu(irqno, DESC) \
+	((DESC)->kstat_irqs[smp_processor_id()]++)
+
+#endif
+
+static inline struct irq_desc *
+irq_remap_to_desc(unsigned int irq, struct irq_desc *desc)
+{
+#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
+	return irq_to_desc(irq);
+#else
+	return desc;
+#endif
+}
+
 /*
  * Migration helpers for obsolete names, they will go away:
  */
@@ -198,19 +257,14 @@ extern int setup_irq(unsigned int irq, struct irqaction *new);
 
 #ifdef CONFIG_GENERIC_HARDIRQS
 
-#ifndef handle_dynamic_tick
-# define handle_dynamic_tick(a)		do { } while (0)
-#endif
-
 #ifdef CONFIG_SMP
 
-#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
+#ifdef CONFIG_GENERIC_PENDING_IRQ
 
-void set_pending_irq(unsigned int irq, cpumask_t mask);
 void move_native_irq(int irq);
 void move_masked_irq(int irq);
 
-#else /* CONFIG_GENERIC_PENDING_IRQ || CONFIG_IRQBALANCE */
+#else /* CONFIG_GENERIC_PENDING_IRQ */
 
 static inline void move_irq(int irq)
 {
@@ -224,10 +278,6 @@ static inline void move_masked_irq(int irq)
 {
 }
 
-static inline void set_pending_irq(unsigned int irq, cpumask_t mask)
-{
-}
-
 #endif /* CONFIG_GENERIC_PENDING_IRQ */
 
 #else /* CONFIG_SMP */
@@ -237,19 +287,14 @@ static inline void set_pending_irq(unsigned int irq, cpumask_t mask)
 
 #endif /* CONFIG_SMP */
 
-#ifdef CONFIG_IRQBALANCE
-extern void set_balance_irq_affinity(unsigned int irq, cpumask_t mask);
-#else
-static inline void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
-{
-}
-#endif
-
 extern int no_irq_affinity;
 
 static inline int irq_balancing_disabled(unsigned int irq)
 {
-	return irq_desc[irq].status & IRQ_NO_BALANCING_MASK;
+	struct irq_desc *desc;
+
+	desc = irq_to_desc(irq);
+	return desc->status & IRQ_NO_BALANCING_MASK;
 }
 
 /* Handle irq action chains: */
@@ -279,10 +324,8 @@ extern unsigned int __do_IRQ(unsigned int irq);
  * irqchip-style controller then we call the ->handle_irq() handler,
  * and it calls __do_IRQ() if it's attached to an irqtype-style controller.
  */
-static inline void generic_handle_irq(unsigned int irq)
+static inline void generic_handle_irq_desc(unsigned int irq, struct irq_desc *desc)
 {
-	struct irq_desc *desc = irq_desc + irq;
-
 #ifdef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
 	desc->handle_irq(irq, desc);
 #else
@@ -293,6 +336,11 @@ static inline void generic_handle_irq(unsigned int irq)
 #endif
 }
 
+static inline void generic_handle_irq(unsigned int irq)
+{
+	generic_handle_irq_desc(irq, irq_to_desc(irq));
+}
+
 /* Handling of unhandled and spurious interrupts: */
 extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
 			   int action_ret);
@@ -325,7 +373,10 @@ __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
 static inline void __set_irq_handler_unlocked(int irq,
 					      irq_flow_handler_t handler)
 {
-	irq_desc[irq].handle_irq = handler;
+	struct irq_desc *desc;
+
+	desc = irq_to_desc(irq);
+	desc->handle_irq = handler;
 }
 
 /*
@@ -353,13 +404,14 @@ extern void set_irq_noprobe(unsigned int irq);
 extern void set_irq_probe(unsigned int irq);
 
 /* Handle dynamic irq creation and destruction */
+extern unsigned int create_irq_nr(unsigned int irq_want);
 extern int create_irq(void);
 extern void destroy_irq(unsigned int irq);
 
 /* Test to see if a driver has successfully requested an irq */
 static inline int irq_has_action(unsigned int irq)
 {
-	struct irq_desc *desc = irq_desc + irq;
+	struct irq_desc *desc = irq_to_desc(irq);
 	return desc->action != NULL;
 }
 
@@ -374,10 +426,15 @@ extern int set_irq_chip_data(unsigned int irq, void *data);
 extern int set_irq_type(unsigned int irq, unsigned int type);
 extern int set_irq_msi(unsigned int irq, struct msi_desc *entry);
 
-#define get_irq_chip(irq)	(irq_desc[irq].chip)
-#define get_irq_chip_data(irq)	(irq_desc[irq].chip_data)
-#define get_irq_data(irq)	(irq_desc[irq].handler_data)
-#define get_irq_msi(irq)	(irq_desc[irq].msi_desc)
+#define get_irq_chip(irq)	(irq_to_desc(irq)->chip)
+#define get_irq_chip_data(irq)	(irq_to_desc(irq)->chip_data)
+#define get_irq_data(irq)	(irq_to_desc(irq)->handler_data)
+#define get_irq_msi(irq)	(irq_to_desc(irq)->msi_desc)
+
+#define get_irq_desc_chip(desc)		((desc)->chip)
+#define get_irq_desc_chip_data(desc)	((desc)->chip_data)
+#define get_irq_desc_data(desc)		((desc)->handler_data)
+#define get_irq_desc_msi(desc)		((desc)->msi_desc)
 
 #endif /* CONFIG_GENERIC_HARDIRQS */
 
diff --git a/include/linux/irqnr.h b/include/linux/irqnr.h
new file mode 100644
index 000000000000..95d2b74641f5
--- /dev/null
+++ b/include/linux/irqnr.h
@@ -0,0 +1,38 @@
+#ifndef _LINUX_IRQNR_H
+#define _LINUX_IRQNR_H
+
+/*
+ * Generic irq_desc iterators:
+ */
+#ifdef __KERNEL__
+
+#ifndef CONFIG_GENERIC_HARDIRQS
+#include <asm/irq.h>
+# define nr_irqs		NR_IRQS
+
+# define for_each_irq_desc(irq, desc)		\
+	for (irq = 0; irq < nr_irqs; irq++)
+
+# define for_each_irq_desc_reverse(irq, desc)                          \
+	for (irq = nr_irqs - 1; irq >= 0; irq--)
+#else
+
+extern int nr_irqs;
+
+#ifndef CONFIG_SPARSE_IRQ
+
+struct irq_desc;
+# define for_each_irq_desc(irq, desc)		\
+	for (irq = 0, desc = irq_desc; irq < nr_irqs; irq++, desc++)
+# define for_each_irq_desc_reverse(irq, desc)                          \
+	for (irq = nr_irqs - 1, desc = irq_desc + (nr_irqs - 1);        \
+	    irq >= 0; irq--, desc--)
+#endif
+#endif
+
+#define for_each_irq_nr(irq)                   \
+       for (irq = 0; irq < nr_irqs; irq++)
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/include/linux/jbd.h b/include/linux/jbd.h
index 07a9b52a2654..346e2b80be7d 100644
--- a/include/linux/jbd.h
+++ b/include/linux/jbd.h
@@ -61,7 +61,7 @@ extern u8 journal_enable_debug;
 	do {								\
 		if ((n) <= journal_enable_debug) {			\
 			printk (KERN_DEBUG "(%s, %d): %s: ",		\
-				__FILE__, __LINE__, __FUNCTION__);	\
+				__FILE__, __LINE__, __func__);	\
 			printk (f, ## a);				\
 		}							\
 	} while (0)
@@ -816,6 +816,9 @@ struct journal_s
 #define JFS_FLUSHED	0x008	/* The journal superblock has been flushed */
 #define JFS_LOADED	0x010	/* The journal superblock has been loaded */
 #define JFS_BARRIER	0x020	/* Use IDE barriers */
+#define JFS_ABORT_ON_SYNCDATA_ERR	0x040  /* Abort the journal on file
+						* data write error in ordered
+						* mode */
 
 /*
  * Function declarations for the journaling transaction and buffer
@@ -908,7 +911,7 @@ extern int	   journal_set_features
 		   (journal_t *, unsigned long, unsigned long, unsigned long);
 extern int	   journal_create     (journal_t *);
 extern int	   journal_load       (journal_t *journal);
-extern void	   journal_destroy    (journal_t *);
+extern int	   journal_destroy    (journal_t *);
 extern int	   journal_recover    (journal_t *journal);
 extern int	   journal_wipe       (journal_t *, int);
 extern int	   journal_skip_recovery	(journal_t *);
@@ -984,7 +987,7 @@ extern int	cleanup_journal_tail(journal_t *);
 
 #define jbd_ENOSYS() \
 do {								           \
-	printk (KERN_ERR "JBD unimplemented function %s\n", __FUNCTION__); \
+	printk (KERN_ERR "JBD unimplemented function %s\n", __func__); \
 	current->state = TASK_UNINTERRUPTIBLE;			           \
 	schedule();						           \
 } while (1)
diff --git a/include/linux/jbd2.h b/include/linux/jbd2.h
index d2e91ea998fd..c7d106ef22e2 100644
--- a/include/linux/jbd2.h
+++ b/include/linux/jbd2.h
@@ -61,7 +61,7 @@ extern u8 jbd2_journal_enable_debug;
 	do {								\
 		if ((n) <= jbd2_journal_enable_debug) {			\
 			printk (KERN_DEBUG "(%s, %d): %s: ",		\
-				__FILE__, __LINE__, __FUNCTION__);	\
+				__FILE__, __LINE__, __func__);	\
 			printk (f, ## a);				\
 		}							\
 	} while (0)
@@ -641,6 +641,11 @@ struct transaction_s
 	 */
 	int t_handle_count;
 
+	/*
+	 * For use by the filesystem to store fs-specific data
+	 * structures associated with the transaction
+	 */
+	struct list_head	t_private_list;
 };
 
 struct transaction_run_stats_s {
@@ -935,6 +940,10 @@ struct journal_s
 
 	pid_t			j_last_sync_writer;
 
+	/* This function is called when a transaction is closed */
+	void			(*j_commit_callback)(journal_t *,
+						     transaction_t *);
+
 	/*
 	 * Journal statistics
 	 */
@@ -1143,7 +1152,7 @@ extern int	jbd2_cleanup_journal_tail(journal_t *);
 
 #define jbd_ENOSYS() \
 do {								           \
-	printk (KERN_ERR "JBD unimplemented function %s\n", __FUNCTION__); \
+	printk (KERN_ERR "JBD unimplemented function %s\n", __func__); \
 	current->state = TASK_UNINTERRUPTIBLE;			           \
 	schedule();						           \
 } while (1)
diff --git a/include/linux/jiffies.h b/include/linux/jiffies.h
index abb6ac639e8e..1a9cf78bfce5 100644
--- a/include/linux/jiffies.h
+++ b/include/linux/jiffies.h
@@ -115,10 +115,20 @@ static inline u64 get_jiffies_64(void)
 	 ((long)(a) - (long)(b) >= 0))
 #define time_before_eq(a,b)	time_after_eq(b,a)
 
+/*
+ * Calculate whether a is in the range of [b, c].
+ */
 #define time_in_range(a,b,c) \
 	(time_after_eq(a,b) && \
 	 time_before_eq(a,c))
 
+/*
+ * Calculate whether a is in the range of [b, c).
+ */
+#define time_in_range_open(a,b,c) \
+	(time_after_eq(a,b) && \
+	 time_before(a,c))
+
 /* Same as above, but does so with platform independent 64bit types.
  * These must be used when utilizing jiffies_64 (i.e. return value of
  * get_jiffies_64() */
diff --git a/include/linux/journal-head.h b/include/linux/journal-head.h
index 8a62d1e84b9b..bb70ebb6a2d5 100644
--- a/include/linux/journal-head.h
+++ b/include/linux/journal-head.h
@@ -3,7 +3,7 @@
  *
  * buffer_head fields for JBD
  *
- * 27 May 2001 Andrew Morton <akpm@digeo.com>
+ * 27 May 2001 Andrew Morton
  *	Created - pulled out of fs.h
  */
 
diff --git a/include/linux/kallsyms.h b/include/linux/kallsyms.h
index b96144887444..f3fe34391d8e 100644
--- a/include/linux/kallsyms.h
+++ b/include/linux/kallsyms.h
@@ -93,12 +93,10 @@ static inline void print_symbol(const char *fmt, unsigned long addr)
 }
 
 /*
- * Pretty-print a function pointer.
- *
- * ia64 and ppc64 function pointers are really function descriptors,
- * which contain a pointer the real address.
+ * Pretty-print a function pointer.  This function is deprecated.
+ * Please use the "%pF" vsprintf format instead.
  */
-static inline void print_fn_descriptor_symbol(const char *fmt, void *addr)
+static inline void __deprecated print_fn_descriptor_symbol(const char *fmt, void *addr)
 {
 #if defined(CONFIG_IA64) || defined(CONFIG_PPC64)
 	addr = *(void **)addr;
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index 75d81f157d2e..ca9ff6411dfa 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -16,6 +16,7 @@
 #include <linux/log2.h>
 #include <linux/typecheck.h>
 #include <linux/ratelimit.h>
+#include <linux/dynamic_printk.h>
 #include <asm/byteorder.h>
 #include <asm/bug.h>
 
@@ -115,6 +116,8 @@ extern int _cond_resched(void);
 # define might_resched() do { } while (0)
 #endif
 
+#ifdef CONFIG_DEBUG_SPINLOCK_SLEEP
+  void __might_sleep(char *file, int line);
 /**
  * might_sleep - annotation for functions that can sleep
  *
@@ -125,8 +128,6 @@ extern int _cond_resched(void);
  * be bitten later when the calling function happens to sleep when it is not
  * supposed to.
  */
-#ifdef CONFIG_DEBUG_SPINLOCK_SLEEP
-  void __might_sleep(char *file, int line);
 # define might_sleep() \
 	do { __might_sleep(__FILE__, __LINE__); might_resched(); } while (0)
 #else
@@ -140,6 +141,15 @@ extern int _cond_resched(void);
 		(__x < 0) ? -__x : __x;		\
 	})
 
+#ifdef CONFIG_PROVE_LOCKING
+void might_fault(void);
+#else
+static inline void might_fault(void)
+{
+	might_sleep();
+}
+#endif
+
 extern struct atomic_notifier_head panic_notifier_list;
 extern long (*panic_blink)(long time);
 NORET_TYPE void panic(const char * fmt, ...)
@@ -187,9 +197,35 @@ extern unsigned long long memparse(const char *ptr, char **retptr);
 extern int core_kernel_text(unsigned long addr);
 extern int __kernel_text_address(unsigned long addr);
 extern int kernel_text_address(unsigned long addr);
+extern int func_ptr_is_kernel_text(void *ptr);
+
 struct pid;
 extern struct pid *session_of_pgrp(struct pid *pgrp);
 
+/*
+ * FW_BUG
+ * Add this to a message where you are sure the firmware is buggy or behaves
+ * really stupid or out of spec. Be aware that the responsible BIOS developer
+ * should be able to fix this issue or at least get a concrete idea of the
+ * problem by reading your message without the need of looking at the kernel
+ * code.
+ * 
+ * Use it for definite and high priority BIOS bugs.
+ *
+ * FW_WARN
+ * Use it for not that clear (e.g. could the kernel messed up things already?)
+ * and medium priority BIOS bugs.
+ *
+ * FW_INFO
+ * Use this one if you want to tell the user or vendor about something
+ * suspicious, but generally harmless related to the firmware.
+ *
+ * Use it for information or very low priority BIOS bugs.
+ */
+#define FW_BUG		"[Firmware Bug]: "
+#define FW_WARN		"[Firmware Warn]: "
+#define FW_INFO		"[Firmware Info]: "
+
 #ifdef CONFIG_PRINTK
 asmlinkage int vprintk(const char *fmt, va_list args)
 	__attribute__ ((format (printf, 1, 0)));
@@ -213,6 +249,9 @@ static inline bool printk_timed_ratelimit(unsigned long *caller_jiffies, \
 		{ return false; }
 #endif
 
+extern int printk_needs_cpu(int cpu);
+extern void printk_tick(void);
+
 extern void asmlinkage __attribute__((format(printf, 1, 2)))
 	early_printk(const char *fmt, ...);
 
@@ -235,9 +274,10 @@ extern int oops_in_progress;		/* If set, an oops, panic(), BUG() or die() is in
 extern int panic_timeout;
 extern int panic_on_oops;
 extern int panic_on_unrecovered_nmi;
-extern int tainted;
 extern const char *print_tainted(void);
-extern void add_taint(unsigned);
+extern void add_taint(unsigned flag);
+extern int test_taint(unsigned flag);
+extern unsigned long get_taint(void);
 extern int root_mountflags;
 
 /* Values used for system_state */
@@ -250,16 +290,17 @@ extern enum system_states {
 	SYSTEM_SUSPEND_DISK,
 } system_state;
 
-#define TAINT_PROPRIETARY_MODULE	(1<<0)
-#define TAINT_FORCED_MODULE		(1<<1)
-#define TAINT_UNSAFE_SMP		(1<<2)
-#define TAINT_FORCED_RMMOD		(1<<3)
-#define TAINT_MACHINE_CHECK		(1<<4)
-#define TAINT_BAD_PAGE			(1<<5)
-#define TAINT_USER			(1<<6)
-#define TAINT_DIE			(1<<7)
-#define TAINT_OVERRIDDEN_ACPI_TABLE	(1<<8)
-#define TAINT_WARN			(1<<9)
+#define TAINT_PROPRIETARY_MODULE	0
+#define TAINT_FORCED_MODULE		1
+#define TAINT_UNSAFE_SMP		2
+#define TAINT_FORCED_RMMOD		3
+#define TAINT_MACHINE_CHECK		4
+#define TAINT_BAD_PAGE			5
+#define TAINT_USER			6
+#define TAINT_DIE			7
+#define TAINT_OVERRIDDEN_ACPI_TABLE	8
+#define TAINT_WARN			9
+#define TAINT_CRAP			10
 
 extern void dump_stack(void) __cold;
 
@@ -288,28 +329,36 @@ static inline char *pack_hex_byte(char *buf, u8 byte)
 	return buf;
 }
 
-#define pr_emerg(fmt, arg...) \
-	printk(KERN_EMERG fmt, ##arg)
-#define pr_alert(fmt, arg...) \
-	printk(KERN_ALERT fmt, ##arg)
-#define pr_crit(fmt, arg...) \
-	printk(KERN_CRIT fmt, ##arg)
-#define pr_err(fmt, arg...) \
-	printk(KERN_ERR fmt, ##arg)
-#define pr_warning(fmt, arg...) \
-	printk(KERN_WARNING fmt, ##arg)
-#define pr_notice(fmt, arg...) \
-	printk(KERN_NOTICE fmt, ##arg)
-#define pr_info(fmt, arg...) \
-	printk(KERN_INFO fmt, ##arg)
-
-#ifdef DEBUG
+#ifndef pr_fmt
+#define pr_fmt(fmt) fmt
+#endif
+
+#define pr_emerg(fmt, ...) \
+        printk(KERN_EMERG pr_fmt(fmt), ##__VA_ARGS__)
+#define pr_alert(fmt, ...) \
+        printk(KERN_ALERT pr_fmt(fmt), ##__VA_ARGS__)
+#define pr_crit(fmt, ...) \
+        printk(KERN_CRIT pr_fmt(fmt), ##__VA_ARGS__)
+#define pr_err(fmt, ...) \
+        printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
+#define pr_warning(fmt, ...) \
+        printk(KERN_WARNING pr_fmt(fmt), ##__VA_ARGS__)
+#define pr_notice(fmt, ...) \
+        printk(KERN_NOTICE pr_fmt(fmt), ##__VA_ARGS__)
+#define pr_info(fmt, ...) \
+        printk(KERN_INFO pr_fmt(fmt), ##__VA_ARGS__)
+
 /* If you are writing a driver, please use dev_dbg instead */
-#define pr_debug(fmt, arg...) \
-	printk(KERN_DEBUG fmt, ##arg)
+#if defined(CONFIG_DYNAMIC_PRINTK_DEBUG)
+#define pr_debug(fmt, ...) do { \
+	dynamic_pr_debug(pr_fmt(fmt), ##__VA_ARGS__); \
+	} while (0)
+#elif defined(DEBUG)
+#define pr_debug(fmt, ...) \
+	printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
 #else
-#define pr_debug(fmt, arg...) \
-	({ if (0) printk(KERN_DEBUG fmt, ##arg); 0; })
+#define pr_debug(fmt, ...) \
+	({ if (0) printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__); 0; })
 #endif
 
 /*
@@ -323,18 +372,6 @@ static inline char *pack_hex_byte(char *buf, u8 byte)
 	((unsigned char *)&addr)[3]
 #define NIPQUAD_FMT "%u.%u.%u.%u"
 
-#define NIP6(addr) \
-	ntohs((addr).s6_addr16[0]), \
-	ntohs((addr).s6_addr16[1]), \
-	ntohs((addr).s6_addr16[2]), \
-	ntohs((addr).s6_addr16[3]), \
-	ntohs((addr).s6_addr16[4]), \
-	ntohs((addr).s6_addr16[5]), \
-	ntohs((addr).s6_addr16[6]), \
-	ntohs((addr).s6_addr16[7])
-#define NIP6_FMT "%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x"
-#define NIP6_SEQFMT "%04x%04x%04x%04x%04x%04x%04x%04x"
-
 #if defined(__LITTLE_ENDIAN)
 #define HIPQUAD(addr) \
 	((unsigned char *)&addr)[3], \
@@ -486,4 +523,9 @@ struct sysinfo {
 #define NUMA_BUILD 0
 #endif
 
+/* Rebuild everything on CONFIG_FTRACE_MCOUNT_RECORD */
+#ifdef CONFIG_FTRACE_MCOUNT_RECORD
+# define REBUILD_DUE_TO_FTRACE_MCOUNT_RECORD
+#endif
+
 #endif
diff --git a/include/linux/kernel_stat.h b/include/linux/kernel_stat.h
index cf9f40a91c9c..4ee4b3d2316f 100644
--- a/include/linux/kernel_stat.h
+++ b/include/linux/kernel_stat.h
@@ -28,7 +28,9 @@ struct cpu_usage_stat {
 
 struct kernel_stat {
 	struct cpu_usage_stat	cpustat;
-	unsigned int irqs[NR_IRQS];
+#ifndef CONFIG_SPARSE_IRQ
+       unsigned int irqs[NR_IRQS];
+#endif
 };
 
 DECLARE_PER_CPU(struct kernel_stat, kstat);
@@ -39,19 +41,44 @@ DECLARE_PER_CPU(struct kernel_stat, kstat);
 
 extern unsigned long long nr_context_switches(void);
 
+#ifndef CONFIG_SPARSE_IRQ
+#define kstat_irqs_this_cpu(irq) \
+	(kstat_this_cpu.irqs[irq])
+
+struct irq_desc;
+
+static inline void kstat_incr_irqs_this_cpu(unsigned int irq,
+					    struct irq_desc *desc)
+{
+	kstat_this_cpu.irqs[irq]++;
+}
+#endif
+
+
+#ifndef CONFIG_SPARSE_IRQ
+static inline unsigned int kstat_irqs_cpu(unsigned int irq, int cpu)
+{
+       return kstat_cpu(cpu).irqs[irq];
+}
+#else
+extern unsigned int kstat_irqs_cpu(unsigned int irq, int cpu);
+#endif
+
 /*
  * Number of interrupts per specific IRQ source, since bootup
  */
-static inline int kstat_irqs(int irq)
+static inline unsigned int kstat_irqs(unsigned int irq)
 {
-	int cpu, sum = 0;
+	unsigned int sum = 0;
+	int cpu;
 
 	for_each_possible_cpu(cpu)
-		sum += kstat_cpu(cpu).irqs[irq];
+		sum += kstat_irqs_cpu(irq, cpu);
 
 	return sum;
 }
 
+extern unsigned long long task_delta_exec(struct task_struct *);
 extern void account_user_time(struct task_struct *, cputime_t);
 extern void account_user_time_scaled(struct task_struct *, cputime_t);
 extern void account_system_time(struct task_struct *, int, cputime_t);
diff --git a/include/linux/kexec.h b/include/linux/kexec.h
index 17f76fc05173..adc34f2c6eff 100644
--- a/include/linux/kexec.h
+++ b/include/linux/kexec.h
@@ -100,6 +100,10 @@ struct kimage {
 #define KEXEC_TYPE_DEFAULT 0
 #define KEXEC_TYPE_CRASH   1
 	unsigned int preserve_context : 1;
+
+#ifdef ARCH_HAS_KIMAGE_ARCH
+	struct kimage_arch arch;
+#endif
 };
 
 
diff --git a/include/linux/key-ui.h b/include/linux/key-ui.h
deleted file mode 100644
index e8b8a7a5c496..000000000000
--- a/include/linux/key-ui.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* key-ui.h: key userspace interface stuff
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _LINUX_KEY_UI_H
-#define _LINUX_KEY_UI_H
-
-#include <linux/key.h>
-
-/* the key tree */
-extern struct rb_root key_serial_tree;
-extern spinlock_t key_serial_lock;
-
-/* required permissions */
-#define	KEY_VIEW	0x01	/* require permission to view attributes */
-#define	KEY_READ	0x02	/* require permission to read content */
-#define	KEY_WRITE	0x04	/* require permission to update / modify */
-#define	KEY_SEARCH	0x08	/* require permission to search (keyring) or find (key) */
-#define	KEY_LINK	0x10	/* require permission to link */
-#define	KEY_SETATTR	0x20	/* require permission to change attributes */
-#define	KEY_ALL		0x3f	/* all the above permissions */
-
-/*
- * the keyring payload contains a list of the keys to which the keyring is
- * subscribed
- */
-struct keyring_list {
-	struct rcu_head	rcu;		/* RCU deletion hook */
-	unsigned short	maxkeys;	/* max keys this list can hold */
-	unsigned short	nkeys;		/* number of keys currently held */
-	unsigned short	delkey;		/* key to be unlinked by RCU */
-	struct key	*keys[0];
-};
-
-/*
- * check to see whether permission is granted to use a key in the desired way
- */
-extern int key_task_permission(const key_ref_t key_ref,
-			       struct task_struct *context,
-			       key_perm_t perm);
-
-static inline int key_permission(const key_ref_t key_ref, key_perm_t perm)
-{
-	return key_task_permission(key_ref, current, perm);
-}
-
-extern key_ref_t lookup_user_key(struct task_struct *context,
-				 key_serial_t id, int create, int partial,
-				 key_perm_t perm);
-
-extern long join_session_keyring(const char *name);
-
-extern struct key_type *key_type_lookup(const char *type);
-extern void key_type_put(struct key_type *ktype);
-
-#define key_negative_timeout	60	/* default timeout on a negative key's existence */
-
-
-#endif /* _LINUX_KEY_UI_H */
diff --git a/include/linux/key.h b/include/linux/key.h
index 1b70e35a71e3..21d32a142c00 100644
--- a/include/linux/key.h
+++ b/include/linux/key.h
@@ -73,6 +73,7 @@ struct key;
 struct seq_file;
 struct user_struct;
 struct signal_struct;
+struct cred;
 
 struct key_type;
 struct key_owner;
@@ -181,7 +182,7 @@ struct key {
 extern struct key *key_alloc(struct key_type *type,
 			     const char *desc,
 			     uid_t uid, gid_t gid,
-			     struct task_struct *ctx,
+			     const struct cred *cred,
 			     key_perm_t perm,
 			     unsigned long flags);
 
@@ -249,7 +250,7 @@ extern int key_unlink(struct key *keyring,
 		      struct key *key);
 
 extern struct key *keyring_alloc(const char *description, uid_t uid, gid_t gid,
-				 struct task_struct *ctx,
+				 const struct cred *cred,
 				 unsigned long flags,
 				 struct key *dest);
 
@@ -276,24 +277,11 @@ extern ctl_table key_sysctls[];
 /*
  * the userspace interface
  */
-extern void switch_uid_keyring(struct user_struct *new_user);
-extern int copy_keys(unsigned long clone_flags, struct task_struct *tsk);
-extern int copy_thread_group_keys(struct task_struct *tsk);
-extern void exit_keys(struct task_struct *tsk);
-extern void exit_thread_group_keys(struct signal_struct *tg);
-extern int suid_keys(struct task_struct *tsk);
-extern int exec_keys(struct task_struct *tsk);
+extern int install_thread_keyring_to_cred(struct cred *cred);
 extern void key_fsuid_changed(struct task_struct *tsk);
 extern void key_fsgid_changed(struct task_struct *tsk);
 extern void key_init(void);
 
-#define __install_session_keyring(tsk, keyring)			\
-({								\
-	struct key *old_session = tsk->signal->session_keyring;	\
-	tsk->signal->session_keyring = keyring;			\
-	old_session;						\
-})
-
 #else /* CONFIG_KEYS */
 
 #define key_validate(k)			0
@@ -302,17 +290,9 @@ extern void key_init(void);
 #define key_revoke(k)			do { } while(0)
 #define key_put(k)			do { } while(0)
 #define key_ref_put(k)			do { } while(0)
-#define make_key_ref(k, p)			({ NULL; })
-#define key_ref_to_ptr(k)		({ NULL; })
+#define make_key_ref(k, p)		NULL
+#define key_ref_to_ptr(k)		NULL
 #define is_key_possessed(k)		0
-#define switch_uid_keyring(u)		do { } while(0)
-#define __install_session_keyring(t, k)	({ NULL; })
-#define copy_keys(f,t)			0
-#define copy_thread_group_keys(t)	0
-#define exit_keys(t)			do { } while(0)
-#define exit_thread_group_keys(tg)	do { } while(0)
-#define suid_keys(t)			do { } while(0)
-#define exec_keys(t)			do { } while(0)
 #define key_fsuid_changed(t)		do { } while(0)
 #define key_fsgid_changed(t)		do { } while(0)
 #define key_init()			do { } while(0)
diff --git a/include/linux/keyctl.h b/include/linux/keyctl.h
index 656ee6b77a4a..c0688eb72093 100644
--- a/include/linux/keyctl.h
+++ b/include/linux/keyctl.h
@@ -1,6 +1,6 @@
 /* keyctl.h: keyctl command IDs
  *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
+ * Copyright (C) 2004, 2008 Red Hat, Inc. All Rights Reserved.
  * Written by David Howells (dhowells@redhat.com)
  *
  * This program is free software; you can redistribute it and/or
@@ -20,6 +20,7 @@
 #define KEY_SPEC_USER_SESSION_KEYRING	-5	/* - key ID for UID-session keyring */
 #define KEY_SPEC_GROUP_KEYRING		-6	/* - key ID for GID-specific keyring */
 #define KEY_SPEC_REQKEY_AUTH_KEY	-7	/* - key ID for assumed request_key auth key */
+#define KEY_SPEC_REQUESTOR_KEYRING	-8	/* - key ID for request_key() dest keyring */
 
 /* request-key default keyrings */
 #define KEY_REQKEY_DEFL_NO_CHANGE		-1
@@ -30,6 +31,7 @@
 #define KEY_REQKEY_DEFL_USER_KEYRING		4
 #define KEY_REQKEY_DEFL_USER_SESSION_KEYRING	5
 #define KEY_REQKEY_DEFL_GROUP_KEYRING		6
+#define KEY_REQKEY_DEFL_REQUESTOR_KEYRING	7
 
 /* keyctl commands */
 #define KEYCTL_GET_KEYRING_ID		0	/* ask for a keyring's ID */
diff --git a/include/linux/kmod.h b/include/linux/kmod.h
index a1a91577813c..92213a9194e1 100644
--- a/include/linux/kmod.h
+++ b/include/linux/kmod.h
@@ -99,4 +99,7 @@ struct file;
 extern int call_usermodehelper_pipe(char *path, char *argv[], char *envp[],
 				    struct file **filp);
 
+extern int usermodehelper_disable(void);
+extern void usermodehelper_enable(void);
+
 #endif /* __LINUX_KMOD_H__ */
diff --git a/include/linux/kprobes.h b/include/linux/kprobes.h
index 0be7795655fa..497b1d1f7a05 100644
--- a/include/linux/kprobes.h
+++ b/include/linux/kprobes.h
@@ -29,6 +29,7 @@
  *		<jkenisto@us.ibm.com>  and Prasanna S Panchamukhi
  *		<prasanna@in.ibm.com> added function-return probes.
  */
+#include <linux/linkage.h>
 #include <linux/list.h>
 #include <linux/notifier.h>
 #include <linux/smp.h>
@@ -47,7 +48,7 @@
 #define KPROBE_HIT_SSDONE	0x00000008
 
 /* Attach to insert probes on any functions which should be ignored*/
-#define __kprobes	__attribute__((__section__(".kprobes.text")))
+#define __kprobes	__attribute__((__section__(".kprobes.text"))) notrace
 
 struct kprobe;
 struct pt_regs;
@@ -256,7 +257,7 @@ void recycle_rp_inst(struct kretprobe_instance *ri, struct hlist_head *head);
 
 #else /* CONFIG_KPROBES */
 
-#define __kprobes	/**/
+#define __kprobes	notrace
 struct jprobe;
 struct kretprobe;
 
diff --git a/include/linux/kvm.h b/include/linux/kvm.h
index 70a30651cd12..f18b86fa8655 100644
--- a/include/linux/kvm.h
+++ b/include/linux/kvm.h
@@ -311,22 +311,33 @@ struct kvm_s390_interrupt {
 
 /* This structure represents a single trace buffer record. */
 struct kvm_trace_rec {
-	__u32 event:28;
-	__u32 extra_u32:3;
-	__u32 cycle_in:1;
+	/* variable rec_val
+	 * is split into:
+	 * bits 0 - 27  -> event id
+	 * bits 28 -30  -> number of extra data args of size u32
+	 * bits 31      -> binary indicator for if tsc is in record
+	 */
+	__u32 rec_val;
 	__u32 pid;
 	__u32 vcpu_id;
 	union {
 		struct {
-			__u64 cycle_u64;
+			__u64 timestamp;
 			__u32 extra_u32[KVM_TRC_EXTRA_MAX];
-		} __attribute__((packed)) cycle;
+		} __attribute__((packed)) timestamp;
 		struct {
 			__u32 extra_u32[KVM_TRC_EXTRA_MAX];
-		} nocycle;
+		} notimestamp;
 	} u;
 };
 
+#define TRACE_REC_EVENT_ID(val) \
+		(0x0fffffff & (val))
+#define TRACE_REC_NUM_DATA_ARGS(val) \
+		(0x70000000 & ((val) << 28))
+#define TRACE_REC_TCS(val) \
+		(0x80000000 & ((val) << 31))
+
 #define KVMIO 0xAE
 
 /*
@@ -372,6 +383,10 @@ struct kvm_trace_rec {
 #define KVM_CAP_MP_STATE 14
 #define KVM_CAP_COALESCED_MMIO 15
 #define KVM_CAP_SYNC_MMU 16  /* Changes to host mmap are reflected in guest */
+#if defined(CONFIG_X86)||defined(CONFIG_IA64)
+#define KVM_CAP_DEVICE_ASSIGNMENT 17
+#endif
+#define KVM_CAP_IOMMU 18
 
 /*
  * ioctls for VM fds
@@ -401,6 +416,10 @@ struct kvm_trace_rec {
 			_IOW(KVMIO,  0x67, struct kvm_coalesced_mmio_zone)
 #define KVM_UNREGISTER_COALESCED_MMIO \
 			_IOW(KVMIO,  0x68, struct kvm_coalesced_mmio_zone)
+#define KVM_ASSIGN_PCI_DEVICE _IOR(KVMIO, 0x69, \
+				   struct kvm_assigned_pci_dev)
+#define KVM_ASSIGN_IRQ _IOR(KVMIO, 0x70, \
+			    struct kvm_assigned_irq)
 
 /*
  * ioctls for vcpu fds
@@ -440,4 +459,51 @@ struct kvm_trace_rec {
 #define KVM_GET_MP_STATE          _IOR(KVMIO,  0x98, struct kvm_mp_state)
 #define KVM_SET_MP_STATE          _IOW(KVMIO,  0x99, struct kvm_mp_state)
 
+#define KVM_TRC_INJ_VIRQ         (KVM_TRC_HANDLER + 0x02)
+#define KVM_TRC_REDELIVER_EVT    (KVM_TRC_HANDLER + 0x03)
+#define KVM_TRC_PEND_INTR        (KVM_TRC_HANDLER + 0x04)
+#define KVM_TRC_IO_READ          (KVM_TRC_HANDLER + 0x05)
+#define KVM_TRC_IO_WRITE         (KVM_TRC_HANDLER + 0x06)
+#define KVM_TRC_CR_READ          (KVM_TRC_HANDLER + 0x07)
+#define KVM_TRC_CR_WRITE         (KVM_TRC_HANDLER + 0x08)
+#define KVM_TRC_DR_READ          (KVM_TRC_HANDLER + 0x09)
+#define KVM_TRC_DR_WRITE         (KVM_TRC_HANDLER + 0x0A)
+#define KVM_TRC_MSR_READ         (KVM_TRC_HANDLER + 0x0B)
+#define KVM_TRC_MSR_WRITE        (KVM_TRC_HANDLER + 0x0C)
+#define KVM_TRC_CPUID            (KVM_TRC_HANDLER + 0x0D)
+#define KVM_TRC_INTR             (KVM_TRC_HANDLER + 0x0E)
+#define KVM_TRC_NMI              (KVM_TRC_HANDLER + 0x0F)
+#define KVM_TRC_VMMCALL          (KVM_TRC_HANDLER + 0x10)
+#define KVM_TRC_HLT              (KVM_TRC_HANDLER + 0x11)
+#define KVM_TRC_CLTS             (KVM_TRC_HANDLER + 0x12)
+#define KVM_TRC_LMSW             (KVM_TRC_HANDLER + 0x13)
+#define KVM_TRC_APIC_ACCESS      (KVM_TRC_HANDLER + 0x14)
+#define KVM_TRC_TDP_FAULT        (KVM_TRC_HANDLER + 0x15)
+#define KVM_TRC_GTLB_WRITE       (KVM_TRC_HANDLER + 0x16)
+#define KVM_TRC_STLB_WRITE       (KVM_TRC_HANDLER + 0x17)
+#define KVM_TRC_STLB_INVAL       (KVM_TRC_HANDLER + 0x18)
+#define KVM_TRC_PPC_INSTR        (KVM_TRC_HANDLER + 0x19)
+
+struct kvm_assigned_pci_dev {
+	__u32 assigned_dev_id;
+	__u32 busnr;
+	__u32 devfn;
+	__u32 flags;
+	union {
+		__u32 reserved[12];
+	};
+};
+
+struct kvm_assigned_irq {
+	__u32 assigned_dev_id;
+	__u32 host_irq;
+	__u32 guest_irq;
+	__u32 flags;
+	union {
+		__u32 reserved[12];
+	};
+};
+
+#define KVM_DEV_ASSIGN_ENABLE_IOMMU	(1 << 0)
+
 #endif
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index 8525afc53107..bb92be2153bc 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -34,6 +34,10 @@
 #define KVM_REQ_MMU_RELOAD         3
 #define KVM_REQ_TRIPLE_FAULT       4
 #define KVM_REQ_PENDING_TIMER      5
+#define KVM_REQ_UNHALT             6
+#define KVM_REQ_MMU_SYNC           7
+
+#define KVM_USERSPACE_IRQ_SOURCE_ID	0
 
 struct kvm_vcpu;
 extern struct kmem_cache *kvm_vcpu_cache;
@@ -279,12 +283,71 @@ void kvm_free_physmem(struct kvm *kvm);
 
 struct  kvm *kvm_arch_create_vm(void);
 void kvm_arch_destroy_vm(struct kvm *kvm);
+void kvm_free_all_assigned_devices(struct kvm *kvm);
 
 int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
 int kvm_cpu_has_interrupt(struct kvm_vcpu *v);
 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu);
 void kvm_vcpu_kick(struct kvm_vcpu *vcpu);
 
+int kvm_is_mmio_pfn(pfn_t pfn);
+
+struct kvm_irq_ack_notifier {
+	struct hlist_node link;
+	unsigned gsi;
+	void (*irq_acked)(struct kvm_irq_ack_notifier *kian);
+};
+
+struct kvm_assigned_dev_kernel {
+	struct kvm_irq_ack_notifier ack_notifier;
+	struct work_struct interrupt_work;
+	struct list_head list;
+	int assigned_dev_id;
+	int host_busnr;
+	int host_devfn;
+	int host_irq;
+	int guest_irq;
+	int irq_requested;
+	int irq_source_id;
+	struct pci_dev *dev;
+	struct kvm *kvm;
+};
+void kvm_set_irq(struct kvm *kvm, int irq_source_id, int irq, int level);
+void kvm_notify_acked_irq(struct kvm *kvm, unsigned gsi);
+void kvm_register_irq_ack_notifier(struct kvm *kvm,
+				   struct kvm_irq_ack_notifier *kian);
+void kvm_unregister_irq_ack_notifier(struct kvm *kvm,
+				     struct kvm_irq_ack_notifier *kian);
+int kvm_request_irq_source_id(struct kvm *kvm);
+void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id);
+
+#ifdef CONFIG_DMAR
+int kvm_iommu_map_pages(struct kvm *kvm, gfn_t base_gfn,
+			unsigned long npages);
+int kvm_iommu_map_guest(struct kvm *kvm,
+			struct kvm_assigned_dev_kernel *assigned_dev);
+int kvm_iommu_unmap_guest(struct kvm *kvm);
+#else /* CONFIG_DMAR */
+static inline int kvm_iommu_map_pages(struct kvm *kvm,
+				      gfn_t base_gfn,
+				      unsigned long npages)
+{
+	return 0;
+}
+
+static inline int kvm_iommu_map_guest(struct kvm *kvm,
+				      struct kvm_assigned_dev_kernel
+				      *assigned_dev)
+{
+	return -ENODEV;
+}
+
+static inline int kvm_iommu_unmap_guest(struct kvm *kvm)
+{
+	return 0;
+}
+#endif /* CONFIG_DMAR */
+
 static inline void kvm_guest_enter(void)
 {
 	account_system_vtime(current);
@@ -307,6 +370,11 @@ static inline gpa_t gfn_to_gpa(gfn_t gfn)
 	return (gpa_t)gfn << PAGE_SHIFT;
 }
 
+static inline hpa_t pfn_to_hpa(pfn_t pfn)
+{
+	return (hpa_t)pfn << PAGE_SHIFT;
+}
+
 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
 {
 	set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
@@ -326,6 +394,25 @@ struct kvm_stats_debugfs_item {
 extern struct kvm_stats_debugfs_item debugfs_entries[];
 extern struct dentry *kvm_debugfs_dir;
 
+#define KVMTRACE_5D(evt, vcpu, d1, d2, d3, d4, d5, name) \
+	trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
+						vcpu, 5, d1, d2, d3, d4, d5)
+#define KVMTRACE_4D(evt, vcpu, d1, d2, d3, d4, name) \
+	trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
+						vcpu, 4, d1, d2, d3, d4, 0)
+#define KVMTRACE_3D(evt, vcpu, d1, d2, d3, name) \
+	trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
+						vcpu, 3, d1, d2, d3, 0, 0)
+#define KVMTRACE_2D(evt, vcpu, d1, d2, name) \
+	trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
+						vcpu, 2, d1, d2, 0, 0, 0)
+#define KVMTRACE_1D(evt, vcpu, d1, name) \
+	trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
+						vcpu, 1, d1, 0, 0, 0, 0)
+#define KVMTRACE_0D(evt, vcpu, name) \
+	trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
+						vcpu, 0, 0, 0, 0, 0, 0)
+
 #ifdef CONFIG_KVM_TRACE
 int kvm_trace_ioctl(unsigned int ioctl, unsigned long arg);
 void kvm_trace_cleanup(void);
diff --git a/include/linux/leds.h b/include/linux/leds.h
index d41ccb56146a..d3a73f5a48c3 100644
--- a/include/linux/leds.h
+++ b/include/linux/leds.h
@@ -123,7 +123,7 @@ extern void ledtrig_ide_activity(void);
  */
 struct led_info {
 	const char	*name;
-	char		*default_trigger;
+	const char	*default_trigger;
 	int		flags;
 };
 
@@ -135,7 +135,7 @@ struct led_platform_data {
 /* For the leds-gpio driver */
 struct gpio_led {
 	const char *name;
-	char *default_trigger;
+	const char *default_trigger;
 	unsigned 	gpio;
 	u8 		active_low;
 };
diff --git a/include/linux/lguest_launcher.h b/include/linux/lguest_launcher.h
index e7217dc58f39..a53407a4165c 100644
--- a/include/linux/lguest_launcher.h
+++ b/include/linux/lguest_launcher.h
@@ -54,9 +54,13 @@ struct lguest_vqconfig {
 /* Write command first word is a request. */
 enum lguest_req
 {
-	LHREQ_INITIALIZE, /* + base, pfnlimit, pgdir, start */
+	LHREQ_INITIALIZE, /* + base, pfnlimit, start */
 	LHREQ_GETDMA, /* No longer used */
 	LHREQ_IRQ, /* + irq */
 	LHREQ_BREAK, /* + on/off flag (on blocks until someone does off) */
 };
+
+/* The alignment to use between consumer and producer parts of vring.
+ * x86 pagesize for historical reasons. */
+#define LGUEST_VRING_ALIGN	4096
 #endif /* _LINUX_LGUEST_LAUNCHER */
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 947cf84e555d..3449de597eff 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -213,10 +213,11 @@ enum {
 	ATA_PFLAG_FROZEN	= (1 << 2), /* port is frozen */
 	ATA_PFLAG_RECOVERED	= (1 << 3), /* recovery action performed */
 	ATA_PFLAG_LOADING	= (1 << 4), /* boot/loading probe */
-	ATA_PFLAG_UNLOADING	= (1 << 5), /* module is unloading */
 	ATA_PFLAG_SCSI_HOTPLUG	= (1 << 6), /* SCSI hotplug scheduled */
 	ATA_PFLAG_INITIALIZING	= (1 << 7), /* being initialized, don't touch */
 	ATA_PFLAG_RESETTING	= (1 << 8), /* reset in progress */
+	ATA_PFLAG_UNLOADING	= (1 << 9), /* driver is being unloaded */
+	ATA_PFLAG_UNLOADED	= (1 << 10), /* driver is unloaded */
 
 	ATA_PFLAG_SUSPENDED	= (1 << 17), /* port is suspended (power) */
 	ATA_PFLAG_PM_PENDING	= (1 << 18), /* PM operation pending */
@@ -340,6 +341,9 @@ enum {
 
 	ATA_EHI_DID_RESET	= ATA_EHI_DID_SOFTRESET | ATA_EHI_DID_HARDRESET,
 
+	/* mask of flags to transfer *to* the slave link */
+	ATA_EHI_TO_SLAVE_MASK	= ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET,
+
 	/* max tries if error condition is still set after ->error_handler */
 	ATA_EH_MAX_TRIES	= 5,
 
@@ -369,6 +373,10 @@ enum {
 	ATA_HORKAGE_IPM		= (1 << 7),	/* Link PM problems */
 	ATA_HORKAGE_IVB		= (1 << 8),	/* cbl det validity bit bugs */
 	ATA_HORKAGE_STUCK_ERR	= (1 << 9),	/* stuck ERR on next PACKET */
+	ATA_HORKAGE_BRIDGE_OK	= (1 << 10),	/* no bridge limits */
+	ATA_HORKAGE_ATAPI_MOD16_DMA = (1 << 11), /* use ATAPI DMA for commands
+						    not multiple of 16 bytes */
+	ATA_HORKAGE_FIRMWARE_WARN = (1 << 12),	/* firwmare update warning */
 
 	 /* DMA mask for user DMA control: User visible values; DO NOT
 	    renumber */
@@ -1278,26 +1286,62 @@ static inline int ata_link_active(struct ata_link *link)
 	return ata_tag_valid(link->active_tag) || link->sactive;
 }
 
-extern struct ata_link *__ata_port_next_link(struct ata_port *ap,
-					     struct ata_link *link,
-					     bool dev_only);
+/*
+ * Iterators
+ *
+ * ATA_LITER_* constants are used to select link iteration mode and
+ * ATA_DITER_* device iteration mode.
+ *
+ * For a custom iteration directly using ata_{link|dev}_next(), if
+ * @link or @dev, respectively, is NULL, the first element is
+ * returned.  @dev and @link can be any valid device or link and the
+ * next element according to the iteration mode will be returned.
+ * After the last element, NULL is returned.
+ */
+enum ata_link_iter_mode {
+	ATA_LITER_EDGE,		/* if present, PMP links only; otherwise,
+				 * host link.  no slave link */
+	ATA_LITER_HOST_FIRST,	/* host link followed by PMP or slave links */
+	ATA_LITER_PMP_FIRST,	/* PMP links followed by host link,
+				 * slave link still comes after host link */
+};
+
+enum ata_dev_iter_mode {
+	ATA_DITER_ENABLED,
+	ATA_DITER_ENABLED_REVERSE,
+	ATA_DITER_ALL,
+	ATA_DITER_ALL_REVERSE,
+};
 
-#define __ata_port_for_each_link(link, ap) \
-	for ((link) = __ata_port_next_link((ap), NULL, false); (link); \
-	     (link) = __ata_port_next_link((ap), (link), false))
+extern struct ata_link *ata_link_next(struct ata_link *link,
+				      struct ata_port *ap,
+				      enum ata_link_iter_mode mode);
 
-#define ata_port_for_each_link(link, ap) \
-	for ((link) = __ata_port_next_link((ap), NULL, true); (link); \
-	     (link) = __ata_port_next_link((ap), (link), true))
+extern struct ata_device *ata_dev_next(struct ata_device *dev,
+				       struct ata_link *link,
+				       enum ata_dev_iter_mode mode);
 
-#define ata_link_for_each_dev(dev, link) \
-	for ((dev) = (link)->device; \
-	     (dev) < (link)->device + ata_link_max_devices(link) || ((dev) = NULL); \
-	     (dev)++)
+/*
+ * Shortcut notation for iterations
+ *
+ * ata_for_each_link() iterates over each link of @ap according to
+ * @mode.  @link points to the current link in the loop.  @link is
+ * NULL after loop termination.  ata_for_each_dev() works the same way
+ * except that it iterates over each device of @link.
+ *
+ * Note that the mode prefixes ATA_{L|D}ITER_ shouldn't need to be
+ * specified when using the following shorthand notations.  Only the
+ * mode itself (EDGE, HOST_FIRST, ENABLED, etc...) should be
+ * specified.  This not only increases brevity but also makes it
+ * impossible to use ATA_LITER_* for device iteration or vice-versa.
+ */
+#define ata_for_each_link(link, ap, mode) \
+	for ((link) = ata_link_next(NULL, (ap), ATA_LITER_##mode); (link); \
+	     (link) = ata_link_next((link), (ap), ATA_LITER_##mode))
 
-#define ata_link_for_each_dev_reverse(dev, link) \
-	for ((dev) = (link)->device + ata_link_max_devices(link) - 1; \
-	     (dev) >= (link)->device || ((dev) = NULL); (dev)--)
+#define ata_for_each_dev(dev, link, mode) \
+	for ((dev) = ata_dev_next(NULL, (link), ATA_DITER_##mode); (dev); \
+	     (dev) = ata_dev_next((dev), (link), ATA_DITER_##mode))
 
 /**
  *	ata_ncq_enabled - Test whether NCQ is enabled
diff --git a/include/linux/linkage.h b/include/linux/linkage.h
index 56ba37394656..fee9e59649c1 100644
--- a/include/linux/linkage.h
+++ b/include/linux/linkage.h
@@ -4,8 +4,6 @@
 #include <linux/compiler.h>
 #include <asm/linkage.h>
 
-#define notrace __attribute__((no_instrument_function))
-
 #ifdef __cplusplus
 #define CPP_ASMLINKAGE extern "C"
 #else
@@ -66,14 +64,6 @@
 	name:
 #endif
 
-#define KPROBE_ENTRY(name) \
-  .pushsection .kprobes.text, "ax"; \
-  ENTRY(name)
-
-#define KPROBE_END(name) \
-  END(name);		 \
-  .popsection
-
 #ifndef END
 #define END(name) \
   .size name, .-name
diff --git a/include/linux/list_nulls.h b/include/linux/list_nulls.h
new file mode 100644
index 000000000000..93150ecf3ea4
--- /dev/null
+++ b/include/linux/list_nulls.h
@@ -0,0 +1,94 @@
+#ifndef _LINUX_LIST_NULLS_H
+#define _LINUX_LIST_NULLS_H
+
+/*
+ * Special version of lists, where end of list is not a NULL pointer,
+ * but a 'nulls' marker, which can have many different values.
+ * (up to 2^31 different values guaranteed on all platforms)
+ *
+ * In the standard hlist, termination of a list is the NULL pointer.
+ * In this special 'nulls' variant, we use the fact that objects stored in
+ * a list are aligned on a word (4 or 8 bytes alignment).
+ * We therefore use the last significant bit of 'ptr' :
+ * Set to 1 : This is a 'nulls' end-of-list marker (ptr >> 1)
+ * Set to 0 : This is a pointer to some object (ptr)
+ */
+
+struct hlist_nulls_head {
+	struct hlist_nulls_node *first;
+};
+
+struct hlist_nulls_node {
+	struct hlist_nulls_node *next, **pprev;
+};
+#define INIT_HLIST_NULLS_HEAD(ptr, nulls) \
+	((ptr)->first = (struct hlist_nulls_node *) (1UL | (((long)nulls) << 1)))
+
+#define hlist_nulls_entry(ptr, type, member) container_of(ptr,type,member)
+/**
+ * ptr_is_a_nulls - Test if a ptr is a nulls
+ * @ptr: ptr to be tested
+ *
+ */
+static inline int is_a_nulls(const struct hlist_nulls_node *ptr)
+{
+	return ((unsigned long)ptr & 1);
+}
+
+/**
+ * get_nulls_value - Get the 'nulls' value of the end of chain
+ * @ptr: end of chain
+ *
+ * Should be called only if is_a_nulls(ptr);
+ */
+static inline unsigned long get_nulls_value(const struct hlist_nulls_node *ptr)
+{
+	return ((unsigned long)ptr) >> 1;
+}
+
+static inline int hlist_nulls_unhashed(const struct hlist_nulls_node *h)
+{
+	return !h->pprev;
+}
+
+static inline int hlist_nulls_empty(const struct hlist_nulls_head *h)
+{
+	return is_a_nulls(h->first);
+}
+
+static inline void __hlist_nulls_del(struct hlist_nulls_node *n)
+{
+	struct hlist_nulls_node *next = n->next;
+	struct hlist_nulls_node **pprev = n->pprev;
+	*pprev = next;
+	if (!is_a_nulls(next))
+		next->pprev = pprev;
+}
+
+/**
+ * hlist_nulls_for_each_entry	- iterate over list of given type
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct hlist_node to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the hlist_node within the struct.
+ *
+ */
+#define hlist_nulls_for_each_entry(tpos, pos, head, member)		       \
+	for (pos = (head)->first;					       \
+	     (!is_a_nulls(pos)) &&					       \
+		({ tpos = hlist_nulls_entry(pos, typeof(*tpos), member); 1;}); \
+	     pos = pos->next)
+
+/**
+ * hlist_nulls_for_each_entry_from - iterate over a hlist continuing from current point
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct hlist_node to use as a loop cursor.
+ * @member:	the name of the hlist_node within the struct.
+ *
+ */
+#define hlist_nulls_for_each_entry_from(tpos, pos, member)	\
+	for (; (!is_a_nulls(pos)) && 				\
+		({ tpos = hlist_nulls_entry(pos, typeof(*tpos), member); 1;}); \
+	     pos = pos->next)
+
+#endif
diff --git a/include/linux/lockd/bind.h b/include/linux/lockd/bind.h
index e5872dc994c0..fbc48f898521 100644
--- a/include/linux/lockd/bind.h
+++ b/include/linux/lockd/bind.h
@@ -41,6 +41,7 @@ struct nlmclnt_initdata {
 	size_t			addrlen;
 	unsigned short		protocol;
 	u32			nfs_version;
+	int			noresvport;
 };
 
 /*
diff --git a/include/linux/lockd/lockd.h b/include/linux/lockd/lockd.h
index b56d5aa9b194..23da3fa69efa 100644
--- a/include/linux/lockd/lockd.h
+++ b/include/linux/lockd/lockd.h
@@ -49,6 +49,7 @@ struct nlm_host {
 	unsigned short		h_proto;	/* transport proto */
 	unsigned short		h_reclaiming : 1,
 				h_server     : 1, /* server side, not client side */
+				h_noresvport : 1,
 				h_inuse      : 1;
 	wait_queue_head_t	h_gracewait;	/* wait while reclaiming */
 	struct rw_semaphore	h_rwsem;	/* Reboot recovery lock */
@@ -220,7 +221,8 @@ struct nlm_host  *nlmclnt_lookup_host(const struct sockaddr *sap,
 					const size_t salen,
 					const unsigned short protocol,
 					const u32 version,
-					const char *hostname);
+					const char *hostname,
+					int noresvport);
 struct nlm_host  *nlmsvc_lookup_host(const struct svc_rqst *rqstp,
 					const char *hostname,
 					const size_t hostname_len);
diff --git a/include/linux/lockdep.h b/include/linux/lockdep.h
index 331e5f1c2d8e..23bf02fb124f 100644
--- a/include/linux/lockdep.h
+++ b/include/linux/lockdep.h
@@ -73,6 +73,8 @@ struct lock_class_key {
 	struct lockdep_subclass_key	subkeys[MAX_LOCKDEP_SUBCLASSES];
 };
 
+#define LOCKSTAT_POINTS		4
+
 /*
  * The lock-class itself:
  */
@@ -119,7 +121,8 @@ struct lock_class {
 	int				name_version;
 
 #ifdef CONFIG_LOCK_STAT
-	unsigned long			contention_point[4];
+	unsigned long			contention_point[LOCKSTAT_POINTS];
+	unsigned long			contending_point[LOCKSTAT_POINTS];
 #endif
 };
 
@@ -144,6 +147,7 @@ enum bounce_type {
 
 struct lock_class_stats {
 	unsigned long			contention_point[4];
+	unsigned long			contending_point[4];
 	struct lock_time		read_waittime;
 	struct lock_time		write_waittime;
 	struct lock_time		read_holdtime;
@@ -165,6 +169,7 @@ struct lockdep_map {
 	const char			*name;
 #ifdef CONFIG_LOCK_STAT
 	int				cpu;
+	unsigned long			ip;
 #endif
 };
 
@@ -309,8 +314,15 @@ extern void lock_acquire(struct lockdep_map *lock, unsigned int subclass,
 extern void lock_release(struct lockdep_map *lock, int nested,
 			 unsigned long ip);
 
-extern void lock_set_subclass(struct lockdep_map *lock, unsigned int subclass,
-			      unsigned long ip);
+extern void lock_set_class(struct lockdep_map *lock, const char *name,
+			   struct lock_class_key *key, unsigned int subclass,
+			   unsigned long ip);
+
+static inline void lock_set_subclass(struct lockdep_map *lock,
+		unsigned int subclass, unsigned long ip)
+{
+	lock_set_class(lock, lock->name, lock->key, subclass, ip);
+}
 
 # define INIT_LOCKDEP				.lockdep_recursion = 0,
 
@@ -328,13 +340,15 @@ static inline void lockdep_on(void)
 
 # define lock_acquire(l, s, t, r, c, n, i)	do { } while (0)
 # define lock_release(l, n, i)			do { } while (0)
+# define lock_set_class(l, n, k, s, i)		do { } while (0)
 # define lock_set_subclass(l, s, i)		do { } while (0)
 # define lockdep_init()				do { } while (0)
 # define lockdep_info()				do { } while (0)
-# define lockdep_init_map(lock, name, key, sub)	do { (void)(key); } while (0)
+# define lockdep_init_map(lock, name, key, sub) \
+		do { (void)(name); (void)(key); } while (0)
 # define lockdep_set_class(lock, key)		do { (void)(key); } while (0)
 # define lockdep_set_class_and_name(lock, key, name) \
-		do { (void)(key); } while (0)
+		do { (void)(key); (void)(name); } while (0)
 #define lockdep_set_class_and_subclass(lock, key, sub) \
 		do { (void)(key); } while (0)
 #define lockdep_set_subclass(lock, sub)		do { } while (0)
@@ -355,7 +369,7 @@ struct lock_class_key { };
 #ifdef CONFIG_LOCK_STAT
 
 extern void lock_contended(struct lockdep_map *lock, unsigned long ip);
-extern void lock_acquired(struct lockdep_map *lock);
+extern void lock_acquired(struct lockdep_map *lock, unsigned long ip);
 
 #define LOCK_CONTENDED(_lock, try, lock)			\
 do {								\
@@ -363,20 +377,20 @@ do {								\
 		lock_contended(&(_lock)->dep_map, _RET_IP_);	\
 		lock(_lock);					\
 	}							\
-	lock_acquired(&(_lock)->dep_map);			\
+	lock_acquired(&(_lock)->dep_map, _RET_IP_);			\
 } while (0)
 
 #else /* CONFIG_LOCK_STAT */
 
 #define lock_contended(lockdep_map, ip) do {} while (0)
-#define lock_acquired(lockdep_map) do {} while (0)
+#define lock_acquired(lockdep_map, ip) do {} while (0)
 
 #define LOCK_CONTENDED(_lock, try, lock) \
 	lock(_lock)
 
 #endif /* CONFIG_LOCK_STAT */
 
-#if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_GENERIC_HARDIRQS)
+#ifdef CONFIG_GENERIC_HARDIRQS
 extern void early_init_irq_lock_class(void);
 #else
 static inline void early_init_irq_lock_class(void)
@@ -480,4 +494,22 @@ static inline void print_irqtrace_events(struct task_struct *curr)
 # define lock_map_release(l)			do { } while (0)
 #endif
 
+#ifdef CONFIG_PROVE_LOCKING
+# define might_lock(lock) 						\
+do {									\
+	typecheck(struct lockdep_map *, &(lock)->dep_map);		\
+	lock_acquire(&(lock)->dep_map, 0, 0, 0, 2, NULL, _THIS_IP_);	\
+	lock_release(&(lock)->dep_map, 0, _THIS_IP_);			\
+} while (0)
+# define might_lock_read(lock) 						\
+do {									\
+	typecheck(struct lockdep_map *, &(lock)->dep_map);		\
+	lock_acquire(&(lock)->dep_map, 0, 0, 1, 2, NULL, _THIS_IP_);	\
+	lock_release(&(lock)->dep_map, 0, _THIS_IP_);			\
+} while (0)
+#else
+# define might_lock(lock) do { } while (0)
+# define might_lock_read(lock) do { } while (0)
+#endif
+
 #endif /* __LINUX_LOCKDEP_H */
diff --git a/include/linux/map_to_7segment.h b/include/linux/map_to_7segment.h
new file mode 100644
index 000000000000..7df8432c4402
--- /dev/null
+++ b/include/linux/map_to_7segment.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2005 Henk Vergonet <Henk.Vergonet@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef MAP_TO_7SEGMENT_H
+#define MAP_TO_7SEGMENT_H
+
+/* This file provides translation primitives and tables for the conversion
+ * of (ASCII) characters to a 7-segments notation.
+ *
+ * The 7 segment's wikipedia notation below is used as standard.
+ * See: http://en.wikipedia.org/wiki/Seven_segment_display
+ *
+ * Notation:	+-a-+
+ *		f   b
+ *		+-g-+
+ *		e   c
+ *		+-d-+
+ *
+ * Usage:
+ *
+ *   Register a map variable, and fill it with a character set:
+ *	static SEG7_DEFAULT_MAP(map_seg7);
+ *
+ *
+ *   Then use for conversion:
+ *	seg7 = map_to_seg7(&map_seg7, some_char);
+ *	...
+ *
+ * In device drivers it is recommended, if required, to make the char map
+ * accessible via the sysfs interface using the following scheme:
+ *
+ * static ssize_t show_map(struct device *dev, char *buf) {
+ *	memcpy(buf, &map_seg7, sizeof(map_seg7));
+ *	return sizeof(map_seg7);
+ * }
+ * static ssize_t store_map(struct device *dev, const char *buf, size_t cnt) {
+ *	if(cnt != sizeof(map_seg7))
+ *		return -EINVAL;
+ *	memcpy(&map_seg7, buf, cnt);
+ *	return cnt;
+ * }
+ * static DEVICE_ATTR(map_seg7, PERMS_RW, show_map, store_map);
+ *
+ * History:
+ * 2005-05-31	RFC linux-kernel@vger.kernel.org
+ */
+#include <linux/errno.h>
+
+
+#define BIT_SEG7_A		0
+#define BIT_SEG7_B		1
+#define BIT_SEG7_C		2
+#define BIT_SEG7_D		3
+#define BIT_SEG7_E		4
+#define BIT_SEG7_F		5
+#define BIT_SEG7_G		6
+#define BIT_SEG7_RESERVED	7
+
+struct seg7_conversion_map {
+	unsigned char	table[128];
+};
+
+static inline int map_to_seg7(struct seg7_conversion_map *map, int c)
+{
+	return c >= 0 && c < sizeof(map->table) ? map->table[c] : -EINVAL;
+}
+
+#define SEG7_CONVERSION_MAP(_name, _map)	\
+	struct seg7_conversion_map _name = { .table = { _map } }
+
+/*
+ * It is recommended to use a facility that allows user space to redefine
+ * custom character sets for LCD devices. Please use a sysfs interface
+ * as described above.
+ */
+#define MAP_TO_SEG7_SYSFS_FILE	"map_seg7"
+
+/*******************************************************************************
+ * ASCII conversion table
+ ******************************************************************************/
+
+#define _SEG7(l,a,b,c,d,e,f,g)	\
+      (	a<<BIT_SEG7_A |	b<<BIT_SEG7_B |	c<<BIT_SEG7_C |	d<<BIT_SEG7_D |	\
+	e<<BIT_SEG7_E |	f<<BIT_SEG7_F |	g<<BIT_SEG7_G )
+
+#define _MAP_0_32_ASCII_SEG7_NON_PRINTABLE	\
+	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+
+#define _MAP_33_47_ASCII_SEG7_SYMBOL		\
+ _SEG7('!',0,0,0,0,1,1,0), _SEG7('"',0,1,0,0,0,1,0), _SEG7('#',0,1,1,0,1,1,0),\
+ _SEG7('$',1,0,1,1,0,1,1), _SEG7('%',0,0,1,0,0,1,0), _SEG7('&',1,0,1,1,1,1,1),\
+ _SEG7('\'',0,0,0,0,0,1,0),_SEG7('(',1,0,0,1,1,1,0), _SEG7(')',1,1,1,1,0,0,0),\
+ _SEG7('*',0,1,1,0,1,1,1), _SEG7('+',0,1,1,0,0,0,1), _SEG7(',',0,0,0,0,1,0,0),\
+ _SEG7('-',0,0,0,0,0,0,1), _SEG7('.',0,0,0,0,1,0,0), _SEG7('/',0,1,0,0,1,0,1),
+
+#define _MAP_48_57_ASCII_SEG7_NUMERIC		\
+ _SEG7('0',1,1,1,1,1,1,0), _SEG7('1',0,1,1,0,0,0,0), _SEG7('2',1,1,0,1,1,0,1),\
+ _SEG7('3',1,1,1,1,0,0,1), _SEG7('4',0,1,1,0,0,1,1), _SEG7('5',1,0,1,1,0,1,1),\
+ _SEG7('6',1,0,1,1,1,1,1), _SEG7('7',1,1,1,0,0,0,0), _SEG7('8',1,1,1,1,1,1,1),\
+ _SEG7('9',1,1,1,1,0,1,1),
+
+#define _MAP_58_64_ASCII_SEG7_SYMBOL		\
+ _SEG7(':',0,0,0,1,0,0,1), _SEG7(';',0,0,0,1,0,0,1), _SEG7('<',1,0,0,0,0,1,1),\
+ _SEG7('=',0,0,0,1,0,0,1), _SEG7('>',1,1,0,0,0,0,1), _SEG7('?',1,1,1,0,0,1,0),\
+ _SEG7('@',1,1,0,1,1,1,1),
+
+#define _MAP_65_90_ASCII_SEG7_ALPHA_UPPR	\
+ _SEG7('A',1,1,1,0,1,1,1), _SEG7('B',1,1,1,1,1,1,1), _SEG7('C',1,0,0,1,1,1,0),\
+ _SEG7('D',1,1,1,1,1,1,0), _SEG7('E',1,0,0,1,1,1,1), _SEG7('F',1,0,0,0,1,1,1),\
+ _SEG7('G',1,1,1,1,0,1,1), _SEG7('H',0,1,1,0,1,1,1), _SEG7('I',0,1,1,0,0,0,0),\
+ _SEG7('J',0,1,1,1,0,0,0), _SEG7('K',0,1,1,0,1,1,1), _SEG7('L',0,0,0,1,1,1,0),\
+ _SEG7('M',1,1,1,0,1,1,0), _SEG7('N',1,1,1,0,1,1,0), _SEG7('O',1,1,1,1,1,1,0),\
+ _SEG7('P',1,1,0,0,1,1,1), _SEG7('Q',1,1,1,1,1,1,0), _SEG7('R',1,1,1,0,1,1,1),\
+ _SEG7('S',1,0,1,1,0,1,1), _SEG7('T',0,0,0,1,1,1,1), _SEG7('U',0,1,1,1,1,1,0),\
+ _SEG7('V',0,1,1,1,1,1,0), _SEG7('W',0,1,1,1,1,1,1), _SEG7('X',0,1,1,0,1,1,1),\
+ _SEG7('Y',0,1,1,0,0,1,1), _SEG7('Z',1,1,0,1,1,0,1),
+
+#define _MAP_91_96_ASCII_SEG7_SYMBOL		\
+ _SEG7('[',1,0,0,1,1,1,0), _SEG7('\\',0,0,1,0,0,1,1),_SEG7(']',1,1,1,1,0,0,0),\
+ _SEG7('^',1,1,0,0,0,1,0), _SEG7('_',0,0,0,1,0,0,0), _SEG7('`',0,1,0,0,0,0,0),
+
+#define _MAP_97_122_ASCII_SEG7_ALPHA_LOWER	\
+ _SEG7('A',1,1,1,0,1,1,1), _SEG7('b',0,0,1,1,1,1,1), _SEG7('c',0,0,0,1,1,0,1),\
+ _SEG7('d',0,1,1,1,1,0,1), _SEG7('E',1,0,0,1,1,1,1), _SEG7('F',1,0,0,0,1,1,1),\
+ _SEG7('G',1,1,1,1,0,1,1), _SEG7('h',0,0,1,0,1,1,1), _SEG7('i',0,0,1,0,0,0,0),\
+ _SEG7('j',0,0,1,1,0,0,0), _SEG7('k',0,0,1,0,1,1,1), _SEG7('L',0,0,0,1,1,1,0),\
+ _SEG7('M',1,1,1,0,1,1,0), _SEG7('n',0,0,1,0,1,0,1), _SEG7('o',0,0,1,1,1,0,1),\
+ _SEG7('P',1,1,0,0,1,1,1), _SEG7('q',1,1,1,0,0,1,1), _SEG7('r',0,0,0,0,1,0,1),\
+ _SEG7('S',1,0,1,1,0,1,1), _SEG7('T',0,0,0,1,1,1,1), _SEG7('u',0,0,1,1,1,0,0),\
+ _SEG7('v',0,0,1,1,1,0,0), _SEG7('W',0,1,1,1,1,1,1), _SEG7('X',0,1,1,0,1,1,1),\
+ _SEG7('y',0,1,1,1,0,1,1), _SEG7('Z',1,1,0,1,1,0,1),
+
+#define _MAP_123_126_ASCII_SEG7_SYMBOL		\
+ _SEG7('{',1,0,0,1,1,1,0), _SEG7('|',0,0,0,0,1,1,0), _SEG7('}',1,1,1,1,0,0,0),\
+ _SEG7('~',1,0,0,0,0,0,0),
+
+/* Maps */
+
+/* This set tries to map as close as possible to the visible characteristics
+ * of the ASCII symbol, lowercase and uppercase letters may differ in
+ * presentation on the display.
+ */
+#define MAP_ASCII7SEG_ALPHANUM			\
+	_MAP_0_32_ASCII_SEG7_NON_PRINTABLE	\
+	_MAP_33_47_ASCII_SEG7_SYMBOL		\
+	_MAP_48_57_ASCII_SEG7_NUMERIC		\
+	_MAP_58_64_ASCII_SEG7_SYMBOL		\
+	_MAP_65_90_ASCII_SEG7_ALPHA_UPPR	\
+	_MAP_91_96_ASCII_SEG7_SYMBOL		\
+	_MAP_97_122_ASCII_SEG7_ALPHA_LOWER	\
+	_MAP_123_126_ASCII_SEG7_SYMBOL
+
+/* This set tries to map as close as possible to the symbolic characteristics
+ * of the ASCII character for maximum discrimination.
+ * For now this means all alpha chars are in lower case representations.
+ * (This for example facilitates the use of hex numbers with uppercase input.)
+ */
+#define MAP_ASCII7SEG_ALPHANUM_LC			\
+	_MAP_0_32_ASCII_SEG7_NON_PRINTABLE	\
+	_MAP_33_47_ASCII_SEG7_SYMBOL		\
+	_MAP_48_57_ASCII_SEG7_NUMERIC		\
+	_MAP_58_64_ASCII_SEG7_SYMBOL		\
+	_MAP_97_122_ASCII_SEG7_ALPHA_LOWER	\
+	_MAP_91_96_ASCII_SEG7_SYMBOL		\
+	_MAP_97_122_ASCII_SEG7_ALPHA_LOWER	\
+	_MAP_123_126_ASCII_SEG7_SYMBOL
+
+#define SEG7_DEFAULT_MAP(_name)		\
+	SEG7_CONVERSION_MAP(_name,MAP_ASCII7SEG_ALPHANUM)
+
+#endif	/* MAP_TO_7SEGMENT_H */
+
diff --git a/include/linux/marker.h b/include/linux/marker.h
index 1290653f9241..b85e74ca782f 100644
--- a/include/linux/marker.h
+++ b/include/linux/marker.h
@@ -12,6 +12,7 @@
  * See the file COPYING for more details.
  */
 
+#include <stdarg.h>
 #include <linux/types.h>
 
 struct module;
@@ -48,10 +49,28 @@ struct marker {
 	void (*call)(const struct marker *mdata, void *call_private, ...);
 	struct marker_probe_closure single;
 	struct marker_probe_closure *multi;
+	const char *tp_name;	/* Optional tracepoint name */
+	void *tp_cb;		/* Optional tracepoint callback */
 } __attribute__((aligned(8)));
 
 #ifdef CONFIG_MARKERS
 
+#define _DEFINE_MARKER(name, tp_name_str, tp_cb, format)		\
+		static const char __mstrtab_##name[]			\
+		__attribute__((section("__markers_strings")))		\
+		= #name "\0" format;					\
+		static struct marker __mark_##name			\
+		__attribute__((section("__markers"), aligned(8))) =	\
+		{ __mstrtab_##name, &__mstrtab_##name[sizeof(#name)],	\
+		  0, 0, marker_probe_cb, { __mark_empty_function, NULL},\
+		  NULL, tp_name_str, tp_cb }
+
+#define DEFINE_MARKER(name, format)					\
+		_DEFINE_MARKER(name, NULL, NULL, format)
+
+#define DEFINE_MARKER_TP(name, tp_name, tp_cb, format)			\
+		_DEFINE_MARKER(name, #tp_name, tp_cb, format)
+
 /*
  * Note : the empty asm volatile with read constraint is used here instead of a
  * "used" attribute to fix a gcc 4.1.x bug.
@@ -65,14 +84,7 @@ struct marker {
  */
 #define __trace_mark(generic, name, call_private, format, args...)	\
 	do {								\
-		static const char __mstrtab_##name[]			\
-		__attribute__((section("__markers_strings")))		\
-		= #name "\0" format;					\
-		static struct marker __mark_##name			\
-		__attribute__((section("__markers"), aligned(8))) =	\
-		{ __mstrtab_##name, &__mstrtab_##name[sizeof(#name)],	\
-		0, 0, marker_probe_cb,					\
-		{ __mark_empty_function, NULL}, NULL };			\
+		DEFINE_MARKER(name, format);				\
 		__mark_check_format(format, ## args);			\
 		if (unlikely(__mark_##name.state)) {			\
 			(*__mark_##name.call)				\
@@ -80,14 +92,39 @@ struct marker {
 		}							\
 	} while (0)
 
+#define __trace_mark_tp(name, call_private, tp_name, tp_cb, format, args...) \
+	do {								\
+		void __check_tp_type(void)				\
+		{							\
+			register_trace_##tp_name(tp_cb);		\
+		}							\
+		DEFINE_MARKER_TP(name, tp_name, tp_cb, format);		\
+		__mark_check_format(format, ## args);			\
+		(*__mark_##name.call)(&__mark_##name, call_private,	\
+					## args);			\
+	} while (0)
+
 extern void marker_update_probe_range(struct marker *begin,
 	struct marker *end);
+
+#define GET_MARKER(name)	(__mark_##name)
+
 #else /* !CONFIG_MARKERS */
+#define DEFINE_MARKER(name, tp_name, tp_cb, format)
 #define __trace_mark(generic, name, call_private, format, args...) \
 		__mark_check_format(format, ## args)
+#define __trace_mark_tp(name, call_private, tp_name, tp_cb, format, args...) \
+	do {								\
+		void __check_tp_type(void)				\
+		{							\
+			register_trace_##tp_name(tp_cb);		\
+		}							\
+		__mark_check_format(format, ## args);			\
+	} while (0)
 static inline void marker_update_probe_range(struct marker *begin,
 	struct marker *end)
 { }
+#define GET_MARKER(name)
 #endif /* CONFIG_MARKERS */
 
 /**
@@ -117,6 +154,20 @@ static inline void marker_update_probe_range(struct marker *begin,
 	__trace_mark(1, name, NULL, format, ## args)
 
 /**
+ * trace_mark_tp - Marker in a tracepoint callback
+ * @name: marker name, not quoted.
+ * @tp_name: tracepoint name, not quoted.
+ * @tp_cb: tracepoint callback. Should have an associated global symbol so it
+ *         is not optimized away by the compiler (should not be static).
+ * @format: format string
+ * @args...: variable argument list
+ *
+ * Places a marker in a tracepoint callback.
+ */
+#define trace_mark_tp(name, tp_name, tp_cb, format, args...)	\
+	__trace_mark_tp(name, NULL, tp_name, tp_cb, format, ## args)
+
+/**
  * MARK_NOARGS - Format string for a marker with no argument.
  */
 #define MARK_NOARGS " "
@@ -136,8 +187,6 @@ extern marker_probe_func __mark_empty_function;
 
 extern void marker_probe_cb(const struct marker *mdata,
 	void *call_private, ...);
-extern void marker_probe_cb_noarg(const struct marker *mdata,
-	void *call_private, ...);
 
 /*
  * Connect a probe to a marker.
@@ -160,4 +209,13 @@ extern int marker_probe_unregister_private_data(marker_probe_func *probe,
 extern void *marker_get_private_data(const char *name, marker_probe_func *probe,
 	int num);
 
+/*
+ * marker_synchronize_unregister must be called between the last marker probe
+ * unregistration and the first one of
+ * - the end of module exit function
+ * - the free of any resource used by the probes
+ * to ensure the code and data are valid for any possibly running probes.
+ */
+#define marker_synchronize_unregister() synchronize_sched()
+
 #endif
diff --git a/include/linux/mdio-gpio.h b/include/linux/mdio-gpio.h
new file mode 100644
index 000000000000..e9d3fdfe41d7
--- /dev/null
+++ b/include/linux/mdio-gpio.h
@@ -0,0 +1,25 @@
+/*
+ * MDIO-GPIO bus platform data structures
+ *
+ * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __LINUX_MDIO_GPIO_H
+#define __LINUX_MDIO_GPIO_H
+
+#include <linux/mdio-bitbang.h>
+
+struct mdio_gpio_platform_data {
+	/* GPIO numbers for bus pins */
+	unsigned int mdc;
+	unsigned int mdio;
+
+	unsigned int phy_mask;
+	int irqs[PHY_MAX_ADDR];
+};
+
+#endif /* __LINUX_MDIO_GPIO_H */
diff --git a/include/linux/memcontrol.h b/include/linux/memcontrol.h
index fdf3967e1397..1fbe14d39521 100644
--- a/include/linux/memcontrol.h
+++ b/include/linux/memcontrol.h
@@ -27,16 +27,13 @@ struct mm_struct;
 
 #ifdef CONFIG_CGROUP_MEM_RES_CTLR
 
-#define page_reset_bad_cgroup(page)	((page)->page_cgroup = 0)
-
-extern struct page_cgroup *page_get_page_cgroup(struct page *page);
 extern int mem_cgroup_charge(struct page *page, struct mm_struct *mm,
 				gfp_t gfp_mask);
 extern int mem_cgroup_cache_charge(struct page *page, struct mm_struct *mm,
 					gfp_t gfp_mask);
+extern void mem_cgroup_move_lists(struct page *page, enum lru_list lru);
 extern void mem_cgroup_uncharge_page(struct page *page);
 extern void mem_cgroup_uncharge_cache_page(struct page *page);
-extern void mem_cgroup_move_lists(struct page *page, bool active);
 extern int mem_cgroup_shrink_usage(struct mm_struct *mm, gfp_t gfp_mask);
 
 extern unsigned long mem_cgroup_isolate_pages(unsigned long nr_to_scan,
@@ -44,7 +41,7 @@ extern unsigned long mem_cgroup_isolate_pages(unsigned long nr_to_scan,
 					unsigned long *scanned, int order,
 					int mode, struct zone *z,
 					struct mem_cgroup *mem_cont,
-					int active);
+					int active, int file);
 extern void mem_cgroup_out_of_memory(struct mem_cgroup *mem, gfp_t gfp_mask);
 int task_in_mem_cgroup(struct task_struct *task, const struct mem_cgroup *mem);
 
@@ -69,21 +66,11 @@ extern void mem_cgroup_note_reclaim_priority(struct mem_cgroup *mem,
 extern void mem_cgroup_record_reclaim_priority(struct mem_cgroup *mem,
 							int priority);
 
-extern long mem_cgroup_calc_reclaim_active(struct mem_cgroup *mem,
-				struct zone *zone, int priority);
-extern long mem_cgroup_calc_reclaim_inactive(struct mem_cgroup *mem,
-				struct zone *zone, int priority);
-
-#else /* CONFIG_CGROUP_MEM_RES_CTLR */
-static inline void page_reset_bad_cgroup(struct page *page)
-{
-}
+extern long mem_cgroup_calc_reclaim(struct mem_cgroup *mem, struct zone *zone,
+					int priority, enum lru_list lru);
 
-static inline struct page_cgroup *page_get_page_cgroup(struct page *page)
-{
-	return NULL;
-}
 
+#else /* CONFIG_CGROUP_MEM_RES_CTLR */
 static inline int mem_cgroup_charge(struct page *page,
 					struct mm_struct *mm, gfp_t gfp_mask)
 {
@@ -159,14 +146,9 @@ static inline void mem_cgroup_record_reclaim_priority(struct mem_cgroup *mem,
 {
 }
 
-static inline long mem_cgroup_calc_reclaim_active(struct mem_cgroup *mem,
-					struct zone *zone, int priority)
-{
-	return 0;
-}
-
-static inline long mem_cgroup_calc_reclaim_inactive(struct mem_cgroup *mem,
-					struct zone *zone, int priority)
+static inline long mem_cgroup_calc_reclaim(struct mem_cgroup *mem,
+					struct zone *zone, int priority,
+					enum lru_list lru)
 {
 	return 0;
 }
diff --git a/include/linux/memory.h b/include/linux/memory.h
index 2f5f8a5ef2a0..36c82c9e6ea7 100644
--- a/include/linux/memory.h
+++ b/include/linux/memory.h
@@ -91,7 +91,7 @@ extern int memory_notify(unsigned long val, void *v);
 
 #ifdef CONFIG_MEMORY_HOTPLUG
 #define hotplug_memory_notifier(fn, pri) {			\
-	static struct notifier_block fn##_mem_nb =		\
+	static __meminitdata struct notifier_block fn##_mem_nb =\
 		{ .notifier_call = fn, .priority = pri };	\
 	register_memory_notifier(&fn##_mem_nb);			\
 }
diff --git a/include/linux/mfd/da903x.h b/include/linux/mfd/da903x.h
new file mode 100644
index 000000000000..cad314c12439
--- /dev/null
+++ b/include/linux/mfd/da903x.h
@@ -0,0 +1,201 @@
+#ifndef __LINUX_PMIC_DA903X_H
+#define __LINUX_PMIC_DA903X_H
+
+/* Unified sub device IDs for DA9030/DA9034 */
+enum {
+	DA9030_ID_LED_1,
+	DA9030_ID_LED_2,
+	DA9030_ID_LED_3,
+	DA9030_ID_LED_4,
+	DA9030_ID_LED_PC,
+	DA9030_ID_VIBRA,
+	DA9030_ID_WLED,
+	DA9030_ID_BUCK1,
+	DA9030_ID_BUCK2,
+	DA9030_ID_LDO1,
+	DA9030_ID_LDO2,
+	DA9030_ID_LDO3,
+	DA9030_ID_LDO4,
+	DA9030_ID_LDO5,
+	DA9030_ID_LDO6,
+	DA9030_ID_LDO7,
+	DA9030_ID_LDO8,
+	DA9030_ID_LDO9,
+	DA9030_ID_LDO10,
+	DA9030_ID_LDO11,
+	DA9030_ID_LDO12,
+	DA9030_ID_LDO13,
+	DA9030_ID_LDO14,
+	DA9030_ID_LDO15,
+	DA9030_ID_LDO16,
+	DA9030_ID_LDO17,
+	DA9030_ID_LDO18,
+	DA9030_ID_LDO19,
+	DA9030_ID_LDO_INT,	/* LDO Internal */
+
+	DA9034_ID_LED_1,
+	DA9034_ID_LED_2,
+	DA9034_ID_VIBRA,
+	DA9034_ID_WLED,
+	DA9034_ID_TOUCH,
+
+	DA9034_ID_BUCK1,
+	DA9034_ID_BUCK2,
+	DA9034_ID_LDO1,
+	DA9034_ID_LDO2,
+	DA9034_ID_LDO3,
+	DA9034_ID_LDO4,
+	DA9034_ID_LDO5,
+	DA9034_ID_LDO6,
+	DA9034_ID_LDO7,
+	DA9034_ID_LDO8,
+	DA9034_ID_LDO9,
+	DA9034_ID_LDO10,
+	DA9034_ID_LDO11,
+	DA9034_ID_LDO12,
+	DA9034_ID_LDO13,
+	DA9034_ID_LDO14,
+	DA9034_ID_LDO15,
+};
+
+/*
+ * DA9030/DA9034 LEDs sub-devices uses generic "struct led_info"
+ * as the platform_data
+ */
+
+/* DA9030 flags for "struct led_info"
+ */
+#define DA9030_LED_RATE_ON	(0 << 5)
+#define DA9030_LED_RATE_052S	(1 << 5)
+#define DA9030_LED_DUTY_1_16	(0 << 3)
+#define DA9030_LED_DUTY_1_8	(1 << 3)
+#define DA9030_LED_DUTY_1_4	(2 << 3)
+#define DA9030_LED_DUTY_1_2	(3 << 3)
+
+#define DA9030_VIBRA_MODE_1P3V	(0 << 1)
+#define DA9030_VIBRA_MODE_2P7V	(1 << 1)
+#define DA9030_VIBRA_FREQ_1HZ	(0 << 2)
+#define DA9030_VIBRA_FREQ_2HZ	(1 << 2)
+#define DA9030_VIBRA_FREQ_4HZ	(2 << 2)
+#define DA9030_VIBRA_FREQ_8HZ	(3 << 2)
+#define DA9030_VIBRA_DUTY_ON	(0 << 4)
+#define DA9030_VIBRA_DUTY_75P	(1 << 4)
+#define DA9030_VIBRA_DUTY_50P	(2 << 4)
+#define DA9030_VIBRA_DUTY_25P	(3 << 4)
+
+/* DA9034 flags for "struct led_info" */
+#define DA9034_LED_RAMP		(1 << 7)
+
+/* DA9034 touch screen platform data */
+struct da9034_touch_pdata {
+	int	interval_ms;	/* sampling interval while pen down */
+	int	x_inverted;
+	int	y_inverted;
+};
+
+struct da903x_subdev_info {
+	int		id;
+	const char	*name;
+	void		*platform_data;
+};
+
+struct da903x_platform_data {
+	int num_subdevs;
+	struct da903x_subdev_info *subdevs;
+};
+
+/* bit definitions for DA9030 events */
+#define DA9030_EVENT_ONKEY		(1 << 0)
+#define	DA9030_EVENT_PWREN		(1 << 1)
+#define	DA9030_EVENT_EXTON		(1 << 2)
+#define	DA9030_EVENT_CHDET		(1 << 3)
+#define	DA9030_EVENT_TBAT		(1 << 4)
+#define	DA9030_EVENT_VBATMON		(1 << 5)
+#define	DA9030_EVENT_VBATMON_TXON	(1 << 6)
+#define	DA9030_EVENT_CHIOVER		(1 << 7)
+#define	DA9030_EVENT_TCTO		(1 << 8)
+#define	DA9030_EVENT_CCTO		(1 << 9)
+#define	DA9030_EVENT_ADC_READY		(1 << 10)
+#define	DA9030_EVENT_VBUS_4P4		(1 << 11)
+#define	DA9030_EVENT_VBUS_4P0		(1 << 12)
+#define	DA9030_EVENT_SESS_VALID		(1 << 13)
+#define	DA9030_EVENT_SRP_DETECT		(1 << 14)
+#define	DA9030_EVENT_WATCHDOG		(1 << 15)
+#define	DA9030_EVENT_LDO15		(1 << 16)
+#define	DA9030_EVENT_LDO16		(1 << 17)
+#define	DA9030_EVENT_LDO17		(1 << 18)
+#define	DA9030_EVENT_LDO18		(1 << 19)
+#define	DA9030_EVENT_LDO19		(1 << 20)
+#define	DA9030_EVENT_BUCK2		(1 << 21)
+
+/* bit definitions for DA9034 events */
+#define DA9034_EVENT_ONKEY		(1 << 0)
+#define DA9034_EVENT_EXTON		(1 << 2)
+#define DA9034_EVENT_CHDET		(1 << 3)
+#define DA9034_EVENT_TBAT		(1 << 4)
+#define DA9034_EVENT_VBATMON		(1 << 5)
+#define DA9034_EVENT_REV_IOVER		(1 << 6)
+#define DA9034_EVENT_CH_IOVER		(1 << 7)
+#define DA9034_EVENT_CH_TCTO		(1 << 8)
+#define DA9034_EVENT_CH_CCTO		(1 << 9)
+#define DA9034_EVENT_USB_DEV		(1 << 10)
+#define DA9034_EVENT_OTGCP_IOVER	(1 << 11)
+#define DA9034_EVENT_VBUS_4P55		(1 << 12)
+#define DA9034_EVENT_VBUS_3P8		(1 << 13)
+#define DA9034_EVENT_SESS_1P8		(1 << 14)
+#define DA9034_EVENT_SRP_READY		(1 << 15)
+#define DA9034_EVENT_ADC_MAN		(1 << 16)
+#define DA9034_EVENT_ADC_AUTO4		(1 << 17)
+#define DA9034_EVENT_ADC_AUTO5		(1 << 18)
+#define DA9034_EVENT_ADC_AUTO6		(1 << 19)
+#define DA9034_EVENT_PEN_DOWN		(1 << 20)
+#define DA9034_EVENT_TSI_READY		(1 << 21)
+#define DA9034_EVENT_UART_TX		(1 << 22)
+#define DA9034_EVENT_UART_RX		(1 << 23)
+#define DA9034_EVENT_HEADSET		(1 << 25)
+#define DA9034_EVENT_HOOKSWITCH		(1 << 26)
+#define DA9034_EVENT_WATCHDOG		(1 << 27)
+
+extern int da903x_register_notifier(struct device *dev,
+		struct notifier_block *nb, unsigned int events);
+extern int da903x_unregister_notifier(struct device *dev,
+		struct notifier_block *nb, unsigned int events);
+
+/* Status Query Interface */
+#define DA9030_STATUS_ONKEY		(1 << 0)
+#define DA9030_STATUS_PWREN1		(1 << 1)
+#define DA9030_STATUS_EXTON		(1 << 2)
+#define DA9030_STATUS_CHDET		(1 << 3)
+#define DA9030_STATUS_TBAT		(1 << 4)
+#define DA9030_STATUS_VBATMON		(1 << 5)
+#define DA9030_STATUS_VBATMON_TXON	(1 << 6)
+#define DA9030_STATUS_MCLKDET		(1 << 7)
+
+#define DA9034_STATUS_ONKEY		(1 << 0)
+#define DA9034_STATUS_EXTON		(1 << 2)
+#define DA9034_STATUS_CHDET		(1 << 3)
+#define DA9034_STATUS_TBAT		(1 << 4)
+#define DA9034_STATUS_VBATMON		(1 << 5)
+#define DA9034_STATUS_PEN_DOWN		(1 << 6)
+#define DA9034_STATUS_MCLKDET		(1 << 7)
+#define DA9034_STATUS_USB_DEV		(1 << 8)
+#define DA9034_STATUS_HEADSET		(1 << 9)
+#define DA9034_STATUS_HOOKSWITCH	(1 << 10)
+#define DA9034_STATUS_REMCON		(1 << 11)
+#define DA9034_STATUS_VBUS_VALID_4P55	(1 << 12)
+#define DA9034_STATUS_VBUS_VALID_3P8	(1 << 13)
+#define DA9034_STATUS_SESS_VALID_1P8	(1 << 14)
+#define DA9034_STATUS_SRP_READY		(1 << 15)
+
+extern int da903x_query_status(struct device *dev, unsigned int status);
+
+
+/* NOTE: the two functions below are not intended for use outside
+ * of the DA9034 sub-device drivers
+ */
+extern int da903x_write(struct device *dev, int reg, uint8_t val);
+extern int da903x_read(struct device *dev, int reg, uint8_t *val);
+extern int da903x_update(struct device *dev, int reg, uint8_t val, uint8_t mask);
+extern int da903x_set_bits(struct device *dev, int reg, uint8_t bit_mask);
+extern int da903x_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
+#endif /* __LINUX_PMIC_DA903X_H */
diff --git a/include/linux/mfd/t7l66xb.h b/include/linux/mfd/t7l66xb.h
index e83c7f2036f9..b4629818aea5 100644
--- a/include/linux/mfd/t7l66xb.h
+++ b/include/linux/mfd/t7l66xb.h
@@ -15,8 +15,6 @@
 #include <linux/mfd/tmio.h>
 
 struct t7l66xb_platform_data {
-	int (*enable_clk32k)(struct platform_device *dev);
-	void (*disable_clk32k)(struct platform_device *dev);
 	int (*enable)(struct platform_device *dev);
 	int (*disable)(struct platform_device *dev);
 	int (*suspend)(struct platform_device *dev);
diff --git a/include/linux/mfd/tc6387xb.h b/include/linux/mfd/tc6387xb.h
index fa06e0610b8e..b4888209494a 100644
--- a/include/linux/mfd/tc6387xb.h
+++ b/include/linux/mfd/tc6387xb.h
@@ -11,9 +11,6 @@
 #define MFD_TC6387XB_H
 
 struct tc6387xb_platform_data {
-	int (*enable_clk32k)(struct platform_device *dev);
-	void (*disable_clk32k)(struct platform_device *dev);
-
 	int (*enable)(struct platform_device *dev);
 	int (*disable)(struct platform_device *dev);
 	int (*suspend)(struct platform_device *dev);
diff --git a/include/linux/mfd/tc6393xb.h b/include/linux/mfd/tc6393xb.h
index fec7b3f7a81f..626e448205c5 100644
--- a/include/linux/mfd/tc6393xb.h
+++ b/include/linux/mfd/tc6393xb.h
@@ -17,12 +17,12 @@
 #ifndef MFD_TC6393XB_H
 #define MFD_TC6393XB_H
 
+#include <linux/fb.h>
+
 /* Also one should provide the CK3P6MI clock */
 struct tc6393xb_platform_data {
 	u16	scr_pll2cr;	/* PLL2 Control */
 	u16	scr_gper;	/* GP Enable */
-	u32	scr_gpo_doecr;	/* GPO Data OE Control */
-	u32	scr_gpo_dsr;	/* GPO Data Set */
 
 	int	(*enable)(struct platform_device *dev);
 	int	(*disable)(struct platform_device *dev);
@@ -31,15 +31,28 @@ struct tc6393xb_platform_data {
 
 	int	irq_base;	/* base for subdevice irqs */
 	int	gpio_base;
+	int	(*setup)(struct platform_device *dev);
+	void	(*teardown)(struct platform_device *dev);
 
 	struct tmio_nand_data	*nand_data;
+	struct tmio_fb_data	*fb_data;
+
+	unsigned resume_restore : 1; /* make special actions
+					to preserve the state
+					on suspend/resume */
 };
 
+extern int tc6393xb_lcd_mode(struct platform_device *fb,
+			     const struct fb_videomode *mode);
+extern int tc6393xb_lcd_set_power(struct platform_device *fb, bool on);
+
 /*
  * Relative to irq_base
  */
 #define	IRQ_TC6393_NAND		0
 #define	IRQ_TC6393_MMC		1
+#define	IRQ_TC6393_OHCI		2
+#define	IRQ_TC6393_FB		4
 
 #define	TC6393XB_NR_IRQS	8
 
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index ec612e66391c..516d955ab8a1 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -1,6 +1,8 @@
 #ifndef MFD_TMIO_H
 #define MFD_TMIO_H
 
+#include <linux/fb.h>
+
 #define tmio_ioread8(addr) readb(addr)
 #define tmio_ioread16(addr) readw(addr)
 #define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
@@ -25,4 +27,21 @@ struct tmio_nand_data {
 	unsigned int		num_partitions;
 };
 
+#define FBIO_TMIO_ACC_WRITE	0x7C639300
+#define FBIO_TMIO_ACC_SYNC	0x7C639301
+
+struct tmio_fb_data {
+	int			(*lcd_set_power)(struct platform_device *fb_dev,
+								bool on);
+	int			(*lcd_mode)(struct platform_device *fb_dev,
+					const struct fb_videomode *mode);
+	int			num_modes;
+	struct fb_videomode	*modes;
+
+	/* in mm: size of screen */
+	int			height;
+	int			width;
+};
+
+
 #endif
diff --git a/include/linux/mfd/wm8350/audio.h b/include/linux/mfd/wm8350/audio.h
index 217bb22ebb8e..af95a1d2f3a1 100644
--- a/include/linux/mfd/wm8350/audio.h
+++ b/include/linux/mfd/wm8350/audio.h
@@ -1,7 +1,7 @@
 /*
  * audio.h  --  Audio Driver for Wolfson WM8350 PMIC
  *
- * Copyright 2007 Wolfson Microelectronics PLC
+ * Copyright 2007, 2008 Wolfson Microelectronics PLC
  *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
@@ -70,9 +70,9 @@
 #define WM8350_CODEC_ISEL_0_5                   3	/* x0.5 */
 
 #define WM8350_VMID_OFF                         0
-#define WM8350_VMID_500K                        1
-#define WM8350_VMID_100K                        2
-#define WM8350_VMID_10K                         3
+#define WM8350_VMID_300K                        1
+#define WM8350_VMID_50K                         2
+#define WM8350_VMID_5K                          3
 
 /*
  * R40 (0x28) - Clock Control 1
@@ -591,8 +591,38 @@
 #define WM8350_IRQ_CODEC_MICSCD			41
 #define WM8350_IRQ_CODEC_MICD			42
 
+/*
+ * WM8350 Platform data.
+ *
+ * This must be initialised per platform for best audio performance.
+ * Please see WM8350 datasheet for information.
+ */
+struct wm8350_audio_platform_data {
+	int vmid_discharge_msecs;	/* VMID --> OFF discharge time */
+	int drain_msecs;	/* OFF drain time */
+	int cap_discharge_msecs;	/* Cap ON (from OFF) discharge time */
+	int vmid_charge_msecs;	/* vmid power up time */
+	u32 vmid_s_curve:2;	/* vmid enable s curve speed */
+	u32 dis_out4:2;		/* out4 discharge speed */
+	u32 dis_out3:2;		/* out3 discharge speed */
+	u32 dis_out2:2;		/* out2 discharge speed */
+	u32 dis_out1:2;		/* out1 discharge speed */
+	u32 vroi_out4:1;	/* out4 tie off */
+	u32 vroi_out3:1;	/* out3 tie off */
+	u32 vroi_out2:1;	/* out2 tie off */
+	u32 vroi_out1:1;	/* out1 tie off */
+	u32 vroi_enable:1;	/* enable tie off */
+	u32 codec_current_on:2;	/* current level ON */
+	u32 codec_current_standby:2;	/* current level STANDBY */
+	u32 codec_current_charge:2;	/* codec current @ vmid charge */
+};
+
+struct snd_soc_codec;
+
 struct wm8350_codec {
 	struct platform_device *pdev;
+	struct snd_soc_codec *codec;
+	struct wm8350_audio_platform_data *platform_data;
 };
 
 #endif
diff --git a/include/linux/mfd/wm8350/rtc.h b/include/linux/mfd/wm8350/rtc.h
index dfda69e9f440..24add2bef6c9 100644
--- a/include/linux/mfd/wm8350/rtc.h
+++ b/include/linux/mfd/wm8350/rtc.h
@@ -261,6 +261,8 @@
 
 struct wm8350_rtc {
 	struct platform_device *pdev;
+	struct rtc_device *rtc;
+	int alarm_enabled;      /* used over suspend/resume */
 };
 
 #endif
diff --git a/include/linux/migrate.h b/include/linux/migrate.h
index 03aea612d284..3f34005068d4 100644
--- a/include/linux/migrate.h
+++ b/include/linux/migrate.h
@@ -7,7 +7,6 @@
 typedef struct page *new_page_t(struct page *, unsigned long private, int **);
 
 #ifdef CONFIG_MIGRATION
-extern int isolate_lru_page(struct page *p, struct list_head *pagelist);
 extern int putback_lru_pages(struct list_head *l);
 extern int migrate_page(struct address_space *,
 			struct page *, struct page *);
@@ -21,8 +20,6 @@ extern int migrate_vmas(struct mm_struct *mm,
 		const nodemask_t *from, const nodemask_t *to,
 		unsigned long flags);
 #else
-static inline int isolate_lru_page(struct page *p, struct list_head *list)
-					{ return -ENOSYS; }
 static inline int putback_lru_pages(struct list_head *l) { return 0; }
 static inline int migrate_pages(struct list_head *l, new_page_t x,
 		unsigned long private) { return -ENOSYS; }
diff --git a/include/linux/mii.h b/include/linux/mii.h
index 151b7e0182c7..ad748588faf1 100644
--- a/include/linux/mii.h
+++ b/include/linux/mii.h
@@ -135,6 +135,10 @@
 #define LPA_1000FULL            0x0800  /* Link partner 1000BASE-T full duplex */
 #define LPA_1000HALF            0x0400  /* Link partner 1000BASE-T half duplex */
 
+/* Flow control flags */
+#define FLOW_CTRL_TX		0x01
+#define FLOW_CTRL_RX		0x02
+
 /* This structure is used in all SIOCxMIIxxx ioctl calls */
 struct mii_ioctl_data {
 	__u16		phy_id;
@@ -235,5 +239,34 @@ static inline unsigned int mii_duplex (unsigned int duplex_lock,
 	return 0;
 }
 
+/**
+ * mii_resolve_flowctrl_fdx
+ * @lcladv: value of MII ADVERTISE register
+ * @rmtadv: value of MII LPA register
+ *
+ * Resolve full duplex flow control as per IEEE 802.3-2005 table 28B-3
+ */
+static inline u8 mii_resolve_flowctrl_fdx(u16 lcladv, u16 rmtadv)
+{
+	u8 cap = 0;
+
+	if (lcladv & ADVERTISE_PAUSE_CAP) {
+		if (lcladv & ADVERTISE_PAUSE_ASYM) {
+			if (rmtadv & LPA_PAUSE_CAP)
+				cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
+			else if (rmtadv & LPA_PAUSE_ASYM)
+				cap = FLOW_CTRL_RX;
+		} else {
+			if (rmtadv & LPA_PAUSE_CAP)
+				cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
+		}
+	} else if (lcladv & ADVERTISE_PAUSE_ASYM) {
+		if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
+			cap = FLOW_CTRL_TX;
+	}
+
+	return cap;
+}
+
 #endif /* __KERNEL__ */
 #endif /* __LINUX_MII_H__ */
diff --git a/include/linux/mlx4/cmd.h b/include/linux/mlx4/cmd.h
index 77323a72dd3c..cf9c679ab38b 100644
--- a/include/linux/mlx4/cmd.h
+++ b/include/linux/mlx4/cmd.h
@@ -132,6 +132,15 @@ enum {
 	MLX4_MAILBOX_SIZE	=  4096
 };
 
+enum {
+	/* set port opcode modifiers */
+	MLX4_SET_PORT_GENERAL   = 0x0,
+	MLX4_SET_PORT_RQP_CALC  = 0x1,
+	MLX4_SET_PORT_MAC_TABLE = 0x2,
+	MLX4_SET_PORT_VLAN_TABLE = 0x3,
+	MLX4_SET_PORT_PRIO_MAP  = 0x4,
+};
+
 struct mlx4_dev;
 
 struct mlx4_cmd_mailbox {
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index b2f944468313..8f659cc29960 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -60,6 +60,7 @@ enum {
 	MLX4_DEV_CAP_FLAG_IPOIB_CSUM	= 1 <<  7,
 	MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR	= 1 <<  8,
 	MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR	= 1 <<  9,
+	MLX4_DEV_CAP_FLAG_DPDP		= 1 << 12,
 	MLX4_DEV_CAP_FLAG_MEM_WINDOW	= 1 << 16,
 	MLX4_DEV_CAP_FLAG_APM		= 1 << 17,
 	MLX4_DEV_CAP_FLAG_ATOMIC	= 1 << 18,
@@ -145,6 +146,29 @@ enum {
 	MLX4_MTT_FLAG_PRESENT		= 1
 };
 
+enum mlx4_qp_region {
+	MLX4_QP_REGION_FW = 0,
+	MLX4_QP_REGION_ETH_ADDR,
+	MLX4_QP_REGION_FC_ADDR,
+	MLX4_QP_REGION_FC_EXCH,
+	MLX4_NUM_QP_REGION
+};
+
+enum mlx4_port_type {
+	MLX4_PORT_TYPE_IB	= 1 << 0,
+	MLX4_PORT_TYPE_ETH	= 1 << 1,
+};
+
+enum mlx4_special_vlan_idx {
+	MLX4_NO_VLAN_IDX        = 0,
+	MLX4_VLAN_MISS_IDX,
+	MLX4_VLAN_REGULAR
+};
+
+enum {
+	MLX4_NUM_FEXCH          = 64 * 1024,
+};
+
 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
 {
 	return (major << 32) | (minor << 16) | subminor;
@@ -154,7 +178,10 @@ struct mlx4_caps {
 	u64			fw_ver;
 	int			num_ports;
 	int			vl_cap[MLX4_MAX_PORTS + 1];
-	int			mtu_cap[MLX4_MAX_PORTS + 1];
+	int			ib_mtu_cap[MLX4_MAX_PORTS + 1];
+	__be32			ib_port_def_cap[MLX4_MAX_PORTS + 1];
+	u64			def_mac[MLX4_MAX_PORTS + 1];
+	int			eth_mtu_cap[MLX4_MAX_PORTS + 1];
 	int			gid_table_len[MLX4_MAX_PORTS + 1];
 	int			pkey_table_len[MLX4_MAX_PORTS + 1];
 	int			local_ca_ack_delay;
@@ -169,7 +196,6 @@ struct mlx4_caps {
 	int			max_rq_desc_sz;
 	int			max_qp_init_rdma;
 	int			max_qp_dest_rdma;
-	int			reserved_qps;
 	int			sqp_start;
 	int			num_srqs;
 	int			max_srq_wqes;
@@ -180,6 +206,7 @@ struct mlx4_caps {
 	int			reserved_cqs;
 	int			num_eqs;
 	int			reserved_eqs;
+	int			num_comp_vectors;
 	int			num_mpts;
 	int			num_mtt_segs;
 	int			fmr_reserved_mtts;
@@ -201,6 +228,15 @@ struct mlx4_caps {
 	u16			stat_rate_support;
 	u8			port_width_cap[MLX4_MAX_PORTS + 1];
 	int			max_gso_sz;
+	int                     reserved_qps_cnt[MLX4_NUM_QP_REGION];
+	int			reserved_qps;
+	int                     reserved_qps_base[MLX4_NUM_QP_REGION];
+	int                     log_num_macs;
+	int                     log_num_vlans;
+	int                     log_num_prios;
+	enum mlx4_port_type	port_type[MLX4_MAX_PORTS + 1];
+	u8			supported_type[MLX4_MAX_PORTS + 1];
+	u32			port_mask;
 };
 
 struct mlx4_buf_list {
@@ -293,6 +329,7 @@ struct mlx4_cq {
 	int			arm_sn;
 
 	int			cqn;
+	unsigned		vector;
 
 	atomic_t		refcount;
 	struct completion	free;
@@ -355,6 +392,11 @@ struct mlx4_init_port_param {
 	u64			si_guid;
 };
 
+#define mlx4_foreach_port(port, dev, type)				\
+	for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++)	\
+		if (((type) == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \
+		     ~(dev)->caps.port_mask) & 1 << ((port) - 1))
+
 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
 		   struct mlx4_buf *buf);
 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
@@ -397,10 +439,13 @@ void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
 
 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
 		  struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
-		  int collapsed);
+		  unsigned vector, int collapsed);
 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
 
-int mlx4_qp_alloc(struct mlx4_dev *dev, int sqpn, struct mlx4_qp *qp);
+int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
+void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
+
+int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
 
 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
@@ -416,6 +461,12 @@ int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
 			  int block_mcast_loopback);
 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
 
+int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *index);
+void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index);
+
+int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
+void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
+
 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
 		      int npages, u64 iova, u32 *lkey, u32 *rkey);
 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
diff --git a/include/linux/mm.h b/include/linux/mm.h
index c61ba10768ea..aaa8b843be28 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -132,6 +132,11 @@ extern unsigned int kobjsize(const void *objp);
 #define VM_RandomReadHint(v)		((v)->vm_flags & VM_RAND_READ)
 
 /*
+ * special vmas that are non-mergable, non-mlock()able
+ */
+#define VM_SPECIAL (VM_IO | VM_DONTEXPAND | VM_RESERVED | VM_PFNMAP)
+
+/*
  * mapping from the currently active vm_flags protection bits (the
  * low four bits) to a page protection mask..
  */
@@ -140,6 +145,23 @@ extern pgprot_t protection_map[16];
 #define FAULT_FLAG_WRITE	0x01	/* Fault was a write access */
 #define FAULT_FLAG_NONLINEAR	0x02	/* Fault was via a nonlinear mapping */
 
+/*
+ * This interface is used by x86 PAT code to identify a pfn mapping that is
+ * linear over entire vma. This is to optimize PAT code that deals with
+ * marking the physical region with a particular prot. This is not for generic
+ * mm use. Note also that this check will not work if the pfn mapping is
+ * linear for a vma starting at physical address 0. In which case PAT code
+ * falls back to slow path of reserving physical range page by page.
+ */
+static inline int is_linear_pfn_mapping(struct vm_area_struct *vma)
+{
+	return ((vma->vm_flags & VM_PFNMAP) && vma->vm_pgoff);
+}
+
+static inline int is_pfn_mapping(struct vm_area_struct *vma)
+{
+	return (vma->vm_flags & VM_PFNMAP);
+}
 
 /*
  * vm_fault is filled by the the pagefault handler and passed to the vma's
@@ -700,10 +722,10 @@ static inline int page_mapped(struct page *page)
 extern void show_free_areas(void);
 
 #ifdef CONFIG_SHMEM
-int shmem_lock(struct file *file, int lock, struct user_struct *user);
+extern int shmem_lock(struct file *file, int lock, struct user_struct *user);
 #else
 static inline int shmem_lock(struct file *file, int lock,
-			     struct user_struct *user)
+			    struct user_struct *user)
 {
 	return 0;
 }
@@ -776,6 +798,8 @@ int copy_page_range(struct mm_struct *dst, struct mm_struct *src,
 			struct vm_area_struct *vma);
 void unmap_mapping_range(struct address_space *mapping,
 		loff_t const holebegin, loff_t const holelen, int even_cows);
+int follow_phys(struct vm_area_struct *vma, unsigned long address,
+		unsigned int flags, unsigned long *prot, resource_size_t *phys);
 int generic_access_phys(struct vm_area_struct *vma, unsigned long addr,
 			void *buf, int len, int write);
 
@@ -1281,5 +1305,7 @@ int vmemmap_populate_basepages(struct page *start_page,
 int vmemmap_populate(struct page *start_page, unsigned long pages, int node);
 void vmemmap_populate_print_last(void);
 
+extern void *alloc_locked_buffer(size_t size);
+extern void free_locked_buffer(void *buffer, size_t size);
 #endif /* __KERNEL__ */
 #endif /* _LINUX_MM_H */
diff --git a/include/linux/mm_inline.h b/include/linux/mm_inline.h
index 895bc4e93039..c948350c378e 100644
--- a/include/linux/mm_inline.h
+++ b/include/linux/mm_inline.h
@@ -1,40 +1,100 @@
-static inline void
-add_page_to_active_list(struct zone *zone, struct page *page)
-{
-	list_add(&page->lru, &zone->active_list);
-	__inc_zone_state(zone, NR_ACTIVE);
-}
+#ifndef LINUX_MM_INLINE_H
+#define LINUX_MM_INLINE_H
 
-static inline void
-add_page_to_inactive_list(struct zone *zone, struct page *page)
+/**
+ * page_is_file_cache - should the page be on a file LRU or anon LRU?
+ * @page: the page to test
+ *
+ * Returns LRU_FILE if @page is page cache page backed by a regular filesystem,
+ * or 0 if @page is anonymous, tmpfs or otherwise ram or swap backed.
+ * Used by functions that manipulate the LRU lists, to sort a page
+ * onto the right LRU list.
+ *
+ * We would like to get this info without a page flag, but the state
+ * needs to survive until the page is last deleted from the LRU, which
+ * could be as far down as __page_cache_release.
+ */
+static inline int page_is_file_cache(struct page *page)
 {
-	list_add(&page->lru, &zone->inactive_list);
-	__inc_zone_state(zone, NR_INACTIVE);
+	if (PageSwapBacked(page))
+		return 0;
+
+	/* The page is page cache backed by a normal filesystem. */
+	return LRU_FILE;
 }
 
 static inline void
-del_page_from_active_list(struct zone *zone, struct page *page)
+add_page_to_lru_list(struct zone *zone, struct page *page, enum lru_list l)
 {
-	list_del(&page->lru);
-	__dec_zone_state(zone, NR_ACTIVE);
+	list_add(&page->lru, &zone->lru[l].list);
+	__inc_zone_state(zone, NR_LRU_BASE + l);
 }
 
 static inline void
-del_page_from_inactive_list(struct zone *zone, struct page *page)
+del_page_from_lru_list(struct zone *zone, struct page *page, enum lru_list l)
 {
 	list_del(&page->lru);
-	__dec_zone_state(zone, NR_INACTIVE);
+	__dec_zone_state(zone, NR_LRU_BASE + l);
 }
 
 static inline void
 del_page_from_lru(struct zone *zone, struct page *page)
 {
+	enum lru_list l = LRU_BASE;
+
 	list_del(&page->lru);
-	if (PageActive(page)) {
-		__ClearPageActive(page);
-		__dec_zone_state(zone, NR_ACTIVE);
+	if (PageUnevictable(page)) {
+		__ClearPageUnevictable(page);
+		l = LRU_UNEVICTABLE;
 	} else {
-		__dec_zone_state(zone, NR_INACTIVE);
+		if (PageActive(page)) {
+			__ClearPageActive(page);
+			l += LRU_ACTIVE;
+		}
+		l += page_is_file_cache(page);
+	}
+	__dec_zone_state(zone, NR_LRU_BASE + l);
+}
+
+/**
+ * page_lru - which LRU list should a page be on?
+ * @page: the page to test
+ *
+ * Returns the LRU list a page should be on, as an index
+ * into the array of LRU lists.
+ */
+static inline enum lru_list page_lru(struct page *page)
+{
+	enum lru_list lru = LRU_BASE;
+
+	if (PageUnevictable(page))
+		lru = LRU_UNEVICTABLE;
+	else {
+		if (PageActive(page))
+			lru += LRU_ACTIVE;
+		lru += page_is_file_cache(page);
 	}
+
+	return lru;
 }
 
+/**
+ * inactive_anon_is_low - check if anonymous pages need to be deactivated
+ * @zone: zone to check
+ *
+ * Returns true if the zone does not have enough inactive anon pages,
+ * meaning some active anon pages need to be deactivated.
+ */
+static inline int inactive_anon_is_low(struct zone *zone)
+{
+	unsigned long active, inactive;
+
+	active = zone_page_state(zone, NR_ACTIVE_ANON);
+	inactive = zone_page_state(zone, NR_INACTIVE_ANON);
+
+	if (inactive * zone->inactive_ratio < active)
+		return 1;
+
+	return 0;
+}
+#endif
diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h
index 9d49fa36bbef..9cfc9b627fdd 100644
--- a/include/linux/mm_types.h
+++ b/include/linux/mm_types.h
@@ -94,9 +94,6 @@ struct page {
 	void *virtual;			/* Kernel virtual address (NULL if
 					   not kmapped, ie. highmem) */
 #endif /* WANT_PAGE_VIRTUAL */
-#ifdef CONFIG_CGROUP_MEM_RES_CTLR
-	unsigned long page_cgroup;
-#endif
 };
 
 /*
@@ -235,8 +232,9 @@ struct mm_struct {
 	struct core_state *core_state; /* coredumping support */
 
 	/* aio bits */
-	rwlock_t		ioctx_list_lock;	/* aio lock */
-	struct kioctx		*ioctx_list;
+	spinlock_t		ioctx_lock;
+	struct hlist_head	ioctx_list;
+
 #ifdef CONFIG_MM_OWNER
 	/*
 	 * "owner" points to a task that is regarded as the canonical
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h
index ee6e822d5994..403aa505f27e 100644
--- a/include/linux/mmc/card.h
+++ b/include/linux/mmc/card.h
@@ -130,7 +130,7 @@ struct mmc_card {
 #define mmc_card_set_blockaddr(c) ((c)->state |= MMC_STATE_BLOCKADDR)
 
 #define mmc_card_name(c)	((c)->cid.prod_name)
-#define mmc_card_id(c)		((c)->dev.bus_id)
+#define mmc_card_id(c)		(dev_name(&(c)->dev))
 
 #define mmc_list_to_card(l)	container_of(l, struct mmc_card, node)
 #define mmc_get_drvdata(c)	dev_get_drvdata(&(c)->dev)
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index bde891f64591..f842f234e44f 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -176,7 +176,7 @@ static inline void *mmc_priv(struct mmc_host *host)
 
 #define mmc_dev(x)	((x)->parent)
 #define mmc_classdev(x)	(&(x)->class_dev)
-#define mmc_hostname(x)	((x)->class_dev.bus_id)
+#define mmc_hostname(x)	(dev_name(&(x)->class_dev))
 
 extern int mmc_suspend_host(struct mmc_host *, pm_message_t);
 extern int mmc_resume_host(struct mmc_host *);
diff --git a/include/linux/mmc/sdio_func.h b/include/linux/mmc/sdio_func.h
index 07bee4a0d457..451bdfc85830 100644
--- a/include/linux/mmc/sdio_func.h
+++ b/include/linux/mmc/sdio_func.h
@@ -63,7 +63,7 @@ struct sdio_func {
 
 #define sdio_func_set_present(f) ((f)->state |= SDIO_STATE_PRESENT)
 
-#define sdio_func_id(f)		((f)->dev.bus_id)
+#define sdio_func_id(f)		(dev_name(&(f)->dev))
 
 #define sdio_get_drvdata(f)	dev_get_drvdata(&(f)->dev)
 #define sdio_set_drvdata(f,d)	dev_set_drvdata(&(f)->dev, d)
diff --git a/include/linux/mmiotrace.h b/include/linux/mmiotrace.h
index 61d19e1b7a0b..139d7c88d9c9 100644
--- a/include/linux/mmiotrace.h
+++ b/include/linux/mmiotrace.h
@@ -34,11 +34,15 @@ extern void unregister_kmmio_probe(struct kmmio_probe *p);
 /* Called from page fault handler. */
 extern int kmmio_handler(struct pt_regs *regs, unsigned long addr);
 
-/* Called from ioremap.c */
 #ifdef CONFIG_MMIOTRACE
+/* Called from ioremap.c */
 extern void mmiotrace_ioremap(resource_size_t offset, unsigned long size,
 							void __iomem *addr);
 extern void mmiotrace_iounmap(volatile void __iomem *addr);
+
+/* For anyone to insert markers. Remember trailing newline. */
+extern int mmiotrace_printk(const char *fmt, ...)
+				__attribute__ ((format (printf, 1, 2)));
 #else
 static inline void mmiotrace_ioremap(resource_size_t offset,
 					unsigned long size, void __iomem *addr)
@@ -48,15 +52,22 @@ static inline void mmiotrace_ioremap(resource_size_t offset,
 static inline void mmiotrace_iounmap(volatile void __iomem *addr)
 {
 }
-#endif /* CONFIG_MMIOTRACE_HOOKS */
+
+static inline int mmiotrace_printk(const char *fmt, ...)
+				__attribute__ ((format (printf, 1, 0)));
+
+static inline int mmiotrace_printk(const char *fmt, ...)
+{
+	return 0;
+}
+#endif /* CONFIG_MMIOTRACE */
 
 enum mm_io_opcode {
 	MMIO_READ = 0x1,     /* struct mmiotrace_rw */
 	MMIO_WRITE = 0x2,    /* struct mmiotrace_rw */
 	MMIO_PROBE = 0x3,    /* struct mmiotrace_map */
 	MMIO_UNPROBE = 0x4,  /* struct mmiotrace_map */
-	MMIO_MARKER = 0x5,   /* raw char data */
-	MMIO_UNKNOWN_OP = 0x6, /* struct mmiotrace_rw */
+	MMIO_UNKNOWN_OP = 0x5, /* struct mmiotrace_rw */
 };
 
 struct mmiotrace_rw {
@@ -81,5 +92,6 @@ extern void enable_mmiotrace(void);
 extern void disable_mmiotrace(void);
 extern void mmio_trace_rw(struct mmiotrace_rw *rw);
 extern void mmio_trace_mapping(struct mmiotrace_map *map);
+extern int mmio_trace_printk(const char *fmt, va_list args);
 
 #endif /* MMIOTRACE_H */
diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
index 428328a05fa1..35a7b5e19465 100644
--- a/include/linux/mmzone.h
+++ b/include/linux/mmzone.h
@@ -81,21 +81,31 @@ struct zone_padding {
 enum zone_stat_item {
 	/* First 128 byte cacheline (assuming 64 bit words) */
 	NR_FREE_PAGES,
-	NR_INACTIVE,
-	NR_ACTIVE,
+	NR_LRU_BASE,
+	NR_INACTIVE_ANON = NR_LRU_BASE, /* must match order of LRU_[IN]ACTIVE */
+	NR_ACTIVE_ANON,		/*  "     "     "   "       "         */
+	NR_INACTIVE_FILE,	/*  "     "     "   "       "         */
+	NR_ACTIVE_FILE,		/*  "     "     "   "       "         */
+#ifdef CONFIG_UNEVICTABLE_LRU
+	NR_UNEVICTABLE,		/*  "     "     "   "       "         */
+	NR_MLOCK,		/* mlock()ed pages found and moved off LRU */
+#else
+	NR_UNEVICTABLE = NR_ACTIVE_FILE, /* avoid compiler errors in dead code */
+	NR_MLOCK = NR_ACTIVE_FILE,
+#endif
 	NR_ANON_PAGES,	/* Mapped anonymous pages */
 	NR_FILE_MAPPED,	/* pagecache pages mapped into pagetables.
 			   only modified from process context */
 	NR_FILE_PAGES,
 	NR_FILE_DIRTY,
 	NR_WRITEBACK,
-	/* Second 128 byte cacheline */
 	NR_SLAB_RECLAIMABLE,
 	NR_SLAB_UNRECLAIMABLE,
 	NR_PAGETABLE,		/* used for pagetables */
 	NR_UNSTABLE_NFS,	/* NFS unstable pages */
 	NR_BOUNCE,
 	NR_VMSCAN_WRITE,
+	/* Second 128 byte cacheline */
 	NR_WRITEBACK_TEMP,	/* Writeback using temporary buffers */
 #ifdef CONFIG_NUMA
 	NUMA_HIT,		/* allocated in intended node */
@@ -107,6 +117,55 @@ enum zone_stat_item {
 #endif
 	NR_VM_ZONE_STAT_ITEMS };
 
+/*
+ * We do arithmetic on the LRU lists in various places in the code,
+ * so it is important to keep the active lists LRU_ACTIVE higher in
+ * the array than the corresponding inactive lists, and to keep
+ * the *_FILE lists LRU_FILE higher than the corresponding _ANON lists.
+ *
+ * This has to be kept in sync with the statistics in zone_stat_item
+ * above and the descriptions in vmstat_text in mm/vmstat.c
+ */
+#define LRU_BASE 0
+#define LRU_ACTIVE 1
+#define LRU_FILE 2
+
+enum lru_list {
+	LRU_INACTIVE_ANON = LRU_BASE,
+	LRU_ACTIVE_ANON = LRU_BASE + LRU_ACTIVE,
+	LRU_INACTIVE_FILE = LRU_BASE + LRU_FILE,
+	LRU_ACTIVE_FILE = LRU_BASE + LRU_FILE + LRU_ACTIVE,
+#ifdef CONFIG_UNEVICTABLE_LRU
+	LRU_UNEVICTABLE,
+#else
+	LRU_UNEVICTABLE = LRU_ACTIVE_FILE, /* avoid compiler errors in dead code */
+#endif
+	NR_LRU_LISTS
+};
+
+#define for_each_lru(l) for (l = 0; l < NR_LRU_LISTS; l++)
+
+#define for_each_evictable_lru(l) for (l = 0; l <= LRU_ACTIVE_FILE; l++)
+
+static inline int is_file_lru(enum lru_list l)
+{
+	return (l == LRU_INACTIVE_FILE || l == LRU_ACTIVE_FILE);
+}
+
+static inline int is_active_lru(enum lru_list l)
+{
+	return (l == LRU_ACTIVE_ANON || l == LRU_ACTIVE_FILE);
+}
+
+static inline int is_unevictable_lru(enum lru_list l)
+{
+#ifdef CONFIG_UNEVICTABLE_LRU
+	return (l == LRU_UNEVICTABLE);
+#else
+	return 0;
+#endif
+}
+
 struct per_cpu_pages {
 	int count;		/* number of pages in the list */
 	int high;		/* high watermark, emptying needed */
@@ -251,10 +310,22 @@ struct zone {
 
 	/* Fields commonly accessed by the page reclaim scanner */
 	spinlock_t		lru_lock;	
-	struct list_head	active_list;
-	struct list_head	inactive_list;
-	unsigned long		nr_scan_active;
-	unsigned long		nr_scan_inactive;
+	struct {
+		struct list_head list;
+		unsigned long nr_scan;
+	} lru[NR_LRU_LISTS];
+
+	/*
+	 * The pageout code in vmscan.c keeps track of how many of the
+	 * mem/swap backed and file backed pages are refeferenced.
+	 * The higher the rotated/scanned ratio, the more valuable
+	 * that cache is.
+	 *
+	 * The anon LRU stats live in [0], file LRU stats in [1]
+	 */
+	unsigned long		recent_rotated[2];
+	unsigned long		recent_scanned[2];
+
 	unsigned long		pages_scanned;	   /* since last reclaim */
 	unsigned long		flags;		   /* zone flags, see below */
 
@@ -276,6 +347,12 @@ struct zone {
 	 */
 	int prev_priority;
 
+	/*
+	 * The target ratio of ACTIVE_ANON to INACTIVE_ANON pages on
+	 * this zone's LRU.  Maintained by the pageout code.
+	 */
+	unsigned int inactive_ratio;
+
 
 	ZONE_PADDING(_pad2_)
 	/* Rarely used or read-mostly fields */
@@ -524,8 +601,11 @@ typedef struct pglist_data {
 	struct zone node_zones[MAX_NR_ZONES];
 	struct zonelist node_zonelists[MAX_ZONELISTS];
 	int nr_zones;
-#ifdef CONFIG_FLAT_NODE_MEM_MAP
+#ifdef CONFIG_FLAT_NODE_MEM_MAP	/* means !SPARSEMEM */
 	struct page *node_mem_map;
+#ifdef CONFIG_CGROUP_MEM_RES_CTLR
+	struct page_cgroup *node_page_cgroup;
+#endif
 #endif
 	struct bootmem_data *bdata;
 #ifdef CONFIG_MEMORY_HOTPLUG
@@ -854,6 +934,7 @@ static inline unsigned long early_pfn_to_nid(unsigned long pfn)
 #endif
 
 struct page;
+struct page_cgroup;
 struct mem_section {
 	/*
 	 * This is, logically, a pointer to an array of struct
@@ -871,6 +952,14 @@ struct mem_section {
 
 	/* See declaration of similar field in struct zone */
 	unsigned long *pageblock_flags;
+#ifdef CONFIG_CGROUP_MEM_RES_CTLR
+	/*
+	 * If !SPARSEMEM, pgdat doesn't have page_cgroup pointer. We use
+	 * section. (see memcontrol.h/page_cgroup.h about this.)
+	 */
+	struct page_cgroup *page_cgroup;
+	unsigned long pad;
+#endif
 };
 
 #ifdef CONFIG_SPARSEMEM_EXTREME
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index d6a3f47e95cb..97b91d1abb43 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -135,6 +135,7 @@ struct usb_device_id {
 
 struct hid_device_id {
 	__u16 bus;
+	__u16 pad1;
 	__u32 vendor;
 	__u32 product;
 	kernel_ulong_t driver_data
@@ -284,7 +285,7 @@ struct pcmcia_device_id {
 /* Input */
 #define INPUT_DEVICE_ID_EV_MAX		0x1f
 #define INPUT_DEVICE_ID_KEY_MIN_INTERESTING	0x71
-#define INPUT_DEVICE_ID_KEY_MAX		0x1ff
+#define INPUT_DEVICE_ID_KEY_MAX		0x2ff
 #define INPUT_DEVICE_ID_REL_MAX		0x0f
 #define INPUT_DEVICE_ID_ABS_MAX		0x3f
 #define INPUT_DEVICE_ID_MSC_MAX		0x07
diff --git a/include/linux/module.h b/include/linux/module.h
index 68e09557c951..3bfed013350b 100644
--- a/include/linux/module.h
+++ b/include/linux/module.h
@@ -16,6 +16,7 @@
 #include <linux/kobject.h>
 #include <linux/moduleparam.h>
 #include <linux/marker.h>
+#include <linux/tracepoint.h>
 #include <asm/local.h>
 
 #include <asm/module.h>
@@ -28,7 +29,7 @@
 #define MODULE_SYMBOL_PREFIX ""
 #endif
 
-#define MODULE_NAME_LEN (64 - sizeof(unsigned long))
+#define MODULE_NAME_LEN MAX_PARAM_PREFIX_LEN
 
 struct kernel_symbol
 {
@@ -59,6 +60,7 @@ struct module_kobject
 	struct kobject kobj;
 	struct module *mod;
 	struct kobject *drivers_dir;
+	struct module_param_attrs *mp;
 };
 
 /* These are either module local, or the kernel's dummy ones. */
@@ -241,7 +243,6 @@ struct module
 
 	/* Sysfs stuff. */
 	struct module_kobject mkobj;
-	struct module_param_attrs *param_attrs;
 	struct module_attribute *modinfo_attrs;
 	const char *version;
 	const char *srcversion;
@@ -276,7 +277,7 @@ struct module
 
 	/* Exception table */
 	unsigned int num_exentries;
-	const struct exception_table_entry *extable;
+	struct exception_table_entry *extable;
 
 	/* Startup function. */
 	int (*init)(void);
@@ -331,6 +332,10 @@ struct module
 	struct marker *markers;
 	unsigned int num_markers;
 #endif
+#ifdef CONFIG_TRACEPOINTS
+	struct tracepoint *tracepoints;
+	unsigned int num_tracepoints;
+#endif
 
 #ifdef CONFIG_MODULE_UNLOAD
 	/* What modules depend on me? */
@@ -345,7 +350,6 @@ struct module
 	/* Reference counts */
 	struct module_ref ref[NR_CPUS];
 #endif
-
 };
 #ifndef MODULE_ARCH_INIT
 #define MODULE_ARCH_INIT {}
@@ -454,6 +458,9 @@ extern void print_modules(void);
 
 extern void module_update_markers(void);
 
+extern void module_update_tracepoints(void);
+extern int module_get_iter_tracepoints(struct tracepoint_iter *iter);
+
 #else /* !CONFIG_MODULES... */
 #define EXPORT_SYMBOL(sym)
 #define EXPORT_SYMBOL_GPL(sym)
@@ -558,6 +565,15 @@ static inline void module_update_markers(void)
 {
 }
 
+static inline void module_update_tracepoints(void)
+{
+}
+
+static inline int module_get_iter_tracepoints(struct tracepoint_iter *iter)
+{
+	return 0;
+}
+
 #endif /* CONFIG_MODULES */
 
 struct device_driver;
diff --git a/include/linux/moduleparam.h b/include/linux/moduleparam.h
index ec624381c844..e4af3399ef48 100644
--- a/include/linux/moduleparam.h
+++ b/include/linux/moduleparam.h
@@ -13,6 +13,9 @@
 #define MODULE_PARAM_PREFIX KBUILD_MODNAME "."
 #endif
 
+/* Chosen so that structs with an unsigned long line up. */
+#define MAX_PARAM_PREFIX_LEN (64 - sizeof(unsigned long))
+
 #ifdef MODULE
 #define ___module_cat(a,b) __mod_ ## a ## b
 #define __module_cat(a,b) ___module_cat(a,b)
@@ -79,7 +82,8 @@ struct kparam_array
 #define __module_param_call(prefix, name, set, get, arg, perm)		\
 	/* Default value instead of permissions? */			\
 	static int __param_perm_check_##name __attribute__((unused)) =	\
-	BUILD_BUG_ON_ZERO((perm) < 0 || (perm) > 0777 || ((perm) & 2));	\
+	BUILD_BUG_ON_ZERO((perm) < 0 || (perm) > 0777 || ((perm) & 2))	\
+	+ BUILD_BUG_ON_ZERO(sizeof(""prefix) > MAX_PARAM_PREFIX_LEN);	\
 	static const char __param_str_##name[] = prefix #name;		\
 	static struct kernel_param __moduleparam_const __param_##name	\
 	__used								\
@@ -100,6 +104,25 @@ struct kparam_array
 #define module_param(name, type, perm)				\
 	module_param_named(name, name, type, perm)
 
+#ifndef MODULE
+/**
+ * core_param - define a historical core kernel parameter.
+ * @name: the name of the cmdline and sysfs parameter (often the same as var)
+ * @var: the variable
+ * @type: the type (for param_set_##type and param_get_##type)
+ * @perm: visibility in sysfs
+ *
+ * core_param is just like module_param(), but cannot be modular and
+ * doesn't add a prefix (such as "printk.").  This is for compatibility
+ * with __setup(), and it makes sense as truly core parameters aren't
+ * tied to the particular file they're in.
+ */
+#define core_param(name, var, type, perm)				\
+	param_check_##type(name, &(var));				\
+	__module_param_call("", name, param_set_##type, param_get_##type, \
+			    &var, perm)
+#endif /* !MODULE */
+
 /* Actually copy string: maxlen param is usually sizeof(string). */
 #define module_param_string(name, string, len, perm)			\
 	static const struct kparam_string __param_string_##name		\
diff --git a/include/linux/mount.h b/include/linux/mount.h
index 30a1d63b6fb5..cab2a85e2ee8 100644
--- a/include/linux/mount.h
+++ b/include/linux/mount.h
@@ -5,8 +5,6 @@
  *
  * Author:  Marco van Wieringen <mvw@planets.elm.net>
  *
- * Version: $Id: mount.h,v 2.0 1996/11/17 16:48:14 mvw Exp mvw $
- *
  */
 #ifndef _LINUX_MOUNT_H
 #define _LINUX_MOUNT_H
diff --git a/include/linux/mroute6.h b/include/linux/mroute6.h
index 6f4c180179e2..5375faca1f72 100644
--- a/include/linux/mroute6.h
+++ b/include/linux/mroute6.h
@@ -117,6 +117,7 @@ struct sioc_mif_req6
 
 #include <linux/pim.h>
 #include <linux/skbuff.h>	/* for struct sk_buff_head */
+#include <net/net_namespace.h>
 
 #ifdef CONFIG_IPV6_MROUTE
 static inline int ip6_mroute_opt(int opt)
@@ -187,6 +188,9 @@ struct mif_device
 struct mfc6_cache
 {
 	struct mfc6_cache *next;		/* Next entry on cache line 	*/
+#ifdef CONFIG_NET_NS
+	struct net *mfc6_net;
+#endif
 	struct in6_addr mf6c_mcastgrp;			/* Group the entry belongs to 	*/
 	struct in6_addr mf6c_origin;			/* Source of packet 		*/
 	mifi_t mf6c_parent;			/* Source interface		*/
@@ -209,6 +213,18 @@ struct mfc6_cache
 	} mfc_un;
 };
 
+static inline
+struct net *mfc6_net(const struct mfc6_cache *mfc)
+{
+	return read_pnet(&mfc->mfc6_net);
+}
+
+static inline
+void mfc6_net_set(struct mfc6_cache *mfc, struct net *net)
+{
+	write_pnet(&mfc->mfc6_net, hold_net(net));
+}
+
 #define MFC_STATIC		1
 #define MFC_NOTIFY		2
 
@@ -229,13 +245,17 @@ struct mfc6_cache
 
 #ifdef __KERNEL__
 struct rtmsg;
-extern int ip6mr_get_route(struct sk_buff *skb, struct rtmsg *rtm, int nowait);
+extern int ip6mr_get_route(struct net *net, struct sk_buff *skb,
+			   struct rtmsg *rtm, int nowait);
 
 #ifdef CONFIG_IPV6_MROUTE
-extern struct sock *mroute6_socket;
+static inline struct sock *mroute6_socket(struct net *net)
+{
+	return net->ipv6.mroute6_sk;
+}
 extern int ip6mr_sk_done(struct sock *sk);
 #else
-#define mroute6_socket NULL
+static inline struct sock *mroute6_socket(struct net *net) { return NULL; }
 static inline int ip6mr_sk_done(struct sock *sk) { return 0; }
 #endif
 #endif
diff --git a/include/linux/msdos_fs.h b/include/linux/msdos_fs.h
index ba63858056c7..e0a9b207920d 100644
--- a/include/linux/msdos_fs.h
+++ b/include/linux/msdos_fs.h
@@ -46,11 +46,6 @@
 #define DELETED_FLAG	0xe5	/* marks file as deleted when in name[0] */
 #define IS_FREE(n)	(!*(n) || *(n) == DELETED_FLAG)
 
-/* valid file mode bits */
-#define MSDOS_VALID_MODE (S_IFREG | S_IFDIR | S_IRWXU | S_IRWXG | S_IRWXO)
-/* Convert attribute bits and a mask to the UNIX mode. */
-#define MSDOS_MKMODE(a, m) (m & (a & ATTR_RO ? S_IRUGO|S_IXUGO : S_IRWXUGO))
-
 #define MSDOS_NAME	11	/* maximum name length */
 #define MSDOS_LONGNAME	256	/* maximum name length */
 #define MSDOS_SLOTS	21	/* max # of slots for short and long names */
@@ -167,282 +162,10 @@ struct msdos_dir_slot {
 };
 
 #ifdef __KERNEL__
-
-#include <linux/buffer_head.h>
-#include <linux/string.h>
-#include <linux/nls.h>
-#include <linux/fs.h>
-#include <linux/mutex.h>
-
-/*
- * vfat shortname flags
- */
-#define VFAT_SFN_DISPLAY_LOWER	0x0001 /* convert to lowercase for display */
-#define VFAT_SFN_DISPLAY_WIN95	0x0002 /* emulate win95 rule for display */
-#define VFAT_SFN_DISPLAY_WINNT	0x0004 /* emulate winnt rule for display */
-#define VFAT_SFN_CREATE_WIN95	0x0100 /* emulate win95 rule for create */
-#define VFAT_SFN_CREATE_WINNT	0x0200 /* emulate winnt rule for create */
-
-struct fat_mount_options {
-	uid_t fs_uid;
-	gid_t fs_gid;
-	unsigned short fs_fmask;
-	unsigned short fs_dmask;
-	unsigned short codepage;  /* Codepage for shortname conversions */
-	char *iocharset;          /* Charset used for filename input/display */
-	unsigned short shortname; /* flags for shortname display/create rule */
-	unsigned char name_check; /* r = relaxed, n = normal, s = strict */
-	unsigned short allow_utime;/* permission for setting the [am]time */
-	unsigned quiet:1,         /* set = fake successful chmods and chowns */
-		 showexec:1,      /* set = only set x bit for com/exe/bat */
-		 sys_immutable:1, /* set = system files are immutable */
-		 dotsOK:1,        /* set = hidden and system files are named '.filename' */
-		 isvfat:1,        /* 0=no vfat long filename support, 1=vfat support */
-		 utf8:1,	  /* Use of UTF-8 character set (Default) */
-		 unicode_xlate:1, /* create escape sequences for unhandled Unicode */
-		 numtail:1,       /* Does first alias have a numeric '~1' type tail? */
-		 flush:1,	  /* write things quickly */
-		 nocase:1,	  /* Does this need case conversion? 0=need case conversion*/
-		 usefree:1,	  /* Use free_clusters for FAT32 */
-		 tz_utc:1;	  /* Filesystem timestamps are in UTC */
-};
-
-#define FAT_HASH_BITS	8
-#define FAT_HASH_SIZE	(1UL << FAT_HASH_BITS)
-#define FAT_HASH_MASK	(FAT_HASH_SIZE-1)
-
-/*
- * MS-DOS file system in-core superblock data
- */
-struct msdos_sb_info {
-	unsigned short sec_per_clus; /* sectors/cluster */
-	unsigned short cluster_bits; /* log2(cluster_size) */
-	unsigned int cluster_size;   /* cluster size */
-	unsigned char fats,fat_bits; /* number of FATs, FAT bits (12 or 16) */
-	unsigned short fat_start;
-	unsigned long fat_length;    /* FAT start & length (sec.) */
-	unsigned long dir_start;
-	unsigned short dir_entries;  /* root dir start & entries */
-	unsigned long data_start;    /* first data sector */
-	unsigned long max_cluster;   /* maximum cluster number */
-	unsigned long root_cluster;  /* first cluster of the root directory */
-	unsigned long fsinfo_sector; /* sector number of FAT32 fsinfo */
-	struct mutex fat_lock;
-	unsigned int prev_free;      /* previously allocated cluster number */
-	unsigned int free_clusters;  /* -1 if undefined */
-	unsigned int free_clus_valid; /* is free_clusters valid? */
-	struct fat_mount_options options;
-	struct nls_table *nls_disk;  /* Codepage used on disk */
-	struct nls_table *nls_io;    /* Charset used for input and display */
-	const void *dir_ops;		     /* Opaque; default directory operations */
-	int dir_per_block;	     /* dir entries per block */
-	int dir_per_block_bits;	     /* log2(dir_per_block) */
-
-	int fatent_shift;
-	struct fatent_operations *fatent_ops;
-
-	spinlock_t inode_hash_lock;
-	struct hlist_head inode_hashtable[FAT_HASH_SIZE];
-};
-
-#define FAT_CACHE_VALID	0	/* special case for valid cache */
-
-/*
- * MS-DOS file system inode data in memory
- */
-struct msdos_inode_info {
-	spinlock_t cache_lru_lock;
-	struct list_head cache_lru;
-	int nr_caches;
-	/* for avoiding the race between fat_free() and fat_get_cluster() */
-	unsigned int cache_valid_id;
-
-	loff_t mmu_private;
-	int i_start;		/* first cluster or 0 */
-	int i_logstart;		/* logical first cluster */
-	int i_attrs;		/* unused attribute bits */
-	loff_t i_pos;		/* on-disk position of directory entry or 0 */
-	struct hlist_node i_fat_hash;	/* hash by i_location */
-	struct inode vfs_inode;
-};
-
-struct fat_slot_info {
-	loff_t i_pos;		/* on-disk position of directory entry */
-	loff_t slot_off;	/* offset for slot or de start */
-	int nr_slots;		/* number of slots + 1(de) in filename */
-	struct msdos_dir_entry *de;
-	struct buffer_head *bh;
-};
-
-static inline struct msdos_sb_info *MSDOS_SB(struct super_block *sb)
-{
-	return sb->s_fs_info;
-}
-
-static inline struct msdos_inode_info *MSDOS_I(struct inode *inode)
-{
-	return container_of(inode, struct msdos_inode_info, vfs_inode);
-}
-
-/* Return the FAT attribute byte for this inode */
-static inline u8 fat_attr(struct inode *inode)
-{
-	return ((inode->i_mode & S_IWUGO) ? ATTR_NONE : ATTR_RO) |
-		(S_ISDIR(inode->i_mode) ? ATTR_DIR : ATTR_NONE) |
-		MSDOS_I(inode)->i_attrs;
-}
-
-static inline unsigned char fat_checksum(const __u8 *name)
-{
-	unsigned char s = name[0];
-	s = (s<<7) + (s>>1) + name[1];	s = (s<<7) + (s>>1) + name[2];
-	s = (s<<7) + (s>>1) + name[3];	s = (s<<7) + (s>>1) + name[4];
-	s = (s<<7) + (s>>1) + name[5];	s = (s<<7) + (s>>1) + name[6];
-	s = (s<<7) + (s>>1) + name[7];	s = (s<<7) + (s>>1) + name[8];
-	s = (s<<7) + (s>>1) + name[9];	s = (s<<7) + (s>>1) + name[10];
-	return s;
-}
-
-static inline sector_t fat_clus_to_blknr(struct msdos_sb_info *sbi, int clus)
-{
-	return ((sector_t)clus - FAT_START_ENT) * sbi->sec_per_clus
-		+ sbi->data_start;
-}
-
-static inline void fat16_towchar(wchar_t *dst, const __u8 *src, size_t len)
-{
-#ifdef __BIG_ENDIAN
-	while (len--) {
-		*dst++ = src[0] | (src[1] << 8);
-		src += 2;
-	}
-#else
-	memcpy(dst, src, len * 2);
-#endif
-}
-
-static inline void fatwchar_to16(__u8 *dst, const wchar_t *src, size_t len)
-{
-#ifdef __BIG_ENDIAN
-	while (len--) {
-		dst[0] = *src & 0x00FF;
-		dst[1] = (*src & 0xFF00) >> 8;
-		dst += 2;
-		src++;
-	}
-#else
-	memcpy(dst, src, len * 2);
-#endif
-}
-
 /* media of boot sector */
 static inline int fat_valid_media(u8 media)
 {
 	return 0xf8 <= media || media == 0xf0;
 }
-
-/* fat/cache.c */
-extern void fat_cache_inval_inode(struct inode *inode);
-extern int fat_get_cluster(struct inode *inode, int cluster,
-			   int *fclus, int *dclus);
-extern int fat_bmap(struct inode *inode, sector_t sector, sector_t *phys,
-		    unsigned long *mapped_blocks);
-
-/* fat/dir.c */
-extern const struct file_operations fat_dir_operations;
-extern int fat_search_long(struct inode *inode, const unsigned char *name,
-			   int name_len, struct fat_slot_info *sinfo);
-extern int fat_dir_empty(struct inode *dir);
-extern int fat_subdirs(struct inode *dir);
-extern int fat_scan(struct inode *dir, const unsigned char *name,
-		    struct fat_slot_info *sinfo);
-extern int fat_get_dotdot_entry(struct inode *dir, struct buffer_head **bh,
-				struct msdos_dir_entry **de, loff_t *i_pos);
-extern int fat_alloc_new_dir(struct inode *dir, struct timespec *ts);
-extern int fat_add_entries(struct inode *dir, void *slots, int nr_slots,
-			   struct fat_slot_info *sinfo);
-extern int fat_remove_entries(struct inode *dir, struct fat_slot_info *sinfo);
-
-/* fat/fatent.c */
-struct fat_entry {
-	int entry;
-	union {
-		u8 *ent12_p[2];
-		__le16 *ent16_p;
-		__le32 *ent32_p;
-	} u;
-	int nr_bhs;
-	struct buffer_head *bhs[2];
-};
-
-static inline void fatent_init(struct fat_entry *fatent)
-{
-	fatent->nr_bhs = 0;
-	fatent->entry = 0;
-	fatent->u.ent32_p = NULL;
-	fatent->bhs[0] = fatent->bhs[1] = NULL;
-}
-
-static inline void fatent_set_entry(struct fat_entry *fatent, int entry)
-{
-	fatent->entry = entry;
-	fatent->u.ent32_p = NULL;
-}
-
-static inline void fatent_brelse(struct fat_entry *fatent)
-{
-	int i;
-	fatent->u.ent32_p = NULL;
-	for (i = 0; i < fatent->nr_bhs; i++)
-		brelse(fatent->bhs[i]);
-	fatent->nr_bhs = 0;
-	fatent->bhs[0] = fatent->bhs[1] = NULL;
-}
-
-extern void fat_ent_access_init(struct super_block *sb);
-extern int fat_ent_read(struct inode *inode, struct fat_entry *fatent,
-			int entry);
-extern int fat_ent_write(struct inode *inode, struct fat_entry *fatent,
-			 int new, int wait);
-extern int fat_alloc_clusters(struct inode *inode, int *cluster,
-			      int nr_cluster);
-extern int fat_free_clusters(struct inode *inode, int cluster);
-extern int fat_count_free_clusters(struct super_block *sb);
-
-/* fat/file.c */
-extern int fat_generic_ioctl(struct inode *inode, struct file *filp,
-			     unsigned int cmd, unsigned long arg);
-extern const struct file_operations fat_file_operations;
-extern const struct inode_operations fat_file_inode_operations;
-extern int fat_setattr(struct dentry * dentry, struct iattr * attr);
-extern void fat_truncate(struct inode *inode);
-extern int fat_getattr(struct vfsmount *mnt, struct dentry *dentry,
-		       struct kstat *stat);
-
-/* fat/inode.c */
-extern void fat_attach(struct inode *inode, loff_t i_pos);
-extern void fat_detach(struct inode *inode);
-extern struct inode *fat_iget(struct super_block *sb, loff_t i_pos);
-extern struct inode *fat_build_inode(struct super_block *sb,
-			struct msdos_dir_entry *de, loff_t i_pos);
-extern int fat_sync_inode(struct inode *inode);
-extern int fat_fill_super(struct super_block *sb, void *data, int silent,
-			const struct inode_operations *fs_dir_inode_ops, int isvfat);
-
-extern int fat_flush_inodes(struct super_block *sb, struct inode *i1,
-		            struct inode *i2);
-/* fat/misc.c */
-extern void fat_fs_panic(struct super_block *s, const char *fmt, ...);
-extern void fat_clusters_flush(struct super_block *sb);
-extern int fat_chain_add(struct inode *inode, int new_dclus, int nr_cluster);
-extern int date_dos2unix(unsigned short time, unsigned short date, int tz_utc);
-extern void fat_date_unix2dos(int unix_date, __le16 *time, __le16 *date,
-			      int tz_utc);
-extern int fat_sync_bhs(struct buffer_head **bhs, int nr_bhs);
-
-int fat_cache_init(void);
-void fat_cache_destroy(void);
-
-#endif /* __KERNEL__ */
-
-#endif
+#endif /* !__KERNEL__ */
+#endif /* !_LINUX_MSDOS_FS_H */
diff --git a/include/linux/msi.h b/include/linux/msi.h
index 8f2939227207..d2b8a1e8ca11 100644
--- a/include/linux/msi.h
+++ b/include/linux/msi.h
@@ -10,8 +10,11 @@ struct msi_msg {
 };
 
 /* Helper functions */
+struct irq_desc;
 extern void mask_msi_irq(unsigned int irq);
 extern void unmask_msi_irq(unsigned int irq);
+extern void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg);
+extern void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg);
 extern void read_msi_msg(unsigned int irq, struct msi_msg *msg);
 extern void write_msi_msg(unsigned int irq, struct msi_msg *msg);
 
diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h
index d6fb115f5a07..00e2b575021f 100644
--- a/include/linux/mtd/cfi.h
+++ b/include/linux/mtd/cfi.h
@@ -12,6 +12,7 @@
 #include <linux/mtd/flashchip.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/cfi_endian.h>
+#include <linux/mtd/xip.h>
 
 #ifdef CONFIG_MTD_CFI_I1
 #define cfi_interleave(cfi) 1
@@ -281,9 +282,25 @@ struct cfi_private {
 /*
  * Returns the command address according to the given geometry.
  */
-static inline uint32_t cfi_build_cmd_addr(uint32_t cmd_ofs, int interleave, int type)
+static inline uint32_t cfi_build_cmd_addr(uint32_t cmd_ofs,
+				struct map_info *map, struct cfi_private *cfi)
 {
-	return (cmd_ofs * type) * interleave;
+	unsigned bankwidth = map_bankwidth(map);
+	unsigned interleave = cfi_interleave(cfi);
+	unsigned type = cfi->device_type;
+	uint32_t addr;
+	
+	addr = (cmd_ofs * type) * interleave;
+
+	/* Modify the unlock address if we are in compatiblity mode.
+	 * For 16bit devices on 8 bit busses
+	 * and 32bit devices on 16 bit busses
+	 * set the low bit of the alternating bit sequence of the address.
+	 */
+	if (((type * interleave) > bankwidth) && ((uint8_t)cmd_ofs == 0xaa))
+		addr |= (type >> 1)*interleave;
+
+	return  addr;
 }
 
 /*
@@ -429,8 +446,7 @@ static inline uint32_t cfi_send_gen_cmd(u_char cmd, uint32_t cmd_addr, uint32_t
 				int type, map_word *prev_val)
 {
 	map_word val;
-	uint32_t addr = base + cfi_build_cmd_addr(cmd_addr, cfi_interleave(cfi), type);
-
+	uint32_t addr = base + cfi_build_cmd_addr(cmd_addr, map, cfi);
 	val = cfi_build_cmd(cmd, map, cfi);
 
 	if (prev_val)
@@ -483,6 +499,13 @@ static inline void cfi_udelay(int us)
 	}
 }
 
+int __xipram cfi_qry_present(struct map_info *map, __u32 base,
+			     struct cfi_private *cfi);
+int __xipram cfi_qry_mode_on(uint32_t base, struct map_info *map,
+			     struct cfi_private *cfi);
+void __xipram cfi_qry_mode_off(uint32_t base, struct map_info *map,
+			       struct cfi_private *cfi);
+
 struct cfi_extquery *cfi_read_pri(struct map_info *map, uint16_t adr, uint16_t size,
 			     const char* name);
 struct cfi_fixup {
diff --git a/include/linux/mtd/flashchip.h b/include/linux/mtd/flashchip.h
index 08dd131301c1..d4f38c5fd44e 100644
--- a/include/linux/mtd/flashchip.h
+++ b/include/linux/mtd/flashchip.h
@@ -73,6 +73,10 @@ struct flchip {
 	int buffer_write_time;
 	int erase_time;
 
+	int word_write_time_max;
+	int buffer_write_time_max;
+	int erase_time_max;
+
 	void *priv;
 };
 
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 922636548558..eae26bb6430a 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -25,8 +25,10 @@
 #define MTD_ERASE_DONE          0x08
 #define MTD_ERASE_FAILED        0x10
 
+#define MTD_FAIL_ADDR_UNKNOWN 0xffffffff
+
 /* If the erase fails, fail_addr might indicate exactly which block failed.  If
-   fail_addr = 0xffffffff, the failure was not at the device level or was not
+   fail_addr = MTD_FAIL_ADDR_UNKNOWN, the failure was not at the device level or was not
    specific to any particular block. */
 struct erase_info {
 	struct mtd_info *mtd;
diff --git a/include/linux/mtd/nand-gpio.h b/include/linux/mtd/nand-gpio.h
new file mode 100644
index 000000000000..51534e50f7fc
--- /dev/null
+++ b/include/linux/mtd/nand-gpio.h
@@ -0,0 +1,19 @@
+#ifndef __LINUX_MTD_NAND_GPIO_H
+#define __LINUX_MTD_NAND_GPIO_H
+
+#include <linux/mtd/nand.h>
+
+struct gpio_nand_platdata {
+	int	gpio_nce;
+	int	gpio_nwp;
+	int	gpio_cle;
+	int	gpio_ale;
+	int	gpio_rdy;
+	void	(*adjust_parts)(struct gpio_nand_platdata *, size_t);
+	struct mtd_partition *parts;
+	unsigned int num_parts;
+	unsigned int options;
+	int	chip_delay;
+};
+
+#endif
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 81774e5facf4..733d3f3b4eb8 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -248,6 +248,7 @@ struct nand_hw_control {
  * @read_page_raw:	function to read a raw page without ECC
  * @write_page_raw:	function to write a raw page without ECC
  * @read_page:	function to read a page according to the ecc generator requirements
+ * @read_subpage:	function to read parts of the page covered by ECC.
  * @write_page:	function to write a page according to the ecc generator requirements
  * @read_oob:	function to read chip OOB data
  * @write_oob:	function to write chip OOB data
diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h
index d1b310c92eb4..0c6bbe28f38c 100644
--- a/include/linux/mtd/onenand_regs.h
+++ b/include/linux/mtd/onenand_regs.h
@@ -152,6 +152,8 @@
 #define ONENAND_SYS_CFG1_INT		(1 << 6)
 #define ONENAND_SYS_CFG1_IOBE		(1 << 5)
 #define ONENAND_SYS_CFG1_RDY_CONF	(1 << 4)
+#define ONENAND_SYS_CFG1_HF		(1 << 2)
+#define ONENAND_SYS_CFG1_SYNC_WRITE	(1 << 1)
 
 /*
  * Controller Status Register F240h (R)
diff --git a/include/linux/mtd/partitions.h b/include/linux/mtd/partitions.h
index 5014f7a9f5df..c92b4d439609 100644
--- a/include/linux/mtd/partitions.h
+++ b/include/linux/mtd/partitions.h
@@ -73,7 +73,6 @@ struct device;
 struct device_node;
 
 int __devinit of_mtd_parse_partitions(struct device *dev,
-                                      struct mtd_info *mtd,
                                       struct device_node *node,
                                       struct mtd_partition **pparts);
 
diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
new file mode 100644
index 000000000000..e77c1cea404d
--- /dev/null
+++ b/include/linux/mtd/sh_flctl.h
@@ -0,0 +1,125 @@
+/*
+ * SuperH FLCTL nand controller
+ *
+ * Copyright © 2008 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __SH_FLCTL_H__
+#define __SH_FLCTL_H__
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+
+/* FLCTL registers */
+#define FLCMNCR(f)		(f->reg + 0x0)
+#define FLCMDCR(f)		(f->reg + 0x4)
+#define FLCMCDR(f)		(f->reg + 0x8)
+#define FLADR(f)		(f->reg + 0xC)
+#define FLADR2(f)		(f->reg + 0x3C)
+#define FLDATAR(f)		(f->reg + 0x10)
+#define FLDTCNTR(f)		(f->reg + 0x14)
+#define FLINTDMACR(f)		(f->reg + 0x18)
+#define FLBSYTMR(f)		(f->reg + 0x1C)
+#define FLBSYCNT(f)		(f->reg + 0x20)
+#define FLDTFIFO(f)		(f->reg + 0x24)
+#define FLECFIFO(f)		(f->reg + 0x28)
+#define FLTRCR(f)		(f->reg + 0x2C)
+#define	FL4ECCRESULT0(f)	(f->reg + 0x80)
+#define	FL4ECCRESULT1(f)	(f->reg + 0x84)
+#define	FL4ECCRESULT2(f)	(f->reg + 0x88)
+#define	FL4ECCRESULT3(f)	(f->reg + 0x8C)
+#define	FL4ECCCR(f)		(f->reg + 0x90)
+#define	FL4ECCCNT(f)		(f->reg + 0x94)
+#define	FLERRADR(f)		(f->reg + 0x98)
+
+/* FLCMNCR control bits */
+#define ECCPOS2		(0x1 << 25)
+#define _4ECCCNTEN	(0x1 << 24)
+#define _4ECCEN		(0x1 << 23)
+#define _4ECCCORRECT	(0x1 << 22)
+#define SNAND_E		(0x1 << 18)	/* SNAND (0=512 1=2048)*/
+#define QTSEL_E		(0x1 << 17)
+#define ENDIAN		(0x1 << 16)	/* 1 = little endian */
+#define FCKSEL_E	(0x1 << 15)
+#define ECCPOS_00	(0x00 << 12)
+#define ECCPOS_01	(0x01 << 12)
+#define ECCPOS_02	(0x02 << 12)
+#define ACM_SACCES_MODE	(0x01 << 10)
+#define NANWF_E		(0x1 << 9)
+#define SE_D		(0x1 << 8)	/* Spare area disable */
+#define	CE1_ENABLE	(0x1 << 4)	/* Chip Enable 1 */
+#define	CE0_ENABLE	(0x1 << 3)	/* Chip Enable 0 */
+#define	TYPESEL_SET	(0x1 << 0)
+
+/* FLCMDCR control bits */
+#define ADRCNT2_E	(0x1 << 31)	/* 5byte address enable */
+#define ADRMD_E		(0x1 << 26)	/* Sector address access */
+#define CDSRC_E		(0x1 << 25)	/* Data buffer selection */
+#define DOSR_E		(0x1 << 24)	/* Status read check */
+#define SELRW		(0x1 << 21)	/*  0:read 1:write */
+#define DOADR_E		(0x1 << 20)	/* Address stage execute */
+#define ADRCNT_1	(0x00 << 18)	/* Address data bytes: 1byte */
+#define ADRCNT_2	(0x01 << 18)	/* Address data bytes: 2byte */
+#define ADRCNT_3	(0x02 << 18)	/* Address data bytes: 3byte */
+#define ADRCNT_4	(0x03 << 18)	/* Address data bytes: 4byte */
+#define DOCMD2_E	(0x1 << 17)	/* 2nd cmd stage execute */
+#define DOCMD1_E	(0x1 << 16)	/* 1st cmd stage execute */
+
+/* FLTRCR control bits */
+#define TRSTRT		(0x1 << 0)	/* translation start */
+#define TREND		(0x1 << 1)	/* translation end */
+
+/* FL4ECCCR control bits */
+#define	_4ECCFA		(0x1 << 2)	/* 4 symbols correct fault */
+#define	_4ECCEND	(0x1 << 1)	/* 4 symbols end */
+#define	_4ECCEXST	(0x1 << 0)	/* 4 symbols exist */
+
+#define INIT_FL4ECCRESULT_VAL	0x03FF03FF
+#define LOOP_TIMEOUT_MAX	0x00010000
+
+#define mtd_to_flctl(mtd)	container_of(mtd, struct sh_flctl, mtd)
+
+struct sh_flctl {
+	struct mtd_info		mtd;
+	struct nand_chip	chip;
+	void __iomem		*reg;
+
+	uint8_t	done_buff[2048 + 64];	/* max size 2048 + 64 */
+	int	read_bytes;
+	int	index;
+	int	seqin_column;		/* column in SEQIN cmd */
+	int	seqin_page_addr;	/* page_addr in SEQIN cmd */
+	uint32_t seqin_read_cmd;		/* read cmd in SEQIN cmd */
+	int	erase1_page_addr;	/* page_addr in ERASE1 cmd */
+	uint32_t erase_ADRCNT;		/* bits of FLCMDCR in ERASE1 cmd */
+	uint32_t rw_ADRCNT;	/* bits of FLCMDCR in READ WRITE cmd */
+
+	int	hwecc_cant_correct[4];
+
+	unsigned page_size:1;	/* NAND page size (0 = 512, 1 = 2048) */
+	unsigned hwecc:1;	/* Hardware ECC (0 = disabled, 1 = enabled) */
+};
+
+struct sh_flctl_platform_data {
+	struct mtd_partition	*parts;
+	int			nr_parts;
+	unsigned long		flcmncr_val;
+
+	unsigned has_hwecc:1;
+};
+
+#endif	/* __SH_FLCTL_H__ */
diff --git a/include/linux/mutex.h b/include/linux/mutex.h
index bc6da10ceee0..7a0e5c4f8072 100644
--- a/include/linux/mutex.h
+++ b/include/linux/mutex.h
@@ -144,6 +144,8 @@ extern int __must_check mutex_lock_killable(struct mutex *lock);
 /*
  * NOTE: mutex_trylock() follows the spin_trylock() convention,
  *       not the down_trylock() convention!
+ *
+ * Returns 1 if the mutex has been acquired successfully, and 0 on contention.
  */
 extern int mutex_trylock(struct mutex *lock);
 extern void mutex_unlock(struct mutex *lock);
diff --git a/include/linux/namei.h b/include/linux/namei.h
index 68f8c3203c89..99eb80306dc5 100644
--- a/include/linux/namei.h
+++ b/include/linux/namei.h
@@ -51,8 +51,10 @@ enum {LAST_NORM, LAST_ROOT, LAST_DOT, LAST_DOTDOT, LAST_BIND};
 /*
  * Intent data
  */
-#define LOOKUP_OPEN		(0x0100)
-#define LOOKUP_CREATE		(0x0200)
+#define LOOKUP_OPEN		0x0100
+#define LOOKUP_CREATE		0x0200
+#define LOOKUP_EXCL		0x0400
+#define LOOKUP_RENAME_TARGET	0x0800
 
 extern int user_path_at(int, const char __user *, unsigned, struct path *);
 
@@ -61,6 +63,8 @@ extern int user_path_at(int, const char __user *, unsigned, struct path *);
 #define user_path_dir(name, path) \
 	user_path_at(AT_FDCWD, name, LOOKUP_FOLLOW | LOOKUP_DIRECTORY, path)
 
+extern int kern_path(const char *, unsigned, struct path *);
+
 extern int path_lookup(const char *, unsigned, struct nameidata *);
 extern int vfs_path_lookup(struct dentry *, struct vfsmount *,
 			   const char *, unsigned int, struct nameidata *);
diff --git a/include/linux/net.h b/include/linux/net.h
index 6dc14a240042..4515efae4c39 100644
--- a/include/linux/net.h
+++ b/include/linux/net.h
@@ -40,7 +40,7 @@
 #define SYS_GETSOCKOPT	15		/* sys_getsockopt(2)		*/
 #define SYS_SENDMSG	16		/* sys_sendmsg(2)		*/
 #define SYS_RECVMSG	17		/* sys_recvmsg(2)		*/
-#define SYS_PACCEPT	18		/* sys_paccept(2)		*/
+#define SYS_ACCEPT4	18		/* sys_accept4(2)		*/
 
 typedef enum {
 	SS_FREE = 0,			/* not allocated		*/
@@ -100,7 +100,7 @@ enum sock_type {
  * remaining bits are used as flags. */
 #define SOCK_TYPE_MASK 0xf
 
-/* Flags for socket, socketpair, paccept */
+/* Flags for socket, socketpair, accept4 */
 #define SOCK_CLOEXEC	O_CLOEXEC
 #ifndef SOCK_NONBLOCK
 #define SOCK_NONBLOCK	O_NONBLOCK
@@ -223,8 +223,6 @@ extern int 	     sock_map_fd(struct socket *sock, int flags);
 extern struct socket *sockfd_lookup(int fd, int *err);
 #define		     sockfd_put(sock) fput(sock->file)
 extern int	     net_ratelimit(void);
-extern long	     do_accept(int fd, struct sockaddr __user *upeer_sockaddr,
-			       int __user *upeer_addrlen, int flags);
 
 #define net_random()		random32()
 #define net_srandom(seed)	srandom32((__force u32)seed)
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index 64875859d654..41e1224651cf 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -43,6 +43,9 @@
 
 #include <net/net_namespace.h>
 #include <net/dsa.h>
+#ifdef CONFIG_DCB
+#include <net/dcbnl.h>
+#endif
 
 struct vlan_group;
 struct ethtool_ops;
@@ -311,14 +314,16 @@ struct napi_struct {
 	spinlock_t		poll_lock;
 	int			poll_owner;
 	struct net_device	*dev;
-	struct list_head	dev_list;
 #endif
+	struct list_head	dev_list;
+	struct sk_buff		*gro_list;
 };
 
 enum
 {
 	NAPI_STATE_SCHED,	/* Poll is scheduled */
 	NAPI_STATE_DISABLE,	/* Disable pending */
+	NAPI_STATE_NPSVC,	/* Netpoll - don't dequeue from poll_list */
 };
 
 extern void __napi_schedule(struct napi_struct *n);
@@ -372,22 +377,8 @@ static inline int napi_reschedule(struct napi_struct *napi)
  *
  * Mark NAPI processing as complete.
  */
-static inline void __napi_complete(struct napi_struct *n)
-{
-	BUG_ON(!test_bit(NAPI_STATE_SCHED, &n->state));
-	list_del(&n->poll_list);
-	smp_mb__before_clear_bit();
-	clear_bit(NAPI_STATE_SCHED, &n->state);
-}
-
-static inline void napi_complete(struct napi_struct *n)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-	__napi_complete(n);
-	local_irq_restore(flags);
-}
+extern void __napi_complete(struct napi_struct *n);
+extern void napi_complete(struct napi_struct *n);
 
 /**
  *	napi_disable - prevent NAPI from scheduling
@@ -451,6 +442,147 @@ struct netdev_queue {
 	struct Qdisc		*qdisc_sleeping;
 } ____cacheline_aligned_in_smp;
 
+
+/*
+ * This structure defines the management hooks for network devices.
+ * The following hooks can be defined; unless noted otherwise, they are
+ * optional and can be filled with a null pointer.
+ *
+ * int (*ndo_init)(struct net_device *dev);
+ *     This function is called once when network device is registered.
+ *     The network device can use this to any late stage initializaton
+ *     or semantic validattion. It can fail with an error code which will
+ *     be propogated back to register_netdev
+ *
+ * void (*ndo_uninit)(struct net_device *dev);
+ *     This function is called when device is unregistered or when registration
+ *     fails. It is not called if init fails.
+ *
+ * int (*ndo_open)(struct net_device *dev);
+ *     This function is called when network device transistions to the up
+ *     state.
+ *
+ * int (*ndo_stop)(struct net_device *dev);
+ *     This function is called when network device transistions to the down
+ *     state.
+ *
+ * int (*ndo_hard_start_xmit)(struct sk_buff *skb, struct net_device *dev);
+ *	Called when a packet needs to be transmitted.
+ *	Must return NETDEV_TX_OK , NETDEV_TX_BUSY, or NETDEV_TX_LOCKED,
+ *	Required can not be NULL.
+ *
+ * u16 (*ndo_select_queue)(struct net_device *dev, struct sk_buff *skb);
+ *	Called to decide which queue to when device supports multiple
+ *	transmit queues.
+ *
+ * void (*ndo_change_rx_flags)(struct net_device *dev, int flags);
+ *	This function is called to allow device receiver to make
+ *	changes to configuration when multicast or promiscious is enabled.
+ *
+ * void (*ndo_set_rx_mode)(struct net_device *dev);
+ *	This function is called device changes address list filtering.
+ *
+ * void (*ndo_set_multicast_list)(struct net_device *dev);
+ *	This function is called when the multicast address list changes.
+ *
+ * int (*ndo_set_mac_address)(struct net_device *dev, void *addr);
+ *	This function  is called when the Media Access Control address
+ *	needs to be changed. If not this interface is not defined, the
+ *	mac address can not be changed.
+ *
+ * int (*ndo_validate_addr)(struct net_device *dev);
+ *	Test if Media Access Control address is valid for the device.
+ *
+ * int (*ndo_do_ioctl)(struct net_device *dev, struct ifreq *ifr, int cmd);
+ *	Called when a user request an ioctl which can't be handled by
+ *	the generic interface code. If not defined ioctl's return
+ *	not supported error code.
+ *
+ * int (*ndo_set_config)(struct net_device *dev, struct ifmap *map);
+ *	Used to set network devices bus interface parameters. This interface
+ *	is retained for legacy reason, new devices should use the bus
+ *	interface (PCI) for low level management.
+ *
+ * int (*ndo_change_mtu)(struct net_device *dev, int new_mtu);
+ *	Called when a user wants to change the Maximum Transfer Unit
+ *	of a device. If not defined, any request to change MTU will
+ *	will return an error.
+ *
+ * void (*ndo_tx_timeout)(struct net_device *dev);
+ *	Callback uses when the transmitter has not made any progress
+ *	for dev->watchdog ticks.
+ *
+ * struct net_device_stats* (*get_stats)(struct net_device *dev);
+ *	Called when a user wants to get the network device usage
+ *	statistics. If not defined, the counters in dev->stats will
+ *	be used.
+ *
+ * void (*ndo_vlan_rx_register)(struct net_device *dev, struct vlan_group *grp);
+ *	If device support VLAN receive accleration
+ *	(ie. dev->features & NETIF_F_HW_VLAN_RX), then this function is called
+ *	when vlan groups for the device changes.  Note: grp is NULL
+ *	if no vlan's groups are being used.
+ *
+ * void (*ndo_vlan_rx_add_vid)(struct net_device *dev, unsigned short vid);
+ *	If device support VLAN filtering (dev->features & NETIF_F_HW_VLAN_FILTER)
+ *	this function is called when a VLAN id is registered.
+ *
+ * void (*ndo_vlan_rx_kill_vid)(struct net_device *dev, unsigned short vid);
+ *	If device support VLAN filtering (dev->features & NETIF_F_HW_VLAN_FILTER)
+ *	this function is called when a VLAN id is unregistered.
+ *
+ * void (*ndo_poll_controller)(struct net_device *dev);
+ */
+#define HAVE_NET_DEVICE_OPS
+struct net_device_ops {
+	int			(*ndo_init)(struct net_device *dev);
+	void			(*ndo_uninit)(struct net_device *dev);
+	int			(*ndo_open)(struct net_device *dev);
+	int			(*ndo_stop)(struct net_device *dev);
+	int			(*ndo_start_xmit) (struct sk_buff *skb,
+						   struct net_device *dev);
+	u16			(*ndo_select_queue)(struct net_device *dev,
+						    struct sk_buff *skb);
+#define HAVE_CHANGE_RX_FLAGS
+	void			(*ndo_change_rx_flags)(struct net_device *dev,
+						       int flags);
+#define HAVE_SET_RX_MODE
+	void			(*ndo_set_rx_mode)(struct net_device *dev);
+#define HAVE_MULTICAST
+	void			(*ndo_set_multicast_list)(struct net_device *dev);
+#define HAVE_SET_MAC_ADDR
+	int			(*ndo_set_mac_address)(struct net_device *dev,
+						       void *addr);
+#define HAVE_VALIDATE_ADDR
+	int			(*ndo_validate_addr)(struct net_device *dev);
+#define HAVE_PRIVATE_IOCTL
+	int			(*ndo_do_ioctl)(struct net_device *dev,
+					        struct ifreq *ifr, int cmd);
+#define HAVE_SET_CONFIG
+	int			(*ndo_set_config)(struct net_device *dev,
+					          struct ifmap *map);
+#define HAVE_CHANGE_MTU
+	int			(*ndo_change_mtu)(struct net_device *dev,
+						  int new_mtu);
+	int			(*ndo_neigh_setup)(struct net_device *dev,
+						   struct neigh_parms *);
+#define HAVE_TX_TIMEOUT
+	void			(*ndo_tx_timeout) (struct net_device *dev);
+
+	struct net_device_stats* (*ndo_get_stats)(struct net_device *dev);
+
+	void			(*ndo_vlan_rx_register)(struct net_device *dev,
+						        struct vlan_group *grp);
+	void			(*ndo_vlan_rx_add_vid)(struct net_device *dev,
+						       unsigned short vid);
+	void			(*ndo_vlan_rx_kill_vid)(struct net_device *dev,
+						        unsigned short vid);
+#ifdef CONFIG_NET_POLL_CONTROLLER
+#define HAVE_NETDEV_POLL
+	void                    (*ndo_poll_controller)(struct net_device *dev);
+#endif
+};
+
 /*
  *	The DEVICE structure.
  *	Actually, this whole structure is a big mistake.  It mixes I/O
@@ -495,14 +627,7 @@ struct net_device
 	unsigned long		state;
 
 	struct list_head	dev_list;
-#ifdef CONFIG_NETPOLL
 	struct list_head	napi_list;
-#endif
-	
-	/* The device initialization function. Called only once. */
-	int			(*init)(struct net_device *dev);
-
-	/* ------- Fields preinitialized in Space.c finish here ------- */
 
 	/* Net device features */
 	unsigned long		features;
@@ -521,6 +646,7 @@ struct net_device
 #define NETIF_F_LLTX		4096	/* LockLess TX - deprecated. Please */
 					/* do not use LLTX in new drivers */
 #define NETIF_F_NETNS_LOCAL	8192	/* Does not change network namespaces */
+#define NETIF_F_GRO		16384	/* Generic receive offload */
 #define NETIF_F_LRO		32768	/* large receive offload */
 
 	/* Segmentation offload features */
@@ -541,12 +667,18 @@ struct net_device
 #define NETIF_F_V6_CSUM		(NETIF_F_GEN_CSUM | NETIF_F_IPV6_CSUM)
 #define NETIF_F_ALL_CSUM	(NETIF_F_V4_CSUM | NETIF_F_V6_CSUM)
 
+	/*
+	 * If one device supports one of these features, then enable them
+	 * for all in netdev_increment_features.
+	 */
+#define NETIF_F_ONE_FOR_ALL	(NETIF_F_GSO_SOFTWARE | NETIF_F_GSO_ROBUST | \
+				 NETIF_F_SG | NETIF_F_HIGHDMA |		\
+				 NETIF_F_FRAGLIST)
+
 	/* Interface index. Unique device identifier	*/
 	int			ifindex;
 	int			iflink;
 
-
-	struct net_device_stats* (*get_stats)(struct net_device *dev);
 	struct net_device_stats	stats;
 
 #ifdef CONFIG_WIRELESS_EXT
@@ -556,18 +688,13 @@ struct net_device
 	/* Instance data managed by the core of Wireless Extensions. */
 	struct iw_public_data *	wireless_data;
 #endif
+	/* Management operations */
+	const struct net_device_ops *netdev_ops;
 	const struct ethtool_ops *ethtool_ops;
 
 	/* Hardware header description */
 	const struct header_ops *header_ops;
 
-	/*
-	 * This marks the end of the "visible" part of the structure. All
-	 * fields hereafter are internal to the system, and may change at
-	 * will (read: may be cleaned up at will).
-	 */
-
-
 	unsigned int		flags;	/* interface flags (a la BSD)	*/
 	unsigned short		gflags;
         unsigned short          priv_flags; /* Like 'flags' but invisible to userspace. */
@@ -626,7 +753,7 @@ struct net_device
 	unsigned long		last_rx;	/* Time of last Rx	*/
 	/* Interface address info used in eth_type_trans() */
 	unsigned char		dev_addr[MAX_ADDR_LEN];	/* hw address, (before bcast 
-							because most packets are unicast) */
+							   because most packets are unicast) */
 
 	unsigned char		broadcast[MAX_ADDR_LEN];	/* hw bcast add	*/
 
@@ -645,18 +772,12 @@ struct net_device
 /*
  * One part is mostly used on xmit path (device)
  */
-	void			*priv;	/* pointer to private data	*/
-	int			(*hard_start_xmit) (struct sk_buff *skb,
-						    struct net_device *dev);
 	/* These may be needed for future network-power-down code. */
 	unsigned long		trans_start;	/* Time (in jiffies) of last Tx	*/
 
 	int			watchdog_timeo; /* used by dev_watchdog() */
 	struct timer_list	watchdog_timer;
 
-/*
- * refcnt is a very hot point, so align it on SMP
- */
 	/* Number of references to this device */
 	atomic_t		refcnt ____cacheline_aligned_in_smp;
 
@@ -675,56 +796,12 @@ struct net_device
 	       NETREG_RELEASED,		/* called free_netdev */
 	} reg_state;
 
-	/* Called after device is detached from network. */
-	void			(*uninit)(struct net_device *dev);
-	/* Called after last user reference disappears. */
-	void			(*destructor)(struct net_device *dev);
-
-	/* Pointers to interface service routines.	*/
-	int			(*open)(struct net_device *dev);
-	int			(*stop)(struct net_device *dev);
-#define HAVE_NETDEV_POLL
-#define HAVE_CHANGE_RX_FLAGS
-	void			(*change_rx_flags)(struct net_device *dev,
-						   int flags);
-#define HAVE_SET_RX_MODE
-	void			(*set_rx_mode)(struct net_device *dev);
-#define HAVE_MULTICAST			 
-	void			(*set_multicast_list)(struct net_device *dev);
-#define HAVE_SET_MAC_ADDR  		 
-	int			(*set_mac_address)(struct net_device *dev,
-						   void *addr);
-#define HAVE_VALIDATE_ADDR
-	int			(*validate_addr)(struct net_device *dev);
-#define HAVE_PRIVATE_IOCTL
-	int			(*do_ioctl)(struct net_device *dev,
-					    struct ifreq *ifr, int cmd);
-#define HAVE_SET_CONFIG
-	int			(*set_config)(struct net_device *dev,
-					      struct ifmap *map);
-#define HAVE_CHANGE_MTU
-	int			(*change_mtu)(struct net_device *dev, int new_mtu);
+	/* Called from unregister, can be used to call free_netdev */
+	void (*destructor)(struct net_device *dev);
 
-#define HAVE_TX_TIMEOUT
-	void			(*tx_timeout) (struct net_device *dev);
-
-	void			(*vlan_rx_register)(struct net_device *dev,
-						    struct vlan_group *grp);
-	void			(*vlan_rx_add_vid)(struct net_device *dev,
-						   unsigned short vid);
-	void			(*vlan_rx_kill_vid)(struct net_device *dev,
-						    unsigned short vid);
-
-	int			(*neigh_setup)(struct net_device *dev, struct neigh_parms *);
 #ifdef CONFIG_NETPOLL
 	struct netpoll_info	*npinfo;
 #endif
-#ifdef CONFIG_NET_POLL_CONTROLLER
-	void                    (*poll_controller)(struct net_device *dev);
-#endif
-
-	u16			(*select_queue)(struct net_device *dev,
-						struct sk_buff *skb);
 
 #ifdef CONFIG_NET_NS
 	/* Network namespace this network device is inside */
@@ -755,6 +832,49 @@ struct net_device
 	/* for setting kernel sock attribute on TCP connection setup */
 #define GSO_MAX_SIZE		65536
 	unsigned int		gso_max_size;
+
+#ifdef CONFIG_DCB
+	/* Data Center Bridging netlink ops */
+	struct dcbnl_rtnl_ops *dcbnl_ops;
+#endif
+
+#ifdef CONFIG_COMPAT_NET_DEV_OPS
+	struct {
+		int			(*init)(struct net_device *dev);
+		void			(*uninit)(struct net_device *dev);
+		int			(*open)(struct net_device *dev);
+		int			(*stop)(struct net_device *dev);
+		int			(*hard_start_xmit) (struct sk_buff *skb,
+							    struct net_device *dev);
+		u16			(*select_queue)(struct net_device *dev,
+							struct sk_buff *skb);
+		void			(*change_rx_flags)(struct net_device *dev,
+							   int flags);
+		void			(*set_rx_mode)(struct net_device *dev);
+		void			(*set_multicast_list)(struct net_device *dev);
+		int			(*set_mac_address)(struct net_device *dev,
+							   void *addr);
+		int			(*validate_addr)(struct net_device *dev);
+		int			(*do_ioctl)(struct net_device *dev,
+						    struct ifreq *ifr, int cmd);
+		int			(*set_config)(struct net_device *dev,
+						      struct ifmap *map);
+		int			(*change_mtu)(struct net_device *dev, int new_mtu);
+		int			(*neigh_setup)(struct net_device *dev,
+						       struct neigh_parms *);
+		void			(*tx_timeout) (struct net_device *dev);
+		struct net_device_stats* (*get_stats)(struct net_device *dev);
+		void			(*vlan_rx_register)(struct net_device *dev,
+							    struct vlan_group *grp);
+		void			(*vlan_rx_add_vid)(struct net_device *dev,
+							   unsigned short vid);
+		void			(*vlan_rx_kill_vid)(struct net_device *dev,
+							    unsigned short vid);
+#ifdef CONFIG_NET_POLL_CONTROLLER
+		void                    (*poll_controller)(struct net_device *dev);
+#endif
+	};
+#endif
 };
 #define to_net_dev(d) container_of(d, struct net_device, dev)
 
@@ -850,22 +970,8 @@ static inline void *netdev_priv(const struct net_device *dev)
  * netif_napi_add() must be used to initialize a napi context prior to calling
  * *any* of the other napi related functions.
  */
-static inline void netif_napi_add(struct net_device *dev,
-				  struct napi_struct *napi,
-				  int (*poll)(struct napi_struct *, int),
-				  int weight)
-{
-	INIT_LIST_HEAD(&napi->poll_list);
-	napi->poll = poll;
-	napi->weight = weight;
-#ifdef CONFIG_NETPOLL
-	napi->dev = dev;
-	list_add(&napi->dev_list, &dev->napi_list);
-	spin_lock_init(&napi->poll_lock);
-	napi->poll_owner = -1;
-#endif
-	set_bit(NAPI_STATE_SCHED, &napi->state);
-}
+void netif_napi_add(struct net_device *dev, struct napi_struct *napi,
+		    int (*poll)(struct napi_struct *, int), int weight);
 
 /**
  *  netif_napi_del - remove a napi context
@@ -873,12 +979,20 @@ static inline void netif_napi_add(struct net_device *dev,
  *
  *  netif_napi_del() removes a napi context from the network device napi list
  */
-static inline void netif_napi_del(struct napi_struct *napi)
-{
-#ifdef CONFIG_NETPOLL
-	list_del(&napi->dev_list);
-#endif
-}
+void netif_napi_del(struct napi_struct *napi);
+
+struct napi_gro_cb {
+	/* This is non-zero if the packet may be of the same flow. */
+	int same_flow;
+
+	/* This is non-zero if the packet cannot be merged with the new skb. */
+	int flush;
+
+	/* Number of segments aggregated. */
+	int count;
+};
+
+#define NAPI_GRO_CB(skb) ((struct napi_gro_cb *)(skb)->cb)
 
 struct packet_type {
 	__be16			type;	/* This is really htons(ether_type). */
@@ -890,6 +1004,9 @@ struct packet_type {
 	struct sk_buff		*(*gso_segment)(struct sk_buff *skb,
 						int features);
 	int			(*gso_send_check)(struct sk_buff *skb);
+	struct sk_buff		**(*gro_receive)(struct sk_buff **head,
+					       struct sk_buff *skb);
+	int			(*gro_complete)(struct sk_buff *skb);
 	void			*af_packet_priv;
 	struct list_head	list;
 };
@@ -1243,6 +1360,9 @@ extern int		netif_rx(struct sk_buff *skb);
 extern int		netif_rx_ni(struct sk_buff *skb);
 #define HAVE_NETIF_RECEIVE_SKB 1
 extern int		netif_receive_skb(struct sk_buff *skb);
+extern void		napi_gro_flush(struct napi_struct *napi);
+extern int		napi_gro_receive(struct napi_struct *napi,
+					 struct sk_buff *skb);
 extern void		netif_nit_deliver(struct sk_buff *skb);
 extern int		dev_valid_name(const char *name);
 extern int		dev_ioctl(struct net *net, unsigned int cmd, void __user *);
@@ -1435,8 +1555,7 @@ static inline u32 netif_msg_init(int debug_value, int default_msg_enable_bits)
 }
 
 /* Test if receive needs to be scheduled but only if up */
-static inline int netif_rx_schedule_prep(struct net_device *dev,
-					 struct napi_struct *napi)
+static inline int netif_rx_schedule_prep(struct napi_struct *napi)
 {
 	return napi_schedule_prep(napi);
 }
@@ -1444,27 +1563,24 @@ static inline int netif_rx_schedule_prep(struct net_device *dev,
 /* Add interface to tail of rx poll list. This assumes that _prep has
  * already been called and returned 1.
  */
-static inline void __netif_rx_schedule(struct net_device *dev,
-				       struct napi_struct *napi)
+static inline void __netif_rx_schedule(struct napi_struct *napi)
 {
 	__napi_schedule(napi);
 }
 
 /* Try to reschedule poll. Called by irq handler. */
 
-static inline void netif_rx_schedule(struct net_device *dev,
-				     struct napi_struct *napi)
+static inline void netif_rx_schedule(struct napi_struct *napi)
 {
-	if (netif_rx_schedule_prep(dev, napi))
-		__netif_rx_schedule(dev, napi);
+	if (netif_rx_schedule_prep(napi))
+		__netif_rx_schedule(napi);
 }
 
 /* Try to reschedule poll. Called by dev->poll() after netif_rx_complete().  */
-static inline int netif_rx_reschedule(struct net_device *dev,
-				      struct napi_struct *napi)
+static inline int netif_rx_reschedule(struct napi_struct *napi)
 {
 	if (napi_schedule_prep(napi)) {
-		__netif_rx_schedule(dev, napi);
+		__netif_rx_schedule(napi);
 		return 1;
 	}
 	return 0;
@@ -1473,8 +1589,7 @@ static inline int netif_rx_reschedule(struct net_device *dev,
 /* same as netif_rx_complete, except that local_irq_save(flags)
  * has already been issued
  */
-static inline void __netif_rx_complete(struct net_device *dev,
-				       struct napi_struct *napi)
+static inline void __netif_rx_complete(struct napi_struct *napi)
 {
 	__napi_complete(napi);
 }
@@ -1484,14 +1599,9 @@ static inline void __netif_rx_complete(struct net_device *dev,
  * it completes the work. The device cannot be out of poll list at this
  * moment, it is BUG().
  */
-static inline void netif_rx_complete(struct net_device *dev,
-				     struct napi_struct *napi)
+static inline void netif_rx_complete(struct napi_struct *napi)
 {
-	unsigned long flags;
-
-	local_irq_save(flags);
-	__netif_rx_complete(dev, napi);
-	local_irq_restore(flags);
+	napi_complete(napi);
 }
 
 static inline void __netif_tx_lock(struct netdev_queue *txq, int cpu)
@@ -1529,7 +1639,6 @@ static inline void __netif_tx_unlock_bh(struct netdev_queue *txq)
 /**
  *	netif_tx_lock - grab network device transmit lock
  *	@dev: network device
- *	@cpu: cpu number of lock owner
  *
  * Get network device transmit lock
  */
@@ -1669,6 +1778,8 @@ extern void		netdev_features_change(struct net_device *dev);
 /* Load a device via the kmod */
 extern void		dev_load(struct net *net, const char *name);
 extern void		dev_mcast_init(void);
+extern const struct net_device_stats *dev_get_stats(struct net_device *dev);
+
 extern int		netdev_max_backlog;
 extern int		weight_p;
 extern int		netdev_set_master(struct net_device *dev, struct net_device *master);
@@ -1698,7 +1809,9 @@ extern char *netdev_drivername(const struct net_device *dev, char *buffer, int l
 
 extern void linkwatch_run_queue(void);
 
-extern int netdev_compute_features(unsigned long all, unsigned long one);
+unsigned long netdev_increment_features(unsigned long all, unsigned long one,
+					unsigned long mask);
+unsigned long netdev_fix_features(unsigned long features, const char *name);
 
 static inline int net_gso_ok(int features, int gso_type)
 {
@@ -1715,6 +1828,8 @@ static inline int netif_needs_gso(struct net_device *dev, struct sk_buff *skb)
 {
 	return skb_is_gso(skb) &&
 	       (!skb_gso_ok(skb, dev->features) ||
+	        (skb_shinfo(skb)->frag_list &&
+	         !(dev->features & NETIF_F_FRAGLIST)) ||
 		unlikely(skb->ip_summed != CHECKSUM_PARTIAL));
 }
 
@@ -1733,26 +1848,31 @@ static inline int skb_bond_should_drop(struct sk_buff *skb)
 	struct net_device *dev = skb->dev;
 	struct net_device *master = dev->master;
 
-	if (master &&
-	    (dev->priv_flags & IFF_SLAVE_INACTIVE)) {
-		if ((dev->priv_flags & IFF_SLAVE_NEEDARP) &&
-		    skb->protocol == __constant_htons(ETH_P_ARP))
-			return 0;
+	if (master) {
+		if (master->priv_flags & IFF_MASTER_ARPMON)
+			dev->last_rx = jiffies;
 
-		if (master->priv_flags & IFF_MASTER_ALB) {
-			if (skb->pkt_type != PACKET_BROADCAST &&
-			    skb->pkt_type != PACKET_MULTICAST)
+		if (dev->priv_flags & IFF_SLAVE_INACTIVE) {
+			if ((dev->priv_flags & IFF_SLAVE_NEEDARP) &&
+			    skb->protocol == __constant_htons(ETH_P_ARP))
 				return 0;
-		}
-		if (master->priv_flags & IFF_MASTER_8023AD &&
-		    skb->protocol == __constant_htons(ETH_P_SLOW))
-			return 0;
 
-		return 1;
+			if (master->priv_flags & IFF_MASTER_ALB) {
+				if (skb->pkt_type != PACKET_BROADCAST &&
+				    skb->pkt_type != PACKET_MULTICAST)
+					return 0;
+			}
+			if (master->priv_flags & IFF_MASTER_8023AD &&
+			    skb->protocol == __constant_htons(ETH_P_SLOW))
+				return 0;
+
+			return 1;
+		}
 	}
 	return 0;
 }
 
+extern struct pernet_operations __net_initdata loopback_net_ops;
 #endif /* __KERNEL__ */
 
 #endif	/* _LINUX_DEV_H */
diff --git a/include/linux/netfilter/nfnetlink.h b/include/linux/netfilter/nfnetlink.h
index 0d8424f76899..7d8e0455ccac 100644
--- a/include/linux/netfilter/nfnetlink.h
+++ b/include/linux/netfilter/nfnetlink.h
@@ -78,6 +78,9 @@ extern int nfnetlink_send(struct sk_buff *skb, u32 pid, unsigned group,
 			  int echo);
 extern int nfnetlink_unicast(struct sk_buff *skb, u_int32_t pid, int flags);
 
+extern void nfnl_lock(void);
+extern void nfnl_unlock(void);
+
 #define MODULE_ALIAS_NFNL_SUBSYS(subsys) \
 	MODULE_ALIAS("nfnetlink-subsys-" __stringify(subsys))
 
diff --git a/include/linux/netfilter/nfnetlink_conntrack.h b/include/linux/netfilter/nfnetlink_conntrack.h
index c19595c89304..29fe9ea1d346 100644
--- a/include/linux/netfilter/nfnetlink_conntrack.h
+++ b/include/linux/netfilter/nfnetlink_conntrack.h
@@ -141,6 +141,7 @@ enum ctattr_protonat {
 #define CTA_PROTONAT_MAX (__CTA_PROTONAT_MAX - 1)
 
 enum ctattr_natseq {
+	CTA_NAT_SEQ_UNSPEC,
 	CTA_NAT_SEQ_CORRECTION_POS,
 	CTA_NAT_SEQ_OFFSET_BEFORE,
 	CTA_NAT_SEQ_OFFSET_AFTER,
diff --git a/include/linux/netfilter/x_tables.h b/include/linux/netfilter/x_tables.h
index be41b609c88f..e52ce475d19f 100644
--- a/include/linux/netfilter/x_tables.h
+++ b/include/linux/netfilter/x_tables.h
@@ -251,7 +251,7 @@ struct xt_target_param {
  */
 struct xt_tgchk_param {
 	const char *table;
-	void *entryinfo;
+	const void *entryinfo;
 	const struct xt_target *target;
 	void *targinfo;
 	unsigned int hook_mask;
diff --git a/include/linux/netfilter_bridge/ebtables.h b/include/linux/netfilter_bridge/ebtables.h
index d45e29cd1cfb..e40ddb94b1af 100644
--- a/include/linux/netfilter_bridge/ebtables.h
+++ b/include/linux/netfilter_bridge/ebtables.h
@@ -300,7 +300,8 @@ struct ebt_table
 
 #define EBT_ALIGN(s) (((s) + (__alignof__(struct ebt_replace)-1)) & \
 		     ~(__alignof__(struct ebt_replace)-1))
-extern int ebt_register_table(struct ebt_table *table);
+extern struct ebt_table *ebt_register_table(struct net *net,
+					    struct ebt_table *table);
 extern void ebt_unregister_table(struct ebt_table *table);
 extern unsigned int ebt_do_table(unsigned int hook, struct sk_buff *skb,
    const struct net_device *in, const struct net_device *out,
diff --git a/include/linux/netfilter_ipv4/ipt_policy.h b/include/linux/netfilter_ipv4/ipt_policy.h
index b9478a255301..1037fb2cd206 100644
--- a/include/linux/netfilter_ipv4/ipt_policy.h
+++ b/include/linux/netfilter_ipv4/ipt_policy.h
@@ -1,6 +1,8 @@
 #ifndef _IPT_POLICY_H
 #define _IPT_POLICY_H
 
+#include <linux/netfilter/xt_policy.h>
+
 #define IPT_POLICY_MAX_ELEM		XT_POLICY_MAX_ELEM
 
 /* ipt_policy_flags */
diff --git a/include/linux/netfilter_ipv6/ip6t_policy.h b/include/linux/netfilter_ipv6/ip6t_policy.h
index 6bab3163d2fb..b1c449d7ec89 100644
--- a/include/linux/netfilter_ipv6/ip6t_policy.h
+++ b/include/linux/netfilter_ipv6/ip6t_policy.h
@@ -1,6 +1,8 @@
 #ifndef _IP6T_POLICY_H
 #define _IP6T_POLICY_H
 
+#include <linux/netfilter/xt_policy.h>
+
 #define IP6T_POLICY_MAX_ELEM		XT_POLICY_MAX_ELEM
 
 /* ip6t_policy_flags */
diff --git a/include/linux/netlink.h b/include/linux/netlink.h
index 9ff1b54908f3..51b09a1f46c3 100644
--- a/include/linux/netlink.h
+++ b/include/linux/netlink.h
@@ -242,7 +242,8 @@ __nlmsg_put(struct sk_buff *skb, u32 pid, u32 seq, int type, int len, int flags)
 	nlh->nlmsg_flags = flags;
 	nlh->nlmsg_pid = pid;
 	nlh->nlmsg_seq = seq;
-	memset(NLMSG_DATA(nlh) + len, 0, NLMSG_ALIGN(size) - size);
+	if (!__builtin_constant_p(size) || NLMSG_ALIGN(size) - size != 0)
+		memset(NLMSG_DATA(nlh) + len, 0, NLMSG_ALIGN(size) - size);
 	return nlh;
 }
 
diff --git a/include/linux/netpoll.h b/include/linux/netpoll.h
index e3d79593fb3a..e38d3c9dccda 100644
--- a/include/linux/netpoll.h
+++ b/include/linux/netpoll.h
@@ -94,11 +94,6 @@ static inline void netpoll_poll_unlock(void *have)
 	rcu_read_unlock();
 }
 
-static inline void netpoll_netdev_init(struct net_device *dev)
-{
-	INIT_LIST_HEAD(&dev->napi_list);
-}
-
 #else
 static inline int netpoll_rx(struct sk_buff *skb)
 {
diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h
index 78a5922a2f11..db867b04ac3c 100644
--- a/include/linux/nfs_fs.h
+++ b/include/linux/nfs_fs.h
@@ -83,7 +83,7 @@ struct nfs_open_context {
 	struct rpc_cred *cred;
 	struct nfs4_state *state;
 	fl_owner_t lockowner;
-	int mode;
+	fmode_t mode;
 
 	unsigned long flags;
 #define NFS_CONTEXT_ERROR_WRITE		(0)
@@ -130,14 +130,17 @@ struct nfs_inode {
 	 *
 	 * We need to revalidate the cached attrs for this inode if
 	 *
-	 *	jiffies - read_cache_jiffies > attrtimeo
+	 *	jiffies - read_cache_jiffies >= attrtimeo
+	 *
+	 * Please note the comparison is greater than or equal
+	 * so that zero timeout values can be specified.
 	 */
 	unsigned long		read_cache_jiffies;
 	unsigned long		attrtimeo;
 	unsigned long		attrtimeo_timestamp;
 	__u64			change_attr;		/* v4 only */
 
-	unsigned long		last_updated;
+	unsigned long		attr_gencount;
 	/* "Generation counter" for the attribute cache. This is
 	 * bumped whenever we update the metadata on the
 	 * server.
@@ -180,7 +183,7 @@ struct nfs_inode {
         /* NFSv4 state */
 	struct list_head	open_states;
 	struct nfs_delegation	*delegation;
-	int			 delegation_state;
+	fmode_t			 delegation_state;
 	struct rw_semaphore	rwsem;
 #endif /* CONFIG_NFS_V4*/
 	struct inode		vfs_inode;
@@ -200,11 +203,10 @@ struct nfs_inode {
 /*
  * Bit offsets in flags field
  */
-#define NFS_INO_REVALIDATING	(0)		/* revalidating attrs */
-#define NFS_INO_ADVISE_RDPLUS	(1)		/* advise readdirplus */
-#define NFS_INO_STALE		(2)		/* possible stale inode */
-#define NFS_INO_ACL_LRU_SET	(3)		/* Inode is on the LRU list */
-#define NFS_INO_MOUNTPOINT	(4)		/* inode is remote mountpoint */
+#define NFS_INO_ADVISE_RDPLUS	(0)		/* advise readdirplus */
+#define NFS_INO_STALE		(1)		/* possible stale inode */
+#define NFS_INO_ACL_LRU_SET	(2)		/* Inode is on the LRU list */
+#define NFS_INO_MOUNTPOINT	(3)		/* inode is remote mountpoint */
 
 static inline struct nfs_inode *NFS_I(const struct inode *inode)
 {
@@ -343,17 +345,13 @@ extern int nfs_setattr(struct dentry *, struct iattr *);
 extern void nfs_setattr_update_inode(struct inode *inode, struct iattr *attr);
 extern struct nfs_open_context *get_nfs_open_context(struct nfs_open_context *ctx);
 extern void put_nfs_open_context(struct nfs_open_context *ctx);
-extern struct nfs_open_context *nfs_find_open_context(struct inode *inode, struct rpc_cred *cred, int mode);
+extern struct nfs_open_context *nfs_find_open_context(struct inode *inode, struct rpc_cred *cred, fmode_t mode);
 extern u64 nfs_compat_user_ino64(u64 fileid);
+extern void nfs_fattr_init(struct nfs_fattr *fattr);
 
 /* linux/net/ipv4/ipconfig.c: trims ip addr off front of name, too. */
 extern __be32 root_nfs_parse_addr(char *name); /*__init*/
-
-static inline void nfs_fattr_init(struct nfs_fattr *fattr)
-{
-	fattr->valid = 0;
-	fattr->time_start = jiffies;
-}
+extern unsigned long nfs_inc_attr_generation_counter(void);
 
 /*
  * linux/fs/nfs/file.c
@@ -372,8 +370,12 @@ static inline struct nfs_open_context *nfs_file_open_context(struct file *filp)
 
 static inline struct rpc_cred *nfs_file_cred(struct file *file)
 {
-	if (file != NULL)
-		return nfs_file_open_context(file)->cred;
+	if (file != NULL) {
+		struct nfs_open_context *ctx =
+			nfs_file_open_context(file);
+		if (ctx)
+			return ctx->cred;
+	}
 	return NULL;
 }
 
@@ -534,12 +536,6 @@ static inline void nfs3_forget_cached_acls(struct inode *inode)
 #endif /* CONFIG_NFS_V3_ACL */
 
 /*
- * linux/fs/mount_clnt.c
- */
-extern int  nfs_mount(struct sockaddr *, size_t, char *, char *,
-		      int, int, struct nfs_fh *);
-
-/*
  * inline functions
  */
 
diff --git a/include/linux/nfs_fs_sb.h b/include/linux/nfs_fs_sb.h
index c9beacd16c00..9bb81aec91cf 100644
--- a/include/linux/nfs_fs_sb.h
+++ b/include/linux/nfs_fs_sb.h
@@ -42,12 +42,6 @@ struct nfs_client {
 	struct rb_root		cl_openowner_id;
 	struct rb_root		cl_lockowner_id;
 
-	/*
-	 * The following rwsem ensures exclusive access to the server
-	 * while we recover the state following a lease expiration.
-	 */
-	struct rw_semaphore	cl_sem;
-
 	struct list_head	cl_delegations;
 	struct rb_root		cl_state_owners;
 	spinlock_t		cl_lock;
@@ -119,7 +113,6 @@ struct nfs_server {
 	void (*destroy)(struct nfs_server *);
 
 	atomic_t active; /* Keep trace of any activity to this server */
-	wait_queue_head_t active_wq;  /* Wait for any activity to stop  */
 
 	/* mountd-related mount options */
 	struct sockaddr_storage	mountd_address;
diff --git a/include/linux/nfs_mount.h b/include/linux/nfs_mount.h
index df7c6b7a7ebb..4499016e6d0d 100644
--- a/include/linux/nfs_mount.h
+++ b/include/linux/nfs_mount.h
@@ -45,7 +45,7 @@ struct nfs_mount_data {
 	char		context[NFS_MAX_CONTEXT_LEN + 1];	/* 6 */
 };
 
-/* bits in the flags field */
+/* bits in the flags field visible to user space */
 
 #define NFS_MOUNT_SOFT		0x0001	/* 1 */
 #define NFS_MOUNT_INTR		0x0002	/* 1 */ /* now unused, but ABI */
@@ -65,4 +65,9 @@ struct nfs_mount_data {
 #define NFS_MOUNT_UNSHARED	0x8000	/* 5 */
 #define NFS_MOUNT_FLAGMASK	0xFFFF
 
+/* The following are for internal use only */
+#define NFS_MOUNT_LOOKUP_CACHE_NONEG	0x10000
+#define NFS_MOUNT_LOOKUP_CACHE_NONE	0x20000
+#define NFS_MOUNT_NORESVPORT		0x40000
+
 #endif
diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h
index 8c77c11224d1..a550b528319f 100644
--- a/include/linux/nfs_xdr.h
+++ b/include/linux/nfs_xdr.h
@@ -36,6 +36,7 @@ struct nfs_fattr {
 	__u32			nlink;
 	__u32			uid;
 	__u32			gid;
+	dev_t			rdev;
 	__u64			size;
 	union {
 		struct {
@@ -46,7 +47,6 @@ struct nfs_fattr {
 			__u64	used;
 		} nfs3;
 	} du;
-	dev_t			rdev;
 	struct nfs_fsid		fsid;
 	__u64			fileid;
 	struct timespec		atime;
@@ -56,6 +56,7 @@ struct nfs_fattr {
 	__u64			change_attr;	/* NFSv4 change attribute */
 	__u64			pre_change_attr;/* pre-op NFSv4 change attribute */
 	unsigned long		time_start;
+	unsigned long		gencount;
 };
 
 #define NFS_ATTR_WCC		0x0001		/* pre-op WCC data    */
@@ -119,13 +120,14 @@ struct nfs_openargs {
 	const struct nfs_fh *	fh;
 	struct nfs_seqid *	seqid;
 	int			open_flags;
+	fmode_t			fmode;
 	__u64                   clientid;
 	__u64                   id;
 	union {
 		struct iattr *  attrs;    /* UNCHECKED, GUARDED */
 		nfs4_verifier   verifier; /* EXCLUSIVE */
 		nfs4_stateid	delegation;		/* CLAIM_DELEGATE_CUR */
-		int		delegation_type;	/* CLAIM_PREVIOUS */
+		fmode_t		delegation_type;	/* CLAIM_PREVIOUS */
 	} u;
 	const struct qstr *	name;
 	const struct nfs_server *server;	 /* Needed for ID mapping */
@@ -142,7 +144,7 @@ struct nfs_openres {
 	struct nfs_fattr *      dir_attr;
 	struct nfs_seqid *	seqid;
 	const struct nfs_server *server;
-	int			delegation_type;
+	fmode_t			delegation_type;
 	nfs4_stateid		delegation;
 	__u32			do_recall;
 	__u64			maxsize;
@@ -170,7 +172,7 @@ struct nfs_closeargs {
 	struct nfs_fh *         fh;
 	nfs4_stateid *		stateid;
 	struct nfs_seqid *	seqid;
-	int			open_flags;
+	fmode_t			fmode;
 	const u32 *		bitmask;
 };
 
@@ -672,16 +674,16 @@ struct nfs4_rename_res {
 	struct nfs_fattr *		new_fattr;
 };
 
-#define NFS4_SETCLIENTID_NAMELEN	(56)
+#define NFS4_SETCLIENTID_NAMELEN	(127)
 struct nfs4_setclientid {
 	const nfs4_verifier *		sc_verifier;
 	unsigned int			sc_name_len;
-	char				sc_name[NFS4_SETCLIENTID_NAMELEN];
+	char				sc_name[NFS4_SETCLIENTID_NAMELEN + 1];
 	u32				sc_prog;
 	unsigned int			sc_netid_len;
-	char				sc_netid[RPCBIND_MAXNETIDLEN];
+	char				sc_netid[RPCBIND_MAXNETIDLEN + 1];
 	unsigned int			sc_uaddr_len;
-	char				sc_uaddr[RPCBIND_MAXUADDRLEN];
+	char				sc_uaddr[RPCBIND_MAXUADDRLEN + 1];
 	u32				sc_cb_ident;
 };
 
diff --git a/include/linux/nfsd/state.h b/include/linux/nfsd/state.h
index d0fe2e378452..128298c0362d 100644
--- a/include/linux/nfsd/state.h
+++ b/include/linux/nfsd/state.h
@@ -124,6 +124,8 @@ struct nfs4_client {
 	nfs4_verifier		cl_verifier; 	/* generated by client */
 	time_t                  cl_time;        /* time of last lease renewal */
 	__be32			cl_addr; 	/* client ipaddress */
+	u32			cl_flavor;	/* setclientid pseudoflavor */
+	char			*cl_principal;	/* setclientid principal name */
 	struct svc_cred		cl_cred; 	/* setclientid principal */
 	clientid_t		cl_clientid;	/* generated by server */
 	nfs4_verifier		cl_confirm;	/* generated by server */
diff --git a/include/linux/nl80211.h b/include/linux/nl80211.h
index 9bad65400fba..e86ed59f9ad5 100644
--- a/include/linux/nl80211.h
+++ b/include/linux/nl80211.h
@@ -3,7 +3,26 @@
 /*
  * 802.11 netlink interface public header
  *
- * Copyright 2006, 2007 Johannes Berg <johannes@sipsolutions.net>
+ * Copyright 2006, 2007, 2008 Johannes Berg <johannes@sipsolutions.net>
+ * Copyright 2008 Michael Wu <flamingice@sourmilk.net>
+ * Copyright 2008 Luis Carlos Cobo <luisca@cozybit.com>
+ * Copyright 2008 Michael Buesch <mb@bu3sch.de>
+ * Copyright 2008 Luis R. Rodriguez <lrodriguez@atheros.com>
+ * Copyright 2008 Jouni Malinen <jouni.malinen@atheros.com>
+ * Copyright 2008 Colin McCabe <colin@cozybit.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
  */
 
 /**
@@ -25,8 +44,10 @@
  *
  * @NL80211_CMD_GET_WIPHY: request information about a wiphy or dump request
  *	to get a list of all present wiphys.
- * @NL80211_CMD_SET_WIPHY: set wiphy name, needs %NL80211_ATTR_WIPHY and
- *	%NL80211_ATTR_WIPHY_NAME.
+ * @NL80211_CMD_SET_WIPHY: set wiphy parameters, needs %NL80211_ATTR_WIPHY or
+ *	%NL80211_ATTR_IFINDEX; can be used to set %NL80211_ATTR_WIPHY_NAME,
+ *	%NL80211_ATTR_WIPHY_TXQ_PARAMS, %NL80211_ATTR_WIPHY_FREQ, and/or
+ *	%NL80211_ATTR_WIPHY_SEC_CHAN_OFFSET.
  * @NL80211_CMD_NEW_WIPHY: Newly created wiphy, response to get request
  *	or rename notification. Has attributes %NL80211_ATTR_WIPHY and
  *	%NL80211_ATTR_WIPHY_NAME.
@@ -106,6 +127,12 @@
  * 	to the the specified ISO/IEC 3166-1 alpha2 country code. The core will
  * 	store this as a valid request and then query userspace for it.
  *
+ * @NL80211_CMD_GET_MESH_PARAMS: Get mesh networking properties for the
+ *	interface identified by %NL80211_ATTR_IFINDEX
+ *
+ * @NL80211_CMD_SET_MESH_PARAMS: Set mesh networking properties for the
+ *      interface identified by %NL80211_ATTR_IFINDEX
+ *
  * @NL80211_CMD_MAX: highest used command number
  * @__NL80211_CMD_AFTER_LAST: internal use
  */
@@ -148,6 +175,9 @@ enum nl80211_commands {
 	NL80211_CMD_SET_REG,
 	NL80211_CMD_REQ_SET_REG,
 
+	NL80211_CMD_GET_MESH_PARAMS,
+	NL80211_CMD_SET_MESH_PARAMS,
+
 	/* add new commands above here */
 
 	/* used to define NL80211_CMD_MAX below */
@@ -169,6 +199,15 @@ enum nl80211_commands {
  * @NL80211_ATTR_WIPHY: index of wiphy to operate on, cf.
  *	/sys/class/ieee80211/<phyname>/index
  * @NL80211_ATTR_WIPHY_NAME: wiphy name (used for renaming)
+ * @NL80211_ATTR_WIPHY_TXQ_PARAMS: a nested array of TX queue parameters
+ * @NL80211_ATTR_WIPHY_FREQ: frequency of the selected channel in MHz
+ * @NL80211_ATTR_WIPHY_CHANNEL_TYPE: included with NL80211_ATTR_WIPHY_FREQ
+ *	if HT20 or HT40 are allowed (i.e., 802.11n disabled if not included):
+ *	NL80211_CHAN_NO_HT = HT not allowed (i.e., same as not including
+ *		this attribute)
+ *	NL80211_CHAN_HT20 = HT20 only
+ *	NL80211_CHAN_HT40MINUS = secondary channel is below the primary channel
+ *	NL80211_CHAN_HT40PLUS = secondary channel is above the primary channel
  *
  * @NL80211_ATTR_IFINDEX: network interface index of the device to operate on
  * @NL80211_ATTR_IFNAME: network interface name
@@ -234,6 +273,9 @@ enum nl80211_commands {
  *	(u8, 0 or 1)
  * @NL80211_ATTR_BSS_SHORT_SLOT_TIME: whether short slot time enabled
  *	(u8, 0 or 1)
+ * @NL80211_ATTR_BSS_BASIC_RATES: basic rates, array of basic
+ *	rates in format defined by IEEE 802.11 7.3.2.2 but without the length
+ *	restriction (at most %NL80211_MAX_SUPP_RATES).
  *
  * @NL80211_ATTR_HT_CAPABILITY: HT Capability information element (from
  *	association request when used with NL80211_CMD_NEW_STATION)
@@ -296,6 +338,14 @@ enum nl80211_attrs {
 	NL80211_ATTR_REG_ALPHA2,
 	NL80211_ATTR_REG_RULES,
 
+	NL80211_ATTR_MESH_PARAMS,
+
+	NL80211_ATTR_BSS_BASIC_RATES,
+
+	NL80211_ATTR_WIPHY_TXQ_PARAMS,
+	NL80211_ATTR_WIPHY_FREQ,
+	NL80211_ATTR_WIPHY_CHANNEL_TYPE,
+
 	/* add attributes here, update the policy in nl80211.c */
 
 	__NL80211_ATTR_AFTER_LAST,
@@ -307,6 +357,10 @@ enum nl80211_attrs {
  * here
  */
 #define NL80211_ATTR_HT_CAPABILITY NL80211_ATTR_HT_CAPABILITY
+#define NL80211_ATTR_BSS_BASIC_RATES NL80211_ATTR_BSS_BASIC_RATES
+#define NL80211_ATTR_WIPHY_TXQ_PARAMS NL80211_ATTR_WIPHY_TXQ_PARAMS
+#define NL80211_ATTR_WIPHY_FREQ NL80211_ATTR_WIPHY_FREQ
+#define NL80211_ATTR_WIPHY_SEC_CHAN_OFFSET NL80211_ATTR_WIPHY_SEC_CHAN_OFFSET
 
 #define NL80211_MAX_SUPP_RATES			32
 #define NL80211_MAX_SUPP_REG_RULES		32
@@ -371,6 +425,32 @@ enum nl80211_sta_flags {
 };
 
 /**
+ * enum nl80211_rate_info - bitrate information
+ *
+ * These attribute types are used with %NL80211_STA_INFO_TXRATE
+ * when getting information about the bitrate of a station.
+ *
+ * @__NL80211_RATE_INFO_INVALID: attribute number 0 is reserved
+ * @NL80211_RATE_INFO_BITRATE: total bitrate (u16, 100kbit/s)
+ * @NL80211_RATE_INFO_MCS: mcs index for 802.11n (u8)
+ * @NL80211_RATE_INFO_40_MHZ_WIDTH: 40 Mhz dualchannel bitrate
+ * @NL80211_RATE_INFO_SHORT_GI: 400ns guard interval
+ * @NL80211_RATE_INFO_MAX: highest rate_info number currently defined
+ * @__NL80211_RATE_INFO_AFTER_LAST: internal use
+ */
+enum nl80211_rate_info {
+	__NL80211_RATE_INFO_INVALID,
+	NL80211_RATE_INFO_BITRATE,
+	NL80211_RATE_INFO_MCS,
+	NL80211_RATE_INFO_40_MHZ_WIDTH,
+	NL80211_RATE_INFO_SHORT_GI,
+
+	/* keep last */
+	__NL80211_RATE_INFO_AFTER_LAST,
+	NL80211_RATE_INFO_MAX = __NL80211_RATE_INFO_AFTER_LAST - 1
+};
+
+/**
  * enum nl80211_sta_info - station information
  *
  * These attribute types are used with %NL80211_ATTR_STA_INFO
@@ -382,6 +462,9 @@ enum nl80211_sta_flags {
  * @NL80211_STA_INFO_TX_BYTES: total transmitted bytes (u32, to this station)
  * @__NL80211_STA_INFO_AFTER_LAST: internal
  * @NL80211_STA_INFO_MAX: highest possible station info attribute
+ * @NL80211_STA_INFO_SIGNAL: signal strength of last received PPDU (u8, dBm)
+ * @NL80211_STA_INFO_TX_BITRATE: current unicast tx rate, nested attribute
+ * 	containing info as possible, see &enum nl80211_sta_info_txrate.
  */
 enum nl80211_sta_info {
 	__NL80211_STA_INFO_INVALID,
@@ -391,6 +474,8 @@ enum nl80211_sta_info {
 	NL80211_STA_INFO_LLID,
 	NL80211_STA_INFO_PLID,
 	NL80211_STA_INFO_PLINK_STATE,
+	NL80211_STA_INFO_SIGNAL,
+	NL80211_STA_INFO_TX_BITRATE,
 
 	/* keep last */
 	__NL80211_STA_INFO_AFTER_LAST,
@@ -452,17 +537,29 @@ enum nl80211_mpath_info {
  *	an array of nested frequency attributes
  * @NL80211_BAND_ATTR_RATES: supported bitrates in this band,
  *	an array of nested bitrate attributes
+ * @NL80211_BAND_ATTR_HT_MCS_SET: 16-byte attribute containing the MCS set as
+ *	defined in 802.11n
+ * @NL80211_BAND_ATTR_HT_CAPA: HT capabilities, as in the HT information IE
+ * @NL80211_BAND_ATTR_HT_AMPDU_FACTOR: A-MPDU factor, as in 11n
+ * @NL80211_BAND_ATTR_HT_AMPDU_DENSITY: A-MPDU density, as in 11n
  */
 enum nl80211_band_attr {
 	__NL80211_BAND_ATTR_INVALID,
 	NL80211_BAND_ATTR_FREQS,
 	NL80211_BAND_ATTR_RATES,
 
+	NL80211_BAND_ATTR_HT_MCS_SET,
+	NL80211_BAND_ATTR_HT_CAPA,
+	NL80211_BAND_ATTR_HT_AMPDU_FACTOR,
+	NL80211_BAND_ATTR_HT_AMPDU_DENSITY,
+
 	/* keep last */
 	__NL80211_BAND_ATTR_AFTER_LAST,
 	NL80211_BAND_ATTR_MAX = __NL80211_BAND_ATTR_AFTER_LAST - 1
 };
 
+#define NL80211_BAND_ATTR_HT_CAPA NL80211_BAND_ATTR_HT_CAPA
+
 /**
  * enum nl80211_frequency_attr - frequency attributes
  * @NL80211_FREQUENCY_ATTR_FREQ: Frequency in MHz
@@ -474,6 +571,8 @@ enum nl80211_band_attr {
  *	on this channel in current regulatory domain.
  * @NL80211_FREQUENCY_ATTR_RADAR: Radar detection is mandatory
  *	on this channel in current regulatory domain.
+ * @NL80211_FREQUENCY_ATTR_MAX_TX_POWER: Maximum transmission power in mBm
+ *	(100 * dBm).
  */
 enum nl80211_frequency_attr {
 	__NL80211_FREQUENCY_ATTR_INVALID,
@@ -482,12 +581,15 @@ enum nl80211_frequency_attr {
 	NL80211_FREQUENCY_ATTR_PASSIVE_SCAN,
 	NL80211_FREQUENCY_ATTR_NO_IBSS,
 	NL80211_FREQUENCY_ATTR_RADAR,
+	NL80211_FREQUENCY_ATTR_MAX_TX_POWER,
 
 	/* keep last */
 	__NL80211_FREQUENCY_ATTR_AFTER_LAST,
 	NL80211_FREQUENCY_ATTR_MAX = __NL80211_FREQUENCY_ATTR_AFTER_LAST - 1
 };
 
+#define NL80211_FREQUENCY_ATTR_MAX_TX_POWER NL80211_FREQUENCY_ATTR_MAX_TX_POWER
+
 /**
  * enum nl80211_bitrate_attr - bitrate attributes
  * @NL80211_BITRATE_ATTR_RATE: Bitrate in units of 100 kbps
@@ -594,4 +696,119 @@ enum nl80211_mntr_flags {
 	NL80211_MNTR_FLAG_MAX = __NL80211_MNTR_FLAG_AFTER_LAST - 1
 };
 
+/**
+ * enum nl80211_meshconf_params - mesh configuration parameters
+ *
+ * Mesh configuration parameters
+ *
+ * @__NL80211_MESHCONF_INVALID: internal use
+ *
+ * @NL80211_MESHCONF_RETRY_TIMEOUT: specifies the initial retry timeout in
+ * millisecond units, used by the Peer Link Open message
+ *
+ * @NL80211_MESHCONF_CONFIRM_TIMEOUT: specifies the inital confirm timeout, in
+ * millisecond units, used by the peer link management to close a peer link
+ *
+ * @NL80211_MESHCONF_HOLDING_TIMEOUT: specifies the holding timeout, in
+ * millisecond units
+ *
+ * @NL80211_MESHCONF_MAX_PEER_LINKS: maximum number of peer links allowed
+ * on this mesh interface
+ *
+ * @NL80211_MESHCONF_MAX_RETRIES: specifies the maximum number of peer link
+ * open retries that can be sent to establish a new peer link instance in a
+ * mesh
+ *
+ * @NL80211_MESHCONF_TTL: specifies the value of TTL field set at a source mesh
+ * point.
+ *
+ * @NL80211_MESHCONF_AUTO_OPEN_PLINKS: whether we should automatically
+ * open peer links when we detect compatible mesh peers.
+ *
+ * @NL80211_MESHCONF_HWMP_MAX_PREQ_RETRIES: the number of action frames
+ * containing a PREQ that an MP can send to a particular destination (path
+ * target)
+ *
+ * @NL80211_MESHCONF_PATH_REFRESH_TIME: how frequently to refresh mesh paths
+ * (in milliseconds)
+ *
+ * @NL80211_MESHCONF_MIN_DISCOVERY_TIMEOUT: minimum length of time to wait
+ * until giving up on a path discovery (in milliseconds)
+ *
+ * @NL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT: The time (in TUs) for which mesh
+ * points receiving a PREQ shall consider the forwarding information from the
+ * root to be valid. (TU = time unit)
+ *
+ * @NL80211_MESHCONF_HWMP_PREQ_MIN_INTERVAL: The minimum interval of time (in
+ * TUs) during which an MP can send only one action frame containing a PREQ
+ * reference element
+ *
+ * @NL80211_MESHCONF_HWMP_NET_DIAM_TRVS_TIME: The interval of time (in TUs)
+ * that it takes for an HWMP information element to propagate across the mesh
+ *
+ * @NL80211_MESHCONF_ATTR_MAX: highest possible mesh configuration attribute
+ *
+ * @__NL80211_MESHCONF_ATTR_AFTER_LAST: internal use
+ */
+enum nl80211_meshconf_params {
+	__NL80211_MESHCONF_INVALID,
+	NL80211_MESHCONF_RETRY_TIMEOUT,
+	NL80211_MESHCONF_CONFIRM_TIMEOUT,
+	NL80211_MESHCONF_HOLDING_TIMEOUT,
+	NL80211_MESHCONF_MAX_PEER_LINKS,
+	NL80211_MESHCONF_MAX_RETRIES,
+	NL80211_MESHCONF_TTL,
+	NL80211_MESHCONF_AUTO_OPEN_PLINKS,
+	NL80211_MESHCONF_HWMP_MAX_PREQ_RETRIES,
+	NL80211_MESHCONF_PATH_REFRESH_TIME,
+	NL80211_MESHCONF_MIN_DISCOVERY_TIMEOUT,
+	NL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT,
+	NL80211_MESHCONF_HWMP_PREQ_MIN_INTERVAL,
+	NL80211_MESHCONF_HWMP_NET_DIAM_TRVS_TIME,
+
+	/* keep last */
+	__NL80211_MESHCONF_ATTR_AFTER_LAST,
+	NL80211_MESHCONF_ATTR_MAX = __NL80211_MESHCONF_ATTR_AFTER_LAST - 1
+};
+
+/**
+ * enum nl80211_txq_attr - TX queue parameter attributes
+ * @__NL80211_TXQ_ATTR_INVALID: Attribute number 0 is reserved
+ * @NL80211_TXQ_ATTR_QUEUE: TX queue identifier (NL80211_TXQ_Q_*)
+ * @NL80211_TXQ_ATTR_TXOP: Maximum burst time in units of 32 usecs, 0 meaning
+ *	disabled
+ * @NL80211_TXQ_ATTR_CWMIN: Minimum contention window [a value of the form
+ *	2^n-1 in the range 1..32767]
+ * @NL80211_TXQ_ATTR_CWMAX: Maximum contention window [a value of the form
+ *	2^n-1 in the range 1..32767]
+ * @NL80211_TXQ_ATTR_AIFS: Arbitration interframe space [0..255]
+ * @__NL80211_TXQ_ATTR_AFTER_LAST: Internal
+ * @NL80211_TXQ_ATTR_MAX: Maximum TXQ attribute number
+ */
+enum nl80211_txq_attr {
+	__NL80211_TXQ_ATTR_INVALID,
+	NL80211_TXQ_ATTR_QUEUE,
+	NL80211_TXQ_ATTR_TXOP,
+	NL80211_TXQ_ATTR_CWMIN,
+	NL80211_TXQ_ATTR_CWMAX,
+	NL80211_TXQ_ATTR_AIFS,
+
+	/* keep last */
+	__NL80211_TXQ_ATTR_AFTER_LAST,
+	NL80211_TXQ_ATTR_MAX = __NL80211_TXQ_ATTR_AFTER_LAST - 1
+};
+
+enum nl80211_txq_q {
+	NL80211_TXQ_Q_VO,
+	NL80211_TXQ_Q_VI,
+	NL80211_TXQ_Q_BE,
+	NL80211_TXQ_Q_BK
+};
+
+enum nl80211_channel_type {
+	NL80211_CHAN_NO_HT,
+	NL80211_CHAN_HT20,
+	NL80211_CHAN_HT40MINUS,
+	NL80211_CHAN_HT40PLUS
+};
 #endif /* __LINUX_NL80211_H */
diff --git a/include/linux/nsproxy.h b/include/linux/nsproxy.h
index c8a768e59640..afad7dec1b36 100644
--- a/include/linux/nsproxy.h
+++ b/include/linux/nsproxy.h
@@ -27,7 +27,6 @@ struct nsproxy {
 	struct ipc_namespace *ipc_ns;
 	struct mnt_namespace *mnt_ns;
 	struct pid_namespace *pid_ns;
-	struct user_namespace *user_ns;
 	struct net 	     *net_ns;
 };
 extern struct nsproxy init_nsproxy;
diff --git a/include/linux/of.h b/include/linux/of.h
index 79886ade070f..6a7efa242f5e 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -57,6 +57,12 @@ extern struct device_node *of_get_next_child(const struct device_node *node,
 	for (child = of_get_next_child(parent, NULL); child != NULL; \
 	     child = of_get_next_child(parent, child))
 
+extern struct device_node *of_find_node_with_property(
+	struct device_node *from, const char *prop_name);
+#define for_each_node_with_property(dn, prop_name) \
+	for (dn = of_find_node_with_property(NULL, prop_name); dn; \
+	     dn = of_find_node_with_property(dn, prop_name))
+
 extern struct property *of_find_property(const struct device_node *np,
 					 const char *name,
 					 int *lenp);
@@ -71,5 +77,8 @@ extern int of_n_size_cells(struct device_node *np);
 extern const struct of_device_id *of_match_node(
 	const struct of_device_id *matches, const struct device_node *node);
 extern int of_modalias_node(struct device_node *node, char *modalias, int len);
+extern int of_parse_phandles_with_args(struct device_node *np,
+	const char *list_name, const char *cells_name, int index,
+	struct device_node **out_node, const void **out_args);
 
 #endif /* _LINUX_OF_H */
diff --git a/include/linux/of_gpio.h b/include/linux/of_gpio.h
index 67db101d0eb8..fc2472c3c254 100644
--- a/include/linux/of_gpio.h
+++ b/include/linux/of_gpio.h
@@ -14,9 +14,22 @@
 #ifndef __LINUX_OF_GPIO_H
 #define __LINUX_OF_GPIO_H
 
+#include <linux/compiler.h>
+#include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/gpio.h>
 
+struct device_node;
+
+/*
+ * This is Linux-specific flags. By default controllers' and Linux' mapping
+ * match, but GPIO controllers are free to translate their own flags to
+ * Linux-specific in their .xlate callback. Though, 1:1 mapping is recommended.
+ */
+enum of_gpio_flags {
+	OF_GPIO_ACTIVE_LOW = 0x1,
+};
+
 #ifdef CONFIG_OF_GPIO
 
 /*
@@ -26,7 +39,7 @@ struct of_gpio_chip {
 	struct gpio_chip gc;
 	int gpio_cells;
 	int (*xlate)(struct of_gpio_chip *of_gc, struct device_node *np,
-		     const void *gpio_spec);
+		     const void *gpio_spec, enum of_gpio_flags *flags);
 };
 
 static inline struct of_gpio_chip *to_of_gpio_chip(struct gpio_chip *gc)
@@ -50,20 +63,43 @@ static inline struct of_mm_gpio_chip *to_of_mm_gpio_chip(struct gpio_chip *gc)
 	return container_of(of_gc, struct of_mm_gpio_chip, of_gc);
 }
 
-extern int of_get_gpio(struct device_node *np, int index);
+extern int of_get_gpio_flags(struct device_node *np, int index,
+			     enum of_gpio_flags *flags);
+extern unsigned int of_gpio_count(struct device_node *np);
+
 extern int of_mm_gpiochip_add(struct device_node *np,
 			      struct of_mm_gpio_chip *mm_gc);
 extern int of_gpio_simple_xlate(struct of_gpio_chip *of_gc,
 				struct device_node *np,
-				const void *gpio_spec);
+				const void *gpio_spec,
+				enum of_gpio_flags *flags);
 #else
 
 /* Drivers may not strictly depend on the GPIO support, so let them link. */
-static inline int of_get_gpio(struct device_node *np, int index)
+static inline int of_get_gpio_flags(struct device_node *np, int index,
+				    enum of_gpio_flags *flags)
 {
 	return -ENOSYS;
 }
 
+static inline unsigned int of_gpio_count(struct device_node *np)
+{
+	return 0;
+}
+
 #endif /* CONFIG_OF_GPIO */
 
+/**
+ * of_get_gpio - Get a GPIO number to use with GPIO API
+ * @np:		device node to get GPIO from
+ * @index:	index of the GPIO
+ *
+ * Returns GPIO number to use with Linux generic GPIO API, or one of the errno
+ * value on the error condition.
+ */
+static inline int of_get_gpio(struct device_node *np, int index)
+{
+	return of_get_gpio_flags(np, index, NULL);
+}
+
 #endif /* __LINUX_OF_GPIO_H */
diff --git a/include/linux/of_platform.h b/include/linux/of_platform.h
index a8efcfeea732..3d327b67d7e2 100644
--- a/include/linux/of_platform.h
+++ b/include/linux/of_platform.h
@@ -26,8 +26,7 @@ extern struct bus_type of_platform_bus_type;
 
 /*
  * An of_platform_driver driver is attached to a basic of_device on
- * the "platform bus" (of_platform_bus_type) (or ISA, EBUS and SBUS
- * busses on sparc).
+ * the "platform bus" (of_platform_bus_type).
  */
 struct of_platform_driver
 {
diff --git a/include/linux/oprofile.h b/include/linux/oprofile.h
index bcb8f725427c..1ce9fe572e51 100644
--- a/include/linux/oprofile.h
+++ b/include/linux/oprofile.h
@@ -86,15 +86,7 @@ int oprofile_arch_init(struct oprofile_operations * ops);
 void oprofile_arch_exit(void);
 
 /**
- * Add data to the event buffer.
- * The data passed is free-form, but typically consists of
- * file offsets, dcookies, context information, and ESCAPE codes.
- */
-void add_event_entry(unsigned long data);
-
-/**
- * Add a sample. This may be called from any context. Pass
- * smp_processor_id() as cpu.
+ * Add a sample. This may be called from any context.
  */
 void oprofile_add_sample(struct pt_regs * const regs, unsigned long event);
 
@@ -162,5 +154,14 @@ int oprofilefs_ulong_from_user(unsigned long * val, char const __user * buf, siz
 
 /** lock for read/write safety */
 extern spinlock_t oprofilefs_lock;
+
+/**
+ * Add the contents of a circular buffer to the event buffer.
+ */
+void oprofile_put_buff(unsigned long *buf, unsigned int start,
+			unsigned int stop, unsigned int max);
+
+unsigned long oprofile_get_cpu_buffer_size(void);
+void oprofile_cpu_buffer_inc_smpl_lost(void);
  
 #endif /* OPROFILE_H */
diff --git a/include/linux/page-flags.h b/include/linux/page-flags.h
index c74d3e875314..b12f93a3c345 100644
--- a/include/linux/page-flags.h
+++ b/include/linux/page-flags.h
@@ -93,6 +93,11 @@ enum pageflags {
 	PG_mappedtodisk,	/* Has blocks allocated on-disk */
 	PG_reclaim,		/* To be reclaimed asap */
 	PG_buddy,		/* Page is free, on buddy lists */
+	PG_swapbacked,		/* Page is backed by RAM/swap */
+#ifdef CONFIG_UNEVICTABLE_LRU
+	PG_unevictable,		/* Page is "unevictable"  */
+	PG_mlocked,		/* Page is vma mlocked */
+#endif
 #ifdef CONFIG_IA64_UNCACHED_ALLOCATOR
 	PG_uncached,		/* Page has been mapped as uncached */
 #endif
@@ -161,6 +166,18 @@ static inline int Page##uname(struct page *page) 			\
 #define TESTSCFLAG(uname, lname)					\
 	TESTSETFLAG(uname, lname) TESTCLEARFLAG(uname, lname)
 
+#define SETPAGEFLAG_NOOP(uname)						\
+static inline void SetPage##uname(struct page *page) {  }
+
+#define CLEARPAGEFLAG_NOOP(uname)					\
+static inline void ClearPage##uname(struct page *page) {  }
+
+#define __CLEARPAGEFLAG_NOOP(uname)					\
+static inline void __ClearPage##uname(struct page *page) {  }
+
+#define TESTCLEARFLAG_FALSE(uname)					\
+static inline int TestClearPage##uname(struct page *page) { return 0; }
+
 struct page;	/* forward declaration */
 
 TESTPAGEFLAG(Locked, locked)
@@ -169,6 +186,7 @@ PAGEFLAG(Referenced, referenced) TESTCLEARFLAG(Referenced, referenced)
 PAGEFLAG(Dirty, dirty) TESTSCFLAG(Dirty, dirty) __CLEARPAGEFLAG(Dirty, dirty)
 PAGEFLAG(LRU, lru) __CLEARPAGEFLAG(LRU, lru)
 PAGEFLAG(Active, active) __CLEARPAGEFLAG(Active, active)
+	TESTCLEARFLAG(Active, active)
 __PAGEFLAG(Slab, slab)
 PAGEFLAG(Checked, checked)		/* Used by some filesystems */
 PAGEFLAG(Pinned, pinned) TESTSCFLAG(Pinned, pinned)	/* Xen */
@@ -176,6 +194,7 @@ PAGEFLAG(SavePinned, savepinned);			/* Xen */
 PAGEFLAG(Reserved, reserved) __CLEARPAGEFLAG(Reserved, reserved)
 PAGEFLAG(Private, private) __CLEARPAGEFLAG(Private, private)
 	__SETPAGEFLAG(Private, private)
+PAGEFLAG(SwapBacked, swapbacked) __CLEARPAGEFLAG(SwapBacked, swapbacked)
 
 __PAGEFLAG(SlobPage, slob_page)
 __PAGEFLAG(SlobFree, slob_free)
@@ -211,6 +230,25 @@ PAGEFLAG(SwapCache, swapcache)
 PAGEFLAG_FALSE(SwapCache)
 #endif
 
+#ifdef CONFIG_UNEVICTABLE_LRU
+PAGEFLAG(Unevictable, unevictable) __CLEARPAGEFLAG(Unevictable, unevictable)
+	TESTCLEARFLAG(Unevictable, unevictable)
+
+#define MLOCK_PAGES 1
+PAGEFLAG(Mlocked, mlocked) __CLEARPAGEFLAG(Mlocked, mlocked)
+	TESTSCFLAG(Mlocked, mlocked)
+
+#else
+
+#define MLOCK_PAGES 0
+PAGEFLAG_FALSE(Mlocked)
+	SETPAGEFLAG_NOOP(Mlocked) TESTCLEARFLAG_FALSE(Mlocked)
+
+PAGEFLAG_FALSE(Unevictable) TESTCLEARFLAG_FALSE(Unevictable)
+	SETPAGEFLAG_NOOP(Unevictable) CLEARPAGEFLAG_NOOP(Unevictable)
+	__CLEARPAGEFLAG_NOOP(Unevictable)
+#endif
+
 #ifdef CONFIG_IA64_UNCACHED_ALLOCATOR
 PAGEFLAG(Uncached, uncached)
 #else
@@ -326,15 +364,25 @@ static inline void __ClearPageTail(struct page *page)
 
 #endif /* !PAGEFLAGS_EXTENDED */
 
+#ifdef CONFIG_UNEVICTABLE_LRU
+#define __PG_UNEVICTABLE	(1 << PG_unevictable)
+#define __PG_MLOCKED		(1 << PG_mlocked)
+#else
+#define __PG_UNEVICTABLE	0
+#define __PG_MLOCKED		0
+#endif
+
 #define PAGE_FLAGS	(1 << PG_lru   | 1 << PG_private   | 1 << PG_locked | \
 			 1 << PG_buddy | 1 << PG_writeback | \
-			 1 << PG_slab  | 1 << PG_swapcache | 1 << PG_active)
+			 1 << PG_slab  | 1 << PG_swapcache | 1 << PG_active | \
+			 __PG_UNEVICTABLE | __PG_MLOCKED)
 
 /*
  * Flags checked in bad_page().  Pages on the free list should not have
  * these flags set.  It they are, there is a problem.
  */
-#define PAGE_FLAGS_CLEAR_WHEN_BAD (PAGE_FLAGS | 1 << PG_reclaim | 1 << PG_dirty)
+#define PAGE_FLAGS_CLEAR_WHEN_BAD (PAGE_FLAGS | \
+		1 << PG_reclaim | 1 << PG_dirty | 1 << PG_swapbacked)
 
 /*
  * Flags checked when a page is freed.  Pages being freed should not have
@@ -347,7 +395,8 @@ static inline void __ClearPageTail(struct page *page)
  * Pages being prepped should not have these flags set.  It they are, there
  * is a problem.
  */
-#define PAGE_FLAGS_CHECK_AT_PREP (PAGE_FLAGS | 1 << PG_reserved | 1 << PG_dirty)
+#define PAGE_FLAGS_CHECK_AT_PREP (PAGE_FLAGS | \
+		1 << PG_reserved | 1 << PG_dirty | 1 << PG_swapbacked)
 
 #endif /* !__GENERATING_BOUNDS_H */
 #endif	/* PAGE_FLAGS_H */
diff --git a/include/linux/page_cgroup.h b/include/linux/page_cgroup.h
new file mode 100644
index 000000000000..1e6d34bfa094
--- /dev/null
+++ b/include/linux/page_cgroup.h
@@ -0,0 +1,108 @@
+#ifndef __LINUX_PAGE_CGROUP_H
+#define __LINUX_PAGE_CGROUP_H
+
+#ifdef CONFIG_CGROUP_MEM_RES_CTLR
+#include <linux/bit_spinlock.h>
+/*
+ * Page Cgroup can be considered as an extended mem_map.
+ * A page_cgroup page is associated with every page descriptor. The
+ * page_cgroup helps us identify information about the cgroup
+ * All page cgroups are allocated at boot or memory hotplug event,
+ * then the page cgroup for pfn always exists.
+ */
+struct page_cgroup {
+	unsigned long flags;
+	struct mem_cgroup *mem_cgroup;
+	struct page *page;
+	struct list_head lru;		/* per cgroup LRU list */
+};
+
+void __meminit pgdat_page_cgroup_init(struct pglist_data *pgdat);
+void __init page_cgroup_init(void);
+struct page_cgroup *lookup_page_cgroup(struct page *page);
+
+enum {
+	/* flags for mem_cgroup */
+	PCG_LOCK,  /* page cgroup is locked */
+	PCG_CACHE, /* charged as cache */
+	PCG_USED, /* this object is in use. */
+	/* flags for LRU placement */
+	PCG_ACTIVE, /* page is active in this cgroup */
+	PCG_FILE, /* page is file system backed */
+	PCG_UNEVICTABLE, /* page is unevictableable */
+};
+
+#define TESTPCGFLAG(uname, lname)			\
+static inline int PageCgroup##uname(struct page_cgroup *pc)	\
+	{ return test_bit(PCG_##lname, &pc->flags); }
+
+#define SETPCGFLAG(uname, lname)			\
+static inline void SetPageCgroup##uname(struct page_cgroup *pc)\
+	{ set_bit(PCG_##lname, &pc->flags);  }
+
+#define CLEARPCGFLAG(uname, lname)			\
+static inline void ClearPageCgroup##uname(struct page_cgroup *pc)	\
+	{ clear_bit(PCG_##lname, &pc->flags);  }
+
+/* Cache flag is set only once (at allocation) */
+TESTPCGFLAG(Cache, CACHE)
+
+TESTPCGFLAG(Used, USED)
+CLEARPCGFLAG(Used, USED)
+
+/* LRU management flags (from global-lru definition) */
+TESTPCGFLAG(File, FILE)
+SETPCGFLAG(File, FILE)
+CLEARPCGFLAG(File, FILE)
+
+TESTPCGFLAG(Active, ACTIVE)
+SETPCGFLAG(Active, ACTIVE)
+CLEARPCGFLAG(Active, ACTIVE)
+
+TESTPCGFLAG(Unevictable, UNEVICTABLE)
+SETPCGFLAG(Unevictable, UNEVICTABLE)
+CLEARPCGFLAG(Unevictable, UNEVICTABLE)
+
+static inline int page_cgroup_nid(struct page_cgroup *pc)
+{
+	return page_to_nid(pc->page);
+}
+
+static inline enum zone_type page_cgroup_zid(struct page_cgroup *pc)
+{
+	return page_zonenum(pc->page);
+}
+
+static inline void lock_page_cgroup(struct page_cgroup *pc)
+{
+	bit_spin_lock(PCG_LOCK, &pc->flags);
+}
+
+static inline int trylock_page_cgroup(struct page_cgroup *pc)
+{
+	return bit_spin_trylock(PCG_LOCK, &pc->flags);
+}
+
+static inline void unlock_page_cgroup(struct page_cgroup *pc)
+{
+	bit_spin_unlock(PCG_LOCK, &pc->flags);
+}
+
+#else /* CONFIG_CGROUP_MEM_RES_CTLR */
+struct page_cgroup;
+
+static inline void __meminit pgdat_page_cgroup_init(struct pglist_data *pgdat)
+{
+}
+
+static inline struct page_cgroup *lookup_page_cgroup(struct page *page)
+{
+	return NULL;
+}
+
+static inline void page_cgroup_init(void)
+{
+}
+
+#endif
+#endif
diff --git a/include/linux/pagemap.h b/include/linux/pagemap.h
index 5da31c12101c..709742be02f0 100644
--- a/include/linux/pagemap.h
+++ b/include/linux/pagemap.h
@@ -32,6 +32,34 @@ static inline void mapping_set_error(struct address_space *mapping, int error)
 	}
 }
 
+#ifdef CONFIG_UNEVICTABLE_LRU
+#define AS_UNEVICTABLE	(__GFP_BITS_SHIFT + 2)	/* e.g., ramdisk, SHM_LOCK */
+
+static inline void mapping_set_unevictable(struct address_space *mapping)
+{
+	set_bit(AS_UNEVICTABLE, &mapping->flags);
+}
+
+static inline void mapping_clear_unevictable(struct address_space *mapping)
+{
+	clear_bit(AS_UNEVICTABLE, &mapping->flags);
+}
+
+static inline int mapping_unevictable(struct address_space *mapping)
+{
+	if (likely(mapping))
+		return test_bit(AS_UNEVICTABLE, &mapping->flags);
+	return !!mapping;
+}
+#else
+static inline void mapping_set_unevictable(struct address_space *mapping) { }
+static inline void mapping_clear_unevictable(struct address_space *mapping) { }
+static inline int mapping_unevictable(struct address_space *mapping)
+{
+	return 0;
+}
+#endif
+
 static inline gfp_t mapping_gfp_mask(struct address_space * mapping)
 {
 	return (__force gfp_t)mapping->flags & __GFP_BITS_MASK;
@@ -271,19 +299,19 @@ extern int __lock_page_killable(struct page *page);
 extern void __lock_page_nosync(struct page *page);
 extern void unlock_page(struct page *page);
 
-static inline void set_page_locked(struct page *page)
+static inline void __set_page_locked(struct page *page)
 {
-	set_bit(PG_locked, &page->flags);
+	__set_bit(PG_locked, &page->flags);
 }
 
-static inline void clear_page_locked(struct page *page)
+static inline void __clear_page_locked(struct page *page)
 {
-	clear_bit(PG_locked, &page->flags);
+	__clear_bit(PG_locked, &page->flags);
 }
 
 static inline int trylock_page(struct page *page)
 {
-	return !test_and_set_bit(PG_locked, &page->flags);
+	return (likely(!test_and_set_bit_lock(PG_locked, &page->flags)));
 }
 
 /*
@@ -410,17 +438,17 @@ extern void __remove_from_page_cache(struct page *page);
 
 /*
  * Like add_to_page_cache_locked, but used to add newly allocated pages:
- * the page is new, so we can just run set_page_locked() against it.
+ * the page is new, so we can just run __set_page_locked() against it.
  */
 static inline int add_to_page_cache(struct page *page,
 		struct address_space *mapping, pgoff_t offset, gfp_t gfp_mask)
 {
 	int error;
 
-	set_page_locked(page);
+	__set_page_locked(page);
 	error = add_to_page_cache_locked(page, mapping, offset, gfp_mask);
 	if (unlikely(error))
-		clear_page_locked(page);
+		__clear_page_locked(page);
 	return error;
 }
 
diff --git a/include/linux/pagevec.h b/include/linux/pagevec.h
index 8eb7fa76c1d0..e90a2cb02915 100644
--- a/include/linux/pagevec.h
+++ b/include/linux/pagevec.h
@@ -23,9 +23,9 @@ struct pagevec {
 void __pagevec_release(struct pagevec *pvec);
 void __pagevec_release_nonlru(struct pagevec *pvec);
 void __pagevec_free(struct pagevec *pvec);
-void __pagevec_lru_add(struct pagevec *pvec);
-void __pagevec_lru_add_active(struct pagevec *pvec);
+void ____pagevec_lru_add(struct pagevec *pvec, enum lru_list lru);
 void pagevec_strip(struct pagevec *pvec);
+void pagevec_swap_free(struct pagevec *pvec);
 unsigned pagevec_lookup(struct pagevec *pvec, struct address_space *mapping,
 		pgoff_t start, unsigned nr_pages);
 unsigned pagevec_lookup_tag(struct pagevec *pvec,
@@ -81,10 +81,36 @@ static inline void pagevec_free(struct pagevec *pvec)
 		__pagevec_free(pvec);
 }
 
-static inline void pagevec_lru_add(struct pagevec *pvec)
+static inline void __pagevec_lru_add_anon(struct pagevec *pvec)
+{
+	____pagevec_lru_add(pvec, LRU_INACTIVE_ANON);
+}
+
+static inline void __pagevec_lru_add_active_anon(struct pagevec *pvec)
+{
+	____pagevec_lru_add(pvec, LRU_ACTIVE_ANON);
+}
+
+static inline void __pagevec_lru_add_file(struct pagevec *pvec)
+{
+	____pagevec_lru_add(pvec, LRU_INACTIVE_FILE);
+}
+
+static inline void __pagevec_lru_add_active_file(struct pagevec *pvec)
+{
+	____pagevec_lru_add(pvec, LRU_ACTIVE_FILE);
+}
+
+static inline void pagevec_lru_add_file(struct pagevec *pvec)
+{
+	if (pagevec_count(pvec))
+		__pagevec_lru_add_file(pvec);
+}
+
+static inline void pagevec_lru_add_anon(struct pagevec *pvec)
 {
 	if (pagevec_count(pvec))
-		__pagevec_lru_add(pvec);
+		__pagevec_lru_add_anon(pvec);
 }
 
 #endif /* _LINUX_PAGEVEC_H */
diff --git a/include/linux/parport.h b/include/linux/parport.h
index 6a0d7cdb5774..e1f83c5065c5 100644
--- a/include/linux/parport.h
+++ b/include/linux/parport.h
@@ -1,5 +1,3 @@
-/* $Id: parport.h,v 1.1 1998/05/17 10:57:52 andrea Exp andrea $ */
-
 /*
  * Any part of this program may be used in documents licensed under
  * the GNU Free Documentation License, Version 1.1 or any later version
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 98dc6243a706..03b0b8c3c81b 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -51,6 +51,7 @@
 #include <linux/kobject.h>
 #include <asm/atomic.h>
 #include <linux/device.h>
+#include <linux/io.h>
 
 /* Include the ID list */
 #include <linux/pci_ids.h>
@@ -64,6 +65,11 @@ struct pci_slot {
 	struct kobject kobj;
 };
 
+static inline const char *pci_slot_name(const struct pci_slot *slot)
+{
+	return kobject_name(&slot->kobj);
+}
+
 /* File state for mmap()s on /proc/bus/pci/X/Y */
 enum pci_mmap_state {
 	pci_mmap_io,
@@ -128,6 +134,11 @@ enum pci_dev_flags {
 	PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
 };
 
+enum pci_irq_reroute_variant {
+	INTEL_IRQ_REROUTE_VARIANT = 1,
+	MAX_IRQ_REROUTE_VARIANTS = 3
+};
+
 typedef unsigned short __bitwise pci_bus_flags_t;
 enum pci_bus_flags {
 	PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
@@ -212,8 +223,10 @@ struct pci_dev {
 	unsigned int	no_msi:1;	/* device may not use msi */
 	unsigned int	block_ucfg_access:1;	/* userspace config space access is blocked */
 	unsigned int	broken_parity_status:1;	/* Device generates false positive parity */
+	unsigned int	irq_reroute_variant:2;	/* device needs IRQ rerouting variant */
 	unsigned int 	msi_enabled:1;
 	unsigned int	msix_enabled:1;
+	unsigned int	ari_enabled:1;	/* ARI forwarding */
 	unsigned int	is_managed:1;
 	unsigned int	is_pcie:1;
 	pci_dev_flags_t dev_flags;
@@ -347,7 +360,6 @@ struct pci_bus_region {
 struct pci_dynids {
 	spinlock_t lock;            /* protects list, index */
 	struct list_head list;      /* for IDs added at runtime */
-	unsigned int use_driver_data:1; /* pci_device_id->driver_data is used */
 };
 
 /* ---------------------------------------------------------------- */
@@ -456,8 +468,8 @@ struct pci_driver {
 
 /**
  * PCI_VDEVICE - macro used to describe a specific pci device in short form
- * @vend: the vendor name
- * @dev: the 16 bit PCI Device ID
+ * @vendor: the vendor name
+ * @device: the 16 bit PCI Device ID
  *
  * This macro is used to create a struct pci_device_id that matches a
  * specific PCI device.  The subvendor, and subdevice fields will be set
@@ -509,9 +521,10 @@ struct pci_bus *pci_create_bus(struct device *parent, int bus,
 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
 				int busnr);
 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
-				 const char *name);
+				 const char *name,
+				 struct hotplug_slot *hotplug);
 void pci_destroy_slot(struct pci_slot *slot);
-void pci_update_slot_number(struct pci_slot *slot, int slot_nr);
+void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
 int pci_scan_slot(struct pci_bus *bus, int devfn);
 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
@@ -539,6 +552,13 @@ struct pci_dev __deprecated *pci_find_slot(unsigned int bus,
 					   unsigned int devfn);
 #endif /* CONFIG_PCI_LEGACY */
 
+enum pci_lost_interrupt_reason {
+	PCI_LOST_IRQ_NO_INFORMATION = 0,
+	PCI_LOST_IRQ_DISABLE_MSI,
+	PCI_LOST_IRQ_DISABLE_MSIX,
+	PCI_LOST_IRQ_DISABLE_ACPI,
+};
+enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
 int pci_find_capability(struct pci_dev *dev, int cap);
 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
 int pci_find_ext_capability(struct pci_dev *dev, int cap);
@@ -626,11 +646,15 @@ int pcix_get_mmrbc(struct pci_dev *dev);
 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
 int pcie_get_readrq(struct pci_dev *dev);
 int pcie_set_readrq(struct pci_dev *dev, int rq);
+int pci_reset_function(struct pci_dev *dev);
+int pci_execute_reset_function(struct pci_dev *dev);
 void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
 
 /* ROM control related routines */
+int pci_enable_rom(struct pci_dev *pdev);
+void pci_disable_rom(struct pci_dev *pdev);
 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
 size_t pci_get_rom_size(void __iomem *rom, size_t size);
@@ -643,6 +667,7 @@ pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
 void pci_pme_active(struct pci_dev *dev, bool enable);
 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
+int pci_wake_from_d3(struct pci_dev *dev, bool enable);
 pci_power_t pci_target_state(struct pci_dev *dev);
 int pci_prepare_to_sleep(struct pci_dev *dev);
 int pci_back_from_sleep(struct pci_dev *dev);
@@ -723,7 +748,7 @@ enum pci_dma_burst_strategy {
 };
 
 struct msix_entry {
-	u16 	vector;	/* kernel uses to write allocated vector */
+	u32	vector;	/* kernel uses to write allocated vector */
 	u16	entry;	/* driver uses to specify entry, OS writes */
 };
 
@@ -1116,5 +1141,20 @@ static inline void pci_mmcfg_early_init(void) { }
 static inline void pci_mmcfg_late_init(void) { }
 #endif
 
+#ifdef CONFIG_HAS_IOMEM
+static inline void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
+{
+	/*
+	 * Make sure the BAR is actually a memory resource, not an IO resource
+	 */
+	if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
+		WARN_ON(1);
+		return NULL;
+	}
+	return ioremap_nocache(pci_resource_start(pdev, bar),
+				     pci_resource_len(pdev, bar));
+}
+#endif
+
 #endif /* __KERNEL__ */
 #endif /* LINUX_PCI_H */
diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h
index a08cd06b541a..a00bd1a0f156 100644
--- a/include/linux/pci_hotplug.h
+++ b/include/linux/pci_hotplug.h
@@ -142,8 +142,6 @@ struct hotplug_slot_info {
 
 /**
  * struct hotplug_slot - used to register a physical slot with the hotplug pci core
- * @name: the name of the slot being registered.  This string must
- * be unique amoung slots registered on this system.
  * @ops: pointer to the &struct hotplug_slot_ops to be used for this slot
  * @info: pointer to the &struct hotplug_slot_info for the initial values for
  * this slot.
@@ -153,7 +151,6 @@ struct hotplug_slot_info {
  * needs.
  */
 struct hotplug_slot {
-	char				*name;
 	struct hotplug_slot_ops		*ops;
 	struct hotplug_slot_info	*info;
 	void (*release) (struct hotplug_slot *slot);
@@ -165,7 +162,13 @@ struct hotplug_slot {
 };
 #define to_hotplug_slot(n) container_of(n, struct hotplug_slot, kobj)
 
-extern int pci_hp_register(struct hotplug_slot *, struct pci_bus *, int nr);
+static inline const char *hotplug_slot_name(const struct hotplug_slot *slot)
+{
+	return pci_slot_name(slot->pci_slot);
+}
+
+extern int pci_hp_register(struct hotplug_slot *, struct pci_bus *, int nr,
+			   const char *name);
 extern int pci_hp_deregister(struct hotplug_slot *slot);
 extern int __must_check pci_hp_change_slot_info	(struct hotplug_slot *slot,
 						 struct hotplug_slot_info *info);
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 1176f1f177e2..b6e694454280 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -587,6 +587,7 @@
 #define PCI_DEVICE_ID_MATROX_G200_PCI	0x0520
 #define PCI_DEVICE_ID_MATROX_G200_AGP	0x0521
 #define	PCI_DEVICE_ID_MATROX_G400	0x0525
+#define	PCI_DEVICE_ID_MATROX_G200EV_PCI	0x0530
 #define PCI_DEVICE_ID_MATROX_G550	0x2527
 #define PCI_DEVICE_ID_MATROX_VIA	0x4536
 
@@ -1943,6 +1944,14 @@
 
 #define PCI_VENDOR_ID_OXSEMI		0x1415
 #define PCI_DEVICE_ID_OXSEMI_12PCI840	0x8403
+#define PCI_DEVICE_ID_OXSEMI_PCIe840		0xC000
+#define PCI_DEVICE_ID_OXSEMI_PCIe840_G		0xC004
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_0		0xC100
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_0_G	0xC104
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_1		0xC110
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_G	0xC114
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_U	0xC118
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU	0xC11C
 #define PCI_DEVICE_ID_OXSEMI_16PCI954	0x9501
 #define PCI_DEVICE_ID_OXSEMI_16PCI95N	0x9511
 #define PCI_DEVICE_ID_OXSEMI_16PCI954PP	0x9513
@@ -2295,6 +2304,10 @@
 #define PCI_DEVICE_ID_INTEL_PXH_0	0x0329
 #define PCI_DEVICE_ID_INTEL_PXH_1	0x032A
 #define PCI_DEVICE_ID_INTEL_PXHV	0x032C
+#define PCI_DEVICE_ID_INTEL_80332_0	0x0330
+#define PCI_DEVICE_ID_INTEL_80332_1	0x0332
+#define PCI_DEVICE_ID_INTEL_80333_0	0x0370
+#define PCI_DEVICE_ID_INTEL_80333_1	0x0372
 #define PCI_DEVICE_ID_INTEL_82375	0x0482
 #define PCI_DEVICE_ID_INTEL_82424	0x0483
 #define PCI_DEVICE_ID_INTEL_82378	0x0484
@@ -2367,6 +2380,7 @@
 #define PCI_DEVICE_ID_INTEL_ESB_4	0x25a4
 #define PCI_DEVICE_ID_INTEL_ESB_5	0x25a6
 #define PCI_DEVICE_ID_INTEL_ESB_9	0x25ab
+#define PCI_DEVICE_ID_INTEL_ESB_10	0x25ac
 #define PCI_DEVICE_ID_INTEL_82820_HB	0x2500
 #define PCI_DEVICE_ID_INTEL_82820_UP_HB	0x2501
 #define PCI_DEVICE_ID_INTEL_82850_HB	0x2530
@@ -2447,15 +2461,16 @@
 #define PCI_DEVICE_ID_INTEL_MCH_PC1	0x359a
 #define PCI_DEVICE_ID_INTEL_E7525_MCH	0x359e
 #define PCI_DEVICE_ID_INTEL_IOAT_CNB	0x360b
+#define PCI_DEVICE_ID_INTEL_FBD_CNB	0x360c
 #define PCI_DEVICE_ID_INTEL_ICH10_0	0x3a14
 #define PCI_DEVICE_ID_INTEL_ICH10_1	0x3a16
 #define PCI_DEVICE_ID_INTEL_ICH10_2	0x3a18
 #define PCI_DEVICE_ID_INTEL_ICH10_3	0x3a1a
 #define PCI_DEVICE_ID_INTEL_ICH10_4	0x3a30
 #define PCI_DEVICE_ID_INTEL_ICH10_5	0x3a60
-#define PCI_DEVICE_ID_INTEL_PCH_0	0x3b10
-#define PCI_DEVICE_ID_INTEL_PCH_1	0x3b11
-#define PCI_DEVICE_ID_INTEL_PCH_2	0x3b30
+#define PCI_DEVICE_ID_INTEL_PCH_LPC_MIN	0x3b00
+#define PCI_DEVICE_ID_INTEL_PCH_LPC_MAX	0x3b1f
+#define PCI_DEVICE_ID_INTEL_PCH_SMBUS	0x3b30
 #define PCI_DEVICE_ID_INTEL_IOAT_SNB	0x402f
 #define PCI_DEVICE_ID_INTEL_5100_16	0x65f0
 #define PCI_DEVICE_ID_INTEL_5100_21	0x65f5
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 450684f7eaac..e5effd47ed74 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -377,6 +377,7 @@
 #define  PCI_EXP_DEVCAP_RBER	0x8000	/* Role-Based Error Reporting */
 #define  PCI_EXP_DEVCAP_PWR_VAL	0x3fc0000 /* Slot Power Limit Value */
 #define  PCI_EXP_DEVCAP_PWR_SCL	0xc000000 /* Slot Power Limit Scale */
+#define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
 #define PCI_EXP_DEVCTL		8	/* Device Control */
 #define  PCI_EXP_DEVCTL_CERE	0x0001	/* Correctable Error Reporting En. */
 #define  PCI_EXP_DEVCTL_NFERE	0x0002	/* Non-Fatal Error Reporting Enable */
@@ -389,6 +390,7 @@
 #define  PCI_EXP_DEVCTL_AUX_PME	0x0400	/* Auxiliary Power PM Enable */
 #define  PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  /* Enable No Snoop */
 #define  PCI_EXP_DEVCTL_READRQ	0x7000	/* Max_Read_Request_Size */
+#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
 #define PCI_EXP_DEVSTA		10	/* Device Status */
 #define  PCI_EXP_DEVSTA_CED	0x01	/* Correctable Error Detected */
 #define  PCI_EXP_DEVSTA_NFED	0x02	/* Non-Fatal Error Detected */
@@ -419,6 +421,10 @@
 #define  PCI_EXP_RTCTL_CRSSVE	0x10	/* CRS Software Visibility Enable */
 #define PCI_EXP_RTCAP		30	/* Root Capabilities */
 #define PCI_EXP_RTSTA		32	/* Root Status */
+#define PCI_EXP_DEVCAP2		36	/* Device Capabilities 2 */
+#define  PCI_EXP_DEVCAP2_ARI	0x20	/* Alternative Routing-ID */
+#define PCI_EXP_DEVCTL2		40	/* Device Control 2 */
+#define  PCI_EXP_DEVCTL2_ARI	0x20	/* Alternative Routing-ID */
 
 /* Extended Capabilities (PCI-X 2.0 and Express) */
 #define PCI_EXT_CAP_ID(header)		(header & 0x0000ffff)
@@ -429,6 +435,7 @@
 #define PCI_EXT_CAP_ID_VC	2
 #define PCI_EXT_CAP_ID_DSN	3
 #define PCI_EXT_CAP_ID_PWR	4
+#define PCI_EXT_CAP_ID_ARI	14
 
 /* Advanced Error Reporting */
 #define PCI_ERR_UNCOR_STATUS	4	/* Uncorrectable Error Status */
@@ -536,5 +543,14 @@
 #define HT_CAPTYPE_GEN3		0xD0	/* Generation 3 hypertransport configuration */
 #define HT_CAPTYPE_PM		0xE0	/* Hypertransport powermanagement configuration */
 
+/* Alternative Routing-ID Interpretation */
+#define PCI_ARI_CAP		0x04	/* ARI Capability Register */
+#define  PCI_ARI_CAP_MFVC	0x0001	/* MFVC Function Groups Capability */
+#define  PCI_ARI_CAP_ACS	0x0002	/* ACS Function Groups Capability */
+#define  PCI_ARI_CAP_NFN(x)	(((x) >> 8) & 0xff) /* Next Function Number */
+#define PCI_ARI_CTRL		0x06	/* ARI Control Register */
+#define  PCI_ARI_CTRL_MFVC	0x0001	/* MFVC Function Groups Enable */
+#define  PCI_ARI_CTRL_ACS	0x0002	/* ACS Function Groups Enable */
+#define  PCI_ARI_CTRL_FG(x)	(((x) >> 4) & 7) /* Function Group */
 
 #endif /* LINUX_PCI_REGS_H */
diff --git a/include/linux/pfn.h b/include/linux/pfn.h
index bb01f8b92b56..7646637221f3 100644
--- a/include/linux/pfn.h
+++ b/include/linux/pfn.h
@@ -1,9 +1,13 @@
 #ifndef _LINUX_PFN_H_
 #define _LINUX_PFN_H_
 
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#endif
+
 #define PFN_ALIGN(x)	(((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
 #define PFN_UP(x)	(((x) + PAGE_SIZE-1) >> PAGE_SHIFT)
 #define PFN_DOWN(x)	((x) >> PAGE_SHIFT)
-#define PFN_PHYS(x)	((x) << PAGE_SHIFT)
+#define PFN_PHYS(x)	((phys_addr_t)(x) << PAGE_SHIFT)
 
 #endif
diff --git a/include/linux/phonet.h b/include/linux/phonet.h
index c9609f9aedac..4157faa857b6 100644
--- a/include/linux/phonet.h
+++ b/include/linux/phonet.h
@@ -72,6 +72,7 @@ struct phonetmsg {
 	} pn_msg_u;
 };
 #define PN_COMMON_MESSAGE	0xF0
+#define PN_COMMGR		0x10
 #define PN_PREFIX		0xE0 /* resource for extended messages */
 #define pn_submsg_id		pn_msg_u.base.pn_submsg_id
 #define pn_e_submsg_id		pn_msg_u.ext.pn_e_submsg_id
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 77c4ed60b982..d7e54d98869f 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -467,6 +467,8 @@ int genphy_restart_aneg(struct phy_device *phydev);
 int genphy_config_aneg(struct phy_device *phydev);
 int genphy_update_link(struct phy_device *phydev);
 int genphy_read_status(struct phy_device *phydev);
+int genphy_suspend(struct phy_device *phydev);
+int genphy_resume(struct phy_device *phydev);
 void phy_driver_unregister(struct phy_driver *drv);
 int phy_driver_register(struct phy_driver *new_driver);
 void phy_prepare_link(struct phy_device *phydev,
diff --git a/include/linux/pid.h b/include/linux/pid.h
index d7e98ff8021e..bb206c56d1f0 100644
--- a/include/linux/pid.h
+++ b/include/linux/pid.h
@@ -147,9 +147,9 @@ pid_t pid_vnr(struct pid *pid);
 #define do_each_pid_task(pid, type, task)				\
 	do {								\
 		struct hlist_node *pos___;				\
-		if (pid != NULL)					\
+		if ((pid) != NULL)					\
 			hlist_for_each_entry_rcu((task), pos___,	\
-				&pid->tasks[type], pids[type].node) {
+				&(pid)->tasks[type], pids[type].node) {
 
 			/*
 			 * Both old and new leaders may be attached to
diff --git a/include/linux/pid_namespace.h b/include/linux/pid_namespace.h
index 1af82c4e17d4..d82fe825d62f 100644
--- a/include/linux/pid_namespace.h
+++ b/include/linux/pid_namespace.h
@@ -84,12 +84,6 @@ static inline struct pid_namespace *task_active_pid_ns(struct task_struct *tsk)
 	return tsk->nsproxy->pid_ns;
 }
 
-static inline struct task_struct *task_child_reaper(struct task_struct *tsk)
-{
-	BUG_ON(tsk != current);
-	return tsk->nsproxy->pid_ns->child_reaper;
-}
-
 void pidhash_init(void);
 void pidmap_init(void);
 
diff --git a/include/linux/pkt_cls.h b/include/linux/pkt_cls.h
index 7cf7824df778..e6aa8482ad7a 100644
--- a/include/linux/pkt_cls.h
+++ b/include/linux/pkt_cls.h
@@ -394,6 +394,20 @@ enum
 
 #define TCA_BASIC_MAX (__TCA_BASIC_MAX - 1)
 
+
+/* Cgroup classifier */
+
+enum
+{
+	TCA_CGROUP_UNSPEC,
+	TCA_CGROUP_ACT,
+	TCA_CGROUP_POLICE,
+	TCA_CGROUP_EMATCHES,
+	__TCA_CGROUP_MAX,
+};
+
+#define TCA_CGROUP_MAX (__TCA_CGROUP_MAX - 1)
+
 /* Extended Matches */
 
 struct tcf_ematch_tree_hdr
diff --git a/include/linux/pkt_sched.h b/include/linux/pkt_sched.h
index 5d921fa91a5b..e3f133adba78 100644
--- a/include/linux/pkt_sched.h
+++ b/include/linux/pkt_sched.h
@@ -500,4 +500,20 @@ struct tc_netem_corrupt
 
 #define NETEM_DIST_SCALE	8192
 
+/* DRR */
+
+enum
+{
+	TCA_DRR_UNSPEC,
+	TCA_DRR_QUANTUM,
+	__TCA_DRR_MAX
+};
+
+#define TCA_DRR_MAX	(__TCA_DRR_MAX - 1)
+
+struct tc_drr_stats
+{
+	u32	deficit;
+};
+
 #endif
diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h
index 95ac21ab3a09..4b8cc6a32479 100644
--- a/include/linux/platform_device.h
+++ b/include/linux/platform_device.h
@@ -37,6 +37,8 @@ extern int platform_add_devices(struct platform_device **, int);
 
 extern struct platform_device *platform_device_register_simple(const char *, int id,
 					struct resource *, unsigned int);
+extern struct platform_device *platform_device_register_data(struct device *,
+		const char *, int, const void *, size_t);
 
 extern struct platform_device *platform_device_alloc(const char *name, int id);
 extern int platform_device_add_resources(struct platform_device *pdev, struct resource *res, unsigned int num);
diff --git a/include/linux/pm.h b/include/linux/pm.h
index 4dcce54b6d76..42de4003c4ee 100644
--- a/include/linux/pm.h
+++ b/include/linux/pm.h
@@ -419,7 +419,7 @@ extern void __suspend_report_result(const char *function, void *fn, int ret);
 
 #define suspend_report_result(fn, ret)					\
 	do {								\
-		__suspend_report_result(__FUNCTION__, fn, ret);		\
+		__suspend_report_result(__func__, fn, ret);		\
 	} while (0)
 
 #else /* !CONFIG_PM_SLEEP */
diff --git a/include/linux/pnp.h b/include/linux/pnp.h
index be764e514e35..ca3c88773028 100644
--- a/include/linux/pnp.h
+++ b/include/linux/pnp.h
@@ -22,9 +22,11 @@ struct pnp_dev;
  * Resource Management
  */
 #ifdef CONFIG_PNP
-struct resource *pnp_get_resource(struct pnp_dev *, unsigned int, unsigned int);
+struct resource *pnp_get_resource(struct pnp_dev *dev, unsigned long type,
+				unsigned int num);
 #else
-static inline struct resource *pnp_get_resource(struct pnp_dev *dev, unsigned int type, unsigned int num)
+static inline struct resource *pnp_get_resource(struct pnp_dev *dev,
+			unsigned long type, unsigned int num)
 {
 	return NULL;
 }
@@ -483,14 +485,4 @@ static inline void pnp_unregister_driver(struct pnp_driver *drv) { }
 
 #endif /* CONFIG_PNP */
 
-#define pnp_err(format, arg...) printk(KERN_ERR "pnp: " format "\n" , ## arg)
-#define pnp_info(format, arg...) printk(KERN_INFO "pnp: " format "\n" , ## arg)
-#define pnp_warn(format, arg...) printk(KERN_WARNING "pnp: " format "\n" , ## arg)
-
-#ifdef CONFIG_PNP_DEBUG
-#define pnp_dbg(format, arg...) printk(KERN_DEBUG "pnp: " format "\n" , ## arg)
-#else
-#define pnp_dbg(format, arg...) do {} while (0)
-#endif
-
 #endif /* _LINUX_PNP_H */
diff --git a/include/linux/poll.h b/include/linux/poll.h
index ef453828877a..badd98ab06f6 100644
--- a/include/linux/poll.h
+++ b/include/linux/poll.h
@@ -114,11 +114,13 @@ void zero_fd_set(unsigned long nr, unsigned long *fdset)
 
 #define MAX_INT64_SECONDS (((s64)(~((u64)0)>>1)/HZ)-1)
 
-extern int do_select(int n, fd_set_bits *fds, s64 *timeout);
+extern int do_select(int n, fd_set_bits *fds, struct timespec *end_time);
 extern int do_sys_poll(struct pollfd __user * ufds, unsigned int nfds,
-		       s64 *timeout);
+		       struct timespec *end_time);
 extern int core_sys_select(int n, fd_set __user *inp, fd_set __user *outp,
-			   fd_set __user *exp, s64 *timeout);
+			   fd_set __user *exp, struct timespec *end_time);
+
+extern int poll_select_set_timeout(struct timespec *to, long sec, long nsec);
 
 #endif /* KERNEL */
 
diff --git a/include/linux/posix-timers.h b/include/linux/posix-timers.h
index a7dd38f30ade..4f71bf4e628c 100644
--- a/include/linux/posix-timers.h
+++ b/include/linux/posix-timers.h
@@ -45,9 +45,11 @@ struct k_itimer {
 	int it_requeue_pending;		/* waiting to requeue this timer */
 #define REQUEUE_PENDING 1
 	int it_sigev_notify;		/* notify word of sigevent struct */
-	int it_sigev_signo;		/* signo word of sigevent struct */
-	sigval_t it_sigev_value;	/* value word of sigevent struct */
-	struct task_struct *it_process;	/* process to send signal to */
+	struct signal_struct *it_signal;
+	union {
+		struct pid *it_pid;	/* pid of process to send signal to */
+		struct task_struct *it_process;	/* for clock_nanosleep */
+	};
 	struct sigqueue *sigq;		/* signal queue entry. */
 	union {
 		struct {
@@ -115,4 +117,6 @@ void set_process_cpu_timer(struct task_struct *task, unsigned int clock_idx,
 
 long clock_nanosleep_restart(struct restart_block *restart_block);
 
+void update_rlimit_cpu(unsigned long rlim_new);
+
 #endif
diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h
index ea96ead1d39d..f9348cba6dc1 100644
--- a/include/linux/power_supply.h
+++ b/include/linux/power_supply.h
@@ -165,6 +165,12 @@ struct power_supply_info {
 extern void power_supply_changed(struct power_supply *psy);
 extern int power_supply_am_i_supplied(struct power_supply *psy);
 
+#if defined(CONFIG_POWER_SUPPLY) || defined(CONFIG_POWER_SUPPLY_MODULE)
+extern int power_supply_is_system_supplied(void);
+#else
+static inline int power_supply_is_system_supplied(void) { return -ENOSYS; }
+#endif
+
 extern int power_supply_register(struct device *parent,
 				 struct power_supply *psy);
 extern void power_supply_unregister(struct power_supply *psy);
diff --git a/include/linux/prctl.h b/include/linux/prctl.h
index 5ad79198d6f9..48d887e3c6e7 100644
--- a/include/linux/prctl.h
+++ b/include/linux/prctl.h
@@ -78,4 +78,11 @@
 #define PR_GET_SECUREBITS 27
 #define PR_SET_SECUREBITS 28
 
+/*
+ * Get/set the timerslack as used by poll/select/nanosleep
+ * A value of 0 means "use default"
+ */
+#define PR_SET_TIMERSLACK 29
+#define PR_GET_TIMERSLACK 30
+
 #endif /* _LINUX_PRCTL_H */
diff --git a/include/linux/proc_fs.h b/include/linux/proc_fs.h
index fb61850d1cfc..b8bdb96eff78 100644
--- a/include/linux/proc_fs.h
+++ b/include/linux/proc_fs.h
@@ -97,12 +97,9 @@ struct vmcore {
 
 #ifdef CONFIG_PROC_FS
 
-extern struct proc_dir_entry *proc_root_kcore;
-
 extern spinlock_t proc_subdir_lock;
 
 extern void proc_root_init(void);
-extern void proc_misc_init(void);
 
 void proc_flush_task(struct task_struct *task);
 struct dentry *proc_pid_lookup(struct inode *dir, struct dentry * dentry, struct nameidata *);
@@ -138,9 +135,6 @@ extern struct inode *proc_get_inode(struct super_block *, unsigned int, struct p
 extern int proc_readdir(struct file *, void *, filldir_t);
 extern struct dentry *proc_lookup(struct inode *, struct dentry *, struct nameidata *);
 
-extern const struct file_operations proc_kcore_operations;
-extern const struct file_operations ppc_htab_operations;
-
 extern int pid_ns_prepare_proc(struct pid_namespace *ns);
 extern void pid_ns_release_proc(struct pid_namespace *ns);
 
diff --git a/include/linux/profile.h b/include/linux/profile.h
index 7e7087239af5..a0fc32279fc0 100644
--- a/include/linux/profile.h
+++ b/include/linux/profile.h
@@ -19,10 +19,16 @@ struct notifier_block;
 
 #if defined(CONFIG_PROFILING) && defined(CONFIG_PROC_FS)
 void create_prof_cpu_mask(struct proc_dir_entry *de);
+int create_proc_profile(void);
 #else
 static inline void create_prof_cpu_mask(struct proc_dir_entry *de)
 {
 }
+
+static inline int create_proc_profile(void)
+{
+	return 0;
+}
 #endif
 
 enum profile_type {
@@ -35,7 +41,8 @@ enum profile_type {
 extern int prof_on __read_mostly;
 
 /* init basic kernel profiler */
-void __init profile_init(void);
+int profile_init(void);
+int profile_setup(char *str);
 void profile_tick(int type);
 
 /*
@@ -84,9 +91,9 @@ struct pt_regs;
 
 #define prof_on 0
 
-static inline void profile_init(void)
+static inline int profile_init(void)
 {
-	return;
+	return 0;
 }
 
 static inline void profile_tick(int type)
diff --git a/include/linux/ptrace.h b/include/linux/ptrace.h
index ea7416c901d1..98b93ca4db06 100644
--- a/include/linux/ptrace.h
+++ b/include/linux/ptrace.h
@@ -94,7 +94,7 @@ extern void ptrace_notify(int exit_code);
 extern void __ptrace_link(struct task_struct *child,
 			  struct task_struct *new_parent);
 extern void __ptrace_unlink(struct task_struct *child);
-extern void ptrace_untrace(struct task_struct *child);
+extern void ptrace_fork(struct task_struct *task, unsigned long clone_flags);
 #define PTRACE_MODE_READ   1
 #define PTRACE_MODE_ATTACH 2
 /* Returns 0 on success, -errno on denial. */
@@ -314,6 +314,27 @@ static inline void user_enable_block_step(struct task_struct *task)
 #define arch_ptrace_stop(code, info)		do { } while (0)
 #endif
 
+#ifndef arch_ptrace_untrace
+/*
+ * Do machine-specific work before untracing child.
+ *
+ * This is called for a normal detach as well as from ptrace_exit()
+ * when the tracing task dies.
+ *
+ * Called with write_lock(&tasklist_lock) held.
+ */
+#define arch_ptrace_untrace(task)		do { } while (0)
+#endif
+
+#ifndef arch_ptrace_fork
+/*
+ * Do machine-specific work to initialize a new task.
+ *
+ * This is called from copy_process().
+ */
+#define arch_ptrace_fork(child, clone_flags)	do { } while (0)
+#endif
+
 extern int task_current_syscall(struct task_struct *target, long *callno,
 				unsigned long args[6], unsigned int maxargs,
 				unsigned long *sp, unsigned long *pc);
diff --git a/include/linux/quota.h b/include/linux/quota.h
index 376a05048bc5..40401b554484 100644
--- a/include/linux/quota.h
+++ b/include/linux/quota.h
@@ -28,8 +28,6 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
- *
- * Version: $Id: quota.h,v 2.0 1996/11/17 16:48:14 mvw Exp mvw $
  */
 
 #ifndef _LINUX_QUOTA_
diff --git a/include/linux/quotaops.h b/include/linux/quotaops.h
index ca6b9b5c8d52..a558a4c1d35a 100644
--- a/include/linux/quotaops.h
+++ b/include/linux/quotaops.h
@@ -3,9 +3,6 @@
  * macros expand to the right source-code.
  *
  * Author:  Marco van Wieringen <mvw@planets.elm.net>
- *
- * Version: $Id: quotaops.h,v 1.2 1998/01/15 16:22:26 ecd Exp $
- *
  */
 #ifndef _LINUX_QUOTAOPS_
 #define _LINUX_QUOTAOPS_
diff --git a/include/linux/raid/linear.h b/include/linux/raid/linear.h
index 7e375111d007..f38b9c586afb 100644
--- a/include/linux/raid/linear.h
+++ b/include/linux/raid/linear.h
@@ -5,8 +5,8 @@
 
 struct dev_info {
 	mdk_rdev_t	*rdev;
-	sector_t	size;
-	sector_t	offset;
+	sector_t	num_sectors;
+	sector_t	start_sector;
 };
 
 typedef struct dev_info dev_info_t;
@@ -15,9 +15,11 @@ struct linear_private_data
 {
 	struct linear_private_data *prev;	/* earlier version */
 	dev_info_t		**hash_table;
-	sector_t		hash_spacing;
+	sector_t		spacing;
 	sector_t		array_sectors;
-	int			preshift; /* shift before dividing by hash_spacing */
+	int			sector_shift;	/* shift before dividing
+						 * by spacing
+						 */
 	dev_info_t		disks[0];
 };
 
diff --git a/include/linux/raid/md.h b/include/linux/raid/md.h
index dc0e3fcb9f28..82bea14cae1a 100644
--- a/include/linux/raid/md.h
+++ b/include/linux/raid/md.h
@@ -19,27 +19,7 @@
 #define _MD_H
 
 #include <linux/blkdev.h>
-#include <linux/major.h>
-#include <linux/ioctl.h>
-#include <linux/types.h>
-#include <linux/bitops.h>
-#include <linux/module.h>
-#include <linux/hdreg.h>
-#include <linux/proc_fs.h>
 #include <linux/seq_file.h>
-#include <linux/smp_lock.h>
-#include <linux/delay.h>
-#include <net/checksum.h>
-#include <linux/random.h>
-#include <linux/kernel_stat.h>
-#include <asm/io.h>
-#include <linux/completion.h>
-#include <linux/mempool.h>
-#include <linux/list.h>
-#include <linux/reboot.h>
-#include <linux/vmalloc.h>
-#include <linux/blkpg.h>
-#include <linux/bio.h>
 
 /*
  * 'md_p.h' holds the 'physical' layout of RAID devices
@@ -74,19 +54,17 @@
 
 extern int mdp_major;
 
-extern int register_md_personality (struct mdk_personality *p);
-extern int unregister_md_personality (struct mdk_personality *p);
-extern mdk_thread_t * md_register_thread (void (*run) (mddev_t *mddev),
+extern int register_md_personality(struct mdk_personality *p);
+extern int unregister_md_personality(struct mdk_personality *p);
+extern mdk_thread_t * md_register_thread(void (*run) (mddev_t *mddev),
 				mddev_t *mddev, const char *name);
-extern void md_unregister_thread (mdk_thread_t *thread);
+extern void md_unregister_thread(mdk_thread_t *thread);
 extern void md_wakeup_thread(mdk_thread_t *thread);
 extern void md_check_recovery(mddev_t *mddev);
 extern void md_write_start(mddev_t *mddev, struct bio *bi);
 extern void md_write_end(mddev_t *mddev);
-extern void md_handle_safemode(mddev_t *mddev);
 extern void md_done_sync(mddev_t *mddev, int blocks, int ok);
-extern void md_error (mddev_t *mddev, mdk_rdev_t *rdev);
-extern void md_unplug_mddev(mddev_t *mddev);
+extern void md_error(mddev_t *mddev, mdk_rdev_t *rdev);
 
 extern void md_super_write(mddev_t *mddev, mdk_rdev_t *rdev,
 			   sector_t sector, int size, struct page *page);
diff --git a/include/linux/raid/md_k.h b/include/linux/raid/md_k.h
index c200b9a34aff..8fc909ef6787 100644
--- a/include/linux/raid/md_k.h
+++ b/include/linux/raid/md_k.h
@@ -115,6 +115,9 @@ struct mdk_rdev_s
 					   * in superblock.
 					   */
 	struct work_struct del_work;	/* used for delayed sysfs removal */
+
+	struct sysfs_dirent *sysfs_state; /* handle for 'state'
+					   * sysfs entry */
 };
 
 struct mddev_s
@@ -128,7 +131,6 @@ struct mddev_s
 #define MD_CHANGE_DEVS	0	/* Some device status has changed */
 #define MD_CHANGE_CLEAN 1	/* transition to or from 'clean' */
 #define MD_CHANGE_PENDING 2	/* superblock update in progress */
-#define MD_NOTIFY_ARRAY_STATE 3	/* atomic context wants to notify userspace */
 
 	int				ro;
 
@@ -239,6 +241,10 @@ struct mddev_s
 	sector_t			resync_max;	/* resync should pause
 							 * when it gets here */
 
+	struct sysfs_dirent		*sysfs_state;	/* handle for 'array_state'
+							 * file in sysfs.
+							 */
+
 	spinlock_t			write_lock;
 	wait_queue_head_t		sb_wait;	/* for waiting on superblock updates */
 	atomic_t			pending_writes;	/* number of active superblock writes */
diff --git a/include/linux/random.h b/include/linux/random.h
index 36f125c0c603..adbf3bd3c6b3 100644
--- a/include/linux/random.h
+++ b/include/linux/random.h
@@ -8,6 +8,7 @@
 #define _LINUX_RANDOM_H
 
 #include <linux/ioctl.h>
+#include <linux/irqnr.h>
 
 /* ioctl()'s for the random number generator */
 
@@ -44,6 +45,56 @@ struct rand_pool_info {
 
 extern void rand_initialize_irq(int irq);
 
+struct timer_rand_state;
+#ifndef CONFIG_SPARSE_IRQ
+
+extern struct timer_rand_state *irq_timer_state[];
+
+static inline struct timer_rand_state *get_timer_rand_state(unsigned int irq)
+{
+	if (irq >= nr_irqs)
+		return NULL;
+
+	return irq_timer_state[irq];
+}
+
+static inline void set_timer_rand_state(unsigned int irq, struct timer_rand_state *state)
+{
+	if (irq >= nr_irqs)
+		return;
+
+	irq_timer_state[irq] = state;
+}
+
+#else
+
+#include <linux/irq.h>
+static inline struct timer_rand_state *get_timer_rand_state(unsigned int irq)
+{
+	struct irq_desc *desc;
+
+	desc = irq_to_desc(irq);
+
+	if (!desc)
+		return NULL;
+
+	return desc->timer_rand_state;
+}
+
+static inline void set_timer_rand_state(unsigned int irq, struct timer_rand_state *state)
+{
+	struct irq_desc *desc;
+
+	desc = irq_to_desc(irq);
+
+	if (!desc)
+		return;
+
+	desc->timer_rand_state = state;
+}
+#endif
+
+
 extern void add_input_randomness(unsigned int type, unsigned int code,
 				 unsigned int value);
 extern void add_interrupt_randomness(int irq);
diff --git a/include/linux/ratelimit.h b/include/linux/ratelimit.h
index 18a5b9ba9d40..00044b856453 100644
--- a/include/linux/ratelimit.h
+++ b/include/linux/ratelimit.h
@@ -17,11 +17,4 @@ struct ratelimit_state {
 		struct ratelimit_state name = {interval, burst,}
 
 extern int __ratelimit(struct ratelimit_state *rs);
-
-static inline int ratelimit(void)
-{
-	static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
-					DEFAULT_RATELIMIT_BURST);
-	return __ratelimit(&rs);
-}
 #endif
diff --git a/include/linux/rcuclassic.h b/include/linux/rcuclassic.h
index 5f89b62e6983..301dda829e37 100644
--- a/include/linux/rcuclassic.h
+++ b/include/linux/rcuclassic.h
@@ -41,7 +41,7 @@
 #include <linux/seqlock.h>
 
 #ifdef CONFIG_RCU_CPU_STALL_DETECTOR
-#define RCU_SECONDS_TILL_STALL_CHECK	( 3 * HZ) /* for rcp->jiffies_stall */
+#define RCU_SECONDS_TILL_STALL_CHECK	(10 * HZ) /* for rcp->jiffies_stall */
 #define RCU_SECONDS_TILL_STALL_RECHECK	(30 * HZ) /* for rcp->jiffies_stall */
 #endif /* #ifdef CONFIG_RCU_CPU_STALL_DETECTOR */
 
diff --git a/include/linux/rculist_nulls.h b/include/linux/rculist_nulls.h
new file mode 100644
index 000000000000..f9ddd03961a8
--- /dev/null
+++ b/include/linux/rculist_nulls.h
@@ -0,0 +1,110 @@
+#ifndef _LINUX_RCULIST_NULLS_H
+#define _LINUX_RCULIST_NULLS_H
+
+#ifdef __KERNEL__
+
+/*
+ * RCU-protected list version
+ */
+#include <linux/list_nulls.h>
+#include <linux/rcupdate.h>
+
+/**
+ * hlist_nulls_del_init_rcu - deletes entry from hash list with re-initialization
+ * @n: the element to delete from the hash list.
+ *
+ * Note: hlist_nulls_unhashed() on the node return true after this. It is
+ * useful for RCU based read lockfree traversal if the writer side
+ * must know if the list entry is still hashed or already unhashed.
+ *
+ * In particular, it means that we can not poison the forward pointers
+ * that may still be used for walking the hash list and we can only
+ * zero the pprev pointer so list_unhashed() will return true after
+ * this.
+ *
+ * The caller must take whatever precautions are necessary (such as
+ * holding appropriate locks) to avoid racing with another
+ * list-mutation primitive, such as hlist_nulls_add_head_rcu() or
+ * hlist_nulls_del_rcu(), running on this same list.  However, it is
+ * perfectly legal to run concurrently with the _rcu list-traversal
+ * primitives, such as hlist_nulls_for_each_entry_rcu().
+ */
+static inline void hlist_nulls_del_init_rcu(struct hlist_nulls_node *n)
+{
+	if (!hlist_nulls_unhashed(n)) {
+		__hlist_nulls_del(n);
+		n->pprev = NULL;
+	}
+}
+
+/**
+ * hlist_nulls_del_rcu - deletes entry from hash list without re-initialization
+ * @n: the element to delete from the hash list.
+ *
+ * Note: hlist_nulls_unhashed() on entry does not return true after this,
+ * the entry is in an undefined state. It is useful for RCU based
+ * lockfree traversal.
+ *
+ * In particular, it means that we can not poison the forward
+ * pointers that may still be used for walking the hash list.
+ *
+ * The caller must take whatever precautions are necessary
+ * (such as holding appropriate locks) to avoid racing
+ * with another list-mutation primitive, such as hlist_nulls_add_head_rcu()
+ * or hlist_nulls_del_rcu(), running on this same list.
+ * However, it is perfectly legal to run concurrently with
+ * the _rcu list-traversal primitives, such as
+ * hlist_nulls_for_each_entry().
+ */
+static inline void hlist_nulls_del_rcu(struct hlist_nulls_node *n)
+{
+	__hlist_nulls_del(n);
+	n->pprev = LIST_POISON2;
+}
+
+/**
+ * hlist_nulls_add_head_rcu
+ * @n: the element to add to the hash list.
+ * @h: the list to add to.
+ *
+ * Description:
+ * Adds the specified element to the specified hlist_nulls,
+ * while permitting racing traversals.
+ *
+ * The caller must take whatever precautions are necessary
+ * (such as holding appropriate locks) to avoid racing
+ * with another list-mutation primitive, such as hlist_nulls_add_head_rcu()
+ * or hlist_nulls_del_rcu(), running on this same list.
+ * However, it is perfectly legal to run concurrently with
+ * the _rcu list-traversal primitives, such as
+ * hlist_nulls_for_each_entry_rcu(), used to prevent memory-consistency
+ * problems on Alpha CPUs.  Regardless of the type of CPU, the
+ * list-traversal primitive must be guarded by rcu_read_lock().
+ */
+static inline void hlist_nulls_add_head_rcu(struct hlist_nulls_node *n,
+					struct hlist_nulls_head *h)
+{
+	struct hlist_nulls_node *first = h->first;
+
+	n->next = first;
+	n->pprev = &h->first;
+	rcu_assign_pointer(h->first, n);
+	if (!is_a_nulls(first))
+		first->pprev = &n->next;
+}
+/**
+ * hlist_nulls_for_each_entry_rcu - iterate over rcu list of given type
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct hlist_nulls_node to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the hlist_nulls_node within the struct.
+ *
+ */
+#define hlist_nulls_for_each_entry_rcu(tpos, pos, head, member) \
+	for (pos = rcu_dereference((head)->first);			 \
+		(!is_a_nulls(pos)) && 			\
+		({ tpos = hlist_nulls_entry(pos, typeof(*tpos), member); 1; }); \
+		pos = rcu_dereference(pos->next))
+
+#endif
+#endif
diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h
index 86f1f5e43e33..1168fbcea8d4 100644
--- a/include/linux/rcupdate.h
+++ b/include/linux/rcupdate.h
@@ -52,11 +52,15 @@ struct rcu_head {
 	void (*func)(struct rcu_head *head);
 };
 
-#ifdef CONFIG_CLASSIC_RCU
+#if defined(CONFIG_CLASSIC_RCU)
 #include <linux/rcuclassic.h>
-#else /* #ifdef CONFIG_CLASSIC_RCU */
+#elif defined(CONFIG_TREE_RCU)
+#include <linux/rcutree.h>
+#elif defined(CONFIG_PREEMPT_RCU)
 #include <linux/rcupreempt.h>
-#endif /* #else #ifdef CONFIG_CLASSIC_RCU */
+#else
+#error "Unknown RCU implementation specified to kernel configuration"
+#endif /* #else #if defined(CONFIG_CLASSIC_RCU) */
 
 #define RCU_HEAD_INIT 	{ .next = NULL, .func = NULL }
 #define RCU_HEAD(head) struct rcu_head head = RCU_HEAD_INIT
@@ -142,6 +146,7 @@ struct rcu_head {
  * on the write-side to insure proper synchronization.
  */
 #define rcu_read_lock_sched() preempt_disable()
+#define rcu_read_lock_sched_notrace() preempt_disable_notrace()
 
 /*
  * rcu_read_unlock_sched - marks the end of a RCU-classic critical section
@@ -149,6 +154,7 @@ struct rcu_head {
  * See rcu_read_lock_sched for more information.
  */
 #define rcu_read_unlock_sched() preempt_enable()
+#define rcu_read_unlock_sched_notrace() preempt_enable_notrace()
 
 
 
diff --git a/include/linux/rcutree.h b/include/linux/rcutree.h
new file mode 100644
index 000000000000..d4368b7975c3
--- /dev/null
+++ b/include/linux/rcutree.h
@@ -0,0 +1,329 @@
+/*
+ * Read-Copy Update mechanism for mutual exclusion (tree-based version)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright IBM Corporation, 2008
+ *
+ * Author: Dipankar Sarma <dipankar@in.ibm.com>
+ *	   Paul E. McKenney <paulmck@linux.vnet.ibm.com> Hierarchical algorithm
+ *
+ * Based on the original work by Paul McKenney <paulmck@us.ibm.com>
+ * and inputs from Rusty Russell, Andrea Arcangeli and Andi Kleen.
+ *
+ * For detailed explanation of Read-Copy Update mechanism see -
+ * 	Documentation/RCU
+ */
+
+#ifndef __LINUX_RCUTREE_H
+#define __LINUX_RCUTREE_H
+
+#include <linux/cache.h>
+#include <linux/spinlock.h>
+#include <linux/threads.h>
+#include <linux/percpu.h>
+#include <linux/cpumask.h>
+#include <linux/seqlock.h>
+
+/*
+ * Define shape of hierarchy based on NR_CPUS and CONFIG_RCU_FANOUT.
+ * In theory, it should be possible to add more levels straightforwardly.
+ * In practice, this has not been tested, so there is probably some
+ * bug somewhere.
+ */
+#define MAX_RCU_LVLS 3
+#define RCU_FANOUT	      (CONFIG_RCU_FANOUT)
+#define RCU_FANOUT_SQ	      (RCU_FANOUT * RCU_FANOUT)
+#define RCU_FANOUT_CUBE	      (RCU_FANOUT_SQ * RCU_FANOUT)
+
+#if NR_CPUS <= RCU_FANOUT
+#  define NUM_RCU_LVLS	      1
+#  define NUM_RCU_LVL_0	      1
+#  define NUM_RCU_LVL_1	      (NR_CPUS)
+#  define NUM_RCU_LVL_2	      0
+#  define NUM_RCU_LVL_3	      0
+#elif NR_CPUS <= RCU_FANOUT_SQ
+#  define NUM_RCU_LVLS	      2
+#  define NUM_RCU_LVL_0	      1
+#  define NUM_RCU_LVL_1	      (((NR_CPUS) + RCU_FANOUT - 1) / RCU_FANOUT)
+#  define NUM_RCU_LVL_2	      (NR_CPUS)
+#  define NUM_RCU_LVL_3	      0
+#elif NR_CPUS <= RCU_FANOUT_CUBE
+#  define NUM_RCU_LVLS	      3
+#  define NUM_RCU_LVL_0	      1
+#  define NUM_RCU_LVL_1	      (((NR_CPUS) + RCU_FANOUT_SQ - 1) / RCU_FANOUT_SQ)
+#  define NUM_RCU_LVL_2	      (((NR_CPUS) + (RCU_FANOUT) - 1) / (RCU_FANOUT))
+#  define NUM_RCU_LVL_3	      NR_CPUS
+#else
+# error "CONFIG_RCU_FANOUT insufficient for NR_CPUS"
+#endif /* #if (NR_CPUS) <= RCU_FANOUT */
+
+#define RCU_SUM (NUM_RCU_LVL_0 + NUM_RCU_LVL_1 + NUM_RCU_LVL_2 + NUM_RCU_LVL_3)
+#define NUM_RCU_NODES (RCU_SUM - NR_CPUS)
+
+/*
+ * Dynticks per-CPU state.
+ */
+struct rcu_dynticks {
+	int dynticks_nesting;	/* Track nesting level, sort of. */
+	int dynticks;		/* Even value for dynticks-idle, else odd. */
+	int dynticks_nmi;	/* Even value for either dynticks-idle or */
+				/*  not in nmi handler, else odd.  So this */
+				/*  remains even for nmi from irq handler. */
+};
+
+/*
+ * Definition for node within the RCU grace-period-detection hierarchy.
+ */
+struct rcu_node {
+	spinlock_t lock;
+	unsigned long qsmask;	/* CPUs or groups that need to switch in */
+				/*  order for current grace period to proceed.*/
+	unsigned long qsmaskinit;
+				/* Per-GP initialization for qsmask. */
+	unsigned long grpmask;	/* Mask to apply to parent qsmask. */
+	int	grplo;		/* lowest-numbered CPU or group here. */
+	int	grphi;		/* highest-numbered CPU or group here. */
+	u8	grpnum;		/* CPU/group number for next level up. */
+	u8	level;		/* root is at level 0. */
+	struct rcu_node *parent;
+} ____cacheline_internodealigned_in_smp;
+
+/* Index values for nxttail array in struct rcu_data. */
+#define RCU_DONE_TAIL		0	/* Also RCU_WAIT head. */
+#define RCU_WAIT_TAIL		1	/* Also RCU_NEXT_READY head. */
+#define RCU_NEXT_READY_TAIL	2	/* Also RCU_NEXT head. */
+#define RCU_NEXT_TAIL		3
+#define RCU_NEXT_SIZE		4
+
+/* Per-CPU data for read-copy update. */
+struct rcu_data {
+	/* 1) quiescent-state and grace-period handling : */
+	long		completed;	/* Track rsp->completed gp number */
+					/*  in order to detect GP end. */
+	long		gpnum;		/* Highest gp number that this CPU */
+					/*  is aware of having started. */
+	long		passed_quiesc_completed;
+					/* Value of completed at time of qs. */
+	bool		passed_quiesc;	/* User-mode/idle loop etc. */
+	bool		qs_pending;	/* Core waits for quiesc state. */
+	bool		beenonline;	/* CPU online at least once. */
+	struct rcu_node *mynode;	/* This CPU's leaf of hierarchy */
+	unsigned long grpmask;		/* Mask to apply to leaf qsmask. */
+
+	/* 2) batch handling */
+	/*
+	 * If nxtlist is not NULL, it is partitioned as follows.
+	 * Any of the partitions might be empty, in which case the
+	 * pointer to that partition will be equal to the pointer for
+	 * the following partition.  When the list is empty, all of
+	 * the nxttail elements point to nxtlist, which is NULL.
+	 *
+	 * [*nxttail[RCU_NEXT_READY_TAIL], NULL = *nxttail[RCU_NEXT_TAIL]):
+	 *	Entries that might have arrived after current GP ended
+	 * [*nxttail[RCU_WAIT_TAIL], *nxttail[RCU_NEXT_READY_TAIL]):
+	 *	Entries known to have arrived before current GP ended
+	 * [*nxttail[RCU_DONE_TAIL], *nxttail[RCU_WAIT_TAIL]):
+	 *	Entries that batch # <= ->completed - 1: waiting for current GP
+	 * [nxtlist, *nxttail[RCU_DONE_TAIL]):
+	 *	Entries that batch # <= ->completed
+	 *	The grace period for these entries has completed, and
+	 *	the other grace-period-completed entries may be moved
+	 *	here temporarily in rcu_process_callbacks().
+	 */
+	struct rcu_head *nxtlist;
+	struct rcu_head **nxttail[RCU_NEXT_SIZE];
+	long		qlen; 	 	/* # of queued callbacks */
+	long		blimit;		/* Upper limit on a processed batch */
+
+#ifdef CONFIG_NO_HZ
+	/* 3) dynticks interface. */
+	struct rcu_dynticks *dynticks;	/* Shared per-CPU dynticks state. */
+	int dynticks_snap;		/* Per-GP tracking for dynticks. */
+	int dynticks_nmi_snap;		/* Per-GP tracking for dynticks_nmi. */
+#endif /* #ifdef CONFIG_NO_HZ */
+
+	/* 4) reasons this CPU needed to be kicked by force_quiescent_state */
+#ifdef CONFIG_NO_HZ
+	unsigned long dynticks_fqs;	/* Kicked due to dynticks idle. */
+#endif /* #ifdef CONFIG_NO_HZ */
+	unsigned long offline_fqs;	/* Kicked due to being offline. */
+	unsigned long resched_ipi;	/* Sent a resched IPI. */
+
+	/* 5) state to allow this CPU to force_quiescent_state on others */
+	long n_rcu_pending;		/* rcu_pending() calls since boot. */
+	long n_rcu_pending_force_qs;	/* when to force quiescent states. */
+
+	int cpu;
+};
+
+/* Values for signaled field in struct rcu_state. */
+#define RCU_GP_INIT		0	/* Grace period being initialized. */
+#define RCU_SAVE_DYNTICK	1	/* Need to scan dyntick state. */
+#define RCU_FORCE_QS		2	/* Need to force quiescent state. */
+#ifdef CONFIG_NO_HZ
+#define RCU_SIGNAL_INIT		RCU_SAVE_DYNTICK
+#else /* #ifdef CONFIG_NO_HZ */
+#define RCU_SIGNAL_INIT		RCU_FORCE_QS
+#endif /* #else #ifdef CONFIG_NO_HZ */
+
+#define RCU_JIFFIES_TILL_FORCE_QS	 3	/* for rsp->jiffies_force_qs */
+#ifdef CONFIG_RCU_CPU_STALL_DETECTOR
+#define RCU_SECONDS_TILL_STALL_CHECK   (10 * HZ)  /* for rsp->jiffies_stall */
+#define RCU_SECONDS_TILL_STALL_RECHECK (30 * HZ)  /* for rsp->jiffies_stall */
+#define RCU_STALL_RAT_DELAY		2	  /* Allow other CPUs time */
+						  /*  to take at least one */
+						  /*  scheduling clock irq */
+						  /*  before ratting on them. */
+
+#endif /* #ifdef CONFIG_RCU_CPU_STALL_DETECTOR */
+
+/*
+ * RCU global state, including node hierarchy.  This hierarchy is
+ * represented in "heap" form in a dense array.  The root (first level)
+ * of the hierarchy is in ->node[0] (referenced by ->level[0]), the second
+ * level in ->node[1] through ->node[m] (->node[1] referenced by ->level[1]),
+ * and the third level in ->node[m+1] and following (->node[m+1] referenced
+ * by ->level[2]).  The number of levels is determined by the number of
+ * CPUs and by CONFIG_RCU_FANOUT.  Small systems will have a "hierarchy"
+ * consisting of a single rcu_node.
+ */
+struct rcu_state {
+	struct rcu_node node[NUM_RCU_NODES];	/* Hierarchy. */
+	struct rcu_node *level[NUM_RCU_LVLS];	/* Hierarchy levels. */
+	u32 levelcnt[MAX_RCU_LVLS + 1];		/* # nodes in each level. */
+	u8 levelspread[NUM_RCU_LVLS];		/* kids/node in each level. */
+	struct rcu_data *rda[NR_CPUS];		/* array of rdp pointers. */
+
+	/* The following fields are guarded by the root rcu_node's lock. */
+
+	u8	signaled ____cacheline_internodealigned_in_smp;
+						/* Force QS state. */
+	long	gpnum;				/* Current gp number. */
+	long	completed;			/* # of last completed gp. */
+	spinlock_t onofflock;			/* exclude on/offline and */
+						/*  starting new GP. */
+	spinlock_t fqslock;			/* Only one task forcing */
+						/*  quiescent states. */
+	unsigned long jiffies_force_qs;		/* Time at which to invoke */
+						/*  force_quiescent_state(). */
+	unsigned long n_force_qs;		/* Number of calls to */
+						/*  force_quiescent_state(). */
+	unsigned long n_force_qs_lh;		/* ~Number of calls leaving */
+						/*  due to lock unavailable. */
+	unsigned long n_force_qs_ngp;		/* Number of calls leaving */
+						/*  due to no GP active. */
+#ifdef CONFIG_RCU_CPU_STALL_DETECTOR
+	unsigned long gp_start;			/* Time at which GP started, */
+						/*  but in jiffies. */
+	unsigned long jiffies_stall;		/* Time at which to check */
+						/*  for CPU stalls. */
+#endif /* #ifdef CONFIG_RCU_CPU_STALL_DETECTOR */
+#ifdef CONFIG_NO_HZ
+	long dynticks_completed;		/* Value of completed @ snap. */
+#endif /* #ifdef CONFIG_NO_HZ */
+};
+
+extern struct rcu_state rcu_state;
+DECLARE_PER_CPU(struct rcu_data, rcu_data);
+
+extern struct rcu_state rcu_bh_state;
+DECLARE_PER_CPU(struct rcu_data, rcu_bh_data);
+
+/*
+ * Increment the quiescent state counter.
+ * The counter is a bit degenerated: We do not need to know
+ * how many quiescent states passed, just if there was at least
+ * one since the start of the grace period. Thus just a flag.
+ */
+static inline void rcu_qsctr_inc(int cpu)
+{
+	struct rcu_data *rdp = &per_cpu(rcu_data, cpu);
+	rdp->passed_quiesc = 1;
+	rdp->passed_quiesc_completed = rdp->completed;
+}
+static inline void rcu_bh_qsctr_inc(int cpu)
+{
+	struct rcu_data *rdp = &per_cpu(rcu_bh_data, cpu);
+	rdp->passed_quiesc = 1;
+	rdp->passed_quiesc_completed = rdp->completed;
+}
+
+extern int rcu_pending(int cpu);
+extern int rcu_needs_cpu(int cpu);
+
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+extern struct lockdep_map rcu_lock_map;
+# define rcu_read_acquire()	\
+			lock_acquire(&rcu_lock_map, 0, 0, 2, 1, NULL, _THIS_IP_)
+# define rcu_read_release()	lock_release(&rcu_lock_map, 1, _THIS_IP_)
+#else
+# define rcu_read_acquire()	do { } while (0)
+# define rcu_read_release()	do { } while (0)
+#endif
+
+static inline void __rcu_read_lock(void)
+{
+	preempt_disable();
+	__acquire(RCU);
+	rcu_read_acquire();
+}
+static inline void __rcu_read_unlock(void)
+{
+	rcu_read_release();
+	__release(RCU);
+	preempt_enable();
+}
+static inline void __rcu_read_lock_bh(void)
+{
+	local_bh_disable();
+	__acquire(RCU_BH);
+	rcu_read_acquire();
+}
+static inline void __rcu_read_unlock_bh(void)
+{
+	rcu_read_release();
+	__release(RCU_BH);
+	local_bh_enable();
+}
+
+#define __synchronize_sched() synchronize_rcu()
+
+#define call_rcu_sched(head, func) call_rcu(head, func)
+
+static inline void rcu_init_sched(void)
+{
+}
+
+extern void __rcu_init(void);
+extern void rcu_check_callbacks(int cpu, int user);
+extern void rcu_restart_cpu(int cpu);
+
+extern long rcu_batches_completed(void);
+extern long rcu_batches_completed_bh(void);
+
+#ifdef CONFIG_NO_HZ
+void rcu_enter_nohz(void);
+void rcu_exit_nohz(void);
+#else /* CONFIG_NO_HZ */
+static inline void rcu_enter_nohz(void)
+{
+}
+static inline void rcu_exit_nohz(void)
+{
+}
+#endif /* CONFIG_NO_HZ */
+
+#endif /* __LINUX_RCUTREE_H */
diff --git a/include/linux/reiserfs_fs.h b/include/linux/reiserfs_fs.h
index e9963af16cda..bc5114d35e99 100644
--- a/include/linux/reiserfs_fs.h
+++ b/include/linux/reiserfs_fs.h
@@ -87,7 +87,7 @@ void reiserfs_warning(struct super_block *s, const char *fmt, ...);
 if( !( cond ) ) 								\
   reiserfs_panic( NULL, "reiserfs[%i]: assertion " scond " failed at "	\
 		  __FILE__ ":%i:%s: " format "\n",		\
-		  in_interrupt() ? -1 : task_pid_nr(current), __LINE__ , __FUNCTION__ , ##args )
+		  in_interrupt() ? -1 : task_pid_nr(current), __LINE__ , __func__ , ##args )
 
 #define RASSERT(cond, format, args...) __RASSERT(cond, #cond, format, ##args)
 
diff --git a/include/linux/reiserfs_fs_sb.h b/include/linux/reiserfs_fs_sb.h
index 315517e8bfa1..bda6b562a1e0 100644
--- a/include/linux/reiserfs_fs_sb.h
+++ b/include/linux/reiserfs_fs_sb.h
@@ -178,6 +178,7 @@ struct reiserfs_journal {
 	struct reiserfs_journal_cnode *j_first;	/*  oldest journal block.  start here for traverse */
 
 	struct block_device *j_dev_bd;
+	fmode_t j_dev_mode;
 	int j_1st_reserved_block;	/* first block on s_dev of reserved area journal */
 
 	unsigned long j_state;
diff --git a/include/linux/resource.h b/include/linux/resource.h
index aaa423a6f3d9..40fc7e626082 100644
--- a/include/linux/resource.h
+++ b/include/linux/resource.h
@@ -59,10 +59,10 @@ struct rlimit {
 #define _STK_LIM	(8*1024*1024)
 
 /*
- * GPG wants 32kB of mlocked memory, to make sure pass phrases
+ * GPG2 wants 64kB of mlocked memory, to make sure pass phrases
  * and other sensitive information are never written to disk.
  */
-#define MLOCK_LIMIT	(8 * PAGE_SIZE)
+#define MLOCK_LIMIT	((PAGE_SIZE > 64*1024) ? PAGE_SIZE : 64*1024)
 
 /*
  * Due to binary compatibility, the actual resource numbers
diff --git a/include/linux/rfkill.h b/include/linux/rfkill.h
index 4cd64b0d9825..164332cbb77c 100644
--- a/include/linux/rfkill.h
+++ b/include/linux/rfkill.h
@@ -108,6 +108,7 @@ struct rfkill {
 
 	struct device dev;
 	struct list_head node;
+	enum rfkill_state state_for_resume;
 };
 #define to_rfkill(d)	container_of(d, struct rfkill, dev)
 
@@ -148,11 +149,4 @@ static inline char *rfkill_get_led_name(struct rfkill *rfkill)
 #endif
 }
 
-/* rfkill notification chain */
-#define RFKILL_STATE_CHANGED		0x0001	/* state of a normal rfkill
-						   switch has changed */
-
-int register_rfkill_notifier(struct notifier_block *nb);
-int unregister_rfkill_notifier(struct notifier_block *nb);
-
 #endif /* RFKILL_H */
diff --git a/include/linux/ring_buffer.h b/include/linux/ring_buffer.h
new file mode 100644
index 000000000000..b3b359660082
--- /dev/null
+++ b/include/linux/ring_buffer.h
@@ -0,0 +1,140 @@
+#ifndef _LINUX_RING_BUFFER_H
+#define _LINUX_RING_BUFFER_H
+
+#include <linux/mm.h>
+#include <linux/seq_file.h>
+
+struct ring_buffer;
+struct ring_buffer_iter;
+
+/*
+ * Don't reference this struct directly, use functions below.
+ */
+struct ring_buffer_event {
+	u32		type:2, len:3, time_delta:27;
+	u32		array[];
+};
+
+/**
+ * enum ring_buffer_type - internal ring buffer types
+ *
+ * @RINGBUF_TYPE_PADDING:	Left over page padding
+ *				 array is ignored
+ *				 size is variable depending on how much
+ *				  padding is needed
+ *
+ * @RINGBUF_TYPE_TIME_EXTEND:	Extend the time delta
+ *				 array[0] = time delta (28 .. 59)
+ *				 size = 8 bytes
+ *
+ * @RINGBUF_TYPE_TIME_STAMP:	Sync time stamp with external clock
+ *				 array[0]    = tv_nsec
+ *				 array[1..2] = tv_sec
+ *				 size = 16 bytes
+ *
+ * @RINGBUF_TYPE_DATA:		Data record
+ *				 If len is zero:
+ *				  array[0] holds the actual length
+ *				  array[1..(length+3)/4] holds data
+ *				  size = 4 + 4 + length (bytes)
+ *				 else
+ *				  length = len << 2
+ *				  array[0..(length+3)/4-1] holds data
+ *				  size = 4 + length (bytes)
+ */
+enum ring_buffer_type {
+	RINGBUF_TYPE_PADDING,
+	RINGBUF_TYPE_TIME_EXTEND,
+	/* FIXME: RINGBUF_TYPE_TIME_STAMP not implemented */
+	RINGBUF_TYPE_TIME_STAMP,
+	RINGBUF_TYPE_DATA,
+};
+
+unsigned ring_buffer_event_length(struct ring_buffer_event *event);
+void *ring_buffer_event_data(struct ring_buffer_event *event);
+
+/**
+ * ring_buffer_event_time_delta - return the delta timestamp of the event
+ * @event: the event to get the delta timestamp of
+ *
+ * The delta timestamp is the 27 bit timestamp since the last event.
+ */
+static inline unsigned
+ring_buffer_event_time_delta(struct ring_buffer_event *event)
+{
+	return event->time_delta;
+}
+
+/*
+ * size is in bytes for each per CPU buffer.
+ */
+struct ring_buffer *
+ring_buffer_alloc(unsigned long size, unsigned flags);
+void ring_buffer_free(struct ring_buffer *buffer);
+
+int ring_buffer_resize(struct ring_buffer *buffer, unsigned long size);
+
+struct ring_buffer_event *
+ring_buffer_lock_reserve(struct ring_buffer *buffer,
+			 unsigned long length,
+			 unsigned long *flags);
+int ring_buffer_unlock_commit(struct ring_buffer *buffer,
+			      struct ring_buffer_event *event,
+			      unsigned long flags);
+int ring_buffer_write(struct ring_buffer *buffer,
+		      unsigned long length, void *data);
+
+struct ring_buffer_event *
+ring_buffer_peek(struct ring_buffer *buffer, int cpu, u64 *ts);
+struct ring_buffer_event *
+ring_buffer_consume(struct ring_buffer *buffer, int cpu, u64 *ts);
+
+struct ring_buffer_iter *
+ring_buffer_read_start(struct ring_buffer *buffer, int cpu);
+void ring_buffer_read_finish(struct ring_buffer_iter *iter);
+
+struct ring_buffer_event *
+ring_buffer_iter_peek(struct ring_buffer_iter *iter, u64 *ts);
+struct ring_buffer_event *
+ring_buffer_read(struct ring_buffer_iter *iter, u64 *ts);
+void ring_buffer_iter_reset(struct ring_buffer_iter *iter);
+int ring_buffer_iter_empty(struct ring_buffer_iter *iter);
+
+unsigned long ring_buffer_size(struct ring_buffer *buffer);
+
+void ring_buffer_reset_cpu(struct ring_buffer *buffer, int cpu);
+void ring_buffer_reset(struct ring_buffer *buffer);
+
+int ring_buffer_swap_cpu(struct ring_buffer *buffer_a,
+			 struct ring_buffer *buffer_b, int cpu);
+
+int ring_buffer_empty(struct ring_buffer *buffer);
+int ring_buffer_empty_cpu(struct ring_buffer *buffer, int cpu);
+
+void ring_buffer_record_disable(struct ring_buffer *buffer);
+void ring_buffer_record_enable(struct ring_buffer *buffer);
+void ring_buffer_record_disable_cpu(struct ring_buffer *buffer, int cpu);
+void ring_buffer_record_enable_cpu(struct ring_buffer *buffer, int cpu);
+
+unsigned long ring_buffer_entries(struct ring_buffer *buffer);
+unsigned long ring_buffer_overruns(struct ring_buffer *buffer);
+unsigned long ring_buffer_entries_cpu(struct ring_buffer *buffer, int cpu);
+unsigned long ring_buffer_overrun_cpu(struct ring_buffer *buffer, int cpu);
+
+u64 ring_buffer_time_stamp(int cpu);
+void ring_buffer_normalize_time_stamp(int cpu, u64 *ts);
+
+void tracing_on(void);
+void tracing_off(void);
+void tracing_off_permanent(void);
+
+void *ring_buffer_alloc_read_page(struct ring_buffer *buffer);
+void ring_buffer_free_read_page(struct ring_buffer *buffer, void *data);
+int ring_buffer_read_page(struct ring_buffer *buffer,
+			  void **data_page, int cpu, int full);
+
+enum ring_buffer_flags {
+	RB_FL_OVERWRITE		= 1 << 0,
+};
+
+#endif /* _LINUX_RING_BUFFER_H */
diff --git a/include/linux/rio_drv.h b/include/linux/rio_drv.h
index 90987b7bcc1b..32c0547ffafc 100644
--- a/include/linux/rio_drv.h
+++ b/include/linux/rio_drv.h
@@ -427,9 +427,9 @@ void rio_dev_put(struct rio_dev *);
  * Get the unique RIO device identifier. Returns the device
  * identifier string.
  */
-static inline char *rio_name(struct rio_dev *rdev)
+static inline const char *rio_name(struct rio_dev *rdev)
 {
-	return rdev->dev.bus_id;
+	return dev_name(&rdev->dev);
 }
 
 /**
diff --git a/include/linux/rmap.h b/include/linux/rmap.h
index fed6f5e0b411..89f0564b10c8 100644
--- a/include/linux/rmap.h
+++ b/include/linux/rmap.h
@@ -39,18 +39,6 @@ struct anon_vma {
 
 #ifdef CONFIG_MMU
 
-extern struct kmem_cache *anon_vma_cachep;
-
-static inline struct anon_vma *anon_vma_alloc(void)
-{
-	return kmem_cache_alloc(anon_vma_cachep, GFP_KERNEL);
-}
-
-static inline void anon_vma_free(struct anon_vma *anon_vma)
-{
-	kmem_cache_free(anon_vma_cachep, anon_vma);
-}
-
 static inline void anon_vma_lock(struct vm_area_struct *vma)
 {
 	struct anon_vma *anon_vma = vma->anon_vma;
@@ -75,6 +63,9 @@ void anon_vma_unlink(struct vm_area_struct *);
 void anon_vma_link(struct vm_area_struct *);
 void __anon_vma_link(struct vm_area_struct *);
 
+extern struct anon_vma *page_lock_anon_vma(struct page *page);
+extern void page_unlock_anon_vma(struct anon_vma *anon_vma);
+
 /*
  * rmap interfaces called when adding or removing pte of page
  */
@@ -117,6 +108,19 @@ unsigned long page_address_in_vma(struct page *, struct vm_area_struct *);
  */
 int page_mkclean(struct page *);
 
+#ifdef CONFIG_UNEVICTABLE_LRU
+/*
+ * called in munlock()/munmap() path to check for other vmas holding
+ * the page mlocked.
+ */
+int try_to_munlock(struct page *);
+#else
+static inline int try_to_munlock(struct page *page)
+{
+	return 0;	/* a.k.a. SWAP_SUCCESS */
+}
+#endif
+
 #else	/* !CONFIG_MMU */
 
 #define anon_vma_init()		do {} while (0)
@@ -140,5 +144,6 @@ static inline int page_mkclean(struct page *page)
 #define SWAP_SUCCESS	0
 #define SWAP_AGAIN	1
 #define SWAP_FAIL	2
+#define SWAP_MLOCK	3
 
 #endif	/* _LINUX_RMAP_H */
diff --git a/include/linux/rtmutex.h b/include/linux/rtmutex.h
index 382bb7951166..f19b00b7d530 100644
--- a/include/linux/rtmutex.h
+++ b/include/linux/rtmutex.h
@@ -54,7 +54,7 @@ struct hrtimer_sleeper;
 #ifdef CONFIG_DEBUG_RT_MUTEXES
 # define __DEBUG_RT_MUTEX_INITIALIZER(mutexname) \
 	, .name = #mutexname, .file = __FILE__, .line = __LINE__
-# define rt_mutex_init(mutex)			__rt_mutex_init(mutex, __FUNCTION__)
+# define rt_mutex_init(mutex)			__rt_mutex_init(mutex, __func__)
  extern void rt_mutex_debug_task_free(struct task_struct *tsk);
 #else
 # define __DEBUG_RT_MUTEX_INITIALIZER(mutexname)
diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h
index 2b3d51c6ec9c..e88f7058b3a1 100644
--- a/include/linux/rtnetlink.h
+++ b/include/linux/rtnetlink.h
@@ -107,6 +107,11 @@ enum {
 	RTM_GETADDRLABEL,
 #define RTM_GETADDRLABEL RTM_GETADDRLABEL
 
+	RTM_GETDCB = 78,
+#define RTM_GETDCB RTM_GETDCB
+	RTM_SETDCB,
+#define RTM_SETDCB RTM_SETDCB
+
 	__RTM_MAX,
 #define RTM_MAX		(((__RTM_MAX + 3) & ~3) - 1)
 };
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 1a7e8461db5a..bd5ff78798c2 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -96,6 +96,7 @@ struct exec_domain;
 struct futex_pi_state;
 struct robust_list_head;
 struct bio;
+struct bts_tracer;
 
 /*
  * List of flags we want to share for kernel threads,
@@ -247,6 +248,7 @@ extern void init_idle(struct task_struct *idle, int cpu);
 extern void init_idle_bootup_task(struct task_struct *idle);
 
 extern int runqueue_is_locked(void);
+extern void task_rq_unlock_wait(struct task_struct *p);
 
 extern cpumask_t nohz_cpu_mask;
 #if defined(CONFIG_SMP) && defined(CONFIG_NO_HZ)
@@ -258,8 +260,6 @@ static inline int select_nohz_load_balancer(int cpu)
 }
 #endif
 
-extern unsigned long rt_needs_cpu(int cpu);
-
 /*
  * Only dump TASK_* tasks. (0 for all tasks)
  */
@@ -287,7 +287,6 @@ extern void trap_init(void);
 extern void account_process_tick(struct task_struct *task, int user);
 extern void update_process_times(int user);
 extern void scheduler_tick(void);
-extern void hrtick_resched(void);
 
 extern void sched_show_task(struct task_struct *p);
 
@@ -403,12 +402,21 @@ extern int get_dumpable(struct mm_struct *mm);
 #define MMF_DUMP_MAPPED_PRIVATE	4
 #define MMF_DUMP_MAPPED_SHARED	5
 #define MMF_DUMP_ELF_HEADERS	6
+#define MMF_DUMP_HUGETLB_PRIVATE 7
+#define MMF_DUMP_HUGETLB_SHARED  8
 #define MMF_DUMP_FILTER_SHIFT	MMF_DUMPABLE_BITS
-#define MMF_DUMP_FILTER_BITS	5
+#define MMF_DUMP_FILTER_BITS	7
 #define MMF_DUMP_FILTER_MASK \
 	(((1 << MMF_DUMP_FILTER_BITS) - 1) << MMF_DUMP_FILTER_SHIFT)
 #define MMF_DUMP_FILTER_DEFAULT \
-	((1 << MMF_DUMP_ANON_PRIVATE) |	(1 << MMF_DUMP_ANON_SHARED))
+	((1 << MMF_DUMP_ANON_PRIVATE) |	(1 << MMF_DUMP_ANON_SHARED) |\
+	 (1 << MMF_DUMP_HUGETLB_PRIVATE) | MMF_DUMP_MASK_DEFAULT_ELF)
+
+#ifdef CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS
+# define MMF_DUMP_MASK_DEFAULT_ELF	(1 << MMF_DUMP_ELF_HEADERS)
+#else
+# define MMF_DUMP_MASK_DEFAULT_ELF	0
+#endif
 
 struct sighand_struct {
 	atomic_t		count;
@@ -425,6 +433,39 @@ struct pacct_struct {
 	unsigned long		ac_minflt, ac_majflt;
 };
 
+/**
+ * struct task_cputime - collected CPU time counts
+ * @utime:		time spent in user mode, in &cputime_t units
+ * @stime:		time spent in kernel mode, in &cputime_t units
+ * @sum_exec_runtime:	total time spent on the CPU, in nanoseconds
+ *
+ * This structure groups together three kinds of CPU time that are
+ * tracked for threads and thread groups.  Most things considering
+ * CPU time want to group these counts together and treat all three
+ * of them in parallel.
+ */
+struct task_cputime {
+	cputime_t utime;
+	cputime_t stime;
+	unsigned long long sum_exec_runtime;
+};
+/* Alternate field names when used to cache expirations. */
+#define prof_exp	stime
+#define virt_exp	utime
+#define sched_exp	sum_exec_runtime
+
+/**
+ * struct thread_group_cputime - thread group interval timer counts
+ * @totals:		thread group interval timers; substructure for
+ *			uniprocessor kernel, per-cpu for SMP kernel.
+ *
+ * This structure contains the version of task_cputime, above, that is
+ * used for thread group CPU clock calculations.
+ */
+struct thread_group_cputime {
+	struct task_cputime *totals;
+};
+
 /*
  * NOTE! "signal_struct" does not have it's own
  * locking, because a shared signal_struct always
@@ -470,6 +511,17 @@ struct signal_struct {
 	cputime_t it_prof_expires, it_virt_expires;
 	cputime_t it_prof_incr, it_virt_incr;
 
+	/*
+	 * Thread group totals for process CPU clocks.
+	 * See thread_group_cputime(), et al, for details.
+	 */
+	struct thread_group_cputime cputime;
+
+	/* Earliest-expiration cache. */
+	struct task_cputime cputime_expires;
+
+	struct list_head cpu_timers[3];
+
 	/* job control IDs */
 
 	/*
@@ -500,7 +552,7 @@ struct signal_struct {
 	 * Live threads maintain their own counters and add to these
 	 * in __exit_signal, except for the group leader.
 	 */
-	cputime_t utime, stime, cutime, cstime;
+	cputime_t cutime, cstime;
 	cputime_t gtime;
 	cputime_t cgtime;
 	unsigned long nvcsw, nivcsw, cnvcsw, cnivcsw;
@@ -509,14 +561,6 @@ struct signal_struct {
 	struct task_io_accounting ioac;
 
 	/*
-	 * Cumulative ns of scheduled CPU time for dead threads in the
-	 * group, not including a zombie group leader.  (This only differs
-	 * from jiffies_to_ns(utime + stime) if sched_clock uses something
-	 * other than jiffies.)
-	 */
-	unsigned long long sum_sched_runtime;
-
-	/*
 	 * We don't bother to synchronize most readers of this at all,
 	 * because there is no reader checking a limit that actually needs
 	 * to get both rlim_cur and rlim_max atomically, and either one
@@ -527,14 +571,6 @@ struct signal_struct {
 	 */
 	struct rlimit rlim[RLIM_NLIMITS];
 
-	struct list_head cpu_timers[3];
-
-	/* keep the process-shared keyrings here so that they do the right
-	 * thing in threads created with CLONE_THREAD */
-#ifdef CONFIG_KEYS
-	struct key *session_keyring;	/* keyring inherited over fork */
-	struct key *process_keyring;	/* keyring private to this process */
-#endif
 #ifdef CONFIG_BSD_PROCESS_ACCT
 	struct pacct_struct pacct;	/* per-process accounting information */
 #endif
@@ -587,6 +623,10 @@ struct user_struct {
 	atomic_t inotify_watches; /* How many inotify watches does this user have? */
 	atomic_t inotify_devs;	/* How many inotify devs does this user have opened? */
 #endif
+#ifdef CONFIG_EPOLL
+	atomic_t epoll_devs;	/* The number of epoll descriptors currently open */
+	atomic_t epoll_watches;	/* The number of file descriptors currently watched */
+#endif
 #ifdef CONFIG_POSIX_MQUEUE
 	/* protected by mq_lock	*/
 	unsigned long mq_bytes;	/* How many bytes can be allocated to mqueue? */
@@ -601,6 +641,7 @@ struct user_struct {
 	/* Hash table maintenance information */
 	struct hlist_node uidhash_node;
 	uid_t uid;
+	struct user_namespace *user_ns;
 
 #ifdef CONFIG_USER_SCHED
 	struct task_group *tg;
@@ -618,6 +659,7 @@ extern struct user_struct *find_user(uid_t);
 extern struct user_struct root_user;
 #define INIT_USER (&root_user)
 
+
 struct backing_dev_info;
 struct reclaim_state;
 
@@ -625,8 +667,7 @@ struct reclaim_state;
 struct sched_info {
 	/* cumulative counters */
 	unsigned long pcount;	      /* # of times run on this cpu */
-	unsigned long long cpu_time,  /* time spent on the cpu */
-			   run_delay; /* time spent waiting on a runqueue */
+	unsigned long long run_delay; /* time spent waiting on a runqueue */
 
 	/* timestamps */
 	unsigned long long last_arrival,/* when we last ran on a cpu */
@@ -638,10 +679,6 @@ struct sched_info {
 };
 #endif /* defined(CONFIG_SCHEDSTATS) || defined(CONFIG_TASK_DELAY_ACCT) */
 
-#ifdef CONFIG_SCHEDSTATS
-extern const struct file_operations proc_schedstat_operations;
-#endif /* CONFIG_SCHEDSTATS */
-
 #ifdef CONFIG_TASK_DELAY_ACCT
 struct task_delay_info {
 	spinlock_t	lock;
@@ -845,38 +882,7 @@ partition_sched_domains(int ndoms_new, cpumask_t *doms_new,
 #endif	/* !CONFIG_SMP */
 
 struct io_context;			/* See blkdev.h */
-#define NGROUPS_SMALL		32
-#define NGROUPS_PER_BLOCK	((unsigned int)(PAGE_SIZE / sizeof(gid_t)))
-struct group_info {
-	int ngroups;
-	atomic_t usage;
-	gid_t small_block[NGROUPS_SMALL];
-	int nblocks;
-	gid_t *blocks[0];
-};
-
-/*
- * get_group_info() must be called with the owning task locked (via task_lock())
- * when task != current.  The reason being that the vast majority of callers are
- * looking at current->group_info, which can not be changed except by the
- * current task.  Changing current->group_info requires the task lock, too.
- */
-#define get_group_info(group_info) do { \
-	atomic_inc(&(group_info)->usage); \
-} while (0)
 
-#define put_group_info(group_info) do { \
-	if (atomic_dec_and_test(&(group_info)->usage)) \
-		groups_free(group_info); \
-} while (0)
-
-extern struct group_info *groups_alloc(int gidsetsize);
-extern void groups_free(struct group_info *group_info);
-extern int set_current_groups(struct group_info *group_info);
-extern int groups_search(struct group_info *group_info, gid_t grp);
-/* access the groups "array" with this macro */
-#define GROUP_AT(gi, i) \
-    ((gi)->blocks[(i)/NGROUPS_PER_BLOCK][(i)%NGROUPS_PER_BLOCK])
 
 #ifdef ARCH_HAS_PREFETCH_SWITCH_STACK
 extern void prefetch_stack(struct task_struct *t);
@@ -898,7 +904,6 @@ struct sched_class {
 	void (*enqueue_task) (struct rq *rq, struct task_struct *p, int wakeup);
 	void (*dequeue_task) (struct rq *rq, struct task_struct *p, int sleep);
 	void (*yield_task) (struct rq *rq);
-	int  (*select_task_rq)(struct task_struct *p, int sync);
 
 	void (*check_preempt_curr) (struct rq *rq, struct task_struct *p, int sync);
 
@@ -906,6 +911,8 @@ struct sched_class {
 	void (*put_prev_task) (struct rq *rq, struct task_struct *p);
 
 #ifdef CONFIG_SMP
+	int  (*select_task_rq)(struct task_struct *p, int sync);
+
 	unsigned long (*load_balance) (struct rq *this_rq, int this_cpu,
 			struct rq *busiest, unsigned long max_load_move,
 			struct sched_domain *sd, enum cpu_idle_type idle,
@@ -917,16 +924,17 @@ struct sched_class {
 	void (*pre_schedule) (struct rq *this_rq, struct task_struct *task);
 	void (*post_schedule) (struct rq *this_rq);
 	void (*task_wake_up) (struct rq *this_rq, struct task_struct *task);
-#endif
 
-	void (*set_curr_task) (struct rq *rq);
-	void (*task_tick) (struct rq *rq, struct task_struct *p, int queued);
-	void (*task_new) (struct rq *rq, struct task_struct *p);
 	void (*set_cpus_allowed)(struct task_struct *p,
 				 const cpumask_t *newmask);
 
 	void (*rq_online)(struct rq *rq);
 	void (*rq_offline)(struct rq *rq);
+#endif
+
+	void (*set_curr_task) (struct rq *rq);
+	void (*task_tick) (struct rq *rq, struct task_struct *p, int queued);
+	void (*task_new) (struct rq *rq, struct task_struct *p);
 
 	void (*switched_from) (struct rq *this_rq, struct task_struct *task,
 			       int running);
@@ -1119,6 +1127,19 @@ struct task_struct {
 	struct list_head ptraced;
 	struct list_head ptrace_entry;
 
+#ifdef CONFIG_X86_PTRACE_BTS
+	/*
+	 * This is the tracer handle for the ptrace BTS extension.
+	 * This field actually belongs to the ptracer task.
+	 */
+	struct bts_tracer *bts;
+	/*
+	 * The buffer to hold the BTS data.
+	 */
+	void *bts_buffer;
+	size_t bts_size;
+#endif /* CONFIG_X86_PTRACE_BTS */
+
 	/* PID/PID hash table linkage. */
 	struct pid_link pids[PIDTYPE_MAX];
 	struct list_head thread_group;
@@ -1136,22 +1157,16 @@ struct task_struct {
 /* mm fault and swap info: this can arguably be seen as either mm-specific or thread-specific */
 	unsigned long min_flt, maj_flt;
 
-  	cputime_t it_prof_expires, it_virt_expires;
-	unsigned long long it_sched_expires;
+	struct task_cputime cputime_expires;
 	struct list_head cpu_timers[3];
 
 /* process credentials */
-	uid_t uid,euid,suid,fsuid;
-	gid_t gid,egid,sgid,fsgid;
-	struct group_info *group_info;
-	kernel_cap_t   cap_effective, cap_inheritable, cap_permitted, cap_bset;
-	struct user_struct *user;
-	unsigned securebits;
-#ifdef CONFIG_KEYS
-	unsigned char jit_keyring;	/* default keyring to attach requested keys to */
-	struct key *request_key_auth;	/* assumed request_key authority */
-	struct key *thread_keyring;	/* keyring private to this thread */
-#endif
+	const struct cred *real_cred;	/* objective and real subjective task
+					 * credentials (COW) */
+	const struct cred *cred;	/* effective (overridable) subjective task
+					 * credentials (COW) */
+	struct mutex cred_exec_mutex;	/* execve vs ptrace cred calculation mutex */
+
 	char comm[TASK_COMM_LEN]; /* executable name excluding path
 				     - access with [gs]et_task_comm (which lock
 				       it with task_lock())
@@ -1188,9 +1203,6 @@ struct task_struct {
 	int (*notifier)(void *priv);
 	void *notifier_data;
 	sigset_t *notifier_mask;
-#ifdef CONFIG_SECURITY
-	void *security;
-#endif
 	struct audit_context *audit_context;
 #ifdef CONFIG_AUDITSYSCALL
 	uid_t loginuid;
@@ -1303,6 +1315,31 @@ struct task_struct {
 	int latency_record_count;
 	struct latency_record latency_record[LT_SAVECOUNT];
 #endif
+	/*
+	 * time slack values; these are used to round up poll() and
+	 * select() etc timeout values. These are in nanoseconds.
+	 */
+	unsigned long timer_slack_ns;
+	unsigned long default_timer_slack_ns;
+
+	struct list_head	*scm_work_list;
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+	/* Index of current stored adress in ret_stack */
+	int curr_ret_stack;
+	/* Stack of return addresses for return function tracing */
+	struct ftrace_ret_stack	*ret_stack;
+	/*
+	 * Number of functions that haven't been traced
+	 * because of depth overrun.
+	 */
+	atomic_t trace_overrun;
+	/* Pause for the tracing */
+	atomic_t tracing_graph_pause;
+#endif
+#ifdef CONFIG_TRACING
+	/* state flags for use by tracers */
+	unsigned long trace;
+#endif
 };
 
 /*
@@ -1587,6 +1624,7 @@ extern unsigned long long cpu_clock(int cpu);
 
 extern unsigned long long
 task_sched_runtime(struct task_struct *task);
+extern unsigned long long thread_group_sched_runtime(struct task_struct *task);
 
 /* sched_exec is called by processes performing an exec */
 #ifdef CONFIG_SMP
@@ -1621,6 +1659,7 @@ extern unsigned int sysctl_sched_features;
 extern unsigned int sysctl_sched_migration_cost;
 extern unsigned int sysctl_sched_nr_migrate;
 extern unsigned int sysctl_sched_shares_ratelimit;
+extern unsigned int sysctl_sched_shares_thresh;
 
 int sched_nr_latency_handler(struct ctl_table *table, int write,
 		struct file *file, void __user *buffer, size_t *length,
@@ -1720,7 +1759,6 @@ static inline struct user_struct *get_uid(struct user_struct *u)
 	return u;
 }
 extern void free_uid(struct user_struct *);
-extern void switch_uid(struct user_struct *);
 extern void release_uids(struct user_namespace *ns);
 
 #include <asm/current.h>
@@ -1739,9 +1777,6 @@ extern void wake_up_new_task(struct task_struct *tsk,
 extern void sched_fork(struct task_struct *p, int clone_flags);
 extern void sched_dead(struct task_struct *p);
 
-extern int in_group_p(gid_t);
-extern int in_egroup_p(gid_t);
-
 extern void proc_caches_init(void);
 extern void flush_signals(struct task_struct *);
 extern void ignore_signals(struct task_struct *);
@@ -1873,6 +1908,8 @@ static inline unsigned long wait_task_inactive(struct task_struct *p,
 #define for_each_process(p) \
 	for (p = &init_task ; (p = next_task(p)) != &init_task ; )
 
+extern bool is_single_threaded(struct task_struct *);
+
 /*
  * Careful: do_each_thread/while_each_thread is a double loop so
  *          'break' will not work as expected - use goto instead.
@@ -2097,6 +2134,30 @@ static inline int spin_needbreak(spinlock_t *lock)
 }
 
 /*
+ * Thread group CPU time accounting.
+ */
+
+extern int thread_group_cputime_alloc(struct task_struct *);
+extern void thread_group_cputime(struct task_struct *, struct task_cputime *);
+
+static inline void thread_group_cputime_init(struct signal_struct *sig)
+{
+	sig->cputime.totals = NULL;
+}
+
+static inline int thread_group_cputime_clone_thread(struct task_struct *curr)
+{
+	if (curr->signal->cputime.totals)
+		return 0;
+	return thread_group_cputime_alloc(curr);
+}
+
+static inline void thread_group_cputime_free(struct signal_struct *sig)
+{
+	free_percpu(sig->cputime.totals);
+}
+
+/*
  * Reevaluate whether the task has signals pending delivery.
  * Wake the task if so.
  * This is required every time the blocked sigset_t changes.
@@ -2158,6 +2219,7 @@ extern void normalize_rt_tasks(void);
 extern struct task_group init_task_group;
 #ifdef CONFIG_USER_SCHED
 extern struct task_group root_task_group;
+extern void set_tg_uid(struct user_struct *user);
 #endif
 
 extern struct task_group *sched_create_group(struct task_group *parent);
diff --git a/include/linux/securebits.h b/include/linux/securebits.h
index 92f09bdf1175..d2c5ed845bcc 100644
--- a/include/linux/securebits.h
+++ b/include/linux/securebits.h
@@ -32,7 +32,7 @@
    setting is locked or not. A setting which is locked cannot be
    changed from user-level. */
 #define issecure_mask(X)	(1 << (X))
-#define issecure(X)		(issecure_mask(X) & current->securebits)
+#define issecure(X)		(issecure_mask(X) & current_cred_xxx(securebits))
 
 #define SECURE_ALL_BITS		(issecure_mask(SECURE_NOROOT) | \
 				 issecure_mask(SECURE_NO_SETUID_FIXUP) | \
diff --git a/include/linux/security.h b/include/linux/security.h
index f5c4a51eb42e..3416cb85e77b 100644
--- a/include/linux/security.h
+++ b/include/linux/security.h
@@ -37,6 +37,10 @@
 /* Maximum number of letters for an LSM name string */
 #define SECURITY_NAME_MAX	10
 
+/* If capable should audit the security request */
+#define SECURITY_CAP_NOAUDIT 0
+#define SECURITY_CAP_AUDIT 1
+
 struct ctl_table;
 struct audit_krule;
 
@@ -44,25 +48,25 @@ struct audit_krule;
  * These functions are in security/capability.c and are used
  * as the default capabilities functions
  */
-extern int cap_capable(struct task_struct *tsk, int cap);
+extern int cap_capable(struct task_struct *tsk, int cap, int audit);
 extern int cap_settime(struct timespec *ts, struct timezone *tz);
 extern int cap_ptrace_may_access(struct task_struct *child, unsigned int mode);
 extern int cap_ptrace_traceme(struct task_struct *parent);
 extern int cap_capget(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted);
-extern int cap_capset_check(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted);
-extern void cap_capset_set(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted);
-extern int cap_bprm_set_security(struct linux_binprm *bprm);
-extern void cap_bprm_apply_creds(struct linux_binprm *bprm, int unsafe);
+extern int cap_capset(struct cred *new, const struct cred *old,
+		      const kernel_cap_t *effective,
+		      const kernel_cap_t *inheritable,
+		      const kernel_cap_t *permitted);
+extern int cap_bprm_set_creds(struct linux_binprm *bprm);
 extern int cap_bprm_secureexec(struct linux_binprm *bprm);
 extern int cap_inode_setxattr(struct dentry *dentry, const char *name,
 			      const void *value, size_t size, int flags);
 extern int cap_inode_removexattr(struct dentry *dentry, const char *name);
 extern int cap_inode_need_killpriv(struct dentry *dentry);
 extern int cap_inode_killpriv(struct dentry *dentry);
-extern int cap_task_post_setuid(uid_t old_ruid, uid_t old_euid, uid_t old_suid, int flags);
-extern void cap_task_reparent_to_init(struct task_struct *p);
+extern int cap_task_fix_setuid(struct cred *new, const struct cred *old, int flags);
 extern int cap_task_prctl(int option, unsigned long arg2, unsigned long arg3,
-			  unsigned long arg4, unsigned long arg5, long *rc_p);
+			  unsigned long arg4, unsigned long arg5);
 extern int cap_task_setscheduler(struct task_struct *p, int policy, struct sched_param *lp);
 extern int cap_task_setioprio(struct task_struct *p, int ioprio);
 extern int cap_task_setnice(struct task_struct *p, int nice);
@@ -105,7 +109,7 @@ extern unsigned long mmap_min_addr;
 struct sched_param;
 struct request_sock;
 
-/* bprm_apply_creds unsafe reasons */
+/* bprm->unsafe reasons */
 #define LSM_UNSAFE_SHARE	1
 #define LSM_UNSAFE_PTRACE	2
 #define LSM_UNSAFE_PTRACE_CAP	4
@@ -149,36 +153,7 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
  *
  * Security hooks for program execution operations.
  *
- * @bprm_alloc_security:
- *	Allocate and attach a security structure to the @bprm->security field.
- *	The security field is initialized to NULL when the bprm structure is
- *	allocated.
- *	@bprm contains the linux_binprm structure to be modified.
- *	Return 0 if operation was successful.
- * @bprm_free_security:
- *	@bprm contains the linux_binprm structure to be modified.
- *	Deallocate and clear the @bprm->security field.
- * @bprm_apply_creds:
- *	Compute and set the security attributes of a process being transformed
- *	by an execve operation based on the old attributes (current->security)
- *	and the information saved in @bprm->security by the set_security hook.
- *	Since this hook function (and its caller) are void, this hook can not
- *	return an error.  However, it can leave the security attributes of the
- *	process unchanged if an access failure occurs at this point.
- *	bprm_apply_creds is called under task_lock.  @unsafe indicates various
- *	reasons why it may be unsafe to change security state.
- *	@bprm contains the linux_binprm structure.
- * @bprm_post_apply_creds:
- *	Runs after bprm_apply_creds with the task_lock dropped, so that
- *	functions which cannot be called safely under the task_lock can
- *	be used.  This hook is a good place to perform state changes on
- *	the process such as closing open file descriptors to which access
- *	is no longer granted if the attributes were changed.
- *	Note that a security module might need to save state between
- *	bprm_apply_creds and bprm_post_apply_creds to store the decision
- *	on whether the process may proceed.
- *	@bprm contains the linux_binprm structure.
- * @bprm_set_security:
+ * @bprm_set_creds:
  *	Save security information in the bprm->security field, typically based
  *	on information about the bprm->file, for later use by the apply_creds
  *	hook.  This hook may also optionally check permissions (e.g. for
@@ -191,15 +166,30 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
  *	@bprm contains the linux_binprm structure.
  *	Return 0 if the hook is successful and permission is granted.
  * @bprm_check_security:
- *	This hook mediates the point when a search for a binary handler	will
- *	begin.  It allows a check the @bprm->security value which is set in
- *	the preceding set_security call.  The primary difference from
- *	set_security is that the argv list and envp list are reliably
- *	available in @bprm.  This hook may be called multiple times
- *	during a single execve; and in each pass set_security is called
- *	first.
+ *	This hook mediates the point when a search for a binary handler will
+ *	begin.  It allows a check the @bprm->security value which is set in the
+ *	preceding set_creds call.  The primary difference from set_creds is
+ *	that the argv list and envp list are reliably available in @bprm.  This
+ *	hook may be called multiple times during a single execve; and in each
+ *	pass set_creds is called first.
  *	@bprm contains the linux_binprm structure.
  *	Return 0 if the hook is successful and permission is granted.
+ * @bprm_committing_creds:
+ *	Prepare to install the new security attributes of a process being
+ *	transformed by an execve operation, based on the old credentials
+ *	pointed to by @current->cred and the information set in @bprm->cred by
+ *	the bprm_set_creds hook.  @bprm points to the linux_binprm structure.
+ *	This hook is a good place to perform state changes on the process such
+ *	as closing open file descriptors to which access will no longer be
+ *	granted when the attributes are changed.  This is called immediately
+ *	before commit_creds().
+ * @bprm_committed_creds:
+ *	Tidy up after the installation of the new security attributes of a
+ *	process being transformed by an execve operation.  The new credentials
+ *	have, by this point, been set to @current->cred.  @bprm points to the
+ *	linux_binprm structure.  This hook is a good place to perform state
+ *	changes on the process such as clearing out non-inheritable signal
+ *	state.  This is called immediately after commit_creds().
  * @bprm_secureexec:
  *	Return a boolean value (0 or 1) indicating whether a "secure exec"
  *	is required.  The flag is passed in the auxiliary table
@@ -585,15 +575,31 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
  *	manual page for definitions of the @clone_flags.
  *	@clone_flags contains the flags indicating what should be shared.
  *	Return 0 if permission is granted.
- * @task_alloc_security:
- *	@p contains the task_struct for child process.
- *	Allocate and attach a security structure to the p->security field. The
- *	security field is initialized to NULL when the task structure is
- *	allocated.
- *	Return 0 if operation was successful.
- * @task_free_security:
- *	@p contains the task_struct for process.
- *	Deallocate and clear the p->security field.
+ * @cred_free:
+ *	@cred points to the credentials.
+ *	Deallocate and clear the cred->security field in a set of credentials.
+ * @cred_prepare:
+ *	@new points to the new credentials.
+ *	@old points to the original credentials.
+ *	@gfp indicates the atomicity of any memory allocations.
+ *	Prepare a new set of credentials by copying the data from the old set.
+ * @cred_commit:
+ *	@new points to the new credentials.
+ *	@old points to the original credentials.
+ *	Install a new set of credentials.
+ * @kernel_act_as:
+ *	Set the credentials for a kernel service to act as (subjective context).
+ *	@new points to the credentials to be modified.
+ *	@secid specifies the security ID to be set
+ *	The current task must be the one that nominated @secid.
+ *	Return 0 if successful.
+ * @kernel_create_files_as:
+ *	Set the file creation context in a set of credentials to be the same as
+ *	the objective context of the specified inode.
+ *	@new points to the credentials to be modified.
+ *	@inode points to the inode to use as a reference.
+ *	The current task must be the one that nominated @inode.
+ *	Return 0 if successful.
  * @task_setuid:
  *	Check permission before setting one or more of the user identity
  *	attributes of the current process.  The @flags parameter indicates
@@ -606,15 +612,13 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
  *	@id2 contains a uid.
  *	@flags contains one of the LSM_SETID_* values.
  *	Return 0 if permission is granted.
- * @task_post_setuid:
+ * @task_fix_setuid:
  *	Update the module's state after setting one or more of the user
  *	identity attributes of the current process.  The @flags parameter
  *	indicates which of the set*uid system calls invoked this hook.  If
- *	@flags is LSM_SETID_FS, then @old_ruid is the old fs uid and the other
- *	parameters are not used.
- *	@old_ruid contains the old real uid (or fs uid if LSM_SETID_FS).
- *	@old_euid contains the old effective uid (or -1 if LSM_SETID_FS).
- *	@old_suid contains the old saved uid (or -1 if LSM_SETID_FS).
+ *	@new is the set of credentials that will be installed.  Modifications
+ *	should be made to this rather than to @current->cred.
+ *	@old is the set of credentials that are being replaces
  *	@flags contains one of the LSM_SETID_* values.
  *	Return 0 on success.
  * @task_setgid:
@@ -717,13 +721,8 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
  *	@arg3 contains a argument.
  *	@arg4 contains a argument.
  *	@arg5 contains a argument.
- *      @rc_p contains a pointer to communicate back the forced return code
- *	Return 0 if permission is granted, and non-zero if the security module
- *      has taken responsibility (setting *rc_p) for the prctl call.
- * @task_reparent_to_init:
- *	Set the security attributes in @p->security for a kernel thread that
- *	is being reparented to the init task.
- *	@p contains the task_struct for the kernel thread.
+ *	Return -ENOSYS if no-one wanted to handle this op, any other value to
+ *	cause prctl() to return immediately with that value.
  * @task_to_inode:
  *	Set the security attributes for an inode based on an associated task's
  *	security attributes, e.g. for /proc/pid inodes.
@@ -1000,7 +999,7 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
  *	See whether a specific operational right is granted to a process on a
  *	key.
  *	@key_ref refers to the key (key pointer + possession attribute bit).
- *	@context points to the process to provide the context against which to
+ *	@cred points to the credentials to provide the context against which to
  *	evaluate the security data on the key.
  *	@perm describes the combination of permissions required of this key.
  *	Return 1 if permission granted, 0 if permission denied and -ve it the
@@ -1162,6 +1161,7 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
  *	@child process.
  *	Security modules may also want to perform a process tracing check
  *	during an execve in the set_security or apply_creds hooks of
+ *	tracing check during an execve in the bprm_set_creds hook of
  *	binprm_security_ops if the process is being traced and its security
  *	attributes would be changed by the execve.
  *	@child contains the task_struct structure for the target process.
@@ -1185,29 +1185,15 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
  *	@inheritable contains the inheritable capability set.
  *	@permitted contains the permitted capability set.
  *	Return 0 if the capability sets were successfully obtained.
- * @capset_check:
- *	Check permission before setting the @effective, @inheritable, and
- *	@permitted capability sets for the @target process.
- *	Caveat:  @target is also set to current if a set of processes is
- *	specified (i.e. all processes other than current and init or a
- *	particular process group).  Hence, the capset_set hook may need to
- *	revalidate permission to the actual target process.
- *	@target contains the task_struct structure for target process.
- *	@effective contains the effective capability set.
- *	@inheritable contains the inheritable capability set.
- *	@permitted contains the permitted capability set.
- *	Return 0 if permission is granted.
- * @capset_set:
+ * @capset:
  *	Set the @effective, @inheritable, and @permitted capability sets for
- *	the @target process.  Since capset_check cannot always check permission
- *	to the real @target process, this hook may also perform permission
- *	checking to determine if the current process is allowed to set the
- *	capability sets of the @target process.  However, this hook has no way
- *	of returning an error due to the structure of the sys_capset code.
- *	@target contains the task_struct structure for target process.
+ *	the current process.
+ *	@new contains the new credentials structure for target process.
+ *	@old contains the current credentials structure for target process.
  *	@effective contains the effective capability set.
  *	@inheritable contains the inheritable capability set.
  *	@permitted contains the permitted capability set.
+ *	Return 0 and update @new if permission is granted.
  * @capable:
  *	Check whether the @tsk process has the @cap capability.
  *	@tsk contains the task_struct for the process.
@@ -1299,15 +1285,12 @@ struct security_operations {
 	int (*capget) (struct task_struct *target,
 		       kernel_cap_t *effective,
 		       kernel_cap_t *inheritable, kernel_cap_t *permitted);
-	int (*capset_check) (struct task_struct *target,
-			     kernel_cap_t *effective,
-			     kernel_cap_t *inheritable,
-			     kernel_cap_t *permitted);
-	void (*capset_set) (struct task_struct *target,
-			    kernel_cap_t *effective,
-			    kernel_cap_t *inheritable,
-			    kernel_cap_t *permitted);
-	int (*capable) (struct task_struct *tsk, int cap);
+	int (*capset) (struct cred *new,
+		       const struct cred *old,
+		       const kernel_cap_t *effective,
+		       const kernel_cap_t *inheritable,
+		       const kernel_cap_t *permitted);
+	int (*capable) (struct task_struct *tsk, int cap, int audit);
 	int (*acct) (struct file *file);
 	int (*sysctl) (struct ctl_table *table, int op);
 	int (*quotactl) (int cmds, int type, int id, struct super_block *sb);
@@ -1316,18 +1299,16 @@ struct security_operations {
 	int (*settime) (struct timespec *ts, struct timezone *tz);
 	int (*vm_enough_memory) (struct mm_struct *mm, long pages);
 
-	int (*bprm_alloc_security) (struct linux_binprm *bprm);
-	void (*bprm_free_security) (struct linux_binprm *bprm);
-	void (*bprm_apply_creds) (struct linux_binprm *bprm, int unsafe);
-	void (*bprm_post_apply_creds) (struct linux_binprm *bprm);
-	int (*bprm_set_security) (struct linux_binprm *bprm);
+	int (*bprm_set_creds) (struct linux_binprm *bprm);
 	int (*bprm_check_security) (struct linux_binprm *bprm);
 	int (*bprm_secureexec) (struct linux_binprm *bprm);
+	void (*bprm_committing_creds) (struct linux_binprm *bprm);
+	void (*bprm_committed_creds) (struct linux_binprm *bprm);
 
 	int (*sb_alloc_security) (struct super_block *sb);
 	void (*sb_free_security) (struct super_block *sb);
 	int (*sb_copy_data) (char *orig, char *copy);
-	int (*sb_kern_mount) (struct super_block *sb, void *data);
+	int (*sb_kern_mount) (struct super_block *sb, int flags, void *data);
 	int (*sb_show_options) (struct seq_file *m, struct super_block *sb);
 	int (*sb_statfs) (struct dentry *dentry);
 	int (*sb_mount) (char *dev_name, struct path *path,
@@ -1406,14 +1387,18 @@ struct security_operations {
 	int (*file_send_sigiotask) (struct task_struct *tsk,
 				    struct fown_struct *fown, int sig);
 	int (*file_receive) (struct file *file);
-	int (*dentry_open) (struct file *file);
+	int (*dentry_open) (struct file *file, const struct cred *cred);
 
 	int (*task_create) (unsigned long clone_flags);
-	int (*task_alloc_security) (struct task_struct *p);
-	void (*task_free_security) (struct task_struct *p);
+	void (*cred_free) (struct cred *cred);
+	int (*cred_prepare)(struct cred *new, const struct cred *old,
+			    gfp_t gfp);
+	void (*cred_commit)(struct cred *new, const struct cred *old);
+	int (*kernel_act_as)(struct cred *new, u32 secid);
+	int (*kernel_create_files_as)(struct cred *new, struct inode *inode);
 	int (*task_setuid) (uid_t id0, uid_t id1, uid_t id2, int flags);
-	int (*task_post_setuid) (uid_t old_ruid /* or fsuid */ ,
-				 uid_t old_euid, uid_t old_suid, int flags);
+	int (*task_fix_setuid) (struct cred *new, const struct cred *old,
+				int flags);
 	int (*task_setgid) (gid_t id0, gid_t id1, gid_t id2, int flags);
 	int (*task_setpgid) (struct task_struct *p, pid_t pgid);
 	int (*task_getpgid) (struct task_struct *p);
@@ -1433,8 +1418,7 @@ struct security_operations {
 	int (*task_wait) (struct task_struct *p);
 	int (*task_prctl) (int option, unsigned long arg2,
 			   unsigned long arg3, unsigned long arg4,
-			   unsigned long arg5, long *rc_p);
-	void (*task_reparent_to_init) (struct task_struct *p);
+			   unsigned long arg5);
 	void (*task_to_inode) (struct task_struct *p, struct inode *inode);
 
 	int (*ipc_permission) (struct kern_ipc_perm *ipcp, short flag);
@@ -1539,10 +1523,10 @@ struct security_operations {
 
 	/* key management security hooks */
 #ifdef CONFIG_KEYS
-	int (*key_alloc) (struct key *key, struct task_struct *tsk, unsigned long flags);
+	int (*key_alloc) (struct key *key, const struct cred *cred, unsigned long flags);
 	void (*key_free) (struct key *key);
 	int (*key_permission) (key_ref_t key_ref,
-			       struct task_struct *context,
+			       const struct cred *cred,
 			       key_perm_t perm);
 	int (*key_getsecurity)(struct key *key, char **_buffer);
 #endif	/* CONFIG_KEYS */
@@ -1568,15 +1552,12 @@ int security_capget(struct task_struct *target,
 		    kernel_cap_t *effective,
 		    kernel_cap_t *inheritable,
 		    kernel_cap_t *permitted);
-int security_capset_check(struct task_struct *target,
-			  kernel_cap_t *effective,
-			  kernel_cap_t *inheritable,
-			  kernel_cap_t *permitted);
-void security_capset_set(struct task_struct *target,
-			 kernel_cap_t *effective,
-			 kernel_cap_t *inheritable,
-			 kernel_cap_t *permitted);
+int security_capset(struct cred *new, const struct cred *old,
+		    const kernel_cap_t *effective,
+		    const kernel_cap_t *inheritable,
+		    const kernel_cap_t *permitted);
 int security_capable(struct task_struct *tsk, int cap);
+int security_capable_noaudit(struct task_struct *tsk, int cap);
 int security_acct(struct file *file);
 int security_sysctl(struct ctl_table *table, int op);
 int security_quotactl(int cmds, int type, int id, struct super_block *sb);
@@ -1585,17 +1566,16 @@ int security_syslog(int type);
 int security_settime(struct timespec *ts, struct timezone *tz);
 int security_vm_enough_memory(long pages);
 int security_vm_enough_memory_mm(struct mm_struct *mm, long pages);
-int security_bprm_alloc(struct linux_binprm *bprm);
-void security_bprm_free(struct linux_binprm *bprm);
-void security_bprm_apply_creds(struct linux_binprm *bprm, int unsafe);
-void security_bprm_post_apply_creds(struct linux_binprm *bprm);
-int security_bprm_set(struct linux_binprm *bprm);
+int security_vm_enough_memory_kern(long pages);
+int security_bprm_set_creds(struct linux_binprm *bprm);
 int security_bprm_check(struct linux_binprm *bprm);
+void security_bprm_committing_creds(struct linux_binprm *bprm);
+void security_bprm_committed_creds(struct linux_binprm *bprm);
 int security_bprm_secureexec(struct linux_binprm *bprm);
 int security_sb_alloc(struct super_block *sb);
 void security_sb_free(struct super_block *sb);
 int security_sb_copy_data(char *orig, char *copy);
-int security_sb_kern_mount(struct super_block *sb, void *data);
+int security_sb_kern_mount(struct super_block *sb, int flags, void *data);
 int security_sb_show_options(struct seq_file *m, struct super_block *sb);
 int security_sb_statfs(struct dentry *dentry);
 int security_sb_mount(char *dev_name, struct path *path,
@@ -1662,13 +1642,16 @@ int security_file_set_fowner(struct file *file);
 int security_file_send_sigiotask(struct task_struct *tsk,
 				 struct fown_struct *fown, int sig);
 int security_file_receive(struct file *file);
-int security_dentry_open(struct file *file);
+int security_dentry_open(struct file *file, const struct cred *cred);
 int security_task_create(unsigned long clone_flags);
-int security_task_alloc(struct task_struct *p);
-void security_task_free(struct task_struct *p);
+void security_cred_free(struct cred *cred);
+int security_prepare_creds(struct cred *new, const struct cred *old, gfp_t gfp);
+void security_commit_creds(struct cred *new, const struct cred *old);
+int security_kernel_act_as(struct cred *new, u32 secid);
+int security_kernel_create_files_as(struct cred *new, struct inode *inode);
 int security_task_setuid(uid_t id0, uid_t id1, uid_t id2, int flags);
-int security_task_post_setuid(uid_t old_ruid, uid_t old_euid,
-			      uid_t old_suid, int flags);
+int security_task_fix_setuid(struct cred *new, const struct cred *old,
+			     int flags);
 int security_task_setgid(gid_t id0, gid_t id1, gid_t id2, int flags);
 int security_task_setpgid(struct task_struct *p, pid_t pgid);
 int security_task_getpgid(struct task_struct *p);
@@ -1687,8 +1670,7 @@ int security_task_kill(struct task_struct *p, struct siginfo *info,
 			int sig, u32 secid);
 int security_task_wait(struct task_struct *p);
 int security_task_prctl(int option, unsigned long arg2, unsigned long arg3,
-			 unsigned long arg4, unsigned long arg5, long *rc_p);
-void security_task_reparent_to_init(struct task_struct *p);
+			unsigned long arg4, unsigned long arg5);
 void security_task_to_inode(struct task_struct *p, struct inode *inode);
 int security_ipc_permission(struct kern_ipc_perm *ipcp, short flag);
 void security_ipc_getsecid(struct kern_ipc_perm *ipcp, u32 *secid);
@@ -1763,25 +1745,23 @@ static inline int security_capget(struct task_struct *target,
 	return cap_capget(target, effective, inheritable, permitted);
 }
 
-static inline int security_capset_check(struct task_struct *target,
-					 kernel_cap_t *effective,
-					 kernel_cap_t *inheritable,
-					 kernel_cap_t *permitted)
+static inline int security_capset(struct cred *new,
+				   const struct cred *old,
+				   const kernel_cap_t *effective,
+				   const kernel_cap_t *inheritable,
+				   const kernel_cap_t *permitted)
 {
-	return cap_capset_check(target, effective, inheritable, permitted);
+	return cap_capset(new, old, effective, inheritable, permitted);
 }
 
-static inline void security_capset_set(struct task_struct *target,
-					kernel_cap_t *effective,
-					kernel_cap_t *inheritable,
-					kernel_cap_t *permitted)
+static inline int security_capable(struct task_struct *tsk, int cap)
 {
-	cap_capset_set(target, effective, inheritable, permitted);
+	return cap_capable(tsk, cap, SECURITY_CAP_AUDIT);
 }
 
-static inline int security_capable(struct task_struct *tsk, int cap)
+static inline int security_capable_noaudit(struct task_struct *tsk, int cap)
 {
-	return cap_capable(tsk, cap);
+	return cap_capable(tsk, cap, SECURITY_CAP_NOAUDIT);
 }
 
 static inline int security_acct(struct file *file)
@@ -1817,40 +1797,39 @@ static inline int security_settime(struct timespec *ts, struct timezone *tz)
 
 static inline int security_vm_enough_memory(long pages)
 {
+	WARN_ON(current->mm == NULL);
 	return cap_vm_enough_memory(current->mm, pages);
 }
 
 static inline int security_vm_enough_memory_mm(struct mm_struct *mm, long pages)
 {
+	WARN_ON(mm == NULL);
 	return cap_vm_enough_memory(mm, pages);
 }
 
-static inline int security_bprm_alloc(struct linux_binprm *bprm)
+static inline int security_vm_enough_memory_kern(long pages)
 {
-	return 0;
+	/* If current->mm is a kernel thread then we will pass NULL,
+	   for this specific case that is fine */
+	return cap_vm_enough_memory(current->mm, pages);
 }
 
-static inline void security_bprm_free(struct linux_binprm *bprm)
-{ }
-
-static inline void security_bprm_apply_creds(struct linux_binprm *bprm, int unsafe)
+static inline int security_bprm_set_creds(struct linux_binprm *bprm)
 {
-	cap_bprm_apply_creds(bprm, unsafe);
+	return cap_bprm_set_creds(bprm);
 }
 
-static inline void security_bprm_post_apply_creds(struct linux_binprm *bprm)
+static inline int security_bprm_check(struct linux_binprm *bprm)
 {
-	return;
+	return 0;
 }
 
-static inline int security_bprm_set(struct linux_binprm *bprm)
+static inline void security_bprm_committing_creds(struct linux_binprm *bprm)
 {
-	return cap_bprm_set_security(bprm);
 }
 
-static inline int security_bprm_check(struct linux_binprm *bprm)
+static inline void security_bprm_committed_creds(struct linux_binprm *bprm)
 {
-	return 0;
 }
 
 static inline int security_bprm_secureexec(struct linux_binprm *bprm)
@@ -1871,7 +1850,7 @@ static inline int security_sb_copy_data(char *orig, char *copy)
 	return 0;
 }
 
-static inline int security_sb_kern_mount(struct super_block *sb, void *data)
+static inline int security_sb_kern_mount(struct super_block *sb, int flags, void *data)
 {
 	return 0;
 }
@@ -2167,7 +2146,8 @@ static inline int security_file_receive(struct file *file)
 	return 0;
 }
 
-static inline int security_dentry_open(struct file *file)
+static inline int security_dentry_open(struct file *file,
+				       const struct cred *cred)
 {
 	return 0;
 }
@@ -2177,13 +2157,31 @@ static inline int security_task_create(unsigned long clone_flags)
 	return 0;
 }
 
-static inline int security_task_alloc(struct task_struct *p)
+static inline void security_cred_free(struct cred *cred)
+{ }
+
+static inline int security_prepare_creds(struct cred *new,
+					 const struct cred *old,
+					 gfp_t gfp)
 {
 	return 0;
 }
 
-static inline void security_task_free(struct task_struct *p)
-{ }
+static inline void security_commit_creds(struct cred *new,
+					 const struct cred *old)
+{
+}
+
+static inline int security_kernel_act_as(struct cred *cred, u32 secid)
+{
+	return 0;
+}
+
+static inline int security_kernel_create_files_as(struct cred *cred,
+						  struct inode *inode)
+{
+	return 0;
+}
 
 static inline int security_task_setuid(uid_t id0, uid_t id1, uid_t id2,
 				       int flags)
@@ -2191,10 +2189,11 @@ static inline int security_task_setuid(uid_t id0, uid_t id1, uid_t id2,
 	return 0;
 }
 
-static inline int security_task_post_setuid(uid_t old_ruid, uid_t old_euid,
-					    uid_t old_suid, int flags)
+static inline int security_task_fix_setuid(struct cred *new,
+					   const struct cred *old,
+					   int flags)
 {
-	return cap_task_post_setuid(old_ruid, old_euid, old_suid, flags);
+	return cap_task_fix_setuid(new, old, flags);
 }
 
 static inline int security_task_setgid(gid_t id0, gid_t id1, gid_t id2,
@@ -2281,14 +2280,9 @@ static inline int security_task_wait(struct task_struct *p)
 static inline int security_task_prctl(int option, unsigned long arg2,
 				      unsigned long arg3,
 				      unsigned long arg4,
-				      unsigned long arg5, long *rc_p)
-{
-	return cap_task_prctl(option, arg2, arg3, arg3, arg5, rc_p);
-}
-
-static inline void security_task_reparent_to_init(struct task_struct *p)
+				      unsigned long arg5)
 {
-	cap_task_reparent_to_init(p);
+	return cap_task_prctl(option, arg2, arg3, arg3, arg5);
 }
 
 static inline void security_task_to_inode(struct task_struct *p, struct inode *inode)
@@ -2714,16 +2708,16 @@ static inline void security_skb_classify_flow(struct sk_buff *skb, struct flowi
 #ifdef CONFIG_KEYS
 #ifdef CONFIG_SECURITY
 
-int security_key_alloc(struct key *key, struct task_struct *tsk, unsigned long flags);
+int security_key_alloc(struct key *key, const struct cred *cred, unsigned long flags);
 void security_key_free(struct key *key);
 int security_key_permission(key_ref_t key_ref,
-			    struct task_struct *context, key_perm_t perm);
+			    const struct cred *cred, key_perm_t perm);
 int security_key_getsecurity(struct key *key, char **_buffer);
 
 #else
 
 static inline int security_key_alloc(struct key *key,
-				     struct task_struct *tsk,
+				     const struct cred *cred,
 				     unsigned long flags)
 {
 	return 0;
@@ -2734,7 +2728,7 @@ static inline void security_key_free(struct key *key)
 }
 
 static inline int security_key_permission(key_ref_t key_ref,
-					  struct task_struct *context,
+					  const struct cred *cred,
 					  key_perm_t perm)
 {
 	return 0;
diff --git a/include/linux/seq_file.h b/include/linux/seq_file.h
index a1783b229ef4..b3dfa72f13b9 100644
--- a/include/linux/seq_file.h
+++ b/include/linux/seq_file.h
@@ -34,6 +34,7 @@ struct seq_operations {
 
 #define SEQ_SKIP 1
 
+char *mangle_path(char *s, char *p, char *esc);
 int seq_open(struct file *, const struct seq_operations *);
 ssize_t seq_read(struct file *, char __user *, size_t, loff_t *);
 loff_t seq_lseek(struct file *, loff_t, int);
@@ -60,6 +61,19 @@ static inline int seq_nodemask(struct seq_file *m, nodemask_t *mask)
 	return seq_bitmap(m, mask->bits, MAX_NUMNODES);
 }
 
+int seq_bitmap_list(struct seq_file *m, unsigned long *bits,
+		unsigned int nr_bits);
+
+static inline int seq_cpumask_list(struct seq_file *m, cpumask_t *mask)
+{
+	return seq_bitmap_list(m, mask->bits, NR_CPUS);
+}
+
+static inline int seq_nodemask_list(struct seq_file *m, nodemask_t *mask)
+{
+	return seq_bitmap_list(m, mask->bits, MAX_NUMNODES);
+}
+
 int single_open(struct file *, int (*)(struct seq_file *, void *), void *);
 int single_release(struct inode *, struct file *);
 void *__seq_open_private(struct file *, const struct seq_operations *, int);
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index e27f216361fc..feb3b939ec4b 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -155,6 +155,11 @@
 
 #define PORT_SC26XX	82
 
+/* SH-SCI */
+#define PORT_SCIFA	83
+
+#define PORT_S3C6400	84
+
 #ifdef __KERNEL__
 
 #include <linux/compiler.h>
diff --git a/include/linux/sh_intc.h b/include/linux/sh_intc.h
new file mode 100644
index 000000000000..68e212ff9dde
--- /dev/null
+++ b/include/linux/sh_intc.h
@@ -0,0 +1,91 @@
+#ifndef __SH_INTC_H
+#define __SH_INTC_H
+
+typedef unsigned char intc_enum;
+
+struct intc_vect {
+	intc_enum enum_id;
+	unsigned short vect;
+};
+
+#define INTC_VECT(enum_id, vect) { enum_id, vect }
+#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
+
+struct intc_group {
+	intc_enum enum_id;
+	intc_enum enum_ids[32];
+};
+
+#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
+
+struct intc_mask_reg {
+	unsigned long set_reg, clr_reg, reg_width;
+	intc_enum enum_ids[32];
+#ifdef CONFIG_SMP
+	unsigned long smp;
+#endif
+};
+
+struct intc_prio_reg {
+	unsigned long set_reg, clr_reg, reg_width, field_width;
+	intc_enum enum_ids[16];
+#ifdef CONFIG_SMP
+	unsigned long smp;
+#endif
+};
+
+struct intc_sense_reg {
+	unsigned long reg, reg_width, field_width;
+	intc_enum enum_ids[16];
+};
+
+#ifdef CONFIG_SMP
+#define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8)
+#else
+#define INTC_SMP(stride, nr)
+#endif
+
+struct intc_desc {
+	struct intc_vect *vectors;
+	unsigned int nr_vectors;
+	struct intc_group *groups;
+	unsigned int nr_groups;
+	struct intc_mask_reg *mask_regs;
+	unsigned int nr_mask_regs;
+	struct intc_prio_reg *prio_regs;
+	unsigned int nr_prio_regs;
+	struct intc_sense_reg *sense_regs;
+	unsigned int nr_sense_regs;
+	char *name;
+#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
+	struct intc_mask_reg *ack_regs;
+	unsigned int nr_ack_regs;
+#endif
+};
+
+#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
+#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups,		\
+	mask_regs, prio_regs, sense_regs)				\
+struct intc_desc symbol __initdata = {					\
+	_INTC_ARRAY(vectors), _INTC_ARRAY(groups),			\
+	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),			\
+	_INTC_ARRAY(sense_regs),					\
+	chipname,							\
+}
+
+#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
+#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups,	\
+	mask_regs, prio_regs, sense_regs, ack_regs)			\
+struct intc_desc symbol __initdata = {					\
+	_INTC_ARRAY(vectors), _INTC_ARRAY(groups),			\
+	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),			\
+	_INTC_ARRAY(sense_regs),					\
+	chipname,							\
+	_INTC_ARRAY(ack_regs),						\
+}
+#endif
+
+void __init register_intc_controller(struct intc_desc *desc);
+int intc_set_priority(unsigned int irq, unsigned int prio);
+
+#endif /* __SH_INTC_H */
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index 2725f4e5a9bf..cf2cb50f77d1 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -250,6 +250,9 @@ typedef unsigned char *sk_buff_data_t;
  *	@tc_verd: traffic control verdict
  *	@ndisc_nodetype: router type (from link layer)
  *	@do_not_encrypt: set to prevent encryption of this frame
+ *	@requeue: set to indicate that the wireless core should attempt
+ *		a software retry on this frame if we failed to
+ *		receive an ACK for it
  *	@dma_cookie: a cookie to one of several possible DMA operations
  *		done by skb DMA functions
  *	@secmark: security marking
@@ -269,8 +272,9 @@ struct sk_buff {
 		struct  dst_entry	*dst;
 		struct  rtable		*rtable;
 	};
+#ifdef CONFIG_XFRM
 	struct	sec_path	*sp;
-
+#endif
 	/*
 	 * This is the control buffer. It is free to use for every
 	 * layer. Please put your private variables there. If you
@@ -325,6 +329,7 @@ struct sk_buff {
 #endif
 #if defined(CONFIG_MAC80211) || defined(CONFIG_MAC80211_MODULE)
 	__u8			do_not_encrypt:1;
+	__u8			requeue:1;
 #endif
 	/* 0/13/14 bit hole */
 
@@ -488,6 +493,19 @@ static inline bool skb_queue_is_last(const struct sk_buff_head *list,
 }
 
 /**
+ *	skb_queue_is_first - check if skb is the first entry in the queue
+ *	@list: queue head
+ *	@skb: buffer
+ *
+ *	Returns true if @skb is the first buffer on the list.
+ */
+static inline bool skb_queue_is_first(const struct sk_buff_head *list,
+				      const struct sk_buff *skb)
+{
+	return (skb->prev == (struct sk_buff *) list);
+}
+
+/**
  *	skb_queue_next - return the next packet in the queue
  *	@list: queue head
  *	@skb: current buffer
@@ -506,6 +524,24 @@ static inline struct sk_buff *skb_queue_next(const struct sk_buff_head *list,
 }
 
 /**
+ *	skb_queue_prev - return the prev packet in the queue
+ *	@list: queue head
+ *	@skb: current buffer
+ *
+ *	Return the prev packet in @list before @skb.  It is only valid to
+ *	call this if skb_queue_is_first() evaluates to false.
+ */
+static inline struct sk_buff *skb_queue_prev(const struct sk_buff_head *list,
+					     const struct sk_buff *skb)
+{
+	/* This BUG_ON may seem severe, but if we just return then we
+	 * are going to dereference garbage.
+	 */
+	BUG_ON(skb_queue_is_first(list, skb));
+	return skb->prev;
+}
+
+/**
  *	skb_get - reference buffer
  *	@skb: buffer to reference
  *
@@ -1647,8 +1683,12 @@ extern int             skb_splice_bits(struct sk_buff *skb,
 extern void	       skb_copy_and_csum_dev(const struct sk_buff *skb, u8 *to);
 extern void	       skb_split(struct sk_buff *skb,
 				 struct sk_buff *skb1, const u32 len);
+extern int	       skb_shift(struct sk_buff *tgt, struct sk_buff *skb,
+				 int shiftlen);
 
 extern struct sk_buff *skb_segment(struct sk_buff *skb, int features);
+extern int	       skb_gro_receive(struct sk_buff **head,
+				       struct sk_buff *skb);
 
 static inline void *skb_header_pointer(const struct sk_buff *skb, int offset,
 				       int len, void *buffer)
@@ -1864,6 +1904,18 @@ static inline void skb_copy_queue_mapping(struct sk_buff *to, const struct sk_bu
 	to->queue_mapping = from->queue_mapping;
 }
 
+#ifdef CONFIG_XFRM
+static inline struct sec_path *skb_sec_path(struct sk_buff *skb)
+{
+	return skb->sp;
+}
+#else
+static inline struct sec_path *skb_sec_path(struct sk_buff *skb)
+{
+	return NULL;
+}
+#endif
+
 static inline int skb_is_gso(const struct sk_buff *skb)
 {
 	return skb_shinfo(skb)->gso_size;
diff --git a/include/linux/slab.h b/include/linux/slab.h
index 5ff9676c1e2c..f96d13c281e8 100644
--- a/include/linux/slab.h
+++ b/include/linux/slab.h
@@ -23,6 +23,34 @@
 #define SLAB_CACHE_DMA		0x00004000UL	/* Use GFP_DMA memory */
 #define SLAB_STORE_USER		0x00010000UL	/* DEBUG: Store the last owner for bug hunting */
 #define SLAB_PANIC		0x00040000UL	/* Panic if kmem_cache_create() fails */
+/*
+ * SLAB_DESTROY_BY_RCU - **WARNING** READ THIS!
+ *
+ * This delays freeing the SLAB page by a grace period, it does _NOT_
+ * delay object freeing. This means that if you do kmem_cache_free()
+ * that memory location is free to be reused at any time. Thus it may
+ * be possible to see another object there in the same RCU grace period.
+ *
+ * This feature only ensures the memory location backing the object
+ * stays valid, the trick to using this is relying on an independent
+ * object validation pass. Something like:
+ *
+ *  rcu_read_lock()
+ * again:
+ *  obj = lockless_lookup(key);
+ *  if (obj) {
+ *    if (!try_get_ref(obj)) // might fail for free objects
+ *      goto again;
+ *
+ *    if (obj->key != key) { // not the object we expected
+ *      put_ref(obj);
+ *      goto again;
+ *    }
+ *  }
+ *  rcu_read_unlock();
+ *
+ * See also the comment on struct slab_rcu in mm/slab.c.
+ */
 #define SLAB_DESTROY_BY_RCU	0x00080000UL	/* Defer freeing slabs to RCU */
 #define SLAB_MEM_SPREAD		0x00100000UL	/* Spread some memory over cpuset */
 #define SLAB_TRACE		0x00200000UL	/* Trace allocations and frees */
@@ -225,9 +253,9 @@ static inline void *kmem_cache_alloc_node(struct kmem_cache *cachep,
  * request comes from.
  */
 #if defined(CONFIG_DEBUG_SLAB) || defined(CONFIG_SLUB)
-extern void *__kmalloc_track_caller(size_t, gfp_t, void*);
+extern void *__kmalloc_track_caller(size_t, gfp_t, unsigned long);
 #define kmalloc_track_caller(size, flags) \
-	__kmalloc_track_caller(size, flags, __builtin_return_address(0))
+	__kmalloc_track_caller(size, flags, _RET_IP_)
 #else
 #define kmalloc_track_caller(size, flags) \
 	__kmalloc(size, flags)
@@ -243,10 +271,10 @@ extern void *__kmalloc_track_caller(size_t, gfp_t, void*);
  * allocation request comes from.
  */
 #if defined(CONFIG_DEBUG_SLAB) || defined(CONFIG_SLUB)
-extern void *__kmalloc_node_track_caller(size_t, gfp_t, int, void *);
+extern void *__kmalloc_node_track_caller(size_t, gfp_t, int, unsigned long);
 #define kmalloc_node_track_caller(size, flags, node) \
 	__kmalloc_node_track_caller(size, flags, node, \
-			__builtin_return_address(0))
+			_RET_IP_)
 #else
 #define kmalloc_node_track_caller(size, flags, node) \
 	__kmalloc_node(size, flags, node)
@@ -257,7 +285,7 @@ extern void *__kmalloc_node_track_caller(size_t, gfp_t, int, void *);
 #define kmalloc_node_track_caller(size, flags, node) \
 	kmalloc_track_caller(size, flags)
 
-#endif /* DEBUG_SLAB */
+#endif /* CONFIG_NUMA */
 
 /*
  * Shortcuts
@@ -288,9 +316,4 @@ static inline void *kzalloc_node(size_t size, gfp_t flags, int node)
 	return kmalloc_node(size, flags | __GFP_ZERO, node);
 }
 
-#ifdef CONFIG_SLABINFO
-extern const struct seq_operations slabinfo_op;
-ssize_t slabinfo_write(struct file *, const char __user *, size_t, loff_t *);
-#endif
-
 #endif	/* _LINUX_SLAB_H */
diff --git a/include/linux/smc911x.h b/include/linux/smc911x.h
index b58f54c24183..521f37143fae 100644
--- a/include/linux/smc911x.h
+++ b/include/linux/smc911x.h
@@ -7,6 +7,7 @@
 struct smc911x_platdata {
 	unsigned long flags;
 	unsigned long irq_flags; /* IRQF_... */
+	int irq_polarity;
 };
 
 #endif /* __SMC911X_H__ */
diff --git a/include/linux/smp.h b/include/linux/smp.h
index 66484d4a8459..6e7ba16ff454 100644
--- a/include/linux/smp.h
+++ b/include/linux/smp.h
@@ -7,6 +7,7 @@
  */
 
 #include <linux/errno.h>
+#include <linux/types.h>
 #include <linux/list.h>
 #include <linux/cpumask.h>
 
@@ -16,7 +17,8 @@ struct call_single_data {
 	struct list_head list;
 	void (*func) (void *info);
 	void *info;
-	unsigned int flags;
+	u16 flags;
+	u16 priv;
 };
 
 #ifdef CONFIG_SMP
@@ -62,8 +64,17 @@ extern void smp_cpus_done(unsigned int max_cpus);
  * Call a function on all other processors
  */
 int smp_call_function(void(*func)(void *info), void *info, int wait);
+/* Deprecated: use smp_call_function_many() which uses a cpumask ptr. */
 int smp_call_function_mask(cpumask_t mask, void(*func)(void *info), void *info,
 				int wait);
+
+static inline void smp_call_function_many(const struct cpumask *mask,
+					  void (*func)(void *info), void *info,
+					  int wait)
+{
+	smp_call_function_mask(*mask, func, info, wait);
+}
+
 int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
 				int wait);
 void __smp_call_function_single(int cpuid, struct call_single_data *data);
@@ -135,6 +146,8 @@ static inline void smp_send_reschedule(int cpu) { }
 })
 #define smp_call_function_mask(mask, func, info, wait) \
 			(up_smp_call_function(func, info))
+#define smp_call_function_many(mask, func, info, wait) \
+			(up_smp_call_function(func, info))
 static inline void init_call_single_data(void)
 {
 }
diff --git a/include/linux/smsc911x.h b/include/linux/smsc911x.h
new file mode 100644
index 000000000000..1cbf0313adde
--- /dev/null
+++ b/include/linux/smsc911x.h
@@ -0,0 +1,47 @@
+/***************************************************************************
+ *
+ * Copyright (C) 2004-2008 SMSC
+ * Copyright (C) 2005-2008 ARM
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ ***************************************************************************/
+#ifndef __LINUX_SMSC911X_H__
+#define __LINUX_SMSC911X_H__
+
+#include <linux/phy.h>
+
+/* platform_device configuration data, should be assigned to
+ * the platform_device's dev.platform_data */
+struct smsc911x_platform_config {
+	unsigned int irq_polarity;
+	unsigned int irq_type;
+	unsigned int flags;
+	phy_interface_t phy_interface;
+};
+
+/* Constants for platform_device irq polarity configuration */
+#define SMSC911X_IRQ_POLARITY_ACTIVE_LOW	0
+#define SMSC911X_IRQ_POLARITY_ACTIVE_HIGH	1
+
+/* Constants for platform_device irq type configuration */
+#define SMSC911X_IRQ_TYPE_OPEN_DRAIN		0
+#define SMSC911X_IRQ_TYPE_PUSH_PULL		1
+
+/* Constants for flags */
+#define SMSC911X_USE_16BIT 			(BIT(0))
+#define SMSC911X_USE_32BIT 			(BIT(1))
+
+#endif /* __LINUX_SMSC911X_H__ */
diff --git a/include/linux/snmp.h b/include/linux/snmp.h
index 7a6e6bba4a71..aee3f1e1d1ce 100644
--- a/include/linux/snmp.h
+++ b/include/linux/snmp.h
@@ -216,6 +216,9 @@ enum
 	LINUX_MIB_TCPSPURIOUSRTOS,		/* TCPSpuriousRTOs */
 	LINUX_MIB_TCPMD5NOTFOUND,		/* TCPMD5NotFound */
 	LINUX_MIB_TCPMD5UNEXPECTED,		/* TCPMD5Unexpected */
+	LINUX_MIB_SACKSHIFTED,
+	LINUX_MIB_SACKMERGED,
+	LINUX_MIB_SACKSHIFTFALLBACK,
 	__LINUX_MIB_MAX
 };
 
diff --git a/include/linux/spi/orion_spi.h b/include/linux/spi/orion_spi.h
index b4d9fa6f797c..decf6d8c77b7 100644
--- a/include/linux/spi/orion_spi.h
+++ b/include/linux/spi/orion_spi.h
@@ -11,6 +11,7 @@
 
 struct orion_spi_info {
 	u32	tclk;		/* no <linux/clk.h> support yet */
+	u32	enable_clock_fix;
 };
 
 
diff --git a/include/linux/spi/spi_bitbang.h b/include/linux/spi/spi_bitbang.h
index b8db32cea1de..bf8de281b4ed 100644
--- a/include/linux/spi/spi_bitbang.h
+++ b/include/linux/spi/spi_bitbang.h
@@ -18,6 +18,9 @@
  *	duplex (MicroWire) controllers.  Provide chipslect() and txrx_bufs(),
  *	and custom setup()/cleanup() methods.
  */
+
+#include <linux/workqueue.h>
+
 struct spi_bitbang {
 	struct workqueue_struct	*workqueue;
 	struct work_struct	work;
diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h
index e530026eedf7..17d9b58f6379 100644
--- a/include/linux/ssb/ssb.h
+++ b/include/linux/ssb/ssb.h
@@ -427,12 +427,16 @@ static inline int ssb_dma_mapping_error(struct ssb_device *dev, dma_addr_t addr)
 {
 	switch (dev->bus->bustype) {
 	case SSB_BUSTYPE_PCI:
+#ifdef CONFIG_SSB_PCIHOST
 		return pci_dma_mapping_error(dev->bus->host_pci, addr);
+#endif
+		break;
 	case SSB_BUSTYPE_SSB:
 		return dma_mapping_error(dev->dev, addr);
 	default:
-		__ssb_dma_not_implemented(dev);
+		break;
 	}
+	__ssb_dma_not_implemented(dev);
 	return -ENOSYS;
 }
 
@@ -441,12 +445,16 @@ static inline dma_addr_t ssb_dma_map_single(struct ssb_device *dev, void *p,
 {
 	switch (dev->bus->bustype) {
 	case SSB_BUSTYPE_PCI:
+#ifdef CONFIG_SSB_PCIHOST
 		return pci_map_single(dev->bus->host_pci, p, size, dir);
+#endif
+		break;
 	case SSB_BUSTYPE_SSB:
 		return dma_map_single(dev->dev, p, size, dir);
 	default:
-		__ssb_dma_not_implemented(dev);
+		break;
 	}
+	__ssb_dma_not_implemented(dev);
 	return 0;
 }
 
@@ -455,14 +463,18 @@ static inline void ssb_dma_unmap_single(struct ssb_device *dev, dma_addr_t dma_a
 {
 	switch (dev->bus->bustype) {
 	case SSB_BUSTYPE_PCI:
+#ifdef CONFIG_SSB_PCIHOST
 		pci_unmap_single(dev->bus->host_pci, dma_addr, size, dir);
 		return;
+#endif
+		break;
 	case SSB_BUSTYPE_SSB:
 		dma_unmap_single(dev->dev, dma_addr, size, dir);
 		return;
 	default:
-		__ssb_dma_not_implemented(dev);
+		break;
 	}
+	__ssb_dma_not_implemented(dev);
 }
 
 static inline void ssb_dma_sync_single_for_cpu(struct ssb_device *dev,
@@ -472,15 +484,19 @@ static inline void ssb_dma_sync_single_for_cpu(struct ssb_device *dev,
 {
 	switch (dev->bus->bustype) {
 	case SSB_BUSTYPE_PCI:
+#ifdef CONFIG_SSB_PCIHOST
 		pci_dma_sync_single_for_cpu(dev->bus->host_pci, dma_addr,
 					    size, dir);
 		return;
+#endif
+		break;
 	case SSB_BUSTYPE_SSB:
 		dma_sync_single_for_cpu(dev->dev, dma_addr, size, dir);
 		return;
 	default:
-		__ssb_dma_not_implemented(dev);
+		break;
 	}
+	__ssb_dma_not_implemented(dev);
 }
 
 static inline void ssb_dma_sync_single_for_device(struct ssb_device *dev,
@@ -490,15 +506,19 @@ static inline void ssb_dma_sync_single_for_device(struct ssb_device *dev,
 {
 	switch (dev->bus->bustype) {
 	case SSB_BUSTYPE_PCI:
+#ifdef CONFIG_SSB_PCIHOST
 		pci_dma_sync_single_for_device(dev->bus->host_pci, dma_addr,
 					       size, dir);
 		return;
+#endif
+		break;
 	case SSB_BUSTYPE_SSB:
 		dma_sync_single_for_device(dev->dev, dma_addr, size, dir);
 		return;
 	default:
-		__ssb_dma_not_implemented(dev);
+		break;
 	}
+	__ssb_dma_not_implemented(dev);
 }
 
 static inline void ssb_dma_sync_single_range_for_cpu(struct ssb_device *dev,
@@ -509,17 +529,21 @@ static inline void ssb_dma_sync_single_range_for_cpu(struct ssb_device *dev,
 {
 	switch (dev->bus->bustype) {
 	case SSB_BUSTYPE_PCI:
+#ifdef CONFIG_SSB_PCIHOST
 		/* Just sync everything. That's all the PCI API can do. */
 		pci_dma_sync_single_for_cpu(dev->bus->host_pci, dma_addr,
 					    offset + size, dir);
 		return;
+#endif
+		break;
 	case SSB_BUSTYPE_SSB:
 		dma_sync_single_range_for_cpu(dev->dev, dma_addr, offset,
 					      size, dir);
 		return;
 	default:
-		__ssb_dma_not_implemented(dev);
+		break;
 	}
+	__ssb_dma_not_implemented(dev);
 }
 
 static inline void ssb_dma_sync_single_range_for_device(struct ssb_device *dev,
@@ -530,17 +554,21 @@ static inline void ssb_dma_sync_single_range_for_device(struct ssb_device *dev,
 {
 	switch (dev->bus->bustype) {
 	case SSB_BUSTYPE_PCI:
+#ifdef CONFIG_SSB_PCIHOST
 		/* Just sync everything. That's all the PCI API can do. */
 		pci_dma_sync_single_for_device(dev->bus->host_pci, dma_addr,
 					       offset + size, dir);
 		return;
+#endif
+		break;
 	case SSB_BUSTYPE_SSB:
 		dma_sync_single_range_for_device(dev->dev, dma_addr, offset,
 						 size, dir);
 		return;
 	default:
-		__ssb_dma_not_implemented(dev);
+		break;
 	}
+	__ssb_dma_not_implemented(dev);
 }
 
 
diff --git a/include/linux/stacktrace.h b/include/linux/stacktrace.h
index b106fd8e0d5c..1a8cecc4f38c 100644
--- a/include/linux/stacktrace.h
+++ b/include/linux/stacktrace.h
@@ -15,9 +15,17 @@ extern void save_stack_trace_tsk(struct task_struct *tsk,
 				struct stack_trace *trace);
 
 extern void print_stack_trace(struct stack_trace *trace, int spaces);
+
+#ifdef CONFIG_USER_STACKTRACE_SUPPORT
+extern void save_stack_trace_user(struct stack_trace *trace);
+#else
+# define save_stack_trace_user(trace)              do { } while (0)
+#endif
+
 #else
 # define save_stack_trace(trace)			do { } while (0)
 # define save_stack_trace_tsk(tsk, trace)		do { } while (0)
+# define save_stack_trace_user(trace)			do { } while (0)
 # define print_stack_trace(trace, spaces)		do { } while (0)
 #endif
 
diff --git a/include/linux/string.h b/include/linux/string.h
index 810d80df0a1d..d18fc198aa2f 100644
--- a/include/linux/string.h
+++ b/include/linux/string.h
@@ -1,7 +1,7 @@
 #ifndef _LINUX_STRING_H_
 #define _LINUX_STRING_H_
 
-/* We don't want strings.h stuff being user by user stuff by accident */
+/* We don't want strings.h stuff being used by user stuff by accident */
 
 #ifndef __KERNEL__
 #include <string.h>
diff --git a/include/linux/sunrpc/clnt.h b/include/linux/sunrpc/clnt.h
index 6f0ee1b84a4f..c39a21040dcb 100644
--- a/include/linux/sunrpc/clnt.h
+++ b/include/linux/sunrpc/clnt.h
@@ -58,6 +58,7 @@ struct rpc_clnt {
 	struct rpc_timeout	cl_timeout_default;
 	struct rpc_program *	cl_program;
 	char			cl_inline_name[32];
+	char			*cl_principal;	/* target to authenticate to */
 };
 
 /*
@@ -108,6 +109,7 @@ struct rpc_create_args {
 	u32			version;
 	rpc_authflavor_t	authflavor;
 	unsigned long		flags;
+	char			*client_name;
 };
 
 /* Values for "flags" field */
diff --git a/include/linux/sunrpc/rpc_pipe_fs.h b/include/linux/sunrpc/rpc_pipe_fs.h
index 51b977a4ca20..cea764c2359f 100644
--- a/include/linux/sunrpc/rpc_pipe_fs.h
+++ b/include/linux/sunrpc/rpc_pipe_fs.h
@@ -15,6 +15,7 @@ struct rpc_pipe_ops {
 	ssize_t (*upcall)(struct file *, struct rpc_pipe_msg *, char __user *, size_t);
 	ssize_t (*downcall)(struct file *, const char __user *, size_t);
 	void (*release_pipe)(struct inode *);
+	int (*open_pipe)(struct inode *);
 	void (*destroy_msg)(struct rpc_pipe_msg *);
 };
 
diff --git a/include/linux/sunrpc/svc_xprt.h b/include/linux/sunrpc/svc_xprt.h
index 6fd7b016517f..0127daca4354 100644
--- a/include/linux/sunrpc/svc_xprt.h
+++ b/include/linux/sunrpc/svc_xprt.h
@@ -139,14 +139,14 @@ static inline char *__svc_print_addr(struct sockaddr *addr,
 {
 	switch (addr->sa_family) {
 	case AF_INET:
-		snprintf(buf, len, "%u.%u.%u.%u, port=%u",
-			NIPQUAD(((struct sockaddr_in *) addr)->sin_addr),
+		snprintf(buf, len, "%pI4, port=%u",
+			&((struct sockaddr_in *)addr)->sin_addr,
 			ntohs(((struct sockaddr_in *) addr)->sin_port));
 		break;
 
 	case AF_INET6:
-		snprintf(buf, len, "%x:%x:%x:%x:%x:%x:%x:%x, port=%u",
-			NIP6(((struct sockaddr_in6 *) addr)->sin6_addr),
+		snprintf(buf, len, "%pI6, port=%u",
+			 &((struct sockaddr_in6 *)addr)->sin6_addr,
 			ntohs(((struct sockaddr_in6 *) addr)->sin6_port));
 		break;
 
diff --git a/include/linux/sunrpc/svcauth_gss.h b/include/linux/sunrpc/svcauth_gss.h
index c9165d9771a8..ca7d725861fc 100644
--- a/include/linux/sunrpc/svcauth_gss.h
+++ b/include/linux/sunrpc/svcauth_gss.h
@@ -20,6 +20,7 @@ int gss_svc_init(void);
 void gss_svc_shutdown(void);
 int svcauth_gss_register_pseudoflavor(u32 pseudoflavor, char * name);
 u32 svcauth_gss_flavor(struct auth_domain *dom);
+char *svc_gss_principal(struct svc_rqst *);
 
 #endif /* __KERNEL__ */
 #endif /* _LINUX_SUNRPC_SVCAUTH_GSS_H */
diff --git a/include/linux/sunrpc/xdr.h b/include/linux/sunrpc/xdr.h
index e4057d729f03..49e1eb454465 100644
--- a/include/linux/sunrpc/xdr.h
+++ b/include/linux/sunrpc/xdr.h
@@ -37,21 +37,6 @@ struct xdr_netobj {
 typedef int	(*kxdrproc_t)(void *rqstp, __be32 *data, void *obj);
 
 /*
- * We're still requiring the BKL in the xdr code until it's been
- * more carefully audited, at which point this wrapper will become
- * unnecessary.
- */
-static inline int rpc_call_xdrproc(kxdrproc_t xdrproc, void *rqstp, __be32 *data, void *obj)
-{
-	int ret;
-
-	lock_kernel();
-	ret = xdrproc(rqstp, data, obj);
-	unlock_kernel();
-	return ret;
-}
-
-/*
  * Basic structure for transmission/reception of a client XDR message.
  * Features a header (for a linear buffer containing RPC headers
  * and the data payload for short messages), and then an array of
diff --git a/include/linux/sunrpc/xprt.h b/include/linux/sunrpc/xprt.h
index 4d80a118d538..11fc71d50c1e 100644
--- a/include/linux/sunrpc/xprt.h
+++ b/include/linux/sunrpc/xprt.h
@@ -76,8 +76,7 @@ struct rpc_rqst {
 	struct list_head	rq_list;
 
 	__u32 *			rq_buffer;	/* XDR encode buffer */
-	size_t			rq_bufsize,
-				rq_callsize,
+	size_t			rq_callsize,
 				rq_rcvsize;
 
 	struct xdr_buf		rq_private_buf;		/* The receive buffer
diff --git a/include/linux/sunrpc/xprtrdma.h b/include/linux/sunrpc/xprtrdma.h
index 4de56b1d372b..54a379c9e8eb 100644
--- a/include/linux/sunrpc/xprtrdma.h
+++ b/include/linux/sunrpc/xprtrdma.h
@@ -66,9 +66,6 @@
 
 #define RPCRDMA_INLINE_PAD_THRESH  (512)/* payload threshold to pad (bytes) */
 
-#define RDMA_RESOLVE_TIMEOUT	(5*HZ)	/* TBD 5 seconds */
-#define RDMA_CONNECT_RETRY_MAX	(2)	/* retries if no listener backlog */
-
 /* memory registration strategies */
 #define RPCRDMA_PERSISTENT_REGISTRATION (1)
 
@@ -78,6 +75,7 @@ enum rpcrdma_memreg {
 	RPCRDMA_MEMWINDOWS,
 	RPCRDMA_MEMWINDOWS_ASYNC,
 	RPCRDMA_MTHCAFMR,
+	RPCRDMA_FRMR,
 	RPCRDMA_ALLPHYSICAL,
 	RPCRDMA_LAST
 };
diff --git a/include/linux/swab.h b/include/linux/swab.h
index 270d5c208a89..bbed279f3b32 100644
--- a/include/linux/swab.h
+++ b/include/linux/swab.h
@@ -47,8 +47,6 @@ static inline __attribute_const__ __u16 ___swab16(__u16 val)
 {
 #ifdef __arch_swab16
 	return __arch_swab16(val);
-#elif defined(__arch_swab16p)
-	return __arch_swab16p(&val);
 #else
 	return __const_swab16(val);
 #endif
@@ -58,8 +56,6 @@ static inline __attribute_const__ __u32 ___swab32(__u32 val)
 {
 #ifdef __arch_swab32
 	return __arch_swab32(val);
-#elif defined(__arch_swab32p)
-	return __arch_swab32p(&val);
 #else
 	return __const_swab32(val);
 #endif
@@ -69,8 +65,6 @@ static inline __attribute_const__ __u64 ___swab64(__u64 val)
 {
 #ifdef __arch_swab64
 	return __arch_swab64(val);
-#elif defined(__arch_swab64p)
-	return __arch_swab64p(&val);
 #elif defined(__SWAB_64_THRU_32__)
 	__u32 h = val >> 32;
 	__u32 l = val & ((1ULL << 32) - 1);
@@ -84,8 +78,6 @@ static inline __attribute_const__ __u32 ___swahw32(__u32 val)
 {
 #ifdef __arch_swahw32
 	return __arch_swahw32(val);
-#elif defined(__arch_swahw32p)
-	return __arch_swahw32p(&val);
 #else
 	return __const_swahw32(val);
 #endif
@@ -95,8 +87,6 @@ static inline __attribute_const__ __u32 ___swahb32(__u32 val)
 {
 #ifdef __arch_swahb32
 	return __arch_swahb32(val);
-#elif defined(__arch_swahb32p)
-	return __arch_swahb32p(&val);
 #else
 	return __const_swahb32(val);
 #endif
diff --git a/include/linux/swap.h b/include/linux/swap.h
index de40f169a4e4..a3af95b2cb6d 100644
--- a/include/linux/swap.h
+++ b/include/linux/swap.h
@@ -7,6 +7,7 @@
 #include <linux/list.h>
 #include <linux/memcontrol.h>
 #include <linux/sched.h>
+#include <linux/node.h>
 
 #include <asm/atomic.h>
 #include <asm/page.h>
@@ -171,8 +172,10 @@ extern unsigned int nr_free_pagecache_pages(void);
 
 
 /* linux/mm/swap.c */
-extern void lru_cache_add(struct page *);
-extern void lru_cache_add_active(struct page *);
+extern void __lru_cache_add(struct page *, enum lru_list lru);
+extern void lru_cache_add_lru(struct page *, enum lru_list lru);
+extern void lru_cache_add_active_or_unevictable(struct page *,
+					struct vm_area_struct *);
 extern void activate_page(struct page *);
 extern void mark_page_accessed(struct page *);
 extern void lru_add_drain(void);
@@ -180,12 +183,38 @@ extern int lru_add_drain_all(void);
 extern void rotate_reclaimable_page(struct page *page);
 extern void swap_setup(void);
 
+extern void add_page_to_unevictable_list(struct page *page);
+
+/**
+ * lru_cache_add: add a page to the page lists
+ * @page: the page to add
+ */
+static inline void lru_cache_add_anon(struct page *page)
+{
+	__lru_cache_add(page, LRU_INACTIVE_ANON);
+}
+
+static inline void lru_cache_add_active_anon(struct page *page)
+{
+	__lru_cache_add(page, LRU_ACTIVE_ANON);
+}
+
+static inline void lru_cache_add_file(struct page *page)
+{
+	__lru_cache_add(page, LRU_INACTIVE_FILE);
+}
+
+static inline void lru_cache_add_active_file(struct page *page)
+{
+	__lru_cache_add(page, LRU_ACTIVE_FILE);
+}
+
 /* linux/mm/vmscan.c */
 extern unsigned long try_to_free_pages(struct zonelist *zonelist, int order,
 					gfp_t gfp_mask);
 extern unsigned long try_to_free_mem_cgroup_pages(struct mem_cgroup *mem,
 							gfp_t gfp_mask);
-extern int __isolate_lru_page(struct page *page, int mode);
+extern int __isolate_lru_page(struct page *page, int mode, int file);
 extern unsigned long shrink_all_memory(unsigned long nr_pages);
 extern int vm_swappiness;
 extern int remove_mapping(struct address_space *mapping, struct page *page);
@@ -204,6 +233,34 @@ static inline int zone_reclaim(struct zone *z, gfp_t mask, unsigned int order)
 }
 #endif
 
+#ifdef CONFIG_UNEVICTABLE_LRU
+extern int page_evictable(struct page *page, struct vm_area_struct *vma);
+extern void scan_mapping_unevictable_pages(struct address_space *);
+
+extern unsigned long scan_unevictable_pages;
+extern int scan_unevictable_handler(struct ctl_table *, int, struct file *,
+					void __user *, size_t *, loff_t *);
+extern int scan_unevictable_register_node(struct node *node);
+extern void scan_unevictable_unregister_node(struct node *node);
+#else
+static inline int page_evictable(struct page *page,
+						struct vm_area_struct *vma)
+{
+	return 1;
+}
+
+static inline void scan_mapping_unevictable_pages(struct address_space *mapping)
+{
+}
+
+static inline int scan_unevictable_register_node(struct node *node)
+{
+	return 0;
+}
+
+static inline void scan_unevictable_unregister_node(struct node *node) { }
+#endif
+
 extern int kswapd_run(int nid);
 
 #ifdef CONFIG_MMU
@@ -251,6 +308,7 @@ extern sector_t swapdev_block(int, pgoff_t);
 extern struct swap_info_struct *get_swap_info_struct(unsigned);
 extern int can_share_swap_page(struct page *);
 extern int remove_exclusive_swap_page(struct page *);
+extern int remove_exclusive_swap_page_ref(struct page *);
 struct backing_dev_info;
 
 /* linux/mm/thrash.c */
@@ -339,6 +397,11 @@ static inline int remove_exclusive_swap_page(struct page *p)
 	return 0;
 }
 
+static inline int remove_exclusive_swap_page_ref(struct page *page)
+{
+	return 0;
+}
+
 static inline swp_entry_t get_swap_page(void)
 {
 	swp_entry_t entry;
diff --git a/include/linux/swiotlb.h b/include/linux/swiotlb.h
new file mode 100644
index 000000000000..325af1de0351
--- /dev/null
+++ b/include/linux/swiotlb.h
@@ -0,0 +1,105 @@
+#ifndef __LINUX_SWIOTLB_H
+#define __LINUX_SWIOTLB_H
+
+#include <linux/types.h>
+
+struct device;
+struct dma_attrs;
+struct scatterlist;
+
+/*
+ * Maximum allowable number of contiguous slabs to map,
+ * must be a power of 2.  What is the appropriate value ?
+ * The complexity of {map,unmap}_single is linearly dependent on this value.
+ */
+#define IO_TLB_SEGSIZE	128
+
+
+/*
+ * log of the size of each IO TLB slab.  The number of slabs is command line
+ * controllable.
+ */
+#define IO_TLB_SHIFT 11
+
+extern void
+swiotlb_init(void);
+
+extern void *swiotlb_alloc_boot(size_t bytes, unsigned long nslabs);
+extern void *swiotlb_alloc(unsigned order, unsigned long nslabs);
+
+extern dma_addr_t swiotlb_phys_to_bus(phys_addr_t address);
+extern phys_addr_t swiotlb_bus_to_phys(dma_addr_t address);
+
+extern int swiotlb_arch_range_needs_mapping(void *ptr, size_t size);
+
+extern void
+*swiotlb_alloc_coherent(struct device *hwdev, size_t size,
+			dma_addr_t *dma_handle, gfp_t flags);
+
+extern void
+swiotlb_free_coherent(struct device *hwdev, size_t size,
+		      void *vaddr, dma_addr_t dma_handle);
+
+extern dma_addr_t
+swiotlb_map_single(struct device *hwdev, void *ptr, size_t size, int dir);
+
+extern void
+swiotlb_unmap_single(struct device *hwdev, dma_addr_t dev_addr,
+		     size_t size, int dir);
+
+extern dma_addr_t
+swiotlb_map_single_attrs(struct device *hwdev, void *ptr, size_t size,
+			 int dir, struct dma_attrs *attrs);
+
+extern void
+swiotlb_unmap_single_attrs(struct device *hwdev, dma_addr_t dev_addr,
+			   size_t size, int dir, struct dma_attrs *attrs);
+
+extern int
+swiotlb_map_sg(struct device *hwdev, struct scatterlist *sg, int nents,
+	       int direction);
+
+extern void
+swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sg, int nents,
+		 int direction);
+
+extern int
+swiotlb_map_sg_attrs(struct device *hwdev, struct scatterlist *sgl, int nelems,
+		     int dir, struct dma_attrs *attrs);
+
+extern void
+swiotlb_unmap_sg_attrs(struct device *hwdev, struct scatterlist *sgl,
+		       int nelems, int dir, struct dma_attrs *attrs);
+
+extern void
+swiotlb_sync_single_for_cpu(struct device *hwdev, dma_addr_t dev_addr,
+			    size_t size, int dir);
+
+extern void
+swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg,
+			int nelems, int dir);
+
+extern void
+swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr,
+			       size_t size, int dir);
+
+extern void
+swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg,
+			   int nelems, int dir);
+
+extern void
+swiotlb_sync_single_range_for_cpu(struct device *hwdev, dma_addr_t dev_addr,
+				  unsigned long offset, size_t size, int dir);
+
+extern void
+swiotlb_sync_single_range_for_device(struct device *hwdev, dma_addr_t dev_addr,
+				     unsigned long offset, size_t size,
+				     int dir);
+
+extern int
+swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t dma_addr);
+
+extern int
+swiotlb_dma_supported(struct device *hwdev, u64 mask);
+
+#endif /* __LINUX_SWIOTLB_H */
diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h
index d6ff145919ca..04fb47bfb920 100644
--- a/include/linux/syscalls.h
+++ b/include/linux/syscalls.h
@@ -410,8 +410,7 @@ asmlinkage long sys_getsockopt(int fd, int level, int optname,
 asmlinkage long sys_bind(int, struct sockaddr __user *, int);
 asmlinkage long sys_connect(int, struct sockaddr __user *, int);
 asmlinkage long sys_accept(int, struct sockaddr __user *, int __user *);
-asmlinkage long sys_paccept(int, struct sockaddr __user *, int __user *,
-			    const __user sigset_t *, size_t, int);
+asmlinkage long sys_accept4(int, struct sockaddr __user *, int __user *, int);
 asmlinkage long sys_getsockname(int, struct sockaddr __user *, int __user *);
 asmlinkage long sys_getpeername(int, struct sockaddr __user *, int __user *);
 asmlinkage long sys_send(int, void __user *, size_t, unsigned);
diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h
index d0437f36921f..39d471d1163b 100644
--- a/include/linux/sysctl.h
+++ b/include/linux/sysctl.h
@@ -972,7 +972,7 @@ extern int sysctl_perm(struct ctl_table_root *root,
 
 typedef struct ctl_table ctl_table;
 
-typedef int ctl_handler (struct ctl_table *table, int __user *name, int nlen,
+typedef int ctl_handler (struct ctl_table *table,
 			 void __user *oldval, size_t __user *oldlenp,
 			 void __user *newval, size_t newlen);
 
diff --git a/include/linux/sysfs.h b/include/linux/sysfs.h
index 37fa24152bd8..9d68fed50f11 100644
--- a/include/linux/sysfs.h
+++ b/include/linux/sysfs.h
@@ -21,8 +21,9 @@ struct kobject;
 struct module;
 
 /* FIXME
- * The *owner field is no longer used, but leave around
- * until the tree gets cleaned up fully.
+ * The *owner field is no longer used.
+ * x86 tree has been cleaned up. The owner
+ * attribute is still left for other arches.
  */
 struct attribute {
 	const char		*name;
@@ -78,6 +79,8 @@ struct sysfs_ops {
 	ssize_t	(*store)(struct kobject *,struct attribute *,const char *, size_t);
 };
 
+struct sysfs_dirent;
+
 #ifdef CONFIG_SYSFS
 
 int sysfs_schedule_callback(struct kobject *kobj, void (*func)(void *),
@@ -117,9 +120,14 @@ int sysfs_add_file_to_group(struct kobject *kobj,
 void sysfs_remove_file_from_group(struct kobject *kobj,
 			const struct attribute *attr, const char *group);
 
-void sysfs_notify(struct kobject *kobj, char *dir, char *attr);
-
-extern int __must_check sysfs_init(void);
+void sysfs_notify(struct kobject *kobj, const char *dir, const char *attr);
+void sysfs_notify_dirent(struct sysfs_dirent *sd);
+struct sysfs_dirent *sysfs_get_dirent(struct sysfs_dirent *parent_sd,
+				      const unsigned char *name);
+struct sysfs_dirent *sysfs_get(struct sysfs_dirent *sd);
+void sysfs_put(struct sysfs_dirent *sd);
+void sysfs_printk_last_file(void);
+int __must_check sysfs_init(void);
 
 #else /* CONFIG_SYSFS */
 
@@ -222,7 +230,24 @@ static inline void sysfs_remove_file_from_group(struct kobject *kobj,
 {
 }
 
-static inline void sysfs_notify(struct kobject *kobj, char *dir, char *attr)
+static inline void sysfs_notify(struct kobject *kobj, const char *dir,
+				const char *attr)
+{
+}
+static inline void sysfs_notify_dirent(struct sysfs_dirent *sd)
+{
+}
+static inline
+struct sysfs_dirent *sysfs_get_dirent(struct sysfs_dirent *parent_sd,
+				      const unsigned char *name)
+{
+	return NULL;
+}
+static inline struct sysfs_dirent *sysfs_get(struct sysfs_dirent *sd)
+{
+	return NULL;
+}
+static inline void sysfs_put(struct sysfs_dirent *sd)
 {
 }
 
@@ -231,6 +256,10 @@ static inline int __must_check sysfs_init(void)
 	return 0;
 }
 
+static inline void sysfs_printk_last_file(void)
+{
+}
+
 #endif /* CONFIG_SYSFS */
 
 #endif /* _SYSFS_H_ */
diff --git a/include/linux/task_io_accounting.h b/include/linux/task_io_accounting.h
index 5e88afc9a2fb..bdf855c2856f 100644
--- a/include/linux/task_io_accounting.h
+++ b/include/linux/task_io_accounting.h
@@ -5,7 +5,7 @@
  * Don't include this header file directly - it is designed to be dragged in via
  * sched.h.
  *
- * Blame akpm@osdl.org for all this.
+ * Blame Andrew Morton for all this.
  */
 
 struct task_io_accounting {
diff --git a/include/linux/telephony.h b/include/linux/telephony.h
index 0d0cf2a1e7bc..f63afe330add 100644
--- a/include/linux/telephony.h
+++ b/include/linux/telephony.h
@@ -14,7 +14,7 @@
  *    Authors:       Ed Okerson, <eokerson@quicknet.net>
  *                   Greg Herlein, <gherlein@quicknet.net>
  *
- *    Contributors:  Alan Cox, <alan@redhat.com>
+ *    Contributors:  Alan Cox, <alan@lxorguk.ukuu.org.uk>
  *                   David W. Erhart, <derhart@quicknet.net>
  *
  * IN NO EVENT SHALL QUICKNET TECHNOLOGIES, INC. BE LIABLE TO ANY PARTY FOR
@@ -28,10 +28,6 @@
  * ON AN "AS IS" BASIS, AND QUICKNET TECHNOLOGIES, INC. HAS NO OBLIGATION
  * TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
  *
- * Version:       $Revision: 4.2 $
- *
- * $Id: telephony.h,v 4.2 2001/08/06 07:09:43 craigs Exp $
- *
  *****************************************************************************/
 
 #ifndef TELEPHONY_H
diff --git a/include/linux/thread_info.h b/include/linux/thread_info.h
index 38a56477f27a..e6b820f8b56b 100644
--- a/include/linux/thread_info.h
+++ b/include/linux/thread_info.h
@@ -38,6 +38,14 @@ struct restart_block {
 #endif
 			u64 expires;
 		} nanosleep;
+		/* For poll */
+		struct {
+			struct pollfd __user *ufds;
+			int nfds;
+			int has_timeout;
+			unsigned long tv_sec;
+			unsigned long tv_nsec;
+		} poll;
 	};
 };
 
diff --git a/include/linux/tick.h b/include/linux/tick.h
index 98921a3e1aa8..b6ec8189ac0c 100644
--- a/include/linux/tick.h
+++ b/include/linux/tick.h
@@ -96,9 +96,11 @@ extern cpumask_t *tick_get_broadcast_oneshot_mask(void);
 extern void tick_clock_notify(void);
 extern int tick_check_oneshot_change(int allow_nohz);
 extern struct tick_sched *tick_get_tick_sched(int cpu);
+extern void tick_check_idle(int cpu);
 # else
 static inline void tick_clock_notify(void) { }
 static inline int tick_check_oneshot_change(int allow_nohz) { return 0; }
+static inline void tick_check_idle(int cpu) { }
 # endif
 
 #else /* CONFIG_GENERIC_CLOCKEVENTS */
@@ -106,26 +108,23 @@ static inline void tick_init(void) { }
 static inline void tick_cancel_sched_timer(int cpu) { }
 static inline void tick_clock_notify(void) { }
 static inline int tick_check_oneshot_change(int allow_nohz) { return 0; }
+static inline void tick_check_idle(int cpu) { }
 #endif /* !CONFIG_GENERIC_CLOCKEVENTS */
 
 # ifdef CONFIG_NO_HZ
 extern void tick_nohz_stop_sched_tick(int inidle);
 extern void tick_nohz_restart_sched_tick(void);
-extern void tick_nohz_update_jiffies(void);
 extern ktime_t tick_nohz_get_sleep_length(void);
-extern void tick_nohz_stop_idle(int cpu);
 extern u64 get_cpu_idle_time_us(int cpu, u64 *last_update_time);
 # else
 static inline void tick_nohz_stop_sched_tick(int inidle) { }
 static inline void tick_nohz_restart_sched_tick(void) { }
-static inline void tick_nohz_update_jiffies(void) { }
 static inline ktime_t tick_nohz_get_sleep_length(void)
 {
 	ktime_t len = { .tv64 = NSEC_PER_SEC/HZ };
 
 	return len;
 }
-static inline void tick_nohz_stop_idle(int cpu) { }
 static inline u64 get_cpu_idle_time_us(int cpu, u64 *unused) { return -1; }
 # endif /* !NO_HZ */
 
diff --git a/include/linux/time.h b/include/linux/time.h
index e15206a7e82e..ce321ac5c8f8 100644
--- a/include/linux/time.h
+++ b/include/linux/time.h
@@ -29,6 +29,8 @@ struct timezone {
 
 #ifdef __KERNEL__
 
+extern struct timezone sys_tz;
+
 /* Parameters used to convert the timespec values: */
 #define MSEC_PER_SEC	1000L
 #define USEC_PER_MSEC	1000L
@@ -38,6 +40,8 @@ struct timezone {
 #define NSEC_PER_SEC	1000000000L
 #define FSEC_PER_SEC	1000000000000000L
 
+#define TIME_T_MAX	(time_t)((1UL << ((sizeof(time_t) << 3) - 1)) - 1)
+
 static inline int timespec_equal(const struct timespec *a,
                                  const struct timespec *b)
 {
@@ -72,6 +76,8 @@ extern unsigned long mktime(const unsigned int year, const unsigned int mon,
 			    const unsigned int min, const unsigned int sec);
 
 extern void set_normalized_timespec(struct timespec *ts, time_t sec, long nsec);
+extern struct timespec timespec_add_safe(const struct timespec lhs,
+					 const struct timespec rhs);
 
 /*
  * sub = lhs - rhs, in normalized form
@@ -117,6 +123,7 @@ extern int do_setitimer(int which, struct itimerval *value,
 extern unsigned int alarm_setitimer(unsigned int seconds);
 extern int do_getitimer(int which, struct itimerval *value);
 extern void getnstimeofday(struct timespec *tv);
+extern void getrawmonotonic(struct timespec *ts);
 extern void getboottime(struct timespec *ts);
 extern void monotonic_to_bootbased(struct timespec *ts);
 
@@ -125,6 +132,9 @@ extern int timekeeping_valid_for_hres(void);
 extern void update_wall_time(void);
 extern void update_xtime_cache(u64 nsec);
 
+struct tms;
+extern void do_sys_times(struct tms *);
+
 /**
  * timespec_to_ns - Convert timespec to nanoseconds
  * @ts:		pointer to the timespec variable to be converted
@@ -214,6 +224,7 @@ struct itimerval {
 #define CLOCK_MONOTONIC			1
 #define CLOCK_PROCESS_CPUTIME_ID	2
 #define CLOCK_THREAD_CPUTIME_ID		3
+#define CLOCK_MONOTONIC_RAW		4
 
 /*
  * The IDs of various hardware clocks:
diff --git a/include/linux/timer.h b/include/linux/timer.h
index d4ba79248a27..daf9685b861c 100644
--- a/include/linux/timer.h
+++ b/include/linux/timer.h
@@ -186,4 +186,9 @@ unsigned long __round_jiffies_relative(unsigned long j, int cpu);
 unsigned long round_jiffies(unsigned long j);
 unsigned long round_jiffies_relative(unsigned long j);
 
+unsigned long __round_jiffies_up(unsigned long j, int cpu);
+unsigned long __round_jiffies_up_relative(unsigned long j, int cpu);
+unsigned long round_jiffies_up(unsigned long j);
+unsigned long round_jiffies_up_relative(unsigned long j);
+
 #endif
diff --git a/include/linux/timex.h b/include/linux/timex.h
index fc6035d29d56..998a55d80acf 100644
--- a/include/linux/timex.h
+++ b/include/linux/timex.h
@@ -53,47 +53,11 @@
 #ifndef _LINUX_TIMEX_H
 #define _LINUX_TIMEX_H
 
-#include <linux/compiler.h>
 #include <linux/time.h>
 
-#include <asm/param.h>
-
 #define NTP_API		4	/* NTP API version */
 
 /*
- * SHIFT_KG and SHIFT_KF establish the damping of the PLL and are chosen
- * for a slightly underdamped convergence characteristic. SHIFT_KH
- * establishes the damping of the FLL and is chosen by wisdom and black
- * art.
- *
- * MAXTC establishes the maximum time constant of the PLL. With the
- * SHIFT_KG and SHIFT_KF values given and a time constant range from
- * zero to MAXTC, the PLL will converge in 15 minutes to 16 hours,
- * respectively.
- */
-#define SHIFT_PLL	4	/* PLL frequency factor (shift) */
-#define SHIFT_FLL	2	/* FLL frequency factor (shift) */
-#define MAXTC		10	/* maximum time constant (shift) */
-
-/*
- * SHIFT_USEC defines the scaling (shift) of the time_freq and
- * time_tolerance variables, which represent the current frequency
- * offset and maximum frequency tolerance.
- */
-#define SHIFT_USEC 16		/* frequency offset scale (shift) */
-#define PPM_SCALE (NSEC_PER_USEC << (NTP_SCALE_SHIFT - SHIFT_USEC))
-#define PPM_SCALE_INV_SHIFT 20
-#define PPM_SCALE_INV ((1ll << (PPM_SCALE_INV_SHIFT + NTP_SCALE_SHIFT)) / \
-		       PPM_SCALE + 1)
-
-#define MAXPHASE 500000000l	/* max phase error (ns) */
-#define MAXFREQ 500000		/* max frequency error (ns/s) */
-#define MAXFREQ_SCALED ((s64)MAXFREQ << NTP_SCALE_SHIFT)
-#define MINSEC 256		/* min interval between updates (s) */
-#define MAXSEC 2048		/* max interval between updates (s) */
-#define NTP_PHASE_LIMIT ((MAXPHASE / NSEC_PER_USEC) << 5) /* beyond max. dispersion */
-
-/*
  * syscall interface - used (mainly by NTP daemon)
  * to discipline kernel clock oscillator
  */
@@ -141,8 +105,15 @@ struct timex {
 #define ADJ_MICRO		0x1000	/* select microsecond resolution */
 #define ADJ_NANO		0x2000	/* select nanosecond resolution */
 #define ADJ_TICK		0x4000	/* tick value */
+
+#ifdef __KERNEL__
+#define ADJ_ADJTIME		0x8000	/* switch between adjtime/adjtimex modes */
+#define ADJ_OFFSET_SINGLESHOT	0x0001	/* old-fashioned adjtime */
+#define ADJ_OFFSET_READONLY	0x2000	/* read-only adjtime */
+#else
 #define ADJ_OFFSET_SINGLESHOT	0x8001	/* old-fashioned adjtime */
-#define ADJ_OFFSET_SS_READ	0xa001  /* read-only adjtime */
+#define ADJ_OFFSET_SS_READ	0xa001	/* read-only adjtime */
+#endif
 
 /* xntp 3.4 compatibility names */
 #define MOD_OFFSET	ADJ_OFFSET
@@ -192,9 +163,46 @@ struct timex {
 #define TIME_BAD	TIME_ERROR /* bw compat */
 
 #ifdef __KERNEL__
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/param.h>
+
 #include <asm/timex.h>
 
 /*
+ * SHIFT_KG and SHIFT_KF establish the damping of the PLL and are chosen
+ * for a slightly underdamped convergence characteristic. SHIFT_KH
+ * establishes the damping of the FLL and is chosen by wisdom and black
+ * art.
+ *
+ * MAXTC establishes the maximum time constant of the PLL. With the
+ * SHIFT_KG and SHIFT_KF values given and a time constant range from
+ * zero to MAXTC, the PLL will converge in 15 minutes to 16 hours,
+ * respectively.
+ */
+#define SHIFT_PLL	4	/* PLL frequency factor (shift) */
+#define SHIFT_FLL	2	/* FLL frequency factor (shift) */
+#define MAXTC		10	/* maximum time constant (shift) */
+
+/*
+ * SHIFT_USEC defines the scaling (shift) of the time_freq and
+ * time_tolerance variables, which represent the current frequency
+ * offset and maximum frequency tolerance.
+ */
+#define SHIFT_USEC 16		/* frequency offset scale (shift) */
+#define PPM_SCALE (NSEC_PER_USEC << (NTP_SCALE_SHIFT - SHIFT_USEC))
+#define PPM_SCALE_INV_SHIFT 19
+#define PPM_SCALE_INV ((1ll << (PPM_SCALE_INV_SHIFT + NTP_SCALE_SHIFT)) / \
+		       PPM_SCALE + 1)
+
+#define MAXPHASE 500000000l	/* max phase error (ns) */
+#define MAXFREQ 500000		/* max frequency error (ns/s) */
+#define MAXFREQ_SCALED ((s64)MAXFREQ << NTP_SCALE_SHIFT)
+#define MINSEC 256		/* min interval between updates (s) */
+#define MAXSEC 2048		/* max interval between updates (s) */
+#define NTP_PHASE_LIMIT ((MAXPHASE / NSEC_PER_USEC) << 5) /* beyond max. dispersion */
+
+/*
  * kernel variables
  * Note: maximum error = NTP synch distance = dispersion + delay / 2;
  * estimated error = NTP dispersion.
diff --git a/include/linux/topology.h b/include/linux/topology.h
index 2158fc0d5a56..0c5b5ac36d8e 100644
--- a/include/linux/topology.h
+++ b/include/linux/topology.h
@@ -49,7 +49,7 @@
 	for_each_online_node(node)			\
 		if (nr_cpus_node(node))
 
-void arch_update_cpu_topology(void);
+int arch_update_cpu_topology(void);
 
 /* Conform to ACPI 2.0 SLIT distance definitions */
 #define LOCAL_DISTANCE		10
@@ -99,7 +99,7 @@ void arch_update_cpu_topology(void);
 				| SD_BALANCE_FORK	\
 				| SD_BALANCE_EXEC	\
 				| SD_WAKE_AFFINE	\
-				| SD_WAKE_IDLE		\
+				| SD_WAKE_BALANCE	\
 				| SD_SHARE_CPUPOWER,	\
 	.last_balance		= jiffies,		\
 	.balance_interval	= 1,			\
@@ -120,10 +120,10 @@ void arch_update_cpu_topology(void);
 	.wake_idx		= 1,			\
 	.forkexec_idx		= 1,			\
 	.flags			= SD_LOAD_BALANCE	\
-				| SD_BALANCE_NEWIDLE	\
 				| SD_BALANCE_FORK	\
 				| SD_BALANCE_EXEC	\
 				| SD_WAKE_AFFINE	\
+				| SD_WAKE_BALANCE	\
 				| SD_SHARE_PKG_RESOURCES\
 				| BALANCE_FOR_MC_POWER,	\
 	.last_balance		= jiffies,		\
@@ -146,10 +146,10 @@ void arch_update_cpu_topology(void);
 	.wake_idx		= 1,			\
 	.forkexec_idx		= 1,			\
 	.flags			= SD_LOAD_BALANCE	\
-				| SD_BALANCE_NEWIDLE	\
-				| SD_BALANCE_FORK	\
 				| SD_BALANCE_EXEC	\
+				| SD_BALANCE_FORK	\
 				| SD_WAKE_AFFINE	\
+				| SD_WAKE_BALANCE	\
 				| BALANCE_FOR_PKG_POWER,\
 	.last_balance		= jiffies,		\
 	.balance_interval	= 1,			\
diff --git a/include/linux/tracepoint.h b/include/linux/tracepoint.h
new file mode 100644
index 000000000000..757005458366
--- /dev/null
+++ b/include/linux/tracepoint.h
@@ -0,0 +1,156 @@
+#ifndef _LINUX_TRACEPOINT_H
+#define _LINUX_TRACEPOINT_H
+
+/*
+ * Kernel Tracepoint API.
+ *
+ * See Documentation/tracepoint.txt.
+ *
+ * (C) Copyright 2008 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+ *
+ * Heavily inspired from the Linux Kernel Markers.
+ *
+ * This file is released under the GPLv2.
+ * See the file COPYING for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/rcupdate.h>
+
+struct module;
+struct tracepoint;
+
+struct tracepoint {
+	const char *name;		/* Tracepoint name */
+	int state;			/* State. */
+	void **funcs;
+} __attribute__((aligned(32)));		/*
+					 * Aligned on 32 bytes because it is
+					 * globally visible and gcc happily
+					 * align these on the structure size.
+					 * Keep in sync with vmlinux.lds.h.
+					 */
+
+#define TPPROTO(args...)	args
+#define TPARGS(args...)		args
+
+#ifdef CONFIG_TRACEPOINTS
+
+/*
+ * it_func[0] is never NULL because there is at least one element in the array
+ * when the array itself is non NULL.
+ */
+#define __DO_TRACE(tp, proto, args)					\
+	do {								\
+		void **it_func;						\
+									\
+		rcu_read_lock_sched_notrace();				\
+		it_func = rcu_dereference((tp)->funcs);			\
+		if (it_func) {						\
+			do {						\
+				((void(*)(proto))(*it_func))(args);	\
+			} while (*(++it_func));				\
+		}							\
+		rcu_read_unlock_sched_notrace();			\
+	} while (0)
+
+/*
+ * Make sure the alignment of the structure in the __tracepoints section will
+ * not add unwanted padding between the beginning of the section and the
+ * structure. Force alignment to the same alignment as the section start.
+ */
+#define DECLARE_TRACE(name, proto, args)				\
+	extern struct tracepoint __tracepoint_##name;			\
+	static inline void trace_##name(proto)				\
+	{								\
+		if (unlikely(__tracepoint_##name.state))		\
+			__DO_TRACE(&__tracepoint_##name,		\
+				TPPROTO(proto), TPARGS(args));		\
+	}								\
+	static inline int register_trace_##name(void (*probe)(proto))	\
+	{								\
+		return tracepoint_probe_register(#name, (void *)probe);	\
+	}								\
+	static inline int unregister_trace_##name(void (*probe)(proto))	\
+	{								\
+		return tracepoint_probe_unregister(#name, (void *)probe);\
+	}
+
+#define DEFINE_TRACE(name)						\
+	static const char __tpstrtab_##name[]				\
+	__attribute__((section("__tracepoints_strings"))) = #name;	\
+	struct tracepoint __tracepoint_##name				\
+	__attribute__((section("__tracepoints"), aligned(32))) =	\
+		{ __tpstrtab_##name, 0, NULL }
+
+#define EXPORT_TRACEPOINT_SYMBOL_GPL(name)				\
+	EXPORT_SYMBOL_GPL(__tracepoint_##name)
+#define EXPORT_TRACEPOINT_SYMBOL(name)					\
+	EXPORT_SYMBOL(__tracepoint_##name)
+
+extern void tracepoint_update_probe_range(struct tracepoint *begin,
+	struct tracepoint *end);
+
+#else /* !CONFIG_TRACEPOINTS */
+#define DECLARE_TRACE(name, proto, args)				\
+	static inline void _do_trace_##name(struct tracepoint *tp, proto) \
+	{ }								\
+	static inline void trace_##name(proto)				\
+	{ }								\
+	static inline int register_trace_##name(void (*probe)(proto))	\
+	{								\
+		return -ENOSYS;						\
+	}								\
+	static inline int unregister_trace_##name(void (*probe)(proto))	\
+	{								\
+		return -ENOSYS;						\
+	}
+
+#define DEFINE_TRACE(name)
+#define EXPORT_TRACEPOINT_SYMBOL_GPL(name)
+#define EXPORT_TRACEPOINT_SYMBOL(name)
+
+static inline void tracepoint_update_probe_range(struct tracepoint *begin,
+	struct tracepoint *end)
+{ }
+#endif /* CONFIG_TRACEPOINTS */
+
+/*
+ * Connect a probe to a tracepoint.
+ * Internal API, should not be used directly.
+ */
+extern int tracepoint_probe_register(const char *name, void *probe);
+
+/*
+ * Disconnect a probe from a tracepoint.
+ * Internal API, should not be used directly.
+ */
+extern int tracepoint_probe_unregister(const char *name, void *probe);
+
+extern int tracepoint_probe_register_noupdate(const char *name, void *probe);
+extern int tracepoint_probe_unregister_noupdate(const char *name, void *probe);
+extern void tracepoint_probe_update_all(void);
+
+struct tracepoint_iter {
+	struct module *module;
+	struct tracepoint *tracepoint;
+};
+
+extern void tracepoint_iter_start(struct tracepoint_iter *iter);
+extern void tracepoint_iter_next(struct tracepoint_iter *iter);
+extern void tracepoint_iter_stop(struct tracepoint_iter *iter);
+extern void tracepoint_iter_reset(struct tracepoint_iter *iter);
+extern int tracepoint_get_iter_range(struct tracepoint **tracepoint,
+	struct tracepoint *begin, struct tracepoint *end);
+
+/*
+ * tracepoint_synchronize_unregister must be called between the last tracepoint
+ * probe unregistration and the end of module exit to make sure there is no
+ * caller executing a probe when it is freed.
+ */
+static inline void tracepoint_synchronize_unregister(void)
+{
+	synchronize_sched();
+}
+
+#endif
diff --git a/include/linux/tty.h b/include/linux/tty.h
index 3b8121d4e36f..3f4954c55e53 100644
--- a/include/linux/tty.h
+++ b/include/linux/tty.h
@@ -325,7 +325,7 @@ extern struct class *tty_class;
  *	go away
  */
 
-extern inline struct tty_struct *tty_kref_get(struct tty_struct *tty)
+static inline struct tty_struct *tty_kref_get(struct tty_struct *tty)
 {
 	if (tty)
 		kref_get(&tty->kref);
@@ -442,6 +442,7 @@ extern void tty_audit_add_data(struct tty_struct *tty, unsigned char *data,
 			       size_t size);
 extern void tty_audit_exit(void);
 extern void tty_audit_fork(struct signal_struct *sig);
+extern void tty_audit_tiocsti(struct tty_struct *tty, char ch);
 extern void tty_audit_push(struct tty_struct *tty);
 extern void tty_audit_push_task(struct task_struct *tsk,
 					uid_t loginuid, u32 sessionid);
@@ -450,6 +451,9 @@ static inline void tty_audit_add_data(struct tty_struct *tty,
 				      unsigned char *data, size_t size)
 {
 }
+static inline void tty_audit_tiocsti(struct tty_struct *tty, char ch)
+{
+}
 static inline void tty_audit_exit(void)
 {
 }
diff --git a/include/linux/types.h b/include/linux/types.h
index d4a9ce6e2760..121f349cb7ec 100644
--- a/include/linux/types.h
+++ b/include/linux/types.h
@@ -135,19 +135,14 @@ typedef		__s64		int64_t;
  *
  * Linux always considers sectors to be 512 bytes long independently
  * of the devices real block size.
+ *
+ * blkcnt_t is the type of the inode's block count.
  */
 #ifdef CONFIG_LBD
 typedef u64 sector_t;
-#else
-typedef unsigned long sector_t;
-#endif
-
-/*
- * The type of the inode's block count.
- */
-#ifdef CONFIG_LSF
 typedef u64 blkcnt_t;
 #else
+typedef unsigned long sector_t;
 typedef unsigned long blkcnt_t;
 #endif
 
@@ -190,13 +185,16 @@ typedef __u32 __bitwise __wsum;
 
 #ifdef __KERNEL__
 typedef unsigned __bitwise__ gfp_t;
+typedef unsigned __bitwise__ fmode_t;
 
-#ifdef CONFIG_RESOURCES_64BIT
-typedef u64 resource_size_t;
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
+typedef u64 phys_addr_t;
 #else
-typedef u32 resource_size_t;
+typedef u32 phys_addr_t;
 #endif
 
+typedef phys_addr_t resource_size_t;
+
 struct ustat {
 	__kernel_daddr_t	f_tfree;
 	__kernel_ino_t		f_tinode;
diff --git a/include/linux/uaccess.h b/include/linux/uaccess.h
index fec6decfb983..6b58367d145e 100644
--- a/include/linux/uaccess.h
+++ b/include/linux/uaccess.h
@@ -78,7 +78,7 @@ static inline unsigned long __copy_from_user_nocache(void *to,
 							\
 		set_fs(KERNEL_DS);			\
 		pagefault_disable();			\
-		ret = __get_user(retval, (__force typeof(retval) __user *)(addr));		\
+		ret = __copy_from_user_inatomic(&(retval), (__force typeof(retval) __user *)(addr), sizeof(retval));		\
 		pagefault_enable();			\
 		set_fs(old_fs);				\
 		ret;					\
diff --git a/include/linux/usb.h b/include/linux/usb.h
index 94ac74aba6b6..f72aa51f7bcd 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -108,6 +108,7 @@ enum usb_interface_condition {
  *	(in probe()), bound to a driver, or unbinding (in disconnect())
  * @is_active: flag set when the interface is bound and not suspended.
  * @sysfs_files_created: sysfs attributes exist
+ * @unregistering: flag set when the interface is being unregistered
  * @needs_remote_wakeup: flag set when the driver requires remote-wakeup
  *	capability during autosuspend.
  * @needs_altsetting0: flag set when a set-interface request for altsetting 0
@@ -163,6 +164,7 @@ struct usb_interface {
 	enum usb_interface_condition condition;		/* state of binding */
 	unsigned is_active:1;		/* the interface is not suspended */
 	unsigned sysfs_files_created:1;	/* the sysfs attributes exist */
+	unsigned unregistering:1;	/* unregistration is in progress */
 	unsigned needs_remote_wakeup:1;	/* driver requires remote wakeup */
 	unsigned needs_altsetting0:1;	/* switch to altsetting 0 is pending */
 	unsigned needs_binding:1;	/* needs delayed unbind/rebind */
@@ -1135,6 +1137,7 @@ struct usb_anchor {
 	struct list_head urb_list;
 	wait_queue_head_t wait;
 	spinlock_t lock;
+	unsigned int poisoned:1;
 };
 
 static inline void init_usb_anchor(struct usb_anchor *anchor)
@@ -1459,12 +1462,18 @@ extern struct urb *usb_get_urb(struct urb *urb);
 extern int usb_submit_urb(struct urb *urb, gfp_t mem_flags);
 extern int usb_unlink_urb(struct urb *urb);
 extern void usb_kill_urb(struct urb *urb);
+extern void usb_poison_urb(struct urb *urb);
+extern void usb_unpoison_urb(struct urb *urb);
 extern void usb_kill_anchored_urbs(struct usb_anchor *anchor);
+extern void usb_poison_anchored_urbs(struct usb_anchor *anchor);
 extern void usb_unlink_anchored_urbs(struct usb_anchor *anchor);
 extern void usb_anchor_urb(struct urb *urb, struct usb_anchor *anchor);
 extern void usb_unanchor_urb(struct urb *urb);
 extern int usb_wait_anchor_empty_timeout(struct usb_anchor *anchor,
 					 unsigned int timeout);
+extern struct urb *usb_get_from_anchor(struct usb_anchor *anchor);
+extern void usb_scuttle_anchored_urbs(struct usb_anchor *anchor);
+extern int usb_anchor_empty(struct usb_anchor *anchor);
 
 /**
  * usb_urb_dir_in - check if an URB describes an IN transfer
diff --git a/include/linux/usb/Kbuild b/include/linux/usb/Kbuild
index 42e84fc315e3..54c446309a2a 100644
--- a/include/linux/usb/Kbuild
+++ b/include/linux/usb/Kbuild
@@ -4,4 +4,5 @@ header-y += ch9.h
 header-y += gadgetfs.h
 header-y += midi.h
 header-y += g_printer.h
-
+header-y += tmc.h
+header-y += vstusb.h
diff --git a/include/linux/usb/cdc.h b/include/linux/usb/cdc.h
index ca228bb94218..18a729343ffa 100644
--- a/include/linux/usb/cdc.h
+++ b/include/linux/usb/cdc.h
@@ -160,6 +160,15 @@ struct usb_cdc_mdlm_detail_desc {
 	__u8	bDetailData[0];
 } __attribute__ ((packed));
 
+/* "OBEX Control Model Functional Descriptor" */
+struct usb_cdc_obex_desc {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	__le16	bcdVersion;
+} __attribute__ ((packed));
+
 /*-------------------------------------------------------------------------*/
 
 /*
diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h
index 73a2f4eb1f7a..9b42baed3900 100644
--- a/include/linux/usb/ch9.h
+++ b/include/linux/usb/ch9.h
@@ -158,8 +158,12 @@ struct usb_ctrlrequest {
  * (rarely) accepted by SET_DESCRIPTOR.
  *
  * Note that all multi-byte values here are encoded in little endian
- * byte order "on the wire".  But when exposed through Linux-USB APIs,
- * they've been converted to cpu byte order.
+ * byte order "on the wire".  Within the kernel and when exposed
+ * through the Linux-USB APIs, they are not converted to cpu byte
+ * order; it is the responsibility of the client code to do this.
+ * The single exception is when device and configuration descriptors (but
+ * not other descriptors) are read from usbfs (i.e. /proc/bus/usb/BBB/DDD);
+ * in this case the fields are converted to host endianness by the kernel.
  */
 
 /*
diff --git a/include/linux/usb/composite.h b/include/linux/usb/composite.h
index c932390c6da0..935c380ffe47 100644
--- a/include/linux/usb/composite.h
+++ b/include/linux/usb/composite.h
@@ -130,6 +130,9 @@ struct usb_function {
 
 int usb_add_function(struct usb_configuration *, struct usb_function *);
 
+int usb_function_deactivate(struct usb_function *);
+int usb_function_activate(struct usb_function *);
+
 int usb_interface_id(struct usb_configuration *, struct usb_function *);
 
 /**
@@ -316,9 +319,13 @@ struct usb_composite_dev {
 	struct usb_composite_driver	*driver;
 	u8				next_string_id;
 
-	spinlock_t			lock;
+	/* the gadget driver won't enable the data pullup
+	 * while the deactivation count is nonzero.
+	 */
+	unsigned			deactivations;
 
-	/* REVISIT use and existence of lock ... */
+	/* protects at least deactivation count */
+	spinlock_t			lock;
 };
 
 extern int usb_string_id(struct usb_composite_dev *c);
diff --git a/include/linux/usb/serial.h b/include/linux/usb/serial.h
index 655341d0f534..0b8617a9176d 100644
--- a/include/linux/usb/serial.h
+++ b/include/linux/usb/serial.h
@@ -192,7 +192,7 @@ static inline void usb_set_serial_data(struct usb_serial *serial, void *data)
  * The driver.owner field should be set to the module owner of this driver.
  * The driver.name field should be set to the name of this driver (remember
  * it will show up in sysfs, so it needs to be short and to the point.
- * Useing the module name is a good idea.)
+ * Using the module name is a good idea.)
  */
 struct usb_serial_driver {
 	const char *description;
diff --git a/include/linux/usb/tmc.h b/include/linux/usb/tmc.h
new file mode 100644
index 000000000000..c045ae12556c
--- /dev/null
+++ b/include/linux/usb/tmc.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2007 Stefan Kopp, Gechingen, Germany
+ * Copyright (C) 2008 Novell, Inc.
+ * Copyright (C) 2008 Greg Kroah-Hartman <gregkh@suse.de>
+ *
+ * This file holds USB constants defined by the USB Device Class
+ * Definition for Test and Measurement devices published by the USB-IF.
+ *
+ * It also has the ioctl definitions for the usbtmc kernel driver that
+ * userspace needs to know about.
+ */
+
+#ifndef __LINUX_USB_TMC_H
+#define __LINUX_USB_TMC_H
+
+/* USB TMC status values */
+#define USBTMC_STATUS_SUCCESS				0x01
+#define USBTMC_STATUS_PENDING				0x02
+#define USBTMC_STATUS_FAILED				0x80
+#define USBTMC_STATUS_TRANSFER_NOT_IN_PROGRESS		0x81
+#define USBTMC_STATUS_SPLIT_NOT_IN_PROGRESS		0x82
+#define USBTMC_STATUS_SPLIT_IN_PROGRESS			0x83
+
+/* USB TMC requests values */
+#define USBTMC_REQUEST_INITIATE_ABORT_BULK_OUT		1
+#define USBTMC_REQUEST_CHECK_ABORT_BULK_OUT_STATUS	2
+#define USBTMC_REQUEST_INITIATE_ABORT_BULK_IN		3
+#define USBTMC_REQUEST_CHECK_ABORT_BULK_IN_STATUS	4
+#define USBTMC_REQUEST_INITIATE_CLEAR			5
+#define USBTMC_REQUEST_CHECK_CLEAR_STATUS		6
+#define USBTMC_REQUEST_GET_CAPABILITIES			7
+#define USBTMC_REQUEST_INDICATOR_PULSE			64
+
+/* Request values for USBTMC driver's ioctl entry point */
+#define USBTMC_IOC_NR			91
+#define USBTMC_IOCTL_INDICATOR_PULSE	_IO(USBTMC_IOC_NR, 1)
+#define USBTMC_IOCTL_CLEAR		_IO(USBTMC_IOC_NR, 2)
+#define USBTMC_IOCTL_ABORT_BULK_OUT	_IO(USBTMC_IOC_NR, 3)
+#define USBTMC_IOCTL_ABORT_BULK_IN	_IO(USBTMC_IOC_NR, 4)
+#define USBTMC_IOCTL_CLEAR_OUT_HALT	_IO(USBTMC_IOC_NR, 6)
+#define USBTMC_IOCTL_CLEAR_IN_HALT	_IO(USBTMC_IOC_NR, 7)
+
+#endif
diff --git a/include/linux/usb/vstusb.h b/include/linux/usb/vstusb.h
new file mode 100644
index 000000000000..1cfac67191ff
--- /dev/null
+++ b/include/linux/usb/vstusb.h
@@ -0,0 +1,71 @@
+/*****************************************************************************
+ *  File: drivers/usb/misc/vstusb.h
+ *
+ *  Purpose: Support for the bulk USB Vernier Spectrophotometers
+ *
+ *  Author:     EQware Engineering, Inc.
+ *              Oregon City, OR, USA 97045
+ *
+ *  Copyright:  2007, 2008
+ *              Vernier Software & Technology
+ *              Beaverton, OR, USA 97005
+ *
+ *  Web:        www.vernier.com
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *****************************************************************************/
+/*****************************************************************************
+ *
+ *  The vstusb module is a standard usb 'client' driver running on top of the
+ *  standard usb host controller stack.
+ *
+ *  In general, vstusb supports standard bulk usb pipes.  It supports multiple
+ *  devices and multiple pipes per device.
+ *
+ *  The vstusb driver supports two interfaces:
+ *  1 - ioctl SEND_PIPE/RECV_PIPE - a general bulk write/read msg
+ *  	interface to any pipe with timeout support;
+ *  2 - standard read/write with ioctl config - offers standard read/write
+ *  	interface with ioctl configured pipes and timeouts.
+ *
+ *  Both interfaces can be signal from other process and will abort its i/o
+ *  operation.
+ *
+ *  A timeout of 0 means NO timeout.  The user can still terminate the read via
+ *  signal.
+ *
+ *  If using multiple threads with this driver, the user should ensure that
+ *  any reads, writes, or ioctls are complete before closing the device.
+ *  Changing read/write timeouts or pipes takes effect on next read/write.
+ *
+ *****************************************************************************/
+
+struct vstusb_args {
+	union {
+		/* this struct is used for IOCTL_VSTUSB_SEND_PIPE,	*
+		 * IOCTL_VSTUSB_RECV_PIPE, and read()/write() fops	*/
+		struct {
+			void __user	*buffer;
+			size_t          count;
+			unsigned int    timeout_ms;
+			int             pipe;
+		};
+
+		/* this one is used for IOCTL_VSTUSB_CONFIG_RW  	*/
+		struct {
+			int rd_pipe;
+			int rd_timeout_ms;
+			int wr_pipe;
+			int wr_timeout_ms;
+		};
+	};
+};
+
+#define VST_IOC_MAGIC 'L'
+#define VST_IOC_FIRST 0x20
+#define IOCTL_VSTUSB_SEND_PIPE	_IO(VST_IOC_MAGIC, VST_IOC_FIRST)
+#define IOCTL_VSTUSB_RECV_PIPE	_IO(VST_IOC_MAGIC, VST_IOC_FIRST + 1)
+#define IOCTL_VSTUSB_CONFIG_RW	_IO(VST_IOC_MAGIC, VST_IOC_FIRST + 2)
diff --git a/include/linux/usb/wusb-wa.h b/include/linux/usb/wusb-wa.h
new file mode 100644
index 000000000000..a102561e7026
--- /dev/null
+++ b/include/linux/usb/wusb-wa.h
@@ -0,0 +1,271 @@
+/*
+ * Wireless USB Wire Adapter constants and structures.
+ *
+ * Copyright (C) 2005-2006 Intel Corporation.
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * FIXME: docs
+ * FIXME: organize properly, group logically
+ *
+ * All the event structures are defined in uwb/spec.h, as they are
+ * common to the WHCI and WUSB radio control interfaces.
+ *
+ * References:
+ *   [WUSB] Wireless Universal Serial Bus Specification, revision 1.0, ch8
+ */
+#ifndef __LINUX_USB_WUSB_WA_H
+#define __LINUX_USB_WUSB_WA_H
+
+/**
+ * Radio Command Request for the Radio Control Interface
+ *
+ * Radio Control Interface command and event codes are the same as
+ * WHCI, and listed in include/linux/uwb.h:UWB_RC_{CMD,EVT}_*
+ */
+enum {
+	WA_EXEC_RC_CMD = 40,	/* Radio Control command Request */
+};
+
+/* Wireless Adapter Requests ([WUSB] table 8-51) */
+enum {
+	WUSB_REQ_ADD_MMC_IE     = 20,
+	WUSB_REQ_REMOVE_MMC_IE  = 21,
+	WUSB_REQ_SET_NUM_DNTS   = 22,
+	WUSB_REQ_SET_CLUSTER_ID = 23,
+	WUSB_REQ_SET_DEV_INFO   = 24,
+	WUSB_REQ_GET_TIME       = 25,
+	WUSB_REQ_SET_STREAM_IDX = 26,
+	WUSB_REQ_SET_WUSB_MAS   = 27,
+};
+
+
+/* Wireless Adapter WUSB Channel Time types ([WUSB] table 8-52) */
+enum {
+	WUSB_TIME_ADJ   = 0,
+	WUSB_TIME_BPST  = 1,
+	WUSB_TIME_WUSB  = 2,
+};
+
+enum {
+	WA_ENABLE = 0x01,
+	WA_RESET = 0x02,
+	RPIPE_PAUSE = 0x1,
+};
+
+/* Responses from Get Status request ([WUSB] section 8.3.1.6) */
+enum {
+	WA_STATUS_ENABLED = 0x01,
+	WA_STATUS_RESETTING = 0x02
+};
+
+enum rpipe_crs {
+	RPIPE_CRS_CTL = 0x01,
+	RPIPE_CRS_ISO = 0x02,
+	RPIPE_CRS_BULK = 0x04,
+	RPIPE_CRS_INTR = 0x08
+};
+
+/**
+ * RPipe descriptor ([WUSB] section 8.5.2.11)
+ *
+ * FIXME: explain rpipes
+ */
+struct usb_rpipe_descriptor {
+	u8 	bLength;
+	u8	bDescriptorType;
+	__le16  wRPipeIndex;
+	__le16	wRequests;
+	__le16	wBlocks;		/* rw if 0 */
+	__le16	wMaxPacketSize;		/* rw? */
+	u8	bHSHubAddress;		/* reserved: 0 */
+	u8	bHSHubPort;		/* ??? FIXME ??? */
+	u8	bSpeed;			/* rw: xfer rate 'enum uwb_phy_rate' */
+	u8	bDeviceAddress;		/* rw: Target device address */
+	u8	bEndpointAddress;	/* rw: Target EP address */
+	u8	bDataSequence;		/* ro: Current Data sequence */
+	__le32	dwCurrentWindow;	/* ro */
+	u8	bMaxDataSequence;	/* ro?: max supported seq */
+	u8	bInterval;		/* rw:  */
+	u8	bOverTheAirInterval;	/* rw:  */
+	u8	bmAttribute;		/* ro?  */
+	u8	bmCharacteristics;	/* ro? enum rpipe_attr, supported xsactions */
+	u8	bmRetryOptions;		/* rw? */
+	__le16	wNumTransactionErrors;	/* rw */
+} __attribute__ ((packed));
+
+/**
+ * Wire Adapter Notification types ([WUSB] sections 8.4.5 & 8.5.4)
+ *
+ * These are the notifications coming on the notification endpoint of
+ * an HWA and a DWA.
+ */
+enum wa_notif_type {
+	DWA_NOTIF_RWAKE = 0x91,
+	DWA_NOTIF_PORTSTATUS = 0x92,
+	WA_NOTIF_TRANSFER = 0x93,
+	HWA_NOTIF_BPST_ADJ = 0x94,
+	HWA_NOTIF_DN = 0x95,
+};
+
+/**
+ * Wire Adapter notification header
+ *
+ * Notifications coming from a wire adapter use a common header
+ * defined in [WUSB] sections 8.4.5 & 8.5.4.
+ */
+struct wa_notif_hdr {
+	u8 bLength;
+	u8 bNotifyType;			/* enum wa_notif_type */
+} __attribute__((packed));
+
+/**
+ * HWA DN Received notification [(WUSB] section 8.5.4.2)
+ *
+ * The DNData is specified in WUSB1.0[7.6]. For each device
+ * notification we received, we just need to dispatch it.
+ *
+ * @dndata:  this is really an array of notifications, but all start
+ *           with the same header.
+ */
+struct hwa_notif_dn {
+	struct wa_notif_hdr hdr;
+	u8 bSourceDeviceAddr;		/* from errata 2005/07 */
+	u8 bmAttributes;
+	struct wusb_dn_hdr dndata[];
+} __attribute__((packed));
+
+/* [WUSB] section 8.3.3 */
+enum wa_xfer_type {
+	WA_XFER_TYPE_CTL = 0x80,
+	WA_XFER_TYPE_BI = 0x81,		/* bulk/interrupt */
+	WA_XFER_TYPE_ISO = 0x82,
+	WA_XFER_RESULT = 0x83,
+	WA_XFER_ABORT = 0x84,
+};
+
+/* [WUSB] section 8.3.3 */
+struct wa_xfer_hdr {
+	u8 bLength;			/* 0x18 */
+	u8 bRequestType;		/* 0x80 WA_REQUEST_TYPE_CTL */
+	__le16 wRPipe;			/* RPipe index */
+	__le32 dwTransferID;		/* Host-assigned ID */
+	__le32 dwTransferLength;	/* Length of data to xfer */
+	u8 bTransferSegment;
+} __attribute__((packed));
+
+struct wa_xfer_ctl {
+	struct wa_xfer_hdr hdr;
+	u8 bmAttribute;
+	__le16 wReserved;
+	struct usb_ctrlrequest baSetupData;
+} __attribute__((packed));
+
+struct wa_xfer_bi {
+	struct wa_xfer_hdr hdr;
+	u8 bReserved;
+	__le16 wReserved;
+} __attribute__((packed));
+
+struct wa_xfer_hwaiso {
+	struct wa_xfer_hdr hdr;
+	u8 bReserved;
+	__le16 wPresentationTime;
+	__le32 dwNumOfPackets;
+	/* FIXME: u8 pktdata[]? */
+} __attribute__((packed));
+
+/* [WUSB] section 8.3.3.5 */
+struct wa_xfer_abort {
+	u8 bLength;
+	u8 bRequestType;
+	__le16 wRPipe;			/* RPipe index */
+	__le32 dwTransferID;		/* Host-assigned ID */
+} __attribute__((packed));
+
+/**
+ * WA Transfer Complete notification ([WUSB] section 8.3.3.3)
+ *
+ */
+struct wa_notif_xfer {
+	struct wa_notif_hdr hdr;
+	u8 bEndpoint;
+	u8 Reserved;
+} __attribute__((packed));
+
+/** Transfer result basic codes [WUSB] table 8-15 */
+enum {
+	WA_XFER_STATUS_SUCCESS,
+	WA_XFER_STATUS_HALTED,
+	WA_XFER_STATUS_DATA_BUFFER_ERROR,
+	WA_XFER_STATUS_BABBLE,
+	WA_XFER_RESERVED,
+	WA_XFER_STATUS_NOT_FOUND,
+	WA_XFER_STATUS_INSUFFICIENT_RESOURCE,
+	WA_XFER_STATUS_TRANSACTION_ERROR,
+	WA_XFER_STATUS_ABORTED,
+	WA_XFER_STATUS_RPIPE_NOT_READY,
+	WA_XFER_INVALID_FORMAT,
+	WA_XFER_UNEXPECTED_SEGMENT_NUMBER,
+	WA_XFER_STATUS_RPIPE_TYPE_MISMATCH,
+};
+
+/** [WUSB] section 8.3.3.4 */
+struct wa_xfer_result {
+	struct wa_notif_hdr hdr;
+	__le32 dwTransferID;
+	__le32 dwTransferLength;
+	u8     bTransferSegment;
+	u8     bTransferStatus;
+	__le32 dwNumOfPackets;
+} __attribute__((packed));
+
+/**
+ * Wire Adapter Class Descriptor ([WUSB] section 8.5.2.7).
+ *
+ * NOTE: u16 fields are read Little Endian from the hardware.
+ *
+ * @bNumPorts is the original max number of devices that the host can
+ *            connect; we might chop this so the stack can handle
+ *            it. In case you need to access it, use wusbhc->ports_max
+ *            if it is a Wireless USB WA.
+ */
+struct usb_wa_descriptor {
+	u8	bLength;
+	u8	bDescriptorType;
+	u16	bcdWAVersion;
+	u8	bNumPorts;		/* don't use!! */
+	u8	bmAttributes;		/* Reserved == 0 */
+	u16	wNumRPipes;
+	u16	wRPipeMaxBlock;
+	u8	bRPipeBlockSize;
+	u8	bPwrOn2PwrGood;
+	u8	bNumMMCIEs;
+	u8	DeviceRemovable;	/* FIXME: in DWA this is up to 16 bytes */
+} __attribute__((packed));
+
+/**
+ * HWA Device Information Buffer (WUSB1.0[T8.54])
+ */
+struct hwa_dev_info {
+	u8	bmDeviceAvailability[32];       /* FIXME: ignored for now */
+	u8	bDeviceAddress;
+	__le16	wPHYRates;
+	u8	bmDeviceAttribute;
+} __attribute__((packed));
+
+#endif /* #ifndef __LINUX_USB_WUSB_WA_H */
diff --git a/include/linux/usb/wusb.h b/include/linux/usb/wusb.h
new file mode 100644
index 000000000000..5f401b644ed5
--- /dev/null
+++ b/include/linux/usb/wusb.h
@@ -0,0 +1,376 @@
+/*
+ * Wireless USB Standard Definitions
+ * Event Size Tables
+ *
+ * Copyright (C) 2005-2006 Intel Corporation
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * FIXME: docs
+ * FIXME: organize properly, group logically
+ *
+ * All the event structures are defined in uwb/spec.h, as they are
+ * common to the WHCI and WUSB radio control interfaces.
+ */
+
+#ifndef __WUSB_H__
+#define __WUSB_H__
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/uwb/spec.h>
+#include <linux/usb/ch9.h>
+#include <linux/param.h>
+
+/**
+ * WUSB Information Element header
+ *
+ * I don't know why, they decided to make it different to the MBOA MAC
+ * IE Header; beats me.
+ */
+struct wuie_hdr {
+	u8 bLength;
+	u8 bIEIdentifier;
+} __attribute__((packed));
+
+enum {
+	WUIE_ID_WCTA = 0x80,
+	WUIE_ID_CONNECTACK,
+	WUIE_ID_HOST_INFO,
+	WUIE_ID_CHANGE_ANNOUNCE,
+	WUIE_ID_DEVICE_DISCONNECT,
+	WUIE_ID_HOST_DISCONNECT,
+	WUIE_ID_KEEP_ALIVE = 0x89,
+	WUIE_ID_ISOCH_DISCARD,
+	WUIE_ID_RESET_DEVICE,
+};
+
+/**
+ * Maximum number of array elements in a WUSB IE.
+ *
+ * WUSB1.0[7.5 before table 7-38] says that in WUSB IEs that
+ * are "arrays" have to limited to 4 elements. So we define it
+ * like that to ease up and submit only the neeed size.
+ */
+#define WUIE_ELT_MAX 4
+
+/**
+ * Wrapper for the data that defines a CHID, a CDID or a CK
+ *
+ * WUSB defines that CHIDs, CDIDs and CKs are a 16 byte string of
+ * data. In order to avoid confusion and enforce types, we wrap it.
+ *
+ * Make it packed, as we use it in some hw defintions.
+ */
+struct wusb_ckhdid {
+	u8 data[16];
+} __attribute__((packed));
+
+const static
+struct wusb_ckhdid wusb_ckhdid_zero = { .data = { 0 } };
+
+#define WUSB_CKHDID_STRSIZE (3 * sizeof(struct wusb_ckhdid) + 1)
+
+/**
+ * WUSB IE: Host Information (WUSB1.0[7.5.2])
+ *
+ * Used to provide information about the host to the Wireless USB
+ * devices in range (CHID can be used as an ASCII string).
+ */
+struct wuie_host_info {
+	struct wuie_hdr hdr;
+	__le16 attributes;
+	struct wusb_ckhdid CHID;
+} __attribute__((packed));
+
+/**
+ * WUSB IE: Connect Ack (WUSB1.0[7.5.1])
+ *
+ * Used to acknowledge device connect requests. See note for
+ * WUIE_ELT_MAX.
+ */
+struct wuie_connect_ack {
+	struct wuie_hdr hdr;
+	struct {
+		struct wusb_ckhdid CDID;
+		u8 bDeviceAddress;	/* 0 means unused */
+		u8 bReserved;
+	} blk[WUIE_ELT_MAX];
+} __attribute__((packed));
+
+/**
+ * WUSB IE Host Information Element, Connect Availability
+ *
+ * WUSB1.0[7.5.2], bmAttributes description
+ */
+enum {
+	WUIE_HI_CAP_RECONNECT = 0,
+	WUIE_HI_CAP_LIMITED,
+	WUIE_HI_CAP_RESERVED,
+	WUIE_HI_CAP_ALL,
+};
+
+/**
+ * WUSB IE: Channel Stop (WUSB1.0[7.5.8])
+ *
+ * Tells devices the host is going to stop sending MMCs and will dissapear.
+ */
+struct wuie_channel_stop {
+	struct wuie_hdr hdr;
+	u8 attributes;
+	u8 timestamp[3];
+} __attribute__((packed));
+
+/**
+ * WUSB IE: Keepalive (WUSB1.0[7.5.9])
+ *
+ * Ask device(s) to send keepalives.
+ */
+struct wuie_keep_alive {
+	struct wuie_hdr hdr;
+	u8 bDeviceAddress[WUIE_ELT_MAX];
+} __attribute__((packed));
+
+/**
+ * WUSB IE: Reset device (WUSB1.0[7.5.11])
+ *
+ * Tell device to reset; in all truth, we can fit 4 CDIDs, but we only
+ * use it for one at the time...
+ *
+ * In any case, this request is a wee bit silly: why don't they target
+ * by address??
+ */
+struct wuie_reset {
+	struct wuie_hdr hdr;
+	struct wusb_ckhdid CDID;
+} __attribute__((packed));
+
+/**
+ * WUSB IE: Disconnect device (WUSB1.0[7.5.11])
+ *
+ * Tell device to disconnect; we can fit 4 addresses, but we only use
+ * it for one at the time...
+ */
+struct wuie_disconnect {
+	struct wuie_hdr hdr;
+	u8 bDeviceAddress;
+	u8 padding;
+} __attribute__((packed));
+
+/**
+ * WUSB IE: Host disconnect ([WUSB] section 7.5.5)
+ *
+ * Tells all connected devices to disconnect.
+ */
+struct wuie_host_disconnect {
+	struct wuie_hdr hdr;
+} __attribute__((packed));
+
+/**
+ * WUSB Device Notification header (WUSB1.0[7.6])
+ */
+struct wusb_dn_hdr {
+	u8 bType;
+	u8 notifdata[];
+} __attribute__((packed));
+
+/** Device Notification codes (WUSB1.0[Table 7-54]) */
+enum WUSB_DN {
+	WUSB_DN_CONNECT = 0x01,
+	WUSB_DN_DISCONNECT = 0x02,
+	WUSB_DN_EPRDY = 0x03,
+	WUSB_DN_MASAVAILCHANGED = 0x04,
+	WUSB_DN_RWAKE = 0x05,
+	WUSB_DN_SLEEP = 0x06,
+	WUSB_DN_ALIVE = 0x07,
+};
+
+/** WUSB Device Notification Connect */
+struct wusb_dn_connect {
+	struct wusb_dn_hdr hdr;
+	__le16 attributes;
+	struct wusb_ckhdid CDID;
+} __attribute__((packed));
+
+static inline int wusb_dn_connect_prev_dev_addr(const struct wusb_dn_connect *dn)
+{
+	return le16_to_cpu(dn->attributes) & 0xff;
+}
+
+static inline int wusb_dn_connect_new_connection(const struct wusb_dn_connect *dn)
+{
+	return (le16_to_cpu(dn->attributes) >> 8) & 0x1;
+}
+
+static inline int wusb_dn_connect_beacon_behavior(const struct wusb_dn_connect *dn)
+{
+	return (le16_to_cpu(dn->attributes) >> 9) & 0x03;
+}
+
+/** Device is alive (aka: pong) (WUSB1.0[7.6.7]) */
+struct wusb_dn_alive {
+	struct wusb_dn_hdr hdr;
+} __attribute__((packed));
+
+/** Device is disconnecting (WUSB1.0[7.6.2]) */
+struct wusb_dn_disconnect {
+	struct wusb_dn_hdr hdr;
+} __attribute__((packed));
+
+/* General constants */
+enum {
+	WUSB_TRUST_TIMEOUT_MS = 4000,	/* [WUSB] section 4.15.1 */
+};
+
+static inline size_t ckhdid_printf(char *pr_ckhdid, size_t size,
+				   const struct wusb_ckhdid *ckhdid)
+{
+	return scnprintf(pr_ckhdid, size,
+			 "%02hx %02hx %02hx %02hx %02hx %02hx %02hx %02hx "
+			 "%02hx %02hx %02hx %02hx %02hx %02hx %02hx %02hx",
+			 ckhdid->data[0],  ckhdid->data[1],
+			 ckhdid->data[2],  ckhdid->data[3],
+			 ckhdid->data[4],  ckhdid->data[5],
+			 ckhdid->data[6],  ckhdid->data[7],
+			 ckhdid->data[8],  ckhdid->data[9],
+			 ckhdid->data[10], ckhdid->data[11],
+			 ckhdid->data[12], ckhdid->data[13],
+			 ckhdid->data[14], ckhdid->data[15]);
+}
+
+/*
+ * WUSB Crypto stuff (WUSB1.0[6])
+ */
+
+extern const char *wusb_et_name(u8);
+
+/**
+ * WUSB key index WUSB1.0[7.3.2.4], for usage when setting keys for
+ * the host or the device.
+ */
+static inline u8 wusb_key_index(int index, int type, int originator)
+{
+	return (originator << 6) | (type << 4) | index;
+}
+
+#define WUSB_KEY_INDEX_TYPE_PTK			0 /* for HWA only */
+#define WUSB_KEY_INDEX_TYPE_ASSOC		1
+#define WUSB_KEY_INDEX_TYPE_GTK			2
+#define WUSB_KEY_INDEX_ORIGINATOR_HOST		0
+#define WUSB_KEY_INDEX_ORIGINATOR_DEVICE	1
+
+/* A CCM Nonce, defined in WUSB1.0[6.4.1] */
+struct aes_ccm_nonce {
+	u8 sfn[6];              /* Little Endian */
+	u8 tkid[3];             /* LE */
+	struct uwb_dev_addr dest_addr;
+	struct uwb_dev_addr src_addr;
+} __attribute__((packed));
+
+/* A CCM operation label, defined on WUSB1.0[6.5.x] */
+struct aes_ccm_label {
+	u8 data[14];
+} __attribute__((packed));
+
+/*
+ * Input to the key derivation sequence defined in
+ * WUSB1.0[6.5.1]. Rest of the data is in the CCM Nonce passed to the
+ * PRF function.
+ */
+struct wusb_keydvt_in {
+	u8 hnonce[16];
+	u8 dnonce[16];
+} __attribute__((packed));
+
+/*
+ * Output from the key derivation sequence defined in
+ * WUSB1.0[6.5.1].
+ */
+struct wusb_keydvt_out {
+	u8 kck[16];
+	u8 ptk[16];
+} __attribute__((packed));
+
+/* Pseudo Random Function WUSB1.0[6.5] */
+extern int wusb_crypto_init(void);
+extern void wusb_crypto_exit(void);
+extern ssize_t wusb_prf(void *out, size_t out_size,
+			const u8 key[16], const struct aes_ccm_nonce *_n,
+			const struct aes_ccm_label *a,
+			const void *b, size_t blen, size_t len);
+
+static inline int wusb_prf_64(void *out, size_t out_size, const u8 key[16],
+			      const struct aes_ccm_nonce *n,
+			      const struct aes_ccm_label *a,
+			      const void *b, size_t blen)
+{
+	return wusb_prf(out, out_size, key, n, a, b, blen, 64);
+}
+
+static inline int wusb_prf_128(void *out, size_t out_size, const u8 key[16],
+			       const struct aes_ccm_nonce *n,
+			       const struct aes_ccm_label *a,
+			       const void *b, size_t blen)
+{
+	return wusb_prf(out, out_size, key, n, a, b, blen, 128);
+}
+
+static inline int wusb_prf_256(void *out, size_t out_size, const u8 key[16],
+			       const struct aes_ccm_nonce *n,
+			       const struct aes_ccm_label *a,
+			       const void *b, size_t blen)
+{
+	return wusb_prf(out, out_size, key, n, a, b, blen, 256);
+}
+
+/* Key derivation WUSB1.0[6.5.1] */
+static inline int wusb_key_derive(struct wusb_keydvt_out *keydvt_out,
+				  const u8 key[16],
+				  const struct aes_ccm_nonce *n,
+				  const struct wusb_keydvt_in *keydvt_in)
+{
+	const struct aes_ccm_label a = { .data = "Pair-wise keys" };
+	return wusb_prf_256(keydvt_out, sizeof(*keydvt_out), key, n, &a,
+			    keydvt_in, sizeof(*keydvt_in));
+}
+
+/*
+ * Out-of-band MIC Generation WUSB1.0[6.5.2]
+ *
+ * Compute the MIC over @key, @n and @hs and place it in @mic_out.
+ *
+ * @mic_out:  Where to place the 8 byte MIC tag
+ * @key:      KCK from the derivation process
+ * @n:        CCM nonce, n->sfn == 0, TKID as established in the
+ *            process.
+ * @hs:       Handshake struct for phase 2 of the 4-way.
+ *            hs->bStatus and hs->bReserved are zero.
+ *            hs->bMessageNumber is 2 (WUSB1.0[7.3.2.5.2]
+ *            hs->dest_addr is the device's USB address padded with 0
+ *            hs->src_addr is the hosts's UWB device address
+ *            hs->mic is ignored (as we compute that value).
+ */
+static inline int wusb_oob_mic(u8 mic_out[8], const u8 key[16],
+			       const struct aes_ccm_nonce *n,
+			       const struct usb_handshake *hs)
+{
+	const struct aes_ccm_label a = { .data = "out-of-bandMIC" };
+	return wusb_prf_64(mic_out, 8, key, n, &a,
+			   hs, sizeof(*hs) - sizeof(hs->MIC));
+}
+
+#endif /* #ifndef __WUSB_H__ */
diff --git a/include/linux/user_namespace.h b/include/linux/user_namespace.h
index b5f41d4c2eec..315bcd375224 100644
--- a/include/linux/user_namespace.h
+++ b/include/linux/user_namespace.h
@@ -12,7 +12,7 @@
 struct user_namespace {
 	struct kref		kref;
 	struct hlist_head	uidhash_table[UIDHASH_SZ];
-	struct user_struct	*root_user;
+	struct user_struct	*creator;
 };
 
 extern struct user_namespace init_user_ns;
@@ -26,8 +26,7 @@ static inline struct user_namespace *get_user_ns(struct user_namespace *ns)
 	return ns;
 }
 
-extern struct user_namespace *copy_user_ns(int flags,
-					   struct user_namespace *old_ns);
+extern int create_user_ns(struct cred *new);
 extern void free_user_ns(struct kref *kref);
 
 static inline void put_user_ns(struct user_namespace *ns)
@@ -43,13 +42,9 @@ static inline struct user_namespace *get_user_ns(struct user_namespace *ns)
 	return &init_user_ns;
 }
 
-static inline struct user_namespace *copy_user_ns(int flags,
-						  struct user_namespace *old_ns)
+static inline int create_user_ns(struct cred *new)
 {
-	if (flags & CLONE_NEWUSER)
-		return ERR_PTR(-EINVAL);
-
-	return old_ns;
+	return -EINVAL;
 }
 
 static inline void put_user_ns(struct user_namespace *ns)
diff --git a/include/linux/uwb.h b/include/linux/uwb.h
new file mode 100644
index 000000000000..f9ccbd9a2ced
--- /dev/null
+++ b/include/linux/uwb.h
@@ -0,0 +1,765 @@
+/*
+ * Ultra Wide Band
+ * UWB API
+ *
+ * Copyright (C) 2005-2006 Intel Corporation
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * FIXME: doc: overview of the API, different parts and pointers
+ */
+
+#ifndef __LINUX__UWB_H__
+#define __LINUX__UWB_H__
+
+#include <linux/limits.h>
+#include <linux/device.h>
+#include <linux/mutex.h>
+#include <linux/timer.h>
+#include <linux/workqueue.h>
+#include <linux/uwb/spec.h>
+
+struct uwb_dev;
+struct uwb_beca_e;
+struct uwb_rc;
+struct uwb_rsv;
+struct uwb_dbg;
+
+/**
+ * struct uwb_dev - a UWB Device
+ * @rc: UWB Radio Controller that discovered the device (kind of its
+ *     parent).
+ * @bce: a beacon cache entry for this device; or NULL if the device
+ *     is a local radio controller.
+ * @mac_addr: the EUI-48 address of this device.
+ * @dev_addr: the current DevAddr used by this device.
+ * @beacon_slot: the slot number the beacon is using.
+ * @streams: bitmap of streams allocated to reservations targeted at
+ *     this device.  For an RC, this is the streams allocated for
+ *     reservations targeted at DevAddrs.
+ *
+ * A UWB device may either by a neighbor or part of a local radio
+ * controller.
+ */
+struct uwb_dev {
+	struct mutex mutex;
+	struct list_head list_node;
+	struct device dev;
+	struct uwb_rc *rc;		/* radio controller */
+	struct uwb_beca_e *bce;		/* Beacon Cache Entry */
+
+	struct uwb_mac_addr mac_addr;
+	struct uwb_dev_addr dev_addr;
+	int beacon_slot;
+	DECLARE_BITMAP(streams, UWB_NUM_STREAMS);
+};
+#define to_uwb_dev(d) container_of(d, struct uwb_dev, dev)
+
+/**
+ * UWB HWA/WHCI Radio Control {Command|Event} Block context IDs
+ *
+ * RC[CE]Bs have a 'context ID' field that matches the command with
+ * the event received to confirm it.
+ *
+ * Maximum number of context IDs
+ */
+enum { UWB_RC_CTX_MAX = 256 };
+
+
+/** Notification chain head for UWB generated events to listeners */
+struct uwb_notifs_chain {
+	struct list_head list;
+	struct mutex mutex;
+};
+
+/**
+ * struct uwb_mas_bm - a bitmap of all MAS in a superframe
+ * @bm: a bitmap of length #UWB_NUM_MAS
+ */
+struct uwb_mas_bm {
+	DECLARE_BITMAP(bm, UWB_NUM_MAS);
+};
+
+/**
+ * uwb_rsv_state - UWB Reservation state.
+ *
+ * NONE - reservation is not active (no DRP IE being transmitted).
+ *
+ * Owner reservation states:
+ *
+ * INITIATED - owner has sent an initial DRP request.
+ * PENDING - target responded with pending Reason Code.
+ * MODIFIED - reservation manager is modifying an established
+ * reservation with a different MAS allocation.
+ * ESTABLISHED - the reservation has been successfully negotiated.
+ *
+ * Target reservation states:
+ *
+ * DENIED - request is denied.
+ * ACCEPTED - request is accepted.
+ * PENDING - PAL has yet to make a decision to whether to accept or
+ * deny.
+ *
+ * FIXME: further target states TBD.
+ */
+enum uwb_rsv_state {
+	UWB_RSV_STATE_NONE,
+	UWB_RSV_STATE_O_INITIATED,
+	UWB_RSV_STATE_O_PENDING,
+	UWB_RSV_STATE_O_MODIFIED,
+	UWB_RSV_STATE_O_ESTABLISHED,
+	UWB_RSV_STATE_T_ACCEPTED,
+	UWB_RSV_STATE_T_DENIED,
+	UWB_RSV_STATE_T_PENDING,
+
+	UWB_RSV_STATE_LAST,
+};
+
+enum uwb_rsv_target_type {
+	UWB_RSV_TARGET_DEV,
+	UWB_RSV_TARGET_DEVADDR,
+};
+
+/**
+ * struct uwb_rsv_target - the target of a reservation.
+ *
+ * Reservations unicast and targeted at a single device
+ * (UWB_RSV_TARGET_DEV); or (e.g., in the case of WUSB) targeted at a
+ * specific (private) DevAddr (UWB_RSV_TARGET_DEVADDR).
+ */
+struct uwb_rsv_target {
+	enum uwb_rsv_target_type type;
+	union {
+		struct uwb_dev *dev;
+		struct uwb_dev_addr devaddr;
+	};
+};
+
+/*
+ * Number of streams reserved for reservations targeted at DevAddrs.
+ */
+#define UWB_NUM_GLOBAL_STREAMS 1
+
+typedef void (*uwb_rsv_cb_f)(struct uwb_rsv *rsv);
+
+/**
+ * struct uwb_rsv - a DRP reservation
+ *
+ * Data structure management:
+ *
+ * @rc:             the radio controller this reservation is for
+ *                  (as target or owner)
+ * @rc_node:        a list node for the RC
+ * @pal_node:       a list node for the PAL
+ *
+ * Owner and target parameters:
+ *
+ * @owner:          the UWB device owning this reservation
+ * @target:         the target UWB device
+ * @type:           reservation type
+ *
+ * Owner parameters:
+ *
+ * @max_mas:        maxiumum number of MAS
+ * @min_mas:        minimum number of MAS
+ * @sparsity:       owner selected sparsity
+ * @is_multicast:   true iff multicast
+ *
+ * @callback:       callback function when the reservation completes
+ * @pal_priv:       private data for the PAL making the reservation
+ *
+ * Reservation status:
+ *
+ * @status:         negotiation status
+ * @stream:         stream index allocated for this reservation
+ * @mas:            reserved MAS
+ * @drp_ie:         the DRP IE
+ * @ie_valid:       true iff the DRP IE matches the reservation parameters
+ *
+ * DRP reservations are uniquely identified by the owner, target and
+ * stream index.  However, when using a DevAddr as a target (e.g., for
+ * a WUSB cluster reservation) the responses may be received from
+ * devices with different DevAddrs.  In this case, reservations are
+ * uniquely identified by just the stream index.  A number of stream
+ * indexes (UWB_NUM_GLOBAL_STREAMS) are reserved for this.
+ */
+struct uwb_rsv {
+	struct uwb_rc *rc;
+	struct list_head rc_node;
+	struct list_head pal_node;
+
+	struct uwb_dev *owner;
+	struct uwb_rsv_target target;
+	enum uwb_drp_type type;
+	int max_mas;
+	int min_mas;
+	int sparsity;
+	bool is_multicast;
+
+	uwb_rsv_cb_f callback;
+	void *pal_priv;
+
+	enum uwb_rsv_state state;
+	u8 stream;
+	struct uwb_mas_bm mas;
+	struct uwb_ie_drp *drp_ie;
+	bool ie_valid;
+	struct timer_list timer;
+	bool expired;
+};
+
+static const
+struct uwb_mas_bm uwb_mas_bm_zero = { .bm = { 0 } };
+
+static inline void uwb_mas_bm_copy_le(void *dst, const struct uwb_mas_bm *mas)
+{
+	bitmap_copy_le(dst, mas->bm, UWB_NUM_MAS);
+}
+
+/**
+ * struct uwb_drp_avail - a radio controller's view of MAS usage
+ * @global:   MAS unused by neighbors (excluding reservations targetted
+ *            or owned by the local radio controller) or the beaon period
+ * @local:    MAS unused by local established reservations
+ * @pending:  MAS unused by local pending reservations
+ * @ie:       DRP Availability IE to be included in the beacon
+ * @ie_valid: true iff @ie is valid and does not need to regenerated from
+ *            @global and @local
+ *
+ * Each radio controller maintains a view of MAS usage or
+ * availability. MAS available for a new reservation are determined
+ * from the intersection of @global, @local, and @pending.
+ *
+ * The radio controller must transmit a DRP Availability IE that's the
+ * intersection of @global and @local.
+ *
+ * A set bit indicates the MAS is unused and available.
+ *
+ * rc->rsvs_mutex should be held before accessing this data structure.
+ *
+ * [ECMA-368] section 17.4.3.
+ */
+struct uwb_drp_avail {
+	DECLARE_BITMAP(global, UWB_NUM_MAS);
+	DECLARE_BITMAP(local, UWB_NUM_MAS);
+	DECLARE_BITMAP(pending, UWB_NUM_MAS);
+	struct uwb_ie_drp_avail ie;
+	bool ie_valid;
+};
+
+
+const char *uwb_rsv_state_str(enum uwb_rsv_state state);
+const char *uwb_rsv_type_str(enum uwb_drp_type type);
+
+struct uwb_rsv *uwb_rsv_create(struct uwb_rc *rc, uwb_rsv_cb_f cb,
+			       void *pal_priv);
+void uwb_rsv_destroy(struct uwb_rsv *rsv);
+
+int uwb_rsv_establish(struct uwb_rsv *rsv);
+int uwb_rsv_modify(struct uwb_rsv *rsv,
+		   int max_mas, int min_mas, int sparsity);
+void uwb_rsv_terminate(struct uwb_rsv *rsv);
+
+void uwb_rsv_accept(struct uwb_rsv *rsv, uwb_rsv_cb_f cb, void *pal_priv);
+
+/**
+ * Radio Control Interface instance
+ *
+ *
+ * Life cycle rules: those of the UWB Device.
+ *
+ * @index:    an index number for this radio controller, as used in the
+ *            device name.
+ * @version:  version of protocol supported by this device
+ * @priv:     Backend implementation; rw with uwb_dev.dev.sem taken.
+ * @cmd:      Backend implementation to execute commands; rw and call
+ *            only  with uwb_dev.dev.sem taken.
+ * @reset:    Hardware reset of radio controller and any PAL controllers.
+ * @filter:   Backend implementation to manipulate data to and from device
+ *            to be compliant to specification assumed by driver (WHCI
+ *            0.95).
+ *
+ *            uwb_dev.dev.mutex is used to execute commands and update
+ *            the corresponding structures; can't use a spinlock
+ *            because rc->cmd() can sleep.
+ * @ies:         This is a dynamically allocated array cacheing the
+ *               IEs (settable by the host) that the beacon of this
+ *               radio controller is currently sending.
+ *
+ *               In reality, we store here the full command we set to
+ *               the radio controller (which is basically a command
+ *               prefix followed by all the IEs the beacon currently
+ *               contains). This way we don't have to realloc and
+ *               memcpy when setting it.
+ *
+ *               We set this up in uwb_rc_ie_setup(), where we alloc
+ *               this struct, call get_ie() [so we know which IEs are
+ *               currently being sent, if any].
+ *
+ * @ies_capacity:Amount of space (in bytes) allocated in @ies. The
+ *               amount used is given by sizeof(*ies) plus ies->wIELength
+ *               (which is a little endian quantity all the time).
+ * @ies_mutex:   protect the IE cache
+ * @dbg:         information for the debug interface
+ */
+struct uwb_rc {
+	struct uwb_dev uwb_dev;
+	int index;
+	u16 version;
+
+	struct module *owner;
+	void *priv;
+	int (*start)(struct uwb_rc *rc);
+	void (*stop)(struct uwb_rc *rc);
+	int (*cmd)(struct uwb_rc *, const struct uwb_rccb *, size_t);
+	int (*reset)(struct uwb_rc *rc);
+	int (*filter_cmd)(struct uwb_rc *, struct uwb_rccb **, size_t *);
+	int (*filter_event)(struct uwb_rc *, struct uwb_rceb **, const size_t,
+			    size_t *, size_t *);
+
+	spinlock_t neh_lock;		/* protects neh_* and ctx_* */
+	struct list_head neh_list;	/* Open NE handles */
+	unsigned long ctx_bm[UWB_RC_CTX_MAX / 8 / sizeof(unsigned long)];
+	u8 ctx_roll;
+
+	int beaconing;			/* Beaconing state [channel number] */
+	int scanning;
+	enum uwb_scan_type scan_type:3;
+	unsigned ready:1;
+	struct uwb_notifs_chain notifs_chain;
+
+	struct uwb_drp_avail drp_avail;
+	struct list_head reservations;
+	struct mutex rsvs_mutex;
+	struct workqueue_struct *rsv_workq;
+	struct work_struct rsv_update_work;
+
+	struct mutex ies_mutex;
+	struct uwb_rc_cmd_set_ie *ies;
+	size_t ies_capacity;
+
+	spinlock_t pal_lock;
+	struct list_head pals;
+
+	struct uwb_dbg *dbg;
+};
+
+
+/**
+ * struct uwb_pal - a UWB PAL
+ * @name:    descriptive name for this PAL (wushc, wlp, etc.).
+ * @device:  a device for the PAL.  Used to link the PAL and the radio
+ *           controller in sysfs.
+ * @new_rsv: called when a peer requests a reservation (may be NULL if
+ *           the PAL cannot accept reservation requests).
+ *
+ * A Protocol Adaptation Layer (PAL) is a user of the WiMedia UWB
+ * radio platform (e.g., WUSB, WLP or Bluetooth UWB AMP).
+ *
+ * The PALs using a radio controller must register themselves to
+ * permit the UWB stack to coordinate usage of the radio between the
+ * various PALs or to allow PALs to response to certain requests from
+ * peers.
+ *
+ * A struct uwb_pal should be embedded in a containing structure
+ * belonging to the PAL and initialized with uwb_pal_init()).  Fields
+ * should be set appropriately by the PAL before registering the PAL
+ * with uwb_pal_register().
+ */
+struct uwb_pal {
+	struct list_head node;
+	const char *name;
+	struct device *device;
+	void (*new_rsv)(struct uwb_rsv *rsv);
+};
+
+void uwb_pal_init(struct uwb_pal *pal);
+int uwb_pal_register(struct uwb_rc *rc, struct uwb_pal *pal);
+void uwb_pal_unregister(struct uwb_rc *rc, struct uwb_pal *pal);
+
+/*
+ * General public API
+ *
+ * This API can be used by UWB device drivers or by those implementing
+ * UWB Radio Controllers
+ */
+struct uwb_dev *uwb_dev_get_by_devaddr(struct uwb_rc *rc,
+				       const struct uwb_dev_addr *devaddr);
+struct uwb_dev *uwb_dev_get_by_rc(struct uwb_dev *, struct uwb_rc *);
+static inline void uwb_dev_get(struct uwb_dev *uwb_dev)
+{
+	get_device(&uwb_dev->dev);
+}
+static inline void uwb_dev_put(struct uwb_dev *uwb_dev)
+{
+	put_device(&uwb_dev->dev);
+}
+struct uwb_dev *uwb_dev_try_get(struct uwb_rc *rc, struct uwb_dev *uwb_dev);
+
+/**
+ * Callback function for 'uwb_{dev,rc}_foreach()'.
+ *
+ * @dev:  Linux device instance
+ *        'uwb_dev = container_of(dev, struct uwb_dev, dev)'
+ * @priv: Data passed by the caller to 'uwb_{dev,rc}_foreach()'.
+ *
+ * @returns: 0 to continue the iterations, any other val to stop
+ *           iterating and return the value to the caller of
+ *           _foreach().
+ */
+typedef int (*uwb_dev_for_each_f)(struct device *dev, void *priv);
+int uwb_dev_for_each(struct uwb_rc *rc, uwb_dev_for_each_f func, void *priv);
+
+struct uwb_rc *uwb_rc_alloc(void);
+struct uwb_rc *uwb_rc_get_by_dev(const struct uwb_dev_addr *);
+struct uwb_rc *uwb_rc_get_by_grandpa(const struct device *);
+void uwb_rc_put(struct uwb_rc *rc);
+
+typedef void (*uwb_rc_cmd_cb_f)(struct uwb_rc *rc, void *arg,
+                                struct uwb_rceb *reply, ssize_t reply_size);
+
+int uwb_rc_cmd_async(struct uwb_rc *rc, const char *cmd_name,
+		     struct uwb_rccb *cmd, size_t cmd_size,
+		     u8 expected_type, u16 expected_event,
+		     uwb_rc_cmd_cb_f cb, void *arg);
+ssize_t uwb_rc_cmd(struct uwb_rc *rc, const char *cmd_name,
+		   struct uwb_rccb *cmd, size_t cmd_size,
+		   struct uwb_rceb *reply, size_t reply_size);
+ssize_t uwb_rc_vcmd(struct uwb_rc *rc, const char *cmd_name,
+		    struct uwb_rccb *cmd, size_t cmd_size,
+		    u8 expected_type, u16 expected_event,
+		    struct uwb_rceb **preply);
+ssize_t uwb_rc_get_ie(struct uwb_rc *, struct uwb_rc_evt_get_ie **);
+int uwb_bg_joined(struct uwb_rc *rc);
+
+size_t __uwb_addr_print(char *, size_t, const unsigned char *, int);
+
+int uwb_rc_dev_addr_set(struct uwb_rc *, const struct uwb_dev_addr *);
+int uwb_rc_dev_addr_get(struct uwb_rc *, struct uwb_dev_addr *);
+int uwb_rc_mac_addr_set(struct uwb_rc *, const struct uwb_mac_addr *);
+int uwb_rc_mac_addr_get(struct uwb_rc *, struct uwb_mac_addr *);
+int __uwb_mac_addr_assigned_check(struct device *, void *);
+int __uwb_dev_addr_assigned_check(struct device *, void *);
+
+/* Print in @buf a pretty repr of @addr */
+static inline size_t uwb_dev_addr_print(char *buf, size_t buf_size,
+					const struct uwb_dev_addr *addr)
+{
+	return __uwb_addr_print(buf, buf_size, addr->data, 0);
+}
+
+/* Print in @buf a pretty repr of @addr */
+static inline size_t uwb_mac_addr_print(char *buf, size_t buf_size,
+					const struct uwb_mac_addr *addr)
+{
+	return __uwb_addr_print(buf, buf_size, addr->data, 1);
+}
+
+/* @returns 0 if device addresses @addr2 and @addr1 are equal */
+static inline int uwb_dev_addr_cmp(const struct uwb_dev_addr *addr1,
+				   const struct uwb_dev_addr *addr2)
+{
+	return memcmp(addr1, addr2, sizeof(*addr1));
+}
+
+/* @returns 0 if MAC addresses @addr2 and @addr1 are equal */
+static inline int uwb_mac_addr_cmp(const struct uwb_mac_addr *addr1,
+				   const struct uwb_mac_addr *addr2)
+{
+	return memcmp(addr1, addr2, sizeof(*addr1));
+}
+
+/* @returns !0 if a MAC @addr is a broadcast address */
+static inline int uwb_mac_addr_bcast(const struct uwb_mac_addr *addr)
+{
+	struct uwb_mac_addr bcast = {
+		.data = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }
+	};
+	return !uwb_mac_addr_cmp(addr, &bcast);
+}
+
+/* @returns !0 if a MAC @addr is all zeroes*/
+static inline int uwb_mac_addr_unset(const struct uwb_mac_addr *addr)
+{
+	struct uwb_mac_addr unset = {
+		.data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
+	};
+	return !uwb_mac_addr_cmp(addr, &unset);
+}
+
+/* @returns !0 if the address is in use. */
+static inline unsigned __uwb_dev_addr_assigned(struct uwb_rc *rc,
+					       struct uwb_dev_addr *addr)
+{
+	return uwb_dev_for_each(rc, __uwb_dev_addr_assigned_check, addr);
+}
+
+/*
+ * UWB Radio Controller API
+ *
+ * This API is used (in addition to the general API) to implement UWB
+ * Radio Controllers.
+ */
+void uwb_rc_init(struct uwb_rc *);
+int uwb_rc_add(struct uwb_rc *, struct device *dev, void *rc_priv);
+void uwb_rc_rm(struct uwb_rc *);
+void uwb_rc_neh_grok(struct uwb_rc *, void *, size_t);
+void uwb_rc_neh_error(struct uwb_rc *, int);
+void uwb_rc_reset_all(struct uwb_rc *rc);
+
+/**
+ * uwb_rsv_is_owner - is the owner of this reservation the RC?
+ * @rsv: the reservation
+ */
+static inline bool uwb_rsv_is_owner(struct uwb_rsv *rsv)
+{
+	return rsv->owner == &rsv->rc->uwb_dev;
+}
+
+/**
+ * Events generated by UWB that can be passed to any listeners
+ *
+ * Higher layers can register callback functions with the radio
+ * controller using uwb_notifs_register(). The radio controller
+ * maintains a list of all registered handlers and will notify all
+ * nodes when an event occurs.
+ */
+enum uwb_notifs {
+	UWB_NOTIF_BG_JOIN = 0,	/* radio controller joined a beacon group */
+	UWB_NOTIF_BG_LEAVE = 1,	/* radio controller left a beacon group */
+	UWB_NOTIF_ONAIR,
+	UWB_NOTIF_OFFAIR,
+};
+
+/* Callback function registered with UWB */
+struct uwb_notifs_handler {
+	struct list_head list_node;
+	void (*cb)(void *, struct uwb_dev *, enum uwb_notifs);
+	void *data;
+};
+
+int uwb_notifs_register(struct uwb_rc *, struct uwb_notifs_handler *);
+int uwb_notifs_deregister(struct uwb_rc *, struct uwb_notifs_handler *);
+
+
+/**
+ * UWB radio controller Event Size Entry (for creating entry tables)
+ *
+ * WUSB and WHCI define events and notifications, and they might have
+ * fixed or variable size.
+ *
+ * Each event/notification has a size which is not necessarily known
+ * in advance based on the event code. As well, vendor specific
+ * events/notifications will have a size impossible to determine
+ * unless we know about the device's specific details.
+ *
+ * It was way too smart of the spec writers not to think that it would
+ * be impossible for a generic driver to skip over vendor specific
+ * events/notifications if there are no LENGTH fields in the HEADER of
+ * each message...the transaction size cannot be counted on as the
+ * spec does not forbid to pack more than one event in a single
+ * transaction.
+ *
+ * Thus, we guess sizes with tables (or for events, when you know the
+ * size ahead of time you can use uwb_rc_neh_extra_size*()). We
+ * register tables with the known events and their sizes, and then we
+ * traverse those tables. For those with variable length, we provide a
+ * way to lookup the size inside the event/notification's
+ * payload. This allows device-specific event size tables to be
+ * registered.
+ *
+ * @size:   Size of the payload
+ *
+ * @offset: if != 0, at offset @offset-1 starts a field with a length
+ *          that has to be added to @size. The format of the field is
+ *          given by @type.
+ *
+ * @type:   Type and length of the offset field. Most common is LE 16
+ *          bits (that's why that is zero); others are there mostly to
+ *          cover for bugs and weirdos.
+ */
+struct uwb_est_entry {
+	size_t size;
+	unsigned offset;
+	enum { UWB_EST_16 = 0, UWB_EST_8 = 1 } type;
+};
+
+int uwb_est_register(u8 type, u8 code_high, u16 vendor, u16 product,
+		     const struct uwb_est_entry *, size_t entries);
+int uwb_est_unregister(u8 type, u8 code_high, u16 vendor, u16 product,
+		       const struct uwb_est_entry *, size_t entries);
+ssize_t uwb_est_find_size(struct uwb_rc *rc, const struct uwb_rceb *rceb,
+			  size_t len);
+
+/* -- Misc */
+
+enum {
+	EDC_MAX_ERRORS = 10,
+	EDC_ERROR_TIMEFRAME = HZ,
+};
+
+/* error density counter */
+struct edc {
+	unsigned long timestart;
+	u16 errorcount;
+};
+
+static inline
+void edc_init(struct edc *edc)
+{
+	edc->timestart = jiffies;
+}
+
+/* Called when an error occured.
+ * This is way to determine if the number of acceptable errors per time
+ * period has been exceeded. It is not accurate as there are cases in which
+ * this scheme will not work, for example if there are periodic occurences
+ * of errors that straddle updates to the start time. This scheme is
+ * sufficient for our usage.
+ *
+ * @returns 1 if maximum acceptable errors per timeframe has been exceeded.
+ */
+static inline int edc_inc(struct edc *err_hist, u16 max_err, u16 timeframe)
+{
+	unsigned long now;
+
+	now = jiffies;
+	if (now - err_hist->timestart > timeframe) {
+		err_hist->errorcount = 1;
+		err_hist->timestart = now;
+	} else if (++err_hist->errorcount > max_err) {
+			err_hist->errorcount = 0;
+			err_hist->timestart = now;
+			return 1;
+	}
+	return 0;
+}
+
+
+/* Information Element handling */
+
+/* For representing the state of writing to a buffer when iterating */
+struct uwb_buf_ctx {
+	char *buf;
+	size_t bytes, size;
+};
+
+typedef int (*uwb_ie_f)(struct uwb_dev *, const struct uwb_ie_hdr *,
+			size_t, void *);
+struct uwb_ie_hdr *uwb_ie_next(void **ptr, size_t *len);
+ssize_t uwb_ie_for_each(struct uwb_dev *uwb_dev, uwb_ie_f fn, void *data,
+			const void *buf, size_t size);
+int uwb_ie_dump_hex(struct uwb_dev *, const struct uwb_ie_hdr *,
+		    size_t, void *);
+int uwb_rc_set_ie(struct uwb_rc *, struct uwb_rc_cmd_set_ie *);
+struct uwb_ie_hdr *uwb_ie_next(void **ptr, size_t *len);
+
+
+/*
+ * Transmission statistics
+ *
+ * UWB uses LQI and RSSI (one byte values) for reporting radio signal
+ * strength and line quality indication. We do quick and dirty
+ * averages of those. They are signed values, btw.
+ *
+ * For 8 bit quantities, we keep the min, the max, an accumulator
+ * (@sigma) and a # of samples. When @samples gets to 255, we compute
+ * the average (@sigma / @samples), place it in @sigma and reset
+ * @samples to 1 (so we use it as the first sample).
+ *
+ * Now, statistically speaking, probably I am kicking the kidneys of
+ * some books I have in my shelves collecting dust, but I just want to
+ * get an approx, not the Nobel.
+ *
+ * LOCKING: there is no locking per se, but we try to keep a lockless
+ * schema. Only _add_samples() modifies the values--as long as you
+ * have other locking on top that makes sure that no two calls of
+ * _add_sample() happen at the same time, then we are fine. Now, for
+ * resetting the values we just set @samples to 0 and that makes the
+ * next _add_sample() to start with defaults. Reading the values in
+ * _show() currently can race, so you need to make sure the calls are
+ * under the same lock that protects calls to _add_sample(). FIXME:
+ * currently unlocked (It is not ultraprecise but does the trick. Bite
+ * me).
+ */
+struct stats {
+	s8 min, max;
+	s16 sigma;
+	atomic_t samples;
+};
+
+static inline
+void stats_init(struct stats *stats)
+{
+	atomic_set(&stats->samples, 0);
+	wmb();
+}
+
+static inline
+void stats_add_sample(struct stats *stats, s8 sample)
+{
+	s8 min, max;
+	s16 sigma;
+	unsigned samples = atomic_read(&stats->samples);
+	if (samples == 0) {	/* it was zero before, so we initialize */
+		min = 127;
+		max = -128;
+		sigma = 0;
+	} else {
+		min = stats->min;
+		max = stats->max;
+		sigma = stats->sigma;
+	}
+
+	if (sample < min)	/* compute new values */
+		min = sample;
+	else if (sample > max)
+		max = sample;
+	sigma += sample;
+
+	stats->min = min;	/* commit */
+	stats->max = max;
+	stats->sigma = sigma;
+	if (atomic_add_return(1, &stats->samples) > 255) {
+		/* wrapped around! reset */
+		stats->sigma = sigma / 256;
+		atomic_set(&stats->samples, 1);
+	}
+}
+
+static inline ssize_t stats_show(struct stats *stats, char *buf)
+{
+	int min, max, avg;
+	int samples = atomic_read(&stats->samples);
+	if (samples == 0)
+		min = max = avg = 0;
+	else {
+		min = stats->min;
+		max = stats->max;
+		avg = stats->sigma / samples;
+	}
+	return scnprintf(buf, PAGE_SIZE, "%d %d %d\n", min, max, avg);
+}
+
+static inline ssize_t stats_store(struct stats *stats, const char *buf,
+				  size_t size)
+{
+	stats_init(stats);
+	return size;
+}
+
+#endif /* #ifndef __LINUX__UWB_H__ */
diff --git a/include/linux/uwb/debug-cmd.h b/include/linux/uwb/debug-cmd.h
new file mode 100644
index 000000000000..1141f41bab5c
--- /dev/null
+++ b/include/linux/uwb/debug-cmd.h
@@ -0,0 +1,57 @@
+/*
+ * Ultra Wide Band
+ * Debug interface commands
+ *
+ * Copyright (C) 2008 Cambridge Silicon Radio Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __LINUX__UWB__DEBUG_CMD_H__
+#define __LINUX__UWB__DEBUG_CMD_H__
+
+#include <linux/types.h>
+
+/*
+ * Debug interface commands
+ *
+ * UWB_DBG_CMD_RSV_ESTABLISH: Establish a new unicast reservation.
+ *
+ * UWB_DBG_CMD_RSV_TERMINATE: Terminate the Nth reservation.
+ */
+
+enum uwb_dbg_cmd_type {
+	UWB_DBG_CMD_RSV_ESTABLISH = 1,
+	UWB_DBG_CMD_RSV_TERMINATE = 2,
+};
+
+struct uwb_dbg_cmd_rsv_establish {
+	__u8  target[6];
+	__u8  type;
+	__u16 max_mas;
+	__u16 min_mas;
+	__u8  sparsity;
+};
+
+struct uwb_dbg_cmd_rsv_terminate {
+	int index;
+};
+
+struct uwb_dbg_cmd {
+	__u32 type;
+	union {
+		struct uwb_dbg_cmd_rsv_establish rsv_establish;
+		struct uwb_dbg_cmd_rsv_terminate rsv_terminate;
+	};
+};
+
+#endif /* #ifndef __LINUX__UWB__DEBUG_CMD_H__ */
diff --git a/include/linux/uwb/debug.h b/include/linux/uwb/debug.h
new file mode 100644
index 000000000000..a86a73fe303f
--- /dev/null
+++ b/include/linux/uwb/debug.h
@@ -0,0 +1,82 @@
+/*
+ * Ultra Wide Band
+ * Debug Support
+ *
+ * Copyright (C) 2005-2006 Intel Corporation
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * FIXME: doc
+ * Invoke like:
+ *
+ * #define D_LOCAL 4
+ * #include <linux/uwb/debug.h>
+ *
+ * At the end of your include files.
+ */
+#include <linux/types.h>
+
+struct device;
+extern void dump_bytes(struct device *dev, const void *_buf, size_t rsize);
+
+/* Master debug switch; !0 enables, 0 disables */
+#define D_MASTER (!0)
+
+/* Local (per-file) debug switch; #define before #including */
+#ifndef D_LOCAL
+#define D_LOCAL 0
+#endif
+
+#undef __d_printf
+#undef d_fnstart
+#undef d_fnend
+#undef d_printf
+#undef d_dump
+
+#define __d_printf(l, _tag, _dev, f, a...)				\
+do {									\
+	struct device *__dev = (_dev);					\
+	if (D_MASTER && D_LOCAL >= (l)) {				\
+		char __head[64] = "";					\
+		if (_dev != NULL) {					\
+			if ((unsigned long)__dev < 4096)		\
+				printk(KERN_ERR "E: Corrupt dev %p\n",	\
+					__dev);				\
+			else						\
+				snprintf(__head, sizeof(__head),	\
+					 "%s %s: ",			\
+					 dev_driver_string(__dev),	\
+					 __dev->bus_id);		\
+		}							\
+		printk(KERN_ERR "%s%s" _tag ": " f, __head,		\
+			__func__, ## a);				\
+	}								\
+} while (0 && _dev)
+
+#define d_fnstart(l, _dev, f, a...)	\
+	__d_printf(l, " FNSTART", _dev, f, ## a)
+#define d_fnend(l, _dev, f, a...)	\
+	__d_printf(l, " FNEND", _dev, f, ## a)
+#define d_printf(l, _dev, f, a...)	\
+	__d_printf(l, "", _dev, f, ## a)
+#define d_dump(l, _dev, ptr, size)		\
+do {						\
+	struct device *__dev = _dev;		\
+	if (D_MASTER && D_LOCAL >= (l))		\
+		dump_bytes(__dev, ptr, size);	\
+} while (0 && _dev)
+#define d_test(l) (D_MASTER && D_LOCAL >= (l))
diff --git a/include/linux/uwb/spec.h b/include/linux/uwb/spec.h
new file mode 100644
index 000000000000..198c15f8e251
--- /dev/null
+++ b/include/linux/uwb/spec.h
@@ -0,0 +1,727 @@
+/*
+ * Ultra Wide Band
+ * UWB Standard definitions
+ *
+ * Copyright (C) 2005-2006 Intel Corporation
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * All these definitions are based on the ECMA-368 standard.
+ *
+ * Note all definitions are Little Endian in the wire, and we will
+ * convert them to host order before operating on the bitfields (that
+ * yes, we use extensively).
+ */
+
+#ifndef __LINUX__UWB_SPEC_H__
+#define __LINUX__UWB_SPEC_H__
+
+#include <linux/types.h>
+#include <linux/bitmap.h>
+
+#define i1480_FW 0x00000303
+/* #define i1480_FW 0x00000302 */
+
+/**
+ * Number of Medium Access Slots in a superframe.
+ *
+ * UWB divides time in SuperFrames, each one divided in 256 pieces, or
+ * Medium Access Slots. See MBOA MAC[5.4.5] for details. The MAS is the
+ * basic bandwidth allocation unit in UWB.
+ */
+enum { UWB_NUM_MAS = 256 };
+
+/**
+ * Number of Zones in superframe.
+ *
+ * UWB divides the superframe into zones with numbering starting from BPST.
+ * See MBOA MAC[16.8.6]
+ */
+enum { UWB_NUM_ZONES = 16 };
+
+/*
+ * Number of MAS in a zone.
+ */
+#define UWB_MAS_PER_ZONE (UWB_NUM_MAS / UWB_NUM_ZONES)
+
+/*
+ * Number of streams per DRP reservation between a pair of devices.
+ *
+ * [ECMA-368] section 16.8.6.
+ */
+enum { UWB_NUM_STREAMS = 8 };
+
+/*
+ * mMasLength
+ *
+ * The length of a MAS in microseconds.
+ *
+ * [ECMA-368] section 17.16.
+ */
+enum { UWB_MAS_LENGTH_US = 256 };
+
+/*
+ * mBeaconSlotLength
+ *
+ * The length of the beacon slot in microseconds.
+ *
+ * [ECMA-368] section 17.16
+ */
+enum { UWB_BEACON_SLOT_LENGTH_US = 85 };
+
+/*
+ * mMaxLostBeacons
+ *
+ * The number beacons missing in consecutive superframes before a
+ * device can be considered as unreachable.
+ *
+ * [ECMA-368] section 17.16
+ */
+enum { UWB_MAX_LOST_BEACONS = 3 };
+
+/*
+ * Length of a superframe in microseconds.
+ */
+#define UWB_SUPERFRAME_LENGTH_US (UWB_MAS_LENGTH_US * UWB_NUM_MAS)
+
+/**
+ * UWB MAC address
+ *
+ * It is *imperative* that this struct is exactly 6 packed bytes (as
+ * it is also used to define headers sent down and up the wire/radio).
+ */
+struct uwb_mac_addr {
+	u8 data[6];
+} __attribute__((packed));
+
+
+/**
+ * UWB device address
+ *
+ * It is *imperative* that this struct is exactly 6 packed bytes (as
+ * it is also used to define headers sent down and up the wire/radio).
+ */
+struct uwb_dev_addr {
+	u8 data[2];
+} __attribute__((packed));
+
+
+/**
+ * Types of UWB addresses
+ *
+ * Order matters (by size).
+ */
+enum uwb_addr_type {
+	UWB_ADDR_DEV = 0,
+	UWB_ADDR_MAC = 1,
+};
+
+
+/** Size of a char buffer for printing a MAC/device address */
+enum { UWB_ADDR_STRSIZE = 32 };
+
+
+/** UWB WiMedia protocol IDs. */
+enum uwb_prid {
+	UWB_PRID_WLP_RESERVED   = 0x0000,
+	UWB_PRID_WLP		= 0x0001,
+	UWB_PRID_WUSB_BOT	= 0x0010,
+	UWB_PRID_WUSB		= 0x0010,
+	UWB_PRID_WUSB_TOP	= 0x001F,
+};
+
+
+/** PHY Rate (MBOA MAC[7.8.12, Table 61]) */
+enum uwb_phy_rate {
+	UWB_PHY_RATE_53 = 0,
+	UWB_PHY_RATE_80,
+	UWB_PHY_RATE_106,
+	UWB_PHY_RATE_160,
+	UWB_PHY_RATE_200,
+	UWB_PHY_RATE_320,
+	UWB_PHY_RATE_400,
+	UWB_PHY_RATE_480,
+	UWB_PHY_RATE_INVALID
+};
+
+
+/**
+ * Different ways to scan (MBOA MAC[6.2.2, Table 8], WUSB[Table 8-78])
+ */
+enum uwb_scan_type {
+	UWB_SCAN_ONLY = 0,
+	UWB_SCAN_OUTSIDE_BP,
+	UWB_SCAN_WHILE_INACTIVE,
+	UWB_SCAN_DISABLED,
+	UWB_SCAN_ONLY_STARTTIME,
+	UWB_SCAN_TOP
+};
+
+
+/** ACK Policy types (MBOA MAC[7.2.1.3]) */
+enum uwb_ack_pol {
+	UWB_ACK_NO = 0,
+	UWB_ACK_INM = 1,
+	UWB_ACK_B = 2,
+	UWB_ACK_B_REQ = 3,
+};
+
+
+/** DRP reservation types ([ECMA-368 table 106) */
+enum uwb_drp_type {
+	UWB_DRP_TYPE_ALIEN_BP = 0,
+	UWB_DRP_TYPE_HARD,
+	UWB_DRP_TYPE_SOFT,
+	UWB_DRP_TYPE_PRIVATE,
+	UWB_DRP_TYPE_PCA,
+};
+
+
+/** DRP Reason Codes ([ECMA-368] table 107) */
+enum uwb_drp_reason {
+	UWB_DRP_REASON_ACCEPTED = 0,
+	UWB_DRP_REASON_CONFLICT,
+	UWB_DRP_REASON_PENDING,
+	UWB_DRP_REASON_DENIED,
+	UWB_DRP_REASON_MODIFIED,
+};
+
+/**
+ *  DRP Notification Reason Codes (WHCI 0.95 [3.1.4.9])
+ */
+enum uwb_drp_notif_reason {
+	UWB_DRP_NOTIF_DRP_IE_RCVD = 0,
+	UWB_DRP_NOTIF_CONFLICT,
+	UWB_DRP_NOTIF_TERMINATE,
+};
+
+
+/** Allocation of MAS slots in a DRP request MBOA MAC[7.8.7] */
+struct uwb_drp_alloc {
+	__le16 zone_bm;
+	__le16 mas_bm;
+} __attribute__((packed));
+
+
+/** General MAC Header format (ECMA-368[16.2]) */
+struct uwb_mac_frame_hdr {
+	__le16 Frame_Control;
+	struct uwb_dev_addr DestAddr;
+	struct uwb_dev_addr SrcAddr;
+	__le16 Sequence_Control;
+	__le16 Access_Information;
+} __attribute__((packed));
+
+
+/**
+ * uwb_beacon_frame - a beacon frame including MAC headers
+ *
+ * [ECMA] section 16.3.
+ */
+struct uwb_beacon_frame {
+	struct uwb_mac_frame_hdr hdr;
+	struct uwb_mac_addr Device_Identifier;	/* may be a NULL EUI-48 */
+	u8 Beacon_Slot_Number;
+	u8 Device_Control;
+	u8 IEData[];
+} __attribute__((packed));
+
+
+/** Information Element codes (MBOA MAC[T54]) */
+enum uwb_ie {
+	UWB_PCA_AVAILABILITY = 2,
+	UWB_IE_DRP_AVAILABILITY = 8,
+	UWB_IE_DRP = 9,
+	UWB_BP_SWITCH_IE = 11,
+	UWB_MAC_CAPABILITIES_IE = 12,
+	UWB_PHY_CAPABILITIES_IE = 13,
+	UWB_APP_SPEC_PROBE_IE = 15,
+	UWB_IDENTIFICATION_IE = 19,
+	UWB_MASTER_KEY_ID_IE = 20,
+	UWB_IE_WLP = 250, /* WiMedia Logical Link Control Protocol WLP 0.99 */
+	UWB_APP_SPEC_IE = 255,
+};
+
+
+/**
+ * Header common to all Information Elements (IEs)
+ */
+struct uwb_ie_hdr {
+	u8 element_id;	/* enum uwb_ie */
+	u8 length;
+} __attribute__((packed));
+
+
+/** Dynamic Reservation Protocol IE (MBOA MAC[7.8.6]) */
+struct uwb_ie_drp {
+	struct uwb_ie_hdr	hdr;
+	__le16                  drp_control;
+	struct uwb_dev_addr	dev_addr;
+	struct uwb_drp_alloc	allocs[];
+} __attribute__((packed));
+
+static inline int uwb_ie_drp_type(struct uwb_ie_drp *ie)
+{
+	return (le16_to_cpu(ie->drp_control) >> 0) & 0x7;
+}
+
+static inline int uwb_ie_drp_stream_index(struct uwb_ie_drp *ie)
+{
+	return (le16_to_cpu(ie->drp_control) >> 3) & 0x7;
+}
+
+static inline int uwb_ie_drp_reason_code(struct uwb_ie_drp *ie)
+{
+	return (le16_to_cpu(ie->drp_control) >> 6) & 0x7;
+}
+
+static inline int uwb_ie_drp_status(struct uwb_ie_drp *ie)
+{
+	return (le16_to_cpu(ie->drp_control) >> 9) & 0x1;
+}
+
+static inline int uwb_ie_drp_owner(struct uwb_ie_drp *ie)
+{
+	return (le16_to_cpu(ie->drp_control) >> 10) & 0x1;
+}
+
+static inline int uwb_ie_drp_tiebreaker(struct uwb_ie_drp *ie)
+{
+	return (le16_to_cpu(ie->drp_control) >> 11) & 0x1;
+}
+
+static inline int uwb_ie_drp_unsafe(struct uwb_ie_drp *ie)
+{
+	return (le16_to_cpu(ie->drp_control) >> 12) & 0x1;
+}
+
+static inline void uwb_ie_drp_set_type(struct uwb_ie_drp *ie, enum uwb_drp_type type)
+{
+	u16 drp_control = le16_to_cpu(ie->drp_control);
+	drp_control = (drp_control & ~(0x7 << 0)) | (type << 0);
+	ie->drp_control = cpu_to_le16(drp_control);
+}
+
+static inline void uwb_ie_drp_set_stream_index(struct uwb_ie_drp *ie, int stream_index)
+{
+	u16 drp_control = le16_to_cpu(ie->drp_control);
+	drp_control = (drp_control & ~(0x7 << 3)) | (stream_index << 3);
+	ie->drp_control = cpu_to_le16(drp_control);
+}
+
+static inline void uwb_ie_drp_set_reason_code(struct uwb_ie_drp *ie,
+				       enum uwb_drp_reason reason_code)
+{
+	u16 drp_control = le16_to_cpu(ie->drp_control);
+	drp_control = (ie->drp_control & ~(0x7 << 6)) | (reason_code << 6);
+	ie->drp_control = cpu_to_le16(drp_control);
+}
+
+static inline void uwb_ie_drp_set_status(struct uwb_ie_drp *ie, int status)
+{
+	u16 drp_control = le16_to_cpu(ie->drp_control);
+	drp_control = (drp_control & ~(0x1 << 9)) | (status << 9);
+	ie->drp_control = cpu_to_le16(drp_control);
+}
+
+static inline void uwb_ie_drp_set_owner(struct uwb_ie_drp *ie, int owner)
+{
+	u16 drp_control = le16_to_cpu(ie->drp_control);
+	drp_control = (drp_control & ~(0x1 << 10)) | (owner << 10);
+	ie->drp_control = cpu_to_le16(drp_control);
+}
+
+static inline void uwb_ie_drp_set_tiebreaker(struct uwb_ie_drp *ie, int tiebreaker)
+{
+	u16 drp_control = le16_to_cpu(ie->drp_control);
+	drp_control = (drp_control & ~(0x1 << 11)) | (tiebreaker << 11);
+	ie->drp_control = cpu_to_le16(drp_control);
+}
+
+static inline void uwb_ie_drp_set_unsafe(struct uwb_ie_drp *ie, int unsafe)
+{
+	u16 drp_control = le16_to_cpu(ie->drp_control);
+	drp_control = (drp_control & ~(0x1 << 12)) | (unsafe << 12);
+	ie->drp_control = cpu_to_le16(drp_control);
+}
+
+/** Dynamic Reservation Protocol IE (MBOA MAC[7.8.7]) */
+struct uwb_ie_drp_avail {
+	struct uwb_ie_hdr	hdr;
+	DECLARE_BITMAP(bmp, UWB_NUM_MAS);
+} __attribute__((packed));
+
+/**
+ * The Vendor ID is set to an OUI that indicates the vendor of the device.
+ * ECMA-368 [16.8.10]
+ */
+struct uwb_vendor_id {
+	u8 data[3];
+} __attribute__((packed));
+
+/**
+ * The device type ID
+ * FIXME: clarify what this means
+ * ECMA-368 [16.8.10]
+ */
+struct uwb_device_type_id {
+	u8 data[3];
+} __attribute__((packed));
+
+
+/**
+ * UWB device information types
+ * ECMA-368 [16.8.10]
+ */
+enum uwb_dev_info_type {
+	UWB_DEV_INFO_VENDOR_ID = 0,
+	UWB_DEV_INFO_VENDOR_TYPE,
+	UWB_DEV_INFO_NAME,
+};
+
+/**
+ * UWB device information found in Identification IE
+ * ECMA-368 [16.8.10]
+ */
+struct uwb_dev_info {
+	u8 type;	/* enum uwb_dev_info_type */
+	u8 length;
+	u8 data[];
+} __attribute__((packed));
+
+/**
+ * UWB Identification IE
+ * ECMA-368 [16.8.10]
+ */
+struct uwb_identification_ie {
+	struct uwb_ie_hdr hdr;
+	struct uwb_dev_info info[];
+} __attribute__((packed));
+
+/*
+ * UWB Radio Controller
+ *
+ * These definitions are common to the Radio Control layers as
+ * exported by the WUSB1.0 HWA and WHCI interfaces.
+ */
+
+/** Radio Control Command Block (WUSB1.0[Table 8-65] and WHCI 0.95) */
+struct uwb_rccb {
+	u8 bCommandType;		/* enum hwa_cet */
+	__le16 wCommand;		/* Command code */
+	u8 bCommandContext;		/* Context ID */
+} __attribute__((packed));
+
+
+/** Radio Control Event Block (WUSB[table 8-66], WHCI 0.95) */
+struct uwb_rceb {
+	u8 bEventType;			/* enum hwa_cet */
+	__le16 wEvent;			/* Event code */
+	u8 bEventContext;		/* Context ID */
+} __attribute__((packed));
+
+
+enum {
+	UWB_RC_CET_GENERAL = 0,		/* General Command/Event type */
+	UWB_RC_CET_EX_TYPE_1 = 1,	/* Extended Type 1 Command/Event type */
+};
+
+/* Commands to the radio controller */
+enum uwb_rc_cmd {
+	UWB_RC_CMD_CHANNEL_CHANGE = 16,
+	UWB_RC_CMD_DEV_ADDR_MGMT = 17,	/* Device Address Management */
+	UWB_RC_CMD_GET_IE = 18,		/* GET Information Elements */
+	UWB_RC_CMD_RESET = 19,
+	UWB_RC_CMD_SCAN = 20,		/* Scan management  */
+	UWB_RC_CMD_SET_BEACON_FILTER = 21,
+	UWB_RC_CMD_SET_DRP_IE = 22,	/* Dynamic Reservation Protocol IEs */
+	UWB_RC_CMD_SET_IE = 23,		/* Information Element management */
+	UWB_RC_CMD_SET_NOTIFICATION_FILTER = 24,
+	UWB_RC_CMD_SET_TX_POWER = 25,
+	UWB_RC_CMD_SLEEP = 26,
+	UWB_RC_CMD_START_BEACON = 27,
+	UWB_RC_CMD_STOP_BEACON = 28,
+	UWB_RC_CMD_BP_MERGE = 29,
+	UWB_RC_CMD_SEND_COMMAND_FRAME = 30,
+	UWB_RC_CMD_SET_ASIE_NOTIF = 31,
+};
+
+/* Notifications from the radio controller */
+enum uwb_rc_evt {
+	UWB_RC_EVT_IE_RCV = 0,
+	UWB_RC_EVT_BEACON = 1,
+	UWB_RC_EVT_BEACON_SIZE = 2,
+	UWB_RC_EVT_BPOIE_CHANGE = 3,
+	UWB_RC_EVT_BP_SLOT_CHANGE = 4,
+	UWB_RC_EVT_BP_SWITCH_IE_RCV = 5,
+	UWB_RC_EVT_DEV_ADDR_CONFLICT = 6,
+	UWB_RC_EVT_DRP_AVAIL = 7,
+	UWB_RC_EVT_DRP = 8,
+	UWB_RC_EVT_BP_SWITCH_STATUS = 9,
+	UWB_RC_EVT_CMD_FRAME_RCV = 10,
+	UWB_RC_EVT_CHANNEL_CHANGE_IE_RCV = 11,
+	/* Events (command responses) use the same code as the command */
+	UWB_RC_EVT_UNKNOWN_CMD_RCV = 65535,
+};
+
+enum uwb_rc_extended_type_1_cmd {
+	UWB_RC_SET_DAA_ENERGY_MASK = 32,
+	UWB_RC_SET_NOTIFICATION_FILTER_EX = 33,
+};
+
+enum uwb_rc_extended_type_1_evt {
+	UWB_RC_DAA_ENERGY_DETECTED = 0,
+};
+
+/* Radio Control Result Code. [WHCI] table 3-3. */
+enum {
+	UWB_RC_RES_SUCCESS = 0,
+	UWB_RC_RES_FAIL,
+	UWB_RC_RES_FAIL_HARDWARE,
+	UWB_RC_RES_FAIL_NO_SLOTS,
+	UWB_RC_RES_FAIL_BEACON_TOO_LARGE,
+	UWB_RC_RES_FAIL_INVALID_PARAMETER,
+	UWB_RC_RES_FAIL_UNSUPPORTED_PWR_LEVEL,
+	UWB_RC_RES_FAIL_INVALID_IE_DATA,
+	UWB_RC_RES_FAIL_BEACON_SIZE_EXCEEDED,
+	UWB_RC_RES_FAIL_CANCELLED,
+	UWB_RC_RES_FAIL_INVALID_STATE,
+	UWB_RC_RES_FAIL_INVALID_SIZE,
+	UWB_RC_RES_FAIL_ACK_NOT_RECEIVED,
+	UWB_RC_RES_FAIL_NO_MORE_ASIE_NOTIF,
+	UWB_RC_RES_FAIL_TIME_OUT = 255,
+};
+
+/* Confirm event. [WHCI] section 3.1.3.1 etc. */
+struct uwb_rc_evt_confirm {
+	struct uwb_rceb rceb;
+	u8 bResultCode;
+} __attribute__((packed));
+
+/* Device Address Management event. [WHCI] section 3.1.3.2. */
+struct uwb_rc_evt_dev_addr_mgmt {
+	struct uwb_rceb rceb;
+	u8 baAddr[6];
+	u8 bResultCode;
+} __attribute__((packed));
+
+
+/* Get IE Event. [WHCI] section 3.1.3.3. */
+struct uwb_rc_evt_get_ie {
+	struct uwb_rceb rceb;
+	__le16 wIELength;
+	u8 IEData[];
+} __attribute__((packed));
+
+/* Set DRP IE Event. [WHCI] section 3.1.3.7. */
+struct uwb_rc_evt_set_drp_ie {
+	struct uwb_rceb rceb;
+	__le16 wRemainingSpace;
+	u8 bResultCode;
+} __attribute__((packed));
+
+/* Set IE Event. [WHCI] section 3.1.3.8. */
+struct uwb_rc_evt_set_ie {
+	struct uwb_rceb rceb;
+	__le16 RemainingSpace;
+	u8 bResultCode;
+} __attribute__((packed));
+
+/* Scan command. [WHCI] 3.1.3.5. */
+struct uwb_rc_cmd_scan {
+	struct uwb_rccb rccb;
+	u8 bChannelNumber;
+	u8 bScanState;
+	__le16 wStartTime;
+} __attribute__((packed));
+
+/* Set DRP IE command. [WHCI] section 3.1.3.7. */
+struct uwb_rc_cmd_set_drp_ie {
+	struct uwb_rccb rccb;
+	__le16 wIELength;
+	struct uwb_ie_drp IEData[];
+} __attribute__((packed));
+
+/* Set IE command. [WHCI] section 3.1.3.8. */
+struct uwb_rc_cmd_set_ie {
+	struct uwb_rccb rccb;
+	__le16 wIELength;
+	u8 IEData[];
+} __attribute__((packed));
+
+/* Set DAA Energy Mask event. [WHCI 0.96] section 3.1.3.17. */
+struct uwb_rc_evt_set_daa_energy_mask {
+	struct uwb_rceb rceb;
+	__le16 wLength;
+	u8 result;
+} __attribute__((packed));
+
+/* Set Notification Filter Extended event. [WHCI 0.96] section 3.1.3.18. */
+struct uwb_rc_evt_set_notification_filter_ex {
+	struct uwb_rceb rceb;
+	__le16 wLength;
+	u8 result;
+} __attribute__((packed));
+
+/* IE Received notification. [WHCI] section 3.1.4.1. */
+struct uwb_rc_evt_ie_rcv {
+	struct uwb_rceb rceb;
+	struct uwb_dev_addr SrcAddr;
+	__le16 wIELength;
+	u8 IEData[];
+} __attribute__((packed));
+
+/* Type of the received beacon. [WHCI] section 3.1.4.2. */
+enum uwb_rc_beacon_type {
+	UWB_RC_BEACON_TYPE_SCAN = 0,
+	UWB_RC_BEACON_TYPE_NEIGHBOR,
+	UWB_RC_BEACON_TYPE_OL_ALIEN,
+	UWB_RC_BEACON_TYPE_NOL_ALIEN,
+};
+
+/* Beacon received notification. [WHCI] 3.1.4.2. */
+struct uwb_rc_evt_beacon {
+	struct uwb_rceb rceb;
+	u8	bChannelNumber;
+	u8	bBeaconType;
+	__le16	wBPSTOffset;
+	u8	bLQI;
+	u8	bRSSI;
+	__le16	wBeaconInfoLength;
+	u8	BeaconInfo[];
+} __attribute__((packed));
+
+
+/* Beacon Size Change notification. [WHCI] section 3.1.4.3 */
+struct uwb_rc_evt_beacon_size {
+	struct uwb_rceb rceb;
+	__le16 wNewBeaconSize;
+} __attribute__((packed));
+
+
+/* BPOIE Change notification. [WHCI] section 3.1.4.4. */
+struct uwb_rc_evt_bpoie_change {
+	struct uwb_rceb rceb;
+	__le16 wBPOIELength;
+	u8 BPOIE[];
+} __attribute__((packed));
+
+
+/* Beacon Slot Change notification. [WHCI] section 3.1.4.5. */
+struct uwb_rc_evt_bp_slot_change {
+	struct uwb_rceb rceb;
+	u8 slot_info;
+} __attribute__((packed));
+
+static inline int uwb_rc_evt_bp_slot_change_slot_num(
+	const struct uwb_rc_evt_bp_slot_change *evt)
+{
+	return evt->slot_info & 0x7f;
+}
+
+static inline int uwb_rc_evt_bp_slot_change_no_slot(
+	const struct uwb_rc_evt_bp_slot_change *evt)
+{
+	return (evt->slot_info & 0x80) >> 7;
+}
+
+/* BP Switch IE Received notification. [WHCI] section 3.1.4.6. */
+struct uwb_rc_evt_bp_switch_ie_rcv {
+	struct uwb_rceb rceb;
+	struct uwb_dev_addr wSrcAddr;
+	__le16 wIELength;
+	u8 IEData[];
+} __attribute__((packed));
+
+/* DevAddr Conflict notification. [WHCI] section 3.1.4.7. */
+struct uwb_rc_evt_dev_addr_conflict {
+	struct uwb_rceb rceb;
+} __attribute__((packed));
+
+/* DRP notification. [WHCI] section 3.1.4.9. */
+struct uwb_rc_evt_drp {
+	struct uwb_rceb           rceb;
+	struct uwb_dev_addr       src_addr;
+	u8                        reason;
+	u8                        beacon_slot_number;
+	__le16                    ie_length;
+	u8                        ie_data[];
+} __attribute__((packed));
+
+static inline enum uwb_drp_notif_reason uwb_rc_evt_drp_reason(struct uwb_rc_evt_drp *evt)
+{
+	return evt->reason & 0x0f;
+}
+
+
+/* DRP Availability Change notification. [WHCI] section 3.1.4.8. */
+struct uwb_rc_evt_drp_avail {
+	struct uwb_rceb rceb;
+	DECLARE_BITMAP(bmp, UWB_NUM_MAS);
+} __attribute__((packed));
+
+/* BP switch status notification. [WHCI] section 3.1.4.10. */
+struct uwb_rc_evt_bp_switch_status {
+	struct uwb_rceb rceb;
+	u8 status;
+	u8 slot_offset;
+	__le16 bpst_offset;
+	u8 move_countdown;
+} __attribute__((packed));
+
+/* Command Frame Received notification. [WHCI] section 3.1.4.11. */
+struct uwb_rc_evt_cmd_frame_rcv {
+	struct uwb_rceb rceb;
+	__le16 receive_time;
+	struct uwb_dev_addr wSrcAddr;
+	struct uwb_dev_addr wDstAddr;
+	__le16 control;
+	__le16 reserved;
+	__le16 dataLength;
+	u8 data[];
+} __attribute__((packed));
+
+/* Channel Change IE Received notification. [WHCI] section 3.1.4.12. */
+struct uwb_rc_evt_channel_change_ie_rcv {
+	struct uwb_rceb rceb;
+	struct uwb_dev_addr wSrcAddr;
+	__le16 wIELength;
+	u8 IEData[];
+} __attribute__((packed));
+
+/* DAA Energy Detected notification. [WHCI 0.96] section 3.1.4.14. */
+struct uwb_rc_evt_daa_energy_detected {
+	struct uwb_rceb rceb;
+	__le16 wLength;
+	u8 bandID;
+	u8 reserved;
+	u8 toneBmp[16];
+} __attribute__((packed));
+
+
+/**
+ * Radio Control Interface Class Descriptor
+ *
+ *  WUSB 1.0 [8.6.1.2]
+ */
+struct uwb_rc_control_intf_class_desc {
+	u8 bLength;
+	u8 bDescriptorType;
+	__le16 bcdRCIVersion;
+} __attribute__((packed));
+
+#endif /* #ifndef __LINUX__UWB_SPEC_H__ */
diff --git a/include/linux/uwb/umc.h b/include/linux/uwb/umc.h
new file mode 100644
index 000000000000..36a39e34f8d7
--- /dev/null
+++ b/include/linux/uwb/umc.h
@@ -0,0 +1,194 @@
+/*
+ * UWB Multi-interface Controller support.
+ *
+ * Copyright (C) 2007 Cambridge Silicon Radio Ltd.
+ *
+ * This file is released under the GPLv2
+ *
+ * UMC (UWB Multi-interface Controller) capabilities (e.g., radio
+ * controller, host controller) are presented as devices on the "umc"
+ * bus.
+ *
+ * The radio controller is not strictly a UMC capability but it's
+ * useful to present it as such.
+ *
+ * References:
+ *
+ *   [WHCI] Wireless Host Controller Interface Specification for
+ *          Certified Wireless Universal Serial Bus, revision 0.95.
+ *
+ * How this works is kind of convoluted but simple. The whci.ko driver
+ * loads when WHCI devices are detected. These WHCI devices expose
+ * many devices in the same PCI function (they couldn't have reused
+ * functions, no), so for each PCI function that exposes these many
+ * devices, whci ceates a umc_dev [whci_probe() -> whci_add_cap()]
+ * with umc_device_create() and adds it to the bus with
+ * umc_device_register().
+ *
+ * umc_device_register() calls device_register() which will push the
+ * bus management code to load your UMC driver's somehting_probe()
+ * that you have registered for that capability code.
+ *
+ * Now when the WHCI device is removed, whci_remove() will go over
+ * each umc_dev assigned to each of the PCI function's capabilities
+ * and through whci_del_cap() call umc_device_unregister() each
+ * created umc_dev. Of course, if you are bound to the device, your
+ * driver's something_remove() will be called.
+ */
+
+#ifndef _LINUX_UWB_UMC_H_
+#define _LINUX_UWB_UMC_H_
+
+#include <linux/device.h>
+#include <linux/pci.h>
+
+/*
+ * UMC capability IDs.
+ *
+ * 0x00 is reserved so use it for the radio controller device.
+ *
+ * [WHCI] table 2-8
+ */
+#define UMC_CAP_ID_WHCI_RC      0x00 /* radio controller */
+#define UMC_CAP_ID_WHCI_WUSB_HC 0x01 /* WUSB host controller */
+
+/**
+ * struct umc_dev - UMC capability device
+ *
+ * @version:  version of the specification this capability conforms to.
+ * @cap_id:   capability ID.
+ * @bar:      PCI Bar (64 bit) where the resource lies
+ * @resource: register space resource.
+ * @irq:      interrupt line.
+ */
+struct umc_dev {
+	u16		version;
+	u8		cap_id;
+	u8		bar;
+	struct resource resource;
+	unsigned	irq;
+	struct device	dev;
+};
+
+#define to_umc_dev(d) container_of(d, struct umc_dev, dev)
+
+/**
+ * struct umc_driver - UMC capability driver
+ * @cap_id: supported capability ID.
+ * @match: driver specific capability matching function.
+ * @match_data: driver specific data for match() (e.g., a
+ * table of pci_device_id's if umc_match_pci_id() is used).
+ */
+struct umc_driver {
+	char *name;
+	u8 cap_id;
+	int (*match)(struct umc_driver *, struct umc_dev *);
+	const void *match_data;
+
+	int  (*probe)(struct umc_dev *);
+	void (*remove)(struct umc_dev *);
+	int  (*suspend)(struct umc_dev *, pm_message_t state);
+	int  (*resume)(struct umc_dev *);
+
+	struct device_driver driver;
+};
+
+#define to_umc_driver(d) container_of(d, struct umc_driver, driver)
+
+extern struct bus_type umc_bus_type;
+
+struct umc_dev *umc_device_create(struct device *parent, int n);
+int __must_check umc_device_register(struct umc_dev *umc);
+void umc_device_unregister(struct umc_dev *umc);
+
+int __must_check __umc_driver_register(struct umc_driver *umc_drv,
+				       struct module *mod,
+				       const char *mod_name);
+
+/**
+ * umc_driver_register - register a UMC capabiltity driver.
+ * @umc_drv:  pointer to the driver.
+ */
+static inline int __must_check umc_driver_register(struct umc_driver *umc_drv)
+{
+	return __umc_driver_register(umc_drv, THIS_MODULE, KBUILD_MODNAME);
+}
+void umc_driver_unregister(struct umc_driver *umc_drv);
+
+/*
+ * Utility function you can use to match (umc_driver->match) against a
+ * null-terminated array of 'struct pci_device_id' in
+ * umc_driver->match_data.
+ */
+int umc_match_pci_id(struct umc_driver *umc_drv, struct umc_dev *umc);
+
+/**
+ * umc_parent_pci_dev - return the UMC's parent PCI device or NULL if none
+ * @umc_dev: UMC device whose parent PCI device we are looking for
+ *
+ * DIRTY!!! DON'T RELY ON THIS
+ *
+ * FIXME: This is as dirty as it gets, but we need some way to check
+ * the correct type of umc_dev->parent (so that for example, we can
+ * cast to pci_dev). Casting to pci_dev is necesary because at some
+ * point we need to request resources from the device. Mapping is
+ * easily over come (ioremap and stuff are bus agnostic), but hooking
+ * up to some error handlers (such as pci error handlers) might need
+ * this.
+ *
+ * THIS might (probably will) be removed in the future, so don't count
+ * on it.
+ */
+static inline struct pci_dev *umc_parent_pci_dev(struct umc_dev *umc_dev)
+{
+	struct pci_dev *pci_dev = NULL;
+	if (umc_dev->dev.parent->bus == &pci_bus_type)
+		pci_dev = to_pci_dev(umc_dev->dev.parent);
+	return pci_dev;
+}
+
+/**
+ * umc_dev_get() - reference a UMC device.
+ * @umc_dev: Pointer to UMC device.
+ *
+ * NOTE: we are assuming in this whole scheme that the parent device
+ *       is referenced at _probe() time and unreferenced at _remove()
+ *       time by the parent's subsystem.
+ */
+static inline struct umc_dev *umc_dev_get(struct umc_dev *umc_dev)
+{
+	get_device(&umc_dev->dev);
+	return umc_dev;
+}
+
+/**
+ * umc_dev_put() - unreference a UMC device.
+ * @umc_dev: Pointer to UMC device.
+ */
+static inline void umc_dev_put(struct umc_dev *umc_dev)
+{
+	put_device(&umc_dev->dev);
+}
+
+/**
+ * umc_set_drvdata - set UMC device's driver data.
+ * @umc_dev: Pointer to UMC device.
+ * @data:    Data to set.
+ */
+static inline void umc_set_drvdata(struct umc_dev *umc_dev, void *data)
+{
+	dev_set_drvdata(&umc_dev->dev, data);
+}
+
+/**
+ * umc_get_drvdata - recover UMC device's driver data.
+ * @umc_dev: Pointer to UMC device.
+ */
+static inline void *umc_get_drvdata(struct umc_dev *umc_dev)
+{
+	return dev_get_drvdata(&umc_dev->dev);
+}
+
+int umc_controller_reset(struct umc_dev *umc);
+
+#endif /* #ifndef _LINUX_UWB_UMC_H_ */
diff --git a/include/linux/uwb/whci.h b/include/linux/uwb/whci.h
new file mode 100644
index 000000000000..915ec23042d4
--- /dev/null
+++ b/include/linux/uwb/whci.h
@@ -0,0 +1,117 @@
+/*
+ * Wireless Host Controller Interface for Ultra-Wide-Band and Wireless USB
+ *
+ * Copyright (C) 2005-2006 Intel Corporation
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ *
+ * References:
+ *   [WHCI] Wireless Host Controller Interface Specification for
+ *          Certified Wireless Universal Serial Bus, revision 0.95.
+ */
+#ifndef _LINUX_UWB_WHCI_H_
+#define _LINUX_UWB_WHCI_H_
+
+#include <linux/pci.h>
+
+/*
+ * UWB interface capability registers (offsets from UWBBASE)
+ *
+ * [WHCI] section 2.2
+ */
+#define UWBCAPINFO	0x00 /* == UWBCAPDATA(0) */
+#  define UWBCAPINFO_TO_N_CAPS(c)	(((c) >> 0)  & 0xFull)
+#define UWBCAPDATA(n)	(8*(n))
+#  define UWBCAPDATA_TO_VERSION(c)	(((c) >> 32) & 0xFFFFull)
+#  define UWBCAPDATA_TO_OFFSET(c)	(((c) >> 18) & 0x3FFFull)
+#  define UWBCAPDATA_TO_BAR(c)		(((c) >> 16) & 0x3ull)
+#  define UWBCAPDATA_TO_SIZE(c)		((((c) >> 8) & 0xFFull) * sizeof(u32))
+#  define UWBCAPDATA_TO_CAP_ID(c)	(((c) >> 0)  & 0xFFull)
+
+/* Size of the WHCI capability data (including the RC capability) for
+   a device with n capabilities. */
+#define UWBCAPDATA_SIZE(n) (8 + 8*(n))
+
+
+/*
+ * URC registers (offsets from URCBASE)
+ *
+ * [WHCI] section 2.3
+ */
+#define URCCMD		0x00
+#  define URCCMD_RESET		(1 << 31)  /* UMC Hardware reset */
+#  define URCCMD_RS		(1 << 30)  /* Run/Stop */
+#  define URCCMD_EARV		(1 << 29)  /* Event Address Register Valid */
+#  define URCCMD_ACTIVE		(1 << 15)  /* Command is active */
+#  define URCCMD_IWR		(1 << 14)  /* Interrupt When Ready */
+#  define URCCMD_SIZE_MASK	0x00000fff /* Command size mask */
+#define URCSTS		0x04
+#  define URCSTS_EPS		(1 << 17)  /* Event Processing Status */
+#  define URCSTS_HALTED		(1 << 16)  /* RC halted */
+#  define URCSTS_HSE		(1 << 10)  /* Host System Error...fried */
+#  define URCSTS_ER		(1 <<  9)  /* Event Ready */
+#  define URCSTS_RCI		(1 <<  8)  /* Ready for Command Interrupt */
+#  define URCSTS_INT_MASK	0x00000700 /* URC interrupt sources */
+#  define URCSTS_ISI		0x000000ff /* Interrupt Source Identification */
+#define URCINTR		0x08
+#  define URCINTR_EN_ALL	0x000007ff /* Enable all interrupt sources */
+#define URCCMDADDR	0x10
+#define URCEVTADDR	0x18
+#  define URCEVTADDR_OFFSET_MASK 0xfff    /* Event pointer offset mask */
+
+
+/** Write 32 bit @value to little endian register at @addr */
+static inline
+void le_writel(u32 value, void __iomem *addr)
+{
+	iowrite32(value, addr);
+}
+
+
+/** Read from 32 bit little endian register at @addr */
+static inline
+u32 le_readl(void __iomem *addr)
+{
+	return ioread32(addr);
+}
+
+
+/** Write 64 bit @value to little endian register at @addr */
+static inline
+void le_writeq(u64 value, void __iomem *addr)
+{
+	iowrite32(value, addr);
+	iowrite32(value >> 32, addr + 4);
+}
+
+
+/** Read from 64 bit little endian register at @addr */
+static inline
+u64 le_readq(void __iomem *addr)
+{
+	u64 value;
+	value  = ioread32(addr);
+	value |= (u64)ioread32(addr + 4) << 32;
+	return value;
+}
+
+extern int whci_wait_for(struct device *dev, u32 __iomem *reg,
+			 u32 mask, u32 result,
+			 unsigned long max_ms,  const char *tag);
+
+#endif /* #ifndef _LINUX_UWB_WHCI_H_ */
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index d4b03034ee73..1f126e30766c 100644
--- a/include/linux/videodev2.h
+++ b/include/linux/videodev2.h
@@ -293,6 +293,7 @@ struct v4l2_pix_format {
 #define V4L2_PIX_FMT_YVU420  v4l2_fourcc('Y', 'V', '1', '2') /* 12  YVU 4:2:0     */
 #define V4L2_PIX_FMT_YUYV    v4l2_fourcc('Y', 'U', 'Y', 'V') /* 16  YUV 4:2:2     */
 #define V4L2_PIX_FMT_UYVY    v4l2_fourcc('U', 'Y', 'V', 'Y') /* 16  YUV 4:2:2     */
+#define V4L2_PIX_FMT_VYUY    v4l2_fourcc('V', 'Y', 'U', 'Y') /* 16  YUV 4:2:2     */
 #define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4', '2', '2', 'P') /* 16  YVU422 planar */
 #define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4', '1', '1', 'P') /* 16  YVU411 planar */
 #define V4L2_PIX_FMT_Y41P    v4l2_fourcc('Y', '4', '1', 'P') /* 12  YUV 4:1:1     */
@@ -304,6 +305,8 @@ struct v4l2_pix_format {
 /* two planes -- one Y, one Cr + Cb interleaved  */
 #define V4L2_PIX_FMT_NV12    v4l2_fourcc('N', 'V', '1', '2') /* 12  Y/CbCr 4:2:0  */
 #define V4L2_PIX_FMT_NV21    v4l2_fourcc('N', 'V', '2', '1') /* 12  Y/CrCb 4:2:0  */
+#define V4L2_PIX_FMT_NV16    v4l2_fourcc('N', 'V', '1', '6') /* 16  Y/CbCr 4:2:2  */
+#define V4L2_PIX_FMT_NV61    v4l2_fourcc('N', 'V', '6', '1') /* 16  Y/CrCb 4:2:2  */
 
 /*  The following formats are not defined in the V4L2 specification */
 #define V4L2_PIX_FMT_YUV410  v4l2_fourcc('Y', 'U', 'V', '9') /*  9  YUV 4:1:0     */
@@ -315,6 +318,13 @@ struct v4l2_pix_format {
 /* see http://www.siliconimaging.com/RGB%20Bayer.htm */
 #define V4L2_PIX_FMT_SBGGR8  v4l2_fourcc('B', 'A', '8', '1') /*  8  BGBG.. GRGR.. */
 #define V4L2_PIX_FMT_SGBRG8  v4l2_fourcc('G', 'B', 'R', 'G') /*  8  GBGB.. RGRG.. */
+/*
+ * 10bit raw bayer, expanded to 16 bits
+ * xxxxrrrrrrrrrrxxxxgggggggggg xxxxggggggggggxxxxbbbbbbbbbb...
+ */
+#define V4L2_PIX_FMT_SGRBG10 v4l2_fourcc('B', 'A', '1', '0')
+/* 10bit raw bayer DPCM compressed to 8 bits */
+#define V4L2_PIX_FMT_SGRBG10DPCM8 v4l2_fourcc('B', 'D', '1', '0')
 #define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B', 'Y', 'R', '2') /* 16  BGBG.. GRGR.. */
 
 /* compressed formats */
@@ -1043,7 +1053,7 @@ enum v4l2_mpeg_video_bitrate_mode {
 #define V4L2_CID_MPEG_VIDEO_MUTE 		(V4L2_CID_MPEG_BASE+210)
 #define V4L2_CID_MPEG_VIDEO_MUTE_YUV 		(V4L2_CID_MPEG_BASE+211)
 
-/*  MPEG-class control IDs specific to the CX2584x driver as defined by V4L2 */
+/*  MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */
 #define V4L2_CID_MPEG_CX2341X_BASE 				(V4L2_CTRL_CLASS_MPEG | 0x1000)
 #define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE 	(V4L2_CID_MPEG_CX2341X_BASE+0)
 enum v4l2_mpeg_cx2341x_video_spatial_filter_mode {
@@ -1110,6 +1120,12 @@ enum  v4l2_exposure_auto_type {
 #define V4L2_CID_FOCUS_RELATIVE			(V4L2_CID_CAMERA_CLASS_BASE+11)
 #define V4L2_CID_FOCUS_AUTO			(V4L2_CID_CAMERA_CLASS_BASE+12)
 
+#define V4L2_CID_ZOOM_ABSOLUTE			(V4L2_CID_CAMERA_CLASS_BASE+13)
+#define V4L2_CID_ZOOM_RELATIVE			(V4L2_CID_CAMERA_CLASS_BASE+14)
+#define V4L2_CID_ZOOM_CONTINUOUS		(V4L2_CID_CAMERA_CLASS_BASE+15)
+
+#define V4L2_CID_PRIVACY			(V4L2_CID_CAMERA_CLASS_BASE+16)
+
 /*
  *	T U N I N G
  */
@@ -1362,6 +1378,7 @@ struct v4l2_streamparm {
 #define V4L2_CHIP_MATCH_HOST       0  /* Match against chip ID on host (0 for the host) */
 #define V4L2_CHIP_MATCH_I2C_DRIVER 1  /* Match against I2C driver ID */
 #define V4L2_CHIP_MATCH_I2C_ADDR   2  /* Match against I2C 7-bit address */
+#define V4L2_CHIP_MATCH_AC97       3  /* Match against anciliary AC97 chip */
 
 struct v4l2_register {
 	__u32 match_type; /* Match type */
@@ -1451,6 +1468,8 @@ struct v4l2_chip_ident {
 #define VIDIOC_G_CHIP_IDENT     _IOWR('V', 81, struct v4l2_chip_ident)
 #endif
 #define VIDIOC_S_HW_FREQ_SEEK	 _IOW('V', 82, struct v4l2_hw_freq_seek)
+/* Reminder: when adding new ioctls please add support for them to
+   drivers/media/video/v4l2-compat-ioctl32.c as well! */
 
 #ifdef __OLD_VIDIOC_
 /* for compatibility, will go away some day */
diff --git a/include/linux/virtio_balloon.h b/include/linux/virtio_balloon.h
index c30c7bfbf39b..8726ff77763e 100644
--- a/include/linux/virtio_balloon.h
+++ b/include/linux/virtio_balloon.h
@@ -10,6 +10,9 @@
 /* The feature bitmap for virtio balloon */
 #define VIRTIO_BALLOON_F_MUST_TELL_HOST	0 /* Tell before reclaiming pages */
 
+/* Size of a PFN in the balloon interface. */
+#define VIRTIO_BALLOON_PFN_SHIFT 12
+
 struct virtio_balloon_config
 {
 	/* Number of pages host wants Guest to give up. */
diff --git a/include/linux/virtio_console.h b/include/linux/virtio_console.h
index 19a0da0dba41..7615ffcdd555 100644
--- a/include/linux/virtio_console.h
+++ b/include/linux/virtio_console.h
@@ -7,6 +7,17 @@
 /* The ID for virtio console */
 #define VIRTIO_ID_CONSOLE	3
 
+/* Feature bits */
+#define VIRTIO_CONSOLE_F_SIZE	0	/* Does host provide console size? */
+
+struct virtio_console_config {
+	/* colums of the screens */
+	__u16 cols;
+	/* rows of the screens */
+	__u16 rows;
+} __attribute__((packed));
+
+
 #ifdef __KERNEL__
 int __init virtio_cons_early_init(int (*put_chars)(u32, const char *, int));
 #endif /* __KERNEL__ */
diff --git a/include/linux/virtio_net.h b/include/linux/virtio_net.h
index 5e33761b9b8a..5cdd0aa8bde9 100644
--- a/include/linux/virtio_net.h
+++ b/include/linux/virtio_net.h
@@ -20,6 +20,7 @@
 #define VIRTIO_NET_F_HOST_TSO6	12	/* Host can handle TSOv6 in. */
 #define VIRTIO_NET_F_HOST_ECN	13	/* Host can handle TSO[6] w/ ECN in. */
 #define VIRTIO_NET_F_HOST_UFO	14	/* Host can handle UFO in. */
+#define VIRTIO_NET_F_MRG_RXBUF	15	/* Host can merge receive buffers. */
 
 struct virtio_net_config
 {
@@ -44,4 +45,12 @@ struct virtio_net_hdr
 	__u16 csum_start;	/* Position to start checksumming from */
 	__u16 csum_offset;	/* Offset after that to place checksum */
 };
+
+/* This is the version of the header to use when the MRG_RXBUF
+ * feature has been negotiated. */
+struct virtio_net_hdr_mrg_rxbuf {
+	struct virtio_net_hdr hdr;
+	__u16 num_buffers;	/* Number of merged rx buffers */
+};
+
 #endif /* _LINUX_VIRTIO_NET_H */
diff --git a/include/linux/virtio_pci.h b/include/linux/virtio_pci.h
index cdef35742932..cd0fd5d181a6 100644
--- a/include/linux/virtio_pci.h
+++ b/include/linux/virtio_pci.h
@@ -53,4 +53,12 @@
 
 /* Virtio ABI version, this must match exactly */
 #define VIRTIO_PCI_ABI_VERSION		0
+
+/* How many bits to shift physical queue address written to QUEUE_PFN.
+ * 12 is historical, and due to x86 page size. */
+#define VIRTIO_PCI_QUEUE_ADDR_SHIFT	12
+
+/* The alignment to use between consumer and producer parts of vring.
+ * x86 pagesize again. */
+#define VIRTIO_PCI_VRING_ALIGN		4096
 #endif
diff --git a/include/linux/virtio_ring.h b/include/linux/virtio_ring.h
index c4a598fb3826..71e03722fb59 100644
--- a/include/linux/virtio_ring.h
+++ b/include/linux/virtio_ring.h
@@ -83,7 +83,7 @@ struct vring {
  *	__u16 avail_idx;
  *	__u16 available[num];
  *
- *	// Padding to the next page boundary.
+ *	// Padding to the next align boundary.
  *	char pad[];
  *
  *	// A ring of used descriptor heads with free-running index.
@@ -93,19 +93,19 @@ struct vring {
  * };
  */
 static inline void vring_init(struct vring *vr, unsigned int num, void *p,
-			      unsigned long pagesize)
+			      unsigned long align)
 {
 	vr->num = num;
 	vr->desc = p;
 	vr->avail = p + num*sizeof(struct vring_desc);
-	vr->used = (void *)(((unsigned long)&vr->avail->ring[num] + pagesize-1)
-			    & ~(pagesize - 1));
+	vr->used = (void *)(((unsigned long)&vr->avail->ring[num] + align-1)
+			    & ~(align - 1));
 }
 
-static inline unsigned vring_size(unsigned int num, unsigned long pagesize)
+static inline unsigned vring_size(unsigned int num, unsigned long align)
 {
 	return ((sizeof(struct vring_desc) * num + sizeof(__u16) * (2 + num)
-		 + pagesize - 1) & ~(pagesize - 1))
+		 + align - 1) & ~(align - 1))
 		+ sizeof(__u16) * 2 + sizeof(struct vring_used_elem) * num;
 }
 
@@ -115,6 +115,7 @@ struct virtio_device;
 struct virtqueue;
 
 struct virtqueue *vring_new_virtqueue(unsigned int num,
+				      unsigned int vring_align,
 				      struct virtio_device *vdev,
 				      void *pages,
 				      void (*notify)(struct virtqueue *vq),
diff --git a/include/linux/vmalloc.h b/include/linux/vmalloc.h
index 328eb4022727..307b88577eaa 100644
--- a/include/linux/vmalloc.h
+++ b/include/linux/vmalloc.h
@@ -2,6 +2,7 @@
 #define _LINUX_VMALLOC_H
 
 #include <linux/spinlock.h>
+#include <linux/init.h>
 #include <asm/page.h>		/* pgprot_t */
 
 struct vm_area_struct;		/* vma defining user mapping in mm_types.h */
@@ -23,7 +24,6 @@ struct vm_area_struct;		/* vma defining user mapping in mm_types.h */
 #endif
 
 struct vm_struct {
-	/* keep next,addr,size together to speedup lookups */
 	struct vm_struct	*next;
 	void			*addr;
 	unsigned long		size;
@@ -37,6 +37,19 @@ struct vm_struct {
 /*
  *	Highlevel APIs for driver use
  */
+extern void vm_unmap_ram(const void *mem, unsigned int count);
+extern void *vm_map_ram(struct page **pages, unsigned int count,
+				int node, pgprot_t prot);
+extern void vm_unmap_aliases(void);
+
+#ifdef CONFIG_MMU
+extern void __init vmalloc_init(void);
+#else
+static inline void vmalloc_init(void)
+{
+}
+#endif
+
 extern void *vmalloc(unsigned long size);
 extern void *vmalloc_user(unsigned long size);
 extern void *vmalloc_node(unsigned long size, int node);
@@ -90,6 +103,4 @@ extern void free_vm_area(struct vm_struct *area);
 extern rwlock_t vmlist_lock;
 extern struct vm_struct *vmlist;
 
-extern const struct seq_operations vmalloc_op;
-
 #endif /* _LINUX_VMALLOC_H */
diff --git a/include/linux/vmstat.h b/include/linux/vmstat.h
index 58334d439516..524cd1b28ecb 100644
--- a/include/linux/vmstat.h
+++ b/include/linux/vmstat.h
@@ -41,13 +41,19 @@ enum vm_event_item { PGPGIN, PGPGOUT, PSWPIN, PSWPOUT,
 #ifdef CONFIG_HUGETLB_PAGE
 		HTLB_BUDDY_PGALLOC, HTLB_BUDDY_PGALLOC_FAIL,
 #endif
+#ifdef CONFIG_UNEVICTABLE_LRU
+		UNEVICTABLE_PGCULLED,	/* culled to noreclaim list */
+		UNEVICTABLE_PGSCANNED,	/* scanned for reclaimability */
+		UNEVICTABLE_PGRESCUED,	/* rescued from noreclaim list */
+		UNEVICTABLE_PGMLOCKED,
+		UNEVICTABLE_PGMUNLOCKED,
+		UNEVICTABLE_PGCLEARED,	/* on COW, page truncate */
+		UNEVICTABLE_PGSTRANDED,	/* unable to isolate on unlock */
+		UNEVICTABLE_MLOCKFREED,
+#endif
 		NR_VM_EVENT_ITEMS
 };
 
-extern const struct seq_operations fragmentation_op;
-extern const struct seq_operations pagetypeinfo_op;
-extern const struct seq_operations zoneinfo_op;
-extern const struct seq_operations vmstat_op;
 extern int sysctl_stat_interval;
 
 #ifdef CONFIG_VM_EVENT_COUNTERS
@@ -159,6 +165,16 @@ static inline unsigned long zone_page_state(struct zone *zone,
 	return x;
 }
 
+extern unsigned long global_lru_pages(void);
+
+static inline unsigned long zone_lru_pages(struct zone *zone)
+{
+	return (zone_page_state(zone, NR_ACTIVE_ANON)
+		+ zone_page_state(zone, NR_ACTIVE_FILE)
+		+ zone_page_state(zone, NR_INACTIVE_ANON)
+		+ zone_page_state(zone, NR_INACTIVE_FILE));
+}
+
 #ifdef CONFIG_NUMA
 /*
  * Determine the per node value of a stat item. This function
diff --git a/include/linux/wait.h b/include/linux/wait.h
index 0081147a9fe8..ef609f842fac 100644
--- a/include/linux/wait.h
+++ b/include/linux/wait.h
@@ -108,15 +108,6 @@ static inline int waitqueue_active(wait_queue_head_t *q)
 	return !list_empty(&q->task_list);
 }
 
-/*
- * Used to distinguish between sync and async io wait context:
- * sync i/o typically specifies a NULL wait queue entry or a wait
- * queue entry bound to a task (current task) to wake up.
- * aio specifies a wait queue entry with an async notification
- * callback routine, not associated with any task.
- */
-#define is_sync_wait(wait)	(!(wait) || ((wait)->private))
-
 extern void add_wait_queue(wait_queue_head_t *q, wait_queue_t *wait);
 extern void add_wait_queue_exclusive(wait_queue_head_t *q, wait_queue_t *wait);
 extern void remove_wait_queue(wait_queue_head_t *q, wait_queue_t *wait);
diff --git a/include/linux/wlp.h b/include/linux/wlp.h
new file mode 100644
index 000000000000..033545e145c7
--- /dev/null
+++ b/include/linux/wlp.h
@@ -0,0 +1,735 @@
+/*
+ * WiMedia Logical Link Control Protocol (WLP)
+ *
+ * Copyright (C) 2005-2006 Intel Corporation
+ * Reinette Chatre <reinette.chatre@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * FIXME: docs
+ *
+ * - Does not (yet) include support for WLP control frames
+ *   WLP Draft 0.99 [6.5].
+ *
+ *   A visual representation of the data structures.
+ *
+ *                              wssidB      wssidB
+ *                               ^           ^
+ *                               |           |
+ *                              wssidA      wssidA
+ *   wlp interface {             ^           ^
+ *       ...                     |           |
+ *       ...               ...  wssid      wssid ...
+ *       wlp --- ...             |           |
+ *   };          neighbors --> neighbA --> neighbB
+ *               ...
+ *               wss
+ *               ...
+ *               eda cache  --> neighborA --> neighborB --> neighborC ...
+ */
+
+#ifndef __LINUX__WLP_H_
+#define __LINUX__WLP_H_
+
+#include <linux/netdevice.h>
+#include <linux/skbuff.h>
+#include <linux/list.h>
+#include <linux/uwb.h>
+
+/**
+ * WLP Protocol ID
+ * WLP Draft 0.99 [6.2]
+ *
+ * The MUX header for all WLP frames
+ */
+#define WLP_PROTOCOL_ID 0x0100
+
+/**
+ * WLP Version
+ * WLP version placed in the association frames (WLP 0.99 [6.6])
+ */
+#define WLP_VERSION 0x10
+
+/**
+ * Bytes needed to print UUID as string
+ */
+#define WLP_WSS_UUID_STRSIZE 48
+
+/**
+ * Bytes needed to print nonce as string
+ */
+#define WLP_WSS_NONCE_STRSIZE 48
+
+
+/**
+ * Size used for WLP name size
+ *
+ * The WSS name is set to 65 bytes, 1 byte larger than the maximum
+ * allowed by the WLP spec. This is to have a null terminated string
+ * for display to the user. A maximum of 64 bytes will still be used
+ * when placing the WSS name field in association frames.
+ */
+#define WLP_WSS_NAME_SIZE 65
+
+/**
+ * Number of bytes added by WLP to data frame
+ *
+ * A data frame transmitted from a host will be placed in a Standard or
+ * Abbreviated WLP frame. These have an extra 4 bytes of header (struct
+ * wlp_frame_std_abbrv_hdr).
+ * When the stack sends this data frame for transmission it needs to ensure
+ * there is enough headroom for this header.
+ */
+#define WLP_DATA_HLEN 4
+
+/**
+ * State of device regarding WLP Service Set
+ *
+ * WLP_WSS_STATE_NONE: the host does not participate in any WSS
+ * WLP_WSS_STATE_PART_ENROLLED: used as part of the enrollment sequence
+ *                            ("Partial Enroll"). This state is used to
+ *                            indicate the first part of enrollment that is
+ *                            unsecure. If the WSS is unsecure then the
+ *                            state will promptly go to WLP_WSS_STATE_ENROLLED,
+ *                            if the WSS is not secure then the enrollment
+ *                            procedure is a few more steps before we are
+ *                            enrolled.
+ * WLP_WSS_STATE_ENROLLED: the host is enrolled in a WSS
+ * WLP_WSS_STATE_ACTIVE: WSS is activated
+ * WLP_WSS_STATE_CONNECTED: host is connected to neighbor in WSS
+ *
+ */
+enum wlp_wss_state {
+	WLP_WSS_STATE_NONE = 0,
+	WLP_WSS_STATE_PART_ENROLLED,
+	WLP_WSS_STATE_ENROLLED,
+	WLP_WSS_STATE_ACTIVE,
+	WLP_WSS_STATE_CONNECTED,
+};
+
+/**
+ * WSS Secure status
+ * WLP 0.99 Table 6
+ *
+ * Set to one if the WSS is secure, zero if it is not secure
+ */
+enum wlp_wss_sec_status {
+	WLP_WSS_UNSECURE = 0,
+	WLP_WSS_SECURE,
+};
+
+/**
+ * WLP frame type
+ * WLP Draft 0.99 [6.2 Table 1]
+ */
+enum wlp_frame_type {
+	WLP_FRAME_STANDARD = 0,
+	WLP_FRAME_ABBREVIATED,
+	WLP_FRAME_CONTROL,
+	WLP_FRAME_ASSOCIATION,
+};
+
+/**
+ * WLP Association Message Type
+ * WLP Draft 0.99 [6.6.1.2 Table 8]
+ */
+enum wlp_assoc_type {
+	WLP_ASSOC_D1 = 2,
+	WLP_ASSOC_D2 = 3,
+	WLP_ASSOC_M1 = 4,
+	WLP_ASSOC_M2 = 5,
+	WLP_ASSOC_M3 = 7,
+	WLP_ASSOC_M4 = 8,
+	WLP_ASSOC_M5 = 9,
+	WLP_ASSOC_M6 = 10,
+	WLP_ASSOC_M7 = 11,
+	WLP_ASSOC_M8 = 12,
+	WLP_ASSOC_F0 = 14,
+	WLP_ASSOC_E1 = 32,
+	WLP_ASSOC_E2 = 33,
+	WLP_ASSOC_C1 = 34,
+	WLP_ASSOC_C2 = 35,
+	WLP_ASSOC_C3 = 36,
+	WLP_ASSOC_C4 = 37,
+};
+
+/**
+ * WLP Attribute Type
+ * WLP Draft 0.99 [6.6.1 Table 6]
+ */
+enum wlp_attr_type {
+	WLP_ATTR_AUTH		= 0x1005, /* Authenticator */
+	WLP_ATTR_DEV_NAME 	= 0x1011, /* Device Name */
+	WLP_ATTR_DEV_PWD_ID 	= 0x1012, /* Device Password ID */
+	WLP_ATTR_E_HASH1	= 0x1014, /* E-Hash1 */
+	WLP_ATTR_E_HASH2	= 0x1015, /* E-Hash2 */
+	WLP_ATTR_E_SNONCE1	= 0x1016, /* E-SNonce1 */
+	WLP_ATTR_E_SNONCE2	= 0x1017, /* E-SNonce2 */
+	WLP_ATTR_ENCR_SET	= 0x1018, /* Encrypted Settings */
+	WLP_ATTR_ENRL_NONCE	= 0x101A, /* Enrollee Nonce */
+	WLP_ATTR_KEYWRAP_AUTH	= 0x101E, /* Key Wrap Authenticator */
+	WLP_ATTR_MANUF		= 0x1021, /* Manufacturer */
+	WLP_ATTR_MSG_TYPE	= 0x1022, /* Message Type */
+	WLP_ATTR_MODEL_NAME	= 0x1023, /* Model Name */
+	WLP_ATTR_MODEL_NR	= 0x1024, /* Model Number */
+	WLP_ATTR_PUB_KEY	= 0x1032, /* Public Key */
+	WLP_ATTR_REG_NONCE	= 0x1039, /* Registrar Nonce */
+	WLP_ATTR_R_HASH1	= 0x103D, /* R-Hash1 */
+	WLP_ATTR_R_HASH2	= 0x103E, /* R-Hash2 */
+	WLP_ATTR_R_SNONCE1	= 0x103F, /* R-SNonce1 */
+	WLP_ATTR_R_SNONCE2	= 0x1040, /* R-SNonce2 */
+	WLP_ATTR_SERIAL		= 0x1042, /* Serial number */
+	WLP_ATTR_UUID_E		= 0x1047, /* UUID-E */
+	WLP_ATTR_UUID_R		= 0x1048, /* UUID-R */
+	WLP_ATTR_PRI_DEV_TYPE	= 0x1054, /* Primary Device Type */
+	WLP_ATTR_SEC_DEV_TYPE	= 0x1055, /* Secondary Device Type */
+	WLP_ATTR_PORT_DEV	= 0x1056, /* Portable Device */
+	WLP_ATTR_APP_EXT	= 0x1058, /* Application Extension */
+	WLP_ATTR_WLP_VER	= 0x2000, /* WLP Version */
+	WLP_ATTR_WSSID		= 0x2001, /* WSSID */
+	WLP_ATTR_WSS_NAME	= 0x2002, /* WSS Name */
+	WLP_ATTR_WSS_SEC_STAT	= 0x2003, /* WSS Secure Status */
+	WLP_ATTR_WSS_BCAST	= 0x2004, /* WSS Broadcast Address */
+	WLP_ATTR_WSS_M_KEY	= 0x2005, /* WSS Master Key */
+	WLP_ATTR_ACC_ENRL	= 0x2006, /* Accepting Enrollment */
+	WLP_ATTR_WSS_INFO	= 0x2007, /* WSS Information */
+	WLP_ATTR_WSS_SEL_MTHD	= 0x2008, /* WSS Selection Method */
+	WLP_ATTR_ASSC_MTHD_LIST	= 0x2009, /* Association Methods List */
+	WLP_ATTR_SEL_ASSC_MTHD	= 0x200A, /* Selected Association Method */
+	WLP_ATTR_ENRL_HASH_COMM	= 0x200B, /* Enrollee Hash Commitment */
+	WLP_ATTR_WSS_TAG	= 0x200C, /* WSS Tag */
+	WLP_ATTR_WSS_VIRT	= 0x200D, /* WSS Virtual EUI-48 */
+	WLP_ATTR_WLP_ASSC_ERR	= 0x200E, /* WLP Association Error */
+	WLP_ATTR_VNDR_EXT	= 0x200F, /* Vendor Extension */
+};
+
+/**
+ * WLP Category ID of primary/secondary device
+ * WLP Draft 0.99 [6.6.1.8 Table 12]
+ */
+enum wlp_dev_category_id {
+	WLP_DEV_CAT_COMPUTER = 1,
+	WLP_DEV_CAT_INPUT,
+	WLP_DEV_CAT_PRINT_SCAN_FAX_COPIER,
+	WLP_DEV_CAT_CAMERA,
+	WLP_DEV_CAT_STORAGE,
+	WLP_DEV_CAT_INFRASTRUCTURE,
+	WLP_DEV_CAT_DISPLAY,
+	WLP_DEV_CAT_MULTIM,
+	WLP_DEV_CAT_GAMING,
+	WLP_DEV_CAT_TELEPHONE,
+	WLP_DEV_CAT_OTHER = 65535,
+};
+
+/**
+ * WLP WSS selection method
+ * WLP Draft 0.99 [6.6.1.6 Table 10]
+ */
+enum wlp_wss_sel_mthd {
+	WLP_WSS_ENRL_SELECT = 1,	/* Enrollee selects */
+	WLP_WSS_REG_SELECT,		/* Registrar selects */
+};
+
+/**
+ * WLP association error values
+ * WLP Draft 0.99 [6.6.1.5 Table 9]
+ */
+enum wlp_assc_error {
+	WLP_ASSOC_ERROR_NONE,
+	WLP_ASSOC_ERROR_AUTH,		/* Authenticator Failure */
+	WLP_ASSOC_ERROR_ROGUE,		/* Rogue activity suspected */
+	WLP_ASSOC_ERROR_BUSY,		/* Device busy */
+	WLP_ASSOC_ERROR_LOCK,		/* Setup Locked */
+	WLP_ASSOC_ERROR_NOT_READY,	/* Registrar not ready */
+	WLP_ASSOC_ERROR_INV,		/* Invalid WSS selection */
+	WLP_ASSOC_ERROR_MSG_TIME,	/* Message timeout */
+	WLP_ASSOC_ERROR_ENR_TIME,	/* Enrollment session timeout */
+	WLP_ASSOC_ERROR_PW,		/* Device password invalid */
+	WLP_ASSOC_ERROR_VER,		/* Unsupported version */
+	WLP_ASSOC_ERROR_INT,		/* Internal error */
+	WLP_ASSOC_ERROR_UNDEF,		/* Undefined error */
+	WLP_ASSOC_ERROR_NUM,		/* Numeric comparison failure */
+	WLP_ASSOC_ERROR_WAIT,		/* Waiting for user input */
+};
+
+/**
+ * WLP Parameters
+ * WLP 0.99 [7.7]
+ */
+enum wlp_parameters {
+	WLP_PER_MSG_TIMEOUT = 15,	/* Seconds to wait for response to
+					   association message. */
+};
+
+/**
+ * WLP IE
+ *
+ * The WLP IE should be included in beacons by all devices.
+ *
+ * The driver can set only a few of the fields in this information element,
+ * most fields are managed by the device self. When the driver needs to set
+ * a field it will only provide values for the fields of interest, the rest
+ * will be filled with zeroes. The fields of interest are:
+ *
+ * Element ID
+ * Length
+ * Capabilities (only to include WSSID Hash list length)
+ * WSSID Hash List fields
+ *
+ * WLP 0.99 [6.7]
+ *
+ * Only the fields that will be used are detailed in this structure, rest
+ * are not detailed or marked as "notused".
+ */
+struct wlp_ie {
+	struct uwb_ie_hdr hdr;
+	__le16 capabilities;
+	__le16 cycle_param;
+	__le16 acw_anchor_addr;
+	u8 wssid_hash_list[];
+} __attribute__((packed));
+
+static inline int wlp_ie_hash_length(struct wlp_ie *ie)
+{
+	return (le16_to_cpu(ie->capabilities) >> 12) & 0xf;
+}
+
+static inline void wlp_ie_set_hash_length(struct wlp_ie *ie, int hash_length)
+{
+	u16 caps = le16_to_cpu(ie->capabilities);
+	caps = (caps & ~(0xf << 12)) | (hash_length << 12);
+	ie->capabilities = cpu_to_le16(caps);
+}
+
+/**
+ * WLP nonce
+ * WLP Draft 0.99 [6.6.1 Table 6]
+ *
+ * A 128-bit random number often used (E-SNonce1, E-SNonce2, Enrollee
+ * Nonce, Registrar Nonce, R-SNonce1, R-SNonce2). It is passed to HW so
+ * it is packed.
+ */
+struct wlp_nonce {
+	u8 data[16];
+} __attribute__((packed));
+
+/**
+ * WLP UUID
+ * WLP Draft 0.99 [6.6.1 Table 6]
+ *
+ * Universally Unique Identifier (UUID) encoded as an octet string in the
+ * order the octets are shown in string representation in RFC4122. A UUID
+ * is often used (UUID-E, UUID-R, WSSID). It is passed to HW so it is packed.
+ */
+struct wlp_uuid {
+	u8 data[16];
+} __attribute__((packed));
+
+
+/**
+ * Primary and secondary device type attributes
+ * WLP Draft 0.99 [6.6.1.8]
+ */
+struct wlp_dev_type {
+	enum wlp_dev_category_id category:16;
+	u8 OUI[3];
+	u8 OUIsubdiv;
+	__le16 subID;
+} __attribute__((packed));
+
+/**
+ * WLP frame header
+ * WLP Draft 0.99 [6.2]
+ */
+struct wlp_frame_hdr {
+	__le16 mux_hdr;			/* WLP_PROTOCOL_ID */
+	enum wlp_frame_type type:8;
+} __attribute__((packed));
+
+/**
+ * WLP attribute field header
+ * WLP Draft 0.99 [6.6.1]
+ *
+ * Header of each attribute found in an association frame
+ */
+struct wlp_attr_hdr {
+	__le16 type;
+	__le16 length;
+} __attribute__((packed));
+
+/**
+ * Device information commonly used together
+ *
+ * Each of these device information elements has a specified range in which it
+ * should fit (WLP 0.99 [Table 6]). This range provided in the spec does not
+ * include the termination null '\0' character (when used in the
+ * association protocol the attribute fields are accompanied
+ * with a "length" field so the full range from the spec can be used for
+ * the value). We thus allocate an extra byte to be able to store a string
+ * of max length with a terminating '\0'.
+ */
+struct wlp_device_info {
+	char name[33];
+	char model_name[33];
+	char manufacturer[65];
+	char model_nr[33];
+	char serial[33];
+	struct wlp_dev_type prim_dev_type;
+};
+
+/**
+ * Macros for the WLP attributes
+ *
+ * There are quite a few attributes (total is 43). The attribute layout can be
+ * in one of three categories: one value, an array, an enum forced to 8 bits.
+ * These macros help with their definitions.
+ */
+#define wlp_attr(type, name)						\
+struct wlp_attr_##name {						\
+	struct wlp_attr_hdr hdr;					\
+	type name;							\
+} __attribute__((packed));
+
+#define wlp_attr_array(type, name)					\
+struct wlp_attr_##name {						\
+	struct wlp_attr_hdr hdr;					\
+	type name[];							\
+} __attribute__((packed));
+
+/**
+ * WLP association attribute fields
+ * WLP Draft 0.99 [6.6.1 Table 6]
+ *
+ * Attributes appear in same order as the Table in the spec
+ * FIXME Does not define all attributes yet
+ */
+
+/* Device name: Friendly name of sending device */
+wlp_attr_array(u8, dev_name)
+
+/* Enrollee Nonce: Random number generated by enrollee for an enrollment
+ * session */
+wlp_attr(struct wlp_nonce, enonce)
+
+/* Manufacturer name: Name of manufacturer of the sending device */
+wlp_attr_array(u8, manufacturer)
+
+/* WLP Message Type */
+wlp_attr(u8, msg_type)
+
+/* WLP Model name: Model name of sending device */
+wlp_attr_array(u8, model_name)
+
+/* WLP Model number: Model number of sending device */
+wlp_attr_array(u8, model_nr)
+
+/* Registrar Nonce: Random number generated by registrar for an enrollment
+ * session */
+wlp_attr(struct wlp_nonce, rnonce)
+
+/* Serial number of device */
+wlp_attr_array(u8, serial)
+
+/* UUID of enrollee */
+wlp_attr(struct wlp_uuid, uuid_e)
+
+/* UUID of registrar */
+wlp_attr(struct wlp_uuid, uuid_r)
+
+/* WLP Primary device type */
+wlp_attr(struct wlp_dev_type, prim_dev_type)
+
+/* WLP Secondary device type */
+wlp_attr(struct wlp_dev_type, sec_dev_type)
+
+/* WLP protocol version */
+wlp_attr(u8, version)
+
+/* WLP service set identifier */
+wlp_attr(struct wlp_uuid, wssid)
+
+/* WLP WSS name */
+wlp_attr_array(u8, wss_name)
+
+/* WLP WSS Secure Status */
+wlp_attr(u8, wss_sec_status)
+
+/* WSS Broadcast Address */
+wlp_attr(struct uwb_mac_addr, wss_bcast)
+
+/* WLP Accepting Enrollment */
+wlp_attr(u8, accept_enrl)
+
+/**
+ * WSS information attributes
+ * WLP Draft 0.99 [6.6.3 Table 15]
+ */
+struct wlp_wss_info {
+	struct wlp_attr_wssid wssid;
+	struct wlp_attr_wss_name name;
+	struct wlp_attr_accept_enrl accept;
+	struct wlp_attr_wss_sec_status sec_stat;
+	struct wlp_attr_wss_bcast bcast;
+} __attribute__((packed));
+
+/* WLP WSS Information */
+wlp_attr_array(struct wlp_wss_info, wss_info)
+
+/* WLP WSS Selection method */
+wlp_attr(u8, wss_sel_mthd)
+
+/* WLP WSS tag */
+wlp_attr(u8, wss_tag)
+
+/* WSS Virtual Address */
+wlp_attr(struct uwb_mac_addr, wss_virt)
+
+/* WLP association error */
+wlp_attr(u8, wlp_assc_err)
+
+/**
+ * WLP standard and abbreviated frames
+ *
+ * WLP Draft 0.99 [6.3] and [6.4]
+ *
+ * The difference between the WLP standard frame and the WLP
+ * abbreviated frame is that the standard frame includes the src
+ * and dest addresses from the Ethernet header, the abbreviated frame does
+ * not.
+ * The src/dest (as well as the type/length and client data) are already
+ * defined as part of the Ethernet header, we do not do this here.
+ * From this perspective the standard and abbreviated frames appear the
+ * same - they will be treated differently though.
+ *
+ * The size of this header is also captured in WLP_DATA_HLEN to enable
+ * interfaces to prepare their headroom.
+ */
+struct wlp_frame_std_abbrv_hdr {
+	struct wlp_frame_hdr hdr;
+	u8 tag;
+} __attribute__((packed));
+
+/**
+ * WLP association frames
+ *
+ * WLP Draft 0.99 [6.6]
+ */
+struct wlp_frame_assoc {
+	struct wlp_frame_hdr hdr;
+	enum wlp_assoc_type type:8;
+	struct wlp_attr_version version;
+	struct wlp_attr_msg_type msg_type;
+	u8 attr[];
+} __attribute__((packed));
+
+/* Ethernet to dev address mapping */
+struct wlp_eda {
+	spinlock_t lock;
+	struct list_head cache;	/* Eth<->Dev Addr cache */
+};
+
+/**
+ * WSS information temporary storage
+ *
+ * This information is only stored temporarily during discovery. It should
+ * not be stored unless the device is enrolled in the advertised WSS. This
+ * is done mainly because we follow the letter of the spec in this regard.
+ * See WLP 0.99 [7.2.3].
+ * When the device does become enrolled in a WSS the WSS information will
+ * be stored as part of the more comprehensive struct wlp_wss.
+ */
+struct wlp_wss_tmp_info {
+	char name[WLP_WSS_NAME_SIZE];
+	u8 accept_enroll;
+	u8 sec_status;
+	struct uwb_mac_addr bcast;
+};
+
+struct wlp_wssid_e {
+	struct list_head node;
+	struct wlp_uuid wssid;
+	struct wlp_wss_tmp_info *info;
+};
+
+/**
+ * A cache entry of WLP neighborhood
+ *
+ * @node: head of list is wlp->neighbors
+ * @wssid: list of wssids of this neighbor, element is wlp_wssid_e
+ * @info:  temporary storage for information learned during discovery. This
+ *         storage is used together with the wssid_e temporary storage
+ *         during discovery.
+ */
+struct wlp_neighbor_e {
+	struct list_head node;
+	struct wlp_uuid uuid;
+	struct uwb_dev *uwb_dev;
+	struct list_head wssid; /* Elements are wlp_wssid_e */
+	struct wlp_device_info *info;
+};
+
+struct wlp;
+/**
+ * Information for an association session in progress.
+ *
+ * @exp_message: The type of the expected message. Both this message and a
+ *               F0 message (which can be sent in response to any
+ *               association frame) will be accepted as a valid message for
+ *               this session.
+ * @cb:          The function that will be called upon receipt of this
+ *               message.
+ * @cb_priv:     Private data of callback
+ * @data:        Data used in association process (always a sk_buff?)
+ * @neighbor:    Address of neighbor with which association session is in
+ *               progress.
+ */
+struct wlp_session {
+	enum wlp_assoc_type exp_message;
+	void (*cb)(struct wlp *);
+	void *cb_priv;
+	void *data;
+	struct uwb_dev_addr neighbor_addr;
+};
+
+/**
+ * WLP Service Set
+ *
+ * @mutex: used to protect entire WSS structure.
+ *
+ * @name: The WSS name is set to 65 bytes, 1 byte larger than the maximum
+ *        allowed by the WLP spec. This is to have a null terminated string
+ *        for display to the user. A maximum of 64 bytes will still be used
+ *        when placing the WSS name field in association frames.
+ *
+ * @accept_enroll: Accepting enrollment: Set to one if registrar is
+ *                 accepting enrollment in WSS, or zero otherwise.
+ *
+ * Global and local information for each WSS in which we are enrolled.
+ * WLP 0.99 Section 7.2.1 and Section 7.2.2
+ */
+struct wlp_wss {
+	struct mutex mutex;
+	struct kobject kobj;
+	/* Global properties. */
+	struct wlp_uuid wssid;
+	u8 hash;
+	char name[WLP_WSS_NAME_SIZE];
+	struct uwb_mac_addr bcast;
+	u8 secure_status:1;
+	u8 master_key[16];
+	/* Local properties. */
+	u8 tag;
+	struct uwb_mac_addr virtual_addr;
+	/* Extra */
+	u8 accept_enroll:1;
+	enum wlp_wss_state state;
+};
+
+/**
+ * WLP main structure
+ * @mutex: protect changes to WLP structure. We only allow changes to the
+ *         uuid, so currently this mutex only protects this field.
+ */
+struct wlp {
+	struct mutex mutex;
+	struct uwb_rc *rc;		/* UWB radio controller */
+	struct uwb_pal pal;
+	struct wlp_eda eda;
+	struct wlp_uuid uuid;
+	struct wlp_session *session;
+	struct wlp_wss wss;
+	struct mutex nbmutex; /* Neighbor mutex protects neighbors list */
+	struct list_head neighbors; /* Elements are wlp_neighbor_e */
+	struct uwb_notifs_handler uwb_notifs_handler;
+	struct wlp_device_info *dev_info;
+	void (*fill_device_info)(struct wlp *wlp, struct wlp_device_info *info);
+	int (*xmit_frame)(struct wlp *, struct sk_buff *,
+			  struct uwb_dev_addr *);
+	void (*stop_queue)(struct wlp *);
+	void (*start_queue)(struct wlp *);
+};
+
+/* sysfs */
+
+
+struct wlp_wss_attribute {
+	struct attribute attr;
+	ssize_t (*show)(struct wlp_wss *wss, char *buf);
+	ssize_t (*store)(struct wlp_wss *wss, const char *buf, size_t count);
+};
+
+#define WSS_ATTR(_name, _mode, _show, _store) \
+static struct wlp_wss_attribute wss_attr_##_name = __ATTR(_name, _mode,	\
+							  _show, _store)
+
+extern int wlp_setup(struct wlp *, struct uwb_rc *);
+extern void wlp_remove(struct wlp *);
+extern ssize_t wlp_neighborhood_show(struct wlp *, char *);
+extern int wlp_wss_setup(struct net_device *, struct wlp_wss *);
+extern void wlp_wss_remove(struct wlp_wss *);
+extern ssize_t wlp_wss_activate_show(struct wlp_wss *, char *);
+extern ssize_t wlp_wss_activate_store(struct wlp_wss *, const char *, size_t);
+extern ssize_t wlp_eda_show(struct wlp *, char *);
+extern ssize_t wlp_eda_store(struct wlp *, const char *, size_t);
+extern ssize_t wlp_uuid_show(struct wlp *, char *);
+extern ssize_t wlp_uuid_store(struct wlp *, const char *, size_t);
+extern ssize_t wlp_dev_name_show(struct wlp *, char *);
+extern ssize_t wlp_dev_name_store(struct wlp *, const char *, size_t);
+extern ssize_t wlp_dev_manufacturer_show(struct wlp *, char *);
+extern ssize_t wlp_dev_manufacturer_store(struct wlp *, const char *, size_t);
+extern ssize_t wlp_dev_model_name_show(struct wlp *, char *);
+extern ssize_t wlp_dev_model_name_store(struct wlp *, const char *, size_t);
+extern ssize_t wlp_dev_model_nr_show(struct wlp *, char *);
+extern ssize_t wlp_dev_model_nr_store(struct wlp *, const char *, size_t);
+extern ssize_t wlp_dev_serial_show(struct wlp *, char *);
+extern ssize_t wlp_dev_serial_store(struct wlp *, const char *, size_t);
+extern ssize_t wlp_dev_prim_category_show(struct wlp *, char *);
+extern ssize_t wlp_dev_prim_category_store(struct wlp *, const char *,
+					   size_t);
+extern ssize_t wlp_dev_prim_OUI_show(struct wlp *, char *);
+extern ssize_t wlp_dev_prim_OUI_store(struct wlp *, const char *, size_t);
+extern ssize_t wlp_dev_prim_OUI_sub_show(struct wlp *, char *);
+extern ssize_t wlp_dev_prim_OUI_sub_store(struct wlp *, const char *,
+					  size_t);
+extern ssize_t wlp_dev_prim_subcat_show(struct wlp *, char *);
+extern ssize_t wlp_dev_prim_subcat_store(struct wlp *, const char *,
+					 size_t);
+extern int wlp_receive_frame(struct device *, struct wlp *, struct sk_buff *,
+			     struct uwb_dev_addr *);
+extern int wlp_prepare_tx_frame(struct device *, struct wlp *,
+			       struct sk_buff *, struct uwb_dev_addr *);
+void wlp_reset_all(struct wlp *wlp);
+
+/**
+ * Initialize WSS
+ */
+static inline
+void wlp_wss_init(struct wlp_wss *wss)
+{
+	mutex_init(&wss->mutex);
+}
+
+static inline
+void wlp_init(struct wlp *wlp)
+{
+	INIT_LIST_HEAD(&wlp->neighbors);
+	mutex_init(&wlp->mutex);
+	mutex_init(&wlp->nbmutex);
+	wlp_wss_init(&wlp->wss);
+}
+
+
+#endif /* #ifndef __LINUX__WLP_H_ */
diff --git a/include/linux/workqueue.h b/include/linux/workqueue.h
index 5c158c477ac7..b36291130f22 100644
--- a/include/linux/workqueue.h
+++ b/include/linux/workqueue.h
@@ -149,11 +149,11 @@ struct execute_work {
 
 extern struct workqueue_struct *
 __create_workqueue_key(const char *name, int singlethread,
-		       int freezeable, struct lock_class_key *key,
+		       int freezeable, int rt, struct lock_class_key *key,
 		       const char *lock_name);
 
 #ifdef CONFIG_LOCKDEP
-#define __create_workqueue(name, singlethread, freezeable)	\
+#define __create_workqueue(name, singlethread, freezeable, rt)	\
 ({								\
 	static struct lock_class_key __key;			\
 	const char *__lock_name;				\
@@ -164,17 +164,19 @@ __create_workqueue_key(const char *name, int singlethread,
 		__lock_name = #name;				\
 								\
 	__create_workqueue_key((name), (singlethread),		\
-			       (freezeable), &__key,		\
+			       (freezeable), (rt), &__key,	\
 			       __lock_name);			\
 })
 #else
-#define __create_workqueue(name, singlethread, freezeable)	\
-	__create_workqueue_key((name), (singlethread), (freezeable), NULL, NULL)
+#define __create_workqueue(name, singlethread, freezeable, rt)	\
+	__create_workqueue_key((name), (singlethread), (freezeable), (rt), \
+			       NULL, NULL)
 #endif
 
-#define create_workqueue(name) __create_workqueue((name), 0, 0)
-#define create_freezeable_workqueue(name) __create_workqueue((name), 1, 1)
-#define create_singlethread_workqueue(name) __create_workqueue((name), 1, 0)
+#define create_workqueue(name) __create_workqueue((name), 0, 0, 0)
+#define create_rt_workqueue(name) __create_workqueue((name), 0, 0, 1)
+#define create_freezeable_workqueue(name) __create_workqueue((name), 1, 1, 0)
+#define create_singlethread_workqueue(name) __create_workqueue((name), 1, 0, 0)
 
 extern void destroy_workqueue(struct workqueue_struct *wq);
 
@@ -238,4 +240,12 @@ void cancel_rearming_delayed_work(struct delayed_work *work)
 	cancel_delayed_work_sync(work);
 }
 
+#ifndef CONFIG_SMP
+static inline long work_on_cpu(unsigned int cpu, long (*fn)(void *), void *arg)
+{
+	return fn(arg);
+}
+#else
+long work_on_cpu(unsigned int cpu, long (*fn)(void *), void *arg);
+#endif /* CONFIG_SMP */
 #endif
diff --git a/include/linux/writeback.h b/include/linux/writeback.h
index 12b15c561a1f..e585657e9831 100644
--- a/include/linux/writeback.h
+++ b/include/linux/writeback.h
@@ -63,7 +63,15 @@ struct writeback_control {
 	unsigned for_writepages:1;	/* This is a writepages() call */
 	unsigned range_cyclic:1;	/* range_start is cyclic */
 	unsigned more_io:1;		/* more io to be dispatched */
-	unsigned range_cont:1;
+	/*
+	 * write_cache_pages() won't update wbc->nr_to_write and
+	 * mapping->writeback_index if no_nrwrite_index_update
+	 * is set.  write_cache_pages() may write more than we
+	 * requested and we want to make sure nr_to_write and
+	 * writeback_index are updated in a consistent manner
+	 * so we use a single control to update them
+	 */
+	unsigned no_nrwrite_index_update:1;
 };
 
 /*
diff --git a/include/linux/xfrm.h b/include/linux/xfrm.h
index 4bc1e6b86cb2..52f3abd453a1 100644
--- a/include/linux/xfrm.h
+++ b/include/linux/xfrm.h
@@ -199,6 +199,9 @@ enum {
 #define XFRM_MSG_NEWSPDINFO XFRM_MSG_NEWSPDINFO
 	XFRM_MSG_GETSPDINFO,
 #define XFRM_MSG_GETSPDINFO XFRM_MSG_GETSPDINFO
+
+	XFRM_MSG_MAPPING,
+#define XFRM_MSG_MAPPING XFRM_MSG_MAPPING
 	__XFRM_MSG_MAX
 };
 #define XFRM_MSG_MAX (__XFRM_MSG_MAX - 1)
@@ -438,6 +441,15 @@ struct xfrm_user_migrate {
 	__u16				new_family;
 };
 
+struct xfrm_user_mapping {
+	struct xfrm_usersa_id		id;
+	__u32				reqid;
+	xfrm_address_t			old_saddr;
+	xfrm_address_t			new_saddr;
+	__be16				old_sport;
+	__be16				new_sport;
+};
+
 #ifndef __KERNEL__
 /* backwards compatibility for userspace */
 #define XFRMGRP_ACQUIRE		1
@@ -464,6 +476,8 @@ enum xfrm_nlgroups {
 #define XFRMNLGRP_REPORT	XFRMNLGRP_REPORT
 	XFRMNLGRP_MIGRATE,
 #define XFRMNLGRP_MIGRATE	XFRMNLGRP_MIGRATE
+	XFRMNLGRP_MAPPING,
+#define XFRMNLGRP_MAPPING	XFRMNLGRP_MAPPING
 	__XFRMNLGRP_MAX
 };
 #define XFRMNLGRP_MAX	(__XFRMNLGRP_MAX - 1)
diff --git a/include/math-emu/op-2.h b/include/math-emu/op-2.h
index e193fb08fd55..4f26ecc1411b 100644
--- a/include/math-emu/op-2.h
+++ b/include/math-emu/op-2.h
@@ -25,7 +25,7 @@
 #ifndef __MATH_EMU_OP_2_H__
 #define __MATH_EMU_OP_2_H__
 
-#define _FP_FRAC_DECL_2(X)	_FP_W_TYPE X##_f0, X##_f1
+#define _FP_FRAC_DECL_2(X)	_FP_W_TYPE X##_f0 = 0, X##_f1 = 0
 #define _FP_FRAC_COPY_2(D,S)	(D##_f0 = S##_f0, D##_f1 = S##_f1)
 #define _FP_FRAC_SET_2(X,I)	__FP_FRAC_SET_2(X, I)
 #define _FP_FRAC_HIGH_2(X)	(X##_f1)
diff --git a/include/math-emu/op-common.h b/include/math-emu/op-common.h
index bb46e7645d53..f456534dcaf9 100644
--- a/include/math-emu/op-common.h
+++ b/include/math-emu/op-common.h
@@ -73,7 +73,7 @@ do {									\
 	X##_c = FP_CLS_NAN;						\
 	/* Check for signaling NaN */					\
 	if (!(_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs))		\
-	  FP_SET_EXCEPTION(FP_EX_INVALID);				\
+	  FP_SET_EXCEPTION(FP_EX_INVALID | FP_EX_INVALID_SNAN);		\
       }									\
     break;								\
   }									\
@@ -139,18 +139,27 @@ do {								\
 	if (X##_e <= _FP_WFRACBITS_##fs)			\
 	  {							\
 	    _FP_FRAC_SRS_##wc(X, X##_e, _FP_WFRACBITS_##fs);	\
-	    _FP_ROUND(wc, X);					\
 	    if (_FP_FRAC_HIGH_##fs(X)				\
 		& (_FP_OVERFLOW_##fs >> 1))			\
 	      {							\
 	        X##_e = 1;					\
 	        _FP_FRAC_SET_##wc(X, _FP_ZEROFRAC_##wc);	\
-	        FP_SET_EXCEPTION(FP_EX_INEXACT);		\
 	      }							\
 	    else						\
 	      {							\
-		X##_e = 0;					\
-		_FP_FRAC_SRL_##wc(X, _FP_WORKBITS);		\
+		_FP_ROUND(wc, X);				\
+		if (_FP_FRAC_HIGH_##fs(X)			\
+		   & (_FP_OVERFLOW_##fs >> 1))			\
+		  {						\
+		    X##_e = 1;					\
+		    _FP_FRAC_SET_##wc(X, _FP_ZEROFRAC_##wc);	\
+		    FP_SET_EXCEPTION(FP_EX_INEXACT);		\
+		  }						\
+		else						\
+		  {						\
+		    X##_e = 0;					\
+		    _FP_FRAC_SRL_##wc(X, _FP_WORKBITS);		\
+		  }						\
 	      }							\
 	    if ((FP_CUR_EXCEPTIONS & FP_EX_INEXACT) ||		\
 		(FP_TRAPPING_EXCEPTIONS & FP_EX_UNDERFLOW))	\
@@ -324,7 +333,7 @@ do {									     \
 	_FP_FRAC_SET_##wc(R, _FP_NANFRAC_##fs);				     \
 	R##_s = _FP_NANSIGN_##fs;					     \
 	R##_c = FP_CLS_NAN;						     \
-	FP_SET_EXCEPTION(FP_EX_INVALID);				     \
+	FP_SET_EXCEPTION(FP_EX_INVALID | FP_EX_INVALID_ISI);		     \
 	break;								     \
       }									     \
     /* FALLTHRU */							     \
@@ -431,7 +440,7 @@ do {							\
     R##_s = _FP_NANSIGN_##fs;				\
     R##_c = FP_CLS_NAN;					\
     _FP_FRAC_SET_##wc(R, _FP_NANFRAC_##fs);		\
-    FP_SET_EXCEPTION(FP_EX_INVALID);			\
+    FP_SET_EXCEPTION(FP_EX_INVALID | FP_EX_INVALID_IMZ);\
     break;						\
 							\
   default:						\
@@ -490,11 +499,17 @@ do {							\
     break;						\
 							\
   case _FP_CLS_COMBINE(FP_CLS_INF,FP_CLS_INF):		\
+    R##_s = _FP_NANSIGN_##fs;				\
+    R##_c = FP_CLS_NAN;					\
+    _FP_FRAC_SET_##wc(R, _FP_NANFRAC_##fs);		\
+    FP_SET_EXCEPTION(FP_EX_INVALID | FP_EX_INVALID_IDI);\
+    break;						\
+							\
   case _FP_CLS_COMBINE(FP_CLS_ZERO,FP_CLS_ZERO):	\
     R##_s = _FP_NANSIGN_##fs;				\
     R##_c = FP_CLS_NAN;					\
     _FP_FRAC_SET_##wc(R, _FP_NANFRAC_##fs);		\
-    FP_SET_EXCEPTION(FP_EX_INVALID);			\
+    FP_SET_EXCEPTION(FP_EX_INVALID | FP_EX_INVALID_ZDZ);\
     break;						\
 							\
   default:						\
diff --git a/include/math-emu/soft-fp.h b/include/math-emu/soft-fp.h
index a6f873b45f98..3f284bc03180 100644
--- a/include/math-emu/soft-fp.h
+++ b/include/math-emu/soft-fp.h
@@ -51,6 +51,25 @@
 #ifndef FP_EX_INVALID
 #define FP_EX_INVALID		0
 #endif
+#ifndef FP_EX_INVALID_SNAN
+#define FP_EX_INVALID_SNAN	0
+#endif
+/* inf - inf */
+#ifndef FP_EX_INVALID_ISI
+#define FP_EX_INVALID_ISI	0
+#endif
+/* inf / inf */
+#ifndef FP_EX_INVALID_IDI
+#define FP_EX_INVALID_IDI	0
+#endif
+/* 0 / 0 */
+#ifndef FP_EX_INVALID_ZDZ
+#define FP_EX_INVALID_ZDZ	0
+#endif
+/* inf * 0 */
+#ifndef FP_EX_INVALID_IMZ
+#define FP_EX_INVALID_IMZ	0
+#endif
 #ifndef FP_EX_OVERFLOW
 #define FP_EX_OVERFLOW		0
 #endif
diff --git a/include/media/i2c-addr.h b/include/media/i2c-addr.h
index e7ff44a35ca0..5d0f56054d26 100644
--- a/include/media/i2c-addr.h
+++ b/include/media/i2c-addr.h
@@ -12,8 +12,6 @@
 /* bttv address list */
 #define I2C_ADDR_TSA5522	0xc2
 #define I2C_ADDR_TDA7432	0x8a
-#define I2C_ADDR_BT832_ALT1	0x88
-#define I2C_ADDR_BT832_ALT2	0x8a // alternate setting
 #define I2C_ADDR_TDA8425	0x82
 #define I2C_ADDR_TDA9840	0x84
 #define I2C_ADDR_TDA9850	0xb6 /* also used by 9855,9873 */
diff --git a/include/media/ir-common.h b/include/media/ir-common.h
index 38f2d93c3957..5bf2ea00678c 100644
--- a/include/media/ir-common.h
+++ b/include/media/ir-common.h
@@ -157,6 +157,8 @@ extern IR_KEYTAB_TYPE ir_codes_avermedia_a16d[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_encore_enltv_fm53[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_real_audio_220_32_keys[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_msi_tvanywhere_plus[IR_KEYTAB_SIZE];
+extern IR_KEYTAB_TYPE ir_codes_ati_tv_wonder_hd_600[IR_KEYTAB_SIZE];
+extern IR_KEYTAB_TYPE ir_codes_kworld_plus_tv_analog[IR_KEYTAB_SIZE];
 #endif
 
 /*
diff --git a/include/media/ov772x.h b/include/media/ov772x.h
new file mode 100644
index 000000000000..e391d55edb95
--- /dev/null
+++ b/include/media/ov772x.h
@@ -0,0 +1,21 @@
+/* ov772x Camera
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __OV772X_H__
+#define __OV772X_H__
+
+#include <media/soc_camera.h>
+
+struct ov772x_camera_info {
+	unsigned long          buswidth;
+	struct soc_camera_link link;
+};
+
+#endif /* __OV772X_H__ */
diff --git a/include/media/saa7146.h b/include/media/saa7146.h
index 64a2ec746a3e..c5a6e22a4b37 100644
--- a/include/media/saa7146.h
+++ b/include/media/saa7146.h
@@ -24,7 +24,7 @@
 
 extern unsigned int saa7146_debug;
 
-//#define DEBUG_PROLOG printk("(0x%08x)(0x%08x) %s: %s(): ",(dev==0?-1:(dev->mem==0?-1:saa7146_read(dev,RPS_ADDR0))),(dev==0?-1:(dev->mem==0?-1:saa7146_read(dev,IER))),KBUILD_MODNAME,__FUNCTION__)
+//#define DEBUG_PROLOG printk("(0x%08x)(0x%08x) %s: %s(): ",(dev==0?-1:(dev->mem==0?-1:saa7146_read(dev,RPS_ADDR0))),(dev==0?-1:(dev->mem==0?-1:saa7146_read(dev,IER))),KBUILD_MODNAME,__func__)
 
 #ifndef DEBUG_VARIABLE
 	#define DEBUG_VARIABLE saa7146_debug
diff --git a/include/media/saa7146_vv.h b/include/media/saa7146_vv.h
index 1d104096619c..6bbb0d93bb5f 100644
--- a/include/media/saa7146_vv.h
+++ b/include/media/saa7146_vv.h
@@ -216,8 +216,7 @@ void saa7146_set_gpio(struct saa7146_dev *saa, u8 pin, u8 data);
 extern struct saa7146_use_ops saa7146_video_uops;
 int saa7146_start_preview(struct saa7146_fh *fh);
 int saa7146_stop_preview(struct saa7146_fh *fh);
-int saa7146_video_do_ioctl(struct inode *inode, struct file *file,
-			   unsigned int cmd, void *arg);
+int saa7146_video_do_ioctl(struct file *file, unsigned int cmd, void *arg);
 
 /* from saa7146_vbi.c */
 extern struct saa7146_use_ops saa7146_vbi_uops;
diff --git a/include/media/soc_camera.h b/include/media/soc_camera.h
index c5de7bb19fda..425b6a98c95c 100644
--- a/include/media/soc_camera.h
+++ b/include/media/soc_camera.h
@@ -12,9 +12,10 @@
 #ifndef SOC_CAMERA_H
 #define SOC_CAMERA_H
 
+#include <linux/mutex.h>
+#include <linux/pm.h>
 #include <linux/videodev2.h>
 #include <media/videobuf-core.h>
-#include <linux/pm.h>
 
 struct soc_camera_device {
 	struct list_head list;
@@ -36,14 +37,19 @@ struct soc_camera_device {
 	unsigned char iface;		/* Host number */
 	unsigned char devnum;		/* Device number per host */
 	unsigned char buswidth;		/* See comment in .c */
+	struct soc_camera_sense *sense;	/* See comment in struct definition */
 	struct soc_camera_ops *ops;
 	struct video_device *vdev;
 	const struct soc_camera_data_format *current_fmt;
 	const struct soc_camera_data_format *formats;
 	int num_formats;
+	struct soc_camera_format_xlate *user_formats;
+	int num_user_formats;
 	struct module *owner;
-	/* soc_camera.c private count. Only accessed with video_lock held */
+	void *host_priv;		/* Per-device host private data */
+	/* soc_camera.c private count. Only accessed with .video_lock held */
 	int use_count;
+	struct mutex video_lock;	/* Protects device data */
 };
 
 struct soc_camera_file {
@@ -56,7 +62,7 @@ struct soc_camera_host {
 	struct device dev;
 	unsigned char nr;				/* Host number */
 	void *priv;
-	char *drv_name;
+	const char *drv_name;
 	struct soc_camera_host_ops *ops;
 };
 
@@ -64,25 +70,33 @@ struct soc_camera_host_ops {
 	struct module *owner;
 	int (*add)(struct soc_camera_device *);
 	void (*remove)(struct soc_camera_device *);
-	int (*suspend)(struct soc_camera_device *, pm_message_t state);
+	int (*suspend)(struct soc_camera_device *, pm_message_t);
 	int (*resume)(struct soc_camera_device *);
-	int (*set_fmt_cap)(struct soc_camera_device *, __u32,
-			   struct v4l2_rect *);
-	int (*try_fmt_cap)(struct soc_camera_device *, struct v4l2_format *);
+	int (*get_formats)(struct soc_camera_device *, int,
+			   struct soc_camera_format_xlate *);
+	int (*set_fmt)(struct soc_camera_device *, __u32, struct v4l2_rect *);
+	int (*try_fmt)(struct soc_camera_device *, struct v4l2_format *);
 	void (*init_videobuf)(struct videobuf_queue *,
 			      struct soc_camera_device *);
 	int (*reqbufs)(struct soc_camera_file *, struct v4l2_requestbuffers *);
 	int (*querycap)(struct soc_camera_host *, struct v4l2_capability *);
-	int (*try_bus_param)(struct soc_camera_device *, __u32);
 	int (*set_bus_param)(struct soc_camera_device *, __u32);
 	unsigned int (*poll)(struct file *, poll_table *);
 };
 
+#define SOCAM_SENSOR_INVERT_PCLK	(1 << 0)
+#define SOCAM_SENSOR_INVERT_MCLK	(1 << 1)
+#define SOCAM_SENSOR_INVERT_HSYNC	(1 << 2)
+#define SOCAM_SENSOR_INVERT_VSYNC	(1 << 3)
+#define SOCAM_SENSOR_INVERT_DATA	(1 << 4)
+
 struct soc_camera_link {
 	/* Camera bus id, used to match a camera and a bus */
 	int bus_id;
 	/* GPIO number to switch between 8 and 10 bit modes */
 	unsigned int gpio;
+	/* Per camera SOCAM_SENSOR_* bus flags */
+	unsigned long flags;
 	/* Optional callbacks to power on or off and reset the sensor */
 	int (*power)(struct device *, int);
 	int (*reset)(struct device *);
@@ -106,13 +120,35 @@ extern void soc_camera_device_unregister(struct soc_camera_device *icd);
 extern int soc_camera_video_start(struct soc_camera_device *icd);
 extern void soc_camera_video_stop(struct soc_camera_device *icd);
 
+extern const struct soc_camera_data_format *soc_camera_format_by_fourcc(
+	struct soc_camera_device *icd, unsigned int fourcc);
+extern const struct soc_camera_format_xlate *soc_camera_xlate_by_fourcc(
+	struct soc_camera_device *icd, unsigned int fourcc);
+
 struct soc_camera_data_format {
-	char *name;
+	const char *name;
 	unsigned int depth;
 	__u32 fourcc;
 	enum v4l2_colorspace colorspace;
 };
 
+/**
+ * struct soc_camera_format_xlate - match between host and sensor formats
+ * @cam_fmt: sensor format provided by the sensor
+ * @host_fmt: host format after host translation from cam_fmt
+ * @buswidth: bus width for this format
+ *
+ * Host and sensor translation structure. Used in table of host and sensor
+ * formats matchings in soc_camera_device. A host can override the generic list
+ * generation by implementing get_formats(), and use it for format checks and
+ * format setup.
+ */
+struct soc_camera_format_xlate {
+	const struct soc_camera_data_format *cam_fmt;
+	const struct soc_camera_data_format *host_fmt;
+	unsigned char buswidth;
+};
+
 struct soc_camera_ops {
 	struct module *owner;
 	int (*probe)(struct soc_camera_device *);
@@ -123,13 +159,14 @@ struct soc_camera_ops {
 	int (*release)(struct soc_camera_device *);
 	int (*start_capture)(struct soc_camera_device *);
 	int (*stop_capture)(struct soc_camera_device *);
-	int (*set_fmt_cap)(struct soc_camera_device *, __u32,
-			   struct v4l2_rect *);
-	int (*try_fmt_cap)(struct soc_camera_device *, struct v4l2_format *);
+	int (*set_fmt)(struct soc_camera_device *, __u32, struct v4l2_rect *);
+	int (*try_fmt)(struct soc_camera_device *, struct v4l2_format *);
 	unsigned long (*query_bus_param)(struct soc_camera_device *);
 	int (*set_bus_param)(struct soc_camera_device *, unsigned long);
 	int (*get_chip_id)(struct soc_camera_device *,
 			   struct v4l2_chip_ident *);
+	int (*set_std)(struct soc_camera_device *, v4l2_std_id *);
+	int (*enum_input)(struct soc_camera_device *, struct v4l2_input *);
 #ifdef CONFIG_VIDEO_ADV_DEBUG
 	int (*get_register)(struct soc_camera_device *, struct v4l2_register *);
 	int (*set_register)(struct soc_camera_device *, struct v4l2_register *);
@@ -140,6 +177,32 @@ struct soc_camera_ops {
 	int num_controls;
 };
 
+#define SOCAM_SENSE_PCLK_CHANGED	(1 << 0)
+
+/**
+ * This struct can be attached to struct soc_camera_device by the host driver
+ * to request sense from the camera, for example, when calling .set_fmt(). The
+ * host then can check which flags are set and verify respective values if any.
+ * For example, if SOCAM_SENSE_PCLK_CHANGED is set, it means, pixclock has
+ * changed during this operation. After completion the host should detach sense.
+ *
+ * @flags		ored SOCAM_SENSE_* flags
+ * @master_clock	if the host wants to be informed about pixel-clock
+ *			change, it better set master_clock.
+ * @pixel_clock_max	maximum pixel clock frequency supported by the host,
+ *			camera is not allowed to exceed this.
+ * @pixel_clock		if the camera driver changed pixel clock during this
+ *			operation, it sets SOCAM_SENSE_PCLK_CHANGED, uses
+ *			master_clock to calculate the new pixel-clock and
+ *			sets this field.
+ */
+struct soc_camera_sense {
+	unsigned long flags;
+	unsigned long master_clock;
+	unsigned long pixel_clock_max;
+	unsigned long pixel_clock;
+};
+
 static inline struct v4l2_queryctrl const *soc_camera_find_qctrl(
 	struct soc_camera_ops *ops, int id)
 {
@@ -158,15 +221,20 @@ static inline struct v4l2_queryctrl const *soc_camera_find_qctrl(
 #define SOCAM_HSYNC_ACTIVE_LOW		(1 << 3)
 #define SOCAM_VSYNC_ACTIVE_HIGH		(1 << 4)
 #define SOCAM_VSYNC_ACTIVE_LOW		(1 << 5)
-#define SOCAM_DATAWIDTH_8		(1 << 6)
-#define SOCAM_DATAWIDTH_9		(1 << 7)
-#define SOCAM_DATAWIDTH_10		(1 << 8)
-#define SOCAM_DATAWIDTH_16		(1 << 9)
-#define SOCAM_PCLK_SAMPLE_RISING	(1 << 10)
-#define SOCAM_PCLK_SAMPLE_FALLING	(1 << 11)
+#define SOCAM_DATAWIDTH_4		(1 << 6)
+#define SOCAM_DATAWIDTH_8		(1 << 7)
+#define SOCAM_DATAWIDTH_9		(1 << 8)
+#define SOCAM_DATAWIDTH_10		(1 << 9)
+#define SOCAM_DATAWIDTH_15		(1 << 10)
+#define SOCAM_DATAWIDTH_16		(1 << 11)
+#define SOCAM_PCLK_SAMPLE_RISING	(1 << 12)
+#define SOCAM_PCLK_SAMPLE_FALLING	(1 << 13)
+#define SOCAM_DATA_ACTIVE_HIGH		(1 << 14)
+#define SOCAM_DATA_ACTIVE_LOW		(1 << 15)
 
-#define SOCAM_DATAWIDTH_MASK (SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_9 | \
-			      SOCAM_DATAWIDTH_10 | SOCAM_DATAWIDTH_16)
+#define SOCAM_DATAWIDTH_MASK (SOCAM_DATAWIDTH_4 | SOCAM_DATAWIDTH_8 | \
+			      SOCAM_DATAWIDTH_9 | SOCAM_DATAWIDTH_10 | \
+			      SOCAM_DATAWIDTH_15 | SOCAM_DATAWIDTH_16)
 
 static inline unsigned long soc_camera_bus_param_compatible(
 			unsigned long camera_flags, unsigned long bus_flags)
@@ -182,4 +250,7 @@ static inline unsigned long soc_camera_bus_param_compatible(
 	return (!hsync || !vsync || !pclk) ? 0 : common_flags;
 }
 
+extern unsigned long soc_camera_apply_sensor_flags(struct soc_camera_link *icl,
+						   unsigned long flags);
+
 #endif
diff --git a/include/media/soc_camera_platform.h b/include/media/soc_camera_platform.h
index 851f18220984..1d092b4678aa 100644
--- a/include/media/soc_camera_platform.h
+++ b/include/media/soc_camera_platform.h
@@ -1,3 +1,13 @@
+/*
+ * Generic Platform Camera Driver Header
+ *
+ * Copyright (C) 2008 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
 #ifndef __SOC_CAMERA_H__
 #define __SOC_CAMERA_H__
 
@@ -9,6 +19,7 @@ struct soc_camera_platform_info {
 	unsigned long format_depth;
 	struct v4l2_pix_format format;
 	unsigned long bus_param;
+	void (*power)(int);
 	int (*set_capture)(struct soc_camera_platform_info *info, int enable);
 };
 
diff --git a/include/media/tuner.h b/include/media/tuner.h
index 67c1f514d0e2..7d4e2db78076 100644
--- a/include/media/tuner.h
+++ b/include/media/tuner.h
@@ -123,6 +123,7 @@
 #define TUNER_TEA5761			75	/* Only FM Radio Tuner */
 #define TUNER_XC5000			76	/* Xceive Silicon Tuner */
 #define TUNER_TCL_MF02GIP_5N		77	/* TCL MF02GIP_5N */
+#define TUNER_PHILIPS_FMD1216MEX_MK3	78
 
 /* tv card specific */
 #define TDA9887_PRESENT 		(1<<0)
diff --git a/include/media/tvp514x.h b/include/media/tvp514x.h
new file mode 100644
index 000000000000..5e7ee968c6dc
--- /dev/null
+++ b/include/media/tvp514x.h
@@ -0,0 +1,118 @@
+/*
+ * drivers/media/video/tvp514x.h
+ *
+ * Copyright (C) 2008 Texas Instruments Inc
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Contributors:
+ *     Sivaraj R <sivaraj@ti.com>
+ *     Brijesh R Jadav <brijesh.j@ti.com>
+ *     Hardik Shah <hardik.shah@ti.com>
+ *     Manjunath Hadli <mrh@ti.com>
+ *     Karicheri Muralidharan <m-karicheri2@ti.com>
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef _TVP514X_H
+#define _TVP514X_H
+
+/*
+ * Other macros
+ */
+#define TVP514X_MODULE_NAME		"tvp514x"
+
+#define TVP514X_XCLK_BT656		(27000000)
+
+/* Number of pixels and number of lines per frame for different standards */
+#define NTSC_NUM_ACTIVE_PIXELS		(720)
+#define NTSC_NUM_ACTIVE_LINES		(480)
+#define PAL_NUM_ACTIVE_PIXELS		(720)
+#define PAL_NUM_ACTIVE_LINES		(576)
+
+/**
+ * enum tvp514x_input - enum for different decoder input pin
+ *		configuration.
+ */
+enum tvp514x_input {
+	/*
+	 * CVBS input selection
+	 */
+	INPUT_CVBS_VI1A = 0x0,
+	INPUT_CVBS_VI1B,
+	INPUT_CVBS_VI1C,
+	INPUT_CVBS_VI2A = 0x04,
+	INPUT_CVBS_VI2B,
+	INPUT_CVBS_VI2C,
+	INPUT_CVBS_VI3A = 0x08,
+	INPUT_CVBS_VI3B,
+	INPUT_CVBS_VI3C,
+	INPUT_CVBS_VI4A = 0x0C,
+	/*
+	 * S-Video input selection
+	 */
+	INPUT_SVIDEO_VI2A_VI1A = 0x44,
+	INPUT_SVIDEO_VI2B_VI1B,
+	INPUT_SVIDEO_VI2C_VI1C,
+	INPUT_SVIDEO_VI2A_VI3A = 0x54,
+	INPUT_SVIDEO_VI2B_VI3B,
+	INPUT_SVIDEO_VI2C_VI3C,
+	INPUT_SVIDEO_VI4A_VI1A = 0x4C,
+	INPUT_SVIDEO_VI4A_VI1B,
+	INPUT_SVIDEO_VI4A_VI1C,
+	INPUT_SVIDEO_VI4A_VI3A = 0x5C,
+	INPUT_SVIDEO_VI4A_VI3B,
+	INPUT_SVIDEO_VI4A_VI3C,
+
+	/* Need to add entries for
+	 * RGB, YPbPr and SCART.
+	 */
+	INPUT_INVALID
+};
+
+/**
+ * enum tvp514x_output - enum for output format
+ *			supported.
+ *
+ */
+enum tvp514x_output {
+	OUTPUT_10BIT_422_EMBEDDED_SYNC = 0,
+	OUTPUT_20BIT_422_SEPERATE_SYNC,
+	OUTPUT_10BIT_422_SEPERATE_SYNC = 3,
+	OUTPUT_INVALID
+};
+
+/**
+ * struct tvp514x_platform_data - Platform data values and access functions.
+ * @power_set: Power state access function, zero is off, non-zero is on.
+ * @ifparm: Interface parameters access function.
+ * @priv_data_set: Device private data (pointer) access function.
+ * @clk_polarity: Clock polarity of the current interface.
+ * @ hs_polarity: HSYNC Polarity configuration for current interface.
+ * @ vs_polarity: VSYNC Polarity configuration for current interface.
+ */
+struct tvp514x_platform_data {
+	char *master;
+	int (*power_set) (enum v4l2_power on);
+	int (*ifparm) (struct v4l2_ifparm *p);
+	int (*priv_data_set) (void *);
+	/* Interface control params */
+	bool clk_polarity;
+	bool hs_polarity;
+	bool vs_polarity;
+};
+
+
+#endif				/* ifndef _TVP514X_H */
diff --git a/include/media/tw9910.h b/include/media/tw9910.h
new file mode 100644
index 000000000000..73231e7880d8
--- /dev/null
+++ b/include/media/tw9910.h
@@ -0,0 +1,39 @@
+/*
+ * tw9910 Driver header
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ * Based on ov772x.h
+ *
+ * Copyright (C) Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __TW9910_H__
+#define __TW9910_H__
+
+#include <media/soc_camera.h>
+
+enum tw9910_mpout_pin {
+	TW9910_MPO_VLOSS,
+	TW9910_MPO_HLOCK,
+	TW9910_MPO_SLOCK,
+	TW9910_MPO_VLOCK,
+	TW9910_MPO_MONO,
+	TW9910_MPO_DET50,
+	TW9910_MPO_FIELD,
+	TW9910_MPO_RTCO,
+};
+
+struct tw9910_video_info {
+	unsigned long          buswidth;
+	enum tw9910_mpout_pin  mpout;
+	struct soc_camera_link link;
+};
+
+
+#endif /* __TW9910_H__ */
diff --git a/include/media/v4l2-chip-ident.h b/include/media/v4l2-chip-ident.h
index d73a8e9028a5..43dbb659f1f5 100644
--- a/include/media/v4l2-chip-ident.h
+++ b/include/media/v4l2-chip-ident.h
@@ -60,6 +60,8 @@ enum {
 
 	/* OmniVision sensors: reserved range 250-299 */
 	V4L2_IDENT_OV7670 = 250,
+	V4L2_IDENT_OV7720 = 251,
+	V4L2_IDENT_OV7725 = 252,
 
 	/* Conexant MPEG encoder/decoders: reserved range 410-420 */
 	V4L2_IDENT_CX23415 = 415,
@@ -69,6 +71,9 @@ enum {
 	/* module vp27smpx: just ident 2700 */
 	V4L2_IDENT_VP27SMPX = 2700,
 
+	/* module tvp5150 */
+	V4L2_IDENT_TVP5150 = 5150,
+
 	/* module cs5345: just ident 5345 */
 	V4L2_IDENT_CS5345 = 5345,
 
@@ -82,6 +87,9 @@ enum {
 	/* module wm8775: just ident 8775 */
 	V4L2_IDENT_WM8775 = 8775,
 
+	/* module tw9910: just ident 9910 */
+	V4L2_IDENT_TW9910 = 9910,
+
 	/* module cs53132a: just ident 53132 */
 	V4L2_IDENT_CS53l32A = 53132,
 
@@ -166,8 +174,10 @@ enum {
 	V4L2_IDENT_MT9M001C12ST		= 45000,
 	V4L2_IDENT_MT9M001C12STM	= 45005,
 	V4L2_IDENT_MT9M111		= 45007,
+	V4L2_IDENT_MT9M112		= 45008,
 	V4L2_IDENT_MT9V022IX7ATC	= 45010, /* No way to detect "normal" I77ATx */
 	V4L2_IDENT_MT9V022IX7ATM	= 45015, /* and "lead free" IA7ATx chips */
+	V4L2_IDENT_MT9T031		= 45020,
 };
 
 #endif
diff --git a/include/media/v4l2-common.h b/include/media/v4l2-common.h
index 2f8719abf5cb..f99c866d8c37 100644
--- a/include/media/v4l2-common.h
+++ b/include/media/v4l2-common.h
@@ -57,6 +57,29 @@
 
 /* ------------------------------------------------------------------------- */
 
+/* These printk constructs can be used with v4l2_device and v4l2_subdev */
+#define v4l2_printk(level, dev, fmt, arg...) \
+	printk(level "%s: " fmt, (dev)->name , ## arg)
+
+#define v4l2_err(dev, fmt, arg...) \
+	v4l2_printk(KERN_ERR, dev, fmt , ## arg)
+
+#define v4l2_warn(dev, fmt, arg...) \
+	v4l2_printk(KERN_WARNING, dev, fmt , ## arg)
+
+#define v4l2_info(dev, fmt, arg...) \
+	v4l2_printk(KERN_INFO, dev, fmt , ## arg)
+
+/* These three macros assume that the debug level is set with a module
+   parameter called 'debug'. */
+#define v4l2_dbg(level, debug, dev, fmt, arg...)			\
+	do { 								\
+		if (debug >= (level))					\
+			v4l2_printk(KERN_DEBUG, dev, fmt , ## arg); 	\
+	} while (0)
+
+/* ------------------------------------------------------------------------- */
+
 /* Priority helper functions */
 
 struct v4l2_prio_state {
@@ -104,11 +127,29 @@ struct i2c_driver;
 struct i2c_adapter;
 struct i2c_client;
 struct i2c_device_id;
+struct v4l2_device;
+struct v4l2_subdev;
+struct v4l2_subdev_ops;
 
 int v4l2_i2c_attach(struct i2c_adapter *adapter, int address, struct i2c_driver *driver,
 		const char *name,
 		int (*probe)(struct i2c_client *, const struct i2c_device_id *));
 
+/* Load an i2c module and return an initialized v4l2_subdev struct.
+   Only call request_module if module_name != NULL.
+   The client_type argument is the name of the chip that's on the adapter. */
+struct v4l2_subdev *v4l2_i2c_new_subdev(struct i2c_adapter *adapter,
+		const char *module_name, const char *client_type, u8 addr);
+/* Probe and load an i2c module and return an initialized v4l2_subdev struct.
+   Only call request_module if module_name != NULL.
+   The client_type argument is the name of the chip that's on the adapter. */
+struct v4l2_subdev *v4l2_i2c_new_probed_subdev(struct i2c_adapter *adapter,
+		const char *module_name, const char *client_type,
+		const unsigned short *addrs);
+/* Initialize an v4l2_subdev with data from an i2c_client struct */
+void v4l2_i2c_subdev_init(struct v4l2_subdev *sd, struct i2c_client *client,
+		const struct v4l2_subdev_ops *ops);
+
 /* ------------------------------------------------------------------------- */
 
 /* Internal ioctls */
diff --git a/include/media/v4l2-dev.h b/include/media/v4l2-dev.h
index a0a6b41c5e09..0a88d1d17d30 100644
--- a/include/media/v4l2-dev.h
+++ b/include/media/v4l2-dev.h
@@ -25,6 +25,12 @@
 #define VFL_TYPE_MAX		4
 
 struct v4l2_ioctl_callbacks;
+struct v4l2_device;
+
+/* Flag to mark the video_device struct as unregistered.
+   Drivers can set this flag if they want to block all future
+   device access. It is set by video_unregister_device. */
+#define V4L2_FL_UNREGISTERED	(0)
 
 /*
  * Newer version of video_device, handled by videodev2.c
@@ -39,15 +45,20 @@ struct video_device
 
 	/* sysfs */
 	struct device dev;		/* v4l device */
-	struct cdev cdev;		/* character device */
-	void (*cdev_release)(struct kobject *kobj);
+	struct cdev *cdev;		/* character device */
+
+	/* Set either parent or v4l2_dev if your driver uses v4l2_device */
 	struct device *parent;		/* device parent */
+	struct v4l2_device *v4l2_dev;	/* v4l2_device parent */
 
 	/* device info */
 	char name[32];
 	int vfl_type;
+	/* 'minor' is set to -1 if the registration failed */
 	int minor;
 	u16 num;
+	/* use bitops to set/clear/test flags */
+	unsigned long flags;
 	/* attribute to differentiate multiple indices on one physical device */
 	int index;
 
@@ -58,7 +69,7 @@ struct video_device
 	v4l2_std_id current_norm;	/* Current tvnorm */
 
 	/* callbacks */
-	void (*release)(struct video_device *vfd);
+	void (*release)(struct video_device *vdev);
 
 	/* ioctl callbacks */
 	const struct v4l2_ioctl_ops *ioctl_ops;
@@ -67,36 +78,41 @@ struct video_device
 /* dev to video-device */
 #define to_video_device(cd) container_of(cd, struct video_device, dev)
 
-/* Register and unregister devices. Note that if video_register_device fails,
+/* Register video devices. Note that if video_register_device fails,
    the release() callback of the video_device structure is *not* called, so
    the caller is responsible for freeing any data. Usually that means that
-   you call video_device_release() on failure. */
-int __must_check video_register_device(struct video_device *vfd, int type, int nr);
-int __must_check video_register_device_index(struct video_device *vfd,
+   you call video_device_release() on failure.
+
+   Also note that vdev->minor is set to -1 if the registration failed. */
+int __must_check video_register_device(struct video_device *vdev, int type, int nr);
+int __must_check video_register_device_index(struct video_device *vdev,
 						int type, int nr, int index);
-void video_unregister_device(struct video_device *vfd);
+
+/* Unregister video devices. Will do nothing if vdev == NULL or
+   vdev->minor < 0. */
+void video_unregister_device(struct video_device *vdev);
 
 /* helper functions to alloc/release struct video_device, the
    latter can also be used for video_device->release(). */
 struct video_device * __must_check video_device_alloc(void);
 
-/* this release function frees the vfd pointer */
-void video_device_release(struct video_device *vfd);
+/* this release function frees the vdev pointer */
+void video_device_release(struct video_device *vdev);
 
 /* this release function does nothing, use when the video_device is a
    static global struct. Note that having a static video_device is
    a dubious construction at best. */
-void video_device_release_empty(struct video_device *vfd);
+void video_device_release_empty(struct video_device *vdev);
 
 /* helper functions to access driver private data. */
-static inline void *video_get_drvdata(struct video_device *dev)
+static inline void *video_get_drvdata(struct video_device *vdev)
 {
-	return dev_get_drvdata(&dev->dev);
+	return dev_get_drvdata(&vdev->dev);
 }
 
-static inline void video_set_drvdata(struct video_device *dev, void *data)
+static inline void video_set_drvdata(struct video_device *vdev, void *data)
 {
-	dev_set_drvdata(&dev->dev, data);
+	dev_set_drvdata(&vdev->dev, data);
 }
 
 struct video_device *video_devdata(struct file *file);
@@ -108,4 +124,9 @@ static inline void *video_drvdata(struct file *file)
 	return video_get_drvdata(video_devdata(file));
 }
 
+static inline int video_is_unregistered(struct video_device *vdev)
+{
+	return test_bit(V4L2_FL_UNREGISTERED, &vdev->flags);
+}
+
 #endif /* _V4L2_DEV_H */
diff --git a/include/media/v4l2-device.h b/include/media/v4l2-device.h
new file mode 100644
index 000000000000..97b283a04289
--- /dev/null
+++ b/include/media/v4l2-device.h
@@ -0,0 +1,109 @@
+/*
+    V4L2 device support header.
+
+    Copyright (C) 2008  Hans Verkuil <hverkuil@xs4all.nl>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef _V4L2_DEVICE_H
+#define _V4L2_DEVICE_H
+
+#include <media/v4l2-subdev.h>
+
+/* Each instance of a V4L2 device should create the v4l2_device struct,
+   either stand-alone or embedded in a larger struct.
+
+   It allows easy access to sub-devices (see v4l2-subdev.h) and provides
+   basic V4L2 device-level support.
+ */
+
+#define V4L2_DEVICE_NAME_SIZE (BUS_ID_SIZE + 16)
+
+struct v4l2_device {
+	/* dev->driver_data points to this struct */
+	struct device *dev;
+	/* used to keep track of the registered subdevs */
+	struct list_head subdevs;
+	/* lock this struct; can be used by the driver as well if this
+	   struct is embedded into a larger struct. */
+	spinlock_t lock;
+	/* unique device name, by default the driver name + bus ID */
+	char name[V4L2_DEVICE_NAME_SIZE];
+};
+
+/* Initialize v4l2_dev and make dev->driver_data point to v4l2_dev */
+int __must_check v4l2_device_register(struct device *dev, struct v4l2_device *v4l2_dev);
+/* Set v4l2_dev->dev->driver_data to NULL and unregister all sub-devices */
+void v4l2_device_unregister(struct v4l2_device *v4l2_dev);
+
+/* Register a subdev with a v4l2 device. While registered the subdev module
+   is marked as in-use. An error is returned if the module is no longer
+   loaded when you attempt to register it. */
+int __must_check v4l2_device_register_subdev(struct v4l2_device *dev, struct v4l2_subdev *sd);
+/* Unregister a subdev with a v4l2 device. Can also be called if the subdev
+   wasn't registered. In that case it will do nothing. */
+void v4l2_device_unregister_subdev(struct v4l2_subdev *sd);
+
+/* Iterate over all subdevs. */
+#define v4l2_device_for_each_subdev(sd, dev)				\
+	list_for_each_entry(sd, &(dev)->subdevs, list)
+
+/* Call the specified callback for all subdevs matching the condition.
+   Ignore any errors. Note that you cannot add or delete a subdev
+   while walking the subdevs list. */
+#define __v4l2_device_call_subdevs(dev, cond, o, f, args...) 		\
+	do { 								\
+		struct v4l2_subdev *sd; 				\
+									\
+		list_for_each_entry(sd, &(dev)->subdevs, list)   	\
+			if ((cond) && sd->ops->o && sd->ops->o->f) 	\
+				sd->ops->o->f(sd , ##args); 		\
+	} while (0)
+
+/* Call the specified callback for all subdevs matching the condition.
+   If the callback returns an error other than 0 or -ENOIOCTLCMD, then
+   return with that error code. Note that you cannot add or delete a
+   subdev while walking the subdevs list. */
+#define __v4l2_device_call_subdevs_until_err(dev, cond, o, f, args...)  \
+({ 									\
+	struct v4l2_subdev *sd; 					\
+	int err = 0; 							\
+									\
+	list_for_each_entry(sd, &(dev)->subdevs, list) { 		\
+		if ((cond) && sd->ops->o && sd->ops->o->f) 		\
+			err = sd->ops->o->f(sd , ##args); 		\
+		if (err && err != -ENOIOCTLCMD)				\
+			break; 						\
+	} 								\
+	(err == -ENOIOCTLCMD) ? 0 : err; 				\
+})
+
+/* Call the specified callback for all subdevs matching grp_id (if 0, then
+   match them all). Ignore any errors. Note that you cannot add or delete
+   a subdev while walking the subdevs list. */
+#define v4l2_device_call_all(dev, grp_id, o, f, args...) 		\
+	__v4l2_device_call_subdevs(dev, 				\
+			!(grp_id) || sd->grp_id == (grp_id), o, f , ##args)
+
+/* Call the specified callback for all subdevs matching grp_id (if 0, then
+   match them all). If the callback returns an error other than 0 or
+   -ENOIOCTLCMD, then return with that error code. Note that you cannot
+   add or delete a subdev while walking the subdevs list. */
+#define v4l2_device_call_until_err(dev, grp_id, o, f, args...) 		\
+	__v4l2_device_call_subdevs_until_err(dev,			\
+		       !(grp_id) || sd->grp_id == (grp_id), o, f , ##args)
+
+#endif
diff --git a/include/media/v4l2-i2c-drv-legacy.h b/include/media/v4l2-i2c-drv-legacy.h
index 975ffbf4e2c5..e65dd9d84e8b 100644
--- a/include/media/v4l2-i2c-drv-legacy.h
+++ b/include/media/v4l2-i2c-drv-legacy.h
@@ -21,6 +21,17 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+/* NOTE: the full version of this header is in the v4l-dvb repository
+ * and allows v4l i2c drivers to be compiled on older kernels as well.
+ * The version of this header as it appears in the kernel is a stripped
+ * version (without all the backwards compatibility stuff) and so it
+ * looks a bit odd.
+ *
+ * If you look at the full version then you will understand the reason
+ * for introducing this header since you really don't want to have all
+ * the tricky backwards compatibility code in each and every i2c driver.
+ */
+
 struct v4l2_i2c_driver_data {
 	const char * const name;
 	int driverid;
diff --git a/include/media/v4l2-i2c-drv.h b/include/media/v4l2-i2c-drv.h
index 40ecef29801d..efdc8bf27f87 100644
--- a/include/media/v4l2-i2c-drv.h
+++ b/include/media/v4l2-i2c-drv.h
@@ -21,6 +21,17 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+/* NOTE: the full version of this header is in the v4l-dvb repository
+ * and allows v4l i2c drivers to be compiled on older kernels as well.
+ * The version of this header as it appears in the kernel is a stripped
+ * version (without all the backwards compatibility stuff) and so it
+ * looks a bit odd.
+ *
+ * If you look at the full version then you will understand the reason
+ * for introducing this header since you really don't want to have all
+ * the tricky backwards compatibility code in each and every i2c driver.
+ */
+
 #ifndef __V4L2_I2C_DRV_H__
 #define __V4L2_I2C_DRV_H__
 
diff --git a/include/media/v4l2-int-device.h b/include/media/v4l2-int-device.h
index c8b80e0f0651..ecda3c725837 100644
--- a/include/media/v4l2-int-device.h
+++ b/include/media/v4l2-int-device.h
@@ -84,6 +84,8 @@ struct v4l2_int_device {
 	void *priv;
 };
 
+void v4l2_int_device_try_attach_all(void);
+
 int v4l2_int_device_register(struct v4l2_int_device *d);
 void v4l2_int_device_unregister(struct v4l2_int_device *d);
 
@@ -96,6 +98,12 @@ int v4l2_int_ioctl_1(struct v4l2_int_device *d, int cmd, void *arg);
  *
  */
 
+enum v4l2_power {
+	V4L2_POWER_OFF = 0,
+	V4L2_POWER_ON,
+	V4L2_POWER_STANDBY,
+};
+
 /* Slave interface type. */
 enum v4l2_if_type {
 	/*
@@ -170,8 +178,14 @@ enum v4l2_int_ioctl_num {
 	vidioc_int_queryctrl_num,
 	vidioc_int_g_ctrl_num,
 	vidioc_int_s_ctrl_num,
+	vidioc_int_cropcap_num,
+	vidioc_int_g_crop_num,
+	vidioc_int_s_crop_num,
 	vidioc_int_g_parm_num,
 	vidioc_int_s_parm_num,
+	vidioc_int_querystd_num,
+	vidioc_int_s_std_num,
+	vidioc_int_s_video_routing_num,
 
 	/*
 	 *
@@ -182,12 +196,19 @@ enum v4l2_int_ioctl_num {
 	vidioc_int_dev_init_num = 1000,
 	/* Delinitialise the device at slave detach. */
 	vidioc_int_dev_exit_num,
-	/* Set device power state: 0 is off, non-zero is on. */
+	/* Set device power state. */
 	vidioc_int_s_power_num,
+	/*
+	* Get slave private data, e.g. platform-specific slave
+	* configuration used by the master.
+	*/
+	vidioc_int_g_priv_num,
 	/* Get slave interface parameters. */
 	vidioc_int_g_ifparm_num,
 	/* Does the slave need to be reset after VIDIOC_DQBUF? */
 	vidioc_int_g_needs_reset_num,
+	vidioc_int_enum_framesizes_num,
+	vidioc_int_enum_frameintervals_num,
 
 	/*
 	 *
@@ -261,14 +282,23 @@ V4L2_INT_WRAPPER_1(try_fmt_cap, struct v4l2_format, *);
 V4L2_INT_WRAPPER_1(queryctrl, struct v4l2_queryctrl, *);
 V4L2_INT_WRAPPER_1(g_ctrl, struct v4l2_control, *);
 V4L2_INT_WRAPPER_1(s_ctrl, struct v4l2_control, *);
+V4L2_INT_WRAPPER_1(cropcap, struct v4l2_cropcap, *);
+V4L2_INT_WRAPPER_1(g_crop, struct v4l2_crop, *);
+V4L2_INT_WRAPPER_1(s_crop, struct v4l2_crop, *);
 V4L2_INT_WRAPPER_1(g_parm, struct v4l2_streamparm, *);
 V4L2_INT_WRAPPER_1(s_parm, struct v4l2_streamparm, *);
+V4L2_INT_WRAPPER_1(querystd, v4l2_std_id, *);
+V4L2_INT_WRAPPER_1(s_std, v4l2_std_id, *);
+V4L2_INT_WRAPPER_1(s_video_routing, struct v4l2_routing, *);
 
 V4L2_INT_WRAPPER_0(dev_init);
 V4L2_INT_WRAPPER_0(dev_exit);
-V4L2_INT_WRAPPER_1(s_power, int, );
+V4L2_INT_WRAPPER_1(s_power, enum v4l2_power, );
+V4L2_INT_WRAPPER_1(g_priv, void, *);
 V4L2_INT_WRAPPER_1(g_ifparm, struct v4l2_ifparm, *);
 V4L2_INT_WRAPPER_1(g_needs_reset, void, *);
+V4L2_INT_WRAPPER_1(enum_framesizes, struct v4l2_frmsizeenum, *);
+V4L2_INT_WRAPPER_1(enum_frameintervals, struct v4l2_frmivalenum, *);
 
 V4L2_INT_WRAPPER_0(reset);
 V4L2_INT_WRAPPER_0(init);
diff --git a/include/media/v4l2-ioctl.h b/include/media/v4l2-ioctl.h
index 0bef03add796..fcdb58c4ce07 100644
--- a/include/media/v4l2-ioctl.h
+++ b/include/media/v4l2-ioctl.h
@@ -232,6 +232,12 @@ struct v4l2_ioctl_ops {
 	int (*vidioc_g_chip_ident)     (struct file *file, void *fh,
 					struct v4l2_chip_ident *chip);
 
+	int (*vidioc_enum_framesizes)   (struct file *file, void *fh,
+					 struct v4l2_frmsizeenum *fsize);
+
+	int (*vidioc_enum_frameintervals) (struct file *file, void *fh,
+					   struct v4l2_frmivalenum *fival);
+
 	/* For other private ioctls */
 	int (*vidioc_default)	       (struct file *file, void *fh,
 					int cmd, void *arg);
@@ -271,26 +277,36 @@ extern const char *v4l2_field_names[];
 extern const char *v4l2_type_names[];
 
 /*  Compatibility layer interface  --  v4l1-compat module */
-typedef int (*v4l2_kioctl)(struct inode *inode, struct file *file,
+typedef int (*v4l2_kioctl)(struct file *file,
 			   unsigned int cmd, void *arg);
 #ifdef CONFIG_VIDEO_V4L1_COMPAT
-int v4l_compat_translate_ioctl(struct inode *inode, struct file *file,
+int v4l_compat_translate_ioctl(struct file *file,
 			       int cmd, void *arg, v4l2_kioctl driver_ioctl);
 #else
-#define v4l_compat_translate_ioctl(inode, file, cmd, arg, ioctl) (-EINVAL)
+#define v4l_compat_translate_ioctl(file, cmd, arg, ioctl) (-EINVAL)
 #endif
 
 /* 32 Bits compatibility layer for 64 bits processors */
 extern long v4l_compat_ioctl32(struct file *file, unsigned int cmd,
 				unsigned long arg);
 
-extern int video_ioctl2(struct inode *inode, struct file *file,
-			  unsigned int cmd, unsigned long arg);
-
 /* Include support for obsoleted stuff */
-extern int video_usercopy(struct inode *inode, struct file *file,
-			  unsigned int cmd, unsigned long arg,
-			  int (*func)(struct inode *inode, struct file *file,
-				      unsigned int cmd, void *arg));
+extern int video_usercopy(struct file *file, unsigned int cmd,
+				unsigned long arg, v4l2_kioctl func);
+
+/* Standard handlers for V4L ioctl's */
+
+/* This prototype is used on fops.unlocked_ioctl */
+extern long __video_ioctl2(struct file *file,
+			unsigned int cmd, unsigned long arg);
+
+/* This prototype is used on fops.ioctl
+ * Since fops.ioctl enables Kernel Big Lock, it is preferred
+ * to use __video_ioctl2 instead.
+ * It should be noticed that there's no lock code inside
+ * video_ioctl2().
+ */
+extern int video_ioctl2(struct inode *inode, struct file *file,
+			unsigned int cmd, unsigned long arg);
 
 #endif /* _V4L2_IOCTL_H */
diff --git a/include/media/v4l2-subdev.h b/include/media/v4l2-subdev.h
new file mode 100644
index 000000000000..ceef016bb0b7
--- /dev/null
+++ b/include/media/v4l2-subdev.h
@@ -0,0 +1,189 @@
+/*
+    V4L2 sub-device support header.
+
+    Copyright (C) 2008  Hans Verkuil <hverkuil@xs4all.nl>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef _V4L2_SUBDEV_H
+#define _V4L2_SUBDEV_H
+
+#include <media/v4l2-common.h>
+
+struct v4l2_device;
+struct v4l2_subdev;
+struct tuner_setup;
+
+/* Sub-devices are devices that are connected somehow to the main bridge
+   device. These devices are usually audio/video muxers/encoders/decoders or
+   sensors and webcam controllers.
+
+   Usually these devices are controlled through an i2c bus, but other busses
+   may also be used.
+
+   The v4l2_subdev struct provides a way of accessing these devices in a
+   generic manner. Most operations that these sub-devices support fall in
+   a few categories: core ops, audio ops, video ops and tuner ops.
+
+   More categories can be added if needed, although this should remain a
+   limited set (no more than approx. 8 categories).
+
+   Each category has its own set of ops that subdev drivers can implement.
+
+   A subdev driver can leave the pointer to the category ops NULL if
+   it does not implement them (e.g. an audio subdev will generally not
+   implement the video category ops). The exception is the core category:
+   this must always be present.
+
+   These ops are all used internally so it is no problem to change, remove
+   or add ops or move ops from one to another category. Currently these
+   ops are based on the original ioctls, but since ops are not limited to
+   one argument there is room for improvement here once all i2c subdev
+   drivers are converted to use these ops.
+ */
+
+/* Core ops: it is highly recommended to implement at least these ops:
+
+   g_chip_ident
+   log_status
+   g_register
+   s_register
+
+   This provides basic debugging support.
+
+   The ioctl ops is meant for generic ioctl-like commands. Depending on
+   the use-case it might be better to use subdev-specific ops (currently
+   not yet implemented) since ops provide proper type-checking.
+ */
+struct v4l2_subdev_core_ops {
+	int (*g_chip_ident)(struct v4l2_subdev *sd, struct v4l2_chip_ident *chip);
+	int (*log_status)(struct v4l2_subdev *sd);
+	int (*init)(struct v4l2_subdev *sd, u32 val);
+	int (*s_standby)(struct v4l2_subdev *sd, u32 standby);
+	int (*reset)(struct v4l2_subdev *sd, u32 val);
+	int (*s_gpio)(struct v4l2_subdev *sd, u32 val);
+	int (*queryctrl)(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc);
+	int (*g_ctrl)(struct v4l2_subdev *sd, struct v4l2_control *ctrl);
+	int (*s_ctrl)(struct v4l2_subdev *sd, struct v4l2_control *ctrl);
+	int (*querymenu)(struct v4l2_subdev *sd, struct v4l2_querymenu *qm);
+	int (*ioctl)(struct v4l2_subdev *sd, unsigned int cmd, void *arg);
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+	int (*g_register)(struct v4l2_subdev *sd, struct v4l2_register *reg);
+	int (*s_register)(struct v4l2_subdev *sd, struct v4l2_register *reg);
+#endif
+};
+
+struct v4l2_subdev_tuner_ops {
+	int (*s_mode)(struct v4l2_subdev *sd, enum v4l2_tuner_type);
+	int (*s_radio)(struct v4l2_subdev *sd);
+	int (*s_frequency)(struct v4l2_subdev *sd, struct v4l2_frequency *freq);
+	int (*g_frequency)(struct v4l2_subdev *sd, struct v4l2_frequency *freq);
+	int (*g_tuner)(struct v4l2_subdev *sd, struct v4l2_tuner *vt);
+	int (*s_tuner)(struct v4l2_subdev *sd, struct v4l2_tuner *vt);
+	int (*s_std)(struct v4l2_subdev *sd, v4l2_std_id norm);
+	int (*s_type_addr)(struct v4l2_subdev *sd, struct tuner_setup *type);
+	int (*s_config)(struct v4l2_subdev *sd, const struct v4l2_priv_tun_config *config);
+};
+
+struct v4l2_subdev_audio_ops {
+	int (*s_clock_freq)(struct v4l2_subdev *sd, u32 freq);
+	int (*s_i2s_clock_freq)(struct v4l2_subdev *sd, u32 freq);
+	int (*s_routing)(struct v4l2_subdev *sd, const struct v4l2_routing *route);
+};
+
+struct v4l2_subdev_video_ops {
+	int (*s_routing)(struct v4l2_subdev *sd, const struct v4l2_routing *route);
+	int (*s_crystal_freq)(struct v4l2_subdev *sd, struct v4l2_crystal_freq *freq);
+	int (*decode_vbi_line)(struct v4l2_subdev *sd, struct v4l2_decode_vbi_line *vbi_line);
+	int (*s_vbi_data)(struct v4l2_subdev *sd, const struct v4l2_sliced_vbi_data *vbi_data);
+	int (*g_vbi_data)(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_data *vbi_data);
+	int (*g_sliced_vbi_cap)(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_cap *cap);
+	int (*s_std_output)(struct v4l2_subdev *sd, v4l2_std_id std);
+	int (*s_stream)(struct v4l2_subdev *sd, int enable);
+	int (*s_fmt)(struct v4l2_subdev *sd, struct v4l2_format *fmt);
+	int (*g_fmt)(struct v4l2_subdev *sd, struct v4l2_format *fmt);
+};
+
+struct v4l2_subdev_ops {
+	const struct v4l2_subdev_core_ops  *core;
+	const struct v4l2_subdev_tuner_ops *tuner;
+	const struct v4l2_subdev_audio_ops *audio;
+	const struct v4l2_subdev_video_ops *video;
+};
+
+#define V4L2_SUBDEV_NAME_SIZE 32
+
+/* Each instance of a subdev driver should create this struct, either
+   stand-alone or embedded in a larger struct.
+ */
+struct v4l2_subdev {
+	struct list_head list;
+	struct module *owner;
+	struct v4l2_device *dev;
+	const struct v4l2_subdev_ops *ops;
+	/* name must be unique */
+	char name[V4L2_SUBDEV_NAME_SIZE];
+	/* can be used to group similar subdevs, value is driver-specific */
+	u32 grp_id;
+	/* pointer to private data */
+	void *priv;
+};
+
+static inline void v4l2_set_subdevdata(struct v4l2_subdev *sd, void *p)
+{
+	sd->priv = p;
+}
+
+static inline void *v4l2_get_subdevdata(const struct v4l2_subdev *sd)
+{
+	return sd->priv;
+}
+
+/* Convert an ioctl-type command to the proper v4l2_subdev_ops function call.
+   This is used by subdev modules that can be called by both old-style ioctl
+   commands and through the v4l2_subdev_ops.
+
+   The ioctl API of the subdev driver can call this function to call the
+   right ops based on the ioctl cmd and arg.
+
+   Once all subdev drivers have been converted and all drivers no longer
+   use the ioctl interface, then this function can be removed.
+ */
+int v4l2_subdev_command(struct v4l2_subdev *sd, unsigned cmd, void *arg);
+
+static inline void v4l2_subdev_init(struct v4l2_subdev *sd,
+					const struct v4l2_subdev_ops *ops)
+{
+	INIT_LIST_HEAD(&sd->list);
+	/* ops->core MUST be set */
+	BUG_ON(!ops || !ops->core);
+	sd->ops = ops;
+	sd->dev = NULL;
+	sd->name[0] = '\0';
+	sd->grp_id = 0;
+	sd->priv = NULL;
+}
+
+/* Call an ops of a v4l2_subdev, doing the right checks against
+   NULL pointers.
+
+   Example: err = v4l2_subdev_call(sd, core, g_chip_ident, &chip);
+ */
+#define v4l2_subdev_call(sd, o, f, args...)				\
+	(!(sd) ? -ENODEV : (((sd) && (sd)->ops->o && (sd)->ops->o->f) ?	\
+		(sd)->ops->o->f((sd) , ##args) : -ENOIOCTLCMD))
+
+#endif
diff --git a/include/media/videobuf-dvb.h b/include/media/videobuf-dvb.h
index b77748696329..6ba4f1271d23 100644
--- a/include/media/videobuf-dvb.h
+++ b/include/media/videobuf-dvb.h
@@ -16,7 +16,6 @@ struct videobuf_dvb {
 	int                        nfeeds;
 
 	/* videobuf_dvb_(un)register manges this */
-	struct dvb_adapter         adapter;
 	struct dvb_demux           demux;
 	struct dmxdev              dmxdev;
 	struct dmx_frontend        fe_hw;
@@ -24,12 +23,35 @@ struct videobuf_dvb {
 	struct dvb_net             net;
 };
 
-int videobuf_dvb_register(struct videobuf_dvb *dvb,
+struct videobuf_dvb_frontend {
+	struct list_head felist;
+	int id;
+	struct videobuf_dvb dvb;
+};
+
+struct videobuf_dvb_frontends {
+	struct list_head felist;
+	struct mutex lock;
+	struct dvb_adapter adapter;
+	int active_fe_id; /* Indicates which frontend in the felist is in use */
+	int gate; /* Frontend with gate control 0=!MFE,1=fe0,2=fe1 etc */
+};
+
+int videobuf_dvb_register_bus(struct videobuf_dvb_frontends *f,
 			  struct module *module,
 			  void *adapter_priv,
 			  struct device *device,
-			  short *adapter_nr);
-void videobuf_dvb_unregister(struct videobuf_dvb *dvb);
+			  short *adapter_nr,
+			  int mfe_shared);
+
+void videobuf_dvb_unregister_bus(struct videobuf_dvb_frontends *f);
+
+struct videobuf_dvb_frontend * videobuf_dvb_alloc_frontend(struct videobuf_dvb_frontends *f, int id);
+void videobuf_dvb_dealloc_frontends(struct videobuf_dvb_frontends *f);
+
+struct videobuf_dvb_frontend * videobuf_dvb_get_frontend(struct videobuf_dvb_frontends *f, int id);
+int videobuf_dvb_find_frontend(struct videobuf_dvb_frontends *f, struct dvb_frontend *p);
+
 
 /*
  * Local variables:
diff --git a/include/net/9p/9p.h b/include/net/9p/9p.h
index c3626c0ba9d3..b77c1478c99f 100644
--- a/include/net/9p/9p.h
+++ b/include/net/9p/9p.h
@@ -27,8 +27,6 @@
 #ifndef NET_9P_H
 #define NET_9P_H
 
-#ifdef CONFIG_NET_9P_DEBUG
-
 /**
  * enum p9_debug_flags - bits for mount time debug parameter
  * @P9_DEBUG_ERROR: more verbose error messages including original error string
@@ -39,6 +37,7 @@
  * @P9_DEBUG_TRANS: transport tracing
  * @P9_DEBUG_SLABS: memory management tracing
  * @P9_DEBUG_FCALL: verbose dump of protocol messages
+ * @P9_DEBUG_FID: fid allocation/deallocation tracking
  *
  * These flags are passed at mount time to turn on various levels of
  * verbosity and tracing which will be output to the system logs.
@@ -53,30 +52,33 @@ enum p9_debug_flags {
 	P9_DEBUG_TRANS =	(1<<6),
 	P9_DEBUG_SLABS =      	(1<<7),
 	P9_DEBUG_FCALL =	(1<<8),
+	P9_DEBUG_FID =		(1<<9),
+	P9_DEBUG_PKT =		(1<<10),
 };
 
+#ifdef CONFIG_NET_9P_DEBUG
 extern unsigned int p9_debug_level;
 
 #define P9_DPRINTK(level, format, arg...) \
 do {  \
-	if ((p9_debug_level & level) == level) \
-		printk(KERN_NOTICE "-- %s (%d): " \
-		format , __FUNCTION__, task_pid_nr(current) , ## arg); \
+	if ((p9_debug_level & level) == level) {\
+		if (level == P9_DEBUG_9P) \
+			printk(KERN_NOTICE "(%8.8d) " \
+			format , task_pid_nr(current) , ## arg); \
+		else \
+			printk(KERN_NOTICE "-- %s (%d): " \
+			format , __func__, task_pid_nr(current) , ## arg); \
+	} \
 } while (0)
 
-#define PRINT_FCALL_ERROR(s, fcall) P9_DPRINTK(P9_DEBUG_ERROR,   \
-	"%s: %.*s\n", s, fcall?fcall->params.rerror.error.len:0, \
-	fcall?fcall->params.rerror.error.str:"");
-
 #else
 #define P9_DPRINTK(level, format, arg...)  do { } while (0)
-#define PRINT_FCALL_ERROR(s, fcall) do { } while (0)
 #endif
 
 #define P9_EPRINTK(level, format, arg...) \
 do { \
 	printk(level "9p: %s (%d): " \
-		format , __FUNCTION__, task_pid_nr(current), ## arg); \
+		format , __func__, task_pid_nr(current), ## arg); \
 } while (0)
 
 /**
@@ -325,33 +327,6 @@ struct p9_qid {
  * See Also: http://plan9.bell-labs.com/magic/man2html/2/stat
  */
 
-struct p9_stat {
-	u16 size;
-	u16 type;
-	u32 dev;
-	struct p9_qid qid;
-	u32 mode;
-	u32 atime;
-	u32 mtime;
-	u64 length;
-	struct p9_str name;
-	struct p9_str uid;
-	struct p9_str gid;
-	struct p9_str muid;
-	struct p9_str extension;	/* 9p2000.u extensions */
-	u32 n_uid;			/* 9p2000.u extensions */
-	u32 n_gid;			/* 9p2000.u extensions */
-	u32 n_muid;			/* 9p2000.u extensions */
-};
-
-/*
- * file metadata (stat) structure used to create Twstat message
- * The is identical to &p9_stat, but the strings don't point to
- * the same memory block and should be freed separately
- *
- * See Also: http://plan9.bell-labs.com/magic/man2html/2/stat
- */
-
 struct p9_wstat {
 	u16 size;
 	u16 type;
@@ -493,12 +468,12 @@ struct p9_tstat {
 };
 
 struct p9_rstat {
-	struct p9_stat stat;
+	struct p9_wstat stat;
 };
 
 struct p9_twstat {
 	u32 fid;
-	struct p9_stat stat;
+	struct p9_wstat stat;
 };
 
 struct p9_rwstat {
@@ -509,8 +484,9 @@ struct p9_rwstat {
  * @size: prefixed length of the structure
  * @id: protocol operating identifier of type &p9_msg_t
  * @tag: transaction id of the request
+ * @offset: used by marshalling routines to track currentposition in buffer
+ * @capacity: used by marshalling routines to track total capacity
  * @sdata: payload
- * @params: per-operation parameters
  *
  * &p9_fcall represents the structure for all 9P RPC
  * transactions.  Requests are packaged into fcalls, and reponses
@@ -523,68 +499,15 @@ struct p9_fcall {
 	u32 size;
 	u8 id;
 	u16 tag;
-	void *sdata;
-
-	union {
-		struct p9_tversion tversion;
-		struct p9_rversion rversion;
-		struct p9_tauth tauth;
-		struct p9_rauth rauth;
-		struct p9_rerror rerror;
-		struct p9_tflush tflush;
-		struct p9_rflush rflush;
-		struct p9_tattach tattach;
-		struct p9_rattach rattach;
-		struct p9_twalk twalk;
-		struct p9_rwalk rwalk;
-		struct p9_topen topen;
-		struct p9_ropen ropen;
-		struct p9_tcreate tcreate;
-		struct p9_rcreate rcreate;
-		struct p9_tread tread;
-		struct p9_rread rread;
-		struct p9_twrite twrite;
-		struct p9_rwrite rwrite;
-		struct p9_tclunk tclunk;
-		struct p9_rclunk rclunk;
-		struct p9_tremove tremove;
-		struct p9_rremove rremove;
-		struct p9_tstat tstat;
-		struct p9_rstat rstat;
-		struct p9_twstat twstat;
-		struct p9_rwstat rwstat;
-	} params;
+
+	size_t offset;
+	size_t capacity;
+
+	uint8_t *sdata;
 };
 
 struct p9_idpool;
 
-int p9_deserialize_stat(void *buf, u32 buflen, struct p9_stat *stat,
-	int dotu);
-int p9_deserialize_fcall(void *buf, u32 buflen, struct p9_fcall *fc, int dotu);
-void p9_set_tag(struct p9_fcall *fc, u16 tag);
-struct p9_fcall *p9_create_tversion(u32 msize, char *version);
-struct p9_fcall *p9_create_tattach(u32 fid, u32 afid, char *uname,
-	char *aname, u32 n_uname, int dotu);
-struct p9_fcall *p9_create_tauth(u32 afid, char *uname, char *aname,
-	u32 n_uname, int dotu);
-struct p9_fcall *p9_create_tflush(u16 oldtag);
-struct p9_fcall *p9_create_twalk(u32 fid, u32 newfid, u16 nwname,
-	char **wnames);
-struct p9_fcall *p9_create_topen(u32 fid, u8 mode);
-struct p9_fcall *p9_create_tcreate(u32 fid, char *name, u32 perm, u8 mode,
-	char *extension, int dotu);
-struct p9_fcall *p9_create_tread(u32 fid, u64 offset, u32 count);
-struct p9_fcall *p9_create_twrite(u32 fid, u64 offset, u32 count,
-	const char *data);
-struct p9_fcall *p9_create_twrite_u(u32 fid, u64 offset, u32 count,
-	const char __user *data);
-struct p9_fcall *p9_create_tclunk(u32 fid);
-struct p9_fcall *p9_create_tremove(u32 fid);
-struct p9_fcall *p9_create_tstat(u32 fid);
-struct p9_fcall *p9_create_twstat(u32 fid, struct p9_wstat *wstat,
-	int dotu);
-
-int p9_printfcall(char *buf, int buflen, struct p9_fcall *fc, int dotu);
 int p9_errstr2errno(char *errstr, int len);
 
 struct p9_idpool *p9_idpool_create(void);
diff --git a/include/net/9p/client.h b/include/net/9p/client.h
index c936dd14de41..4012e07162e5 100644
--- a/include/net/9p/client.h
+++ b/include/net/9p/client.h
@@ -26,6 +26,87 @@
 #ifndef NET_9P_CLIENT_H
 #define NET_9P_CLIENT_H
 
+/* Number of requests per row */
+#define P9_ROW_MAXTAG 255
+
+/**
+ * enum p9_trans_status - different states of underlying transports
+ * @Connected: transport is connected and healthy
+ * @Disconnected: transport has been disconnected
+ * @Hung: transport is connected by wedged
+ *
+ * This enumeration details the various states a transport
+ * instatiation can be in.
+ */
+
+enum p9_trans_status {
+	Connected,
+	Disconnected,
+	Hung,
+};
+
+/**
+ * enum p9_req_status_t - virtio request status
+ * @REQ_STATUS_IDLE: request slot unused
+ * @REQ_STATUS_ALLOC: request has been allocated but not sent
+ * @REQ_STATUS_UNSENT: request waiting to be sent
+ * @REQ_STATUS_SENT: request sent to server
+ * @REQ_STATUS_FLSH: a flush has been sent for this request
+ * @REQ_STATUS_RCVD: response received from server
+ * @REQ_STATUS_FLSHD: request has been flushed
+ * @REQ_STATUS_ERROR: request encountered an error on the client side
+ *
+ * The @REQ_STATUS_IDLE state is used to mark a request slot as unused
+ * but use is actually tracked by the idpool structure which handles tag
+ * id allocation.
+ *
+ */
+
+enum p9_req_status_t {
+	REQ_STATUS_IDLE,
+	REQ_STATUS_ALLOC,
+	REQ_STATUS_UNSENT,
+	REQ_STATUS_SENT,
+	REQ_STATUS_FLSH,
+	REQ_STATUS_RCVD,
+	REQ_STATUS_FLSHD,
+	REQ_STATUS_ERROR,
+};
+
+/**
+ * struct p9_req_t - request slots
+ * @status: status of this request slot
+ * @t_err: transport error
+ * @flush_tag: tag of request being flushed (for flush requests)
+ * @wq: wait_queue for the client to block on for this request
+ * @tc: the request fcall structure
+ * @rc: the response fcall structure
+ * @aux: transport specific data (provided for trans_fd migration)
+ * @req_list: link for higher level objects to chain requests
+ *
+ * Transport use an array to track outstanding requests
+ * instead of a list.  While this may incurr overhead during initial
+ * allocation or expansion, it makes request lookup much easier as the
+ * tag id is a index into an array.  (We use tag+1 so that we can accomodate
+ * the -1 tag for the T_VERSION request).
+ * This also has the nice effect of only having to allocate wait_queues
+ * once, instead of constantly allocating and freeing them.  Its possible
+ * other resources could benefit from this scheme as well.
+ *
+ */
+
+struct p9_req_t {
+	int status;
+	int t_err;
+	u16 flush_tag;
+	wait_queue_head_t *wq;
+	struct p9_fcall *tc;
+	struct p9_fcall *rc;
+	void *aux;
+
+	struct list_head req_list;
+};
+
 /**
  * struct p9_client - per client instance state
  * @lock: protect @fidlist
@@ -36,9 +117,20 @@
  * @conn: connection state information used by trans_fd
  * @fidpool: fid handle accounting for session
  * @fidlist: List of active fid handles
+ * @tagpool - transaction id accounting for session
+ * @reqs - 2D array of requests
+ * @max_tag - current maximum tag id allocated
  *
  * The client structure is used to keep track of various per-client
  * state that has been instantiated.
+ * In order to minimize per-transaction overhead we use a
+ * simple array to lookup requests instead of a hash table
+ * or linked list.  In order to support larger number of
+ * transactions, we make this a 2D array, allocating new rows
+ * when we need to grow the total number of the transactions.
+ *
+ * Each row is 256 requests and we'll support up to 256 rows for
+ * a total of 64k concurrent requests per session.
  *
  * Bugs: duplicated data and potentially unnecessary elements.
  */
@@ -48,11 +140,16 @@ struct p9_client {
 	int msize;
 	unsigned char dotu;
 	struct p9_trans_module *trans_mod;
-	struct p9_trans *trans;
+	enum p9_trans_status status;
+	void *trans;
 	struct p9_conn *conn;
 
 	struct p9_idpool *fidpool;
 	struct list_head fidlist;
+
+	struct p9_idpool *tagpool;
+	struct p9_req_t *reqs[P9_ROW_MAXTAG];
+	int max_tag;
 };
 
 /**
@@ -65,8 +162,6 @@ struct p9_client {
  * @uid: the numeric uid of the local user who owns this handle
  * @aux: transport specific information (unused?)
  * @rdir_fpos: tracks offset of file position when reading directory contents
- * @rdir_pos: (unused?)
- * @rdir_fcall: holds response of last directory read request
  * @flist: per-client-instance fid tracking
  * @dlist: per-dentry fid tracking
  *
@@ -83,12 +178,11 @@ struct p9_fid {
 	void *aux;
 
 	int rdir_fpos;
-	int rdir_pos;
-	struct p9_fcall *rdir_fcall;
 	struct list_head flist;
 	struct list_head dlist;	/* list of all fids attached to a dentry */
 };
 
+int p9_client_version(struct p9_client *);
 struct p9_client *p9_client_create(const char *dev_name, char *options);
 void p9_client_destroy(struct p9_client *clnt);
 void p9_client_disconnect(struct p9_client *clnt);
@@ -103,15 +197,19 @@ int p9_client_fcreate(struct p9_fid *fid, char *name, u32 perm, int mode,
 							char *extension);
 int p9_client_clunk(struct p9_fid *fid);
 int p9_client_remove(struct p9_fid *fid);
-int p9_client_read(struct p9_fid *fid, char *data, u64 offset, u32 count);
-int p9_client_readn(struct p9_fid *fid, char *data, u64 offset, u32 count);
-int p9_client_write(struct p9_fid *fid, char *data, u64 offset, u32 count);
-int p9_client_uread(struct p9_fid *fid, char __user *data, u64 offset,
-								u32 count);
-int p9_client_uwrite(struct p9_fid *fid, const char __user *data, u64 offset,
-								u32 count);
-struct p9_stat *p9_client_stat(struct p9_fid *fid);
+int p9_client_read(struct p9_fid *fid, char *data, char __user *udata,
+							u64 offset, u32 count);
+int p9_client_write(struct p9_fid *fid, char *data, const char __user *udata,
+							u64 offset, u32 count);
+struct p9_wstat *p9_client_stat(struct p9_fid *fid);
 int p9_client_wstat(struct p9_fid *fid, struct p9_wstat *wst);
-struct p9_stat *p9_client_dirread(struct p9_fid *fid, u64 offset);
+
+struct p9_req_t *p9_tag_lookup(struct p9_client *, u16);
+void p9_client_cb(struct p9_client *c, struct p9_req_t *req);
+
+int p9_parse_header(struct p9_fcall *, int32_t *, int8_t *, int16_t *, int);
+int p9stat_read(char *, int, struct p9_wstat *, int);
+void p9stat_free(struct p9_wstat *);
+
 
 #endif /* NET_9P_CLIENT_H */
diff --git a/include/net/9p/transport.h b/include/net/9p/transport.h
index 3ca737120a90..6d5886efb102 100644
--- a/include/net/9p/transport.h
+++ b/include/net/9p/transport.h
@@ -26,52 +26,6 @@
 #ifndef NET_9P_TRANSPORT_H
 #define NET_9P_TRANSPORT_H
 
-#include <linux/module.h>
-
-/**
- * enum p9_trans_status - different states of underlying transports
- * @Connected: transport is connected and healthy
- * @Disconnected: transport has been disconnected
- * @Hung: transport is connected by wedged
- *
- * This enumeration details the various states a transport
- * instatiation can be in.
- */
-
-enum p9_trans_status {
-	Connected,
-	Disconnected,
-	Hung,
-};
-
-/**
- * struct p9_trans - per-transport state and API
- * @status: transport &p9_trans_status
- * @msize: negotiated maximum packet size (duplicate from client)
- * @extended: negotiated protocol extensions (duplicate from client)
- * @priv: transport private data
- * @close: member function to disconnect and close the transport
- * @rpc: member function to issue a request to the transport
- *
- * This is the basic API for a transport instance.  It is used as
- * a handle by the client to issue requests.  This interface is currently
- * in flux during reorganization.
- *
- * Bugs: there is lots of duplicated data here and its not clear that
- * the member functions need to be per-instance versus per transport
- * module.
- */
-
-struct p9_trans {
-	enum p9_trans_status status;
-	int msize;
-	unsigned char extended;
-	void *priv;
-	void (*close) (struct p9_trans *);
-	int (*rpc) (struct p9_trans *t, struct p9_fcall *tc,
-							struct p9_fcall **rc);
-};
-
 /**
  * struct p9_trans_module - transport module interface
  * @list: used to maintain a list of currently available transports
@@ -79,12 +33,14 @@ struct p9_trans {
  * @maxsize: transport provided maximum packet size
  * @def: set if this transport should be considered the default
  * @create: member function to create a new connection on this transport
+ * @request: member function to issue a request to the transport
+ * @cancel: member function to cancel a request (if it hasn't been sent)
  *
  * This is the basic API for a transport module which is registered by the
  * transport module with the 9P core network module and used by the client
  * to instantiate a new connection on a transport.
  *
- * Bugs: the transport module list isn't protected.
+ * BUGS: the transport module list isn't protected.
  */
 
 struct p9_trans_module {
@@ -92,8 +48,11 @@ struct p9_trans_module {
 	char *name;		/* name of transport */
 	int maxsize;		/* max message size of transport */
 	int def;		/* this transport should be default */
-	struct p9_trans * (*create)(const char *, char *, int, unsigned char);
 	struct module *owner;
+	int (*create)(struct p9_client *, const char *, char *);
+	void (*close) (struct p9_client *);
+	int (*request) (struct p9_client *, struct p9_req_t *req);
+	int (*cancel) (struct p9_client *, struct p9_req_t *req);
 };
 
 void v9fs_register_trans(struct p9_trans_module *m);
diff --git a/include/net/af_unix.h b/include/net/af_unix.h
index 7dd29b7e461d..1614d78c60ed 100644
--- a/include/net/af_unix.h
+++ b/include/net/af_unix.h
@@ -9,6 +9,7 @@
 extern void unix_inflight(struct file *fp);
 extern void unix_notinflight(struct file *fp);
 extern void unix_gc(void);
+extern void wait_for_unix_gc(void);
 
 #define UNIX_HASH_SIZE	256
 
@@ -54,6 +55,7 @@ struct unix_sock {
         atomic_long_t           inflight;
         spinlock_t		lock;
 	unsigned int		gc_candidate : 1;
+	unsigned int		gc_maybe_cycle : 1;
         wait_queue_head_t       peer_wait;
 };
 #define unix_sk(__sk) ((struct unix_sock *)__sk)
diff --git a/include/net/bluetooth/bluetooth.h b/include/net/bluetooth/bluetooth.h
index 6f8418bf4241..a04f8463ac7e 100644
--- a/include/net/bluetooth/bluetooth.h
+++ b/include/net/bluetooth/bluetooth.h
@@ -54,8 +54,8 @@
 #define SOL_RFCOMM	18
 
 #define BT_INFO(fmt, arg...) printk(KERN_INFO "Bluetooth: " fmt "\n" , ## arg)
-#define BT_DBG(fmt, arg...)  printk(KERN_INFO "%s: " fmt "\n" , __FUNCTION__ , ## arg)
-#define BT_ERR(fmt, arg...)  printk(KERN_ERR  "%s: " fmt "\n" , __FUNCTION__ , ## arg)
+#define BT_ERR(fmt, arg...)  printk(KERN_ERR "%s: " fmt "\n" , __func__ , ## arg)
+#define BT_DBG(fmt, arg...)  pr_debug("%s: " fmt "\n" , __func__ , ## arg)
 
 /* Connection and socket states */
 enum {
diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h
index 3cc294919312..3645139e68c7 100644
--- a/include/net/bluetooth/hci.h
+++ b/include/net/bluetooth/hci.h
@@ -54,7 +54,7 @@
 
 /* HCI device quirks */
 enum {
-	HCI_QUIRK_RESET_ON_INIT,
+	HCI_QUIRK_NO_RESET,
 	HCI_QUIRK_RAW_DEVICE,
 	HCI_QUIRK_FIXUP_BUFFER_SIZE
 };
diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h
index 0e85ec39b638..23c0ab74ded6 100644
--- a/include/net/cfg80211.h
+++ b/include/net/cfg80211.h
@@ -5,6 +5,8 @@
 #include <linux/skbuff.h>
 #include <linux/nl80211.h>
 #include <net/genetlink.h>
+/* remove once we remove the wext stuff */
+#include <net/iw_handler.h>
 
 /*
  * 802.11 configuration in-kernel interface
@@ -167,6 +169,9 @@ struct station_parameters {
  * @STATION_INFO_LLID: @llid filled
  * @STATION_INFO_PLID: @plid filled
  * @STATION_INFO_PLINK_STATE: @plink_state filled
+ * @STATION_INFO_SIGNAL: @signal filled
+ * @STATION_INFO_TX_BITRATE: @tx_bitrate fields are filled
+ *  (tx_bitrate, tx_bitrate_flags and tx_bitrate_mcs)
  */
 enum station_info_flags {
 	STATION_INFO_INACTIVE_TIME	= 1<<0,
@@ -175,6 +180,39 @@ enum station_info_flags {
 	STATION_INFO_LLID		= 1<<3,
 	STATION_INFO_PLID		= 1<<4,
 	STATION_INFO_PLINK_STATE	= 1<<5,
+	STATION_INFO_SIGNAL		= 1<<6,
+	STATION_INFO_TX_BITRATE		= 1<<7,
+};
+
+/**
+ * enum station_info_rate_flags - bitrate info flags
+ *
+ * Used by the driver to indicate the specific rate transmission
+ * type for 802.11n transmissions.
+ *
+ * @RATE_INFO_FLAGS_MCS: @tx_bitrate_mcs filled
+ * @RATE_INFO_FLAGS_40_MHZ_WIDTH: 40 Mhz width transmission
+ * @RATE_INFO_FLAGS_SHORT_GI: 400ns guard interval
+ */
+enum rate_info_flags {
+	RATE_INFO_FLAGS_MCS		= 1<<0,
+	RATE_INFO_FLAGS_40_MHZ_WIDTH	= 1<<1,
+	RATE_INFO_FLAGS_SHORT_GI	= 1<<2,
+};
+
+/**
+ * struct rate_info - bitrate information
+ *
+ * Information about a receiving or transmitting bitrate
+ *
+ * @flags: bitflag of flags from &enum rate_info_flags
+ * @mcs: mcs index if struct describes a 802.11n bitrate
+ * @legacy: bitrate in 100kbit/s for 802.11abg
+ */
+struct rate_info {
+	u8 flags;
+	u8 mcs;
+	u16 legacy;
 };
 
 /**
@@ -189,6 +227,8 @@ enum station_info_flags {
  * @llid: mesh local link id
  * @plid: mesh peer link id
  * @plink_state: mesh peer link state
+ * @signal: signal strength of last received packet in dBm
+ * @txrate: current unicast bitrate to this station
  */
 struct station_info {
 	u32 filled;
@@ -198,6 +238,8 @@ struct station_info {
 	u16 llid;
 	u16 plid;
 	u8 plink_state;
+	s8 signal;
+	struct rate_info txrate;
 };
 
 /**
@@ -280,11 +322,16 @@ struct mpath_info {
  *	(0 = no, 1 = yes, -1 = do not change)
  * @use_short_slot_time: Whether the use of short slot time is allowed
  *	(0 = no, 1 = yes, -1 = do not change)
+ * @basic_rates: basic rates in IEEE 802.11 format
+ *	(or NULL for no change)
+ * @basic_rates_len: number of basic rates
  */
 struct bss_parameters {
 	int use_cts_prot;
 	int use_short_preamble;
 	int use_short_slot_time;
+	u8 *basic_rates;
+	u8 basic_rates_len;
 };
 
 /**
@@ -331,25 +378,65 @@ struct ieee80211_regdomain {
 	struct ieee80211_reg_rule reg_rules[];
 };
 
-#define MHZ_TO_KHZ(freq) (freq * 1000)
-#define KHZ_TO_MHZ(freq) (freq / 1000)
-#define DBI_TO_MBI(gain) (gain * 100)
-#define MBI_TO_DBI(gain) (gain / 100)
-#define DBM_TO_MBM(gain) (gain * 100)
-#define MBM_TO_DBM(gain) (gain / 100)
+#define MHZ_TO_KHZ(freq) ((freq) * 1000)
+#define KHZ_TO_MHZ(freq) ((freq) / 1000)
+#define DBI_TO_MBI(gain) ((gain) * 100)
+#define MBI_TO_DBI(gain) ((gain) / 100)
+#define DBM_TO_MBM(gain) ((gain) * 100)
+#define MBM_TO_DBM(gain) ((gain) / 100)
 
 #define REG_RULE(start, end, bw, gain, eirp, reg_flags) { \
-	.freq_range.start_freq_khz = (start) * 1000, \
-	.freq_range.end_freq_khz = (end) * 1000, \
-	.freq_range.max_bandwidth_khz = (bw) * 1000, \
-	.power_rule.max_antenna_gain = (gain) * 100, \
-	.power_rule.max_eirp = (eirp) * 100, \
+	.freq_range.start_freq_khz = MHZ_TO_KHZ(start), \
+	.freq_range.end_freq_khz = MHZ_TO_KHZ(end), \
+	.freq_range.max_bandwidth_khz = MHZ_TO_KHZ(bw), \
+	.power_rule.max_antenna_gain = DBI_TO_MBI(gain), \
+	.power_rule.max_eirp = DBM_TO_MBM(eirp), \
 	.flags = reg_flags, \
 	}
 
+struct mesh_config {
+	/* Timeouts in ms */
+	/* Mesh plink management parameters */
+	u16 dot11MeshRetryTimeout;
+	u16 dot11MeshConfirmTimeout;
+	u16 dot11MeshHoldingTimeout;
+	u16 dot11MeshMaxPeerLinks;
+	u8  dot11MeshMaxRetries;
+	u8  dot11MeshTTL;
+	bool auto_open_plinks;
+	/* HWMP parameters */
+	u8  dot11MeshHWMPmaxPREQretries;
+	u32 path_refresh_time;
+	u16 min_discovery_timeout;
+	u32 dot11MeshHWMPactivePathTimeout;
+	u16 dot11MeshHWMPpreqMinInterval;
+	u16 dot11MeshHWMPnetDiameterTraversalTime;
+};
+
+/**
+ * struct ieee80211_txq_params - TX queue parameters
+ * @queue: TX queue identifier (NL80211_TXQ_Q_*)
+ * @txop: Maximum burst time in units of 32 usecs, 0 meaning disabled
+ * @cwmin: Minimum contention window [a value of the form 2^n-1 in the range
+ *	1..32767]
+ * @cwmax: Maximum contention window [a value of the form 2^n-1 in the range
+ *	1..32767]
+ * @aifs: Arbitration interframe space [0..255]
+ */
+struct ieee80211_txq_params {
+	enum nl80211_txq_q queue;
+	u16 txop;
+	u16 cwmin;
+	u16 cwmax;
+	u8 aifs;
+};
+
 /* from net/wireless.h */
 struct wiphy;
 
+/* from net/ieee80211.h */
+struct ieee80211_channel;
+
 /**
  * struct cfg80211_ops - backend description for wireless configuration
  *
@@ -397,9 +484,19 @@ struct wiphy;
  *
  * @change_station: Modify a given station.
  *
+ * @get_mesh_params: Put the current mesh parameters into *params
+ *
+ * @set_mesh_params: Set mesh parameters.
+ *	The mask is a bitfield which tells us which parameters to
+ *	set, and which to leave alone.
+ *
  * @set_mesh_cfg: set mesh parameters (by now, just mesh id)
  *
  * @change_bss: Modify parameters for a given BSS.
+ *
+ * @set_txq_params: Set TX queue parameters
+ *
+ * @set_channel: Set channel
  */
 struct cfg80211_ops {
 	int	(*add_virtual_intf)(struct wiphy *wiphy, char *name,
@@ -452,9 +549,30 @@ struct cfg80211_ops {
 	int	(*dump_mpath)(struct wiphy *wiphy, struct net_device *dev,
 			       int idx, u8 *dst, u8 *next_hop,
 			       struct mpath_info *pinfo);
-
+	int	(*get_mesh_params)(struct wiphy *wiphy,
+				struct net_device *dev,
+				struct mesh_config *conf);
+	int	(*set_mesh_params)(struct wiphy *wiphy,
+				struct net_device *dev,
+				const struct mesh_config *nconf, u32 mask);
 	int	(*change_bss)(struct wiphy *wiphy, struct net_device *dev,
 			      struct bss_parameters *params);
+
+	int	(*set_txq_params)(struct wiphy *wiphy,
+				  struct ieee80211_txq_params *params);
+
+	int	(*set_channel)(struct wiphy *wiphy,
+			       struct ieee80211_channel *chan,
+			       enum nl80211_channel_type channel_type);
 };
 
+/* temporary wext handlers */
+int cfg80211_wext_giwname(struct net_device *dev,
+			  struct iw_request_info *info,
+			  char *name, char *extra);
+int cfg80211_wext_siwmode(struct net_device *dev, struct iw_request_info *info,
+			  u32 *mode, char *extra);
+int cfg80211_wext_giwmode(struct net_device *dev, struct iw_request_info *info,
+			  u32 *mode, char *extra);
+
 #endif /* __NET_CFG80211_H */
diff --git a/include/net/checksum.h b/include/net/checksum.h
index 07602b7fa218..ba55d8b8c87c 100644
--- a/include/net/checksum.h
+++ b/include/net/checksum.h
@@ -98,7 +98,7 @@ static inline void csum_replace4(__sum16 *sum, __be32 from, __be32 to)
 {
 	__be32 diff[] = { ~from, to };
 
-	*sum = csum_fold(csum_partial((char *)diff, sizeof(diff), ~csum_unfold(*sum)));
+	*sum = csum_fold(csum_partial(diff, sizeof(diff), ~csum_unfold(*sum)));
 }
 
 static inline void csum_replace2(__sum16 *sum, __be16 from, __be16 to)
diff --git a/include/net/dcbnl.h b/include/net/dcbnl.h
new file mode 100644
index 000000000000..775cfc8055be
--- /dev/null
+++ b/include/net/dcbnl.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2008, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * Author: Lucy Liu <lucy.liu@intel.com>
+ */
+
+#ifndef __NET_DCBNL_H__
+#define __NET_DCBNL_H__
+
+/*
+ * Ops struct for the netlink callbacks.  Used by DCB-enabled drivers through
+ * the netdevice struct.
+ */
+struct dcbnl_rtnl_ops {
+	u8   (*getstate)(struct net_device *);
+	u8   (*setstate)(struct net_device *, u8);
+	void (*getpermhwaddr)(struct net_device *, u8 *);
+	void (*setpgtccfgtx)(struct net_device *, int, u8, u8, u8, u8);
+	void (*setpgbwgcfgtx)(struct net_device *, int, u8);
+	void (*setpgtccfgrx)(struct net_device *, int, u8, u8, u8, u8);
+	void (*setpgbwgcfgrx)(struct net_device *, int, u8);
+	void (*getpgtccfgtx)(struct net_device *, int, u8 *, u8 *, u8 *, u8 *);
+	void (*getpgbwgcfgtx)(struct net_device *, int, u8 *);
+	void (*getpgtccfgrx)(struct net_device *, int, u8 *, u8 *, u8 *, u8 *);
+	void (*getpgbwgcfgrx)(struct net_device *, int, u8 *);
+	void (*setpfccfg)(struct net_device *, int, u8);
+	void (*getpfccfg)(struct net_device *, int, u8 *);
+	u8   (*setall)(struct net_device *);
+	u8   (*getcap)(struct net_device *, int, u8 *);
+	u8   (*getnumtcs)(struct net_device *, int, u8 *);
+	u8   (*setnumtcs)(struct net_device *, int, u8);
+	u8   (*getpfcstate)(struct net_device *);
+	void (*setpfcstate)(struct net_device *, u8);
+	void (*getbcncfg)(struct net_device *, int, u32 *);
+	void (*setbcncfg)(struct net_device *, int, u32);
+	void (*getbcnrp)(struct net_device *, int, u8 *);
+	void (*setbcnrp)(struct net_device *, int, u8);
+};
+
+#endif /* __NET_DCBNL_H__ */
diff --git a/include/net/dn.h b/include/net/dn.h
index 627778384c84..e5469f7b67a3 100644
--- a/include/net/dn.h
+++ b/include/net/dn.h
@@ -4,9 +4,7 @@
 #include <linux/dn.h>
 #include <net/sock.h>
 #include <asm/byteorder.h>
-
-#define dn_ntohs(x) le16_to_cpu(x)
-#define dn_htons(x) cpu_to_le16(x)
+#include <asm/unaligned.h>
 
 struct dn_scp                                   /* Session Control Port */
 {
@@ -175,7 +173,7 @@ struct dn_skb_cb {
 
 static inline __le16 dn_eth2dn(unsigned char *ethaddr)
 {
-	return dn_htons(ethaddr[4] | (ethaddr[5] << 8));
+	return get_unaligned((__le16 *)(ethaddr + 4));
 }
 
 static inline __le16 dn_saddr2dn(struct sockaddr_dn *saddr)
@@ -185,7 +183,7 @@ static inline __le16 dn_saddr2dn(struct sockaddr_dn *saddr)
 
 static inline void dn_dn2eth(unsigned char *ethaddr, __le16 addr)
 {
-	__u16 a = dn_ntohs(addr);
+	__u16 a = le16_to_cpu(addr);
 	ethaddr[0] = 0xAA;
 	ethaddr[1] = 0x00;
 	ethaddr[2] = 0x04;
diff --git a/include/net/dn_fib.h b/include/net/dn_fib.h
index 30125119c950..c378be7bf960 100644
--- a/include/net/dn_fib.h
+++ b/include/net/dn_fib.h
@@ -181,9 +181,9 @@ static inline void dn_fib_res_put(struct dn_fib_res *res)
 
 static inline __le16 dnet_make_mask(int n)
 {
-        if (n)
-                return dn_htons(~((1<<(16-n))-1));
-        return 0;
+	if (n)
+		return cpu_to_le16(~((1 << (16 - n)) - 1));
+	return cpu_to_le16(0);
 }
 
 #endif /* _NET_DN_FIB_H */
diff --git a/include/net/dst.h b/include/net/dst.h
index 8a8b71e5f3f1..6be3b082a070 100644
--- a/include/net/dst.h
+++ b/include/net/dst.h
@@ -59,8 +59,11 @@ struct dst_entry
 
 	struct neighbour	*neighbour;
 	struct hh_cache		*hh;
+#ifdef CONFIG_XFRM
 	struct xfrm_state	*xfrm;
-
+#else
+	void			*__pad1;
+#endif
 	int			(*input)(struct sk_buff*);
 	int			(*output)(struct sk_buff*);
 
@@ -70,8 +73,20 @@ struct dst_entry
 
 #ifdef CONFIG_NET_CLS_ROUTE
 	__u32			tclassid;
+#else
+	__u32			__pad2;
 #endif
 
+
+	/*
+	 * Align __refcnt to a 64 bytes alignment
+	 * (L1_CACHE_SIZE would be too much)
+	 */
+#ifdef CONFIG_64BIT
+	long			__pad_to_align_refcnt[2];
+#else
+	long			__pad_to_align_refcnt[1];
+#endif
 	/*
 	 * __refcnt wants to be on a different cache line from
 	 * input/output/ops or performance tanks badly
@@ -103,7 +118,6 @@ struct dst_ops
 	void			(*link_failure)(struct sk_buff *);
 	void			(*update_pmtu)(struct dst_entry *dst, u32 mtu);
 	int			(*local_out)(struct sk_buff *skb);
-	int			entry_size;
 
 	atomic_t		entries;
 	struct kmem_cache 		*kmem_cachep;
@@ -157,6 +171,11 @@ dst_metric_locked(struct dst_entry *dst, int metric)
 
 static inline void dst_hold(struct dst_entry * dst)
 {
+	/*
+	 * If your kernel compilation stops here, please check
+	 * __pad_to_align_refcnt declaration in struct dst_entry
+	 */
+	BUILD_BUG_ON(offsetof(struct dst_entry, __refcnt) & 63);
 	atomic_inc(&dst->__refcnt);
 }
 
@@ -272,21 +291,21 @@ enum {
 
 struct flowi;
 #ifndef CONFIG_XFRM
-static inline int xfrm_lookup(struct dst_entry **dst_p, struct flowi *fl,
-		       struct sock *sk, int flags)
+static inline int xfrm_lookup(struct net *net, struct dst_entry **dst_p,
+			      struct flowi *fl, struct sock *sk, int flags)
 {
 	return 0;
 } 
-static inline int __xfrm_lookup(struct dst_entry **dst_p, struct flowi *fl,
-				struct sock *sk, int flags)
+static inline int __xfrm_lookup(struct net *net, struct dst_entry **dst_p,
+				struct flowi *fl, struct sock *sk, int flags)
 {
 	return 0;
 }
 #else
-extern int xfrm_lookup(struct dst_entry **dst_p, struct flowi *fl,
-		       struct sock *sk, int flags);
-extern int __xfrm_lookup(struct dst_entry **dst_p, struct flowi *fl,
-			 struct sock *sk, int flags);
+extern int xfrm_lookup(struct net *net, struct dst_entry **dst_p,
+		       struct flowi *fl, struct sock *sk, int flags);
+extern int __xfrm_lookup(struct net *net, struct dst_entry **dst_p,
+			 struct flowi *fl, struct sock *sk, int flags);
 #endif
 #endif
 
diff --git a/include/net/flow.h b/include/net/flow.h
index b45a5e4fcadd..809970b7dfee 100644
--- a/include/net/flow.h
+++ b/include/net/flow.h
@@ -84,12 +84,13 @@ struct flowi {
 #define FLOW_DIR_OUT	1
 #define FLOW_DIR_FWD	2
 
+struct net;
 struct sock;
-typedef int (*flow_resolve_t)(struct flowi *key, u16 family, u8 dir,
-			       void **objp, atomic_t **obj_refp);
+typedef int (*flow_resolve_t)(struct net *net, struct flowi *key, u16 family,
+			      u8 dir, void **objp, atomic_t **obj_refp);
 
-extern void *flow_cache_lookup(struct flowi *key, u16 family, u8 dir,
-	 		       flow_resolve_t resolver);
+extern void *flow_cache_lookup(struct net *net, struct flowi *key, u16 family,
+			       u8 dir, flow_resolve_t resolver);
 extern void flow_cache_flush(void);
 extern atomic_t flow_cache_genid;
 
diff --git a/include/net/gen_stats.h b/include/net/gen_stats.h
index 8cd8185fa2ed..d136b5240ef2 100644
--- a/include/net/gen_stats.h
+++ b/include/net/gen_stats.h
@@ -45,5 +45,6 @@ extern void gen_kill_estimator(struct gnet_stats_basic *bstats,
 extern int gen_replace_estimator(struct gnet_stats_basic *bstats,
 				 struct gnet_stats_rate_est *rate_est,
 				 spinlock_t *stats_lock, struct nlattr *opt);
-
+extern bool gen_estimator_active(const struct gnet_stats_basic *bstats,
+				 const struct gnet_stats_rate_est *rate_est);
 #endif
diff --git a/include/net/ieee80211.h b/include/net/ieee80211.h
index 6048579d0b24..adb7cf31f781 100644
--- a/include/net/ieee80211.h
+++ b/include/net/ieee80211.h
@@ -28,6 +28,9 @@
 #include <linux/if_ether.h>	/* ETH_ALEN */
 #include <linux/kernel.h>	/* ARRAY_SIZE */
 #include <linux/wireless.h>
+#include <linux/ieee80211.h>
+
+#include <net/lib80211.h>
 
 #define IEEE80211_VERSION "git-1.1.13"
 
@@ -114,7 +117,7 @@ extern u32 ieee80211_debug_level;
 #define IEEE80211_DEBUG(level, fmt, args...) \
 do { if (ieee80211_debug_level & (level)) \
   printk(KERN_DEBUG "ieee80211: %c %s " fmt, \
-         in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
+         in_interrupt() ? 'I' : 'U', __func__ , ## args); } while (0)
 static inline bool ieee80211_ratelimit_debug(u32 level)
 {
 	return (ieee80211_debug_level & level) && net_ratelimit();
@@ -127,10 +130,6 @@ static inline bool ieee80211_ratelimit_debug(u32 level)
 }
 #endif				/* CONFIG_IEEE80211_DEBUG */
 
-/* escape_essid() is intended to be used in debug (and possibly error)
- * messages. It should never be used for passing essid to user space. */
-const char *escape_essid(const char *essid, u8 essid_len);
-
 /*
  * To use the debug system:
  *
@@ -218,94 +217,6 @@ struct ieee80211_snap_hdr {
 #define WLAN_GET_SEQ_FRAG(seq) ((seq) & IEEE80211_SCTL_FRAG)
 #define WLAN_GET_SEQ_SEQ(seq)  (((seq) & IEEE80211_SCTL_SEQ) >> 4)
 
-/* Authentication algorithms */
-#define WLAN_AUTH_OPEN 0
-#define WLAN_AUTH_SHARED_KEY 1
-#define WLAN_AUTH_LEAP 2
-
-#define WLAN_AUTH_CHALLENGE_LEN 128
-
-#define WLAN_CAPABILITY_ESS (1<<0)
-#define WLAN_CAPABILITY_IBSS (1<<1)
-#define WLAN_CAPABILITY_CF_POLLABLE (1<<2)
-#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3)
-#define WLAN_CAPABILITY_PRIVACY (1<<4)
-#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5)
-#define WLAN_CAPABILITY_PBCC (1<<6)
-#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7)
-#define WLAN_CAPABILITY_SPECTRUM_MGMT (1<<8)
-#define WLAN_CAPABILITY_QOS (1<<9)
-#define WLAN_CAPABILITY_SHORT_SLOT_TIME (1<<10)
-#define WLAN_CAPABILITY_DSSS_OFDM (1<<13)
-
-/* 802.11g ERP information element */
-#define WLAN_ERP_NON_ERP_PRESENT (1<<0)
-#define WLAN_ERP_USE_PROTECTION (1<<1)
-#define WLAN_ERP_BARKER_PREAMBLE (1<<2)
-
-/* Status codes */
-enum ieee80211_statuscode {
-	WLAN_STATUS_SUCCESS = 0,
-	WLAN_STATUS_UNSPECIFIED_FAILURE = 1,
-	WLAN_STATUS_CAPS_UNSUPPORTED = 10,
-	WLAN_STATUS_REASSOC_NO_ASSOC = 11,
-	WLAN_STATUS_ASSOC_DENIED_UNSPEC = 12,
-	WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG = 13,
-	WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION = 14,
-	WLAN_STATUS_CHALLENGE_FAIL = 15,
-	WLAN_STATUS_AUTH_TIMEOUT = 16,
-	WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA = 17,
-	WLAN_STATUS_ASSOC_DENIED_RATES = 18,
-	/* 802.11b */
-	WLAN_STATUS_ASSOC_DENIED_NOSHORTPREAMBLE = 19,
-	WLAN_STATUS_ASSOC_DENIED_NOPBCC = 20,
-	WLAN_STATUS_ASSOC_DENIED_NOAGILITY = 21,
-	/* 802.11h */
-	WLAN_STATUS_ASSOC_DENIED_NOSPECTRUM = 22,
-	WLAN_STATUS_ASSOC_REJECTED_BAD_POWER = 23,
-	WLAN_STATUS_ASSOC_REJECTED_BAD_SUPP_CHAN = 24,
-	/* 802.11g */
-	WLAN_STATUS_ASSOC_DENIED_NOSHORTTIME = 25,
-	WLAN_STATUS_ASSOC_DENIED_NODSSSOFDM = 26,
-	/* 802.11i */
-	WLAN_STATUS_INVALID_IE = 40,
-	WLAN_STATUS_INVALID_GROUP_CIPHER = 41,
-	WLAN_STATUS_INVALID_PAIRWISE_CIPHER = 42,
-	WLAN_STATUS_INVALID_AKMP = 43,
-	WLAN_STATUS_UNSUPP_RSN_VERSION = 44,
-	WLAN_STATUS_INVALID_RSN_IE_CAP = 45,
-	WLAN_STATUS_CIPHER_SUITE_REJECTED = 46,
-};
-
-/* Reason codes */
-enum ieee80211_reasoncode {
-	WLAN_REASON_UNSPECIFIED = 1,
-	WLAN_REASON_PREV_AUTH_NOT_VALID = 2,
-	WLAN_REASON_DEAUTH_LEAVING = 3,
-	WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY = 4,
-	WLAN_REASON_DISASSOC_AP_BUSY = 5,
-	WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA = 6,
-	WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA = 7,
-	WLAN_REASON_DISASSOC_STA_HAS_LEFT = 8,
-	WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH = 9,
-	/* 802.11h */
-	WLAN_REASON_DISASSOC_BAD_POWER = 10,
-	WLAN_REASON_DISASSOC_BAD_SUPP_CHAN = 11,
-	/* 802.11i */
-	WLAN_REASON_INVALID_IE = 13,
-	WLAN_REASON_MIC_FAILURE = 14,
-	WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT = 15,
-	WLAN_REASON_GROUP_KEY_HANDSHAKE_TIMEOUT = 16,
-	WLAN_REASON_IE_DIFFERENT = 17,
-	WLAN_REASON_INVALID_GROUP_CIPHER = 18,
-	WLAN_REASON_INVALID_PAIRWISE_CIPHER = 19,
-	WLAN_REASON_INVALID_AKMP = 20,
-	WLAN_REASON_UNSUPP_RSN_VERSION = 21,
-	WLAN_REASON_INVALID_RSN_IE_CAP = 22,
-	WLAN_REASON_IEEE8021X_FAILED = 23,
-	WLAN_REASON_CIPHER_SUITE_REJECTED = 24,
-};
-
 /* Action categories - 802.11h */
 enum ieee80211_actioncategories {
 	WLAN_ACTION_SPECTRUM_MGMT = 0,
@@ -446,8 +357,6 @@ struct ieee80211_stats {
 
 struct ieee80211_device;
 
-#include "ieee80211_crypt.h"
-
 #define SEC_KEY_1		(1<<0)
 #define SEC_KEY_2		(1<<1)
 #define SEC_KEY_3		(1<<2)
@@ -476,9 +385,8 @@ struct ieee80211_device;
 #define SCM_TEMPORAL_KEY_LENGTH	16
 
 struct ieee80211_security {
-	u16 active_key:2,
-	    enabled:1,
-	    auth_mode:2, auth_algo:4, unicast_uses_group:1, encrypt:1;
+	u16 active_key:2, enabled:1, unicast_uses_group:1, encrypt:1;
+	u8 auth_mode;
 	u8 encode_alg[WEP_KEYS];
 	u8 key_sizes[WEP_KEYS];
 	u8 keys[WEP_KEYS][SCM_KEY_LEN];
@@ -534,15 +442,6 @@ enum ieee80211_mfie {
 	MFIE_TYPE_QOS_PARAMETER = 222,
 };
 
-/* Minimal header; can be used for passing 802.11 frames with sufficient
- * information to determine what type of underlying data type is actually
- * stored in the data. */
-struct ieee80211_hdr {
-	__le16 frame_ctl;
-	__le16 duration_id;
-	u8 payload[0];
-} __attribute__ ((packed));
-
 struct ieee80211_hdr_1addr {
 	__le16 frame_ctl;
 	__le16 duration_id;
@@ -590,18 +489,6 @@ struct ieee80211_hdr_3addrqos {
 	__le16 qos_ctl;
 } __attribute__ ((packed));
 
-struct ieee80211_hdr_4addrqos {
-	__le16 frame_ctl;
-	__le16 duration_id;
-	u8 addr1[ETH_ALEN];
-	u8 addr2[ETH_ALEN];
-	u8 addr3[ETH_ALEN];
-	__le16 seq_ctl;
-	u8 addr4[ETH_ALEN];
-	u8 payload[0];
-	__le16 qos_ctl;
-} __attribute__ ((packed));
-
 struct ieee80211_info_element {
 	u8 id;
 	u8 len;
@@ -733,7 +620,6 @@ struct ieee80211_txb {
 
 #define MAX_WPA_IE_LEN 64
 
-#define NETWORK_EMPTY_ESSID    (1<<0)
 #define NETWORK_HAS_OFDM       (1<<1)
 #define NETWORK_HAS_CCK        (1<<2)
 
@@ -1050,11 +936,7 @@ struct ieee80211_device {
 	size_t wpa_ie_len;
 	u8 *wpa_ie;
 
-	struct list_head crypt_deinit_list;
-	struct ieee80211_crypt_data *crypt[WEP_KEYS];
-	int tx_keyidx;		/* default TX key index (crypt[tx_keyidx]) */
-	struct timer_list crypt_deinit_timer;
-	int crypt_quiesced;
+	struct lib80211_crypt_info crypt_info;
 
 	int bcrx_sta_key;	/* use individual keys to override default keys even
 				 * with RX of broad/multicast frames */
@@ -1135,22 +1017,6 @@ static inline void *ieee80211_priv(struct net_device *dev)
 	return ((struct ieee80211_device *)netdev_priv(dev))->priv;
 }
 
-static inline int ieee80211_is_empty_essid(const char *essid, int essid_len)
-{
-	/* Single white space is for Linksys APs */
-	if (essid_len == 1 && essid[0] == ' ')
-		return 1;
-
-	/* Otherwise, if the entire essid is 0, we assume it is hidden */
-	while (essid_len) {
-		essid_len--;
-		if (essid[essid_len] != '\0')
-			return 0;
-	}
-
-	return 1;
-}
-
 static inline int ieee80211_is_valid_mode(struct ieee80211_device *ieee,
 					  int mode)
 {
@@ -1208,7 +1074,7 @@ static inline int ieee80211_get_hdrlen(u16 fc)
 
 static inline u8 *ieee80211_get_payload(struct ieee80211_hdr *hdr)
 {
-	switch (ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_ctl))) {
+	switch (ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_control))) {
 	case IEEE80211_1ADDR_LEN:
 		return ((struct ieee80211_hdr_1addr *)hdr)->payload;
 	case IEEE80211_2ADDR_LEN:
diff --git a/include/net/ieee80211_radiotap.h b/include/net/ieee80211_radiotap.h
index d364fd594ea4..384698cb773a 100644
--- a/include/net/ieee80211_radiotap.h
+++ b/include/net/ieee80211_radiotap.h
@@ -1,7 +1,4 @@
-/* $FreeBSD: src/sys/net80211/ieee80211_radiotap.h,v 1.5 2005/01/22 20:12:05 sam Exp $ */
-/* $NetBSD: ieee80211_radiotap.h,v 1.11 2005/06/22 06:16:02 dyoung Exp $ */
-
-/*-
+/*
  * Copyright (c) 2003, 2004 David Young.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -42,8 +39,6 @@
 #include <linux/kernel.h>
 #include <asm/unaligned.h>
 
-/* Radiotap header version (from official NetBSD feed) */
-#define IEEE80211RADIOTAP_VERSION	"1.5"
 /* Base version of the radiotap packet header data */
 #define PKTHDR_RADIOTAP_VERSION		0
 
@@ -62,12 +57,8 @@
  * readers.
  */
 
-/* XXX tcpdump/libpcap do not tolerate variable-length headers,
- * yet, so we pad every radiotap header to 64 bytes. Ugh.
- */
-#define IEEE80211_RADIOTAP_HDRLEN	64
-
-/* The radio capture header precedes the 802.11 header.
+/*
+ * The radio capture header precedes the 802.11 header.
  * All data in the header is little endian on all platforms.
  */
 struct ieee80211_radiotap_header {
diff --git a/include/net/inet_hashtables.h b/include/net/inet_hashtables.h
index 5cc182f9ecae..f44bb5c77a70 100644
--- a/include/net/inet_hashtables.h
+++ b/include/net/inet_hashtables.h
@@ -41,8 +41,8 @@
  * I'll experiment with dynamic table growth later.
  */
 struct inet_ehash_bucket {
-	struct hlist_head chain;
-	struct hlist_head twchain;
+	struct hlist_nulls_head chain;
+	struct hlist_nulls_head twchain;
 };
 
 /* There are a few simple rules, which allow for local port reuse by
@@ -77,13 +77,20 @@ struct inet_ehash_bucket {
  * ports are created in O(1) time?  I thought so. ;-)	-DaveM
  */
 struct inet_bind_bucket {
+#ifdef CONFIG_NET_NS
 	struct net		*ib_net;
+#endif
 	unsigned short		port;
 	signed short		fastreuse;
 	struct hlist_node	node;
 	struct hlist_head	owners;
 };
 
+static inline struct net *ib_net(struct inet_bind_bucket *ib)
+{
+	return read_pnet(&ib->ib_net);
+}
+
 #define inet_bind_bucket_for_each(tb, node, head) \
 	hlist_for_each_entry(tb, node, head, node)
 
@@ -92,6 +99,18 @@ struct inet_bind_hashbucket {
 	struct hlist_head	chain;
 };
 
+/*
+ * Sockets can be hashed in established or listening table
+ * We must use different 'nulls' end-of-chain value for listening
+ * hash table, or we might find a socket that was closed and
+ * reallocated/inserted into established hash table
+ */
+#define LISTENING_NULLS_BASE (1U << 29)
+struct inet_listen_hashbucket {
+	spinlock_t		lock;
+	struct hlist_nulls_head	head;
+};
+
 /* This is for listening sockets, thus all sockets which possess wildcards. */
 #define INET_LHTABLE_SIZE	32	/* Yes, really, this is all you need. */
 
@@ -104,7 +123,7 @@ struct inet_hashinfo {
 	 * TIME_WAIT sockets use a separate chain (twchain).
 	 */
 	struct inet_ehash_bucket	*ehash;
-	rwlock_t			*ehash_locks;
+	spinlock_t			*ehash_locks;
 	unsigned int			ehash_size;
 	unsigned int			ehash_locks_mask;
 
@@ -116,22 +135,21 @@ struct inet_hashinfo {
 	unsigned int			bhash_size;
 	/* Note : 4 bytes padding on 64 bit arches */
 
-	/* All sockets in TCP_LISTEN state will be in here.  This is the only
-	 * table where wildcard'd TCP sockets can exist.  Hash function here
-	 * is just local port number.
-	 */
-	struct hlist_head		listening_hash[INET_LHTABLE_SIZE];
+	struct kmem_cache		*bind_bucket_cachep;
 
 	/* All the above members are written once at bootup and
 	 * never written again _or_ are predominantly read-access.
 	 *
 	 * Now align to a new cache line as all the following members
-	 * are often dirty.
+	 * might be often dirty.
 	 */
-	rwlock_t			lhash_lock ____cacheline_aligned;
-	atomic_t			lhash_users;
-	wait_queue_head_t		lhash_wait;
-	struct kmem_cache			*bind_bucket_cachep;
+	/* All sockets in TCP_LISTEN state will be in here.  This is the only
+	 * table where wildcard'd TCP sockets can exist.  Hash function here
+	 * is just local port number.
+	 */
+	struct inet_listen_hashbucket	listening_hash[INET_LHTABLE_SIZE]
+					____cacheline_aligned_in_smp;
+
 };
 
 static inline struct inet_ehash_bucket *inet_ehash_bucket(
@@ -141,7 +159,7 @@ static inline struct inet_ehash_bucket *inet_ehash_bucket(
 	return &hashinfo->ehash[hash & (hashinfo->ehash_size - 1)];
 }
 
-static inline rwlock_t *inet_ehash_lockp(
+static inline spinlock_t *inet_ehash_lockp(
 	struct inet_hashinfo *hashinfo,
 	unsigned int hash)
 {
@@ -166,16 +184,16 @@ static inline int inet_ehash_locks_alloc(struct inet_hashinfo *hashinfo)
 		size = 4096;
 	if (sizeof(rwlock_t) != 0) {
 #ifdef CONFIG_NUMA
-		if (size * sizeof(rwlock_t) > PAGE_SIZE)
-			hashinfo->ehash_locks = vmalloc(size * sizeof(rwlock_t));
+		if (size * sizeof(spinlock_t) > PAGE_SIZE)
+			hashinfo->ehash_locks = vmalloc(size * sizeof(spinlock_t));
 		else
 #endif
-		hashinfo->ehash_locks =	kmalloc(size * sizeof(rwlock_t),
+		hashinfo->ehash_locks =	kmalloc(size * sizeof(spinlock_t),
 						GFP_KERNEL);
 		if (!hashinfo->ehash_locks)
 			return ENOMEM;
 		for (i = 0; i < size; i++)
-			rwlock_init(&hashinfo->ehash_locks[i]);
+			spin_lock_init(&hashinfo->ehash_locks[i]);
 	}
 	hashinfo->ehash_locks_mask = size - 1;
 	return 0;
@@ -186,7 +204,7 @@ static inline void inet_ehash_locks_free(struct inet_hashinfo *hashinfo)
 	if (hashinfo->ehash_locks) {
 #ifdef CONFIG_NUMA
 		unsigned int size = (hashinfo->ehash_locks_mask + 1) *
-							sizeof(rwlock_t);
+							sizeof(spinlock_t);
 		if (size > PAGE_SIZE)
 			vfree(hashinfo->ehash_locks);
 		else
@@ -229,26 +247,7 @@ extern void __inet_inherit_port(struct sock *sk, struct sock *child);
 
 extern void inet_put_port(struct sock *sk);
 
-extern void inet_listen_wlock(struct inet_hashinfo *hashinfo);
-
-/*
- * - We may sleep inside this lock.
- * - If sleeping is not required (or called from BH),
- *   use plain read_(un)lock(&inet_hashinfo.lhash_lock).
- */
-static inline void inet_listen_lock(struct inet_hashinfo *hashinfo)
-{
-	/* read_lock synchronizes to candidates to writers */
-	read_lock(&hashinfo->lhash_lock);
-	atomic_inc(&hashinfo->lhash_users);
-	read_unlock(&hashinfo->lhash_lock);
-}
-
-static inline void inet_listen_unlock(struct inet_hashinfo *hashinfo)
-{
-	if (atomic_dec_and_test(&hashinfo->lhash_users))
-		wake_up(&hashinfo->lhash_wait);
-}
+void inet_hashinfo_init(struct inet_hashinfo *h);
 
 extern void __inet_hash_nolisten(struct sock *sk);
 extern void inet_hash(struct sock *sk);
@@ -299,25 +298,25 @@ typedef __u64 __bitwise __addrpair;
 				   ((__force __u64)(__be32)(__saddr)));
 #endif /* __BIG_ENDIAN */
 #define INET_MATCH(__sk, __net, __hash, __cookie, __saddr, __daddr, __ports, __dif)\
-	(((__sk)->sk_hash == (__hash)) && sock_net((__sk)) == (__net)	&&	\
+	(((__sk)->sk_hash == (__hash)) && net_eq(sock_net(__sk), (__net)) &&	\
 	 ((*((__addrpair *)&(inet_sk(__sk)->daddr))) == (__cookie))	&&	\
 	 ((*((__portpair *)&(inet_sk(__sk)->dport))) == (__ports))	&&	\
 	 (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif))))
 #define INET_TW_MATCH(__sk, __net, __hash, __cookie, __saddr, __daddr, __ports, __dif)\
-	(((__sk)->sk_hash == (__hash)) && sock_net((__sk)) == (__net)	&&	\
+	(((__sk)->sk_hash == (__hash)) && net_eq(sock_net(__sk), (__net)) &&	\
 	 ((*((__addrpair *)&(inet_twsk(__sk)->tw_daddr))) == (__cookie)) &&	\
 	 ((*((__portpair *)&(inet_twsk(__sk)->tw_dport))) == (__ports)) &&	\
 	 (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif))))
 #else /* 32-bit arch */
 #define INET_ADDR_COOKIE(__name, __saddr, __daddr)
 #define INET_MATCH(__sk, __net, __hash, __cookie, __saddr, __daddr, __ports, __dif)	\
-	(((__sk)->sk_hash == (__hash)) && sock_net((__sk)) == (__net)	&&	\
+	(((__sk)->sk_hash == (__hash)) && net_eq(sock_net(__sk), (__net))	&&	\
 	 (inet_sk(__sk)->daddr		== (__saddr))		&&	\
 	 (inet_sk(__sk)->rcv_saddr	== (__daddr))		&&	\
 	 ((*((__portpair *)&(inet_sk(__sk)->dport))) == (__ports))	&&	\
 	 (!((__sk)->sk_bound_dev_if) || ((__sk)->sk_bound_dev_if == (__dif))))
 #define INET_TW_MATCH(__sk, __net, __hash,__cookie, __saddr, __daddr, __ports, __dif)	\
-	(((__sk)->sk_hash == (__hash)) && sock_net((__sk)) == (__net)	&&	\
+	(((__sk)->sk_hash == (__hash)) && net_eq(sock_net(__sk), (__net))	&&	\
 	 (inet_twsk(__sk)->tw_daddr	== (__saddr))		&&	\
 	 (inet_twsk(__sk)->tw_rcv_saddr	== (__daddr))		&&	\
 	 ((*((__portpair *)&(inet_twsk(__sk)->tw_dport))) == (__ports)) &&	\
diff --git a/include/net/inet_timewait_sock.h b/include/net/inet_timewait_sock.h
index 80e4977631b8..4b8ece22b8e9 100644
--- a/include/net/inet_timewait_sock.h
+++ b/include/net/inet_timewait_sock.h
@@ -110,7 +110,7 @@ struct inet_timewait_sock {
 #define tw_state		__tw_common.skc_state
 #define tw_reuse		__tw_common.skc_reuse
 #define tw_bound_dev_if		__tw_common.skc_bound_dev_if
-#define tw_node			__tw_common.skc_node
+#define tw_node			__tw_common.skc_nulls_node
 #define tw_bind_node		__tw_common.skc_bind_node
 #define tw_refcnt		__tw_common.skc_refcnt
 #define tw_hash			__tw_common.skc_hash
@@ -137,10 +137,10 @@ struct inet_timewait_sock {
 	struct hlist_node	tw_death_node;
 };
 
-static inline void inet_twsk_add_node(struct inet_timewait_sock *tw,
-				      struct hlist_head *list)
+static inline void inet_twsk_add_node_rcu(struct inet_timewait_sock *tw,
+				      struct hlist_nulls_head *list)
 {
-	hlist_add_head(&tw->tw_node, list);
+	hlist_nulls_add_head_rcu(&tw->tw_node, list);
 }
 
 static inline void inet_twsk_add_bind_node(struct inet_timewait_sock *tw,
@@ -175,7 +175,7 @@ static inline int inet_twsk_del_dead_node(struct inet_timewait_sock *tw)
 }
 
 #define inet_twsk_for_each(tw, node, head) \
-	hlist_for_each_entry(tw, node, head, tw_node)
+	hlist_nulls_for_each_entry(tw, node, head, tw_node)
 
 #define inet_twsk_for_each_inmate(tw, node, jail) \
 	hlist_for_each_entry(tw, node, jail, tw_death_node)
diff --git a/include/net/ip.h b/include/net/ip.h
index 1cbccaf0de3f..10868139e656 100644
--- a/include/net/ip.h
+++ b/include/net/ip.h
@@ -110,7 +110,7 @@ extern int		ip_append_data(struct sock *sk,
 						   int odd, struct sk_buff *skb),
 				void *from, int len, int protolen,
 				struct ipcm_cookie *ipc,
-				struct rtable *rt,
+				struct rtable **rt,
 				unsigned int flags);
 extern int		ip_generic_getfrag(void *from, char *to, int offset, int len, int odd, struct sk_buff *skb);
 extern ssize_t		ip_append_page(struct sock *sk, struct page *page,
@@ -187,6 +187,7 @@ extern void inet_get_local_port_range(int *low, int *high);
 extern int sysctl_ip_default_ttl;
 extern int sysctl_ip_nonlocal_bind;
 
+extern struct ctl_path net_core_path[];
 extern struct ctl_path net_ipv4_ctl_path[];
 
 /* From inetpeer.c */
@@ -396,7 +397,7 @@ extern void	ip_local_error(struct sock *sk, int err, __be32 daddr, __be16 dport,
 int ipv4_doint_and_flush(ctl_table *ctl, int write,
 			 struct file* filp, void __user *buffer,
 			 size_t *lenp, loff_t *ppos);
-int ipv4_doint_and_flush_strategy(ctl_table *table, int __user *name, int nlen,
+int ipv4_doint_and_flush_strategy(ctl_table *table,
 				  void __user *oldval, size_t __user *oldlenp,
 				  void __user *newval, size_t newlen);
 #ifdef CONFIG_PROC_FS
diff --git a/include/net/ip_vs.h b/include/net/ip_vs.h
index 0b2071d9326d..ab9b003ab671 100644
--- a/include/net/ip_vs.h
+++ b/include/net/ip_vs.h
@@ -87,12 +87,12 @@ static inline const char *ip_vs_dbg_addr(int af, char *buf, size_t buf_len,
 	int len;
 #ifdef CONFIG_IP_VS_IPV6
 	if (af == AF_INET6)
-		len = snprintf(&buf[*idx], buf_len - *idx, "[" NIP6_FMT "]",
-			       NIP6(addr->in6)) + 1;
+		len = snprintf(&buf[*idx], buf_len - *idx, "[%pI6]",
+			       &addr->in6) + 1;
 	else
 #endif
-		len = snprintf(&buf[*idx], buf_len - *idx, NIPQUAD_FMT,
-			       NIPQUAD(addr->ip)) + 1;
+		len = snprintf(&buf[*idx], buf_len - *idx, "%pI4",
+			       &addr->ip) + 1;
 
 	*idx += len;
 	BUG_ON(*idx > buf_len + 1);
@@ -165,13 +165,13 @@ static inline const char *ip_vs_dbg_addr(int af, char *buf, size_t buf_len,
     do {								\
 	    if (level <= ip_vs_get_debug_level())			\
 		    printk(KERN_DEBUG "Enter: %s, %s line %i\n",	\
-			   __FUNCTION__, __FILE__, __LINE__);		\
+			   __func__, __FILE__, __LINE__);		\
     } while (0)
 #define LeaveFunction(level)                                            \
     do {                                                                \
 	    if (level <= ip_vs_get_debug_level())                       \
 			printk(KERN_DEBUG "Leave: %s, %s line %i\n",    \
-			       __FUNCTION__, __FILE__, __LINE__);       \
+			       __func__, __FILE__, __LINE__);       \
     } while (0)
 #else
 #define EnterFunction(level)   do {} while (0)
@@ -503,9 +503,6 @@ struct ip_vs_scheduler {
 	char			*name;		/* scheduler name */
 	atomic_t		refcnt;		/* reference counter */
 	struct module		*module;	/* THIS_MODULE/NULL */
-#ifdef CONFIG_IP_VS_IPV6
-	int			supports_ipv6;	/* scheduler has IPv6 support */
-#endif
 
 	/* scheduler initializing service */
 	int (*init_service)(struct ip_vs_service *svc);
@@ -916,7 +913,7 @@ static inline __wsum ip_vs_check_diff4(__be32 old, __be32 new, __wsum oldsum)
 {
 	__be32 diff[2] = { ~old, new };
 
-	return csum_partial((char *) diff, sizeof(diff), oldsum);
+	return csum_partial(diff, sizeof(diff), oldsum);
 }
 
 #ifdef CONFIG_IP_VS_IPV6
@@ -926,7 +923,7 @@ static inline __wsum ip_vs_check_diff16(const __be32 *old, const __be32 *new,
 	__be32 diff[8] = { ~old[3], ~old[2], ~old[1], ~old[0],
 			    new[3],  new[2],  new[1],  new[0] };
 
-	return csum_partial((char *) diff, sizeof(diff), oldsum);
+	return csum_partial(diff, sizeof(diff), oldsum);
 }
 #endif
 
@@ -934,7 +931,7 @@ static inline __wsum ip_vs_check_diff2(__be16 old, __be16 new, __wsum oldsum)
 {
 	__be16 diff[2] = { ~old, new };
 
-	return csum_partial((char *) diff, sizeof(diff), oldsum);
+	return csum_partial(diff, sizeof(diff), oldsum);
 }
 
 #endif /* __KERNEL__ */
diff --git a/include/net/irda/irda.h b/include/net/irda/irda.h
index 08387553b57e..7e582061b230 100644
--- a/include/net/irda/irda.h
+++ b/include/net/irda/irda.h
@@ -72,7 +72,7 @@ do {	if (irda_debug >= (n)) \
 #define IRDA_ASSERT(expr, func) \
 do { if(!(expr)) { \
 	printk( "Assertion failed! %s:%s:%d %s\n", \
-		__FILE__,__FUNCTION__,__LINE__,(#expr) ); \
+		__FILE__,__func__,__LINE__,(#expr) ); \
 	func } } while (0)
 #define IRDA_ASSERT_LABEL(label)	label
 #else
diff --git a/include/net/irda/irda_device.h b/include/net/irda/irda_device.h
index 3025ae17ddbe..94c852d47d0f 100644
--- a/include/net/irda/irda_device.h
+++ b/include/net/irda/irda_device.h
@@ -135,9 +135,11 @@ struct dongle_reg {
 
 /* 
  * Per-packet information we need to hide inside sk_buff 
- * (must not exceed 48 bytes, check with struct sk_buff) 
+ * (must not exceed 48 bytes, check with struct sk_buff)
+ * The default_qdisc_pad field is a temporary hack.
  */
 struct irda_skb_cb {
+	unsigned int default_qdisc_pad;
 	magic_t magic;       /* Be sure that we can trust the information */
 	__u32   next_speed;  /* The Speed to be set *after* this frame */
 	__u16   mtt;         /* Minimum turn around time */
diff --git a/include/net/iucv/iucv.h b/include/net/iucv/iucv.h
index fd70adbb3566..5e310c8d8e2f 100644
--- a/include/net/iucv/iucv.h
+++ b/include/net/iucv/iucv.h
@@ -337,12 +337,35 @@ int iucv_message_purge(struct iucv_path *path, struct iucv_message *msg,
  * established paths. This function will deal with RMDATA messages
  * embedded in struct iucv_message as well.
  *
+ * Locking:	local_bh_enable/local_bh_disable
+ *
  * Returns the result from the CP IUCV call.
  */
 int iucv_message_receive(struct iucv_path *path, struct iucv_message *msg,
 			 u8 flags, void *buffer, size_t size, size_t *residual);
 
 /**
+ * __iucv_message_receive
+ * @path: address of iucv path structure
+ * @msg: address of iucv msg structure
+ * @flags: flags that affect how the message is received (IUCV_IPBUFLST)
+ * @buffer: address of data buffer or address of struct iucv_array
+ * @size: length of data buffer
+ * @residual:
+ *
+ * This function receives messages that are being sent to you over
+ * established paths. This function will deal with RMDATA messages
+ * embedded in struct iucv_message as well.
+ *
+ * Locking:	no locking.
+ *
+ * Returns the result from the CP IUCV call.
+ */
+int __iucv_message_receive(struct iucv_path *path, struct iucv_message *msg,
+			   u8 flags, void *buffer, size_t size,
+			   size_t *residual);
+
+/**
  * iucv_message_reject
  * @path: address of iucv path structure
  * @msg: address of iucv msg structure
@@ -386,12 +409,34 @@ int iucv_message_reply(struct iucv_path *path, struct iucv_message *msg,
  * transmitted is in a buffer and this is a one-way message and the
  * receiver will not reply to the message.
  *
+ * Locking:	local_bh_enable/local_bh_disable
+ *
  * Returns the result from the CP IUCV call.
  */
 int iucv_message_send(struct iucv_path *path, struct iucv_message *msg,
 		      u8 flags, u32 srccls, void *buffer, size_t size);
 
 /**
+ * __iucv_message_send
+ * @path: address of iucv path structure
+ * @msg: address of iucv msg structure
+ * @flags: how the message is sent (IUCV_IPRMDATA, IUCV_IPPRTY, IUCV_IPBUFLST)
+ * @srccls: source class of message
+ * @buffer: address of data buffer or address of struct iucv_array
+ * @size: length of send buffer
+ *
+ * This function transmits data to another application. Data to be
+ * transmitted is in a buffer and this is a one-way message and the
+ * receiver will not reply to the message.
+ *
+ * Locking:	no locking.
+ *
+ * Returns the result from the CP IUCV call.
+ */
+int __iucv_message_send(struct iucv_path *path, struct iucv_message *msg,
+			u8 flags, u32 srccls, void *buffer, size_t size);
+
+/**
  * iucv_message_send2way
  * @path: address of iucv path structure
  * @msg: address of iucv msg structure
diff --git a/include/net/ieee80211_crypt.h b/include/net/lib80211.h
index b3d65e0bedd3..fb4e2784857d 100644
--- a/include/net/ieee80211_crypt.h
+++ b/include/net/lib80211.h
@@ -1,4 +1,11 @@
 /*
+ * lib80211.h -- common bits for IEEE802.11 wireless drivers
+ *
+ * Copyright (c) 2008, John W. Linville <linville@tuxdriver.com>
+ *
+ * Some bits copied from old ieee80211 component, w/ original copyright
+ * notices below:
+ *
  * Original code based on Host AP (software wireless LAN access point) driver
  * for Intersil Prism2/2.5/3.
  *
@@ -11,31 +18,31 @@
  *
  * Copyright (c) 2004, Intel Corporation
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation. See README and COPYING for
- * more details.
  */
 
-/*
- * This file defines the interface to the ieee80211 crypto module.
- */
-#ifndef IEEE80211_CRYPT_H
-#define IEEE80211_CRYPT_H
+#ifndef LIB80211_H
+#define LIB80211_H
 
 #include <linux/types.h>
 #include <linux/list.h>
-#include <net/ieee80211.h>
+#include <linux/module.h>
 #include <asm/atomic.h>
+#include <linux/if.h>
+#include <linux/skbuff.h>
+#include <linux/ieee80211.h>
+#include <linux/timer.h>
+/* print_ssid() is intended to be used in debug (and possibly error)
+ * messages. It should never be used for passing ssid to user space. */
+const char *print_ssid(char *buf, const char *ssid, u8 ssid_len);
+#define DECLARE_SSID_BUF(var) char var[IEEE80211_MAX_SSID_LEN * 4 + 1] __maybe_unused
+
+#define NUM_WEP_KEYS	4
 
 enum {
 	IEEE80211_CRYPTO_TKIP_COUNTERMEASURES = (1 << 0),
 };
 
-struct sk_buff;
-struct module;
-
-struct ieee80211_crypto_ops {
+struct lib80211_crypto_ops {
 	const char *name;
 	struct list_head list;
 
@@ -87,22 +94,36 @@ struct ieee80211_crypto_ops {
 	struct module *owner;
 };
 
-struct ieee80211_crypt_data {
+struct lib80211_crypt_data {
 	struct list_head list;	/* delayed deletion list */
-	struct ieee80211_crypto_ops *ops;
+	struct lib80211_crypto_ops *ops;
 	void *priv;
 	atomic_t refcnt;
 };
 
-struct ieee80211_device;
-
-int ieee80211_register_crypto_ops(struct ieee80211_crypto_ops *ops);
-int ieee80211_unregister_crypto_ops(struct ieee80211_crypto_ops *ops);
-struct ieee80211_crypto_ops *ieee80211_get_crypto_ops(const char *name);
-void ieee80211_crypt_deinit_entries(struct ieee80211_device *, int);
-void ieee80211_crypt_deinit_handler(unsigned long);
-void ieee80211_crypt_delayed_deinit(struct ieee80211_device *ieee,
-				    struct ieee80211_crypt_data **crypt);
-void ieee80211_crypt_quiescing(struct ieee80211_device *ieee);
+struct lib80211_crypt_info {
+	char *name;
+	/* Most clients will already have a lock,
+	   so just point to that. */
+	spinlock_t *lock;
+
+	struct lib80211_crypt_data *crypt[NUM_WEP_KEYS];
+	int tx_keyidx;		/* default TX key index (crypt[tx_keyidx]) */
+	struct list_head crypt_deinit_list;
+	struct timer_list crypt_deinit_timer;
+	int crypt_quiesced;
+};
 
-#endif
+int lib80211_crypt_info_init(struct lib80211_crypt_info *info, char *name,
+                                spinlock_t *lock);
+void lib80211_crypt_info_free(struct lib80211_crypt_info *info);
+int lib80211_register_crypto_ops(struct lib80211_crypto_ops *ops);
+int lib80211_unregister_crypto_ops(struct lib80211_crypto_ops *ops);
+struct lib80211_crypto_ops *lib80211_get_crypto_ops(const char *name);
+void lib80211_crypt_deinit_entries(struct lib80211_crypt_info *, int);
+void lib80211_crypt_deinit_handler(unsigned long);
+void lib80211_crypt_delayed_deinit(struct lib80211_crypt_info *info,
+				    struct lib80211_crypt_data **crypt);
+void lib80211_crypt_quiescing(struct lib80211_crypt_info *info);
+
+#endif /* LIB80211_H */
diff --git a/include/net/mac80211.h b/include/net/mac80211.h
index 5617a1613c91..b3bd00a9d992 100644
--- a/include/net/mac80211.h
+++ b/include/net/mac80211.h
@@ -3,7 +3,7 @@
  *
  * Copyright 2002-2005, Devicescape Software, Inc.
  * Copyright 2006-2007	Jiri Benc <jbenc@suse.cz>
- * Copyright 2007	Johannes Berg <johannes@sipsolutions.net>
+ * Copyright 2007-2008	Johannes Berg <johannes@sipsolutions.net>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -74,14 +74,6 @@
  */
 
 /**
- * enum ieee80211_notification_type - Low level driver notification
- * @IEEE80211_NOTIFY_RE_ASSOC: start the re-association sequence
- */
-enum ieee80211_notification_types {
-	IEEE80211_NOTIFY_RE_ASSOC,
-};
-
-/**
  * struct ieee80211_ht_bss_info - describing BSS's HT characteristics
  *
  * This structure describes most essential parameters needed
@@ -115,7 +107,7 @@ enum ieee80211_max_queues {
  * The information provided in this structure is required for QoS
  * transmit queue configuration. Cf. IEEE 802.11 7.3.2.29.
  *
- * @aifs: arbitration interface space [0..255]
+ * @aifs: arbitration interframe space [0..255]
  * @cw_min: minimum contention window [a value of the form
  *	2^n-1 in the range 1..32767]
  * @cw_max: maximum contention window [like @cw_min]
@@ -172,6 +164,14 @@ enum ieee80211_bss_change {
 };
 
 /**
+ * struct ieee80211_bss_ht_conf - BSS's changing HT configuration
+ * @operation_mode: HT operation mode (like in &struct ieee80211_ht_info)
+ */
+struct ieee80211_bss_ht_conf {
+	u16 operation_mode;
+};
+
+/**
  * struct ieee80211_bss_conf - holds the BSS's changing parameters
  *
  * This structure keeps information about a BSS (and an association
@@ -180,15 +180,17 @@ enum ieee80211_bss_change {
  * @assoc: association status
  * @aid: association ID number, valid only when @assoc is true
  * @use_cts_prot: use CTS protection
- * @use_short_preamble: use 802.11b short preamble
- * @use_short_slot: use short slot time (only relevant for ERP)
+ * @use_short_preamble: use 802.11b short preamble;
+ *	if the hardware cannot handle this it must set the
+ *	IEEE80211_HW_2GHZ_SHORT_PREAMBLE_INCAPABLE hardware flag
+ * @use_short_slot: use short slot time (only relevant for ERP);
+ *	if the hardware cannot handle this it must set the
+ *	IEEE80211_HW_2GHZ_SHORT_SLOT_INCAPABLE hardware flag
  * @dtim_period: num of beacons before the next DTIM, for PSM
  * @timestamp: beacon timestamp
  * @beacon_int: beacon interval
  * @assoc_capability: capabilities taken from assoc resp
- * @assoc_ht: association in HT mode
- * @ht_conf: ht capabilities
- * @ht_bss_conf: ht extended capabilities
+ * @ht: BSS's HT configuration
  * @basic_rates: bitmap of basic rates, each bit stands for an
  *	index into the rate table configured by the driver in
  *	the current band.
@@ -206,10 +208,7 @@ struct ieee80211_bss_conf {
 	u16 assoc_capability;
 	u64 timestamp;
 	u64 basic_rates;
-	/* ht related data */
-	bool assoc_ht;
-	struct ieee80211_ht_info *ht_conf;
-	struct ieee80211_ht_bss_info *ht_bss_conf;
+	struct ieee80211_bss_ht_conf ht;
 };
 
 /**
@@ -218,29 +217,24 @@ struct ieee80211_bss_conf {
  * These flags are used with the @flags member of &ieee80211_tx_info.
  *
  * @IEEE80211_TX_CTL_REQ_TX_STATUS: request TX status callback for this frame.
- * @IEEE80211_TX_CTL_USE_RTS_CTS: use RTS-CTS before sending frame
- * @IEEE80211_TX_CTL_USE_CTS_PROTECT: use CTS protection for the frame (e.g.,
- *	for combined 802.11g / 802.11b networks)
+ * @IEEE80211_TX_CTL_ASSIGN_SEQ: The driver has to assign a sequence
+ *	number to this frame, taking care of not overwriting the fragment
+ *	number and increasing the sequence number only when the
+ *	IEEE80211_TX_CTL_FIRST_FRAGMENT flag is set. mac80211 will properly
+ *	assign sequence numbers to QoS-data frames but cannot do so correctly
+ *	for non-QoS-data and management frames because beacons need them from
+ *	that counter as well and mac80211 cannot guarantee proper sequencing.
+ *	If this flag is set, the driver should instruct the hardware to
+ *	assign a sequence number to the frame or assign one itself. Cf. IEEE
+ *	802.11-2007 7.1.3.4.1 paragraph 3. This flag will always be set for
+ *	beacons and always be clear for frames without a sequence number field.
  * @IEEE80211_TX_CTL_NO_ACK: tell the low level not to wait for an ack
- * @IEEE80211_TX_CTL_RATE_CTRL_PROBE: TBD
  * @IEEE80211_TX_CTL_CLEAR_PS_FILT: clear powersave filter for destination
  *	station
- * @IEEE80211_TX_CTL_REQUEUE: TBD
  * @IEEE80211_TX_CTL_FIRST_FRAGMENT: this is a first fragment of the frame
- * @IEEE80211_TX_CTL_SHORT_PREAMBLE: TBD
- * @IEEE80211_TX_CTL_LONG_RETRY_LIMIT: this frame should be send using the
- *	through set_retry_limit configured long retry value
  * @IEEE80211_TX_CTL_SEND_AFTER_DTIM: send this frame after DTIM beacon
  * @IEEE80211_TX_CTL_AMPDU: this frame should be sent as part of an A-MPDU
- * @IEEE80211_TX_CTL_OFDM_HT: this frame can be sent in HT OFDM rates. number
- *	of streams when this flag is on can be extracted from antenna_sel_tx,
- *	so if 1 antenna is marked use SISO, 2 antennas marked use MIMO, n
- *	antennas marked use MIMO_n.
- * @IEEE80211_TX_CTL_GREEN_FIELD: use green field protection for this frame
- * @IEEE80211_TX_CTL_40_MHZ_WIDTH: send this frame using 40 Mhz channel width
- * @IEEE80211_TX_CTL_DUP_DATA: duplicate data frame on both 20 Mhz channels
- * @IEEE80211_TX_CTL_SHORT_GI: send this frame using short guard interval
- * @IEEE80211_TX_CTL_INJECTED: TBD
+ * @IEEE80211_TX_CTL_INJECTED: Frame was injected, internal to mac80211.
  * @IEEE80211_TX_STAT_TX_FILTERED: The frame was not transmitted
  *	because the destination STA was in powersave mode.
  * @IEEE80211_TX_STAT_ACK: Frame was acknowledged
@@ -248,63 +242,67 @@ struct ieee80211_bss_conf {
  * 	is for the whole aggregation.
  * @IEEE80211_TX_STAT_AMPDU_NO_BACK: no block ack was returned,
  * 	so consider using block ack request (BAR).
- * @IEEE80211_TX_CTL_ASSIGN_SEQ: The driver has to assign a sequence
- *	number to this frame, taking care of not overwriting the fragment
- *	number and increasing the sequence number only when the
- *	IEEE80211_TX_CTL_FIRST_FRAGMENT flags is set. mac80211 will properly
- *	assign sequence numbers to QoS-data frames but cannot do so correctly
- *	for non-QoS-data and management frames because beacons need them from
- *	that counter as well and mac80211 cannot guarantee proper sequencing.
- *	If this flag is set, the driver should instruct the hardware to
- *	assign a sequence number to the frame or assign one itself. Cf. IEEE
- *	802.11-2007 7.1.3.4.1 paragraph 3. This flag will always be set for
- *	beacons always be clear for frames without a sequence number field.
+ * @IEEE80211_TX_CTL_RATE_CTRL_PROBE: internal to mac80211, can be
+ *	set by rate control algorithms to indicate probe rate, will
+ *	be cleared for fragmented frames (except on the last fragment)
  */
 enum mac80211_tx_control_flags {
 	IEEE80211_TX_CTL_REQ_TX_STATUS		= BIT(0),
-	IEEE80211_TX_CTL_USE_RTS_CTS		= BIT(2),
-	IEEE80211_TX_CTL_USE_CTS_PROTECT	= BIT(3),
-	IEEE80211_TX_CTL_NO_ACK			= BIT(4),
-	IEEE80211_TX_CTL_RATE_CTRL_PROBE	= BIT(5),
-	IEEE80211_TX_CTL_CLEAR_PS_FILT		= BIT(6),
-	IEEE80211_TX_CTL_REQUEUE		= BIT(7),
-	IEEE80211_TX_CTL_FIRST_FRAGMENT		= BIT(8),
-	IEEE80211_TX_CTL_SHORT_PREAMBLE		= BIT(9),
-	IEEE80211_TX_CTL_LONG_RETRY_LIMIT	= BIT(10),
-	IEEE80211_TX_CTL_SEND_AFTER_DTIM	= BIT(12),
-	IEEE80211_TX_CTL_AMPDU			= BIT(13),
-	IEEE80211_TX_CTL_OFDM_HT		= BIT(14),
-	IEEE80211_TX_CTL_GREEN_FIELD		= BIT(15),
-	IEEE80211_TX_CTL_40_MHZ_WIDTH		= BIT(16),
-	IEEE80211_TX_CTL_DUP_DATA		= BIT(17),
-	IEEE80211_TX_CTL_SHORT_GI		= BIT(18),
-	IEEE80211_TX_CTL_INJECTED		= BIT(19),
-	IEEE80211_TX_STAT_TX_FILTERED		= BIT(20),
-	IEEE80211_TX_STAT_ACK			= BIT(21),
-	IEEE80211_TX_STAT_AMPDU			= BIT(22),
-	IEEE80211_TX_STAT_AMPDU_NO_BACK		= BIT(23),
-	IEEE80211_TX_CTL_ASSIGN_SEQ		= BIT(24),
+	IEEE80211_TX_CTL_ASSIGN_SEQ		= BIT(1),
+	IEEE80211_TX_CTL_NO_ACK			= BIT(2),
+	IEEE80211_TX_CTL_CLEAR_PS_FILT		= BIT(3),
+	IEEE80211_TX_CTL_FIRST_FRAGMENT		= BIT(4),
+	IEEE80211_TX_CTL_SEND_AFTER_DTIM	= BIT(5),
+	IEEE80211_TX_CTL_AMPDU			= BIT(6),
+	IEEE80211_TX_CTL_INJECTED		= BIT(7),
+	IEEE80211_TX_STAT_TX_FILTERED		= BIT(8),
+	IEEE80211_TX_STAT_ACK			= BIT(9),
+	IEEE80211_TX_STAT_AMPDU			= BIT(10),
+	IEEE80211_TX_STAT_AMPDU_NO_BACK		= BIT(11),
+	IEEE80211_TX_CTL_RATE_CTRL_PROBE	= BIT(12),
+};
+
+enum mac80211_rate_control_flags {
+	IEEE80211_TX_RC_USE_RTS_CTS		= BIT(0),
+	IEEE80211_TX_RC_USE_CTS_PROTECT		= BIT(1),
+	IEEE80211_TX_RC_USE_SHORT_PREAMBLE	= BIT(2),
+
+	/* rate index is an MCS rate number instead of an index */
+	IEEE80211_TX_RC_MCS			= BIT(3),
+	IEEE80211_TX_RC_GREEN_FIELD		= BIT(4),
+	IEEE80211_TX_RC_40_MHZ_WIDTH		= BIT(5),
+	IEEE80211_TX_RC_DUP_DATA		= BIT(6),
+	IEEE80211_TX_RC_SHORT_GI		= BIT(7),
 };
 
 
-#define IEEE80211_TX_INFO_DRIVER_DATA_SIZE \
-	(sizeof(((struct sk_buff *)0)->cb) - 8)
-#define IEEE80211_TX_INFO_DRIVER_DATA_PTRS \
-	(IEEE80211_TX_INFO_DRIVER_DATA_SIZE / sizeof(void *))
+/* there are 40 bytes if you don't need the rateset to be kept */
+#define IEEE80211_TX_INFO_DRIVER_DATA_SIZE 40
 
-/* maximum number of alternate rate retry stages */
-#define IEEE80211_TX_MAX_ALTRATE	3
+/* if you do need the rateset, then you have less space */
+#define IEEE80211_TX_INFO_RATE_DRIVER_DATA_SIZE 24
+
+/* maximum number of rate stages */
+#define IEEE80211_TX_MAX_RATES	5
 
 /**
- * struct ieee80211_tx_altrate - alternate rate selection/status
+ * struct ieee80211_tx_rate - rate selection/status
+ *
+ * @idx: rate index to attempt to send with
+ * @flags: rate control flags (&enum mac80211_rate_control_flags)
+ * @count: number of tries in this rate before going to the next rate
  *
- * @rate_idx: rate index to attempt to send with
- * @limit: number of retries before fallback
+ * A value of -1 for @idx indicates an invalid rate and, if used
+ * in an array of retry rates, that no more rates should be tried.
+ *
+ * When used for transmit status reporting, the driver should
+ * always report the rate along with the flags it used.
  */
-struct ieee80211_tx_altrate {
-	s8 rate_idx;
-	u8 limit;
-};
+struct ieee80211_tx_rate {
+	s8 idx;
+	u8 count;
+	u8 flags;
+} __attribute__((packed));
 
 /**
  * struct ieee80211_tx_info - skb transmit information
@@ -318,15 +316,13 @@ struct ieee80211_tx_altrate {
  * it may be NULL.
  *
  * @flags: transmit info flags, defined above
- * @band: TBD
- * @tx_rate_idx: TBD
- * @antenna_sel_tx: TBD
+ * @band: the band to transmit on (use for checking for races)
+ * @antenna_sel_tx: antenna to use, 0 for automatic diversity
+ * @pad: padding, ignore
  * @control: union for control data
  * @status: union for status data
  * @driver_data: array of driver_data pointers
  * @retry_count: number of retries
- * @excessive_retries: set to 1 if the frame was retried many times
- *	but not acknowledged
  * @ampdu_ack_len: number of aggregated frames.
  * 	relevant only if IEEE80211_TX_STATUS_AMPDU was set.
  * @ampdu_ack_map: block ack bit map for the aggregation.
@@ -337,31 +333,44 @@ struct ieee80211_tx_info {
 	/* common information */
 	u32 flags;
 	u8 band;
-	s8 tx_rate_idx;
+
 	u8 antenna_sel_tx;
 
-	/* 1 byte hole */
+	/* 2 byte hole */
+	u8 pad[2];
 
 	union {
 		struct {
+			union {
+				/* rate control */
+				struct {
+					struct ieee80211_tx_rate rates[
+						IEEE80211_TX_MAX_RATES];
+					s8 rts_cts_rate_idx;
+				};
+				/* only needed before rate control */
+				unsigned long jiffies;
+			};
 			/* NB: vif can be NULL for injected frames */
 			struct ieee80211_vif *vif;
 			struct ieee80211_key_conf *hw_key;
 			struct ieee80211_sta *sta;
-			unsigned long jiffies;
-			s8 rts_cts_rate_idx;
-			u8 retry_limit;
-			struct ieee80211_tx_altrate retries[IEEE80211_TX_MAX_ALTRATE];
 		} control;
 		struct {
+			struct ieee80211_tx_rate rates[IEEE80211_TX_MAX_RATES];
+			u8 ampdu_ack_len;
 			u64 ampdu_ack_map;
 			int ack_signal;
-			struct ieee80211_tx_altrate retries[IEEE80211_TX_MAX_ALTRATE + 1];
-			u8 retry_count;
-			bool excessive_retries;
-			u8 ampdu_ack_len;
+			/* 8 bytes free */
 		} status;
-		void *driver_data[IEEE80211_TX_INFO_DRIVER_DATA_PTRS];
+		struct {
+			struct ieee80211_tx_rate driver_rates[
+				IEEE80211_TX_MAX_RATES];
+			void *rate_driver_data[
+				IEEE80211_TX_INFO_RATE_DRIVER_DATA_SIZE / sizeof(void *)];
+		};
+		void *driver_data[
+			IEEE80211_TX_INFO_DRIVER_DATA_SIZE / sizeof(void *)];
 	};
 };
 
@@ -370,6 +379,41 @@ static inline struct ieee80211_tx_info *IEEE80211_SKB_CB(struct sk_buff *skb)
 	return (struct ieee80211_tx_info *)skb->cb;
 }
 
+/**
+ * ieee80211_tx_info_clear_status - clear TX status
+ *
+ * @info: The &struct ieee80211_tx_info to be cleared.
+ *
+ * When the driver passes an skb back to mac80211, it must report
+ * a number of things in TX status. This function clears everything
+ * in the TX status but the rate control information (it does clear
+ * the count since you need to fill that in anyway).
+ *
+ * NOTE: You can only use this function if you do NOT use
+ *	 info->driver_data! Use info->rate_driver_data
+ *	 instead if you need only the less space that allows.
+ */
+static inline void
+ieee80211_tx_info_clear_status(struct ieee80211_tx_info *info)
+{
+	int i;
+
+	BUILD_BUG_ON(offsetof(struct ieee80211_tx_info, status.rates) !=
+		     offsetof(struct ieee80211_tx_info, control.rates));
+	BUILD_BUG_ON(offsetof(struct ieee80211_tx_info, status.rates) !=
+		     offsetof(struct ieee80211_tx_info, driver_rates));
+	BUILD_BUG_ON(offsetof(struct ieee80211_tx_info, status.rates) != 8);
+	/* clear the rate counts */
+	for (i = 0; i < IEEE80211_TX_MAX_RATES; i++)
+		info->status.rates[i].count = 0;
+
+	BUILD_BUG_ON(
+	    offsetof(struct ieee80211_tx_info, status.ampdu_ack_len) != 23);
+	memset(&info->status.ampdu_ack_len, 0,
+	       sizeof(struct ieee80211_tx_info) -
+	       offsetof(struct ieee80211_tx_info, status.ampdu_ack_len));
+}
+
 
 /**
  * enum mac80211_rx_flags - receive flags
@@ -392,6 +436,9 @@ static inline struct ieee80211_tx_info *IEEE80211_SKB_CB(struct sk_buff *skb)
  *	is valid. This is useful in monitor mode and necessary for beacon frames
  *	to enable IBSS merging.
  * @RX_FLAG_SHORTPRE: Short preamble was used for this frame
+ * @RX_FLAG_HT: HT MCS was used and rate_idx is MCS index
+ * @RX_FLAG_40MHZ: HT40 (40 MHz) was used
+ * @RX_FLAG_SHORT_GI: Short guard interval was used
  */
 enum mac80211_rx_flags {
 	RX_FLAG_MMIC_ERROR	= 1<<0,
@@ -402,7 +449,10 @@ enum mac80211_rx_flags {
 	RX_FLAG_FAILED_FCS_CRC	= 1<<5,
 	RX_FLAG_FAILED_PLCP_CRC = 1<<6,
 	RX_FLAG_TSFT		= 1<<7,
-	RX_FLAG_SHORTPRE	= 1<<8
+	RX_FLAG_SHORTPRE	= 1<<8,
+	RX_FLAG_HT		= 1<<9,
+	RX_FLAG_40MHZ		= 1<<10,
+	RX_FLAG_SHORT_GI	= 1<<11,
 };
 
 /**
@@ -422,7 +472,8 @@ enum mac80211_rx_flags {
  * @noise: noise when receiving this frame, in dBm.
  * @qual: overall signal quality indication, in percent (0-100).
  * @antenna: antenna used
- * @rate_idx: index of data rate into band's supported rates
+ * @rate_idx: index of data rate into band's supported rates or MCS index if
+ *	HT rates are use (RX_FLAG_HT)
  * @flag: %RX_FLAG_*
  */
 struct ieee80211_rx_status {
@@ -442,21 +493,49 @@ struct ieee80211_rx_status {
  *
  * Flags to define PHY configuration options
  *
- * @IEEE80211_CONF_SHORT_SLOT_TIME: use 802.11g short slot time
  * @IEEE80211_CONF_RADIOTAP: add radiotap header at receive time (if supported)
- * @IEEE80211_CONF_SUPPORT_HT_MODE: use 802.11n HT capabilities (if supported)
  * @IEEE80211_CONF_PS: Enable 802.11 power save mode
  */
 enum ieee80211_conf_flags {
-	/*
-	 * TODO: IEEE80211_CONF_SHORT_SLOT_TIME will be removed once drivers
-	 * have been converted to use bss_info_changed() for slot time
-	 * configuration
-	 */
-	IEEE80211_CONF_SHORT_SLOT_TIME	= (1<<0),
-	IEEE80211_CONF_RADIOTAP		= (1<<1),
-	IEEE80211_CONF_SUPPORT_HT_MODE	= (1<<2),
-	IEEE80211_CONF_PS		= (1<<3),
+	IEEE80211_CONF_RADIOTAP		= (1<<0),
+	IEEE80211_CONF_PS		= (1<<1),
+};
+
+/* XXX: remove all this once drivers stop trying to use it */
+static inline int __deprecated __IEEE80211_CONF_SHORT_SLOT_TIME(void)
+{
+	return 0;
+}
+#define IEEE80211_CONF_SHORT_SLOT_TIME (__IEEE80211_CONF_SHORT_SLOT_TIME())
+
+struct ieee80211_ht_conf {
+	bool enabled;
+	enum nl80211_channel_type channel_type;
+};
+
+/**
+ * enum ieee80211_conf_changed - denotes which configuration changed
+ *
+ * @IEEE80211_CONF_CHANGE_RADIO_ENABLED: the value of radio_enabled changed
+ * @IEEE80211_CONF_CHANGE_BEACON_INTERVAL: the beacon interval changed
+ * @IEEE80211_CONF_CHANGE_LISTEN_INTERVAL: the listen interval changed
+ * @IEEE80211_CONF_CHANGE_RADIOTAP: the radiotap flag changed
+ * @IEEE80211_CONF_CHANGE_PS: the PS flag changed
+ * @IEEE80211_CONF_CHANGE_POWER: the TX power changed
+ * @IEEE80211_CONF_CHANGE_CHANNEL: the channel changed
+ * @IEEE80211_CONF_CHANGE_RETRY_LIMITS: retry limits changed
+ * @IEEE80211_CONF_CHANGE_HT: HT configuration changed
+ */
+enum ieee80211_conf_changed {
+	IEEE80211_CONF_CHANGE_RADIO_ENABLED	= BIT(0),
+	IEEE80211_CONF_CHANGE_BEACON_INTERVAL	= BIT(1),
+	IEEE80211_CONF_CHANGE_LISTEN_INTERVAL	= BIT(2),
+	IEEE80211_CONF_CHANGE_RADIOTAP		= BIT(3),
+	IEEE80211_CONF_CHANGE_PS		= BIT(4),
+	IEEE80211_CONF_CHANGE_POWER		= BIT(5),
+	IEEE80211_CONF_CHANGE_CHANNEL		= BIT(6),
+	IEEE80211_CONF_CHANGE_RETRY_LIMITS	= BIT(7),
+	IEEE80211_CONF_CHANGE_HT		= BIT(8),
 };
 
 /**
@@ -465,34 +544,31 @@ enum ieee80211_conf_flags {
  * This struct indicates how the driver shall configure the hardware.
  *
  * @radio_enabled: when zero, driver is required to switch off the radio.
- *	TODO make a flag
  * @beacon_int: beacon interval (TODO make interface config)
  * @listen_interval: listen interval in units of beacon interval
  * @flags: configuration flags defined above
  * @power_level: requested transmit power (in dBm)
- * @max_antenna_gain: maximum antenna gain (in dBi)
- * @antenna_sel_tx: transmit antenna selection, 0: default/diversity,
- *	1/2: antenna 0/1
- * @antenna_sel_rx: receive antenna selection, like @antenna_sel_tx
- * @ht_conf: describes current self configuration of 802.11n HT capabilies
- * @ht_bss_conf: describes current BSS configuration of 802.11n HT parameters
  * @channel: the channel to tune to
+ * @ht: the HT configuration for the device
+ * @long_frame_max_tx_count: Maximum number of transmissions for a "long" frame
+ *    (a frame not RTS protected), called "dot11LongRetryLimit" in 802.11,
+ *    but actually means the number of transmissions not the number of retries
+ * @short_frame_max_tx_count: Maximum number of transmissions for a "short"
+ *    frame, called "dot11ShortRetryLimit" in 802.11, but actually means the
+ *    number of transmissions not the number of retries
  */
 struct ieee80211_conf {
-	int radio_enabled;
-
 	int beacon_int;
-	u16 listen_interval;
 	u32 flags;
 	int power_level;
-	int max_antenna_gain;
-	u8 antenna_sel_tx;
-	u8 antenna_sel_rx;
 
-	struct ieee80211_channel *channel;
+	u16 listen_interval;
+	bool radio_enabled;
+
+	u8 long_frame_max_tx_count, short_frame_max_tx_count;
 
-	struct ieee80211_ht_info ht_conf;
-	struct ieee80211_ht_bss_info ht_bss_conf;
+	struct ieee80211_channel *channel;
+	struct ieee80211_ht_conf ht;
 };
 
 /**
@@ -502,11 +578,14 @@ struct ieee80211_conf {
  * use during the life of a virtual interface.
  *
  * @type: type of this virtual interface
+ * @bss_conf: BSS configuration for this interface, either our own
+ *	or the BSS we're associated to
  * @drv_priv: data area for driver use, will always be aligned to
  *	sizeof(void *).
  */
 struct ieee80211_vif {
 	enum nl80211_iftype type;
+	struct ieee80211_bss_conf bss_conf;
 	/* must be last */
 	u8 drv_priv[0] __attribute__((__aligned__(sizeof(void *))));
 };
@@ -550,14 +629,12 @@ struct ieee80211_if_init_conf {
  * enum ieee80211_if_conf_change - interface config change flags
  *
  * @IEEE80211_IFCC_BSSID: The BSSID changed.
- * @IEEE80211_IFCC_SSID: The SSID changed.
  * @IEEE80211_IFCC_BEACON: The beacon for this interface changed
  *	(currently AP and MESH only), use ieee80211_beacon_get().
  */
 enum ieee80211_if_conf_change {
 	IEEE80211_IFCC_BSSID	= BIT(0),
-	IEEE80211_IFCC_SSID	= BIT(1),
-	IEEE80211_IFCC_BEACON	= BIT(2),
+	IEEE80211_IFCC_BEACON	= BIT(1),
 };
 
 /**
@@ -565,11 +642,6 @@ enum ieee80211_if_conf_change {
  *
  * @changed: parameters that have changed, see &enum ieee80211_if_conf_change.
  * @bssid: BSSID of the network we are associated to/creating.
- * @ssid: used (together with @ssid_len) by drivers for hardware that
- *	generate beacons independently. The pointer is valid only during the
- *	config_interface() call, so copy the value somewhere if you need
- *	it.
- * @ssid_len: length of the @ssid field.
  *
  * This structure is passed to the config_interface() callback of
  * &struct ieee80211_hw.
@@ -577,8 +649,6 @@ enum ieee80211_if_conf_change {
 struct ieee80211_if_conf {
 	u32 changed;
 	u8 *bssid;
-	u8 *ssid;
-	size_t ssid_len;
 };
 
 /**
@@ -645,7 +715,8 @@ enum ieee80211_key_flags {
  * 	- Temporal Encryption Key (128 bits)
  * 	- Temporal Authenticator Tx MIC Key (64 bits)
  * 	- Temporal Authenticator Rx MIC Key (64 bits)
- *
+ * @icv_len: FIXME
+ * @iv_len: FIXME
  */
 struct ieee80211_key_conf {
 	enum ieee80211_key_alg alg;
@@ -684,7 +755,7 @@ enum set_key_cmd {
  * @addr: MAC address
  * @aid: AID we assigned to the station if we're an AP
  * @supp_rates: Bitmap of supported rates (per band)
- * @ht_info: HT capabilities of this STA
+ * @ht_cap: HT capabilities of this STA; restricted to our own TX capabilities
  * @drv_priv: data area for driver use, will always be aligned to
  *	sizeof(void *), size is determined in hw information.
  */
@@ -692,7 +763,7 @@ struct ieee80211_sta {
 	u64 supp_rates[IEEE80211_NUM_BANDS];
 	u8 addr[ETH_ALEN];
 	u16 aid;
-	struct ieee80211_ht_info ht_info;
+	struct ieee80211_sta_ht_cap ht_cap;
 
 	/* must be last */
 	u8 drv_priv[0] __attribute__((__aligned__(sizeof(void *))));
@@ -702,13 +773,17 @@ struct ieee80211_sta {
  * enum sta_notify_cmd - sta notify command
  *
  * Used with the sta_notify() callback in &struct ieee80211_ops, this
- * indicates addition and removal of a station to station table.
+ * indicates addition and removal of a station to station table,
+ * or if a associated station made a power state transition.
  *
  * @STA_NOTIFY_ADD: a station was added to the station table
  * @STA_NOTIFY_REMOVE: a station being removed from the station table
+ * @STA_NOTIFY_SLEEP: a station is now sleeping
+ * @STA_NOTIFY_AWAKE: a sleeping station woke up
  */
 enum sta_notify_cmd {
-	STA_NOTIFY_ADD, STA_NOTIFY_REMOVE
+	STA_NOTIFY_ADD, STA_NOTIFY_REMOVE,
+	STA_NOTIFY_SLEEP, STA_NOTIFY_AWAKE,
 };
 
 /**
@@ -776,6 +851,14 @@ enum ieee80211_tkip_key_type {
  * @IEEE80211_HW_SPECTRUM_MGMT:
  * 	Hardware supports spectrum management defined in 802.11h
  * 	Measurement, Channel Switch, Quieting, TPC
+ *
+ * @IEEE80211_HW_AMPDU_AGGREGATION:
+ *	Hardware supports 11n A-MPDU aggregation.
+ *
+ * @IEEE80211_HW_NO_STACK_DYNAMIC_PS:
+ *	Hardware which has dynamic power save support, meaning
+ *	that power save is enabled in idle periods, and don't need support
+ *	from stack.
  */
 enum ieee80211_hw_flags {
 	IEEE80211_HW_RX_INCLUDES_FCS			= 1<<1,
@@ -787,6 +870,8 @@ enum ieee80211_hw_flags {
 	IEEE80211_HW_SIGNAL_DBM				= 1<<7,
 	IEEE80211_HW_NOISE_DBM				= 1<<8,
 	IEEE80211_HW_SPECTRUM_MGMT			= 1<<9,
+	IEEE80211_HW_AMPDU_AGGREGATION			= 1<<10,
+	IEEE80211_HW_NO_STACK_DYNAMIC_PS		= 1<<11,
 };
 
 /**
@@ -845,8 +930,8 @@ enum ieee80211_hw_flags {
  * @sta_data_size: size (in bytes) of the drv_priv data area
  *	within &struct ieee80211_sta.
  *
- * @max_altrates: maximum number of alternate rate retry stages
- * @max_altrate_tries: maximum number of tries for each stage
+ * @max_rates: maximum number of alternate rate retry stages
+ * @max_rate_tries: maximum number of tries for each stage
  */
 struct ieee80211_hw {
 	struct ieee80211_conf conf;
@@ -863,12 +948,10 @@ struct ieee80211_hw {
 	u16 ampdu_queues;
 	u16 max_listen_interval;
 	s8 max_signal;
-	u8 max_altrates;
-	u8 max_altrate_tries;
+	u8 max_rates;
+	u8 max_rate_tries;
 };
 
-struct ieee80211_hw *wiphy_to_hw(struct wiphy *wiphy);
-
 /**
  * SET_IEEE80211_DEV - set device for 802.11 hardware
  *
@@ -881,7 +964,7 @@ static inline void SET_IEEE80211_DEV(struct ieee80211_hw *hw, struct device *dev
 }
 
 /**
- * SET_IEEE80211_PERM_ADDR - set the permanenet MAC address for 802.11 hardware
+ * SET_IEEE80211_PERM_ADDR - set the permanent MAC address for 802.11 hardware
  *
  * @hw: the &struct ieee80211_hw to set the MAC address for
  * @addr: the address to set
@@ -905,9 +988,9 @@ static inline struct ieee80211_rate *
 ieee80211_get_tx_rate(const struct ieee80211_hw *hw,
 		      const struct ieee80211_tx_info *c)
 {
-	if (WARN_ON(c->tx_rate_idx < 0))
+	if (WARN_ON(c->control.rates[0].idx < 0))
 		return NULL;
-	return &hw->wiphy->bands[c->band]->bitrates[c->tx_rate_idx];
+	return &hw->wiphy->bands[c->band]->bitrates[c->control.rates[0].idx];
 }
 
 static inline struct ieee80211_rate *
@@ -923,9 +1006,9 @@ static inline struct ieee80211_rate *
 ieee80211_get_alt_retry_rate(const struct ieee80211_hw *hw,
 			     const struct ieee80211_tx_info *c, int idx)
 {
-	if (c->control.retries[idx].rate_idx < 0)
+	if (c->control.rates[idx + 1].idx < 0)
 		return NULL;
-	return &hw->wiphy->bands[c->band]->bitrates[c->control.retries[idx].rate_idx];
+	return &hw->wiphy->bands[c->band]->bitrates[c->control.rates[idx + 1].idx];
 }
 
 /**
@@ -974,7 +1057,7 @@ ieee80211_get_alt_retry_rate(const struct ieee80211_hw *hw,
  * This happens everytime the iv16 wraps around (every 65536 packets). The
  * set_key() call will happen only once for each key (unless the AP did
  * rekeying), it will not include a valid phase 1 key. The valid phase 1 key is
- * provided by udpate_tkip_key only. The trigger that makes mac80211 call this
+ * provided by update_tkip_key only. The trigger that makes mac80211 call this
  * handler is software decryption with wrap around of iv16.
  */
 
@@ -1067,12 +1150,14 @@ enum ieee80211_filter_flags {
  * @IEEE80211_AMPDU_RX_STOP: stop Rx aggregation
  * @IEEE80211_AMPDU_TX_START: start Tx aggregation
  * @IEEE80211_AMPDU_TX_STOP: stop Tx aggregation
+ * @IEEE80211_AMPDU_TX_RESUME: resume TX aggregation
  */
 enum ieee80211_ampdu_mlme_action {
 	IEEE80211_AMPDU_RX_START,
 	IEEE80211_AMPDU_RX_STOP,
 	IEEE80211_AMPDU_TX_START,
 	IEEE80211_AMPDU_TX_STOP,
+	IEEE80211_AMPDU_TX_RESUME,
 };
 
 /**
@@ -1108,7 +1193,7 @@ enum ieee80211_ampdu_mlme_action {
  *	Must be implemented.
  *
  * @add_interface: Called when a netdevice attached to the hardware is
- *	enabled. Because it is not called for monitor mode devices, @open
+ *	enabled. Because it is not called for monitor mode devices, @start
  *	and @stop must be implemented.
  *	The driver should perform any initialization it needs before
  *	the device can be enabled. The initial configuration for the
@@ -1170,14 +1255,9 @@ enum ieee80211_ampdu_mlme_action {
  *
  * @set_rts_threshold: Configuration of RTS threshold (if device needs it)
  *
- * @set_frag_threshold: Configuration of fragmentation threshold. Assign this if
- *	the device does fragmentation by itself; if this method is assigned then
- *	the stack will not do fragmentation.
- *
- * @set_retry_limit: Configuration of retry limits (if device needs it)
- *
- * @sta_notify: Notifies low level driver about addition or removal
- *	of assocaited station or AP.
+ * @sta_notify: Notifies low level driver about addition, removal or power
+ *	state transition of an associated station, AP,  IBSS/WDS/mesh peer etc.
+ *	Must be atomic.
  *
  * @conf_tx: Configure TX queue parameters (EDCF (aifs, cw_min, cw_max),
  *	bursting) for a hardware TX queue.
@@ -1201,8 +1281,6 @@ enum ieee80211_ampdu_mlme_action {
  *	This is needed only for IBSS mode and the result of this function is
  *	used to determine whether to reply to Probe Requests.
  *
- * @conf_ht: Configures low level driver with 802.11n HT data. Must be atomic.
- *
  * @ampdu_action: Perform a certain A-MPDU action
  * 	The RA/TID combination determines the destination and TID we want
  * 	the ampdu action to be performed for. The action is defined through
@@ -1218,7 +1296,7 @@ struct ieee80211_ops {
 			     struct ieee80211_if_init_conf *conf);
 	void (*remove_interface)(struct ieee80211_hw *hw,
 				 struct ieee80211_if_init_conf *conf);
-	int (*config)(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
+	int (*config)(struct ieee80211_hw *hw, u32 changed);
 	int (*config_interface)(struct ieee80211_hw *hw,
 				struct ieee80211_vif *vif,
 				struct ieee80211_if_conf *conf);
@@ -1244,9 +1322,6 @@ struct ieee80211_ops {
 	void (*get_tkip_seq)(struct ieee80211_hw *hw, u8 hw_key_idx,
 			     u32 *iv32, u16 *iv16);
 	int (*set_rts_threshold)(struct ieee80211_hw *hw, u32 value);
-	int (*set_frag_threshold)(struct ieee80211_hw *hw, u32 value);
-	int (*set_retry_limit)(struct ieee80211_hw *hw,
-			       u32 short_retry, u32 long_retr);
 	void (*sta_notify)(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 			enum sta_notify_cmd, struct ieee80211_sta *sta);
 	int (*conf_tx)(struct ieee80211_hw *hw, u16 queue,
@@ -1473,14 +1548,13 @@ void ieee80211_tx_status_irqsafe(struct ieee80211_hw *hw,
  * ieee80211_beacon_get - beacon generation function
  * @hw: pointer obtained from ieee80211_alloc_hw().
  * @vif: &struct ieee80211_vif pointer from &struct ieee80211_if_init_conf.
- * @control: will be filled with information needed to send this beacon.
  *
  * If the beacon frames are generated by the host system (i.e., not in
  * hardware/firmware), the low-level driver uses this function to receive
  * the next beacon frame from the 802.11 code. The low-level is responsible
  * for calling this function before beacon data is needed (e.g., based on
  * hardware interrupt). Returned skb is used only once and low-level driver
- * is responsible of freeing it.
+ * is responsible for freeing it.
  */
 struct sk_buff *ieee80211_beacon_get(struct ieee80211_hw *hw,
 				     struct ieee80211_vif *vif);
@@ -1574,7 +1648,6 @@ __le16 ieee80211_generic_frame_duration(struct ieee80211_hw *hw,
  * ieee80211_get_buffered_bc - accessing buffered broadcast and multicast frames
  * @hw: pointer as obtained from ieee80211_alloc_hw().
  * @vif: &struct ieee80211_vif pointer from &struct ieee80211_if_init_conf.
- * @control: will be filled with information needed to send returned frame.
  *
  * Function for accessing buffered broadcast and multicast frames. If
  * hardware/firmware does not implement buffering of broadcast/multicast
@@ -1622,9 +1695,8 @@ unsigned int ieee80211_hdrlen(__le16 fc);
  *
  * @keyconf: the parameter passed with the set key
  * @skb: the skb for which the key is needed
- * @rc4key: a buffer to which the key will be written
  * @type: TBD
- * @key: TBD
+ * @key: a buffer to which the key will be written
  */
 void ieee80211_get_tkip_key(struct ieee80211_key_conf *keyconf,
 				struct sk_buff *skb,
@@ -1725,7 +1797,8 @@ void ieee80211_iterate_active_interfaces_atomic(struct ieee80211_hw *hw,
  * @hw: pointer as obtained from ieee80211_alloc_hw().
  * @ra: receiver address of the BA session recipient
  * @tid: the TID to BA on.
- * @return: success if addBA request was sent, failure otherwise
+ *
+ * Return: success if addBA request was sent, failure otherwise
  *
  * Although mac80211/low level driver/user space application can estimate
  * the need to start aggregation on a certain RA/TID, the session level
@@ -1763,7 +1836,8 @@ void ieee80211_start_tx_ba_cb_irqsafe(struct ieee80211_hw *hw, const u8 *ra,
  * @ra: receiver address of the BA session recipient
  * @tid: the TID to stop BA.
  * @initiator: if indicates initiator DELBA frame will be sent.
- * @return: error if no sta with matching da found, success otherwise
+ *
+ * Return: error if no sta with matching da found, success otherwise
  *
  * Although mac80211/low level driver/user space application can estimate
  * the need to stop aggregation on a certain RA/TID, the session level
@@ -1798,18 +1872,6 @@ void ieee80211_stop_tx_ba_cb_irqsafe(struct ieee80211_hw *hw, const u8 *ra,
 				     u16 tid);
 
 /**
- * ieee80211_notify_mac - low level driver notification
- * @hw: pointer as obtained from ieee80211_alloc_hw().
- * @notif_type: enum ieee80211_notification_types
- *
- * This function must be called by low level driver to inform mac80211 of
- * low level driver status change or force mac80211 to re-assoc for low
- * level driver internal error that require re-assoc.
- */
-void ieee80211_notify_mac(struct ieee80211_hw *hw,
-			  enum ieee80211_notification_types  notif_type);
-
-/**
  * ieee80211_find_sta - find a station
  *
  * @hw: pointer as obtained from ieee80211_alloc_hw()
@@ -1823,24 +1885,38 @@ struct ieee80211_sta *ieee80211_find_sta(struct ieee80211_hw *hw,
 
 
 /* Rate control API */
+
 /**
- * struct rate_selection - rate information for/from rate control algorithms
- *
- * @rate_idx: selected transmission rate index
- * @nonerp_idx: Non-ERP rate to use instead if ERP cannot be used
- * @probe_idx: rate for probing (or -1)
- * @max_rate_idx: maximum rate index that can be used, this is
- *	input to the algorithm and will be enforced
- */
-struct rate_selection {
-	s8 rate_idx, nonerp_idx, probe_idx, max_rate_idx;
+ * struct ieee80211_tx_rate_control - rate control information for/from RC algo
+ *
+ * @hw: The hardware the algorithm is invoked for.
+ * @sband: The band this frame is being transmitted on.
+ * @bss_conf: the current BSS configuration
+ * @reported_rate: The rate control algorithm can fill this in to indicate
+ *	which rate should be reported to userspace as the current rate and
+ *	used for rate calculations in the mesh network.
+ * @rts: whether RTS will be used for this frame because it is longer than the
+ *	RTS threshold
+ * @short_preamble: whether mac80211 will request short-preamble transmission
+ *	if the selected rate supports it
+ * @max_rate_idx: user-requested maximum rate (not MCS for now)
+ * @skb: the skb that will be transmitted, the control information in it needs
+ *	to be filled in
+ */
+struct ieee80211_tx_rate_control {
+	struct ieee80211_hw *hw;
+	struct ieee80211_supported_band *sband;
+	struct ieee80211_bss_conf *bss_conf;
+	struct sk_buff *skb;
+	struct ieee80211_tx_rate reported_rate;
+	bool rts, short_preamble;
+	u8 max_rate_idx;
 };
 
 struct rate_control_ops {
 	struct module *module;
 	const char *name;
 	void *(*alloc)(struct ieee80211_hw *hw, struct dentry *debugfsdir);
-	void (*clear)(void *priv);
 	void (*free)(void *priv);
 
 	void *(*alloc_sta)(void *priv, struct ieee80211_sta *sta, gfp_t gfp);
@@ -1852,10 +1928,8 @@ struct rate_control_ops {
 	void (*tx_status)(void *priv, struct ieee80211_supported_band *sband,
 			  struct ieee80211_sta *sta, void *priv_sta,
 			  struct sk_buff *skb);
-	void (*get_rate)(void *priv, struct ieee80211_supported_band *sband,
-			 struct ieee80211_sta *sta, void *priv_sta,
-			 struct sk_buff *skb,
-			 struct rate_selection *sel);
+	void (*get_rate)(void *priv, struct ieee80211_sta *sta, void *priv_sta,
+			 struct ieee80211_tx_rate_control *txrc);
 
 	void (*add_sta_debugfs)(void *priv, void *priv_sta,
 				struct dentry *dir);
diff --git a/include/net/ndisc.h b/include/net/ndisc.h
index a01b7c4dc763..ce532f2222ce 100644
--- a/include/net/ndisc.h
+++ b/include/net/ndisc.h
@@ -108,6 +108,20 @@ extern void			ndisc_send_redirect(struct sk_buff *skb,
 
 extern int			ndisc_mc_map(struct in6_addr *addr, char *buf, struct net_device *dev, int dir);
 
+extern struct sk_buff		*ndisc_build_skb(struct net_device *dev,
+						 const struct in6_addr *daddr,
+						 const struct in6_addr *saddr,
+						 struct icmp6hdr *icmp6h,
+						 const struct in6_addr *target,
+						 int llinfo);
+
+extern void			ndisc_send_skb(struct sk_buff *skb,
+					       struct net_device *dev,
+					       struct neighbour *neigh,
+					       const struct in6_addr *daddr,
+					       const struct in6_addr *saddr,
+					       struct icmp6hdr *icmp6h);
+
 
 
 /*
@@ -129,9 +143,8 @@ extern int 			ndisc_ifinfo_sysctl_change(struct ctl_table *ctl,
 							   void __user *buffer,
 							   size_t *lenp,
 							   loff_t *ppos);
-int ndisc_ifinfo_sysctl_strategy(ctl_table *ctl, int __user *name,
-				 int nlen, void __user *oldval,
-				 size_t __user *oldlenp,
+int ndisc_ifinfo_sysctl_strategy(ctl_table *ctl,
+				 void __user *oldval, size_t __user *oldlenp,
 				 void __user *newval, size_t newlen);
 #endif
 
diff --git a/include/net/neighbour.h b/include/net/neighbour.h
index aa4b708654a4..d8d790e56d3d 100644
--- a/include/net/neighbour.h
+++ b/include/net/neighbour.h
@@ -180,9 +180,6 @@ struct neigh_table
 	__u32			hash_rnd;
 	unsigned int		hash_chain_gc;
 	struct pneigh_entry	**phash_buckets;
-#ifdef CONFIG_PROC_FS
-	struct proc_dir_entry	*pde;
-#endif
 };
 
 /* flags for neigh_update() */
@@ -223,11 +220,7 @@ extern void			neigh_parms_release(struct neigh_table *tbl, struct neigh_parms *p
 static inline
 struct net			*neigh_parms_net(const struct neigh_parms *parms)
 {
-#ifdef CONFIG_NET_NS
-	return parms->net;
-#else
-	return &init_net;
-#endif
+	return read_pnet(&parms->net);
 }
 
 extern unsigned long		neigh_rand_reach_time(unsigned long base);
@@ -244,11 +237,7 @@ extern int			pneigh_delete(struct neigh_table *tbl, struct net *net, const void
 static inline
 struct net			*pneigh_net(const struct pneigh_entry *pneigh)
 {
-#ifdef CONFIG_NET_NS
-	return pneigh->net;
-#else
-	return &init_net;
-#endif
+	return read_pnet(&pneigh->net);
 }
 
 extern void neigh_app_ns(struct neighbour *n);
diff --git a/include/net/net_namespace.h b/include/net/net_namespace.h
index 708009be88b6..6fc13d905c5f 100644
--- a/include/net/net_namespace.h
+++ b/include/net/net_namespace.h
@@ -19,6 +19,7 @@
 #if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE)
 #include <net/netns/conntrack.h>
 #endif
+#include <net/netns/xfrm.h>
 
 struct proc_dir_entry;
 struct net_device;
@@ -74,6 +75,9 @@ struct net {
 	struct netns_ct		ct;
 #endif
 #endif
+#ifdef CONFIG_XFRM
+	struct netns_xfrm	xfrm;
+#endif
 	struct net_generic	*gen;
 };
 
@@ -192,6 +196,24 @@ static inline void release_net(struct net *net)
 }
 #endif
 
+#ifdef CONFIG_NET_NS
+
+static inline void write_pnet(struct net **pnet, struct net *net)
+{
+	*pnet = net;
+}
+
+static inline struct net *read_pnet(struct net * const *pnet)
+{
+	return *pnet;
+}
+
+#else
+
+#define write_pnet(pnet, net)	do { (void)(net);} while (0)
+#define read_pnet(pnet)		(&init_net)
+
+#endif
 
 #define for_each_net(VAR)				\
 	list_for_each_entry(VAR, &net_namespace_list, list)
@@ -214,6 +236,8 @@ struct pernet_operations {
 
 extern int register_pernet_subsys(struct pernet_operations *);
 extern void unregister_pernet_subsys(struct pernet_operations *);
+extern int register_pernet_gen_subsys(int *id, struct pernet_operations *);
+extern void unregister_pernet_gen_subsys(int id, struct pernet_operations *);
 extern int register_pernet_device(struct pernet_operations *);
 extern void unregister_pernet_device(struct pernet_operations *);
 extern int register_pernet_gen_device(int *id, struct pernet_operations *);
diff --git a/include/net/netfilter/nf_conntrack.h b/include/net/netfilter/nf_conntrack.h
index b76a8685b5b5..2e0c53641cbe 100644
--- a/include/net/netfilter/nf_conntrack.h
+++ b/include/net/netfilter/nf_conntrack.h
@@ -199,7 +199,7 @@ __nf_conntrack_find(struct net *net, const struct nf_conntrack_tuple *tuple);
 
 extern void nf_conntrack_hash_insert(struct nf_conn *ct);
 
-extern void nf_conntrack_flush(struct net *net);
+extern void nf_conntrack_flush(struct net *net, u32 pid, int report);
 
 extern bool nf_ct_get_tuplepr(const struct sk_buff *skb,
 			      unsigned int nhoff, u_int16_t l3num,
@@ -298,5 +298,8 @@ do {							\
 	local_bh_enable();				\
 } while (0)
 
+#define MODULE_ALIAS_NFCT_HELPER(helper) \
+        MODULE_ALIAS("nfct-helper-" helper)
+
 #endif /* __KERNEL__ */
 #endif /* _NF_CONNTRACK_H */
diff --git a/include/net/netfilter/nf_conntrack_ecache.h b/include/net/netfilter/nf_conntrack_ecache.h
index 1285ff26a014..0ff0dc69ca4a 100644
--- a/include/net/netfilter/nf_conntrack_ecache.h
+++ b/include/net/netfilter/nf_conntrack_ecache.h
@@ -17,6 +17,13 @@ struct nf_conntrack_ecache {
 	unsigned int events;
 };
 
+/* This structure is passed to event handler */
+struct nf_ct_event {
+	struct nf_conn *ct;
+	u32 pid;
+	int report;
+};
+
 extern struct atomic_notifier_head nf_conntrack_chain;
 extern int nf_conntrack_register_notifier(struct notifier_block *nb);
 extern int nf_conntrack_unregister_notifier(struct notifier_block *nb);
@@ -39,22 +46,56 @@ nf_conntrack_event_cache(enum ip_conntrack_events event, struct nf_conn *ct)
 	local_bh_enable();
 }
 
-static inline void nf_conntrack_event(enum ip_conntrack_events event,
-				      struct nf_conn *ct)
+static inline void
+nf_conntrack_event_report(enum ip_conntrack_events event,
+			  struct nf_conn *ct,
+			  u32 pid,
+			  int report)
 {
+	struct nf_ct_event item = {
+		.ct 	= ct,
+		.pid	= pid,
+		.report = report
+	};
 	if (nf_ct_is_confirmed(ct) && !nf_ct_is_dying(ct))
-		atomic_notifier_call_chain(&nf_conntrack_chain, event, ct);
+		atomic_notifier_call_chain(&nf_conntrack_chain, event, &item);
 }
 
+static inline void
+nf_conntrack_event(enum ip_conntrack_events event, struct nf_conn *ct)
+{
+	nf_conntrack_event_report(event, ct, 0, 0);
+}
+
+struct nf_exp_event {
+	struct nf_conntrack_expect *exp;
+	u32 pid;
+	int report;
+};
+
 extern struct atomic_notifier_head nf_ct_expect_chain;
 extern int nf_ct_expect_register_notifier(struct notifier_block *nb);
 extern int nf_ct_expect_unregister_notifier(struct notifier_block *nb);
 
 static inline void
+nf_ct_expect_event_report(enum ip_conntrack_expect_events event,
+			  struct nf_conntrack_expect *exp,
+			  u32 pid,
+			  int report)
+{
+	struct nf_exp_event item = {
+		.exp	= exp,
+		.pid	= pid,
+		.report = report
+	};
+	atomic_notifier_call_chain(&nf_ct_expect_chain, event, &item);
+}
+
+static inline void
 nf_ct_expect_event(enum ip_conntrack_expect_events event,
 		   struct nf_conntrack_expect *exp)
 {
-	atomic_notifier_call_chain(&nf_ct_expect_chain, event, exp);
+	nf_ct_expect_event_report(event, exp, 0, 0);
 }
 
 extern int nf_conntrack_ecache_init(struct net *net);
@@ -66,9 +107,17 @@ static inline void nf_conntrack_event_cache(enum ip_conntrack_events event,
 					    struct nf_conn *ct) {}
 static inline void nf_conntrack_event(enum ip_conntrack_events event,
 				      struct nf_conn *ct) {}
+static inline void nf_conntrack_event_report(enum ip_conntrack_events event,
+					     struct nf_conn *ct,
+					     u32 pid,
+					     int report) {}
 static inline void nf_ct_deliver_cached_events(const struct nf_conn *ct) {}
 static inline void nf_ct_expect_event(enum ip_conntrack_expect_events event,
 				      struct nf_conntrack_expect *exp) {}
+static inline void nf_ct_expect_event_report(enum ip_conntrack_expect_events e,
+					     struct nf_conntrack_expect *exp,
+ 					     u32 pid,
+ 					     int report) {}
 static inline void nf_ct_event_cache_flush(struct net *net) {}
 
 static inline int nf_conntrack_ecache_init(struct net *net)
diff --git a/include/net/netfilter/nf_conntrack_expect.h b/include/net/netfilter/nf_conntrack_expect.h
index 37a7fc1164b0..ab17a159ac66 100644
--- a/include/net/netfilter/nf_conntrack_expect.h
+++ b/include/net/netfilter/nf_conntrack_expect.h
@@ -100,6 +100,8 @@ void nf_ct_expect_init(struct nf_conntrack_expect *, unsigned int, u_int8_t,
 		       u_int8_t, const __be16 *, const __be16 *);
 void nf_ct_expect_put(struct nf_conntrack_expect *exp);
 int nf_ct_expect_related(struct nf_conntrack_expect *expect);
+int nf_ct_expect_related_report(struct nf_conntrack_expect *expect, 
+				u32 pid, int report);
 
 #endif /*_NF_CONNTRACK_EXPECT_H*/
 
diff --git a/include/net/netfilter/nf_conntrack_helper.h b/include/net/netfilter/nf_conntrack_helper.h
index f8060ab5a083..66d65a7caa39 100644
--- a/include/net/netfilter/nf_conntrack_helper.h
+++ b/include/net/netfilter/nf_conntrack_helper.h
@@ -39,9 +39,6 @@ struct nf_conntrack_helper
 };
 
 extern struct nf_conntrack_helper *
-__nf_ct_helper_find(const struct nf_conntrack_tuple *tuple);
-
-extern struct nf_conntrack_helper *
 __nf_conntrack_helper_find_byname(const char *name);
 
 extern int nf_conntrack_helper_register(struct nf_conntrack_helper *);
@@ -49,6 +46,8 @@ extern void nf_conntrack_helper_unregister(struct nf_conntrack_helper *);
 
 extern struct nf_conn_help *nf_ct_helper_ext_add(struct nf_conn *ct, gfp_t gfp);
 
+extern int __nf_ct_try_assign_helper(struct nf_conn *ct, gfp_t flags);
+
 static inline struct nf_conn_help *nfct_help(const struct nf_conn *ct)
 {
 	return nf_ct_ext_find(ct, NF_CT_EXT_HELPER);
diff --git a/include/net/netfilter/nf_conntrack_l4proto.h b/include/net/netfilter/nf_conntrack_l4proto.h
index 7f2f43c77284..debdaf75cecf 100644
--- a/include/net/netfilter/nf_conntrack_l4proto.h
+++ b/include/net/netfilter/nf_conntrack_l4proto.h
@@ -129,7 +129,7 @@ extern const struct nla_policy nf_ct_port_nla_policy[];
 	 && net_ratelimit())
 #endif
 #else
-#define LOG_INVALID(net, proto) 0
+static inline int LOG_INVALID(struct net *net, int proto) { return 0; }
 #endif /* CONFIG_SYSCTL */
 
 #endif /*_NF_CONNTRACK_PROTOCOL_H*/
diff --git a/include/net/netfilter/nf_conntrack_tuple.h b/include/net/netfilter/nf_conntrack_tuple.h
index a6874ba22d54..f2f6aa73dc10 100644
--- a/include/net/netfilter/nf_conntrack_tuple.h
+++ b/include/net/netfilter/nf_conntrack_tuple.h
@@ -112,20 +112,20 @@ struct nf_conntrack_tuple_mask
 static inline void nf_ct_dump_tuple_ip(const struct nf_conntrack_tuple *t)
 {
 #ifdef DEBUG
-	printk("tuple %p: %u " NIPQUAD_FMT ":%hu -> " NIPQUAD_FMT ":%hu\n",
+	printk("tuple %p: %u %pI4:%hu -> %pI4:%hu\n",
 	       t, t->dst.protonum,
-	       NIPQUAD(t->src.u3.ip), ntohs(t->src.u.all),
-	       NIPQUAD(t->dst.u3.ip), ntohs(t->dst.u.all));
+	       &t->src.u3.ip, ntohs(t->src.u.all),
+	       &t->dst.u3.ip, ntohs(t->dst.u.all));
 #endif
 }
 
 static inline void nf_ct_dump_tuple_ipv6(const struct nf_conntrack_tuple *t)
 {
 #ifdef DEBUG
-	printk("tuple %p: %u " NIP6_FMT " %hu -> " NIP6_FMT " %hu\n",
+	printk("tuple %p: %u %pI6 %hu -> %pI6 %hu\n",
 	       t, t->dst.protonum,
-	       NIP6(*(struct in6_addr *)t->src.u3.all), ntohs(t->src.u.all),
-	       NIP6(*(struct in6_addr *)t->dst.u3.all), ntohs(t->dst.u.all));
+	       t->src.u3.all, ntohs(t->src.u.all),
+	       t->dst.u3.all, ntohs(t->dst.u.all));
 #endif
 }
 
diff --git a/include/net/netfilter/nf_nat_core.h b/include/net/netfilter/nf_nat_core.h
index f29eeb9777e0..58684066388c 100644
--- a/include/net/netfilter/nf_nat_core.h
+++ b/include/net/netfilter/nf_nat_core.h
@@ -25,4 +25,12 @@ static inline int nf_nat_initialized(struct nf_conn *ct,
 	else
 		return test_bit(IPS_DST_NAT_DONE_BIT, &ct->status);
 }
+
+struct nlattr;
+
+extern int
+(*nfnetlink_parse_nat_setup_hook)(struct nf_conn *ct,
+				  enum nf_nat_manip_type manip,
+				  struct nlattr *attr);
+
 #endif /* _NF_NAT_CORE_H */
diff --git a/include/net/netfilter/nfnetlink_log.h b/include/net/netfilter/nfnetlink_log.h
new file mode 100644
index 000000000000..b0569ff0775e
--- /dev/null
+++ b/include/net/netfilter/nfnetlink_log.h
@@ -0,0 +1,14 @@
+#ifndef _KER_NFNETLINK_LOG_H
+#define _KER_NFNETLINK_LOG_H
+
+void
+nfulnl_log_packet(u_int8_t pf,
+		  unsigned int hooknum,
+		  const struct sk_buff *skb,
+		  const struct net_device *in,
+		  const struct net_device *out,
+		  const struct nf_loginfo *li_user,
+		  const char *prefix);
+
+#endif /* _KER_NFNETLINK_LOG_H */
+
diff --git a/include/net/netlink.h b/include/net/netlink.h
index 3643bbb8e585..8a6150a3f4c7 100644
--- a/include/net/netlink.h
+++ b/include/net/netlink.h
@@ -233,7 +233,7 @@ extern int		nla_parse(struct nlattr *tb[], int maxtype,
 extern struct nlattr *	nla_find(struct nlattr *head, int len, int attrtype);
 extern size_t		nla_strlcpy(char *dst, const struct nlattr *nla,
 				    size_t dstsize);
-extern int		nla_memcpy(void *dest, struct nlattr *src, int count);
+extern int		nla_memcpy(void *dest, const struct nlattr *src, int count);
 extern int		nla_memcmp(const struct nlattr *nla, const void *data,
 				   size_t size);
 extern int		nla_strcmp(const struct nlattr *nla, const char *str);
@@ -332,7 +332,7 @@ static inline int nlmsg_attrlen(const struct nlmsghdr *nlh, int hdrlen)
  */
 static inline int nlmsg_ok(const struct nlmsghdr *nlh, int remaining)
 {
-	return (remaining >= sizeof(struct nlmsghdr) &&
+	return (remaining >= (int) sizeof(struct nlmsghdr) &&
 		nlh->nlmsg_len >= sizeof(struct nlmsghdr) &&
 		nlh->nlmsg_len <= remaining);
 }
@@ -741,7 +741,7 @@ static inline struct nlattr *nla_find_nested(struct nlattr *nla, int attrtype)
  * See nla_parse()
  */
 static inline int nla_parse_nested(struct nlattr *tb[], int maxtype,
-				   struct nlattr *nla,
+				   const struct nlattr *nla,
 				   const struct nla_policy *policy)
 {
 	return nla_parse(tb, maxtype, nla_data(nla), nla_len(nla), policy);
@@ -875,7 +875,7 @@ static inline int nla_put_msecs(struct sk_buff *skb, int attrtype,
  * nla_get_u32 - return payload of u32 attribute
  * @nla: u32 netlink attribute
  */
-static inline u32 nla_get_u32(struct nlattr *nla)
+static inline u32 nla_get_u32(const struct nlattr *nla)
 {
 	return *(u32 *) nla_data(nla);
 }
@@ -884,7 +884,7 @@ static inline u32 nla_get_u32(struct nlattr *nla)
  * nla_get_be32 - return payload of __be32 attribute
  * @nla: __be32 netlink attribute
  */
-static inline __be32 nla_get_be32(struct nlattr *nla)
+static inline __be32 nla_get_be32(const struct nlattr *nla)
 {
 	return *(__be32 *) nla_data(nla);
 }
@@ -893,7 +893,7 @@ static inline __be32 nla_get_be32(struct nlattr *nla)
  * nla_get_u16 - return payload of u16 attribute
  * @nla: u16 netlink attribute
  */
-static inline u16 nla_get_u16(struct nlattr *nla)
+static inline u16 nla_get_u16(const struct nlattr *nla)
 {
 	return *(u16 *) nla_data(nla);
 }
@@ -902,7 +902,7 @@ static inline u16 nla_get_u16(struct nlattr *nla)
  * nla_get_be16 - return payload of __be16 attribute
  * @nla: __be16 netlink attribute
  */
-static inline __be16 nla_get_be16(struct nlattr *nla)
+static inline __be16 nla_get_be16(const struct nlattr *nla)
 {
 	return *(__be16 *) nla_data(nla);
 }
@@ -911,7 +911,7 @@ static inline __be16 nla_get_be16(struct nlattr *nla)
  * nla_get_le16 - return payload of __le16 attribute
  * @nla: __le16 netlink attribute
  */
-static inline __le16 nla_get_le16(struct nlattr *nla)
+static inline __le16 nla_get_le16(const struct nlattr *nla)
 {
 	return *(__le16 *) nla_data(nla);
 }
@@ -920,7 +920,7 @@ static inline __le16 nla_get_le16(struct nlattr *nla)
  * nla_get_u8 - return payload of u8 attribute
  * @nla: u8 netlink attribute
  */
-static inline u8 nla_get_u8(struct nlattr *nla)
+static inline u8 nla_get_u8(const struct nlattr *nla)
 {
 	return *(u8 *) nla_data(nla);
 }
@@ -929,7 +929,7 @@ static inline u8 nla_get_u8(struct nlattr *nla)
  * nla_get_u64 - return payload of u64 attribute
  * @nla: u64 netlink attribute
  */
-static inline u64 nla_get_u64(struct nlattr *nla)
+static inline u64 nla_get_u64(const struct nlattr *nla)
 {
 	u64 tmp;
 
@@ -942,7 +942,7 @@ static inline u64 nla_get_u64(struct nlattr *nla)
  * nla_get_flag - return payload of flag attribute
  * @nla: flag netlink attribute
  */
-static inline int nla_get_flag(struct nlattr *nla)
+static inline int nla_get_flag(const struct nlattr *nla)
 {
 	return !!nla;
 }
@@ -953,7 +953,7 @@ static inline int nla_get_flag(struct nlattr *nla)
  *
  * Returns the number of milliseconds in jiffies.
  */
-static inline unsigned long nla_get_msecs(struct nlattr *nla)
+static inline unsigned long nla_get_msecs(const struct nlattr *nla)
 {
 	u64 msecs = nla_get_u64(nla);
 
diff --git a/include/net/netns/ipv4.h b/include/net/netns/ipv4.h
index ece1c926b5d1..977f482d97a9 100644
--- a/include/net/netns/ipv4.h
+++ b/include/net/netns/ipv4.h
@@ -49,6 +49,8 @@ struct netns_ipv4 {
 	int sysctl_icmp_ratelimit;
 	int sysctl_icmp_ratemask;
 	int sysctl_icmp_errors_use_inbound_ifaddr;
+	int sysctl_rt_cache_rebuild_count;
+	int current_rt_cache_rebuild_count;
 
 	struct timer_list rt_secret_timer;
 	atomic_t rt_genid;
diff --git a/include/net/netns/ipv6.h b/include/net/netns/ipv6.h
index 2932721180c0..afab4e4cbac7 100644
--- a/include/net/netns/ipv6.h
+++ b/include/net/netns/ipv6.h
@@ -55,5 +55,17 @@ struct netns_ipv6 {
 	struct sock             *ndisc_sk;
 	struct sock             *tcp_sk;
 	struct sock             *igmp_sk;
+#ifdef CONFIG_IPV6_MROUTE
+	struct sock		*mroute6_sk;
+	struct mfc6_cache	**mfc6_cache_array;
+	struct mif_device	*vif6_table;
+	int			maxvif;
+	atomic_t		cache_resolve_queue_len;
+	int			mroute_do_assert;
+	int			mroute_do_pim;
+#ifdef CONFIG_IPV6_PIMSM_V2
+	int			mroute_reg_vif_num;
+#endif
+#endif
 };
 #endif
diff --git a/include/net/netns/mib.h b/include/net/netns/mib.h
index 10cb7c336de5..0b44112e2366 100644
--- a/include/net/netns/mib.h
+++ b/include/net/netns/mib.h
@@ -20,6 +20,9 @@ struct netns_mib {
 	DEFINE_SNMP_STAT(struct icmpv6_mib, icmpv6_statistics);
 	DEFINE_SNMP_STAT(struct icmpv6msg_mib, icmpv6msg_statistics);
 #endif
+#ifdef CONFIG_XFRM_STATISTICS
+	DEFINE_SNMP_STAT(struct linux_xfrm_mib, xfrm_statistics);
+#endif
 };
 
 #endif
diff --git a/include/net/netns/x_tables.h b/include/net/netns/x_tables.h
index 0cb63ed2c1fc..9554a644a8f8 100644
--- a/include/net/netns/x_tables.h
+++ b/include/net/netns/x_tables.h
@@ -2,9 +2,14 @@
 #define __NETNS_X_TABLES_H
 
 #include <linux/list.h>
-#include <linux/net.h>
+#include <linux/netfilter.h>
+
+struct ebt_table;
 
 struct netns_xt {
-	struct list_head tables[NPROTO];
+	struct list_head tables[NFPROTO_NUMPROTO];
+	struct ebt_table *broute_table;
+	struct ebt_table *frame_filter;
+	struct ebt_table *frame_nat;
 };
 #endif
diff --git a/include/net/netns/xfrm.h b/include/net/netns/xfrm.h
new file mode 100644
index 000000000000..1ba912749caa
--- /dev/null
+++ b/include/net/netns/xfrm.h
@@ -0,0 +1,56 @@
+#ifndef __NETNS_XFRM_H
+#define __NETNS_XFRM_H
+
+#include <linux/list.h>
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+#include <linux/xfrm.h>
+
+struct ctl_table_header;
+
+struct xfrm_policy_hash {
+	struct hlist_head	*table;
+	unsigned int		hmask;
+};
+
+struct netns_xfrm {
+	struct list_head	state_all;
+	/*
+	 * Hash table to find appropriate SA towards given target (endpoint of
+	 * tunnel or destination of transport mode) allowed by selector.
+	 *
+	 * Main use is finding SA after policy selected tunnel or transport
+	 * mode. Also, it can be used by ah/esp icmp error handler to find
+	 * offending SA.
+	 */
+	struct hlist_head	*state_bydst;
+	struct hlist_head	*state_bysrc;
+	struct hlist_head	*state_byspi;
+	unsigned int		state_hmask;
+	unsigned int		state_num;
+	struct work_struct	state_hash_work;
+	struct hlist_head	state_gc_list;
+	struct work_struct	state_gc_work;
+
+	wait_queue_head_t	km_waitq;
+
+	struct list_head	policy_all;
+	struct hlist_head	*policy_byidx;
+	unsigned int		policy_idx_hmask;
+	struct hlist_head	policy_inexact[XFRM_POLICY_MAX * 2];
+	struct xfrm_policy_hash	policy_bydst[XFRM_POLICY_MAX * 2];
+	unsigned int		policy_count[XFRM_POLICY_MAX * 2];
+	struct work_struct	policy_hash_work;
+
+	struct sock		*nlsk;
+
+	u32			sysctl_aevent_etime;
+	u32			sysctl_aevent_rseqth;
+	int			sysctl_larval_drop;
+	u32			sysctl_acq_expires;
+#ifdef CONFIG_SYSCTL
+	struct ctl_table_header	*sysctl_hdr;
+#endif
+};
+
+#endif
diff --git a/include/net/phonet/pep.h b/include/net/phonet/pep.h
index fcd793030e4d..4c61cdce4e5f 100644
--- a/include/net/phonet/pep.h
+++ b/include/net/phonet/pep.h
@@ -35,12 +35,12 @@ struct pep_sock {
 	struct sock		*listener;
 	struct sk_buff_head	ctrlreq_queue;
 #define PNPIPE_CTRLREQ_MAX	10
+	atomic_t		tx_credits;
 	int			ifindex;
 	u16			peer_type;	/* peer type/subtype */
 	u8			pipe_handle;
 
 	u8			rx_credits;
-	u8			tx_credits;
 	u8			rx_fc;	/* RX flow control */
 	u8			tx_fc;	/* TX flow control */
 	u8			init_enable;	/* auto-enable at creation */
diff --git a/include/net/phonet/phonet.h b/include/net/phonet/phonet.h
index d4e72508e145..057b0a8a2885 100644
--- a/include/net/phonet/phonet.h
+++ b/include/net/phonet/phonet.h
@@ -27,7 +27,7 @@
  * The lower layers may not require more space, ever. Make sure it's
  * enough.
  */
-#define MAX_PHONET_HEADER	8
+#define MAX_PHONET_HEADER	(8 + MAX_HEADER)
 
 /*
  * Every Phonet* socket has this structure first in its
@@ -46,7 +46,7 @@ static inline struct pn_sock *pn_sk(struct sock *sk)
 
 extern const struct proto_ops phonet_dgram_ops;
 
-struct sock *pn_find_sock_by_sa(const struct sockaddr_pn *sa);
+struct sock *pn_find_sock_by_sa(struct net *net, const struct sockaddr_pn *sa);
 void phonet_get_local_port_range(int *min, int *max);
 void pn_sock_hash(struct sock *sk);
 void pn_sock_unhash(struct sock *sk);
diff --git a/include/net/phonet/pn_dev.h b/include/net/phonet/pn_dev.h
index bbd2a836e04c..aa1c59a1d33f 100644
--- a/include/net/phonet/pn_dev.h
+++ b/include/net/phonet/pn_dev.h
@@ -43,7 +43,7 @@ struct net_device *phonet_device_get(struct net *net);
 int phonet_address_add(struct net_device *dev, u8 addr);
 int phonet_address_del(struct net_device *dev, u8 addr);
 u8 phonet_address_get(struct net_device *dev, u8 addr);
-int phonet_address_lookup(u8 addr);
+int phonet_address_lookup(struct net *net, u8 addr);
 
 #define PN_NO_ADDR	0xff
 
diff --git a/include/net/pkt_cls.h b/include/net/pkt_cls.h
index aa9e282db485..d1ca31444644 100644
--- a/include/net/pkt_cls.h
+++ b/include/net/pkt_cls.h
@@ -246,7 +246,7 @@ struct tcf_ematch_ops
 };
 
 extern int tcf_em_register(struct tcf_ematch_ops *);
-extern int tcf_em_unregister(struct tcf_ematch_ops *);
+extern void tcf_em_unregister(struct tcf_ematch_ops *);
 extern int tcf_em_tree_validate(struct tcf_proto *, struct nlattr *,
 				struct tcf_ematch_tree *);
 extern void tcf_em_tree_destroy(struct tcf_proto *, struct tcf_ematch_tree *);
diff --git a/include/net/protocol.h b/include/net/protocol.h
index 8d024d7cb741..cb2965aa1b62 100644
--- a/include/net/protocol.h
+++ b/include/net/protocol.h
@@ -39,6 +39,9 @@ struct net_protocol {
 	int			(*gso_send_check)(struct sk_buff *skb);
 	struct sk_buff	       *(*gso_segment)(struct sk_buff *skb,
 					       int features);
+	struct sk_buff	      **(*gro_receive)(struct sk_buff **head,
+					       struct sk_buff *skb);
+	int			(*gro_complete)(struct sk_buff *skb);
 	unsigned int		no_policy:1,
 				netns_ok:1;
 };
diff --git a/include/net/request_sock.h b/include/net/request_sock.h
index cac811e51f6d..c7190846e128 100644
--- a/include/net/request_sock.h
+++ b/include/net/request_sock.h
@@ -31,6 +31,7 @@ struct request_sock_ops {
 	int		family;
 	int		obj_size;
 	struct kmem_cache	*slab;
+	char		*slab_name;
 	int		(*rtx_syn_ack)(struct sock *sk,
 				       struct request_sock *req);
 	void		(*send_ack)(struct sock *sk, struct sk_buff *skb,
diff --git a/include/net/sch_generic.h b/include/net/sch_generic.h
index 3fe49d808957..f8c47429044a 100644
--- a/include/net/sch_generic.h
+++ b/include/net/sch_generic.h
@@ -53,7 +53,6 @@ struct Qdisc
 	atomic_t		refcnt;
 	unsigned long		state;
 	struct sk_buff		*gso_skb;
-	struct sk_buff_head	requeue;
 	struct sk_buff_head	q;
 	struct netdev_queue	*dev_queue;
 	struct Qdisc		*next_sched;
@@ -111,7 +110,7 @@ struct Qdisc_ops
 
 	int 			(*enqueue)(struct sk_buff *, struct Qdisc *);
 	struct sk_buff *	(*dequeue)(struct Qdisc *);
-	int 			(*requeue)(struct sk_buff *, struct Qdisc *);
+	struct sk_buff *	(*peek)(struct Qdisc *);
 	unsigned int		(*drop)(struct Qdisc *);
 
 	int			(*init)(struct Qdisc *, struct nlattr *arg);
@@ -432,19 +431,38 @@ static inline struct sk_buff *qdisc_dequeue_tail(struct Qdisc *sch)
 	return __qdisc_dequeue_tail(sch, &sch->q);
 }
 
-static inline int __qdisc_requeue(struct sk_buff *skb, struct Qdisc *sch,
-				  struct sk_buff_head *list)
+static inline struct sk_buff *qdisc_peek_head(struct Qdisc *sch)
 {
-	__skb_queue_head(list, skb);
-	sch->qstats.backlog += qdisc_pkt_len(skb);
-	sch->qstats.requeues++;
+	return skb_peek(&sch->q);
+}
 
-	return NET_XMIT_SUCCESS;
+/* generic pseudo peek method for non-work-conserving qdisc */
+static inline struct sk_buff *qdisc_peek_dequeued(struct Qdisc *sch)
+{
+	/* we can reuse ->gso_skb because peek isn't called for root qdiscs */
+	if (!sch->gso_skb) {
+		sch->gso_skb = sch->dequeue(sch);
+		if (sch->gso_skb)
+			/* it's still part of the queue */
+			sch->q.qlen++;
+	}
+
+	return sch->gso_skb;
 }
 
-static inline int qdisc_requeue(struct sk_buff *skb, struct Qdisc *sch)
+/* use instead of qdisc->dequeue() for all qdiscs queried with ->peek() */
+static inline struct sk_buff *qdisc_dequeue_peeked(struct Qdisc *sch)
 {
-	return __qdisc_requeue(skb, sch, &sch->q);
+	struct sk_buff *skb = sch->gso_skb;
+
+	if (skb) {
+		sch->gso_skb = NULL;
+		sch->q.qlen--;
+	} else {
+		skb = sch->dequeue(sch);
+	}
+
+	return skb;
 }
 
 static inline void __qdisc_reset_queue(struct Qdisc *sch,
diff --git a/include/net/scm.h b/include/net/scm.h
index 06df126103ca..f45bb6eca7d4 100644
--- a/include/net/scm.h
+++ b/include/net/scm.h
@@ -14,8 +14,9 @@
 
 struct scm_fp_list
 {
-	int		count;
-	struct file	*fp[SCM_MAX_FD];
+	struct list_head	list;
+	int			count;
+	struct file		*fp[SCM_MAX_FD];
 };
 
 struct scm_cookie
@@ -54,8 +55,8 @@ static __inline__ int scm_send(struct socket *sock, struct msghdr *msg,
 			       struct scm_cookie *scm)
 {
 	struct task_struct *p = current;
-	scm->creds.uid = p->uid;
-	scm->creds.gid = p->gid;
+	scm->creds.uid = current_uid();
+	scm->creds.gid = current_gid();
 	scm->creds.pid = task_tgid_vnr(p);
 	scm->fp = NULL;
 	scm->seq = 0;
diff --git a/include/net/sctp/sctp.h b/include/net/sctp/sctp.h
index 703305d00365..bbb7742195b0 100644
--- a/include/net/sctp/sctp.h
+++ b/include/net/sctp/sctp.h
@@ -138,6 +138,7 @@ void sctp_write_space(struct sock *sk);
 unsigned int sctp_poll(struct file *file, struct socket *sock,
 		poll_table *wait);
 void sctp_sock_rfree(struct sk_buff *skb);
+extern struct percpu_counter sctp_sockets_allocated;
 
 /*
  * sctp/primitive.c
@@ -285,15 +286,15 @@ extern int sctp_debug_flag;
 	if (sctp_debug_flag) { \
 		if (saddr->sa.sa_family == AF_INET6) { \
 			printk(KERN_DEBUG \
-			       lead NIP6_FMT trail, \
+			       lead "%pI6" trail, \
 			       leadparm, \
-			       NIP6(saddr->v6.sin6_addr), \
+			       &saddr->v6.sin6_addr, \
 			       otherparms); \
 		} else { \
 			printk(KERN_DEBUG \
-			       lead NIPQUAD_FMT trail, \
+			       lead "%pI4" trail, \
 			       leadparm, \
-			       NIPQUAD(saddr->v4.sin_addr.s_addr), \
+			       &saddr->v4.sin_addr.s_addr, \
 			       otherparms); \
 		} \
 	}
@@ -303,7 +304,7 @@ extern int sctp_debug_flag;
 #define SCTP_ASSERT(expr, str, func) \
 	if (!(expr)) { \
 		SCTP_DEBUG_PRINTK("Assertion Failed: %s(%s) at %s:%s:%d\n", \
-			str, (#expr), __FILE__, __FUNCTION__, __LINE__); \
+			str, (#expr), __FILE__, __func__, __LINE__); \
 		func; \
 	}
 
diff --git a/include/net/sctp/sm.h b/include/net/sctp/sm.h
index 029a54a02396..c1dd89365833 100644
--- a/include/net/sctp/sm.h
+++ b/include/net/sctp/sm.h
@@ -125,6 +125,7 @@ sctp_state_fn_t sctp_sf_beat_8_3;
 sctp_state_fn_t sctp_sf_backbeat_8_3;
 sctp_state_fn_t sctp_sf_do_9_2_final;
 sctp_state_fn_t sctp_sf_do_9_2_shutdown;
+sctp_state_fn_t sctp_sf_do_9_2_shut_ctsn;
 sctp_state_fn_t sctp_sf_do_ecn_cwr;
 sctp_state_fn_t sctp_sf_do_ecne;
 sctp_state_fn_t sctp_sf_ootb;
diff --git a/include/net/sctp/user.h b/include/net/sctp/user.h
index f205b10f0ab9..b259fc5798fb 100644
--- a/include/net/sctp/user.h
+++ b/include/net/sctp/user.h
@@ -118,6 +118,8 @@ enum sctp_optname {
 #define SCTP_PEER_AUTH_CHUNKS SCTP_PEER_AUTH_CHUNKS
 	SCTP_LOCAL_AUTH_CHUNKS,		/* Read only */
 #define SCTP_LOCAL_AUTH_CHUNKS SCTP_LOCAL_AUTH_CHUNKS
+	SCTP_GET_ASSOC_NUMBER,		/* Read only */
+#define SCTP_GET_ASSOC_NUMBER SCTP_GET_ASSOC_NUMBER
 
 
 	/* Internal Socket Options. Some of the sctp library functions are 
diff --git a/include/net/sock.h b/include/net/sock.h
index ada50c04d09f..5a3a151bd730 100644
--- a/include/net/sock.h
+++ b/include/net/sock.h
@@ -42,6 +42,7 @@
 
 #include <linux/kernel.h>
 #include <linux/list.h>
+#include <linux/list_nulls.h>
 #include <linux/timer.h>
 #include <linux/cache.h>
 #include <linux/module.h>
@@ -52,6 +53,7 @@
 #include <linux/security.h>
 
 #include <linux/filter.h>
+#include <linux/rculist_nulls.h>
 
 #include <asm/atomic.h>
 #include <net/dst.h>
@@ -106,6 +108,7 @@ struct net;
  *	@skc_reuse: %SO_REUSEADDR setting
  *	@skc_bound_dev_if: bound device index if != 0
  *	@skc_node: main hash linkage for various protocol lookup tables
+ *	@skc_nulls_node: main hash linkage for UDP/UDP-Lite protocol
  *	@skc_bind_node: bind hash linkage for various protocol lookup tables
  *	@skc_refcnt: reference count
  *	@skc_hash: hash value used with various protocol lookup tables
@@ -120,7 +123,10 @@ struct sock_common {
 	volatile unsigned char	skc_state;
 	unsigned char		skc_reuse;
 	int			skc_bound_dev_if;
-	struct hlist_node	skc_node;
+	union {
+		struct hlist_node	skc_node;
+		struct hlist_nulls_node skc_nulls_node;
+	};
 	struct hlist_node	skc_bind_node;
 	atomic_t		skc_refcnt;
 	unsigned int		skc_hash;
@@ -206,6 +212,7 @@ struct sock {
 #define sk_reuse		__sk_common.skc_reuse
 #define sk_bound_dev_if		__sk_common.skc_bound_dev_if
 #define sk_node			__sk_common.skc_node
+#define sk_nulls_node		__sk_common.skc_nulls_node
 #define sk_bind_node		__sk_common.skc_bind_node
 #define sk_refcnt		__sk_common.skc_refcnt
 #define sk_hash			__sk_common.skc_hash
@@ -229,7 +236,9 @@ struct sock {
 	} sk_backlog;
 	wait_queue_head_t	*sk_sleep;
 	struct dst_entry	*sk_dst_cache;
+#ifdef CONFIG_XFRM
 	struct xfrm_policy	*sk_policy[2];
+#endif
 	rwlock_t		sk_dst_lock;
 	atomic_t		sk_rmem_alloc;
 	atomic_t		sk_wmem_alloc;
@@ -237,7 +246,9 @@ struct sock {
 	int			sk_sndbuf;
 	struct sk_buff_head	sk_receive_queue;
 	struct sk_buff_head	sk_write_queue;
+#ifdef CONFIG_NET_DMA
 	struct sk_buff_head	sk_async_wait_queue;
+#endif
 	int			sk_wmem_queued;
 	int			sk_forward_alloc;
 	gfp_t			sk_allocation;
@@ -269,7 +280,9 @@ struct sock {
 	struct sk_buff		*sk_send_head;
 	__u32			sk_sndmsg_off;
 	int			sk_write_pending;
+#ifdef CONFIG_SECURITY
 	void			*sk_security;
+#endif
 	__u32			sk_mark;
 	/* XXX 4 bytes hole on 64 bit */
 	void			(*sk_state_change)(struct sock *sk);
@@ -294,12 +307,30 @@ static inline struct sock *sk_head(const struct hlist_head *head)
 	return hlist_empty(head) ? NULL : __sk_head(head);
 }
 
+static inline struct sock *__sk_nulls_head(const struct hlist_nulls_head *head)
+{
+	return hlist_nulls_entry(head->first, struct sock, sk_nulls_node);
+}
+
+static inline struct sock *sk_nulls_head(const struct hlist_nulls_head *head)
+{
+	return hlist_nulls_empty(head) ? NULL : __sk_nulls_head(head);
+}
+
 static inline struct sock *sk_next(const struct sock *sk)
 {
 	return sk->sk_node.next ?
 		hlist_entry(sk->sk_node.next, struct sock, sk_node) : NULL;
 }
 
+static inline struct sock *sk_nulls_next(const struct sock *sk)
+{
+	return (!is_a_nulls(sk->sk_nulls_node.next)) ?
+		hlist_nulls_entry(sk->sk_nulls_node.next,
+				  struct sock, sk_nulls_node) :
+		NULL;
+}
+
 static inline int sk_unhashed(const struct sock *sk)
 {
 	return hlist_unhashed(&sk->sk_node);
@@ -315,6 +346,11 @@ static __inline__ void sk_node_init(struct hlist_node *node)
 	node->pprev = NULL;
 }
 
+static __inline__ void sk_nulls_node_init(struct hlist_nulls_node *node)
+{
+	node->pprev = NULL;
+}
+
 static __inline__ void __sk_del_node(struct sock *sk)
 {
 	__hlist_del(&sk->sk_node);
@@ -361,6 +397,27 @@ static __inline__ int sk_del_node_init(struct sock *sk)
 	return rc;
 }
 
+static __inline__ int __sk_nulls_del_node_init_rcu(struct sock *sk)
+{
+	if (sk_hashed(sk)) {
+		hlist_nulls_del_init_rcu(&sk->sk_nulls_node);
+		return 1;
+	}
+	return 0;
+}
+
+static __inline__ int sk_nulls_del_node_init_rcu(struct sock *sk)
+{
+	int rc = __sk_nulls_del_node_init_rcu(sk);
+
+	if (rc) {
+		/* paranoid for a while -acme */
+		WARN_ON(atomic_read(&sk->sk_refcnt) == 1);
+		__sock_put(sk);
+	}
+	return rc;
+}
+
 static __inline__ void __sk_add_node(struct sock *sk, struct hlist_head *list)
 {
 	hlist_add_head(&sk->sk_node, list);
@@ -372,6 +429,17 @@ static __inline__ void sk_add_node(struct sock *sk, struct hlist_head *list)
 	__sk_add_node(sk, list);
 }
 
+static __inline__ void __sk_nulls_add_node_rcu(struct sock *sk, struct hlist_nulls_head *list)
+{
+	hlist_nulls_add_head_rcu(&sk->sk_nulls_node, list);
+}
+
+static __inline__ void sk_nulls_add_node_rcu(struct sock *sk, struct hlist_nulls_head *list)
+{
+	sock_hold(sk);
+	__sk_nulls_add_node_rcu(sk, list);
+}
+
 static __inline__ void __sk_del_bind_node(struct sock *sk)
 {
 	__hlist_del(&sk->sk_bind_node);
@@ -385,9 +453,16 @@ static __inline__ void sk_add_bind_node(struct sock *sk,
 
 #define sk_for_each(__sk, node, list) \
 	hlist_for_each_entry(__sk, node, list, sk_node)
+#define sk_nulls_for_each(__sk, node, list) \
+	hlist_nulls_for_each_entry(__sk, node, list, sk_nulls_node)
+#define sk_nulls_for_each_rcu(__sk, node, list) \
+	hlist_nulls_for_each_entry_rcu(__sk, node, list, sk_nulls_node)
 #define sk_for_each_from(__sk, node) \
 	if (__sk && ({ node = &(__sk)->sk_node; 1; })) \
 		hlist_for_each_entry_from(__sk, node, sk_node)
+#define sk_nulls_for_each_from(__sk, node) \
+	if (__sk && ({ node = &(__sk)->sk_nulls_node; 1; })) \
+		hlist_nulls_for_each_entry_from(__sk, node, sk_nulls_node)
 #define sk_for_each_continue(__sk, node) \
 	if (__sk && ({ node = &(__sk)->sk_node; 1; })) \
 		hlist_for_each_entry_continue(__sk, node, sk_node)
@@ -574,7 +649,7 @@ struct proto {
 	/* Memory pressure */
 	void			(*enter_memory_pressure)(struct sock *sk);
 	atomic_t		*memory_allocated;	/* Current allocated memory. */
-	atomic_t		*sockets_allocated;	/* Current number of sockets. */
+	struct percpu_counter	*sockets_allocated;	/* Current number of sockets. */
 	/*
 	 * Pressure flag: try to collapse.
 	 * Technical note: it is used by multiple contexts non atomically.
@@ -587,17 +662,18 @@ struct proto {
 	int			*sysctl_rmem;
 	int			max_header;
 
-	struct kmem_cache		*slab;
+	struct kmem_cache	*slab;
 	unsigned int		obj_size;
+	int			slab_flags;
 
-	atomic_t		*orphan_count;
+	struct percpu_counter	*orphan_count;
 
 	struct request_sock_ops	*rsk_prot;
 	struct timewait_sock_ops *twsk_prot;
 
 	union {
 		struct inet_hashinfo	*hashinfo;
-		struct hlist_head	*udp_hash;
+		struct udp_table	*udp_table;
 		struct raw_hashinfo	*raw_hash;
 	} h;
 
@@ -815,7 +891,7 @@ static inline void sk_wmem_free_skb(struct sock *sk, struct sk_buff *skb)
  */
 #define sock_lock_init_class_and_name(sk, sname, skey, name, key) 	\
 do {									\
-	sk->sk_lock.owned = 0;					\
+	sk->sk_lock.owned = 0;						\
 	init_waitqueue_head(&sk->sk_lock.wq);				\
 	spin_lock_init(&(sk)->sk_lock.slock);				\
 	debug_check_no_locks_freed((void *)&(sk)->sk_lock,		\
@@ -936,7 +1012,6 @@ extern void sock_init_data(struct socket *sock, struct sock *sk);
 
 /**
  *	sk_filter_release: Release a socket filter
- *	@sk: socket
  *	@fp: filter to remove
  *
  *	Remove a filter from a socket and release its resources.
diff --git a/include/net/syncppp.h b/include/net/syncppp.h
deleted file mode 100644
index 9e306f7f579a..000000000000
--- a/include/net/syncppp.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Defines for synchronous PPP/Cisco link level subroutines.
- *
- * Copyright (C) 1994 Cronyx Ltd.
- * Author: Serge Vakulenko, <vak@zebub.msk.su>
- *
- * This software is distributed with NO WARRANTIES, not even the implied
- * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Authors grant any other persons or organizations permission to use
- * or modify this software as long as this message is kept with the software,
- * all derivative works or modified versions.
- *
- * Version 1.7, Wed Jun  7 22:12:02 MSD 1995
- *
- *
- *
- */
-
-#ifndef _SYNCPPP_H_
-#define _SYNCPPP_H_ 1
-
-#ifdef __KERNEL__
-struct slcp {
-	u16	state;          /* state machine */
-	u32	magic;          /* local magic number */
-	u_char	echoid;         /* id of last keepalive echo request */
-	u_char	confid;         /* id of last configuration request */
-};
-
-struct sipcp {
-	u16	state;          /* state machine */
-	u_char  confid;         /* id of last configuration request */
-};
-
-struct sppp 
-{
-	struct sppp *	pp_next;	/* next interface in keepalive list */
-	u32		pp_flags;	/* use Cisco protocol instead of PPP */
-	u16		pp_alivecnt;	/* keepalive packets counter */
-	u16		pp_loopcnt;	/* loopback detection counter */
-	u32		pp_seq;		/* local sequence number */
-	u32		pp_rseq;	/* remote sequence number */
-	struct slcp	lcp;		/* LCP params */
-	struct sipcp	ipcp;		/* IPCP params */
-	struct timer_list	pp_timer;
-	struct net_device	*pp_if;
-	char		pp_link_state;	/* Link status */
-	spinlock_t      lock;
-};
-
-struct ppp_device
-{	
-	struct net_device *dev;	/* Network device pointer */
-	struct sppp sppp;	/* Synchronous PPP */
-};
-
-static inline struct sppp *sppp_of(struct net_device *dev) 
-{
-	struct ppp_device **ppp = dev->ml_priv;
-	BUG_ON((*ppp)->dev != dev);
-	return &(*ppp)->sppp;
-}
-
-#define PP_KEEPALIVE    0x01    /* use keepalive protocol */
-#define PP_CISCO        0x02    /* use Cisco protocol instead of PPP */
-#define PP_TIMO         0x04    /* cp_timeout routine active */
-#define PP_DEBUG	0x08
-
-#define PPP_MTU          1500    /* max. transmit unit */
-
-#define LCP_STATE_CLOSED        0       /* LCP state: closed (conf-req sent) */
-#define LCP_STATE_ACK_RCVD      1       /* LCP state: conf-ack received */
-#define LCP_STATE_ACK_SENT      2       /* LCP state: conf-ack sent */
-#define LCP_STATE_OPENED        3       /* LCP state: opened */
-
-#define IPCP_STATE_CLOSED       0       /* IPCP state: closed (conf-req sent) */
-#define IPCP_STATE_ACK_RCVD     1       /* IPCP state: conf-ack received */
-#define IPCP_STATE_ACK_SENT     2       /* IPCP state: conf-ack sent */
-#define IPCP_STATE_OPENED       3       /* IPCP state: opened */
-
-#define SPPP_LINK_DOWN		0	/* link down - no keepalive */
-#define SPPP_LINK_UP		1	/* link is up - keepalive ok */
-
-void sppp_attach (struct ppp_device *pd);
-void sppp_detach (struct net_device *dev);
-int sppp_do_ioctl (struct net_device *dev, struct ifreq *ifr, int cmd);
-struct sk_buff *sppp_dequeue (struct net_device *dev);
-int sppp_isempty (struct net_device *dev);
-void sppp_flush (struct net_device *dev);
-int sppp_open (struct net_device *dev);
-int sppp_reopen (struct net_device *dev);
-int sppp_close (struct net_device *dev);
-#endif
-
-#define SPPPIOCCISCO	(SIOCDEVPRIVATE)
-#define SPPPIOCPPP	(SIOCDEVPRIVATE+1)
-#define SPPPIOCDEBUG	(SIOCDEVPRIVATE+2)
-#define SPPPIOCSFLAGS	(SIOCDEVPRIVATE+3)
-#define SPPPIOCGFLAGS	(SIOCDEVPRIVATE+4)
-
-#endif /* _SYNCPPP_H_ */
diff --git a/include/net/tcp.h b/include/net/tcp.h
index 438014d57610..218235de8963 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -46,7 +46,7 @@
 
 extern struct inet_hashinfo tcp_hashinfo;
 
-extern atomic_t tcp_orphan_count;
+extern struct percpu_counter tcp_orphan_count;
 extern void tcp_time_wait(struct sock *sk, int state, int timeo);
 
 #define MAX_TCP_HEADER	(128 + MAX_HEADER)
@@ -238,7 +238,7 @@ extern int sysctl_tcp_slow_start_after_idle;
 extern int sysctl_tcp_max_ssthresh;
 
 extern atomic_t tcp_memory_allocated;
-extern atomic_t tcp_sockets_allocated;
+extern struct percpu_counter tcp_sockets_allocated;
 extern int tcp_memory_pressure;
 
 /*
@@ -472,8 +472,6 @@ extern void tcp_send_delayed_ack(struct sock *sk);
 
 /* tcp_input.c */
 extern void tcp_cwnd_application_limited(struct sock *sk);
-extern void tcp_skb_mark_lost_uncond_verify(struct tcp_sock *tp,
-					    struct sk_buff *skb);
 
 /* tcp_timer.c */
 extern void tcp_init_xmit_timers(struct sock *);
@@ -590,7 +588,6 @@ struct tcp_skb_cb {
 #define TCPCB_EVER_RETRANS	0x80	/* Ever retransmitted frame	*/
 #define TCPCB_RETRANS		(TCPCB_SACKED_RETRANS|TCPCB_EVER_RETRANS)
 
-	__u16		urg_ptr;	/* Valid w/URG flags is set.	*/
 	__u32		ack_seq;	/* Sequence number ACK'd	*/
 };
 
@@ -764,8 +761,6 @@ static inline unsigned int tcp_packets_in_flight(const struct tcp_sock *tp)
 	return tp->packets_out - tcp_left_out(tp) + tp->retrans_out;
 }
 
-extern int tcp_limit_reno_sacked(struct tcp_sock *tp);
-
 /* If cwnd > ssthresh, we may raise ssthresh to be half-way to cwnd.
  * The exception is rate halving phase, when cwnd is decreasing towards
  * ssthresh.
@@ -1195,6 +1190,11 @@ static inline struct sk_buff *tcp_write_queue_next(struct sock *sk, struct sk_bu
 	return skb_queue_next(&sk->sk_write_queue, skb);
 }
 
+static inline struct sk_buff *tcp_write_queue_prev(struct sock *sk, struct sk_buff *skb)
+{
+	return skb_queue_prev(&sk->sk_write_queue, skb);
+}
+
 #define tcp_for_write_queue(skb, sk)					\
 	skb_queue_walk(&(sk)->sk_write_queue, skb)
 
@@ -1358,6 +1358,12 @@ extern void tcp_v4_destroy_sock(struct sock *sk);
 
 extern int tcp_v4_gso_send_check(struct sk_buff *skb);
 extern struct sk_buff *tcp_tso_segment(struct sk_buff *skb, int features);
+extern struct sk_buff **tcp_gro_receive(struct sk_buff **head,
+					struct sk_buff *skb);
+extern struct sk_buff **tcp4_gro_receive(struct sk_buff **head,
+					 struct sk_buff *skb);
+extern int tcp_gro_complete(struct sk_buff *skb);
+extern int tcp4_gro_complete(struct sk_buff *skb);
 
 #ifdef CONFIG_PROC_FS
 extern int  tcp4_proc_init(void);
diff --git a/include/net/timewait_sock.h b/include/net/timewait_sock.h
index 1e1ee3253fd8..97c3b14da55d 100644
--- a/include/net/timewait_sock.h
+++ b/include/net/timewait_sock.h
@@ -16,6 +16,7 @@
 
 struct timewait_sock_ops {
 	struct kmem_cache	*twsk_slab;
+	char		*twsk_slab_name;
 	unsigned int	twsk_obj_size;
 	int		(*twsk_unique)(struct sock *sk,
 				       struct sock *sktw, void *twp);
diff --git a/include/net/udp.h b/include/net/udp.h
index 1e205095ea68..90e6ce56be65 100644
--- a/include/net/udp.h
+++ b/include/net/udp.h
@@ -50,8 +50,15 @@ struct udp_skb_cb {
 };
 #define UDP_SKB_CB(__skb)	((struct udp_skb_cb *)((__skb)->cb))
 
-extern struct hlist_head udp_hash[UDP_HTABLE_SIZE];
-extern rwlock_t udp_hash_lock;
+struct udp_hslot {
+	struct hlist_nulls_head	head;
+	spinlock_t		lock;
+} __attribute__((aligned(2 * sizeof(long))));
+struct udp_table {
+	struct udp_hslot	hash[UDP_HTABLE_SIZE];
+};
+extern struct udp_table udp_table;
+extern void udp_table_init(struct udp_table *);
 
 
 /* Note: this must match 'valbool' in sock_setsockopt */
@@ -110,15 +117,7 @@ static inline void udp_lib_hash(struct sock *sk)
 	BUG();
 }
 
-static inline void udp_lib_unhash(struct sock *sk)
-{
-	write_lock_bh(&udp_hash_lock);
-	if (sk_del_node_init(sk)) {
-		inet_sk(sk)->num = 0;
-		sock_prot_inuse_add(sock_net(sk), sk->sk_prot, -1);
-	}
-	write_unlock_bh(&udp_hash_lock);
-}
+extern void udp_lib_unhash(struct sock *sk);
 
 static inline void udp_lib_close(struct sock *sk, long timeout)
 {
@@ -187,7 +186,7 @@ extern struct sock *udp4_lib_lookup(struct net *net, __be32 saddr, __be16 sport,
 struct udp_seq_afinfo {
 	char			*name;
 	sa_family_t		family;
-	struct hlist_head	*hashtable;
+	struct udp_table	*udp_table;
 	struct file_operations	seq_fops;
 	struct seq_operations	seq_ops;
 };
@@ -196,7 +195,7 @@ struct udp_iter_state {
 	struct seq_net_private  p;
 	sa_family_t		family;
 	int			bucket;
-	struct hlist_head	*hashtable;
+	struct udp_table	*udp_table;
 };
 
 #ifdef CONFIG_PROC_FS
diff --git a/include/net/udplite.h b/include/net/udplite.h
index b76b2e377af4..afdffe607b24 100644
--- a/include/net/udplite.h
+++ b/include/net/udplite.h
@@ -11,7 +11,7 @@
 #define UDPLITE_RECV_CSCOV   11 /* receiver partial coverage (threshold ) */
 
 extern struct proto 		udplite_prot;
-extern struct hlist_head 	udplite_hash[UDP_HTABLE_SIZE];
+extern struct udp_table		udplite_table;
 
 /*
  *	Checksum computation is all in software, hence simpler getfrag.
diff --git a/include/net/wireless.h b/include/net/wireless.h
index 721efb363db7..21c5d966142d 100644
--- a/include/net/wireless.h
+++ b/include/net/wireless.h
@@ -10,6 +10,7 @@
 #include <linux/netdevice.h>
 #include <linux/debugfs.h>
 #include <linux/list.h>
+#include <linux/ieee80211.h>
 #include <net/cfg80211.h>
 
 /**
@@ -133,23 +134,23 @@ struct ieee80211_rate {
 };
 
 /**
- * struct ieee80211_ht_info - describing STA's HT capabilities
+ * struct ieee80211_sta_ht_cap - STA's HT capabilities
  *
  * This structure describes most essential parameters needed
  * to describe 802.11n HT capabilities for an STA.
  *
- * @ht_supported: is HT supported by STA, 0: no, 1: yes
+ * @ht_supported: is HT supported by the STA
  * @cap: HT capabilities map as described in 802.11n spec
  * @ampdu_factor: Maximum A-MPDU length factor
  * @ampdu_density: Minimum A-MPDU spacing
- * @supp_mcs_set: Supported MCS set as described in 802.11n spec
+ * @mcs: Supported MCS rates
  */
-struct ieee80211_ht_info {
+struct ieee80211_sta_ht_cap {
 	u16 cap; /* use IEEE80211_HT_CAP_ */
-	u8 ht_supported;
+	bool ht_supported;
 	u8 ampdu_factor;
 	u8 ampdu_density;
-	u8 supp_mcs_set[16];
+	struct ieee80211_mcs_info mcs;
 };
 
 /**
@@ -173,13 +174,18 @@ struct ieee80211_supported_band {
 	enum ieee80211_band band;
 	int n_channels;
 	int n_bitrates;
-	struct ieee80211_ht_info ht_info;
+	struct ieee80211_sta_ht_cap ht_cap;
 };
 
 /**
  * struct wiphy - wireless hardware description
  * @idx: the wiphy index assigned to this item
  * @class_dev: the class device representing /sys/class/ieee80211/<wiphy-name>
+ * @fw_handles_regulatory: tells us the firmware for this device
+ * 	has its own regulatory solution and cannot identify the
+ * 	ISO / IEC 3166 alpha2 it belongs to. When this is enabled
+ * 	we will disregard the first regulatory hint (when the
+ * 	initiator is %REGDOM_SET_BY_CORE).
  * @reg_notifier: the driver's regulatory notification callback
  */
 struct wiphy {
@@ -191,6 +197,8 @@ struct wiphy {
 	/* Supported interface modes, OR together BIT(NL80211_IFTYPE_...) */
 	u16 interface_modes;
 
+	bool fw_handles_regulatory;
+
 	/* If multiple wiphys are registered and you're handed e.g.
 	 * a regular netdev with assigned ieee80211_ptr, you won't
 	 * know whether it points to a wiphy your driver has registered
@@ -262,9 +270,9 @@ static inline struct device *wiphy_dev(struct wiphy *wiphy)
 /**
  * wiphy_name - get wiphy name
  */
-static inline char *wiphy_name(struct wiphy *wiphy)
+static inline const char *wiphy_name(struct wiphy *wiphy)
 {
-	return wiphy->dev.bus_id;
+	return dev_name(&wiphy->dev);
 }
 
 /**
@@ -340,55 +348,51 @@ ieee80211_get_channel(struct wiphy *wiphy, int freq)
 }
 
 /**
- * __regulatory_hint - hint to the wireless core a regulatory domain
- * @wiphy: if a driver is providing the hint this is the driver's very
- * 	own &struct wiphy
- * @alpha2: the ISO/IEC 3166 alpha2 being claimed the regulatory domain
- * 	should be in. If @rd is set this should be NULL
- * @rd: a complete regulatory domain, if passed the caller need not worry
- * 	about freeing it
- *
- * The Wireless subsystem can use this function to hint to the wireless core
- * what it believes should be the current regulatory domain by
- * giving it an ISO/IEC 3166 alpha2 country code it knows its regulatory
- * domain should be in or by providing a completely build regulatory domain.
+ * ieee80211_get_response_rate - get basic rate for a given rate
  *
- * Returns -EALREADY if *a regulatory domain* has already been set. Note that
- * this could be by another driver. It is safe for drivers to continue if
- * -EALREADY is returned, if drivers are not capable of world roaming they
- * should not register more channels than they support. Right now we only
- * support listening to the first driver hint. If the driver is capable
- * of world roaming but wants to respect its own EEPROM mappings for
- * specific regulatory domains it should register the @reg_notifier callback
- * on the &struct wiphy. Returns 0 if the hint went through fine or through an
- * intersection operation. Otherwise a standard error code is returned.
+ * @sband: the band to look for rates in
+ * @basic_rates: bitmap of basic rates
+ * @bitrate: the bitrate for which to find the basic rate
  *
+ * This function returns the basic rate corresponding to a given
+ * bitrate, that is the next lower bitrate contained in the basic
+ * rate map, which is, for this function, given as a bitmap of
+ * indices of rates in the band's bitrate table.
  */
-extern int __regulatory_hint(struct wiphy *wiphy, enum reg_set_by set_by,
-		const char *alpha2, struct ieee80211_regdomain *rd);
+struct ieee80211_rate *
+ieee80211_get_response_rate(struct ieee80211_supported_band *sband,
+			    u64 basic_rates, int bitrate);
+
 /**
  * regulatory_hint - driver hint to the wireless core a regulatory domain
- * @wiphy: the driver's very own &struct wiphy
+ * @wiphy: the wireless device giving the hint (used only for reporting
+ *	conflicts)
  * @alpha2: the ISO/IEC 3166 alpha2 the driver claims its regulatory domain
  * 	should be in. If @rd is set this should be NULL. Note that if you
  * 	set this to NULL you should still set rd->alpha2 to some accepted
  * 	alpha2.
- * @rd: a complete regulatory domain provided by the driver. If passed
- * 	the driver does not need to worry about freeing it.
  *
  * Wireless drivers can use this function to hint to the wireless core
  * what it believes should be the current regulatory domain by
  * giving it an ISO/IEC 3166 alpha2 country code it knows its regulatory
  * domain should be in or by providing a completely build regulatory domain.
  * If the driver provides an ISO/IEC 3166 alpha2 userspace will be queried
- * for a regulatory domain structure for the respective country. If
- * a regulatory domain is build and passed you should set the alpha2
- * if possible, otherwise set it to the special value of "99" which tells
- * the wireless core it is unknown. If you pass a built regulatory domain
- * and we return non zero you are in charge of kfree()'ing the structure.
+ * for a regulatory domain structure for the respective country.
+ */
+extern void regulatory_hint(struct wiphy *wiphy, const char *alpha2);
+
+/**
+ * regulatory_hint_11d - hints a country IE as a regulatory domain
+ * @wiphy: the wireless device giving the hint (used only for reporting
+ *	conflicts)
+ * @country_ie: pointer to the country IE
+ * @country_ie_len: length of the country IE
  *
- * See __regulatory_hint() documentation for possible return values.
+ * We will intersect the rd with the what CRDA tells us should apply
+ * for the alpha2 this country IE belongs to, this prevents APs from
+ * sending us incorrect or outdated information against a country.
  */
-extern int regulatory_hint(struct wiphy *wiphy,
-		const char *alpha2, struct ieee80211_regdomain *rd);
+extern void regulatory_hint_11d(struct wiphy *wiphy,
+				u8 *country_ie,
+				u8 country_ie_len);
 #endif /* __NET_WIRELESS_H */
diff --git a/include/net/xfrm.h b/include/net/xfrm.h
index 11c890ad8ebb..2e9f5c0018ae 100644
--- a/include/net/xfrm.h
+++ b/include/net/xfrm.h
@@ -38,22 +38,15 @@
 	MODULE_ALIAS("xfrm-type-" __stringify(family) "-" __stringify(proto))
 
 #ifdef CONFIG_XFRM_STATISTICS
-DECLARE_SNMP_STAT(struct linux_xfrm_mib, xfrm_statistics);
-#define XFRM_INC_STATS(field)		SNMP_INC_STATS(xfrm_statistics, field)
-#define XFRM_INC_STATS_BH(field)	SNMP_INC_STATS_BH(xfrm_statistics, field)
-#define XFRM_INC_STATS_USER(field) 	SNMP_INC_STATS_USER(xfrm_statistics, field)
+#define XFRM_INC_STATS(net, field)	SNMP_INC_STATS((net)->mib.xfrm_statistics, field)
+#define XFRM_INC_STATS_BH(net, field)	SNMP_INC_STATS_BH((net)->mib.xfrm_statistics, field)
+#define XFRM_INC_STATS_USER(net, field)	SNMP_INC_STATS_USER((net)-mib.xfrm_statistics, field)
 #else
-#define XFRM_INC_STATS(field)
-#define XFRM_INC_STATS_BH(field)
-#define XFRM_INC_STATS_USER(field)
+#define XFRM_INC_STATS(net, field)	((void)(net))
+#define XFRM_INC_STATS_BH(net, field)	((void)(net))
+#define XFRM_INC_STATS_USER(net, field)	((void)(net))
 #endif
 
-extern struct sock *xfrm_nl;
-extern u32 sysctl_xfrm_aevent_etime;
-extern u32 sysctl_xfrm_aevent_rseqth;
-extern int sysctl_xfrm_larval_drop;
-extern u32 sysctl_xfrm_acq_expires;
-
 extern struct mutex xfrm_cfg_mutex;
 
 /* Organization of SPD aka "XFRM rules"
@@ -130,6 +123,9 @@ struct xfrm_state_walk {
 /* Full description of state of transformer. */
 struct xfrm_state
 {
+#ifdef CONFIG_NET_NS
+	struct net		*xs_net;
+#endif
 	union {
 		struct hlist_node	gclist;
 		struct hlist_node	bydst;
@@ -223,6 +219,11 @@ struct xfrm_state
 	void			*data;
 };
 
+static inline struct net *xs_net(struct xfrm_state *x)
+{
+	return read_pnet(&x->xs_net);
+}
+
 /* xflags - make enum if more show up */
 #define XFRM_TIME_DEFER	1
 
@@ -249,6 +250,7 @@ struct km_event
 	u32	seq;
 	u32	pid;
 	u32	event;
+	struct net *net;
 };
 
 struct net_device;
@@ -257,10 +259,11 @@ struct xfrm_dst;
 struct xfrm_policy_afinfo {
 	unsigned short		family;
 	struct dst_ops		*dst_ops;
-	void			(*garbage_collect)(void);
-	struct dst_entry	*(*dst_lookup)(int tos, xfrm_address_t *saddr,
+	void			(*garbage_collect)(struct net *net);
+	struct dst_entry	*(*dst_lookup)(struct net *net, int tos,
+					       xfrm_address_t *saddr,
 					       xfrm_address_t *daddr);
-	int			(*get_saddr)(xfrm_address_t *saddr, xfrm_address_t *daddr);
+	int			(*get_saddr)(struct net *net, xfrm_address_t *saddr, xfrm_address_t *daddr);
 	struct dst_entry	*(*find_bundle)(struct flowi *fl, struct xfrm_policy *policy);
 	void			(*decode_session)(struct sk_buff *skb,
 						  struct flowi *fl,
@@ -467,7 +470,9 @@ struct xfrm_policy_walk {
 
 struct xfrm_policy
 {
-	struct xfrm_policy	*next;
+#ifdef CONFIG_NET_NS
+	struct net		*xp_net;
+#endif
 	struct hlist_node	bydst;
 	struct hlist_node	byidx;
 
@@ -492,6 +497,11 @@ struct xfrm_policy
 	struct xfrm_tmpl       	xfrm_vec[XFRM_MAX_DEPTH];
 };
 
+static inline struct net *xp_net(struct xfrm_policy *xp)
+{
+	return read_pnet(&xp->xp_net);
+}
+
 struct xfrm_kmaddress {
 	xfrm_address_t          local;
 	xfrm_address_t          remote;
@@ -537,15 +547,13 @@ struct xfrm_mgr
 	struct xfrm_policy	*(*compile_policy)(struct sock *sk, int opt, u8 *data, int len, int *dir);
 	int			(*new_mapping)(struct xfrm_state *x, xfrm_address_t *ipaddr, __be16 sport);
 	int			(*notify_policy)(struct xfrm_policy *x, int dir, struct km_event *c);
-	int			(*report)(u8 proto, struct xfrm_selector *sel, xfrm_address_t *addr);
+	int			(*report)(struct net *net, u8 proto, struct xfrm_selector *sel, xfrm_address_t *addr);
 	int			(*migrate)(struct xfrm_selector *sel, u8 dir, u8 type, struct xfrm_migrate *m, int num_bundles, struct xfrm_kmaddress *k);
 };
 
 extern int xfrm_register_km(struct xfrm_mgr *km);
 extern int xfrm_unregister_km(struct xfrm_mgr *km);
 
-extern unsigned int xfrm_policy_count[XFRM_POLICY_MAX*2];
-
 /*
  * This structure is used for the duration where packets are being
  * transformed by IPsec.  As soon as the packet leaves IPsec the
@@ -882,6 +890,7 @@ struct xfrm_dst
 	u32 path_cookie;
 };
 
+#ifdef CONFIG_XFRM
 static inline void xfrm_dst_destroy(struct xfrm_dst *xdst)
 {
 	dst_release(xdst->route);
@@ -894,6 +903,7 @@ static inline void xfrm_dst_destroy(struct xfrm_dst *xdst)
 	xdst->partner = NULL;
 #endif
 }
+#endif
 
 extern void xfrm_dst_ifdown(struct dst_entry *dst, struct net_device *dev);
 
@@ -977,12 +987,13 @@ static inline int __xfrm_policy_check2(struct sock *sk, int dir,
 				       struct sk_buff *skb,
 				       unsigned int family, int reverse)
 {
+	struct net *net = dev_net(skb->dev);
 	int ndir = dir | (reverse ? XFRM_POLICY_MASK + 1 : 0);
 
 	if (sk && sk->sk_policy[XFRM_POLICY_IN])
 		return __xfrm_policy_check(sk, ndir, skb, family);
 
-	return	(!xfrm_policy_count[dir] && !skb->sp) ||
+	return	(!net->xfrm.policy_count[dir] && !skb->sp) ||
 		(skb->dst->flags & DST_NOPOLICY) ||
 		__xfrm_policy_check(sk, ndir, skb, family);
 }
@@ -1034,7 +1045,9 @@ extern int __xfrm_route_forward(struct sk_buff *skb, unsigned short family);
 
 static inline int xfrm_route_forward(struct sk_buff *skb, unsigned short family)
 {
-	return	!xfrm_policy_count[XFRM_POLICY_OUT] ||
+	struct net *net = dev_net(skb->dev);
+
+	return	!net->xfrm.policy_count[XFRM_POLICY_OUT] ||
 		(skb->dst->flags & DST_NOXFRM) ||
 		__xfrm_route_forward(skb, family);
 }
@@ -1268,7 +1281,8 @@ struct xfrm6_tunnel {
 
 extern void xfrm_init(void);
 extern void xfrm4_init(void);
-extern void xfrm_state_init(void);
+extern int xfrm_state_init(struct net *net);
+extern void xfrm_state_fini(struct net *net);
 extern void xfrm4_state_init(void);
 #ifdef CONFIG_XFRM
 extern int xfrm6_init(void);
@@ -1287,19 +1301,30 @@ static inline void xfrm6_fini(void)
 #endif
 
 #ifdef CONFIG_XFRM_STATISTICS
-extern int xfrm_proc_init(void);
+extern int xfrm_proc_init(struct net *net);
+extern void xfrm_proc_fini(struct net *net);
+#endif
+
+extern int xfrm_sysctl_init(struct net *net);
+#ifdef CONFIG_SYSCTL
+extern void xfrm_sysctl_fini(struct net *net);
+#else
+static inline void xfrm_sysctl_fini(struct net *net)
+{
+}
 #endif
 
 extern void xfrm_state_walk_init(struct xfrm_state_walk *walk, u8 proto);
-extern int xfrm_state_walk(struct xfrm_state_walk *walk,
+extern int xfrm_state_walk(struct net *net, struct xfrm_state_walk *walk,
 			   int (*func)(struct xfrm_state *, int, void*), void *);
 extern void xfrm_state_walk_done(struct xfrm_state_walk *walk);
-extern struct xfrm_state *xfrm_state_alloc(void);
+extern struct xfrm_state *xfrm_state_alloc(struct net *net);
 extern struct xfrm_state *xfrm_state_find(xfrm_address_t *daddr, xfrm_address_t *saddr, 
 					  struct flowi *fl, struct xfrm_tmpl *tmpl,
 					  struct xfrm_policy *pol, int *err,
 					  unsigned short family);
-extern struct xfrm_state * xfrm_stateonly_find(xfrm_address_t *daddr,
+extern struct xfrm_state * xfrm_stateonly_find(struct net *net,
+					       xfrm_address_t *daddr,
 					       xfrm_address_t *saddr,
 					       unsigned short family,
 					       u8 mode, u8 proto, u32 reqid);
@@ -1307,8 +1332,8 @@ extern int xfrm_state_check_expire(struct xfrm_state *x);
 extern void xfrm_state_insert(struct xfrm_state *x);
 extern int xfrm_state_add(struct xfrm_state *x);
 extern int xfrm_state_update(struct xfrm_state *x);
-extern struct xfrm_state *xfrm_state_lookup(xfrm_address_t *daddr, __be32 spi, u8 proto, unsigned short family);
-extern struct xfrm_state *xfrm_state_lookup_byaddr(xfrm_address_t *daddr, xfrm_address_t *saddr, u8 proto, unsigned short family);
+extern struct xfrm_state *xfrm_state_lookup(struct net *net, xfrm_address_t *daddr, __be32 spi, u8 proto, unsigned short family);
+extern struct xfrm_state *xfrm_state_lookup_byaddr(struct net *net, xfrm_address_t *daddr, xfrm_address_t *saddr, u8 proto, unsigned short family);
 #ifdef CONFIG_XFRM_SUB_POLICY
 extern int xfrm_tmpl_sort(struct xfrm_tmpl **dst, struct xfrm_tmpl **src,
 			  int n, unsigned short family);
@@ -1345,9 +1370,9 @@ struct xfrmk_spdinfo {
 	u32 spdhmcnt;
 };
 
-extern struct xfrm_state *xfrm_find_acq_byseq(u32 seq);
+extern struct xfrm_state *xfrm_find_acq_byseq(struct net *net, u32 seq);
 extern int xfrm_state_delete(struct xfrm_state *x);
-extern int xfrm_state_flush(u8 proto, struct xfrm_audit *audit_info);
+extern int xfrm_state_flush(struct net *net, u8 proto, struct xfrm_audit *audit_info);
 extern void xfrm_sad_getinfo(struct xfrmk_sadinfo *si);
 extern void xfrm_spd_getinfo(struct xfrmk_spdinfo *si);
 extern int xfrm_replay_check(struct xfrm_state *x,
@@ -1415,22 +1440,22 @@ static inline int xfrm4_udp_encap_rcv(struct sock *sk, struct sk_buff *skb)
 }
 #endif
 
-struct xfrm_policy *xfrm_policy_alloc(gfp_t gfp);
+struct xfrm_policy *xfrm_policy_alloc(struct net *net, gfp_t gfp);
 
 extern void xfrm_policy_walk_init(struct xfrm_policy_walk *walk, u8 type);
-extern int xfrm_policy_walk(struct xfrm_policy_walk *walk,
+extern int xfrm_policy_walk(struct net *net, struct xfrm_policy_walk *walk,
 	int (*func)(struct xfrm_policy *, int, int, void*), void *);
 extern void xfrm_policy_walk_done(struct xfrm_policy_walk *walk);
 int xfrm_policy_insert(int dir, struct xfrm_policy *policy, int excl);
-struct xfrm_policy *xfrm_policy_bysel_ctx(u8 type, int dir,
+struct xfrm_policy *xfrm_policy_bysel_ctx(struct net *net, u8 type, int dir,
 					  struct xfrm_selector *sel,
 					  struct xfrm_sec_ctx *ctx, int delete,
 					  int *err);
-struct xfrm_policy *xfrm_policy_byid(u8, int dir, u32 id, int delete, int *err);
-int xfrm_policy_flush(u8 type, struct xfrm_audit *audit_info);
+struct xfrm_policy *xfrm_policy_byid(struct net *net, u8, int dir, u32 id, int delete, int *err);
+int xfrm_policy_flush(struct net *net, u8 type, struct xfrm_audit *audit_info);
 u32 xfrm_get_acqseq(void);
 extern int xfrm_alloc_spi(struct xfrm_state *x, u32 minspi, u32 maxspi);
-struct xfrm_state * xfrm_find_acq(u8 mode, u32 reqid, u8 proto,
+struct xfrm_state * xfrm_find_acq(struct net *net, u8 mode, u32 reqid, u8 proto,
 				  xfrm_address_t *daddr, xfrm_address_t *saddr,
 				  int create, unsigned short family);
 extern int xfrm_sk_policy_insert(struct sock *sk, int dir, struct xfrm_policy *pol);
@@ -1449,10 +1474,9 @@ extern int xfrm_migrate(struct xfrm_selector *sel, u8 dir, u8 type,
 			struct xfrm_kmaddress *k);
 #endif
 
-extern wait_queue_head_t km_waitq;
 extern int km_new_mapping(struct xfrm_state *x, xfrm_address_t *ipaddr, __be16 sport);
 extern void km_policy_expired(struct xfrm_policy *pol, int dir, int hard, u32 pid);
-extern int km_report(u8 proto, struct xfrm_selector *sel, xfrm_address_t *addr);
+extern int km_report(struct net *net, u8 proto, struct xfrm_selector *sel, xfrm_address_t *addr);
 
 extern void xfrm_input_init(void);
 extern int xfrm_parse_spi(struct sk_buff *skb, u8 nexthdr, __be32 *spi, __be32 *seq);
@@ -1497,18 +1521,20 @@ static inline int xfrm_policy_id2dir(u32 index)
 	return index & 7;
 }
 
-static inline int xfrm_aevent_is_on(void)
+#ifdef CONFIG_XFRM
+static inline int xfrm_aevent_is_on(struct net *net)
 {
 	struct sock *nlsk;
 	int ret = 0;
 
 	rcu_read_lock();
-	nlsk = rcu_dereference(xfrm_nl);
+	nlsk = rcu_dereference(net->xfrm.nlsk);
 	if (nlsk)
 		ret = netlink_has_listeners(nlsk, XFRMNLGRP_AEVENTS);
 	rcu_read_unlock();
 	return ret;
 }
+#endif
 
 static inline int xfrm_alg_len(struct xfrm_algo *alg)
 {
@@ -1536,9 +1562,11 @@ static inline void xfrm_states_delete(struct xfrm_state **states, int n)
 }
 #endif
 
+#ifdef CONFIG_XFRM
 static inline struct xfrm_state *xfrm_input_state(struct sk_buff *skb)
 {
 	return skb->sp->xvec[skb->sp->len - 1];
 }
+#endif
 
 #endif	/* _NET_XFRM_H */
diff --git a/include/scsi/fc/fc_els.h b/include/scsi/fc/fc_els.h
new file mode 100644
index 000000000000..195ca014d3ce
--- /dev/null
+++ b/include/scsi/fc/fc_els.h
@@ -0,0 +1,816 @@
+/*
+ * Copyright(c) 2007 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Maintained at www.Open-FCoE.org
+ */
+
+#ifndef _FC_ELS_H_
+#define	_FC_ELS_H_
+
+/*
+ * Fibre Channel Switch - Enhanced Link Services definitions.
+ * From T11 FC-LS Rev 1.2 June 7, 2005.
+ */
+
+/*
+ * ELS Command codes - byte 0 of the frame payload
+ */
+enum fc_els_cmd {
+	ELS_LS_RJT =	0x01,	/* ESL reject */
+	ELS_LS_ACC =	0x02,	/* ESL Accept */
+	ELS_PLOGI =	0x03,	/* N_Port login */
+	ELS_FLOGI =	0x04,	/* F_Port login */
+	ELS_LOGO =	0x05,	/* Logout */
+	ELS_ABTX =	0x06,	/* Abort exchange - obsolete */
+	ELS_RCS =	0x07,	/* read connection status */
+	ELS_RES =	0x08,	/* read exchange status block */
+	ELS_RSS =	0x09,	/* read sequence status block */
+	ELS_RSI =	0x0a,	/* read sequence initiative */
+	ELS_ESTS =	0x0b,	/* establish streaming */
+	ELS_ESTC =	0x0c,	/* estimate credit */
+	ELS_ADVC =	0x0d,	/* advise credit */
+	ELS_RTV =	0x0e,	/* read timeout value */
+	ELS_RLS =	0x0f,	/* read link error status block */
+	ELS_ECHO =	0x10,	/* echo */
+	ELS_TEST =	0x11,	/* test */
+	ELS_RRQ =	0x12,	/* reinstate recovery qualifier */
+	ELS_REC =	0x13,	/* read exchange concise */
+	ELS_SRR =	0x14,	/* sequence retransmission request */
+	ELS_PRLI =	0x20,	/* process login */
+	ELS_PRLO =	0x21,	/* process logout */
+	ELS_SCN =	0x22,	/* state change notification */
+	ELS_TPLS =	0x23,	/* test process login state */
+	ELS_TPRLO =	0x24,	/* third party process logout */
+	ELS_LCLM =	0x25,	/* login control list mgmt (obs) */
+	ELS_GAID =	0x30,	/* get alias_ID */
+	ELS_FACT =	0x31,	/* fabric activate alias_id */
+	ELS_FDACDT =	0x32,	/* fabric deactivate alias_id */
+	ELS_NACT =	0x33,	/* N-port activate alias_id */
+	ELS_NDACT =	0x34,	/* N-port deactivate alias_id */
+	ELS_QOSR =	0x40,	/* quality of service request */
+	ELS_RVCS =	0x41,	/* read virtual circuit status */
+	ELS_PDISC =	0x50,	/* discover N_port service params */
+	ELS_FDISC =	0x51,	/* discover F_port service params */
+	ELS_ADISC =	0x52,	/* discover address */
+	ELS_RNC =	0x53,	/* report node cap (obs) */
+	ELS_FARP_REQ =	0x54,	/* FC ARP request */
+	ELS_FARP_REPL =	0x55,	/* FC ARP reply */
+	ELS_RPS =	0x56,	/* read port status block */
+	ELS_RPL =	0x57,	/* read port list */
+	ELS_RPBC =	0x58,	/* read port buffer condition */
+	ELS_FAN =	0x60,	/* fabric address notification */
+	ELS_RSCN =	0x61,	/* registered state change notification */
+	ELS_SCR =	0x62,	/* state change registration */
+	ELS_RNFT =	0x63,	/* report node FC-4 types */
+	ELS_CSR =	0x68,	/* clock synch. request */
+	ELS_CSU =	0x69,	/* clock synch. update */
+	ELS_LINIT =	0x70,	/* loop initialize */
+	ELS_LSTS =	0x72,	/* loop status */
+	ELS_RNID =	0x78,	/* request node ID data */
+	ELS_RLIR =	0x79,	/* registered link incident report */
+	ELS_LIRR =	0x7a,	/* link incident record registration */
+	ELS_SRL =	0x7b,	/* scan remote loop */
+	ELS_SBRP =	0x7c,	/* set bit-error reporting params */
+	ELS_RPSC =	0x7d,	/* report speed capabilities */
+	ELS_QSA =	0x7e,	/* query security attributes */
+	ELS_EVFP =	0x7f,	/* exchange virt. fabrics params */
+	ELS_LKA =	0x80,	/* link keep-alive */
+	ELS_AUTH_ELS =	0x90,	/* authentication ELS */
+};
+
+/*
+ * Initializer useful for decoding table.
+ * Please keep this in sync with the above definitions.
+ */
+#define	FC_ELS_CMDS_INIT {			\
+	[ELS_LS_RJT] =	"LS_RJT",		\
+	[ELS_LS_ACC] =	"LS_ACC",		\
+	[ELS_PLOGI] =	"PLOGI",		\
+	[ELS_FLOGI] =	"FLOGI",		\
+	[ELS_LOGO] =	"LOGO",			\
+	[ELS_ABTX] =	"ABTX",			\
+	[ELS_RCS] =	"RCS",			\
+	[ELS_RES] =	"RES",			\
+	[ELS_RSS] =	"RSS",			\
+	[ELS_RSI] =	"RSI",			\
+	[ELS_ESTS] =	"ESTS",			\
+	[ELS_ESTC] =	"ESTC",			\
+	[ELS_ADVC] =	"ADVC",			\
+	[ELS_RTV] =	"RTV",			\
+	[ELS_RLS] =	"RLS",			\
+	[ELS_ECHO] =	"ECHO",			\
+	[ELS_TEST] =	"TEST",			\
+	[ELS_RRQ] =	"RRQ",			\
+	[ELS_REC] =	"REC",			\
+	[ELS_SRR] =	"SRR",			\
+	[ELS_PRLI] =	"PRLI",			\
+	[ELS_PRLO] =	"PRLO",			\
+	[ELS_SCN] =	"SCN",			\
+	[ELS_TPLS] =	"TPLS",			\
+	[ELS_TPRLO] =	"TPRLO",		\
+	[ELS_LCLM] =	"LCLM",			\
+	[ELS_GAID] =	"GAID",			\
+	[ELS_FACT] =	"FACT",			\
+	[ELS_FDACDT] =	"FDACDT",		\
+	[ELS_NACT] =	"NACT",			\
+	[ELS_NDACT] =	"NDACT",		\
+	[ELS_QOSR] =	"QOSR",			\
+	[ELS_RVCS] =	"RVCS",			\
+	[ELS_PDISC] =	"PDISC",		\
+	[ELS_FDISC] =	"FDISC",		\
+	[ELS_ADISC] =	"ADISC",		\
+	[ELS_RNC] =	"RNC",			\
+	[ELS_FARP_REQ] = "FARP_REQ",		\
+	[ELS_FARP_REPL] =  "FARP_REPL",		\
+	[ELS_RPS] =	"RPS",			\
+	[ELS_RPL] =	"RPL",			\
+	[ELS_RPBC] =	"RPBC",			\
+	[ELS_FAN] =	"FAN",			\
+	[ELS_RSCN] =	"RSCN",			\
+	[ELS_SCR] =	"SCR",			\
+	[ELS_RNFT] =	"RNFT",			\
+	[ELS_CSR] =	"CSR",			\
+	[ELS_CSU] =	"CSU",			\
+	[ELS_LINIT] =	"LINIT",		\
+	[ELS_LSTS] =	"LSTS",			\
+	[ELS_RNID] =	"RNID",			\
+	[ELS_RLIR] =	"RLIR",			\
+	[ELS_LIRR] =	"LIRR",			\
+	[ELS_SRL] =	"SRL",			\
+	[ELS_SBRP] =	"SBRP",			\
+	[ELS_RPSC] =	"RPSC",			\
+	[ELS_QSA] =	"QSA",			\
+	[ELS_EVFP] =	"EVFP",			\
+	[ELS_LKA] =	"LKA",			\
+	[ELS_AUTH_ELS] = "AUTH_ELS",		\
+}
+
+/*
+ * LS_ACC payload.
+ */
+struct fc_els_ls_acc {
+	__u8          la_cmd;		/* command code ELS_LS_ACC */
+	__u8          la_resv[3];	/* reserved */
+};
+
+/*
+ * ELS reject payload.
+ */
+struct fc_els_ls_rjt {
+	__u8	er_cmd;		/* command code ELS_LS_RJT */
+	__u8	er_resv[4];	/* reserved must be zero */
+	__u8	er_reason;	/* reason (enum fc_els_rjt_reason below) */
+	__u8	er_explan;	/* explanation (enum fc_els_rjt_explan below) */
+	__u8	er_vendor;	/* vendor specific code */
+};
+
+/*
+ * ELS reject reason codes (er_reason).
+ */
+enum fc_els_rjt_reason {
+	ELS_RJT_NONE =		0,	/* no reject - not to be sent */
+	ELS_RJT_INVAL =		0x01,	/* invalid ELS command code */
+	ELS_RJT_LOGIC =		0x03,	/* logical error */
+	ELS_RJT_BUSY =		0x05,	/* logical busy */
+	ELS_RJT_PROT =		0x07,	/* protocol error */
+	ELS_RJT_UNAB =		0x09,	/* unable to perform command request */
+	ELS_RJT_UNSUP =		0x0b,	/* command not supported */
+	ELS_RJT_INPROG =	0x0e,	/* command already in progress */
+	ELS_RJT_VENDOR =	0xff,	/* vendor specific error */
+};
+
+
+/*
+ * reason code explanation (er_explan).
+ */
+enum fc_els_rjt_explan {
+	ELS_EXPL_NONE =		0x00,	/* No additional explanation */
+	ELS_EXPL_SPP_OPT_ERR =	0x01,	/* service parameter error - options */
+	ELS_EXPL_SPP_ICTL_ERR =	0x03,	/* service parm error - initiator ctl */
+	ELS_EXPL_AH =		0x11,	/* invalid association header */
+	ELS_EXPL_AH_REQ =	0x13,	/* association_header required */
+	ELS_EXPL_SID =		0x15,	/* invalid originator S_ID */
+	ELS_EXPL_OXID_RXID =	0x17,	/* invalid OX_ID-RX_ID combination */
+	ELS_EXPL_INPROG =	0x19,	/* Request already in progress */
+	ELS_EXPL_PLOGI_REQD =	0x1e,	/* N_Port login required */
+	ELS_EXPL_INSUF_RES =	0x29,	/* insufficient resources */
+	ELS_EXPL_UNAB_DATA =	0x2a,	/* unable to supply requested data */
+	ELS_EXPL_UNSUPR =	0x2c,	/* Request not supported */
+	ELS_EXPL_INV_LEN =	0x2d,	/* Invalid payload length */
+	/* TBD - above definitions incomplete */
+};
+
+/*
+ * Common service parameters (N ports).
+ */
+struct fc_els_csp {
+	__u8		sp_hi_ver;	/* highest version supported (obs.) */
+	__u8		sp_lo_ver;	/* highest version supported (obs.) */
+	__be16		sp_bb_cred;	/* buffer-to-buffer credits */
+	__be16		sp_features;	/* common feature flags */
+	__be16		sp_bb_data;	/* b-b state number and data field sz */
+	union {
+		struct {
+			__be16	_sp_tot_seq; /* total concurrent sequences */
+			__be16	_sp_rel_off; /* rel. offset by info cat */
+		} sp_plogi;
+		struct {
+			__be32	_sp_r_a_tov; /* resource alloc. timeout msec */
+		} sp_flogi_acc;
+	} sp_u;
+	__be32		sp_e_d_tov;	/* error detect timeout value */
+};
+#define	sp_tot_seq	sp_u.sp_plogi._sp_tot_seq
+#define	sp_rel_off	sp_u.sp_plogi._sp_rel_off
+#define	sp_r_a_tov	sp_u.sp_flogi_acc._sp_r_a_tov
+
+#define	FC_SP_BB_DATA_MASK 0xfff /* mask for data field size in sp_bb_data */
+
+/*
+ * Minimum and maximum values for max data field size in service parameters.
+ */
+#define	FC_SP_MIN_MAX_PAYLOAD	FC_MIN_MAX_PAYLOAD
+#define	FC_SP_MAX_MAX_PAYLOAD	FC_MAX_PAYLOAD
+
+/*
+ * sp_features
+ */
+#define	FC_SP_FT_CIRO	0x8000	/* continuously increasing rel. off. */
+#define	FC_SP_FT_CLAD	0x8000	/* clean address (in FLOGI LS_ACC) */
+#define	FC_SP_FT_RAND	0x4000	/* random relative offset */
+#define	FC_SP_FT_VAL	0x2000	/* valid vendor version level */
+#define	FC_SP_FT_FPORT	0x1000	/* F port (1) vs. N port (0) */
+#define	FC_SP_FT_ABB	0x0800	/* alternate BB_credit management */
+#define	FC_SP_FT_EDTR	0x0400	/* E_D_TOV Resolution is nanoseconds */
+#define	FC_SP_FT_MCAST	0x0200	/* multicast */
+#define	FC_SP_FT_BCAST	0x0100	/* broadcast */
+#define	FC_SP_FT_HUNT	0x0080	/* hunt group */
+#define	FC_SP_FT_SIMP	0x0040	/* dedicated simplex */
+#define	FC_SP_FT_SEC	0x0020	/* reserved for security */
+#define	FC_SP_FT_CSYN	0x0010	/* clock synch. supported */
+#define	FC_SP_FT_RTTOV	0x0008	/* R_T_TOV value 100 uS, else 100 mS */
+#define	FC_SP_FT_HALF	0x0004	/* dynamic half duplex */
+#define	FC_SP_FT_SEQC	0x0002	/* SEQ_CNT */
+#define	FC_SP_FT_PAYL	0x0001	/* FLOGI payload length 256, else 116 */
+
+/*
+ * Class-specific service parameters.
+ */
+struct fc_els_cssp {
+	__be16		cp_class;	/* class flags */
+	__be16		cp_init;	/* initiator flags */
+	__be16		cp_recip;	/* recipient flags */
+	__be16		cp_rdfs;	/* receive data field size */
+	__be16		cp_con_seq;	/* concurrent sequences */
+	__be16		cp_ee_cred;	/* N-port end-to-end credit */
+	__u8		cp_resv1;	/* reserved */
+	__u8		cp_open_seq;	/* open sequences per exchange */
+	__u8		_cp_resv2[2];	/* reserved */
+};
+
+/*
+ * cp_class flags.
+ */
+#define	FC_CPC_VALID	0x8000		/* class valid */
+#define	FC_CPC_IMIX	0x4000		/* intermix mode */
+#define	FC_CPC_SEQ	0x0800		/* sequential delivery */
+#define	FC_CPC_CAMP	0x0200		/* camp-on */
+#define	FC_CPC_PRI	0x0080		/* priority */
+
+/*
+ * cp_init flags.
+ * (TBD: not all flags defined here).
+ */
+#define	FC_CPI_CSYN	0x0010		/* clock synch. capable */
+
+/*
+ * cp_recip flags.
+ */
+#define	FC_CPR_CSYN	0x0008		/* clock synch. capable */
+
+/*
+ * NFC_ELS_FLOGI: Fabric login request.
+ * NFC_ELS_PLOGI: Port login request (same format).
+ */
+struct fc_els_flogi {
+	__u8		fl_cmd;		/* command */
+	__u8		_fl_resvd[3];	/* must be zero */
+	struct fc_els_csp fl_csp;	/* common service parameters */
+	__be64		fl_wwpn;	/* port name */
+	__be64		fl_wwnn;	/* node name */
+	struct fc_els_cssp fl_cssp[4];	/* class 1-4 service parameters */
+	__u8		fl_vend[16];	/* vendor version level */
+} __attribute__((__packed__));
+
+/*
+ * Process login service parameter page.
+ */
+struct fc_els_spp {
+	__u8		spp_type;	/* type code or common service params */
+	__u8		spp_type_ext;	/* type code extension */
+	__u8		spp_flags;
+	__u8		_spp_resvd;
+	__be32		spp_orig_pa;	/* originator process associator */
+	__be32		spp_resp_pa;	/* responder process associator */
+	__be32		spp_params;	/* service parameters */
+};
+
+/*
+ * spp_flags.
+ */
+#define	FC_SPP_OPA_VAL	    0x80	/* originator proc. assoc. valid */
+#define	FC_SPP_RPA_VAL	    0x40	/* responder proc. assoc. valid */
+#define	FC_SPP_EST_IMG_PAIR 0x20	/* establish image pair */
+#define	FC_SPP_RESP_MASK    0x0f	/* mask for response code (below) */
+
+/*
+ * SPP response code in spp_flags - lower 4 bits.
+ */
+enum fc_els_spp_resp {
+	FC_SPP_RESP_ACK	=	1,	/* request executed */
+	FC_SPP_RESP_RES =	2,	/* unable due to lack of resources */
+	FC_SPP_RESP_INIT =	3,	/* initialization not complete */
+	FC_SPP_RESP_NO_PA = 	4,	/* unknown process associator */
+	FC_SPP_RESP_CONF = 	5,	/* configuration precludes image pair */
+	FC_SPP_RESP_COND = 	6,	/* request completed conditionally */
+	FC_SPP_RESP_MULT = 	7,	/* unable to handle multiple SPPs */
+	FC_SPP_RESP_INVL = 	8,	/* SPP is invalid */
+};
+
+/*
+ * ELS_RRQ - Reinstate Recovery Qualifier
+ */
+struct fc_els_rrq {
+	__u8		rrq_cmd;	/* command (0x12) */
+	__u8		rrq_zero[3];	/* specified as zero - part of cmd */
+	__u8		rrq_resvd;	/* reserved */
+	__u8		rrq_s_id[3];	/* originator FID */
+	__be16		rrq_ox_id;	/* originator exchange ID */
+	__be16		rrq_rx_id;	/* responders exchange ID */
+};
+
+/*
+ * ELS_REC - Read exchange concise.
+ */
+struct fc_els_rec {
+	__u8		rec_cmd;	/* command (0x13) */
+	__u8		rec_zero[3];	/* specified as zero - part of cmd */
+	__u8		rec_resvd;	/* reserved */
+	__u8		rec_s_id[3];	/* originator FID */
+	__be16		rec_ox_id;	/* originator exchange ID */
+	__be16		rec_rx_id;	/* responders exchange ID */
+};
+
+/*
+ * ELS_REC LS_ACC payload.
+ */
+struct fc_els_rec_acc {
+	__u8		reca_cmd;	/* accept (0x02) */
+	__u8		reca_zero[3];	/* specified as zero - part of cmd */
+	__be16		reca_ox_id;	/* originator exchange ID */
+	__be16		reca_rx_id;	/* responders exchange ID */
+	__u8		reca_resvd1;	/* reserved */
+	__u8		reca_ofid[3];	/* originator FID */
+	__u8		reca_resvd2;	/* reserved */
+	__u8		reca_rfid[3];	/* responder FID */
+	__be32		reca_fc4value;	/* FC4 value */
+	__be32		reca_e_stat;	/* ESB (exchange status block) status */
+};
+
+/*
+ * ELS_PRLI - Process login request and response.
+ */
+struct fc_els_prli {
+	__u8		prli_cmd;	/* command */
+	__u8		prli_spp_len;	/* length of each serv. parm. page */
+	__be16		prli_len;	/* length of entire payload */
+	/* service parameter pages follow */
+};
+
+/*
+ * ELS_ADISC payload
+ */
+struct fc_els_adisc {
+	__u8		adisc_cmd;
+	__u8		adisc_resv[3];
+	__u8            adisc_resv1;
+	__u8            adisc_hard_addr[3];
+	__be64          adisc_wwpn;
+	__be64          adisc_wwnn;
+	__u8            adisc_resv2;
+	__u8            adisc_port_id[3];
+} __attribute__((__packed__));
+
+/*
+ * ELS_LOGO - process or fabric logout.
+ */
+struct fc_els_logo {
+	__u8		fl_cmd;		/* command code */
+	__u8		fl_zero[3];	/* specified as zero - part of cmd */
+	__u8		fl_resvd;	/* reserved */
+	__u8		fl_n_port_id[3];/* N port ID */
+	__be64		fl_n_port_wwn;	/* port name */
+};
+
+/*
+ * ELS_RTV - read timeout value.
+ */
+struct fc_els_rtv {
+	__u8		rtv_cmd;	/* command code 0x0e */
+	__u8		rtv_zero[3];	/* specified as zero - part of cmd */
+};
+
+/*
+ * LS_ACC for ELS_RTV - read timeout value.
+ */
+struct fc_els_rtv_acc {
+	__u8		rtv_cmd;	/* command code 0x02 */
+	__u8		rtv_zero[3];	/* specified as zero - part of cmd */
+	__be32		rtv_r_a_tov;	/* resource allocation timeout value */
+	__be32		rtv_e_d_tov;	/* error detection timeout value */
+	__be32		rtv_toq;	/* timeout qualifier (see below) */
+};
+
+/*
+ * rtv_toq bits.
+ */
+#define	FC_ELS_RTV_EDRES (1 << 26)	/* E_D_TOV resolution is nS else mS */
+#define	FC_ELS_RTV_RTTOV (1 << 19)	/* R_T_TOV is 100 uS else 100 mS */
+
+/*
+ * ELS_SCR - state change registration payload.
+ */
+struct fc_els_scr {
+	__u8		scr_cmd;	/* command code */
+	__u8		scr_resv[6];	/* reserved */
+	__u8		scr_reg_func;	/* registration function (see below) */
+};
+
+enum fc_els_scr_func {
+	ELS_SCRF_FAB =	1,	/* fabric-detected registration */
+	ELS_SCRF_NPORT = 2,	/* Nx_Port-detected registration */
+	ELS_SCRF_FULL =	3,	/* full registration */
+	ELS_SCRF_CLEAR = 255,	/* remove any current registrations */
+};
+
+/*
+ * ELS_RSCN - registered state change notification payload.
+ */
+struct fc_els_rscn {
+	__u8		rscn_cmd;	/* RSCN opcode (0x61) */
+	__u8		rscn_page_len;	/* page length (4) */
+	__be16		rscn_plen;	/* payload length including this word */
+
+	/* followed by 4-byte generic affected Port_ID pages */
+};
+
+struct fc_els_rscn_page {
+	__u8		rscn_page_flags; /* event and address format */
+	__u8		rscn_fid[3];	/* fabric ID */
+};
+
+#define	ELS_RSCN_EV_QUAL_BIT	2	/* shift count for event qualifier */
+#define	ELS_RSCN_EV_QUAL_MASK	0xf	/* mask for event qualifier */
+#define	ELS_RSCN_ADDR_FMT_BIT	0	/* shift count for address format */
+#define	ELS_RSCN_ADDR_FMT_MASK	0x3	/* mask for address format */
+
+enum fc_els_rscn_ev_qual {
+	ELS_EV_QUAL_NONE = 0,		/* unspecified */
+	ELS_EV_QUAL_NS_OBJ = 1,		/* changed name server object */
+	ELS_EV_QUAL_PORT_ATTR = 2,	/* changed port attribute */
+	ELS_EV_QUAL_SERV_OBJ = 3,	/* changed service object */
+	ELS_EV_QUAL_SW_CONFIG = 4,	/* changed switch configuration */
+	ELS_EV_QUAL_REM_OBJ = 5,	/* removed object */
+};
+
+enum fc_els_rscn_addr_fmt {
+	ELS_ADDR_FMT_PORT = 0,	/* rscn_fid is a port address */
+	ELS_ADDR_FMT_AREA = 1,	/* rscn_fid is a area address */
+	ELS_ADDR_FMT_DOM = 2,	/* rscn_fid is a domain address */
+	ELS_ADDR_FMT_FAB = 3,	/* anything on fabric may have changed */
+};
+
+/*
+ * ELS_RNID - request Node ID.
+ */
+struct fc_els_rnid {
+	__u8		rnid_cmd;	/* RNID opcode (0x78) */
+	__u8		rnid_resv[3];	/* reserved */
+	__u8		rnid_fmt;	/* data format */
+	__u8		rnid_resv2[3];	/* reserved */
+};
+
+/*
+ * Node Identification Data formats (rnid_fmt)
+ */
+enum fc_els_rnid_fmt {
+	ELS_RNIDF_NONE = 0,		/* no specific identification data */
+	ELS_RNIDF_GEN = 0xdf,		/* general topology discovery format */
+};
+
+/*
+ * ELS_RNID response.
+ */
+struct fc_els_rnid_resp {
+	__u8		rnid_cmd;	/* response code (LS_ACC) */
+	__u8		rnid_resv[3];	/* reserved */
+	__u8		rnid_fmt;	/* data format */
+	__u8		rnid_cid_len;	/* common ID data length */
+	__u8		rnid_resv2;	/* reserved */
+	__u8		rnid_sid_len;	/* specific ID data length */
+};
+
+struct fc_els_rnid_cid {
+	__be64		rnid_wwpn;	/* N port name */
+	__be64		rnid_wwnn;	/* node name */
+};
+
+struct fc_els_rnid_gen {
+	__u8		rnid_vend_id[16]; /* vendor-unique ID */
+	__be32		rnid_atype;	/* associated type (see below) */
+	__be32		rnid_phys_port;	/* physical port number */
+	__be32		rnid_att_nodes;	/* number of attached nodes */
+	__u8		rnid_node_mgmt;	/* node management (see below) */
+	__u8		rnid_ip_ver;	/* IP version (see below) */
+	__be16		rnid_prot_port;	/* UDP / TCP port number */
+	__be32		rnid_ip_addr[4]; /* IP address */
+	__u8		rnid_resvd[2];	/* reserved */
+	__be16		rnid_vend_spec;	/* vendor-specific field */
+};
+
+enum fc_els_rnid_atype {
+	ELS_RNIDA_UNK =		0x01,	/* unknown */
+	ELS_RNIDA_OTHER =	0x02,	/* none of the following */
+	ELS_RNIDA_HUB =		0x03,
+	ELS_RNIDA_SWITCH =	0x04,
+	ELS_RNIDA_GATEWAY =	0x05,
+	ELS_RNIDA_CONV =	0x06,   /* Obsolete, do not use this value */
+	ELS_RNIDA_HBA =	        0x07,   /* Obsolete, do not use this value */
+	ELS_RNIDA_PROXY =       0x08,   /* Obsolete, do not use this value */
+	ELS_RNIDA_STORAGE =	0x09,
+	ELS_RNIDA_HOST =	0x0a,
+	ELS_RNIDA_SUBSYS =	0x0b,	/* storage subsystem (e.g., RAID) */
+	ELS_RNIDA_ACCESS =	0x0e,	/* access device (e.g. media changer) */
+	ELS_RNIDA_NAS =		0x11,	/* NAS server */
+	ELS_RNIDA_BRIDGE =	0x12,	/* bridge */
+	ELS_RNIDA_VIRT =	0x13,	/* virtualization device */
+	ELS_RNIDA_MF =		0xff,	/* multifunction device (bits below) */
+	ELS_RNIDA_MF_HUB =	1UL << 31, 	/* hub */
+	ELS_RNIDA_MF_SW =	1UL << 30, 	/* switch */
+	ELS_RNIDA_MF_GW =	1UL << 29,	/* gateway */
+	ELS_RNIDA_MF_ST =	1UL << 28,	/* storage */
+	ELS_RNIDA_MF_HOST =	1UL << 27,	/* host */
+	ELS_RNIDA_MF_SUB =	1UL << 26,	/* storage subsystem */
+	ELS_RNIDA_MF_ACC =	1UL << 25,	/* storage access dev */
+	ELS_RNIDA_MF_WDM =	1UL << 24,	/* wavelength division mux */
+	ELS_RNIDA_MF_NAS =	1UL << 23,	/* NAS server */
+	ELS_RNIDA_MF_BR =	1UL << 22,	/* bridge */
+	ELS_RNIDA_MF_VIRT =	1UL << 21,	/* virtualization device */
+};
+
+enum fc_els_rnid_mgmt {
+	ELS_RNIDM_SNMP =	0,
+	ELS_RNIDM_TELNET =	1,
+	ELS_RNIDM_HTTP =	2,
+	ELS_RNIDM_HTTPS =	3,
+	ELS_RNIDM_XML =		4,	/* HTTP + XML */
+};
+
+enum fc_els_rnid_ipver {
+	ELS_RNIDIP_NONE =	0,	/* no IP support or node mgmt. */
+	ELS_RNIDIP_V4 =		1,	/* IPv4 */
+	ELS_RNIDIP_V6 =		2,	/* IPv6 */
+};
+
+/*
+ * ELS RPL - Read Port List.
+ */
+struct fc_els_rpl {
+	__u8		rpl_cmd;	/* command */
+	__u8		rpl_resv[5];	/* reserved - must be zero */
+	__be16		rpl_max_size;	/* maximum response size or zero */
+	__u8		rpl_resv1;	/* reserved - must be zero */
+	__u8		rpl_index[3];	/* starting index */
+};
+
+/*
+ * Port number block in RPL response.
+ */
+struct fc_els_pnb {
+	__be32		pnb_phys_pn;	/* physical port number */
+	__u8		pnb_resv;	/* reserved */
+	__u8		pnb_port_id[3];	/* port ID */
+	__be64		pnb_wwpn;	/* port name */
+};
+
+/*
+ * RPL LS_ACC response.
+ */
+struct fc_els_rpl_resp {
+	__u8		rpl_cmd;	/* ELS_LS_ACC */
+	__u8		rpl_resv1;	/* reserved - must be zero */
+	__be16		rpl_plen;	/* payload length */
+	__u8		rpl_resv2;	/* reserved - must be zero */
+	__u8		rpl_llen[3];	/* list length */
+	__u8		rpl_resv3;	/* reserved - must be zero */
+	__u8		rpl_index[3];	/* starting index */
+	struct fc_els_pnb rpl_pnb[1];	/* variable number of PNBs */
+};
+
+/*
+ * Link Error Status Block.
+ */
+struct fc_els_lesb {
+	__be32		lesb_link_fail;	/* link failure count */
+	__be32		lesb_sync_loss;	/* loss of synchronization count */
+	__be32		lesb_sig_loss;	/* loss of signal count */
+	__be32		lesb_prim_err;	/* primitive sequence error count */
+	__be32		lesb_inv_word;	/* invalid transmission word count */
+	__be32		lesb_inv_crc;	/* invalid CRC count */
+};
+
+/*
+ * ELS RPS - Read Port Status Block request.
+ */
+struct fc_els_rps {
+	__u8		rps_cmd;	/* command */
+	__u8		rps_resv[2];	/* reserved - must be zero */
+	__u8		rps_flag;	/* flag - see below */
+	__be64		rps_port_spec;	/* port selection */
+};
+
+enum fc_els_rps_flag {
+	FC_ELS_RPS_DID =	0x00,	/* port identified by D_ID of req. */
+	FC_ELS_RPS_PPN =	0x01,	/* port_spec is physical port number */
+	FC_ELS_RPS_WWPN =	0x02,	/* port_spec is port WWN */
+};
+
+/*
+ * ELS RPS LS_ACC response.
+ */
+struct fc_els_rps_resp {
+	__u8		rps_cmd;	/* command - LS_ACC */
+	__u8		rps_resv[2];	/* reserved - must be zero */
+	__u8		rps_flag;	/* flag - see below */
+	__u8		rps_resv2[2];	/* reserved */
+	__be16		rps_status;	/* port status - see below */
+	struct fc_els_lesb rps_lesb;	/* link error status block */
+};
+
+enum fc_els_rps_resp_flag {
+	FC_ELS_RPS_LPEV =	0x01,	/* L_port extension valid */
+};
+
+enum fc_els_rps_resp_status {
+	FC_ELS_RPS_PTP =	1 << 5,	/* point-to-point connection */
+	FC_ELS_RPS_LOOP =	1 << 4,	/* loop mode */
+	FC_ELS_RPS_FAB =	1 << 3,	/* fabric present */
+	FC_ELS_RPS_NO_SIG =	1 << 2,	/* loss of signal */
+	FC_ELS_RPS_NO_SYNC =	1 << 1,	/* loss of synchronization */
+	FC_ELS_RPS_RESET =	1 << 0,	/* in link reset protocol */
+};
+
+/*
+ * ELS LIRR - Link Incident Record Registration request.
+ */
+struct fc_els_lirr {
+	__u8		lirr_cmd;	/* command */
+	__u8		lirr_resv[3];	/* reserved - must be zero */
+	__u8		lirr_func;	/* registration function */
+	__u8		lirr_fmt;	/* FC-4 type of RLIR requested */
+	__u8		lirr_resv2[2];	/* reserved - must be zero */
+};
+
+enum fc_els_lirr_func {
+	ELS_LIRR_SET_COND = 	0x01,	/* set - conditionally receive */
+	ELS_LIRR_SET_UNCOND = 	0x02,	/* set - unconditionally receive */
+	ELS_LIRR_CLEAR = 	0xff	/* clear registration */
+};
+
+/*
+ * ELS SRL - Scan Remote Loop request.
+ */
+struct fc_els_srl {
+	__u8		srl_cmd;	/* command */
+	__u8		srl_resv[3];	/* reserved - must be zero */
+	__u8		srl_flag;	/* flag - see below */
+	__u8		srl_flag_param[3];	/* flag parameter */
+};
+
+enum fc_els_srl_flag {
+	FC_ELS_SRL_ALL =	0x00,	/* scan all FL ports */
+	FC_ELS_SRL_ONE =	0x01,	/* scan specified loop */
+	FC_ELS_SRL_EN_PER =	0x02,	/* enable periodic scanning (param) */
+	FC_ELS_SRL_DIS_PER =	0x03,	/* disable periodic scanning */
+};
+
+/*
+ * ELS RLS - Read Link Error Status Block request.
+ */
+struct fc_els_rls {
+	__u8		rls_cmd;	/* command */
+	__u8		rls_resv[4];	/* reserved - must be zero */
+	__u8		rls_port_id[3];	/* port ID */
+};
+
+/*
+ * ELS RLS LS_ACC Response.
+ */
+struct fc_els_rls_resp {
+	__u8		rls_cmd;	/* ELS_LS_ACC */
+	__u8		rls_resv[3];	/* reserved - must be zero */
+	struct fc_els_lesb rls_lesb;	/* link error status block */
+};
+
+/*
+ * ELS RLIR - Registered Link Incident Report.
+ * This is followed by the CLIR and the CLID, described below.
+ */
+struct fc_els_rlir {
+	__u8		rlir_cmd;	/* command */
+	__u8		rlir_resv[3];	/* reserved - must be zero */
+	__u8		rlir_fmt;	/* format (FC4-type if type specific) */
+	__u8		rlir_clr_len;	/* common link incident record length */
+	__u8		rlir_cld_len;	/* common link incident desc. length */
+	__u8		rlir_slr_len;	/* spec. link incident record length */
+};
+
+/*
+ * CLIR - Common Link Incident Record Data. - Sent via RLIR.
+ */
+struct fc_els_clir {
+	__be64		clir_wwpn;	/* incident port name */
+	__be64		clir_wwnn;	/* incident port node name */
+	__u8		clir_port_type;	/* incident port type */
+	__u8		clir_port_id[3];	/* incident port ID */
+
+	__be64		clir_conn_wwpn;	/* connected port name */
+	__be64		clir_conn_wwnn;	/* connected node name */
+	__be64		clir_fab_name;	/* fabric name */
+	__be32		clir_phys_port;	/* physical port number */
+	__be32		clir_trans_id;	/* transaction ID */
+	__u8		clir_resv[3];	/* reserved */
+	__u8		clir_ts_fmt;	/* time stamp format */
+	__be64		clir_timestamp;	/* time stamp */
+};
+
+/*
+ * CLIR clir_ts_fmt - time stamp format values.
+ */
+enum fc_els_clir_ts_fmt {
+	ELS_CLIR_TS_UNKNOWN = 	0,	/* time stamp field unknown */
+	ELS_CLIR_TS_SEC_FRAC = 	1,	/* time in seconds and fractions */
+	ELS_CLIR_TS_CSU =	2,	/* time in clock synch update format */
+};
+
+/*
+ * Common Link Incident Descriptor - sent via RLIR.
+ */
+struct fc_els_clid {
+	__u8		clid_iq;	/* incident qualifier flags */
+	__u8		clid_ic;	/* incident code */
+	__be16		clid_epai;	/* domain/area of ISL */
+};
+
+/*
+ * CLID incident qualifier flags.
+ */
+enum fc_els_clid_iq {
+	ELS_CLID_SWITCH =	0x20,	/* incident port is a switch node */
+	ELS_CLID_E_PORT =	0x10,	/* incident is an ISL (E) port */
+	ELS_CLID_SEV_MASK =	0x0c,	/* severity 2-bit field mask */
+	ELS_CLID_SEV_INFO =	0x00,	/* report is informational */
+	ELS_CLID_SEV_INOP =	0x08,	/* link not operational */
+	ELS_CLID_SEV_DEG =	0x04,	/* link degraded but operational */
+	ELS_CLID_LASER =	0x02,	/* subassembly is a laser */
+	ELS_CLID_FRU =		0x01,	/* format can identify a FRU */
+};
+
+/*
+ * CLID incident code.
+ */
+enum fc_els_clid_ic {
+	ELS_CLID_IC_IMPL =	1,	/* implicit incident */
+	ELS_CLID_IC_BER =	2,	/* bit-error-rate threshold exceeded */
+	ELS_CLID_IC_LOS =	3,	/* loss of synch or signal */
+	ELS_CLID_IC_NOS =	4,	/* non-operational primitive sequence */
+	ELS_CLID_IC_PST =	5,	/* primitive sequence timeout */
+	ELS_CLID_IC_INVAL =	6,	/* invalid primitive sequence */
+	ELS_CLID_IC_LOOP_TO =	7,	/* loop initialization time out */
+	ELS_CLID_IC_LIP =	8,	/* receiving LIP */
+};
+
+#endif /* _FC_ELS_H_ */
diff --git a/include/scsi/fc/fc_encaps.h b/include/scsi/fc/fc_encaps.h
new file mode 100644
index 000000000000..f180c3e16220
--- /dev/null
+++ b/include/scsi/fc/fc_encaps.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright(c) 2007 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Maintained at www.Open-FCoE.org
+ */
+#ifndef _FC_ENCAPS_H_
+#define _FC_ENCAPS_H_
+
+/*
+ * Protocol definitions from RFC 3643 - Fibre Channel Frame Encapsulation.
+ *
+ * Note:  The frame length field is the number of 32-bit words in
+ * the encapsulation including the fcip_encaps_header, CRC and EOF words.
+ * The minimum frame length value in bytes is (32 + 24 + 4 + 4) * 4 = 64.
+ * The maximum frame length value in bytes is (32 + 24 + 2112 + 4 + 4) = 2172.
+ */
+#define FC_ENCAPS_MIN_FRAME_LEN 64	/* min frame len (bytes) (see above) */
+#define FC_ENCAPS_MAX_FRAME_LEN (FC_ENCAPS_MIN_FRAME_LEN + FC_MAX_PAYLOAD)
+
+#define FC_ENCAPS_VER       1           /* current version number */
+
+struct fc_encaps_hdr {
+	__u8	fc_proto;	/* protocol number */
+	__u8	fc_ver;		/* version of encapsulation */
+	__u8	fc_proto_n;	/* ones complement of protocol */
+	__u8	fc_ver_n;	/* ones complement of version */
+
+	unsigned char fc_proto_data[8]; /* protocol specific data */
+
+	__be16	fc_len_flags;	/* 10-bit length/4 w/ 6 flag bits */
+	__be16	fc_len_flags_n;	/* ones complement of length / flags */
+
+	/*
+	 * Offset 0x10
+	 */
+	__be32	fc_time[2];	/* time stamp: seconds and fraction */
+	__be32	fc_crc;		/* CRC */
+	__be32	fc_sof;		/* start of frame (see FC_SOF below) */
+
+	/* 0x20 - FC frame content followed by EOF word */
+};
+
+#define FCIP_ENCAPS_HDR_LEN 0x20	/* expected length for asserts */
+
+/*
+ * Macro's for making redundant copies of EOF and SOF.
+ */
+#define FC_XY(x, y)		((((x) & 0xff) << 8) | ((y) & 0xff))
+#define FC_XYXY(x, y)		((FCIP_XY(x, y) << 16) | FCIP_XY(x, y))
+#define FC_XYNN(x, y)		(FCIP_XYXY(x, y) ^ 0xffff)
+
+#define FC_SOF_ENCODE(n)	FC_XYNN(n, n)
+#define FC_EOF_ENCODE(n)	FC_XYNN(n, n)
+
+/*
+ * SOF / EOF bytes.
+ */
+enum fc_sof {
+	FC_SOF_F =	0x28,	/* fabric */
+	FC_SOF_I4 =	0x29,	/* initiate class 4 */
+	FC_SOF_I2 =	0x2d,	/* initiate class 2 */
+	FC_SOF_I3 =	0x2e,	/* initiate class 3 */
+	FC_SOF_N4 =	0x31,	/* normal class 4 */
+	FC_SOF_N2 =	0x35,	/* normal class 2 */
+	FC_SOF_N3 =	0x36,	/* normal class 3 */
+	FC_SOF_C4 =	0x39,	/* activate class 4 */
+} __attribute__((packed));
+
+enum fc_eof {
+	FC_EOF_N =	0x41,	/* normal (not last frame of seq) */
+	FC_EOF_T =	0x42,	/* terminate (last frame of sequence) */
+	FC_EOF_RT =	0x44,
+	FC_EOF_DT =	0x46,	/* disconnect-terminate class-1 */
+	FC_EOF_NI =	0x49,	/* normal-invalid */
+	FC_EOF_DTI =	0x4e,	/* disconnect-terminate-invalid */
+	FC_EOF_RTI =	0x4f,
+	FC_EOF_A =	0x50,	/* abort */
+} __attribute__((packed));
+
+#define FC_SOF_CLASS_MASK 0x06	/* mask for class of service in SOF */
+
+/*
+ * Define classes in terms of the SOF code (initial).
+ */
+enum fc_class {
+	FC_CLASS_NONE = 0,	/* software value indicating no class */
+	FC_CLASS_2 =	FC_SOF_I2,
+	FC_CLASS_3 =	FC_SOF_I3,
+	FC_CLASS_4 =	FC_SOF_I4,
+	FC_CLASS_F =	FC_SOF_F,
+};
+
+/*
+ * Determine whether SOF code indicates the need for a BLS ACK.
+ */
+static inline int fc_sof_needs_ack(enum fc_sof sof)
+{
+	return (~sof) & 0x02;	/* true for class 1, 2, 4, 6, or F */
+}
+
+/*
+ * Given an fc_class, return the normal (non-initial) SOF value.
+ */
+static inline enum fc_sof fc_sof_normal(enum fc_class class)
+{
+	return class + FC_SOF_N3 - FC_SOF_I3;	/* diff is always 8 */
+}
+
+/*
+ * Compute class from SOF value.
+ */
+static inline enum fc_class fc_sof_class(enum fc_sof sof)
+{
+	return (sof & 0x7) | FC_SOF_F;
+}
+
+/*
+ * Determine whether SOF is for the initial frame of a sequence.
+ */
+static inline int fc_sof_is_init(enum fc_sof sof)
+{
+	return sof < 0x30;
+}
+
+#endif /* _FC_ENCAPS_H_ */
diff --git a/include/scsi/fc/fc_fc2.h b/include/scsi/fc/fc_fc2.h
new file mode 100644
index 000000000000..cff8a8c22f50
--- /dev/null
+++ b/include/scsi/fc/fc_fc2.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright(c) 2007 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Maintained at www.Open-FCoE.org
+ */
+
+#ifndef _FC_FC2_H_
+#define _FC_FC2_H_
+
+/*
+ * Fibre Channel Exchanges and Sequences.
+ */
+#ifndef PACKED
+#define PACKED  __attribute__ ((__packed__))
+#endif /* PACKED */
+
+
+/*
+ * Sequence Status Block.
+ * This format is set by the FC-FS standard and is sent over the wire.
+ * Note that the fields aren't all naturally aligned.
+ */
+struct fc_ssb {
+	__u8	ssb_seq_id;		/* sequence ID */
+	__u8	_ssb_resvd;
+	__be16	ssb_low_seq_cnt;	/* lowest SEQ_CNT */
+
+	__be16	ssb_high_seq_cnt;	/* highest SEQ_CNT */
+	__be16	ssb_s_stat;		/* sequence status flags */
+
+	__be16	ssb_err_seq_cnt;	/* error SEQ_CNT */
+	__u8	ssb_fh_cs_ctl;		/* frame header CS_CTL */
+	__be16	ssb_fh_ox_id;		/* frame header OX_ID */
+	__be16	ssb_rx_id;		/* responder's exchange ID */
+	__u8	_ssb_resvd2[2];
+} PACKED;
+
+/*
+ * The SSB should be 17 bytes.  Since it's layout is somewhat strange,
+ * we define the size here so that code can ASSERT that the size comes out
+ * correct.
+ */
+#define FC_SSB_SIZE         17          /* length of fc_ssb for assert */
+
+/*
+ * ssb_s_stat - flags from FC-FS-2 T11/1619-D Rev 0.90.
+ */
+#define SSB_ST_RESP         (1 << 15)   /* sequence responder */
+#define SSB_ST_ACTIVE       (1 << 14)   /* sequence is active */
+#define SSB_ST_ABNORMAL     (1 << 12)   /* abnormal ending condition */
+
+#define SSB_ST_REQ_MASK     (3 << 10)   /* ACK, abort sequence condition */
+#define SSB_ST_REQ_CONT     (0 << 10)
+#define SSB_ST_REQ_ABORT    (1 << 10)
+#define SSB_ST_REQ_STOP     (2 << 10)
+#define SSB_ST_REQ_RETRANS  (3 << 10)
+
+#define SSB_ST_ABTS         (1 << 9)    /* ABTS protocol completed */
+#define SSB_ST_RETRANS      (1 << 8)    /* retransmission completed */
+#define SSB_ST_TIMEOUT      (1 << 7)    /* sequence timed out by recipient */
+#define SSB_ST_P_RJT        (1 << 6)    /* P_RJT transmitted */
+
+#define SSB_ST_CLASS_BIT    4           /* class of service field LSB */
+#define SSB_ST_CLASS_MASK   3           /* class of service mask */
+#define SSB_ST_ACK          (1 << 3)    /* ACK (EOFt or EOFdt) transmitted */
+
+/*
+ * Exchange Status Block.
+ * This format is set by the FC-FS standard and is sent over the wire.
+ * Note that the fields aren't all naturally aligned.
+ */
+struct fc_esb {
+	__u8	esb_cs_ctl;		/* CS_CTL for frame header */
+	__be16	esb_ox_id;		/* originator exchange ID */
+	__be16	esb_rx_id;		/* responder exchange ID */
+	__be32	esb_orig_fid;		/* fabric ID of originator */
+	__be32	esb_resp_fid;		/* fabric ID of responder */
+	__be32	esb_e_stat;		/* status */
+	__u8	_esb_resvd[4];
+	__u8	esb_service_params[112]; /* TBD */
+	__u8	esb_seq_status[8];	/* sequence statuses, 8 bytes each */
+} __attribute__((packed));;
+
+
+/*
+ * Define expected size for ASSERTs.
+ * See comments on FC_SSB_SIZE.
+ */
+#define FC_ESB_SIZE         (1 + 5*4 + 112 + 8)     /* expected size */
+
+/*
+ * esb_e_stat - flags from FC-FS-2 T11/1619-D Rev 0.90.
+ */
+#define ESB_ST_RESP         (1 << 31)   /* responder to exchange */
+#define ESB_ST_SEQ_INIT     (1 << 30)   /* port holds sequence initiaive */
+#define ESB_ST_COMPLETE     (1 << 29)   /* exchange is complete */
+#define ESB_ST_ABNORMAL     (1 << 28)   /* abnormal ending condition */
+#define ESB_ST_REC_QUAL     (1 << 26)   /* recovery qualifier active */
+
+#define ESB_ST_ERRP_BIT     24          /* LSB for error policy */
+#define ESB_ST_ERRP_MASK    (3 << 24)   /* mask for error policy */
+#define ESB_ST_ERRP_MULT    (0 << 24)   /* abort, discard multiple sequences */
+#define ESB_ST_ERRP_SING    (1 << 24)   /* abort, discard single sequence */
+#define ESB_ST_ERRP_INF     (2 << 24)   /* process with infinite buffers */
+#define ESB_ST_ERRP_IMM     (3 << 24)   /* discard mult. with immed. retran. */
+
+#define ESB_ST_OX_ID_INVL   (1 << 23)   /* originator XID invalid */
+#define ESB_ST_RX_ID_INVL   (1 << 22)   /* responder XID invalid */
+#define ESB_ST_PRI_INUSE    (1 << 21)   /* priority / preemption in use */
+
+#endif /* _FC_FC2_H_ */
diff --git a/include/scsi/fc/fc_fcoe.h b/include/scsi/fc/fc_fcoe.h
new file mode 100644
index 000000000000..57aaa8f0d613
--- /dev/null
+++ b/include/scsi/fc/fc_fcoe.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright(c) 2007 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Maintained at www.Open-FCoE.org
+ */
+
+#ifndef _FC_FCOE_H_
+#define	_FC_FCOE_H_
+
+/*
+ * FCoE - Fibre Channel over Ethernet.
+ */
+
+/*
+ * The FCoE ethertype eventually goes in net/if_ether.h.
+ */
+#ifndef ETH_P_FCOE
+#define	ETH_P_FCOE	0x8906		/* FCOE ether type */
+#endif
+
+#ifndef ETH_P_8021Q
+#define	ETH_P_8021Q	0x8100
+#endif
+
+/*
+ * FC_FCOE_OUI hasn't been standardized yet.   XXX TBD.
+ */
+#ifndef FC_FCOE_OUI
+#define	FC_FCOE_OUI	0x0efc00	/* upper 24 bits of FCOE dest MAC TBD */
+#endif
+
+/*
+ * The destination MAC address for the fabric login may get a different OUI.
+ * This isn't standardized yet.
+ */
+#ifndef FC_FCOE_FLOGI_MAC
+/* gateway MAC - TBD */
+#define	FC_FCOE_FLOGI_MAC { 0x0e, 0xfc, 0x00, 0xff, 0xff, 0xfe }
+#endif
+
+#define	FC_FCOE_VER	0			/* version */
+
+/*
+ * Ethernet Addresses based on FC S_ID and D_ID.
+ * Generated by FC_FCOE_OUI | S_ID/D_ID
+ */
+#define	FC_FCOE_ENCAPS_ID(n)	(((u64) FC_FCOE_OUI << 24) | (n))
+#define	FC_FCOE_DECAPS_ID(n)	((n) >> 24)
+
+/*
+ * FCoE frame header - 14 bytes
+ *
+ * This is the August 2007 version of the FCoE header as defined by T11.
+ * This follows the VLAN header, which includes the ethertype.
+ */
+struct fcoe_hdr {
+	__u8		fcoe_ver;	/* version field - upper 4 bits */
+	__u8		fcoe_resvd[12];	/* reserved - send zero and ignore */
+	__u8		fcoe_sof;	/* start of frame per RFC 3643 */
+};
+
+#define FC_FCOE_DECAPS_VER(hp)	    ((hp)->fcoe_ver >> 4)
+#define FC_FCOE_ENCAPS_VER(hp, ver) ((hp)->fcoe_ver = (ver) << 4)
+
+/*
+ * FCoE CRC & EOF - 8 bytes.
+ */
+struct fcoe_crc_eof {
+	__le32		fcoe_crc32;	/* CRC for FC packet */
+	__u8		fcoe_eof;	/* EOF from RFC 3643 */
+	__u8		fcoe_resvd[3];	/* reserved - send zero and ignore */
+} __attribute__((packed));
+
+/*
+ * Minimum FCoE + FC header length
+ * 14 bytes FCoE header + 24 byte FC header = 38 bytes
+ */
+#define FCOE_HEADER_LEN 38
+
+/*
+ * Minimum FCoE frame size
+ * 14 bytes FCoE header + 24 byte FC header + 8 byte FCoE trailer = 46 bytes
+ */
+#define FCOE_MIN_FRAME 46
+
+/*
+ * fc_fcoe_set_mac - Store OUI + DID into MAC address field.
+ * @mac: mac address to be set
+ * @did: fc dest id to use
+ */
+static inline void fc_fcoe_set_mac(u8 *mac, u8 *did)
+{
+	mac[0] = (u8) (FC_FCOE_OUI >> 16);
+	mac[1] = (u8) (FC_FCOE_OUI >> 8);
+	mac[2] = (u8) FC_FCOE_OUI;
+	mac[3] = did[0];
+	mac[4] = did[1];
+	mac[5] = did[2];
+}
+
+#endif /* _FC_FCOE_H_ */
diff --git a/include/scsi/fc/fc_fcp.h b/include/scsi/fc/fc_fcp.h
new file mode 100644
index 000000000000..5d38f1989f37
--- /dev/null
+++ b/include/scsi/fc/fc_fcp.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright(c) 2007 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Maintained at www.Open-FCoE.org
+ */
+
+#ifndef _FC_FCP_H_
+#define	_FC_FCP_H_
+
+/*
+ * Fibre Channel Protocol for SCSI.
+ * From T10 FCP-3, T10 project 1560-D Rev 4, Sept. 13, 2005.
+ */
+
+/*
+ * fc/fs.h defines FC_TYPE_FCP.
+ */
+
+/*
+ * Service parameter page parameters (word 3 bits) for Process Login.
+ */
+#define	FCP_SPPF_TASK_RETRY_ID	0x0200	/* task retry ID requested */
+#define	FCP_SPPF_RETRY		0x0100	/* retry supported */
+#define	FCP_SPPF_CONF_COMPL	0x0080	/* confirmed completion allowed */
+#define	FCP_SPPF_OVLY_ALLOW	0x0040	/* data overlay allowed */
+#define	FCP_SPPF_INIT_FCN	0x0020	/* initiator function */
+#define	FCP_SPPF_TARG_FCN	0x0010	/* target function */
+#define	FCP_SPPF_RD_XRDY_DIS	0x0002	/* disable XFER_RDY for reads */
+#define	FCP_SPPF_WR_XRDY_DIS	0x0001	/* disable XFER_RDY for writes */
+
+/*
+ * FCP_CMND IU Payload.
+ */
+struct fcp_cmnd {
+	__u8		fc_lun[8];	/* logical unit number */
+	__u8		fc_cmdref;	/* commmand reference number */
+	__u8		fc_pri_ta;	/* priority and task attribute */
+	__u8		fc_tm_flags;	/* task management flags */
+	__u8		fc_flags;	/* additional len & flags */
+	__u8		fc_cdb[16];	/* base CDB */
+	__be32		fc_dl;		/* data length (must follow fc_cdb) */
+};
+
+#define	FCP_CMND_LEN	32	/* expected length of structure */
+
+struct fcp_cmnd32 {
+	__u8		fc_lun[8];	/* logical unit number */
+	__u8		fc_cmdref;	/* commmand reference number */
+	__u8		fc_pri_ta;	/* priority and task attribute */
+	__u8		fc_tm_flags;	/* task management flags */
+	__u8		fc_flags;	/* additional len & flags */
+	__u8		fc_cdb[32];	/* base CDB */
+	__be32		fc_dl;		/* data length (must follow fc_cdb) */
+};
+
+#define	FCP_CMND32_LEN	    48	/* expected length of structure */
+#define	FCP_CMND32_ADD_LEN  (16 / 4)	/* Additional cdb length */
+
+/*
+ * fc_pri_ta.
+ */
+#define	FCP_PTA_SIMPLE	    0	/* simple task attribute */
+#define	FCP_PTA_HEADQ	    1	/* head of queue task attribute */
+#define	FCP_PTA_ORDERED     2	/* ordered task attribute */
+#define	FCP_PTA_ACA	    4	/* auto. contigent allegiance */
+#define	FCP_PRI_SHIFT	    3	/* priority field starts in bit 3 */
+#define	FCP_PRI_RESVD_MASK  0x80	/* reserved bits in priority field */
+
+/*
+ * fc_tm_flags - task management flags field.
+ */
+#define	FCP_TMF_CLR_ACA		0x40	/* clear ACA condition */
+#define	FCP_TMF_LUN_RESET	0x10	/* logical unit reset task management */
+#define	FCP_TMF_CLR_TASK_SET	0x04	/* clear task set */
+#define	FCP_TMF_ABT_TASK_SET	0x02	/* abort task set */
+
+/*
+ * fc_flags.
+ *  Bits 7:2 are the additional FCP_CDB length / 4.
+ */
+#define	FCP_CFL_LEN_MASK	0xfc	/* mask for additional length */
+#define	FCP_CFL_LEN_SHIFT	2	/* shift bits for additional length */
+#define	FCP_CFL_RDDATA		0x02	/* read data */
+#define	FCP_CFL_WRDATA		0x01	/* write data */
+
+/*
+ * FCP_TXRDY IU - transfer ready payload.
+ */
+struct fcp_txrdy {
+	__be32		ft_data_ro;	/* data relative offset */
+	__be32		ft_burst_len;	/* burst length */
+	__u8		_ft_resvd[4];	/* reserved */
+};
+
+#define	FCP_TXRDY_LEN	12	/* expected length of structure */
+
+/*
+ * FCP_RESP IU - response payload.
+ *
+ * The response payload comes in three parts: the flags/status, the
+ * sense/response lengths and the sense data/response info section.
+ *
+ * From FCP3r04, note 6 of section 9.5.13:
+ *
+ * Some early implementations presented the FCP_RSP IU without the FCP_RESID,
+ * FCP_SNS_LEN, and FCP_RSP_LEN fields if the FCP_RESID_UNDER, FCP_RESID_OVER,
+ * FCP_SNS_LEN_VALID, and FCP_RSP_LEN_VALID bits were all set to zero. This
+ * non-standard behavior should be tolerated.
+ *
+ * All response frames will always contain the fcp_resp template.  Some
+ * will also include the fcp_resp_len template.
+ */
+struct fcp_resp {
+	__u8		_fr_resvd[8];	/* reserved */
+	__be16		fr_retry_delay;	/* retry delay timer */
+	__u8		fr_flags;	/* flags */
+	__u8		fr_status;	/* SCSI status code */
+};
+
+#define	FCP_RESP_LEN	12	/* expected length of structure */
+
+struct fcp_resp_ext {
+	__be32		fr_resid;	/* Residual value */
+	__be32		fr_sns_len;	/* SCSI Sense length */
+	__be32		fr_rsp_len;	/* Response Info length */
+
+	/*
+	 * Optionally followed by RSP info and/or SNS info and/or
+	 * bidirectional read residual length, if any.
+	 */
+};
+
+#define FCP_RESP_EXT_LEN    12  /* expected length of the structure */
+
+struct fcp_resp_rsp_info {
+    __u8      _fr_resvd[3];       /* reserved */
+    __u8      rsp_code;           /* Response Info Code */
+    __u8      _fr_resvd2[4];      /* reserved */
+};
+
+struct fcp_resp_with_ext {
+	struct fcp_resp resp;
+	struct fcp_resp_ext ext;
+};
+
+#define	FCP_RESP_WITH_EXT   (FCP_RESP_LEN + FCP_RESP_EXT_LEN)
+
+/*
+ * fr_flags.
+ */
+#define	FCP_BIDI_RSP	    0x80	/* bidirectional read response */
+#define	FCP_BIDI_READ_UNDER 0x40	/* bidir. read less than requested */
+#define	FCP_BIDI_READ_OVER  0x20	/* DL insufficient for full transfer */
+#define	FCP_CONF_REQ	    0x10	/* confirmation requested */
+#define	FCP_RESID_UNDER     0x08	/* transfer shorter than expected */
+#define	FCP_RESID_OVER	    0x04	/* DL insufficient for full transfer */
+#define	FCP_SNS_LEN_VAL     0x02	/* SNS_LEN field is valid */
+#define	FCP_RSP_LEN_VAL     0x01	/* RSP_LEN field is valid */
+
+/*
+ * rsp_codes
+ */
+enum fcp_resp_rsp_codes {
+	FCP_TMF_CMPL = 0,
+	FCP_DATA_LEN_INVALID = 1,
+	FCP_CMND_FIELDS_INVALID = 2,
+	FCP_DATA_PARAM_MISMATCH = 3,
+	FCP_TMF_REJECTED = 4,
+	FCP_TMF_FAILED = 5,
+	FCP_TMF_INVALID_LUN = 9,
+};
+
+/*
+ * FCP SRR Link Service request - Sequence Retransmission Request.
+ */
+struct fcp_srr {
+	__u8		srr_op;		/* opcode ELS_SRR */
+	__u8		srr_resvd[3];	/* opcode / reserved - must be zero */
+	__be16		srr_ox_id;	/* OX_ID of failed command */
+	__be16		srr_rx_id;	/* RX_ID of failed command */
+	__be32		srr_rel_off;	/* relative offset */
+	__u8		srr_r_ctl;	/* r_ctl for the information unit */
+	__u8		srr_resvd2[3];	/* reserved */
+};
+
+#endif /* _FC_FCP_H_ */
diff --git a/include/scsi/fc/fc_fs.h b/include/scsi/fc/fc_fs.h
new file mode 100644
index 000000000000..3e4801d2bdbb
--- /dev/null
+++ b/include/scsi/fc/fc_fs.h
@@ -0,0 +1,340 @@
+/*
+ * Copyright(c) 2007 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Maintained at www.Open-FCoE.org
+ */
+
+#ifndef _FC_FS_H_
+#define _FC_FS_H_
+
+/*
+ * Fibre Channel Framing and Signalling definitions.
+ * From T11 FC-FS-2 Rev 0.90 - 9 August 2005.
+ */
+
+/*
+ * Frame header
+ */
+struct fc_frame_header {
+	__u8          fh_r_ctl;	/* routing control */
+	__u8          fh_d_id[3];	/* Destination ID */
+
+	__u8          fh_cs_ctl;	/* class of service control / pri */
+	__u8          fh_s_id[3];	/* Source ID */
+
+	__u8          fh_type;		/* see enum fc_fh_type below */
+	__u8          fh_f_ctl[3];	/* frame control */
+
+	__u8          fh_seq_id;	/* sequence ID */
+	__u8          fh_df_ctl;	/* data field control */
+	__be16        fh_seq_cnt;	/* sequence count */
+
+	__be16        fh_ox_id;		/* originator exchange ID */
+	__be16        fh_rx_id;		/* responder exchange ID */
+	__be32        fh_parm_offset;	/* parameter or relative offset */
+};
+
+#define FC_FRAME_HEADER_LEN 24	/* expected length of structure */
+
+#define FC_MAX_PAYLOAD  2112U		/* max payload length in bytes */
+#define FC_MIN_MAX_PAYLOAD  256U 	/* lower limit on max payload */
+
+#define FC_MAX_FRAME	(FC_MAX_PAYLOAD + FC_FRAME_HEADER_LEN)
+#define FC_MIN_MAX_FRAME (FC_MIN_MAX_PAYLOAD + FC_FRAME_HEADER_LEN)
+
+/*
+ * fh_r_ctl - Routing control definitions.
+ */
+    /*
+     * FC-4 device_data.
+     */
+enum fc_rctl {
+	FC_RCTL_DD_UNCAT = 0x00,	/* uncategorized information */
+	FC_RCTL_DD_SOL_DATA = 0x01,	/* solicited data */
+	FC_RCTL_DD_UNSOL_CTL = 0x02,	/* unsolicited control */
+	FC_RCTL_DD_SOL_CTL = 0x03,	/* solicited control or reply */
+	FC_RCTL_DD_UNSOL_DATA = 0x04,	/* unsolicited data */
+	FC_RCTL_DD_DATA_DESC = 0x05,	/* data descriptor */
+	FC_RCTL_DD_UNSOL_CMD = 0x06,	/* unsolicited command */
+	FC_RCTL_DD_CMD_STATUS = 0x07,	/* command status */
+
+#define FC_RCTL_ILS_REQ FC_RCTL_DD_UNSOL_CTL	/* ILS request */
+#define FC_RCTL_ILS_REP FC_RCTL_DD_SOL_CTL	/* ILS reply */
+
+	/*
+	 * Extended Link_Data
+	 */
+	FC_RCTL_ELS_REQ = 0x22,	/* extended link services request */
+	FC_RCTL_ELS_REP = 0x23,	/* extended link services reply */
+	FC_RCTL_ELS4_REQ = 0x32, /* FC-4 ELS request */
+	FC_RCTL_ELS4_REP = 0x33, /* FC-4 ELS reply */
+	/*
+	 * Optional Extended Headers
+	 */
+	FC_RCTL_VFTH = 0x50,	/* virtual fabric tagging header */
+	FC_RCTL_IFRH = 0x51,	/* inter-fabric routing header */
+	FC_RCTL_ENCH = 0x52,	/* encapsulation header */
+	/*
+	 * Basic Link Services fh_r_ctl values.
+	 */
+	FC_RCTL_BA_NOP = 0x80,	/* basic link service NOP */
+	FC_RCTL_BA_ABTS = 0x81,	/* basic link service abort */
+	FC_RCTL_BA_RMC = 0x82,	/* remove connection */
+	FC_RCTL_BA_ACC = 0x84,	/* basic accept */
+	FC_RCTL_BA_RJT = 0x85,	/* basic reject */
+	FC_RCTL_BA_PRMT = 0x86,	/* dedicated connection preempted */
+	/*
+	 * Link Control Information.
+	 */
+	FC_RCTL_ACK_1 = 0xc0,	/* acknowledge_1 */
+	FC_RCTL_ACK_0 = 0xc1,	/* acknowledge_0 */
+	FC_RCTL_P_RJT = 0xc2,	/* port reject */
+	FC_RCTL_F_RJT = 0xc3,	/* fabric reject */
+	FC_RCTL_P_BSY = 0xc4,	/* port busy */
+	FC_RCTL_F_BSY = 0xc5,	/* fabric busy to data frame */
+	FC_RCTL_F_BSYL = 0xc6,	/* fabric busy to link control frame */
+	FC_RCTL_LCR = 0xc7,	/* link credit reset */
+	FC_RCTL_END = 0xc9,	/* end */
+};
+				    /* incomplete list of definitions */
+
+/*
+ * R_CTL names initializer.
+ * Please keep this matching the above definitions.
+ */
+#define FC_RCTL_NAMES_INIT { \
+	[FC_RCTL_DD_UNCAT] =		"uncat",			\
+	[FC_RCTL_DD_SOL_DATA] =		"sol data",			\
+	[FC_RCTL_DD_UNSOL_CTL] =	"unsol ctl",			\
+	[FC_RCTL_DD_SOL_CTL] =		"sol ctl/reply",		\
+	[FC_RCTL_DD_UNSOL_DATA] =	"unsol data",			\
+	[FC_RCTL_DD_DATA_DESC] =	"data desc",			\
+	[FC_RCTL_DD_UNSOL_CMD] =	"unsol cmd",			\
+	[FC_RCTL_DD_CMD_STATUS] =	"cmd status",			\
+	[FC_RCTL_ELS_REQ] =		"ELS req",			\
+	[FC_RCTL_ELS_REP] =		"ELS rep",			\
+	[FC_RCTL_ELS4_REQ] =		"FC-4 ELS req",			\
+	[FC_RCTL_ELS4_REP] =		"FC-4 ELS rep",			\
+	[FC_RCTL_BA_NOP] =		"BLS NOP",			\
+	[FC_RCTL_BA_ABTS] =		"BLS abort",			\
+	[FC_RCTL_BA_RMC] =		"BLS remove connection",	\
+	[FC_RCTL_BA_ACC] =		"BLS accept",			\
+	[FC_RCTL_BA_RJT] =		"BLS reject",			\
+	[FC_RCTL_BA_PRMT] =		"BLS dedicated connection preempted", \
+	[FC_RCTL_ACK_1] =		"LC ACK_1",			\
+	[FC_RCTL_ACK_0] =		"LC ACK_0",			\
+	[FC_RCTL_P_RJT] =		"LC port reject",		\
+	[FC_RCTL_F_RJT] =		"LC fabric reject",		\
+	[FC_RCTL_P_BSY] =		"LC port busy",			\
+	[FC_RCTL_F_BSY] =		"LC fabric busy to data frame",	\
+	[FC_RCTL_F_BSYL] =		"LC fabric busy to link control frame",\
+	[FC_RCTL_LCR] =			"LC link credit reset",		\
+	[FC_RCTL_END] =			"LC end",			\
+}
+
+/*
+ * Well-known fabric addresses.
+ */
+enum fc_well_known_fid {
+	FC_FID_BCAST =		0xffffff,	/* broadcast */
+	FC_FID_FLOGI =		0xfffffe,	/* fabric login */
+	FC_FID_FCTRL =		0xfffffd,	/* fabric controller */
+	FC_FID_DIR_SERV =	0xfffffc,	/* directory server */
+	FC_FID_TIME_SERV =	0xfffffb,	/* time server */
+	FC_FID_MGMT_SERV =	0xfffffa,	/* management server */
+	FC_FID_QOS =		0xfffff9,	/* QoS Facilitator */
+	FC_FID_ALIASES =	0xfffff8,	/* alias server (FC-PH2) */
+	FC_FID_SEC_KEY =	0xfffff7,	/* Security key dist. server */
+	FC_FID_CLOCK =		0xfffff6,	/* clock synch server */
+	FC_FID_MCAST_SERV =	0xfffff5,	/* multicast server */
+};
+
+#define	FC_FID_WELL_KNOWN_MAX	0xffffff /* highest well-known fabric ID */
+#define	FC_FID_WELL_KNOWN_BASE	0xfffff5 /* start of well-known fabric ID */
+
+/*
+ * Other well-known addresses, outside the above contiguous range.
+ */
+#define	FC_FID_DOM_MGR		0xfffc00	/* domain manager base */
+
+/*
+ * Fabric ID bytes.
+ */
+#define	FC_FID_DOMAIN		0
+#define	FC_FID_PORT		1
+#define	FC_FID_LINK		2
+
+/*
+ * fh_type codes
+ */
+enum fc_fh_type {
+	FC_TYPE_BLS =	0x00,	/* basic link service */
+	FC_TYPE_ELS =	0x01,	/* extended link service */
+	FC_TYPE_IP =	0x05,	/* IP over FC, RFC 4338 */
+	FC_TYPE_FCP =	0x08,	/* SCSI FCP */
+	FC_TYPE_CT =	0x20,	/* Fibre Channel Services (FC-CT) */
+	FC_TYPE_ILS =	0x22,	/* internal link service */
+};
+
+/*
+ * FC_TYPE names initializer.
+ * Please keep this matching the above definitions.
+ */
+#define FC_TYPE_NAMES_INIT {				\
+	[FC_TYPE_BLS] =		"BLS",			\
+	[FC_TYPE_ELS] =		"ELS",			\
+	[FC_TYPE_IP] =		"IP",			\
+	[FC_TYPE_FCP] =		"FCP",			\
+	[FC_TYPE_CT] =		"CT",			\
+	[FC_TYPE_ILS] =		"ILS",			\
+}
+
+/*
+ * Exchange IDs.
+ */
+#define FC_XID_UNKNOWN  0xffff	/* unknown exchange ID */
+#define FC_XID_MIN	0x0	/* supported min exchange ID */
+#define FC_XID_MAX	0xfffe	/* supported max exchange ID */
+
+/*
+ * fh_f_ctl - Frame control flags.
+ */
+#define	FC_FC_EX_CTX	(1 << 23)	/* sent by responder to exchange */
+#define	FC_FC_SEQ_CTX	(1 << 22)	/* sent by responder to sequence */
+#define	FC_FC_FIRST_SEQ (1 << 21)	/* first sequence of this exchange */
+#define	FC_FC_LAST_SEQ	(1 << 20)	/* last sequence of this exchange */
+#define	FC_FC_END_SEQ	(1 << 19)	/* last frame of sequence */
+#define	FC_FC_END_CONN	(1 << 18)	/* end of class 1 connection pending */
+#define	FC_FC_RES_B17	(1 << 17)	/* reserved */
+#define	FC_FC_SEQ_INIT	(1 << 16)	/* transfer of sequence initiative */
+#define	FC_FC_X_ID_REASS (1 << 15)	/* exchange ID has been changed */
+#define	FC_FC_X_ID_INVAL (1 << 14)	/* exchange ID invalidated */
+
+#define	FC_FC_ACK_1	(1 << 12)	/* 13:12 = 1: ACK_1 expected */
+#define	FC_FC_ACK_N	(2 << 12)	/* 13:12 = 2: ACK_N expected */
+#define	FC_FC_ACK_0	(3 << 12)	/* 13:12 = 3: ACK_0 expected */
+
+#define	FC_FC_RES_B11	(1 << 11)	/* reserved */
+#define	FC_FC_RES_B10	(1 << 10)	/* reserved */
+#define	FC_FC_RETX_SEQ	(1 << 9)	/* retransmitted sequence */
+#define	FC_FC_UNI_TX	(1 << 8)	/* unidirectional transmit (class 1) */
+#define	FC_FC_CONT_SEQ(i) ((i) << 6)
+#define	FC_FC_ABT_SEQ(i) ((i) << 4)
+#define	FC_FC_REL_OFF	(1 << 3)	/* parameter is relative offset */
+#define	FC_FC_RES2	(1 << 2)	/* reserved */
+#define	FC_FC_FILL(i)	((i) & 3)	/* 1:0: bytes of trailing fill */
+
+/*
+ * BA_ACC payload.
+ */
+struct fc_ba_acc {
+	__u8		ba_seq_id_val;	/* SEQ_ID validity */
+#define FC_BA_SEQ_ID_VAL 0x80
+	__u8		ba_seq_id;	/* SEQ_ID of seq last deliverable */
+	__u8		ba_resvd[2];	/* reserved */
+	__be16		ba_ox_id;	/* OX_ID for aborted seq or exch */
+	__be16		ba_rx_id;	/* RX_ID for aborted seq or exch */
+	__be16		ba_low_seq_cnt;	/* low SEQ_CNT of aborted seq */
+	__be16		ba_high_seq_cnt; /* high SEQ_CNT of aborted seq */
+};
+
+/*
+ * BA_RJT: Basic Reject payload.
+ */
+struct fc_ba_rjt {
+	__u8		br_resvd;	/* reserved */
+	__u8		br_reason;	/* reason code */
+	__u8		br_explan;	/* reason explanation */
+	__u8		br_vendor;	/* vendor unique code */
+};
+
+/*
+ * BA_RJT reason codes.
+ * From FS-2.
+ */
+enum fc_ba_rjt_reason {
+	FC_BA_RJT_NONE =	0,	/* in software this means no reject */
+	FC_BA_RJT_INVL_CMD =	0x01,	/* invalid command code */
+	FC_BA_RJT_LOG_ERR =	0x03,	/* logical error */
+	FC_BA_RJT_LOG_BUSY =	0x05,	/* logical busy */
+	FC_BA_RJT_PROTO_ERR =	0x07,	/* protocol error */
+	FC_BA_RJT_UNABLE =	0x09,	/* unable to perform request */
+	FC_BA_RJT_VENDOR =	0xff,	/* vendor-specific (see br_vendor) */
+};
+
+/*
+ * BA_RJT reason code explanations.
+ */
+enum fc_ba_rjt_explan {
+	FC_BA_RJT_EXP_NONE =	0x00,	/* no additional expanation */
+	FC_BA_RJT_INV_XID =	0x03,	/* invalid OX_ID-RX_ID combination */
+	FC_BA_RJT_ABT =		0x05,	/* sequence aborted, no seq info */
+};
+
+/*
+ * P_RJT or F_RJT: Port Reject or Fabric Reject parameter field.
+ */
+struct fc_pf_rjt {
+	__u8		rj_action;	/* reserved */
+	__u8		rj_reason;	/* reason code */
+	__u8		rj_resvd;	/* reserved */
+	__u8		rj_vendor;	/* vendor unique code */
+};
+
+/*
+ * P_RJT and F_RJT reject reason codes.
+ */
+enum fc_pf_rjt_reason {
+	FC_RJT_NONE =		0,	/* non-reject (reserved by standard) */
+	FC_RJT_INVL_DID =	0x01,	/* invalid destination ID */
+	FC_RJT_INVL_SID =	0x02,	/* invalid source ID */
+	FC_RJT_P_UNAV_T =	0x03,	/* port unavailable, temporary */
+	FC_RJT_P_UNAV =		0x04,	/* port unavailable, permanent */
+	FC_RJT_CLS_UNSUP =	0x05,	/* class not supported */
+	FC_RJT_DEL_USAGE =	0x06,	/* delimiter usage error */
+	FC_RJT_TYPE_UNSUP =	0x07,	/* type not supported */
+	FC_RJT_LINK_CTL =	0x08,	/* invalid link control */
+	FC_RJT_R_CTL =		0x09,	/* invalid R_CTL field */
+	FC_RJT_F_CTL =		0x0a,	/* invalid F_CTL field */
+	FC_RJT_OX_ID =		0x0b,	/* invalid originator exchange ID */
+	FC_RJT_RX_ID =		0x0c,	/* invalid responder exchange ID */
+	FC_RJT_SEQ_ID =		0x0d,	/* invalid sequence ID */
+	FC_RJT_DF_CTL =		0x0e,	/* invalid DF_CTL field */
+	FC_RJT_SEQ_CNT =	0x0f,	/* invalid SEQ_CNT field */
+	FC_RJT_PARAM =		0x10,	/* invalid parameter field */
+	FC_RJT_EXCH_ERR =	0x11,	/* exchange error */
+	FC_RJT_PROTO =		0x12,	/* protocol error */
+	FC_RJT_LEN =		0x13,	/* incorrect length */
+	FC_RJT_UNEXP_ACK =	0x14,	/* unexpected ACK */
+	FC_RJT_FAB_CLASS =	0x15,	/* class unsupported by fabric entity */
+	FC_RJT_LOGI_REQ =	0x16,	/* login required */
+	FC_RJT_SEQ_XS =		0x17,	/* excessive sequences attempted */
+	FC_RJT_EXCH_EST =	0x18,	/* unable to establish exchange */
+	FC_RJT_FAB_UNAV =	0x1a,	/* fabric unavailable */
+	FC_RJT_VC_ID =		0x1b,	/* invalid VC_ID (class 4) */
+	FC_RJT_CS_CTL =		0x1c,	/* invalid CS_CTL field */
+	FC_RJT_INSUF_RES =	0x1d,	/* insuff. resources for VC (Class 4) */
+	FC_RJT_INVL_CLS =	0x1f,	/* invalid class of service */
+	FC_RJT_PREEMT_RJT =	0x20,	/* preemption request rejected */
+	FC_RJT_PREEMT_DIS =	0x21,	/* preemption not enabled */
+	FC_RJT_MCAST_ERR =	0x22,	/* multicast error */
+	FC_RJT_MCAST_ET =	0x23,	/* multicast error terminate */
+	FC_RJT_PRLI_REQ =	0x24,	/* process login required */
+	FC_RJT_INVL_ATT =	0x25,	/* invalid attachment */
+	FC_RJT_VENDOR =		0xff,	/* vendor specific reject */
+};
+
+#endif /* _FC_FS_H_ */
diff --git a/include/scsi/fc/fc_gs.h b/include/scsi/fc/fc_gs.h
new file mode 100644
index 000000000000..ffab0272c65a
--- /dev/null
+++ b/include/scsi/fc/fc_gs.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright(c) 2007 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Maintained at www.Open-FCoE.org
+ */
+
+#ifndef _FC_GS_H_
+#define	_FC_GS_H_
+
+/*
+ * Fibre Channel Services - Common Transport.
+ * From T11.org FC-GS-2 Rev 5.3 November 1998.
+ */
+
+struct fc_ct_hdr {
+	__u8		ct_rev;		/* revision */
+	__u8		ct_in_id[3];	/* N_Port ID of original requestor */
+	__u8		ct_fs_type;	/* type of fibre channel service */
+	__u8		ct_fs_subtype;	/* subtype */
+	__u8		ct_options;
+	__u8		_ct_resvd1;
+	__be16		ct_cmd;		/* command / response code */
+	__be16		ct_mr_size;	/* maximum / residual size */
+	__u8		_ct_resvd2;
+	__u8		ct_reason;	/* reject reason */
+	__u8		ct_explan;	/* reason code explanation */
+	__u8		ct_vendor;	/* vendor unique data */
+};
+
+#define	FC_CT_HDR_LEN	16	/* expected sizeof (struct fc_ct_hdr) */
+
+enum fc_ct_rev {
+	FC_CT_REV = 1		/* common transport revision */
+};
+
+/*
+ * ct_fs_type values.
+ */
+enum fc_ct_fs_type {
+	FC_FST_ALIAS =	0xf8,	/* alias service */
+	FC_FST_MGMT =	0xfa,	/* management service */
+	FC_FST_TIME =	0xfb,	/* time service */
+	FC_FST_DIR =	0xfc,	/* directory service */
+};
+
+/*
+ * ct_cmd: Command / response codes
+ */
+enum fc_ct_cmd {
+	FC_FS_RJT =	0x8001,	/* reject */
+	FC_FS_ACC =	0x8002,	/* accept */
+};
+
+/*
+ * FS_RJT reason codes.
+ */
+enum fc_ct_reason {
+	FC_FS_RJT_CMD =		0x01,	/* invalid command code */
+	FC_FS_RJT_VER =		0x02,	/* invalid version level */
+	FC_FS_RJT_LOG =		0x03,	/* logical error */
+	FC_FS_RJT_IUSIZ =	0x04,	/* invalid IU size */
+	FC_FS_RJT_BSY =		0x05,	/* logical busy */
+	FC_FS_RJT_PROTO =	0x07,	/* protocol error */
+	FC_FS_RJT_UNABL =	0x09,	/* unable to perform command request */
+	FC_FS_RJT_UNSUP =	0x0b,	/* command not supported */
+};
+
+/*
+ * FS_RJT reason code explanations.
+ */
+enum fc_ct_explan {
+	FC_FS_EXP_NONE =	0x00,	/* no additional explanation */
+	FC_FS_EXP_PID =		0x01,	/* port ID not registered */
+	FC_FS_EXP_PNAM =	0x02,	/* port name not registered */
+	FC_FS_EXP_NNAM =	0x03,	/* node name not registered */
+	FC_FS_EXP_COS =		0x04,	/* class of service not registered */
+	/* definitions not complete */
+};
+
+#endif /* _FC_GS_H_ */
diff --git a/include/scsi/fc/fc_ns.h b/include/scsi/fc/fc_ns.h
new file mode 100644
index 000000000000..790d7b97d4bc
--- /dev/null
+++ b/include/scsi/fc/fc_ns.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright(c) 2007 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Maintained at www.Open-FCoE.org
+ */
+
+#ifndef _FC_NS_H_
+#define	_FC_NS_H_
+
+/*
+ * Fibre Channel Services - Name Service (dNS)
+ * From T11.org FC-GS-2 Rev 5.3 November 1998.
+ */
+
+/*
+ * Common-transport sub-type for Name Server.
+ */
+#define	FC_NS_SUBTYPE	    2	/* fs_ct_hdr.ct_fs_subtype */
+
+/*
+ * Name server Requests.
+ * Note:  this is an incomplete list, some unused requests are omitted.
+ */
+enum fc_ns_req {
+	FC_NS_GA_NXT =	0x0100,		/* get all next */
+	FC_NS_GI_A =	0x0101,		/* get identifiers - scope */
+	FC_NS_GPN_ID =	0x0112,		/* get port name by ID */
+	FC_NS_GNN_ID =	0x0113,		/* get node name by ID */
+	FC_NS_GID_PN =	0x0121,		/* get ID for port name */
+	FC_NS_GID_NN =	0x0131,		/* get IDs for node name */
+	FC_NS_GID_FT =	0x0171,		/* get IDs by FC4 type */
+	FC_NS_GPN_FT =	0x0172,		/* get port names by FC4 type */
+	FC_NS_GID_PT =	0x01a1,		/* get IDs by port type */
+	FC_NS_RFT_ID =	0x0217,		/* reg FC4 type for ID */
+	FC_NS_RPN_ID =	0x0212,		/* reg port name for ID */
+	FC_NS_RNN_ID =	0x0213,		/* reg node name for ID */
+};
+
+/*
+ * Port type values.
+ */
+enum fc_ns_pt {
+	FC_NS_UNID_PORT = 0x00,	/* unidentified */
+	FC_NS_N_PORT =	0x01,	/* N port */
+	FC_NS_NL_PORT =	0x02,	/* NL port */
+	FC_NS_FNL_PORT = 0x03,	/* F/NL port */
+	FC_NS_NX_PORT =	0x7f,	/* Nx port */
+	FC_NS_F_PORT =	0x81,	/* F port */
+	FC_NS_FL_PORT =	0x82,	/* FL port */
+	FC_NS_E_PORT =	0x84,	/* E port */
+	FC_NS_B_PORT =	0x85,	/* B port */
+};
+
+/*
+ * Port type object.
+ */
+struct fc_ns_pt_obj {
+	__u8		pt_type;
+};
+
+/*
+ * Port ID object
+ */
+struct fc_ns_fid {
+	__u8		fp_flags;	/* flags for responses only */
+	__u8		fp_fid[3];
+};
+
+/*
+ * fp_flags in port ID object, for responses only.
+ */
+#define	FC_NS_FID_LAST	0x80		/* last object */
+
+/*
+ * FC4-types object.
+ */
+#define	FC_NS_TYPES	256	/* number of possible FC-4 types */
+#define	FC_NS_BPW	32	/* bits per word in bitmap */
+
+struct fc_ns_fts {
+	__be32	ff_type_map[FC_NS_TYPES / FC_NS_BPW]; /* bitmap of FC-4 types */
+};
+
+/*
+ * GID_PT request.
+ */
+struct fc_ns_gid_pt {
+	__u8		fn_pt_type;
+	__u8		fn_domain_id_scope;
+	__u8		fn_area_id_scope;
+	__u8		fn_resvd;
+};
+
+/*
+ * GID_FT or GPN_FT request.
+ */
+struct fc_ns_gid_ft {
+	__u8		fn_resvd;
+	__u8		fn_domain_id_scope;
+	__u8		fn_area_id_scope;
+	__u8		fn_fc4_type;
+};
+
+/*
+ * GPN_FT response.
+ */
+struct fc_gpn_ft_resp {
+	__u8		fp_flags;	/* see fp_flags definitions above */
+	__u8		fp_fid[3];	/* port ID */
+	__be32		fp_resvd;
+	__be64		fp_wwpn;	/* port name */
+};
+
+/*
+ * GID_PN request
+ */
+struct fc_ns_gid_pn {
+	__be64     fn_wwpn;    /* port name */
+};
+
+/*
+ * GID_PN response
+ */
+struct fc_gid_pn_resp {
+	__u8      fp_resvd;
+	__u8      fp_fid[3];     /* port ID */
+};
+
+/*
+ * RFT_ID request - register FC-4 types for ID.
+ */
+struct fc_ns_rft_id {
+	struct fc_ns_fid fr_fid;	/* port ID object */
+	struct fc_ns_fts fr_fts;	/* FC-4 types object */
+};
+
+/*
+ * RPN_ID request - register port name for ID.
+ * RNN_ID request - register node name for ID.
+ */
+struct fc_ns_rn_id {
+	struct fc_ns_fid fr_fid;	/* port ID object */
+	__be64		fr_wwn;		/* node name or port name */
+} __attribute__((__packed__));
+
+#endif /* _FC_NS_H_ */
diff --git a/include/scsi/fc_encode.h b/include/scsi/fc_encode.h
new file mode 100644
index 000000000000..6300f556bce5
--- /dev/null
+++ b/include/scsi/fc_encode.h
@@ -0,0 +1,309 @@
+/*
+ * Copyright(c) 2008 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Maintained at www.Open-FCoE.org
+ */
+
+#ifndef _FC_ENCODE_H_
+#define _FC_ENCODE_H_
+#include <asm/unaligned.h>
+
+struct fc_ns_rft {
+	struct fc_ns_fid fid;	/* port ID object */
+	struct fc_ns_fts fts;	/* FC4-types object */
+};
+
+struct fc_ct_req {
+	struct fc_ct_hdr hdr;
+	union {
+		struct fc_ns_gid_ft gid;
+		struct fc_ns_rn_id  rn;
+		struct fc_ns_rft rft;
+	} payload;
+};
+
+/**
+ * fill FC header fields in specified fc_frame
+ */
+static inline void fc_fill_fc_hdr(struct fc_frame *fp, enum fc_rctl r_ctl,
+				  u32 did, u32 sid, enum fc_fh_type type,
+				  u32 f_ctl, u32 parm_offset)
+{
+	struct fc_frame_header *fh;
+
+	fh = fc_frame_header_get(fp);
+	WARN_ON(r_ctl == 0);
+	fh->fh_r_ctl = r_ctl;
+	hton24(fh->fh_d_id, did);
+	hton24(fh->fh_s_id, sid);
+	fh->fh_type = type;
+	hton24(fh->fh_f_ctl, f_ctl);
+	fh->fh_cs_ctl = 0;
+	fh->fh_df_ctl = 0;
+	fh->fh_parm_offset = htonl(parm_offset);
+}
+
+/**
+ * fc_ct_hdr_fill- fills ct header and reset ct payload
+ * returns pointer to ct request.
+ */
+static inline struct fc_ct_req *fc_ct_hdr_fill(const struct fc_frame *fp,
+					       unsigned int op, size_t req_size)
+{
+	struct fc_ct_req *ct;
+	size_t ct_plen;
+
+	ct_plen  = sizeof(struct fc_ct_hdr) + req_size;
+	ct = fc_frame_payload_get(fp, ct_plen);
+	memset(ct, 0, ct_plen);
+	ct->hdr.ct_rev = FC_CT_REV;
+	ct->hdr.ct_fs_type = FC_FST_DIR;
+	ct->hdr.ct_fs_subtype = FC_NS_SUBTYPE;
+	ct->hdr.ct_cmd = htons((u16) op);
+	return ct;
+}
+
+/**
+ * fc_ct_fill - Fill in a name service request frame
+ */
+static inline int fc_ct_fill(struct fc_lport *lport, struct fc_frame *fp,
+		      unsigned int op, enum fc_rctl *r_ctl, u32 *did,
+		      enum fc_fh_type *fh_type)
+{
+	struct fc_ct_req *ct;
+
+	switch (op) {
+	case FC_NS_GPN_FT:
+		ct = fc_ct_hdr_fill(fp, op, sizeof(struct fc_ns_gid_ft));
+		ct->payload.gid.fn_fc4_type = FC_TYPE_FCP;
+		break;
+
+	case FC_NS_RFT_ID:
+		ct = fc_ct_hdr_fill(fp, op, sizeof(struct fc_ns_rft));
+		hton24(ct->payload.rft.fid.fp_fid,
+		       fc_host_port_id(lport->host));
+		ct->payload.rft.fts = lport->fcts;
+		break;
+
+	case FC_NS_RPN_ID:
+		ct = fc_ct_hdr_fill(fp, op, sizeof(struct fc_ns_rn_id));
+		hton24(ct->payload.rn.fr_fid.fp_fid,
+		       fc_host_port_id(lport->host));
+		ct->payload.rft.fts = lport->fcts;
+		put_unaligned_be64(lport->wwpn, &ct->payload.rn.fr_wwn);
+		break;
+
+	default:
+		FC_DBG("Invalid op code %x \n", op);
+		return -EINVAL;
+	}
+	*r_ctl = FC_RCTL_DD_UNSOL_CTL;
+	*did = FC_FID_DIR_SERV;
+	*fh_type = FC_TYPE_CT;
+	return 0;
+}
+
+/**
+ * fc_plogi_fill - Fill in plogi request frame
+ */
+static inline void fc_plogi_fill(struct fc_lport *lport, struct fc_frame *fp,
+				 unsigned int op)
+{
+	struct fc_els_flogi *plogi;
+	struct fc_els_csp *csp;
+	struct fc_els_cssp *cp;
+
+	plogi = fc_frame_payload_get(fp, sizeof(*plogi));
+	memset(plogi, 0, sizeof(*plogi));
+	plogi->fl_cmd = (u8) op;
+	put_unaligned_be64(lport->wwpn, &plogi->fl_wwpn);
+	put_unaligned_be64(lport->wwnn, &plogi->fl_wwnn);
+
+	csp = &plogi->fl_csp;
+	csp->sp_hi_ver = 0x20;
+	csp->sp_lo_ver = 0x20;
+	csp->sp_bb_cred = htons(10);	/* this gets set by gateway */
+	csp->sp_bb_data = htons((u16) lport->mfs);
+	cp = &plogi->fl_cssp[3 - 1];	/* class 3 parameters */
+	cp->cp_class = htons(FC_CPC_VALID | FC_CPC_SEQ);
+	csp->sp_features = htons(FC_SP_FT_CIRO);
+	csp->sp_tot_seq = htons(255);	/* seq. we accept */
+	csp->sp_rel_off = htons(0x1f);
+	csp->sp_e_d_tov = htonl(lport->e_d_tov);
+
+	cp->cp_rdfs = htons((u16) lport->mfs);
+	cp->cp_con_seq = htons(255);
+	cp->cp_open_seq = 1;
+}
+
+/**
+ * fc_flogi_fill - Fill in a flogi request frame.
+ */
+static inline void fc_flogi_fill(struct fc_lport *lport, struct fc_frame *fp)
+{
+	struct fc_els_csp *sp;
+	struct fc_els_cssp *cp;
+	struct fc_els_flogi *flogi;
+
+	flogi = fc_frame_payload_get(fp, sizeof(*flogi));
+	memset(flogi, 0, sizeof(*flogi));
+	flogi->fl_cmd = (u8) ELS_FLOGI;
+	put_unaligned_be64(lport->wwpn, &flogi->fl_wwpn);
+	put_unaligned_be64(lport->wwnn, &flogi->fl_wwnn);
+	sp = &flogi->fl_csp;
+	sp->sp_hi_ver = 0x20;
+	sp->sp_lo_ver = 0x20;
+	sp->sp_bb_cred = htons(10);	/* this gets set by gateway */
+	sp->sp_bb_data = htons((u16) lport->mfs);
+	cp = &flogi->fl_cssp[3 - 1];	/* class 3 parameters */
+	cp->cp_class = htons(FC_CPC_VALID | FC_CPC_SEQ);
+}
+
+/**
+ * fc_logo_fill - Fill in a logo request frame.
+ */
+static inline void fc_logo_fill(struct fc_lport *lport, struct fc_frame *fp)
+{
+	struct fc_els_logo *logo;
+
+	logo = fc_frame_payload_get(fp, sizeof(*logo));
+	memset(logo, 0, sizeof(*logo));
+	logo->fl_cmd = ELS_LOGO;
+	hton24(logo->fl_n_port_id, fc_host_port_id(lport->host));
+	logo->fl_n_port_wwn = htonll(lport->wwpn);
+}
+
+/**
+ * fc_rtv_fill - Fill in RTV (read timeout value) request frame.
+ */
+static inline void fc_rtv_fill(struct fc_lport *lport, struct fc_frame *fp)
+{
+	struct fc_els_rtv *rtv;
+
+	rtv = fc_frame_payload_get(fp, sizeof(*rtv));
+	memset(rtv, 0, sizeof(*rtv));
+	rtv->rtv_cmd = ELS_RTV;
+}
+
+/**
+ * fc_rec_fill - Fill in rec request frame
+ */
+static inline void fc_rec_fill(struct fc_lport *lport, struct fc_frame *fp)
+{
+	struct fc_els_rec *rec;
+	struct fc_exch *ep = fc_seq_exch(fr_seq(fp));
+
+	rec = fc_frame_payload_get(fp, sizeof(*rec));
+	memset(rec, 0, sizeof(*rec));
+	rec->rec_cmd = ELS_REC;
+	hton24(rec->rec_s_id, fc_host_port_id(lport->host));
+	rec->rec_ox_id = htons(ep->oxid);
+	rec->rec_rx_id = htons(ep->rxid);
+}
+
+/**
+ * fc_prli_fill - Fill in prli request frame
+ */
+static inline void fc_prli_fill(struct fc_lport *lport, struct fc_frame *fp)
+{
+	struct {
+		struct fc_els_prli prli;
+		struct fc_els_spp spp;
+	} *pp;
+
+	pp = fc_frame_payload_get(fp, sizeof(*pp));
+	memset(pp, 0, sizeof(*pp));
+	pp->prli.prli_cmd = ELS_PRLI;
+	pp->prli.prli_spp_len = sizeof(struct fc_els_spp);
+	pp->prli.prli_len = htons(sizeof(*pp));
+	pp->spp.spp_type = FC_TYPE_FCP;
+	pp->spp.spp_flags = FC_SPP_EST_IMG_PAIR;
+	pp->spp.spp_params = htonl(lport->service_params);
+}
+
+/**
+ * fc_scr_fill - Fill in a scr request frame.
+ */
+static inline void fc_scr_fill(struct fc_lport *lport, struct fc_frame *fp)
+{
+	struct fc_els_scr *scr;
+
+	scr = fc_frame_payload_get(fp, sizeof(*scr));
+	memset(scr, 0, sizeof(*scr));
+	scr->scr_cmd = ELS_SCR;
+	scr->scr_reg_func = ELS_SCRF_FULL;
+}
+
+/**
+ * fc_els_fill - Fill in an ELS  request frame
+ */
+static inline int fc_els_fill(struct fc_lport *lport, struct fc_rport *rport,
+		       struct fc_frame *fp, unsigned int op,
+		       enum fc_rctl *r_ctl, u32 *did, enum fc_fh_type *fh_type)
+{
+	switch (op) {
+	case ELS_PLOGI:
+		fc_plogi_fill(lport, fp, ELS_PLOGI);
+		*did = rport->port_id;
+		break;
+
+	case ELS_FLOGI:
+		fc_flogi_fill(lport, fp);
+		*did = FC_FID_FLOGI;
+		break;
+
+	case ELS_LOGO:
+		fc_logo_fill(lport, fp);
+		*did = FC_FID_FLOGI;
+		/*
+		 * if rport is valid then it
+		 * is port logo, therefore
+		 * set did to rport id.
+		 */
+		if (rport)
+			*did = rport->port_id;
+		break;
+
+	case ELS_RTV:
+		fc_rtv_fill(lport, fp);
+		*did = rport->port_id;
+		break;
+
+	case ELS_REC:
+		fc_rec_fill(lport, fp);
+		*did = rport->port_id;
+		break;
+
+	case ELS_PRLI:
+		fc_prli_fill(lport, fp);
+		*did = rport->port_id;
+		break;
+
+	case ELS_SCR:
+		fc_scr_fill(lport, fp);
+		*did = FC_FID_FCTRL;
+		break;
+
+	default:
+		FC_DBG("Invalid op code %x \n", op);
+		return -EINVAL;
+	}
+
+	*r_ctl = FC_RCTL_ELS_REQ;
+	*fh_type = FC_TYPE_ELS;
+	return 0;
+}
+#endif /* _FC_ENCODE_H_ */
diff --git a/include/scsi/fc_frame.h b/include/scsi/fc_frame.h
new file mode 100644
index 000000000000..04d34a71355f
--- /dev/null
+++ b/include/scsi/fc_frame.h
@@ -0,0 +1,242 @@
+/*
+ * Copyright(c) 2007 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Maintained at www.Open-FCoE.org
+ */
+
+#ifndef _FC_FRAME_H_
+#define _FC_FRAME_H_
+
+#include <linux/scatterlist.h>
+#include <linux/skbuff.h>
+#include <scsi/scsi_cmnd.h>
+
+#include <scsi/fc/fc_fs.h>
+#include <scsi/fc/fc_fcp.h>
+#include <scsi/fc/fc_encaps.h>
+
+/*
+ * The fc_frame interface is used to pass frame data between functions.
+ * The frame includes the data buffer, length, and SOF / EOF delimiter types.
+ * A pointer to the port structure of the receiving port is also includeded.
+ */
+
+#define	FC_FRAME_HEADROOM	32	/* headroom for VLAN + FCoE headers */
+#define	FC_FRAME_TAILROOM	8	/* trailer space for FCoE */
+
+/*
+ * Information about an individual fibre channel frame received or to be sent.
+ * The buffer may be in up to 4 additional non-contiguous sections,
+ * but the linear section must hold the frame header.
+ */
+#define FC_FRAME_SG_LEN		4	/* scatter/gather list maximum length */
+
+#define fp_skb(fp)	(&((fp)->skb))
+#define fr_hdr(fp)	((fp)->skb.data)
+#define fr_len(fp)	((fp)->skb.len)
+#define fr_cb(fp)	((struct fcoe_rcv_info *)&((fp)->skb.cb[0]))
+#define fr_dev(fp)	(fr_cb(fp)->fr_dev)
+#define fr_seq(fp)	(fr_cb(fp)->fr_seq)
+#define fr_sof(fp)	(fr_cb(fp)->fr_sof)
+#define fr_eof(fp)	(fr_cb(fp)->fr_eof)
+#define fr_flags(fp)	(fr_cb(fp)->fr_flags)
+#define fr_max_payload(fp)	(fr_cb(fp)->fr_max_payload)
+#define fr_cmd(fp)	(fr_cb(fp)->fr_cmd)
+#define fr_dir(fp)	(fr_cmd(fp)->sc_data_direction)
+#define fr_crc(fp)	(fr_cb(fp)->fr_crc)
+
+struct fc_frame {
+	struct sk_buff skb;
+};
+
+struct fcoe_rcv_info {
+	struct packet_type  *ptype;
+	struct fc_lport	*fr_dev;	/* transport layer private pointer */
+	struct fc_seq	*fr_seq;	/* for use with exchange manager */
+	struct scsi_cmnd *fr_cmd;	/* for use of scsi command */
+	u32		fr_crc;
+	u16		fr_max_payload;	/* max FC payload */
+	enum fc_sof	fr_sof;		/* start of frame delimiter */
+	enum fc_eof	fr_eof;		/* end of frame delimiter */
+	u8		fr_flags;	/* flags - see below */
+};
+
+
+/*
+ * Get fc_frame pointer for an skb that's already been imported.
+ */
+static inline struct fcoe_rcv_info *fcoe_dev_from_skb(const struct sk_buff *skb)
+{
+	BUILD_BUG_ON(sizeof(struct fcoe_rcv_info) > sizeof(skb->cb));
+	return (struct fcoe_rcv_info *) skb->cb;
+}
+
+/*
+ * fr_flags.
+ */
+#define	FCPHF_CRC_UNCHECKED	0x01	/* CRC not computed, still appended */
+
+/*
+ * Initialize a frame.
+ * We don't do a complete memset here for performance reasons.
+ * The caller must set fr_free, fr_hdr, fr_len, fr_sof, and fr_eof eventually.
+ */
+static inline void fc_frame_init(struct fc_frame *fp)
+{
+	fr_dev(fp) = NULL;
+	fr_seq(fp) = NULL;
+	fr_flags(fp) = 0;
+}
+
+struct fc_frame *fc_frame_alloc_fill(struct fc_lport *, size_t payload_len);
+
+struct fc_frame *__fc_frame_alloc(size_t payload_len);
+
+/*
+ * Get frame for sending via port.
+ */
+static inline struct fc_frame *_fc_frame_alloc(struct fc_lport *dev,
+					       size_t payload_len)
+{
+	return __fc_frame_alloc(payload_len);
+}
+
+/*
+ * Allocate fc_frame structure and buffer.  Set the initial length to
+ * payload_size + sizeof (struct fc_frame_header).
+ */
+static inline struct fc_frame *fc_frame_alloc(struct fc_lport *dev, size_t len)
+{
+	struct fc_frame *fp;
+
+	/*
+	 * Note: Since len will often be a constant multiple of 4,
+	 * this check will usually be evaluated and eliminated at compile time.
+	 */
+	if ((len % 4) != 0)
+		fp = fc_frame_alloc_fill(dev, len);
+	else
+		fp = _fc_frame_alloc(dev, len);
+	return fp;
+}
+
+/*
+ * Free the fc_frame structure and buffer.
+ */
+static inline void fc_frame_free(struct fc_frame *fp)
+{
+	kfree_skb(fp_skb(fp));
+}
+
+static inline int fc_frame_is_linear(struct fc_frame *fp)
+{
+	return !skb_is_nonlinear(fp_skb(fp));
+}
+
+/*
+ * Get frame header from message in fc_frame structure.
+ * This hides a cast and provides a place to add some checking.
+ */
+static inline
+struct fc_frame_header *fc_frame_header_get(const struct fc_frame *fp)
+{
+	WARN_ON(fr_len(fp) < sizeof(struct fc_frame_header));
+	return (struct fc_frame_header *) fr_hdr(fp);
+}
+
+/*
+ * Get frame payload from message in fc_frame structure.
+ * This hides a cast and provides a place to add some checking.
+ * The len parameter is the minimum length for the payload portion.
+ * Returns NULL if the frame is too short.
+ *
+ * This assumes the interesting part of the payload is in the first part
+ * of the buffer for received data.  This may not be appropriate to use for
+ * buffers being transmitted.
+ */
+static inline void *fc_frame_payload_get(const struct fc_frame *fp,
+					 size_t len)
+{
+	void *pp = NULL;
+
+	if (fr_len(fp) >= sizeof(struct fc_frame_header) + len)
+		pp = fc_frame_header_get(fp) + 1;
+	return pp;
+}
+
+/*
+ * Get frame payload opcode (first byte) from message in fc_frame structure.
+ * This hides a cast and provides a place to add some checking. Return 0
+ * if the frame has no payload.
+ */
+static inline u8 fc_frame_payload_op(const struct fc_frame *fp)
+{
+	u8 *cp;
+
+	cp = fc_frame_payload_get(fp, sizeof(u8));
+	if (!cp)
+		return 0;
+	return *cp;
+
+}
+
+/*
+ * Get FC class from frame.
+ */
+static inline enum fc_class fc_frame_class(const struct fc_frame *fp)
+{
+	return fc_sof_class(fr_sof(fp));
+}
+
+/*
+ * Check the CRC in a frame.
+ * The CRC immediately follows the last data item *AFTER* the length.
+ * The return value is zero if the CRC matches.
+ */
+u32 fc_frame_crc_check(struct fc_frame *);
+
+static inline u8 fc_frame_rctl(const struct fc_frame *fp)
+{
+	return fc_frame_header_get(fp)->fh_r_ctl;
+}
+
+static inline bool fc_frame_is_cmd(const struct fc_frame *fp)
+{
+	return fc_frame_rctl(fp) == FC_RCTL_DD_UNSOL_CMD;
+}
+
+static inline bool fc_frame_is_read(const struct fc_frame *fp)
+{
+	if (fc_frame_is_cmd(fp) && fr_cmd(fp))
+		return fr_dir(fp) == DMA_FROM_DEVICE;
+	return false;
+}
+
+static inline bool fc_frame_is_write(const struct fc_frame *fp)
+{
+	if (fc_frame_is_cmd(fp) && fr_cmd(fp))
+		return fr_dir(fp) == DMA_TO_DEVICE;
+	return false;
+}
+
+/*
+ * Check for leaks.
+ * Print the frame header of any currently allocated frame, assuming there
+ * should be none at this point.
+ */
+void fc_frame_leak_check(void);
+
+#endif /* _FC_FRAME_H_ */
diff --git a/include/scsi/fc_transport_fcoe.h b/include/scsi/fc_transport_fcoe.h
new file mode 100644
index 000000000000..8dca2af14ffc
--- /dev/null
+++ b/include/scsi/fc_transport_fcoe.h
@@ -0,0 +1,54 @@
+#ifndef FC_TRANSPORT_FCOE_H
+#define FC_TRANSPORT_FCOE_H
+
+#include <linux/device.h>
+#include <linux/netdevice.h>
+#include <scsi/scsi_host.h>
+#include <scsi/libfc.h>
+
+/**
+ * struct fcoe_transport - FCoE transport struct for generic transport
+ * for Ethernet devices as well as pure HBAs
+ *
+ * @name: name for thsi transport
+ * @bus: physical bus type (pci_bus_type)
+ * @driver: physical bus driver for network device
+ * @create: entry create function
+ * @destroy: exit destroy function
+ * @list: list of transports
+ */
+struct fcoe_transport {
+	char *name;
+	unsigned short vendor;
+	unsigned short device;
+	struct bus_type *bus;
+	struct device_driver *driver;
+	int (*create)(struct net_device *device);
+	int (*destroy)(struct net_device *device);
+	bool (*match)(struct net_device *device);
+	struct list_head list;
+	struct list_head devlist;
+	struct mutex devlock;
+};
+
+/**
+ * MODULE_ALIAS_FCOE_PCI
+ *
+ * some care must be taken with this, vendor and device MUST be a hex value
+ * preceded with 0x and with letters in lower case (0x12ab, not 0x12AB or 12AB)
+ */
+#define MODULE_ALIAS_FCOE_PCI(vendor, device) \
+	MODULE_ALIAS("fcoe-pci-" __stringify(vendor) "-" __stringify(device))
+
+/* exported funcs */
+int fcoe_transport_attach(struct net_device *netdev);
+int fcoe_transport_release(struct net_device *netdev);
+int fcoe_transport_register(struct fcoe_transport *t);
+int fcoe_transport_unregister(struct fcoe_transport *t);
+int fcoe_load_transport_driver(struct net_device *netdev);
+int __init fcoe_transport_init(void);
+int __exit fcoe_transport_exit(void);
+
+/* fcow_sw is the default transport */
+extern struct fcoe_transport fcoe_sw_transport;
+#endif /* FC_TRANSPORT_FCOE_H */
diff --git a/include/scsi/iscsi_if.h b/include/scsi/iscsi_if.h
index 16be12f1cbe8..d0ed5226f8c4 100644
--- a/include/scsi/iscsi_if.h
+++ b/include/scsi/iscsi_if.h
@@ -213,6 +213,8 @@ enum iscsi_err {
 	ISCSI_ERR_DATA_DGST		= ISCSI_ERR_BASE + 15,
 	ISCSI_ERR_PARAM_NOT_FOUND	= ISCSI_ERR_BASE + 16,
 	ISCSI_ERR_NO_SCSI_CMD		= ISCSI_ERR_BASE + 17,
+	ISCSI_ERR_INVALID_HOST		= ISCSI_ERR_BASE + 18,
+	ISCSI_ERR_XMIT_FAILED		= ISCSI_ERR_BASE + 19,
 };
 
 /*
@@ -331,8 +333,11 @@ enum iscsi_host_param {
 #define CAP_TEXT_NEGO		0x80
 #define CAP_MARKERS		0x100
 #define CAP_FW_DB		0x200
-#define CAP_SENDTARGETS_OFFLOAD	0x400
-#define CAP_DATA_PATH_OFFLOAD	0x800
+#define CAP_SENDTARGETS_OFFLOAD	0x400	/* offload discovery process */
+#define CAP_DATA_PATH_OFFLOAD	0x800	/* offload entire IO path */
+#define CAP_DIGEST_OFFLOAD	0x1000	/* offload hdr and data digests */
+#define CAP_PADDING_OFFLOAD	0x2000	/* offload padding insertion, removal,
+					 and verification */
 
 /*
  * These flags describes reason of stop_conn() call
diff --git a/include/scsi/libfc.h b/include/scsi/libfc.h
new file mode 100644
index 000000000000..9f2876397dda
--- /dev/null
+++ b/include/scsi/libfc.h
@@ -0,0 +1,938 @@
+/*
+ * Copyright(c) 2007 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Maintained at www.Open-FCoE.org
+ */
+
+#ifndef _LIBFC_H_
+#define _LIBFC_H_
+
+#include <linux/timer.h>
+#include <linux/if.h>
+
+#include <scsi/scsi_transport.h>
+#include <scsi/scsi_transport_fc.h>
+
+#include <scsi/fc/fc_fcp.h>
+#include <scsi/fc/fc_ns.h>
+#include <scsi/fc/fc_els.h>
+#include <scsi/fc/fc_gs.h>
+
+#include <scsi/fc_frame.h>
+
+#define LIBFC_DEBUG
+
+#ifdef LIBFC_DEBUG
+/* Log messages */
+#define FC_DBG(fmt, args...)						\
+	do {								\
+		printk(KERN_INFO "%s " fmt, __func__, ##args);		\
+	} while (0)
+#else
+#define FC_DBG(fmt, args...)
+#endif
+
+/*
+ * libfc error codes
+ */
+#define	FC_NO_ERR	0	/* no error */
+#define	FC_EX_TIMEOUT	1	/* Exchange timeout */
+#define	FC_EX_CLOSED	2	/* Exchange closed */
+
+/* some helpful macros */
+
+#define ntohll(x) be64_to_cpu(x)
+#define htonll(x) cpu_to_be64(x)
+
+#define ntoh24(p) (((p)[0] << 16) | ((p)[1] << 8) | ((p)[2]))
+
+#define hton24(p, v)	do {			\
+		p[0] = (((v) >> 16) & 0xFF);	\
+		p[1] = (((v) >> 8) & 0xFF);	\
+		p[2] = ((v) & 0xFF);		\
+	} while (0)
+
+/*
+ * FC HBA status
+ */
+#define FC_PAUSE		    (1 << 1)
+#define FC_LINK_UP		    (1 << 0)
+
+enum fc_lport_state {
+	LPORT_ST_NONE = 0,
+	LPORT_ST_FLOGI,
+	LPORT_ST_DNS,
+	LPORT_ST_RPN_ID,
+	LPORT_ST_RFT_ID,
+	LPORT_ST_SCR,
+	LPORT_ST_READY,
+	LPORT_ST_LOGO,
+	LPORT_ST_RESET
+};
+
+enum fc_disc_event {
+	DISC_EV_NONE = 0,
+	DISC_EV_SUCCESS,
+	DISC_EV_FAILED
+};
+
+enum fc_rport_state {
+	RPORT_ST_NONE = 0,
+	RPORT_ST_INIT,		/* initialized */
+	RPORT_ST_PLOGI,		/* waiting for PLOGI completion */
+	RPORT_ST_PRLI,		/* waiting for PRLI completion */
+	RPORT_ST_RTV,		/* waiting for RTV completion */
+	RPORT_ST_READY,		/* ready for use */
+	RPORT_ST_LOGO,		/* port logout sent */
+};
+
+enum fc_rport_trans_state {
+	FC_PORTSTATE_ROGUE,
+	FC_PORTSTATE_REAL,
+};
+
+/**
+ * struct fc_disc_port - temporary discovery port to hold rport identifiers
+ * @lp: Fibre Channel host port instance
+ * @peers: node for list management during discovery and RSCN processing
+ * @ids: identifiers structure to pass to fc_remote_port_add()
+ * @rport_work: work struct for starting the rport state machine
+ */
+struct fc_disc_port {
+	struct fc_lport             *lp;
+	struct list_head            peers;
+	struct fc_rport_identifiers ids;
+	struct work_struct	    rport_work;
+};
+
+enum fc_rport_event {
+	RPORT_EV_NONE = 0,
+	RPORT_EV_CREATED,
+	RPORT_EV_FAILED,
+	RPORT_EV_STOP,
+	RPORT_EV_LOGO
+};
+
+struct fc_rport_operations {
+	void (*event_callback)(struct fc_lport *, struct fc_rport *,
+			       enum fc_rport_event);
+};
+
+/**
+ * struct fc_rport_libfc_priv - libfc internal information about a remote port
+ * @local_port: Fibre Channel host port instance
+ * @rp_state: state tracks progress of PLOGI, PRLI, and RTV exchanges
+ * @flags: REC and RETRY supported flags
+ * @max_seq: maximum number of concurrent sequences
+ * @retries: retry count in current state
+ * @e_d_tov: error detect timeout value (in msec)
+ * @r_a_tov: resource allocation timeout value (in msec)
+ * @rp_mutex: mutex protects rport
+ * @retry_work:
+ * @event_callback: Callback for rport READY, FAILED or LOGO
+ */
+struct fc_rport_libfc_priv {
+	struct fc_lport		   *local_port;
+	enum fc_rport_state        rp_state;
+	u16			   flags;
+	#define FC_RP_FLAGS_REC_SUPPORTED	(1 << 0)
+	#define FC_RP_FLAGS_RETRY		(1 << 1)
+	u16		           max_seq;
+	unsigned int	           retries;
+	unsigned int	           e_d_tov;
+	unsigned int	           r_a_tov;
+	enum fc_rport_trans_state  trans_state;
+	struct mutex               rp_mutex;
+	struct delayed_work	   retry_work;
+	enum fc_rport_event        event;
+	struct fc_rport_operations *ops;
+	struct list_head           peers;
+	struct work_struct         event_work;
+};
+
+#define PRIV_TO_RPORT(x)						\
+	(struct fc_rport *)((void *)x - sizeof(struct fc_rport));
+#define RPORT_TO_PRIV(x)						\
+	(struct fc_rport_libfc_priv *)((void *)x + sizeof(struct fc_rport));
+
+struct fc_rport *fc_rport_rogue_create(struct fc_disc_port *);
+
+static inline void fc_rport_set_name(struct fc_rport *rport, u64 wwpn, u64 wwnn)
+{
+	rport->node_name = wwnn;
+	rport->port_name = wwpn;
+}
+
+/*
+ * fcoe stats structure
+ */
+struct fcoe_dev_stats {
+	u64		SecondsSinceLastReset;
+	u64		TxFrames;
+	u64		TxWords;
+	u64		RxFrames;
+	u64		RxWords;
+	u64		ErrorFrames;
+	u64		DumpedFrames;
+	u64		LinkFailureCount;
+	u64		LossOfSignalCount;
+	u64		InvalidTxWordCount;
+	u64		InvalidCRCCount;
+	u64		InputRequests;
+	u64		OutputRequests;
+	u64		ControlRequests;
+	u64		InputMegabytes;
+	u64		OutputMegabytes;
+};
+
+/*
+ * els data is used for passing ELS respone specific
+ * data to send ELS response mainly using infomation
+ * in exchange and sequence in EM layer.
+ */
+struct fc_seq_els_data {
+	struct fc_frame *fp;
+	enum fc_els_rjt_reason reason;
+	enum fc_els_rjt_explan explan;
+};
+
+/*
+ * FCP request structure, one for each scsi cmd request
+ */
+struct fc_fcp_pkt {
+	/*
+	 * housekeeping stuff
+	 */
+	struct fc_lport *lp;	/* handle to hba struct */
+	u16		state;		/* scsi_pkt state state */
+	u16		tgt_flags;	/* target flags	 */
+	atomic_t	ref_cnt;	/* fcp pkt ref count */
+	spinlock_t	scsi_pkt_lock;	/* Must be taken before the host lock
+					 * if both are held at the same time */
+	/*
+	 * SCSI I/O related stuff
+	 */
+	struct scsi_cmnd *cmd;		/* scsi command pointer. set/clear
+					 * under host lock */
+	struct list_head list;		/* tracks queued commands. access under
+					 * host lock */
+	/*
+	 * timeout related stuff
+	 */
+	struct timer_list timer;	/* command timer */
+	struct completion tm_done;
+	int	wait_for_comp;
+	unsigned long	start_time;	/* start jiffie */
+	unsigned long	end_time;	/* end jiffie */
+	unsigned long	last_pkt_time;	 /* jiffies of last frame received */
+
+	/*
+	 * scsi cmd and data transfer information
+	 */
+	u32		data_len;
+	/*
+	 * transport related veriables
+	 */
+	struct fcp_cmnd cdb_cmd;
+	size_t		xfer_len;
+	u32		xfer_contig_end; /* offset of end of contiguous xfer */
+	u16		max_payload;	/* max payload size in bytes */
+
+	/*
+	 * scsi/fcp return status
+	 */
+	u32		io_status;	/* SCSI result upper 24 bits */
+	u8		cdb_status;
+	u8		status_code;	/* FCP I/O status */
+	/* bit 3 Underrun bit 2: overrun */
+	u8		scsi_comp_flags;
+	u32		req_flags;	/* bit 0: read bit:1 write */
+	u32		scsi_resid;	/* residule length */
+
+	struct fc_rport	*rport;		/* remote port pointer */
+	struct fc_seq	*seq_ptr;	/* current sequence pointer */
+	/*
+	 * Error Processing
+	 */
+	u8		recov_retry;	/* count of recovery retries */
+	struct fc_seq	*recov_seq;	/* sequence for REC or SRR */
+};
+
+/*
+ * Structure and function definitions for managing Fibre Channel Exchanges
+ * and Sequences
+ *
+ * fc_exch holds state for one exchange and links to its active sequence.
+ *
+ * fc_seq holds the state for an individual sequence.
+ */
+
+struct fc_exch_mgr;
+
+/*
+ * Sequence.
+ */
+struct fc_seq {
+	u8	id;		/* seq ID */
+	u16	ssb_stat;	/* status flags for sequence status block */
+	u16	cnt;		/* frames sent so far on sequence */
+	u32	rec_data;	/* FC-4 value for REC */
+};
+
+#define FC_EX_DONE		(1 << 0) /* ep is completed */
+#define FC_EX_RST_CLEANUP	(1 << 1) /* reset is forcing completion */
+
+/*
+ * Exchange.
+ *
+ * Locking notes: The ex_lock protects following items:
+ *	state, esb_stat, f_ctl, seq.ssb_stat
+ *	seq_id
+ *	sequence allocation
+ */
+struct fc_exch {
+	struct fc_exch_mgr *em;		/* exchange manager */
+	u32		state;		/* internal driver state */
+	u16		xid;		/* our exchange ID */
+	struct list_head	ex_list;	/* free or busy list linkage */
+	spinlock_t	ex_lock;	/* lock covering exchange state */
+	atomic_t	ex_refcnt;	/* reference counter */
+	struct delayed_work timeout_work; /* timer for upper level protocols */
+	struct fc_lport	*lp;		/* fc device instance */
+	u16		oxid;		/* originator's exchange ID */
+	u16		rxid;		/* responder's exchange ID */
+	u32		oid;		/* originator's FCID */
+	u32		sid;		/* source FCID */
+	u32		did;		/* destination FCID */
+	u32		esb_stat;	/* exchange status for ESB */
+	u32		r_a_tov;	/* r_a_tov from rport (msec) */
+	u8		seq_id;		/* next sequence ID to use */
+	u32		f_ctl;		/* F_CTL flags for sequences */
+	u8		fh_type;	/* frame type */
+	enum fc_class	class;		/* class of service */
+	struct fc_seq	seq;		/* single sequence */
+	/*
+	 * Handler for responses to this current exchange.
+	 */
+	void		(*resp)(struct fc_seq *, struct fc_frame *, void *);
+	void		(*destructor)(struct fc_seq *, void *);
+	/*
+	 * arg is passed as void pointer to exchange
+	 * resp and destructor handlers
+	 */
+	void		*arg;
+};
+#define	fc_seq_exch(sp) container_of(sp, struct fc_exch, seq)
+
+struct libfc_function_template {
+
+	/**
+	 * Mandatory Fields
+	 *
+	 * These handlers must be implemented by the LLD.
+	 */
+
+	/*
+	 * Interface to send a FC frame
+	 */
+	int (*frame_send)(struct fc_lport *lp, struct fc_frame *fp);
+
+	/**
+	 * Optional Fields
+	 *
+	 * The LLD may choose to implement any of the following handlers.
+	 * If LLD doesn't specify hander and leaves its pointer NULL then
+	 * the default libfc function will be used for that handler.
+	 */
+
+	/**
+	 * ELS/CT interfaces
+	 */
+
+	/*
+	 * elsct_send - sends ELS/CT frame
+	 */
+	struct fc_seq *(*elsct_send)(struct fc_lport *lport,
+				     struct fc_rport *rport,
+				     struct fc_frame *fp,
+				     unsigned int op,
+				     void (*resp)(struct fc_seq *,
+					     struct fc_frame *fp,
+					     void *arg),
+				     void *arg, u32 timer_msec);
+	/**
+	 * Exhance Manager interfaces
+	 */
+
+	/*
+	 * Send the FC frame payload using a new exchange and sequence.
+	 *
+	 * The frame pointer with some of the header's fields must be
+	 * filled before calling exch_seq_send(), those fields are,
+	 *
+	 * - routing control
+	 * - FC port did
+	 * - FC port sid
+	 * - FC header type
+	 * - frame control
+	 * - parameter or relative offset
+	 *
+	 * The exchange response handler is set in this routine to resp()
+	 * function pointer. It can be called in two scenarios: if a timeout
+	 * occurs or if a response frame is received for the exchange. The
+	 * fc_frame pointer in response handler will also indicate timeout
+	 * as error using IS_ERR related macros.
+	 *
+	 * The exchange destructor handler is also set in this routine.
+	 * The destructor handler is invoked by EM layer when exchange
+	 * is about to free, this can be used by caller to free its
+	 * resources along with exchange free.
+	 *
+	 * The arg is passed back to resp and destructor handler.
+	 *
+	 * The timeout value (in msec) for an exchange is set if non zero
+	 * timer_msec argument is specified. The timer is canceled when
+	 * it fires or when the exchange is done. The exchange timeout handler
+	 * is registered by EM layer.
+	 */
+	struct fc_seq *(*exch_seq_send)(struct fc_lport *lp,
+					struct fc_frame *fp,
+					void (*resp)(struct fc_seq *sp,
+						     struct fc_frame *fp,
+						     void *arg),
+					void (*destructor)(struct fc_seq *sp,
+							   void *arg),
+					void *arg, unsigned int timer_msec);
+
+	/*
+	 * send a frame using existing sequence and exchange.
+	 */
+	int (*seq_send)(struct fc_lport *lp, struct fc_seq *sp,
+			struct fc_frame *fp);
+
+	/*
+	 * Send ELS response using mainly infomation
+	 * in exchange and sequence in EM layer.
+	 */
+	void (*seq_els_rsp_send)(struct fc_seq *sp, enum fc_els_cmd els_cmd,
+				 struct fc_seq_els_data *els_data);
+
+	/*
+	 * Abort an exchange and sequence. Generally called because of a
+	 * exchange timeout or an abort from the upper layer.
+	 *
+	 * A timer_msec can be specified for abort timeout, if non-zero
+	 * timer_msec value is specified then exchange resp handler
+	 * will be called with timeout error if no response to abort.
+	 */
+	int (*seq_exch_abort)(const struct fc_seq *req_sp,
+			      unsigned int timer_msec);
+
+	/*
+	 * Indicate that an exchange/sequence tuple is complete and the memory
+	 * allocated for the related objects may be freed.
+	 */
+	void (*exch_done)(struct fc_seq *sp);
+
+	/*
+	 * Assigns a EM and a free XID for an new exchange and then
+	 * allocates a new exchange and sequence pair.
+	 * The fp can be used to determine free XID.
+	 */
+	struct fc_exch *(*exch_get)(struct fc_lport *lp, struct fc_frame *fp);
+
+	/*
+	 * Release previously assigned XID by exch_get API.
+	 * The LLD may implement this if XID is assigned by LLD
+	 * in exch_get().
+	 */
+	void (*exch_put)(struct fc_lport *lp, struct fc_exch_mgr *mp,
+			 u16 ex_id);
+
+	/*
+	 * Start a new sequence on the same exchange/sequence tuple.
+	 */
+	struct fc_seq *(*seq_start_next)(struct fc_seq *sp);
+
+	/*
+	 * Reset an exchange manager, completing all sequences and exchanges.
+	 * If s_id is non-zero, reset only exchanges originating from that FID.
+	 * If d_id is non-zero, reset only exchanges sending to that FID.
+	 */
+	void (*exch_mgr_reset)(struct fc_exch_mgr *,
+			       u32 s_id, u32 d_id);
+
+	void (*rport_flush_queue)(void);
+	/**
+	 * Local Port interfaces
+	 */
+
+	/*
+	 * Receive a frame to a local port.
+	 */
+	void (*lport_recv)(struct fc_lport *lp, struct fc_seq *sp,
+			   struct fc_frame *fp);
+
+	int (*lport_reset)(struct fc_lport *);
+
+	/**
+	 * Remote Port interfaces
+	 */
+
+	/*
+	 * Initiates the RP state machine. It is called from the LP module.
+	 * This function will issue the following commands to the N_Port
+	 * identified by the FC ID provided.
+	 *
+	 * - PLOGI
+	 * - PRLI
+	 * - RTV
+	 */
+	int (*rport_login)(struct fc_rport *rport);
+
+	/*
+	 * Logoff, and remove the rport from the transport if
+	 * it had been added. This will send a LOGO to the target.
+	 */
+	int (*rport_logoff)(struct fc_rport *rport);
+
+	/*
+	 * Recieve a request from a remote port.
+	 */
+	void (*rport_recv_req)(struct fc_seq *, struct fc_frame *,
+			       struct fc_rport *);
+
+	struct fc_rport *(*rport_lookup)(const struct fc_lport *, u32);
+
+	/**
+	 * FCP interfaces
+	 */
+
+	/*
+	 * Send a fcp cmd from fsp pkt.
+	 * Called with the SCSI host lock unlocked and irqs disabled.
+	 *
+	 * The resp handler is called when FCP_RSP received.
+	 *
+	 */
+	int (*fcp_cmd_send)(struct fc_lport *lp, struct fc_fcp_pkt *fsp,
+			    void (*resp)(struct fc_seq *, struct fc_frame *fp,
+					 void *arg));
+
+	/*
+	 * Used at least durring linkdown and reset
+	 */
+	void (*fcp_cleanup)(struct fc_lport *lp);
+
+	/*
+	 * Abort all I/O on a local port
+	 */
+	void (*fcp_abort_io)(struct fc_lport *lp);
+
+	/**
+	 * Discovery interfaces
+	 */
+
+	void (*disc_recv_req)(struct fc_seq *,
+			      struct fc_frame *, struct fc_lport *);
+
+	/*
+	 * Start discovery for a local port.
+	 */
+	void (*disc_start)(void (*disc_callback)(struct fc_lport *,
+						 enum fc_disc_event),
+			   struct fc_lport *);
+
+	/*
+	 * Stop discovery for a given lport. This will remove
+	 * all discovered rports
+	 */
+	void (*disc_stop) (struct fc_lport *);
+
+	/*
+	 * Stop discovery for a given lport. This will block
+	 * until all discovered rports are deleted from the
+	 * FC transport class
+	 */
+	void (*disc_stop_final) (struct fc_lport *);
+};
+
+/* information used by the discovery layer */
+struct fc_disc {
+	unsigned char		retry_count;
+	unsigned char		delay;
+	unsigned char		pending;
+	unsigned char		requested;
+	unsigned short		seq_count;
+	unsigned char		buf_len;
+	enum fc_disc_event	event;
+
+	void (*disc_callback)(struct fc_lport *,
+			      enum fc_disc_event);
+
+	struct list_head	 rports;
+	struct fc_lport		*lport;
+	struct mutex		disc_mutex;
+	struct fc_gpn_ft_resp	partial_buf;	/* partial name buffer */
+	struct delayed_work	disc_work;
+};
+
+struct fc_lport {
+	struct list_head list;
+
+	/* Associations */
+	struct Scsi_Host	*host;
+	struct fc_exch_mgr	*emp;
+	struct fc_rport		*dns_rp;
+	struct fc_rport		*ptp_rp;
+	void			*scsi_priv;
+	struct fc_disc          disc;
+
+	/* Operational Information */
+	struct libfc_function_template tt;
+	u16			link_status;
+	enum fc_lport_state	state;
+	unsigned long		boot_time;
+
+	struct fc_host_statistics host_stats;
+	struct fcoe_dev_stats	*dev_stats[NR_CPUS];
+	u64			wwpn;
+	u64			wwnn;
+	u8			retry_count;
+
+	/* Capabilities */
+	u32			sg_supp:1;	/* scatter gather supported */
+	u32			seq_offload:1;	/* seq offload supported */
+	u32			crc_offload:1;	/* crc offload supported */
+	u32			lro_enabled:1;	/* large receive offload */
+	u32			mfs;	        /* max FC payload size */
+	unsigned int		service_params;
+	unsigned int		e_d_tov;
+	unsigned int		r_a_tov;
+	u8			max_retry_count;
+	u16			link_speed;
+	u16			link_supported_speeds;
+	u16			lro_xid;	/* max xid for fcoe lro */
+	struct fc_ns_fts	fcts;	        /* FC-4 type masks */
+	struct fc_els_rnid_gen	rnid_gen;	/* RNID information */
+
+	/* Semaphores */
+	struct mutex lp_mutex;
+
+	/* Miscellaneous */
+	struct delayed_work	retry_work;
+	struct delayed_work	disc_work;
+};
+
+/**
+ * FC_LPORT HELPER FUNCTIONS
+ *****************************/
+static inline void *lport_priv(const struct fc_lport *lp)
+{
+	return (void *)(lp + 1);
+}
+
+static inline int fc_lport_test_ready(struct fc_lport *lp)
+{
+	return lp->state == LPORT_ST_READY;
+}
+
+static inline void fc_set_wwnn(struct fc_lport *lp, u64 wwnn)
+{
+	lp->wwnn = wwnn;
+}
+
+static inline void fc_set_wwpn(struct fc_lport *lp, u64 wwnn)
+{
+	lp->wwpn = wwnn;
+}
+
+static inline void fc_lport_state_enter(struct fc_lport *lp,
+					enum fc_lport_state state)
+{
+	if (state != lp->state)
+		lp->retry_count = 0;
+	lp->state = state;
+}
+
+
+/**
+ * LOCAL PORT LAYER
+ *****************************/
+int fc_lport_init(struct fc_lport *lp);
+
+/*
+ * Destroy the specified local port by finding and freeing all
+ * fc_rports associated with it and then by freeing the fc_lport
+ * itself.
+ */
+int fc_lport_destroy(struct fc_lport *lp);
+
+/*
+ * Logout the specified local port from the fabric
+ */
+int fc_fabric_logoff(struct fc_lport *lp);
+
+/*
+ * Initiate the LP state machine. This handler will use fc_host_attr
+ * to store the FLOGI service parameters, so fc_host_attr must be
+ * initialized before calling this handler.
+ */
+int fc_fabric_login(struct fc_lport *lp);
+
+/*
+ * The link is up for the given local port.
+ */
+void fc_linkup(struct fc_lport *);
+
+/*
+ * Link is down for the given local port.
+ */
+void fc_linkdown(struct fc_lport *);
+
+/*
+ * Pause and unpause traffic.
+ */
+void fc_pause(struct fc_lport *);
+void fc_unpause(struct fc_lport *);
+
+/*
+ * Configure the local port.
+ */
+int fc_lport_config(struct fc_lport *);
+
+/*
+ * Reset the local port.
+ */
+int fc_lport_reset(struct fc_lport *);
+
+/*
+ * Set the mfs or reset
+ */
+int fc_set_mfs(struct fc_lport *lp, u32 mfs);
+
+
+/**
+ * REMOTE PORT LAYER
+ *****************************/
+int fc_rport_init(struct fc_lport *lp);
+void fc_rport_terminate_io(struct fc_rport *rp);
+
+/**
+ * DISCOVERY LAYER
+ *****************************/
+int fc_disc_init(struct fc_lport *lp);
+
+
+/**
+ * SCSI LAYER
+ *****************************/
+/*
+ * Initialize the SCSI block of libfc
+ */
+int fc_fcp_init(struct fc_lport *);
+
+/*
+ * This section provides an API which allows direct interaction
+ * with the SCSI-ml. Each of these functions satisfies a function
+ * pointer defined in Scsi_Host and therefore is always called
+ * directly from the SCSI-ml.
+ */
+int fc_queuecommand(struct scsi_cmnd *sc_cmd,
+		    void (*done)(struct scsi_cmnd *));
+
+/*
+ * complete processing of a fcp packet
+ *
+ * This function may sleep if a fsp timer is pending.
+ * The host lock must not be held by caller.
+ */
+void fc_fcp_complete(struct fc_fcp_pkt *fsp);
+
+/*
+ * Send an ABTS frame to the target device. The sc_cmd argument
+ * is a pointer to the SCSI command to be aborted.
+ */
+int fc_eh_abort(struct scsi_cmnd *sc_cmd);
+
+/*
+ * Reset a LUN by sending send the tm cmd to the target.
+ */
+int fc_eh_device_reset(struct scsi_cmnd *sc_cmd);
+
+/*
+ * Reset the host adapter.
+ */
+int fc_eh_host_reset(struct scsi_cmnd *sc_cmd);
+
+/*
+ * Check rport status.
+ */
+int fc_slave_alloc(struct scsi_device *sdev);
+
+/*
+ * Adjust the queue depth.
+ */
+int fc_change_queue_depth(struct scsi_device *sdev, int qdepth);
+
+/*
+ * Change the tag type.
+ */
+int fc_change_queue_type(struct scsi_device *sdev, int tag_type);
+
+/*
+ * Free memory pools used by the FCP layer.
+ */
+void fc_fcp_destroy(struct fc_lport *);
+
+/**
+ * ELS/CT interface
+ *****************************/
+/*
+ * Initializes ELS/CT interface
+ */
+int fc_elsct_init(struct fc_lport *lp);
+
+
+/**
+ * EXCHANGE MANAGER LAYER
+ *****************************/
+/*
+ * Initializes Exchange Manager related
+ * function pointers in struct libfc_function_template.
+ */
+int fc_exch_init(struct fc_lport *lp);
+
+/*
+ * Allocates an Exchange Manager (EM).
+ *
+ * The EM manages exchanges for their allocation and
+ * free, also allows exchange lookup for received
+ * frame.
+ *
+ * The class is used for initializing FC class of
+ * allocated exchange from EM.
+ *
+ * The min_xid and max_xid will limit new
+ * exchange ID (XID) within this range for
+ * a new exchange.
+ * The LLD may choose to have multiple EMs,
+ * e.g. one EM instance per CPU receive thread in LLD.
+ * The LLD can use exch_get() of struct libfc_function_template
+ * to specify XID for a new exchange within
+ * a specified EM instance.
+ *
+ * The em_idx to uniquely identify an EM instance.
+ */
+struct fc_exch_mgr *fc_exch_mgr_alloc(struct fc_lport *lp,
+				      enum fc_class class,
+				      u16 min_xid,
+				      u16 max_xid);
+
+/*
+ * Free an exchange manager.
+ */
+void fc_exch_mgr_free(struct fc_exch_mgr *mp);
+
+/*
+ * Receive a frame on specified local port and exchange manager.
+ */
+void fc_exch_recv(struct fc_lport *lp, struct fc_exch_mgr *mp,
+		  struct fc_frame *fp);
+
+/*
+ * This function is for exch_seq_send function pointer in
+ * struct libfc_function_template, see comment block on
+ * exch_seq_send for description of this function.
+ */
+struct fc_seq *fc_exch_seq_send(struct fc_lport *lp,
+				struct fc_frame *fp,
+				void (*resp)(struct fc_seq *sp,
+					     struct fc_frame *fp,
+					     void *arg),
+				void (*destructor)(struct fc_seq *sp,
+						   void *arg),
+				void *arg, u32 timer_msec);
+
+/*
+ * send a frame using existing sequence and exchange.
+ */
+int fc_seq_send(struct fc_lport *lp, struct fc_seq *sp, struct fc_frame *fp);
+
+/*
+ * Send ELS response using mainly infomation
+ * in exchange and sequence in EM layer.
+ */
+void fc_seq_els_rsp_send(struct fc_seq *sp, enum fc_els_cmd els_cmd,
+			 struct fc_seq_els_data *els_data);
+
+/*
+ * This function is for seq_exch_abort function pointer in
+ * struct libfc_function_template, see comment block on
+ * seq_exch_abort for description of this function.
+ */
+int fc_seq_exch_abort(const struct fc_seq *req_sp, unsigned int timer_msec);
+
+/*
+ * Indicate that an exchange/sequence tuple is complete and the memory
+ * allocated for the related objects may be freed.
+ */
+void fc_exch_done(struct fc_seq *sp);
+
+/*
+ * Assigns a EM and XID for a frame and then allocates
+ * a new exchange and sequence pair.
+ * The fp can be used to determine free XID.
+ */
+struct fc_exch *fc_exch_get(struct fc_lport *lp, struct fc_frame *fp);
+
+/*
+ * Allocate a new exchange and sequence pair.
+ * if ex_id is zero then next free exchange id
+ * from specified exchange manger mp will be assigned.
+ */
+struct fc_exch *fc_exch_alloc(struct fc_exch_mgr *mp,
+			      struct fc_frame *fp, u16 ex_id);
+/*
+ * Start a new sequence on the same exchange as the supplied sequence.
+ */
+struct fc_seq *fc_seq_start_next(struct fc_seq *sp);
+
+/*
+ * Reset an exchange manager, completing all sequences and exchanges.
+ * If s_id is non-zero, reset only exchanges originating from that FID.
+ * If d_id is non-zero, reset only exchanges sending to that FID.
+ */
+void fc_exch_mgr_reset(struct fc_exch_mgr *, u32 s_id, u32 d_id);
+
+/*
+ * Functions for fc_functions_template
+ */
+void fc_get_host_speed(struct Scsi_Host *shost);
+void fc_get_host_port_type(struct Scsi_Host *shost);
+void fc_get_host_port_state(struct Scsi_Host *shost);
+void fc_set_rport_loss_tmo(struct fc_rport *rport, u32 timeout);
+struct fc_host_statistics *fc_get_host_stats(struct Scsi_Host *);
+
+/*
+ * module setup functions.
+ */
+int fc_setup_exch_mgr(void);
+void fc_destroy_exch_mgr(void);
+int fc_setup_rport(void);
+void fc_destroy_rport(void);
+
+#endif /* _LIBFC_H_ */
diff --git a/include/scsi/libfcoe.h b/include/scsi/libfcoe.h
new file mode 100644
index 000000000000..89fdbb9a6a1b
--- /dev/null
+++ b/include/scsi/libfcoe.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright(c) 2007 - 2008 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Maintained at www.Open-FCoE.org
+ */
+
+#ifndef _LIBFCOE_H
+#define _LIBFCOE_H
+
+#include <linux/netdevice.h>
+#include <linux/skbuff.h>
+#include <scsi/fc/fc_fcoe.h>
+#include <scsi/libfc.h>
+
+/*
+ * this percpu struct for fcoe
+ */
+struct fcoe_percpu_s {
+	int		cpu;
+	struct task_struct *thread;
+	struct sk_buff_head fcoe_rx_list;
+	struct page *crc_eof_page;
+	int crc_eof_offset;
+};
+
+/*
+ * the fcoe sw transport private data
+ */
+struct fcoe_softc {
+	struct list_head list;
+	struct fc_lport *lp;
+	struct net_device *real_dev;
+	struct net_device *phys_dev;		/* device with ethtool_ops */
+	struct packet_type  fcoe_packet_type;
+	struct sk_buff_head fcoe_pending_queue;
+
+	u8 dest_addr[ETH_ALEN];
+	u8 ctl_src_addr[ETH_ALEN];
+	u8 data_src_addr[ETH_ALEN];
+	/*
+	 * fcoe protocol address learning related stuff
+	 */
+	u16 flogi_oxid;
+	u8 flogi_progress;
+	u8 address_mode;
+};
+
+static inline struct fcoe_softc *fcoe_softc(
+	const struct fc_lport *lp)
+{
+	return (struct fcoe_softc *)lport_priv(lp);
+}
+
+static inline struct net_device *fcoe_netdev(
+	const struct fc_lport *lp)
+{
+	return fcoe_softc(lp)->real_dev;
+}
+
+static inline struct fcoe_hdr *skb_fcoe_header(const struct sk_buff *skb)
+{
+	return (struct fcoe_hdr *)skb_network_header(skb);
+}
+
+static inline int skb_fcoe_offset(const struct sk_buff *skb)
+{
+	return skb_network_offset(skb);
+}
+
+static inline struct fc_frame_header *skb_fc_header(const struct sk_buff *skb)
+{
+	return (struct fc_frame_header *)skb_transport_header(skb);
+}
+
+static inline int skb_fc_offset(const struct sk_buff *skb)
+{
+	return skb_transport_offset(skb);
+}
+
+static inline void skb_reset_fc_header(struct sk_buff *skb)
+{
+	skb_reset_network_header(skb);
+	skb_set_transport_header(skb, skb_network_offset(skb) +
+				 sizeof(struct fcoe_hdr));
+}
+
+static inline bool skb_fc_is_data(const struct sk_buff *skb)
+{
+	return skb_fc_header(skb)->fh_r_ctl == FC_RCTL_DD_SOL_DATA;
+}
+
+static inline bool skb_fc_is_cmd(const struct sk_buff *skb)
+{
+	return skb_fc_header(skb)->fh_r_ctl == FC_RCTL_DD_UNSOL_CMD;
+}
+
+static inline bool skb_fc_has_exthdr(const struct sk_buff *skb)
+{
+	return (skb_fc_header(skb)->fh_r_ctl == FC_RCTL_VFTH) ||
+	    (skb_fc_header(skb)->fh_r_ctl == FC_RCTL_IFRH) ||
+	    (skb_fc_header(skb)->fh_r_ctl == FC_RCTL_ENCH);
+}
+
+static inline bool skb_fc_is_roff(const struct sk_buff *skb)
+{
+	return skb_fc_header(skb)->fh_f_ctl[2] & FC_FC_REL_OFF;
+}
+
+static inline u16 skb_fc_oxid(const struct sk_buff *skb)
+{
+	return be16_to_cpu(skb_fc_header(skb)->fh_ox_id);
+}
+
+static inline u16 skb_fc_rxid(const struct sk_buff *skb)
+{
+	return be16_to_cpu(skb_fc_header(skb)->fh_rx_id);
+}
+
+/* FIXME - DMA_BIDIRECTIONAL ? */
+#define skb_cb(skb)	((struct fcoe_rcv_info *)&((skb)->cb[0]))
+#define skb_cmd(skb)	(skb_cb(skb)->fr_cmd)
+#define skb_dir(skb)	(skb_cmd(skb)->sc_data_direction)
+static inline bool skb_fc_is_read(const struct sk_buff *skb)
+{
+	if (skb_fc_is_cmd(skb) && skb_cmd(skb))
+		return skb_dir(skb) == DMA_FROM_DEVICE;
+	return false;
+}
+
+static inline bool skb_fc_is_write(const struct sk_buff *skb)
+{
+	if (skb_fc_is_cmd(skb) && skb_cmd(skb))
+		return skb_dir(skb) == DMA_TO_DEVICE;
+	return false;
+}
+
+/* libfcoe funcs */
+int fcoe_reset(struct Scsi_Host *shost);
+u64 fcoe_wwn_from_mac(unsigned char mac[MAX_ADDR_LEN],
+		      unsigned int scheme, unsigned int port);
+
+u32 fcoe_fc_crc(struct fc_frame *fp);
+int fcoe_xmit(struct fc_lport *, struct fc_frame *);
+int fcoe_rcv(struct sk_buff *, struct net_device *,
+	     struct packet_type *, struct net_device *);
+
+int fcoe_percpu_receive_thread(void *arg);
+void fcoe_clean_pending_queue(struct fc_lport *lp);
+void fcoe_percpu_clean(struct fc_lport *lp);
+void fcoe_watchdog(ulong vp);
+int fcoe_link_ok(struct fc_lport *lp);
+
+struct fc_lport *fcoe_hostlist_lookup(const struct net_device *);
+int fcoe_hostlist_add(const struct fc_lport *);
+int fcoe_hostlist_remove(const struct fc_lport *);
+
+struct Scsi_Host *fcoe_host_alloc(struct scsi_host_template *, int);
+int fcoe_libfc_config(struct fc_lport *, struct libfc_function_template *);
+
+/* fcoe sw hba */
+int __init fcoe_sw_init(void);
+int __exit fcoe_sw_exit(void);
+#endif /* _LIBFCOE_H */
diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h
index 5e75bb7f311c..7360e1916e75 100644
--- a/include/scsi/libiscsi.h
+++ b/include/scsi/libiscsi.h
@@ -30,6 +30,7 @@
 #include <linux/workqueue.h>
 #include <scsi/iscsi_proto.h>
 #include <scsi/iscsi_if.h>
+#include <scsi/scsi_transport_iscsi.h>
 
 struct scsi_transport_template;
 struct scsi_host_template;
@@ -70,12 +71,12 @@ enum {
 /* Connection suspend "bit" */
 #define ISCSI_SUSPEND_BIT		1
 
-#define ISCSI_ITT_MASK			(0x1fff)
+#define ISCSI_ITT_MASK			0x1fff
 #define ISCSI_TOTAL_CMDS_MAX		4096
 /* this must be a power of two greater than ISCSI_MGMT_CMDS_MAX */
 #define ISCSI_TOTAL_CMDS_MIN		16
 #define ISCSI_AGE_SHIFT			28
-#define ISCSI_AGE_MASK			(0xf << ISCSI_AGE_SHIFT)
+#define ISCSI_AGE_MASK			0xf
 
 #define ISCSI_ADDRESS_BUF_LEN		64
 
@@ -93,24 +94,38 @@ enum {
 	ISCSI_TASK_RUNNING,
 };
 
+struct iscsi_r2t_info {
+	__be32			ttt;		/* copied from R2T */
+	__be32			exp_statsn;	/* copied from R2T */
+	uint32_t		data_length;	/* copied from R2T */
+	uint32_t		data_offset;	/* copied from R2T */
+	int			data_count;	/* DATA-Out payload progress */
+	int			datasn;
+	/* LLDs should set/update these values */
+	int			sent;		/* R2T sequence progress */
+};
+
 struct iscsi_task {
 	/*
 	 * Because LLDs allocate their hdr differently, this is a pointer
 	 * and length to that storage. It must be setup at session
 	 * creation time.
 	 */
-	struct iscsi_cmd	*hdr;
+	struct iscsi_hdr	*hdr;
 	unsigned short		hdr_max;
 	unsigned short		hdr_len;	/* accumulated size of hdr used */
+	/* copied values in case we need to send tmfs */
+	itt_t			hdr_itt;
+	__be32			cmdsn;
+	uint8_t			lun[8];
+
 	int			itt;		/* this ITT */
 
-	uint32_t		unsol_datasn;
 	unsigned		imm_count;	/* imm-data (bytes)   */
-	unsigned		unsol_count;	/* unsolicited (bytes)*/
 	/* offset in unsolicited stream (bytes); */
-	unsigned		unsol_offset;
-	unsigned		data_count;	/* remaining Data-Out */
+	struct iscsi_r2t_info	unsol_r2t;
 	char			*data;		/* mgmt payload */
+	unsigned		data_count;
 	struct scsi_cmnd	*sc;		/* associated SCSI cmd*/
 	struct iscsi_conn	*conn;		/* used connection    */
 
@@ -121,6 +136,11 @@ struct iscsi_task {
 	void			*dd_data;	/* driver/transport data */
 };
 
+static inline int iscsi_task_has_unsol_data(struct iscsi_task *task)
+{
+	return task->unsol_r2t.data_length > task->unsol_r2t.sent;
+}
+
 static inline void* iscsi_next_hdr(struct iscsi_task *task)
 {
 	return (void*)task->hdr + task->hdr_len;
@@ -287,6 +307,11 @@ struct iscsi_session {
 	struct iscsi_pool	cmdpool;	/* PDU's pool */
 };
 
+enum {
+	ISCSI_HOST_SETUP,
+	ISCSI_HOST_REMOVED,
+};
+
 struct iscsi_host {
 	char			*initiatorname;
 	/* hw address or netdev iscsi connection is bound to */
@@ -295,6 +320,12 @@ struct iscsi_host {
 	/* local address */
 	int			local_port;
 	char			local_address[ISCSI_ADDRESS_BUF_LEN];
+
+	wait_queue_head_t	session_removal_wq;
+	/* protects sessions and state */
+	spinlock_t		lock;
+	int			num_sessions;
+	int			state;
 };
 
 /*
@@ -302,7 +333,7 @@ struct iscsi_host {
  */
 extern int iscsi_change_queue_depth(struct scsi_device *sdev, int depth);
 extern int iscsi_eh_abort(struct scsi_cmnd *sc);
-extern int iscsi_eh_host_reset(struct scsi_cmnd *sc);
+extern int iscsi_eh_target_reset(struct scsi_cmnd *sc);
 extern int iscsi_eh_device_reset(struct scsi_cmnd *sc);
 extern int iscsi_queuecommand(struct scsi_cmnd *sc,
 			      void (*done)(struct scsi_cmnd *));
@@ -351,6 +382,8 @@ extern void iscsi_conn_stop(struct iscsi_cls_conn *, int);
 extern int iscsi_conn_bind(struct iscsi_cls_session *, struct iscsi_cls_conn *,
 			   int);
 extern void iscsi_conn_failure(struct iscsi_conn *conn, enum iscsi_err err);
+extern void iscsi_session_failure(struct iscsi_cls_session *cls_session,
+				  enum iscsi_err err);
 extern int iscsi_conn_get_param(struct iscsi_cls_conn *cls_conn,
 				enum iscsi_param param, char *buf);
 extern void iscsi_suspend_tx(struct iscsi_conn *conn);
@@ -363,8 +396,9 @@ extern void iscsi_suspend_tx(struct iscsi_conn *conn);
  * pdu and task processing
  */
 extern void iscsi_update_cmdsn(struct iscsi_session *, struct iscsi_nopin *);
-extern void iscsi_prep_unsolicit_data_pdu(struct iscsi_task *,
-					struct iscsi_data *hdr);
+extern void iscsi_prep_data_out_pdu(struct iscsi_task *task,
+				    struct iscsi_r2t_info *r2t,
+				    struct iscsi_data *hdr);
 extern int iscsi_conn_send_pdu(struct iscsi_cls_conn *, struct iscsi_hdr *,
 				char *, uint32_t);
 extern int iscsi_complete_pdu(struct iscsi_conn *, struct iscsi_hdr *,
diff --git a/include/scsi/libiscsi_tcp.h b/include/scsi/libiscsi_tcp.h
new file mode 100644
index 000000000000..83e32f6d7859
--- /dev/null
+++ b/include/scsi/libiscsi_tcp.h
@@ -0,0 +1,132 @@
+/*
+ * iSCSI over TCP/IP Data-Path lib
+ *
+ * Copyright (C) 2008 Mike Christie
+ * Copyright (C) 2008 Red Hat, Inc.  All rights reserved.
+ * maintained by open-iscsi@googlegroups.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * See the file COPYING included with this distribution for more details.
+ */
+
+#ifndef LIBISCSI_TCP_H
+#define LIBISCSI_TCP_H
+
+#include <scsi/libiscsi.h>
+
+struct iscsi_tcp_conn;
+struct iscsi_segment;
+struct sk_buff;
+struct hash_desc;
+
+typedef int iscsi_segment_done_fn_t(struct iscsi_tcp_conn *,
+				    struct iscsi_segment *);
+
+struct iscsi_segment {
+	unsigned char		*data;
+	unsigned int		size;
+	unsigned int		copied;
+	unsigned int		total_size;
+	unsigned int		total_copied;
+
+	struct hash_desc	*hash;
+	unsigned char		recv_digest[ISCSI_DIGEST_SIZE];
+	unsigned char		digest[ISCSI_DIGEST_SIZE];
+	unsigned int		digest_len;
+
+	struct scatterlist	*sg;
+	void			*sg_mapped;
+	unsigned int		sg_offset;
+
+	iscsi_segment_done_fn_t	*done;
+};
+
+/* Socket connection recieve helper */
+struct iscsi_tcp_recv {
+	struct iscsi_hdr	*hdr;
+	struct iscsi_segment	segment;
+
+	/* Allocate buffer for BHS + AHS */
+	uint32_t		hdr_buf[64];
+
+	/* copied and flipped values */
+	int			datalen;
+};
+
+struct iscsi_tcp_conn {
+	struct iscsi_conn	*iscsi_conn;
+	void			*dd_data;
+	int			stop_stage;	/* conn_stop() flag: *
+						 * stop to recover,  *
+						 * stop to terminate */
+	/* control data */
+	struct iscsi_tcp_recv	in;		/* TCP receive context */
+	/* CRC32C (Rx) LLD should set this is they do not offload */
+	struct hash_desc	*rx_hash;
+};
+
+struct iscsi_tcp_task {
+	uint32_t		exp_datasn;	/* expected target's R2TSN/DataSN */
+	int			data_offset;
+	struct iscsi_r2t_info	*r2t;		/* in progress solict R2T */
+	struct iscsi_pool	r2tpool;
+	struct kfifo		*r2tqueue;
+	void			*dd_data;
+};
+
+enum {
+	ISCSI_TCP_SEGMENT_DONE,		/* curr seg has been processed */
+	ISCSI_TCP_SKB_DONE,		/* skb is out of data */
+	ISCSI_TCP_CONN_ERR,		/* iscsi layer has fired a conn err */
+	ISCSI_TCP_SUSPENDED,		/* conn is suspended */
+};
+
+extern void iscsi_tcp_hdr_recv_prep(struct iscsi_tcp_conn *tcp_conn);
+extern int iscsi_tcp_recv_skb(struct iscsi_conn *conn, struct sk_buff *skb,
+			      unsigned int offset, bool offloaded, int *status);
+extern void iscsi_tcp_cleanup_task(struct iscsi_task *task);
+extern int iscsi_tcp_task_init(struct iscsi_task *task);
+extern int iscsi_tcp_task_xmit(struct iscsi_task *task);
+
+/* segment helpers */
+extern int iscsi_tcp_recv_segment_is_hdr(struct iscsi_tcp_conn *tcp_conn);
+extern int iscsi_tcp_segment_done(struct iscsi_tcp_conn *tcp_conn,
+				  struct iscsi_segment *segment, int recv,
+				  unsigned copied);
+extern void iscsi_tcp_segment_unmap(struct iscsi_segment *segment);
+
+extern void iscsi_segment_init_linear(struct iscsi_segment *segment,
+				      void *data, size_t size,
+				      iscsi_segment_done_fn_t *done,
+				      struct hash_desc *hash);
+extern int
+iscsi_segment_seek_sg(struct iscsi_segment *segment,
+		      struct scatterlist *sg_list, unsigned int sg_count,
+		      unsigned int offset, size_t size,
+		      iscsi_segment_done_fn_t *done, struct hash_desc *hash);
+
+/* digest helpers */
+extern void iscsi_tcp_dgst_header(struct hash_desc *hash, const void *hdr,
+				  size_t hdrlen,
+				  unsigned char digest[ISCSI_DIGEST_SIZE]);
+extern struct iscsi_cls_conn *
+iscsi_tcp_conn_setup(struct iscsi_cls_session *cls_session, int dd_data_size,
+		     uint32_t conn_idx);
+extern void iscsi_tcp_conn_teardown(struct iscsi_cls_conn *cls_conn);
+
+/* misc helpers */
+extern int iscsi_tcp_r2tpool_alloc(struct iscsi_session *session);
+extern void iscsi_tcp_r2tpool_free(struct iscsi_session *session);
+
+extern void iscsi_tcp_conn_get_stats(struct iscsi_cls_conn *cls_conn,
+				     struct iscsi_stats *stats);
+#endif /* LIBISCSI_TCP_H */
diff --git a/include/scsi/scsi.h b/include/scsi/scsi.h
index 192f8716aa9e..a109165714d6 100644
--- a/include/scsi/scsi.h
+++ b/include/scsi/scsi.h
@@ -381,6 +381,11 @@ static inline int scsi_is_wlun(unsigned int lun)
 #define DID_IMM_RETRY   0x0c	/* Retry without decrementing retry count  */
 #define DID_REQUEUE	0x0d	/* Requeue command (no immediate retry) also
 				 * without decrementing the retry count	   */
+#define DID_TRANSPORT_DISRUPTED 0x0e /* Transport error disrupted execution
+				      * and the driver blocked the port to
+				      * recover the link. Transport class will
+				      * retry or fail IO */
+#define DID_TRANSPORT_FAILFAST	0x0f /* Transport class fastfailed the io */
 #define DRIVER_OK       0x00	/* Driver status                           */
 
 /*
@@ -426,6 +431,7 @@ static inline int scsi_is_wlun(unsigned int lun)
 #define SCSI_MLQUEUE_HOST_BUSY   0x1055
 #define SCSI_MLQUEUE_DEVICE_BUSY 0x1056
 #define SCSI_MLQUEUE_EH_RETRY    0x1057
+#define SCSI_MLQUEUE_TARGET_BUSY 0x1058
 
 /*
  *  Use these to separate status msg and our bytes
diff --git a/include/scsi/scsi_device.h b/include/scsi/scsi_device.h
index b49e725be039..01a4c58f8bad 100644
--- a/include/scsi/scsi_device.h
+++ b/include/scsi/scsi_device.h
@@ -159,8 +159,6 @@ struct scsi_device {
 	atomic_t iodone_cnt;
 	atomic_t ioerr_cnt;
 
-	int timeout;
-
 	struct device		sdev_gendev,
 				sdev_dev;
 
@@ -238,6 +236,16 @@ struct scsi_target {
 						 * for the device at a time. */
 	unsigned int		pdt_1f_for_no_lun;	/* PDT = 0x1f */
 						/* means no lun present */
+	/* commands actually active on LLD. protected by host lock. */
+	unsigned int		target_busy;
+	/*
+	 * LLDs should set this in the slave_alloc host template callout.
+	 * If set to zero then there is not limit.
+	 */
+	unsigned int		can_queue;
+	unsigned int		target_blocked;
+	unsigned int		max_target_blocked;
+#define SCSI_DEFAULT_TARGET_BLOCKED	3
 
 	char			scsi_level;
 	struct execute_work	ew;
@@ -357,10 +365,11 @@ extern int scsi_is_target_device(const struct device *);
 extern int scsi_execute(struct scsi_device *sdev, const unsigned char *cmd,
 			int data_direction, void *buffer, unsigned bufflen,
 			unsigned char *sense, int timeout, int retries,
-			int flag);
+			int flag, int *resid);
 extern int scsi_execute_req(struct scsi_device *sdev, const unsigned char *cmd,
 			    int data_direction, void *buffer, unsigned bufflen,
-			    struct scsi_sense_hdr *, int timeout, int retries);
+			    struct scsi_sense_hdr *, int timeout, int retries,
+			    int *resid);
 extern int scsi_execute_async(struct scsi_device *sdev,
 			      const unsigned char *cmd, int cmd_len, int data_direction,
 			      void *buffer, unsigned bufflen, int use_sg,
diff --git a/include/scsi/scsi_ioctl.h b/include/scsi/scsi_ioctl.h
index edb9525386da..b9006848b813 100644
--- a/include/scsi/scsi_ioctl.h
+++ b/include/scsi/scsi_ioctl.h
@@ -42,7 +42,7 @@ typedef struct scsi_fctargaddress {
 
 extern int scsi_ioctl(struct scsi_device *, int, void __user *);
 extern int scsi_nonblockable_ioctl(struct scsi_device *sdev, int cmd,
-				   void __user *arg, struct file *filp);
+				   void __user *arg, int ndelay);
 
 #endif /* __KERNEL__ */
 #endif /* _SCSI_IOCTL_H */
diff --git a/include/scsi/scsi_tcq.h b/include/scsi/scsi_tcq.h
index cf4c219c0b5c..17231385cb37 100644
--- a/include/scsi/scsi_tcq.h
+++ b/include/scsi/scsi_tcq.h
@@ -140,8 +140,18 @@ static inline struct scsi_cmnd *scsi_find_tag(struct scsi_device *sdev, int tag)
  */
 static inline int scsi_init_shared_tag_map(struct Scsi_Host *shost, int depth)
 {
-	shost->bqt = blk_init_tags(depth);
-	return shost->bqt ? 0 : -ENOMEM;
+	/*
+	 * If the shared tag map isn't already initialized, do it now.
+	 * This saves callers from having to check ->bqt when setting up
+	 * devices on the shared host (for libata)
+	 */
+	if (!shost->bqt) {
+		shost->bqt = blk_init_tags(depth);
+		if (!shost->bqt)
+			return -ENOMEM;
+	}
+
+	return 0;
 }
 
 /**
diff --git a/include/scsi/scsi_transport_fc.h b/include/scsi/scsi_transport_fc.h
index 21018a4df452..6e04e6fe79c7 100644
--- a/include/scsi/scsi_transport_fc.h
+++ b/include/scsi/scsi_transport_fc.h
@@ -357,6 +357,7 @@ struct fc_rport {	/* aka fc_starget_attrs */
 /* bit field values for struct fc_rport "flags" field: */
 #define FC_RPORT_DEVLOSS_PENDING	0x01
 #define FC_RPORT_SCAN_PENDING		0x02
+#define FC_RPORT_FAST_FAIL_TIMEDOUT	0x04
 
 #define	dev_to_rport(d)				\
 	container_of(d, struct fc_rport, dev)
@@ -678,12 +679,15 @@ fc_remote_port_chkready(struct fc_rport *rport)
 		if (rport->roles & FC_PORT_ROLE_FCP_TARGET)
 			result = 0;
 		else if (rport->flags & FC_RPORT_DEVLOSS_PENDING)
-			result = DID_IMM_RETRY << 16;
+			result = DID_TRANSPORT_DISRUPTED << 16;
 		else
 			result = DID_NO_CONNECT << 16;
 		break;
 	case FC_PORTSTATE_BLOCKED:
-		result = DID_IMM_RETRY << 16;
+		if (rport->flags & FC_RPORT_FAST_FAIL_TIMEDOUT)
+			result = DID_TRANSPORT_FAILFAST << 16;
+		else
+			result = DID_TRANSPORT_DISRUPTED << 16;
 		break;
 	default:
 		result = DID_NO_CONNECT << 16;
diff --git a/include/scsi/scsi_transport_iscsi.h b/include/scsi/scsi_transport_iscsi.h
index 8b6c91df4c7a..b50aabe2861e 100644
--- a/include/scsi/scsi_transport_iscsi.h
+++ b/include/scsi/scsi_transport_iscsi.h
@@ -113,10 +113,18 @@ struct iscsi_transport {
 			 char *data, uint32_t data_size);
 	void (*get_stats) (struct iscsi_cls_conn *conn,
 			   struct iscsi_stats *stats);
+
 	int (*init_task) (struct iscsi_task *task);
 	int (*xmit_task) (struct iscsi_task *task);
-	void (*cleanup_task) (struct iscsi_conn *conn,
-				  struct iscsi_task *task);
+	void (*cleanup_task) (struct iscsi_task *task);
+
+	int (*alloc_pdu) (struct iscsi_task *task, uint8_t opcode);
+	int (*xmit_pdu) (struct iscsi_task *task);
+	int (*init_pdu) (struct iscsi_task *task, unsigned int offset,
+			 unsigned int count);
+	void (*parse_pdu_itt) (struct iscsi_conn *conn, itt_t itt,
+			       int *index, int *age);
+
 	void (*session_recovery_timedout) (struct iscsi_cls_session *session);
 	struct iscsi_endpoint *(*ep_connect) (struct sockaddr *dst_addr,
 					      int non_blocking);
@@ -135,7 +143,8 @@ extern int iscsi_unregister_transport(struct iscsi_transport *tt);
 /*
  * control plane upcalls
  */
-extern void iscsi_conn_error(struct iscsi_cls_conn *conn, enum iscsi_err error);
+extern void iscsi_conn_error_event(struct iscsi_cls_conn *conn,
+				   enum iscsi_err error);
 extern int iscsi_recv_pdu(struct iscsi_cls_conn *conn, struct iscsi_hdr *hdr,
 			  char *data, uint32_t data_size);
 
@@ -207,7 +216,7 @@ extern void iscsi_host_for_each_session(struct Scsi_Host *shost,
 struct iscsi_endpoint {
 	void *dd_data;			/* LLD private data */
 	struct device dev;
-	unsigned int id;
+	uint64_t id;
 };
 
 /*
diff --git a/include/sound/ac97_codec.h b/include/sound/ac97_codec.h
index 9c309daf492b..251fc1cd5002 100644
--- a/include/sound/ac97_codec.h
+++ b/include/sound/ac97_codec.h
@@ -281,10 +281,12 @@
 /* specific - Analog Devices */
 #define AC97_AD_TEST		0x5a	/* test register */
 #define AC97_AD_TEST2		0x5c	/* undocumented test register 2 */
+#define AC97_AD_HPFD_SHIFT	12	/* High Pass Filter Disable */
 #define AC97_AD_CODEC_CFG	0x70	/* codec configuration */
 #define AC97_AD_JACK_SPDIF	0x72	/* Jack Sense & S/PDIF */
 #define AC97_AD_SERIAL_CFG	0x74	/* Serial Configuration */
 #define AC97_AD_MISC		0x76	/* Misc Control Bits */
+#define AC97_AD_VREFD_SHIFT	2	/* V_REFOUT Disable (AD1888) */
 
 /* specific - Cirrus Logic */
 #define AC97_CSR_ACMODE		0x5e	/* AC Mode Register */
diff --git a/include/sound/asound.h b/include/sound/asound.h
index 2c4dc908a54a..1c02ed1d7c4a 100644
--- a/include/sound/asound.h
+++ b/include/sound/asound.h
@@ -575,6 +575,7 @@ enum {
 #define SNDRV_TIMER_GLOBAL_SYSTEM	0
 #define SNDRV_TIMER_GLOBAL_RTC		1
 #define SNDRV_TIMER_GLOBAL_HPET		2
+#define SNDRV_TIMER_GLOBAL_HRTIMER	3
 
 /* info flags */
 #define SNDRV_TIMER_FLG_SLAVE		(1<<0)	/* cannot be controlled */
diff --git a/include/sound/core.h b/include/sound/core.h
index 35424a971b7a..f632484bc743 100644
--- a/include/sound/core.h
+++ b/include/sound/core.h
@@ -353,7 +353,7 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...)
  * snd_printk - printk wrapper
  * @fmt: format string
  *
- * Works like print() but prints the file and the line of the caller
+ * Works like printk() but prints the file and the line of the caller
  * when configured with CONFIG_SND_VERBOSE_PRINTK.
  */
 #define snd_printk(fmt, args...) \
@@ -380,14 +380,40 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...)
 	printk(fmt ,##args)
 #endif
 
+/**
+ * snd_BUG - give a BUG warning message and stack trace
+ *
+ * Calls WARN() if CONFIG_SND_DEBUG is set.
+ * Ignored when CONFIG_SND_DEBUG is not set.
+ */
 #define snd_BUG()		WARN(1, "BUG?\n")
+
+/**
+ * snd_BUG_ON - debugging check macro
+ * @cond: condition to evaluate
+ *
+ * When CONFIG_SND_DEBUG is set, this macro evaluates the given condition,
+ * and call WARN() and returns the value if it's non-zero.
+ * 
+ * When CONFIG_SND_DEBUG is not set, this just returns zero, and the given
+ * condition is ignored.
+ *
+ * NOTE: the argument won't be evaluated at all when CONFIG_SND_DEBUG=n.
+ * Thus, don't put any statement that influences on the code behavior,
+ * such as pre/post increment, to the argument of this macro.
+ * If you want to evaluate and give a warning, use standard WARN_ON().
+ */
 #define snd_BUG_ON(cond)	WARN((cond), "BUG? (%s)\n", __stringify(cond))
 
 #else /* !CONFIG_SND_DEBUG */
 
-#define snd_printd(fmt, args...)	/* nothing */
-#define snd_BUG()			/* nothing */
-#define snd_BUG_ON(cond)	({/*(void)(cond);*/ 0;})  /* always false */
+#define snd_printd(fmt, args...)	do { } while (0)
+#define snd_BUG()			do { } while (0)
+static inline int __snd_bug_on(int cond)
+{
+	return 0;
+}
+#define snd_BUG_ON(cond)	__snd_bug_on(0 && (cond))  /* always false */
 
 #endif /* CONFIG_SND_DEBUG */
 
diff --git a/include/sound/info.h b/include/sound/info.h
index 8ae72e74f898..7c2ee1a21b00 100644
--- a/include/sound/info.h
+++ b/include/sound/info.h
@@ -40,30 +40,34 @@ struct snd_info_buffer {
 struct snd_info_entry;
 
 struct snd_info_entry_text {
-	void (*read) (struct snd_info_entry *entry, struct snd_info_buffer *buffer);
-	void (*write) (struct snd_info_entry *entry, struct snd_info_buffer *buffer);
+	void (*read)(struct snd_info_entry *entry,
+		     struct snd_info_buffer *buffer);
+	void (*write)(struct snd_info_entry *entry,
+		      struct snd_info_buffer *buffer);
 };
 
 struct snd_info_entry_ops {
-	int (*open) (struct snd_info_entry *entry,
-		     unsigned short mode, void **file_private_data);
-	int (*release) (struct snd_info_entry * entry,
-			unsigned short mode, void *file_private_data);
-	long (*read) (struct snd_info_entry *entry, void *file_private_data,
-		      struct file * file, char __user *buf,
+	int (*open)(struct snd_info_entry *entry,
+		    unsigned short mode, void **file_private_data);
+	int (*release)(struct snd_info_entry *entry,
+		       unsigned short mode, void *file_private_data);
+	long (*read)(struct snd_info_entry *entry, void *file_private_data,
+		     struct file *file, char __user *buf,
+		     unsigned long count, unsigned long pos);
+	long (*write)(struct snd_info_entry *entry, void *file_private_data,
+		      struct file *file, const char __user *buf,
 		      unsigned long count, unsigned long pos);
-	long (*write) (struct snd_info_entry *entry, void *file_private_data,
-		       struct file * file, const char __user *buf,
-		       unsigned long count, unsigned long pos);
-	long long (*llseek) (struct snd_info_entry *entry, void *file_private_data,
-			    struct file * file, long long offset, int orig);
-	unsigned int (*poll) (struct snd_info_entry *entry, void *file_private_data,
-			      struct file * file, poll_table * wait);
-	int (*ioctl) (struct snd_info_entry *entry, void *file_private_data,
-		      struct file * file, unsigned int cmd, unsigned long arg);
-	int (*mmap) (struct snd_info_entry *entry, void *file_private_data,
-		     struct inode * inode, struct file * file,
-		     struct vm_area_struct * vma);
+	long long (*llseek)(struct snd_info_entry *entry,
+			    void *file_private_data, struct file *file,
+			    long long offset, int orig);
+	unsigned int(*poll)(struct snd_info_entry *entry,
+			    void *file_private_data, struct file *file,
+			    poll_table *wait);
+	int (*ioctl)(struct snd_info_entry *entry, void *file_private_data,
+		     struct file *file, unsigned int cmd, unsigned long arg);
+	int (*mmap)(struct snd_info_entry *entry, void *file_private_data,
+		    struct inode *inode, struct file *file,
+		    struct vm_area_struct *vma);
 };
 
 struct snd_info_entry {
@@ -106,34 +110,37 @@ void snd_card_info_read_oss(struct snd_info_buffer *buffer);
 static inline void snd_card_info_read_oss(struct snd_info_buffer *buffer) {}
 #endif
 
-int snd_iprintf(struct snd_info_buffer * buffer, char *fmt,...) __attribute__ ((format (printf, 2, 3)));
+int snd_iprintf(struct snd_info_buffer *buffer, char *fmt, ...) \
+				__attribute__ ((format (printf, 2, 3)));
 int snd_info_init(void);
 int snd_info_done(void);
 
-int snd_info_get_line(struct snd_info_buffer * buffer, char *line, int len);
+int snd_info_get_line(struct snd_info_buffer *buffer, char *line, int len);
 char *snd_info_get_str(char *dest, char *src, int len);
-struct snd_info_entry *snd_info_create_module_entry(struct module * module,
+struct snd_info_entry *snd_info_create_module_entry(struct module *module,
 					       const char *name,
-					       struct snd_info_entry * parent);
-struct snd_info_entry *snd_info_create_card_entry(struct snd_card * card,
+					       struct snd_info_entry *parent);
+struct snd_info_entry *snd_info_create_card_entry(struct snd_card *card,
 					     const char *name,
-					     struct snd_info_entry * parent);
-void snd_info_free_entry(struct snd_info_entry * entry);
-int snd_info_store_text(struct snd_info_entry * entry);
-int snd_info_restore_text(struct snd_info_entry * entry);
-
-int snd_info_card_create(struct snd_card * card);
-int snd_info_card_register(struct snd_card * card);
-int snd_info_card_free(struct snd_card * card);
-void snd_info_card_disconnect(struct snd_card * card);
-int snd_info_register(struct snd_info_entry * entry);
+					     struct snd_info_entry *parent);
+void snd_info_free_entry(struct snd_info_entry *entry);
+int snd_info_store_text(struct snd_info_entry *entry);
+int snd_info_restore_text(struct snd_info_entry *entry);
+
+int snd_info_card_create(struct snd_card *card);
+int snd_info_card_register(struct snd_card *card);
+int snd_info_card_free(struct snd_card *card);
+void snd_info_card_disconnect(struct snd_card *card);
+void snd_info_card_id_change(struct snd_card *card);
+int snd_info_register(struct snd_info_entry *entry);
 
 /* for card drivers */
-int snd_card_proc_new(struct snd_card *card, const char *name, struct snd_info_entry **entryp);
+int snd_card_proc_new(struct snd_card *card, const char *name,
+		      struct snd_info_entry **entryp);
 
 static inline void snd_info_set_text_ops(struct snd_info_entry *entry, 
-					 void *private_data,
-					 void (*read)(struct snd_info_entry *, struct snd_info_buffer *))
+	void *private_data,
+	void (*read)(struct snd_info_entry *, struct snd_info_buffer *))
 {
 	entry->private_data = private_data;
 	entry->c.text.read = read;
@@ -146,21 +153,22 @@ int snd_info_check_reserved_words(const char *str);
 #define snd_seq_root NULL
 #define snd_oss_root NULL
 
-static inline int snd_iprintf(struct snd_info_buffer * buffer, char *fmt,...) { return 0; }
+static inline int snd_iprintf(struct snd_info_buffer *buffer, char *fmt, ...) { return 0; }
 static inline int snd_info_init(void) { return 0; }
 static inline int snd_info_done(void) { return 0; }
 
-static inline int snd_info_get_line(struct snd_info_buffer * buffer, char *line, int len) { return 0; }
+static inline int snd_info_get_line(struct snd_info_buffer *buffer, char *line, int len) { return 0; }
 static inline char *snd_info_get_str(char *dest, char *src, int len) { return NULL; }
-static inline struct snd_info_entry *snd_info_create_module_entry(struct module * module, const char *name, struct snd_info_entry * parent) { return NULL; }
-static inline struct snd_info_entry *snd_info_create_card_entry(struct snd_card * card, const char *name, struct snd_info_entry * parent) { return NULL; }
-static inline void snd_info_free_entry(struct snd_info_entry * entry) { ; }
-
-static inline int snd_info_card_create(struct snd_card * card) { return 0; }
-static inline int snd_info_card_register(struct snd_card * card) { return 0; }
-static inline int snd_info_card_free(struct snd_card * card) { return 0; }
-static inline void snd_info_card_disconnect(struct snd_card * card) { }
-static inline int snd_info_register(struct snd_info_entry * entry) { return 0; }
+static inline struct snd_info_entry *snd_info_create_module_entry(struct module *module, const char *name, struct snd_info_entry *parent) { return NULL; }
+static inline struct snd_info_entry *snd_info_create_card_entry(struct snd_card *card, const char *name, struct snd_info_entry *parent) { return NULL; }
+static inline void snd_info_free_entry(struct snd_info_entry *entry) { ; }
+
+static inline int snd_info_card_create(struct snd_card *card) { return 0; }
+static inline int snd_info_card_register(struct snd_card *card) { return 0; }
+static inline int snd_info_card_free(struct snd_card *card) { return 0; }
+static inline void snd_info_card_disconnect(struct snd_card *card) { }
+static inline void snd_info_card_id_change(struct snd_card *card) { }
+static inline int snd_info_register(struct snd_info_entry *entry) { return 0; }
 
 static inline int snd_card_proc_new(struct snd_card *card, const char *name,
 				    struct snd_info_entry **entryp) { return -EINVAL; }
diff --git a/include/sound/jack.h b/include/sound/jack.h
index b1b2b8b59adb..2e0315cdd0d6 100644
--- a/include/sound/jack.h
+++ b/include/sound/jack.h
@@ -35,6 +35,8 @@ enum snd_jack_types {
 	SND_JACK_HEADPHONE	= 0x0001,
 	SND_JACK_MICROPHONE	= 0x0002,
 	SND_JACK_HEADSET	= SND_JACK_HEADPHONE | SND_JACK_MICROPHONE,
+	SND_JACK_LINEOUT	= 0x0004,
+	SND_JACK_MECHANICAL	= 0x0008, /* If detected separately */
 };
 
 struct snd_jack {
diff --git a/include/sound/l3.h b/include/sound/l3.h
new file mode 100644
index 000000000000..423a08f0f1b0
--- /dev/null
+++ b/include/sound/l3.h
@@ -0,0 +1,18 @@
+#ifndef _L3_H_
+#define _L3_H_ 1
+
+struct l3_pins {
+	void (*setdat)(int);
+	void (*setclk)(int);
+	void (*setmode)(int);
+	int data_hold;
+	int data_setup;
+	int clock_high;
+	int mode_hold;
+	int mode;
+	int mode_setup;
+};
+
+int l3_write(struct l3_pins *adap, u8 addr, u8 *data, int len);
+
+#endif
diff --git a/include/sound/s3c24xx_uda134x.h b/include/sound/s3c24xx_uda134x.h
new file mode 100644
index 000000000000..33df4cb909d3
--- /dev/null
+++ b/include/sound/s3c24xx_uda134x.h
@@ -0,0 +1,14 @@
+#ifndef _S3C24XX_UDA134X_H_
+#define _S3C24XX_UDA134X_H_ 1
+
+#include <sound/uda134x.h>
+
+struct s3c24xx_uda134x_platform_data {
+	int l3_clk;
+	int l3_mode;
+	int l3_data;
+	void (*power) (int);
+	int model;
+};
+
+#endif
diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h
new file mode 100644
index 000000000000..24247f763608
--- /dev/null
+++ b/include/sound/soc-dai.h
@@ -0,0 +1,231 @@
+/*
+ * linux/sound/soc-dai.h -- ALSA SoC Layer
+ *
+ * Copyright:	2005-2008 Wolfson Microelectronics. PLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Digital Audio Interface (DAI) API.
+ */
+
+#ifndef __LINUX_SND_SOC_DAI_H
+#define __LINUX_SND_SOC_DAI_H
+
+
+#include <linux/list.h>
+
+struct snd_pcm_substream;
+
+/*
+ * DAI hardware audio formats.
+ *
+ * Describes the physical PCM data formating and clocking. Add new formats
+ * to the end.
+ */
+#define SND_SOC_DAIFMT_I2S		0 /* I2S mode */
+#define SND_SOC_DAIFMT_RIGHT_J		1 /* Right Justified mode */
+#define SND_SOC_DAIFMT_LEFT_J		2 /* Left Justified mode */
+#define SND_SOC_DAIFMT_DSP_A		3 /* L data msb after FRM LRC */
+#define SND_SOC_DAIFMT_DSP_B		4 /* L data msb during FRM LRC */
+#define SND_SOC_DAIFMT_AC97		5 /* AC97 */
+
+/* left and right justified also known as MSB and LSB respectively */
+#define SND_SOC_DAIFMT_MSB		SND_SOC_DAIFMT_LEFT_J
+#define SND_SOC_DAIFMT_LSB		SND_SOC_DAIFMT_RIGHT_J
+
+/*
+ * DAI Clock gating.
+ *
+ * DAI bit clocks can be be gated (disabled) when not the DAI is not
+ * sending or receiving PCM data in a frame. This can be used to save power.
+ */
+#define SND_SOC_DAIFMT_CONT		(0 << 4) /* continuous clock */
+#define SND_SOC_DAIFMT_GATED		(1 << 4) /* clock is gated */
+
+/*
+ * DAI Left/Right Clocks.
+ *
+ * Specifies whether the DAI can support different samples for similtanious
+ * playback and capture. This usually requires a seperate physical frame
+ * clock for playback and capture.
+ */
+#define SND_SOC_DAIFMT_SYNC		(0 << 5) /* Tx FRM = Rx FRM */
+#define SND_SOC_DAIFMT_ASYNC		(1 << 5) /* Tx FRM ~ Rx FRM */
+
+/*
+ * TDM
+ *
+ * Time Division Multiplexing. Allows PCM data to be multplexed with other
+ * data on the DAI.
+ */
+#define SND_SOC_DAIFMT_TDM		(1 << 6)
+
+/*
+ * DAI hardware signal inversions.
+ *
+ * Specifies whether the DAI can also support inverted clocks for the specified
+ * format.
+ */
+#define SND_SOC_DAIFMT_NB_NF		(0 << 8) /* normal bit clock + frame */
+#define SND_SOC_DAIFMT_NB_IF		(1 << 8) /* normal bclk + inv frm */
+#define SND_SOC_DAIFMT_IB_NF		(2 << 8) /* invert bclk + nor frm */
+#define SND_SOC_DAIFMT_IB_IF		(3 << 8) /* invert bclk + frm */
+
+/*
+ * DAI hardware clock masters.
+ *
+ * This is wrt the codec, the inverse is true for the interface
+ * i.e. if the codec is clk and frm master then the interface is
+ * clk and frame slave.
+ */
+#define SND_SOC_DAIFMT_CBM_CFM		(0 << 12) /* codec clk & frm master */
+#define SND_SOC_DAIFMT_CBS_CFM		(1 << 12) /* codec clk slave & frm master */
+#define SND_SOC_DAIFMT_CBM_CFS		(2 << 12) /* codec clk master & frame slave */
+#define SND_SOC_DAIFMT_CBS_CFS		(3 << 12) /* codec clk & frm slave */
+
+#define SND_SOC_DAIFMT_FORMAT_MASK	0x000f
+#define SND_SOC_DAIFMT_CLOCK_MASK	0x00f0
+#define SND_SOC_DAIFMT_INV_MASK		0x0f00
+#define SND_SOC_DAIFMT_MASTER_MASK	0xf000
+
+/*
+ * Master Clock Directions
+ */
+#define SND_SOC_CLOCK_IN		0
+#define SND_SOC_CLOCK_OUT		1
+
+struct snd_soc_dai_ops;
+struct snd_soc_dai;
+struct snd_ac97_bus_ops;
+
+/* Digital Audio Interface registration */
+int snd_soc_register_dai(struct snd_soc_dai *dai);
+void snd_soc_unregister_dai(struct snd_soc_dai *dai);
+int snd_soc_register_dais(struct snd_soc_dai *dai, size_t count);
+void snd_soc_unregister_dais(struct snd_soc_dai *dai, size_t count);
+
+/* Digital Audio Interface clocking API.*/
+int snd_soc_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
+	unsigned int freq, int dir);
+
+int snd_soc_dai_set_clkdiv(struct snd_soc_dai *dai,
+	int div_id, int div);
+
+int snd_soc_dai_set_pll(struct snd_soc_dai *dai,
+	int pll_id, unsigned int freq_in, unsigned int freq_out);
+
+/* Digital Audio interface formatting */
+int snd_soc_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt);
+
+int snd_soc_dai_set_tdm_slot(struct snd_soc_dai *dai,
+	unsigned int mask, int slots);
+
+int snd_soc_dai_set_tristate(struct snd_soc_dai *dai, int tristate);
+
+/* Digital Audio Interface mute */
+int snd_soc_dai_digital_mute(struct snd_soc_dai *dai, int mute);
+
+/*
+ * Digital Audio Interface.
+ *
+ * Describes the Digital Audio Interface in terms of it's ALSA, DAI and AC97
+ * operations an capabilities. Codec and platfom drivers will register a this
+ * structure for every DAI they have.
+ *
+ * This structure covers the clocking, formating and ALSA operations for each
+ * interface a
+ */
+struct snd_soc_dai_ops {
+	/*
+	 * DAI clocking configuration, all optional.
+	 * Called by soc_card drivers, normally in their hw_params.
+	 */
+	int (*set_sysclk)(struct snd_soc_dai *dai,
+		int clk_id, unsigned int freq, int dir);
+	int (*set_pll)(struct snd_soc_dai *dai,
+		int pll_id, unsigned int freq_in, unsigned int freq_out);
+	int (*set_clkdiv)(struct snd_soc_dai *dai, int div_id, int div);
+
+	/*
+	 * DAI format configuration
+	 * Called by soc_card drivers, normally in their hw_params.
+	 */
+	int (*set_fmt)(struct snd_soc_dai *dai, unsigned int fmt);
+	int (*set_tdm_slot)(struct snd_soc_dai *dai,
+		unsigned int mask, int slots);
+	int (*set_tristate)(struct snd_soc_dai *dai, int tristate);
+
+	/*
+	 * DAI digital mute - optional.
+	 * Called by soc-core to minimise any pops.
+	 */
+	int (*digital_mute)(struct snd_soc_dai *dai, int mute);
+
+	/*
+	 * ALSA PCM audio operations - all optional.
+	 * Called by soc-core during audio PCM operations.
+	 */
+	int (*startup)(struct snd_pcm_substream *,
+		struct snd_soc_dai *);
+	void (*shutdown)(struct snd_pcm_substream *,
+		struct snd_soc_dai *);
+	int (*hw_params)(struct snd_pcm_substream *,
+		struct snd_pcm_hw_params *, struct snd_soc_dai *);
+	int (*hw_free)(struct snd_pcm_substream *,
+		struct snd_soc_dai *);
+	int (*prepare)(struct snd_pcm_substream *,
+		struct snd_soc_dai *);
+	int (*trigger)(struct snd_pcm_substream *, int,
+		struct snd_soc_dai *);
+};
+
+/*
+ * Digital Audio Interface runtime data.
+ *
+ * Holds runtime data for a DAI.
+ */
+struct snd_soc_dai {
+	/* DAI description */
+	char *name;
+	unsigned int id;
+	int ac97_control;
+
+	struct device *dev;
+
+	/* DAI callbacks */
+	int (*probe)(struct platform_device *pdev,
+		     struct snd_soc_dai *dai);
+	void (*remove)(struct platform_device *pdev,
+		       struct snd_soc_dai *dai);
+	int (*suspend)(struct snd_soc_dai *dai);
+	int (*resume)(struct snd_soc_dai *dai);
+
+	/* ops */
+	struct snd_soc_dai_ops ops;
+
+	/* DAI capabilities */
+	struct snd_soc_pcm_stream capture;
+	struct snd_soc_pcm_stream playback;
+
+	/* DAI runtime info */
+	struct snd_pcm_runtime *runtime;
+	struct snd_soc_codec *codec;
+	unsigned int active;
+	unsigned char pop_wait:1;
+	void *dma_data;
+
+	/* DAI private data */
+	void *private_data;
+
+	/* parent codec/platform */
+	union {
+		struct snd_soc_codec *codec;
+		struct snd_soc_platform *platform;
+	};
+
+	struct list_head list;
+};
+
+#endif
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
index ca699a3017f3..7ee2f70ca42e 100644
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -221,8 +221,6 @@ int snd_soc_dapm_new_controls(struct snd_soc_codec *codec,
 	int num);
 
 /* dapm path setup */
-int  __deprecated snd_soc_dapm_connect_input(struct snd_soc_codec *codec,
-	const char *sink_name, const char *control_name, const char *src_name);
 int snd_soc_dapm_new_widgets(struct snd_soc_codec *codec);
 void snd_soc_dapm_free(struct snd_soc_device *socdev);
 int snd_soc_dapm_add_routes(struct snd_soc_codec *codec,
diff --git a/include/sound/soc.h b/include/sound/soc.h
index a1e0357a84d7..f86e455d3828 100644
--- a/include/sound/soc.h
+++ b/include/sound/soc.h
@@ -21,14 +21,13 @@
 #include <sound/control.h>
 #include <sound/ac97_codec.h>
 
-#define SND_SOC_VERSION "0.13.2"
-
 /*
  * Convenience kcontrol builders
  */
 #define SOC_SINGLE_VALUE(xreg, xshift, xmax, xinvert) \
 	((unsigned long)&(struct soc_mixer_control) \
-	{.reg = xreg, .shift = xshift, .max = xmax, .invert = xinvert})
+	{.reg = xreg, .shift = xshift, .rshift = xshift, .max = xmax, \
+	.invert = xinvert})
 #define SOC_SINGLE_VALUE_EXT(xreg, xmax, xinvert) \
 	((unsigned long)&(struct soc_mixer_control) \
 	{.reg = xreg, .max = xmax, .invert = xinvert})
@@ -144,105 +143,31 @@ enum snd_soc_bias_level {
 	SND_SOC_BIAS_OFF,
 };
 
-/*
- * Digital Audio Interface (DAI) types
- */
-#define SND_SOC_DAI_AC97	0x1
-#define SND_SOC_DAI_I2S		0x2
-#define SND_SOC_DAI_PCM		0x4
-#define SND_SOC_DAI_AC97_BUS	0x8	/* for custom i.e. non ac97_codec.c */
-
-/*
- * DAI hardware audio formats
- */
-#define SND_SOC_DAIFMT_I2S		0	/* I2S mode */
-#define SND_SOC_DAIFMT_RIGHT_J	1	/* Right justified mode */
-#define SND_SOC_DAIFMT_LEFT_J	2	/* Left Justified mode */
-#define SND_SOC_DAIFMT_DSP_A	3	/* L data msb after FRM or LRC */
-#define SND_SOC_DAIFMT_DSP_B	4	/* L data msb during FRM or LRC */
-#define SND_SOC_DAIFMT_AC97		5	/* AC97 */
-
-#define SND_SOC_DAIFMT_MSB 	SND_SOC_DAIFMT_LEFT_J
-#define SND_SOC_DAIFMT_LSB	SND_SOC_DAIFMT_RIGHT_J
-
-/*
- * DAI Gating
- */
-#define SND_SOC_DAIFMT_CONT			(0 << 4)	/* continuous clock */
-#define SND_SOC_DAIFMT_GATED		(1 << 4)	/* clock is gated when not Tx/Rx */
-
-/*
- * DAI Sync
- * Synchronous LR (Left Right) clocks and Frame signals.
- */
-#define SND_SOC_DAIFMT_SYNC		(0 << 5)	/* Tx FRM = Rx FRM */
-#define SND_SOC_DAIFMT_ASYNC		(1 << 5)	/* Tx FRM ~ Rx FRM */
-
-/*
- * TDM
- */
-#define SND_SOC_DAIFMT_TDM		(1 << 6)
-
-/*
- * DAI hardware signal inversions
- */
-#define SND_SOC_DAIFMT_NB_NF		(0 << 8)	/* normal bclk + frm */
-#define SND_SOC_DAIFMT_NB_IF		(1 << 8)	/* normal bclk + inv frm */
-#define SND_SOC_DAIFMT_IB_NF		(2 << 8)	/* invert bclk + nor frm */
-#define SND_SOC_DAIFMT_IB_IF		(3 << 8)	/* invert bclk + frm */
-
-/*
- * DAI hardware clock masters
- * This is wrt the codec, the inverse is true for the interface
- * i.e. if the codec is clk and frm master then the interface is
- * clk and frame slave.
- */
-#define SND_SOC_DAIFMT_CBM_CFM	(0 << 12) /* codec clk & frm master */
-#define SND_SOC_DAIFMT_CBS_CFM	(1 << 12) /* codec clk slave & frm master */
-#define SND_SOC_DAIFMT_CBM_CFS	(2 << 12) /* codec clk master & frame slave */
-#define SND_SOC_DAIFMT_CBS_CFS	(3 << 12) /* codec clk & frm slave */
-
-#define SND_SOC_DAIFMT_FORMAT_MASK		0x000f
-#define SND_SOC_DAIFMT_CLOCK_MASK		0x00f0
-#define SND_SOC_DAIFMT_INV_MASK			0x0f00
-#define SND_SOC_DAIFMT_MASTER_MASK		0xf000
-
-
-/*
- * Master Clock Directions
- */
-#define SND_SOC_CLOCK_IN	0
-#define SND_SOC_CLOCK_OUT	1
-
-/*
- * AC97 codec ID's bitmask
- */
-#define SND_SOC_DAI_AC97_ID0	(1 << 0)
-#define SND_SOC_DAI_AC97_ID1	(1 << 1)
-#define SND_SOC_DAI_AC97_ID2	(1 << 2)
-#define SND_SOC_DAI_AC97_ID3	(1 << 3)
-
 struct snd_soc_device;
 struct snd_soc_pcm_stream;
 struct snd_soc_ops;
 struct snd_soc_dai_mode;
 struct snd_soc_pcm_runtime;
 struct snd_soc_dai;
+struct snd_soc_platform;
 struct snd_soc_codec;
-struct snd_soc_machine_config;
 struct soc_enum;
 struct snd_soc_ac97_ops;
-struct snd_soc_clock_info;
 
 typedef int (*hw_write_t)(void *,const char* ,int);
 typedef int (*hw_read_t)(void *,char* ,int);
 
 extern struct snd_ac97_bus_ops soc_ac97_ops;
 
+int snd_soc_register_platform(struct snd_soc_platform *platform);
+void snd_soc_unregister_platform(struct snd_soc_platform *platform);
+int snd_soc_register_codec(struct snd_soc_codec *codec);
+void snd_soc_unregister_codec(struct snd_soc_codec *codec);
+
 /* pcm <-> DAI connect */
 void snd_soc_free_pcms(struct snd_soc_device *socdev);
 int snd_soc_new_pcms(struct snd_soc_device *socdev, int idx, const char *xid);
-int snd_soc_register_card(struct snd_soc_device *socdev);
+int snd_soc_init_card(struct snd_soc_device *socdev);
 
 /* set runtime hw params */
 int snd_soc_set_runtime_hwparams(struct snd_pcm_substream *substream,
@@ -262,27 +187,6 @@ int snd_soc_new_ac97_codec(struct snd_soc_codec *codec,
 	struct snd_ac97_bus_ops *ops, int num);
 void snd_soc_free_ac97_codec(struct snd_soc_codec *codec);
 
-/* Digital Audio Interface clocking API.*/
-int snd_soc_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
-	unsigned int freq, int dir);
-
-int snd_soc_dai_set_clkdiv(struct snd_soc_dai *dai,
-	int div_id, int div);
-
-int snd_soc_dai_set_pll(struct snd_soc_dai *dai,
-	int pll_id, unsigned int freq_in, unsigned int freq_out);
-
-/* Digital Audio interface formatting */
-int snd_soc_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt);
-
-int snd_soc_dai_set_tdm_slot(struct snd_soc_dai *dai,
-	unsigned int mask, int slots);
-
-int snd_soc_dai_set_tristate(struct snd_soc_dai *dai, int tristate);
-
-/* Digital Audio Interface mute */
-int snd_soc_dai_digital_mute(struct snd_soc_dai *dai, int mute);
-
 /*
  *Controls
  */
@@ -340,66 +244,14 @@ struct snd_soc_ops {
 	int (*trigger)(struct snd_pcm_substream *, int);
 };
 
-/* ASoC DAI ops */
-struct snd_soc_dai_ops {
-	/* DAI clocking configuration */
-	int (*set_sysclk)(struct snd_soc_dai *dai,
-		int clk_id, unsigned int freq, int dir);
-	int (*set_pll)(struct snd_soc_dai *dai,
-		int pll_id, unsigned int freq_in, unsigned int freq_out);
-	int (*set_clkdiv)(struct snd_soc_dai *dai, int div_id, int div);
-
-	/* DAI format configuration */
-	int (*set_fmt)(struct snd_soc_dai *dai, unsigned int fmt);
-	int (*set_tdm_slot)(struct snd_soc_dai *dai,
-		unsigned int mask, int slots);
-	int (*set_tristate)(struct snd_soc_dai *dai, int tristate);
-
-	/* digital mute */
-	int (*digital_mute)(struct snd_soc_dai *dai, int mute);
-};
-
-/* SoC  DAI (Digital Audio Interface) */
-struct snd_soc_dai {
-	/* DAI description */
-	char *name;
-	unsigned int id;
-	unsigned char type;
-
-	/* DAI callbacks */
-	int (*probe)(struct platform_device *pdev,
-		     struct snd_soc_dai *dai);
-	void (*remove)(struct platform_device *pdev,
-		       struct snd_soc_dai *dai);
-	int (*suspend)(struct platform_device *pdev,
-		struct snd_soc_dai *dai);
-	int (*resume)(struct platform_device *pdev,
-		struct snd_soc_dai *dai);
-
-	/* ops */
-	struct snd_soc_ops ops;
-	struct snd_soc_dai_ops dai_ops;
-
-	/* DAI capabilities */
-	struct snd_soc_pcm_stream capture;
-	struct snd_soc_pcm_stream playback;
-
-	/* DAI runtime info */
-	struct snd_pcm_runtime *runtime;
-	struct snd_soc_codec *codec;
-	unsigned int active;
-	unsigned char pop_wait:1;
-	void *dma_data;
-
-	/* DAI private data */
-	void *private_data;
-};
-
 /* SoC Audio Codec */
 struct snd_soc_codec {
 	char *name;
 	struct module *owner;
 	struct mutex mutex;
+	struct device *dev;
+
+	struct list_head list;
 
 	/* callbacks */
 	int (*set_bias_level)(struct snd_soc_codec *,
@@ -425,6 +277,7 @@ struct snd_soc_codec {
 	short reg_cache_step;
 
 	/* dapm */
+	u32 pop_time;
 	struct list_head dapm_widgets;
 	struct list_head dapm_paths;
 	enum snd_soc_bias_level bias_level;
@@ -434,6 +287,11 @@ struct snd_soc_codec {
 	/* codec DAI's */
 	struct snd_soc_dai *dai;
 	unsigned int num_dai;
+
+#ifdef CONFIG_DEBUG_FS
+	struct dentry *debugfs_reg;
+	struct dentry *debugfs_pop_time;
+#endif
 };
 
 /* codec device */
@@ -447,13 +305,12 @@ struct snd_soc_codec_device {
 /* SoC platform interface */
 struct snd_soc_platform {
 	char *name;
+	struct list_head list;
 
 	int (*probe)(struct platform_device *pdev);
 	int (*remove)(struct platform_device *pdev);
-	int (*suspend)(struct platform_device *pdev,
-		struct snd_soc_dai *dai);
-	int (*resume)(struct platform_device *pdev,
-		struct snd_soc_dai *dai);
+	int (*suspend)(struct snd_soc_dai *dai);
+	int (*resume)(struct snd_soc_dai *dai);
 
 	/* pcm creation and destruction */
 	int (*pcm_new)(struct snd_card *, struct snd_soc_dai *,
@@ -483,9 +340,14 @@ struct snd_soc_dai_link  {
 	struct snd_pcm *pcm;
 };
 
-/* SoC machine */
-struct snd_soc_machine {
+/* SoC card */
+struct snd_soc_card {
 	char *name;
+	struct device *dev;
+
+	struct list_head list;
+
+	int instantiated;
 
 	int (*probe)(struct platform_device *pdev);
 	int (*remove)(struct platform_device *pdev);
@@ -498,23 +360,26 @@ struct snd_soc_machine {
 	int (*resume_post)(struct platform_device *pdev);
 
 	/* callbacks */
-	int (*set_bias_level)(struct snd_soc_machine *,
+	int (*set_bias_level)(struct snd_soc_card *,
 			      enum snd_soc_bias_level level);
 
 	/* CPU <--> Codec DAI links  */
 	struct snd_soc_dai_link *dai_link;
 	int num_links;
+
+	struct snd_soc_device *socdev;
+
+	struct snd_soc_platform *platform;
+	struct delayed_work delayed_work;
+	struct work_struct deferred_resume_work;
 };
 
 /* SoC Device - the audio subsystem */
 struct snd_soc_device {
 	struct device *dev;
-	struct snd_soc_machine *machine;
-	struct snd_soc_platform *platform;
+	struct snd_soc_card *card;
 	struct snd_soc_codec *codec;
 	struct snd_soc_codec_device *codec_dev;
-	struct delayed_work delayed_work;
-	struct work_struct deferred_resume_work;
 	void *codec_data;
 };
 
@@ -541,4 +406,6 @@ struct soc_enum {
 	void *dapm;
 };
 
+#include <sound/soc-dai.h>
+
 #endif
diff --git a/include/sound/uda134x.h b/include/sound/uda134x.h
new file mode 100644
index 000000000000..475ef8bb7dcd
--- /dev/null
+++ b/include/sound/uda134x.h
@@ -0,0 +1,26 @@
+/*
+ * uda134x.h  --  UDA134x ALSA SoC Codec driver
+ *
+ * Copyright 2007 Dension Audio Systems Ltd.
+ * Author: Zoltan Devai
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _UDA134X_H
+#define _UDA134X_H
+
+#include <sound/l3.h>
+
+struct uda134x_platform_data {
+	struct l3_pins l3;
+	void (*power) (int);
+	int model;
+#define UDA134X_UDA1340 1
+#define UDA134X_UDA1341 2
+#define UDA134X_UDA1344 3
+};
+
+#endif /* _UDA134X_H */
diff --git a/include/sound/version.h b/include/sound/version.h
index 4aafeda88634..2b48237e23bf 100644
--- a/include/sound/version.h
+++ b/include/sound/version.h
@@ -1,3 +1,3 @@
 /* include/version.h */
-#define CONFIG_SND_VERSION "1.0.18rc3"
+#define CONFIG_SND_VERSION "1.0.18a"
 #define CONFIG_SND_DATE ""
diff --git a/include/trace/block.h b/include/trace/block.h
new file mode 100644
index 000000000000..25c6a1fd5b77
--- /dev/null
+++ b/include/trace/block.h
@@ -0,0 +1,76 @@
+#ifndef _TRACE_BLOCK_H
+#define _TRACE_BLOCK_H
+
+#include <linux/blkdev.h>
+#include <linux/tracepoint.h>
+
+DECLARE_TRACE(block_rq_abort,
+	TPPROTO(struct request_queue *q, struct request *rq),
+		TPARGS(q, rq));
+
+DECLARE_TRACE(block_rq_insert,
+	TPPROTO(struct request_queue *q, struct request *rq),
+		TPARGS(q, rq));
+
+DECLARE_TRACE(block_rq_issue,
+	TPPROTO(struct request_queue *q, struct request *rq),
+		TPARGS(q, rq));
+
+DECLARE_TRACE(block_rq_requeue,
+	TPPROTO(struct request_queue *q, struct request *rq),
+		TPARGS(q, rq));
+
+DECLARE_TRACE(block_rq_complete,
+	TPPROTO(struct request_queue *q, struct request *rq),
+		TPARGS(q, rq));
+
+DECLARE_TRACE(block_bio_bounce,
+	TPPROTO(struct request_queue *q, struct bio *bio),
+		TPARGS(q, bio));
+
+DECLARE_TRACE(block_bio_complete,
+	TPPROTO(struct request_queue *q, struct bio *bio),
+		TPARGS(q, bio));
+
+DECLARE_TRACE(block_bio_backmerge,
+	TPPROTO(struct request_queue *q, struct bio *bio),
+		TPARGS(q, bio));
+
+DECLARE_TRACE(block_bio_frontmerge,
+	TPPROTO(struct request_queue *q, struct bio *bio),
+		TPARGS(q, bio));
+
+DECLARE_TRACE(block_bio_queue,
+	TPPROTO(struct request_queue *q, struct bio *bio),
+		TPARGS(q, bio));
+
+DECLARE_TRACE(block_getrq,
+	TPPROTO(struct request_queue *q, struct bio *bio, int rw),
+		TPARGS(q, bio, rw));
+
+DECLARE_TRACE(block_sleeprq,
+	TPPROTO(struct request_queue *q, struct bio *bio, int rw),
+		TPARGS(q, bio, rw));
+
+DECLARE_TRACE(block_plug,
+	TPPROTO(struct request_queue *q),
+		TPARGS(q));
+
+DECLARE_TRACE(block_unplug_timer,
+	TPPROTO(struct request_queue *q),
+		TPARGS(q));
+
+DECLARE_TRACE(block_unplug_io,
+	TPPROTO(struct request_queue *q),
+		TPARGS(q));
+
+DECLARE_TRACE(block_split,
+	TPPROTO(struct request_queue *q, struct bio *bio, unsigned int pdu),
+		TPARGS(q, bio, pdu));
+
+DECLARE_TRACE(block_remap,
+	TPPROTO(struct request_queue *q, struct bio *bio, dev_t dev,
+		sector_t from, sector_t to),
+		TPARGS(q, bio, dev, from, to));
+
+#endif
diff --git a/include/trace/boot.h b/include/trace/boot.h
new file mode 100644
index 000000000000..088ea089e31d
--- /dev/null
+++ b/include/trace/boot.h
@@ -0,0 +1,60 @@
+#ifndef _LINUX_TRACE_BOOT_H
+#define _LINUX_TRACE_BOOT_H
+
+#include <linux/module.h>
+#include <linux/kallsyms.h>
+#include <linux/init.h>
+
+/*
+ * Structure which defines the trace of an initcall
+ * while it is called.
+ * You don't have to fill the func field since it is
+ * only used internally by the tracer.
+ */
+struct boot_trace_call {
+	pid_t			caller;
+	char			func[KSYM_SYMBOL_LEN];
+};
+
+/*
+ * Structure which defines the trace of an initcall
+ * while it returns.
+ */
+struct boot_trace_ret {
+	char			func[KSYM_SYMBOL_LEN];
+	int				result;
+	unsigned long long	duration;		/* nsecs */
+};
+
+#ifdef CONFIG_BOOT_TRACER
+/* Append the traces on the ring-buffer */
+extern void trace_boot_call(struct boot_trace_call *bt, initcall_t fn);
+extern void trace_boot_ret(struct boot_trace_ret *bt, initcall_t fn);
+
+/* Tells the tracer that smp_pre_initcall is finished.
+ * So we can start the tracing
+ */
+extern void start_boot_trace(void);
+
+/* Resume the tracing of other necessary events
+ * such as sched switches
+ */
+extern void enable_boot_trace(void);
+
+/* Suspend this tracing. Actually, only sched_switches tracing have
+ * to be suspended. Initcalls doesn't need it.)
+ */
+extern void disable_boot_trace(void);
+#else
+static inline
+void trace_boot_call(struct boot_trace_call *bt, initcall_t fn) { }
+
+static inline
+void trace_boot_ret(struct boot_trace_ret *bt, initcall_t fn) { }
+
+static inline void start_boot_trace(void) { }
+static inline void enable_boot_trace(void) { }
+static inline void disable_boot_trace(void) { }
+#endif /* CONFIG_BOOT_TRACER */
+
+#endif /* __LINUX_TRACE_BOOT_H */
diff --git a/include/trace/sched.h b/include/trace/sched.h
new file mode 100644
index 000000000000..0d81098ee9fc
--- /dev/null
+++ b/include/trace/sched.h
@@ -0,0 +1,56 @@
+#ifndef _TRACE_SCHED_H
+#define _TRACE_SCHED_H
+
+#include <linux/sched.h>
+#include <linux/tracepoint.h>
+
+DECLARE_TRACE(sched_kthread_stop,
+	TPPROTO(struct task_struct *t),
+		TPARGS(t));
+
+DECLARE_TRACE(sched_kthread_stop_ret,
+	TPPROTO(int ret),
+		TPARGS(ret));
+
+DECLARE_TRACE(sched_wait_task,
+	TPPROTO(struct rq *rq, struct task_struct *p),
+		TPARGS(rq, p));
+
+DECLARE_TRACE(sched_wakeup,
+	TPPROTO(struct rq *rq, struct task_struct *p, int success),
+		TPARGS(rq, p, success));
+
+DECLARE_TRACE(sched_wakeup_new,
+	TPPROTO(struct rq *rq, struct task_struct *p, int success),
+		TPARGS(rq, p, success));
+
+DECLARE_TRACE(sched_switch,
+	TPPROTO(struct rq *rq, struct task_struct *prev,
+		struct task_struct *next),
+		TPARGS(rq, prev, next));
+
+DECLARE_TRACE(sched_migrate_task,
+	TPPROTO(struct task_struct *p, int orig_cpu, int dest_cpu),
+		TPARGS(p, orig_cpu, dest_cpu));
+
+DECLARE_TRACE(sched_process_free,
+	TPPROTO(struct task_struct *p),
+		TPARGS(p));
+
+DECLARE_TRACE(sched_process_exit,
+	TPPROTO(struct task_struct *p),
+		TPARGS(p));
+
+DECLARE_TRACE(sched_process_wait,
+	TPPROTO(struct pid *pid),
+		TPARGS(pid));
+
+DECLARE_TRACE(sched_process_fork,
+	TPPROTO(struct task_struct *parent, struct task_struct *child),
+		TPARGS(parent, child));
+
+DECLARE_TRACE(sched_signal_send,
+	TPPROTO(int sig, struct task_struct *p),
+		TPARGS(sig, p));
+
+#endif
diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h
index 6ad87f485992..0c864db1a466 100644
--- a/include/video/atmel_lcdc.h
+++ b/include/video/atmel_lcdc.h
@@ -38,7 +38,7 @@ struct atmel_lcdfb_info {
 	spinlock_t		lock;
 	struct fb_info		*info;
 	void __iomem		*mmio;
-	unsigned long		irq_base;
+	int			irq_base;
 	struct work_struct	task;
 
 	unsigned int		guard_time;
diff --git a/include/video/cyblafb.h b/include/video/cyblafb.h
index 717440575380..d3c1d4e2c8e3 100644
--- a/include/video/cyblafb.h
+++ b/include/video/cyblafb.h
@@ -4,7 +4,7 @@
 #endif
 
 #if CYBLAFB_DEBUG
-#define debug(f,a...)	printk("%s:" f,  __FUNCTION__ , ## a);
+#define debug(f,a...)	printk("%s:" f,  __func__ , ## a);
 #else
 #define debug(f,a...)
 #endif
diff --git a/include/video/neomagic.h b/include/video/neomagic.h
index 38910da0ae59..08b663782956 100644
--- a/include/video/neomagic.h
+++ b/include/video/neomagic.h
@@ -123,7 +123,6 @@ typedef volatile struct {
 
 struct neofb_par {
 	struct vgastate state;
-	struct mutex open_lock;
 	unsigned int ref_count;
 
 	unsigned char MiscOutReg;	/* Misc */
diff --git a/include/video/radeon.h b/include/video/radeon.h
index 099ffa5e5bee..1cd09cc5b169 100644
--- a/include/video/radeon.h
+++ b/include/video/radeon.h
@@ -386,7 +386,7 @@
 #define SC_BOTTOM_RIGHT                        0x16F0  
 #define SRC_SC_BOTTOM_RIGHT                    0x16F4  
 #define RB2D_DSTCACHE_MODE		       0x3428
-#define RB2D_DSTCACHE_CTLSTAT		       0x342C
+#define RB2D_DSTCACHE_CTLSTAT_broken	       0x342C /* do not use */
 #define LVDS_GEN_CNTL			       0x02d0
 #define LVDS_PLL_CNTL			       0x02d4
 #define FP2_GEN_CNTL                           0x0288
@@ -532,6 +532,9 @@
 #define RB2D_DC_FLUSH_ALL			   (RB2D_DC_FLUSH_2D | RB2D_DC_FREE_2D)
 #define RB2D_DC_BUSY				   (1 << 31)
 
+/* DSTCACHE_MODE bits constants */
+#define RB2D_DC_AUTOFLUSH_ENABLE                   (1 << 8)
+#define RB2D_DC_DC_DISABLE_IGNORE_PE               (1 << 17)
 
 /* CRTC_GEN_CNTL bit constants */
 #define CRTC_DBL_SCAN_EN                           0x00000001
diff --git a/include/video/s1d13xxxfb.h b/include/video/s1d13xxxfb.h
index c99d261df8f7..fe41b8407946 100644
--- a/include/video/s1d13xxxfb.h
+++ b/include/video/s1d13xxxfb.h
@@ -14,7 +14,8 @@
 #define	S1D13XXXFB_H
 
 #define S1D_PALETTE_SIZE		256
-#define S1D_CHIP_REV			7	/* expected chip revision number for s1d13806 */
+#define S1D13506_CHIP_REV		4	/* expected chip revision number for s1d13506 */
+#define S1D13806_CHIP_REV		7	/* expected chip revision number for s1d13806 */
 #define S1D_FBID			"S1D13806"
 #define S1D_DEVICENAME			"s1d13806fb"
 
diff --git a/include/video/sh_mobile_lcdc.h b/include/video/sh_mobile_lcdc.h
new file mode 100644
index 000000000000..25144ab22b95
--- /dev/null
+++ b/include/video/sh_mobile_lcdc.h
@@ -0,0 +1,79 @@
+#ifndef __ASM_SH_MOBILE_LCDC_H__
+#define __ASM_SH_MOBILE_LCDC_H__
+
+#include <linux/fb.h>
+
+enum { RGB8,   /* 24bpp, 8:8:8 */
+       RGB9,   /* 18bpp, 9:9 */
+       RGB12A, /* 24bpp, 12:12 */
+       RGB12B, /* 12bpp */
+       RGB16,  /* 16bpp */
+       RGB18,  /* 18bpp */
+       RGB24,  /* 24bpp */
+       SYS8A,  /* 24bpp, 8:8:8 */
+       SYS8B,  /* 18bpp, 8:8:2 */
+       SYS8C,  /* 18bpp, 2:8:8 */
+       SYS8D,  /* 16bpp, 8:8 */
+       SYS9,   /* 18bpp, 9:9 */
+       SYS12,  /* 24bpp, 12:12 */
+       SYS16A, /* 16bpp */
+       SYS16B, /* 18bpp, 16:2 */
+       SYS16C, /* 18bpp, 2:16 */
+       SYS18,  /* 18bpp */
+       SYS24 };/* 24bpp */
+
+enum { LCDC_CHAN_DISABLED = 0,
+       LCDC_CHAN_MAINLCD,
+       LCDC_CHAN_SUBLCD };
+
+enum { LCDC_CLK_BUS, LCDC_CLK_PERIPHERAL, LCDC_CLK_EXTERNAL };
+
+#define LCDC_FLAGS_DWPOL (1 << 0) /* Rising edge dot clock data latch */
+#define LCDC_FLAGS_DIPOL (1 << 1) /* Active low display enable polarity */
+#define LCDC_FLAGS_DAPOL (1 << 2) /* Active low display data polarity */
+#define LCDC_FLAGS_HSCNT (1 << 3) /* Disable HSYNC during VBLANK */
+#define LCDC_FLAGS_DWCNT (1 << 4) /* Disable dotclock during blanking */
+
+struct sh_mobile_lcdc_sys_bus_cfg {
+	unsigned long ldmt2r;
+	unsigned long ldmt3r;
+	unsigned long deferred_io_msec;
+};
+
+struct sh_mobile_lcdc_sys_bus_ops {
+	void (*write_index)(void *handle, unsigned long data);
+	void (*write_data)(void *handle, unsigned long data);
+	unsigned long (*read_data)(void *handle);
+};
+
+struct sh_mobile_lcdc_board_cfg {
+	void *board_data;
+	int (*setup_sys)(void *board_data, void *sys_ops_handle,
+			 struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
+	void (*display_on)(void *board_data);
+	void (*display_off)(void *board_data);
+};
+
+struct sh_mobile_lcdc_lcd_size_cfg { /* width and height of panel in mm */
+	unsigned long width;
+	unsigned long height;
+};
+
+struct sh_mobile_lcdc_chan_cfg {
+	int chan;
+	int bpp;
+	int interface_type; /* selects RGBn or SYSn I/F, see above */
+	int clock_divider;
+	unsigned long flags; /* LCDC_FLAGS_... */
+	struct fb_videomode lcd_cfg;
+	struct sh_mobile_lcdc_lcd_size_cfg lcd_size_cfg;
+	struct sh_mobile_lcdc_board_cfg board_cfg;
+	struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */
+};
+
+struct sh_mobile_lcdc_info {
+	int clock_source;
+	struct sh_mobile_lcdc_chan_cfg ch[2];
+};
+
+#endif /* __ASM_SH_MOBILE_LCDC_H__ */
diff --git a/include/xen/interface/event_channel.h b/include/xen/interface/event_channel.h
index 919b5bdcb2bd..2090881c3650 100644
--- a/include/xen/interface/event_channel.h
+++ b/include/xen/interface/event_channel.h
@@ -9,6 +9,8 @@
 #ifndef __XEN_PUBLIC_EVENT_CHANNEL_H__
 #define __XEN_PUBLIC_EVENT_CHANNEL_H__
 
+#include <xen/interface/xen.h>
+
 typedef uint32_t evtchn_port_t;
 DEFINE_GUEST_HANDLE(evtchn_port_t);