diff options
Diffstat (limited to 'include/linux')
80 files changed, 4463 insertions, 29 deletions
diff --git a/include/linux/backlight.h b/include/linux/backlight.h index af7003548593..ace825e2ca2d 100644 --- a/include/linux/backlight.h +++ b/include/linux/backlight.h @@ -130,6 +130,38 @@ static inline int backlight_update_status(struct backlight_device *bd) return ret; } +/** + * backlight_enable - Enable backlight + * @bd: the backlight device to enable + */ +static inline int backlight_enable(struct backlight_device *bd) +{ + if (!bd) + return 0; + + bd->props.power = FB_BLANK_UNBLANK; + bd->props.fb_blank = FB_BLANK_UNBLANK; + bd->props.state &= ~BL_CORE_FBBLANK; + + return backlight_update_status(bd); +} + +/** + * backlight_disable - Disable backlight + * @bd: the backlight device to disable + */ +static inline int backlight_disable(struct backlight_device *bd) +{ + if (!bd) + return 0; + + bd->props.power = FB_BLANK_POWERDOWN; + bd->props.fb_blank = FB_BLANK_POWERDOWN; + bd->props.state |= BL_CORE_FBBLANK; + + return backlight_update_status(bd); +} + extern struct backlight_device *backlight_device_register(const char *name, struct device *dev, void *devdata, const struct backlight_ops *ops, const struct backlight_properties *props); diff --git a/include/linux/blk_types.h b/include/linux/blk_types.h index 91072b68dc38..86173bafcd39 100644 --- a/include/linux/blk_types.h +++ b/include/linux/blk_types.h @@ -229,11 +229,14 @@ enum req_flag_bits { __REQ_PREFLUSH, /* request for cache flush */ __REQ_RAHEAD, /* read ahead, can fail anytime */ __REQ_BACKGROUND, /* background IO */ + __REQ_NOWAIT, /* Don't wait if request will block */ /* command specific flags for REQ_OP_WRITE_ZEROES: */ __REQ_NOUNMAP, /* do not free blocks when zeroing */ - __REQ_NOWAIT, /* Don't wait if request will block */ + /* for driver use */ + __REQ_DRV, + __REQ_NR_BITS, /* stops here */ }; @@ -250,9 +253,11 @@ enum req_flag_bits { #define REQ_PREFLUSH (1ULL << __REQ_PREFLUSH) #define REQ_RAHEAD (1ULL << __REQ_RAHEAD) #define REQ_BACKGROUND (1ULL << __REQ_BACKGROUND) +#define REQ_NOWAIT (1ULL << __REQ_NOWAIT) #define REQ_NOUNMAP (1ULL << __REQ_NOUNMAP) -#define REQ_NOWAIT (1ULL << __REQ_NOWAIT) + +#define REQ_DRV (1ULL << __REQ_DRV) #define REQ_FAILFAST_MASK \ (REQ_FAILFAST_DEV | REQ_FAILFAST_TRANSPORT | REQ_FAILFAST_DRIVER) diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index 4d4af0e94059..1b671119e2ae 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -284,6 +284,7 @@ struct blk_queue_ctx; typedef void (request_fn_proc) (struct request_queue *q); typedef blk_qc_t (make_request_fn) (struct request_queue *q, struct bio *bio); +typedef bool (poll_q_fn) (struct request_queue *q, blk_qc_t); typedef int (prep_rq_fn) (struct request_queue *, struct request *); typedef void (unprep_rq_fn) (struct request_queue *, struct request *); @@ -426,6 +427,7 @@ struct request_queue { request_fn_proc *request_fn; make_request_fn *make_request_fn; + poll_q_fn *poll_fn; prep_rq_fn *prep_rq_fn; unprep_rq_fn *unprep_rq_fn; softirq_done_fn *softirq_done_fn; @@ -954,6 +956,7 @@ do { \ extern int blk_register_queue(struct gendisk *disk); extern void blk_unregister_queue(struct gendisk *disk); extern blk_qc_t generic_make_request(struct bio *bio); +extern blk_qc_t direct_make_request(struct bio *bio); extern void blk_rq_init(struct request_queue *q, struct request *rq); extern void blk_init_request_from_bio(struct request *req, struct bio *bio); extern void blk_put_request(struct request *); @@ -1008,7 +1011,7 @@ extern void blk_execute_rq_nowait(struct request_queue *, struct gendisk *, int blk_status_to_errno(blk_status_t status); blk_status_t errno_to_blk_status(int errno); -bool blk_mq_poll(struct request_queue *q, blk_qc_t cookie); +bool blk_poll(struct request_queue *q, blk_qc_t cookie); static inline struct request_queue *bdev_get_queue(struct block_device *bdev) { @@ -1127,6 +1130,8 @@ extern struct request *blk_peek_request(struct request_queue *q); extern void blk_start_request(struct request *rq); extern struct request *blk_fetch_request(struct request_queue *q); +void blk_steal_bios(struct bio_list *list, struct request *rq); + /* * Request completion related functions. * diff --git a/include/linux/busfreq-imx.h b/include/linux/busfreq-imx.h new file mode 100644 index 000000000000..17b8991d69bd --- /dev/null +++ b/include/linux/busfreq-imx.h @@ -0,0 +1,77 @@ +/* + * Copyright 2012-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_BUSFREQ_H__ +#define __ASM_ARCH_MXC_BUSFREQ_H__ + +#include <linux/notifier.h> +#include <linux/regulator/consumer.h> + +/* + * This enumerates busfreq low power mode entry and exit. + */ +enum busfreq_event { + LOW_BUSFREQ_ENTER, + LOW_BUSFREQ_EXIT, +}; + +/* + * This enumerates the system bus and ddr frequencies in various modes. + * BUS_FREQ_HIGH - DDR @ 528MHz, AHB @ 132MHz. + * BUS_FREQ_MED - DDR @ 400MHz, AHB @ 132MHz + * BUS_FREQ_AUDIO - DDR @ 50MHz/100MHz, AHB @ 24MHz. + * BUS_FREQ_LOW - DDR @ 24MHz, AHB @ 24MHz. + * BUS_FREQ_ULTRA_LOW - DDR @ 1MHz, AHB - 3MHz. + * + * Drivers need to request/release the bus/ddr frequencies based on + * their performance requirements. Drivers cannot request/release + * BUS_FREQ_ULTRA_LOW mode as this mode is automatically entered from + * either BUS_FREQ_AUDIO or BUS_FREQ_LOW + * modes. + */ +enum bus_freq_mode { + BUS_FREQ_HIGH, + BUS_FREQ_MED, + BUS_FREQ_AUDIO, + BUS_FREQ_LOW, + BUS_FREQ_ULTRA_LOW, +}; + +#if defined(CONFIG_CPU_FREQ) && !defined(CONFIG_ARM64) +extern struct regulator *arm_reg; +extern struct regulator *soc_reg; +void request_bus_freq(enum bus_freq_mode mode); +void release_bus_freq(enum bus_freq_mode mode); +int register_busfreq_notifier(struct notifier_block *nb); +int unregister_busfreq_notifier(struct notifier_block *nb); +int get_bus_freq_mode(void); +#elif defined(CONFIG_ARCH_FSL_IMX8MQ) +void request_bus_freq(enum bus_freq_mode mode); +void release_bus_freq(enum bus_freq_mode mode); +int get_bus_freq_mode(void); +#else +static inline void request_bus_freq(enum bus_freq_mode mode) +{ +} +static inline void release_bus_freq(enum bus_freq_mode mode) +{ +} +static inline int register_busfreq_notifier(struct notifier_block *nb) +{ + return 0; +} +static inline int unregister_busfreq_notifier(struct notifier_block *nb) +{ + return 0; +} +static inline int get_bus_freq_mode(void) +{ + return BUS_FREQ_HIGH; +} +#endif +#endif diff --git a/include/linux/can/platform/flexcan.h b/include/linux/can/platform/flexcan.h new file mode 100644 index 000000000000..fdfe76f16ea7 --- /dev/null +++ b/include/linux/can/platform/flexcan.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This file is released under the GPLv2 + * + */ + +#ifndef __CAN_PLATFORM_FLEXCAN_H +#define __CAN_PLATFORM_FLEXCAN_H + +/** + * struct flexcan_platform_data - flex CAN controller platform data + * @transceiver_enable: - called to power on/off the transceiver + * + */ +struct flexcan_platform_data { + void (*transceiver_switch)(int enable); +}; + +#endif /* __CAN_PLATFORM_FLEXCAN_H */ diff --git a/include/linux/can/rx-offload.h b/include/linux/can/rx-offload.h index 8268811a697e..6448e7dfc170 100644 --- a/include/linux/can/rx-offload.h +++ b/include/linux/can/rx-offload.h @@ -23,7 +23,7 @@ struct can_rx_offload { struct net_device *dev; - unsigned int (*mailbox_read)(struct can_rx_offload *offload, struct can_frame *cf, + unsigned int (*mailbox_read)(struct can_rx_offload *offload, struct canfd_frame *cf, u32 *timestamp, unsigned int mb); struct sk_buff_head skb_queue; @@ -35,6 +35,8 @@ struct can_rx_offload { struct napi_struct napi; bool inc; + + bool is_canfd; }; int can_rx_offload_add_timestamp(struct net_device *dev, struct can_rx_offload *offload); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 3eb3376f1cc8..9ae6613db10c 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -35,6 +35,7 @@ #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ /* parents need enable during gate/ungate, set rate and re-parent */ #define CLK_OPS_PARENT_ENABLE BIT(12) +#define CLK_SET_PARENT_NOCACHE BIT(13) /* do not use the cached clk parent */ struct clk; struct clk_hw; @@ -358,6 +359,7 @@ struct clk_div_table { * @shift: shift to the divider bit field * @width: width of the divider bit field * @table: array of value/divider pairs, last entry should have div = 0 + * @cached_val: cached div hw value used for CLK_DIVIDER_ZERO_GATE * @lock: register lock * * Clock with an adjustable divider affecting its output frequency. Implements @@ -386,6 +388,12 @@ struct clk_div_table { * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED * except when the value read from the register is zero, the divisor is * 2^width of the field. + * CLK_DIVIDER_ZERO_GATE - For dividers when the value read from the register + * is zero, it means the divisor is gated. For this case, the cached_val + * will be used to store the intermediate div for the normal rate + * operation, like set_rate/get_rate/recalc_rate. When the divider is + * ungated, the driver will actually program the hardware to have the + * requested divider value. */ struct clk_divider { struct clk_hw hw; @@ -394,6 +402,7 @@ struct clk_divider { u8 width; u8 flags; const struct clk_div_table *table; + u32 cached_val; spinlock_t *lock; }; @@ -406,6 +415,7 @@ struct clk_divider { #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) #define CLK_DIVIDER_READ_ONLY BIT(5) #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) +#define CLK_DIVIDER_ZERO_GATE BIT(7) extern const struct clk_ops clk_divider_ops; extern const struct clk_ops clk_divider_ro_ops; @@ -555,6 +565,12 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw); * @lock: register lock * * Clock with adjustable fractional divider affecting its output frequency. + * + * Flags: + * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator + * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED + * is set then the numerator and denominator are both the value read + * plus one. */ struct clk_fractional_divider { struct clk_hw hw; @@ -574,6 +590,8 @@ struct clk_fractional_divider { #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) +#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) + extern const struct clk_ops clk_fractional_divider_ops; struct clk *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index cad1eb50d668..b9c6fff3cc9f 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -548,6 +548,18 @@ struct gov_attr_set { int usage_count; }; +#define gov_attr_ro(_name) \ +static struct governor_attr _name = \ +__ATTR(_name, 0444, show_##_name, NULL) + +#define gov_attr_wo(_name) \ +static struct governor_attr _name = \ +__ATTR(_name, 0200, NULL, store_##_name) + +#define gov_attr_rw(_name) \ +static struct governor_attr _name = \ +__ATTR(_name, 0644, show_##_name, store_##_name) + /* sysfs ops for cpufreq governors */ extern const struct sysfs_ops governor_sysfs_ops; diff --git a/include/linux/device_cooling.h b/include/linux/device_cooling.h new file mode 100644 index 000000000000..18d9e3b90ed9 --- /dev/null +++ b/include/linux/device_cooling.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DEVICE_THERMAL_H__ +#define __DEVICE_THERMAL_H__ + +#include <linux/thermal.h> + +#ifdef CONFIG_DEVICE_THERMAL +int register_devfreq_cooling_notifier(struct notifier_block *nb); +int unregister_devfreq_cooling_notifier(struct notifier_block *nb); +struct thermal_cooling_device *devfreq_cooling_register(void); +void devfreq_cooling_unregister(struct thermal_cooling_device *cdev); +#else +static inline +int register_devfreq_cooling_notifier(struct notifier_block *nb) +{ + return 0; +} + +static inline +int unregister_devfreq_cooling_notifier(struct notifier_block *nb) +{ + return 0; +} + +static inline +struct thermal_cooling_device *devfreq_cooling_register(void) +{ + return NULL; +} + +static inline +void devfreq_cooling_unregister(struct thermal_cooling_device *cdev) +{ + return; +} +#endif +#endif /* __DEVICE_THERMAL_H__ */ diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 8319101170fc..8dc150f27dcf 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -345,6 +345,8 @@ enum dma_slave_buswidth { * loops in this area in order to transfer the data. * @dst_port_window_size: same as src_port_window_size but for the destination * port. + * @src_fifo_num: bit 0-7 is the fifo number, bit:8-11 is the fifo offset; + * @dst_fifo_num: same as src_fifo_num * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill * with 'true' if peripheral should be flow controller. Direction will be * selected at Runtime. @@ -374,6 +376,8 @@ struct dma_slave_config { u32 dst_maxburst; u32 src_port_window_size; u32 dst_port_window_size; + u32 src_fifo_num; + u32 dst_fifo_num; bool device_fc; unsigned int slave_id; }; diff --git a/include/linux/elevator.h b/include/linux/elevator.h index ddb7632d73b9..b974133b3b99 100644 --- a/include/linux/elevator.h +++ b/include/linux/elevator.h @@ -197,8 +197,6 @@ extern bool elv_attempt_insert_merge(struct request_queue *, struct request *); extern void elv_requeue_request(struct request_queue *, struct request *); extern struct request *elv_former_request(struct request_queue *, struct request *); extern struct request *elv_latter_request(struct request_queue *, struct request *); -extern int elv_register_queue(struct request_queue *q); -extern void elv_unregister_queue(struct request_queue *q); extern int elv_may_queue(struct request_queue *, unsigned int); extern void elv_completed_request(struct request_queue *, struct request *); extern int elv_set_request(struct request_queue *q, struct request *rq, diff --git a/include/linux/genhd.h b/include/linux/genhd.h index 550fa358893a..4ed6f5256710 100644 --- a/include/linux/genhd.h +++ b/include/linux/genhd.h @@ -141,6 +141,7 @@ struct hd_struct { #define GENHD_FL_NATIVE_CAPACITY 128 #define GENHD_FL_BLOCK_EVENTS_ON_EXCL_WRITE 256 #define GENHD_FL_NO_PART_SCAN 512 +#define GENHD_FL_HIDDEN 1024 enum { DISK_EVENT_MEDIA_CHANGE = 1 << 0, /* media changed */ @@ -235,7 +236,7 @@ static inline bool disk_part_scan_enabled(struct gendisk *disk) static inline dev_t disk_devt(struct gendisk *disk) { - return disk_to_dev(disk)->devt; + return MKDEV(disk->major, disk->first_minor); } static inline dev_t part_devt(struct hd_struct *part) @@ -395,6 +396,11 @@ static inline void add_disk(struct gendisk *disk) { device_add_disk(NULL, disk); } +extern void device_add_disk_no_queue_reg(struct device *parent, struct gendisk *disk); +static inline void add_disk_no_queue_reg(struct gendisk *disk) +{ + device_add_disk_no_queue_reg(NULL, disk); +} extern void del_gendisk(struct gendisk *gp); extern struct gendisk *get_gendisk(dev_t dev, int *partno); diff --git a/include/linux/hantrodec.h b/include/linux/hantrodec.h new file mode 100755 index 000000000000..f423ea82a04e --- /dev/null +++ b/include/linux/hantrodec.h @@ -0,0 +1,29 @@ +/***************************************************************************** +* +* The GPL License (GPL) +* +* Copyright (c) 2015-2017, VeriSilicon Inc. +* Copyright (c) 2011-2014, Google Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software Foundation, +* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +* +*****************************************************************************/ + +#ifndef _HANTRODEC_H_ +#define _HANTRODEC_H_ + +#include <uapi/linux/hantrodec.h> + +#endif /* !_HANTRODEC_H_ */ diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h index d271ff23984f..e367de96076b 100644 --- a/include/linux/hdmi.h +++ b/include/linux/hdmi.h @@ -32,6 +32,7 @@ enum hdmi_infoframe_type { HDMI_INFOFRAME_TYPE_AVI = 0x82, HDMI_INFOFRAME_TYPE_SPD = 0x83, HDMI_INFOFRAME_TYPE_AUDIO = 0x84, + HDMI_INFOFRAME_TYPE_DRM = 0x87, }; #define HDMI_IEEE_OUI 0x000c03 @@ -160,10 +161,28 @@ struct hdmi_avi_infoframe { unsigned short right_bar; }; +struct hdmi_drm_infoframe { + enum hdmi_infoframe_type type; + unsigned char version; + unsigned char length; + uint8_t eotf; + uint8_t metadata_type; + uint16_t display_primaries_x[3]; + uint16_t display_primaries_y[3]; + uint16_t white_point_x; + uint16_t white_point_y; + uint16_t max_mastering_display_luminance; + uint16_t min_mastering_display_luminance; + uint16_t max_fall; + uint16_t max_cll; +}; + int hdmi_avi_infoframe_init(struct hdmi_avi_infoframe *frame); ssize_t hdmi_avi_infoframe_pack(struct hdmi_avi_infoframe *frame, void *buffer, size_t size); +int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame); + enum hdmi_spd_sdi { HDMI_SPD_SDI_UNKNOWN, HDMI_SPD_SDI_DSTB, @@ -328,6 +347,7 @@ union hdmi_infoframe { struct hdmi_spd_infoframe spd; union hdmi_vendor_any_infoframe vendor; struct hdmi_audio_infoframe audio; + struct hdmi_drm_infoframe drm; }; ssize_t diff --git a/include/linux/hx280enc.h b/include/linux/hx280enc.h new file mode 100755 index 000000000000..186a00e3446f --- /dev/null +++ b/include/linux/hx280enc.h @@ -0,0 +1,31 @@ +/***************************************************************************** + * Encoder device driver (kernel module header) + * + * Copyright (C) 2012 Google Finland Oy. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * +-------------------------------------------------------------------------------- +-- +-- Abstract : 6280/7280/8270/8290/H1 Encoder device driver (kernel module) +-- +*****************************************************************************/ + +#ifndef _HX280ENC_H_ +#define _HX280ENC_H_ + +#include <uapi/linux/hx280enc.h> + +#endif /* !_HX280ENC_H_ */ diff --git a/include/linux/imx_gpc.h b/include/linux/imx_gpc.h new file mode 100644 index 000000000000..0eb38224c438 --- /dev/null +++ b/include/linux/imx_gpc.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/* + * @file linux/imx_gpc.h + * + * @brief Global header file for imx GPC + * + * @ingroup GPC + */ +#ifndef __LINUX_IMX_GPC_H__ +#define __LINUX_IMX_GPC_H__ + +#ifdef CONFIG_HAVE_IMX_GPC +int imx_gpc_mf_request_on(unsigned int irq, unsigned int on); +#else +static inline int imx_gpc_mf_request_on(unsigned int irq, unsigned int on) { return 0; } +#endif + +#endif /* __LINUX_IMX_GPC_H__ */ diff --git a/include/linux/imx_rpmsg.h b/include/linux/imx_rpmsg.h new file mode 100644 index 000000000000..cabb6d6e03ce --- /dev/null +++ b/include/linux/imx_rpmsg.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2017 NXP. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/* + * @file linux/imx_rpmsg.h + * + * @brief Global header file for imx RPMSG + * + * @ingroup RPMSG + */ +#ifndef __LINUX_IMX_RPMSG_H__ +#define __LINUX_IMX_RPMSG_H__ + +/* Category define */ +#define IMX_RMPSG_LIFECYCLE 1 +#define IMX_RPMSG_PMIC 2 +#define IMX_RPMSG_AUDIO 3 +#define IMX_RPMSG_KEY 4 +#define IMX_RPMSG_GPIO 5 +#define IMX_RPMSG_RTC 6 +#define IMX_RPMSG_SENSOR 7 +/* rpmsg version */ +#define IMX_RMPSG_MAJOR 1 +#define IMX_RMPSG_MINOR 0 + +struct imx_rpmsg_head { + u8 cate; + u8 major; + u8 minor; + u8 type; + u8 cmd; + u8 reserved[5]; +} __attribute__ ((packed)); + +#endif /* __LINUX_IMX_RPMSG_H__ */ diff --git a/include/linux/imx_sema4.h b/include/linux/imx_sema4.h new file mode 100644 index 000000000000..19850ae7742b --- /dev/null +++ b/include/linux/imx_sema4.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_IMX_SEMA4_H__ +#define __LINUX_IMX_SEMA4_H__ + +#define SEMA4_NUM_DEVICES 1 +#define SEMA4_NUM_GATES 16 + +#define SEMA4_UNLOCK 0x00 +#define SEMA4_A9_LOCK 0x01 +#define SEMA4_GATE_MASK 0x03 + +#define CORE_MUTEX_VALID (('c'<<24)|('m'<<24)|('t'<<24)|'x') + +/* + * The enumerates + */ +enum { + /* sema4 registers offset */ + SEMA4_CP0INE = 0x40, + SEMA4_CP1INE = 0x48, + SEMA4_CP0NTF = 0x80, + SEMA4_CP1NTF = 0x88, +}; + +static const unsigned int idx_sema4[SEMA4_NUM_GATES] = { + 1 << 7, 1 << 6, 1 << 5, 1 << 4, + 1 << 3, 1 << 2, 1 << 1, 1 << 0, + 1 << 15, 1 << 14, 1 << 13, 1 << 12, + 1 << 11, 1 << 10, 1 << 9, 1 << 8, +}; + +struct imx_sema4_mutex { + u32 valid; + u32 gate_num; + unsigned char gate_val; + wait_queue_head_t wait_q; +}; + +struct imx_sema4_mutex_device { + struct device *dev; + u16 cpntf_val; + u16 cpine_val; + void __iomem *ioaddr; /* Mapped address */ + spinlock_t lock; /* Mutex */ + int irq; + + u16 alloced; + struct imx_sema4_mutex *mutex_ptr[SEMA4_NUM_GATES]; +}; + +struct imx_sema4_mutex * + imx_sema4_mutex_create(u32 dev_num, u32 mutex_num); +#ifdef CONFIG_IMX_SEMA4 +int imx_sema4_mutex_destroy(struct imx_sema4_mutex *mutex_ptr); +int imx_sema4_mutex_trylock(struct imx_sema4_mutex *mutex_ptr); +int imx_sema4_mutex_lock(struct imx_sema4_mutex *mutex_ptr); +int imx_sema4_mutex_unlock(struct imx_sema4_mutex *mutex_ptr); +#else +static inline int imx_sema4_mutex_destroy(struct imx_sema4_mutex *mutex_ptr) +{ + return 0; +} +static inline int imx_sema4_mutex_trylock(struct imx_sema4_mutex *mutex_ptr) +{ + return 0; +} +static inline int imx_sema4_mutex_lock(struct imx_sema4_mutex *mutex_ptr) +{ + return 0; +} +static inline int imx_sema4_mutex_unlock(struct imx_sema4_mutex *mutex_ptr) +{ + return 0; +} +#endif +#endif /* __LINUX_IMX_SEMA4_H__ */ diff --git a/include/linux/ipu-v3-pre.h b/include/linux/ipu-v3-pre.h new file mode 100644 index 000000000000..f5a26e5eadbf --- /dev/null +++ b/include/linux/ipu-v3-pre.h @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __LINUX_IPU_V3_PRE_H_ +#define __LINUX_IPU_V3_PRE_H_ + +#define IPU_PRE_MAX_WIDTH 1920 +#define IPU_PRE_MAX_BPP 4 +#define IPU_PRE_SMALL_LINE 9 /* to workaround errata ERR009624*/ + +struct ipu_rect { + int left; + int top; + int width; + int height; +}; + +struct ipu_pre_context { + bool repeat; + bool vflip; + bool handshake_en; + bool hsk_abort_en; + unsigned int hsk_line_num; + bool sdw_update; + unsigned int block_size; + unsigned int interlaced; + unsigned int prefetch_mode; + + unsigned long cur_buf; + unsigned long next_buf; + + unsigned int tile_fmt; + + unsigned int read_burst; + unsigned int prefetch_input_bpp; + unsigned int prefetch_input_pixel_fmt; + unsigned int prefetch_shift_offset; + unsigned int prefetch_shift_width; + bool shift_bypass; + bool field_inverse; + bool tpr_coor_offset_en; + /* the output of prefetch is + * also the input of store + */ + struct ipu_rect prefetch_output_size; + unsigned int prefetch_input_active_width; + unsigned int prefetch_input_width; + unsigned int prefetch_input_height; + unsigned int store_pitch; + int interlace_offset; + + bool store_en; + unsigned int write_burst; + unsigned int store_output_bpp; + + unsigned int sec_buf_off; + unsigned int trd_buf_off; + + /* return for IPU fb caller */ + unsigned long store_addr; +}; + +/* + * In order to workaround the PRE SoC bug recorded by errata ERR009624, + * the software cannot write the PRE_CTRL register when the PRE writes + * the PRE_CTRL register automatically to set the ENABLE bit(bit0) to 1 + * in the PRE repeat mode. + * The software mechanism to set the PRE_CTRL register is different for + * PRE Y resolution higher than 9 lines and lower or equal to 9 lines. + * Use this helper to check the Y resolution. + */ +static inline bool ipu_pre_yres_is_small(unsigned int yres) +{ + return yres <= IPU_PRE_SMALL_LINE; +} + +#ifdef CONFIG_MXC_IPU_V3_PRE +int ipu_pre_alloc(int ipu_id, ipu_channel_t ipu_ch); +void ipu_pre_free(unsigned int *id); +unsigned long ipu_pre_alloc_double_buffer(unsigned int id, unsigned int size); +void ipu_pre_free_double_buffer(unsigned int id); +int ipu_pre_config(int id, struct ipu_pre_context *config); +int ipu_pre_set_ctrl(unsigned int id, struct ipu_pre_context *config); +int ipu_pre_enable(int id); +void ipu_pre_disable(int id); +int ipu_pre_set_fb_buffer(int id, bool resolve, + unsigned long fb_paddr, + unsigned int y_res, + unsigned int x_crop, + unsigned int y_crop, + unsigned int sec_buf_off, + unsigned int trd_buf_off); +int ipu_pre_sdw_update(int id); +#else +int ipu_pre_alloc(int ipu_id, ipu_channel_t channel) +{ + return -ENODEV; +} + +void ipu_pre_free(unsigned int *id) +{ +} + +unsigned long ipu_pre_alloc_double_buffer(unsigned int id, unsigned int size) +{ + return -ENODEV; +} + +void ipu_pre_free_double_buffer(unsigned int id) +{ +} + +int ipu_pre_config(int id, struct ipu_pre_context *config) +{ + return -ENODEV; +} + +int ipu_pre_set_ctrl(unsigned int id, struct ipu_pre_context *config) +{ + return -ENODEV; +} + +int ipu_pre_enable(int id) +{ + return -ENODEV; +} + +void ipu_pre_disable(int id) +{ + return; +} + +int ipu_pre_set_fb_buffer(int id, bool resolve, + unsigned long fb_paddr, + unsigned int y_res, + unsigned int x_crop, + unsigned int y_crop, + unsigned int sec_buf_off, + unsigned int trd_buf_off) +{ + return -ENODEV; +} +int ipu_pre_sdw_update(int id) +{ + return -ENODEV; +} +#endif +#endif /* __LINUX_IPU_V3_PRE_H_ */ diff --git a/include/linux/ipu-v3-prg.h b/include/linux/ipu-v3-prg.h new file mode 100644 index 000000000000..2ab803a6699f --- /dev/null +++ b/include/linux/ipu-v3-prg.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __LINUX_IPU_V3_PRG_H_ +#define __LINUX_IPU_V3_PRG_H_ + +#include <linux/ipu-v3.h> + +#define PRG_SO_INTERLACE 1 +#define PRG_SO_PROGRESSIVE 0 +#define PRG_BLOCK_MODE 1 +#define PRG_SCAN_MODE 0 + +struct ipu_prg_config { + unsigned int id; + unsigned int pre_num; + ipu_channel_t ipu_ch; + unsigned int stride; + unsigned int height; + unsigned int ipu_height; + unsigned int crop_line; + unsigned int so; + unsigned int ilo; + unsigned int block_mode; + bool vflip; + u32 baddr; + u32 offset; +}; + +#ifdef CONFIG_MXC_IPU_V3_PRG +int ipu_prg_config(struct ipu_prg_config *config); +int ipu_prg_disable(unsigned int ipu_id, unsigned int pre_num); +int ipu_prg_wait_buf_ready(unsigned int ipu_id, unsigned int pre_num, + unsigned int hsk_line_num, + int pre_store_out_height); +#else +int ipu_prg_config(struct ipu_prg_config *config) +{ + return -ENODEV; +} + +int ipu_prg_disable(unsigned int ipu_id, unsigned int pre_num) +{ + return -ENODEV; +} + +int ipu_prg_wait_buf_ready(unsigned int ipu_id, unsigned int pre_num, + unsigned int hsk_line_num, + int pre_store_out_height) +{ + return -ENODEV; +} +#endif +#endif /* __LINUX_IPU_V3_PRG_H_ */ diff --git a/include/linux/ipu-v3.h b/include/linux/ipu-v3.h new file mode 100644 index 000000000000..ae09614a2257 --- /dev/null +++ b/include/linux/ipu-v3.h @@ -0,0 +1,770 @@ +/* + * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de> + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef __LINUX_IPU_V3_H_ +#define __LINUX_IPU_V3_H_ + +#include <linux/ipu.h> + +/* IPU Driver channels definitions. */ +/* Note these are different from IDMA channels */ +#define IPU_MAX_CH 32 +#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \ + ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out) +#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24)) +#define IPU_CHAN_ID(ch) (ch >> 24) +#define IPU_CHAN_ALT(ch) (ch & 0x02000000) +#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F) +#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F) +#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F) +#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F)) +#define NO_DMA 0x3F +#define ALT 1 +/*! + * Enumeration of IPU logical channels. An IPU logical channel is defined as a + * combination of an input (memory to IPU), output (IPU to memory), and/or + * secondary input IDMA channels and in some cases an Image Converter task. + * Some channels consist of only an input or output. + */ +typedef enum { + CHAN_NONE = -1, + MEM_ROT_ENC_MEM = _MAKE_CHAN(1, 45, NO_DMA, NO_DMA, 48), + MEM_ROT_VF_MEM = _MAKE_CHAN(2, 46, NO_DMA, NO_DMA, 49), + MEM_ROT_PP_MEM = _MAKE_CHAN(3, 47, NO_DMA, NO_DMA, 50), + + MEM_PRP_ENC_MEM = _MAKE_CHAN(4, 12, 14, 17, 20), + MEM_PRP_VF_MEM = _MAKE_CHAN(5, 12, 14, 17, 21), + MEM_PP_MEM = _MAKE_CHAN(6, 11, 15, 18, 22), + + MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA), + MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA), + MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA), + MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA), + + MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA), + MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA), + MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0), + MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0), + + DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + + CSI_MEM0 = _MAKE_CHAN(15, NO_DMA, NO_DMA, NO_DMA, 0), + CSI_MEM1 = _MAKE_CHAN(16, NO_DMA, NO_DMA, NO_DMA, 1), + CSI_MEM2 = _MAKE_CHAN(17, NO_DMA, NO_DMA, NO_DMA, 2), + CSI_MEM3 = _MAKE_CHAN(18, NO_DMA, NO_DMA, NO_DMA, 3), + + CSI_MEM = CSI_MEM0, + + CSI_PRP_ENC_MEM = _MAKE_CHAN(19, NO_DMA, NO_DMA, NO_DMA, 20), + CSI_PRP_VF_MEM = _MAKE_CHAN(20, NO_DMA, NO_DMA, NO_DMA, 21), + + /* for vdi mem->vdi->ic->mem , add graphics plane and alpha*/ + MEM_VDI_PRP_VF_MEM_P = _MAKE_CHAN(21, 8, 14, 17, 21), + MEM_VDI_PRP_VF_MEM = _MAKE_CHAN(22, 9, 14, 17, 21), + MEM_VDI_PRP_VF_MEM_N = _MAKE_CHAN(23, 10, 14, 17, 21), + + /* for vdi mem->vdi->mem */ + MEM_VDI_MEM_P = _MAKE_CHAN(24, 8, NO_DMA, NO_DMA, 5), + MEM_VDI_MEM = _MAKE_CHAN(25, 9, NO_DMA, NO_DMA, 5), + MEM_VDI_MEM_N = _MAKE_CHAN(26, 10, NO_DMA, NO_DMA, 5), + + /* fake channel for vdoa to link with IPU */ + MEM_VDOA_MEM = _MAKE_CHAN(27, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + + MEM_PP_ADC = CHAN_NONE, + ADC_SYS2 = CHAN_NONE, + +} ipu_channel_t; + +/*! + * Enumeration of types of buffers for a logical channel. + */ +typedef enum { + IPU_OUTPUT_BUFFER = 0, /*!< Buffer for output from IPU */ + IPU_ALPHA_IN_BUFFER = 1, /*!< Buffer for input to IPU */ + IPU_GRAPH_IN_BUFFER = 2, /*!< Buffer for input to IPU */ + IPU_VIDEO_IN_BUFFER = 3, /*!< Buffer for input to IPU */ + IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER, + IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER, +} ipu_buffer_t; + +#define IPU_PANEL_SERIAL 1 +#define IPU_PANEL_PARALLEL 2 + +/*! + * Enumeration of ADC channel operation mode. + */ +typedef enum { + Disable, + WriteTemplateNonSeq, + ReadTemplateNonSeq, + WriteTemplateUnCon, + ReadTemplateUnCon, + WriteDataWithRS, + WriteDataWoRS, + WriteCmd +} mcu_mode_t; + +/*! + * Enumeration of ADC channel addressing mode. + */ +typedef enum { + FullWoBE, + FullWithBE, + XY +} display_addressing_t; + +/*! + * Union of initialization parameters for a logical channel. + */ +typedef union { + struct { + uint32_t csi; + uint32_t mipi_id; + uint32_t mipi_vc; + bool mipi_en; + bool interlaced; + } csi_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + uint32_t csi; + uint32_t mipi_id; + uint32_t mipi_vc; + bool mipi_en; + } csi_prp_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + } mem_prp_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + } mem_rot_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t in_g_pixel_fmt; + uint8_t alpha; + uint32_t key_color; + bool alpha_chan_en; + ipu_motion_sel motion_sel; + enum v4l2_field field_fmt; + uint32_t csi; + uint32_t mipi_id; + uint32_t mipi_vc; + bool mipi_en; + } csi_prp_vf_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + display_port_t disp; + uint32_t out_left; + uint32_t out_top; + } csi_prp_vf_adc; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t in_g_pixel_fmt; + uint8_t alpha; + uint32_t key_color; + bool alpha_chan_en; + ipu_motion_sel motion_sel; + enum v4l2_field field_fmt; + } mem_prp_vf_mem; + struct { + uint32_t temp; + } mem_prp_vf_adc; + struct { + uint32_t temp; + } mem_rot_vf_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t in_g_pixel_fmt; + uint8_t alpha; + uint32_t key_color; + bool alpha_chan_en; + } mem_pp_mem; + struct { + uint32_t temp; + } mem_rot_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + display_port_t disp; + uint32_t out_left; + uint32_t out_top; + } mem_pp_adc; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + } mem_dc_sync; + struct { + uint32_t temp; + } mem_sdc_fg; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + bool alpha_chan_en; + } mem_dp_bg_sync; + struct { + uint32_t temp; + } mem_sdc_bg; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + bool alpha_chan_en; + } mem_dp_fg_sync; + struct { + uint32_t di; + } direct_async; + struct { + display_port_t disp; + mcu_mode_t ch_mode; + uint32_t out_left; + uint32_t out_top; + } adc_sys1; + struct { + display_port_t disp; + mcu_mode_t ch_mode; + uint32_t out_left; + uint32_t out_top; + } adc_sys2; +} ipu_channel_params_t; + +/* + * IPU_IRQF_ONESHOT - Interrupt is not reenabled after the irq handler finished. + */ +#define IPU_IRQF_NONE 0x00000000 +#define IPU_IRQF_ONESHOT 0x00000001 + +/*! + * Enumeration of IPU interrupt sources. + */ +enum ipu_irq_line { + IPU_IRQ_CSI0_OUT_EOF = 0, + IPU_IRQ_CSI1_OUT_EOF = 1, + IPU_IRQ_CSI2_OUT_EOF = 2, + IPU_IRQ_CSI3_OUT_EOF = 3, + IPU_IRQ_VDIC_OUT_EOF = 5, + IPU_IRQ_VDI_P_IN_EOF = 8, + IPU_IRQ_VDI_C_IN_EOF = 9, + IPU_IRQ_VDI_N_IN_EOF = 10, + IPU_IRQ_PP_IN_EOF = 11, + IPU_IRQ_PRP_IN_EOF = 12, + IPU_IRQ_PRP_GRAPH_IN_EOF = 14, + IPU_IRQ_PP_GRAPH_IN_EOF = 15, + IPU_IRQ_PRP_ALPHA_IN_EOF = 17, + IPU_IRQ_PP_ALPHA_IN_EOF = 18, + IPU_IRQ_PRP_ENC_OUT_EOF = 20, + IPU_IRQ_PRP_VF_OUT_EOF = 21, + IPU_IRQ_PP_OUT_EOF = 22, + IPU_IRQ_BG_SYNC_EOF = 23, + IPU_IRQ_BG_ASYNC_EOF = 24, + IPU_IRQ_FG_SYNC_EOF = 27, + IPU_IRQ_DC_SYNC_EOF = 28, + IPU_IRQ_FG_ASYNC_EOF = 29, + IPU_IRQ_FG_ALPHA_SYNC_EOF = 31, + + IPU_IRQ_FG_ALPHA_ASYNC_EOF = 33, + IPU_IRQ_DC_READ_EOF = 40, + IPU_IRQ_DC_ASYNC_EOF = 41, + IPU_IRQ_DC_CMD1_EOF = 42, + IPU_IRQ_DC_CMD2_EOF = 43, + IPU_IRQ_DC_MASK_EOF = 44, + IPU_IRQ_PRP_ENC_ROT_IN_EOF = 45, + IPU_IRQ_PRP_VF_ROT_IN_EOF = 46, + IPU_IRQ_PP_ROT_IN_EOF = 47, + IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 48, + IPU_IRQ_PRP_VF_ROT_OUT_EOF = 49, + IPU_IRQ_PP_ROT_OUT_EOF = 50, + IPU_IRQ_BG_ALPHA_SYNC_EOF = 51, + IPU_IRQ_BG_ALPHA_ASYNC_EOF = 52, + + IPU_IRQ_BG_SYNC_NFACK = 64 + 23, + IPU_IRQ_FG_SYNC_NFACK = 64 + 27, + IPU_IRQ_DC_SYNC_NFACK = 64 + 28, + + IPU_IRQ_DP_SF_START = 448 + 2, + IPU_IRQ_DP_SF_END = 448 + 3, + IPU_IRQ_BG_SF_END = IPU_IRQ_DP_SF_END, + IPU_IRQ_DC_FC_0 = 448 + 8, + IPU_IRQ_DC_FC_1 = 448 + 9, + IPU_IRQ_DC_FC_2 = 448 + 10, + IPU_IRQ_DC_FC_3 = 448 + 11, + IPU_IRQ_DC_FC_4 = 448 + 12, + IPU_IRQ_DC_FC_6 = 448 + 13, + IPU_IRQ_VSYNC_PRE_0 = 448 + 14, + IPU_IRQ_VSYNC_PRE_1 = 448 + 15, + + IPU_IRQ_COUNT +}; + +/*! + * Bitfield of Display Interface signal polarities. + */ +typedef struct { + unsigned datamask_en:1; + unsigned int_clk:1; + unsigned interlaced:1; + unsigned odd_field_first:1; + unsigned clksel_en:1; + unsigned clkidle_en:1; + unsigned data_pol:1; /* true = inverted */ + unsigned clk_pol:1; /* true = rising edge */ + unsigned enable_pol:1; + unsigned Hsync_pol:1; /* true = active high */ + unsigned Vsync_pol:1; +} ipu_di_signal_cfg_t; + +/*! + * Bitfield of CSI signal polarities and modes. + */ + +typedef struct { + unsigned data_width:4; + unsigned clk_mode:3; + unsigned ext_vsync:1; + unsigned Vsync_pol:1; + unsigned Hsync_pol:1; + unsigned pixclk_pol:1; + unsigned data_pol:1; + unsigned sens_clksrc:1; + unsigned pack_tight:1; + unsigned force_eof:1; + unsigned data_en_pol:1; + unsigned data_fmt; + unsigned csi; + unsigned mclk; +} ipu_csi_signal_cfg_t; + +/*! + * Enumeration of CSI data bus widths. + */ +enum { + IPU_CSI_DATA_WIDTH_4 = 0, + IPU_CSI_DATA_WIDTH_8 = 1, + IPU_CSI_DATA_WIDTH_10 = 3, + IPU_CSI_DATA_WIDTH_16 = 9, +}; + +/*! + * Enumeration of CSI clock modes. + */ +enum { + IPU_CSI_CLK_MODE_GATED_CLK, + IPU_CSI_CLK_MODE_NONGATED_CLK, + IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE, + IPU_CSI_CLK_MODE_CCIR656_INTERLACED, + IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR, + IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR, + IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR, + IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR, +}; + +enum { + IPU_CSI_MIPI_DI0, + IPU_CSI_MIPI_DI1, + IPU_CSI_MIPI_DI2, + IPU_CSI_MIPI_DI3, +}; + +typedef enum { + RGB, + YCbCr, + YUV +} ipu_color_space_t; + +/*! + * Enumeration of ADC vertical sync mode. + */ +typedef enum { + VsyncNone, + VsyncInternal, + VsyncCSI, + VsyncExternal +} vsync_t; + +typedef enum { + DAT, + CMD +} cmddata_t; + +/*! + * Enumeration of ADC display update mode. + */ +typedef enum { + IPU_ADC_REFRESH_NONE, + IPU_ADC_AUTO_REFRESH, + IPU_ADC_AUTO_REFRESH_SNOOP, + IPU_ADC_SNOOPING, +} ipu_adc_update_mode_t; + +/*! + * Enumeration of ADC display interface types (serial or parallel). + */ +enum { + IPU_ADC_IFC_MODE_SYS80_TYPE1, + IPU_ADC_IFC_MODE_SYS80_TYPE2, + IPU_ADC_IFC_MODE_SYS68K_TYPE1, + IPU_ADC_IFC_MODE_SYS68K_TYPE2, + IPU_ADC_IFC_MODE_3WIRE_SERIAL, + IPU_ADC_IFC_MODE_4WIRE_SERIAL, + IPU_ADC_IFC_MODE_5WIRE_SERIAL_CLK, + IPU_ADC_IFC_MODE_5WIRE_SERIAL_CS, +}; + +enum { + IPU_ADC_IFC_WIDTH_8, + IPU_ADC_IFC_WIDTH_16, +}; + +/*! + * Enumeration of ADC display interface burst mode. + */ +enum { + IPU_ADC_BURST_WCS, + IPU_ADC_BURST_WBLCK, + IPU_ADC_BURST_NONE, + IPU_ADC_BURST_SERIAL, +}; + +/*! + * Enumeration of ADC display interface RW signal timing modes. + */ +enum { + IPU_ADC_SER_NO_RW, + IPU_ADC_SER_RW_BEFORE_RS, + IPU_ADC_SER_RW_AFTER_RS, +}; + +/*! + * Bitfield of ADC signal polarities and modes. + */ +typedef struct { + unsigned data_pol:1; + unsigned clk_pol:1; + unsigned cs_pol:1; + unsigned rs_pol:1; + unsigned addr_pol:1; + unsigned read_pol:1; + unsigned write_pol:1; + unsigned Vsync_pol:1; + unsigned burst_pol:1; + unsigned burst_mode:2; + unsigned ifc_mode:3; + unsigned ifc_width:5; + unsigned ser_preamble_len:4; + unsigned ser_preamble:8; + unsigned ser_rw_mode:2; +} ipu_adc_sig_cfg_t; + +/*! + * Enumeration of ADC template commands. + */ +enum { + RD_DATA, + RD_ACK, + RD_WAIT, + WR_XADDR, + WR_YADDR, + WR_ADDR, + WR_CMND, + WR_DATA, +}; + +/*! + * Enumeration of ADC template command flow control. + */ +enum { + SINGLE_STEP, + PAUSE, + STOP, +}; + + +/*Define template constants*/ +#define ATM_ADDR_RANGE 0x20 /*offset address of DISP */ +#define TEMPLATE_BUF_SIZE 0x20 /*size of template */ + +/*! + * Define to create ADC template command entry. + */ +#define ipu_adc_template_gen(oc, rs, fc, dat) (((rs) << 29) | ((fc) << 27) | \ + ((oc) << 24) | (dat)) + +typedef struct { + u32 reg; + u32 value; +} ipu_lpmc_reg_t; + +#define IPU_LPMC_REG_READ 0x80000000L + +#define CSI_MCLK_VF 1 +#define CSI_MCLK_ENC 2 +#define CSI_MCLK_RAW 4 +#define CSI_MCLK_I2C 8 + +struct ipu_soc; +/* Common IPU API */ +struct ipu_soc *ipu_get_soc(int id); +int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params); +void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel); +void ipu_disable_hsp_clk(struct ipu_soc *ipu); + +static inline bool ipu_can_rotate_in_place(ipu_rotate_mode_t rot) +{ +#ifdef CONFIG_MXC_IPU_V3D + return (rot < IPU_ROTATE_HORIZ_FLIP); +#else + return (rot < IPU_ROTATE_90_RIGHT); +#endif +} + +int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + ipu_rotate_mode_t rot_mode, + dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, + dma_addr_t phyaddr_2, + uint32_t u_offset, uint32_t v_offset); + +int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum, dma_addr_t phyaddr); + +int32_t ipu_update_channel_offset(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + uint32_t u, uint32_t v, + uint32_t vertical_offset, uint32_t horizontal_offset); + +int32_t ipu_get_channel_offset(uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + uint32_t u, uint32_t v, + uint32_t vertical_offset, uint32_t horizontal_offset, + uint32_t *u_offset, uint32_t *v_offset); + +int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel, + ipu_buffer_t type, uint32_t bufNum); +int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum); + +int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch); +int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch); + +int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel); +int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum); +void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum); +uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type); +int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel); +int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop); +int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch); +uint32_t ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel); + +int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi); +int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi); + +int ipu_lowpwr_display_enable(void); +int ipu_lowpwr_display_disable(void); + +int ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq); +void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq); +void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq); +int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq, + irqreturn_t(*handler) (int, void *), + uint32_t irq_flags, const char *devname, void *dev_id); +void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id); +bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq); +void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3]); +int32_t ipu_set_channel_bandmode(struct ipu_soc *ipu, ipu_channel_t channel, + ipu_buffer_t type, uint32_t band_height); + +/* two stripe calculations */ +struct stripe_param{ + unsigned int input_width; /* width of the input stripe */ + unsigned int output_width; /* width of the output stripe */ + unsigned int input_column; /* the first column on the input stripe */ + unsigned int output_column; /* the first column on the output stripe */ + unsigned int idr; + /* inverse downisizing ratio parameter; expressed as a power of 2 */ + unsigned int irr; + /* inverse resizing ratio parameter; expressed as a multiple of 2^-13 */ +}; +int ipu_calc_stripes_sizes(const unsigned int input_frame_width, + unsigned int output_frame_width, + const unsigned int maximal_stripe_width, + const unsigned long long cirr, + const unsigned int equal_stripes, + u32 input_pixelformat, + u32 output_pixelformat, + struct stripe_param *left, + struct stripe_param *right); + +/* SDC API */ +int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp, + uint32_t pixel_clk, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint16_t h_start_width, uint16_t h_sync_width, + uint16_t h_end_width, uint16_t v_start_width, + uint16_t v_sync_width, uint16_t v_end_width, + uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig); + +void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp); + +int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t x_pos, + int16_t y_pos); +int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t *x_pos, + int16_t *y_pos); +int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, + uint8_t alpha); +int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, + uint32_t colorKey); +int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, + int constk[], int slopek[]); + +int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time, + uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig); +void ipu_reset_disp_panel(struct ipu_soc *ipu); + +/* CMOS Sensor Interface API */ +int32_t ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height, + uint32_t pixel_fmt, ipu_csi_signal_cfg_t sig); + +int32_t ipu_csi_get_sensor_protocol(struct ipu_soc *ipu, uint32_t csi); + +int32_t ipu_csi_enable_mclk(struct ipu_soc *ipu, int src, bool flag, bool wait); + +static inline int32_t ipu_csi_enable_mclk_if(struct ipu_soc *ipu, int src, uint32_t csi, + bool flag, bool wait) +{ + return ipu_csi_enable_mclk(ipu, csi, flag, wait); +} + +int ipu_csi_read_mclk_flag(void); + +void ipu_csi_flash_strobe(bool flag); + +void ipu_csi_get_window_size(struct ipu_soc *ipu, uint32_t *width, uint32_t *height, uint32_t csi); + +void ipu_csi_set_window_size(struct ipu_soc *ipu, uint32_t width, uint32_t height, uint32_t csi); + +void ipu_csi_set_window_pos(struct ipu_soc *ipu, uint32_t left, uint32_t top, uint32_t csi); + +uint32_t bytes_per_pixel(uint32_t fmt); + +bool ipu_ch_param_bad_alpha_pos(uint32_t fmt); +int ipu_ch_param_get_axi_id(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type); +ipu_color_space_t format_to_colorspace(uint32_t fmt); +bool ipu_pixel_format_is_gpu_tile(uint32_t fmt); +bool ipu_pixel_format_is_split_gpu_tile(uint32_t fmt); +bool ipu_pixel_format_is_pre_yuv(uint32_t fmt); +bool ipu_pixel_format_is_multiplanar_yuv(uint32_t fmt); + +struct ipuv3_fb_platform_data { + char disp_dev[32]; + u32 interface_pix_fmt; + char *mode_str; + int default_bpp; + bool int_clk; + + /* reserved mem */ + resource_size_t res_base[2]; + resource_size_t res_size[2]; + + /* + * Late init to avoid display channel being + * re-initialized as we've probably setup the + * channel in bootloader. + */ + bool late_init; + + /* Enable prefetch engine or not? */ + bool prefetch; + + /* Enable the PRE resolve engine or not? */ + bool resolve; +}; + +#endif /* __LINUX_IPU_V3_H_ */ diff --git a/include/linux/ipu.h b/include/linux/ipu.h new file mode 100644 index 000000000000..1090ac65f24b --- /dev/null +++ b/include/linux/ipu.h @@ -0,0 +1,38 @@ +/* + * Copyright 2005-2015 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @defgroup IPU MXC Image Processing Unit (IPU) Driver + */ +/*! + * @file linux/ipu.h + * + * @brief This file contains the IPU driver API declarations. + * + * @ingroup IPU + */ + +#ifndef __LINUX_IPU_H__ +#define __LINUX_IPU_H__ + +#include <linux/interrupt.h> +#include <uapi/linux/ipu.h> + +unsigned int fmt_to_bpp(unsigned int pixelformat); +cs_t colorspaceofpixel(int fmt); +int need_csc(int ifmt, int ofmt); + +int ipu_queue_task(struct ipu_task *task); +int ipu_check_task(struct ipu_task *task); + +#endif diff --git a/include/linux/isl29023.h b/include/linux/isl29023.h new file mode 100644 index 000000000000..5c84566b7b21 --- /dev/null +++ b/include/linux/isl29023.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ISL29023_H__ +#define __ISL29023_H__ + +#include <linux/types.h> + +#define ISL29023_PD_MODE 0x0 +#define ISL29023_ALS_ONCE_MODE 0x1 +#define ISL29023_IR_ONCE_MODE 0x2 +#define ISL29023_ALS_CONT_MODE 0x5 +#define ISL29023_IR_CONT_MODE 0x6 + +#define ISL29023_INT_PERSISTS_1 0x0 +#define ISL29023_INT_PERSISTS_4 0x1 +#define ISL29023_INT_PERSISTS_8 0x2 +#define ISL29023_INT_PERSISTS_16 0x3 + +#define ISL29023_RES_16 0x0 +#define ISL29023_RES_12 0x1 +#define ISL29023_RES_8 0x2 +#define ISL29023_RES_4 0x3 + +#define ISL29023_RANGE_1K 0x0 +#define ISL29023_RANGE_4K 0x1 +#define ISL29023_RANGE_16K 0x2 +#define ISL29023_RANGE_64K 0x3 + +#endif diff --git a/include/linux/mfd/bd71837.h b/include/linux/mfd/bd71837.h new file mode 100644 index 000000000000..3cd51f314b20 --- /dev/null +++ b/include/linux/mfd/bd71837.h @@ -0,0 +1,413 @@ +/** + * @file bd71837.h ROHM BD71837MWV header file + * + * Copyright 2017 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * @author cpham2403@gmail.com + */ + +#ifndef __LINUX_MFD_BD71837_H +#define __LINUX_MFD_BD71837_H + +#include <linux/regmap.h> + +enum { + BD71837_BUCK1 = 0, + BD71837_BUCK2, + BD71837_BUCK3, + BD71837_BUCK4, + BD71837_BUCK5, + BD71837_BUCK6, + BD71837_BUCK7, + BD71837_BUCK8, + // General Purpose + BD71837_LDO1, + BD71837_LDO2, + BD71837_LDO3, + BD71837_LDO4, + BD71837_LDO5, + BD71837_LDO6, + BD71837_LDO7, + BD71837_REGULATOR_CNT, +}; + +#define BD71837_SUPPLY_STATE_ENABLED 0x1 + +#define BD71837_BUCK1_VOLTAGE_NUM 0x40 +#define BD71837_BUCK2_VOLTAGE_NUM 0x40 +#define BD71837_BUCK3_VOLTAGE_NUM 0x40 +#define BD71837_BUCK4_VOLTAGE_NUM 0x40 + +#define BD71837_BUCK5_VOLTAGE_NUM 0x08 +#define BD71837_BUCK6_VOLTAGE_NUM 0x04 +#define BD71837_BUCK7_VOLTAGE_NUM 0x08 +#define BD71837_BUCK8_VOLTAGE_NUM 0x40 + +#define BD71837_LDO1_VOLTAGE_NUM 0x04 +#define BD71837_LDO2_VOLTAGE_NUM 0x02 +#define BD71837_LDO3_VOLTAGE_NUM 0x10 +#define BD71837_LDO4_VOLTAGE_NUM 0x10 +#define BD71837_LDO5_VOLTAGE_NUM 0x10 +#define BD71837_LDO6_VOLTAGE_NUM 0x10 +#define BD71837_LDO7_VOLTAGE_NUM 0x10 + +enum { + BD71837_REG_REV = 0x00, + BD71837_REG_SWRESET = 0x01, + BD71837_REG_I2C_DEV = 0x02, + BD71837_REG_PWRCTRL0 = 0x03, + BD71837_REG_PWRCTRL1 = 0x04, + BD71837_REG_BUCK1_CTRL = 0x05, + BD71837_REG_BUCK2_CTRL = 0x06, + BD71837_REG_BUCK3_CTRL = 0x07, + BD71837_REG_BUCK4_CTRL = 0x08, + BD71837_REG_BUCK5_CTRL = 0x09, + BD71837_REG_BUCK6_CTRL = 0x0A, + BD71837_REG_BUCK7_CTRL = 0x0B, + BD71837_REG_BUCK8_CTRL = 0x0C, + BD71837_REG_BUCK1_VOLT_RUN = 0x0D, + BD71837_REG_BUCK1_VOLT_IDLE = 0x0E, + BD71837_REG_BUCK1_VOLT_SUSP = 0x0F, + BD71837_REG_BUCK2_VOLT_RUN = 0x10, + BD71837_REG_BUCK2_VOLT_IDLE = 0x11, + BD71837_REG_BUCK3_VOLT_RUN = 0x12, + BD71837_REG_BUCK4_VOLT_RUN = 0x13, + BD71837_REG_BUCK5_VOLT = 0x14, + BD71837_REG_BUCK6_VOLT = 0x15, + BD71837_REG_BUCK7_VOLT = 0x16, + BD71837_REG_BUCK8_VOLT = 0x17, + BD71837_REG_LDO1_VOLT = 0x18, + BD71837_REG_LDO2_VOLT = 0x19, + BD71837_REG_LDO3_VOLT = 0x1A, + BD71837_REG_LDO4_VOLT = 0x1B, + BD71837_REG_LDO5_VOLT = 0x1C, + BD71837_REG_LDO6_VOLT = 0x1D, + BD71837_REG_LDO7_VOLT = 0x1E, + BD71837_REG_TRANS_COND0 = 0x1F, + BD71837_REG_TRANS_COND1 = 0x20, + BD71837_REG_VRFAULTEN = 0x21, + BD71837_REG_MVRFLTMASK0 = 0x22, + BD71837_REG_MVRFLTMASK1 = 0x23, + BD71837_REG_MVRFLTMASK2 = 0x24, + BD71837_REG_RCVCFG = 0x25, + BD71837_REG_RCVNUM = 0x26, + BD71837_REG_PWRONCONFIG0 = 0x27, + BD71837_REG_PWRONCONFIG1 = 0x28, + BD71837_REG_RESETSRC = 0x29, + BD71837_REG_MIRQ = 0x2A, + BD71837_REG_IRQ = 0x2B, + BD71837_REG_IN_MON = 0x2C, + BD71837_REG_POW_STATE = 0x2D, + BD71837_REG_OUT32K = 0x2E, + BD71837_REG_REGLOCK = 0x2F, + BD71837_REG_OTPVER = 0xFF, + BD71837_MAX_REGISTER = 0x100, +}; + +/* BD71837_REG_BUCK1_CTRL bits */ +#define BUCK1_RAMPRATE_MASK 0xC0 +#define BUCK1_RAMPRATE_10P00MV 0x0 +#define BUCK1_RAMPRATE_5P00MV 0x1 +#define BUCK1_RAMPRATE_2P50MV 0x2 +#define BUCK1_RAMPRATE_1P25MV 0x3 +#define BUCK1_SEL 0x02 +#define BUCK1_EN 0x01 + +/* BD71837_REG_BUCK2_CTRL bits */ +#define BUCK2_RAMPRATE_MASK 0xC0 +#define BUCK2_RAMPRATE_10P00MV 0x0 +#define BUCK2_RAMPRATE_5P00MV 0x1 +#define BUCK2_RAMPRATE_2P50MV 0x2 +#define BUCK2_RAMPRATE_1P25MV 0x3 +#define BUCK2_SEL 0x02 +#define BUCK2_EN 0x01 + +/* BD71837_REG_BUCK3_CTRL bits */ +#define BUCK3_RAMPRATE_MASK 0xC0 +#define BUCK3_RAMPRATE_10P00MV 0x0 +#define BUCK3_RAMPRATE_5P00MV 0x1 +#define BUCK3_RAMPRATE_2P50MV 0x2 +#define BUCK3_RAMPRATE_1P25MV 0x3 +#define BUCK3_SEL 0x02 +#define BUCK3_EN 0x01 + +/* BD71837_REG_BUCK4_CTRL bits */ +#define BUCK4_RAMPRATE_MASK 0xC0 +#define BUCK4_RAMPRATE_10P00MV 0x0 +#define BUCK4_RAMPRATE_5P00MV 0x1 +#define BUCK4_RAMPRATE_2P50MV 0x2 +#define BUCK4_RAMPRATE_1P25MV 0x3 +#define BUCK4_SEL 0x02 +#define BUCK4_EN 0x01 + +/* BD71837_REG_BUCK5_CTRL bits */ +#define BUCK5_SEL 0x02 +#define BUCK5_EN 0x01 + +/* BD71837_REG_BUCK6_CTRL bits */ +#define BUCK6_SEL 0x02 +#define BUCK6_EN 0x01 + +/* BD71837_REG_BUCK7_CTRL bits */ +#define BUCK7_SEL 0x02 +#define BUCK7_EN 0x01 + +/* BD71837_REG_BUCK8_CTRL bits */ +#define BUCK8_SEL 0x02 +#define BUCK8_EN 0x01 + +/* BD71837_REG_BUCK1_VOLT_RUN bits */ +#define BUCK1_RUN_MASK 0x3F +#define BUCK1_RUN_DEFAULT 0x14 + +/* BD71837_REG_BUCK1_VOLT_SUSP bits */ +#define BUCK1_SUSP_MASK 0x3F +#define BUCK1_SUSP_DEFAULT 0x14 + +/* BD71837_REG_BUCK1_VOLT_IDLE bits */ +#define BUCK1_IDLE_MASK 0x3F +#define BUCK1_IDLE_DEFAULT 0x14 + +/* BD71837_REG_BUCK2_VOLT_RUN bits */ +#define BUCK2_RUN_MASK 0x3F +#define BUCK2_RUN_DEFAULT 0x1E + +/* BD71837_REG_BUCK2_VOLT_IDLE bits */ +#define BUCK2_IDLE_MASK 0x3F +#define BUCK2_IDLE_DEFAULT 0x14 + +/* BD71837_REG_BUCK3_VOLT_RUN bits */ +#define BUCK3_RUN_MASK 0x3F +#define BUCK3_RUN_DEFAULT 0x1E + +/* BD71837_REG_BUCK4_VOLT_RUN bits */ +#define BUCK4_RUN_MASK 0x3F +#define BUCK4_RUN_DEFAULT 0x1E + +/* BD71837_REG_BUCK5_VOLT bits */ +#define BUCK5_MASK 0x07 +#define BUCK5_DEFAULT 0x02 + +/* BD71837_REG_BUCK6_VOLT bits */ +#define BUCK6_MASK 0x03 +#define BUCK6_DEFAULT 0x03 + +/* BD71837_REG_BUCK7_VOLT bits */ +#define BUCK7_MASK 0x07 +#define BUCK7_DEFAULT 0x03 + +/* BD71837_REG_BUCK8_VOLT bits */ +#define BUCK8_MASK 0x3F +#define BUCK8_DEFAULT 0x1E + +/* BD71837_REG_IRQ bits */ +#define IRQ_SWRST 0x40 +#define IRQ_PWRON_S 0x20 +#define IRQ_PWRON_L 0x10 +#define IRQ_PWRON 0x08 +#define IRQ_WDOG 0x04 +#define IRQ_ON_REQ 0x02 +#define IRQ_STBY_REQ 0x01 + +/* BD71837_REG_OUT32K bits */ +#define OUT32K_EN 0x01 + +/* BD71837 interrupt masks */ +enum { + BD71837_INT_MASK = 0x7F, +}; +/* BD71837 interrupt irqs */ +enum { + BD71837_IRQ = 0x0, +}; + +/* BD71837_REG_LDO1_VOLT bits */ +#define LDO1_SEL 0x80 +#define LDO1_EN 0x40 +#define LDO1_MASK 0x03 + +/* BD71837_REG_LDO2_VOLT bits */ +#define LDO2_SEL 0x80 +#define LDO2_EN 0x40 + +/* BD71837_REG_LDO3_VOLT bits */ +#define LDO3_SEL 0x80 +#define LDO3_EN 0x40 +#define LDO3_MASK 0x0F + +/* BD71837_REG_LDO4_VOLT bits */ +#define LDO4_SEL 0x80 +#define LDO4_EN 0x40 +#define LDO4_MASK 0x0F + +/* BD71837_REG_LDO5_VOLT bits */ +#define LDO5_EN 0x40 +#define LDO5_MASK 0x0F + +/* BD71837_REG_LDO6_VOLT bits */ +#define LDO6_EN 0x40 +#define LDO6_MASK 0x0F + +/* BD71837_REG_LDO7_VOLT bits */ +#define LDO7_EN 0x40 +#define LDO7_MASK 0x0F + +/** @brief charge state enumuration */ +enum CHG_STATE { + CHG_STATE_SUSPEND = 0x0, /**< suspend state */ + CHG_STATE_TRICKLE_CHARGE, /**< trickle charge state */ + CHG_STATE_PRE_CHARGE, /**< precharge state */ + CHG_STATE_FAST_CHARGE, /**< fast charge state */ + CHG_STATE_TOP_OFF, /**< top off state */ + CHG_STATE_DONE, /**< charge complete */ +}; + +struct bd71837; + +/** + * @brief Board platform data may be used to initialize regulators. + */ + +struct bd71837_board { + struct regulator_init_data *init_data[BD71837_REGULATOR_CNT]; + /**< regulator initialize data */ + int gpio_intr; /**< gpio connected to bd71837 INTB */ + int irq_base; /**< bd71837 sub irqs base # */ +}; + +/** + * @brief bd71837 sub-driver chip access routines + */ + +struct bd71837 { + struct device *dev; + struct i2c_client *i2c_client; + struct regmap *regmap; + struct mutex io_mutex; + unsigned int id; + + /* IRQ Handling */ + int chip_irq; /**< bd71837 irq to host cpu */ + struct regmap_irq_chip_data *irq_data; + + /* Client devices */ + struct bd71837_pmic *pmic; /**< client device regulator */ + struct bd71837_power *power; /**< client device battery */ + + struct bd71837_board *of_plat_data; + /**< Device node parsed board data */ +}; + +static inline int bd71837_chip_id(struct bd71837 *bd71837) +{ + return bd71837->id; +} + + +/** + * @brief bd71837_reg_read + * read single register's value of bd71837 + * @param bd71837 device to read + * @param reg register address + * @return register value if success + * error number if fail + */ +static inline int bd71837_reg_read(struct bd71837 *bd71837, u8 reg) +{ + int r, val; + + r = regmap_read(bd71837->regmap, reg, &val); + if (r < 0) { + return r; + } + return val; +} + +/** + * @brief bd71837_reg_write + * write single register of bd71837 + * @param bd71837 device to write + * @param reg register address + * @param val value to write + * @retval 0 if success + * @retval negative error number if fail + */ + +static inline int bd71837_reg_write(struct bd71837 *bd71837, u8 reg, + unsigned int val) +{ + return regmap_write(bd71837->regmap, reg, val); +} + +/** + * @brief bd71837_set_bits + * set bits in one register of bd71837 + * @param bd71837 device to read + * @param reg register address + * @param mask mask bits + * @retval 0 if success + * @retval negative error number if fail + */ +static inline int bd71837_set_bits(struct bd71837 *bd71837, u8 reg, u8 mask) +{ + return regmap_update_bits(bd71837->regmap, reg, mask, mask); +} + +/** + * @brief bd71837_clear_bits + * clear bits in one register of bd71837 + * @param bd71837 device to read + * @param reg register address + * @param mask mask bits + * @retval 0 if success + * @retval negative error number if fail + */ + +static inline int bd71837_clear_bits(struct bd71837 *bd71837, u8 reg, + u8 mask) +{ + return regmap_update_bits(bd71837->regmap, reg, mask, 0); +} + +/** + * @brief bd71837_update_bits + * update bits in one register of bd71837 + * @param bd71837 device to read + * @param reg register address + * @param mask mask bits + * @param val value to update + * @retval 0 if success + * @retval negative error number if fail + */ + +static inline int bd71837_update_bits(struct bd71837 *bd71837, u8 reg, + u8 mask, u8 val) +{ + return regmap_update_bits(bd71837->regmap, reg, mask, val); +} + +/** + * @brief bd71837 platform data type + */ +struct bd71837_gpo_plat_data { + u32 drv; ///< gpo output drv + int gpio_base; ///< base gpio number in system +}; + +u8 ext_bd71837_reg_read8(u8 reg); +int ext_bd71837_reg_write8(int reg, u8 val); + +#define BD71837_DBG0 0x0001 +#define BD71837_DBG1 0x0002 +#define BD71837_DBG2 0x0004 +#define BD71837_DBG3 0x0008 + +extern unsigned int bd71837_debug_mask; +#define bd71837_debug(debug, fmt, arg...) do { if (debug & bd71837_debug_mask) printk("BD71837:" fmt, ##arg); } while (0) + +#endif /* __LINUX_MFD_BD71837_H */ diff --git a/include/linux/mfd/max17135.h b/include/linux/mfd/max17135.h new file mode 100644 index 000000000000..e3b8777c8630 --- /dev/null +++ b/include/linux/mfd/max17135.h @@ -0,0 +1,220 @@ +/* + * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef __LINUX_REGULATOR_MAX17135_H_ +#define __LINUX_REGULATOR_MAX17135_H_ + +/* + * PMIC Register Addresses + */ +enum { + REG_MAX17135_EXT_TEMP = 0x0, + REG_MAX17135_CONFIG, + REG_MAX17135_INT_TEMP = 0x4, + REG_MAX17135_STATUS, + REG_MAX17135_PRODUCT_REV, + REG_MAX17135_PRODUCT_ID, + REG_MAX17135_DVR, + REG_MAX17135_ENABLE, + REG_MAX17135_FAULT, /*0x0A*/ + REG_MAX17135_HVINP, + REG_MAX17135_PRGM_CTRL, + REG_MAX17135_TIMING1 = 0x10, /* Timing regs base address is 0x10 */ + REG_MAX17135_TIMING2, + REG_MAX17135_TIMING3, + REG_MAX17135_TIMING4, + REG_MAX17135_TIMING5, + REG_MAX17135_TIMING6, + REG_MAX17135_TIMING7, + REG_MAX17135_TIMING8, +}; +#define MAX17135_REG_NUM 21 +#define MAX17135_MAX_REGISTER 0xFF + +/* + * Bitfield macros that use rely on bitfield width/shift information. + */ +#define BITFMASK(field) (((1U << (field ## _WID)) - 1) << (field ## _LSH)) +#define BITFVAL(field, val) ((val) << (field ## _LSH)) +#define BITFEXT(var, bit) ((var & BITFMASK(bit)) >> (bit ## _LSH)) + +/* + * Shift and width values for each register bitfield + */ +#define EXT_TEMP_LSH 7 +#define EXT_TEMP_WID 9 + +#define THERMAL_SHUTDOWN_LSH 0 +#define THERMAL_SHUTDOWN_WID 1 + +#define INT_TEMP_LSH 7 +#define INT_TEMP_WID 9 + +#define STAT_BUSY_LSH 0 +#define STAT_BUSY_WID 1 +#define STAT_OPEN_LSH 1 +#define STAT_OPEN_WID 1 +#define STAT_SHRT_LSH 2 +#define STAT_SHRT_WID 1 + +#define PROD_REV_LSH 0 +#define PROD_REV_WID 8 + +#define PROD_ID_LSH 0 +#define PROD_ID_WID 8 + +#define DVR_LSH 0 +#define DVR_WID 8 + +#define ENABLE_LSH 0 +#define ENABLE_WID 1 +#define VCOM_ENABLE_LSH 1 +#define VCOM_ENABLE_WID 1 + +#define FAULT_FBPG_LSH 0 +#define FAULT_FBPG_WID 1 +#define FAULT_HVINP_LSH 1 +#define FAULT_HVINP_WID 1 +#define FAULT_HVINN_LSH 2 +#define FAULT_HVINN_WID 1 +#define FAULT_FBNG_LSH 3 +#define FAULT_FBNG_WID 1 +#define FAULT_HVINPSC_LSH 4 +#define FAULT_HVINPSC_WID 1 +#define FAULT_HVINNSC_LSH 5 +#define FAULT_HVINNSC_WID 1 +#define FAULT_OT_LSH 6 +#define FAULT_OT_WID 1 +#define FAULT_POK_LSH 7 +#define FAULT_POK_WID 1 + +#define HVINP_LSH 0 +#define HVINP_WID 4 + +#define CTRL_DVR_LSH 0 +#define CTRL_DVR_WID 1 +#define CTRL_TIMING_LSH 1 +#define CTRL_TIMING_WID 1 + +#define TIMING1_LSH 0 +#define TIMING1_WID 8 +#define TIMING2_LSH 0 +#define TIMING2_WID 8 +#define TIMING3_LSH 0 +#define TIMING3_WID 8 +#define TIMING4_LSH 0 +#define TIMING4_WID 8 +#define TIMING5_LSH 0 +#define TIMING5_WID 8 +#define TIMING6_LSH 0 +#define TIMING6_WID 8 +#define TIMING7_LSH 0 +#define TIMING7_WID 8 +#define TIMING8_LSH 0 +#define TIMING8_WID 8 + +struct max17135 { + /* chip revision */ + int rev; + + struct device *dev; + struct max17135_platform_data *pdata; + + /* Platform connection */ + struct i2c_client *i2c_client; + + /* Timings */ + unsigned int gvee_pwrup; + unsigned int vneg_pwrup; + unsigned int vpos_pwrup; + unsigned int gvdd_pwrup; + unsigned int gvdd_pwrdn; + unsigned int vpos_pwrdn; + unsigned int vneg_pwrdn; + unsigned int gvee_pwrdn; + + /* GPIOs */ + int gpio_pmic_pwrgood; + int gpio_pmic_vcom_ctrl; + int gpio_pmic_wakeup; + int gpio_pmic_v3p3; + int gpio_pmic_intr; + + /* MAX17135 part variables */ + int pass_num; + int vcom_uV; + + /* One-time VCOM setup marker */ + bool vcom_setup; + + /* powerup/powerdown wait time */ + int max_wait; +}; + +enum { + /* In alphabetical order */ + MAX17135_DISPLAY, /* virtual master enable */ + MAX17135_GVDD, + MAX17135_GVEE, + MAX17135_HVINN, + MAX17135_HVINP, + MAX17135_VCOM, + MAX17135_VNEG, + MAX17135_VPOS, + MAX17135_V3P3, + MAX17135_NUM_REGULATORS, +}; + +/* + * Declarations + */ +struct regulator_init_data; +struct max17135_regulator_data; + +struct max17135_platform_data { + unsigned int gvee_pwrup; + unsigned int vneg_pwrup; + unsigned int vpos_pwrup; + unsigned int gvdd_pwrup; + unsigned int gvdd_pwrdn; + unsigned int vpos_pwrdn; + unsigned int vneg_pwrdn; + unsigned int gvee_pwrdn; + int gpio_pmic_pwrgood; + int gpio_pmic_vcom_ctrl; + int gpio_pmic_wakeup; + int gpio_pmic_v3p3; + int gpio_pmic_intr; + int pass_num; + int vcom_uV; + + /* PMIC */ + struct max17135_regulator_data *regulators; + int num_regulators; +}; + +struct max17135_regulator_data { + int id; + struct regulator_init_data *initdata; + struct device_node *reg_node; +}; + +int max17135_reg_read(int reg_num, unsigned int *reg_val); +int max17135_reg_write(int reg_num, const unsigned int reg_val); + +#endif diff --git a/include/linux/mfd/mxc-hdmi-core.h b/include/linux/mfd/mxc-hdmi-core.h new file mode 100644 index 000000000000..b2696b951f43 --- /dev/null +++ b/include/linux/mfd/mxc-hdmi-core.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __LINUX_MXC_HDMI_CORE_H_ +#define __LINUX_MXC_HDMI_CORE_H_ + +#include <video/mxc_edid.h> + +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> + +#define IRQ_DISABLE_SUCCEED 0 +#define IRQ_DISABLE_FAIL 1 + +bool hdmi_check_overflow(void); + +u8 hdmi_readb(unsigned int reg); +void hdmi_writeb(u8 value, unsigned int reg); +void hdmi_mask_writeb(u8 data, unsigned int addr, u8 shift, u8 mask); +unsigned int hdmi_read4(unsigned int reg); +void hdmi_write4(unsigned int value, unsigned int reg); + +void hdmi_irq_init(void); +void hdmi_irq_enable(int irq); +unsigned int hdmi_irq_disable(int irq); + +void hdmi_set_sample_rate(unsigned int rate); +void hdmi_set_dma_mode(unsigned int dma_running); +void hdmi_init_clk_regenerator(void); +void hdmi_clk_regenerator_update_pixel_clock(u32 pixclock); + +void hdmi_set_edid_cfg(struct mxc_edid_cfg *cfg); +void hdmi_get_edid_cfg(struct mxc_edid_cfg *cfg); + +extern int mxc_hdmi_ipu_id; +extern int mxc_hdmi_disp_id; + +void hdmi_set_registered(int registered); +int hdmi_get_registered(void); +int mxc_hdmi_abort_stream(void); +int mxc_hdmi_register_audio(struct snd_pcm_substream *substream); +void mxc_hdmi_unregister_audio(struct snd_pcm_substream *substream); +unsigned int hdmi_set_cable_state(unsigned int state); +unsigned int hdmi_set_blank_state(unsigned int state); +int check_hdmi_state(void); + +#endif diff --git a/include/linux/mfd/pf1550.h b/include/linux/mfd/pf1550.h new file mode 100644 index 000000000000..7d0a13e1144a --- /dev/null +++ b/include/linux/mfd/pf1550.h @@ -0,0 +1,250 @@ +/* + * pf1550.h - mfd head file for PF1550 + * + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Robin Gong <yibin.gong@freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __LINUX_MFD_PF1550_H +#define __LINUX_MFD_PF1550_H + +#include <linux/i2c.h> + +enum chips { PF1550 = 1, }; + +enum pf1550_pmic_reg { + /* PMIC regulator part */ + PF1550_PMIC_REG_DEVICE_ID = 0x00, + PF1550_PMIC_REG_OTP_FLAVOR = 0x01, + PF1550_PMIC_REG_SILICON_REV = 0x02, + + PF1550_PMIC_REG_INT_CATEGORY = 0x06, + PF1550_PMIC_REG_SW_INT_STAT0 = 0x08, + PF1550_PMIC_REG_SW_INT_MASK0 = 0x09, + PF1550_PMIC_REG_SW_INT_SENSE0 = 0x0A, + PF1550_PMIC_REG_SW_INT_STAT1 = 0x0B, + PF1550_PMIC_REG_SW_INT_MASK1 = 0x0C, + PF1550_PMIC_REG_SW_INT_SENSE1 = 0x0D, + PF1550_PMIC_REG_SW_INT_STAT2 = 0x0E, + PF1550_PMIC_REG_SW_INT_MASK2 = 0x0F, + PF1550_PMIC_REG_SW_INT_SENSE2 = 0x10, + PF1550_PMIC_REG_LDO_INT_STAT0 = 0x18, + PF1550_PMIC_REG_LDO_INT_MASK0 = 0x19, + PF1550_PMIC_REG_LDO_INT_SENSE0 = 0x1A, + PF1550_PMIC_REG_TEMP_INT_STAT0 = 0x20, + PF1550_PMIC_REG_TEMP_INT_MASK0 = 0x21, + PF1550_PMIC_REG_TEMP_INT_SENSE0 = 0x22, + PF1550_PMIC_REG_ONKEY_INT_STAT0 = 0x24, + PF1550_PMIC_REG_ONKEY_INT_MASK0 = 0x25, + PF1550_PMIC_REG_ONKEY_INT_SENSE0 = 0x26, + PF1550_PMIC_REG_MISC_INT_STAT0 = 0x28, + PF1550_PMIC_REG_MISC_INT_MASK0 = 0x29, + PF1550_PMIC_REG_MISC_INT_SENSE0 = 0x2A, + + PF1550_PMIC_REG_COINCELL_CONTROL = 0x30, + + PF1550_PMIC_REG_SW1_VOLT = 0x32, + PF1550_PMIC_REG_SW1_STBY_VOLT = 0x33, + PF1550_PMIC_REG_SW1_SLP_VOLT = 0x34, + PF1550_PMIC_REG_SW1_CTRL = 0x35, + PF1550_PMIC_REG_SW1_CTRL1 = 0x36, + PF1550_PMIC_REG_SW2_VOLT = 0x38, + PF1550_PMIC_REG_SW2_STBY_VOLT = 0x39, + PF1550_PMIC_REG_SW2_SLP_VOLT = 0x3A, + PF1550_PMIC_REG_SW2_CTRL = 0x3B, + PF1550_PMIC_REG_SW2_CTRL1 = 0x3C, + PF1550_PMIC_REG_SW3_VOLT = 0x3E, + PF1550_PMIC_REG_SW3_STBY_VOLT = 0x3F, + PF1550_PMIC_REG_SW3_SLP_VOLT = 0x40, + PF1550_PMIC_REG_SW3_CTRL = 0x41, + PF1550_PMIC_REG_SW3_CTRL1 = 0x42, + PF1550_PMIC_REG_VSNVS_CTRL = 0x48, + PF1550_PMIC_REG_VREFDDR_CTRL = 0x4A, + PF1550_PMIC_REG_LDO1_VOLT = 0x4C, + PF1550_PMIC_REG_LDO1_CTRL = 0x4D, + PF1550_PMIC_REG_LDO2_VOLT = 0x4F, + PF1550_PMIC_REG_LDO2_CTRL = 0x50, + PF1550_PMIC_REG_LDO3_VOLT = 0x52, + PF1550_PMIC_REG_LDO3_CTRL = 0x53, + PF1550_PMIC_REG_PWRCTRL0 = 0x58, + PF1550_PMIC_REG_PWRCTRL1 = 0x59, + PF1550_PMIC_REG_PWRCTRL2 = 0x5A, + PF1550_PMIC_REG_PWRCTRL3 = 0x5B, + PF1550_PMIC_REG_SW1_PWRDN_SEQ = 0x5F, + PF1550_PMIC_REG_SW2_PWRDN_SEQ = 0x60, + PF1550_PMIC_REG_SW3_PWRDN_SEQ = 0x61, + PF1550_PMIC_REG_LDO1_PWRDN_SEQ = 0x62, + PF1550_PMIC_REG_LDO2_PWRDN_SEQ = 0x63, + PF1550_PMIC_REG_LDO3_PWRDN_SEQ = 0x64, + PF1550_PMIC_REG_VREFDDR_PWRDN_SEQ = 0x65, + + PF1550_PMIC_REG_STATE_INFO = 0x67, + PF1550_PMIC_REG_I2C_ADDR = 0x68, + PF1550_PMIC_REG_IO_DRV0 = 0x69, + PF1550_PMIC_REG_IO_DRV1 = 0x6A, + PF1550_PMIC_REG_RC_16MHZ = 0x6B, + PF1550_PMIC_REG_KEY = 0x6F, + + /* charger part */ + PF1550_CHARG_REG_CHG_INT = 0x80, + PF1550_CHARG_REG_CHG_INT_MASK = 0x82, + PF1550_CHARG_REG_CHG_INT_OK = 0x84, + PF1550_CHARG_REG_VBUS_SNS = 0x86, + PF1550_CHARG_REG_CHG_SNS = 0x87, + PF1550_CHARG_REG_BATT_SNS = 0x88, + PF1550_CHARG_REG_CHG_OPER = 0x89, + PF1550_CHARG_REG_CHG_TMR = 0x8A, + PF1550_CHARG_REG_CHG_EOC_CNFG = 0x8D, + PF1550_CHARG_REG_CHG_CURR_CNFG = 0x8E, + PF1550_CHARG_REG_BATT_REG = 0x8F, + PF1550_CHARG_REG_BATFET_CNFG = 0x91, + PF1550_CHARG_REG_THM_REG_CNFG = 0x92, + PF1550_CHARG_REG_VBUS_INLIM_CNFG = 0x94, + PF1550_CHARG_REG_VBUS_LIN_DPM = 0x95, + PF1550_CHARG_REG_USB_PHY_LDO_CNFG = 0x96, + PF1550_CHARG_REG_DBNC_DELAY_TIME = 0x98, + PF1550_CHARG_REG_CHG_INT_CNFG = 0x99, + PF1550_CHARG_REG_THM_ADJ_SETTING = 0x9A, + PF1550_CHARG_REG_VBUS2SYS_CNFG = 0x9B, + PF1550_CHARG_REG_LED_PWM = 0x9C, + PF1550_CHARG_REG_FAULT_BATFET_CNFG = 0x9D, + PF1550_CHARG_REG_LED_CNFG = 0x9E, + PF1550_CHARG_REG_CHGR_KEY2 = 0x9F, + + PF1550_TEST_REG_FMRADDR = 0xC4, + PF1550_TEST_REG_FMRDATA = 0xC5, + PF1550_TEST_REG_KEY3 = 0xDF, + + PF1550_PMIC_REG_END = 0xff, +}; + +#define PF1550_CHG_PRECHARGE 0 +#define PF1550_CHG_CONSTANT_CURRENT 1 +#define PF1550_CHG_CONSTANT_VOL 2 +#define PF1550_CHG_EOC 3 +#define PF1550_CHG_DONE 4 +#define PF1550_CHG_TIMER_FAULT 6 +#define PF1550_CHG_SUSPEND 7 +#define PF1550_CHG_OFF_INV 8 +#define PF1550_CHG_BAT_OVER 9 +#define PF1550_CHG_OFF_TEMP 10 +#define PF1550_CHG_LINEAR_ONLY 12 +#define PF1550_CHG_SNS_MASK 0xf + +#define PF1550_BAT_NO_VBUS 0 +#define PF1550_BAT_LOW_THAN_PRECHARG 1 +#define PF1550_BAT_CHARG_FAIL 2 +#define PF1550_BAT_HIGH_THAN_PRECHARG 4 +#define PF1550_BAT_OVER_VOL 5 +#define PF1550_BAT_NO_DETECT 6 +#define PF1550_BAT_SNS_MASK 0x7 + +#define PF1550_VBUS_UVLO BIT(2) +#define PF1550_VBUS_IN2SYS BIT(3) +#define PF1550_VBUS_OVLO BIT(4) +#define PF1550_VBUS_VALID BIT(5) + +#define PF1550_CHARG_REG_BATT_REG_CHGCV_MASK 0x3f +#define PF1550_CHARG_REG_BATT_REG_VMINSYS_SHIFT 6 +#define PF1550_CHARG_REG_BATT_REG_VMINSYS_MASK (0x3 << 6) +#define PF1550_CHARG_REG_THM_REG_CNFG_REGTEMP_SHIFT 2 +#define PF1550_CHARG_REG_THM_REG_CNFG_REGTEMP_MASK (0x3 << 2) + +#define PMIC_IRQ_SW1_LS BIT(0) +#define PMIC_IRQ_SW2_LS BIT(1) +#define PMIC_IRQ_SW3_LS BIT(2) +#define PMIC_IRQ_SW1_HS BIT(0) +#define PMIC_IRQ_SW2_HS BIT(1) +#define PMIC_IRQ_SW3_HS BIT(2) +#define PMIC_IRQ_LDO1_FAULT BIT(0) +#define PMIC_IRQ_LDO2_FAULT BIT(1) +#define PMIC_IRQ_LDO3_FAULT BIT(2) +#define PMIC_IRQ_TEMP_110 BIT(0) +#define PMIC_IRQ_TEMP_125 BIT(1) + +#define ONKEY_IRQ_PUSHI BIT(0) +#define ONKEY_IRQ_1SI BIT(1) +#define ONKEY_IRQ_2SI BIT(2) +#define ONKEY_IRQ_3SI BIT(3) +#define ONKEY_IRQ_4SI BIT(4) +#define ONKEY_IRQ_8SI BIT(5) + +#define CHARG_IRQ_BAT2SOCI BIT(1) +#define CHARG_IRQ_BATI BIT(2) +#define CHARG_IRQ_CHGI BIT(3) +#define CHARG_IRQ_VBUSI BIT(5) +#define CHARG_IRQ_DPMI BIT(6) +#define CHARG_IRQ_THMI BIT(7) + +enum pf1550_pmic_irq { + PF1550_PMIC_IRQ_SW1_LS, + PF1550_PMIC_IRQ_SW2_LS, + PF1550_PMIC_IRQ_SW3_LS, + PF1550_PMIC_IRQ_SW1_HS, + PF1550_PMIC_IRQ_SW2_HS, + PF1550_PMIC_IRQ_SW3_HS, + PF1550_PMIC_IRQ_LDO1_FAULT, + PF1550_PMIC_IRQ_LDO2_FAULT, + PF1550_PMIC_IRQ_LDO3_FAULT, + PF1550_PMIC_IRQ_TEMP_110, + PF1550_PMIC_IRQ_TEMP_125, +}; + +enum pf1550_onkey_irq { + PF1550_ONKEY_IRQ_PUSHI, + PF1550_ONKEY_IRQ_1SI, + PF1550_ONKEY_IRQ_2SI, + PF1550_ONKEY_IRQ_3SI, + PF1550_ONKEY_IRQ_4SI, + PF1550_ONKEY_IRQ_8SI, +}; + +enum pf1550_charg_irq { + PF1550_CHARG_IRQ_BAT2SOCI, + PF1550_CHARG_IRQ_BATI, + PF1550_CHARG_IRQ_CHGI, + PF1550_CHARG_IRQ_VBUSI, + PF1550_CHARG_IRQ_THMI, +}; + +enum pf1550_regulators { + PF1550_SW1, + PF1550_SW2, + PF1550_SW3, + PF1550_VREFDDR, + PF1550_LDO1, + PF1550_LDO2, + PF1550_LDO3, +}; + +struct pf1550_irq_info { + unsigned int irq; + const char *name; + unsigned int virq; +}; + +struct pf1550_dev { + struct device *dev; + struct i2c_client *i2c; + int type; + struct regmap *regmap; + struct regmap_irq_chip_data *irq_data_regulator; + struct regmap_irq_chip_data *irq_data_onkey; + struct regmap_irq_chip_data *irq_data_charger; + int irq; +}; + +int pf1550_read_otp(struct pf1550_dev *pf1550, unsigned int index, + unsigned int *val); + +#endif /* __LINUX_MFD_PF1550_H */ diff --git a/include/linux/mfd/si476x-core.h b/include/linux/mfd/si476x-core.h index 674b45d5a757..78a2b2c936f3 100644 --- a/include/linux/mfd/si476x-core.h +++ b/include/linux/mfd/si476x-core.h @@ -493,6 +493,8 @@ enum si476x_common_receiver_properties { SI476X_PROP_DIGITAL_IO_OUTPUT_SAMPLE_RATE = 0x0202, SI476X_PROP_DIGITAL_IO_OUTPUT_FORMAT = 0x0203, + SI476X_PROP_AUDIO_MUTE = 0x0301, + SI476X_PROP_SEEK_BAND_BOTTOM = 0x1100, SI476X_PROP_SEEK_BAND_TOP = 0x1101, SI476X_PROP_SEEK_FREQUENCY_SPACING = 0x1102, diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index c8e0164c5423..29f225235782 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -101,6 +101,7 @@ #define IMX6Q_GPR1_PCIE_ENTER_L1 BIT(26) #define IMX6Q_GPR1_MIPI_COLOR_SW BIT(25) #define IMX6Q_GPR1_DPI_OFF BIT(24) +#define IMX6Q_GPR1_PCIE_SW_PERST BIT(23) #define IMX6Q_GPR1_EXC_MON_MASK BIT(22) #define IMX6Q_GPR1_EXC_MON_OKAY 0x0 #define IMX6Q_GPR1_EXC_MON_SLVE BIT(22) @@ -243,6 +244,23 @@ #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR5_ENET_TX_CLK_SEL BIT(9) +#define IMX6Q_GPR5_PRE_PRG_SEL0_MASK (0x3 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL0_SHIFT 12 +#define IMX6Q_GPR5_PRE_PRG_SEL0_MSB 13 +#define IMX6Q_GPR5_PRE_PRG_SEL0_LSB 12 +#define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG0_CHAN1 (0x0 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG0_CHAN2 (0x1 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG1_CHAN1 (0x2 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG1_CHAN2 (0x3 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL1_MASK (0x3 << 14) +#define IMX6Q_GPR5_PRE_PRG_SEL1_SHIFT 14 +#define IMX6Q_GPR5_PRE_PRG_SEL1_MSB 15 +#define IMX6Q_GPR5_PRE_PRG_SEL1_LSB 14 +#define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG0_CHAN1 (0x0 << 14) +#define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG0_CHAN2 (0x1 << 14) +#define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG1_CHAN1 (0x2 << 14) +#define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG1_CHAN2 (0x3 << 14) #define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK (0xf << 0) #define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK (0xf << 4) @@ -286,23 +304,25 @@ #define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << 5) #define IMX6Q_GPR10_OCRAM_TZ_EN_MASK BIT(4) #define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK (0x3 << 2) -#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0 (0x0 << 2) -#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x1 << 2) -#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0 (0x2 << 2) -#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1 (0x3 << 2) +#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x0 << 2) +#define IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS0 (0x1 << 2) +#define IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS1 (0x2 << 2) +#define IMX6Q_GPR10_DCIC2_MUX_CTL_MIPI (0x3 << 2) #define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK (0x3 << 0) #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0 (0x0 << 0) -#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1 (0x1 << 0) -#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0 (0x2 << 0) -#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1 (0x3 << 0) +#define IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS0 (0x1 << 0) +#define IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS1 (0x2 << 0) +#define IMX6Q_GPR10_DCIC1_MUX_CTL_HDMI (0x3 << 0) #define IMX6Q_GPR12_ARMP_IPG_CLK_EN BIT(27) #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25) #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24) +#define IMX6Q_GPR12_PCIE_PM_TURN_OFF BIT(16) #define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12) #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) #define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4) +#define IMX6Q_GPR12_LOS_LEVEL_9 (0x9 << 4) #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) @@ -411,6 +431,15 @@ #define IMX6SX_GPR4_FEC_ENET1_STOP_REQ (0x1 << 3) #define IMX6SX_GPR4_FEC_ENET2_STOP_REQ (0x1 << 4) +#define IMX6SX_GPR2_MQS_OVERSAMPLE_MASK (0x1 << 26) +#define IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT (26) +#define IMX6SX_GPR2_MQS_EN_MASK (0x1 << 25) +#define IMX6SX_GPR2_MQS_EN_SHIFT (25) +#define IMX6SX_GPR2_MQS_SW_RST_MASK (0x1 << 24) +#define IMX6SX_GPR2_MQS_SW_RST_SHIFT (24) +#define IMX6SX_GPR2_MQS_CLK_DIV_MASK (0xFF << 16) +#define IMX6SX_GPR2_MQS_CLK_DIV_SHIFT (16) + #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK (0x1 << 3) #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1 (0x0 << 3) #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2 (0x1 << 3) @@ -423,6 +452,7 @@ #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK (0x1 << 26) #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_ENABLE (0x1 << 26) #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_DISABLE (0x0 << 26) +#define IMX6SX_GPR5_PCIE_PERST BIT(18) #define IMX6SX_GPR5_PCIE_BTNRST_RESET BIT(19) #define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK (0x3 << 4) #define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN (0x0 << 4) @@ -437,10 +467,21 @@ #define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS (0x1 << 1) #define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1) +#define IMX6SX_GPR12_PCIE_PM_TURN_OFF BIT(16) #define IMX6SX_GPR12_PCIE_TEST_POWERDOWN BIT(30) #define IMX6SX_GPR12_PCIE_RX_EQ_MASK (0x7 << 0) #define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0) +/* For imx6dl iomux gpr register field definitions */ +#define IMX6DL_GPR3_LVDS1_MUX_CTL_MASK (0x3 << 8) +#define IMX6DL_GPR3_LVDS1_MUX_CTL_IPU1_DI0 (0x0 << 8) +#define IMX6DL_GPR3_LVDS1_MUX_CTL_IPU1_DI1 (0x1 << 8) +#define IMX6DL_GPR3_LVDS1_MUX_CTL_LCDIF (0x2 << 8) +#define IMX6DL_GPR3_LVDS0_MUX_CTL_MASK (0x3 << 6) +#define IMX6DL_GPR3_LVDS0_MUX_CTL_IPU1_DI0 (0x0 << 6) +#define IMX6DL_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6) +#define IMX6DL_GPR3_LVDS0_MUX_CTL_LCDIF (0x2 << 6) + /* For imx6ul iomux gpr register field define */ #define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17) #define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18) diff --git a/include/linux/mfd/syscon/imx7-iomuxc-gpr.h b/include/linux/mfd/syscon/imx7-iomuxc-gpr.h index abbd52466573..af33fcb13339 100644 --- a/include/linux/mfd/syscon/imx7-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx7-iomuxc-gpr.h @@ -34,6 +34,8 @@ #define IOMUXC_GPR22 0x58 /* For imx7d iomux gpr register field define */ +#define IMX7D_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (0x3 << 7) + #define IMX7D_GPR1_IRQ_MASK (0x1 << 12) #define IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK (0x1 << 13) #define IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK (0x1 << 14) diff --git a/include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h b/include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h new file mode 100644 index 000000000000..cfb857774cf5 --- /dev/null +++ b/include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_IMX8MQ_IOMUXC_GPR_H +#define __LINUX_IMX8MQ_IOMUXC_GPR_H + +#define IOMUXC_GPR0 0x00 +#define IOMUXC_GPR1 0x04 +#define IOMUXC_GPR2 0x08 +#define IOMUXC_GPR3 0x0c +#define IOMUXC_GPR4 0x10 +#define IOMUXC_GPR5 0x14 +#define IOMUXC_GPR6 0x18 +#define IOMUXC_GPR7 0x1c +#define IOMUXC_GPR8 0x20 +#define IOMUXC_GPR9 0x24 +#define IOMUXC_GPR10 0x28 +#define IOMUXC_GPR11 0x2c +#define IOMUXC_GPR12 0x30 +#define IOMUXC_GPR13 0x34 +#define IOMUXC_GPR14 0x38 +#define IOMUXC_GPR15 0x3c +#define IOMUXC_GPR16 0x40 +#define IOMUXC_GPR17 0x44 +#define IOMUXC_GPR18 0x48 +#define IOMUXC_GPR19 0x4c +#define IOMUXC_GPR20 0x50 +#define IOMUXC_GPR21 0x54 +#define IOMUXC_GPR22 0x58 +#define IOMUXC_GPR23 0x5c +#define IOMUXC_GPR24 0x60 +#define IOMUXC_GPR25 0x64 +#define IOMUXC_GPR26 0x68 +#define IOMUXC_GPR27 0x6c +#define IOMUXC_GPR28 0x70 +#define IOMUXC_GPR29 0x74 +#define IOMUXC_GPR30 0x78 +#define IOMUXC_GPR31 0x7c +#define IOMUXC_GPR32 0x80 +#define IOMUXC_GPR33 0x84 +#define IOMUXC_GPR34 0x88 +#define IOMUXC_GPR35 0x8c +#define IOMUXC_GPR36 0x90 +#define IOMUXC_GPR37 0x94 +#define IOMUXC_GPR38 0x98 +#define IOMUXC_GPR39 0x9c +#define IOMUXC_GPR40 0xa0 +#define IOMUXC_GPR41 0xa4 +#define IOMUXC_GPR42 0xa8 +#define IOMUXC_GPR43 0xac +#define IOMUXC_GPR44 0xb0 +#define IOMUXC_GPR45 0xb4 +#define IOMUXC_GPR46 0xb8 +#define IOMUXC_GPR47 0xbc + +#define IMX8MQ_GPR13_MIPI_MUX_SEL BIT(2) + +#endif /* __LINUX_IMX8MQ_IOMUXC_GPR_H */ diff --git a/include/linux/mipi_csi2.h b/include/linux/mipi_csi2.h new file mode 100644 index 000000000000..7dc76fd293f8 --- /dev/null +++ b/include/linux/mipi_csi2.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __INCLUDE_MIPI_CSI2_H +#define __INCLUDE_MIPI_CSI2_H + +/* MIPI CSI2 registers */ +#define MIPI_CSI2_REG(offset) (offset) + +#define MIPI_CSI2_VERSION MIPI_CSI2_REG(0x000) +#define MIPI_CSI2_N_LANES MIPI_CSI2_REG(0x004) +#define MIPI_CSI2_PHY_SHUTDOWNZ MIPI_CSI2_REG(0x008) +#define MIPI_CSI2_DPHY_RSTZ MIPI_CSI2_REG(0x00c) +#define MIPI_CSI2_CSI2_RESETN MIPI_CSI2_REG(0x010) +#define MIPI_CSI2_PHY_STATE MIPI_CSI2_REG(0x014) +#define MIPI_CSI2_DATA_IDS_1 MIPI_CSI2_REG(0x018) +#define MIPI_CSI2_DATA_IDS_2 MIPI_CSI2_REG(0x01c) +#define MIPI_CSI2_ERR1 MIPI_CSI2_REG(0x020) +#define MIPI_CSI2_ERR2 MIPI_CSI2_REG(0x024) +#define MIPI_CSI2_MASK1 MIPI_CSI2_REG(0x028) +#define MIPI_CSI2_MASK2 MIPI_CSI2_REG(0x02c) +#define MIPI_CSI2_PHY_TST_CTRL0 MIPI_CSI2_REG(0x030) +#define MIPI_CSI2_PHY_TST_CTRL1 MIPI_CSI2_REG(0x034) +#define MIPI_CSI2_SFT_RESET MIPI_CSI2_REG(0xf00) + +/* mipi data type */ +#define MIPI_DT_YUV420 0x18 /* YYY.../UYVY.... */ +#define MIPI_DT_YUV420_LEGACY 0x1a /* UYY.../VYY... */ +#define MIPI_DT_YUV422 0x1e /* UYVY... */ +#define MIPI_DT_RGB444 0x20 +#define MIPI_DT_RGB555 0x21 +#define MIPI_DT_RGB565 0x22 +#define MIPI_DT_RGB666 0x23 +#define MIPI_DT_RGB888 0x24 +#define MIPI_DT_RAW6 0x28 +#define MIPI_DT_RAW7 0x29 +#define MIPI_DT_RAW8 0x2a +#define MIPI_DT_RAW10 0x2b +#define MIPI_DT_RAW12 0x2c +#define MIPI_DT_RAW14 0x2d + + +struct mipi_csi2_info; +/* mipi csi2 API */ +struct mipi_csi2_info *mipi_csi2_get_info(void); + +bool mipi_csi2_enable(struct mipi_csi2_info *info); + +bool mipi_csi2_disable(struct mipi_csi2_info *info); + +bool mipi_csi2_get_status(struct mipi_csi2_info *info); + +int mipi_csi2_get_bind_ipu(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_get_bind_csi(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_get_virtual_channel(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_set_lanes(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_set_datatype(struct mipi_csi2_info *info, + unsigned int datatype); + +unsigned int mipi_csi2_get_datatype(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_dphy_status(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_get_error1(struct mipi_csi2_info *info); + +unsigned int mipi_csi2_get_error2(struct mipi_csi2_info *info); + +int mipi_csi2_pixelclk_enable(struct mipi_csi2_info *info); + +void mipi_csi2_pixelclk_disable(struct mipi_csi2_info *info); + +int mipi_csi2_reset(struct mipi_csi2_info *info); + +#endif diff --git a/include/linux/mipi_dsi.h b/include/linux/mipi_dsi.h new file mode 100644 index 000000000000..dbc249a38f68 --- /dev/null +++ b/include/linux/mipi_dsi.h @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __INCLUDE_MIPI_DSI_H +#define __INCLUDE_MIPI_DSI_H + +#define MIPI_DSI_VERSION (0x000) +#define MIPI_DSI_PWR_UP (0x004) +#define MIPI_DSI_CLKMGR_CFG (0x008) +#define MIPI_DSI_DPI_CFG (0x00c) +#define MIPI_DSI_DBI_CFG (0x010) +#define MIPI_DSI_DBIS_CMDSIZE (0x014) +#define MIPI_DSI_PCKHDL_CFG (0x018) +#define MIPI_DSI_VID_MODE_CFG (0x01c) +#define MIPI_DSI_VID_PKT_CFG (0x020) +#define MIPI_DSI_CMD_MODE_CFG (0x024) +#define MIPI_DSI_TMR_LINE_CFG (0x028) +#define MIPI_DSI_VTIMING_CFG (0x02c) +#define MIPI_DSI_PHY_TMR_CFG (0x030) +#define MIPI_DSI_GEN_HDR (0x034) +#define MIPI_DSI_GEN_PLD_DATA (0x038) +#define MIPI_DSI_CMD_PKT_STATUS (0x03c) +#define MIPI_DSI_TO_CNT_CFG (0x040) +#define MIPI_DSI_ERROR_ST0 (0x044) +#define MIPI_DSI_ERROR_ST1 (0x048) +#define MIPI_DSI_ERROR_MSK0 (0x04c) +#define MIPI_DSI_ERROR_MSK1 (0x050) +#define MIPI_DSI_PHY_RSTZ (0x054) +#define MIPI_DSI_PHY_IF_CFG (0x058) +#define MIPI_DSI_PHY_IF_CTRL (0x05c) +#define MIPI_DSI_PHY_STATUS (0x060) +#define MIPI_DSI_PHY_TST_CTRL0 (0x064) +#define MIPI_DSI_PHY_TST_CTRL1 (0x068) + +#define DSI_PWRUP_RESET (0x0 << 0) +#define DSI_PWRUP_POWERUP (0x1 << 0) + +#define DSI_DPI_CFG_VID_SHIFT (0) +#define DSI_DPI_CFG_VID_MASK (0x3) +#define DSI_DPI_CFG_COLORCODE_SHIFT (2) +#define DSI_DPI_CFG_COLORCODE_MASK (0x7) +#define DSI_DPI_CFG_DATAEN_ACT_LOW (0x1 << 5) +#define DSI_DPI_CFG_DATAEN_ACT_HIGH (0x0 << 5) +#define DSI_DPI_CFG_VSYNC_ACT_LOW (0x1 << 6) +#define DSI_DPI_CFG_VSYNC_ACT_HIGH (0x0 << 6) +#define DSI_DPI_CFG_HSYNC_ACT_LOW (0x1 << 7) +#define DSI_DPI_CFG_HSYNC_ACT_HIGH (0x0 << 7) +#define DSI_DPI_CFG_SHUTD_ACT_LOW (0x1 << 8) +#define DSI_DPI_CFG_SHUTD_ACT_HIGH (0x0 << 8) +#define DSI_DPI_CFG_COLORMODE_ACT_LOW (0x1 << 9) +#define DSI_DPI_CFG_COLORMODE_ACT_HIGH (0x0 << 9) +#define DSI_DPI_CFG_EN18LOOSELY (0x1 << 10) + +#define DSI_PCKHDL_CFG_EN_EOTP_TX (0x1 << 0) +#define DSI_PCKHDL_CFG_EN_EOTP_RX (0x1 << 1) +#define DSI_PCKHDL_CFG_EN_BTA (0x1 << 2) +#define DSI_PCKHDL_CFG_EN_ECC_RX (0x1 << 3) +#define DSI_PCKHDL_CFG_EN_CRC_RX (0x1 << 4) +#define DSI_PCKHDL_CFG_GEN_VID_RX_MASK (0x3) +#define DSI_PCKHDL_CFG_GEN_VID_RX_SHIFT (5) + +#define DSI_VID_MODE_CFG_EN (0x1 << 0) +#define DSI_VID_MODE_CFG_EN_BURSTMODE (0x3 << 1) +#define DSI_VID_MODE_CFG_TYPE_MASK (0x3) +#define DSI_VID_MODE_CFG_TYPE_SHIFT (1) +#define DSI_VID_MODE_CFG_EN_LP_VSA (0x1 << 3) +#define DSI_VID_MODE_CFG_EN_LP_VBP (0x1 << 4) +#define DSI_VID_MODE_CFG_EN_LP_VFP (0x1 << 5) +#define DSI_VID_MODE_CFG_EN_LP_VACT (0x1 << 6) +#define DSI_VID_MODE_CFG_EN_LP_HBP (0x1 << 7) +#define DSI_VID_MODE_CFG_EN_LP_HFP (0x1 << 8) +#define DSI_VID_MODE_CFG_EN_MULTI_PKT (0x1 << 9) +#define DSI_VID_MODE_CFG_EN_NULL_PKT (0x1 << 10) +#define DSI_VID_MODE_CFG_EN_FRAME_ACK (0x1 << 11) +#define DSI_VID_MODE_CFG_EN_LP_MODE (DSI_VID_MODE_CFG_EN_LP_VSA | \ + DSI_VID_MODE_CFG_EN_LP_VBP | \ + DSI_VID_MODE_CFG_EN_LP_VFP | \ + DSI_VID_MODE_CFG_EN_LP_HFP | \ + DSI_VID_MODE_CFG_EN_LP_HBP | \ + DSI_VID_MODE_CFG_EN_LP_VACT) + + + +#define DSI_VID_PKT_CFG_VID_PKT_SZ_MASK (0x7ff) +#define DSI_VID_PKT_CFG_VID_PKT_SZ_SHIFT (0) +#define DSI_VID_PKT_CFG_NUM_CHUNKS_MASK (0x3ff) +#define DSI_VID_PKT_CFG_NUM_CHUNKS_SHIFT (11) +#define DSI_VID_PKT_CFG_NULL_PKT_SZ_MASK (0x3ff) +#define DSI_VID_PKT_CFG_NULL_PKT_SZ_SHIFT (21) + +#define MIPI_DSI_CMD_MODE_CFG_EN_LOWPOWER (0x1FFF) +#define MIPI_DSI_CMD_MODE_CFG_EN_CMD_MODE (0x1 << 0) + +#define DSI_TME_LINE_CFG_HSA_TIME_MASK (0x1ff) +#define DSI_TME_LINE_CFG_HSA_TIME_SHIFT (0) +#define DSI_TME_LINE_CFG_HBP_TIME_MASK (0x1ff) +#define DSI_TME_LINE_CFG_HBP_TIME_SHIFT (9) +#define DSI_TME_LINE_CFG_HLINE_TIME_MASK (0x3fff) +#define DSI_TME_LINE_CFG_HLINE_TIME_SHIFT (18) + +#define DSI_VTIMING_CFG_VSA_LINES_MASK (0xf) +#define DSI_VTIMING_CFG_VSA_LINES_SHIFT (0) +#define DSI_VTIMING_CFG_VBP_LINES_MASK (0x3f) +#define DSI_VTIMING_CFG_VBP_LINES_SHIFT (4) +#define DSI_VTIMING_CFG_VFP_LINES_MASK (0x3f) +#define DSI_VTIMING_CFG_VFP_LINES_SHIFT (10) +#define DSI_VTIMING_CFG_V_ACT_LINES_MASK (0x7ff) +#define DSI_VTIMING_CFG_V_ACT_LINES_SHIFT (16) + +#define DSI_PHY_TMR_CFG_BTA_TIME_MASK (0xfff) +#define DSI_PHY_TMR_CFG_BTA_TIME_SHIFT (0) +#define DSI_PHY_TMR_CFG_LP2HS_TIME_MASK (0xff) +#define DSI_PHY_TMR_CFG_LP2HS_TIME_SHIFT (12) +#define DSI_PHY_TMR_CFG_HS2LP_TIME_MASK (0xff) +#define DSI_PHY_TMR_CFG_HS2LP_TIME_SHIFT (20) + +#define DSI_PHY_IF_CFG_N_LANES_MASK (0x3) +#define DSI_PHY_IF_CFG_N_LANES_SHIFT (0) +#define DSI_PHY_IF_CFG_WAIT_TIME_MASK (0xff) +#define DSI_PHY_IF_CFG_WAIT_TIME_SHIFT (2) + +#define DSI_PHY_RSTZ_EN_CLK (0x1 << 2) +#define DSI_PHY_RSTZ_DISABLE_RST (0x1 << 1) +#define DSI_PHY_RSTZ_DISABLE_SHUTDOWN (0x1 << 0) +#define DSI_PHY_RSTZ_RST (0x0) + +#define DSI_PHY_STATUS_LOCK (0x1 << 0) +#define DSI_PHY_STATUS_STOPSTATE_CLK_LANE (0x1 << 2) + +#define DSI_GEN_HDR_TYPE_MASK (0xff) +#define DSI_GEN_HDR_TYPE_SHIFT (0) +#define DSI_GEN_HDR_DATA_MASK (0xffff) +#define DSI_GEN_HDR_DATA_SHIFT (8) + +#define DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY (0x1 << 0) +#define DSI_CMD_PKT_STATUS_GEN_CMD_FULL (0x1 << 1) +#define DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY (0x1 << 2) +#define DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL (0x1 << 3) +#define DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY (0x1 << 4) +#define DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY (0x1 << 6) + +#define DSI_ERROR_MSK0_ALL_MASK (0x1fffff) +#define DSI_ERROR_MSK1_ALL_MASK (0x3ffff) + +#define DSI_PHY_IF_CTRL_RESET (0x0) +#define DSI_PHY_IF_CTRL_TX_REQ_CLK_HS (0x1 << 0) +#define DSI_PHY_IF_CTRL_TX_REQ_CLK_ULPS (0x1 << 1) +#define DSI_PHY_IF_CTRL_TX_EXIT_CLK_ULPS (0x1 << 2) +#define DSI_PHY_IF_CTRL_TX_REQ_DATA_ULPS (0x1 << 3) +#define DSI_PHY_IF_CTRL_TX_EXIT_DATA_ULPS (0x1 << 4) +#define DSI_PHY_IF_CTRL_TX_TRIG_MASK (0xF) +#define DSI_PHY_IF_CTRL_TX_TRIG_SHIFT (5) + +#define DSI_PHY_CLK_INIT_COMMAND (0x44) +#define DSI_GEN_PLD_DATA_BUF_SIZE (0x4) +#endif diff --git a/include/linux/mipi_dsi_northwest.h b/include/linux/mipi_dsi_northwest.h new file mode 100644 index 000000000000..8cb379c85ef5 --- /dev/null +++ b/include/linux/mipi_dsi_northwest.h @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __INCLUDE_MIPI_DSI_NORTHWEST_H +#define __INCLUDE_MIPI_DSI_NORTHWEST_H + +/* ---------------------------- register offsets --------------------------- */ + +/* sim */ +#define SIM_SOPT1 0x0 +#define MIPI_ISO_DISABLE 0x8 + +#define SIM_SOPT1CFG 0x4 +#define DSI_RST_DPI_N 0x80000000 +#define DSI_RST_ESC_N 0x40000000 +#define DSI_RST_BYTE_N 0x20000000 +#define DSI_SD 0x200 +#define DSI_CM 0x100 +#define DSI_PLL_EN 0x80 + +/* SRC */ +#define SRC_MIPIPHY_RCR 0x28 +#define MIPI_DSI_RESET_BYTE_N 0x2 +#define MIPI_DSI_RESET_N 0x4 +#define MIPI_DSI_DPI_RESET_N 0x8 +#define MIPI_DSI_ESC_RESET_N 0x10 +#define MIPI_DSI_PCLK_RESET_N 0x20 + +/* GPR */ +#define IOMUXC_GPR_GPR13 0x34 +#define GPR_MIPI_MUX_SEL 0x4 + +/* dphy */ +#define DPHY_PD_DPHY 0x300 +#define DPHY_M_PRG_HS_PREPARE 0x304 +#define DPHY_MC_PRG_HS_PREPARE 0x308 +#define DPHY_M_PRG_HS_ZERO 0x30c +#define DPHY_MC_PRG_HS_ZERO 0x310 +#define DPHY_M_PRG_HS_TRAIL 0x314 +#define DPHY_MC_PRG_HS_TRAIL 0x318 +#define DPHY_PD_PLL 0x31c +#define DPHY_TST 0x320 +#define DPHY_CN 0x324 +#define DPHY_CM 0x328 +#define DPHY_CO 0x32c +#define DPHY_LOCK 0x330 +#define DPHY_LOCK_BYP 0x334 +#define DPHY_RTERM_SEL 0x338 +#define DPHY_AUTO_PD_EN 0x33c +#define DPHY_RXLPRP 0x340 +#define DPHY_RXCDRP 0x344 + +/* host */ +#define HOST_CFG_NUM_LANES 0x0 +#define HOST_CFG_NONCONTINUOUS_CLK 0x4 +#define HOST_CFG_T_PRE 0x8 +#define HOST_CFG_T_POST 0xc +#define HOST_CFG_TX_GAP 0x10 +#define HOST_CFG_AUTOINSERT_EOTP 0x14 +#define HOST_CFG_EXTRA_CMDS_AFTER_EOTP 0x18 +#define HOST_CFG_HTX_TO_COUNT 0x1c +#define HOST_CFG_LRX_H_TO_COUNT 0x20 +#define HOST_CFG_BTA_H_TO_COUNT 0x24 +#define HOST_CFG_TWAKEUP 0x28 +#define HOST_CFG_STATUS_OUT 0x2c +#define HOST_RX_ERROR_STATUS 0x30 + +/* dpi */ +#define DPI_PIXEL_PAYLOAD_SIZE 0x200 +#define DPI_PIXEL_FIFO_SEND_LEVEL 0x204 +#define DPI_INTERFACE_COLOR_CODING 0x208 +#define DPI_PIXEL_FORMAT 0x20c +#define DPI_VSYNC_POLARITY 0x210 +#define DPI_HSYNC_POLARITY 0x214 +#define DPI_VIDEO_MODE 0x218 +#define DPI_HFP 0x21c +#define DPI_HBP 0x220 +#define DPI_HSA 0x224 +#define DPI_ENABLE_MULT_PKTS 0x228 +#define DPI_VBP 0x22c +#define DPI_VFP 0x230 +#define DPI_BLLP_MODE 0x234 +#define DPI_USE_NULL_PKT_BLLP 0x238 +#define DPI_VACTIVE 0x23c +#define DPI_VC 0x240 + +/* apb pkt */ +#define HOST_TX_PAYLOAD 0x280 + +#define HOST_PKT_CONTROL 0x284 +#define HOST_PKT_CONTROL_WC(x) (((x) & 0xffff) << 0) +#define HOST_PKT_CONTROL_VC(x) (((x) & 0x3) << 16) +#define HOST_PKT_CONTROL_DT(x) (((x) & 0x3f) << 18) +#define HOST_PKT_CONTROL_HS_SEL(x) (((x) & 0x1) << 24) +#define HOST_PKT_CONTROL_BTA_TX(x) (((x) & 0x1) << 25) +#define HOST_PKT_CONTROL_BTA_NO_TX(x) (((x) & 0x1) << 26) + +#define HOST_SEND_PACKET 0x288 +#define HOST_PKT_STATUS 0x28c +#define HOST_PKT_FIFO_WR_LEVEL 0x290 +#define HOST_PKT_FIFO_RD_LEVEL 0x294 +#define HOST_PKT_RX_PAYLOAD 0x298 + +#define HOST_PKT_RX_PKT_HEADER 0x29c +#define HOST_PKT_RX_PKT_HEADER_WC(x) (((x) & 0xffff) << 0) +#define HOST_PKT_RX_PKT_HEADER_DT(x) (((x) & 0x3f) << 16) +#define HOST_PKT_RX_PKT_HEADER_VC(x) (((x) & 0x3) << 22) + +#define HOST_IRQ_STATUS 0x2a0 +#define HOST_IRQ_STATUS_SM_NOT_IDLE (1 << 0) +#define HOST_IRQ_STATUS_TX_PKT_DONE (1 << 1) +#define HOST_IRQ_STATUS_DPHY_DIRECTION (1 << 2) +#define HOST_IRQ_STATUS_TX_FIFO_OVFLW (1 << 3) +#define HOST_IRQ_STATUS_TX_FIFO_UDFLW (1 << 4) +#define HOST_IRQ_STATUS_RX_FIFO_OVFLW (1 << 5) +#define HOST_IRQ_STATUS_RX_FIFO_UDFLW (1 << 6) +#define HOST_IRQ_STATUS_RX_PKT_HDR_RCVD (1 << 7) +#define HOST_IRQ_STATUS_RX_PKT_PAYLOAD_DATA_RCVD (1 << 8) +#define HOST_IRQ_STATUS_HOST_BTA_TIMEOUT (1 << 29) +#define HOST_IRQ_STATUS_LP_RX_TIMEOUT (1 << 30) +#define HOST_IRQ_STATUS_HS_TX_TIMEOUT (1 << 31) + +#define HOST_IRQ_STATUS2 0x2a4 +#define HOST_IRQ_STATUS2_SINGLE_BIT_ECC_ERR (1 << 0) +#define HOST_IRQ_STATUS2_MULTI_BIT_ECC_ERR (1 << 1) +#define HOST_IRQ_STATUS2_CRC_ERR (1 << 2) + +#define HOST_IRQ_MASK 0x2a8 +#define HOST_IRQ_MASK_SM_NOT_IDLE_MASK (1 << 0) +#define HOST_IRQ_MASK_TX_PKT_DONE_MASK (1 << 1) +#define HOST_IRQ_MASK_DPHY_DIRECTION_MASK (1 << 2) +#define HOST_IRQ_MASK_TX_FIFO_OVFLW_MASK (1 << 3) +#define HOST_IRQ_MASK_TX_FIFO_UDFLW_MASK (1 << 4) +#define HOST_IRQ_MASK_RX_FIFO_OVFLW_MASK (1 << 5) +#define HOST_IRQ_MASK_RX_FIFO_UDFLW_MASK (1 << 6) +#define HOST_IRQ_MASK_RX_PKT_HDR_RCVD_MASK (1 << 7) +#define HOST_IRQ_MASK_RX_PKT_PAYLOAD_DATA_RCVD_MASK (1 << 8) +#define HOST_IRQ_MASK_HOST_BTA_TIMEOUT_MASK (1 << 29) +#define HOST_IRQ_MASK_LP_RX_TIMEOUT_MASK (1 << 30) +#define HOST_IRQ_MASK_HS_TX_TIMEOUT_MASK (1 << 31) + +#define HOST_IRQ_MASK2 0x2ac +#define HOST_IRQ_MASK2_SINGLE_BIT_ECC_ERR_MASK (1 << 0) +#define HOST_IRQ_MASK2_MULTI_BIT_ECC_ERR_MASK (1 << 1) +#define HOST_IRQ_MASK2_CRC_ERR_MASK (1 << 2) + +/* ------------------------------------- end -------------------------------- */ + +#endif diff --git a/include/linux/mipi_dsi_samsung.h b/include/linux/mipi_dsi_samsung.h new file mode 100644 index 000000000000..e58da9541cfb --- /dev/null +++ b/include/linux/mipi_dsi_samsung.h @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __INCLUDE_MIPI_DSI_SAMSUNG_H +#define __INCLUDE_MIPI_DSI_SAMSUNG_H + +#define MIPI_DSI_VERSION (0x000) +#define MIPI_DSI_STATUS (0x004) +#define MIPI_DSI_RGB_STATUS (0x008) +#define MIPI_DSI_SWRST (0x00c) +#define MIPI_DSI_CLKCTRL (0x010) +#define MIPI_DSI_TIMEOUT (0x014) +#define MIPI_DSI_CONFIG (0x018) +#define MIPI_DSI_ESCMODE (0x01c) +#define MIPI_DSI_MDRESOL (0x020) +#define MIPI_DSI_MVPORCH (0x024) +#define MIPI_DSI_MHPORCH (0x028) +#define MIPI_DSI_MSYNC (0x02c) +#define MIPI_DSI_SDRESOL (0x030) +#define MIPI_DSI_INTSRC (0x034) +#define MIPI_DSI_INTMSK (0x038) +#define MIPI_DSI_PKTHDR (0x03c) +#define MIPI_DSI_PAYLOAD (0x040) +#define MIPI_DSI_RXFIFO (0x044) +#define MIPI_DSI_FIFOTHLD (0x048) +#define MIPI_DSI_FIFOCTRL (0x04c) +#define MIPI_DSI_MEMACCHR (0x050) +#define MIPI_DSI_MULTI_PKT (0x078) +#define MIPI_DSI_PLLCTRL_1G (0x090) +#define MIPI_DSI_PLLCTRL (0x094) +#define MIPI_DSI_PLLCTRL1 (0x098) +#define MIPI_DSI_PLLCTRL2 (0x09c) +#define MIPI_DSI_PLLTMR (0x0a0) +#define MIPI_DSI_PHYCTRL_B1 (0x0a4) +#define MIPI_DSI_PHYCTRL_B2 (0x0a8) +#define MIPI_DSI_PHYCTRL_M1 (0x0a8) +#define MIPI_DSI_PHYCTRL_M2 (0x0ac) +#define MIPI_DSI_PHYTIMING (0x0b4) +#define MIPI_DSI_PHYTIMING1 (0x0b8) +#define MIPI_DSI_PHYTIMING2 (0x0bc) + +#define MIPI_DSI_SWRST_SWRST (0x1 << 0) +#define MIPI_DSI_SWRST_FUNCRST (0x1 << 16) +#define MIPI_DSI_MAIN_HRESOL(x) (((x) & 0x7ff) << 0) +#define MIPI_DSI_MAIN_VRESOL(x) (((x) & 0x7ff) << 16) +#define MIPI_DSI_MAIN_STANDBY(x) (((x) & 0x1) << 31) +#define MIPI_DSI_MAIN_VBP(x) (((x) & 0x7ff) << 0) +#define MIPI_DSI_STABLE_VFP(x) (((x) & 0x7ff) << 16) +#define MIPI_DSI_CMDALLOW(x) (((x) & 0xf) << 28) +#define MIPI_DSI_MAIN_HBP(x) (((x) & 0xffff) << 0) +#define MIPI_DSI_MAIN_HFP(x) (((x) & 0xffff) << 16) +#define MIPI_DSI_MAIN_VSA(x) (((x) & 0x3ff) << 22) +#define MIPI_DSI_MAIN_HSA(x) (((x) & 0xffff) << 0) + +#define MIPI_DSI_LANE_EN(x) (((x) & 0x1f) << 0) +#define MIPI_DSI_NUM_OF_DATALANE(x) (((x) & 0x3) << 5) +#define MIPI_DSI_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) +#define MIPI_DSI_MAIN_PIX_FORMAT(x) (((x) & 0x7) << 12) +#define MIPI_DSI_SUB_VC(x) (((x) & 0x3) << 16) +#define MIPI_DSI_MAIN_VC(x) (((x) & 0x3) << 18) +#define MIPI_DSI_HSA_DISABLE_MODE(x) (((x) & 0x1) << 20) +#define MIPI_DSI_HBP_DISABLE_MODE(x) (((x) & 0x1) << 21) +#define MIPI_DSI_HFP_DISABLE_MODE(x) (((x) & 0x1) << 22) +#define MIPI_DSI_HSE_DISABLE_MODE(x) (((x) & 0x1) << 23) +#define MIPI_DSI_AUTO_MODE(x) (((x) & 0x1) << 24) +#define MIPI_DSI_VIDEO_MODE(x) (((x) & 0x1) << 25) +#define MIPI_DSI_BURST_MODE(x) (((x) & 0x1) << 26) +#define MIPI_DSI_SYNC_IN_FORM(x) (((x) & 0x1) << 27) +#define MIPI_DSI_EOT_R03(x) (((x) & 0x1) << 28) +#define MIPI_DSI_MFLUSH_VS(x) (((x) & 0x1) << 29) + +#define MIPI_DSI_DP_DN_SWAP_DATA (0x1 << 24) +#define MIPI_DSI_PLL_EN(x) (((x) & 0x1) << 23) +#define MIPI_DSI_PMS(x) (((x) & 0x7ffff) << 1) + +#define MIPI_DSI_TX_REQUEST_HSCLK(x) (((x) & 0x1) << 31) +#define MIPI_DSI_DPHY_SEL(x) (((x) & 0x1) << 29) +#define MIPI_DSI_ESC_CLK_EN(x) (((x) & 0x1) << 28) +#define MIPI_DSI_PLL_BYPASS(x) (((x) & 0x1) << 27) +#define MIPI_DSI_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) +#define MIPI_DSI_BYTE_CLK_EN(x) (((x) & 0x1) << 24) +#define MIPI_DSI_LANE_ESC_CLK_EN(x) (((x) & 0x1f) << 19) + +#define MIPI_DSI_FORCE_STOP_STATE(x) (((x) & 0x1) << 20) + +#define MIPI_DSI_M_TLPXCTL(x) (((x) & 0xff) << 8) +#define MIPI_DSI_M_THSEXITCTL(x) (((x) & 0xff) << 0) + +#define MIPI_DSI_M_TCLKPRPRCTL(x) (((x) & 0xff) << 24) +#define MIPI_DSI_M_TCLKZEROCTL(x) (((x) & 0xff) << 16) +#define MIPI_DSI_M_TCLKPOSTCTL(x) (((x) & 0xff) << 8) +#define MIPI_DSI_M_TCLKTRAILCTL(x) (((x) & 0xff) << 0) + +#define MIPI_DSI_M_THSPRPRCTL(x) (((x) & 0xff) << 16) +#define MIPI_DSI_M_THSZEROCTL(x) (((x) & 0xff) << 8) +#define MIPI_DSI_M_THSTRAILCTL(x) (((x) & 0xff) << 0) + +#define MIPI_DSI_PLL_STABLE(x) (((x) & 0x1) << 31) +#define MIPI_DSI_TX_READY_HS_CLK(x) (((x) & 0x1) << 10) +#define MIPI_DSI_ULPS_CLK(x) (((x) & 0x1) << 9) +#define MIPI_DSI_STOP_STATE_CLK(x) (((x) & 0x1) << 8) +#define MIPI_DSI_ULPS_DAT(x) (((x) & 0xf) << 4) +#define MIPI_DSI_STOP_STATE_DAT(x) (((x) & 0xf) << 0) + +#define INTSRC_SFR_PL_FIFO_EMPTY (0x1 << 29) +#define INTSRC_SFR_PH_FIFO_EMPTY (0x1 << 28) +#define INTSRC_RX_DATA_DONE (0x1 << 18) +#define INTMSK_SFR_PL_FIFO_EMPTY (0x1 << 29) +#define INTMSK_SFR_PH_FIFO_EMPTY (0x1 << 28) +#define INTMSK_RX_DATA_DONE (0x1 << 18) + +#define MIPI_DSI_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) +#define MIPI_DSI_CMD_LPDT (0x1 << 7) +#define MIPI_DSI_TX_LPDT (0x1 << 6) + +#endif diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 9a43763a68ad..e315691e1ce1 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -255,6 +255,10 @@ struct mmc_supply { struct regulator *vqmmc; /* Optional Vccq supply */ }; +struct mmc_ctx { + struct task_struct *task; +}; + struct mmc_host { struct device *parent; struct device class_dev; @@ -349,6 +353,8 @@ struct mmc_host { #define MMC_CAP2_NO_MMC (1 << 22) /* Do not send (e)MMC commands during initialization */ #define MMC_CAP2_CQE (1 << 23) /* Has eMMC command queue engine */ #define MMC_CAP2_CQE_DCMD (1 << 24) /* CQE can issue a direct command */ +#define MMC_CAP2_CD_POST (1 << 25) /* post card rescan, let client driver to start */ +#define MMC_CAP2_DDR52_3_3V (1 << 26) /* Only supprot eMMC DDR52 at 3.3v */ mmc_pm_flag_t pm_caps; /* supported pm features */ @@ -374,6 +380,7 @@ struct mmc_host { unsigned int doing_retune:1; /* re-tuning in progress */ unsigned int retune_now:1; /* do re-tuning at next req */ unsigned int retune_paused:1; /* re-tuning is temporarily disabled */ + unsigned int use_blk_mq:1; /* use blk-mq */ int rescan_disable; /* disable card detection */ int rescan_entered; /* used with nonremovable devices */ @@ -388,8 +395,9 @@ struct mmc_host { struct mmc_card *card; /* device attached to this host */ wait_queue_head_t wq; - struct task_struct *claimer; /* task that has host claimed */ + struct mmc_ctx *claimer; /* context that has host claimed */ int claim_cnt; /* "claim" nesting count */ + struct mmc_ctx default_ctx; /* default context */ struct delayed_work detect; int detect_change; /* card detect flag */ @@ -469,6 +477,8 @@ void mmc_detect_change(struct mmc_host *, unsigned long delay); void mmc_request_done(struct mmc_host *, struct mmc_request *); void mmc_command_done(struct mmc_host *host, struct mmc_request *mrq); +void mmc_cqe_request_done(struct mmc_host *host, struct mmc_request *mrq); + static inline void mmc_signal_sdio_irq(struct mmc_host *host) { host->ops->enable_sdio_irq(host, 0); diff --git a/include/linux/mmc/pm.h b/include/linux/mmc/pm.h index 4a139204c20c..6e2d6a135c7e 100644 --- a/include/linux/mmc/pm.h +++ b/include/linux/mmc/pm.h @@ -26,5 +26,6 @@ typedef unsigned int mmc_pm_flag_t; #define MMC_PM_KEEP_POWER (1 << 0) /* preserve card power during suspend */ #define MMC_PM_WAKE_SDIO_IRQ (1 << 1) /* wake up host system on SDIO IRQ assertion */ +#define MMC_PM_IGNORE_PM_NOTIFY (1 << 2) /* ignore mmc pm notify */ #endif /* LINUX_MMC_PM_H */ diff --git a/include/linux/mmc/sdio.h b/include/linux/mmc/sdio.h index 17446d3c3602..bbb9c0010cce 100644 --- a/include/linux/mmc/sdio.h +++ b/include/linux/mmc/sdio.h @@ -12,6 +12,8 @@ #ifndef LINUX_MMC_SDIO_H #define LINUX_MMC_SDIO_H +#include <linux/mmc/host.h> + /* SDIO commands type argument response */ #define SD_IO_SEND_OP_COND 5 /* bcr [23:0] OCR R4 */ #define SD_IO_RW_DIRECT 52 /* ac [31:0] See below R5 */ @@ -190,4 +192,6 @@ #define SDIO_FBR_BLKSIZE 0x10 /* block size (2 bytes) */ +void mmc_sdio_force_remove(struct mmc_host *host); + #endif /* LINUX_MMC_SDIO_H */ diff --git a/include/linux/mmc/sdio_ids.h b/include/linux/mmc/sdio_ids.h index 0a7abe8a407f..41cf7eae61de 100644 --- a/include/linux/mmc/sdio_ids.h +++ b/include/linux/mmc/sdio_ids.h @@ -36,12 +36,14 @@ #define SDIO_DEVICE_ID_BROADCOM_4339 0x4339 #define SDIO_DEVICE_ID_BROADCOM_43362 0xa962 #define SDIO_DEVICE_ID_BROADCOM_43364 0xa9a4 +#define SDIO_DEVICE_ID_BROADCOM_43428 0xa9a4 #define SDIO_DEVICE_ID_BROADCOM_43430 0xa9a6 #define SDIO_DEVICE_ID_BROADCOM_4345 0x4345 #define SDIO_DEVICE_ID_BROADCOM_43455 0xa9bf #define SDIO_DEVICE_ID_BROADCOM_4354 0x4354 #define SDIO_DEVICE_ID_BROADCOM_4356 0x4356 #define SDIO_DEVICE_ID_CYPRESS_4373 0x4373 +#define SDIO_DEVICE_ID_CYPRESS_43012 43012 #define SDIO_VENDOR_ID_INTEL 0x0089 #define SDIO_DEVICE_ID_INTEL_IWMC3200WIMAX 0x1402 diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h index 9b57a9b1b081..f56b52e60f43 100644 --- a/include/linux/mtd/cfi.h +++ b/include/linux/mtd/cfi.h @@ -377,6 +377,7 @@ struct cfi_fixup { #define CFI_MFR_SHARP 0x00B0 #define CFI_MFR_SST 0x00BF #define CFI_MFR_ST 0x0020 /* STMicroelectronics */ +#define CFI_MFR_MICRON 0x002C #define CFI_MFR_TOSHIBA 0x0098 #define CFI_MFR_WINBOND 0x00DA diff --git a/include/linux/mtd/map.h b/include/linux/mtd/map.h index 01b990e4b228..9a397595b68c 100644 --- a/include/linux/mtd/map.h +++ b/include/linux/mtd/map.h @@ -446,7 +446,7 @@ static inline void inline_map_copy_from(struct map_info *map, void *to, unsigned if (map->cached) memcpy(to, (char *)map->cached + from, len); else - memcpy_fromio(to, map->virt + from, len); + memcpy(to, map->virt + from, len); } static inline void inline_map_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 1f0a7fc7772f..9c9401c7e1a5 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,6 +24,7 @@ #define SNOR_MFR_GIGADEVICE 0xc8 #define SNOR_MFR_INTEL CFI_MFR_INTEL #define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */ +#define SNOR_MFR_MICRONO CFI_MFR_MICRON /* Original Micron */ #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX #define SNOR_MFR_SPANSION CFI_MFR_AMD #define SNOR_MFR_SST CFI_MFR_SST @@ -69,6 +70,7 @@ #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */ #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */ #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */ +#define SPINOR_OP_READ_1_4_4_D_4B 0xee /* Read data bytes (DDR Quad SPI) */ #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */ #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */ @@ -79,11 +81,13 @@ /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */ #define SPINOR_OP_READ_1_1_1_DTR 0x0d #define SPINOR_OP_READ_1_2_2_DTR 0xbd +#define SPINOR_OP_READ_1_1_4_DTR 0x6d #define SPINOR_OP_READ_1_4_4_DTR 0xed #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee +#define SPINOR_OP_READ_1_8_8_DTR_4B 0x9d /* Used for SST flashes only. */ #define SPINOR_OP_BP 0x02 /* Byte program */ @@ -110,6 +114,8 @@ /* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ +#define SPINOR_OP_RD_VCR 0x85 /* Read VCR register */ +#define SPINOR_OP_WR_VCR 0x81 /* Write VCR register */ /* Status Register bits. */ #define SR_WIP BIT(0) /* Write in progress */ diff --git a/include/linux/mx8_mu.h b/include/linux/mx8_mu.h new file mode 100644 index 000000000000..b31e52693db8 --- /dev/null +++ b/include/linux/mx8_mu.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define MU_ATR0_OFFSET1 0x0 +#define MU_ARR0_OFFSET1 0x10 +#define MU_ASR_OFFSET1 0x20 +#define MU_ACR_OFFSET1 0x24 + +/* Registers offsets of the MU Version 1.0 */ +#define MU_V10_VER_OFFSET1 0x0 +#define MU_V10_ATR0_OFFSET1 0x20 +#define MU_V10_ARR0_OFFSET1 0x40 +#define MU_V10_ASR_OFFSET1 0x60 +#define MU_V10_ACR_OFFSET1 0x64 +#define MU_VER_ID_V10 0x0100 /* Version 1.0 */ + +#define MU_TR_COUNT1 4 +#define MU_RR_COUNT1 4 + +#define MU_CR_GIEn_MASK1 (0xF << 28) +#define MU_CR_RIEn_MASK1 (0xF << 24) +#define MU_CR_TIEn_MASK1 (0xF << 20) +#define MU_CR_GIRn_MASK1 (0xF << 16) +#define MU_CR_NMI_MASK1 (1 << 3) +#define MU_CR_Fn_MASK1 0x7 + +#define MU_SR_TE0_MASK1 (1 << 23) +#define MU_SR_RF0_MASK1 (1 << 27) +#define MU_CR_RIE0_MASK1 (1 << 27) +#define MU_CR_GIE0_MASK1 (1 << 31) + +#define MU_TR_COUNT 4 +#define MU_RR_COUNT 4 + + +void MU_Init(void __iomem *base); +void MU_SendMessage(void __iomem *base, uint32_t regIndex, uint32_t msg); +void MU_SendMessageTimeout(void __iomem *base, uint32_t regIndex, uint32_t msg, uint32_t t); +void MU_ReceiveMsg(void __iomem *base, uint32_t regIndex, uint32_t *msg); +void MU_EnableGeneralInt(void __iomem *base, uint32_t index); +void MU_EnableRxFullInt(void __iomem *base, uint32_t index); +uint32_t MU_ReadStatus(void __iomem *base); +int32_t MU_SetFn(void __iomem *base, uint32_t Fn); + diff --git a/include/linux/mxc_dcic.h b/include/linux/mxc_dcic.h new file mode 100644 index 000000000000..8e330bd466da --- /dev/null +++ b/include/linux/mxc_dcic.h @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @file linux/mxc_dcic.h + * + * @brief Global header file for the MXC DCIC driver + * + * @ingroup MXC DCIC + */ + +#ifndef __LINUX_DCIC_H__ +#define __LINUX_DCIC_H__ + +#include <uapi/linux/mxc_dcic.h> + +#define DCICC_IC_ENABLE 0x1 +#define DCICC_IC_DISABLE 0x0 +#define DCICC_IC_MASK 0x1 +#define DCICC_DE_ACTIVE_HIGH 0 +#define DCICC_DE_ACTIVE_LOW (0x1 << 4) +#define DCICC_DE_ACTIVE_MASK (0x1 << 4) +#define DCICC_HSYNC_POL_ACTIVE_HIGH 0 +#define DCICC_HSYNC_POL_ACTIVE_LOW (0x1 << 5) +#define DCICC_HSYNC_POL_ACTIVE_MASK (0x1 << 5) +#define DCICC_VSYNC_POL_ACTIVE_HIGH 0 +#define DCICC_VSYNC_POL_ACTIVE_LOW (0x1 << 6) +#define DCICC_VSYNC_POL_ACTIVE_MASK (0x1 << 6) +#define DCICC_CLK_POL_NO_INVERTED 0 +#define DCICC_CLK_POL_INVERTED (0x1 << 7) +#define DCICC_CLK_POL_INVERTED_MASK (0x1 << 7) + +#define DCICIC_ERROR_INT_DISABLE 1 +#define DCICIC_ERROR_INT_ENABLE 0 +#define DCICIC_ERROR_INT_MASK_MASK 1 +#define DCICIC_FUN_INT_DISABLE (0x1 << 1) +#define DCICIC_FUN_INT_ENABLE 0 +#define DCICIC_FUN_INT_MASK (0x1 << 1) +#define DCICIC_FREEZE_MASK_CHANGED 0 +#define DCICIC_FREEZE_MASK_FORZEN (0x1 << 3) +#define DCICIC_FREEZE_MASK_MASK (0x1 << 3) +#define DCICIC_EXT_SIG_EX_DISABLE 0 +#define DCICIC_EXT_SIG_EN_ENABLE (0x1 << 16) +#define DCICIC_EXT_SIG_EN_MASK (0x1 << 16) + +#define DCICS_ROI_MATCH_STAT_MASK 0xFFFF +#define DCICS_EI_STAT_PENDING (0x1 << 16) +#define DCICS_EI_STAT_NO_PENDING 0 +#define DCICS_FI_STAT_PENDING (0x1 << 17) +#define DCICS_FI_STAT_NO_PENDING 0 + +#define DCICRC_ROI_START_OFFSET_X_MASK 0x1FFF +#define DCICRC_ROI_START_OFFSET_X_SHIFT 0 +#define DCICRC_ROI_START_OFFSET_Y_MASK (0xFFF << 16) +#define DCICRC_ROI_START_OFFSET_Y_SHIFT 16 +#define DCICRC_ROI_CHANGED 0 +#define DCICRC_ROI_FROZEN (0x1 << 30) +#define DCICRC_ROI_ENABLE (0x1 << 31) +#define DCICRC_ROI_DISABLE 0 + +#define DCICRS_ROI_END_OFFSET_X_MASK 0x1FFF +#define DCICRS_ROI_END_OFFSET_X_SHIFT 0 +#define DCICRS_ROI_END_OFFSET_Y_MASK (0xFFF << 16) +#define DCICRS_ROI_END_OFFSET_Y_SHIFT 16 + +struct roi_regs { + u32 dcicrc; + u32 dcicrs; + u32 dcicrrs; + u32 dcicrcs; +}; + +struct dcic_regs { + u32 dcicc; + u32 dcicic; + u32 dcics; + u32 dcic_reserved; + struct roi_regs ROI[16]; +}; + +struct dcic_mux { + char dcic[16]; + u32 val; +}; + +struct bus_mux { + char name[16]; + int reg; + int shift; + int mask; + int dcic_mux_num; + const struct dcic_mux *dcics; +}; + +struct dcic_info { + int bus_mux_num; + const struct bus_mux *buses; +}; + +struct dcic_data { + struct regmap *regmap; + struct device *dev; + struct dcic_regs *regs; + const struct bus_mux *buses; + u32 bus_n; + u32 mux_n; + struct clk *disp_axi_clk; + struct clk *dcic_clk; + struct mutex lock; + struct completion roi_crc_comp; + struct class *class; + int major; + struct cdev cdev; /* Char device structure */ + dev_t devt; + unsigned int result; +}; +#endif diff --git a/include/linux/mxc_mlb.h b/include/linux/mxc_mlb.h new file mode 100644 index 000000000000..d7c792a2bee4 --- /dev/null +++ b/include/linux/mxc_mlb.h @@ -0,0 +1,55 @@ +/* + * mxc_mlb.h + * + * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _MXC_MLB_H +#define _MXC_MLB_H + +/* define IOCTL command */ +#define MLB_DBG_RUNTIME _IO('S', 0x09) +#define MLB_SET_FPS _IOW('S', 0x10, unsigned int) +#define MLB_GET_VER _IOR('S', 0x11, unsigned long) +#define MLB_SET_DEVADDR _IOR('S', 0x12, unsigned char) + +/*! + * set channel address for each logical channel + * the MSB 16bits is for tx channel, the left LSB is for rx channel + */ +#define MLB_CHAN_SETADDR _IOW('S', 0x13, unsigned int) +#define MLB_CHAN_STARTUP _IO('S', 0x14) +#define MLB_CHAN_SHUTDOWN _IO('S', 0x15) +#define MLB_CHAN_GETEVENT _IOR('S', 0x16, unsigned long) + +#define MLB_SET_ISOC_BLKSIZE_188 _IO('S', 0x17) +#define MLB_SET_ISOC_BLKSIZE_196 _IO('S', 0x18) +#define MLB_SET_SYNC_QUAD _IOW('S', 0x19, unsigned int) +#define MLB_IRQ_ENABLE _IO('S', 0x20) +#define MLB_IRQ_DISABLE _IO('S', 0x21) + +/*! + * MLB event define + */ +enum { + MLB_EVT_TX_PROTO_ERR_CUR = 1 << 0, + MLB_EVT_TX_BRK_DETECT_CUR = 1 << 1, + MLB_EVT_TX_PROTO_ERR_PREV = 1 << 8, + MLB_EVT_TX_BRK_DETECT_PREV = 1 << 9, + MLB_EVT_RX_PROTO_ERR_CUR = 1 << 16, + MLB_EVT_RX_BRK_DETECT_CUR = 1 << 17, + MLB_EVT_RX_PROTO_ERR_PREV = 1 << 24, + MLB_EVT_RX_BRK_DETECT_PREV = 1 << 25, +}; + + +#endif /* _MXC_MLB_H */ diff --git a/include/linux/mxc_sim_interface.h b/include/linux/mxc_sim_interface.h new file mode 100644 index 000000000000..5eae53a59075 --- /dev/null +++ b/include/linux/mxc_sim_interface.h @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef MXC_SIM_INTERFACE_H +#define MXC_SIM_INTERFACE_H + +#define SIM_ATR_LENGTH_MAX 32 + +/* Raw ATR SIM_IOCTL_GET_ATR */ +typedef struct { + unsigned int size;/* length of ATR received */ + unsigned char *atr_buffer;/* raw ATR string received */ + int errval;/* The error vale reported to user space after completing ATR*/ +} sim_atr_t; + +/* ISO7816-3 protocols */ +#define SIM_PROTOCOL_T0 1 +#define SIM_PROTOCOL_T1 2 + +/* Transfer types for SIM_IOCTL_XFER */ +#define SIM_XFER_TYPE_TPDU 1 +#define SIM_XFER_TYPE_PTS 2 + +typedef struct { + unsigned int wwt; + unsigned int cwt; + unsigned int bwt; + unsigned int bgt; + unsigned int cgt; +} sim_timing_t; + +/* Transfer data for SIM_IOCTL_XFER */ +typedef struct { + unsigned char *xmt_buffer; /* transmit buffer pointer */ + int xmt_length;/* transmit buffer length */ + int timeout;/* transfer timeout in milliseconds */ + int errval;/* The error vale reported to user space after completing transmitting*/ +} sim_xmt_t; + +typedef struct { + unsigned char *rcv_buffer; /* receive buffer pointer */ + int rcv_length; /* receive buffer length */ + int timeout;/* transfer timeout in milliseconds */ + int errval;/* The error vale reported to user space after receiving*/ +} sim_rcv_t; + +typedef struct { + unsigned char di; + unsigned char fi; +} sim_baud_t; + +/* Interface power states */ +#define SIM_POWER_OFF (0) +#define SIM_POWER_ON (1) + +/* Return values for SIM_IOCTL_GET_PRESENSE */ +#define SIM_PRESENT_REMOVED (0) +#define SIM_PRESENT_DETECTED (1) +#define SIM_PRESENT_OPERATIONAL (2) + +/* The error value */ +#define SIM_OK (0) +#define SIM_ERROR_CWT (1 << 0) +#define SIM_ERROR_BWT (1 << 1) +#define SIM_ERROR_PARITY (1 << 2) +#define SIM_ERROR_INVALID_TS (1 << 3) +#define SIM_ERROR_FRAME (1 << 4) +#define SIM_ERROR_ATR_TIMEROUT (1 << 5) +#define SIM_ERROR_NACK_THRESHOLD (1 << 6) +#define SIM_ERROR_BGT (1 << 7) +#define SIM_ERROR_ATR_DELAY (1 << 8) + +/* Return values for SIM_IOCTL_GET_ERROR */ +#define SIM_E_ACCESS (1) +#define SIM_E_TPDUSHORT (2) +#define SIM_E_PTSEMPTY (3) +#define SIM_E_INVALIDXFERTYPE (4) +#define SIM_E_INVALIDXMTLENGTH (5) +#define SIM_E_INVALIDRCVLENGTH (6) +#define SIM_E_NACK (7) +#define SIM_E_TIMEOUT (8) +#define SIM_E_NOCARD (9) +#define SIM_E_PARAM_FI_INVALID (10) +#define SIM_E_PARAM_DI_INVALID (11) +#define SIM_E_PARAM_FBYD_WITHFRACTION (12) +#define SIM_E_PARAM_FBYD_NOTDIVBY8OR12 (13) +#define SIM_E_PARAM_DIVISOR_RANGE (14) +#define SIM_E_MALLOC (15) +#define SIM_E_IRQ (16) +#define SIM_E_POWERED_ON (17) +#define SIM_E_POWERED_OFF (18) + +/* ioctl encodings */ +#define SIM_IOCTL_BASE (0xc0) +#define SIM_IOCTL_GET_PRESENSE _IOR(SIM_IOCTL_BASE, 1, int) +#define SIM_IOCTL_GET_ATR _IOR(SIM_IOCTL_BASE, 2, sim_atr_t) +#define SIM_IOCTL_XMT _IOR(SIM_IOCTL_BASE, 3, sim_xmt_t) +#define SIM_IOCTL_RCV _IOR(SIM_IOCTL_BASE, 4, sim_rcv_t) +#define SIM_IOCTL_ACTIVATE _IO(SIM_IOCTL_BASE, 5) +#define SIM_IOCTL_DEACTIVATE _IO(SIM_IOCTL_BASE, 6) +#define SIM_IOCTL_WARM_RESET _IO(SIM_IOCTL_BASE, 7) +#define SIM_IOCTL_COLD_RESET _IO(SIM_IOCTL_BASE, 8) +#define SIM_IOCTL_CARD_LOCK _IO(SIM_IOCTL_BASE, 9) +#define SIM_IOCTL_CARD_EJECT _IO(SIM_IOCTL_BASE, 10) +#define SIM_IOCTL_SET_PROTOCOL _IOR(SIM_IOCTL_BASE, 11, unsigned int) +#define SIM_IOCTL_SET_TIMING _IOR(SIM_IOCTL_BASE, 12, sim_timing_t) +#define SIM_IOCTL_SET_BAUD _IOR(SIM_IOCTL_BASE, 13, sim_baud_t) +#define SIM_IOCTL_WAIT _IOR(SIM_IOCTL_BASE, 14, unsigned int) + +#endif diff --git a/include/linux/mxc_v4l2.h b/include/linux/mxc_v4l2.h new file mode 100644 index 000000000000..6d778e83ef53 --- /dev/null +++ b/include/linux/mxc_v4l2.h @@ -0,0 +1,27 @@ +/* + * Copyright 2004-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @file linux/mxc_v4l2.h + * + * @brief MXC V4L2 private header file + * + * @ingroup MXC V4L2 + */ + +#ifndef __LINUX_MXC_V4L2_H__ +#define __LINUX_MXC_V4L2_H__ + +#include <uapi/linux/mxc_v4l2.h> + +#endif diff --git a/include/linux/mxc_vpu-malone.h b/include/linux/mxc_vpu-malone.h new file mode 100755 index 000000000000..4541c8733124 --- /dev/null +++ b/include/linux/mxc_vpu-malone.h @@ -0,0 +1,49 @@ +/* + * Copyright 2017 NXP + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup VPU Video Processor Unit Driver + */ + +/*! + * @file linux/mxc_vpu-malone.h + * + * @brief VPU system initialization and file operation definition + * + * @ingroup VPU + */ + +#ifndef __LINUX_MXC_VPU_MALONE_H__ +#define __LINUX_MXC_VPU_MALONE_H__ + +#include <linux/fs.h> + +struct vpu_mem_desc { + u32 size; + dma_addr_t phy_addr; + void *cpu_addr; /* cpu address to free the dma mem */ + u64 virt_uaddr; /* virtual user space address */ +}; + +#define VPU_IOC_MAGIC 'V' + +#define VPU_IOC_PHYMEM_ALLOC _IO(VPU_IOC_MAGIC, 0) +#define VPU_IOC_PHYMEM_FREE _IO(VPU_IOC_MAGIC, 1) +#define VPU_IOC_WAIT4INT _IO(VPU_IOC_MAGIC, 2) +#define VPU_IOC_CLKGATE_SETTING _IO(VPU_IOC_MAGIC, 3) +#define VPU_IOC_REQ_VSHARE_MEM _IO(VPU_IOC_MAGIC, 4) +#define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 5) +#define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 6) +#define VPU_IOC_LOCK_DEV _IO(VPU_IOC_MAGIC, 7) + +#endif diff --git a/include/linux/mxc_vpu.h b/include/linux/mxc_vpu.h new file mode 100644 index 000000000000..df024698dee7 --- /dev/null +++ b/include/linux/mxc_vpu.h @@ -0,0 +1,118 @@ +/* + * Copyright 2004-2013, 2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @defgroup VPU Video Processor Unit Driver + */ + +/*! + * @file linux/mxc_vpu.h + * + * @brief VPU system initialization and file operation definition + * + * @ingroup VPU + */ + +#ifndef __LINUX_MXC_VPU_H__ +#define __LINUX_MXC_VPU_H__ + +#include <linux/fs.h> + +struct mxc_vpu_platform_data { + bool iram_enable; + int iram_size; + void (*reset) (void); + void (*pg) (int); +}; + +struct vpu_mem_desc { + u32 size; + dma_addr_t phy_addr; + u32 cpu_addr; /* cpu address to free the dma mem */ + u32 virt_uaddr; /* virtual user space address */ +}; + +#define VPU_IOC_MAGIC 'V' + +#define VPU_IOC_PHYMEM_ALLOC _IO(VPU_IOC_MAGIC, 0) +#define VPU_IOC_PHYMEM_FREE _IO(VPU_IOC_MAGIC, 1) +#define VPU_IOC_WAIT4INT _IO(VPU_IOC_MAGIC, 2) +#define VPU_IOC_PHYMEM_DUMP _IO(VPU_IOC_MAGIC, 3) +#define VPU_IOC_REG_DUMP _IO(VPU_IOC_MAGIC, 4) +#define VPU_IOC_IRAM_SETTING _IO(VPU_IOC_MAGIC, 6) +#define VPU_IOC_CLKGATE_SETTING _IO(VPU_IOC_MAGIC, 7) +#define VPU_IOC_GET_WORK_ADDR _IO(VPU_IOC_MAGIC, 8) +#define VPU_IOC_REQ_VSHARE_MEM _IO(VPU_IOC_MAGIC, 9) +#define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 11) +#define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 12) +#define VPU_IOC_QUERY_BITWORK_MEM _IO(VPU_IOC_MAGIC, 13) +#define VPU_IOC_SET_BITWORK_MEM _IO(VPU_IOC_MAGIC, 14) +#define VPU_IOC_PHYMEM_CHECK _IO(VPU_IOC_MAGIC, 15) +#define VPU_IOC_LOCK_DEV _IO(VPU_IOC_MAGIC, 16) + +#define BIT_CODE_RUN 0x000 +#define BIT_CODE_DOWN 0x004 +#define BIT_INT_CLEAR 0x00C +#define BIT_INT_STATUS 0x010 +#define BIT_CUR_PC 0x018 +#define BIT_INT_REASON 0x174 + +#define MJPEG_PIC_STATUS_REG 0x3004 +#define MBC_SET_SUBBLK_EN 0x4A0 + +#define BIT_WORK_CTRL_BUF_BASE 0x100 +#define BIT_WORK_CTRL_BUF_REG(i) (BIT_WORK_CTRL_BUF_BASE + i * 4) +#define BIT_CODE_BUF_ADDR BIT_WORK_CTRL_BUF_REG(0) +#define BIT_WORK_BUF_ADDR BIT_WORK_CTRL_BUF_REG(1) +#define BIT_PARA_BUF_ADDR BIT_WORK_CTRL_BUF_REG(2) +#define BIT_BIT_STREAM_CTRL BIT_WORK_CTRL_BUF_REG(3) +#define BIT_FRAME_MEM_CTRL BIT_WORK_CTRL_BUF_REG(4) +#define BIT_BIT_STREAM_PARAM BIT_WORK_CTRL_BUF_REG(5) + +#ifndef CONFIG_SOC_IMX6Q +#define BIT_RESET_CTRL 0x11C +#else +#define BIT_RESET_CTRL 0x128 +#endif + +/* i could be 0, 1, 2, 3 */ +#define BIT_RD_PTR_BASE 0x120 +#define BIT_RD_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8) +#define BIT_WR_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8 + 4) + +/* i could be 0, 1, 2, 3 */ +#define BIT_FRM_DIS_FLG_BASE (cpu_is_mx51() ? 0x150 : 0x140) +#define BIT_FRM_DIS_FLG_REG(i) (BIT_FRM_DIS_FLG_BASE + i * 4) + +#define BIT_BUSY_FLAG 0x160 +#define BIT_RUN_COMMAND 0x164 +#define BIT_INT_ENABLE 0x170 + +#define BITVAL_PIC_RUN 8 + +#define VPU_SLEEP_REG_VALUE 10 +#define VPU_WAKE_REG_VALUE 11 + +int vl2cc_init(u32 vl2cc_hw_base); +void vl2cc_enable(void); +void vl2cc_flush(void); +void vl2cc_disable(void); +void vl2cc_cleanup(void); + +int vl2cc_init(u32 vl2cc_hw_base); +void vl2cc_enable(void); +void vl2cc_flush(void); +void vl2cc_disable(void); +void vl2cc_cleanup(void); + +#endif diff --git a/include/linux/mxcfb.h b/include/linux/mxcfb.h new file mode 100644 index 000000000000..67db5ee3fd11 --- /dev/null +++ b/include/linux/mxcfb.h @@ -0,0 +1,46 @@ +/* + * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/* + * @file linux/mxcfb.h + * + * @brief Global header file for the MXC Frame buffer + * + * @ingroup Framebuffer + */ +#ifndef __LINUX_MXCFB_H__ +#define __LINUX_MXCFB_H__ + +#include <uapi/linux/mxcfb.h> + +extern struct fb_videomode mxcfb_modedb[]; +extern int mxcfb_modedb_sz; + +enum { + MXC_DISP_SPEC_DEV = 0, + MXC_DISP_DDC_DEV = 1, +}; + +enum { + MXCFB_REFRESH_OFF, + MXCFB_REFRESH_AUTO, + MXCFB_REFRESH_PARTIAL, +}; + +int mxcfb_set_refresh_mode(struct fb_info *fbi, int mode, + struct mxcfb_rect *update_region); +int mxc_elcdif_frame_addr_setup(dma_addr_t phys); +void mxcfb_elcdif_register_mode(const struct fb_videomode *modedb, + int num_modes, int dev_mode); + +#endif diff --git a/include/linux/mxcfb_epdc.h b/include/linux/mxcfb_epdc.h new file mode 100644 index 000000000000..35a8b83b22d3 --- /dev/null +++ b/include/linux/mxcfb_epdc.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef _MXCFB_EPDC_KERNEL +#define _MXCFB_EPDC_KERNEL + +struct imx_epdc_fb_mode { + struct fb_videomode *vmode; + int vscan_holdoff; + int sdoed_width; + int sdoed_delay; + int sdoez_width; + int sdoez_delay; + int gdclk_hp_offs; + int gdsp_offs; + int gdoe_offs; + int gdclk_offs; + int num_ce; +}; + +struct imx_epdc_fb_platform_data { + struct imx_epdc_fb_mode *epdc_mode; + int num_modes; + int (*get_pins) (void); + void (*put_pins) (void); + void (*enable_pins) (void); + void (*disable_pins) (void); +}; + +#endif diff --git a/include/linux/of.h b/include/linux/of.h index 70b7dacf9238..d4e1745a1d2e 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -384,6 +384,7 @@ extern int of_phandle_iterator_args(struct of_phandle_iterator *it, extern void of_alias_scan(void * (*dt_alloc)(u64 size, u64 align)); extern int of_alias_get_id(struct device_node *np, const char *stem); extern int of_alias_get_highest_id(const char *stem); +extern int of_alias_max_index(const char *stem); extern int of_machine_is_compatible(const char *compat); @@ -826,6 +827,11 @@ static inline int of_alias_get_highest_id(const char *stem) return -ENOSYS; } +static inline int of_alias_max_index(const char *stem) +{ + return -ENODEV; +} + static inline int of_machine_is_compatible(const char *compat) { return 0; diff --git a/include/linux/of_reserved_mem.h b/include/linux/of_reserved_mem.h index bb4fda7317be..2a37f8490ea0 100644 --- a/include/linux/of_reserved_mem.h +++ b/include/linux/of_reserved_mem.h @@ -35,13 +35,13 @@ int of_reserved_mem_device_init_by_idx(struct device *dev, struct device_node *np, int idx); void of_reserved_mem_device_release(struct device *dev); -int early_init_dt_alloc_reserved_memory_arch(phys_addr_t size, +int early_init_dt_alloc_reserved_memory_arch(unsigned long node, + phys_addr_t size, phys_addr_t align, phys_addr_t start, phys_addr_t end, bool nomap, phys_addr_t *res_base); - void fdt_init_reserved_mem(void); void fdt_reserved_mem_save_node(unsigned long node, const char *uname, phys_addr_t base, phys_addr_t size); diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h index 809c2f1873ac..36c9ddbb6d30 100644 --- a/include/linux/pci-ecam.h +++ b/include/linux/pci-ecam.h @@ -73,5 +73,6 @@ extern struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */ /* for DT-based PCI controllers that support ECAM */ int pci_host_common_probe(struct platform_device *pdev, struct pci_ecam_ops *ops); +int pci_host_common_remove(struct platform_device *pdev); #endif #endif diff --git a/include/linux/pci.h b/include/linux/pci.h index b1abbcc614cf..103728bac8d1 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1523,12 +1523,10 @@ void pci_cfg_access_unlock(struct pci_dev *dev); */ #ifdef CONFIG_PCI_DOMAINS extern int pci_domains_supported; -int pci_get_new_domain_nr(void); #else enum { pci_domains_supported = 0 }; static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } -static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } #endif /* CONFIG_PCI_DOMAINS */ /* @@ -1684,7 +1682,6 @@ static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } -static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } #define dev_is_pci(d) (false) #define dev_is_pf(d) (false) diff --git a/include/linux/phy.h b/include/linux/phy.h index efc04c2d92c9..16caed3a7f8a 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -867,6 +867,7 @@ void phy_attached_info(struct phy_device *phydev); int genphy_config_init(struct phy_device *phydev); int genphy_setup_forced(struct phy_device *phydev); int genphy_restart_aneg(struct phy_device *phydev); +int genphy_config_aneg_check(struct phy_device *phydev); int genphy_config_aneg(struct phy_device *phydev); int genphy_aneg_done(struct phy_device *phydev); int genphy_update_link(struct phy_device *phydev); diff --git a/include/linux/phy/phy-mixel-lvds-combo.h b/include/linux/phy/phy-mixel-lvds-combo.h new file mode 100644 index 000000000000..9eac98c42829 --- /dev/null +++ b/include/linux/phy/phy-mixel-lvds-combo.h @@ -0,0 +1,38 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef PHY_MIXEL_LVDS_COMBO_H_ +#define PHY_MIXEL_LVDS_COMBO_H_ + +#include "phy.h" + +#if IS_ENABLED(CONFIG_PHY_MIXEL_LVDS_COMBO) +void mixel_phy_combo_lvds_set_phy_speed(struct phy *phy, + unsigned long phy_clk_rate); +void mixel_phy_combo_lvds_set_hsync_pol(struct phy *phy, bool active_high); +void mixel_phy_combo_lvds_set_vsync_pol(struct phy *phy, bool active_high); +#else +void mixel_phy_combo_lvds_set_phy_speed(struct phy *phy, + unsigned long phy_clk_rate) +{ +} +void mixel_phy_combo_lvds_set_hsync_pol(struct phy *phy, bool active_high) +{ +} +void mixel_phy_combo_lvds_set_vsync_pol(struct phy *phy, bool active_high) +{ +} +#endif + +#endif /* PHY_MIXEL_LVDS_COMBO_H_ */ diff --git a/include/linux/phy/phy-mixel-lvds.h b/include/linux/phy/phy-mixel-lvds.h new file mode 100644 index 000000000000..3540857b7a65 --- /dev/null +++ b/include/linux/phy/phy-mixel-lvds.h @@ -0,0 +1,36 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef PHY_MIXEL_LVDS_H_ +#define PHY_MIXEL_LVDS_H_ + +#include "phy.h" + +#if IS_ENABLED(CONFIG_PHY_MIXEL_LVDS) +void mixel_phy_lvds_set_phy_speed(struct phy *phy, unsigned long phy_clk_rate); +void mixel_phy_lvds_set_hsync_pol(struct phy *phy, bool active_high); +void mixel_phy_lvds_set_vsync_pol(struct phy *phy, bool active_high); +#else +void mixel_phy_lvds_set_phy_speed(struct phy *phy, unsigned long phy_clk_rate) +{ +} +void mixel_phy_lvds_set_hsync_pol(struct phy *phy, bool active_high) +{ +} +void mixel_phy_lvds_set_vsync_pol(struct phy *phy, bool active_high) +{ +} +#endif + +#endif /* PHY_MIXEL_LVDS_H_ */ diff --git a/include/linux/phy/phy-mixel-mipi-dsi.h b/include/linux/phy/phy-mixel-mipi-dsi.h new file mode 100644 index 000000000000..a76eea4d2704 --- /dev/null +++ b/include/linux/phy/phy-mixel-mipi-dsi.h @@ -0,0 +1,35 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef PHY_MIXEL_MIPI_DSI_H_ +#define PHY_MIXEL_MIPI_DSI_H_ + +#include "phy.h" + +#if IS_ENABLED(CONFIG_PHY_MIXEL_MIPI_DSI) +int mixel_phy_mipi_set_phy_speed(struct phy *phy, + unsigned long bit_clk, + unsigned long ref_clk, + bool best_match); +#else +int mixel_phy_mipi_set_phy_speed(struct phy *phy, + unsigned long bit_clk, + unsigned long ref_clk, + bool best_match) +{ + return -ENODEV; +} +#endif + +#endif /* PHY_MIXEL_MIPI_DSI_H_ */ diff --git a/include/linux/platform_data/brcmfmac.h b/include/linux/platform_data/brcmfmac.h index 1d30bf278231..b737c0a8e58d 100644 --- a/include/linux/platform_data/brcmfmac.h +++ b/include/linux/platform_data/brcmfmac.h @@ -178,6 +178,7 @@ struct brcmfmac_platform_data { void (*power_off)(void); char *fw_alternative_path; int device_count; + struct device *dev; struct brcmfmac_pd_device devices[0]; }; diff --git a/include/linux/platform_data/dma-imx-sdma.h b/include/linux/platform_data/dma-imx-sdma.h index 6eaa53cef0bd..da06645bea80 100644 --- a/include/linux/platform_data/dma-imx-sdma.h +++ b/include/linux/platform_data/dma-imx-sdma.h @@ -51,7 +51,12 @@ struct sdma_script_start_addrs { /* End of v2 array */ s32 zcanfd_2_mcu_addr; s32 zqspi_2_mcu_addr; + s32 mcu_2_ecspi_addr; + s32 mcu_2_sai_addr; + s32 sai_2_mcu_addr; /* End of v3 array */ + s32 mcu_2_zqspi_addr; + /* End of v4 array */ }; /** diff --git a/include/linux/platform_data/dma-imx.h b/include/linux/platform_data/dma-imx.h index 7d964e787299..59e34a321da4 100644 --- a/include/linux/platform_data/dma-imx.h +++ b/include/linux/platform_data/dma-imx.h @@ -1,5 +1,6 @@ /* - * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2018 NXP. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -42,6 +43,8 @@ enum sdma_peripheral_type { IMX_DMATYPE_SSI_DUAL, /* SSI Dual FIFO */ IMX_DMATYPE_ASRC_SP, /* Shared ASRC */ IMX_DMATYPE_SAI, /* SAI */ + IMX_DMATYPE_HDMI, /* HDMI Audio */ + IMX_DMATYPE_MULTI_SAI, /* MULTI FIFOs For Audio */ }; enum imx_dma_prio { @@ -55,6 +58,10 @@ struct imx_dma_data { int dma_request2; /* secondary DMA request line */ enum sdma_peripheral_type peripheral_type; int priority; + bool src_dualfifo; + bool dst_dualfifo; + int idx; + int done_sel; }; static inline int imx_dma_is_ipu(struct dma_chan *chan) @@ -62,6 +69,11 @@ static inline int imx_dma_is_ipu(struct dma_chan *chan) return !strcmp(dev_name(chan->device->dev), "ipu-core"); } +static inline int imx_dma_is_pxp(struct dma_chan *chan) +{ + return strstr(dev_name(chan->device->dev), "pxp") != NULL; +} + static inline int imx_dma_is_general_purpose(struct dma_chan *chan) { return !strcmp(chan->device->dev->driver->name, "imx-sdma") || diff --git a/include/linux/platform_data/mmc-esdhc-imx.h b/include/linux/platform_data/mmc-esdhc-imx.h index 7daa78a2f342..9888c868423b 100644 --- a/include/linux/platform_data/mmc-esdhc-imx.h +++ b/include/linux/platform_data/mmc-esdhc-imx.h @@ -34,7 +34,6 @@ enum cd_types { * @cd_gpio: gpio for card_detect interrupt * @wp_type: type of write_protect method (see wp_types enum above) * @cd_type: type of card_detect method (see cd_types enum above) - * @support_vsel: indicate it supports 1.8v switching */ struct esdhc_platform_data { @@ -43,9 +42,9 @@ struct esdhc_platform_data { enum wp_types wp_type; enum cd_types cd_type; int max_bus_width; - bool support_vsel; unsigned int delay_line; unsigned int tuning_step; /* The delay cell steps in tuning procedure */ unsigned int tuning_start_tap; /* The start delay cell point in tuning procedure */ + unsigned int strobe_dll_delay_target; /* The delay cell for strobe pad (read clock) */ }; #endif /* __ASM_ARCH_IMX_ESDHC_H */ diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h index 84f423d5633e..49e92073517c 100644 --- a/include/linux/pm_domain.h +++ b/include/linux/pm_domain.h @@ -90,6 +90,7 @@ struct generic_pm_domain { }; }; + unsigned int state_idx_saved; /* saved power state for recovery after system suspend/resume */ }; static inline struct generic_pm_domain *pd_to_genpd(struct dev_pm_domain *pd) @@ -233,6 +234,8 @@ extern int of_genpd_parse_idle_states(struct device_node *dn, struct genpd_power_state **states, int *n); int genpd_dev_pm_attach(struct device *dev); +struct generic_pm_domain *genpd_get_from_provider( + struct of_phandle_args *genpdspec); #else /* !CONFIG_PM_GENERIC_DOMAINS_OF */ static inline int of_genpd_add_provider_simple(struct device_node *np, struct generic_pm_domain *genpd) @@ -276,6 +279,13 @@ struct generic_pm_domain *of_genpd_remove_last(struct device_node *np) { return ERR_PTR(-ENOTSUPP); } + +static inline +struct generic_pm_domain *genpd_get_from_provider( + struct of_phandle_args *genpdspec) +{ + return ERR_PTR(-ENOTSUPP); +} #endif /* CONFIG_PM_GENERIC_DOMAINS_OF */ #ifdef CONFIG_PM diff --git a/include/linux/pmic_status.h b/include/linux/pmic_status.h new file mode 100644 index 000000000000..a127c7117e13 --- /dev/null +++ b/include/linux/pmic_status.h @@ -0,0 +1,82 @@ +/* + * Copyright 2004-2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ +#ifndef __ASM_ARCH_MXC_PMIC_STATUS_H__ +#define __ASM_ARCH_MXC_PMIC_STATUS_H__ +#include <asm-generic/errno-base.h> +#ifdef __KERNEL__ +#include <asm/uaccess.h> /* copy_{from,to}_user() */ +#endif +/*! + * @file arch-mxc/pmic_status.h + * @brief PMIC APIs return code definition. + * + * @ingroup PMIC_CORE + */ + +/*! + * @enum PMIC_STATUS + * @brief Define return values for all PMIC APIs. + * + * These return values are used by all of the PMIC APIs. + * + * @ingroup PMIC + */ +typedef enum { + PMIC_SUCCESS = 0, /*!< The requested operation was successfully + completed. */ + PMIC_ERROR = -1, /*!< The requested operation could not be completed + due to an error. */ + PMIC_PARAMETER_ERROR = -2, /*!< The requested operation failed because + one or more of the parameters was + invalid. */ + PMIC_NOT_SUPPORTED = -3, /*!< The requested operation could not be + completed because the PMIC hardware + does not support it. */ + PMIC_SYSTEM_ERROR_EINTR = -EINTR, + + PMIC_MALLOC_ERROR = -5, /*!< Error in malloc function */ + PMIC_UNSUBSCRIBE_ERROR = -6, /*!< Error in un-subscribe event */ + PMIC_EVENT_NOT_SUBSCRIBED = -7, /*!< Event occur and not subscribed */ + PMIC_EVENT_CALL_BACK = -8, /*!< Error - bad call back */ + PMIC_CLIENT_NBOVERFLOW = -9, /*!< The requested operation could not be + completed because there are too many + PMIC client requests */ +} PMIC_STATUS; + +/* + * Bitfield macros that use rely on bitfield width/shift information. + */ +#define BITFMASK(field) (((1U << (field ## _WID)) - 1) << (field ## _LSH)) +#define BITFVAL(field, val) ((val) << (field ## _LSH)) +#define BITFEXT(var, bit) ((var & BITFMASK(bit)) >> (bit ## _LSH)) + +/* + * Macros implementing error handling + */ +#define CHECK_ERROR(a) \ +do { \ + int ret = (a); \ + if (ret != PMIC_SUCCESS) \ + return ret; \ +} while (0) + +#define CHECK_ERROR_KFREE(func, freeptrs) \ +do { \ + int ret = (func); \ + if (ret != PMIC_SUCCESS) { \ + freeptrs; \ + return ret; \ + } \ +} while (0); + +#endif /* __ASM_ARCH_MXC_PMIC_STATUS_H__ */ diff --git a/include/linux/power/sabresd_battery.h b/include/linux/power/sabresd_battery.h new file mode 100644 index 000000000000..10bfa4588864 --- /dev/null +++ b/include/linux/power/sabresd_battery.h @@ -0,0 +1,65 @@ +/* + * sabresd_battery.h - Maxim 8903 USB/Adapter Charger Driver + * + * Copyright (C) 2011 Samsung Electronics + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. + * Based on max8903_charger.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MAX8903_SABRESD_H__ +#define __MAX8903_SABRESD_H__ + +struct max8903_pdata { + /* + * GPIOs + * cen, chg, flt, and usus are optional. + * dok, dcm, and uok are not optional depending on the status of + * dc_valid and usb_valid. + */ + int cen; /* Charger Enable input */ + int dok; /* DC(Adapter) Power OK output */ + int uok; /* USB Power OK output */ + int chg; /* Charger status output */ + int flt; /* Fault output */ + int dcm; /* Current-Limit Mode input (1: DC, 2: USB) */ + int usus; /* USB Suspend Input (1: suspended) */ + int feature_flag;/* battery capacity feature(0:enable, 1:disable) */ + + /* + * DCM wired to Logic High Set this true when DCM pin connect to + * Logic high. + */ + bool dcm_always_high; + + /* + * DC(Adapter/TA) is wired + * When dc_valid is true, + * dok and dcm should be valid. + * + * At least one of dc_valid or usb_valid should be true. + */ + bool dc_valid; + /* + * USB is wired + * When usb_valid is true, + * uok should be valid. + */ + bool usb_valid; +}; + +#endif /* __SABRESD_BATTERY_H__ */ diff --git a/include/linux/pwm_backlight.h b/include/linux/pwm_backlight.h index e8afbd71a140..cac4d427cde4 100644 --- a/include/linux/pwm_backlight.h +++ b/include/linux/pwm_backlight.h @@ -21,6 +21,7 @@ struct platform_pwm_backlight_data { void (*notify_after)(struct device *dev, int brightness); void (*exit)(struct device *dev); int (*check_fb)(struct device *dev, struct fb_info *info); + char fb_id[16]; }; #endif diff --git a/include/linux/pxp_device.h b/include/linux/pxp_device.h new file mode 100644 index 000000000000..df185c49d017 --- /dev/null +++ b/include/linux/pxp_device.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef _PXP_DEVICE +#define _PXP_DEVICE + +#include <linux/idr.h> +#include <linux/hash.h> +#include <uapi/linux/pxp_device.h> + +struct pxp_irq_info { + wait_queue_head_t waitq; + atomic_t irq_pending; + int hist_status; +}; + +struct pxp_buffer_hash { + struct hlist_head *hash_table; + u32 order; + spinlock_t hash_lock; +}; + +struct pxp_buf_obj { + uint32_t handle; + + uint32_t size; + uint32_t mem_type; + + unsigned long offset; + void *virtual; + + struct hlist_node item; +}; + +struct pxp_chan_obj { + uint32_t handle; + struct dma_chan *chan; +}; + +/* File private data */ +struct pxp_file { + struct file *filp; + + /* record allocated dma buffer */ + struct idr buffer_idr; + spinlock_t buffer_lock; + + /* record allocated dma channel */ + struct idr channel_idr; + spinlock_t channel_lock; +}; + +#endif diff --git a/include/linux/pxp_dma.h b/include/linux/pxp_dma.h new file mode 100644 index 000000000000..a48871caebfc --- /dev/null +++ b/include/linux/pxp_dma.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef _PXP_DMA +#define _PXP_DMA + +#include <uapi/linux/pxp_dma.h> + +struct pxp_tx_desc { + struct dma_async_tx_descriptor txd; + struct list_head tx_list; + struct list_head list; + int len; + union { + struct pxp_layer_param s0_param; + struct pxp_layer_param out_param; + struct pxp_layer_param ol_param; + struct pxp_layer_param processing_param; + } layer_param; + struct pxp_proc_data proc_data; + + u32 hist_status; /* Histogram output status */ + + struct pxp_tx_desc *next; +}; + +struct pxp_channel { + struct dma_chan dma_chan; + dma_cookie_t completed; /* last completed cookie */ + enum pxp_channel_status status; + void *client; /* Only one client per channel */ + unsigned int n_tx_desc; + struct pxp_tx_desc *desc; /* allocated tx-descriptors */ + struct list_head active_list; /* active tx-descriptors */ + struct list_head free_list; /* free tx-descriptors */ + struct list_head queue; /* queued tx-descriptors */ + struct list_head list; /* track queued channel number */ + spinlock_t lock; /* protects sg[0,1], queue */ + struct mutex chan_mutex; /* protects status, cookie, free_list */ + int active_buffer; + unsigned int eof_irq; + char eof_name[16]; /* EOF IRQ name for request_irq() */ +}; + +#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd) +#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan) + +void pxp_txd_ack(struct dma_async_tx_descriptor *txd, + struct pxp_channel *pxp_chan); + +#ifdef CONFIG_MXC_PXP_CLIENT_DEVICE +int register_pxp_device(void); +void unregister_pxp_device(void); +#else +static int register_pxp_device(void) { return 0; } +static void unregister_pxp_device(void) {} +#endif +void pxp_fill( + u32 bpp, + u32 value, + u32 width, + u32 height, + u32 output_buffer, + u32 output_pitch); + +void m4_process(void); +#endif diff --git a/include/linux/regulator/consumer.h b/include/linux/regulator/consumer.h index 25602afd4844..bb9693bed08a 100644 --- a/include/linux/regulator/consumer.h +++ b/include/linux/regulator/consumer.h @@ -121,6 +121,9 @@ struct regmap; #define REGULATOR_EVENT_PRE_DISABLE 0x400 #define REGULATOR_EVENT_ABORT_DISABLE 0x800 #define REGULATOR_EVENT_ENABLE 0x1000 +#define REGULATOR_EVENT_PRE_DO_ENABLE 0x2000 +#define REGULATOR_EVENT_PRE_DO_DISABLE 0x4000 +#define REGULATOR_EVENT_AFT_DO_ENABLE 0x8000 /* * Regulator errors that can be queried using regulator_get_error_flags diff --git a/include/linux/regulator/fixed.h b/include/linux/regulator/fixed.h index 48918be649d4..ba4ac009d832 100644 --- a/include/linux/regulator/fixed.h +++ b/include/linux/regulator/fixed.h @@ -51,6 +51,7 @@ struct fixed_voltage_config { int microvolts; int gpio; unsigned startup_delay; + unsigned off_on_delay; unsigned gpio_is_open_drain:1; unsigned enable_high:1; unsigned enabled_at_boot:1; diff --git a/include/linux/rpmsg.h b/include/linux/rpmsg.h index 10d6ae8bbb7d..df056ad6bf78 100644 --- a/include/linux/rpmsg.h +++ b/include/linux/rpmsg.h @@ -43,6 +43,8 @@ #include <linux/mutex.h> #include <linux/poll.h> +#define VIRTIO_RPMSG_F_NS 0 + #define RPMSG_ADDR_ANY 0xFFFFFFFF struct rpmsg_device; diff --git a/include/linux/tee_drv.h b/include/linux/tee_drv.h index cb889afe576b..07bd226cd5f9 100644 --- a/include/linux/tee_drv.h +++ b/include/linux/tee_drv.h @@ -25,8 +25,9 @@ * specific TEE driver. */ -#define TEE_SHM_MAPPED 0x1 /* Memory mapped by the kernel */ -#define TEE_SHM_DMA_BUF 0x2 /* Memory with dma-buf handle */ +#define TEE_SHM_MAPPED BIT(0) /* Memory mapped by the kernel */ +#define TEE_SHM_DMA_BUF BIT(1) /* Memory with dma-buf handle */ +#define TEE_SHM_EXT_DMA_BUF BIT(2) /* Memory with dma-buf handle */ struct device; struct tee_device; @@ -211,6 +212,16 @@ void *tee_get_drvdata(struct tee_device *teedev); struct tee_shm *tee_shm_alloc(struct tee_context *ctx, size_t size, u32 flags); /** + * tee_shm_register_fd() - Register shared memory from file descriptor + * + * @ctx: Context that allocates the shared memory + * @fd: shared memory file descriptor reference. + * + * @returns a pointer to 'struct tee_shm' + */ +struct tee_shm *tee_shm_register_fd(struct tee_context *ctx, int fd); + +/** * tee_shm_free() - Free shared memory * @shm: Handle to shared memory to free */ @@ -275,4 +286,36 @@ int tee_shm_get_id(struct tee_shm *shm); */ struct tee_shm *tee_shm_get_from_id(struct tee_context *ctx, int id); +static inline bool tee_param_is_memref(struct tee_param *param) +{ + switch (param->attr & TEE_IOCTL_PARAM_ATTR_TYPE_MASK) { + case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT: + case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_OUTPUT: + case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INOUT: + return true; + default: + return false; + } +} + +struct tee_context *tee_client_open_context(struct tee_context *start, + int (*match)(struct tee_ioctl_version_data *, + const void *), + const void *data, struct tee_ioctl_version_data *vers); + +void tee_client_close_context(struct tee_context *ctx); + +void tee_client_get_version(struct tee_context *ctx, + struct tee_ioctl_version_data *vers); + +int tee_client_open_session(struct tee_context *ctx, + struct tee_ioctl_open_session_arg *arg, + struct tee_param *param); + +int tee_client_close_session(struct tee_context *ctx, u32 session); + +int tee_client_invoke_func(struct tee_context *ctx, + struct tee_ioctl_invoke_arg *arg, + struct tee_param *param); + #endif /*__TEE_DRV_H*/ diff --git a/include/linux/usb.h b/include/linux/usb.h index a22a3e139e96..991b467012ac 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -431,6 +431,7 @@ struct usb_bus { * Does the host controller use PIO * for control transfers? */ + struct otg_fsm *otg_fsm; /* usb otg finite state machine */ u8 otg_port; /* 0, or number of OTG/HNP port */ unsigned is_b_host:1; /* true during some HNP roleswitches */ unsigned b_hnp_enable:1; /* OTG: did A-Host enable HNP? */ diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h index 07f99362bc90..f572e1e01c63 100644 --- a/include/linux/usb/chipidea.h +++ b/include/linux/usb/chipidea.h @@ -60,9 +60,20 @@ struct ci_hdrc_platform_data { #define CI_HDRC_OVERRIDE_RX_BURST BIT(11) #define CI_HDRC_OVERRIDE_PHY_CONTROL BIT(12) /* Glue layer manages phy */ #define CI_HDRC_REQUIRES_ALIGNED_DMA BIT(13) +#define CI_HDRC_IMX_EHCI_QUIRK BIT(14) +#define CI_HDRC_IMX_IS_HSIC BIT(15) +/* need request pmqos during low power */ +#define CI_HDRC_PMQOS BIT(16) +/* Using PHY's charger detection */ +#define CI_HDRC_PHY_CHARGER_DETECTION BIT(17) enum usb_dr_mode dr_mode; #define CI_HDRC_CONTROLLER_RESET_EVENT 0 #define CI_HDRC_CONTROLLER_STOPPED_EVENT 1 +#define CI_HDRC_CONTROLLER_VBUS_EVENT 2 +#define CI_HDRC_IMX_HSIC_ACTIVE_EVENT 5 +#define CI_HDRC_IMX_HSIC_SUSPEND_EVENT 6 +#define CI_HDRC_IMX_TERM_SELECT_OVERRIDE_FS 7 +#define CI_HDRC_IMX_TERM_SELECT_OVERRIDE_OFF 8 int (*notify_event) (struct ci_hdrc *ci, unsigned event); struct regulator *reg_vbus; struct usb_otg_caps ci_otg_caps; @@ -89,4 +100,6 @@ struct platform_device *ci_hdrc_add_device(struct device *dev, /* Remove ci hdrc device */ void ci_hdrc_remove_device(struct platform_device *pdev); +/* Get current available role */ +enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev); #endif diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h index a1f03ebfde47..ea7fe49daa1d 100644 --- a/include/linux/usb/hcd.h +++ b/include/linux/usb/hcd.h @@ -398,7 +398,10 @@ struct hc_driver { int (*find_raw_port_number)(struct usb_hcd *, int); /* Call for power on/off the port if necessary */ int (*port_power)(struct usb_hcd *hcd, int portnum, bool enable); - + /* Call for SINGLE_STEP_SET_FEATURE Test for USB2 EH certification */ +#define EHSET_TEST_SINGLE_STEP_SET_FEATURE 0x06 + int (*submit_single_step_set_feature)(struct usb_hcd *, + struct urb *, int); }; static inline int hcd_giveback_urb_in_bh(struct usb_hcd *hcd) @@ -456,6 +459,14 @@ extern int usb_hcd_find_raw_port_number(struct usb_hcd *hcd, int port1); struct platform_device; extern void usb_hcd_platform_shutdown(struct platform_device *dev); +#ifdef CONFIG_USB_HCD_TEST_MODE +extern int ehset_single_step_set_feature(struct usb_hcd *hcd, int port); +#else +static inline int ehset_single_step_set_feature(struct usb_hcd *hcd, int port) +{ + return 0; +} +#endif /* CONFIG_USB_HCD_TEST_MODE */ #ifdef CONFIG_USB_PCI struct pci_dev; diff --git a/include/linux/usb/otg-fsm.h b/include/linux/usb/otg-fsm.h index a0a8f878503c..afebc95703d0 100644 --- a/include/linux/usb/otg-fsm.h +++ b/include/linux/usb/otg-fsm.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007,2008 Freescale Semiconductor, Inc. +/* Copyright (C) 2007-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -53,6 +53,10 @@ enum otg_fsm_timer { A_WAIT_ENUM, B_DATA_PLS, B_SSEND_SRP, + A_DP_END, + A_TST_MAINT, + B_SRP_REQD, + B_TST_SUSP, NUM_OTG_FSM_TIMERS, }; @@ -170,6 +174,13 @@ struct otg_fsm { int b_srp_done; int b_hnp_enable; int a_clr_err; + int hnp_polling; + + /* OTG test device */ + int tst_maint; + int otg_vbus_off; + int otg_srp_reqd; + int otg_hnp_reqd; /* Informative variables. All unused as of now */ int a_bus_drop_inf; diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h index b7a2625947f5..ef89950cb68a 100644 --- a/include/linux/usb/phy.h +++ b/include/linux/usb/phy.h @@ -63,6 +63,13 @@ enum usb_otg_state { OTG_STATE_A_VBUS_ERR, }; +/* The usb role of phy to be working with */ +enum usb_current_mode { + USB_MODE_NONE, + USB_MODE_HOST, + USB_MODE_DEVICE, +}; + struct usb_phy; struct usb_otg; @@ -155,6 +162,15 @@ struct usb_phy { * manually detect the charger type. */ enum usb_charger_type (*charger_detect)(struct usb_phy *x); + + int (*notify_suspend)(struct usb_phy *x, + enum usb_device_speed speed); + int (*notify_resume)(struct usb_phy *x, + enum usb_device_speed speed); + + int (*set_mode)(struct usb_phy *x, + enum usb_current_mode mode); + }; /** @@ -229,6 +245,15 @@ usb_phy_vbus_off(struct usb_phy *x) return x->set_vbus(x, false); } +static inline int +usb_phy_set_mode(struct usb_phy *x, enum usb_current_mode mode) +{ + if (!x || !x->set_mode) + return 0; + + return x->set_mode(x, mode); +} + /* for usb host and peripheral controller drivers */ #if IS_ENABLED(CONFIG_USB_PHY) extern struct usb_phy *usb_get_phy(enum usb_phy_type type); @@ -370,6 +395,24 @@ usb_phy_notify_disconnect(struct usb_phy *x, enum usb_device_speed speed) return 0; } +static inline int usb_phy_notify_suspend + (struct usb_phy *x, enum usb_device_speed speed) +{ + if (x && x->notify_suspend) + return x->notify_suspend(x, speed); + else + return 0; +} + +static inline int usb_phy_notify_resume + (struct usb_phy *x, enum usb_device_speed speed) +{ + if (x && x->notify_resume) + return x->notify_resume(x, speed); + else + return 0; +} + /* notifiers */ static inline int usb_register_notifier(struct usb_phy *x, struct notifier_block *nb) diff --git a/include/linux/usb/typec.h b/include/linux/usb/typec.h index 0d44ce6af08f..41320b14d29c 100644 --- a/include/linux/usb/typec.h +++ b/include/linux/usb/typec.h @@ -25,6 +25,7 @@ enum typec_port_type { TYPEC_PORT_DFP, TYPEC_PORT_UFP, TYPEC_PORT_DRP, + TYPEC_PORT_TYPE_UNKNOWN, }; enum typec_plug_type { @@ -43,6 +44,7 @@ enum typec_data_role { enum typec_role { TYPEC_SINK, TYPEC_SOURCE, + TYPEC_ROLE_UNKNOWN, }; enum typec_pwr_opmode { @@ -244,5 +246,7 @@ void typec_set_data_role(struct typec_port *port, enum typec_data_role role); void typec_set_pwr_role(struct typec_port *port, enum typec_role role); void typec_set_vconn_role(struct typec_port *port, enum typec_role role); void typec_set_pwr_opmode(struct typec_port *port, enum typec_pwr_opmode mode); +enum typec_port_type typec_get_port_type(struct device *dev); +enum typec_role typec_get_power_role(struct device *dev); #endif /* __LINUX_USB_TYPEC_H */ diff --git a/include/linux/wakelock.h b/include/linux/wakelock.h new file mode 100644 index 000000000000..f4a698a22880 --- /dev/null +++ b/include/linux/wakelock.h @@ -0,0 +1,67 @@ +/* include/linux/wakelock.h + * + * Copyright (C) 2007-2012 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _LINUX_WAKELOCK_H +#define _LINUX_WAKELOCK_H + +#include <linux/ktime.h> +#include <linux/device.h> + +/* A wake_lock prevents the system from entering suspend or other low power + * states when active. If the type is set to WAKE_LOCK_SUSPEND, the wake_lock + * prevents a full system suspend. + */ + +enum { + WAKE_LOCK_SUSPEND, /* Prevent suspend */ + WAKE_LOCK_TYPE_COUNT +}; + +struct wake_lock { + struct wakeup_source ws; +}; + +static inline void wake_lock_init(struct wake_lock *lock, int type, + const char *name) +{ + wakeup_source_init(&lock->ws, name); +} + +static inline void wake_lock_destroy(struct wake_lock *lock) +{ + wakeup_source_trash(&lock->ws); +} + +static inline void wake_lock(struct wake_lock *lock) +{ + __pm_stay_awake(&lock->ws); +} + +static inline void wake_lock_timeout(struct wake_lock *lock, long timeout) +{ + __pm_wakeup_event(&lock->ws, jiffies_to_msecs(timeout)); +} + +static inline void wake_unlock(struct wake_lock *lock) +{ + __pm_relax(&lock->ws); +} + +static inline int wake_lock_active(struct wake_lock *lock) +{ + return lock->ws.active; +} + +#endif |