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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-06-05 19:17:13 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2018-06-25 15:30:27 +0200 |
| commit | 7085f5d9e803688045e92ccb69e1f7fe0eee9621 (patch) | |
| tree | 3107fc4f263613165590c9ab912ff328c50493bd /tools/perf/scripts/python/call-graph-from-sql.py | |
| parent | eb614d94395293da7beecaa29555acb8966a2796 (diff) | |
arm64: dts: renesas: r8a77990: Add secondary CA53 CPU core
Add a device node for the second Cortex-A53 CPU core on the Renesas
R-Car E3 (r8a77990) SoC, and adjust the interrupt delivery masks for ARM
Generic Interrupt Controller and Architectured Timer.
Based on a patch in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-sql.py')
0 files changed, 0 insertions, 0 deletions