ARM: dts: imx6q-apalis: adjust display clock source

The default clock source for all display interfaces is PLL5. If
vastly different clocks are requested, the second display interface
might change the root clock leading to a wrong clock for the first
display. E.g. when combinding HDMI at full HD and parallel RGB at
VGA resolution. In the Apalis case the parallel RGB interface gets
probed second. The HDMI port needs a clock of 148.5MHz and therefor
sets the shared root clock to pll5_video_div. The parallel RGB
interface needs a clock of 25.175MHz which changes the shared root
clock pll5_video_div to 50.35MHz, which then leads to a wrong clock
for HDMI.

Other root clocks do not support very accurate clock setting, but
avoids conflicts between the two interfaces.

Use PLL2 PFD2 for the typically slower parallel RGB interfaces to
avoid messing with the PLL5 clock.

Signed-off-by: Stefan Agner <stefan@agner.ch>

0 files changed, 0 insertions, 0 deletions