ENGR00174037-1 Add HSIC suspend/resume feature

MSL part

- For HSIC, not connect nor disconnect, then WKCN,
  WKDC must not be set during suspend
- For HSIC, must set bit 21 in host control registry
  after device connected to host controller
- USB PHY 480M clock output must turn on to avoid about
  10ms delay before sending out resume signal
- HW_ANA_MISC clkgate delay must be set to 2 or 3 to
  avoid 24M OSCI not stable issue

Signed-off-by: Tony LIU <junjie.liu@freescale.com>

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