diff options
| author | Shengjiu Wang <shengjiu.wang@freescale.com> | 2015-01-27 16:43:17 +0800 |
|---|---|---|
| committer | Shengjiu Wang <shengjiu.wang@freescale.com> | 2015-01-28 15:44:35 +0800 |
| commit | 7f9e3777ffe7e9d06b598a63dc40372c7bafaa47 (patch) | |
| tree | e2cae945d1a157268c3e9619ef94cdecf594ac21 /include/dt-bindings/clock | |
| parent | d467cd78be24dc9c18bb3d0bb481fe5cf77e4c83 (diff) | |
MLK-10161-2: ARM: imx6sl: Add SPDIF_GCLK clock in clock tree
As spdif driver will register SPDIF clock to regmap, regmap will do
clk_prepare in init function, so SPDIF clock is prepared in probe, then its
root clock (pll clock) is prepared also, which cause the arm can't enter
low power mode.
Add SPDIF_GCLK in clock tree which share same gate bits with SPDIF clock.
Its root clock is ipg clock, and register it to regmap, then the issue can be
fixed.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/imx6sl-clock.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h index 9af14ae859db..4a2c4c61f766 100644 --- a/include/dt-bindings/clock/imx6sl-clock.h +++ b/include/dt-bindings/clock/imx6sl-clock.h @@ -1,5 +1,5 @@ /* - * Copyright 2013-2014 Freescale Semiconductor, Inc. + * Copyright 2013-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -174,7 +174,8 @@ #define IMX6SL_CLK_SSI2_IPG 161 #define IMX6SL_CLK_SSI3_IPG 162 #define IMX6SL_CLK_UART_OSC_4M 163 -#define IMX6SL_CLK_END 164 +#define IMX6SL_CLK_SPDIF_GCLK 164 +#define IMX6SL_CLK_END 165 #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ |