diff options
| author | Shengjiu Wang <shengjiu.wang@freescale.com> | 2015-01-27 16:44:34 +0800 |
|---|---|---|
| committer | Shengjiu Wang <shengjiu.wang@freescale.com> | 2015-01-28 15:44:35 +0800 |
| commit | 11b7dbb125f6cbe4f07238bc15abe1f1d1b9b1c5 (patch) | |
| tree | 2a3d4400c74b67e456651ba2a395b469f7bfec45 /include/dt-bindings/clock | |
| parent | 7f9e3777ffe7e9d06b598a63dc40372c7bafaa47 (diff) | |
MLK-10161-3: ARM: imx6sx: Add SPDIF_GCLK clock in clock tree
As spdif driver will register SPDIF clock to regmap, regmap will do
clk_prepare in init function, so SPDIF clock is prepared in probe, then its
root clock (pll clock) is prepared also, which cause the arm can't enter
low power mode.
Add SPDIF_GCLK in clock tree which share same gate bits with SPDIF clock.
Its root clock is ipg clock, and register it to regmap, then the issue can be
fixed.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/imx6sx-clock.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h index b47ff25d9b38..c399bbbac973 100644 --- a/include/dt-bindings/clock/imx6sx-clock.h +++ b/include/dt-bindings/clock/imx6sx-clock.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -279,6 +279,7 @@ #define IMX6SX_CLK_LVDS2_OUT 266 #define IMX6SX_CLK_LVDS2_IN 267 #define IMX6SX_CLK_ANACLK2 268 -#define IMX6SX_CLK_CLK_END 269 +#define IMX6SX_CLK_SPDIF_GCLK 269 +#define IMX6SX_CLK_CLK_END 270 #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ |