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authorKukjin Kim <kgene.kim@samsung.com>2013-04-09 01:10:13 +0900
committerKukjin Kim <kgene.kim@samsung.com>2013-04-09 01:10:13 +0900
commitda821eb7d42935b0f7056d98c75fd1150f6636f4 (patch)
treede83ac171d51bbe7621110c3145a68c198b13711 /drivers/gpu/drm/i915/intel_pm.c
parent296f3f2c9322480400338f71d8c118107f9a7f20 (diff)
parent07961ac7c0ee8b546658717034fe692fd12eefa9 (diff)
Merge commit 'v3.9-rc5' into next/clk-exynos
Conflicts: arch/arm/boot/dts/exynos4.dtsi arch/arm/boot/dts/exynos5440.dtsi
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 61fee7fcdc2c..adca00783e61 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2574,7 +2574,7 @@ static void gen6_enable_rps(struct drm_device *dev)
I915_WRITE(GEN6_RC_SLEEP, 0);
I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
- I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
+ I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
/* Check if we are enabling RC6 */
@@ -4079,6 +4079,9 @@ void intel_set_power_well(struct drm_device *dev, bool enable)
if (!IS_HASWELL(dev))
return;
+ if (!i915_disable_power_well && !enable)
+ return;
+
tmp = I915_READ(HSW_PWR_WELL_DRIVER);
is_enabled = tmp & HSW_PWR_WELL_STATE;
enable_requested = tmp & HSW_PWR_WELL_ENABLE;