diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2012-03-27 16:17:20 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2012-03-27 13:10:32 -0700 |
| commit | ded5b840dc4f24ed51d779024a87fba36a33b073 (patch) | |
| tree | 645d043cf75354b3e9d9798b10a51c74d51b92e8 /arch | |
| parent | 2d5b0acfa3a4be1cbd9b92c515daf8ebf3efd860 (diff) | |
ARM: tegra30: pm: clean L1 data before secondary CPU sleep
Change-Id: Ib16ee5efdf8686d750a5263baa8fff4d258e68cd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t3.S | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S index 96002dafca2c..5b303c9eb616 100644 --- a/arch/arm/mach-tegra/sleep-t3.S +++ b/arch/arm/mach-tegra/sleep-t3.S @@ -235,6 +235,16 @@ ENDPROC(tegra3_sleep_core_finish) */ ENTRY(tegra3_sleep_cpu_secondary_finish) mov r6, lr + + dsb +#ifdef MULTI_CACHE + mov32 r10, cpu_cache + mov lr, pc + ldr pc, [r10, #CACHE_FLUSH_KERN_ALL] +#else + bl __cpuc_flush_kern_all +#endif + bl tegra_cpu_exit_coherency /* Powergate this CPU. */ |