diff options
| author | Naveen Kumar Arepalli <naveenk@nvidia.com> | 2013-02-28 16:57:12 +0530 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2013-03-08 14:05:35 -0800 |
| commit | 506954ad565954f4e86b8b925311e2b0291ab4f2 (patch) | |
| tree | 7deb7260d9f866db52afe31d7219a0e7ecc6039a /arch | |
| parent | 490584489acde7046744c5863df30473aaa20336 (diff) | |
ARM: tegra: Roth: Set SD clock to 156 MHZ
1. Adding vdd_core regulators for sdmmc3 to be used for
setting core voltage constraints during frequency tuning.
2. Pass nominal core voltage value through mmc platform data to be used
for setting core voltage constraints during tuning.
3. Setting SD clock to 156MHz in SDR104 mode.
Change-Id: Ie48df23c051b0251f037dd4ba942cec570eefd90
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/207448
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/board-roth-power.c | 1 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/board-roth-sdhci.c | 7 |
2 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/board-roth-power.c b/arch/arm/mach-tegra/board-roth-power.c index 4c9f73618767..86a1c44acdd3 100644 --- a/arch/arm/mach-tegra/board-roth-power.c +++ b/arch/arm/mach-tegra/board-roth-power.c @@ -205,6 +205,7 @@ static struct regulator_consumer_supply palmas_smps3_supply[] = { static struct regulator_consumer_supply palmas_smps45_supply[] = { REGULATOR_SUPPLY("vdd_core", NULL), REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.0"), + REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.2"), REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.3"), }; diff --git a/arch/arm/mach-tegra/board-roth-sdhci.c b/arch/arm/mach-tegra/board-roth-sdhci.c index 044ecc407ecc..3d6d38c07453 100644 --- a/arch/arm/mach-tegra/board-roth-sdhci.c +++ b/arch/arm/mach-tegra/board-roth-sdhci.c @@ -160,7 +160,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = { .tap_delay = 0x3, .trim_delay = 0x3, .ddr_clk_limit = 41000000, - .max_clk_limit = 82000000, + .max_clk_limit = 156000000, .uhs_mask = MMC_UHS_MASK_DDR50, }; @@ -416,10 +416,13 @@ int __init roth_sdhci_init(void) { int nominal_core_mv; - nominal_core_mv = tegra_dvfs_rail_get_nominal_millivolts(tegra_core_rail); + nominal_core_mv = + tegra_dvfs_rail_get_nominal_millivolts(tegra_core_rail); if (nominal_core_mv > 0) { tegra_sdhci_platform_data0.nominal_vcore_uV = nominal_core_mv * 1000; + tegra_sdhci_platform_data2.nominal_vcore_uV = nominal_core_mv * + 1000; tegra_sdhci_platform_data3.nominal_vcore_uV = nominal_core_mv * 1000; } |