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| author | Thomas Gleixner <tglx@linutronix.de> | 2015-12-19 11:49:13 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2015-12-19 11:49:13 +0100 |
| commit | 0fa85119cd480c1ded7a81ed64f723fe16a15355 (patch) | |
| tree | 8648434601c5112a1d9ab091ab11507fe88e0962 /arch/mips/ralink/reset.c | |
| parent | d6ccc3ec95251d8d3276f2900b59cbc468dd74f4 (diff) | |
| parent | 1eab0e42450c6038e2bb17da438370fe639973f3 (diff) | |
Merge branch 'linus' into x86/cleanups
Pull in upstream changes so we can apply depending patches.
Diffstat (limited to 'arch/mips/ralink/reset.c')
| -rw-r--r-- | arch/mips/ralink/reset.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c index 55c7ec59df3c..ee117c4bc4a3 100644 --- a/arch/mips/ralink/reset.c +++ b/arch/mips/ralink/reset.c @@ -11,6 +11,7 @@ #include <linux/pm.h> #include <linux/io.h> #include <linux/of.h> +#include <linux/delay.h> #include <linux/reset-controller.h> #include <asm/reboot.h> @@ -18,8 +19,10 @@ #include <asm/mach-ralink/ralink_regs.h> /* Reset Control */ -#define SYSC_REG_RESET_CTRL 0x034 -#define RSTCTL_RESET_SYSTEM BIT(0) +#define SYSC_REG_RESET_CTRL 0x034 + +#define RSTCTL_RESET_PCI BIT(26) +#define RSTCTL_RESET_SYSTEM BIT(0) static int ralink_assert_device(struct reset_controller_dev *rcdev, unsigned long id) @@ -83,6 +86,11 @@ void ralink_rst_init(void) static void ralink_restart(char *command) { + if (IS_ENABLED(CONFIG_PCI)) { + rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL); + mdelay(50); + } + local_irq_disable(); rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL); unreachable(); @@ -98,7 +106,6 @@ static int __init mips_reboot_setup(void) { _machine_restart = ralink_restart; _machine_halt = ralink_halt; - pm_power_off = ralink_halt; return 0; } |