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| author | James Morris <jmorris@namei.org> | 2011-03-08 10:55:06 +1100 |
|---|---|---|
| committer | James Morris <jmorris@namei.org> | 2011-03-08 10:55:06 +1100 |
| commit | 1cc26bada9f6807814806db2f0d78792eecdac71 (patch) | |
| tree | 5509b5139db04af6c13db0a580c84116a4a54039 /arch/m68k/include/asm/m5272sim.h | |
| parent | eae61f3c829439f8f9121b5cd48a14be04df451f (diff) | |
| parent | 214d93b02c4fe93638ad268613c9702a81ed9192 (diff) | |
Merge branch 'master'; commit 'v2.6.38-rc7' into next
Diffstat (limited to 'arch/m68k/include/asm/m5272sim.h')
| -rw-r--r-- | arch/m68k/include/asm/m5272sim.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h index df3332c2317d..b7cc50abc831 100644 --- a/arch/m68k/include/asm/m5272sim.h +++ b/arch/m68k/include/asm/m5272sim.h @@ -12,6 +12,11 @@ #define m5272sim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m5272)" +#define CPU_INSTR_PER_JIFFY 3 + +#include <asm/m52xxacr.h> + /* * Define the 5272 SIM register set addresses. */ @@ -62,6 +67,9 @@ #define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ #define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ +#define MCFUART_BASE1 0x100 /* Base address of UART1 */ +#define MCFUART_BASE2 0x140 /* Base address of UART2 */ + #define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ #define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ #define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */ |