diff options
author | Ingo Molnar <mingo@elte.hu> | 2009-06-07 12:22:15 +0200 |
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committer | Ingo Molnar <mingo@elte.hu> | 2009-06-07 12:22:15 +0200 |
commit | 5f4457a4f62cc9d78e04c0eb12ff0540899aad89 (patch) | |
tree | 0b973d527ea6b2ae31e08da0746b4965a3c5a6d8 /arch/m32r/include/asm/cachectl.h | |
parent | 9b94b3a19b13e094c10f65f24bc358f6ffe4eacd (diff) | |
parent | b87297fb405ef13cac375f202d114323b076a56d (diff) |
Merge branch 'linus' into x86/cpu
Diffstat (limited to 'arch/m32r/include/asm/cachectl.h')
-rw-r--r-- | arch/m32r/include/asm/cachectl.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/m32r/include/asm/cachectl.h b/arch/m32r/include/asm/cachectl.h new file mode 100644 index 000000000000..2aab8f6fff41 --- /dev/null +++ b/arch/m32r/include/asm/cachectl.h @@ -0,0 +1,26 @@ +/* + * cachectl.h -- defines for M32R cache control system calls + * + * Copyright (C) 2003 by Kazuhiro Inaoka + */ +#ifndef __ASM_M32R_CACHECTL +#define __ASM_M32R_CACHECTL + +/* + * Options for cacheflush system call + * + * cacheflush() is currently fluch_cache_all(). + */ +#define ICACHE (1<<0) /* flush instruction cache */ +#define DCACHE (1<<1) /* writeback and flush data cache */ +#define BCACHE (ICACHE|DCACHE) /* flush both caches */ + +/* + * Caching modes for the cachectl(2) call + * + * cachectl(2) is currently not supported and returns ENOSYS. + */ +#define CACHEABLE 0 /* make pages cacheable */ +#define UNCACHEABLE 1 /* make pages uncacheable */ + +#endif /* __ASM_M32R_CACHECTL */ |