Merge tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic

Pul removal of obsolete architecture ports from Arnd Bergmann:
 "This removes the entire architecture code for blackfin, cris, frv,
  m32r, metag, mn10300, score, and tile, including the associated device
  drivers.

  I have been working with the (former) maintainers for each one to
  ensure that my interpretation was right and the code is definitely
  unused in mainline kernels. Many had fond memories of working on the
  respective ports to start with and getting them included in upstream,
  but also saw no point in keeping the port alive without any users.

  In the end, it seems that while the eight architectures are extremely
  different, they all suffered the same fate: There was one company in
  charge of an SoC line, a CPU microarchitecture and a software
  ecosystem, which was more costly than licensing newer off-the-shelf
  CPU cores from a third party (typically ARM, MIPS, or RISC-V). It
  seems that all the SoC product lines are still around, but have not
  used the custom CPU architectures for several years at this point. In
  contrast, CPU instruction sets that remain popular and have actively
  maintained kernel ports tend to all be used across multiple licensees.

  [ See the new nds32 port merged in the previous commit for the next
    generation of "one company in charge of an SoC line, a CPU
    microarchitecture and a software ecosystem"   - Linus ]

  The removal came out of a discussion that is now documented at
  https://lwn.net/Articles/748074/. Unlike the original plans, I'm not
  marking any ports as deprecated but remove them all at once after I
  made sure that they are all unused. Some architectures (notably tile,
  mn10300, and blackfin) are still being shipped in products with old
  kernels, but those products will never be updated to newer kernel
  releases.

  After this series, we still have a few architectures without mainline
  gcc support:

   - unicore32 and hexagon both have very outdated gcc releases, but the
     maintainers promised to work on providing something newer. At least
     in case of hexagon, this will only be llvm, not gcc.

   - openrisc, risc-v and nds32 are still in the process of finishing
     their support or getting it added to mainline gcc in the first
     place. They all have patched gcc-7.3 ports that work to some
     degree, but complete upstream support won't happen before gcc-8.1.
     Csky posted their first kernel patch set last week, their situation
     will be similar

  [ Palmer Dabbelt points out that RISC-V support is in mainline gcc
    since gcc-7, although gcc-7.3.0 is the recommended minimum  - Linus ]"

This really says it all:

 2498 files changed, 95 insertions(+), 467668 deletions(-)

* tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: (74 commits)
  MAINTAINERS: UNICORE32: Change email account
  staging: iio: remove iio-trig-bfin-timer driver
  tty: hvc: remove tile driver
  tty: remove bfin_jtag_comm and hvc_bfin_jtag drivers
  serial: remove tile uart driver
  serial: remove m32r_sio driver
  serial: remove blackfin drivers
  serial: remove cris/etrax uart drivers
  usb: Remove Blackfin references in USB support
  usb: isp1362: remove blackfin arch glue
  usb: musb: remove blackfin port
  usb: host: remove tilegx platform glue
  pwm: remove pwm-bfin driver
  i2c: remove bfin-twi driver
  spi: remove blackfin related host drivers
  watchdog: remove bfin_wdt driver
  can: remove bfin_can driver
  mmc: remove bfin_sdh driver
  input: misc: remove blackfin rotary driver
  input: keyboard: remove bf54x driver
  ...

1 files changed, 0 insertions, 163 deletions

diff --git a/arch/cris/arch-v32/mm/init.c b/arch/cris/arch-v32/mm/init.c
deleted file mode 100644
index 784876afa001..000000000000
--- a/arch/cris/arch-v32/mm/init.c
+++ /dev/null
@@ -1,163 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Set up paging and the MMU.
- *
- * Copyright (C) 2000-2003, Axis Communications AB.
- *
- * Authors:   Bjorn Wesen <bjornw@axis.com>
- *            Tobias Anderberg <tobiasa@axis.com>, CRISv32 port.
- */
-#include <linux/mmzone.h>
-#include <linux/init.h>
-#include <linux/bootmem.h>
-#include <linux/mm.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/types.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/mmu_context.h>
-#include <arch/hwregs/asm/mmu_defs_asm.h>
-#include <arch/hwregs/supp_reg.h>
-
-extern void tlb_init(void);
-
-/*
- * The kernel is already mapped with linear mapping at kseg_c so there's no
- * need to map it with a page table. However, head.S also temporarily mapped it
- * at kseg_4 thus the ksegs are set up again. Also clear the TLB and do various
- * other paging stuff.
- */
-void __init cris_mmu_init(void)
-{
-	unsigned long mmu_config;
-	unsigned long mmu_kbase_hi;
-	unsigned long mmu_kbase_lo;
-	unsigned short mmu_page_id;
-
-	/*
-	 * Make sure the current pgd table points to something sane, even if it
-	 * is most probably not used until the next switch_mm.
-	 */
-	per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd;
-
-	/* Initialise the TLB. Function found in tlb.c. */
-	tlb_init();
-
-	/*
-	 * Enable exceptions and initialize the kernel segments.
-	 * See head.S for differences between ARTPEC-3 and ETRAX FS.
-	 */
-	mmu_config = ( REG_STATE(mmu, rw_mm_cfg, we, on)        |
-		       REG_STATE(mmu, rw_mm_cfg, acc, on)       |
-		       REG_STATE(mmu, rw_mm_cfg, ex, on)        |
-		       REG_STATE(mmu, rw_mm_cfg, inv, on)       |
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
-		       REG_STATE(mmu, rw_mm_cfg, seg_f, page)   |
-		       REG_STATE(mmu, rw_mm_cfg, seg_e, page)   |
-		       REG_STATE(mmu, rw_mm_cfg, seg_d, linear) |
-#else
-		       REG_STATE(mmu, rw_mm_cfg, seg_f, linear) |
-		       REG_STATE(mmu, rw_mm_cfg, seg_e, linear) |
-		       REG_STATE(mmu, rw_mm_cfg, seg_d, page)   |
-#endif
-		       REG_STATE(mmu, rw_mm_cfg, seg_c, linear) |
-		       REG_STATE(mmu, rw_mm_cfg, seg_b, linear) |
-                       REG_STATE(mmu, rw_mm_cfg, seg_a, page)   |
-		       REG_STATE(mmu, rw_mm_cfg, seg_9, page)   |
-		       REG_STATE(mmu, rw_mm_cfg, seg_8, page)   |
-		       REG_STATE(mmu, rw_mm_cfg, seg_7, page)   |
-		       REG_STATE(mmu, rw_mm_cfg, seg_6, page)   |
-		       REG_STATE(mmu, rw_mm_cfg, seg_5, page)   |
-		       REG_STATE(mmu, rw_mm_cfg, seg_4, page)   |
-		       REG_STATE(mmu, rw_mm_cfg, seg_3, page)   |
-		       REG_STATE(mmu, rw_mm_cfg, seg_2, page)   |
-		       REG_STATE(mmu, rw_mm_cfg, seg_1, page)   |
-		       REG_STATE(mmu, rw_mm_cfg, seg_0, page));
-
-	/* See head.S for differences between ARTPEC-3 and ETRAX FS. */
-	mmu_kbase_hi = ( REG_FIELD(mmu, rw_mm_kbase_hi, base_f, 0x0) |
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
-			 REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x0) |
-			 REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x5) |
-#else
-			 REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x8) |
-			 REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x0) |
-#endif
-                         REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0x4) |
-			 REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb) |
-			 REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0x0) |
-			 REG_FIELD(mmu, rw_mm_kbase_hi, base_9, 0x0) |
-			 REG_FIELD(mmu, rw_mm_kbase_hi, base_8, 0x0));
-
-	mmu_kbase_lo = ( REG_FIELD(mmu, rw_mm_kbase_lo, base_7, 0x0) |
-			 REG_FIELD(mmu, rw_mm_kbase_lo, base_6, 0x0) |
-			 REG_FIELD(mmu, rw_mm_kbase_lo, base_5, 0x0) |
-			 REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 0x0) |
-			 REG_FIELD(mmu, rw_mm_kbase_lo, base_3, 0x0) |
-			 REG_FIELD(mmu, rw_mm_kbase_lo, base_2, 0x0) |
-			 REG_FIELD(mmu, rw_mm_kbase_lo, base_1, 0x0) |
-			 REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0x0));
-
-	mmu_page_id = REG_FIELD(mmu, rw_mm_tlb_hi, pid, 0);
-
-	/* Update the instruction MMU. */
-	SUPP_BANK_SEL(BANK_IM);
-	SUPP_REG_WR(RW_MM_CFG, mmu_config);
-	SUPP_REG_WR(RW_MM_KBASE_HI, mmu_kbase_hi);
-	SUPP_REG_WR(RW_MM_KBASE_LO, mmu_kbase_lo);
-	SUPP_REG_WR(RW_MM_TLB_HI, mmu_page_id);
-
-	/* Update the data MMU. */
-	SUPP_BANK_SEL(BANK_DM);
-	SUPP_REG_WR(RW_MM_CFG, mmu_config);
-	SUPP_REG_WR(RW_MM_KBASE_HI, mmu_kbase_hi);
-	SUPP_REG_WR(RW_MM_KBASE_LO, mmu_kbase_lo);
-	SUPP_REG_WR(RW_MM_TLB_HI, mmu_page_id);
-
-	SPEC_REG_WR(SPEC_REG_PID, 0);
-
-	/*
-	 * The MMU has been enabled ever since head.S but just to make it
-	 * totally obvious enable it here as well.
-	 */
-	SUPP_BANK_SEL(BANK_GC);
-	SUPP_REG_WR(RW_GC_CFG, 0xf); /* IMMU, DMMU, ICache, DCache on */
-}
-
-void __init paging_init(void)
-{
-	int i;
-	unsigned long zones_size[MAX_NR_ZONES];
-
-	printk("Setting up paging and the MMU.\n");
-
-	/* Clear out the init_mm.pgd that will contain the kernel's mappings. */
-	for(i = 0; i < PTRS_PER_PGD; i++)
-		swapper_pg_dir[i] = __pgd(0);
-
-	cris_mmu_init();
-
-	/*
-	 * Initialize the bad page table and bad page to point to a couple of
-	 * allocated pages.
-	 */
-	empty_zero_page = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
-	memset((void *) empty_zero_page, 0, PAGE_SIZE);
-
-	/* All pages are DMA'able in Etrax, so put all in the DMA'able zone. */
-	zones_size[0] = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
-
-	for (i = 1; i < MAX_NR_ZONES; i++)
-		zones_size[i] = 0;
-
-	/*
-	 * Use free_area_init_node instead of free_area_init, because it is
-	 * designed for systems where the DRAM starts at an address
-	 * substantially higher than 0, like us (we start at PAGE_OFFSET). This
-	 * saves space in the mem_map page array.
-	 */
-	free_area_init_node(0, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0);
-
-	mem_map = contig_page_data.node_mem_map;
-}