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| author | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 14:32:24 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 14:32:24 -0700 |
| commit | a348a7e6fdbcd2d5192a09719a479bb238fde727 (patch) | |
| tree | 5ff94185f4e5a810777469d7fe7832a8ec2d3430 /arch/blackfin/include/asm/traps.h | |
| parent | 808347f6a31792079e345ec865e9cfcb6e8ae6b2 (diff) | |
| parent | 28d0325ce6e0a52f53d8af687e6427fee59004d3 (diff) | |
Merge commit 'v2.6.31-rc1' into dmaengine
Diffstat (limited to 'arch/blackfin/include/asm/traps.h')
| -rw-r--r-- | arch/blackfin/include/asm/traps.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h index 34f7295fb070..3cdc454cde23 100644 --- a/arch/blackfin/include/asm/traps.h +++ b/arch/blackfin/include/asm/traps.h @@ -111,9 +111,7 @@ level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" #define EXC_0x2A(level) \ "Instruction fetch misaligned address violation\n" \ - level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \ - level " exception, the return address provided in RETX is the destination address which is\n" \ - level " misaligned, rather than the address of the offending instruction.\n" + level " - Attempted misaligned instruction cache fetch.\n" #define EXC_0x2B(level) \ "CPLB protection violation\n" \ level " - Illegal instruction fetch access (memory protection violation).\n" |