diff options
| author | Florian Fainelli <f.fainelli@gmail.com> | 2015-02-10 17:33:07 -0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2015-03-06 14:57:30 -0800 |
| commit | ede1c87dab875cb070f4f4d00a6e19315f6163c8 (patch) | |
| tree | 4ecd8461ccce35ca627762c7c55ec9bdfc20ea5d /arch/arm | |
| parent | 42b3f837879d1d8539b2a9f57fd4d6417f5d2a66 (diff) | |
ARM: dts: BCM63xx: fix L2 cache properties
commit 9df11828d9b5665ddef81e45f83dd5376a8cd620 upstream.
The L2 cache properties were completely off with respect to what the
hardware is configured for. Fix the cache-size, cache-line-size and
cache-sets to reflect the L2 cache controller we have: 512KB, 16 ways
and 32 bytes per cache-line.
Fixes: 46d4bca0445a0 ("ARM: BCM63XX: add BCM63138 minimal Device Tree")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/bcm63138.dtsi | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi index d2d8e94e0aa2..f46329c8ad75 100644 --- a/arch/arm/boot/dts/bcm63138.dtsi +++ b/arch/arm/boot/dts/bcm63138.dtsi @@ -66,8 +66,9 @@ reg = <0x1d000 0x1000>; cache-unified; cache-level = <2>; - cache-sets = <16>; - cache-size = <0x80000>; + cache-size = <524288>; + cache-sets = <1024>; + cache-line-size = <32>; interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; }; |