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authorRob Herring <r.herring@freescale.com>2009-10-19 14:43:19 -0500
committerRob Herring <r.herring@freescale.com>2009-10-26 16:57:04 -0500
commit460b55880e47a98943f5072bc03ffcfcc8a40a14 (patch)
tree5690552665f0b7843e6552e4d5fe7b63cbc78f51 /arch/arm/mm/cache-l2x0.c
parent40abba66d676c6c7aff57a5fbd1345974c90b2fe (diff)
ENGR00117389 Port 5.0.0 release to 2.6.31
This is i.MX BSP 5.0.0 release ported to 2.6.31 Signed-off-by: Rob Herring <r.herring@freescale.com> Signed-off-by: Alan Tull <r80115@freescale.com> Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
Diffstat (limited to 'arch/arm/mm/cache-l2x0.c')
-rw-r--r--arch/arm/mm/cache-l2x0.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index ca69ff5981a6..6688b9bd17ec 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -17,6 +17,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
+#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/io.h>
@@ -25,7 +26,6 @@
#define CACHE_LINE_SIZE 32
#ifdef CONFIG_OPROFILE_ARM11_EVTMON
-#include <linux/module.h>
#define L2_ENABLE_BIT 0x1
#define L2_EVTBUS_BIT 0x100000
#define L2_CTL_REG (l2x0_base + L2X0_CTRL)