diff options
| author | Anson Huang <b20788@freescale.com> | 2012-10-09 15:30:20 -0400 |
|---|---|---|
| committer | Anson Huang <b20788@freescale.com> | 2012-10-09 15:40:32 -0400 |
| commit | d9a5a4033656d5290b627aa94bf03821b64abb13 (patch) | |
| tree | 20f286860f953efec3511725c04c0a6e42ddee94 /arch/arm/mach-mx6/devices-imx6q.h | |
| parent | ea2d0606fb7e7b3ed162e95736b8f78a986b4235 (diff) | |
ENGR00227477 mx6qdl: system resume fail due to DDR not accessable
For DQ and DL, we must make sure DDR can be accessed after resume,
our code did NOT get a valid base address for MMDC to exit from
DVFS mode, need to fix it.
According to ARM, we only need to save r0-r3 and r12 before calling
C function.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/devices-imx6q.h')
0 files changed, 0 insertions, 0 deletions