diff options
| author | Anson Huang <b20788@freescale.com> | 2013-10-31 15:27:19 -0400 |
|---|---|---|
| committer | Anson Huang <b20788@freescale.com> | 2013-11-01 15:48:59 -0400 |
| commit | 6063e4c5c91662b1ce30e83c36a91ae4f7d8878a (patch) | |
| tree | 4280b52e8c843de6a022f2d0a7f3ed6b7d619aef /arch/arm/mach-imx | |
| parent | 28774b788ae0de5d88045dd60cac3656c305821d (diff) | |
ENGR00285692 arm: imx: add necessary clock gates into clk tree
1. add epit1, epit2 and tzasc2 clock gate to clk tree so that
clk framework can manage these clock gates;
2. adjust ipu2_di1 clock gate registry code to follow hardware
register CG index sequence.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 1c7179f537fd..9a27141485c3 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -108,7 +108,7 @@ enum mx6q_clks { spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, gpt_3m, video_27m, ldb_di0_div_7, ldb_di1_div_7, ldb_di0_div_sel, ldb_di1_div_sel, pll4_audio_div, lvds1_sel, lvds1_in, lvds1_out, caam_mem, caam_aclk, - caam_ipg, clk_max + caam_ipg, epit1, epit2, tzasc2, clk_max }; static struct clk *clk[clk_max]; @@ -354,6 +354,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); + clk[epit1] = imx_clk_gate2("epit1", "ipg", base + 0x6c, 12); + clk[epit2] = imx_clk_gate2("epit2", "ipg", base + 0x6c, 14); clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16); clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); @@ -373,15 +375,16 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); + clk[tzasc2] = imx_clk_gate2("tzasc2", "mmdc_ch0_axi_podf", base + 0x70, 24); clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26); clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6); clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); + clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_div_sel", base + 0x74, 12); clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_div_sel", base + 0x74, 14); - clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16); if (cpu_is_imx6dl()) /* |