diff options
| author | Jiri Kosina <jkosina@suse.cz> | 2013-07-25 12:30:27 +0200 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2013-07-25 12:30:49 +0200 |
| commit | a3f8612700507a10ad7186fd77e9f46c7af88335 (patch) | |
| tree | f00be0b726748113ffeb4e1caf7ade7ef33cfabe /arch/arm/mach-exynos/platsmp.c | |
| parent | 8ecada16512c90ae782b00f15ebff0c32e4cd92a (diff) | |
| parent | 07bc9dc1b01bad7084fed3d2659e5d83317869bc (diff) | |
Merge branch 'master' into for-next
Sync with Linus' master to be able to apply
trivial patche to newer code.
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Diffstat (limited to 'arch/arm/mach-exynos/platsmp.c')
| -rw-r--r-- | arch/arm/mach-exynos/platsmp.c | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index a0e8ff7758a4..58b43e6f9262 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -50,6 +50,8 @@ static inline void __iomem *cpu_boot_reg(int cpu) boot_reg = cpu_boot_reg_base(); if (soc_is_exynos4412()) boot_reg += 4*cpu; + else if (soc_is_exynos5420()) + boot_reg += 4; return boot_reg; } @@ -73,7 +75,7 @@ static void __iomem *scu_base_addr(void) static DEFINE_SPINLOCK(boot_lock); -static void __cpuinit exynos_secondary_init(unsigned int cpu) +static void exynos_secondary_init(unsigned int cpu) { /* * let the primary processor know we're out of the @@ -88,7 +90,7 @@ static void __cpuinit exynos_secondary_init(unsigned int cpu) spin_unlock(&boot_lock); } -static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; unsigned long phys_cpu = cpu_logical_map(cpu); @@ -180,10 +182,14 @@ static void __init exynos_smp_init_cpus(void) void __iomem *scu_base = scu_base_addr(); unsigned int i, ncores; - if (soc_is_exynos5250()) - ncores = 2; - else + if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) ncores = scu_base ? scu_get_core_count(scu_base) : 1; + else + /* + * CPU Nodes are passed thru DT and set_cpu_possible + * is set by "arm_dt_init_cpu_maps". + */ + return; /* sanity check */ if (ncores > nr_cpu_ids) { @@ -200,7 +206,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) { int i; - if (!(soc_is_exynos5250() || soc_is_exynos5440())) + if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) scu_enable(scu_base_addr()); /* |