// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2020 NXP
 */

/dts-v1/;

#include "fsl-imx8dxl.dtsi"

/ {
	model = "NXP i.MX8DXL DDR3 VAL Board";
	compatible = "fsl,imx8dxl-ddr3-val", "fsl,imx8dxl";

	chosen {
		bootargs = "console=ttyLP0,115200 earlycon";
		stdout-path = &lpuart0;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_usdhc2_vmmc: usdhc2_vmmc {
			compatible = "regulator-fixed";
			regulator-name = "SD1_SPWR";
			regulator-min-microvolt = <3000000>;
			regulator-max-microvolt = <3000000>;
			gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
			enable-active-high;
			startup-delay-us = <100>;
			u-boot,off-on-delay-us = <12000>;
		};

		reg_usb_otg1_vbus: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "usb_otg1_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_usb_otg2_vbus: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "usb_otg2_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx8dxl-evk {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x00000021
				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021
			>;
		};

		pinctrl_eqos: eqosgrp {
			fsl,pins = <
				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD		0x000514a0
				SC_P_ENET0_MDC_CONN_EQOS_MDC				0x06000020
				SC_P_ENET0_MDIO_CONN_EQOS_MDIO			0x06000020
				SC_P_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL		0x00000060
				SC_P_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC		0x00000060
				SC_P_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0	0x00000060
				SC_P_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1	0x00000060
				SC_P_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2	0x00000060
				SC_P_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3	0x00000060
				SC_P_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC		0x00000060
				SC_P_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL	0x00000060
				SC_P_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0	0x00000060
				SC_P_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1	0x00000060
				SC_P_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2	0x00000060
				SC_P_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3	0x00000060
			>;
		};

		pinctrl_gpmi_nand_1: gpmi-nand-1 {
			fsl,pins = <
				SC_P_EMMC0_DATA0_CONN_NAND_DATA00	0x0e00004c
				SC_P_EMMC0_DATA1_CONN_NAND_DATA01	0x0e00004c
				SC_P_EMMC0_DATA2_CONN_NAND_DATA02	0x0e00004c
				SC_P_EMMC0_DATA3_CONN_NAND_DATA03	0x0e00004c
				SC_P_EMMC0_DATA4_CONN_NAND_DATA04	0x0e00004c
				SC_P_EMMC0_DATA5_CONN_NAND_DATA05	0x0e00004c
				SC_P_EMMC0_DATA6_CONN_NAND_DATA06	0x0e00004c
				SC_P_EMMC0_DATA7_CONN_NAND_DATA07	0x0e00004c
				SC_P_EMMC0_CLK_CONN_NAND_READY_B	0x0e00004c
				SC_P_EMMC0_STROBE_CONN_NAND_CLE		0x0e00004c
				SC_P_EMMC0_RESET_B_CONN_NAND_WP_B	0x0e00004c
				SC_P_EMMC0_CMD_CONN_NAND_DQS		0x0e00004c

				SC_P_USDHC1_RESET_B_CONN_NAND_WE_B	0x0e00004c
				SC_P_USDHC1_WP_CONN_NAND_ALE		0x0e00004c
				SC_P_USDHC1_VSELECT_CONN_NAND_RE_B  	0x0e00004c
			>;
		};

		pinctrl_lpuart0: lpuart0grp {
			fsl,pins = <
				SC_P_UART0_RX_ADMA_UART0_RX	0x06000020
				SC_P_UART0_TX_ADMA_UART0_TX	0x06000020
			>;
		};

		pinctrl_lpi2c2: lpi2c2grp {
			fsl,pins = <
				SC_P_SPI1_SDO_ADMA_I2C2_SCL	0x06000021
				SC_P_SPI1_SCK_ADMA_I2C2_SDA	0x06000021
			>;
		};

		pinctrl_lpi2c3: lpi2c3grp {
			fsl,pins = <
				SC_P_SPI1_SDI_ADMA_I2C3_SCL	0x06000021
				SC_P_SPI1_CS0_ADMA_I2C3_SDA	0x06000021
			>;
		};

		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
			fsl,pins = <
				SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x00000021 /* RESET_B */
				SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00		0x00000021 /* WP */
				SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x00000021 /* CD */
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
				SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD		0x00000021
				SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
				SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
				SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
				SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
				SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
			fsl,pins = <
				SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
				SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD		0x00000021
				SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
				SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
				SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
				SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
				SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
			fsl,pins = <
				SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
				SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD		0x00000021
				SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
				SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
				SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
				SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
				SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
			>;
		};

		pinctrl_flexspi0: flexspi0grp {
			fsl,pins = <
				SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x06000021
				SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x06000021
				SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x06000021
				SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x06000021
				SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x06000021
				SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x06000021
				SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x06000021
				SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x06000021
				SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x06000021
				SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x06000021
				SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x06000021
			>;
		};

		pinctrl_pcieb: pcieagrp{
			fsl,pins = <
				SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x06000021
				SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x06000021
				SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02		0x04000021
			>;
		};
	};
};

&A35_0 {
	u-boot,dm-pre-reloc;
};

&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};

&gpio4 {
	status = "okay";
};

&gpio5 {
	status = "okay";
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c2>;
	status = "okay";

	i2cswitch@70 {
		compatible = "nxp,pca9646";
		reg = <0x70>;
		u-boot,i2c-offset-len = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		v2x_i2c2: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0>;
		};

		audio_codec1_i2c2: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x1>;
		};

		audio_codec2_i2c2: i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2>;
		};

		audio_codec3_i2c2: i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;
		};

		audio_codec0_i2c2: i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x4>;
		};
	};

	pca6416_a: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pca6416_b: gpio@21 {
		compatible = "ti,tca6416";
		reg = <0x21>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c3>;
	status = "okay";

	i2cswitch@70 {
		compatible = "nxp,pca9646";
		reg = <0x70>;
		u-boot,i2c-offset-len = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		alt_audio_codec1_i2c3: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0>;
		};

		alt_audio_codec2_i2c3: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x1>;
		};

		alt_audio_codec3_i2c3: i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2>;
		};

		usb1_i2c3: i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;
		};

		usb2_i2c3: i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x4>;
		};
	};

	pca6416_c: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&flexspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	status = "okay";

	flash0: mt35xu512aba@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "spi-flash";
		spi-max-frequency = <29000000>;
		spi-nor,ddr-quad-read-dummy = <8>;
	};
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	bus-width = <4>;
	cd-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy0>;
	fsl,ar8031-phy-fixup;
	fsl,magic-packet;
	status = "okay";

	phy-reset-gpios = <&pca6416_a 2 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <10>;
	phy-reset-post-delay = <150>;

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};

	};
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
	status = "okay";
	nand-on-flash-bbt;
};

&pcieb{
	ext_osc = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcieb>;
	clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>;
	reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usb_otg1_vbus>;
	dr_mode = "otg";
	srp-disable;
	hnp-disable;
	adp-disable;
	power-polarity-active-high;
	disable-over-current;
	status = "okay";
};

&usbotg2 {
	vbus-supply = <&reg_usb_otg2_vbus>;
	dr_mode = "otg";
	srp-disable;
	hnp-disable;
	adp-disable;
	power-polarity-active-high;
	disable-over-current;
	status = "okay";
};