// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2017-2018 NXP
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		idle-states {
			entry-method = "psci";

			CPU_SLEEP: cpu-sleep {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0000000>;
				entry-latency-us = <700>;
				exit-latency-us = <250>;
				min-residency-us = <1000>;
			};

			CLUSTER_SLEEP: cluster-sleep {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x1000000>;
				entry-latency-us = <1000>;
				exit-latency-us = <700>;
				min-residency-us = <2700>;
				wakeup-latency-us = <1500>;
			};
		};

		/* We have 2nd clusters having 2 Cortex-A72 cores */
		A72_0: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72","arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&A72_L2>;
			cpu-idle-states = <&CPU_SLEEP>;
		};

		A72_1: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72","arm,armv8";
			reg = <0x0 0x101>;
			enable-method = "psci";
			next-level-cache = <&A72_L2>;
			cpu-idle-states = <&CPU_SLEEP>;
		};

		A72_L2: l2-cache1 {
			compatible = "cache";
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7
			(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
		interrupt-affinity = <&A72_0>, <&A72_1>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
		cpu_suspend   = <0xc4000001>;
		cpu_off       = <0xc4000002>;
		cpu_on        = <0xc4000003>;
	};
};