From 3fd673cf363bc86ed42eff713d4e3506720e91a2 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 30 Dec 2011 23:53:07 -0500 Subject: sbc8548: relocate 64MB user flash to sane boundary The current situation has the 64MB user flash at an awkward alignment; shifted back from 0xfc00_0000 by 8M, to leave an 8MB hole for the soldered on boot flash @ EOM. But to switch to optionally supporting booting off the 64MB flash, the 64MB will then be mapped at the sane address of 0xfc00_0000. This leads to awkward things when programming the 64MB flash prior to transitioning to it -- i.e. even though the chip spans from 0xfb80_0000 to 0xff7f_ffff, you would have to program a u-boot image into the two sectors from 0xfbf0_0000 --> 0xfbff_ffff so that it was in the right place when JP12/SW2.8 were switched to make the 64MB on /CS0. (i.e. the chip is only looking at the bits in mask 0x3ff_ffff) We also have to have three TLB entries responsible for dealing with mapping the 64MB flash due to this 8MB of misalignment. In the end, there is address space from 0xec00_0000 to 0xefff_ffff where we can map it, and then the transition from booting from one config to the other will be a simple 0xec --> 0xfc mapping. Plus we can toss out a TLB entry. Note that TLB0 is kept at 64MB and not shrunk down to the 8MB boot flash; this means we won't have to change it when the alternate config uses the full 64MB for booting, in TLB0. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- doc/README.sbc8548 | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'doc') diff --git a/doc/README.sbc8548 b/doc/README.sbc8548 index 6cbe12f1f5..5fa9c93685 100644 --- a/doc/README.sbc8548 +++ b/doc/README.sbc8548 @@ -100,6 +100,9 @@ Boot flash: Sodimm flash: intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000 + Note that this address reflects the default setting for + the JTAG debugging tools, but since the alignment is + rather inconvenient, u-boot puts it at 0xec00_0000. Jumpers: @@ -187,9 +190,12 @@ start end CS width Desc. 0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB) f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB) f800_0000 f8b0_1fff CS5 - EPLD -fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) +fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) [*] ff80_0000 ffff_ffff CS0 8 Boot flash (8MB) +[*] fb80 represents the default programmed by WR JTAG register files, + but u-boot places the flash at either ec00 or fc00 based on JP12. + The EPLD on CS5 demuxes the following devices at the following offsets: offset size width device -- cgit v1.2.3 From f0aec4ea3301f7db3a691ec0cbb5230e99cceb34 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 30 Dec 2011 23:53:08 -0500 Subject: sbc8548: enable ability to boot from alternate flash This board has an 8MB soldered on flash, and a 64MB SODIMM flash module. Normally the board boots from the 8MB flash, but the hardware can be configured for booting from the 64MB flash as well by swapping CS0 and CS6. This can be handy for recovery purposes, or for supporting u-boot and VxBoot at the same time. To support this in u-boot, we need to have different BR0/OR0 and BR6/OR6 settings in place for when the board is configured in this way, and a different TEXT_BASE needs to be used due to the larger sector size of the 64MB flash module. We introduce the suffix _8M and _64M for the BR0/BR6 and the OR0/OR6 values so it is clear which is being used to map what specific device. The larger sector size (512k) of the alternate flash needs a larger malloc pool, otherwise you'll get failures when running saveenv, so bump it up accordingly. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- doc/README.sbc8548 | 34 ++++++++++++++++++++++++++++++---- 1 file changed, 30 insertions(+), 4 deletions(-) (limited to 'doc') diff --git a/doc/README.sbc8548 b/doc/README.sbc8548 index 5fa9c93685..e6b8abe2b3 100644 --- a/doc/README.sbc8548 +++ b/doc/README.sbc8548 @@ -86,6 +86,33 @@ The "md" steps in the above are just a precautionary step that allow you to confirm the u-boot version that was downloaded, and then confirm that it was copied to flash. +The above assumes that you are using the default board settings which +have u-boot in the 8MB flash, tied to /CS0. + +If you are running the default 8MB /CS0 settings but want to store an +image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled, +(as a backup, etc) then the steps will become: + + tftp u-boot.bin + md 200000 10 + protect off all + era eff00000 efffffff + cp.b 200000 eff00000 100000 + md eff00000 10 + protect on all + +Finally, if you are running the alternate 64MB /CS0 settings and want +to update the in-use u-boot image, then (again with CONFIG_SYS_ALT_BOOT +enabled) the steps will become: + + tftp u-boot.bin + md 200000 10 + protect off all + era fff00000 ffffffff + cp.b 200000 fff00000 100000 + md fff00000 10 + protect on all + Hardware Reference: =================== @@ -127,10 +154,9 @@ JP19 PCI mode PCI PCI-X onto /CS0 and the SODIMM flash on /CS6 (default). When JP12 is jumpered parallel to the LBC-SDRAM, then /CS0 is for the SODIMM flash and /CS6 is for the boot flash. Note that in this -alternate setting, you also need to switch SW2.8 to ON. Currently -u-boot doesn't support booting off the SODIMM in this alternate -setting without manually altering BR0/OR0 and BR6/OR6 in the -board config file appropriately. +alternate setting, you also need to switch SW2.8 to ON. +See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting +and boot u-boot from the 64MB SODIMM Switches: -- cgit v1.2.3 From 7e44f2b710db09a1b02e55246e0915732cc4775e Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 30 Dec 2011 23:53:10 -0500 Subject: sbc8548: Make enabling SPD RAM configuration work Previously, SPD configuration of RAM was non functional on this board. Now that the root cause is known (an i2c address conflict), there is a simple end-user workaround - remove the old slower local bus 128MB module and then SPD detection on the main DDR2 memory module works fine. We make the enablement of the LBC SDRAM support conditional on being not SPD enabled. We can revisit this dependency as the hardware workaround becomes available. Turning off LBC SDRAM support revealed a couple implict dependencies in the tlb/law code that always expected an LBC SDRAM address. This has been tested with the default 256MB module, a 512MB a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration worked fine in all cases. The default configuration remains to go with the hard coded DDR config, so the default build will continue to work on boards where people don't bother to read the docs. But the advantage of going to the SPD config is that even the small default module gets configured for CL3 instead of CL4. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- doc/README.sbc8548 | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'doc') diff --git a/doc/README.sbc8548 b/doc/README.sbc8548 index e6b8abe2b3..f9e2dea573 100644 --- a/doc/README.sbc8548 +++ b/doc/README.sbc8548 @@ -62,6 +62,27 @@ a 33MHz PCI configuration is currently untested.) 02.00.00 0x1148 0x9e00 Network controller 0x00 => +Memory Size and using SPD: +========================== + +The default configuration uses hard coded memory configuration settings +for 256MB of DDR2 @400MHz. It does not by default use the DDR2 SPD +EEPROM data to read what memory is installed. + +There is a hardware errata, which causes the older local bus SDRAM +SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so +that the SPD data can not be read reliably. + +If you want to upgrade to larger RAM size, you can simply enable + #define CONFIG_SPD_EEPROM + #define CONFIG_DDR_SPD +in include/configs/sbc8548.h file. (The lines are already there +but listed as #undef). + +Note that you will have to physically remove the LBC 128MB DIMM +from the board's socket to resolve the above i2c address overlap +issue and allow SPD autodetection of RAM to work. + Updating U-boot with U-boot: ============================ -- cgit v1.2.3 From 3e3262bd149e21d0f5a82648218c26f2aa0e15e7 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 30 Dec 2011 23:53:12 -0500 Subject: sbc8548: enable support for hardware SPD errata workaround Existing boards by default have an issue where the LBC SDRAM SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51. After the hardware modification listed in the README is made, then the DDR2 SPD EEPROM appears at 0x53. So this implements a board specific get_spd() by taking advantage of the existing weak linkage, that 1st tries reading at 0x53 and then if that fails, it falls back to the old 0x51. Since the old dependency issue of "SPD implies no LBC SDRAM" gets removed with the hardware errata fix, remove that restriction in the code, so both LBC SDRAM and SPD can be selected. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- doc/README.sbc8548 | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) (limited to 'doc') diff --git a/doc/README.sbc8548 b/doc/README.sbc8548 index f9e2dea573..0f3f5432f2 100644 --- a/doc/README.sbc8548 +++ b/doc/README.sbc8548 @@ -71,7 +71,22 @@ EEPROM data to read what memory is installed. There is a hardware errata, which causes the older local bus SDRAM SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so -that the SPD data can not be read reliably. +that the SPD data can not be read reliably. You can test if your +board has the errata fix by running "i2c probe". If you see 0x53 +as a valid device, it has been fixed. If you only see 0x50, 0x51 +then your board does not have the fix. + +You can also visually inspect the board to see if this hardware +fix has been applied: + + 1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on + the back of the PCB behind the DDR SDRAM SODIMM connector. + 2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad + to R313 pin 2. Pin 2 for each resistor is the end of the + resistor closest to the CPU. + +Boards without the mod will have R314 and R313 in parallel, like "||". +After the mod, they will be touching and form an "L" shape. If you want to upgrade to larger RAM size, you can simply enable #define CONFIG_SPD_EEPROM @@ -79,7 +94,8 @@ If you want to upgrade to larger RAM size, you can simply enable in include/configs/sbc8548.h file. (The lines are already there but listed as #undef). -Note that you will have to physically remove the LBC 128MB DIMM +If you did the i2c test, and your board does not have the errata +fix, then you will have to physically remove the LBC 128MB DIMM from the board's socket to resolve the above i2c address overlap issue and allow SPD autodetection of RAM to work. -- cgit v1.2.3