From d6f939a90c3192adf5c5bec1ec4fbc05ec36144e Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Thu, 7 Dec 2023 16:15:08 +0200 Subject: mtd: rawnand: omap_elm: Fix elm_init definition The macro ELM_BASE is defined in mach/hardware.h and is not visible at the omap_elm.h header file. Avoid using it in omap_elm.h. Reported-by: Hong Guan Fixes: 7363cf0581a3 ("mtd: rawnand: omap_elm: u-boot driver model support") Signed-off-by: Roger Quadros --- drivers/mtd/nand/raw/omap_elm.c | 4 ++-- drivers/mtd/nand/raw/omap_elm.h | 6 ------ 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/nand/raw/omap_elm.c b/drivers/mtd/nand/raw/omap_elm.c index 35a066df41..0e4954a051 100644 --- a/drivers/mtd/nand/raw/omap_elm.c +++ b/drivers/mtd/nand/raw/omap_elm.c @@ -185,7 +185,6 @@ void elm_reset(void) ; } -#ifdef ELM_BASE /** * elm_init - Initialize ELM module * @@ -194,10 +193,11 @@ void elm_reset(void) */ void elm_init(void) { +#ifdef ELM_BASE elm_cfg = (struct elm *)ELM_BASE; elm_reset(); -} #endif +} #ifdef CONFIG_SYS_NAND_SELF_INIT static int elm_probe(struct udevice *dev) diff --git a/drivers/mtd/nand/raw/omap_elm.h b/drivers/mtd/nand/raw/omap_elm.h index a7f7bacb15..f3db00d55d 100644 --- a/drivers/mtd/nand/raw/omap_elm.h +++ b/drivers/mtd/nand/raw/omap_elm.h @@ -74,12 +74,6 @@ int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count, u32 *error_locations); int elm_config(enum bch_level level); void elm_reset(void); -#ifdef ELM_BASE void elm_init(void); -#else -static inline void elm_init(void) -{ -} -#endif #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_ELM_H */ -- cgit v1.2.3 From 1b4c370fd4e167d0713a00827ff807df9489a3fa Mon Sep 17 00:00:00 2001 From: Prasanth Babu Mantena Date: Tue, 7 Nov 2023 19:12:50 +0530 Subject: board: ti: j721e: Prefix BBAI64 DTB name with directory Update variable name_fdt for beagleboneai64 case with vendor prefix to locate the dtb files. This prefix of vendor specific directory is made to avoid naming issues and match the path on the latest kernel versions. Signed-off-by: Prasanth Babu Mantena Reviewed-by: Neha Malcom Francis --- board/ti/j721e/j721e.env | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env index 4f91859c2e..8edbdd7ad6 100644 --- a/board/ti/j721e/j721e.env +++ b/board/ti/j721e/j721e.env @@ -18,7 +18,7 @@ findfdt= if test $board_name = j721e; then setenv name_fdt ti/k3-j721e-common-proc-board.dtb; fi; if test $board_name = BBONEAI-64-B0-; then - setenv name_fdt k3-j721e-beagleboneai64.dtb; fi; + setenv name_fdt ti/k3-j721e-beagleboneai64.dtb; fi; if test $board_name = j7200; then setenv name_fdt ti/k3-j7200-common-proc-board.dtb; fi; if test $board_name = j721e-eaik || test $board_name = j721e-sk; then -- cgit v1.2.3 From 26a3d6687ea20d3bdc9905494f00bc0bdc4b7696 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Mon, 18 Dec 2023 21:26:26 +0530 Subject: soc: add info to identify the J722S SoC family Include the part number for TI's j722s family of SoC to identify it during boot. Signed-off-by: Vaishnav Achath Signed-off-by: Jayesh Choudhary --- arch/arm/mach-k3/include/mach/hardware.h | 2 ++ drivers/soc/soc_ti_k3.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 20e9634513..e2ab243ae4 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -56,6 +56,7 @@ #define JTAG_ID_PARTNO_AM62AX 0xbb8d #define JTAG_ID_PARTNO_J784S4 0xbb80 #define JTAG_ID_PARTNO_AM62PX 0xbb9d +#define JTAG_ID_PARTNO_J722S 0xbba0 #define K3_SOC_ID(id, ID) \ static inline bool soc_is_##id(void) \ @@ -73,6 +74,7 @@ K3_SOC_ID(am62x, AM62X) K3_SOC_ID(am62ax, AM62AX) K3_SOC_ID(j784s4, J784S4) K3_SOC_ID(am62px, AM62PX) +K3_SOC_ID(j722s, J722S) #define K3_SEC_MGR_SYS_STATUS 0x44234100 #define SYS_STATUS_DEV_TYPE_SHIFT 0 diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index 7b9fdba5bc..3c0d2a2e85 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -51,6 +51,9 @@ static const char *get_family_string(u32 idreg) case JTAG_ID_PARTNO_AM62PX: family = "AM62PX"; break; + case JTAG_ID_PARTNO_J722S: + family = "J722S"; + break; default: family = "Unknown Silicon"; }; -- cgit v1.2.3 From 1e11fcfad5826dfa5233c1f129c01e4a642aa073 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Mon, 18 Dec 2023 21:26:27 +0530 Subject: arm: mach-k3: j722s: introduce clock and device files for J722S SoC Introduce support for J722S SoC. Signed-off-by: Vaishnav Achath Signed-off-by: Jayesh Choudhary --- arch/arm/mach-k3/j722s/Makefile | 6 + arch/arm/mach-k3/j722s/clk-data.c | 312 +++++++++++++++++++++++++++++++++ arch/arm/mach-k3/j722s/dev-data.c | 69 ++++++++ drivers/clk/ti/clk-k3.c | 6 + drivers/power/domain/ti-power-domain.c | 6 + include/k3-clk.h | 1 + include/k3-dev.h | 1 + 7 files changed, 401 insertions(+) create mode 100644 arch/arm/mach-k3/j722s/Makefile create mode 100644 arch/arm/mach-k3/j722s/clk-data.c create mode 100644 arch/arm/mach-k3/j722s/dev-data.c diff --git a/arch/arm/mach-k3/j722s/Makefile b/arch/arm/mach-k3/j722s/Makefile new file mode 100644 index 0000000000..50b0df20a3 --- /dev/null +++ b/arch/arm/mach-k3/j722s/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/j722s/clk-data.c b/arch/arm/mach-k3/j722s/clk-data.c new file mode 100644 index 0000000000..d61e240c3d --- /dev/null +++ b/arch/arm/mach-k3/j722s/clk-data.c @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J722S specific clock platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof . + * + * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + NULL, + NULL, + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + NULL, +}; + +static const char * const clk_32k_rc_sel_out0_parents[] = { + "gluelogic_rcosc_clk_1p0v_97p65k", + "gluelogic_hfosc0_clkout", + "gluelogic_rcosc_clk_1p0v_97p65k", + "gluelogic_lfosc0_clkout", +}; + +static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = { + "board_0_mmc1_clklb_out", + "board_0_mmc1_clk_out", +}; + +static const char * const main_ospi_loopback_clk_sel_out0_parents[] = { + "board_0_ospi0_dqs_out", + "board_0_ospi0_lbclko_out", +}; + +static const char * const main_usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const clkout0_ctrl_out0_parents[] = { + "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", +}; + +static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_gtcclk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const main_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout1_clk", + "postdiv1_16fft_main_1_hsdivout5_clk", +}; + +static const char * const main_timerclkn_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "clk_32k_rc_sel_out0", + "postdiv4_16ff_main_0_hsdivout7_clk", + "gluelogic_rcosc_clkout", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + "board_0_cp_gemac_cpts0_rft_clk_out", + "hsdiv4_16fft_main_1_hsdivout3_clk", + "postdiv4_16ff_main_2_hsdivout6_clk", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +static const char * const wkup_clkout_sel_out0_parents[] = { + NULL, + "gluelogic_lfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "postdiv4_16ff_main_2_hsdivout9_clk", + "clk_32k_rc_sel_out0", + "gluelogic_rcosc_clkout", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clkout_sel_io_out0_parents[] = { + "wkup_clkout_sel_out0", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clksel_out0_parents[] = { + "hsdiv3_16fft_main_15_hsdivout0_clk", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const main_usart0_fclk_sel_out0_parents[] = { + "usart_programmable_clock_divider_out0", + "hsdiv4_16fft_main_1_hsdivout1_clk", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0), + CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0), + CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0, 1920000000), + CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0), + CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0), + CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x68009c, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682098, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0), + CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0), + CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0), + CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0), + CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), + CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x68108c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), + CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), + CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), + CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), + CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0), + CLK_MUX("main_timerclkn_sel_out0", main_timerclkn_sel_out0_parents, 16, 0x1081b0, 0, 4, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000), + CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0), + CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0), + CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0), + CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 5, "board_0_ext_refclk1_out"), + DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"), + DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 9, "board_0_ext_refclk1_out"), + DEV_CLK(16, 10, "gluelogic_rcosc_clkout"), + DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(36, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(36, 2, "main_timerclkn_sel_out0"), + DEV_CLK(36, 3, "gluelogic_hfosc0_clkout"), + DEV_CLK(36, 4, "clk_32k_rc_sel_out0"), + DEV_CLK(36, 5, "postdiv4_16ff_main_0_hsdivout7_clk"), + DEV_CLK(36, 6, "gluelogic_rcosc_clkout"), + DEV_CLK(36, 7, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(36, 8, "board_0_ext_refclk1_out"), + DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"), + DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"), + DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"), + DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), + DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), + DEV_CLK(58, 2, "board_0_mmc1_clk_out"), + DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"), + DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(61, 0, "main_gtcclk_sel_out0"), + DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(61, 6, "board_0_ext_refclk1_out"), + DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 9, "wkup_clksel_out0"), + DEV_CLK(61, 10, "hsdiv3_16fft_main_15_hsdivout0_clk"), + DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(75, 0, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"), + DEV_CLK(75, 3, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"), + DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"), + DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"), + DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(102, 1, "board_0_i2c0_scl_out"), + DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"), + DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"), + DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"), + DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 54, "clkout0_ctrl_out0"), + DEV_CLK(157, 55, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 56, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 74, "mshsi2c_main_0_porscl"), + DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 159, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 173, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"), + DEV_CLK(157, 174, "wkup_clkout_sel_io_out0"), + DEV_CLK(157, 175, "wkup_clkout_sel_out0"), + DEV_CLK(157, 176, "gluelogic_hfosc0_clkout"), + DEV_CLK(157, 178, "dmtimer_dmc1ms_main_0_timer_pwm"), + DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"), + DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(161, 10, "board_0_tck_out"), + DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(170, 2, "board_0_tck_out"), + DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), +}; + +const struct ti_k3_clk_platdata j722s_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = ARRAY_SIZE(clk_list), + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data), +}; diff --git a/arch/arm/mach-k3/j722s/dev-data.c b/arch/arm/mach-k3/j722s/dev-data.c new file mode 100644 index 0000000000..0f2a652b10 --- /dev/null +++ b/arch/arm/mach-k3/j722s/dev-data.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J722S specific device platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof . + * + * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x00400000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[0], NULL), + [1] = PSC_PD(3, &soc_psc_list[0], &soc_pd_list[0]), + [2] = PSC_PD(4, &soc_psc_list[0], &soc_pd_list[1]), + [3] = PSC_PD(13, &soc_psc_list[0], &soc_pd_list[0]), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]), + [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]), + [3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), + [4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), + [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), + [6] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), + [7] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), + [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[7]), + [9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]), + [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]), + [11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[10]), + [12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(16, &soc_lpsc_list[0]), + PSC_DEV(77, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[0]), + PSC_DEV(178, &soc_lpsc_list[1]), + PSC_DEV(179, &soc_lpsc_list[2]), + PSC_DEV(57, &soc_lpsc_list[3]), + PSC_DEV(58, &soc_lpsc_list[4]), + PSC_DEV(161, &soc_lpsc_list[5]), + PSC_DEV(75, &soc_lpsc_list[6]), + PSC_DEV(36, &soc_lpsc_list[7]), + PSC_DEV(102, &soc_lpsc_list[7]), + PSC_DEV(146, &soc_lpsc_list[7]), + PSC_DEV(166, &soc_lpsc_list[8]), + PSC_DEV(135, &soc_lpsc_list[9]), + PSC_DEV(170, &soc_lpsc_list[10]), + PSC_DEV(177, &soc_lpsc_list[11]), + PSC_DEV(55, &soc_lpsc_list[12]), +}; + +const struct ti_k3_pd_platdata j722s_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = ARRAY_SIZE(soc_psc_list), + .num_pd = ARRAY_SIZE(soc_pd_list), + .num_lpsc = ARRAY_SIZE(soc_lpsc_list), + .num_devs = ARRAY_SIZE(soc_dev_list), +}; diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c index 81a112e518..a27e840303 100644 --- a/drivers/clk/ti/clk-k3.c +++ b/drivers/clk/ti/clk-k3.c @@ -97,6 +97,12 @@ static const struct soc_attr ti_k3_soc_clk_data[] = { .family = "AM62PX", .data = &am62px_clk_platdata, }, +#endif +#ifdef CONFIG_SOC_K3_J722S + { + .family = "J722S", + .data = &j722s_clk_platdata, + }, #endif { /* sentinel */ } }; diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c index de6e2b70c8..76a063714c 100644 --- a/drivers/power/domain/ti-power-domain.c +++ b/drivers/power/domain/ti-power-domain.c @@ -110,6 +110,12 @@ static const struct soc_attr ti_k3_soc_pd_data[] = { .family = "AM62PX", .data = &am62px_pd_platdata, }, +#endif +#ifdef CONFIG_SOC_K3_J722S + { + .family = "J722S", + .data = &j722s_pd_platdata, + }, #endif { /* sentinel */ } }; diff --git a/include/k3-clk.h b/include/k3-clk.h index 71e8cfcc26..a14647ff27 100644 --- a/include/k3-clk.h +++ b/include/k3-clk.h @@ -178,6 +178,7 @@ extern const struct ti_k3_clk_platdata am62x_clk_platdata; extern const struct ti_k3_clk_platdata am62ax_clk_platdata; extern const struct ti_k3_clk_platdata j784s4_clk_platdata; extern const struct ti_k3_clk_platdata am62px_clk_platdata; +extern const struct ti_k3_clk_platdata j722s_clk_platdata; struct clk *clk_register_ti_pll(const char *name, const char *parent_name, void __iomem *reg); diff --git a/include/k3-dev.h b/include/k3-dev.h index 4908473ba3..fd7a5f6d67 100644 --- a/include/k3-dev.h +++ b/include/k3-dev.h @@ -82,6 +82,7 @@ extern const struct ti_k3_pd_platdata am62x_pd_platdata; extern const struct ti_k3_pd_platdata am62ax_pd_platdata; extern const struct ti_k3_pd_platdata j784s4_pd_platdata; extern const struct ti_k3_pd_platdata am62px_pd_platdata; +extern const struct ti_k3_pd_platdata j722s_pd_platdata; u8 ti_pd_state(struct ti_pd *pd); u8 lpsc_get_state(struct ti_lpsc *lpsc); -- cgit v1.2.3 From 19bf6f866a60971d1f0d7333e0aa867935f7fd79 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Mon, 18 Dec 2023 21:26:28 +0530 Subject: ram: k3-ddrss: Enable the am62ax's DDR controller for J722S The J722S family of SoCs uses the same DDR controller as found on the AM62A family. Enable this option when building for the J722S family. Signed-off-by: Vaishnav Achath Signed-off-by: Jayesh Choudhary Reviewed-by: Neha Malcom Francis --- drivers/ram/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 81dc2666e8..49ba10e57e 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -65,7 +65,7 @@ choice default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4 default K3_AM64_DDRSS if SOC_K3_AM642 default K3_AM64_DDRSS if SOC_K3_AM625 - default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5 + default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5 || SOC_K3_J722S config K3_J721E_DDRSS bool "Enable J721E DDRSS support" -- cgit v1.2.3 From f314ff8918def3af1d2f4112f541946496ee09e8 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Mon, 18 Dec 2023 21:26:29 +0530 Subject: arch: mach-k3: Introduce basic files to support J722S SoC family Introduce the basic functions and definitions needed to properly initialize TI J722S family of SoCs. Co-developed-by: Vaishnav Achath Signed-off-by: Vaishnav Achath Signed-off-by: Jayesh Choudhary --- arch/arm/mach-k3/Kconfig | 6 +- arch/arm/mach-k3/Makefile | 2 + arch/arm/mach-k3/arm64-mmu.c | 3 +- arch/arm/mach-k3/include/mach/hardware.h | 4 + arch/arm/mach-k3/include/mach/j722s_hardware.h | 83 ++++++++ arch/arm/mach-k3/include/mach/j722s_spl.h | 49 +++++ arch/arm/mach-k3/include/mach/spl.h | 4 + arch/arm/mach-k3/j722s_init.c | 256 +++++++++++++++++++++++++ 8 files changed, 405 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-k3/include/mach/j722s_hardware.h create mode 100644 arch/arm/mach-k3/include/mach/j722s_spl.h create mode 100644 arch/arm/mach-k3/j722s_init.c diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 3c3d971e13..0d5219f241 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -28,6 +28,9 @@ config SOC_K3_J784S4 config SOC_K3_AM62P5 bool "TI's K3 based AM62P5 SoC Family Support" +config SOC_K3_J722S + bool "TI's K3 based J722S SoC Family Support" + endchoice config SYS_SOC @@ -35,7 +38,7 @@ config SYS_SOC config SYS_K3_NON_SECURE_MSRAM_SIZE hex - default 0x80000 if SOC_K3_AM654 || SOC_K3_AM62P5 + default 0x80000 if SOC_K3_AM654 || SOC_K3_AM62P5 || SOC_K3_J722S default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4 default 0x1c0000 if SOC_K3_AM642 default 0x3c000 if SOC_K3_AM625 || SOC_K3_AM62A7 @@ -81,6 +84,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R default 0x7000f290 if SOC_K3_AM62A7 && ARM64 default 0x43c4f290 if SOC_K3_AM62P5 + default 0x43c7f290 if SOC_K3_J722S help Address at which ROM stores the value which determines if SPL is booted up by primary boot media or secondary boot media. diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index d77bf46572..9a3c735327 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_SOC_K3_AM625) += am62x/ obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/ obj-$(CONFIG_SOC_K3_J784S4) += j784s4/ obj-$(CONFIG_SOC_K3_AM62P5) += am62px/ +obj-$(CONFIG_SOC_K3_J722S) += j722s/ obj-$(CONFIG_ARM64) += arm64-mmu.o obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o obj-$(CONFIG_ARM64) += cache.o @@ -21,6 +22,7 @@ obj-$(CONFIG_SOC_K3_AM625) += am625_init.o obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o obj-$(CONFIG_SOC_K3_J784S4) += j784s4_init.o obj-$(CONFIG_SOC_K3_AM62P5) += am62p5_init.o +obj-$(CONFIG_SOC_K3_J722S) += j722s_init.o obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o endif obj-y += common.o security.o diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index 732a9ede02..c26a015166 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -235,7 +235,8 @@ struct mm_region *mem_map = j721s2_mem_map; #endif /* CONFIG_SOC_K3_J721S2 */ #if defined(CONFIG_SOC_K3_AM642) || defined(CONFIG_SOC_K3_AM625) || \ - defined(CONFIG_SOC_K3_AM62A7) || defined(CONFIG_SOC_K3_AM62P5) + defined(CONFIG_SOC_K3_AM62A7) || defined(CONFIG_SOC_K3_AM62P5) || \ + defined(CONFIG_SOC_K3_J722S) /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3) diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index e2ab243ae4..90a65eeaff 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -41,6 +41,10 @@ #include "am62p_hardware.h" #endif +#ifdef CONFIG_SOC_K3_J722S +#include "j722s_hardware.h" +#endif + /* Assuming these addresses and definitions stay common across K3 devices */ #define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14) #define JTAG_ID_VARIANT_SHIFT 28 diff --git a/arch/arm/mach-k3/include/mach/j722s_hardware.h b/arch/arm/mach-k3/include/mach/j722s_hardware.h new file mode 100644 index 0000000000..13cd8924d9 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/j722s_hardware.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K3: J722S SoC definitions, structures etc. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef __ASM_ARCH_J722S_HARDWARE_H +#define __ASM_ARCH_J722S_HARDWARE_H + +#include +#ifndef __ASSEMBLY__ +#include +#endif + +#define PADCFG_MMR0_BASE 0x04080000 +#define PADCFG_MMR1_BASE 0x000f0000 +#define CTRL_MMR0_BASE 0x00100000 +#define MCU_CTRL_MMR0_BASE 0x04500000 +#define WKUP_CTRL_MMR0_BASE 0x43000000 + +#define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7 +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10) +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10 +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13) +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13 + +/* Primary Bootmode MMC Config macros */ +#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4 +#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2 +#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1 +#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0 + +/* Primary Bootmode USB Config macros */ +#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1 +#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02 + +/* Backup Bootmode USB Config macros */ +#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01 + +/* + * The CTRL_MMR0 memory space is divided into several equally-spaced + * partitions, so defining the partition size allows us to determine + * register addresses common to those partitions. + */ +#define CTRL_MMR0_PARTITION_SIZE 0x4000 + +/* + * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism + * shared register definitions. The same registers are also used for + * PADCFG_MMR lock/kick-mechanism. + */ +#define CTRLMMR_LOCK_KICK0 0x1008 +#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 +#define CTRLMMR_LOCK_KICK1 0x100c +#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a + +#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038) +#define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c) +#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7) + +#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058) +#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3) + +#define ROM_EXTENDED_BOOT_DATA_INFO 0x43c7f1e0 + +#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290 + +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000 + +#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) + +static const u32 put_device_ids[] = {}; + +static const u32 put_core_ids[] = {}; + +#endif + +#endif /* __ASM_ARCH_J722S_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/j722s_spl.h b/arch/arm/mach-k3/include/mach/j722s_spl.h new file mode 100644 index 0000000000..b529db6189 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/j722s_spl.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef _ASM_ARCH_J722S_SPL_H_ +#define _ASM_ARCH_J722S_SPL_H_ + +/* Primary BootMode devices */ +#define BOOT_DEVICE_SPI_NAND 0x00 +#define BOOT_DEVICE_RAM 0xFF +#define BOOT_DEVICE_OSPI 0x01 +#define BOOT_DEVICE_QSPI 0x02 +#define BOOT_DEVICE_SPI 0x03 +#define BOOT_DEVICE_CPGMAC 0x04 +#define BOOT_DEVICE_ETHERNET_RGMII 0x04 +#define BOOT_DEVICE_ETHERNET_RMII 0x05 +#define BOOT_DEVICE_I2C 0x06 +#define BOOT_DEVICE_UART 0x07 +#define BOOT_DEVICE_MMC 0x08 +#define BOOT_DEVICE_EMMC 0x09 + +#define BOOT_DEVICE_USB 0x2A +#define BOOT_DEVICE_DFU 0x0A +#define BOOT_DEVICE_GPMC_NAND 0x0B +#define BOOT_DEVICE_GPMC_NOR 0x0C +#define BOOT_DEVICE_XSPI 0x0E +#define BOOT_DEVICE_NOBOOT 0x0F + +/* U-Boot used aliases */ +#define BOOT_DEVICE_ETHERNET 0x04 +#define BOOT_DEVICE_SPINAND 0x10 +#define BOOT_DEVICE_MMC2 0x08 +#define BOOT_DEVICE_MMC1 0x09 +/* Invalid */ +#define BOOT_DEVICE_MMC2_2 0x1F + +/* Backup BootMode devices */ +#define BACKUP_BOOT_DEVICE_DFU 0x01 +#define BACKUP_BOOT_DEVICE_UART 0x03 +#define BACKUP_BOOT_DEVICE_ETHERNET 0x04 +#define BACKUP_BOOT_DEVICE_MMC 0x05 +#define BACKUP_BOOT_DEVICE_SPI 0x06 +#define BACKUP_BOOT_DEVICE_I2C 0x07 +#define BACKUP_BOOT_DEVICE_USB 0x09 + +#define K3_PRIMARY_BOOTMODE 0x0 + +#endif /* _ASM_ARCH_J722S_SPL_H_ */ diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h index 86e2fc0327..827fa93010 100644 --- a/arch/arm/mach-k3/include/mach/spl.h +++ b/arch/arm/mach-k3/include/mach/spl.h @@ -38,4 +38,8 @@ #include "am62p_spl.h" #endif +#ifdef CONFIG_SOC_K3_J722S +#include "j722s_spl.h" +#endif + #endif /* _ASM_ARCH_SPL_H_ */ diff --git a/arch/arm/mach-k3/j722s_init.c b/arch/arm/mach-k3/j722s_init.c new file mode 100644 index 0000000000..df7a1ce1b9 --- /dev/null +++ b/arch/arm/mach-k3/j722s_init.c @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * J722S: SoC specific initialization + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include +#include "common.h" +#include +#include +#include + +struct fwl_data cbass_main_fwls[] = { + { "FSS_DAT_REG3", 7, 8 }, +}; + +/* + * This uninitialized global variable would normal end up in the .bss section, + * but the .bss is cleared between writing and reading this variable, so move + * it to the .data section. + */ +u32 bootindex __section(".data"); +static struct rom_extended_boot_data bootdata __section(".data"); + +static void store_boot_info_from_rom(void) +{ + bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); + memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO, + sizeof(struct rom_extended_boot_data)); +} + +static void ctrl_mmr_unlock(void) +{ + /* Unlock all WKUP_CTRL_MMR0 module registers */ + mmr_unlock(WKUP_CTRL_MMR0_BASE, 0); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 1); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 2); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 3); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 4); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 5); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 6); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 7); + + /* Unlock all CTRL_MMR0 module registers */ + mmr_unlock(CTRL_MMR0_BASE, 0); + mmr_unlock(CTRL_MMR0_BASE, 1); + mmr_unlock(CTRL_MMR0_BASE, 2); + mmr_unlock(CTRL_MMR0_BASE, 4); + mmr_unlock(CTRL_MMR0_BASE, 5); + mmr_unlock(CTRL_MMR0_BASE, 6); + + /* Unlock all MCU_CTRL_MMR0 module registers */ + mmr_unlock(MCU_CTRL_MMR0_BASE, 0); + mmr_unlock(MCU_CTRL_MMR0_BASE, 1); + mmr_unlock(MCU_CTRL_MMR0_BASE, 2); + mmr_unlock(MCU_CTRL_MMR0_BASE, 3); + mmr_unlock(MCU_CTRL_MMR0_BASE, 4); + mmr_unlock(MCU_CTRL_MMR0_BASE, 6); + + /* Unlock PADCFG_CTRL_MMR padconf registers */ + mmr_unlock(PADCFG_MMR0_BASE, 1); + mmr_unlock(PADCFG_MMR1_BASE, 1); +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + if (IS_ENABLED(CONFIG_CPU_V7R)) + setup_k3_mpu_regions(); + + /* + * Cannot delay this further as there is a chance that + * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section. + */ + store_boot_info_from_rom(); + + ctrl_mmr_unlock(); + + /* Init DM early */ + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed: %d\n", ret); + + /* + * Process pinctrl for the serial0 and serial3, aka WKUP_UART0 and + * MAIN_UART1 modules and continue regardless of the result of pinctrl. + * Do this without probing the device, but instead by searching the + * device that would request the given sequence number if probed. The + * UARTs will be used by the DM firmware and TIFS firmware images + * respectively and the firmware depend on SPL to initialize the pin + * settings. + */ + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev); + if (!ret) + pinctrl_select_state(dev, "default"); + + if (IS_ENABLED(CONFIG_K3_EARLY_CONS)) { + /* + * Allow establishing an early console as required for example + * when doing a UART-based boot. Note that this console may not + * "survive" through a SYSFW PM-init step and will need a re-init + * in some way due to changing module clock frequencies. + */ + ret = early_console_init(); + if (ret) + panic("early_console_init() failed: %d\n", ret); + } + + if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) { + /* + * Configure and start up system controller firmware. Provide + * the U-Boot console init function to the SYSFW post-PM + * configuration callback hook, effectively switching on (or + * over) the console output. + */ + ret = is_rom_loaded_sysfw(&bootdata); + if (!ret) + panic("ROM has not loaded TIFS firmware\n"); + + k3_sysfw_loader(true, NULL, NULL); + } + + /* + * Force probe of clk_k3 driver here to ensure basic default clock + * configuration is always done. + */ + if (IS_ENABLED(CONFIG_SPL_CLK_K3)) { + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(ti_clk), + &dev); + if (ret) + printf("Failed to initialize clk-k3!\n"); + } + + preloader_console_init(); + + /* Output System Firmware version info */ + k3_sysfw_print_ver(); + + /* Disable ROM configured firewalls right after loading sysfw */ + remove_fwl_configs(cbass_main_fwls, ARRAY_SIZE(cbass_main_fwls)); + + if (IS_ENABLED(CONFIG_K3_AM62A_DDRSS)) { + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("DRAM init failed: %d\n", ret); + } + + debug("j722s_init: %s done\n", __func__); +} + +static u32 __get_backup_bootmedia(u32 devstat) +{ + u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; + u32 bkup_bootmode_cfg = + (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; + + switch (bkup_bootmode) { + case BACKUP_BOOT_DEVICE_UART: + return BOOT_DEVICE_UART; + + case BACKUP_BOOT_DEVICE_USB: + return BOOT_DEVICE_USB; + + case BACKUP_BOOT_DEVICE_ETHERNET: + return BOOT_DEVICE_ETHERNET; + + case BACKUP_BOOT_DEVICE_MMC: + if (bkup_bootmode_cfg) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BACKUP_BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BACKUP_BOOT_DEVICE_I2C: + return BOOT_DEVICE_I2C; + + case BACKUP_BOOT_DEVICE_DFU: + if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + }; + + return BOOT_DEVICE_RAM; +} + +static u32 __get_primary_bootmedia(u32 devstat) +{ + u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_OSPI: + fallthrough; + case BOOT_DEVICE_QSPI: + fallthrough; + case BOOT_DEVICE_XSPI: + fallthrough; + case BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BOOT_DEVICE_ETHERNET_RGMII: + fallthrough; + case BOOT_DEVICE_ETHERNET_RMII: + return BOOT_DEVICE_ETHERNET; + + case BOOT_DEVICE_EMMC: + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_SPI_NAND: + return BOOT_DEVICE_SPINAND; + + case BOOT_DEVICE_MMC: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> + MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_DFU: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + + case BOOT_DEVICE_NOBOOT: + return BOOT_DEVICE_RAM; + } + + return bootmode; +} + +u32 spl_boot_device(void) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmedia; + + if (bootindex == K3_PRIMARY_BOOTMODE) + bootmedia = __get_primary_bootmedia(devstat); + else + bootmedia = __get_backup_bootmedia(devstat); + + debug("j722s_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n", + __func__, devstat, bootmedia, bootindex); + return bootmedia; +} -- cgit v1.2.3 From 64f207873fc7d0d9c2acfda169a409fb3a84bd4a Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Mon, 18 Dec 2023 21:26:30 +0530 Subject: firmware: ti_sci_static_data: Add static DMA channel Include the static DMA channel data for using DMA at SPL stage for J722S SoC family. Signed-off-by: Vaishnav Achath Signed-off-by: Jayesh Choudhary --- drivers/firmware/ti_sci_static_data.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h index 00da76a3cb..269f6d46d5 100644 --- a/drivers/firmware/ti_sci_static_data.h +++ b/drivers/firmware/ti_sci_static_data.h @@ -85,7 +85,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = { #endif /* CONFIG_SOC_K3_J721S2 */ #if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7) || \ - IS_ENABLED(CONFIG_SOC_K3_AM62P5) + IS_ENABLED(CONFIG_SOC_K3_AM62P5) || IS_ENABLED(CONFIG_SOC_K3_J722S) static struct ti_sci_resource_static_data rm_static_data[] = { /* BC channels */ -- cgit v1.2.3 From b8567f6f5a1e7d4c844f29f3b3d01f230c0f1e76 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Mon, 18 Dec 2023 21:26:31 +0530 Subject: board: ti: Introduce basic board files for the J722S family Introduce the basic files needed to support the TI J722S family of SoCs. Co-developed-by: Vaishnav Achath Signed-off-by: Vaishnav Achath Signed-off-by: Jayesh Choudhary --- arch/arm/mach-k3/Kconfig | 1 + board/ti/j722s/Kconfig | 52 ++ board/ti/j722s/MAINTAINERS | 9 + board/ti/j722s/Makefile | 7 + board/ti/j722s/board-cfg.yaml | 36 ++ board/ti/j722s/evm.c | 71 +++ board/ti/j722s/j722s.env | 23 + board/ti/j722s/pm-cfg.yaml | 12 + board/ti/j722s/rm-cfg.yaml | 1149 +++++++++++++++++++++++++++++++++++++++ board/ti/j722s/sec-cfg.yaml | 379 +++++++++++++ board/ti/j722s/tifs-rm-cfg.yaml | 1005 ++++++++++++++++++++++++++++++++++ 11 files changed, 2744 insertions(+) create mode 100644 board/ti/j722s/Kconfig create mode 100644 board/ti/j722s/MAINTAINERS create mode 100644 board/ti/j722s/Makefile create mode 100644 board/ti/j722s/board-cfg.yaml create mode 100644 board/ti/j722s/evm.c create mode 100644 board/ti/j722s/j722s.env create mode 100644 board/ti/j722s/pm-cfg.yaml create mode 100644 board/ti/j722s/rm-cfg.yaml create mode 100644 board/ti/j722s/sec-cfg.yaml create mode 100644 board/ti/j722s/tifs-rm-cfg.yaml diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 0d5219f241..cad27376cf 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -207,5 +207,6 @@ source "board/ti/am62px/Kconfig" source "board/ti/j721e/Kconfig" source "board/siemens/iot2050/Kconfig" source "board/ti/j721s2/Kconfig" +source "board/ti/j722s/Kconfig" source "board/ti/j784s4/Kconfig" endif diff --git a/board/ti/j722s/Kconfig b/board/ti/j722s/Kconfig new file mode 100644 index 0000000000..569f40487f --- /dev/null +++ b/board/ti/j722s/Kconfig @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# + +choice + prompt "TI K3 J722S based boards" + optional + +config TARGET_J722S_A53_EVM + bool "TI K3 based J722S EVM running on A53" + select ARM64 + select BINMAN + imply BOARD + imply SPL_BOARD + imply TI_I2C_BOARD_DETECT + +config TARGET_J722S_R5_EVM + bool "TI K3 based J722S EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + imply TI_I2C_BOARD_DETECT + +endchoice + +if TARGET_J722S_R5_EVM || TARGET_J722S_A53_EVM + +config SYS_BOARD + default "j722s" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "j722s_evm" + +source "board/ti/common/Kconfig" + +endif + +if TARGET_J722S_R5_EVM + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +endif diff --git a/board/ti/j722s/MAINTAINERS b/board/ti/j722s/MAINTAINERS new file mode 100644 index 0000000000..7908c30def --- /dev/null +++ b/board/ti/j722s/MAINTAINERS @@ -0,0 +1,9 @@ +J722S BOARD +M: Vaishnav Achath +M: Jayesh Choudhary +M: Tom Rini +S: Maintained +F: board/ti/j722s/ +F: include/configs/j722s_evm.h +F: configs/j722s_evm_r5_defconfig +F: configs/j722s_evm_a53_defconfig diff --git a/board/ti/j722s/Makefile b/board/ti/j722s/Makefile new file mode 100644 index 0000000000..921afdff27 --- /dev/null +++ b/board/ti/j722s/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evm.o diff --git a/board/ti/j722s/board-cfg.yaml b/board/ti/j722s/board-cfg.yaml new file mode 100644 index 0000000000..3758f569a9 --- /dev/null +++ b/board/ti/j722s/board-cfg.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for J722S +# + +--- + +board-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable: 0x5A + main_isolation_hostid: 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor: 0x1 + scaling_profile: 0x1 + disable_main_nav_secure_proxy: 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size: 0x0 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables: 0x00 + trace_src_enables: 0x00 diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c new file mode 100644 index 0000000000..aa273e3dd4 --- /dev/null +++ b/board/ti/j722s/evm.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board specific initialization for J722S platforms + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../common/board_detect.h" + +#ifdef CONFIG_TI_I2C_BOARD_DETECT +/* + * Functions specific to EVM of J722S family. + */ + +#define board_is_j722s() board_ti_k3_is("J722SX-EVM") + +int do_board_detect(void) +{ + int ret; + + if (board_ti_was_eeprom_read()) + return 0; + + ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS, + CONFIG_EEPROM_CHIP_ADDRESS); + if (ret) { + pr_err("Reading on-board EEPROM at 0x%02x failed %d\n", + CONFIG_EEPROM_CHIP_ADDRESS, ret); + } + + return ret; +} + +int checkboard(void) +{ + struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA; + + if (do_board_detect()) + /* EEPROM not populated */ + printf("Board: %s rev %s\n", "J722SX-EVM", "E1"); + else + printf("Board: %s rev %s\n", ep->name, ep->version); + + return 0; +} + +#endif + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} diff --git a/board/ti/j722s/j722s.env b/board/ti/j722s/j722s.env new file mode 100644 index 0000000000..28fb1776a4 --- /dev/null +++ b/board/ti/j722s/j722s.env @@ -0,0 +1,23 @@ +#include +#include +#include +#include +#if CONFIG_CMD_REMOTEPROC +#include +#endif + +default_device_tree=ti/k3-j722s-evm.dtb +findfdt= + setenv name_fdt ${default_device_tree}; + setenv fdtfile ${name_fdt} +name_kern=Image +console=ttyS2,115200n8 +args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000 + ${mtdparts} +run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr} + +boot=mmc +mmcdev=1 +bootpart=1:2 +bootdir=/boot +rd_spec=- diff --git a/board/ti/j722s/pm-cfg.yaml b/board/ti/j722s/pm-cfg.yaml new file mode 100644 index 0000000000..4eb0188029 --- /dev/null +++ b/board/ti/j722s/pm-cfg.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for J722S +# + +--- + +pm-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 diff --git a/board/ti/j722s/rm-cfg.yaml b/board/ti/j722s/rm-cfg.yaml new file mode 100644 index 0000000000..2639c9935e --- /dev/null +++ b/board/ti/j722s/rm-cfg.yaml @@ -0,0 +1,1149 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for J722S +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size : 356 + host_cfg_entries: + - #1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #2 + host_id: 20 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #3 + host_id: 22 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #4 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #5 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #6 + host_id: 38 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - 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+ start_resource: 3584 + num_resource: 32 + type: 12827 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 32 + type: 12828 + host_id: 128 + reserved: 0 diff --git a/board/ti/j722s/sec-cfg.yaml b/board/ti/j722s/sec-cfg.yaml new file mode 100644 index 0000000000..bbe1049a4f --- /dev/null +++ b/board/ti/j722s/sec-cfg.yaml @@ -0,0 +1,379 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Security management configuration for J722S +# + +--- + +sec-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - #1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - #1 + host_id: 0 + supervisor_host_id: 0 + - #2 + host_id: 0 + supervisor_host_id: 0 + - #3 + host_id: 0 + supervisor_host_id: 0 + - #4 + host_id: 0 + supervisor_host_id: 0 + - #5 + host_id: 0 + supervisor_host_id: 0 + - #6 + host_id: 0 + supervisor_host_id: 0 + - #7 + host_id: 0 + supervisor_host_id: 0 + - #8 + host_id: 0 + supervisor_host_id: 0 + - #9 + host_id: 0 + supervisor_host_id: 0 + - #10 + host_id: 0 + supervisor_host_id: 0 + - #11 + host_id: 0 + supervisor_host_id: 0 + - #12 + host_id: 0 + supervisor_host_id: 0 + - #13 + host_id: 0 + supervisor_host_id: 0 + - #14 + host_id: 0 + supervisor_host_id: 0 + - #15 + host_id: 0 + supervisor_host_id: 0 + - #16 + host_id: 0 + supervisor_host_id: 0 + - #17 + host_id: 0 + supervisor_host_id: 0 + - #18 + host_id: 0 + supervisor_host_id: 0 + - #19 + host_id: 0 + supervisor_host_id: 0 + - #20 + host_id: 0 + supervisor_host_id: 0 + - #21 + host_id: 0 + supervisor_host_id: 0 + - #22 + host_id: 0 + supervisor_host_id: 0 + - #23 + host_id: 0 + supervisor_host_id: 0 + - #24 + host_id: 0 + supervisor_host_id: 0 + - #25 + host_id: 0 + supervisor_host_id: 0 + - #26 + host_id: 0 + supervisor_host_id: 0 + - #27 + host_id: 0 + supervisor_host_id: 0 + - #28 + host_id: 0 + supervisor_host_id: 0 + - #29 + host_id: 0 + supervisor_host_id: 0 + - #30 + host_id: 0 + supervisor_host_id: 0 + - #31 + host_id: 0 + supervisor_host_id: 0 + - #32 + host_id: 0 + supervisor_host_id: 0 + otp_config: + subhdr: + magic: 0x4081 + size: 69 + write_host_id: 0 + otp_entry: + - #1 + host_id: 0 + host_perms: 0 + - #2 + host_id: 0 + host_perms: 0 + - #3 + host_id: 0 + host_perms: 0 + - #4 + host_id: 0 + host_perms: 0 + - #5 + host_id: 0 + host_perms: 0 + - #6 + host_id: 0 + host_perms: 0 + - #7 + host_id: 0 + host_perms: 0 + - #8 + host_id: 0 + host_perms: 0 + - #9 + host_id: 0 + host_perms: 0 + - #10 + host_id: 0 + host_perms: 0 + - #11 + host_id: 0 + host_perms: 0 + - #12 + host_id: 0 + host_perms: 0 + - #13 + host_id: 0 + host_perms: 0 + - #14 + host_id: 0 + host_perms: 0 + - #15 + host_id: 0 + host_perms: 0 + - #16 + host_id: 0 + host_perms: 0 + - #17 + host_id: 0 + host_perms: 0 + - #18 + host_id: 0 + host_perms: 0 + - #19 + host_id: 0 + host_perms: 0 + - #20 + host_id: 0 + host_perms: 0 + - #21 + host_id: 0 + host_perms: 0 + - #22 + host_id: 0 + host_perms: 0 + - #23 + host_id: 0 + host_perms: 0 + - #24 + host_id: 0 + host_perms: 0 + - #25 + host_id: 0 + host_perms: 0 + - #26 + host_id: 0 + host_perms: 0 + - #27 + host_id: 0 + host_perms: 0 + - #28 + host_id: 0 + host_perms: 0 + - #29 + host_id: 0 + host_perms: 0 + - #30 + host_id: 0 + host_perms: 0 + - #31 + host_id: 0 + host_perms: 0 + - #32 + host_id: 0 + host_perms: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci : 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size : 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0x5A + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock : 0x5A + allow_wildcard_unlock : 0x5A + allowed_debug_level_rsvd: 0 + rsvd: 0 + min_cert_rev : 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender : 0 + handover_to_host_id : 0 + rsvd: [0, 0, 0, 0] diff --git a/board/ti/j722s/tifs-rm-cfg.yaml b/board/ti/j722s/tifs-rm-cfg.yaml new file mode 100644 index 0000000000..a06af08e58 --- /dev/null +++ b/board/ti/j722s/tifs-rm-cfg.yaml @@ -0,0 +1,1005 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for J722S +# + +--- + +tifs-rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size : 356 + host_cfg_entries: + - #1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #2 + host_id: 20 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #3 + host_id: 22 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #4 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #5 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #6 + host_id: 38 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #32 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + resasg: + subhdr: + magic: 0x7B25 + size: 8 + resasg_entries_size: 1008 + reserved: 0 + resasg_entries: + - + start_resource: 0 + num_resource: 16 + type: 1677 + host_id: 12 + reserved: 0 + - + start_resource: 16 + num_resource: 6 + type: 1677 + host_id: 20 + reserved: 0 + - + start_resource: 16 + num_resource: 6 + type: 1677 + host_id: 36 + reserved: 0 + - + start_resource: 22 + num_resource: 2 + type: 1677 + host_id: 30 + reserved: 0 + - + start_resource: 24 + num_resource: 4 + type: 1677 + host_id: 22 + reserved: 0 + - + start_resource: 28 + num_resource: 4 + type: 1677 + host_id: 38 + reserved: 0 + - + start_resource: 57 + num_resource: 16 + type: 1678 + host_id: 12 + reserved: 0 + - + start_resource: 73 + num_resource: 5 + type: 1678 + host_id: 20 + reserved: 0 + - + start_resource: 73 + num_resource: 5 + type: 1678 + host_id: 36 + reserved: 0 + - + start_resource: 78 + num_resource: 2 + type: 1678 + host_id: 30 + reserved: 0 + - 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+ start_resource: 13 + num_resource: 3 + type: 1936 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1936 + host_id: 38 + reserved: 0 + - + start_resource: 19 + num_resource: 64 + type: 1937 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 64 + type: 1937 + host_id: 36 + reserved: 0 + - + start_resource: 83 + num_resource: 8 + type: 1938 + host_id: 12 + reserved: 0 + - + start_resource: 91 + num_resource: 8 + type: 1939 + host_id: 12 + reserved: 0 + - + start_resource: 99 + num_resource: 10 + type: 1942 + host_id: 12 + reserved: 0 + - + start_resource: 109 + num_resource: 3 + type: 1942 + host_id: 35 + reserved: 0 + - + start_resource: 109 + num_resource: 3 + type: 1942 + host_id: 36 + reserved: 0 + - + start_resource: 112 + num_resource: 3 + type: 1942 + host_id: 30 + reserved: 0 + - + start_resource: 115 + num_resource: 3 + type: 1942 + host_id: 38 + reserved: 0 + - + start_resource: 118 + num_resource: 16 + type: 1943 + host_id: 12 + reserved: 0 + - + start_resource: 118 + num_resource: 16 + type: 1943 + host_id: 36 + reserved: 0 + - + start_resource: 134 + num_resource: 8 + type: 1944 + host_id: 12 + reserved: 0 + - + start_resource: 134 + num_resource: 8 + type: 1945 + host_id: 12 + reserved: 0 + - + start_resource: 142 + num_resource: 8 + type: 1946 + host_id: 12 + reserved: 0 + - + start_resource: 142 + num_resource: 8 + type: 1947 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1955 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1955 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1955 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1955 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1955 + host_id: 38 + reserved: 0 + - + start_resource: 19 + num_resource: 8 + type: 1956 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 8 + type: 1956 + host_id: 36 + reserved: 0 + - + start_resource: 27 + num_resource: 1 + type: 1957 + host_id: 12 + reserved: 0 + - + start_resource: 28 + num_resource: 1 + type: 1958 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1961 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1961 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1961 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1961 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1961 + host_id: 38 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1962 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1962 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1962 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1962 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1962 + host_id: 38 + reserved: 0 + - + start_resource: 19 + num_resource: 1 + type: 1963 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 1 + type: 1963 + host_id: 36 + reserved: 0 + - + start_resource: 19 + num_resource: 16 + type: 1964 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 16 + type: 1964 + host_id: 36 + reserved: 0 + - + start_resource: 20 + num_resource: 1 + type: 1965 + host_id: 12 + reserved: 0 + - + start_resource: 35 + num_resource: 8 + type: 1966 + host_id: 12 + reserved: 0 + - + start_resource: 21 + num_resource: 1 + type: 1967 + host_id: 12 + reserved: 0 + - + start_resource: 35 + num_resource: 8 + type: 1968 + host_id: 12 + reserved: 0 + - + start_resource: 22 + num_resource: 1 + type: 1969 + host_id: 12 + reserved: 0 + - + start_resource: 43 + num_resource: 8 + type: 1970 + host_id: 12 + reserved: 0 + - + start_resource: 23 + num_resource: 1 + type: 1971 + host_id: 12 + reserved: 0 + - + start_resource: 43 + num_resource: 8 + type: 1972 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 1 + type: 2112 + host_id: 128 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 2122 + host_id: 12 + reserved: 0 + - + start_resource: 8 + num_resource: 4 + type: 12750 + host_id: 12 + reserved: 0 + - + start_resource: 12 + num_resource: 20 + type: 12750 + host_id: 38 + reserved: 0 + - + start_resource: 32 + num_resource: 8 + type: 12750 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 8 + type: 12751 + host_id: 38 + reserved: 0 + - + start_resource: 0 + num_resource: 4 + type: 12769 + host_id: 12 + reserved: 0 + - + start_resource: 4 + num_resource: 20 + type: 12769 + host_id: 38 + reserved: 0 + - + start_resource: 24 + num_resource: 8 + type: 12769 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 8 + type: 12770 + host_id: 38 + reserved: 0 + - + start_resource: 0 + num_resource: 2 + type: 12810 + host_id: 12 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 12810 + host_id: 20 + reserved: 0 + - + start_resource: 4 + num_resource: 2 + type: 12810 + host_id: 22 + reserved: 0 + - + start_resource: 22 + num_resource: 18 + type: 12810 + host_id: 38 + reserved: 0 + - + start_resource: 1536 + num_resource: 8 + type: 12823 + host_id: 128 + reserved: 0 + - + start_resource: 2048 + num_resource: 8 + type: 12824 + host_id: 128 + reserved: 0 + - + start_resource: 2560 + num_resource: 8 + type: 12825 + host_id: 128 + reserved: 0 + - + start_resource: 3072 + num_resource: 32 + type: 12826 + host_id: 128 + reserved: 0 + - + start_resource: 3584 + num_resource: 32 + type: 12827 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 32 + type: 12828 + host_id: 128 + reserved: 0 -- cgit v1.2.3 From 6398de0abf5b6707a691c4dadf279c754efdd803 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Mon, 18 Dec 2023 21:26:32 +0530 Subject: dma: ti: k3-udma: Add DMA PSIL mappings for CSI for J722S PSIL mapping is same as AM62P other than extra instances of CSI-RX. Reuse the same file and add CSI PSIL mapping there. Signed-off-by: Vaishnav Achath Signed-off-by: Jayesh Choudhary --- drivers/dma/ti/Makefile | 1 + drivers/dma/ti/k3-psil-am62p.c | 129 +++++++++++++++++++++++++++++++++++++++++ drivers/dma/ti/k3-psil.c | 2 + 3 files changed, 132 insertions(+) diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile index e4732518b3..94ec13ba7c 100644 --- a/drivers/dma/ti/Makefile +++ b/drivers/dma/ti/Makefile @@ -11,3 +11,4 @@ k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o k3-psil-data-$(CONFIG_SOC_K3_AM62A7) += k3-psil-am62a.o k3-psil-data-$(CONFIG_SOC_K3_J784S4) += k3-psil-j784s4.o k3-psil-data-$(CONFIG_SOC_K3_AM62P5) += k3-psil-am62p.o +k3-psil-data-$(CONFIG_SOC_K3_J722S) += k3-psil-am62p.o diff --git a/drivers/dma/ti/k3-psil-am62p.c b/drivers/dma/ti/k3-psil-am62p.c index fda27a42bf..8739bf41b5 100644 --- a/drivers/dma/ti/k3-psil-am62p.c +++ b/drivers/dma/ti/k3-psil-am62p.c @@ -144,6 +144,135 @@ static struct psil_ep am62p_src_ep_map[] = { PSIL_CSI2RX(0x501d), PSIL_CSI2RX(0x501e), PSIL_CSI2RX(0x501f), + PSIL_CSI2RX(0x5000), + PSIL_CSI2RX(0x5001), + PSIL_CSI2RX(0x5002), + PSIL_CSI2RX(0x5003), + PSIL_CSI2RX(0x5004), + PSIL_CSI2RX(0x5005), + PSIL_CSI2RX(0x5006), + PSIL_CSI2RX(0x5007), + PSIL_CSI2RX(0x5008), + PSIL_CSI2RX(0x5009), + PSIL_CSI2RX(0x500a), + PSIL_CSI2RX(0x500b), + PSIL_CSI2RX(0x500c), + PSIL_CSI2RX(0x500d), + PSIL_CSI2RX(0x500e), + PSIL_CSI2RX(0x500f), + PSIL_CSI2RX(0x5010), + PSIL_CSI2RX(0x5011), + PSIL_CSI2RX(0x5012), + PSIL_CSI2RX(0x5013), + PSIL_CSI2RX(0x5014), + PSIL_CSI2RX(0x5015), + PSIL_CSI2RX(0x5016), + PSIL_CSI2RX(0x5017), + PSIL_CSI2RX(0x5018), + PSIL_CSI2RX(0x5019), + PSIL_CSI2RX(0x501a), + PSIL_CSI2RX(0x501b), + PSIL_CSI2RX(0x501c), + PSIL_CSI2RX(0x501d), + PSIL_CSI2RX(0x501e), + PSIL_CSI2RX(0x501f), + /* CSIRX 1-3 (only for J722S) */ + PSIL_CSI2RX(0x5100), + PSIL_CSI2RX(0x5101), + PSIL_CSI2RX(0x5102), + PSIL_CSI2RX(0x5103), + PSIL_CSI2RX(0x5104), + PSIL_CSI2RX(0x5105), + PSIL_CSI2RX(0x5106), + PSIL_CSI2RX(0x5107), + PSIL_CSI2RX(0x5108), + PSIL_CSI2RX(0x5109), + PSIL_CSI2RX(0x510a), + PSIL_CSI2RX(0x510b), + PSIL_CSI2RX(0x510c), + PSIL_CSI2RX(0x510d), + PSIL_CSI2RX(0x510e), + PSIL_CSI2RX(0x510f), + PSIL_CSI2RX(0x5110), + PSIL_CSI2RX(0x5111), + PSIL_CSI2RX(0x5112), + PSIL_CSI2RX(0x5113), + PSIL_CSI2RX(0x5114), + PSIL_CSI2RX(0x5115), + PSIL_CSI2RX(0x5116), + PSIL_CSI2RX(0x5117), + PSIL_CSI2RX(0x5118), + PSIL_CSI2RX(0x5119), + PSIL_CSI2RX(0x511a), + PSIL_CSI2RX(0x511b), + PSIL_CSI2RX(0x511c), + PSIL_CSI2RX(0x511d), + PSIL_CSI2RX(0x511e), + PSIL_CSI2RX(0x511f), + PSIL_CSI2RX(0x5200), + PSIL_CSI2RX(0x5201), + PSIL_CSI2RX(0x5202), + PSIL_CSI2RX(0x5203), + PSIL_CSI2RX(0x5204), + PSIL_CSI2RX(0x5205), + PSIL_CSI2RX(0x5206), + PSIL_CSI2RX(0x5207), + PSIL_CSI2RX(0x5208), + PSIL_CSI2RX(0x5209), + PSIL_CSI2RX(0x520a), + PSIL_CSI2RX(0x520b), + PSIL_CSI2RX(0x520c), + PSIL_CSI2RX(0x520d), + PSIL_CSI2RX(0x520e), + PSIL_CSI2RX(0x520f), + PSIL_CSI2RX(0x5210), + PSIL_CSI2RX(0x5211), + PSIL_CSI2RX(0x5212), + PSIL_CSI2RX(0x5213), + PSIL_CSI2RX(0x5214), + PSIL_CSI2RX(0x5215), + PSIL_CSI2RX(0x5216), + PSIL_CSI2RX(0x5217), + PSIL_CSI2RX(0x5218), + PSIL_CSI2RX(0x5219), + PSIL_CSI2RX(0x521a), + PSIL_CSI2RX(0x521b), + PSIL_CSI2RX(0x521c), + PSIL_CSI2RX(0x521d), + PSIL_CSI2RX(0x521e), + PSIL_CSI2RX(0x521f), + PSIL_CSI2RX(0x5300), + PSIL_CSI2RX(0x5301), + PSIL_CSI2RX(0x5302), + PSIL_CSI2RX(0x5303), + PSIL_CSI2RX(0x5304), + PSIL_CSI2RX(0x5305), + PSIL_CSI2RX(0x5306), + PSIL_CSI2RX(0x5307), + PSIL_CSI2RX(0x5308), + PSIL_CSI2RX(0x5309), + PSIL_CSI2RX(0x530a), + PSIL_CSI2RX(0x530b), + PSIL_CSI2RX(0x530c), + PSIL_CSI2RX(0x530d), + PSIL_CSI2RX(0x530e), + PSIL_CSI2RX(0x530f), + PSIL_CSI2RX(0x5310), + PSIL_CSI2RX(0x5311), + PSIL_CSI2RX(0x5312), + PSIL_CSI2RX(0x5313), + PSIL_CSI2RX(0x5314), + PSIL_CSI2RX(0x5315), + PSIL_CSI2RX(0x5316), + PSIL_CSI2RX(0x5317), + PSIL_CSI2RX(0x5318), + PSIL_CSI2RX(0x5319), + PSIL_CSI2RX(0x531a), + PSIL_CSI2RX(0x531b), + PSIL_CSI2RX(0x531c), + PSIL_CSI2RX(0x531d), + PSIL_CSI2RX(0x531e), + PSIL_CSI2RX(0x531f), }; /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c index bb0408fc08..1daa7d7680 100644 --- a/drivers/dma/ti/k3-psil.c +++ b/drivers/dma/ti/k3-psil.c @@ -32,6 +32,8 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id) soc_ep_map = &j784s4_ep_map; else if (IS_ENABLED(CONFIG_SOC_K3_AM62P5)) soc_ep_map = &am62p_ep_map; + else if (IS_ENABLED(CONFIG_SOC_K3_J722S)) + soc_ep_map = &am62p_ep_map; } if (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET && soc_ep_map->dst) { -- cgit v1.2.3 From 3ee2c6b5c1dec7b6787719de5aa3243cb482288a Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Mon, 18 Dec 2023 21:26:33 +0530 Subject: arm: dts: Add J722S Device Tree from Linux Pull in the device tree source files for TI's J722S SoCs needed to boot the board from v6.6-rc5. These are an early release with only the peripherals to boot the board via UART boot. Co-developed-by: Vaishnav Achath Signed-off-by: Vaishnav Achath Signed-off-by: Jayesh Choudhary --- arch/arm/dts/Makefile | 4 + arch/arm/dts/k3-j722s-evm.dts | 295 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/k3-j722s.dtsi | 91 +++++++++++++ arch/arm/dts/k3-pinctrl.h | 3 + 4 files changed, 393 insertions(+) create mode 100644 arch/arm/dts/k3-j722s-evm.dts create mode 100644 arch/arm/dts/k3-j722s.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f5c4141b3b..6c719ade1a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1273,6 +1273,10 @@ dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\ k3-am68-sk-r5-base-board.dtb\ k3-j721s2-common-proc-board.dtb\ k3-j721s2-r5-common-proc-board.dtb + +dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-evm.dtb \ + k3-j722s-r5-evm.dtb + dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-sk.dtb \ k3-am69-r5-sk.dtb \ k3-j784s4-evm.dtb \ diff --git a/arch/arm/dts/k3-j722s-evm.dts b/arch/arm/dts/k3-j722s-evm.dts new file mode 100644 index 0000000000..acdad22531 --- /dev/null +++ b/arch/arm/dts/k3-j722s-evm.dts @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the J722S-EVM + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * Schematics: https://www.ti.com/lit/zip/sprr495 + */ + +/dts-v1/; + +#include "k3-j722s.dtsi" + +/ { + compatible = "ti,j722s-evm", "ti,j722s"; + model = "Texas Instruments J722S EVM"; + + aliases { + serial0 = &wkup_uart0; + serial2 = &main_uart0; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + }; + + chosen { + stdout-path = &main_uart0; + }; + + memory@80000000 { + /* 8G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000001 0x80000000>; + device_type = "memory"; + bootph-pre-ram; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vsys_5v0: regulator-vsys5v0 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-mmc1 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&exp1 15 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vdd_sd_dv: regulator-TLV71033 { + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 70 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&main_pmx0 { + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */ + J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */ + >; + bootph-all; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ + J722S_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ + >; + bootph-all; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */ + >; + bootph-all; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x023c, PIN_INPUT, 0) /* (H22) MMC1_CMD */ + J722S_IOPAD(0x0234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */ + J722S_IOPAD(0x0230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */ + J722S_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H20) MMC1_DAT1 */ + J722S_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (J23) MMC1_DAT2 */ + J722S_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */ + J722S_IOPAD(0x0240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */ + >; + bootph-all; + }; +}; + +&main_gpio1 { + status = "okay"; + bootph-all; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + status = "okay"; + bootph-all; +}; + +&mcu_pmx0 { + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ + J722S_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ + J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ + J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ + >; + bootph-all; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0) /* (C7) WKUP_I2C0_SCL */ + J722S_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_I2C1_SDA */ + >; + bootph-all; + }; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "reserved"; + bootph-all; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + bootph-all; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + exp1: gpio@23 { + compatible = "ti,tca6424"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + bootph-all; + gpio-line-names = "TRC_MUX_SEL", "OSPI/ONAND_MUX_SEL", + "MCASP1_FET_SEL", "CTRL_PM_I2C_OE#", + "CSI_VIO_SEL", "USB2.0_MUX_SEL", + "CSI01_MUX_SEL_2", "CSI23_MUX_SEL_2", + "LMK1_OE1", "LMK1_OE0", + "LMK2_OE0", "LMK2_OE1", + "GPIO_RGMII1_RST#", "GPIO_AUD_RSTn", + "GPIO_eMMC_RSTn", "GPIO_uSD_PWR_EN", + "USER_LED2", "MCAN0_STB", + "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#", + "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN", + "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ"; + }; +}; + +&sdhci1 { + /* SD/MMC */ + status = "okay"; + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; + no-1-8-v; + bootph-all; +}; + +&mailbox0_cluster0 { + status = "okay"; + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + mbox_main_r5_0: mbox-main-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c7x_1: mbox-c7x-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mcu_r5fss0 { + status = "disabled"; +}; + +&wkup_r5fss0 { + status = "disabled"; +}; diff --git a/arch/arm/dts/k3-j722s.dtsi b/arch/arm/dts/k3-j722s.dtsi new file mode 100644 index 0000000000..c876be927d --- /dev/null +++ b/arch/arm/dts/k3-j722s.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J722S SoC Family + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include + +#include "k3-am62p5.dtsi" + +/ { + model = "Texas Instruments K3 J722S SoC"; + compatible = "ti,j722s"; + + cbass_main: bus@f0000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ + <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_0 */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ + <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */ + <0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */ + <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */ + <0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ + <0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */ + <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI-base1 */ + <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI-base2 */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ + <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe0 DAT0 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00040000>, /* OCSRAM */ + <0x00 0x78400000 0x00 0x78400000 0x00 0x00008000>, /* MAIN R5FSS0 ATCM */ + <0x00 0x78500000 0x00 0x78500000 0x00 0x00008000>, /* MAIN R5FSS0 BTCM */ + <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00200000>, /* C7X_0 L2SRAM */ + <0x00 0x7e200000 0x00 0x7e200000 0x00 0x00200000>, /* C7X_1 L2SRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */ + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, + /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; + }; +}; + +/* Main domain overrides */ + +&inta_main_dmss { + ti,interrupt-ranges = <7 71 21>; +}; + +&inta_main_dmss_csi { + ti,interrupt-ranges = <0 237 8>; +}; + +&oc_sram { + reg = <0x00 0x70000000 0x00 0x40000>; + ranges = <0x00 0x00 0x70000000 0x40000>; +}; diff --git a/arch/arm/dts/k3-pinctrl.h b/arch/arm/dts/k3-pinctrl.h index 2a4e0e084d..591be4489f 100644 --- a/arch/arm/dts/k3-pinctrl.h +++ b/arch/arm/dts/k3-pinctrl.h @@ -59,6 +59,9 @@ #define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J722S_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J722S_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #define J784S4_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define J784S4_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -- cgit v1.2.3 From 3e01106af425ac6d67f0210231e307c0960d0906 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Mon, 18 Dec 2023 21:26:34 +0530 Subject: arm: dts: Introduce J722S uboot dts files Include the uboot device tree files needed to boot the board. Co-developed-by: Vaishnav Achath Signed-off-by: Vaishnav Achath Signed-off-by: Jayesh Choudhary --- arch/arm/dts/k3-j722s-binman.dtsi | 284 +++ arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi | 2795 ++++++++++++++++++++++++++++ arch/arm/dts/k3-j722s-evm-u-boot.dtsi | 27 + arch/arm/dts/k3-j722s-r5-evm.dts | 82 + 4 files changed, 3188 insertions(+) create mode 100644 arch/arm/dts/k3-j722s-binman.dtsi create mode 100644 arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi create mode 100644 arch/arm/dts/k3-j722s-evm-u-boot.dtsi create mode 100644 arch/arm/dts/k3-j722s-r5-evm.dts diff --git a/arch/arm/dts/k3-j722s-binman.dtsi b/arch/arm/dts/k3-j722s-binman.dtsi new file mode 100644 index 0000000000..d5ccfdd939 --- /dev/null +++ b/arch/arm/dts/k3-j722s-binman.dtsi @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-binman.dtsi" + +#ifdef CONFIG_TARGET_J722S_R5_EVM + +&binman { + tiboot3-j722s-hs-evm.bin { + filename = "tiboot3-j722s-hs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>, + <&combined_dm_cfg>, <&sysfw_inner_cert>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl>; + content-sysfw = <&ti_fs_enc>; + content-sysfw-data = <&combined_tifs_cfg>; + content-sysfw-inner-cert = <&sysfw_inner_cert>; + content-dm-data = <&combined_dm_cfg>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c4a800>; + }; + u_boot_spl: u-boot-spl { + no-expanded; + }; + ti_fs_enc: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j722s-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-j722s-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +&binman { + tiboot3-j722s-hs-fs-evm.bin { + filename = "tiboot3-j722s-hs-fs-evm.bin"; + symlink = "tiboot3.bin"; + ti-secure-rom { + content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>, + <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_fs>; + content-sysfw = <&ti_fs_enc_fs>; + content-sysfw-data = <&combined_tifs_cfg_fs>; + content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; + content-dm-data = <&combined_dm_cfg_fs>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c7a800>; + }; + u_boot_spl_fs: u-boot-spl { + no-expanded; + }; + ti_fs_enc_fs: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_fs: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert_fs: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg_fs: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; +#endif + +#ifdef CONFIG_TARGET_J722S_A53_EVM + +#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" +#define SPL_J722S_EVM_DTB "spl/dts/k3-j722s-evm.dtb" + +#define UBOOT_NODTB "u-boot-nodtb.bin" +#define J722S_EVM_DTB "u-boot.dtb" + +&binman { + ti-dm { + filename = "ti-dm.bin"; + blob-ext { + filename = "ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + + ti-spl { + filename = "tispl.bin"; + pad-byte = <0xff>; + + fit { + description = "Configuration to load ATF and SPL"; + #address-cells = <1>; + + images { + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = ; + entry = ; + ti-secure { + content = <&atf>; + keyfile = "custMpk.pem"; + }; + atf: atf-bl31 { + }; + }; + + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + ti-secure { + content = <&tee>; + keyfile = "custMpk.pem"; + }; + tee: tee-os { + }; + }; + + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + ti-secure { + content = <&dm>; + keyfile = "custMpk.pem"; + }; + dm: blob-ext { + filename = "ti-dm.bin"; + }; + }; + + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = ; + entry = ; + ti-secure { + content = <&u_boot_spl_nodtb>; + keyfile = "custMpk.pem"; + }; + u_boot_spl_nodtb: blob-ext { + filename = SPL_NODTB; + }; + }; + + fdt-0 { + description = "k3-j722s-evm"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_j722s_evm_dtb>; + keyfile = "custMpk.pem"; + }; + spl_j722s_evm_dtb: blob-ext { + filename = SPL_J722S_EVM_DTB; + }; + + }; + + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j722s-evm"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot { + filename = "u-boot.img"; + pad-byte = <0xff>; + + fit { + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot for J722S board"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = ; + ti-secure { + content = <&u_boot_nodtb>; + keyfile = "custMpk.pem"; + }; + u_boot_nodtb: u-boot-nodtb { + }; + hash { + algo = "crc32"; + }; + }; + + fdt-0 { + description = "k3-j722s-evm"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&j722s_evm_dtb>; + keyfile = "custMpk.pem"; + }; + j722s_evm_dtb: blob-ext { + filename = J722S_EVM_DTB; + }; + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j722s-evm"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + + }; + }; + }; +}; +#endif diff --git a/arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi b/arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi new file mode 100644 index 0000000000..87ac07a00c --- /dev/null +++ b/arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi @@ -0,0 +1,2795 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the Jacinto7_DDRSS_RegConfigTool, Revision: J722S - v0.0.0 + * This file was generated on Fri Nov 17 2023 13:18:41 GMT-0600 (Central Standard Time) + */ + +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS_PLL_FREQUENCY_0 25000000 +#define DDRSS_PLL_FREQUENCY_1 933000000 +#define DDRSS_PLL_FREQUENCY_2 933000000 + +#define DDRSS_CTL_0_DATA 0x00000B00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x00002710 +#define DDRSS_CTL_8_DATA 0x000186A0 +#define DDRSS_CTL_9_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_11_DATA 0x0005B18F +#define DDRSS_CTL_12_DATA 0x0038EF90 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000E94 +#define DDRSS_CTL_15_DATA 0x0005B18F +#define DDRSS_CTL_16_DATA 0x0038EF90 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000E94 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01010100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x0000000A +#define DDRSS_CTL_24_DATA 0x000186A0 +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00020200 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00004B4B +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x00000000 +#define DDRSS_CTL_39_DATA 0x00000000 +#define DDRSS_CTL_40_DATA 0x0000040C +#define DDRSS_CTL_41_DATA 0x00000000 +#define DDRSS_CTL_42_DATA 0x00001040 +#define DDRSS_CTL_43_DATA 0x00000000 +#define DDRSS_CTL_44_DATA 0x00001040 +#define DDRSS_CTL_45_DATA 0x00000000 +#define DDRSS_CTL_46_DATA 0x05000804 +#define DDRSS_CTL_47_DATA 0x00000800 +#define DDRSS_CTL_48_DATA 0x09090004 +#define DDRSS_CTL_49_DATA 0x00000204 +#define DDRSS_CTL_50_DATA 0x007A0012 +#define DDRSS_CTL_51_DATA 0x09140054 +#define DDRSS_CTL_52_DATA 0x00003A26 +#define DDRSS_CTL_53_DATA 0x007A0012 +#define DDRSS_CTL_54_DATA 0x09140054 +#define DDRSS_CTL_55_DATA 0x09003A26 +#define DDRSS_CTL_56_DATA 0x000A0A09 +#define DDRSS_CTL_57_DATA 0x0400036D +#define DDRSS_CTL_58_DATA 0x090F2005 +#define DDRSS_CTL_59_DATA 0x00001B13 +#define DDRSS_CTL_60_DATA 0x0E007FE6 +#define DDRSS_CTL_61_DATA 0x090F200F +#define DDRSS_CTL_62_DATA 0x00001B13 +#define DDRSS_CTL_63_DATA 0x0E007FE6 +#define DDRSS_CTL_64_DATA 0x0304200F +#define DDRSS_CTL_65_DATA 0x04050002 +#define DDRSS_CTL_66_DATA 0x24262426 +#define DDRSS_CTL_67_DATA 0x01010008 +#define DDRSS_CTL_68_DATA 0x044A4A08 +#define DDRSS_CTL_69_DATA 0x042B2B04 +#define DDRSS_CTL_70_DATA 0x00002B2B +#define DDRSS_CTL_71_DATA 0x00000101 +#define DDRSS_CTL_72_DATA 0x00000000 +#define DDRSS_CTL_73_DATA 0x01000000 +#define DDRSS_CTL_74_DATA 0x00130803 +#define DDRSS_CTL_75_DATA 0x00000059 +#define DDRSS_CTL_76_DATA 0x000002C5 +#define DDRSS_CTL_77_DATA 0x00000E2E +#define DDRSS_CTL_78_DATA 0x000002C5 +#define DDRSS_CTL_79_DATA 0x00000E2E +#define DDRSS_CTL_80_DATA 0x00000005 +#define DDRSS_CTL_81_DATA 0x0000000A +#define DDRSS_CTL_82_DATA 0x00000010 +#define DDRSS_CTL_83_DATA 0x00000163 +#define DDRSS_CTL_84_DATA 0x00000386 +#define DDRSS_CTL_85_DATA 0x00000163 +#define DDRSS_CTL_86_DATA 0x00000386 +#define DDRSS_CTL_87_DATA 0x03004000 +#define DDRSS_CTL_88_DATA 0x00001201 +#define DDRSS_CTL_89_DATA 0x000E0005 +#define DDRSS_CTL_90_DATA 0x2908000E +#define DDRSS_CTL_91_DATA 0x0A050529 +#define DDRSS_CTL_92_DATA 0x1B0E0A03 +#define DDRSS_CTL_93_DATA 0x1B0E0A04 +#define DDRSS_CTL_94_DATA 0x04010104 +#define DDRSS_CTL_95_DATA 0x00010401 +#define DDRSS_CTL_96_DATA 0x00140014 +#define DDRSS_CTL_97_DATA 0x02D302D3 +#define DDRSS_CTL_98_DATA 0x02D302D3 +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x03030000 +#define DDRSS_CTL_101_DATA 0x05050501 +#define DDRSS_CTL_102_DATA 0x04041C04 +#define DDRSS_CTL_103_DATA 0x0E0A0E0A +#define DDRSS_CTL_104_DATA 0x0A04041C +#define DDRSS_CTL_105_DATA 0x030E0A0E +#define DDRSS_CTL_106_DATA 0x00000404 +#define DDRSS_CTL_107_DATA 0x00000301 +#define DDRSS_CTL_108_DATA 0x00000001 +#define DDRSS_CTL_109_DATA 0x00000000 +#define DDRSS_CTL_110_DATA 0x40020100 +#define DDRSS_CTL_111_DATA 0x00038010 +#define DDRSS_CTL_112_DATA 0x00050004 +#define DDRSS_CTL_113_DATA 0x00000004 +#define DDRSS_CTL_114_DATA 0x00040003 +#define DDRSS_CTL_115_DATA 0x00040005 +#define DDRSS_CTL_116_DATA 0x00030000 +#define DDRSS_CTL_117_DATA 0x00050004 +#define DDRSS_CTL_118_DATA 0x00000004 +#define DDRSS_CTL_119_DATA 0x00001640 +#define DDRSS_CTL_120_DATA 0x00001640 +#define DDRSS_CTL_121_DATA 0x00001640 +#define DDRSS_CTL_122_DATA 0x00001640 +#define DDRSS_CTL_123_DATA 0x00001640 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000026F +#define DDRSS_CTL_126_DATA 0x00038B80 +#define DDRSS_CTL_127_DATA 0x00038B80 +#define DDRSS_CTL_128_DATA 0x00038B80 +#define DDRSS_CTL_129_DATA 0x00038B80 +#define DDRSS_CTL_130_DATA 0x00038B80 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x00006342 +#define DDRSS_CTL_133_DATA 0x00038B80 +#define DDRSS_CTL_134_DATA 0x00038B80 +#define DDRSS_CTL_135_DATA 0x00038B80 +#define DDRSS_CTL_136_DATA 0x00038B80 +#define DDRSS_CTL_137_DATA 0x00038B80 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x00006342 +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x00000000 +#define DDRSS_CTL_157_DATA 0x00000000 +#define DDRSS_CTL_158_DATA 0x03050000 +#define DDRSS_CTL_159_DATA 0x040A040A +#define DDRSS_CTL_160_DATA 0x00000000 +#define DDRSS_CTL_161_DATA 0x07010A09 +#define DDRSS_CTL_162_DATA 0x000E0A09 +#define DDRSS_CTL_163_DATA 0x010A0900 +#define DDRSS_CTL_164_DATA 0x0E0A0907 +#define DDRSS_CTL_165_DATA 0x0A090000 +#define DDRSS_CTL_166_DATA 0x0A090701 +#define DDRSS_CTL_167_DATA 0x0000000E +#define DDRSS_CTL_168_DATA 0x00040003 +#define DDRSS_CTL_169_DATA 0x00000007 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x00000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x01000000 +#define DDRSS_CTL_177_DATA 0x00000000 +#define DDRSS_CTL_178_DATA 0x00001700 +#define DDRSS_CTL_179_DATA 0x0000100E +#define DDRSS_CTL_180_DATA 0x00000002 +#define DDRSS_CTL_181_DATA 0x00000000 +#define DDRSS_CTL_182_DATA 0x00000001 +#define DDRSS_CTL_183_DATA 0x00000002 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00008000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00008000 +#define DDRSS_CTL_188_DATA 0x00000C00 +#define DDRSS_CTL_189_DATA 0x00008000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x00000000 +#define DDRSS_CTL_193_DATA 0x00000000 +#define DDRSS_CTL_194_DATA 0x00000000 +#define DDRSS_CTL_195_DATA 0x0005000A +#define DDRSS_CTL_196_DATA 0x0404000D +#define DDRSS_CTL_197_DATA 0x0000000D +#define DDRSS_CTL_198_DATA 0x00BB0176 +#define DDRSS_CTL_199_DATA 0x0E0E01D3 +#define DDRSS_CTL_200_DATA 0x000001D3 +#define DDRSS_CTL_201_DATA 0x00BB0176 +#define DDRSS_CTL_202_DATA 0x0E0E01D3 +#define DDRSS_CTL_203_DATA 0x000001D3 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000000 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000000 +#define DDRSS_CTL_208_DATA 0x00000084 +#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x000000E4 +#define DDRSS_CTL_212_DATA 0x00000036 +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x000000E4 +#define DDRSS_CTL_215_DATA 0x00000036 +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000084 +#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x000000E4 +#define DDRSS_CTL_221_DATA 0x00000036 +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x000000E4 +#define DDRSS_CTL_224_DATA 0x00000036 +#define DDRSS_CTL_225_DATA 0x00000000 +#define DDRSS_CTL_226_DATA 0x00000000 +#define DDRSS_CTL_227_DATA 0x00000033 +#define DDRSS_CTL_228_DATA 0x00000033 +#define DDRSS_CTL_229_DATA 0x00000033 +#define DDRSS_CTL_230_DATA 0x00000033 +#define DDRSS_CTL_231_DATA 0x00000033 +#define DDRSS_CTL_232_DATA 0x00000033 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0x00000000 +#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00000000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x00000000 +#define DDRSS_CTL_255_DATA 0x00000000 +#define DDRSS_CTL_256_DATA 0x35000000 +#define DDRSS_CTL_257_DATA 0x35353535 +#define DDRSS_CTL_258_DATA 0x00002735 +#define DDRSS_CTL_259_DATA 0x00000027 +#define DDRSS_CTL_260_DATA 0x00000027 +#define DDRSS_CTL_261_DATA 0x00000027 +#define DDRSS_CTL_262_DATA 0x00000027 +#define DDRSS_CTL_263_DATA 0x00000027 +#define DDRSS_CTL_264_DATA 0x00000000 +#define DDRSS_CTL_265_DATA 0x00000000 +#define DDRSS_CTL_266_DATA 0x0000000F +#define DDRSS_CTL_267_DATA 0x0000000F +#define DDRSS_CTL_268_DATA 0x0000000F +#define DDRSS_CTL_269_DATA 0x0000000F +#define DDRSS_CTL_270_DATA 0x0000000F +#define DDRSS_CTL_271_DATA 0x0000000F +#define DDRSS_CTL_272_DATA 0x00000000 +#define DDRSS_CTL_273_DATA 0x00001600 +#define DDRSS_CTL_274_DATA 0x00000016 +#define DDRSS_CTL_275_DATA 0x00000016 +#define DDRSS_CTL_276_DATA 0x00000016 +#define DDRSS_CTL_277_DATA 0x00000016 +#define DDRSS_CTL_278_DATA 0x00000016 +#define DDRSS_CTL_279_DATA 0x00000020 +#define DDRSS_CTL_280_DATA 0x00010000 +#define DDRSS_CTL_281_DATA 0x00000100 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000101 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x00000000 +#define DDRSS_CTL_291_DATA 0x00000000 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x0C181511 +#define DDRSS_CTL_297_DATA 0x00000304 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00000000 +#define DDRSS_CTL_306_DATA 0x00000000 +#define DDRSS_CTL_307_DATA 0x00000000 +#define DDRSS_CTL_308_DATA 0x00000000 +#define DDRSS_CTL_309_DATA 0x00000000 +#define DDRSS_CTL_310_DATA 0x00000000 +#define DDRSS_CTL_311_DATA 0x00020000 +#define DDRSS_CTL_312_DATA 0x00400100 +#define DDRSS_CTL_313_DATA 0x00080032 +#define DDRSS_CTL_314_DATA 0x01000200 +#define DDRSS_CTL_315_DATA 0x074A0040 +#define DDRSS_CTL_316_DATA 0x00020038 +#define DDRSS_CTL_317_DATA 0x00400100 +#define DDRSS_CTL_318_DATA 0x0038074A +#define DDRSS_CTL_319_DATA 0x00030000 +#define DDRSS_CTL_320_DATA 0x005E005E +#define DDRSS_CTL_321_DATA 0x00000100 +#define DDRSS_CTL_322_DATA 0x01010000 +#define DDRSS_CTL_323_DATA 0x00000101 +#define DDRSS_CTL_324_DATA 0x1FFF0000 +#define DDRSS_CTL_325_DATA 0x000FFF00 +#define DDRSS_CTL_326_DATA 0x3FFF2000 +#define DDRSS_CTL_327_DATA 0x000FFF00 +#define DDRSS_CTL_328_DATA 0x0B000001 +#define DDRSS_CTL_329_DATA 0x0001FFFF +#define DDRSS_CTL_330_DATA 0x01010101 +#define DDRSS_CTL_331_DATA 0x01010101 +#define DDRSS_CTL_332_DATA 0x00000118 +#define DDRSS_CTL_333_DATA 0x00000C03 +#define DDRSS_CTL_334_DATA 0x00040100 +#define DDRSS_CTL_335_DATA 0x00040100 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x01030303 +#define DDRSS_CTL_339_DATA 0x00000000 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x00000000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x00000000 +#define DDRSS_CTL_361_DATA 0x00000000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0x00000000 +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00000000 +#define DDRSS_CTL_366_DATA 0x00000000 +#define DDRSS_CTL_367_DATA 0x00000000 +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x00000000 +#define DDRSS_CTL_372_DATA 0x00000000 +#define DDRSS_CTL_373_DATA 0x00000000 +#define DDRSS_CTL_374_DATA 0x00000000 +#define DDRSS_CTL_375_DATA 0x00000000 +#define DDRSS_CTL_376_DATA 0x00000000 +#define DDRSS_CTL_377_DATA 0x00000000 +#define DDRSS_CTL_378_DATA 0x00000000 +#define DDRSS_CTL_379_DATA 0x00000000 +#define DDRSS_CTL_380_DATA 0x00000000 +#define DDRSS_CTL_381_DATA 0x00000000 +#define DDRSS_CTL_382_DATA 0x00000000 +#define DDRSS_CTL_383_DATA 0x01000101 +#define DDRSS_CTL_384_DATA 0x01010001 +#define DDRSS_CTL_385_DATA 0x00010101 +#define DDRSS_CTL_386_DATA 0x01090903 +#define DDRSS_CTL_387_DATA 0x05020201 +#define DDRSS_CTL_388_DATA 0x0E081B1B +#define DDRSS_CTL_389_DATA 0x0009040E +#define DDRSS_CTL_390_DATA 0x0B0D040F +#define DDRSS_CTL_391_DATA 0x0B0D0406 +#define DDRSS_CTL_392_DATA 0x0D0D0906 +#define DDRSS_CTL_393_DATA 0x01000000 +#define DDRSS_CTL_394_DATA 0x07030701 +#define DDRSS_CTL_395_DATA 0x04000103 +#define DDRSS_CTL_396_DATA 0x1B000004 +#define DDRSS_CTL_397_DATA 0x000000B2 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00000200 +#define DDRSS_CTL_400_DATA 0x00000200 +#define DDRSS_CTL_401_DATA 0x00000200 +#define DDRSS_CTL_402_DATA 0x00000321 +#define DDRSS_CTL_403_DATA 0x000006F4 +#define DDRSS_CTL_404_DATA 0x03000202 +#define DDRSS_CTL_405_DATA 0x37200201 +#define DDRSS_CTL_406_DATA 0x00001C5C +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00000200 +#define DDRSS_CTL_409_DATA 0x00000200 +#define DDRSS_CTL_410_DATA 0x00000200 +#define DDRSS_CTL_411_DATA 0x00007F9E +#define DDRSS_CTL_412_DATA 0x00011B98 +#define DDRSS_CTL_413_DATA 0x111A0402 +#define DDRSS_CTL_414_DATA 0x37200C09 +#define DDRSS_CTL_415_DATA 0x00001C5C +#define DDRSS_CTL_416_DATA 0x00000200 +#define DDRSS_CTL_417_DATA 0x00000200 +#define DDRSS_CTL_418_DATA 0x00000200 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x00007F9E +#define DDRSS_CTL_421_DATA 0x00011B98 +#define DDRSS_CTL_422_DATA 0x111A0402 +#define DDRSS_CTL_423_DATA 0x00200C09 +#define DDRSS_CTL_424_DATA 0x00000000 +#define DDRSS_CTL_425_DATA 0x02000A00 +#define DDRSS_CTL_426_DATA 0x00050003 +#define DDRSS_CTL_427_DATA 0x00010101 +#define DDRSS_CTL_428_DATA 0x00010101 +#define DDRSS_CTL_429_DATA 0x00010001 +#define DDRSS_CTL_430_DATA 0x00000101 +#define DDRSS_CTL_431_DATA 0x02000201 +#define DDRSS_CTL_432_DATA 0x02010000 +#define DDRSS_CTL_433_DATA 0x06000200 +#define DDRSS_CTL_434_DATA 0x00002222 +#define DDRSS_PI_0_DATA 0x00000B00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000002 +#define DDRSS_PI_12_DATA 0x00000005 +#define DDRSS_PI_13_DATA 0x000F0001 +#define DDRSS_PI_14_DATA 0x08000000 +#define DDRSS_PI_15_DATA 0x00010300 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00000000 +#define DDRSS_PI_24_DATA 0x00000000 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x01010000 +#define DDRSS_PI_27_DATA 0x0A000100 +#define DDRSS_PI_28_DATA 0x00000028 +#define DDRSS_PI_29_DATA 0x0F000000 +#define DDRSS_PI_30_DATA 0x00320000 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x01010102 +#define DDRSS_PI_34_DATA 0x00000000 +#define DDRSS_PI_35_DATA 0x00000000 +#define DDRSS_PI_36_DATA 0x00000000 +#define DDRSS_PI_37_DATA 0x00000001 +#define DDRSS_PI_38_DATA 0x000000AA +#define DDRSS_PI_39_DATA 0x00000055 +#define DDRSS_PI_40_DATA 0x000000B5 +#define DDRSS_PI_41_DATA 0x0000004A +#define DDRSS_PI_42_DATA 0x00000056 +#define DDRSS_PI_43_DATA 0x000000A9 +#define DDRSS_PI_44_DATA 0x000000A9 +#define DDRSS_PI_45_DATA 0x000000B5 +#define DDRSS_PI_46_DATA 0x00000000 +#define DDRSS_PI_47_DATA 0x00000000 +#define DDRSS_PI_48_DATA 0x000F0F00 +#define DDRSS_PI_49_DATA 0x0000001A +#define DDRSS_PI_50_DATA 0x000007D0 +#define DDRSS_PI_51_DATA 0x00000300 +#define DDRSS_PI_52_DATA 0x00000000 +#define DDRSS_PI_53_DATA 0x00000000 +#define DDRSS_PI_54_DATA 0x01000000 +#define DDRSS_PI_55_DATA 0x00010101 +#define DDRSS_PI_56_DATA 0x01000000 +#define DDRSS_PI_57_DATA 0x03000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x0000170F +#define DDRSS_PI_60_DATA 0x00000000 +#define DDRSS_PI_61_DATA 0x00000000 +#define DDRSS_PI_62_DATA 0x00000000 +#define DDRSS_PI_63_DATA 0x0A0A140A +#define DDRSS_PI_64_DATA 0x10020101 +#define DDRSS_PI_65_DATA 0x01000210 +#define DDRSS_PI_66_DATA 0x05000404 +#define DDRSS_PI_67_DATA 0x00010001 +#define DDRSS_PI_68_DATA 0x0001000E +#define DDRSS_PI_69_DATA 0x01010F00 +#define DDRSS_PI_70_DATA 0x00010000 +#define DDRSS_PI_71_DATA 0x00000034 +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x0000FFFF +#define DDRSS_PI_75_DATA 0x00000000 +#define DDRSS_PI_76_DATA 0x00000000 +#define DDRSS_PI_77_DATA 0x00000000 +#define DDRSS_PI_78_DATA 0x00000000 +#define DDRSS_PI_79_DATA 0x01000000 +#define DDRSS_PI_80_DATA 0x01010001 +#define DDRSS_PI_81_DATA 0x02000008 +#define DDRSS_PI_82_DATA 0x01000200 +#define DDRSS_PI_83_DATA 0x00000100 +#define DDRSS_PI_84_DATA 0x02000100 +#define DDRSS_PI_85_DATA 0x02000200 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000000 +#define DDRSS_PI_92_DATA 0x00000000 +#define DDRSS_PI_93_DATA 0x00000000 +#define DDRSS_PI_94_DATA 0x00000000 +#define DDRSS_PI_95_DATA 0x00000000 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00000000 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x01000400 +#define DDRSS_PI_100_DATA 0x0E0D0F12 +#define DDRSS_PI_101_DATA 0x08111413 +#define DDRSS_PI_102_DATA 0x01000009 +#define DDRSS_PI_103_DATA 0x00000302 +#define DDRSS_PI_104_DATA 0x00000008 +#define DDRSS_PI_105_DATA 0x08000000 +#define DDRSS_PI_106_DATA 0x00000100 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x0000AA00 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00010000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000000 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00000000 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x00000008 +#define DDRSS_PI_137_DATA 0x00000000 +#define DDRSS_PI_138_DATA 0x00000000 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x00000000 +#define DDRSS_PI_145_DATA 0x00010000 +#define DDRSS_PI_146_DATA 0x00000000 +#define DDRSS_PI_147_DATA 0x00000000 +#define DDRSS_PI_148_DATA 0x0000000A +#define DDRSS_PI_149_DATA 0x000186A0 +#define DDRSS_PI_150_DATA 0x00000100 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00000000 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x01000000 +#define DDRSS_PI_157_DATA 0x00010003 +#define DDRSS_PI_158_DATA 0x02000101 +#define DDRSS_PI_159_DATA 0x01030001 +#define DDRSS_PI_160_DATA 0x00010400 +#define DDRSS_PI_161_DATA 0x06000105 +#define DDRSS_PI_162_DATA 0x01070001 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00000000 +#define DDRSS_PI_165_DATA 0x00000000 +#define DDRSS_PI_166_DATA 0x00010001 +#define DDRSS_PI_167_DATA 0x00000000 +#define DDRSS_PI_168_DATA 0x00000000 +#define DDRSS_PI_169_DATA 0x00000000 +#define DDRSS_PI_170_DATA 0x00000000 +#define DDRSS_PI_171_DATA 0x00010000 +#define DDRSS_PI_172_DATA 0x00000004 +#define DDRSS_PI_173_DATA 0x00000000 +#define DDRSS_PI_174_DATA 0x00010000 +#define DDRSS_PI_175_DATA 0x00000000 +#define DDRSS_PI_176_DATA 0x00080000 +#define DDRSS_PI_177_DATA 0x01180118 +#define DDRSS_PI_178_DATA 0x00262601 +#define DDRSS_PI_179_DATA 0x00000034 +#define DDRSS_PI_180_DATA 0x0000005E +#define DDRSS_PI_181_DATA 0x0002005E +#define DDRSS_PI_182_DATA 0x02000200 +#define DDRSS_PI_183_DATA 0x00000004 +#define DDRSS_PI_184_DATA 0x0000100C +#define DDRSS_PI_185_DATA 0x00104000 +#define DDRSS_PI_186_DATA 0x00400000 +#define DDRSS_PI_187_DATA 0x00000013 +#define DDRSS_PI_188_DATA 0x00000059 +#define DDRSS_PI_189_DATA 0x000002C5 +#define DDRSS_PI_190_DATA 0x00000E2E +#define DDRSS_PI_191_DATA 0x000002C5 +#define DDRSS_PI_192_DATA 0x04000E2E +#define DDRSS_PI_193_DATA 0x01010404 +#define DDRSS_PI_194_DATA 0x00001501 +#define DDRSS_PI_195_DATA 0x00270027 +#define DDRSS_PI_196_DATA 0x01000100 +#define DDRSS_PI_197_DATA 0x00000100 +#define DDRSS_PI_198_DATA 0x00000000 +#define DDRSS_PI_199_DATA 0x05090903 +#define DDRSS_PI_200_DATA 0x01011B1B +#define DDRSS_PI_201_DATA 0x01010101 +#define DDRSS_PI_202_DATA 0x000C0C0A +#define DDRSS_PI_203_DATA 0x00000000 +#define DDRSS_PI_204_DATA 0x00000000 +#define DDRSS_PI_205_DATA 0x04000000 +#define DDRSS_PI_206_DATA 0x0C021212 +#define DDRSS_PI_207_DATA 0x0404020C +#define DDRSS_PI_208_DATA 0x00090031 +#define DDRSS_PI_209_DATA 0x001B0043 +#define DDRSS_PI_210_DATA 0x001B0043 +#define DDRSS_PI_211_DATA 0x01010101 +#define DDRSS_PI_212_DATA 0x0003000D +#define DDRSS_PI_213_DATA 0x000301D3 +#define DDRSS_PI_214_DATA 0x010001D3 +#define DDRSS_PI_215_DATA 0x000E000E +#define DDRSS_PI_216_DATA 0x01D40100 +#define DDRSS_PI_217_DATA 0x010001D4 +#define DDRSS_PI_218_DATA 0x01D401D4 +#define DDRSS_PI_219_DATA 0x32103200 +#define DDRSS_PI_220_DATA 0x01013210 +#define DDRSS_PI_221_DATA 0x0A070601 +#define DDRSS_PI_222_DATA 0x1C11090D +#define DDRSS_PI_223_DATA 0x1C110913 +#define DDRSS_PI_224_DATA 0x000C0013 +#define DDRSS_PI_225_DATA 0x00001000 +#define DDRSS_PI_226_DATA 0x00000C00 +#define DDRSS_PI_227_DATA 0x00001000 +#define DDRSS_PI_228_DATA 0x00000C00 +#define DDRSS_PI_229_DATA 0x02001000 +#define DDRSS_PI_230_DATA 0x0021000D +#define DDRSS_PI_231_DATA 0x002101D3 +#define DDRSS_PI_232_DATA 0x000001D3 +#define DDRSS_PI_233_DATA 0x00001900 +#define DDRSS_PI_234_DATA 0x32000056 +#define DDRSS_PI_235_DATA 0x06000301 +#define DDRSS_PI_236_DATA 0x00300204 +#define DDRSS_PI_237_DATA 0x3212005A +#define DDRSS_PI_238_DATA 0x17000301 +#define DDRSS_PI_239_DATA 0x00300C12 +#define DDRSS_PI_240_DATA 0x3212005A +#define DDRSS_PI_241_DATA 0x17000301 +#define DDRSS_PI_242_DATA 0x00000C12 +#define DDRSS_PI_243_DATA 0x05040900 +#define DDRSS_PI_244_DATA 0x00040900 +#define DDRSS_PI_245_DATA 0x00000315 +#define DDRSS_PI_246_DATA 0x20010004 +#define DDRSS_PI_247_DATA 0x0A0A0A03 +#define DDRSS_PI_248_DATA 0x2B0F0000 +#define DDRSS_PI_249_DATA 0x24140026 +#define DDRSS_PI_250_DATA 0x0000731B +#define DDRSS_PI_251_DATA 0x20070054 +#define DDRSS_PI_252_DATA 0x1B131B1C +#define DDRSS_PI_253_DATA 0x2B0F0000 +#define DDRSS_PI_254_DATA 0x24140026 +#define DDRSS_PI_255_DATA 0x0000731B +#define DDRSS_PI_256_DATA 0x20070054 +#define DDRSS_PI_257_DATA 0x1B131B1C +#define DDRSS_PI_258_DATA 0x00000000 +#define DDRSS_PI_259_DATA 0x000000B2 +#define DDRSS_PI_260_DATA 0x000006F4 +#define DDRSS_PI_261_DATA 0x00001C5C +#define DDRSS_PI_262_DATA 0x00011B98 +#define DDRSS_PI_263_DATA 0x00001C5C +#define DDRSS_PI_264_DATA 0x00011B98 +#define DDRSS_PI_265_DATA 0x02D30014 +#define DDRSS_PI_266_DATA 0x030302D3 +#define DDRSS_PI_267_DATA 0x00000003 +#define DDRSS_PI_268_DATA 0x00000000 +#define DDRSS_PI_269_DATA 0x0A040503 +#define DDRSS_PI_270_DATA 0x00000A04 +#define DDRSS_PI_271_DATA 0x00002710 +#define DDRSS_PI_272_DATA 0x000186A0 +#define DDRSS_PI_273_DATA 0x00000005 +#define DDRSS_PI_274_DATA 0x00000064 +#define DDRSS_PI_275_DATA 0x00000014 +#define DDRSS_PI_276_DATA 0x0005B18F +#define DDRSS_PI_277_DATA 0x000186A0 +#define DDRSS_PI_278_DATA 0x00000005 +#define DDRSS_PI_279_DATA 0x00000E94 +#define DDRSS_PI_280_DATA 0x000002D3 +#define DDRSS_PI_281_DATA 0x0005B18F +#define DDRSS_PI_282_DATA 0x000186A0 +#define DDRSS_PI_283_DATA 0x00000005 +#define DDRSS_PI_284_DATA 0x00000E94 +#define DDRSS_PI_285_DATA 0x010002D3 +#define DDRSS_PI_286_DATA 0x00320040 +#define DDRSS_PI_287_DATA 0x00010008 +#define DDRSS_PI_288_DATA 0x074A0040 +#define DDRSS_PI_289_DATA 0x00010038 +#define DDRSS_PI_290_DATA 0x074A0040 +#define DDRSS_PI_291_DATA 0x00000338 +#define DDRSS_PI_292_DATA 0x0028005D +#define DDRSS_PI_293_DATA 0x03040404 +#define DDRSS_PI_294_DATA 0x00000303 +#define DDRSS_PI_295_DATA 0x01010000 +#define DDRSS_PI_296_DATA 0x04040202 +#define DDRSS_PI_297_DATA 0x67670808 +#define DDRSS_PI_298_DATA 0x67676767 +#define DDRSS_PI_299_DATA 0x67676767 +#define DDRSS_PI_300_DATA 0x67676767 +#define DDRSS_PI_301_DATA 0x00006767 +#define DDRSS_PI_302_DATA 0x00000000 +#define DDRSS_PI_303_DATA 0x00000000 +#define DDRSS_PI_304_DATA 0x00000000 +#define DDRSS_PI_305_DATA 0x00000000 +#define DDRSS_PI_306_DATA 0x55000000 +#define DDRSS_PI_307_DATA 0x00000000 +#define DDRSS_PI_308_DATA 0x3C00005A +#define DDRSS_PI_309_DATA 0x00005500 +#define DDRSS_PI_310_DATA 0x00005A00 +#define DDRSS_PI_311_DATA 0x0055003C +#define DDRSS_PI_312_DATA 0x00000000 +#define DDRSS_PI_313_DATA 0x3C00005A +#define DDRSS_PI_314_DATA 0x00005500 +#define DDRSS_PI_315_DATA 0x00005A00 +#define DDRSS_PI_316_DATA 0x1716153C +#define DDRSS_PI_317_DATA 0x13100A18 +#define DDRSS_PI_318_DATA 0x06050414 +#define DDRSS_PI_319_DATA 0x02010007 +#define DDRSS_PI_320_DATA 0x00000003 +#define DDRSS_PI_321_DATA 0x00000000 +#define DDRSS_PI_322_DATA 0x00000000 +#define DDRSS_PI_323_DATA 0x01000000 +#define DDRSS_PI_324_DATA 0x04020201 +#define DDRSS_PI_325_DATA 0x00080804 +#define DDRSS_PI_326_DATA 0x00000000 +#define DDRSS_PI_327_DATA 0x00000000 +#define DDRSS_PI_328_DATA 0x00000000 +#define DDRSS_PI_329_DATA 0x00000084 +#define DDRSS_PI_330_DATA 0x00000000 +#define DDRSS_PI_331_DATA 0x00000033 +#define DDRSS_PI_332_DATA 0x00000000 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x35000000 +#define DDRSS_PI_335_DATA 0x20160F27 +#define DDRSS_PI_336_DATA 0x00000000 +#define DDRSS_PI_337_DATA 0x000000E4 +#define DDRSS_PI_338_DATA 0x00000036 +#define DDRSS_PI_339_DATA 0x00000033 +#define DDRSS_PI_340_DATA 0x00000000 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x35000000 +#define DDRSS_PI_343_DATA 0x20160F27 +#define DDRSS_PI_344_DATA 0x00000000 +#define DDRSS_PI_345_DATA 0x000000E4 +#define DDRSS_PI_346_DATA 0x00000036 +#define DDRSS_PI_347_DATA 0x00000033 +#define DDRSS_PI_348_DATA 0x00000000 +#define DDRSS_PI_349_DATA 0x00000000 +#define DDRSS_PI_350_DATA 0x35000000 +#define DDRSS_PI_351_DATA 0x20160F27 +#define DDRSS_PI_352_DATA 0x00000000 +#define DDRSS_PI_353_DATA 0x00000084 +#define DDRSS_PI_354_DATA 0x00000000 +#define DDRSS_PI_355_DATA 0x00000033 +#define DDRSS_PI_356_DATA 0x00000000 +#define DDRSS_PI_357_DATA 0x00000000 +#define DDRSS_PI_358_DATA 0x35000000 +#define DDRSS_PI_359_DATA 0x20160F27 +#define DDRSS_PI_360_DATA 0x00000000 +#define DDRSS_PI_361_DATA 0x000000E4 +#define DDRSS_PI_362_DATA 0x00000036 +#define DDRSS_PI_363_DATA 0x00000033 +#define DDRSS_PI_364_DATA 0x00000000 +#define DDRSS_PI_365_DATA 0x00000000 +#define DDRSS_PI_366_DATA 0x35000000 +#define DDRSS_PI_367_DATA 0x20160F27 +#define DDRSS_PI_368_DATA 0x00000000 +#define DDRSS_PI_369_DATA 0x000000E4 +#define DDRSS_PI_370_DATA 0x00000036 +#define DDRSS_PI_371_DATA 0x00000033 +#define DDRSS_PI_372_DATA 0x00000000 +#define DDRSS_PI_373_DATA 0x00000000 +#define DDRSS_PI_374_DATA 0x35000000 +#define DDRSS_PI_375_DATA 0x20160F27 +#define DDRSS_PI_376_DATA 0x00000000 +#define DDRSS_PI_377_DATA 0x00000084 +#define DDRSS_PI_378_DATA 0x00000000 +#define DDRSS_PI_379_DATA 0x00000033 +#define DDRSS_PI_380_DATA 0x00000000 +#define DDRSS_PI_381_DATA 0x00000000 +#define DDRSS_PI_382_DATA 0x35000000 +#define DDRSS_PI_383_DATA 0x20160F27 +#define DDRSS_PI_384_DATA 0x00000000 +#define DDRSS_PI_385_DATA 0x000000E4 +#define DDRSS_PI_386_DATA 0x00000036 +#define DDRSS_PI_387_DATA 0x00000033 +#define DDRSS_PI_388_DATA 0x00000000 +#define DDRSS_PI_389_DATA 0x00000000 +#define DDRSS_PI_390_DATA 0x35000000 +#define DDRSS_PI_391_DATA 0x20160F27 +#define DDRSS_PI_392_DATA 0x00000000 +#define DDRSS_PI_393_DATA 0x000000E4 +#define DDRSS_PI_394_DATA 0x00000036 +#define DDRSS_PI_395_DATA 0x00000033 +#define DDRSS_PI_396_DATA 0x00000000 +#define DDRSS_PI_397_DATA 0x00000000 +#define DDRSS_PI_398_DATA 0x35000000 +#define DDRSS_PI_399_DATA 0x20160F27 +#define DDRSS_PI_400_DATA 0x00000000 +#define DDRSS_PI_401_DATA 0x00000084 +#define DDRSS_PI_402_DATA 0x00000000 +#define DDRSS_PI_403_DATA 0x00000033 +#define DDRSS_PI_404_DATA 0x00000000 +#define DDRSS_PI_405_DATA 0x00000000 +#define DDRSS_PI_406_DATA 0x35000000 +#define DDRSS_PI_407_DATA 0x20160F27 +#define DDRSS_PI_408_DATA 0x00000000 +#define DDRSS_PI_409_DATA 0x000000E4 +#define DDRSS_PI_410_DATA 0x00000036 +#define DDRSS_PI_411_DATA 0x00000033 +#define DDRSS_PI_412_DATA 0x00000000 +#define DDRSS_PI_413_DATA 0x00000000 +#define DDRSS_PI_414_DATA 0x35000000 +#define DDRSS_PI_415_DATA 0x20160F27 +#define DDRSS_PI_416_DATA 0x00000000 +#define DDRSS_PI_417_DATA 0x000000E4 +#define DDRSS_PI_418_DATA 0x00000036 +#define DDRSS_PI_419_DATA 0x00000033 +#define DDRSS_PI_420_DATA 0x00000000 +#define DDRSS_PI_421_DATA 0x00000000 +#define DDRSS_PI_422_DATA 0x35000000 +#define DDRSS_PI_423_DATA 0x20160F27 +#define DDRSS_PHY_0_DATA 0x04F00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00030200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x01030000 +#define DDRSS_PHY_6_DATA 0x00010000 +#define DDRSS_PHY_7_DATA 0x01030004 +#define DDRSS_PHY_8_DATA 0x01000000 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x00000000 +#define DDRSS_PHY_12_DATA 0x01010000 +#define DDRSS_PHY_13_DATA 0x00010000 +#define DDRSS_PHY_14_DATA 0x00C00001 +#define DDRSS_PHY_15_DATA 0x00CC0008 +#define DDRSS_PHY_16_DATA 0x00660601 +#define DDRSS_PHY_17_DATA 0x00000003 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x00000301 +#define DDRSS_PHY_20_DATA 0x0000AAAA +#define DDRSS_PHY_21_DATA 0x00005555 +#define DDRSS_PHY_22_DATA 0x0000B5B5 +#define DDRSS_PHY_23_DATA 0x00004A4A +#define DDRSS_PHY_24_DATA 0x00005656 +#define DDRSS_PHY_25_DATA 0x0000A9A9 +#define DDRSS_PHY_26_DATA 0x0000B7B7 +#define DDRSS_PHY_27_DATA 0x00004848 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x00000000 +#define DDRSS_PHY_30_DATA 0x08000000 +#define DDRSS_PHY_31_DATA 0x0F000008 +#define DDRSS_PHY_32_DATA 0x00000F0F +#define DDRSS_PHY_33_DATA 0x00E4E400 +#define DDRSS_PHY_34_DATA 0x00071040 +#define DDRSS_PHY_35_DATA 0x000C0020 +#define DDRSS_PHY_36_DATA 0x00062000 +#define DDRSS_PHY_37_DATA 0x00000000 +#define DDRSS_PHY_38_DATA 0x55555555 +#define DDRSS_PHY_39_DATA 0xAAAAAAAA +#define DDRSS_PHY_40_DATA 0x55555555 +#define DDRSS_PHY_41_DATA 0xAAAAAAAA +#define DDRSS_PHY_42_DATA 0x00005555 +#define DDRSS_PHY_43_DATA 0x01000100 +#define DDRSS_PHY_44_DATA 0x00800180 +#define DDRSS_PHY_45_DATA 0x00000001 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000000 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000004 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x00000000 +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x081F07FF +#define DDRSS_PHY_75_DATA 0x10200080 +#define DDRSS_PHY_76_DATA 0x00000008 +#define DDRSS_PHY_77_DATA 0x00000401 +#define DDRSS_PHY_78_DATA 0x00000000 +#define DDRSS_PHY_79_DATA 0x01CC0C01 +#define DDRSS_PHY_80_DATA 0x1003CC0C +#define DDRSS_PHY_81_DATA 0x20000140 +#define DDRSS_PHY_82_DATA 0x07FF0200 +#define DDRSS_PHY_83_DATA 0x0000DD01 +#define DDRSS_PHY_84_DATA 0x00100303 +#define DDRSS_PHY_85_DATA 0x00000000 +#define DDRSS_PHY_86_DATA 0x00000000 +#define DDRSS_PHY_87_DATA 0x00041000 +#define DDRSS_PHY_88_DATA 0x00100010 +#define DDRSS_PHY_89_DATA 0x00100010 +#define DDRSS_PHY_90_DATA 0x00100010 +#define DDRSS_PHY_91_DATA 0x00100010 +#define DDRSS_PHY_92_DATA 0x02000010 +#define DDRSS_PHY_93_DATA 0x00000005 +#define DDRSS_PHY_94_DATA 0x51516042 +#define DDRSS_PHY_95_DATA 0x31C06000 +#define DDRSS_PHY_96_DATA 0x07AB0340 +#define DDRSS_PHY_97_DATA 0x00C0C001 +#define DDRSS_PHY_98_DATA 0x0D000000 +#define DDRSS_PHY_99_DATA 0x000D0C0C +#define DDRSS_PHY_100_DATA 0x42100010 +#define DDRSS_PHY_101_DATA 0x010C073E +#define DDRSS_PHY_102_DATA 0x000F0C32 +#define DDRSS_PHY_103_DATA 0x01000140 +#define DDRSS_PHY_104_DATA 0x011E0120 +#define DDRSS_PHY_105_DATA 0x00000C00 +#define DDRSS_PHY_106_DATA 0x000002DD +#define DDRSS_PHY_107_DATA 0x00030200 +#define DDRSS_PHY_108_DATA 0x02800000 +#define DDRSS_PHY_109_DATA 0x80800000 +#define DDRSS_PHY_110_DATA 0x000D2010 +#define DDRSS_PHY_111_DATA 0x76543210 +#define DDRSS_PHY_112_DATA 0x00000008 +#define DDRSS_PHY_113_DATA 0x045D045D +#define DDRSS_PHY_114_DATA 0x045D045D +#define DDRSS_PHY_115_DATA 0x045D045D +#define DDRSS_PHY_116_DATA 0x045D045D +#define DDRSS_PHY_117_DATA 0x0000045D +#define DDRSS_PHY_118_DATA 0x0000A000 +#define DDRSS_PHY_119_DATA 0x00A000A0 +#define DDRSS_PHY_120_DATA 0x00A000A0 +#define DDRSS_PHY_121_DATA 0x00A000A0 +#define DDRSS_PHY_122_DATA 0x00A000A0 +#define DDRSS_PHY_123_DATA 0x00A000A0 +#define DDRSS_PHY_124_DATA 0x00A000A0 +#define DDRSS_PHY_125_DATA 0x00A000A0 +#define DDRSS_PHY_126_DATA 0x00A000A0 +#define DDRSS_PHY_127_DATA 0x00B200A0 +#define DDRSS_PHY_128_DATA 0x01000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00080200 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x20202020 +#define DDRSS_PHY_134_DATA 0x20202020 +#define DDRSS_PHY_135_DATA 0xF0F02020 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04F00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01030000 +#define DDRSS_PHY_262_DATA 0x00010000 +#define DDRSS_PHY_263_DATA 0x01030004 +#define DDRSS_PHY_264_DATA 0x01000000 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x00000000 +#define DDRSS_PHY_268_DATA 0x01010000 +#define DDRSS_PHY_269_DATA 0x00010000 +#define DDRSS_PHY_270_DATA 0x00C00001 +#define DDRSS_PHY_271_DATA 0x00CC0008 +#define DDRSS_PHY_272_DATA 0x00660601 +#define DDRSS_PHY_273_DATA 0x00000003 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x00000301 +#define DDRSS_PHY_276_DATA 0x0000AAAA +#define DDRSS_PHY_277_DATA 0x00005555 +#define DDRSS_PHY_278_DATA 0x0000B5B5 +#define DDRSS_PHY_279_DATA 0x00004A4A +#define DDRSS_PHY_280_DATA 0x00005656 +#define DDRSS_PHY_281_DATA 0x0000A9A9 +#define DDRSS_PHY_282_DATA 0x0000B7B7 +#define DDRSS_PHY_283_DATA 0x00004848 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x00000000 +#define DDRSS_PHY_286_DATA 0x08000000 +#define DDRSS_PHY_287_DATA 0x0F000008 +#define DDRSS_PHY_288_DATA 0x00000F0F +#define DDRSS_PHY_289_DATA 0x00E4E400 +#define DDRSS_PHY_290_DATA 0x00071040 +#define DDRSS_PHY_291_DATA 0x000C0020 +#define DDRSS_PHY_292_DATA 0x00062000 +#define DDRSS_PHY_293_DATA 0x00000000 +#define DDRSS_PHY_294_DATA 0x55555555 +#define DDRSS_PHY_295_DATA 0xAAAAAAAA +#define DDRSS_PHY_296_DATA 0x55555555 +#define DDRSS_PHY_297_DATA 0xAAAAAAAA +#define DDRSS_PHY_298_DATA 0x00005555 +#define DDRSS_PHY_299_DATA 0x01000100 +#define DDRSS_PHY_300_DATA 0x00800180 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000000 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000004 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x00000000 +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x081F07FF +#define DDRSS_PHY_331_DATA 0x10200080 +#define DDRSS_PHY_332_DATA 0x00000008 +#define DDRSS_PHY_333_DATA 0x00000401 +#define DDRSS_PHY_334_DATA 0x00000000 +#define DDRSS_PHY_335_DATA 0x01CC0C01 +#define DDRSS_PHY_336_DATA 0x1003CC0C +#define DDRSS_PHY_337_DATA 0x20000140 +#define DDRSS_PHY_338_DATA 0x07FF0200 +#define DDRSS_PHY_339_DATA 0x0000DD01 +#define DDRSS_PHY_340_DATA 0x00100303 +#define DDRSS_PHY_341_DATA 0x00000000 +#define DDRSS_PHY_342_DATA 0x00000000 +#define DDRSS_PHY_343_DATA 0x00041000 +#define DDRSS_PHY_344_DATA 0x00100010 +#define DDRSS_PHY_345_DATA 0x00100010 +#define DDRSS_PHY_346_DATA 0x00100010 +#define DDRSS_PHY_347_DATA 0x00100010 +#define DDRSS_PHY_348_DATA 0x02000010 +#define DDRSS_PHY_349_DATA 0x00000005 +#define DDRSS_PHY_350_DATA 0x51516042 +#define DDRSS_PHY_351_DATA 0x31C06000 +#define DDRSS_PHY_352_DATA 0x07AB0340 +#define DDRSS_PHY_353_DATA 0x00C0C001 +#define DDRSS_PHY_354_DATA 0x0D000000 +#define DDRSS_PHY_355_DATA 0x000D0C0C +#define DDRSS_PHY_356_DATA 0x42100010 +#define DDRSS_PHY_357_DATA 0x010C073E +#define DDRSS_PHY_358_DATA 0x000F0C32 +#define DDRSS_PHY_359_DATA 0x01000140 +#define DDRSS_PHY_360_DATA 0x011E0120 +#define DDRSS_PHY_361_DATA 0x00000C00 +#define DDRSS_PHY_362_DATA 0x000002DD +#define DDRSS_PHY_363_DATA 0x00030200 +#define DDRSS_PHY_364_DATA 0x02800000 +#define DDRSS_PHY_365_DATA 0x80800000 +#define DDRSS_PHY_366_DATA 0x000D2010 +#define DDRSS_PHY_367_DATA 0x76543210 +#define DDRSS_PHY_368_DATA 0x00000008 +#define DDRSS_PHY_369_DATA 0x045D045D +#define DDRSS_PHY_370_DATA 0x045D045D +#define DDRSS_PHY_371_DATA 0x045D045D +#define DDRSS_PHY_372_DATA 0x045D045D +#define DDRSS_PHY_373_DATA 0x0000045D +#define DDRSS_PHY_374_DATA 0x0000A000 +#define DDRSS_PHY_375_DATA 0x00A000A0 +#define DDRSS_PHY_376_DATA 0x00A000A0 +#define DDRSS_PHY_377_DATA 0x00A000A0 +#define DDRSS_PHY_378_DATA 0x00A000A0 +#define DDRSS_PHY_379_DATA 0x00A000A0 +#define DDRSS_PHY_380_DATA 0x00A000A0 +#define DDRSS_PHY_381_DATA 0x00A000A0 +#define DDRSS_PHY_382_DATA 0x00A000A0 +#define DDRSS_PHY_383_DATA 0x00B200A0 +#define DDRSS_PHY_384_DATA 0x01000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00080200 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x20202020 +#define DDRSS_PHY_390_DATA 0x20202020 +#define DDRSS_PHY_391_DATA 0xF0F02020 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x04F00000 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00030200 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x01030000 +#define DDRSS_PHY_518_DATA 0x00010000 +#define DDRSS_PHY_519_DATA 0x01030004 +#define DDRSS_PHY_520_DATA 0x01000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00000000 +#define DDRSS_PHY_524_DATA 0x01010000 +#define DDRSS_PHY_525_DATA 0x00010000 +#define DDRSS_PHY_526_DATA 0x00C00001 +#define DDRSS_PHY_527_DATA 0x00CC0008 +#define DDRSS_PHY_528_DATA 0x00660601 +#define DDRSS_PHY_529_DATA 0x00000003 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000301 +#define DDRSS_PHY_532_DATA 0x0000AAAA +#define DDRSS_PHY_533_DATA 0x00005555 +#define DDRSS_PHY_534_DATA 0x0000B5B5 +#define DDRSS_PHY_535_DATA 0x00004A4A +#define DDRSS_PHY_536_DATA 0x00005656 +#define DDRSS_PHY_537_DATA 0x0000A9A9 +#define DDRSS_PHY_538_DATA 0x0000B7B7 +#define DDRSS_PHY_539_DATA 0x00004848 +#define DDRSS_PHY_540_DATA 0x00000000 +#define DDRSS_PHY_541_DATA 0x00000000 +#define DDRSS_PHY_542_DATA 0x08000000 +#define DDRSS_PHY_543_DATA 0x0F000008 +#define DDRSS_PHY_544_DATA 0x00000F0F +#define DDRSS_PHY_545_DATA 0x00E4E400 +#define DDRSS_PHY_546_DATA 0x00071040 +#define DDRSS_PHY_547_DATA 0x000C0020 +#define DDRSS_PHY_548_DATA 0x00062000 +#define DDRSS_PHY_549_DATA 0x00000000 +#define DDRSS_PHY_550_DATA 0x55555555 +#define DDRSS_PHY_551_DATA 0xAAAAAAAA +#define DDRSS_PHY_552_DATA 0x55555555 +#define DDRSS_PHY_553_DATA 0xAAAAAAAA +#define DDRSS_PHY_554_DATA 0x00005555 +#define DDRSS_PHY_555_DATA 0x01000100 +#define DDRSS_PHY_556_DATA 0x00800180 +#define DDRSS_PHY_557_DATA 0x00000001 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000004 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x081F07FF +#define DDRSS_PHY_587_DATA 0x10200080 +#define DDRSS_PHY_588_DATA 0x00000008 +#define DDRSS_PHY_589_DATA 0x00000401 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x01CC0C01 +#define DDRSS_PHY_592_DATA 0x1003CC0C +#define DDRSS_PHY_593_DATA 0x20000140 +#define DDRSS_PHY_594_DATA 0x07FF0200 +#define DDRSS_PHY_595_DATA 0x0000DD01 +#define DDRSS_PHY_596_DATA 0x00100303 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00041000 +#define DDRSS_PHY_600_DATA 0x00100010 +#define DDRSS_PHY_601_DATA 0x00100010 +#define DDRSS_PHY_602_DATA 0x00100010 +#define DDRSS_PHY_603_DATA 0x00100010 +#define DDRSS_PHY_604_DATA 0x02000010 +#define DDRSS_PHY_605_DATA 0x00000005 +#define DDRSS_PHY_606_DATA 0x51516042 +#define DDRSS_PHY_607_DATA 0x31C06000 +#define DDRSS_PHY_608_DATA 0x07AB0340 +#define DDRSS_PHY_609_DATA 0x00C0C001 +#define DDRSS_PHY_610_DATA 0x0D000000 +#define DDRSS_PHY_611_DATA 0x000D0C0C +#define DDRSS_PHY_612_DATA 0x42100010 +#define DDRSS_PHY_613_DATA 0x010C073E +#define DDRSS_PHY_614_DATA 0x000F0C32 +#define DDRSS_PHY_615_DATA 0x01000140 +#define DDRSS_PHY_616_DATA 0x011E0120 +#define DDRSS_PHY_617_DATA 0x00000C00 +#define DDRSS_PHY_618_DATA 0x000002DD +#define DDRSS_PHY_619_DATA 0x00030200 +#define DDRSS_PHY_620_DATA 0x02800000 +#define DDRSS_PHY_621_DATA 0x80800000 +#define DDRSS_PHY_622_DATA 0x000D2010 +#define DDRSS_PHY_623_DATA 0x76543210 +#define DDRSS_PHY_624_DATA 0x00000008 +#define DDRSS_PHY_625_DATA 0x045D045D +#define DDRSS_PHY_626_DATA 0x045D045D +#define DDRSS_PHY_627_DATA 0x045D045D +#define DDRSS_PHY_628_DATA 0x045D045D +#define DDRSS_PHY_629_DATA 0x0000045D +#define DDRSS_PHY_630_DATA 0x0000A000 +#define DDRSS_PHY_631_DATA 0x00A000A0 +#define DDRSS_PHY_632_DATA 0x00A000A0 +#define DDRSS_PHY_633_DATA 0x00A000A0 +#define DDRSS_PHY_634_DATA 0x00A000A0 +#define DDRSS_PHY_635_DATA 0x00A000A0 +#define DDRSS_PHY_636_DATA 0x00A000A0 +#define DDRSS_PHY_637_DATA 0x00A000A0 +#define DDRSS_PHY_638_DATA 0x00A000A0 +#define DDRSS_PHY_639_DATA 0x00B200A0 +#define DDRSS_PHY_640_DATA 0x01000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00080200 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x20202020 +#define DDRSS_PHY_646_DATA 0x20202020 +#define DDRSS_PHY_647_DATA 0xF0F02020 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x04F00000 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00030200 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x01030000 +#define DDRSS_PHY_774_DATA 0x00010000 +#define DDRSS_PHY_775_DATA 0x01030004 +#define DDRSS_PHY_776_DATA 0x01000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00000000 +#define DDRSS_PHY_780_DATA 0x01010000 +#define DDRSS_PHY_781_DATA 0x00010000 +#define DDRSS_PHY_782_DATA 0x00C00001 +#define DDRSS_PHY_783_DATA 0x00CC0008 +#define DDRSS_PHY_784_DATA 0x00660601 +#define DDRSS_PHY_785_DATA 0x00000003 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000301 +#define DDRSS_PHY_788_DATA 0x0000AAAA +#define DDRSS_PHY_789_DATA 0x00005555 +#define DDRSS_PHY_790_DATA 0x0000B5B5 +#define DDRSS_PHY_791_DATA 0x00004A4A +#define DDRSS_PHY_792_DATA 0x00005656 +#define DDRSS_PHY_793_DATA 0x0000A9A9 +#define DDRSS_PHY_794_DATA 0x0000B7B7 +#define DDRSS_PHY_795_DATA 0x00004848 +#define DDRSS_PHY_796_DATA 0x00000000 +#define DDRSS_PHY_797_DATA 0x00000000 +#define DDRSS_PHY_798_DATA 0x08000000 +#define DDRSS_PHY_799_DATA 0x0F000008 +#define DDRSS_PHY_800_DATA 0x00000F0F +#define DDRSS_PHY_801_DATA 0x00E4E400 +#define DDRSS_PHY_802_DATA 0x00071040 +#define DDRSS_PHY_803_DATA 0x000C0020 +#define DDRSS_PHY_804_DATA 0x00062000 +#define DDRSS_PHY_805_DATA 0x00000000 +#define DDRSS_PHY_806_DATA 0x55555555 +#define DDRSS_PHY_807_DATA 0xAAAAAAAA +#define DDRSS_PHY_808_DATA 0x55555555 +#define DDRSS_PHY_809_DATA 0xAAAAAAAA +#define DDRSS_PHY_810_DATA 0x00005555 +#define DDRSS_PHY_811_DATA 0x01000100 +#define DDRSS_PHY_812_DATA 0x00800180 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000004 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x081F07FF +#define DDRSS_PHY_843_DATA 0x10200080 +#define DDRSS_PHY_844_DATA 0x00000008 +#define DDRSS_PHY_845_DATA 0x00000401 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x01CC0C01 +#define DDRSS_PHY_848_DATA 0x1003CC0C +#define DDRSS_PHY_849_DATA 0x20000140 +#define DDRSS_PHY_850_DATA 0x07FF0200 +#define DDRSS_PHY_851_DATA 0x0000DD01 +#define DDRSS_PHY_852_DATA 0x00100303 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00041000 +#define DDRSS_PHY_856_DATA 0x00100010 +#define DDRSS_PHY_857_DATA 0x00100010 +#define DDRSS_PHY_858_DATA 0x00100010 +#define DDRSS_PHY_859_DATA 0x00100010 +#define DDRSS_PHY_860_DATA 0x02000010 +#define DDRSS_PHY_861_DATA 0x00000005 +#define DDRSS_PHY_862_DATA 0x51516042 +#define DDRSS_PHY_863_DATA 0x31C06000 +#define DDRSS_PHY_864_DATA 0x07AB0340 +#define DDRSS_PHY_865_DATA 0x00C0C001 +#define DDRSS_PHY_866_DATA 0x0D000000 +#define DDRSS_PHY_867_DATA 0x000D0C0C +#define DDRSS_PHY_868_DATA 0x42100010 +#define DDRSS_PHY_869_DATA 0x010C073E +#define DDRSS_PHY_870_DATA 0x000F0C32 +#define DDRSS_PHY_871_DATA 0x01000140 +#define DDRSS_PHY_872_DATA 0x011E0120 +#define DDRSS_PHY_873_DATA 0x00000C00 +#define DDRSS_PHY_874_DATA 0x000002DD +#define DDRSS_PHY_875_DATA 0x00030200 +#define DDRSS_PHY_876_DATA 0x02800000 +#define DDRSS_PHY_877_DATA 0x80800000 +#define DDRSS_PHY_878_DATA 0x000D2010 +#define DDRSS_PHY_879_DATA 0x76543210 +#define DDRSS_PHY_880_DATA 0x00000008 +#define DDRSS_PHY_881_DATA 0x045D045D +#define DDRSS_PHY_882_DATA 0x045D045D +#define DDRSS_PHY_883_DATA 0x045D045D +#define DDRSS_PHY_884_DATA 0x045D045D +#define DDRSS_PHY_885_DATA 0x0000045D +#define DDRSS_PHY_886_DATA 0x0000A000 +#define DDRSS_PHY_887_DATA 0x00A000A0 +#define DDRSS_PHY_888_DATA 0x00A000A0 +#define DDRSS_PHY_889_DATA 0x00A000A0 +#define DDRSS_PHY_890_DATA 0x00A000A0 +#define DDRSS_PHY_891_DATA 0x00A000A0 +#define DDRSS_PHY_892_DATA 0x00A000A0 +#define DDRSS_PHY_893_DATA 0x00A000A0 +#define DDRSS_PHY_894_DATA 0x00A000A0 +#define DDRSS_PHY_895_DATA 0x00B200A0 +#define DDRSS_PHY_896_DATA 0x01000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00080200 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x20202020 +#define DDRSS_PHY_902_DATA 0x20202020 +#define DDRSS_PHY_903_DATA 0xF0F02020 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x00000000 +#define DDRSS_PHY_1045_DATA 0x0000002A +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x00000015 +#define DDRSS_PHY_1048_DATA 0x0000002A +#define DDRSS_PHY_1049_DATA 0x00000033 +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x0000000C +#define DDRSS_PHY_1052_DATA 0x00000033 +#define DDRSS_PHY_1053_DATA 0x0A418820 +#define DDRSS_PHY_1054_DATA 0x003F0000 +#define DDRSS_PHY_1055_DATA 0x000F013F +#define DDRSS_PHY_1056_DATA 0x20202003 +#define DDRSS_PHY_1057_DATA 0x00202020 +#define DDRSS_PHY_1058_DATA 0x20008008 +#define DDRSS_PHY_1059_DATA 0x00000810 +#define DDRSS_PHY_1060_DATA 0x00000F00 +#define DDRSS_PHY_1061_DATA 0x000405CC +#define DDRSS_PHY_1062_DATA 0x03000004 +#define DDRSS_PHY_1063_DATA 0x00030000 +#define DDRSS_PHY_1064_DATA 0x00000300 +#define DDRSS_PHY_1065_DATA 0x00000300 +#define DDRSS_PHY_1066_DATA 0x00000300 +#define DDRSS_PHY_1067_DATA 0x00000300 +#define DDRSS_PHY_1068_DATA 0x42080010 +#define DDRSS_PHY_1069_DATA 0x0000803E +#define DDRSS_PHY_1070_DATA 0x00000001 +#define DDRSS_PHY_1071_DATA 0x01000002 +#define DDRSS_PHY_1072_DATA 0x00008000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00000000 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000100 +#define DDRSS_PHY_1286_DATA 0x00000200 +#define DDRSS_PHY_1287_DATA 0x00000000 +#define DDRSS_PHY_1288_DATA 0x00000000 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00400000 +#define DDRSS_PHY_1292_DATA 0x00000080 +#define DDRSS_PHY_1293_DATA 0x00DCBA98 +#define DDRSS_PHY_1294_DATA 0x03000000 +#define DDRSS_PHY_1295_DATA 0x00200000 +#define DDRSS_PHY_1296_DATA 0x00000000 +#define DDRSS_PHY_1297_DATA 0x00000000 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x00000000 +#define DDRSS_PHY_1300_DATA 0x00000000 +#define DDRSS_PHY_1301_DATA 0x0000002A +#define DDRSS_PHY_1302_DATA 0x00000015 +#define DDRSS_PHY_1303_DATA 0x00000015 +#define DDRSS_PHY_1304_DATA 0x0000002A +#define DDRSS_PHY_1305_DATA 0x00000033 +#define DDRSS_PHY_1306_DATA 0x0000000C +#define DDRSS_PHY_1307_DATA 0x0000000C +#define DDRSS_PHY_1308_DATA 0x00000033 +#define DDRSS_PHY_1309_DATA 0x0A418820 +#define DDRSS_PHY_1310_DATA 0x00000000 +#define DDRSS_PHY_1311_DATA 0x000F0000 +#define DDRSS_PHY_1312_DATA 0x20202003 +#define DDRSS_PHY_1313_DATA 0x00202020 +#define DDRSS_PHY_1314_DATA 0x20008008 +#define DDRSS_PHY_1315_DATA 0x00000810 +#define DDRSS_PHY_1316_DATA 0x00000F00 +#define DDRSS_PHY_1317_DATA 0x000405CC +#define DDRSS_PHY_1318_DATA 0x03000004 +#define DDRSS_PHY_1319_DATA 0x00030000 +#define DDRSS_PHY_1320_DATA 0x00000300 +#define DDRSS_PHY_1321_DATA 0x00000300 +#define DDRSS_PHY_1322_DATA 0x00000300 +#define DDRSS_PHY_1323_DATA 0x00000300 +#define DDRSS_PHY_1324_DATA 0x42080010 +#define DDRSS_PHY_1325_DATA 0x0000803E +#define DDRSS_PHY_1326_DATA 0x00000001 +#define DDRSS_PHY_1327_DATA 0x01000002 +#define DDRSS_PHY_1328_DATA 0x00008000 +#define DDRSS_PHY_1329_DATA 0x00000000 +#define DDRSS_PHY_1330_DATA 0x00000000 +#define DDRSS_PHY_1331_DATA 0x00000000 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000000 +#define DDRSS_PHY_1334_DATA 0x00000000 +#define DDRSS_PHY_1335_DATA 0x00000000 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x00000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x00000000 +#define DDRSS_PHY_1346_DATA 0x00000000 +#define DDRSS_PHY_1347_DATA 0x00000000 +#define DDRSS_PHY_1348_DATA 0x00000000 +#define DDRSS_PHY_1349_DATA 0x00000000 +#define DDRSS_PHY_1350_DATA 0x00000000 +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000000 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x00000000 +#define DDRSS_PHY_1360_DATA 0x00000000 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00000000 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000000 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x00000000 +#define DDRSS_PHY_1372_DATA 0x00000000 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00000000 +#define DDRSS_PHY_1375_DATA 0x00000000 +#define DDRSS_PHY_1376_DATA 0x00000000 +#define DDRSS_PHY_1377_DATA 0x00000000 +#define DDRSS_PHY_1378_DATA 0x00000000 +#define DDRSS_PHY_1379_DATA 0x00000000 +#define DDRSS_PHY_1380_DATA 0x00000000 +#define DDRSS_PHY_1381_DATA 0x00000000 +#define DDRSS_PHY_1382_DATA 0x00000000 +#define DDRSS_PHY_1383_DATA 0x00000000 +#define DDRSS_PHY_1384_DATA 0x00000000 +#define DDRSS_PHY_1385_DATA 0x00000000 +#define DDRSS_PHY_1386_DATA 0x00000000 +#define DDRSS_PHY_1387_DATA 0x00000000 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x00000000 +#define DDRSS_PHY_1390_DATA 0x00000000 +#define DDRSS_PHY_1391_DATA 0x00000000 +#define DDRSS_PHY_1392_DATA 0x00000000 +#define DDRSS_PHY_1393_DATA 0x00000000 +#define DDRSS_PHY_1394_DATA 0x00000000 +#define DDRSS_PHY_1395_DATA 0x00000000 +#define DDRSS_PHY_1396_DATA 0x00000000 +#define DDRSS_PHY_1397_DATA 0x00000000 +#define DDRSS_PHY_1398_DATA 0x00000000 +#define DDRSS_PHY_1399_DATA 0x00000000 +#define DDRSS_PHY_1400_DATA 0x00000000 +#define DDRSS_PHY_1401_DATA 0x00000000 +#define DDRSS_PHY_1402_DATA 0x00000000 +#define DDRSS_PHY_1403_DATA 0x00000000 +#define DDRSS_PHY_1404_DATA 0x00000000 +#define DDRSS_PHY_1405_DATA 0x00000000 +#define DDRSS_PHY_1406_DATA 0x00000000 +#define DDRSS_PHY_1407_DATA 0x00000000 +#define DDRSS_PHY_1408_DATA 0x00000000 +#define DDRSS_PHY_1409_DATA 0x00000000 +#define DDRSS_PHY_1410_DATA 0x00000000 +#define DDRSS_PHY_1411_DATA 0x00000000 +#define DDRSS_PHY_1412_DATA 0x00000000 +#define DDRSS_PHY_1413_DATA 0x00000000 +#define DDRSS_PHY_1414_DATA 0x00000000 +#define DDRSS_PHY_1415_DATA 0x00000000 +#define DDRSS_PHY_1416_DATA 0x00000000 +#define DDRSS_PHY_1417_DATA 0x00000000 +#define DDRSS_PHY_1418_DATA 0x00000000 +#define DDRSS_PHY_1419_DATA 0x00000000 +#define DDRSS_PHY_1420_DATA 0x00000000 +#define DDRSS_PHY_1421_DATA 0x00000000 +#define DDRSS_PHY_1422_DATA 0x00000000 +#define DDRSS_PHY_1423_DATA 0x00000000 +#define DDRSS_PHY_1424_DATA 0x00000000 +#define DDRSS_PHY_1425_DATA 0x00000000 +#define DDRSS_PHY_1426_DATA 0x00000000 +#define DDRSS_PHY_1427_DATA 0x00000000 +#define DDRSS_PHY_1428_DATA 0x00000000 +#define DDRSS_PHY_1429_DATA 0x00000000 +#define DDRSS_PHY_1430_DATA 0x00000000 +#define DDRSS_PHY_1431_DATA 0x00000000 +#define DDRSS_PHY_1432_DATA 0x00000000 +#define DDRSS_PHY_1433_DATA 0x00000000 +#define DDRSS_PHY_1434_DATA 0x00000000 +#define DDRSS_PHY_1435_DATA 0x00000000 +#define DDRSS_PHY_1436_DATA 0x00000000 +#define DDRSS_PHY_1437_DATA 0x00000000 +#define DDRSS_PHY_1438_DATA 0x00000000 +#define DDRSS_PHY_1439_DATA 0x00000000 +#define DDRSS_PHY_1440_DATA 0x00000000 +#define DDRSS_PHY_1441_DATA 0x00000000 +#define DDRSS_PHY_1442_DATA 0x00000000 +#define DDRSS_PHY_1443_DATA 0x00000000 +#define DDRSS_PHY_1444_DATA 0x00000000 +#define DDRSS_PHY_1445_DATA 0x00000000 +#define DDRSS_PHY_1446_DATA 0x00000000 +#define DDRSS_PHY_1447_DATA 0x00000000 +#define DDRSS_PHY_1448_DATA 0x00000000 +#define DDRSS_PHY_1449_DATA 0x00000000 +#define DDRSS_PHY_1450_DATA 0x00000000 +#define DDRSS_PHY_1451_DATA 0x00000000 +#define DDRSS_PHY_1452_DATA 0x00000000 +#define DDRSS_PHY_1453_DATA 0x00000000 +#define DDRSS_PHY_1454_DATA 0x00000000 +#define DDRSS_PHY_1455_DATA 0x00000000 +#define DDRSS_PHY_1456_DATA 0x00000000 +#define DDRSS_PHY_1457_DATA 0x00000000 +#define DDRSS_PHY_1458_DATA 0x00000000 +#define DDRSS_PHY_1459_DATA 0x00000000 +#define DDRSS_PHY_1460_DATA 0x00000000 +#define DDRSS_PHY_1461_DATA 0x00000000 +#define DDRSS_PHY_1462_DATA 0x00000000 +#define DDRSS_PHY_1463_DATA 0x00000000 +#define DDRSS_PHY_1464_DATA 0x00000000 +#define DDRSS_PHY_1465_DATA 0x00000000 +#define DDRSS_PHY_1466_DATA 0x00000000 +#define DDRSS_PHY_1467_DATA 0x00000000 +#define DDRSS_PHY_1468_DATA 0x00000000 +#define DDRSS_PHY_1469_DATA 0x00000000 +#define DDRSS_PHY_1470_DATA 0x00000000 +#define DDRSS_PHY_1471_DATA 0x00000000 +#define DDRSS_PHY_1472_DATA 0x00000000 +#define DDRSS_PHY_1473_DATA 0x00000000 +#define DDRSS_PHY_1474_DATA 0x00000000 +#define DDRSS_PHY_1475_DATA 0x00000000 +#define DDRSS_PHY_1476_DATA 0x00000000 +#define DDRSS_PHY_1477_DATA 0x00000000 +#define DDRSS_PHY_1478_DATA 0x00000000 +#define DDRSS_PHY_1479_DATA 0x00000000 +#define DDRSS_PHY_1480_DATA 0x00000000 +#define DDRSS_PHY_1481_DATA 0x00000000 +#define DDRSS_PHY_1482_DATA 0x00000000 +#define DDRSS_PHY_1483_DATA 0x00000000 +#define DDRSS_PHY_1484_DATA 0x00000000 +#define DDRSS_PHY_1485_DATA 0x00000000 +#define DDRSS_PHY_1486_DATA 0x00000000 +#define DDRSS_PHY_1487_DATA 0x00000000 +#define DDRSS_PHY_1488_DATA 0x00000000 +#define DDRSS_PHY_1489_DATA 0x00000000 +#define DDRSS_PHY_1490_DATA 0x00000000 +#define DDRSS_PHY_1491_DATA 0x00000000 +#define DDRSS_PHY_1492_DATA 0x00000000 +#define DDRSS_PHY_1493_DATA 0x00000000 +#define DDRSS_PHY_1494_DATA 0x00000000 +#define DDRSS_PHY_1495_DATA 0x00000000 +#define DDRSS_PHY_1496_DATA 0x00000000 +#define DDRSS_PHY_1497_DATA 0x00000000 +#define DDRSS_PHY_1498_DATA 0x00000000 +#define DDRSS_PHY_1499_DATA 0x00000000 +#define DDRSS_PHY_1500_DATA 0x00000000 +#define DDRSS_PHY_1501_DATA 0x00000000 +#define DDRSS_PHY_1502_DATA 0x00000000 +#define DDRSS_PHY_1503_DATA 0x00000000 +#define DDRSS_PHY_1504_DATA 0x00000000 +#define DDRSS_PHY_1505_DATA 0x00000000 +#define DDRSS_PHY_1506_DATA 0x00000000 +#define DDRSS_PHY_1507_DATA 0x00000000 +#define DDRSS_PHY_1508_DATA 0x00000000 +#define DDRSS_PHY_1509_DATA 0x00000000 +#define DDRSS_PHY_1510_DATA 0x00000000 +#define DDRSS_PHY_1511_DATA 0x00000000 +#define DDRSS_PHY_1512_DATA 0x00000000 +#define DDRSS_PHY_1513_DATA 0x00000000 +#define DDRSS_PHY_1514_DATA 0x00000000 +#define DDRSS_PHY_1515_DATA 0x00000000 +#define DDRSS_PHY_1516_DATA 0x00000000 +#define DDRSS_PHY_1517_DATA 0x00000000 +#define DDRSS_PHY_1518_DATA 0x00000000 +#define DDRSS_PHY_1519_DATA 0x00000000 +#define DDRSS_PHY_1520_DATA 0x00000000 +#define DDRSS_PHY_1521_DATA 0x00000000 +#define DDRSS_PHY_1522_DATA 0x00000000 +#define DDRSS_PHY_1523_DATA 0x00000000 +#define DDRSS_PHY_1524_DATA 0x00000000 +#define DDRSS_PHY_1525_DATA 0x00000000 +#define DDRSS_PHY_1526_DATA 0x00000000 +#define DDRSS_PHY_1527_DATA 0x00000000 +#define DDRSS_PHY_1528_DATA 0x00000000 +#define DDRSS_PHY_1529_DATA 0x00000000 +#define DDRSS_PHY_1530_DATA 0x00000000 +#define DDRSS_PHY_1531_DATA 0x00000000 +#define DDRSS_PHY_1532_DATA 0x00000000 +#define DDRSS_PHY_1533_DATA 0x00000000 +#define DDRSS_PHY_1534_DATA 0x00000000 +#define DDRSS_PHY_1535_DATA 0x00000000 +#define DDRSS_PHY_1536_DATA 0x00000000 +#define DDRSS_PHY_1537_DATA 0x00000000 +#define DDRSS_PHY_1538_DATA 0x00000000 +#define DDRSS_PHY_1539_DATA 0x00000000 +#define DDRSS_PHY_1540_DATA 0x00000000 +#define DDRSS_PHY_1541_DATA 0x00000100 +#define DDRSS_PHY_1542_DATA 0x00000200 +#define DDRSS_PHY_1543_DATA 0x00000000 +#define DDRSS_PHY_1544_DATA 0x00000000 +#define DDRSS_PHY_1545_DATA 0x00000000 +#define DDRSS_PHY_1546_DATA 0x00000000 +#define DDRSS_PHY_1547_DATA 0x00400000 +#define DDRSS_PHY_1548_DATA 0x00000080 +#define DDRSS_PHY_1549_DATA 0x00DCBA98 +#define DDRSS_PHY_1550_DATA 0x03000000 +#define DDRSS_PHY_1551_DATA 0x00200000 +#define DDRSS_PHY_1552_DATA 0x00000000 +#define DDRSS_PHY_1553_DATA 0x00000000 +#define DDRSS_PHY_1554_DATA 0x00000000 +#define DDRSS_PHY_1555_DATA 0x00000000 +#define DDRSS_PHY_1556_DATA 0x00000000 +#define DDRSS_PHY_1557_DATA 0x0000002A +#define DDRSS_PHY_1558_DATA 0x00000015 +#define DDRSS_PHY_1559_DATA 0x00000015 +#define DDRSS_PHY_1560_DATA 0x0000002A +#define DDRSS_PHY_1561_DATA 0x00000033 +#define DDRSS_PHY_1562_DATA 0x0000000C +#define DDRSS_PHY_1563_DATA 0x0000000C +#define DDRSS_PHY_1564_DATA 0x00000033 +#define DDRSS_PHY_1565_DATA 0x0A418820 +#define DDRSS_PHY_1566_DATA 0x10000000 +#define DDRSS_PHY_1567_DATA 0x000F0000 +#define DDRSS_PHY_1568_DATA 0x20202003 +#define DDRSS_PHY_1569_DATA 0x00202020 +#define DDRSS_PHY_1570_DATA 0x20008008 +#define DDRSS_PHY_1571_DATA 0x00000810 +#define DDRSS_PHY_1572_DATA 0x00000F00 +#define DDRSS_PHY_1573_DATA 0x000405CC +#define DDRSS_PHY_1574_DATA 0x03000004 +#define DDRSS_PHY_1575_DATA 0x00030000 +#define DDRSS_PHY_1576_DATA 0x00000300 +#define DDRSS_PHY_1577_DATA 0x00000300 +#define DDRSS_PHY_1578_DATA 0x00000300 +#define DDRSS_PHY_1579_DATA 0x00000300 +#define DDRSS_PHY_1580_DATA 0x42080010 +#define DDRSS_PHY_1581_DATA 0x0000803E +#define DDRSS_PHY_1582_DATA 0x00000001 +#define DDRSS_PHY_1583_DATA 0x01000002 +#define DDRSS_PHY_1584_DATA 0x00008000 +#define DDRSS_PHY_1585_DATA 0x00000000 +#define DDRSS_PHY_1586_DATA 0x00000000 +#define DDRSS_PHY_1587_DATA 0x00000000 +#define DDRSS_PHY_1588_DATA 0x00000000 +#define DDRSS_PHY_1589_DATA 0x00000000 +#define DDRSS_PHY_1590_DATA 0x00000000 +#define DDRSS_PHY_1591_DATA 0x00000000 +#define DDRSS_PHY_1592_DATA 0x00000000 +#define DDRSS_PHY_1593_DATA 0x00000000 +#define DDRSS_PHY_1594_DATA 0x00000000 +#define DDRSS_PHY_1595_DATA 0x00000000 +#define DDRSS_PHY_1596_DATA 0x00000000 +#define DDRSS_PHY_1597_DATA 0x00000000 +#define DDRSS_PHY_1598_DATA 0x00000000 +#define DDRSS_PHY_1599_DATA 0x00000000 +#define DDRSS_PHY_1600_DATA 0x00000000 +#define DDRSS_PHY_1601_DATA 0x00000000 +#define DDRSS_PHY_1602_DATA 0x00000000 +#define DDRSS_PHY_1603_DATA 0x00000000 +#define DDRSS_PHY_1604_DATA 0x00000000 +#define DDRSS_PHY_1605_DATA 0x00000000 +#define DDRSS_PHY_1606_DATA 0x00000000 +#define DDRSS_PHY_1607_DATA 0x00000000 +#define DDRSS_PHY_1608_DATA 0x00000000 +#define DDRSS_PHY_1609_DATA 0x00000000 +#define DDRSS_PHY_1610_DATA 0x00000000 +#define DDRSS_PHY_1611_DATA 0x00000000 +#define DDRSS_PHY_1612_DATA 0x00000000 +#define DDRSS_PHY_1613_DATA 0x00000000 +#define DDRSS_PHY_1614_DATA 0x00000000 +#define DDRSS_PHY_1615_DATA 0x00000000 +#define DDRSS_PHY_1616_DATA 0x00000000 +#define DDRSS_PHY_1617_DATA 0x00000000 +#define DDRSS_PHY_1618_DATA 0x00000000 +#define DDRSS_PHY_1619_DATA 0x00000000 +#define DDRSS_PHY_1620_DATA 0x00000000 +#define DDRSS_PHY_1621_DATA 0x00000000 +#define DDRSS_PHY_1622_DATA 0x00000000 +#define DDRSS_PHY_1623_DATA 0x00000000 +#define DDRSS_PHY_1624_DATA 0x00000000 +#define DDRSS_PHY_1625_DATA 0x00000000 +#define DDRSS_PHY_1626_DATA 0x00000000 +#define DDRSS_PHY_1627_DATA 0x00000000 +#define DDRSS_PHY_1628_DATA 0x00000000 +#define DDRSS_PHY_1629_DATA 0x00000000 +#define DDRSS_PHY_1630_DATA 0x00000000 +#define DDRSS_PHY_1631_DATA 0x00000000 +#define DDRSS_PHY_1632_DATA 0x00000000 +#define DDRSS_PHY_1633_DATA 0x00000000 +#define DDRSS_PHY_1634_DATA 0x00000000 +#define DDRSS_PHY_1635_DATA 0x00000000 +#define DDRSS_PHY_1636_DATA 0x00000000 +#define DDRSS_PHY_1637_DATA 0x00000000 +#define DDRSS_PHY_1638_DATA 0x00000000 +#define DDRSS_PHY_1639_DATA 0x00000000 +#define DDRSS_PHY_1640_DATA 0x00000000 +#define DDRSS_PHY_1641_DATA 0x00000000 +#define DDRSS_PHY_1642_DATA 0x00000000 +#define DDRSS_PHY_1643_DATA 0x00000000 +#define DDRSS_PHY_1644_DATA 0x00000000 +#define DDRSS_PHY_1645_DATA 0x00000000 +#define DDRSS_PHY_1646_DATA 0x00000000 +#define DDRSS_PHY_1647_DATA 0x00000000 +#define DDRSS_PHY_1648_DATA 0x00000000 +#define DDRSS_PHY_1649_DATA 0x00000000 +#define DDRSS_PHY_1650_DATA 0x00000000 +#define DDRSS_PHY_1651_DATA 0x00000000 +#define DDRSS_PHY_1652_DATA 0x00000000 +#define DDRSS_PHY_1653_DATA 0x00000000 +#define DDRSS_PHY_1654_DATA 0x00000000 +#define DDRSS_PHY_1655_DATA 0x00000000 +#define DDRSS_PHY_1656_DATA 0x00000000 +#define DDRSS_PHY_1657_DATA 0x00000000 +#define DDRSS_PHY_1658_DATA 0x00000000 +#define DDRSS_PHY_1659_DATA 0x00000000 +#define DDRSS_PHY_1660_DATA 0x00000000 +#define DDRSS_PHY_1661_DATA 0x00000000 +#define DDRSS_PHY_1662_DATA 0x00000000 +#define DDRSS_PHY_1663_DATA 0x00000000 +#define DDRSS_PHY_1664_DATA 0x00000000 +#define DDRSS_PHY_1665_DATA 0x00000000 +#define DDRSS_PHY_1666_DATA 0x00000000 +#define DDRSS_PHY_1667_DATA 0x00000000 +#define DDRSS_PHY_1668_DATA 0x00000000 +#define DDRSS_PHY_1669_DATA 0x00000000 +#define DDRSS_PHY_1670_DATA 0x00000000 +#define DDRSS_PHY_1671_DATA 0x00000000 +#define DDRSS_PHY_1672_DATA 0x00000000 +#define DDRSS_PHY_1673_DATA 0x00000000 +#define DDRSS_PHY_1674_DATA 0x00000000 +#define DDRSS_PHY_1675_DATA 0x00000000 +#define DDRSS_PHY_1676_DATA 0x00000000 +#define DDRSS_PHY_1677_DATA 0x00000000 +#define DDRSS_PHY_1678_DATA 0x00000000 +#define DDRSS_PHY_1679_DATA 0x00000000 +#define DDRSS_PHY_1680_DATA 0x00000000 +#define DDRSS_PHY_1681_DATA 0x00000000 +#define DDRSS_PHY_1682_DATA 0x00000000 +#define DDRSS_PHY_1683_DATA 0x00000000 +#define DDRSS_PHY_1684_DATA 0x00000000 +#define DDRSS_PHY_1685_DATA 0x00000000 +#define DDRSS_PHY_1686_DATA 0x00000000 +#define DDRSS_PHY_1687_DATA 0x00000000 +#define DDRSS_PHY_1688_DATA 0x00000000 +#define DDRSS_PHY_1689_DATA 0x00000000 +#define DDRSS_PHY_1690_DATA 0x00000000 +#define DDRSS_PHY_1691_DATA 0x00000000 +#define DDRSS_PHY_1692_DATA 0x00000000 +#define DDRSS_PHY_1693_DATA 0x00000000 +#define DDRSS_PHY_1694_DATA 0x00000000 +#define DDRSS_PHY_1695_DATA 0x00000000 +#define DDRSS_PHY_1696_DATA 0x00000000 +#define DDRSS_PHY_1697_DATA 0x00000000 +#define DDRSS_PHY_1698_DATA 0x00000000 +#define DDRSS_PHY_1699_DATA 0x00000000 +#define DDRSS_PHY_1700_DATA 0x00000000 +#define DDRSS_PHY_1701_DATA 0x00000000 +#define DDRSS_PHY_1702_DATA 0x00000000 +#define DDRSS_PHY_1703_DATA 0x00000000 +#define DDRSS_PHY_1704_DATA 0x00000000 +#define DDRSS_PHY_1705_DATA 0x00000000 +#define DDRSS_PHY_1706_DATA 0x00000000 +#define DDRSS_PHY_1707_DATA 0x00000000 +#define DDRSS_PHY_1708_DATA 0x00000000 +#define DDRSS_PHY_1709_DATA 0x00000000 +#define DDRSS_PHY_1710_DATA 0x00000000 +#define DDRSS_PHY_1711_DATA 0x00000000 +#define DDRSS_PHY_1712_DATA 0x00000000 +#define DDRSS_PHY_1713_DATA 0x00000000 +#define DDRSS_PHY_1714_DATA 0x00000000 +#define DDRSS_PHY_1715_DATA 0x00000000 +#define DDRSS_PHY_1716_DATA 0x00000000 +#define DDRSS_PHY_1717_DATA 0x00000000 +#define DDRSS_PHY_1718_DATA 0x00000000 +#define DDRSS_PHY_1719_DATA 0x00000000 +#define DDRSS_PHY_1720_DATA 0x00000000 +#define DDRSS_PHY_1721_DATA 0x00000000 +#define DDRSS_PHY_1722_DATA 0x00000000 +#define DDRSS_PHY_1723_DATA 0x00000000 +#define DDRSS_PHY_1724_DATA 0x00000000 +#define DDRSS_PHY_1725_DATA 0x00000000 +#define DDRSS_PHY_1726_DATA 0x00000000 +#define DDRSS_PHY_1727_DATA 0x00000000 +#define DDRSS_PHY_1728_DATA 0x00000000 +#define DDRSS_PHY_1729_DATA 0x00000000 +#define DDRSS_PHY_1730_DATA 0x00000000 +#define DDRSS_PHY_1731_DATA 0x00000000 +#define DDRSS_PHY_1732_DATA 0x00000000 +#define DDRSS_PHY_1733_DATA 0x00000000 +#define DDRSS_PHY_1734_DATA 0x00000000 +#define DDRSS_PHY_1735_DATA 0x00000000 +#define DDRSS_PHY_1736_DATA 0x00000000 +#define DDRSS_PHY_1737_DATA 0x00000000 +#define DDRSS_PHY_1738_DATA 0x00000000 +#define DDRSS_PHY_1739_DATA 0x00000000 +#define DDRSS_PHY_1740_DATA 0x00000000 +#define DDRSS_PHY_1741_DATA 0x00000000 +#define DDRSS_PHY_1742_DATA 0x00000000 +#define DDRSS_PHY_1743_DATA 0x00000000 +#define DDRSS_PHY_1744_DATA 0x00000000 +#define DDRSS_PHY_1745_DATA 0x00000000 +#define DDRSS_PHY_1746_DATA 0x00000000 +#define DDRSS_PHY_1747_DATA 0x00000000 +#define DDRSS_PHY_1748_DATA 0x00000000 +#define DDRSS_PHY_1749_DATA 0x00000000 +#define DDRSS_PHY_1750_DATA 0x00000000 +#define DDRSS_PHY_1751_DATA 0x00000000 +#define DDRSS_PHY_1752_DATA 0x00000000 +#define DDRSS_PHY_1753_DATA 0x00000000 +#define DDRSS_PHY_1754_DATA 0x00000000 +#define DDRSS_PHY_1755_DATA 0x00000000 +#define DDRSS_PHY_1756_DATA 0x00000000 +#define DDRSS_PHY_1757_DATA 0x00000000 +#define DDRSS_PHY_1758_DATA 0x00000000 +#define DDRSS_PHY_1759_DATA 0x00000000 +#define DDRSS_PHY_1760_DATA 0x00000000 +#define DDRSS_PHY_1761_DATA 0x00000000 +#define DDRSS_PHY_1762_DATA 0x00000000 +#define DDRSS_PHY_1763_DATA 0x00000000 +#define DDRSS_PHY_1764_DATA 0x00000000 +#define DDRSS_PHY_1765_DATA 0x00000000 +#define DDRSS_PHY_1766_DATA 0x00000000 +#define DDRSS_PHY_1767_DATA 0x00000000 +#define DDRSS_PHY_1768_DATA 0x00000000 +#define DDRSS_PHY_1769_DATA 0x00000000 +#define DDRSS_PHY_1770_DATA 0x00000000 +#define DDRSS_PHY_1771_DATA 0x00000000 +#define DDRSS_PHY_1772_DATA 0x00000000 +#define DDRSS_PHY_1773_DATA 0x00000000 +#define DDRSS_PHY_1774_DATA 0x00000000 +#define DDRSS_PHY_1775_DATA 0x00000000 +#define DDRSS_PHY_1776_DATA 0x00000000 +#define DDRSS_PHY_1777_DATA 0x00000000 +#define DDRSS_PHY_1778_DATA 0x00000000 +#define DDRSS_PHY_1779_DATA 0x00000000 +#define DDRSS_PHY_1780_DATA 0x00000000 +#define DDRSS_PHY_1781_DATA 0x00000000 +#define DDRSS_PHY_1782_DATA 0x00000000 +#define DDRSS_PHY_1783_DATA 0x00000000 +#define DDRSS_PHY_1784_DATA 0x00000000 +#define DDRSS_PHY_1785_DATA 0x00000000 +#define DDRSS_PHY_1786_DATA 0x00000000 +#define DDRSS_PHY_1787_DATA 0x00000000 +#define DDRSS_PHY_1788_DATA 0x00000000 +#define DDRSS_PHY_1789_DATA 0x00000000 +#define DDRSS_PHY_1790_DATA 0x00000000 +#define DDRSS_PHY_1791_DATA 0x00000000 +#define DDRSS_PHY_1792_DATA 0x00000000 +#define DDRSS_PHY_1793_DATA 0x00010100 +#define DDRSS_PHY_1794_DATA 0x00000000 +#define DDRSS_PHY_1795_DATA 0x00000000 +#define DDRSS_PHY_1796_DATA 0x00000000 +#define DDRSS_PHY_1797_DATA 0x00000000 +#define DDRSS_PHY_1798_DATA 0x00050000 +#define DDRSS_PHY_1799_DATA 0x04000000 +#define DDRSS_PHY_1800_DATA 0x00000055 +#define DDRSS_PHY_1801_DATA 0x00000000 +#define DDRSS_PHY_1802_DATA 0x00000000 +#define DDRSS_PHY_1803_DATA 0x00000000 +#define DDRSS_PHY_1804_DATA 0x00000000 +#define DDRSS_PHY_1805_DATA 0x00002001 +#define DDRSS_PHY_1806_DATA 0x00004003 +#define DDRSS_PHY_1807_DATA 0x50020028 +#define DDRSS_PHY_1808_DATA 0x01010000 +#define DDRSS_PHY_1809_DATA 0x80080001 +#define DDRSS_PHY_1810_DATA 0x10200000 +#define DDRSS_PHY_1811_DATA 0x00000008 +#define DDRSS_PHY_1812_DATA 0x00000000 +#define DDRSS_PHY_1813_DATA 0x06000000 +#define DDRSS_PHY_1814_DATA 0x010F0F0E +#define DDRSS_PHY_1815_DATA 0x00040101 +#define DDRSS_PHY_1816_DATA 0x0000010F +#define DDRSS_PHY_1817_DATA 0x00000000 +#define DDRSS_PHY_1818_DATA 0x00000064 +#define DDRSS_PHY_1819_DATA 0x00000000 +#define DDRSS_PHY_1820_DATA 0x00000000 +#define DDRSS_PHY_1821_DATA 0x0F0F0F0F +#define DDRSS_PHY_1822_DATA 0x0F0F0F0F +#define DDRSS_PHY_1823_DATA 0x0F0F0F0F +#define DDRSS_PHY_1824_DATA 0x02010804 +#define DDRSS_PHY_1825_DATA 0x00800120 +#define DDRSS_PHY_1826_DATA 0x00041B42 +#define DDRSS_PHY_1827_DATA 0x00004201 +#define DDRSS_PHY_1828_DATA 0x00000000 +#define DDRSS_PHY_1829_DATA 0x00000000 +#define DDRSS_PHY_1830_DATA 0x00000000 +#define DDRSS_PHY_1831_DATA 0x00000000 +#define DDRSS_PHY_1832_DATA 0x00000000 +#define DDRSS_PHY_1833_DATA 0x00000000 +#define DDRSS_PHY_1834_DATA 0x03010100 +#define DDRSS_PHY_1835_DATA 0x00540007 +#define DDRSS_PHY_1836_DATA 0x000040A2 +#define DDRSS_PHY_1837_DATA 0x00024410 +#define DDRSS_PHY_1838_DATA 0x00004410 +#define DDRSS_PHY_1839_DATA 0x00004410 +#define DDRSS_PHY_1840_DATA 0x00004410 +#define DDRSS_PHY_1841_DATA 0x00004410 +#define DDRSS_PHY_1842_DATA 0x00004410 +#define DDRSS_PHY_1843_DATA 0x00004410 +#define DDRSS_PHY_1844_DATA 0x00004410 +#define DDRSS_PHY_1845_DATA 0x00004410 +#define DDRSS_PHY_1846_DATA 0x00004410 +#define DDRSS_PHY_1847_DATA 0x00000000 +#define DDRSS_PHY_1848_DATA 0x00000076 +#define DDRSS_PHY_1849_DATA 0x00000400 +#define DDRSS_PHY_1850_DATA 0x00000008 +#define DDRSS_PHY_1851_DATA 0x00000000 +#define DDRSS_PHY_1852_DATA 0x00000000 +#define DDRSS_PHY_1853_DATA 0x00000000 +#define DDRSS_PHY_1854_DATA 0x00000000 +#define DDRSS_PHY_1855_DATA 0x00000000 +#define DDRSS_PHY_1856_DATA 0x03000000 +#define DDRSS_PHY_1857_DATA 0x00000000 +#define DDRSS_PHY_1858_DATA 0x00000000 +#define DDRSS_PHY_1859_DATA 0x00000000 +#define DDRSS_PHY_1860_DATA 0x04102006 +#define DDRSS_PHY_1861_DATA 0x00041020 +#define DDRSS_PHY_1862_DATA 0x01C98C98 +#define DDRSS_PHY_1863_DATA 0x3F400000 +#define DDRSS_PHY_1864_DATA 0x3F3F1F3F +#define DDRSS_PHY_1865_DATA 0x0000001F +#define DDRSS_PHY_1866_DATA 0x00000000 +#define DDRSS_PHY_1867_DATA 0x00000000 +#define DDRSS_PHY_1868_DATA 0x00000000 +#define DDRSS_PHY_1869_DATA 0x00000001 +#define DDRSS_PHY_1870_DATA 0x00000000 +#define DDRSS_PHY_1871_DATA 0x00000000 +#define DDRSS_PHY_1872_DATA 0x00000000 +#define DDRSS_PHY_1873_DATA 0x00000000 +#define DDRSS_PHY_1874_DATA 0x76543210 +#define DDRSS_PHY_1875_DATA 0x06010198 +#define DDRSS_PHY_1876_DATA 0x00000000 +#define DDRSS_PHY_1877_DATA 0x00000000 +#define DDRSS_PHY_1878_DATA 0x00000000 +#define DDRSS_PHY_1879_DATA 0x00040700 +#define DDRSS_PHY_1880_DATA 0x00000000 +#define DDRSS_PHY_1881_DATA 0x00000000 +#define DDRSS_PHY_1882_DATA 0x00000000 +#define DDRSS_PHY_1883_DATA 0x00000000 +#define DDRSS_PHY_1884_DATA 0x00000000 +#define DDRSS_PHY_1885_DATA 0x00000002 +#define DDRSS_PHY_1886_DATA 0x00000000 +#define DDRSS_PHY_1887_DATA 0x00000000 +#define DDRSS_PHY_1888_DATA 0x0001F7C4 +#define DDRSS_PHY_1889_DATA 0x04000004 +#define DDRSS_PHY_1890_DATA 0x00000000 +#define DDRSS_PHY_1891_DATA 0x00001142 +#define DDRSS_PHY_1892_DATA 0x01020000 +#define DDRSS_PHY_1893_DATA 0x00000080 +#define DDRSS_PHY_1894_DATA 0x03900390 +#define DDRSS_PHY_1895_DATA 0x03900390 +#define DDRSS_PHY_1896_DATA 0x03900390 +#define DDRSS_PHY_1897_DATA 0x03900390 +#define DDRSS_PHY_1898_DATA 0x03000300 +#define DDRSS_PHY_1899_DATA 0x03000300 +#define DDRSS_PHY_1900_DATA 0x00000300 +#define DDRSS_PHY_1901_DATA 0x00000300 +#define DDRSS_PHY_1902_DATA 0x00000300 +#define DDRSS_PHY_1903_DATA 0x00000300 +#define DDRSS_PHY_1904_DATA 0x00000005 +#define DDRSS_PHY_1905_DATA 0x3183BF77 +#define DDRSS_PHY_1906_DATA 0x00000000 +#define DDRSS_PHY_1907_DATA 0x0C000DFF +#define DDRSS_PHY_1908_DATA 0x30000DFF +#define DDRSS_PHY_1909_DATA 0x3F0DFF11 +#define DDRSS_PHY_1910_DATA 0x00EF0000 +#define DDRSS_PHY_1911_DATA 0x780DFFCC +#define DDRSS_PHY_1912_DATA 0x00000C11 +#define DDRSS_PHY_1913_DATA 0x00018011 +#define DDRSS_PHY_1914_DATA 0x0089FF00 +#define DDRSS_PHY_1915_DATA 0x000C3F11 +#define DDRSS_PHY_1916_DATA 0x01990000 +#define DDRSS_PHY_1917_DATA 0x000C3F11 +#define DDRSS_PHY_1918_DATA 0x01990000 +#define DDRSS_PHY_1919_DATA 0x3F0DFF11 +#define DDRSS_PHY_1920_DATA 0x00EF0000 +#define DDRSS_PHY_1921_DATA 0x00018011 +#define DDRSS_PHY_1922_DATA 0x0089FF00 +#define DDRSS_PHY_1923_DATA 0x20040006 diff --git a/arch/arm/dts/k3-j722s-evm-u-boot.dtsi b/arch/arm/dts/k3-j722s-evm-u-boot.dtsi new file mode 100644 index 0000000000..4dad876a91 --- /dev/null +++ b/arch/arm/dts/k3-j722s-evm-u-boot.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common J722S EVM dts file for SPLs + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-j722s-binman.dtsi" + +/ { + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &main_timer0; + }; +}; + +&main_pktdma { + reg = <0x00 0x485c0000 0x00 0x100>, + <0x00 0x4a800000 0x00 0x20000>, + <0x00 0x4aa00000 0x00 0x40000>, + <0x00 0x4b800000 0x00 0x400000>, + <0x00 0x485e0000 0x00 0x20000>, + <0x00 0x484a0000 0x00 0x4000>, + <0x00 0x484c0000 0x00 0x2000>, + <0x00 0x48430000 0x00 0x4000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", + "cfg", "tchan", "rchan", "rflow"; +}; diff --git a/arch/arm/dts/k3-j722s-r5-evm.dts b/arch/arm/dts/k3-j722s-r5-evm.dts new file mode 100644 index 0000000000..d49049db7e --- /dev/null +++ b/arch/arm/dts/k3-j722s-r5-evm.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * J722S EVM dts file for R5 SPL + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-j722s-evm.dts" +#include "k3-j722s-evm-u-boot.dtsi" + +#include "k3-j722s-ddr-lp4-50-3733.dtsi" +#include "k3-am62a-ddr.dtsi" + +/ { + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + serial0 = &wkup_uart0; + serial2 = &main_uart0; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + clocks = <&k3_clks 61 0>; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <1200000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-all; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <36>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 22>, + <&secure_proxy_main 23>; + bootph-all; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; + +&cbass_main { + sa3_secproxy: secproxy@44880000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg = <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>, + <0x00 0x43600000 0x00 0x10000>; + reg-names = "rt", "scfg", "target_data"; + bootph-all; + }; + + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_main 1>, + <&secure_proxy_main 0>, + <&sa3_secproxy 0>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-all; + }; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + status = "okay"; +}; -- cgit v1.2.3 From b5d58d70642fc3b08e117128dc897d0a3ec98798 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Mon, 18 Dec 2023 21:26:35 +0530 Subject: configs: introduce configs needed for the J722S Introduce the initial configs needed to support the J722S SoC family. Signed-off-by: Vaishnav Achath Signed-off-by: Jayesh Choudhary --- configs/j722s_evm_a53_defconfig | 179 ++++++++++++++++++++++++++++++++++++++++ configs/j722s_evm_r5_defconfig | 138 +++++++++++++++++++++++++++++++ include/configs/j722s_evm.h | 17 ++++ 3 files changed, 334 insertions(+) create mode 100644 configs/j722s_evm_a53_defconfig create mode 100644 configs/j722s_evm_r5_defconfig create mode 100644 include/configs/j722s_evm.h diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig new file mode 100644 index 0000000000..08eff9731a --- /dev/null +++ b/configs/j722s_evm_a53_defconfig @@ -0,0 +1,179 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_EEPROM_CHIP_ADDRESS=0x51 +CONFIG_TI_SECURE_DEVICE=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_J722S=y +CONFIG_K3_ATF_LOAD_ADDR=0x9e780000 +CONFIG_TARGET_J722S_A53_EVM=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 +CONFIG_SF_DEFAULT_SPEED=25000000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="k3-j722s-evm" +CONFIG_SPL_TEXT_BASE=0x80080000 +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 +CONFIG_SPL_THERMAL=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_MTD=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 +CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_SPL_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_I2C_EEPROM=y +CONFIG_SPL_I2C_EEPROM=y +CONFIG_FS_LOADER=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_PHY_TI_DP83867=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_REMOTEPROC_TI_K3_DSP=y +CONFIG_REMOTEPROC_TI_K3_R5F=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_SPL_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_AM62=y +CONFIG_USB_DWC3_AM62=y +CONFIG_SPL_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_SPL_DFU=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig new file mode 100644 index 0000000000..c131ccc6dd --- /dev/null +++ b/configs/j722s_evm_r5_defconfig @@ -0,0 +1,138 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_EEPROM_CHIP_ADDRESS=0x51 +CONFIG_TI_SECURE_DEVICE=y +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SOC_K3_J722S=y +CONFIG_TARGET_J722S_R5_EVM=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c4a7f0 +CONFIG_SF_DEFAULT_SPEED=25000000 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x680000 +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="k3-j722s-r5-evm" +CONFIG_SPL_TEXT_BASE=0x43c00000 +CONFIG_DM_RESET=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_SIZE_LIMIT=0x3C000 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x5000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_MAX_SIZE=0x3B000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x43c4b000 +CONFIG_SPL_BSS_MAX_SIZE=0x3000 +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 +CONFIG_SPL_EARLY_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_DMA=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 +CONFIG_SPL_THERMAL=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +# CONFIG_NET is not set +CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_SCI_PROTOCOL=y +# CONFIG_GPIO is not set +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_RESET_TI_SCI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y diff --git a/include/configs/j722s_evm.h b/include/configs/j722s_evm.h new file mode 100644 index 0000000000..d052ff2553 --- /dev/null +++ b/include/configs/j722s_evm.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for K3 J722S SoC family + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef __CONFIG_J722S_EVM_H +#define __CONFIG_J722S_EVM_H + +#include +#include + +/* Now for the remaining common defines */ +#include + +#endif /* __CONFIG_J722S_EVM_H */ -- cgit v1.2.3 From 62aa27098647ab005bac275fe0193f2a1a339942 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Mon, 18 Dec 2023 21:26:36 +0530 Subject: arm: dts: k3-j722s-evm: Sync with Linux CPSW3G DT Sync with Linux device-tree w.r.t. CPSW3G. With this, MAC Port 1 of the CPSW3G instance of CPSW Ethernet Switch is functional in RGMII-RXID mode of operation. Signed-off-by: Siddharth Vadapalli Signed-off-by: Jayesh Choudhary --- arch/arm/dts/k3-j722s-evm.dts | 51 +++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/k3-j722s.dtsi | 4 ++++ 2 files changed, 55 insertions(+) diff --git a/arch/arm/dts/k3-j722s-evm.dts b/arch/arm/dts/k3-j722s-evm.dts index acdad22531..15c402662b 100644 --- a/arch/arm/dts/k3-j722s-evm.dts +++ b/arch/arm/dts/k3-j722s-evm.dts @@ -9,6 +9,7 @@ /dts-v1/; #include "k3-j722s.dtsi" +#include / { compatible = "ti,j722s-evm", "ti,j722s"; @@ -159,6 +160,32 @@ >; bootph-all; }; + + mdio_pins_default: mdio-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ + J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ + >; + bootph-all; + }; + + rgmii1_pins_default: rgmii1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ + J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ + J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ + J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ + J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ + J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ + J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ + J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ + J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ + J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ + J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ + J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ + >; + bootph-all; + }; }; &main_gpio1 { @@ -293,3 +320,27 @@ &wkup_r5fss0 { status = "disabled"; }; + +&cpsw3g { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins_default>; +}; + +&cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; diff --git a/arch/arm/dts/k3-j722s.dtsi b/arch/arm/dts/k3-j722s.dtsi index c876be927d..17555145cc 100644 --- a/arch/arm/dts/k3-j722s.dtsi +++ b/arch/arm/dts/k3-j722s.dtsi @@ -89,3 +89,7 @@ reg = <0x00 0x70000000 0x00 0x40000>; ranges = <0x00 0x00 0x70000000 0x40000>; }; + +&cpsw_port2 { + status = "disabled"; +}; -- cgit v1.2.3 From a51316d36812d65ca740ff36cc56727e5e931605 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Mon, 18 Dec 2023 21:26:37 +0530 Subject: arch: arm: mach-k3: Update ARM64 MMU entries for J722S Update ARM64 MMU entries for J722S to support early remoteproc boot requirements. Signed-off-by: Vaishnav Achath Signed-off-by: Jayesh Choudhary --- arch/arm/mach-k3/arm64-mmu.c | 52 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 50 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index c26a015166..696b276058 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -235,8 +235,7 @@ struct mm_region *mem_map = j721s2_mem_map; #endif /* CONFIG_SOC_K3_J721S2 */ #if defined(CONFIG_SOC_K3_AM642) || defined(CONFIG_SOC_K3_AM625) || \ - defined(CONFIG_SOC_K3_AM62A7) || defined(CONFIG_SOC_K3_AM62P5) || \ - defined(CONFIG_SOC_K3_J722S) + defined(CONFIG_SOC_K3_AM62A7) || defined(CONFIG_SOC_K3_AM62P5) /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3) @@ -278,6 +277,55 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = { struct mm_region *mem_map = am64_mem_map; #endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 || ... */ +#if defined(CONFIG_SOC_K3_J722S) + +#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4) + +/* ToDo: Add 64bit IO */ +struct mm_region j722s_mem_map[NR_MMU_REGIONS] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x880000000UL, + .phys = 0x880000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x500000000UL, + .phys = 0x500000000UL, + .size = 0x400000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + .virt = 0xa0000000UL, + .phys = 0xa0000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | + PTE_BLOCK_NON_SHARE + }, + { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = j722s_mem_map; +#endif /* CONFIG_SOC_K3_J722S */ + #if defined(CONFIG_SOC_K3_J784S4) #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5) -- cgit v1.2.3 From c837e0c05ac0d769c93d883abfa668fe42d8041c Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Thu, 21 Dec 2023 11:13:30 +0530 Subject: binman: etype: dm: Add entry type for TI DM commit 23d2ef91efa40d525a4a5557704184bcfd64ca16 upstream K3 devices introduces the concept of centralized power, resource and security management to System Firmware. This is to overcome challenges by the traditional approach that implements system control functions on each of the processing units. The software interface for System Firmware is split into TIFS and DM. DM (Device Manager) is responsible for resource and power management from secure and non-secure hosts. This additional binary is necessary for specific platforms' ROM boot images and is to be packaged into tispl.bin Add an entry for DM. The entry can be used for the packaging of tispl.bin by binman along with ATF and TEE. Signed-off-by: Neha Malcom Francis Reviewed-by: Andrew Davis --- Makefile | 1 + tools/binman/entries.rst | 14 ++++++++++++++ tools/binman/etype/ti_dm.py | 22 ++++++++++++++++++++++ tools/binman/ftest.py | 7 +++++++ tools/binman/test/225_ti_dm.dts | 13 +++++++++++++ 5 files changed, 57 insertions(+) create mode 100644 tools/binman/etype/ti_dm.py create mode 100644 tools/binman/test/225_ti_dm.dts diff --git a/Makefile b/Makefile index af1408222d..e07c1137ba 100644 --- a/Makefile +++ b/Makefile @@ -1333,6 +1333,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \ $(foreach f,$(BINMAN_INDIRS),-I $(f)) \ -a atf-bl31-path=${BL31} \ -a tee-os-path=${TEE} \ + -a ti-dm-path=${TI_DM} \ -a opensbi-path=${OPENSBI} \ -a default-dt=$(default_dt) \ -a scp-path=$(SCP) \ diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst index fa6d1b6afa..2339a5ec9d 100644 --- a/tools/binman/entries.rst +++ b/tools/binman/entries.rst @@ -1701,6 +1701,20 @@ the included board config binaries. Example:: +.. _etype_ti_dm: + +Entry: ti-dm: TI Device Manager (DM) blob +----------------------------------------- + +Properties / Entry arguments: + - ti-dm-path: Filename of file to read into the entry, typically ti-dm.bin + +This entry holds the device manager responsible for resource and power management +in K3 devices. See https://software-dl.ti.com/tisci/esd/latest/ for more information +about TI DM. + + + .. _etype_ti_secure: Entry: ti-secure: Entry containing a TI x509 certificate binary diff --git a/tools/binman/etype/ti_dm.py b/tools/binman/etype/ti_dm.py new file mode 100644 index 0000000000..0faa0bf0ca --- /dev/null +++ b/tools/binman/etype/ti_dm.py @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# Written by Neha Malcom Francis +# +# Entry-type module for TI Device Manager (DM) +# + +from binman.etype.blob_named_by_arg import Entry_blob_named_by_arg + +class Entry_ti_dm(Entry_blob_named_by_arg): + """TI Device Manager (DM) blob + + Properties / Entry arguments: + - ti-dm-path: Filename of file to read into the entry, typically ti-dm.bin + + This entry holds the device manager responsible for resource and power management + in K3 devices. See https://software-dl.ti.com/tisci/esd/latest/ for more information + about TI DM. + """ + def __init__(self, section, etype, node): + super().__init__(section, etype, node, 'ti-dm') + self.external = True diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index 5a5da4f53d..db2d830600 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -87,6 +87,7 @@ FSP_S_DATA = b'fsp_s' FSP_T_DATA = b'fsp_t' ATF_BL31_DATA = b'bl31' TEE_OS_DATA = b'this is some tee OS data' +TI_DM_DATA = b'tidmtidm' ATF_BL2U_DATA = b'bl2u' OPENSBI_DATA = b'opensbi' SCP_DATA = b'scp' @@ -208,6 +209,7 @@ class TestFunctional(unittest.TestCase): TestFunctional._MakeInputFile('compress_big', COMPRESS_DATA_BIG) TestFunctional._MakeInputFile('bl31.bin', ATF_BL31_DATA) TestFunctional._MakeInputFile('tee-pager.bin', TEE_OS_DATA) + TestFunctional._MakeInputFile('dm.bin', TI_DM_DATA) TestFunctional._MakeInputFile('bl2u.bin', ATF_BL2U_DATA) TestFunctional._MakeInputFile('fw_dynamic.bin', OPENSBI_DATA) TestFunctional._MakeInputFile('scp.bin', SCP_DATA) @@ -5387,6 +5389,11 @@ fdt fdtmap Extract the devicetree blob from the fdtmap data = self._DoReadFile('222_tee_os.dts') self.assertEqual(TEE_OS_DATA, data[:len(TEE_OS_DATA)]) + def testPackTiDm(self): + """Test that an image with a TI DM binary can be created""" + data = self._DoReadFile('225_ti_dm.dts') + self.assertEqual(TI_DM_DATA, data[:len(TI_DM_DATA)]) + def testFitFdtOper(self): """Check handling of a specified FIT operation""" entry_args = { diff --git a/tools/binman/test/225_ti_dm.dts b/tools/binman/test/225_ti_dm.dts new file mode 100644 index 0000000000..3ab754131e --- /dev/null +++ b/tools/binman/test/225_ti_dm.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + binman { + ti-dm { + filename = "dm.bin"; + }; + }; +}; -- cgit v1.2.3 From 892169440513e947ab7d69b471946f7e6bea3de7 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Thu, 21 Dec 2023 11:13:31 +0530 Subject: arm: dts: k3-*-binman: Move to using ti-dm entry type commit 3ef977e085767df31e42262f15837a66558052db upstream Move the DM entry in tispl.bin FIT image from default fetching an external blob entry to fetching using ti-dm entry type. This way, the DM entry will be populated by the TI_DM pathname if provided. Else it will resort to the ti-dm.bin file. Signed-off-by: Neha Malcom Francis Reviewed-by: Andrew Davis --- arch/arm/dts/k3-am625-sk-binman.dtsi | 4 ++-- arch/arm/dts/k3-am62a-sk-binman.dtsi | 4 ++-- arch/arm/dts/k3-j7200-binman.dtsi | 4 ++-- arch/arm/dts/k3-j721e-binman.dtsi | 4 ++-- arch/arm/dts/k3-j721s2-binman.dtsi | 4 ++-- arch/arm/dts/k3-j784s4-binman.dtsi | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index 87d65a4f15..d037ebf770 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -303,7 +303,7 @@ content = <&dm>; keyfile = "custMpk.pem"; }; - dm: blob-ext { + dm: ti-dm { filename = "ti-dm.bin"; }; }; @@ -501,7 +501,7 @@ os = "DM"; load = <0x89000000>; entry = <0x89000000>; - blob-ext { + ti-dm { filename = "ti-dm.bin"; }; }; diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index 2523e08984..991c328393 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -306,7 +306,7 @@ content = <&dm>; keyfile = "custMpk.pem"; }; - dm: blob-ext { + dm: ti-dm { filename = "ti-dm.bin"; }; }; @@ -504,7 +504,7 @@ os = "DM"; load = <0x89000000>; entry = <0x89000000>; - blob-ext { + ti-dm { filename = "ti-dm.bin"; }; }; diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index d55b3ba403..95ae2798a0 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -394,7 +394,7 @@ keyfile = "custMpk.pem"; }; - dm: blob-ext { + dm: ti-dm { filename = "ti-dm.bin"; }; }; @@ -551,7 +551,7 @@ os = "DM"; load = <0x89000000>; entry = <0x89000000>; - blob-ext { + ti-dm { filename = "ti-dm.bin"; }; }; diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi index 8f58f4e17f..a3a24489d7 100644 --- a/arch/arm/dts/k3-j721e-binman.dtsi +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -553,7 +553,7 @@ content = <&dm>; keyfile = "custMpk.pem"; }; - dm: blob-ext { + dm: ti-dm { filename = "ti-dm.bin"; }; }; @@ -757,7 +757,7 @@ os = "DM"; load = <0x89000000>; entry = <0x89000000>; - blob-ext { + ti-dm { filename = "ti-dm.bin"; }; }; diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi index 72278f8322..5c8db0a309 100644 --- a/arch/arm/dts/k3-j721s2-binman.dtsi +++ b/arch/arm/dts/k3-j721s2-binman.dtsi @@ -421,7 +421,7 @@ content = <&dm>; keyfile = "custMpk.pem"; }; - dm: blob-ext { + dm: ti-dm { filename = "ti-dm.bin"; }; }; @@ -625,7 +625,7 @@ os = "DM"; load = <0x89000000>; entry = <0x89000000>; - blob-ext { + ti-dm { filename = "ti-dm.bin"; }; }; diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi index 78fa4b80a0..0926bc631f 100644 --- a/arch/arm/dts/k3-j784s4-binman.dtsi +++ b/arch/arm/dts/k3-j784s4-binman.dtsi @@ -216,7 +216,7 @@ content = <&dm>; keyfile = "custMpk.pem"; }; - dm: blob-ext { + dm: ti-dm { filename = "ti-dm.bin"; }; }; @@ -419,7 +419,7 @@ os = "DM"; load = <0x89000000>; entry = <0x89000000>; - blob-ext { + ti-dm { filename = "ti-dm.bin"; }; }; -- cgit v1.2.3 From af9dbe05069bc1a868bf65ecc6b9a1cd24625a7d Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Thu, 21 Dec 2023 11:13:32 +0530 Subject: doc: board: ti: k3: Mention TI_DM argument commit 09a17b0d01dd7c81f6fd96228581d7df47a1a7b1 upstream Mention TI_DM argument can be used to fetch a custom DM binary in the A72 build instructions for K3 devices. Signed-off-by: Neha Malcom Francis Reviewed-by: Andrew Davis --- doc/board/ti/k3.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index e9a65e00ee..e8bb19ab3f 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -278,6 +278,12 @@ use the `lite` option. BL31= Date: Fri, 22 Dec 2023 12:28:30 -0600 Subject: arm: dts: k3-j7200-r5-common: Add msmc clk to a72 node Define the MSMC clk in the a72 node Reviewed-by: Udit Kumar Signed-off-by: Reid Tonking --- arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index 5e39b10f3a..fe0280e833 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -33,10 +33,11 @@ <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 0>; - assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>; - assigned-clock-rates = <2000000000>, <200000000>; + clocks = <&k3_clks 61 1>, <&k3_clks 4 1>, <&k3_clks 202 2>; + clock-names = "gtc_clk", "msmc_clk", "arm_clk"; + assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 4 1>, <&k3_clks 323 0>; + assigned-clock-parents= <0>, <0>, <0>, <&k3_clks 323 2>; + assigned-clock-rates = <2000000000>, <200000000>, <1000000000>; ti,sci = <&dmsc>; ti,sci-proc-id = <32>; ti,sci-host-id = <10>; -- cgit v1.2.3 From 2544c46895fe811ff10d8b2a486523567855b37c Mon Sep 17 00:00:00 2001 From: Reid Tonking Date: Fri, 22 Dec 2023 12:28:31 -0600 Subject: arm: dts: k3-j7200-r5-common: Reduce min voltage on avs regulator node The J7200 SoC supports MPU core voltage of 760mv Reviewed-by: Udit Kumar Signed-off-by: Reid Tonking --- arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index fe0280e833..d10e510749 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -257,7 +257,7 @@ buck1_reg: buck1 { /*VDD_CPU_AVS_REG*/ regulator-name = "buck1"; - regulator-min-microvolt = <800000>; + regulator-min-microvolt = <760000>; regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; -- cgit v1.2.3 From cc85a5c7c11b2ddc975df080bccf6583abc23873 Mon Sep 17 00:00:00 2001 From: Reid Tonking Date: Fri, 22 Dec 2023 12:28:32 -0600 Subject: misc: k3_avs: Add opp_low support J7200 has support for opp_low, so adding the option here Reviewed-by: Udit Kumar Signed-off-by: Reid Tonking --- include/k3-avs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/k3-avs.h b/include/k3-avs.h index e3c3cafbb9..855fbebd3b 100644 --- a/include/k3-avs.h +++ b/include/k3-avs.h @@ -20,6 +20,7 @@ #define NUM_OPPS 4 +#define AM6_OPP_LOW 0 #define AM6_OPP_NOM 1 #define AM6_OPP_OD 2 #define AM6_OPP_TURBO 3 -- cgit v1.2.3 From e76ebaf5c704e4c4a3d41790ba526c48f2291679 Mon Sep 17 00:00:00 2001 From: Reid Tonking Date: Fri, 22 Dec 2023 12:28:33 -0600 Subject: misc: k3_avs: Add new opp_low to vd_data Add opp_low to j721e vd_data Reviewed-by: Udit Kumar Signed-off-by: Reid Tonking --- drivers/misc/k3_avs.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index 38411e79c8..88db75d99e 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -464,6 +464,10 @@ static struct vd_data j721e_vd_data[] = { .dev_id = 202, /* J721E_DEV_A72SS0_CORE0 */ .clk_id = 2, /* ARM clock */ .opps = { + [AM6_OPP_LOW] = { + .volt = 0, /* voltage TBD after OPP fuse reading */ + .freq = 1000000000, + }, [AM6_OPP_NOM] = { .volt = 880000, /* TBD in DM */ .freq = 2000000000, -- cgit v1.2.3 From 765a9235ca26cf65b738a130d758b09ea64c087e Mon Sep 17 00:00:00 2001 From: Reid Tonking Date: Fri, 22 Dec 2023 12:28:34 -0600 Subject: misc: k3_avs: Change j7200 vtm compatible to align with upstream Upstream u-boot changed to using the ti,j7200-vtm compatible with the Linux 6.6 DT sync, so using the same here Reviewed-by: Udit Kumar Signed-off-by: Reid Tonking --- arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 2 +- drivers/misc/k3_avs.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index d10e510749..2e1c26d6de 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -94,7 +94,7 @@ }; wkup_vtm0: vtm@42040000 { - compatible = "ti,am654-vtm", "ti,j721e-avs"; + compatible = "ti,j7200-vtm"; reg = <0x0 0x42040000 0x0 0x330>, <0x00 0x42050000 0x00 0x350>; power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index 88db75d99e..d7312175f1 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -512,6 +512,7 @@ static const struct udevice_id k3_avs_ids[] = { { .compatible = "ti,am654-avs", .data = (ulong)&am654_vd_config }, { .compatible = "ti,j721e-avs", .data = (ulong)&j721e_vd_config }, { .compatible = "ti,j721s2-avs", .data = (ulong)&j721s2_vd_config }, + { .compatible = "ti,j7200-vtm", .data = (ulong)&j721e_vd_config }, {} }; -- cgit v1.2.3 From ce7ce164287f769f470d205b39a1c6eb9aefa9fc Mon Sep 17 00:00:00 2001 From: Reid Tonking Date: Fri, 22 Dec 2023 12:28:35 -0600 Subject: misc: k3_avs: add k3_check_opp function Useful when trying to check if an opp efuse is burned in or not. k3_avs driver checks opp_ids when probing and overwrites the voltage values in vd_data for the respective board. This can be called to check that data and returns 0 if valid. Reviewed-by: Udit Kumar Signed-off-by: Reid Tonking --- drivers/misc/k3_avs.c | 23 +++++++++++++++++++++++ include/k3-avs.h | 1 + 2 files changed, 24 insertions(+) diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index d7312175f1..d922b8808b 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -193,6 +193,29 @@ static int match_opp(struct vd_data *vd, u32 freq) return -EINVAL; } +/** + * k3_check_opp: Check for presence of opp efuse + * @opp_id: opp id to check if voltage is present + * + * Checks to see if an opp has voltage. k3_avs probe will populate + * votlage data if efuse is present. Returns 0 if data is valid. + */ +int k3_check_opp(int opp_id) +{ + struct vd_data *vd; + struct k3_avs_privdata *priv = k3_avs_priv; + int volt; + + vd = priv->vd_config->vds; + volt = vd->opps[opp_id].volt; + + if (volt) + return 0; + + printf("No efuse found for opp_%d\n", opp_id); + return -EINVAL; +} + /** * k3_avs_notify_freq: Notify clock rate change towards AVS subsystem * @dev_id: Device ID for the clock to be changed diff --git a/include/k3-avs.h b/include/k3-avs.h index 855fbebd3b..52bbb2fe7f 100644 --- a/include/k3-avs.h +++ b/include/k3-avs.h @@ -27,5 +27,6 @@ int k3_avs_set_opp(struct udevice *dev, int vdd_id, int opp_id); int k3_avs_notify_freq(int dev_id, int clk_id, u32 freq); +int k3_check_opp(int opp_id); #endif -- cgit v1.2.3 From c265936601607d848115523f80b655f5dbedca6e Mon Sep 17 00:00:00 2001 From: Reid Tonking Date: Fri, 22 Dec 2023 12:28:36 -0600 Subject: arm: mach-k3: J7200: Add support for OPP_LOW Adds a check for K3_OPP_LOW config and will change MPU freq/voltage and msmc clock according to opp_low spec. Reviewed-by: Udit Kumar Signed-off-by: Reid Tonking --- arch/arm/mach-k3/j721e_init.c | 45 ++++++++++++++++++++++++++++++++++++++++++- drivers/misc/k3_avs.c | 5 +++++ 2 files changed, 49 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index fb36574a9a..93b4e553a8 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -23,6 +23,7 @@ #include #include #include +#include #ifdef CONFIG_K3_LOAD_SYSFW struct fwl_data cbass_hc_cfg0_fwls[] = { @@ -125,6 +126,32 @@ void k3_mmc_restart_clock(void) } #endif +int fix_freq(const void *fdt) +{ + int node, ret; + u32 opp_low_freq[3]; + + node = fdt_node_offset_by_compatible(fdt, -1, "ti,am654-rproc"); + if (node < 0) { + printf("%s: A72 not found\n", __func__); + return node; + } + + /* j7200 opp low values according to data sheet */ + opp_low_freq[0] = cpu_to_fdt32(1000000000); /* 202-2 -> A72SS0_CORE0_0_ARM_CLK */ + opp_low_freq[1] = cpu_to_fdt32(200000000); /* 61-1 -> GTC0_GTC_CLK */ + opp_low_freq[2] = cpu_to_fdt32(500000000); /* 4-1 -> A72SS0_CORE0_MSMC_CLK */ + + ret = fdt_setprop((void *)fdt, node, "assigned-clock-rates", + opp_low_freq, sizeof(opp_low_freq)); + if (ret) { + printf("%s: Can not set value\n", __func__); + return ret; + } + + return 0; +} + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -280,8 +307,24 @@ void board_init_f(ulong dummy) #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0) ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs), &dev); - if (ret) + if (!ret) { + if (IS_ENABLED(CONFIG_K3_OPP_LOW)) { + ret = k3_check_opp(AM6_OPP_LOW); + if (!ret) { + ret = fix_freq(gd->fdt_blob); + if (ret) + printf("Failed to set OPP_LOW frequency\n"); + + ret = k3_avs_set_opp(dev, J721E_VDD_MPU, AM6_OPP_LOW); + if (ret) + printf("Failed to set OPP_LOW voltage\n"); + } else { + printf("Failed to enable K3_OPP_LOW\n"); + } + } + } else { printf("AVS init failed: %d\n", ret); + } #endif #if defined(CONFIG_K3_J721E_DDRSS) diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index d922b8808b..11990545b0 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -122,6 +122,11 @@ static int k3_avs_program_voltage(struct k3_avs_privdata *priv, if (!vd->supply) return -ENODEV; + if (!volt) { + dev_err(priv->dev, "Fuse is not set for selected opp %d\n", opp_id); + return -EINVAL; + } + vd->opp = opp_id; vd->flags |= VD_FLAG_INIT_DONE; -- cgit v1.2.3 From 233f462f4e809b90f192e58af4f85e7c2be68948 Mon Sep 17 00:00:00 2001 From: Reid Tonking Date: Fri, 22 Dec 2023 12:28:37 -0600 Subject: configs: j7200_evm_r5_defconfig: Define K3_OPP_LOW Adds the default config for K3_OPP_LOW in J7200 Reviewed-by: Udit Kumar Signed-off-by: Reid Tonking --- arch/arm/mach-k3/Kconfig | 6 ++++++ configs/j7200_evm_r5_defconfig | 1 + 2 files changed, 7 insertions(+) diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index cad27376cf..c5c909919d 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -100,6 +100,12 @@ config SYS_K3_BOOT_CORE_ID int default 16 +config K3_OPP_LOW + bool "Enable OPP_LOW on supported TI K3 SoCs" + help + Enabling this will allow Socs with the proper efuse to run + at a lower MPU core voltage and adjust freqrency according to SoC trm + config K3_EARLY_CONS bool "Activate to allow for an early console during SPL" depends on SPL diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index a491992df3..56b134ae0f 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -106,6 +106,7 @@ CONFIG_SPL_FS_LOADER=y CONFIG_ESM_K3=y CONFIG_ESM_PMIC=y CONFIG_K3_AVS0=y +# CONFIG_K3_OPP_LOW is not set CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_MMC_SDHCI=y -- cgit v1.2.3 From 40682843ba90a42b1d8ec702865eeac35eed1de1 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Thu, 4 Jan 2024 19:02:46 +0200 Subject: arm: dts: k3-am642: Fix boot on SK-AM64B SK-AM64B boot is broken. The main_i2c0 node is left disabled in r5-evm.dts preventing proper board detection. Explicitly enable the main_i2c0 node in r5-evm.dts. Fixes boot and below error message: "Reading on-board EEPROM at 0x51 failed -19" Fixes: cc471479d3850: ("arm: dts: k3-am642: main_i2c0 cleanup") Reported-by: Andreas Dannenberg Suggested-by: Vignesh Raghavendra Signed-off-by: Roger Quadros --- arch/arm/dts/k3-am642-r5-evm.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts index b10e6d9b17..57d78e449c 100644 --- a/arch/arm/dts/k3-am642-r5-evm.dts +++ b/arch/arm/dts/k3-am642-r5-evm.dts @@ -291,6 +291,11 @@ /* EEPROM might be read before SYSFW is available */ &main_i2c0 { /delete-property/ power-domains; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + tca9554: gpio@38 { /* TCA9554 */ compatible = "nxp,pca9554"; -- cgit v1.2.3 From 57820c133a06b875c0da01776909ced81eed2ad5 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Fri, 5 Jan 2024 11:59:30 +0200 Subject: configs: am64x_evm_r5_defconfig: Enable I2C GPIO drivers We need the I2C GPIO drivers to detect expansion cards. Gets rid of below error message at R5 SPL on AM64-EVM "Failed to lookup gpio gpio@38_0: -22" Signed-off-by: Roger Quadros --- configs/am64x_evm_r5_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index 222aeb887d..722f3e7149 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -188,3 +188,6 @@ CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y +CONFIG_DM_PCA953X=y +CONFIG_SPL_DM_PCA953X=y +CONFIG_DM_I2C_GPIO=y -- cgit v1.2.3 From 4ded867357dad368f886e2df45fea2a8475bcc90 Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Mon, 8 Jan 2024 11:26:47 +0530 Subject: arm: dts: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode DDR52 speed mode is enabled for eMMC in J7200 but its Itap Delay Value is not present in the device tree. Thus, add Itap Delay Value for eMMC High Speed DDR which is DDR52 speed mode for J7200 SoC according to datasheet for J7200 [1]. [1] Refer to : section 7.9.5.16.1 MMCSD0 - eMMC Interface, in J7200 datasheet - https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf Signed-off-by: Bhavya Kapoor Reviewed-by: Neha Malcom Francis --- arch/arm/dts/k3-j7200-main.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi index d8db2d2d01..5ac2d871b9 100644 --- a/arch/arm/dts/k3-j7200-main.dtsi +++ b/arch/arm/dts/k3-j7200-main.dtsi @@ -499,6 +499,7 @@ ti,otap-del-sel-hs400 = <0x5>; ti,itap-del-sel-legacy = <0x10>; ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; ti,strobe-sel = <0x77>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; -- cgit v1.2.3 From 874327a0ef55832f1816034108248c3289d74636 Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Mon, 8 Jan 2024 11:26:48 +0530 Subject: arm: dts: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode DDR50 speed mode is enabled for MMCSD in J721s2 but its Itap Delay Value is not present in the device tree. Thus, add Itap Delay Value for MMCSD Ultra High Speed DDR which is DDR50 speed mode for J721s2 SoC according to datasheet for J721s2 [1]. [1] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in J721s2 datasheet - https://www.ti.com/lit/ds/symlink/tda4vl-q1.pdf Signed-off-by: Bhavya Kapoor Reviewed-by: Neha Malcom Francis --- arch/arm/dts/k3-j721s2-main.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi index da63385646..c3ee187ff8 100644 --- a/arch/arm/dts/k3-j721s2-main.dtsi +++ b/arch/arm/dts/k3-j721s2-main.dtsi @@ -392,6 +392,7 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; + ti,itap-del-sel-ddr50 = <0x2>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; -- cgit v1.2.3 From a97ca328b3df6abf79c5cc01878290e03131bbba Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Mon, 8 Jan 2024 11:26:49 +0530 Subject: arm: dts: k3-j784s4-main: Add Itap Delay Value For DDR50 speed mode DDR50 speed mode is enabled for MMCSD in J784s4 but its Itap Delay Value is not present in the device tree. Thus, add Itap Delay Value for MMCSD Ultra High Speed DDR which is DDR50 speed mode for J784s4 SoC according to datasheet for J784s4 [1]. [1] Refer to : section 6.10.5.17.2 MMC1/2 - SD/SDIO Interface, in J784s4 datasheet - https://www.ti.com/lit/ds/symlink/tda4vh-q1.pdf Signed-off-by: Bhavya Kapoor Reviewed-by: Neha Malcom Francis --- arch/arm/dts/k3-j784s4-main.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/k3-j784s4-main.dtsi b/arch/arm/dts/k3-j784s4-main.dtsi index f3f689c166..46445e7d7c 100644 --- a/arch/arm/dts/k3-j784s4-main.dtsi +++ b/arch/arm/dts/k3-j784s4-main.dtsi @@ -422,6 +422,7 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; + ti,itap-del-sel-ddr50 = <0x2>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; -- cgit v1.2.3 From ea155ff62af9f25a3295bd19ee869d97d2eb0299 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Tue, 9 Jan 2024 14:36:24 +0530 Subject: arch: mach-k3: Fix incorrect mapping of higher DDR addresses as device memory Entry for physical address 0x500000000 in memory map table for MMU configuration is spilling over and inadvertently making DDR available at higher address (above 4GB address space) get mapped as device memory (nGnRnE). Fix this by adjusting entry size. Tested on AM62A SK. Before this patch: => time crc32 0x881000000 0x20000000 crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca time: 1 minutes, 14.716 seconds After patch: => time crc32 0x881000000 0x20000000 crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca time: 2.710 seconds Acked-by: Andrew Davis Signed-off-by: Sekhar Nori Tested-by: Andreas Dannenberg --- arch/arm/mach-k3/arm64-mmu.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index 696b276058..3d3d26da54 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -53,7 +53,7 @@ struct mm_region am654_mem_map[NR_MMU_REGIONS] = { }, { .virt = 0x500000000UL, .phys = 0x500000000UL, - .size = 0x400000000UL, + .size = 0x380000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN @@ -108,7 +108,7 @@ struct mm_region j721e_mem_map[NR_MMU_REGIONS] = { }, { .virt = 0x500000000UL, .phys = 0x500000000UL, - .size = 0x400000000UL, + .size = 0x380000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN @@ -166,7 +166,7 @@ struct mm_region j7200_mem_map[NR_MMU_REGIONS] = { }, { .virt = 0x500000000UL, .phys = 0x500000000UL, - .size = 0x400000000UL, + .size = 0x380000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN @@ -220,7 +220,7 @@ struct mm_region j721s2_mem_map[NR_MMU_REGIONS] = { }, { .virt = 0x500000000UL, .phys = 0x500000000UL, - .size = 0x400000000UL, + .size = 0x380000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN @@ -264,7 +264,7 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = { }, { .virt = 0x500000000UL, .phys = 0x500000000UL, - .size = 0x400000000UL, + .size = 0x380000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN @@ -305,7 +305,7 @@ struct mm_region j722s_mem_map[NR_MMU_REGIONS] = { }, { .virt = 0x500000000UL, .phys = 0x500000000UL, - .size = 0x400000000UL, + .size = 0x380000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN @@ -364,7 +364,7 @@ struct mm_region j784s4_mem_map[NR_MMU_REGIONS] = { }, { .virt = 0x500000000UL, .phys = 0x500000000UL, - .size = 0x400000000UL, + .size = 0x380000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN -- cgit v1.2.3 From ca7a671dcf7d70132f9f484db3c655be9648a572 Mon Sep 17 00:00:00 2001 From: Manorit Chawdhry Date: Thu, 4 Jan 2024 14:39:09 +0530 Subject: env: ti: ti_armv7_common: Run main_cpsw0_qsgmii_phyinit conditionally commit 0d72b0f2f83b788273c40ed4a64d1adf74877726 upstream. Since upstream U-Boot uses ti_common.env instead of ti_armv7_common.env, the implementation here differs in this aspect from the upstream commit. The main_cpsw0_qsgmii_phyinit command is defined only for certain TI SoCs which have the do_main_cpsw0_qsgmii_phyinit variable set. Add a check to ensure that the main_cpsw0_qsgmii_phyinit command is run only for such SoCs. Signed-off-by: Manorit Chawdhry Signed-off-by: Siddharth Vadapalli Reviewed-by: Tom Rini Reviewed-by: Mattijs Korpershoek --- include/environment/ti/ti_armv7_common.env | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/environment/ti/ti_armv7_common.env b/include/environment/ti/ti_armv7_common.env index f5d84216e3..5473f633aa 100644 --- a/include/environment/ti/ti_armv7_common.env +++ b/include/environment/ti/ti_armv7_common.env @@ -25,7 +25,10 @@ run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring} bootcmd_ti_mmc= run findfdt; run init_${boot}; #if CONFIG_CMD_REMOTEPROC - run main_cpsw0_qsgmii_phyinit; run boot_rprocs; + if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1; + then run main_cpsw0_qsgmii_phyinit; + fi; + run boot_rprocs; #endif if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_fit_overlaystring; run run_fit; -- cgit v1.2.3 From 218eff500748b1085821a3e5abcd620f71650160 Mon Sep 17 00:00:00 2001 From: Manorit Chawdhry Date: Thu, 11 Jan 2024 10:07:28 +0530 Subject: arm: dts: j7xx: Allow privID 0 to pass through background firewalls Firewalling IP has 3 permissions slots for slave and DRU firewalls. Each permission slot can be populated with different accesses to different privIDs. Configuring a background firewall with an allow all permission (0xc3ffff) in just one slot doesn't work as intendted as the other permission slots which are essentially 0x0000 act as a block all transaction for privID 0. Explicitly fill all the permission registers of background firewall regions to allow all transactions to go through including privID 0. Foreground firewalls are intendted to block privID 0 as well so they are not touched. [ AM68-SK CSI Test ] Tested-by: Vaishnav Achath Signed-off-by: Manorit Chawdhry --- arch/arm/dts/k3-j7200-binman.dtsi | 20 +++++++++++++++++++ arch/arm/dts/k3-j721e-binman.dtsi | 30 ++++++++++++++++++++++++++++ arch/arm/dts/k3-j721s2-binman.dtsi | 41 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 91 insertions(+) diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index 95ae2798a0..1e1b3d8a36 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -327,6 +327,16 @@ control = <(FWCTRL_EN | FWCTRL_LOCK | FWCTRL_BG | FWCTRL_CACHE)>; permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | FWPERM_SECURE_PRIV_RWCD | FWPERM_SECURE_USER_RWCD | FWPERM_NON_SECURE_PRIV_RWCD | @@ -355,6 +365,16 @@ control = <(FWCTRL_EN | FWCTRL_LOCK | FWCTRL_BG | FWCTRL_CACHE)>; permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | FWPERM_SECURE_PRIV_RWCD | FWPERM_SECURE_USER_RWCD | FWPERM_NON_SECURE_PRIV_RWCD | diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi index a3a24489d7..b6f6ad4068 100644 --- a/arch/arm/dts/k3-j721e-binman.dtsi +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -370,6 +370,16 @@ control = <(FWCTRL_EN | FWCTRL_LOCK | FWCTRL_BG | FWCTRL_CACHE)>; permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | FWPERM_SECURE_PRIV_RWCD | FWPERM_SECURE_USER_RWCD | FWPERM_NON_SECURE_PRIV_RWCD | @@ -488,6 +498,16 @@ control = <(FWCTRL_EN | FWCTRL_LOCK | FWCTRL_BG | FWCTRL_CACHE)>; permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | FWPERM_SECURE_PRIV_RWCD | FWPERM_SECURE_USER_RWCD | FWPERM_NON_SECURE_PRIV_RWCD | @@ -516,6 +536,16 @@ control = <(FWCTRL_EN | FWCTRL_LOCK | FWCTRL_BG | FWCTRL_CACHE)>; permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | FWPERM_SECURE_PRIV_RWCD | FWPERM_SECURE_USER_RWCD | FWPERM_NON_SECURE_PRIV_RWCD | diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi index 5c8db0a309..890504ca7f 100644 --- a/arch/arm/dts/k3-j721s2-binman.dtsi +++ b/arch/arm/dts/k3-j721s2-binman.dtsi @@ -217,6 +217,16 @@ control = <(FWCTRL_EN | FWCTRL_LOCK | FWCTRL_BG | FWCTRL_CACHE)>; permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | FWPERM_SECURE_PRIV_RWCD | FWPERM_SECURE_USER_RWCD | FWPERM_NON_SECURE_PRIV_RWCD | @@ -327,6 +337,16 @@ control = <(FWCTRL_EN | FWCTRL_LOCK | FWCTRL_BG | FWCTRL_CACHE)>; permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | FWPERM_SECURE_PRIV_RWCD | FWPERM_SECURE_USER_RWCD | FWPERM_NON_SECURE_PRIV_RWCD | @@ -355,10 +375,21 @@ control = <(FWCTRL_EN | FWCTRL_LOCK | FWCTRL_BG | FWCTRL_CACHE)>; permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | FWPERM_SECURE_PRIV_RWCD | FWPERM_SECURE_USER_RWCD | FWPERM_NON_SECURE_PRIV_RWCD | FWPERM_NON_SECURE_USER_RWCD)>; + start_address = <0x0 0x0>; end_address = <0xff 0xffffffff>; }; @@ -383,6 +414,16 @@ control = <(FWCTRL_EN | FWCTRL_LOCK | FWCTRL_BG | FWCTRL_CACHE)>; permissions = <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | + FWPERM_SECURE_PRIV_RWCD | + FWPERM_SECURE_USER_RWCD | + FWPERM_NON_SECURE_PRIV_RWCD | + FWPERM_NON_SECURE_USER_RWCD)>, + <((FWPRIVID_ALL << FWPRIVID_SHIFT) | FWPERM_SECURE_PRIV_RWCD | FWPERM_SECURE_USER_RWCD | FWPERM_NON_SECURE_PRIV_RWCD | -- cgit v1.2.3 From a1448e3cf9a0602d284566d6cacf60b96c3c1316 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 8 Jan 2024 16:17:46 +0200 Subject: board: ti: am64: Support TMDS64EVM The TMDS64EVM [1] ships with AM64X SR2.0 HS-FS chip and a slightly different board name in the board information EEPROM header. Support this board. [1] https://www.ti.com/tool/TMDS64EVM Gets rid of below message at boot "Unidentified board claims AM64-EVM in eeprom header" Signed-off-by: Roger Quadros Reviewed-by: Neha Malcom Francis --- board/ti/am64x/evm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index 12b4f26325..c42afa581b 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -22,6 +22,7 @@ #include "../common/board_detect.h" #define board_is_am64x_gpevm() (board_ti_k3_is("AM64-GPEVM") || \ + board_ti_k3_is("AM64-EVM") || \ board_ti_k3_is("AM64-HSEVM")) #define board_is_am64x_skevm() (board_ti_k3_is("AM64-SKEVM") || \ -- cgit v1.2.3 From 57f1e97afad6dbaa5b5514c2c473fb1f41688669 Mon Sep 17 00:00:00 2001 From: Dhruva Gole Date: Thu, 18 Jan 2024 16:53:22 +0530 Subject: arm: dts: k3-*: s/fsstub/tifsstub/ Replace all the fsstub occurences with tifsstub to avoid new terminology and resulting confusion. Suggested-by: Nishanth Menon Signed-off-by: Dhruva Gole --- arch/arm/dts/k3-am625-sk-binman.dtsi | 86 ++++++++++++++++++------------------ arch/arm/dts/k3-am62a-sk-binman.dtsi | 86 ++++++++++++++++++------------------ arch/arm/dts/k3-am62p-sk-binman.dtsi | 56 +++++++++++------------ arch/arm/mach-k3/common.c | 14 +++--- 4 files changed, 121 insertions(+), 121 deletions(-) diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index d037ebf770..9bb9662f25 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -155,37 +155,37 @@ }; }; - fsstub-hs { - filename = "fsstub.bin_hs"; + tifsstub-hs { + filename = "tifsstub.bin_hs"; ti-secure-rom { - content = <&fsstub_hs_cert>; + content = <&tifsstub_hs_cert>; core = "secure"; load = <0x40000>; sw-rev = ; keyfile = "custMpk.pem"; countersign; - fsstub; + tifsstub; }; - fsstub_hs_cert: fsstub-hs-cert.bin { + tifsstub_hs_cert: tifsstub-hs-cert.bin { filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin"; type = "blob-ext"; optional; }; - fsstub_hs_enc: fsstub-hs-enc.bin { + tifsstub_hs_enc: tifsstub-hs-enc.bin { filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin"; type = "blob-ext"; optional; }; }; - fsstub-fs { - filename = "fsstub.bin_fs"; - fsstub_fs_cert: fsstub-fs-cert.bin { + tifsstub-fs { + filename = "tifsstub.bin_fs"; + tifsstub_fs_cert: tifsstub-fs-cert.bin { filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin"; type = "blob-ext"; optional; }; - fsstub_fs_enc: fsstub-fs-enc.bin { + tifsstub_fs_enc: tifsstub-fs-enc.bin { filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin"; type = "blob-ext"; optional; @@ -193,17 +193,17 @@ }; - fsstub-gp { - filename = "fsstub.bin_gp"; + tifsstub-gp { + filename = "tifsstub.bin_gp"; ti-secure-rom { - content = <&fsstub_gp>; + content = <&tifsstub_gp>; core = "secure"; load = <0x60000>; sw-rev = ; keyfile = "ti-degenerate-key.pem"; - fsstub; + tifsstub; }; - fsstub_gp: fsstub-gp.bin { + tifsstub_gp: tifsstub-gp.bin { filename = "ti-sysfw/ti-fs-stub-firmware-am62x-gp.bin"; type = "blob-ext"; optional; @@ -252,42 +252,42 @@ }; }; - fsstub-hs { - description = "FSSTUB"; + tifsstub-hs { + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; - os = "fsstub-hs"; + os = "tifsstub-hs"; load = <0x9dc00000>; entry = <0x9dc00000>; blob-ext { - filename = "fsstub.bin_hs"; + filename = "tifsstub.bin_hs"; }; }; - fsstub-fs { - description = "FSSTUB"; + tifsstub-fs { + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; - os = "fsstub-fs"; + os = "tifsstub-fs"; load = <0x9dc00000>; entry = <0x9dc00000>; blob-ext { - filename = "fsstub.bin_fs"; + filename = "tifsstub.bin_fs"; }; }; - fsstub-gp { - description = "FSSTUB"; + tifsstub-gp { + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; - os = "fsstub-gp"; + os = "tifsstub-gp"; load = <0x9dc00000>; entry = <0x9dc00000>; blob-ext { - filename = "fsstub.bin_gp"; + filename = "tifsstub.bin_gp"; }; }; @@ -348,8 +348,8 @@ conf-0 { description = "k3-am625-sk"; firmware = "atf"; - loadables = "tee", "fsstub-hs", "fsstub-fs", - "fsstub-gp", "dm", "spl"; + loadables = "tee", "tifsstub-hs", "tifsstub-fs", + "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; @@ -454,42 +454,42 @@ }; }; - fsstub-hs { - description = "FSSTUB"; + tifsstub-hs { + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; - os = "fsstub-hs"; + os = "tifsstub-hs"; load = <0x9dc00000>; entry = <0x9dc00000>; blob-ext { - filename = "fsstub.bin_hs"; + filename = "tifsstub.bin_hs"; }; }; - fsstub-fs { - description = "FSSTUB"; + tifsstub-fs { + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; - os = "fsstub-fs"; + os = "tifsstub-fs"; load = <0x9dc00000>; entry = <0x9dc00000>; blob-ext { - filename = "fsstub.bin_fs"; + filename = "tifsstub.bin_fs"; }; }; - fsstub-gp { - description = "FSSTUB"; + tifsstub-gp { + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; - os = "fsstub-gp"; + os = "tifsstub-gp"; load = <0x9dc00000>; entry = <0x9dc00000>; blob-ext { - filename = "fsstub.bin_gp"; + filename = "tifsstub.bin_gp"; }; }; @@ -536,8 +536,8 @@ conf-0 { description = "k3-am625-sk"; firmware = "atf"; - loadables = "tee", "fsstub-hs", "fsstub-fs", - "fsstub-gp", "dm", "spl"; + loadables = "tee", "tifsstub-hs", "tifsstub-fs", + "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index 991c328393..777630f2b8 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -158,37 +158,37 @@ }; }; - fsstub-hs { - filename = "fsstub.bin_hs"; + tifsstub-hs { + filename = "tifsstub.bin_hs"; ti-secure-rom { - content = <&fsstub_hs_cert>; + content = <&tifsstub_hs_cert>; core = "secure"; load = <0x60000>; sw-rev = ; keyfile = "custMpk.pem"; countersign; - fsstub; + tifsstub; }; - fsstub_hs_cert: fsstub-hs-cert.bin { + tifsstub_hs_cert: tifsstub-hs-cert.bin { filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin"; type = "blob-ext"; optional; }; - fsstub_hs_enc: fsstub-hs-enc.bin { + tifsstub_hs_enc: tifsstub-hs-enc.bin { filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin"; type = "blob-ext"; optional; }; }; - fsstub-fs { - filename = "fsstub.bin_fs"; - fsstub_fs_cert: fsstub-fs-cert.bin { + tifsstub-fs { + filename = "tifsstub.bin_fs"; + tifsstub_fs_cert: tifsstub-fs-cert.bin { filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin"; type = "blob-ext"; optional; }; - fsstub_fs_enc: fsstub-fs-enc.bin { + tifsstub_fs_enc: tifsstub-fs-enc.bin { filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin"; type = "blob-ext"; optional; @@ -196,17 +196,17 @@ }; - fsstub-gp { - filename = "fsstub.bin_gp"; + tifsstub-gp { + filename = "tifsstub.bin_gp"; ti-secure-rom { - content = <&fsstub_gp>; + content = <&tifsstub_gp>; core = "secure"; load = <0x60000>; sw-rev = ; keyfile = "ti-degenerate-key.pem"; - fsstub; + tifsstub; }; - fsstub_gp: fsstub-gp.bin { + tifsstub_gp: tifsstub-gp.bin { filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-gp.bin"; type = "blob-ext"; optional; @@ -255,42 +255,42 @@ }; }; - fsstub-hs { - description = "FSSTUB"; + tifsstub-hs { + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; - os = "fsstub-hs"; + os = "tifsstub-hs"; load = <0x9ca00000>; entry = <0x9ca00000>; blob-ext { - filename = "fsstub.bin_hs"; + filename = "tifsstub.bin_hs"; }; }; - fsstub-fs { - description = "FSSTUB"; + tifsstub-fs { + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; - os = "fsstub-fs"; + os = "tifsstub-fs"; load = <0x9ca00000>; entry = <0x9ca00000>; blob-ext { - filename = "fsstub.bin_fs"; + filename = "tifsstub.bin_fs"; }; }; - fsstub-gp { - description = "FSSTUB"; + tifsstub-gp { + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; - os = "fsstub-gp"; + os = "tifsstub-gp"; load = <0x9ca00000>; entry = <0x9ca00000>; blob-ext { - filename = "fsstub.bin_gp"; + filename = "tifsstub.bin_gp"; }; }; @@ -351,8 +351,8 @@ conf-0 { description = "k3-am62a7-sk"; firmware = "atf"; - loadables = "tee", "fsstub-hs", "fsstub-fs", - "fsstub-gp", "dm", "spl"; + loadables = "tee", "tifsstub-hs", "tifsstub-fs", + "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; @@ -457,42 +457,42 @@ }; }; - fsstub-hs { - description = "FSSTUB"; + tifsstub-hs { + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; - os = "fsstub-hs"; + os = "tifsstub-hs"; load = <0x9ca00000>; entry = <0x9ca00000>; blob-ext { - filename = "fsstub.bin_hs"; + filename = "tifsstub.bin_hs"; }; }; - fsstub-fs { - description = "FSSTUB"; + tifsstub-fs { + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; - os = "fsstub-fs"; + os = "tifsstub-fs"; load = <0x9ca00000>; entry = <0x9ca00000>; blob-ext { - filename = "fsstub.bin_fs"; + filename = "tifsstub.bin_fs"; }; }; - fsstub-gp { - description = "FSSTUB"; + tifsstub-gp { + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; - os = "fsstub-gp"; + os = "tifsstub-gp"; load = <0x9ca00000>; entry = <0x9ca00000>; blob-ext { - filename = "fsstub.bin_gp"; + filename = "tifsstub.bin_gp"; }; }; @@ -539,8 +539,8 @@ conf-0 { description = "k3-am62a7-sk"; firmware = "atf"; - loadables = "tee", "fsstub-hs", "fsstub-fs", - "fsstub-gp", "dm", "spl"; + loadables = "tee", "tifsstub-hs", "tifsstub-fs", + "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi index 1c30ed8680..6bc5ef7582 100644 --- a/arch/arm/dts/k3-am62p-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -116,37 +116,37 @@ }; }; - fsstub-hs { - filename = "fsstub.bin_hs"; + tifsstub-hs { + filename = "tifsstub.bin_hs"; ti-secure-rom { - content = <&fsstub_hs_cert>; + content = <&tifsstub_hs_cert>; core = "secure"; load = <0x60000>; sw-rev = ; keyfile = "custMpk.pem"; countersign; - fsstub; + tifsstub; }; - fsstub_hs_cert: fsstub-hs-cert.bin { + tifsstub_hs_cert: tifsstub-hs-cert.bin { filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-cert.bin"; type = "blob-ext"; optional; }; - fsstub_hs_enc: fsstub-hs-enc.bin { + tifsstub_hs_enc: tifsstub-hs-enc.bin { filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-enc.bin"; type = "blob-ext"; optional; }; }; - fsstub-fs { - filename = "fsstub.bin_fs"; - fsstub_fs_cert: fsstub-fs-cert.bin { + tifsstub-fs { + filename = "tifsstub.bin_fs"; + tifsstub_fs_cert: tifsstub-fs-cert.bin { filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-cert.bin"; type = "blob-ext"; optional; }; - fsstub_fs_enc: fsstub-fs-enc.bin { + tifsstub_fs_enc: tifsstub-fs-enc.bin { filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-enc.bin"; type = "blob-ext"; optional; @@ -196,29 +196,29 @@ }; }; - fsstub-hs { - description = "FSSTUB"; + tifsstub-hs { + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; - os = "fsstub-hs"; + os = "tifsstub-hs"; load = <0x9ca00000>; entry = <0x9ca00000>; blob-ext { - filename = "fsstub.bin_hs"; + filename = "tifsstub.bin_hs"; }; }; - fsstub-fs { - description = "FSSTUB"; + tifsstub-fs { + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; - os = "fsstub-fs"; + os = "tifsstub-fs"; load = <0x9ca00000>; entry = <0x9ca00000>; blob-ext { - filename = "fsstub.bin_fs"; + filename = "tifsstub.bin_fs"; }; }; @@ -279,7 +279,7 @@ conf-0 { description = "k3-am62px-sk"; firmware = "atf"; - loadables = "tee", "fsstub-hs", "fsstub-fs", + loadables = "tee", "tifsstub-hs", "tifsstub-fs", "dm", "spl"; fdt = "fdt-0"; }; @@ -385,29 +385,29 @@ }; }; - fsstub-hs { - description = "FSSTUB"; + tifsstub-hs { + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; - os = "fsstub-hs"; + os = "tifsstub-hs"; load = <0x9ca00000>; entry = <0x9ca00000>; blob-ext { - filename = "fsstub.bin_hs"; + filename = "tifsstub.bin_hs"; }; }; - fsstub-fs { - description = "FSSTUB"; + tifsstub-fs { + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; - os = "fsstub-fs"; + os = "tifsstub-fs"; load = <0x9ca00000>; entry = <0x9ca00000>; blob-ext { - filename = "fsstub.bin_fs"; + filename = "tifsstub.bin_fs"; }; }; @@ -454,7 +454,7 @@ conf-0 { description = "k3-am62px-sk"; firmware = "atf"; - loadables = "tee", "fsstub-hs", "fsstub-fs", + loadables = "tee", "tifsstub-hs", "tifsstub-fs", "dm", "spl"; fdt = "fdt-0"; }; diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index a64f7e3cba..9e535d04d2 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -49,9 +49,9 @@ static const char *image_os_match[IMAGE_AMT] = { "tee", "U-Boot", "DM", - "fsstub-hs", - "fsstub-fs", - "fsstub-gp", + "tifsstub-hs", + "tifsstub-fs", + "tifsstub-gp", }; #endif @@ -380,14 +380,14 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image, int device_type = get_device_type(); if ((device_type == K3_DEVICE_TYPE_HS_SE && - strcmp(os, "fsstub-hs")) || + strcmp(os, "tifsstub-hs")) || (device_type == K3_DEVICE_TYPE_HS_FS && - strcmp(os, "fsstub-fs")) || + strcmp(os, "tifsstub-fs")) || (device_type == K3_DEVICE_TYPE_GP && - strcmp(os, "fsstub-gp"))) { + strcmp(os, "tifsstub-gp"))) { *p_size = 0; } else { - debug("fsstub-type: %s\n", os); + debug("tifsstub-type: %s\n", os); } return; -- cgit v1.2.3 From d876900fdc090e0666717615457947c1410a7dbd Mon Sep 17 00:00:00 2001 From: Dhruva Gole Date: Thu, 18 Jan 2024 16:53:23 +0530 Subject: binman: etype: ti_secure_rom.py: remove unused fsstub fsstub seems to be unused and should be removed. Suggested-by: Neha Malcom Francis Signed-off-by: Dhruva Gole Reviewed-by: Neha Malcom Francis --- tools/binman/etype/ti_secure_rom.py | 1 - 1 file changed, 1 deletion(-) diff --git a/tools/binman/etype/ti_secure_rom.py b/tools/binman/etype/ti_secure_rom.py index ff55d9d1a4..74375fc182 100644 --- a/tools/binman/etype/ti_secure_rom.py +++ b/tools/binman/etype/ti_secure_rom.py @@ -66,7 +66,6 @@ class Entry_ti_secure_rom(Entry_x509_cert): super().ReadNode() self.combined = fdt_util.GetBool(self._node, 'combined', False) self.countersign = fdt_util.GetBool(self._node, 'countersign', False) - self.fsstub = fdt_util.GetBool(self._node, 'fsstub', False) self.load_addr = fdt_util.GetInt(self._node, 'load', 0x00000000) self.sw_rev = fdt_util.GetInt(self._node, 'sw-rev', 1) self.sha = fdt_util.GetInt(self._node, 'sha', 512) -- cgit v1.2.3 From 69aea076beafd804d7e51e681a5e29ebd1e75109 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Tue, 23 Jan 2024 13:47:31 +0530 Subject: configs: j722s_evm_r5_defconfig: Increase SPL size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Increase the SPL_MAX_SIZE to 0x6ce00 as J7AEN SRAM has larger loadable memory space for SBL (0x7e000). This also ensures that the SPL does not go beyond the limit while having a single defconfig for different boot modes. Correspondingly, increase CONFIG_SPL_BSS_START_ADDR from 0x43c4b000 to 0x43c7b000 ensuring no overlap in memory. SRAM memory allocation map: ┌─────────────────────────────────────┐ (0x43c00000) │ SPL (0x6ce00) │ ├─────────────────────────────────────┤ (0x43c6ce00) │ EMPTY (0x50) │ ├─────────────────────────────────────┤ (0x43C6CE50) │ STACK │ │ SPL_SIZE_LIMIT_PROVIDE_STACK=0x5000 │ ├─────────────────────────────────────┤ (0x43C71E50) │ Global data │ │ sizeof(struct global_data) = 0x1ac | | (+0x4) │ ├─────────────────────────────────────┤ (0x43C72000) │ HEAP │ │ CONFIG_SYS_MALLOC_F_LEN = 0x9000 │ ├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR │ SPL BSS │ (0x43c7b000) │ CONFIG_SPL_BSS_MAX_SIZE = 0x3000 │ ├─────────────────────────────────────┤ (0x43c7e000) │ ROM Boot parameter table │ └─────────────────────────────────────┘CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX (0x43c7f290) Fixes: b5d58d70642f ("configs: introduce configs needed for the J722S") Signed-off-by: Jayesh Choudhary --- configs/j722s_evm_r5_defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig index c131ccc6dd..9860fa8d62 100644 --- a/configs/j722s_evm_r5_defconfig +++ b/configs/j722s_evm_r5_defconfig @@ -32,10 +32,10 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y -CONFIG_SPL_MAX_SIZE=0x3B000 +CONFIG_SPL_MAX_SIZE=0x6ce00 CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x43c4b000 +CONFIG_SPL_BSS_START_ADDR=0x43c7b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -- cgit v1.2.3 From e44db31e6ac36183bd3e93e5c671aca567093da7 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Tue, 23 Jan 2024 13:47:32 +0530 Subject: arm: mach-k3: j722s: Enable QoS for DSS and MAIN-R5F Enable Quality of Service blocks for Display Subsystem DSS0 and DSS1 and Main R5F core by servicing their traffic from RT queue. Signed-off-by: Jayesh Choudhary --- arch/arm/mach-k3/include/mach/hardware.h | 4 ++ arch/arm/mach-k3/include/mach/j722s_qos.h | 87 +++++++++++++++++++++++++++++++ arch/arm/mach-k3/j722s/Makefile | 1 + arch/arm/mach-k3/j722s/j722s_qos_data.c | 79 ++++++++++++++++++++++++++++ arch/arm/mach-k3/j722s_init.c | 16 ++++++ 5 files changed, 187 insertions(+) create mode 100644 arch/arm/mach-k3/include/mach/j722s_qos.h create mode 100644 arch/arm/mach-k3/j722s/j722s_qos_data.c diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 90a65eeaff..f7f0100358 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -43,6 +43,7 @@ #ifdef CONFIG_SOC_K3_J722S #include "j722s_hardware.h" +#include "j722s_qos.h" #endif /* Assuming these addresses and definitions stay common across K3 devices */ @@ -152,4 +153,7 @@ struct k3_qos_data { extern struct k3_qos_data am62a_qos_data[]; extern u32 am62a_qos_count; +extern struct k3_qos_data j722s_qos_data[]; +extern u32 j722s_qos_count; + #endif /* _ASM_ARCH_HARDWARE_H_ */ diff --git a/arch/arm/mach-k3/include/mach/j722s_qos.h b/arch/arm/mach-k3/include/mach/j722s_qos.h new file mode 100644 index 0000000000..3c49c51fb9 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/j722s_qos.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Keystone3 Quality of service endpoint definitions + * Auto generated by K3 Resource Partitioning Tool + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#define QOS_0 (0 << 0) +#define QOS_1 (1 << 0) +#define QOS_2 (2 << 0) +#define QOS_3 (3 << 0) +#define QOS_4 (4 << 0) +#define QOS_5 (5 << 0) +#define QOS_6 (6 << 0) +#define QOS_7 (7 << 0) + +#define ORDERID_0 (0 << 4) +#define ORDERID_1 (1 << 4) +#define ORDERID_2 (2 << 4) +#define ORDERID_3 (3 << 4) +#define ORDERID_4 (4 << 4) +#define ORDERID_5 (5 << 4) +#define ORDERID_6 (6 << 4) +#define ORDERID_7 (7 << 4) +#define ORDERID_8 (8 << 4) +#define ORDERID_9 (9 << 4) +#define ORDERID_10 (10 << 4) +#define ORDERID_11 (11 << 4) +#define ORDERID_12 (12 << 4) +#define ORDERID_13 (13 << 4) +#define ORDERID_14 (14 << 4) +#define ORDERID_15 (15 << 4) + +#define ASEL_0 (0 << 8) +#define ASEL_1 (1 << 8) +#define ASEL_2 (2 << 8) +#define ASEL_3 (3 << 8) +#define ASEL_4 (4 << 8) +#define ASEL_5 (5 << 8) +#define ASEL_6 (6 << 8) +#define ASEL_7 (7 << 8) +#define ASEL_8 (8 << 8) +#define ASEL_9 (9 << 8) +#define ASEL_10 (10 << 8) +#define ASEL_11 (11 << 8) +#define ASEL_12 (12 << 8) +#define ASEL_13 (13 << 8) +#define ASEL_14 (14 << 8) +#define ASEL_15 (15 << 8) + +#define EPRIORITY_0 (0 << 12) +#define EPRIORITY_1 (1 << 12) +#define EPRIORITY_2 (2 << 12) +#define EPRIORITY_3 (3 << 12) +#define EPRIORITY_4 (4 << 12) +#define EPRIORITY_5 (5 << 12) +#define EPRIORITY_6 (6 << 12) +#define EPRIORITY_7 (7 << 12) + +#define VIRTID_0 (0 << 16) +#define VIRTID_1 (1 << 16) +#define VIRTID_2 (2 << 16) +#define VIRTID_3 (3 << 16) +#define VIRTID_4 (4 << 16) +#define VIRTID_5 (5 << 16) +#define VIRTID_6 (6 << 16) +#define VIRTID_7 (7 << 16) +#define VIRTID_8 (8 << 16) +#define VIRTID_9 (9 << 16) +#define VIRTID_10 (10 << 16) +#define VIRTID_11 (11 << 16) +#define VIRTID_12 (12 << 16) +#define VIRTID_13 (13 << 16) +#define VIRTID_14 (14 << 16) +#define VIRTID_15 (15 << 16) + +#define ATYPE_0 (0 << 28) +#define ATYPE_1 (1 << 28) +#define ATYPE_2 (2 << 28) +#define ATYPE_3 (3 << 28) + +#define PULSAR_UL_MAIN_0_CPU0_RMST 0x45D15000 +#define PULSAR_UL_MAIN_0_CPU0_WMST 0x45D15400 +#define PULSAR_UL_MAIN_0_CPU0_PMST 0x45D15800 +#define K3_DSS_UL_MAIN_0_VBUSM_DMA 0x45D30000 +#define K3_DSS_UL_MAIN_1_VBUSM_DMA 0x45D30400 diff --git a/arch/arm/mach-k3/j722s/Makefile b/arch/arm/mach-k3/j722s/Makefile index 50b0df20a3..1aa540d0a2 100644 --- a/arch/arm/mach-k3/j722s/Makefile +++ b/arch/arm/mach-k3/j722s/Makefile @@ -4,3 +4,4 @@ obj-y += clk-data.o obj-y += dev-data.o +obj-y += j722s_qos_data.o diff --git a/arch/arm/mach-k3/j722s/j722s_qos_data.c b/arch/arm/mach-k3/j722s/j722s_qos_data.c new file mode 100644 index 0000000000..fb1b04f2f5 --- /dev/null +++ b/arch/arm/mach-k3/j722s/j722s_qos_data.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * j722s Quality of Service (QoS) Configuration Data + * Auto generated from K3 Resource Partitioning tool + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ +#include +#include +#include "common.h" + +struct k3_qos_data j722s_qos_data[] = { + /* modules_qosConfig0 - 1 endpoints, 4 channels */ + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0, + .val = ORDERID_15, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 1, + .val = ORDERID_15, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 2, + .val = ORDERID_15, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 3, + .val = ORDERID_15, + }, + + /* modules_qosConfig1 - 1 endpoints, 4 channels */ + { + .reg = K3_DSS_UL_MAIN_1_VBUSM_DMA + 0x100 + 0x4 * 0, + .val = ORDERID_15, + }, + { + .reg = K3_DSS_UL_MAIN_1_VBUSM_DMA + 0x100 + 0x4 * 1, + .val = ORDERID_15, + }, + { + .reg = K3_DSS_UL_MAIN_1_VBUSM_DMA + 0x100 + 0x4 * 2, + .val = ORDERID_15, + }, + { + .reg = K3_DSS_UL_MAIN_1_VBUSM_DMA + 0x100 + 0x4 * 3, + .val = ORDERID_15, + }, + + /* modules_qosConfig2 - 3 endpoints, 1 channels */ + { + .reg = PULSAR_UL_MAIN_0_CPU0_PMST + 0x100 + 0x4 * 0, + .val = ORDERID_15, + }, + { + .reg = PULSAR_UL_MAIN_0_CPU0_RMST + 0x100 + 0x4 * 0, + .val = ORDERID_15, + }, + { + .reg = PULSAR_UL_MAIN_0_CPU0_WMST + 0x100 + 0x4 * 0, + .val = ORDERID_15, + }, + + /* Following registers set 1:1 mapping for orderID MAP1/MAP2 + * remap registers. orderID x is remapped to orderID x again + * This is to ensure orderID from MAP register is unchanged + */ + + /* K3_DSS_UL_MAIN_0_VBUSM_DMA - 0 groups */ + + /* K3_DSS_UL_MAIN_1_VBUSM_DMA - 0 groups */ + + /* PULSAR_UL_MAIN_0_CPU0_PMST - 0 groups */ + + /* PULSAR_UL_MAIN_0_CPU0_RMST - 0 groups */ + + /* PULSAR_UL_MAIN_0_CPU0_WMST - 0 groups */ +}; + +uint32_t j722s_qos_count = sizeof(j722s_qos_data) / sizeof(j722s_qos_data[0]); diff --git a/arch/arm/mach-k3/j722s_init.c b/arch/arm/mach-k3/j722s_init.c index df7a1ce1b9..4708a3498c 100644 --- a/arch/arm/mach-k3/j722s_init.c +++ b/arch/arm/mach-k3/j722s_init.c @@ -66,6 +66,20 @@ static void ctrl_mmr_unlock(void) mmr_unlock(PADCFG_MMR1_BASE, 1); } +#if (IS_ENABLED(CONFIG_CPU_V7R)) +static void setup_qos(void) +{ + u32 i; + + for (i = 0; i < j722s_qos_count; i++) + writel(j722s_qos_data[i].val, (uintptr_t)j722s_qos_data[i].reg); +} +#else +static void setup_qos(void) +{ +} +#endif + void board_init_f(ulong dummy) { struct udevice *dev; @@ -152,6 +166,8 @@ void board_init_f(ulong dummy) panic("DRAM init failed: %d\n", ret); } + setup_qos(); + debug("j722s_init: %s done\n", __func__); } -- cgit v1.2.3 From 99ba8b38f3d710e6dd5553c959685dd5d87aac8c Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Tue, 23 Jan 2024 13:47:33 +0530 Subject: arm: dts: k3-am62p: Disable R5FSS nodes at SoC level and enable in EVM K3 R5 remoteproc driver requires reserved memory carveouts and mailbox configuration to instantiate the cores successfully. Since this is a board level resource dependency, keep the R5 subsystem disabled at SoC level and enable them at EVM where the dependencies are met. Signed-off-by: Vaishnav Achath Signed-off-by: Jayesh Choudhary --- arch/arm/dts/k3-am62p-mcu.dtsi | 2 ++ arch/arm/dts/k3-am62p-wakeup.dtsi | 1 + arch/arm/dts/k3-am62p5-sk.dts | 8 ++++++++ 3 files changed, 11 insertions(+) diff --git a/arch/arm/dts/k3-am62p-mcu.dtsi b/arch/arm/dts/k3-am62p-mcu.dtsi index c4b0b91d70..14eb9ba836 100644 --- a/arch/arm/dts/k3-am62p-mcu.dtsi +++ b/arch/arm/dts/k3-am62p-mcu.dtsi @@ -187,6 +187,8 @@ ranges = <0x79000000 0x00 0x79000000 0x8000>, <0x79020000 0x00 0x79020000 0x8000>; power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + mcu_r5fss0_core0: r5f@79000000 { compatible = "ti,am62-r5f"; reg = <0x79000000 0x00008000>, diff --git a/arch/arm/dts/k3-am62p-wakeup.dtsi b/arch/arm/dts/k3-am62p-wakeup.dtsi index 4c3a74cb97..2883bea201 100644 --- a/arch/arm/dts/k3-am62p-wakeup.dtsi +++ b/arch/arm/dts/k3-am62p-wakeup.dtsi @@ -78,6 +78,7 @@ ranges = <0x78000000 0x00 0x78000000 0x8000>, <0x78100000 0x00 0x78100000 0x8000>; power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; wkup_r5fss0_core0: r5f@78000000 { compatible = "ti,am62-r5f"; diff --git a/arch/arm/dts/k3-am62p5-sk.dts b/arch/arm/dts/k3-am62p5-sk.dts index 9e4479aa78..a7edaa299d 100644 --- a/arch/arm/dts/k3-am62p5-sk.dts +++ b/arch/arm/dts/k3-am62p5-sk.dts @@ -760,12 +760,20 @@ }; }; +&wkup_r5fss0 { + status = "okay"; +}; + &wkup_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_r5_0>; memory-region = <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; }; +&mcu_r5fss0 { + status = "okay"; +}; + &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, -- cgit v1.2.3 From d915176f4863e469625a6a8c36824707ed53b13e Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Tue, 23 Jan 2024 13:47:34 +0530 Subject: arm: dts: k3-j722s: Add IPC support Add Main-R5F and C7x nodes to the SOC file and keep them disabled. Rename the firmwares for MCU and WKUP R5F cores. Enable IPC support for main, mcu and wakeup R5F and C7x cores with memory craveouts and mailboxes. Signed-off-by: Apurva Nandan Signed-off-by: Jayesh Choudhary --- arch/arm/dts/k3-j722s-evm.dts | 112 +++++++++++++++++++++++++++++++++++++++--- arch/arm/dts/k3-j722s.dtsi | 61 +++++++++++++++++++++++ board/ti/j722s/j722s.env | 2 + 3 files changed, 167 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/k3-j722s-evm.dts b/arch/arm/dts/k3-j722s-evm.dts index 15c402662b..7576eca4f8 100644 --- a/arch/arm/dts/k3-j722s-evm.dts +++ b/arch/arm/dts/k3-j722s-evm.dts @@ -49,12 +49,72 @@ no-map; }; + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + c7x_1_memory_region: c7x-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x1c00000>; + alignment = <0x1000>; + no-map; + }; + }; vmain_pd: regulator-0 { @@ -313,14 +373,6 @@ }; }; -&mcu_r5fss0 { - status = "disabled"; -}; - -&wkup_r5fss0 { - status = "disabled"; -}; - &cpsw3g { status = "okay"; pinctrl-names = "default"; @@ -344,3 +396,47 @@ phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy0>; }; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&main_r5fss0 { + status = "okay"; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&c7x_0 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_c7x_0>; + memory-region = <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; +}; + +&c7x_1 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_c7x_1>; + memory-region = <&c7x_1_dma_memory_region>, + <&c7x_1_memory_region>; +}; diff --git a/arch/arm/dts/k3-j722s.dtsi b/arch/arm/dts/k3-j722s.dtsi index 17555145cc..a635d547e7 100644 --- a/arch/arm/dts/k3-j722s.dtsi +++ b/arch/arm/dts/k3-j722s.dtsi @@ -93,3 +93,64 @@ &cpsw_port2 { status = "disabled"; }; + +&cbass_main { + main_r5fss0: r5fss@78400000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x78400000 0x00 0x78400000 0x8000>, + <0x78500000 0x00 0x78500000 0x8000>; + power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + main_r5fss0_core0: r5f@78400000 { + compatible = "ti,am62-r5f"; + reg = <0x78400000 0x00008000>, + <0x78500000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <262>; + ti,sci-proc-ids = <0x04 0xff>; + resets = <&k3_reset 262 1>; + firmware-name = "j722s-main-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + c7x_0: dsp@7e000000 { + compatible = "ti,am62a-c7xv-dsp"; + reg = <0x00 0x7e000000 0x00 0x00200000>; + reg-names = "l2sram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <208>; + ti,sci-proc-ids = <0x30 0xff>; + resets = <&k3_reset 208 1>; + firmware-name = "j722s-c71_0-fw"; + status = "disabled"; + }; + + c7x_1: dsp@7e200000 { + compatible = "ti,am62a-c7xv-dsp"; + reg = <0x00 0x7e200000 0x00 0x00200000>; + reg-names = "l2sram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <268>; + ti,sci-proc-ids = <0x31 0xff>; + resets = <&k3_reset 268 1>; + firmware-name = "j722s-c71_1-fw"; + status = "disabled"; + }; +}; + +/* MCU domain overrides */ +&mcu_r5fss0_core0 { + firmware-name = "j722s-mcu-r5f0_0-fw"; +}; + +/* Wakeup domain overrides */ +&wkup_r5fss0_core0 { + firmware-name = "j722s-wkup-r5f0_0-fw"; +}; diff --git a/board/ti/j722s/j722s.env b/board/ti/j722s/j722s.env index 28fb1776a4..dd8498aba4 100644 --- a/board/ti/j722s/j722s.env +++ b/board/ti/j722s/j722s.env @@ -21,3 +21,5 @@ mmcdev=1 bootpart=1:2 bootdir=/boot rd_spec=- + +rproc_fw_binaries= 0 /lib/firmware/j722s-mcu-r5f0_0-fw 2 /lib/firmware/j722s-main-r5f0_0-fw 3 /lib/firmware/j722s-c71_0-fw 4 /lib/firmware/j722s-c71_1-fw -- cgit v1.2.3 From 2994c329fd5e51277ce74e1e95c1fc64c3d9df0e Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Tue, 23 Jan 2024 13:47:35 +0530 Subject: arm: dts: k3-j722s-evm-u-boot: Add sysreset-controller node Add DMSC child node sysreset-controller for uboot reset. Signed-off-by: Jayesh Choudhary Reviewed-by: Udit Kumar --- arch/arm/dts/k3-j722s-evm-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/k3-j722s-evm-u-boot.dtsi b/arch/arm/dts/k3-j722s-evm-u-boot.dtsi index 4dad876a91..cb5e8e53c0 100644 --- a/arch/arm/dts/k3-j722s-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-j722s-evm-u-boot.dtsi @@ -25,3 +25,11 @@ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg", "tchan", "rchan", "rflow"; }; + +&dmsc { + bootph-pre-ram; + k3_sysreset: sysreset-controller { + compatible = "ti,sci-sysreset"; + bootph-pre-ram; + }; +}; -- cgit v1.2.3 From fe679e57ff2e678ed7152c61cdb1a414cc1f0b59 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Tue, 23 Jan 2024 13:47:36 +0530 Subject: mach-k3: j722s_init: Add FS and raw boot mode support This adds FS and raw boot mode support similar to other K3 platforms with the default boot mode being filesystem. Signed-off-by: Jayesh Choudhary --- arch/arm/mach-k3/j722s_init.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/mach-k3/j722s_init.c b/arch/arm/mach-k3/j722s_init.c index 4708a3498c..4823e5526c 100644 --- a/arch/arm/mach-k3/j722s_init.c +++ b/arch/arm/mach-k3/j722s_init.c @@ -270,3 +270,22 @@ u32 spl_boot_device(void) __func__, devstat, bootmedia, bootindex); return bootmedia; } + +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_EMMC: + return MMCSD_MODE_EMMCBOOT; + case BOOT_DEVICE_MMC: + if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK) + return MMCSD_MODE_RAW; + default: + return MMCSD_MODE_FS; + } +} -- cgit v1.2.3 From 8e29cc8dec2dda343e4751d917e14a2962d081d5 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Tue, 23 Jan 2024 13:47:37 +0530 Subject: arm: dts: k3-j722s-evm: Syncing device tree with kernel Enable eMMC support by adding sdhci0 node. Add cma node and led node as well. Also add missing bootph-all flag for main_i2c0 node. Signed-off-by: Jayesh Choudhary --- arch/arm/dts/k3-j722s-evm.dts | 46 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm/dts/k3-j722s-evm.dts b/arch/arm/dts/k3-j722s-evm.dts index 7576eca4f8..193ce9a551 100644 --- a/arch/arm/dts/k3-j722s-evm.dts +++ b/arch/arm/dts/k3-j722s-evm.dts @@ -8,7 +8,9 @@ /dts-v1/; +#include #include "k3-j722s.dtsi" +#include #include / { @@ -39,6 +41,14 @@ #size-cells = <2>; ranges; + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x38000000>; + linux,cma-default; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; no-map; @@ -182,6 +192,27 @@ regulator-always-on; regulator-boot-on; }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_default>; + + led-0 { + label = "j722s-evm:red:heartbeat"; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "j722s-evm:green:disk-activity"; + gpios = <&exp1 16 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_DISK_ACTIVITY; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + }; }; &main_pmx0 { @@ -246,6 +277,12 @@ >; bootph-all; }; + + led_pins_default: led-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0244, PIN_INPUT, 7) /* (A24) MMC1_SDWP */ + >; + }; }; &main_gpio1 { @@ -301,6 +338,7 @@ pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + bootph-all; exp1: gpio@23 { compatible = "ti,tca6424"; @@ -323,6 +361,14 @@ }; }; +&sdhci0 { + /*eMMC*/ + status = "okay"; + ti,driver-strength-ohm = <50>; + disable-wp; + bootph-all; +}; + &sdhci1 { /* SD/MMC */ status = "okay"; -- cgit v1.2.3 From 64962b62f04a5b17729d3d3c27e90686230c65de Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Tue, 30 Jan 2024 18:33:02 +0530 Subject: arm: mach-k3: j721s2_init: Support less than max DDR controllers The number of DDR controllers to be initialised and used should depend on the device tree with the constraint of the maximum number of controllers the device supports. Since J721S2 has multiple (2) controllers, instead of hardcoding the number of probes, move to depending on the device tree UCLASS_RAM nodes present. Signed-off-by: Neha Malcom Francis Reviewed-by: Udit Kumar --- arch/arm/mach-k3/j721s2_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c index f30a65c375..6995099a21 100644 --- a/arch/arm/mach-k3/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2_init.c @@ -236,7 +236,7 @@ void k3_mem_init(void) panic("DRAM 0 init failed: %d\n", ret); ret = uclass_next_device_err(&dev); - if (ret) + if (ret && ret != -ENODEV) panic("DRAM 1 init failed: %d\n", ret); } spl_enable_dcache(); -- cgit v1.2.3 From 40cc7d7e0382cece400e74b4972e998ffa03c74d Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Tue, 30 Jan 2024 18:33:03 +0530 Subject: arm: mach-k3: j784s4_init: Support less than max DDR controllers The number of DDR controllers to be initialised and used should depend on the device tree with the constraint of the maximum number of controllers the device supports. Since J784S4 has multiple (4) controllers, instead of hardcoding the number of probes, move to depending on the device tree UCLASS_RAM nodes present. Signed-off-by: Neha Malcom Francis --- arch/arm/mach-k3/j784s4_init.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-k3/j784s4_init.c b/arch/arm/mach-k3/j784s4_init.c index 9bd71d0257..5854e645bc 100644 --- a/arch/arm/mach-k3/j784s4_init.c +++ b/arch/arm/mach-k3/j784s4_init.c @@ -137,10 +137,12 @@ static void store_boot_info_from_rom(void) sizeof(struct rom_extended_boot_data)); } +#define J784S4_MAX_CONTROLLERS 4 + void board_init_f(ulong dummy) { struct udevice *dev; - int ret; + int ret, ctr = 1; /* * Cannot delay this further as there is a chance that @@ -222,17 +224,13 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM 0 init failed: %d\n", ret); - ret = uclass_next_device_err(&dev); - if (ret) - panic("DRAM 1 init failed: %d\n", ret); - - ret = uclass_next_device_err(&dev); - if (ret) - panic("DRAM 2 init failed: %d\n", ret); + while (ctr < J784S4_MAX_CONTROLLERS) { + ret = uclass_next_device_err(&dev); - ret = uclass_next_device_err(&dev); - if (ret) - panic("DRAM 3 init failed: %d\n", ret); + if (ret && ret != -ENODEV) + panic("DRAM %d init failed: %d\n", ctr, ret); + ctr++; + } } spl_enable_dcache(); -- cgit v1.2.3 From 8bc0f4b92b66ef0b76319d36c2ce0e50870534fe Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Wed, 24 Jan 2024 20:33:42 +0530 Subject: configs: am62px_evm_a53_defconfig: Sort the defconfig Run `make savedefconfig` to sort the defconfig. Signed-off-by: Devarsh Thakkar --- configs/am62px_evm_a53_defconfig | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig index 25df83fbea..637a52fa09 100644 --- a/configs/am62px_evm_a53_defconfig +++ b/configs/am62px_evm_a53_defconfig @@ -12,13 +12,11 @@ CONFIG_K3_ATF_LOAD_ADDR=0x9e780000 CONFIG_TARGET_AM62P5_A53_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 -CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_ENV_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-sk" CONFIG_SPL_TEXT_BASE=0x80080000 -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y @@ -56,6 +54,10 @@ CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_THERMAL=y +CONFIG_SPL_USB_HOST=y +CONFIG_SPL_USB_STORAGE=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_CLK=y @@ -127,6 +129,7 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_SPI_NAND=y CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_SOFT_RESET=y CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y @@ -165,18 +168,15 @@ CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y -CONFIG_SPL_USB_HOST=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_SPL_USB_DWC3_AM62=y CONFIG_USB_DWC3_AM62=y -CONFIG_SPL_USB_STORAGE=y CONFIG_USB_GADGET=y -CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 -CONFIG_SPL_DFU=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_OF_LIBFDT_OVERLAY=y -- cgit v1.2.3 From 7b99bf9139e5622eff835a4f6e4baf96f3a3fccf Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Wed, 24 Jan 2024 20:33:43 +0530 Subject: common: splash_source: Don't compile ubifs splash cmd for SPL build Don't compile ubifs splash mount command for SPL build as this command is not supported (and also not enabled) during SPL stage. This fixes below compilation error, when CONFIG_CMD_UBIFS is enabled in defconfig along with splash screen enabled at SPL stage: "aarch64-none-linux-gnu-ld.bfd: common/cli.o: in function `run_command': u-boot-next/u-boot/common/cli.c:51: undefined reference to `parse_string_outer' u-boot-next/u-boot/common/cli.c:51:(.text.run_command+0x10): relocation truncated to fit: R_AARCH64_JUMP26 against undefined symbol `parse_string_outer' make[2]: *** [u-boot-next/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make[1]: *** [u-boot-next/u-boot/Makefile:2053: spl/u-boot-spl] Error 2 make[1]: Leaving directory 'u-boot-next/u-boot/out/a53' make: *** [Makefile:177: sub-make] Error 2" Fixes: eb9217dc03 ("common: Enable splash functions at SPL") Signed-off-by: Devarsh Thakkar --- common/splash_source.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/splash_source.c b/common/splash_source.c index 7fb28d7713..a17a797fbd 100644 --- a/common/splash_source.c +++ b/common/splash_source.c @@ -216,7 +216,7 @@ static int splash_init_virtio(void) } } -#ifdef CONFIG_CMD_UBIFS +#if defined(CONFIG_CMD_UBIFS) && !defined(CONFIG_SPL_BUILD) static int splash_mount_ubifs(struct splash_location *location) { int res; -- cgit v1.2.3 From 6552a089757bb00bb62d081b0c596e33b9fd3a25 Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Wed, 24 Jan 2024 20:33:44 +0530 Subject: video: tidss: Use DT property names for parsing nodes Use device-tree node property names for parsing nodes instead of indexing as indexing could be different between different SoCs based on number of DSS entities available on that particular SoC. Also correct the video layer naming in driver to match to actual one being used in upstream DSS device-tree node [1]. This also fixes AM62x splash screen usage using the latest upstream DSS device-tree nodes where hard-coded indexing which driver was using before this patch was not matching the correct properties in the DT node. [1]: Upstream AM62x DSS node: https://github.com/torvalds/linux/blob/v6.8-rc1/arch/arm64/boot/dts/ti/k3-am62-main.dtsi#L774 Fixes: 5f9f816bb8 ("drivers: video: tidss: TIDSS video driver support for AM62x") Signed-off-by: Devarsh Thakkar --- drivers/video/tidss/tidss_drv.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/video/tidss/tidss_drv.c b/drivers/video/tidss/tidss_drv.c index e285f255d7..1380c6b693 100644 --- a/drivers/video/tidss/tidss_drv.c +++ b/drivers/video/tidss/tidss_drv.c @@ -107,7 +107,7 @@ const struct dss_features dss_am625_feats = { .num_planes = 2, /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ - .vid_name = { "vidl1", "vid1" }, + .vid_name = { "vidl1", "vid" }, .vid_lite = { true, false }, .vid_order = { 1, 0 }, }; @@ -814,13 +814,13 @@ static int tidss_drv_probe(struct udevice *dev) priv->bus_format = &dss_bus_formats[8]; /* Common address */ - priv->base_common = dev_remap_addr_index(dev, 0); + priv->base_common = dev_remap_addr_name(dev, priv->feat->common); if (!priv->base_common) return -EINVAL; /* plane address setup and enable */ for (i = 0; i < priv->feat->num_planes; i++) { - priv->base_vid[i] = dev_remap_addr_index(dev, i + 2); + priv->base_vid[i] = dev_remap_addr_name(dev, priv->feat->vid_name[i]); if (!priv->base_vid[i]) return -EINVAL; } @@ -841,8 +841,8 @@ static int tidss_drv_probe(struct udevice *dev) /* video port address clocks and enable */ for (i = 0; i < priv->feat->num_vps; i++) { - priv->base_ovr[i] = dev_remap_addr_index(dev, i + 4); - priv->base_vp[i] = dev_remap_addr_index(dev, i + 6); + priv->base_ovr[i] = dev_remap_addr_name(dev, priv->feat->ovr_name[i]); + priv->base_vp[i] = dev_remap_addr_name(dev, priv->feat->vp_name[i]); } ret = clk_get_by_name(dev, "vp1", &priv->vp_clk[0]); -- cgit v1.2.3 From 66d40b4cd79189a36d326263afd1c8c6f04cd0e4 Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Wed, 24 Jan 2024 20:33:45 +0530 Subject: arm: mach-k3: am62p5: Setup data cache and video memory for SPL Setup page table, data cache and reserve memory for SPL as a precursor to enable splash screen for AM62P platform Signed-off-by: Devarsh Thakkar --- arch/arm/mach-k3/am62p5_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-k3/am62p5_init.c b/arch/arm/mach-k3/am62p5_init.c index ac1b01bd84..19ddefc3e9 100644 --- a/arch/arm/mach-k3/am62p5_init.c +++ b/arch/arm/mach-k3/am62p5_init.c @@ -158,6 +158,7 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM init failed: %d\n", ret); #endif + spl_enable_dcache(); debug("am62px_init: %s done\n", __func__); } -- cgit v1.2.3 From a7e8f56abf905ee0984f93766f9065e65e215fed Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Wed, 24 Jan 2024 20:33:46 +0530 Subject: board: ti: am62p: Add splash screen support Add MMC and OSPI NOR flash as storage locations for splash screen Enable video memory reservation and splash display by calling board specific routine for splash screen. Signed-off-by: Devarsh Thakkar --- board/ti/am62px/evm.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c index 60b5606dea..23716ed99a 100644 --- a/board/ti/am62px/evm.c +++ b/board/ti/am62px/evm.c @@ -13,9 +13,34 @@ #include #include #include +#include +#include #include "../common/rtc.c" +#if CONFIG_IS_ENABLED(SPLASH_SCREEN) +static struct splash_location default_splash_locations[] = { + { + .name = "sf", + .storage = SPLASH_STORAGE_SF, + .flags = SPLASH_STORAGE_RAW, + .offset = 0x700000, + }, + { + .name = "mmc", + .storage = SPLASH_STORAGE_MMC, + .flags = SPLASH_STORAGE_FS, + .devpart = "1:1", + }, +}; + +int splash_screen_prepare(void) +{ + return splash_source_load(default_splash_locations, + ARRAY_SIZE(default_splash_locations)); +} +#endif + int board_init(void) { if (IS_ENABLED(CONFIG_BOARD_HAS_32K_RTC_CRYSTAL)) @@ -33,3 +58,31 @@ int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); } + +#if defined(CONFIG_SPL_BUILD) +static int video_setup(void) +{ + if (CONFIG_IS_ENABLED(VIDEO)) { + ulong addr; + int ret; + + addr = gd->relocaddr; + ret = video_reserve(&addr); + if (ret) + return ret; + debug("Reserving %luk for video at: %08lx\n", + ((unsigned long)gd->relocaddr - addr) >> 10, addr); + gd->relocaddr = addr; + } + + return 0; +} + +void spl_board_init(void) +{ + video_setup(); + enable_caches(); + if (IS_ENABLED(CONFIG_SPL_SPLASH_SCREEN) && IS_ENABLED(CONFIG_SPL_BMP)) + splash_display(); +} +#endif -- cgit v1.2.3 From fe9d957bc8c7637bd1a3c43773a3e891bebd35b5 Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Wed, 24 Jan 2024 20:33:47 +0530 Subject: board: ti: am62p: Add splash screen specific environment support - Add splash screen related environment variables for AM62P platform. - Set default splash location to MMC. Signed-off-by: Devarsh Thakkar --- board/ti/am62px/am62px.env | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/board/ti/am62px/am62px.env b/board/ti/am62px/am62px.env index 2e49ebfa27..7df87bb8ad 100644 --- a/board/ti/am62px/am62px.env +++ b/board/ti/am62px/am62px.env @@ -23,6 +23,11 @@ bootdir=/boot rd_spec=- rproc_fw_binaries= 0 /lib/firmware/am62p-mcu-r5f0_0-fw +splashfile=ti_logo_414x97_32bpp.bmp.gz +splashimage=0x80200000 +splashpos=m,m +splashsource=mmc + #if CONFIG_CMD_ABOOTIMG #include #endif -- cgit v1.2.3 From 7f95e3e7cbbbcecc75a6820044846a32658dea06 Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Wed, 24 Jan 2024 20:33:48 +0530 Subject: configs: am62px: Add splash screen support at A53 SPL - Enable BMP and Splash screen related configs - Enable bloblist support to pass video blob from SPL stage to U-boot proper. - Use same memory map for enabling splash screen as used for AM62x[1] : -> Create space for loading bmp image file by moving the malloc area and BSS region down to 0x80b80000 and 0x80c80000 respectively -> Increase the SPL size limit and SPL stack size to 512 KiB and 2KiB respectively to accommodate splash support -> Set stack above the malloc region and report stack overflow by setting CONFIG_SPL_SYS_REPORT_STACK_F_USAGE - Enable simple malloc() for A53 SPL [1]: https://source.denx.de/u-boot/u-boot/-/blob/v2024.01/doc/board/ti/am62x_sk.rst?ref_type=tags Signed-off-by: Devarsh Thakkar --- configs/am62px_evm_a53_defconfig | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig index 637a52fa09..3c739d7ac8 100644 --- a/configs/am62px_evm_a53_defconfig +++ b/configs/am62px_evm_a53_defconfig @@ -11,7 +11,7 @@ CONFIG_SOC_K3_AM62P5=y CONFIG_K3_ATF_LOAD_ADDR=0x9e780000 CONFIG_TARGET_AM62P5_A53_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000 CONFIG_ENV_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y @@ -21,6 +21,8 @@ CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SIZE_LIMIT=0x80000 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -30,13 +32,18 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" +CONFIG_BLOBLIST=y +CONFIG_BLOBLIST_ADDR=0x80D00000 CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_START_ADDR=0x80c80000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y @@ -59,6 +66,7 @@ CONFIG_SPL_USB_STORAGE=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SPL_BMP=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y @@ -71,6 +79,7 @@ CONFIG_CMD_MTD=y CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_BMP=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y @@ -178,5 +187,21 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPL_VIDEO_TIDSS=y +CONFIG_VIDEO_BMP_GZIP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_SPL_VIDEO=y +CONFIG_SPL_SPLASH_SCREEN=y +CONFIG_SPL_SYS_WHITE_ON_BLACK=y +CONFIG_SPL_SPLASH_SCREEN_ALIGN=y +CONFIG_SPL_SPLASH_SOURCE=y +CONFIG_SPL_VIDEO_BMP_GZIP=y +CONFIG_SPL_BMP_24BPP=y +CONFIG_SPL_BMP_32BPP=y +CONFIG_SPL_HIDE_LOGO_VERSION=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_SPL_GZIP=y CONFIG_OF_LIBFDT_OVERLAY=y -- cgit v1.2.3 From 546af1adfaf48edc31940c10f3eb8aa5775f64f4 Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Wed, 24 Jan 2024 20:33:49 +0530 Subject: arm: dts: k3-am62p: Enable splash screen using OLDI panel - Enable splash screen for AM62P using DSS0 instance and microtips mf101hie OLDI panel. - As DSS0 instance has same register space , video ports and video planes as AM62x use the same compatible as AM62x. Signed-off-by: Devarsh Thakkar --- arch/arm/dts/k3-am62p-main.dtsi | 4 +++- arch/arm/dts/k3-am62p5-sk.dts | 52 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-am62p-main.dtsi b/arch/arm/dts/k3-am62p-main.dtsi index 9281a3f2a5..90427985ee 100644 --- a/arch/arm/dts/k3-am62p-main.dtsi +++ b/arch/arm/dts/k3-am62p-main.dtsi @@ -42,6 +42,7 @@ main_conf: bus@100000 { compatible = "simple-bus"; + bootph-pre-ram; reg = <0x00 0x00100000 0x00 0x20000>; #address-cells = <1>; #size-cells = <1>; @@ -60,6 +61,7 @@ }; dss_oldi_io_ctrl: dss-oldi-io-ctrl@8600 { + bootph-pre-ram; compatible = "syscon"; reg = <0x8600 0x200>; }; @@ -1017,7 +1019,7 @@ }; dss0: dss@30200000 { - compatible = "ti,am62p51-dss"; + compatible = "ti,am625-dss"; reg = <0x00 0x30200000 0x00 0x1000>, /* common */ <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ <0x00 0x30206000 0x00 0x1000>, /* vid */ diff --git a/arch/arm/dts/k3-am62p5-sk.dts b/arch/arm/dts/k3-am62p5-sk.dts index a7edaa299d..1843ea59d3 100644 --- a/arch/arm/dts/k3-am62p5-sk.dts +++ b/arch/arm/dts/k3-am62p5-sk.dts @@ -744,6 +744,41 @@ }; }; }; + + panel_lvds: panel-lvds { + bootph-pre-ram; + compatible = "simple-panel"; + status= "okay"; + width-mm = <217>; + height-mm = <136>; + data-mapping = "vesa-24"; + panel-timings { + bootph-pre-ram; + clock-frequency = <150274>; + hactive = <1920>; + vactive = <1200>; + hback-porch = <32>; + hfront-porch = <52>; + vback-porch = <24>; + vfront-porch = <8>; + hsync-len = <24>; + vsync-len = <3>; + de-active = <1>; + }; + port@0 { + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_out0>; + }; + }; + + port@1 { + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_out1>; + }; + }; + }; }; &mailbox0_cluster0 { @@ -818,6 +853,7 @@ }; &dss0 { + bootph-pre-ram; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_dpi_pins_default>; @@ -825,12 +861,28 @@ &dss0_ports { /* DSS0-VP2: DPI/HDMI Output */ + /* VP1: LVDS Output (OLDI TX 0) */ + port@0 { + reg = <0>; + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; + port@1 { reg = <1>; dss0_dpi1_out: endpoint { remote-endpoint = <&sii9022_in>; }; }; + + /* VP1: LVDS Output (OLDI TX 1) */ + port@2 { + reg = <2>; + oldi_out1: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; }; &ti_csi2rx0 { -- cgit v1.2.3 From e7d2df2ecfb3591938087335d81ebf0498dc8ece Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Wed, 31 Jan 2024 18:35:35 +0530 Subject: configs: am62px: Add config fragment to disable splashscreen Add config fragment to disable splashscreen related Kconfigs and also revert back to older memory map to save space. It is especially required to disable U-boot splash screen when using custom device manager firmware which use RTOS based splash screen during bootup. Signed-off-by: Devarsh Thakkar --- configs/am62px_evm_prune_splashscreen.config | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 configs/am62px_evm_prune_splashscreen.config diff --git a/configs/am62px_evm_prune_splashscreen.config b/configs/am62px_evm_prune_splashscreen.config new file mode 100644 index 0000000000..b45a7b347f --- /dev/null +++ b/configs/am62px_evm_prune_splashscreen.config @@ -0,0 +1,28 @@ +CONFIG_VIDEO=n +CONFIG_SYS_WHITE_ON_BLACK=n +CONFIG_SPL_VIDEO_TIDSS=n +CONFIG_VIDEO_BMP_GZIP=n +CONFIG_BMP=n +CONFIG_BMP_24BPP=n +CONFIG_BMP_32BPP=n +CONFIG_SPL_VIDEO=n +CONFIG_SPL_SPLASH_SCREEN=n +CONFIG_SPL_SYS_WHITE_ON_BLACK=n +CONFIG_SPL_SPLASH_SCREEN_ALIGN=n +CONFIG_SPL_SPLASH_SOURCE=n +CONFIG_SPL_VIDEO_BMP_GZIP=n +CONFIG_SPL_BMP_24BPP=n +CONFIG_SPL_BMP_32BPP=n +CONFIG_SPL_HIDE_LOGO_VERSION=n +CONFIG_SPL_GZIP=n +CONFIG_CMD_BMP=n +CONFIG_CMD_BLOBLIST=n +CONFIG_SPL_BMP=n +CONFIG_SYS_SPL_MALLOC=n +CONFIG_SPL_BOARD_INIT=n +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=n +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_BLOBLIST=n +# CONFIG_SPL_SIZE_LIMIT is not set +# CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK is not set +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 -- cgit v1.2.3 From 42ac92110c35a83b60514ff56b30ffba3ef0c79b Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 6 Feb 2024 15:54:37 +0200 Subject: memory: ti-gpmc: use printf to dump settings/timings pr_info() depends on CONFIG_LOGLEVEL > 6. If user has enabled CONFIG_TI_GPMC_DEBUG then we should print the GPMC settings/timings regardless of CONFIG_LOGLEVEL. So use printf() instead of pr_info(). Signed-off-by: Roger Quadros --- drivers/memory/ti-gpmc.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/memory/ti-gpmc.c b/drivers/memory/ti-gpmc.c index 399b683373..220e58bab2 100644 --- a/drivers/memory/ti-gpmc.c +++ b/drivers/memory/ti-gpmc.c @@ -244,20 +244,20 @@ static int get_gpmc_timing_reg(/* timing specifiers */ if (l) time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1; time_ns = gpmc_clk_ticks_to_ns(l, cs, cd); - pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n", - name, time_ns, time_ns_min, time_ns, l, - invalid ? "; invalid " : " "); + printf("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n", + name, time_ns, time_ns_min, time_ns, l, + invalid ? "; invalid " : " "); } else { /* raw format */ - pr_info("gpmc,%s = <%u>;%s\n", name, l, - invalid ? " /* invalid */" : ""); + printf("gpmc,%s = <%u>;%s\n", name, l, + invalid ? " /* invalid */" : ""); } return l; } #define GPMC_PRINT_CONFIG(cs, config) \ - pr_info("CS%i %s: 0x%08x\n", cs, #config, \ + printf("CS%i %s: 0x%08x\n", cs, #config, \ gpmc_cs_read_reg(cs, config)) #define GPMC_GET_RAW(reg, st, end, field) \ get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0) @@ -276,7 +276,7 @@ static int get_gpmc_timing_reg(/* timing specifiers */ static void gpmc_show_regs(int cs, const char *desc) { - pr_info("gpmc cs%i %s:\n", cs, desc); + printf("gpmc cs%i %s:\n", cs, desc); GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1); GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2); GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3); @@ -293,7 +293,7 @@ static void gpmc_cs_show_timings(int cs, const char *desc) { gpmc_show_regs(cs, desc); - pr_info("gpmc cs%i access configuration:\n", cs); + printf("gpmc cs%i access configuration:\n", cs); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity"); GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data"); GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1, @@ -320,7 +320,7 @@ static void gpmc_cs_show_timings(int cs, const char *desc) GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen"); - pr_info("gpmc cs%i timings configuration:\n", cs); + printf("gpmc cs%i timings configuration:\n", cs); GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns"); GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns"); @@ -411,9 +411,9 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max l = gpmc_cs_read_reg(cs, reg); if (IS_ENABLED(CONFIG_TI_GPMC_DEBUG)) { - pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", - cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000, - (l >> st_bit) & mask, time); + printf("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", + cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000, + (l >> st_bit) & mask, time); } l &= ~(mask << st_bit); @@ -620,8 +620,8 @@ static int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t, return -ENXIO; if (IS_ENABLED(CONFIG_TI_GPMC_DEBUG)) { - pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n", - cs, (div * gpmc_get_fclk_period()) / 1000, div); + printf("GPMC CS%d CLK period is %lu ns (div %d)\n", + cs, (div * gpmc_get_fclk_period()) / 1000, div); } gpmc_cs_bool_timings(cs, &t->bool_timings); -- cgit v1.2.3 From fffb6d1b1a156f37a38fb2f0cb36f35b19c49874 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 6 Feb 2024 15:54:38 +0200 Subject: memory: ti-gpmc: Fix lock up at A53 SPL during NAND boot on AM64-EVM AM64 ES2.0 bootrom seems to enable WAIT0EDGEDETECTION interrupt. This causes a lockup at A53 SPL when accessing NAND controller or ELM registers. A good option would be to softrest GPMC block at probe but this cannot be done for AM64 as SOFTRESET bit is marked as reserved in SYSCONFIG register. Fix the issue by disabling all IRQs at probe. Signed-off-by: Roger Quadros --- drivers/memory/ti-gpmc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/memory/ti-gpmc.c b/drivers/memory/ti-gpmc.c index 220e58bab2..76d80a2317 100644 --- a/drivers/memory/ti-gpmc.c +++ b/drivers/memory/ti-gpmc.c @@ -1197,6 +1197,12 @@ static int gpmc_probe(struct udevice *dev) gpmc_cfg = (struct gpmc *)priv->base; gpmc_base = priv->base; + /* + * Disable all IRQs as some bootroms might leave them enabled + * and that will cause a lock-up later + */ + gpmc_write_reg(GPMC_IRQENABLE, 0); + priv->l3_clk = devm_clk_get(dev, "fck"); if (IS_ERR(priv->l3_clk)) return PTR_ERR(priv->l3_clk); -- cgit v1.2.3 From 54de08386bbf9d62aebf4760ff0fb9443ff95400 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 6 Feb 2024 15:54:39 +0200 Subject: configs: am64x_evm_r5_defconfig: Enable CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY Expansion cards like NAND are available as a Device Tree Overlay blob in the FIT image. Enable CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY to R5 SPL can apply the overlay before loading next stage. Signed-off-by: Roger Quadros --- configs/am64x_evm_r5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index 722f3e7149..7f7c3cf0be 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run distro_bootcmd" -- cgit v1.2.3 From e37265b19fcac37b7e745d829f155ebe7207fc88 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 6 Feb 2024 15:54:40 +0200 Subject: configs: am64x_evm_r5_defconfig: Add NAND boot support Include the configuration required for booting from NAND. Signed-off-by: Roger Quadros --- configs/am64x_evm_r5_defconfig | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index 7f7c3cf0be..8a7d6a1b3a 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -192,3 +192,29 @@ CONFIG_SYSRESET_TI_SCI=y CONFIG_DM_PCA953X=y CONFIG_SPL_DM_PCA953X=y CONFIG_DM_I2C_GPIO=y +CONFIG_MTD=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_DM_MTD=y +CONFIG_MEMORY=y +CONFIG_SPL_MEMORY=y +CONFIG_TI_GPMC=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_OMAP_GPMC=y +CONFIG_NAND_OMAP_ELM=y +CONFIG_NAND_OMAP_ELM=y +CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW=y +CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_PAGE_SIZE=0x1000 +CONFIG_SYS_NAND_PAGE_COUNT=0x40 +CONFIG_SYS_NAND_OOBSIZE=0x100 +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_NAND_DRIVERS=y +CONFIG_SPL_NAND_BASE=y +CONFIG_SPL_NAND_IDENT=y +CONFIG_SPL_NAND_ECC=y +CONFIG_SYS_NAND_MAX_CHIPS=1 +CONFIG_SYS_MAX_NAND_DEVICE=1 +# CONFIG_SPL_NAND_AM33XX_BCH is not set +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000 -- cgit v1.2.3 From 28eaa6eb15204cb3e3cc8ed938341392c62dc218 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 6 Feb 2024 15:54:41 +0200 Subject: arm: dts: k3-am642-r5-evm.dts: Add NAND boot support For R5 SPL, we include the NAND support in the board DTS file (k3-am642-r5-evm.dts) as there is no way to use overlay in BootROM at the moment. Signed-off-by: Roger Quadros --- arch/arm/dts/k3-am642-r5-evm.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts index 57d78e449c..534c6b9dc8 100644 --- a/arch/arm/dts/k3-am642-r5-evm.dts +++ b/arch/arm/dts/k3-am642-r5-evm.dts @@ -382,4 +382,22 @@ }; }; +#include "k3-am642-evm-nand.dtsi" + +&gpmc0_pins_default { + bootph-all; +}; + +&gpmc0 { + bootph-all; +}; + +&main_gpio0 { + bootph-all; +}; + +&nand0_0 { + bootph-all; +}; + #include "k3-am642-evm-u-boot.dtsi" -- cgit v1.2.3 From 5a514a5c3962848a06d98f2dd319f9731f968123 Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Fri, 2 Feb 2024 15:49:55 +0530 Subject: arm: dts: k3-j721e-main: Update delay select values for MMC subsystems Update the delay values for various speed modes supported, based on the revised august 2021 J721E Datasheet [1]. [1] https://www.ti.com/lit/ds/symlink/tda4vm.pdf, (SPRSP36J - FEBRUARY 2019 - REVISED AUGUST 2021) - Table 7-77. MMC0 DLL Delay Mapping for All Timing Modes and - Table 7-86. MMC1/2 DLL Delay Mapping for All Timing Modes, in Signed-off-by: Bhavya Kapoor --- arch/arm/dts/k3-j721e-main.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi index 2142f9c163..3306fba5d1 100644 --- a/arch/arm/dts/k3-j721e-main.dtsi +++ b/arch/arm/dts/k3-j721e-main.dtsi @@ -1040,8 +1040,8 @@ bus-width = <8>; mmc-hs200-1_8v; mmc-ddr-1_8v; - ti,otap-del-sel-legacy = <0xf>; - ti,otap-del-sel-mmc-hs = <0xf>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x6>; ti,otap-del-sel-hs400 = <0x0>; @@ -1063,11 +1063,12 @@ assigned-clocks = <&k3_clks 92 0>; assigned-clock-parents = <&k3_clks 92 1>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; @@ -1089,11 +1090,12 @@ assigned-clocks = <&k3_clks 93 0>; assigned-clock-parents = <&k3_clks 93 1>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; -- cgit v1.2.3 From 29e892fb57d85c438a744e06b21276b2d692fa3a Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Wed, 14 Feb 2024 16:10:59 +0530 Subject: board: ti: j722s: Sync board files with latest RM config Update to the latest RM (Resource Management) auto-generated YAMLs. This accommodates CSI INT_AGG fix for Linux and RTOS both. Signed-off-by: Jayesh Choudhary Reviewed-by: Udit Kumar Reviewed-by: Neha Malcom Francis --- board/ti/j722s/rm-cfg.yaml | 80 +++++++++++++---------------------------- board/ti/j722s/tifs-rm-cfg.yaml | 60 ++++++++++--------------------- 2 files changed, 43 insertions(+), 97 deletions(-) diff --git a/board/ti/j722s/rm-cfg.yaml b/board/ti/j722s/rm-cfg.yaml index 2639c9935e..5297884305 100644 --- a/board/ti/j722s/rm-cfg.yaml +++ b/board/ti/j722s/rm-cfg.yaml @@ -244,7 +244,7 @@ rm-cfg: subhdr: magic: 0x7B25 size: 8 - resasg_entries_size: 1200 + resasg_entries_size: 1160 reserved: 0 resasg_entries: - @@ -511,18 +511,6 @@ rm-cfg: type: 1802 host_id: 12 reserved: 0 - - - start_resource: 28 - num_resource: 6 - type: 1802 - host_id: 20 - reserved: 0 - - - start_resource: 34 - num_resource: 6 - type: 1802 - host_id: 22 - reserved: 0 - start_resource: 44 num_resource: 36 @@ -535,6 +523,18 @@ rm-cfg: type: 1802 host_id: 36 reserved: 0 + - + start_resource: 84 + num_resource: 16 + type: 1802 + host_id: 20 + reserved: 0 + - + start_resource: 100 + num_resource: 16 + type: 1802 + host_id: 22 + reserved: 0 - start_resource: 154 num_resource: 14 @@ -1017,22 +1017,16 @@ rm-cfg: reserved: 0 - start_resource: 8 - num_resource: 4 + num_resource: 12 type: 12750 host_id: 12 reserved: 0 - - start_resource: 12 + start_resource: 20 num_resource: 20 type: 12750 host_id: 38 reserved: 0 - - - start_resource: 32 - num_resource: 8 - type: 12750 - host_id: 128 - reserved: 0 - start_resource: 0 num_resource: 8 @@ -1041,22 +1035,16 @@ rm-cfg: reserved: 0 - start_resource: 0 - num_resource: 4 + num_resource: 12 type: 12769 host_id: 12 reserved: 0 - - start_resource: 4 + start_resource: 12 num_resource: 20 type: 12769 host_id: 38 reserved: 0 - - - start_resource: 24 - num_resource: 8 - type: 12769 - host_id: 128 - reserved: 0 - start_resource: 0 num_resource: 8 @@ -1065,22 +1053,10 @@ rm-cfg: reserved: 0 - start_resource: 0 - num_resource: 2 + num_resource: 8 type: 12810 host_id: 12 reserved: 0 - - - start_resource: 2 - num_resource: 2 - type: 12810 - host_id: 20 - reserved: 0 - - - start_resource: 4 - num_resource: 2 - type: 12810 - host_id: 22 - reserved: 0 - start_resource: 22 num_resource: 18 @@ -1089,27 +1065,21 @@ rm-cfg: reserved: 0 - start_resource: 12288 - num_resource: 56 + num_resource: 64 type: 12813 host_id: 12 reserved: 0 - - start_resource: 12344 - num_resource: 48 - type: 12813 - host_id: 20 - reserved: 0 - - - start_resource: 12392 - num_resource: 48 + start_resource: 12352 + num_resource: 64 type: 12813 - host_id: 22 + host_id: 38 reserved: 0 - - start_resource: 12440 - num_resource: 64 + start_resource: 12416 + num_resource: 88 type: 12813 - host_id: 38 + host_id: 128 reserved: 0 - start_resource: 1536 diff --git a/board/ti/j722s/tifs-rm-cfg.yaml b/board/ti/j722s/tifs-rm-cfg.yaml index a06af08e58..cb10785865 100644 --- a/board/ti/j722s/tifs-rm-cfg.yaml +++ b/board/ti/j722s/tifs-rm-cfg.yaml @@ -244,7 +244,7 @@ tifs-rm-cfg: subhdr: magic: 0x7B25 size: 8 - resasg_entries_size: 1008 + resasg_entries_size: 976 reserved: 0 resasg_entries: - @@ -457,18 +457,6 @@ tifs-rm-cfg: type: 1802 host_id: 12 reserved: 0 - - - start_resource: 28 - num_resource: 6 - type: 1802 - host_id: 20 - reserved: 0 - - - start_resource: 34 - num_resource: 6 - type: 1802 - host_id: 22 - reserved: 0 - start_resource: 44 num_resource: 36 @@ -481,6 +469,18 @@ tifs-rm-cfg: type: 1802 host_id: 36 reserved: 0 + - + start_resource: 84 + num_resource: 16 + type: 1802 + host_id: 20 + reserved: 0 + - + start_resource: 100 + num_resource: 16 + type: 1802 + host_id: 22 + reserved: 0 - start_resource: 154 num_resource: 14 @@ -897,22 +897,16 @@ tifs-rm-cfg: reserved: 0 - start_resource: 8 - num_resource: 4 + num_resource: 12 type: 12750 host_id: 12 reserved: 0 - - start_resource: 12 + start_resource: 20 num_resource: 20 type: 12750 host_id: 38 reserved: 0 - - - start_resource: 32 - num_resource: 8 - type: 12750 - host_id: 128 - reserved: 0 - start_resource: 0 num_resource: 8 @@ -921,22 +915,16 @@ tifs-rm-cfg: reserved: 0 - start_resource: 0 - num_resource: 4 + num_resource: 12 type: 12769 host_id: 12 reserved: 0 - - start_resource: 4 + start_resource: 12 num_resource: 20 type: 12769 host_id: 38 reserved: 0 - - - start_resource: 24 - num_resource: 8 - type: 12769 - host_id: 128 - reserved: 0 - start_resource: 0 num_resource: 8 @@ -945,22 +933,10 @@ tifs-rm-cfg: reserved: 0 - start_resource: 0 - num_resource: 2 + num_resource: 8 type: 12810 host_id: 12 reserved: 0 - - - start_resource: 2 - num_resource: 2 - type: 12810 - host_id: 20 - reserved: 0 - - - start_resource: 4 - num_resource: 2 - type: 12810 - host_id: 22 - reserved: 0 - start_resource: 22 num_resource: 18 -- cgit v1.2.3 From ea7f8cf62031b16bd7485e1aae48ae9b75d2a6f6 Mon Sep 17 00:00:00 2001 From: Georgi Vlaev Date: Wed, 14 Feb 2024 16:27:44 +0530 Subject: ram: k3-ddrss: Use the DDR controller BIST engine for ECC priming The 1-bit inline ECC support in TI's DDRSS bridge requires the configured memory regions to be preloaded with a pattern before use. This is done by the k3-ddrss driver from the R5 SPL in a 'for' loop. It takes around 10 seconds to fill 2GB of memory, for example. Memset can cut the time in half and using DMA currently yields a similar result. The BIST engine of DDR controller provides support for initializing any memory region with a pattern. This bypasses the DDRSS bridge, so the required inline ECC data is not computed and populated in the memory. For some values like zero, the computed ECC syndrome is also zero and we can use these values to preload the memory from the DDR controller, without the assistance of the bridge. The registers involved in the process are described in the 'DDR controller registers' topic in [1] AM62 and [2] J721E reference manuals. The patch replaces the 'for' loop memory fill function with the BIST memory initialization procedure. This cuts the time to preload the 2GB memory from 10 seconds down to 1 second. The bist preload function uses the lpddr4 APIs in the k3-ddrss, so this is compatible with devices with both 16-bit LPDDR4 and 32-bit LPDDR4 interfaces (e.g J721E). [1] AM62x: https://www.ti.com/lit/pdf/spruiv7 [2] DRA829/TDA4VM: https://www.ti.com/lit/zip/spruil1 Signed-off-by: Georgi Vlaev Signed-off-by: Santhosh Kumar K Reviewed-by: Neha Malcom Francis --- drivers/ram/k3-ddrss/k3-ddrss.c | 122 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 114 insertions(+), 8 deletions(-) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 28129d52a6..b6ff73e74e 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -557,14 +558,118 @@ static void k3_ddrss_set_ecc_range_r0(u32 base, u32 start_address, u32 size) writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG); } -static void k3_ddrss_preload_ecc_mem_region(u32 *addr, u32 size, u32 word) +#define BIST_MODE_MEM_INIT 4 +#define BIST_MEM_INIT_TIMEOUT 10000 /* 1msec loops per block = 10s */ +static void k3_lpddr4_bist_init_mem_region(struct k3_ddrss_desc *ddrss, + u64 addr, u64 size, + u32 pattern) { - int i; + lpddr4_obj *driverdt = ddrss->driverdt; + lpddr4_privatedata *pd = &ddrss->pd; + u32 status, offset, regval; + bool int_status; + int i = 0; + + /* Set BIST_START_ADDR_0 [31:0] */ + regval = (u32)(addr & TH_FLD_MASK(LPDDR4__BIST_START_ADDRESS_0__FLD)); + TH_OFFSET_FROM_REG(LPDDR4__BIST_START_ADDRESS_0__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set BIST_START_ADDR_1 [32 or 34:32] */ + regval = (u32)(addr >> TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_0__FLD)); + regval &= TH_FLD_MASK(LPDDR4__BIST_START_ADDRESS_1__FLD); + TH_OFFSET_FROM_REG(LPDDR4__BIST_START_ADDRESS_1__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set ADDR_SPACE = log2(size) */ + regval = (u32)(ilog2(size) << TH_FLD_SHIFT(LPDDR4__ADDR_SPACE__FLD)); + TH_OFFSET_FROM_REG(LPDDR4__ADDR_SPACE__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Enable the BIST data check. On 32bit lpddr4 (e.g J7) this shares a + * register with ADDR_SPACE and BIST_GO. + */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_CHECK__REG, CTL_SHIFT, offset); + driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); + regval |= TH_FLD_MASK(LPDDR4__BIST_DATA_CHECK__FLD); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + /* Clear the address check bit */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_ADDR_CHECK__REG, CTL_SHIFT, offset); + driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); + regval &= ~TH_FLD_MASK(LPDDR4__BIST_ADDR_CHECK__FLD); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set BIST_TEST_MODE[2:0] to memory initialize (4) */ + regval = BIST_MODE_MEM_INIT; + TH_OFFSET_FROM_REG(LPDDR4__BIST_TEST_MODE__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set BIST_DATA_PATTERN[31:0] */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_PATTERN_0__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, pattern); + + /* Set BIST_DATA_PATTERN[63:32] */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_PATTERN_1__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, pattern); + + udelay(1000); + + /* Enable the programmed BIST operation - BIST_GO = 1 */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_GO__REG, CTL_SHIFT, offset); + driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); + regval |= TH_FLD_MASK(LPDDR4__BIST_GO__FLD); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Wait for the BIST_DONE interrupt */ + while (i < BIST_MEM_INIT_TIMEOUT) { + status = driverdt->checkctlinterrupt(pd, LPDDR4_INTR_BIST_DONE, + &int_status); + if (!status & int_status) { + /* Clear LPDDR4_INTR_BIST_DONE */ + driverdt->ackctlinterrupt(pd, LPDDR4_INTR_BIST_DONE); + break; + } + udelay(1000); + i++; + } - printf("ECC is enabled, priming DDR which will take several seconds.\n"); + /* Before continuing we have to stop BIST - BIST_GO = 0 */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_GO__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, 0); + + /* Timeout hit while priming the memory. We can't continue, + * since the memory is not fully initialized and we most + * likely get an uncorrectable error exception while booting. + */ + if (i == BIST_MEM_INIT_TIMEOUT) { + printf("ERROR: Timeout while priming the memory.\n"); + hang(); + } +} - for (i = 0; i < (size / 4); i++) - addr[i] = word; +static void k3_ddrss_lpddr4_preload_full_mem(struct k3_ddrss_desc *ddrss, + u64 total_size, u32 pattern) +{ + u32 done, max_size2; + + /* Get the max size (log2) supported in this config (16/32 lpddr4) + * from the start_addess width - 16bit: 8G, 32bit: 32G + */ + max_size2 = TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_0__FLD) + + TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_1__FLD) + 1; + + /* ECC is enabled in dt but we can't preload the memory if + * the memory configuration is recognized and supported. + */ + if (!total_size || total_size > (1ull << max_size2) || + total_size & (total_size - 1)) { + printf("ECC: the memory configuration is not supported\n"); + hang(); + } + printf("ECC is enabled, priming DDR which will take several seconds.\n"); + done = get_timer(0); + k3_lpddr4_bist_init_mem_region(ddrss, 0, total_size, pattern); + printf("ECC: priming DDR completed in %lu msec\n", get_timer(done)); } static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) @@ -592,9 +697,10 @@ static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN | DDRSS_ECC_CTRL_REG_WR_ALLOC, base + DDRSS_ECC_CTRL_REG); - /* Preload ECC Mem region with 0's */ - k3_ddrss_preload_ecc_mem_region((u32 *)ecc_region_start, ecc_range, - 0x00000000); + /* Preload the full memory with 0's using the BIST engine of + * the LPDDR4 controller. + */ + k3_ddrss_lpddr4_preload_full_mem(ddrss, gd->ram_size, 0); /* Clear Error Count Register */ writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG); -- cgit v1.2.3 From de74380cb2a8c2a42df7575d51873f1aaccb22a6 Mon Sep 17 00:00:00 2001 From: Santhosh Kumar K Date: Wed, 14 Feb 2024 16:27:45 +0530 Subject: ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve 'calculations restricted to 32 bits' issue As R5 is a 32 bit processor, the RAM banks' base and size calculation is restricted to 32 bits, which results in wrong values if bank's base is greater than 32 bits or bank's size is greater than or equal to 4GB. So, add k3_ddrss_ddr_bank_base_size_calc() to get the base address and size of RAM's banks from the device tree memory node, and store in a 64 bit device private data which can be used for ECC reserved memory calculation, Setting ECC range and Fixing up bank size in device tree when ECC is enabled. Signed-off-by: Santhosh Kumar K Reviewed-by: Neha Malcom Francis --- drivers/ram/k3-ddrss/k3-ddrss.c | 72 ++++++++++++++++++++++++++++++++--------- 1 file changed, 57 insertions(+), 15 deletions(-) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index b6ff73e74e..c6a62785bd 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -148,6 +148,9 @@ struct k3_ddrss_desc { struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REGIONS]; u64 ecc_reserved_space; bool ti_ecc_enabled; + unsigned long long ddr_bank_base[CONFIG_NR_DRAM_BANKS]; + unsigned long long ddr_bank_size[CONFIG_NR_DRAM_BANKS]; + unsigned long long ddr_ram_size; }; struct reginitdata { @@ -672,11 +675,54 @@ static void k3_ddrss_lpddr4_preload_full_mem(struct k3_ddrss_desc *ddrss, printf("ECC: priming DDR completed in %lu msec\n", get_timer(done)); } +static void k3_ddrss_ddr_bank_base_size_calc(struct k3_ddrss_desc *ddrss) +{ + int bank, na, ns, len, parent; + const fdt32_t *ptr, *end; + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + ddrss->ddr_bank_base[bank] = 0; + ddrss->ddr_bank_size[bank] = 0; + } + + ofnode mem = ofnode_null(); + + do { + mem = ofnode_by_prop_value(mem, "device_type", "memory", 7); + } while (!ofnode_is_enabled(mem)); + + const void *fdt = ofnode_to_fdt(mem); + int node = ofnode_to_offset(mem); + const char *property = "reg"; + + parent = fdt_parent_offset(fdt, node); + na = fdt_address_cells(fdt, parent); + ns = fdt_size_cells(fdt, parent); + ptr = fdt_getprop(fdt, node, property, &len); + end = ptr + len / sizeof(*ptr); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + if (ptr + na + ns <= end) { + if (CONFIG_IS_ENABLED(OF_TRANSLATE)) + ddrss->ddr_bank_base[bank] = fdt_translate_address(fdt, node, ptr); + else + ddrss->ddr_bank_base[bank] = fdtdec_get_number(ptr, na); + + ddrss->ddr_bank_size[bank] = fdtdec_get_number(&ptr[na], ns); + } + + ptr += na + ns; + } + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) + ddrss->ddr_ram_size += ddrss->ddr_bank_size[bank]; +} + static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) { fdtdec_setup_mem_size_base_lowest(); - ddrss->ecc_reserved_space = gd->ram_size; + ddrss->ecc_reserved_space = ddrss->ddr_ram_size; do_div(ddrss->ecc_reserved_space, 9); /* Round to clean number */ @@ -700,7 +746,7 @@ static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) /* Preload the full memory with 0's using the BIST engine of * the LPDDR4 controller. */ - k3_ddrss_lpddr4_preload_full_mem(ddrss, gd->ram_size, 0); + k3_ddrss_lpddr4_preload_full_mem(ddrss, ddrss->ddr_ram_size, 0); /* Clear Error Count Register */ writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG); @@ -745,6 +791,8 @@ static int k3_ddrss_probe(struct udevice *dev) k3_lpddr4_start(ddrss); + k3_ddrss_ddr_bank_base_size_calc(ddrss); + if (ddrss->ti_ecc_enabled) { if (!ddrss->ddrss_ss_cfg) { printf("%s: ss_cfg is required if ecc is enabled but not provided.", @@ -765,27 +813,21 @@ static int k3_ddrss_probe(struct udevice *dev) int k3_ddrss_ddr_fdt_fixup(struct udevice *dev, void *blob, struct bd_info *bd) { - struct k3_ddrss_desc *ddrss = dev_get_priv(dev); - u64 start[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; int bank; + struct k3_ddrss_desc *ddrss = dev_get_priv(dev); for (bank = CONFIG_NR_DRAM_BANKS - 1; bank >= 0; bank--) { - if (ddrss->ecc_reserved_space > bd->bi_dram[bank].size) { - ddrss->ecc_reserved_space -= bd->bi_dram[bank].size; - bd->bi_dram[bank].size = 0; + if (ddrss->ecc_reserved_space > ddrss->ddr_bank_size[bank]) { + ddrss->ecc_reserved_space -= ddrss->ddr_bank_size[bank]; + ddrss->ddr_bank_size[bank] = 0; } else { - bd->bi_dram[bank].size -= ddrss->ecc_reserved_space; + ddrss->ddr_bank_size[bank] -= ddrss->ecc_reserved_space; break; } } - for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = bd->bi_dram[bank].start; - size[bank] = bd->bi_dram[bank].size; - } - - return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); + return fdt_fixup_memory_banks(blob, ddrss->ddr_bank_base, + ddrss->ddr_bank_size, CONFIG_NR_DRAM_BANKS); } static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info) -- cgit v1.2.3 From 11c7e63f4e94d133dccb42e895ad8babc1b12335 Mon Sep 17 00:00:00 2001 From: Santhosh Kumar K Date: Wed, 14 Feb 2024 16:27:46 +0530 Subject: ram: k3-ddrss: Setup ECC region start and range Setup the ECC region's start and range using the device private data, ddrss->ddr_bank_base[0] and ddrss->ddr_ram_size. Also, move start and range of ECC regions from 32 bits to 64 bits to accommodate for DDR greater than or equal to 4GB. Signed-off-by: Santhosh Kumar K Reviewed-by: Neha Malcom Francis --- drivers/ram/k3-ddrss/k3-ddrss.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index c6a62785bd..b34f645396 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -122,8 +122,8 @@ struct k3_msmc { #define K3_DDRSS_MAX_ECC_REGIONS 3 struct k3_ddrss_ecc_region { - u32 start; - u32 range; + u64 start; + u64 range; }; struct k3_ddrss_desc { @@ -555,7 +555,7 @@ void k3_lpddr4_start(struct k3_ddrss_desc *ddrss) } } -static void k3_ddrss_set_ecc_range_r0(u32 base, u32 start_address, u32 size) +static void k3_ddrss_set_ecc_range_r0(u32 base, u64 start_address, u64 size) { writel((start_address) >> 16, base + DDRSS_ECC_R0_STR_ADDR_REG); writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG); @@ -731,13 +731,13 @@ static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) { - u32 ecc_region_start = ddrss->ecc_regions[0].start; - u32 ecc_range = ddrss->ecc_regions[0].range; + u64 ecc_region_start = ddrss->ecc_regions[0].start; + u64 ecc_range = ddrss->ecc_regions[0].range; u32 base = (u32)ddrss->ddrss_ss_cfg; u32 val; /* Only Program region 0 which covers full ddr space */ - k3_ddrss_set_ecc_range_r0(base, ecc_region_start - gd->ram_base, ecc_range); + k3_ddrss_set_ecc_range_r0(base, ecc_region_start - ddrss->ddr_bank_base[0], ecc_range); /* Enable ECC, RMW, WR_ALLOC */ writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN | @@ -803,8 +803,8 @@ static int k3_ddrss_probe(struct udevice *dev) k3_ddrss_lpddr4_ecc_calc_reserved_mem(ddrss); /* Always configure one region that covers full DDR space */ - ddrss->ecc_regions[0].start = gd->ram_base; - ddrss->ecc_regions[0].range = gd->ram_size - ddrss->ecc_reserved_space; + ddrss->ecc_regions[0].start = ddrss->ddr_bank_base[0]; + ddrss->ecc_regions[0].range = ddrss->ddr_ram_size - ddrss->ecc_reserved_space; k3_ddrss_lpddr4_ecc_init(ddrss); } -- cgit v1.2.3 From b907add57a8d1ac28289100c02fc23535118b4d4 Mon Sep 17 00:00:00 2001 From: Santhosh Kumar K Date: Wed, 14 Feb 2024 16:27:47 +0530 Subject: ram: k3-ddrss: Enable ECC interrupts Enable ECC 1-bit error, 2-bit error, multiple 1-bit error interrupts by setting the respective bits in the DDRSS_V2A_INT_SET_REG register. Signed-off-by: Santhosh Kumar K --- drivers/ram/k3-ddrss/k3-ddrss.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index b34f645396..a7a0b8bca9 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -46,6 +46,11 @@ #define DDRSS_ECC_R2_STR_ADDR_REG 0x0140 #define DDRSS_ECC_R2_END_ADDR_REG 0x0144 #define DDRSS_ECC_1B_ERR_CNT_REG 0x0150 +#define DDRSS_V2A_INT_SET_REG 0x00a8 + +#define DDRSS_V2A_INT_SET_REG_ECC1BERR_EN BIT(3) +#define DDRSS_V2A_INT_SET_REG_ECC2BERR_EN BIT(4) +#define DDRSS_V2A_INT_SET_REG_ECCM1BERR_EN BIT(5) #define SINGLE_DDR_SUBSYSTEM 0x1 #define MULTI_DDR_SUBSYSTEM 0x2 @@ -751,6 +756,9 @@ static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) /* Clear Error Count Register */ writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG); + writel(DDRSS_V2A_INT_SET_REG_ECC1BERR_EN | DDRSS_V2A_INT_SET_REG_ECC2BERR_EN | + DDRSS_V2A_INT_SET_REG_ECCM1BERR_EN, base + DDRSS_V2A_INT_SET_REG); + /* Enable ECC Check */ val = readl(base + DDRSS_ECC_CTRL_REG); val |= DDRSS_ECC_CTRL_REG_ECC_CK; -- cgit v1.2.3 From 44c3e47fd1dc87817068260309a2277cb82ffa48 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Wed, 14 Feb 2024 16:27:48 +0530 Subject: drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECC Add CONFIG_K3_INLINE_ECC so that ECC functions can be compiled into R5 SPL only when the config has been enabled. Signed-off-by: Neha Malcom Francis --- drivers/ram/Kconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 49ba10e57e..62e6dfcb76 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -107,6 +107,17 @@ config IMXRT_SDRAM to support external memories like sdram, psram & nand. This driver is for the sdram memory interface with the SEMC. +config K3_INLINE_ECC + bool "Enable TI Inline ECC support" + depends on K3_DDRSS + default n + help + Enable Inline ECC support on K3 platforms. 1/9th of the SDRAM space + is used for ECC storage and the rest 8/9th is available for system + use. Enabling ECC increases boot time as the ECC protected regions + need to be primed with a predefined value prior to enabling ECC + check. + source "drivers/ram/aspeed/Kconfig" source "drivers/ram/rockchip/Kconfig" source "drivers/ram/sifive/Kconfig" -- cgit v1.2.3 From 860caf570e5394003c64447d0cc50875db850cb2 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Wed, 14 Feb 2024 16:27:49 +0530 Subject: arm: dts: k3-*: Add memory node at R5 stage Add the bootph-pre-ram property to the memory node so that it can be accessed by FDT functions at R5 stage. The fdt_setup_mem*() functions require the memory node to be able to initialize and set the size of the DRAM banks. For this purpose, make sure all memory nodes are present and standardized, and add them if not. Also make sure they have bootph-pre-ram property so that it can be accessible at R5 SPL stage. Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-am654-base-board.dts | 1 + arch/arm/dts/k3-am654-r5-base-board.dts | 8 ++++++++ arch/arm/dts/k3-am68-sk-som.dtsi | 5 +++-- arch/arm/dts/k3-am69-r5-sk.dts | 5 +++-- arch/arm/dts/k3-am69-sk.dts | 5 +++-- arch/arm/dts/k3-j7200-som-p0.dtsi | 5 +++-- arch/arm/dts/k3-j721e-r5-sk.dts | 1 + arch/arm/dts/k3-j721e-sk.dts | 1 + arch/arm/dts/k3-j721e-som-p0.dtsi | 1 + arch/arm/dts/k3-j721s2-som-p0.dtsi | 5 +++-- arch/arm/dts/k3-j784s4-evm.dts | 5 +++-- 11 files changed, 30 insertions(+), 12 deletions(-) diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts index 7bc8b0d5b6..999b65e7be 100644 --- a/arch/arm/dts/k3-am654-base-board.dts +++ b/arch/arm/dts/k3-am654-base-board.dts @@ -23,6 +23,7 @@ /* 4G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>, <0x00000008 0x80000000 0x00000000 0x80000000>; + bootph-pre-ram; }; reserved-memory { diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index 7671875a55..671b30b219 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -24,6 +24,14 @@ tick-timer = &timer1; }; + memory@80000000 { + device_type = "memory"; + /* 4G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + bootph-pre-ram; + }; + aliases { remoteproc0 = &sysctrler; remoteproc1 = &a53_0; diff --git a/arch/arm/dts/k3-am68-sk-som.dtsi b/arch/arm/dts/k3-am68-sk-som.dtsi index a3036f9c69..e7b45694fa 100644 --- a/arch/arm/dts/k3-am68-sk-som.dtsi +++ b/arch/arm/dts/k3-am68-sk-som.dtsi @@ -12,8 +12,9 @@ memory@80000000 { device_type = "memory"; /* 16 GB RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x03 0x80000000>; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000003 0x80000000>; + bootph-pre-ram; }; /* Reserving memory regions still pending */ diff --git a/arch/arm/dts/k3-am69-r5-sk.dts b/arch/arm/dts/k3-am69-r5-sk.dts index b9e8036f20..166ab203e4 100644 --- a/arch/arm/dts/k3-am69-r5-sk.dts +++ b/arch/arm/dts/k3-am69-r5-sk.dts @@ -30,8 +30,9 @@ memory@80000000 { device_type = "memory"; /* 32G RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x07 0x80000000>; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000007 0x80000000>; + bootph-pre-ram; }; a72_0: a72@0 { diff --git a/arch/arm/dts/k3-am69-sk.dts b/arch/arm/dts/k3-am69-sk.dts index 212e746e08..508fbee411 100644 --- a/arch/arm/dts/k3-am69-sk.dts +++ b/arch/arm/dts/k3-am69-sk.dts @@ -31,8 +31,9 @@ memory@80000000 { device_type = "memory"; /* 32G RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x07 0x80000000>; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000007 0x80000000>; + bootph-pre-ram; }; reserved_memory: reserved-memory { diff --git a/arch/arm/dts/k3-j7200-som-p0.dtsi b/arch/arm/dts/k3-j7200-som-p0.dtsi index 73a7d5266c..91e78d99a4 100644 --- a/arch/arm/dts/k3-j7200-som-p0.dtsi +++ b/arch/arm/dts/k3-j7200-som-p0.dtsi @@ -11,8 +11,9 @@ memory@80000000 { device_type = "memory"; /* 4G RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x00 0x80000000>; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + bootph-pre-ram; }; reserved_memory: reserved-memory { diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts index 89344a4b24..74cb1b13e0 100644 --- a/arch/arm/dts/k3-j721e-r5-sk.dts +++ b/arch/arm/dts/k3-j721e-r5-sk.dts @@ -27,6 +27,7 @@ /* 4G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>, <0x00000008 0x80000000 0x00000000 0x80000000>; + bootph-pre-ram; }; reserved_memory: reserved-memory { diff --git a/arch/arm/dts/k3-j721e-sk.dts b/arch/arm/dts/k3-j721e-sk.dts index 847ff73431..34b762cd0e 100644 --- a/arch/arm/dts/k3-j721e-sk.dts +++ b/arch/arm/dts/k3-j721e-sk.dts @@ -24,6 +24,7 @@ /* 4G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>, <0x00000008 0x80000000 0x00000000 0x80000000>; + bootph-pre-ram; }; reserved_memory: reserved-memory { diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e-som-p0.dtsi index 45e0f322f9..e0950fb3a5 100644 --- a/arch/arm/dts/k3-j721e-som-p0.dtsi +++ b/arch/arm/dts/k3-j721e-som-p0.dtsi @@ -13,6 +13,7 @@ /* 4G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>, <0x00000008 0x80000000 0x00000000 0x80000000>; + bootph-pre-ram; }; reserved_memory: reserved-memory { diff --git a/arch/arm/dts/k3-j721s2-som-p0.dtsi b/arch/arm/dts/k3-j721s2-som-p0.dtsi index 11d620a78c..570c0442ba 100644 --- a/arch/arm/dts/k3-j721s2-som-p0.dtsi +++ b/arch/arm/dts/k3-j721s2-som-p0.dtsi @@ -12,8 +12,9 @@ memory@80000000 { device_type = "memory"; /* 16 GB RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x03 0x80000000>; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000003 0x80000000>; + bootph-pre-ram; }; reserved_memory: reserved-memory { diff --git a/arch/arm/dts/k3-j784s4-evm.dts b/arch/arm/dts/k3-j784s4-evm.dts index 19e4bf72c9..e936a82002 100644 --- a/arch/arm/dts/k3-j784s4-evm.dts +++ b/arch/arm/dts/k3-j784s4-evm.dts @@ -29,8 +29,9 @@ memory@80000000 { device_type = "memory"; /* 32G RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x07 0x80000000>; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000007 0x80000000>; + bootph-pre-ram; }; reserved_memory: reserved-memory { -- cgit v1.2.3 From 410888e38c7eb9b5e10e3461019d933546e3c2bd Mon Sep 17 00:00:00 2001 From: Santhosh Kumar K Date: Wed, 14 Feb 2024 16:27:50 +0530 Subject: board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled As there are few redundant functions in board/ti/*/evm.c files, pull them to a common location of access to reuse and include the common file to access the functions. Call k3-ddrss driver through fixup_ddr_driver_for_ecc() to fixup the device tree and resize the available amount of DDR, if ECC is enabled. Otherwise, fixup the device tree using the regular fdt_fixup_memory_banks(). Modify fixup_ddr_driver_for_ecc() to make the function agnostic to the number of DDR controllers present. Signed-off-by: Santhosh Kumar K Signed-off-by: Neha Malcom Francis --- board/ti/am62ax/evm.c | 15 ++++---- board/ti/am62px/evm.c | 15 ++++---- board/ti/am62x/evm.c | 61 +++--------------------------- board/ti/am64x/evm.c | 71 +++-------------------------------- board/ti/am65x/evm.c | 29 +-------------- board/ti/common/Makefile | 1 + board/ti/common/k3-ddr-init.c | 86 +++++++++++++++++++++++++++++++++++++++++++ board/ti/common/k3-ddr-init.h | 15 ++++++++ board/ti/j721e/evm.c | 29 +-------------- board/ti/j721s2/evm.c | 31 ++-------------- board/ti/j722s/evm.c | 11 +----- board/ti/j784s4/evm.c | 31 ++-------------- 12 files changed, 137 insertions(+), 258 deletions(-) create mode 100644 board/ti/common/k3-ddr-init.c create mode 100644 board/ti/common/k3-ddr-init.h diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c index 71fbc9e9c2..de5a193c63 100644 --- a/board/ti/am62ax/evm.c +++ b/board/ti/am62ax/evm.c @@ -16,6 +16,7 @@ #include #include "../common/rtc.c" +#include "../common/k3-ddr-init.h" #define CTRLMMR_USB0_PHY_CTRL 0x43004008 #define CTRLMMR_USB1_PHY_CTRL 0x43004018 @@ -29,15 +30,15 @@ int board_init(void) return 0; } -int dram_init(void) +#if defined(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) { - return fdtdec_setup_mem_size_base(); -} - -int dram_init_banksize(void) -{ - return fdtdec_setup_memory_banksize(); + if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) + fixup_ddr_driver_for_ecc(spl_image); + else + fixup_memory_node(spl_image); } +#endif #if defined(CONFIG_SPL_BOARD_INIT) void spl_board_init(void) diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c index 23716ed99a..341bc48ba8 100644 --- a/board/ti/am62px/evm.c +++ b/board/ti/am62px/evm.c @@ -17,6 +17,7 @@ #include #include "../common/rtc.c" +#include "../common/k3-ddr-init.h" #if CONFIG_IS_ENABLED(SPLASH_SCREEN) static struct splash_location default_splash_locations[] = { @@ -49,17 +50,15 @@ int board_init(void) return 0; } -int dram_init(void) -{ - return fdtdec_setup_mem_size_base(); -} - -int dram_init_banksize(void) +#if defined(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) { - return fdtdec_setup_memory_banksize(); + if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) + fixup_ddr_driver_for_ecc(spl_image); + else + fixup_memory_node(spl_image); } -#if defined(CONFIG_SPL_BUILD) static int video_setup(void) { if (CONFIG_IS_ENABLED(VIDEO)) { diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index d84c85b122..fb74f5967f 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -29,6 +29,8 @@ #include "../common/rtc.c" +#include "../common/k3-ddr-init.h" + DECLARE_GLOBAL_DATA_PTR; #define AM62X_MAX_DAUGHTER_CARDS 8 @@ -84,16 +86,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - return fdtdec_setup_mem_size_base(); -} - -int dram_init_banksize(void) -{ - return fdtdec_setup_memory_banksize(); -} - phys_size_t get_effective_memsize(void) { /* @@ -151,53 +143,12 @@ void spl_board_init(void) dram_init_banksize(); } -#if defined(CONFIG_K3_AM64_DDRSS) -static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image) -{ - struct udevice *dev; - int ret; - - dram_init_banksize(); - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) - panic("Cannot get RAM device for ddr size fixup: %d\n", ret); - - ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd); - if (ret) - printf("Error fixing up ddr node for ECC use! %d\n", ret); -} -#else -static void fixup_memory_node(struct spl_image_info *spl_image) -{ - u64 start[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - int bank; - int ret; - - dram_init(); - dram_init_banksize(); - - for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; - } - - /* dram_init functions use SPL fdt, and we must fixup u-boot fdt */ - ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, - CONFIG_NR_DRAM_BANKS); - if (ret) - printf("Error fixing up memory node! %d\n", ret); -} -#endif - void spl_perform_fixups(struct spl_image_info *spl_image) { -#if defined(CONFIG_K3_AM64_DDRSS) - fixup_ddr_driver_for_ecc(spl_image); -#else - fixup_memory_node(spl_image); -#endif + if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) + fixup_ddr_driver_for_ecc(spl_image); + else + fixup_memory_node(spl_image); } #endif diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index c42afa581b..e990ba0d43 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -20,6 +20,7 @@ #include #include "../common/board_detect.h" +#include "../common/k3-ddr-init.h" #define board_is_am64x_gpevm() (board_ti_k3_is("AM64-GPEVM") || \ board_ti_k3_is("AM64-EVM") || \ @@ -50,28 +51,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - s32 ret; - - ret = fdtdec_setup_mem_size_base(); - if (ret) - printf("Error setting up mem size and base. %d\n", ret); - - return ret; -} - -int dram_init_banksize(void) -{ - s32 ret; - - ret = fdtdec_setup_memory_banksize(); - if (ret) - printf("Error setting up memory banksize. %d\n", ret); - - return ret; -} - static bool is_nand; #if defined(CONFIG_SPL_LOAD_FIT) int board_fit_config_name_match(const char *name) @@ -122,52 +101,12 @@ static int fixup_usb_boot(const void *fdt_blob) } #endif -#if defined(CONFIG_K3_AM64_DDRSS) -static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image) -{ - struct udevice *dev; - int ret; - - dram_init_banksize(); - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) - panic("Cannot get RAM device for ddr size fixup: %d\n", ret); - - ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd); - if (ret) - printf("Error fixing up ddr node for ECC use! %d\n", ret); -} -#else -static void fixup_memory_node(struct spl_image_info *spl_image) -{ - u64 start[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - int bank; - int ret; - - dram_init(); - dram_init_banksize(); - - for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; - } - - /* dram_init functions use SPL fdt, and we must fixup u-boot fdt */ - ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, CONFIG_NR_DRAM_BANKS); - if (ret) - printf("Error fixing up memory node! %d\n", ret); -} -#endif - void spl_perform_fixups(struct spl_image_info *spl_image) { -#if defined(CONFIG_K3_AM64_DDRSS) - fixup_ddr_driver_for_ecc(spl_image); -#else - fixup_memory_node(spl_image); -#endif + if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) + fixup_ddr_driver_for_ecc(spl_image); + else + fixup_memory_node(spl_image); #if CONFIG_IS_ENABLED(USB_STORAGE) fixup_usb_boot(spl_image->fdt_addr); diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index b266ccb4b8..5743bb4f4d 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -24,6 +24,7 @@ #include #include "../common/board_detect.h" +#include "../common/k3-ddr-init.h" #define board_is_am65x_base_board() board_ti_is("AM6-COMPROCEVM") @@ -50,17 +51,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ -#ifdef CONFIG_PHYS_64BIT - gd->ram_size = 0x100000000; -#else - gd->ram_size = 0x80000000; -#endif - - return 0; -} - phys_size_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT @@ -72,23 +62,6 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) return gd->ram_top; } -int dram_init_banksize(void) -{ - /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; - gd->ram_size = 0x80000000; - -#ifdef CONFIG_PHYS_64BIT - /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; - gd->bd->bi_dram[1].size = 0x80000000; - gd->ram_size = 0x100000000; -#endif - - return 0; -} - #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/board/ti/common/Makefile b/board/ti/common/Makefile index 515d8c2e8d..1c1a6a237c 100644 --- a/board/ti/common/Makefile +++ b/board/ti/common/Makefile @@ -4,3 +4,4 @@ obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o obj-${CONFIG_CMD_EXTENSION} += cape_detect.o obj-$(CONFIG_SET_DFU_ALT_INFO) += k3_dfu.o +obj-${CONFIG_ARCH_K3} += k3-ddr-init.o diff --git a/board/ti/common/k3-ddr-init.c b/board/ti/common/k3-ddr-init.c new file mode 100644 index 0000000000..2e0b7ed860 --- /dev/null +++ b/board/ti/common/k3-ddr-init.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include + +#include "k3-ddr-init.h" + +int dram_init(void) +{ + s32 ret; + + ret = fdtdec_setup_mem_size_base_lowest(); + if (ret) + printf("Error setting up mem size and base. %d\n", ret); + + return ret; +} + +int dram_init_banksize(void) +{ + s32 ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + printf("Error setting up memory banksize. %d\n", ret); + + return ret; +} + +#if defined(CONFIG_SPL_BUILD) + +void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image) +{ + struct udevice *dev; + int ret, ctr = 1; + + dram_init_banksize(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("Cannnot get RAM device for ddr size fixup: %d\n", ret); + + ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd); + if (ret) + printf("Error fixing up ddr node for ECC use! %d\n", ret); + + ret = uclass_next_device_err(&dev); + + while (ret && ret != -ENODEV) { + ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd); + if (ret) + printf("Error fixing up ddr node %d for ECC use! %d\n", ctr, ret); + + ret = uclass_next_device_err(&dev); + ctr++; + } +} + +void fixup_memory_node(struct spl_image_info *spl_image) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int bank; + int ret; + + dram_init(); + dram_init_banksize(); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start[bank] = gd->bd->bi_dram[bank].start; + size[bank] = gd->bd->bi_dram[bank].size; + } + + ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, + CONFIG_NR_DRAM_BANKS); + + if (ret) + printf("Error fixing up memory node! %d\n", ret); +} + +#endif diff --git a/board/ti/common/k3-ddr-init.h b/board/ti/common/k3-ddr-init.h new file mode 100644 index 0000000000..9d1826815d --- /dev/null +++ b/board/ti/common/k3-ddr-init.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023, Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef __K3_DDR_INIT_H +#define __K3_DDR_INIT_H + +int dram_init(void); +int dram_init_banksize(void); + +void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image); +void fixup_memory_node(struct spl_image_info *spl_image); + +#endif /* __K3_DDR_INIT_H */ diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index d0077cebc4..313c1cb034 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -26,6 +26,7 @@ #include #include "../common/board_detect.h" +#include "../common/k3-ddr-init.h" #define board_is_bboneai_64_b0() (board_ti_k3_is("BBONEAI-64-B0-")) @@ -48,17 +49,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ -#ifdef CONFIG_PHYS_64BIT - gd->ram_size = 0x100000000; -#else - gd->ram_size = 0x80000000; -#endif - - return 0; -} - phys_size_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT @@ -70,23 +60,6 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) return gd->ram_top; } -int dram_init_banksize(void) -{ - /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; - gd->ram_size = 0x80000000; - -#ifdef CONFIG_PHYS_64BIT - /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; - gd->bd->bi_dram[1].size = 0x80000000; - gd->ram_size = 0x100000000; -#endif - - return 0; -} - #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index eea2c256b3..3847587961 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -26,6 +26,7 @@ #include #include "../common/board_detect.h" +#include "../common/k3-ddr-init.h" DECLARE_GLOBAL_DATA_PTR; @@ -34,17 +35,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ -#ifdef CONFIG_PHYS_64BIT - gd->ram_size = 0x100000000; -#else - gd->ram_size = 0x80000000; -#endif - - return 0; -} - phys_size_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT @@ -56,23 +46,6 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) return gd->ram_top; } -int dram_init_banksize(void) -{ - /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x7fffffff; - gd->ram_size = 0x80000000; - -#ifdef CONFIG_PHYS_64BIT - /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; - gd->bd->bi_dram[1].size = 0x37fffffff; - gd->ram_size = 0x400000000; -#endif - - return 0; -} - /* Enables the spi-nand dts node, if onboard mux is set to spinand */ static void __maybe_unused detect_enable_spinand(void *blob) { @@ -108,6 +81,8 @@ static void __maybe_unused detect_enable_spinand(void *blob) void spl_perform_fixups(struct spl_image_info *spl_image) { detect_enable_spinand(spl_image->fdt_addr); + if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) + fixup_ddr_driver_for_ecc(spl_image); } #endif diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c index aa273e3dd4..8469467b7d 100644 --- a/board/ti/j722s/evm.c +++ b/board/ti/j722s/evm.c @@ -15,6 +15,7 @@ #include #include "../common/board_detect.h" +#include "../common/k3-ddr-init.h" #ifdef CONFIG_TI_I2C_BOARD_DETECT /* @@ -59,13 +60,3 @@ int board_init(void) { return 0; } - -int dram_init(void) -{ - return fdtdec_setup_mem_size_base(); -} - -int dram_init_banksize(void) -{ - return fdtdec_setup_memory_banksize(); -} diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c index 8f8cb4f1cf..7e7f4a5593 100644 --- a/board/ti/j784s4/evm.c +++ b/board/ti/j784s4/evm.c @@ -25,6 +25,7 @@ #include #include "../common/board_detect.h" +#include "../common/k3-ddr-init.h" DECLARE_GLOBAL_DATA_PTR; @@ -33,17 +34,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ -#ifdef CONFIG_PHYS_64BIT - gd->ram_size = 0x100000000; -#else - gd->ram_size = 0x80000000; -#endif - - return 0; -} - phys_size_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT @@ -55,23 +45,6 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) return gd->ram_top; } -int dram_init_banksize(void) -{ - /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x7fffffff; - gd->ram_size = 0x80000000; - -#ifdef CONFIG_PHYS_64BIT - /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; - gd->bd->bi_dram[1].size = 0x77fffffff; - gd->ram_size = 0x800000000; -#endif - - return 0; -} - /* Enables the spi-nand dts node, if onboard mux is set to spinand */ static void __maybe_unused detect_enable_spinand(void *blob) { @@ -107,6 +80,8 @@ static void __maybe_unused detect_enable_spinand(void *blob) void spl_perform_fixups(struct spl_image_info *spl_image) { detect_enable_spinand(spl_image->fdt_addr); + if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) + fixup_ddr_driver_for_ecc(spl_image); } #endif -- cgit v1.2.3 From e99e0373f8cce25c9fd1cdd6fafaca92b2605389 Mon Sep 17 00:00:00 2001 From: Santhosh Kumar K Date: Wed, 14 Feb 2024 16:27:51 +0530 Subject: arm: dts: k3-*-ddr: Add ss_cfg reg entry Add ss_cfg memory region which maps the DDRSS configuration region for the memory controller node. Signed-off-by: Santhosh Kumar K Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-am62a-ddr.dtsi | 7 ++++--- arch/arm/dts/k3-j721s2-ddr.dtsi | 12 ++++++++---- arch/arm/dts/k3-j784s4-ddr.dtsi | 24 ++++++++++++++++-------- 3 files changed, 28 insertions(+), 15 deletions(-) diff --git a/arch/arm/dts/k3-am62a-ddr.dtsi b/arch/arm/dts/k3-am62a-ddr.dtsi index 8629ea45b8..42e41f7850 100644 --- a/arch/arm/dts/k3-am62a-ddr.dtsi +++ b/arch/arm/dts/k3-am62a-ddr.dtsi @@ -4,11 +4,12 @@ */ / { - memorycontroller: memory-controller@f308000 { + memorycontroller: memory-controller@f300000 { compatible = "ti,am62a-ddrss"; reg = <0x00 0x0f308000 0x00 0x4000>, - <0x00 0x43014000 0x00 0x100>; - reg-names = "cfg", "ctrl_mmr_lp4"; + <0x00 0x43014000 0x00 0x100>, + <0x00 0x0f300000 0x00 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; ti,ddr-freq1 = ; ti,ddr-freq2 = ; ti,ddr-fhs-cnt = ; diff --git a/arch/arm/dts/k3-j721s2-ddr.dtsi b/arch/arm/dts/k3-j721s2-ddr.dtsi index 345e2b84f9..9764085163 100644 --- a/arch/arm/dts/k3-j721s2-ddr.dtsi +++ b/arch/arm/dts/k3-j721s2-ddr.dtsi @@ -5,6 +5,8 @@ &main_navss { ranges = <0x00 0x00114000 0x00 0x00114000 0x00 0x00000100>, // ctrl_mmr_lpr + <0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0 + <0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1 <0x00 0x02990000 0x00 0x02990000 0x00 0x00004000>, // ddr0 cfg <0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; @@ -24,8 +26,9 @@ memorycontroller0: memorycontroller@2990000 { compatible = "ti,j721s2-ddrss"; reg = <0x0 0x02990000 0x0 0x4000>, - <0x0 0x0114000 0x0 0x100>; - reg-names = "cfg", "ctrl_mmr_lp4"; + <0x0 0x0114000 0x0 0x100>, + <0x0 0x02980000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>, <&k3_pds 96 TI_SCI_PD_SHARED>; clocks = <&k3_clks 138 0>, <&k3_clks 43 2>; @@ -2232,8 +2235,9 @@ memorycontroller1: memorycontroller@29b0000 { compatible = "ti,j721s2-ddrss"; reg = <0x0 0x029b0000 0x0 0x4000>, - <0x0 0x0114000 0x0 0x100>; - reg-names = "cfg", "ctrl_mmr_lp4"; + <0x0 0x0114000 0x0 0x100>, + <0x0 0x029a0000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; power-domains = <&k3_pds 139 TI_SCI_PD_SHARED>, <&k3_pds 97 TI_SCI_PD_SHARED>; clocks = <&k3_clks 139 0>, <&k3_clks 43 2>; diff --git a/arch/arm/dts/k3-j784s4-ddr.dtsi b/arch/arm/dts/k3-j784s4-ddr.dtsi index 45aeac082b..ba5eb2d7a1 100644 --- a/arch/arm/dts/k3-j784s4-ddr.dtsi +++ b/arch/arm/dts/k3-j784s4-ddr.dtsi @@ -9,6 +9,10 @@ <0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg <0x00 0x029d0000 0x00 0x029d0000 0x00 0x00004000>, // ddr2 cfg <0x00 0x029f0000 0x00 0x029f0000 0x00 0x00004000>, // ddr3 cfg + <0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0 + <0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1 + <0x00 0x029c0000 0x00 0x029c0000 0x00 0x00000200>, // ss cfg 2 + <0x00 0x029e0000 0x00 0x029e0000 0x00 0x00000200>, // ss cfg 3 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; msmc0: msmc { @@ -26,8 +30,9 @@ memorycontroller0: memorycontroller@2990000 { compatible = "ti,j721s2-ddrss"; reg = <0x0 0x02990000 0x0 0x4000>, - <0x0 0x0114000 0x0 0x100>; - reg-names = "cfg", "ctrl_mmr_lp4"; + <0x0 0x0114000 0x0 0x100>, + <0x0 0x02980000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>, <&k3_pds 131 TI_SCI_PD_SHARED>; clocks = <&k3_clks 191 1>, <&k3_clks 78 2>; @@ -2234,8 +2239,9 @@ memorycontroller1: memorycontroller@29b0000 { compatible = "ti,j721s2-ddrss"; reg = <0x0 0x029b0000 0x0 0x4000>, - <0x0 0x0114000 0x0 0x100>; - reg-names = "cfg", "ctrl_mmr_lp4"; + <0x0 0x0114000 0x0 0x100>, + <0x0 0x029a0000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>, <&k3_pds 132 TI_SCI_PD_SHARED>; clocks = <&k3_clks 192 1>, <&k3_clks 78 2>; @@ -4442,8 +4448,9 @@ memorycontroller2: memorycontroller@29d0000 { compatible = "ti,j721s2-ddrss"; reg = <0x0 0x029d0000 0x0 0x4000>, - <0x0 0x0114000 0x0 0x100>; - reg-names = "cfg", "ctrl_mmr_lp4"; + <0x0 0x0114000 0x0 0x100>, + <0x0 0x029c0000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>, <&k3_pds 133 TI_SCI_PD_SHARED>; clocks = <&k3_clks 193 1>, <&k3_clks 78 2>; @@ -6650,8 +6657,9 @@ memorycontroller3: memorycontroller@29f0000 { compatible = "ti,j721s2-ddrss"; reg = <0x0 0x029f0000 0x0 0x4000>, - <0x0 0x0114000 0x0 0x100>; - reg-names = "cfg", "ctrl_mmr_lp4"; + <0x0 0x0114000 0x0 0x100>, + <0x0 0x29e0000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>, <&k3_pds 139 TI_SCI_PD_SHARED>; clocks = <&k3_clks 194 1>, <&k3_clks 78 2>; -- cgit v1.2.3 From af5609db6d1124e046cf623f80e00c3d27ff5fec Mon Sep 17 00:00:00 2001 From: Georgi Vlaev Date: Wed, 14 Feb 2024 16:27:52 +0530 Subject: cmd: ti: Add DDRSS ECC test command Introduce a new version of the Keystone-II "ddr" command for testing the inline ECC support in the DDRSS bridge available on K3 devices. The ECC hardware support in K3's DDRSS and the test method differ substantially from what we support in the K2 variant of the command. The name of the new command is "ddrss". The ECC test procedure follows these steps: 1) Flush and disable the data cache. 2) Shrink the protected ECC R0 range. 3) Flip a bit outside the shrunk range. 4) Restore the range to original. 5) Read the modified value (corrected). 6) Re-enable the data cache. This which will cause the 1-bit ECC error count to increase while the read will return the corrected value. The K3 version of the command preserves the syntax for the "ecc_err" argument. Signed-off-by: Georgi Vlaev Signed-off-by: Santhosh Kumar K --- cmd/ti/Kconfig | 7 ++ cmd/ti/Makefile | 1 + cmd/ti/ddrss.c | 241 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 249 insertions(+) create mode 100644 cmd/ti/ddrss.c diff --git a/cmd/ti/Kconfig b/cmd/ti/Kconfig index db557445a8..34ebd266c3 100644 --- a/cmd/ti/Kconfig +++ b/cmd/ti/Kconfig @@ -7,6 +7,13 @@ config CMD_DDR3 supports memory verification, memory comapre and ecc verification if supported. +config CMD_DDRSS + bool "command for verifying DDRSS ECC features" + help + Support for testing DDRSS on TI platforms. This command + supports memory verification, memory compare and ecc + verification if supported. + config CMD_PD bool "command for verifying power domains" depends on TI_POWER_DOMAIN diff --git a/cmd/ti/Makefile b/cmd/ti/Makefile index 045593396b..5443cc9fd3 100644 --- a/cmd/ti/Makefile +++ b/cmd/ti/Makefile @@ -5,5 +5,6 @@ obj- += dummy.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_DDR3) += ddr3.o +obj-$(CONFIG_CMD_DDRSS) += ddrss.o obj-$(CONFIG_CMD_PD) += pd.o endif diff --git a/cmd/ti/ddrss.c b/cmd/ti/ddrss.c new file mode 100644 index 0000000000..be1ecc50b7 --- /dev/null +++ b/cmd/ti/ddrss.c @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * DDRSS: DDR 1-bit inline ECC test command + * + * Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define K3_DDRSS_MAX_ECC_REGIONS 3 + +#define DDRSS_BASE 0x0f300000 +#define DDRSS_V2A_CTL_REG 0x0020 +#define DDRSS_V2A_INT_RAW_REG 0x00a0 +#define DDRSS_V2A_INT_STAT_REG 0x00a4 +#define DDRSS_V2A_INT_ECC1BERR BIT(3) +#define DDRSS_V2A_INT_ECC2BERR BIT(4) +#define DDRSS_V2A_INT_ECCM1BERR BIT(5) +#define DDRSS_ECC_CTRL_REG 0x0120 +#define DDRSS_ECC_CTRL_REG_ECC_EN BIT(0) +#define DDRSS_ECC_CTRL_REG_RMW_EN BIT(1) +#define DDRSS_ECC_CTRL_REG_ECC_CK BIT(2) +#define DDRSS_ECC_CTRL_REG_WR_ALLOC BIT(4) +#define DDRSS_ECC_R0_STR_ADDR_REG 0x0130 +#define DDRSS_ECC_Rx_STR_ADDR_REG(x) (0x0130 + ((x) * 8)) +#define DDRSS_ECC_Rx_END_ADDR_REG(x) (0x0134 + ((x) * 8)) +#define DDRSS_ECC_1B_ERR_CNT_REG 0x0150 +#define DDRSS_ECC_1B_ERR_THRSH_REG 0x0154 +#define DDRSS_ECC_1B_ERR_ADR_REG 0x0158 +#define DDRSS_ECC_1B_ERR_MSK_LOG_REG 0x015c + +static inline u32 ddrss_read(u32 reg) +{ + return readl((unsigned long)(DDRSS_BASE + reg)); +} + +static inline void ddrss_write(u32 value, u32 reg) +{ + writel(value, (unsigned long)(DDRSS_BASE + reg)); +} + +/* ddrss_check_ecc_status() + * Report the ECC state after test. Check/clear the interrupt + * status register, dump the ECC err counters and ECC error offset. + */ +static void ddrss_check_ecc_status(void) +{ + u32 ecc_1b_err_cnt, v2a_int_raw, ecc_1b_err_msk; + phys_addr_t ecc_1b_err_adr; + + v2a_int_raw = ddrss_read(DDRSS_V2A_INT_RAW_REG); + + /* 1-bit correctable */ + if (v2a_int_raw & DDRSS_V2A_INT_ECC1BERR) { + puts("\tECC test: DDR ECC 1-bit error\n"); + + /* Dump the 1-bit counter and reset it, as we want a + * new interrupt to be generated when above the error + * threshold + */ + ecc_1b_err_cnt = ddrss_read(DDRSS_ECC_1B_ERR_CNT_REG); + if (ecc_1b_err_cnt) { + printf("\tECC test: 1-bit ECC err count: %u\n", + ecc_1b_err_cnt & 0xffff); + ddrss_write(1, DDRSS_ECC_1B_ERR_CNT_REG); + } + + /* ECC fault addresses are also recorded in a 2-word deep + * FIFO. Calculate and report the 8-byte range of the error + */ + ecc_1b_err_adr = ddrss_read(DDRSS_ECC_1B_ERR_ADR_REG); + ecc_1b_err_msk = ddrss_read(DDRSS_ECC_1B_ERR_MSK_LOG_REG); + if (ecc_1b_err_msk) { + if ((IS_ENABLED(CONFIG_SOC_K3_AM642)) || + (IS_ENABLED(CONFIG_SOC_K3_AM625))) { + /* AM64/AM62: + * The address of the ecc error is 16-byte aligned. + * Each bit in 4 bit mask represents 8 bytes ECC quanta + * that has the 1-bit error + */ + ecc_1b_err_msk &= 0xf; + ecc_1b_err_adr <<= 4; + ecc_1b_err_adr += (fls(ecc_1b_err_msk) - 1) * 8; + } + if ((IS_ENABLED(CONFIG_SOC_K3_AM62A7)) || + (IS_ENABLED(CONFIG_SOC_K3_AM62P5))) { + /* AM62A/AM62P: + * The address of the ecc error is 32-byte aligned. + * Each bit in 8 bit mask represents 8 bytes ECC quanta + * that has the 1-bit error + */ + ecc_1b_err_msk &= 0xff; + ecc_1b_err_adr <<= 5; + ecc_1b_err_adr += (fls(ecc_1b_err_msk) - 1) * 8; + } + + printf("\tECC test: 1-bit error in [0x%llx:0x%llx]\n", + ecc_1b_err_adr, ecc_1b_err_adr + 8); + /* Pop the top of the addr/mask FIFOs */ + ddrss_write(1, DDRSS_ECC_1B_ERR_ADR_REG); + ddrss_write(1, DDRSS_ECC_1B_ERR_MSK_LOG_REG); + } + ddrss_write(DDRSS_V2A_INT_ECC1BERR, DDRSS_V2A_INT_STAT_REG); + } + + /* 2-bit uncorrectable */ + if (v2a_int_raw & DDRSS_V2A_INT_ECC2BERR) { + puts("\tECC test: DDR ECC 2-bit error\n"); + ddrss_write(DDRSS_V2A_INT_ECC2BERR, DDRSS_V2A_INT_STAT_REG); + } + + /* multiple 1-bit errors (uncorrectable) in multpile words */ + if (v2a_int_raw & DDRSS_V2A_INT_ECCM1BERR) { + puts("\tECC test: DDR ECC multi 1-bit errors\n"); + ddrss_write(DDRSS_V2A_INT_ECCM1BERR, DDRSS_V2A_INT_STAT_REG); + } +} + +/* ddrss_memory_ecc_err() + * Simulate an ECC error - change a 32b word at address in an ECC enabled + * range. This removes the tested address from the ECC checks, changes a + * word, and then restores the ECC range as configured by k3_ddrss in R5 SPL. + */ +static int ddrss_memory_ecc_err(u64 addr, u64 ecc_err, int range) +{ + u64 ecc_start_addr, ecc_end_addr, ecc_temp_addr; + u64 val1, val2, val3; + + /* Flush and disable dcache */ + flush_dcache_all(); + dcache_disable(); + + /* Setup a threshold for 1-bit errors to generate interrupt */ + ddrss_write(1, DDRSS_ECC_1B_ERR_THRSH_REG); + + puts("Testing DDR ECC:\n"); + /* Get the Rx range configuration */ + ecc_start_addr = ddrss_read(DDRSS_ECC_Rx_STR_ADDR_REG(range)); + ecc_end_addr = ddrss_read(DDRSS_ECC_Rx_END_ADDR_REG(range)); + + /* Calculate the end of the Rx ECC region up to the tested address */ + ecc_temp_addr = (addr - gd->ram_base) >> 16; + if (ecc_temp_addr) + ecc_temp_addr--; + puts("\tECC test: Disabling DDR ECC ...\n"); + /* Set the new range */ + ddrss_write(ecc_temp_addr, DDRSS_ECC_Rx_END_ADDR_REG(range)); + /* ECC is still on in a single block. The range is disabled if start > end */ + if (ecc_temp_addr == ecc_start_addr) + ddrss_write(ecc_temp_addr + 1, DDRSS_ECC_Rx_STR_ADDR_REG(range)); + + /* Flip some bits, one bit preferably, but let's allow more */ + addr &= ~3; + val1 = readl((unsigned long long)addr); + val2 = val1 ^ ecc_err; + writel(val2, (unsigned long long)addr); + val3 = readl((unsigned long long)addr); + + /* Re-enable the ECC checks for the R0 region */ + ddrss_write(ecc_end_addr, DDRSS_ECC_Rx_END_ADDR_REG(range)); + ddrss_write(ecc_start_addr, DDRSS_ECC_Rx_STR_ADDR_REG(range)); + /* Make sure the ECC range is restored before doing anything else */ + mb(); + + printf("\tECC test: addr 0x%llx, read data 0x%llx, written data 0x%llx, " + "err pattern: 0x%llx, read after write data 0x%llx\n", + addr, val1, val2, ecc_err, val3); + + puts("\tECC test: Enabled DDR ECC ...\n"); + /* Read again from the address. This creates an ECC 1-bit error + * condition, and returns the corrected value + */ + val1 = readl((unsigned long long)addr); + printf("\tECC test: addr 0x%llx, read data 0x%llx\n", addr, val1); + + /* Set threshold for 1-bit errors to 0 to disable the interrupt */ + ddrss_write(0, DDRSS_ECC_1B_ERR_THRSH_REG); + /* Report the ECC status */ + ddrss_check_ecc_status(); + + dcache_enable(); + + return 0; +} + +/* ddrss_is_ecc_enabled() + * Report if ECC is enabled. + */ +static int ddrss_is_ecc_enabled(void) +{ + u32 ecc_ctrl = ddrss_read(DDRSS_ECC_CTRL_REG); + + /* Assume ECC is enabled only if all bits set by k3_ddrss are set */ + return (ecc_ctrl & (DDRSS_ECC_CTRL_REG_ECC_EN | + DDRSS_ECC_CTRL_REG_RMW_EN | + DDRSS_ECC_CTRL_REG_WR_ALLOC | + DDRSS_ECC_CTRL_REG_ECC_CK)); +} + +static int do_ddrss_test(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + u64 start_addr, ecc_err; + + if (!(argc == 4 && (strncmp(argv[1], "ecc_err", 8) == 0))) + return cmd_usage(cmdtp); + + if (!ddrss_is_ecc_enabled()) { + puts("ECC not enabled. Please enable ECC any try again\n"); + return CMD_RET_FAILURE; + } + + start_addr = simple_strtoul(argv[2], NULL, 16); + ecc_err = simple_strtoul(argv[3], NULL, 16); + + if (!((start_addr >= gd->bd->bi_dram[0].start && + (start_addr <= (gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - 1))) || + (start_addr >= gd->bd->bi_dram[1].start && + (start_addr <= (gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size - 1))))) { + puts("Address is not in the DDR range\n"); + return CMD_RET_FAILURE; + } + + ddrss_memory_ecc_err(start_addr, ecc_err, 0); + return 0; +} + +U_BOOT_CMD(ddrss, 5, 1, do_ddrss_test, + "DDRSS test", + "ecc_err - generate bit errors\n" + " in DDR data at , the command will read a 32-bit data\n" + " from , and write (data ^ bit_err) back to \n" +); -- cgit v1.2.3 From c759775f48ee22812e311b56a16bc6a45dbb87f5 Mon Sep 17 00:00:00 2001 From: Santhosh Kumar K Date: Wed, 14 Feb 2024 16:27:53 +0530 Subject: configs: am6*_a53: Enable 'ddrss' ECC test command Enable CONFIG_TI_COMMON_CMD_OPTIONS and CONFIG_CMD_DDRSS to use the 'ddrss' command for testing ECC. Signed-off-by: Santhosh Kumar K --- configs/am62ax_evm_a53_defconfig | 2 ++ configs/am62px_evm_a53_defconfig | 2 ++ configs/am62x_evm_a53_defconfig | 2 ++ configs/am62x_lpsk_a53_defconfig | 2 ++ configs/am64x_evm_a53_defconfig | 2 ++ 5 files changed, 10 insertions(+) diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig index 45bbffada4..5442796a82 100644 --- a/configs/am62ax_evm_a53_defconfig +++ b/configs/am62ax_evm_a53_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y CONFIG_TI_SECURE_DEVICE=y +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_GPIO=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_BOARD_HAS_32K_RTC_CRYSTAL=y @@ -57,6 +58,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_MMC=y CONFIG_CMD_CLK=y +CONFIG_CMD_DDRSS=y CONFIG_CMD_DFU=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig index 3c739d7ac8..4dc85af7f9 100644 --- a/configs/am62px_evm_a53_defconfig +++ b/configs/am62px_evm_a53_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y CONFIG_TI_SECURE_DEVICE=y +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_BOARD_HAS_32K_RTC_CRYSTAL=y CONFIG_SPL_GPIO=y @@ -69,6 +70,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SPL_BMP=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_CLK=y +CONFIG_CMD_DDRSS=y CONFIG_CMD_DFU=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index 9774efed73..4478d362f4 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y CONFIG_TI_SECURE_DEVICE=y +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_TI_I2C_BOARD_DETECT=y CONFIG_SPL_GPIO=y @@ -72,6 +73,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SPL_BMP=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_CLK=y +CONFIG_CMD_DDRSS=y CONFIG_CMD_DFU=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/am62x_lpsk_a53_defconfig b/configs/am62x_lpsk_a53_defconfig index c30fa1cbae..652327b3fe 100644 --- a/configs/am62x_lpsk_a53_defconfig +++ b/configs/am62x_lpsk_a53_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y CONFIG_SYS_K3_SPL_ATF=y CONFIG_TI_SECURE_DEVICE=y +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_TI_I2C_BOARD_DETECT=y CONFIG_SPL_GPIO=y @@ -76,6 +77,7 @@ CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_CLK=y +CONFIG_CMD_DDRSS=y CONFIG_CMD_DFU=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index f86d31110c..a6cccd06a4 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_K3=y CONFIG_TI_SECURE_DEVICE=y +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -68,6 +69,7 @@ CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_ASKENV=y +CONFIG_CMD_DDRSS=y CONFIG_CMD_DFU=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y -- cgit v1.2.3 From 18a3c5117fff296e4f4f7486c2d3007a31067b1e Mon Sep 17 00:00:00 2001 From: Santhosh Kumar K Date: Wed, 14 Feb 2024 16:27:54 +0530 Subject: arm: dts: k3-am62a: Add ESM nodes Add Main ESM and MCU ESM nodes to the AM62A device tree. Signed-off-by: Santhosh Kumar K --- arch/arm/dts/k3-am62a7-r5-sk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts index 5f1bd32a75..3c63b99f17 100644 --- a/arch/arm/dts/k3-am62a7-r5-sk.dts +++ b/arch/arm/dts/k3-am62a7-r5-sk.dts @@ -81,6 +81,15 @@ ti,secure-host; }; +&cbass_mcu { + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x4100000 0x0 0x1000>; + ti,esm-pins = <0>, <1>, <2>, <85>; + bootph-pre-ram; + }; +}; + &cbass_main { sa3_secproxy: secproxy@44880000 { compatible = "ti,am654-secure-proxy"; @@ -100,6 +109,13 @@ mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; }; + + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x420000 0x0 0x1000>; + ti,esm-pins = <69>, <160>, <161>, <162>, <163>, <177>, <178>; + bootph-pre-ram; + }; }; &mcu_pmx0 { -- cgit v1.2.3 From 12a2039cb9c7eb836d12f012eaf545df2aa1c4cc Mon Sep 17 00:00:00 2001 From: Santhosh Kumar K Date: Wed, 14 Feb 2024 16:27:55 +0530 Subject: arm: dts: k3-am62p: Remove 'reserved' status Remove 'reserved' status for MCU ESM node in AM62P device tree Signed-off-by: Santhosh Kumar K --- arch/arm/dts/k3-am62p-mcu.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/k3-am62p-mcu.dtsi b/arch/arm/dts/k3-am62p-mcu.dtsi index 14eb9ba836..512a4e1750 100644 --- a/arch/arm/dts/k3-am62p-mcu.dtsi +++ b/arch/arm/dts/k3-am62p-mcu.dtsi @@ -18,7 +18,6 @@ compatible = "ti,j721e-esm"; reg = <0x00 0x4100000 0x00 0x1000>; ti,esm-pins = <0>, <1>, <2>, <85>; - status = "reserved"; bootph-pre-ram; }; -- cgit v1.2.3 From 6f8bf697f9a6203917ff346e68b17cb2efe2f47a Mon Sep 17 00:00:00 2001 From: Santhosh Kumar K Date: Wed, 14 Feb 2024 16:27:56 +0530 Subject: arm: mach-k3: am62*_init: Probe ESM nodes On AM62A and AM62P devices, it is possible to route Main ESM error events to MCU ESM. MCU ESM high error output can trigger the reset logic to reset the device. So, for these devices we have Main ESM and MCU ESM nodes in the device tree. Add functions to probe these nodes if CONFIG_ESM_K3 is enabled. Signed-off-by: Santhosh Kumar K --- arch/arm/mach-k3/am62a7_init.c | 26 ++++++++++++++++++++++++++ arch/arm/mach-k3/am62p5_init.c | 26 ++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c index 5a96683c53..b3efe9c36e 100644 --- a/arch/arm/mach-k3/am62a7_init.c +++ b/arch/arm/mach-k3/am62a7_init.c @@ -14,6 +14,9 @@ #include #include +#define CTRLMMR_MCU_RST_CTRL 0x04518170 +#define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK 0xFFFDFFFF + struct fwl_data cbass_main_fwls[] = { { "FSS_DAT_REG3", 7, 8 }, }; @@ -83,6 +86,15 @@ static void setup_qos(void) } #endif +static __maybe_unused void enable_mcu_esm_reset(void) +{ + /* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */ + u32 stat = readl(CTRLMMR_MCU_RST_CTRL); + + stat &= RST_CTRL_ESM_ERROR_RST_EN_Z_MASK; + writel(stat, CTRLMMR_MCU_RST_CTRL); +} + void board_init_f(ulong dummy) { struct udevice *dev; @@ -175,6 +187,20 @@ void board_init_f(ulong dummy) /* Disable ROM configured firewalls right after loading sysfw */ remove_fwl_configs(cbass_main_fwls, ARRAY_SIZE(cbass_main_fwls)); + if (IS_ENABLED(CONFIG_ESM_K3)) { + /* Probe/configure ESM0 */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev); + if (ret) + printf("esm main init failed: %d\n", ret); + + /* Probe/configure MCUESM */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev); + if (ret) + printf("esm mcu init failed: %d\n", ret); + + enable_mcu_esm_reset(); + } + #if defined(CONFIG_K3_AM62A_DDRSS) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) diff --git a/arch/arm/mach-k3/am62p5_init.c b/arch/arm/mach-k3/am62p5_init.c index 19ddefc3e9..08ad6cfee1 100644 --- a/arch/arm/mach-k3/am62p5_init.c +++ b/arch/arm/mach-k3/am62p5_init.c @@ -14,6 +14,9 @@ #include #include +#define CTRLMMR_MCU_RST_CTRL 0x04518170 +#define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK 0xFFFDFFFF + struct fwl_data cbass_main_fwls[] = { { "FSS_DAT_REG3", 7, 8 }, }; @@ -66,6 +69,15 @@ static void ctrl_mmr_unlock(void) mmr_unlock(PADCFG_MMR1_BASE, 1); } +static __maybe_unused void enable_mcu_esm_reset(void) +{ + /* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */ + u32 stat = readl(CTRLMMR_MCU_RST_CTRL); + + stat &= RST_CTRL_ESM_ERROR_RST_EN_Z_MASK; + writel(stat, CTRLMMR_MCU_RST_CTRL); +} + void board_init_f(ulong dummy) { struct udevice *dev; @@ -153,6 +165,20 @@ void board_init_f(ulong dummy) /* Disable ROM configured firewalls right after loading sysfw */ remove_fwl_configs(cbass_main_fwls, ARRAY_SIZE(cbass_main_fwls)); + if (IS_ENABLED(CONFIG_ESM_K3)) { + /* Probe/configure ESM0 */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev); + if (ret) + printf("esm main init failed: %d\n", ret); + + /* Probe/configure MCUESM */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev); + if (ret) + printf("esm mcu init failed: %d\n", ret); + + enable_mcu_esm_reset(); + } + #if defined(CONFIG_K3_AM62A_DDRSS) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) -- cgit v1.2.3 From fab3a043af23eb62254fc16e970d41cda1f0e9c5 Mon Sep 17 00:00:00 2001 From: Santhosh Kumar K Date: Wed, 14 Feb 2024 16:27:57 +0530 Subject: configs: am62*_evm_r5: Enable ESM and MISC configs Enable CONFIG_SPL_DRIVERS_MISC, CONFIG_SPL_MISC, CONFIG_ESM_K3 to probe the Main ESM and MCU ESM nodes. Signed-off-by: Santhosh Kumar K --- configs/am62ax_evm_r5_defconfig | 3 +++ configs/am62px_evm_r5_defconfig | 3 +++ 2 files changed, 6 insertions(+) diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig index b92fea415a..156d5a1880 100644 --- a/configs/am62ax_evm_r5_defconfig +++ b/configs/am62ax_evm_r5_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_TEXT_BASE=0x43c00000 CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7145 CONFIG_SPL_SIZE_LIMIT=0x3A7F0 @@ -93,6 +94,8 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y +CONFIG_SPL_MISC=y +CONFIG_ESM_K3=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig index 25505167f0..e31f06402f 100644 --- a/configs/am62px_evm_r5_defconfig +++ b/configs/am62px_evm_r5_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_TEXT_BASE=0x43c00000 CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_SIZE_LIMIT=0x3C000 @@ -98,6 +99,8 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y +CONFIG_SPL_MISC=y +CONFIG_ESM_K3=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y -- cgit v1.2.3 From 0d08c733ec146bf07210932687349cec378136d6 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Mon, 12 Feb 2024 14:42:58 +0530 Subject: arm: dts: k3-j784s4-r5 Add AVS and TPS62873 node Add AVS and Tulip TPS62873 regulator node. Signed-off-by: Keerthy --- arch/arm/dts/k3-j784s4-r5-evm.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts index c38deb49a4..269f227f33 100644 --- a/arch/arm/dts/k3-j784s4-r5-evm.dts +++ b/arch/arm/dts/k3-j784s4-r5-evm.dts @@ -95,6 +95,15 @@ <&mcu_secproxy 23>; bootph-pre-ram; }; + + wkup_vtm0: vtm@42040000 { + compatible = "ti,j721s2-avs"; + reg = <0x0 0x42040000 0x0 0x350>, + <0x0 0x42050000 0x0 0x350>, + <0x0 0x43000300 0x0 0x10>; + power-domains = <&k3_pds 243 TI_SCI_PD_SHARED>; + #thermal-sensor-cells = <1>; + }; }; &main_pmx0 { @@ -243,4 +252,20 @@ bootph-pre-ram; }; }; + + tps62873: tps62873@40 { + compatible = "ti,tps6287x"; + bootph-pre-ram; + reg = <0x40>; + regulator-name = "VDD_CPU_AVS"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1330000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&wkup_vtm0 { + vdd-supply-2 = <&tps62873>; + bootph-pre-ram; }; -- cgit v1.2.3 From aca5ba4b387b6d793177e4da9f79c63797510286 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Mon, 12 Feb 2024 14:42:59 +0530 Subject: arm: mach-k3: j784s4_init: Enable AVS Enable probing of AVS node in R5 SPL. Signed-off-by: Keerthy Reviewed-by: Dhruva Gole --- arch/arm/mach-k3/j784s4_init.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-k3/j784s4_init.c b/arch/arm/mach-k3/j784s4_init.c index 5854e645bc..af0f46e2ab 100644 --- a/arch/arm/mach-k3/j784s4_init.c +++ b/arch/arm/mach-k3/j784s4_init.c @@ -215,6 +215,13 @@ void board_init_f(ulong dummy) /* Output System Firmware version info */ k3_sysfw_print_ver(); + if (IS_ENABLED(CONFIG_K3_AVS0)) { + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs), + &dev); + if (ret) + pr_err("AVS init failed: %d\n", ret); + } + if (IS_ENABLED(CONFIG_TARGET_J784S4_R5_EVM)) { ret = uclass_get_device_by_name(UCLASS_MISC, "msmc", &dev); if (ret) -- cgit v1.2.3 From 50ad6313bd4b910ec11b7bbdc4ca5d6b62397428 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Mon, 12 Feb 2024 14:43:00 +0530 Subject: power: regulator: tps6287x: Add driver for TPS6287x step down convertors Add driver for TPS6287x step down convertors Signed-off-by: Keerthy Reviewed-by: Kamlesh Gurudasani --- drivers/power/regulator/Kconfig | 18 +++ drivers/power/regulator/Makefile | 1 + drivers/power/regulator/tps6287x_regulator.c | 173 +++++++++++++++++++++++++++ 3 files changed, 192 insertions(+) create mode 100644 drivers/power/regulator/tps6287x_regulator.c diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index c346d03507..3893f8d7e0 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -340,6 +340,15 @@ config DM_REGULATOR_TPS62360 implements the get/set api for value only, as the power line is always on. +config DM_REGULATOR_TPS6287X + bool "Enable driver for TPS6287x Power Regulator" + depends on DM_REGULATOR + help + The TPS6287X is a step down converter with a fast transient + response. This driver supports all four variants of the chip + (TPS62870, TPS62871, TPS62872, TPS62873). It implements the + get/set api for value only, as the power line is always on. + config DM_REGULATOR_STPMIC1 bool "Enable driver for STPMIC1 regulators" depends on DM_REGULATOR && PMIC_STPMIC1 @@ -359,6 +368,15 @@ config DM_REGULATOR_ANATOP regulators. It is recommended that this option be enabled on i.MX6 platform. +config SPL_DM_REGULATOR_TPS6287X + bool "Enable driver for TPS6287x Power Regulator" + depends on SPL_DM_REGULATOR + help + The TPS6287X is a step down converter with a fast transient + response. This driver supports all four variants of the chip + (TPS62870, TPS62871, TPS62872, TPS62873). It implements the + get/set api for value only, as the power line is always on. + config SPL_DM_REGULATOR_STPMIC1 bool "Enable driver for STPMIC1 regulators in SPL" depends on SPL_DM_REGULATOR && PMIC_STPMIC1 diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index 2d97e1033a..2bf63474f9 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o obj-$(CONFIG_DM_REGULATOR_TPS62360) += tps62360_regulator.o +obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS6287X) += tps6287x_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_STPMIC1) += stpmic1.o obj-$(CONFIG_DM_REGULATOR_TPS65941) += tps65941_regulator.o obj-$(CONFIG_DM_REGULATOR_SCMI) += scmi_regulator.o diff --git a/drivers/power/regulator/tps6287x_regulator.c b/drivers/power/regulator/tps6287x_regulator.c new file mode 100644 index 0000000000..5c3828c4cf --- /dev/null +++ b/drivers/power/regulator/tps6287x_regulator.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + * Keerthy + */ + +#include +#include +#include +#include +#include + +#define TPS6287X_REG_VSET 0x0 +#define TPS6287X_REG_CONTROL1 0x1 +#define TPS6287X_REG_CONTROL2 0x2 +#define TPS6287X_REG_CONTROL3 0x3 +#define TPS6287X_REG_STATUS 0x4 +#define TPS6287X_REG_VSET_VSET_MASK 0xff +#define TPS6287X_REG_CONTROL2_VRANGE_MASK 0xc + +struct tps6287x_regulator_config { + u32 vmin; + u32 vmax; +}; + +struct tps6287x_regulator_pdata { + u8 vsel_offset; + struct udevice *i2c; + struct tps6287x_regulator_config *config; +}; + +static struct tps6287x_regulator_config tps6287x_data = { + .vmin = 400000, + .vmax = 3350000, +}; + +static int tps6287x_regulator_set_value(struct udevice *dev, int uV) +{ + struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev); + u8 regval, vset; + int ret; + + if (uV < pdata->config->vmin || uV > pdata->config->vmax) + return -EINVAL; + /* + * Based on the value of VRANGE bit field of CONTROL2 reg the range + * varies. + */ + ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_CONTROL2, ®val, 1); + if (ret) { + dev_err(dev, "CTRL2 reg read failed: %d\n", ret); + return ret; + } + + regval &= TPS6287X_REG_CONTROL2_VRANGE_MASK; + regval >>= ffs(TPS6287X_REG_CONTROL2_VRANGE_MASK) - 1; + + /* + * VRANGE = 0. Increment step 1250 uV starting with 0 --> 400000 uV + * VRANGE = 1. Increment step 2500 uV starting with 0 --> 400000 uV + * VRANGE = 2. Increment step 5000 uV starting with 0 --> 400000 uV + * VRANGE = 3. Increment step 10000 uV starting with 0 --> 800000 uV + */ + switch (regval) { + case 0: + vset = (uV - 400000) / 1250; + break; + case 1: + vset = (uV - 400000) / 2500; + break; + case 2: + vset = (uV - 400000) / 5000; + break; + case 3: + vset = (uV - 800000) / 10000; + break; + default: + pr_err("%s: invalid regval %d\n", dev->name, regval); + return -EINVAL; + } + + return dm_i2c_write(pdata->i2c, TPS6287X_REG_VSET, &vset, 1); +} + +static int tps6287x_regulator_get_value(struct udevice *dev) +{ + u8 regval, vset; + int uV; + int ret; + struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev); + + /* + * Based on the value of VRANGE bit field of CONTROL2 reg the range + * varies. + */ + ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_CONTROL2, ®val, 1); + if (ret) { + dev_err(dev, "i2c read failed: %d\n", ret); + return ret; + } + + regval &= TPS6287X_REG_CONTROL2_VRANGE_MASK; + regval >>= ffs(TPS6287X_REG_CONTROL2_VRANGE_MASK) - 1; + + ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_VSET, &vset, 1); + if (ret) { + dev_err(dev, "i2c VSET read failed: %d\n", ret); + return ret; + } + + /* + * VRANGE = 0. Increment step 1250 uV starting with 0 --> 400000 uV + * VRANGE = 1. Increment step 2500 uV starting with 0 --> 400000 uV + * VRANGE = 2. Increment step 5000 uV starting with 0 --> 400000 uV + * VRANGE = 3. Increment step 10000 uV starting with 0 --> 800000 uV + */ + switch (regval) { + case 0: + uV = 400000 + vset * 1250; + break; + case 1: + uV = 400000 + vset * 2500; + break; + case 2: + uV = 400000 + vset * 5000; + break; + case 3: + uV = 800000 + vset * 10000; + break; + default: + pr_err("%s: invalid regval %d\n", dev->name, regval); + return -EINVAL; + } + + return uV; +} + +static int tps6287x_regulator_probe(struct udevice *dev) +{ + struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev); + int ret, slave_id; + + pdata->config = (void *)dev_get_driver_data(dev); + + slave_id = devfdt_get_addr_index(dev, 0); + + ret = i2c_get_chip(dev->parent, slave_id, 1, &pdata->i2c); + if (ret) { + dev_err(dev, "i2c dev get failed.\n"); + return ret; + } + + return 0; +} + +static const struct dm_regulator_ops tps6287x_regulator_ops = { + .get_value = tps6287x_regulator_get_value, + .set_value = tps6287x_regulator_set_value, +}; + +static const struct udevice_id tps6287x_regulator_ids[] = { + { .compatible = "ti,tps6287x", .data = (ulong)&tps6287x_data }, + { }, +}; + +U_BOOT_DRIVER(tps6287x_regulator) = { + .name = "tps6287x_regulator", + .id = UCLASS_REGULATOR, + .ops = &tps6287x_regulator_ops, + .of_match = tps6287x_regulator_ids, + .plat_auto = sizeof(struct tps6287x_regulator_pdata), + .probe = tps6287x_regulator_probe, +}; -- cgit v1.2.3 From fcc10ec072d9a55ee7636e023b8a7e6d8a657aa3 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Mon, 12 Feb 2024 14:43:01 +0530 Subject: configs: j784s4_evm_r5_defconfig: Enable AVS and TPS6287X configs Enable AVS and TPS6287X configs Signed-off-by: Keerthy --- configs/j784s4_evm_r5_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index 2cb5be7da5..e892603118 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -40,6 +40,9 @@ CONFIG_SPL_BSS_START_ADDR=0x41c76000 CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR_TPS6287X=y +CONFIG_K3_AVS0=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_TI_I2C_BOARD_DETECT=y CONFIG_SPL_STACK_R=y -- cgit v1.2.3 From fc93dfaf5ed175b5336632e4b2a5064db6521c16 Mon Sep 17 00:00:00 2001 From: Vishal Mahaveer Date: Wed, 14 Feb 2024 10:03:32 -0600 Subject: board: ti: rm-cfg: Update rm-cfg to reflect new resource reservation With the latest TIFS firmware, an additional virtual interrupt and event is reserved for TIFS usage on am62x, am62ax and am62px devices. Update the rm-cfg to reflect this new reservation. Signed-off-by: Vishal Mahaveer --- board/ti/am62ax/rm-cfg.yaml | 8 ++++---- board/ti/am62px/rm-cfg.yaml | 8 ++++---- board/ti/am62x/rm-cfg.yaml | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/board/ti/am62ax/rm-cfg.yaml b/board/ti/am62ax/rm-cfg.yaml index c4380a9e4d..25d71e3147 100644 --- a/board/ti/am62ax/rm-cfg.yaml +++ b/board/ti/am62ax/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for AM62A # @@ -519,13 +519,13 @@ rm-cfg: reserved: 0 - start_resource: 44 - num_resource: 36 + num_resource: 35 type: 1802 host_id: 35 reserved: 0 - start_resource: 44 - num_resource: 36 + num_resource: 35 type: 1802 host_id: 36 reserved: 0 @@ -567,7 +567,7 @@ rm-cfg: reserved: 0 - start_resource: 1038 - num_resource: 498 + num_resource: 497 type: 1805 host_id: 128 reserved: 0 diff --git a/board/ti/am62px/rm-cfg.yaml b/board/ti/am62px/rm-cfg.yaml index b7a5fa0cd1..e0ffc5aae9 100644 --- a/board/ti/am62px/rm-cfg.yaml +++ b/board/ti/am62px/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for AM62P # @@ -477,13 +477,13 @@ rm-cfg: reserved: 0 - start_resource: 44 - num_resource: 36 + num_resource: 35 type: 1802 host_id: 35 reserved: 0 - start_resource: 44 - num_resource: 36 + num_resource: 35 type: 1802 host_id: 36 reserved: 0 @@ -519,7 +519,7 @@ rm-cfg: reserved: 0 - start_resource: 909 - num_resource: 627 + num_resource: 626 type: 1805 host_id: 128 reserved: 0 diff --git a/board/ti/am62x/rm-cfg.yaml b/board/ti/am62x/rm-cfg.yaml index 3ce72f5a62..f82aa7370d 100644 --- a/board/ti/am62x/rm-cfg.yaml +++ b/board/ti/am62x/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for AM62X # @@ -513,13 +513,13 @@ rm-cfg: reserved: 0 - start_resource: 44 - num_resource: 36 + num_resource: 35 type: 1802 host_id: 35 reserved: 0 - start_resource: 44 - num_resource: 36 + num_resource: 35 type: 1802 host_id: 36 reserved: 0 @@ -555,7 +555,7 @@ rm-cfg: reserved: 0 - start_resource: 909 - num_resource: 627 + num_resource: 626 type: 1805 host_id: 128 reserved: 0 -- cgit v1.2.3 From 0b1de6c55226cd23ed0162a4143a5b08ecffbc72 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Thu, 15 Feb 2024 12:41:10 +0530 Subject: board: ti: common: Add header file for rtc Add the header file for rtc with the macros and declarations to avoid including '.c' file in the platform evm.c files. Signed-off-by: Jayesh Choudhary --- board/ti/common/Makefile | 1 + board/ti/common/rtc.c | 7 +------ board/ti/common/rtc.h | 27 +++++++++++++++++++++++++++ 3 files changed, 29 insertions(+), 6 deletions(-) create mode 100644 board/ti/common/rtc.h diff --git a/board/ti/common/Makefile b/board/ti/common/Makefile index 1c1a6a237c..46e38aaad9 100644 --- a/board/ti/common/Makefile +++ b/board/ti/common/Makefile @@ -5,3 +5,4 @@ obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o obj-${CONFIG_CMD_EXTENSION} += cape_detect.o obj-$(CONFIG_SET_DFU_ALT_INFO) += k3_dfu.o obj-${CONFIG_ARCH_K3} += k3-ddr-init.o +obj-${CONFIG_BOARD_HAS_32K_RTC_CRYSTAL} += rtc.o diff --git a/board/ti/common/rtc.c b/board/ti/common/rtc.c index e117a92776..65c1f75c89 100644 --- a/board/ti/common/rtc.c +++ b/board/ti/common/rtc.c @@ -8,12 +8,7 @@ #include #include -#define WKUP_CTRLMMR_DBOUNCE_CFG1 0x04504084 -#define WKUP_CTRLMMR_DBOUNCE_CFG2 0x04504088 -#define WKUP_CTRLMMR_DBOUNCE_CFG3 0x0450408c -#define WKUP_CTRLMMR_DBOUNCE_CFG4 0x04504090 -#define WKUP_CTRLMMR_DBOUNCE_CFG5 0x04504094 -#define WKUP_CTRLMMR_DBOUNCE_CFG6 0x04504098 +#include "rtc.h" void board_rtc_init(void) { diff --git a/board/ti/common/rtc.h b/board/ti/common/rtc.h new file mode 100644 index 0000000000..57737829b6 --- /dev/null +++ b/board/ti/common/rtc.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * RTC setup include file for TI Platforms + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef __RTC_H +#define __RTC_H + +/* Debounce configuration register*/ +#define WKUP_CTRLMMR_DBOUNCE_CFG1 0x04504084 +#define WKUP_CTRLMMR_DBOUNCE_CFG2 0x04504088 +#define WKUP_CTRLMMR_DBOUNCE_CFG3 0x0450408c +#define WKUP_CTRLMMR_DBOUNCE_CFG4 0x04504090 +#define WKUP_CTRLMMR_DBOUNCE_CFG5 0x04504094 +#define WKUP_CTRLMMR_DBOUNCE_CFG6 0x04504098 + +/** + * board_rtc_init() - Enable the external 32k crystal and configure debounce + * registers. + * This function enables the 32k crystal, add required TRIM settings for the + * crystals and add debounce configuration. + */ +void board_rtc_init(void); + +#endif /* __RTC_H */ -- cgit v1.2.3 From fc039592e3dff11fcfc9ba369b1003459c98cb96 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Thu, 15 Feb 2024 12:41:11 +0530 Subject: board: ti: am62*: Fix the rtc file inclusion Include the header file instead of c file. Fixes: d36ad81d25a9 ("board: ti: common: add rtc setup to common folder") Signed-off-by: Jayesh Choudhary --- board/ti/am62ax/evm.c | 2 +- board/ti/am62px/evm.c | 2 +- board/ti/am62x/evm.c | 3 +-- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c index de5a193c63..8b3fced0a2 100644 --- a/board/ti/am62ax/evm.c +++ b/board/ti/am62ax/evm.c @@ -15,7 +15,7 @@ #include #include -#include "../common/rtc.c" +#include "../common/rtc.h" #include "../common/k3-ddr-init.h" #define CTRLMMR_USB0_PHY_CTRL 0x43004008 diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c index 341bc48ba8..3cbada5405 100644 --- a/board/ti/am62px/evm.c +++ b/board/ti/am62px/evm.c @@ -16,7 +16,7 @@ #include #include -#include "../common/rtc.c" +#include "../common/rtc.h" #include "../common/k3-ddr-init.h" #if CONFIG_IS_ENABLED(SPLASH_SCREEN) diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index fb74f5967f..6a5a7804b1 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -26,8 +26,7 @@ #include #include "../common/board_detect.h" - -#include "../common/rtc.c" +#include "../common/rtc.h" #include "../common/k3-ddr-init.h" -- cgit v1.2.3 From 1db6181b63e23be96752ec50d3aa2bd3261aa5e5 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Thu, 15 Feb 2024 12:41:12 +0530 Subject: board: ti: j722s: Enable 32k crystal for RTC Currently, the rtc clock is being set to 32552 instead of exact 32k. Enable the 32k crystal and setup debounce conf registers by invoking board_rtc_init call so that rtc clock is set accurately to 32768. Signed-off-by: Jayesh Choudhary --- board/ti/j722s/evm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c index 8469467b7d..81feb312e3 100644 --- a/board/ti/j722s/evm.c +++ b/board/ti/j722s/evm.c @@ -16,6 +16,7 @@ #include "../common/board_detect.h" #include "../common/k3-ddr-init.h" +#include "../common/rtc.h" #ifdef CONFIG_TI_I2C_BOARD_DETECT /* @@ -58,5 +59,8 @@ int checkboard(void) int board_init(void) { + if (IS_ENABLED(CONFIG_BOARD_HAS_32K_RTC_CRYSTAL)) + board_rtc_init(); + return 0; } -- cgit v1.2.3 From a12771ffc0939fc4675de1de4ed9406a7e26bf6a Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Thu, 15 Feb 2024 12:41:13 +0530 Subject: configs: j722s_evm_a53_defconfig: Add CONFIG_BOARD_HAS_32K_RTC_CRYSTAL Enable CONFIG_BOARD_HAS_32K_RTC_CRYSTAL to enable 32k crystal. Signed-off-by: Jayesh Choudhary --- configs/j722s_evm_a53_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig index 08eff9731a..96fe237cc4 100644 --- a/configs/j722s_evm_a53_defconfig +++ b/configs/j722s_evm_a53_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_K3=y CONFIG_EEPROM_CHIP_ADDRESS=0x51 CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_BOARD_HAS_32K_RTC_CRYSTAL=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -- cgit v1.2.3 From fda91ea9bea6fbfa8c7ca6563646a522ecd93bf0 Mon Sep 17 00:00:00 2001 From: Ravi Gunasekaran Date: Wed, 14 Feb 2024 16:22:00 +0530 Subject: arm: dts: k3-j722s: Add support for SERDES0 Add SERDES0 and its wrapper description to support USB3 and SGMII interfaces. Signed-off-by: Ravi Gunasekaran --- arch/arm/dts/k3-j722s.dtsi | 54 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm/dts/k3-j722s.dtsi b/arch/arm/dts/k3-j722s.dtsi index a635d547e7..d689845418 100644 --- a/arch/arm/dts/k3-j722s.dtsi +++ b/arch/arm/dts/k3-j722s.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include "k3-am62p5.dtsi" @@ -73,6 +74,50 @@ <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; }; + + serdes_refclk: clock-cmnrefclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + serdes_wiz0: wiz@f000000 { + compatible = "ti,am64-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <1>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; + + assigned-clocks = <&k3_clks 279 1>; + assigned-clock-parents = <&k3_clks 279 5>; + + serdes0: serdes@f000000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x0f000000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 279 1>, + <&k3_clks 279 1>, + <&k3_clks 279 1>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; /* Needs lane config */ + }; + }; }; /* Main domain overrides */ @@ -85,6 +130,15 @@ ti,interrupt-ranges = <0 237 8>; }; +&main_conf { + serdes0_ln_ctrl: mux-controller@4080 { + compatible = "mmio-mux"; + reg = <0x4080 0x4>; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ + }; +}; + &oc_sram { reg = <0x00 0x70000000 0x00 0x40000>; ranges = <0x00 0x00 0x70000000 0x40000>; -- cgit v1.2.3 From 837d28f0c66c968f9d3809580f630798e0e887f6 Mon Sep 17 00:00:00 2001 From: Ravi Gunasekaran Date: Wed, 14 Feb 2024 16:22:01 +0530 Subject: arm: dts: k3-j722s: Redefine USB1 node description USB1 controller on J722S and AM62P are from different vendors. Redefine the USB1 node description for J722S by deleting the node inherited from AM62P dtsi. Signed-off-by: Ravi Gunasekaran --- arch/arm/dts/k3-j722s.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/dts/k3-j722s.dtsi b/arch/arm/dts/k3-j722s.dtsi index d689845418..0e94c596cc 100644 --- a/arch/arm/dts/k3-j722s.dtsi +++ b/arch/arm/dts/k3-j722s.dtsi @@ -13,6 +13,13 @@ #include "k3-am62p5.dtsi" +/* + * USB1 controller on AM62P and J722S are of different IP. + * Delete AM62P's USBSS1 node definition and redefine it for J722S. + */ + +/delete-node/ &usbss1; + / { model = "Texas Instruments K3 J722S SoC"; compatible = "ti,j722s"; @@ -81,6 +88,38 @@ clock-frequency = <0>; }; + usbss1: cdns-usb@f920000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x0f920000 0x00 0x100>; + power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 278 3>, <&k3_clks 278 1>; + clock-names = "ref", "lpm"; + assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb1: usb@31200000{ + compatible = "cdns,usb3"; + reg = <0x00 0x31200000 0x00 0x10000>, + <0x00 0x31210000 0x00 0x10000>, + <0x00 0x31220000 0x00 0x10000>; + reg-names = "otg", + "xhci", + "dev"; + interrupts = , /* irq.0 */ + , /* irq.6 */ + ; /* otgirq */ + interrupt-names = "host", + "peripheral", + "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + serdes_wiz0: wiz@f000000 { compatible = "ti,am64-wiz-10g"; #address-cells = <1>; -- cgit v1.2.3 From 4b3cf6ca7685f4dd7419f8aa5f40deaf7eba5958 Mon Sep 17 00:00:00 2001 From: Ravi Gunasekaran Date: Wed, 14 Feb 2024 16:22:02 +0530 Subject: arm: dts: ti: k3-j722s: Enable USB support Update the USB0, USB1 nodes and enable them. Signed-off-by: Ravi Gunasekaran --- arch/arm/dts/k3-j722s-evm-u-boot.dtsi | 17 ++++++++++++ arch/arm/dts/k3-j722s-evm.dts | 49 +++++++++++++++++++++++++++++++++++ include/dt-bindings/mux/ti-serdes.h | 3 +++ 3 files changed, 69 insertions(+) diff --git a/arch/arm/dts/k3-j722s-evm-u-boot.dtsi b/arch/arm/dts/k3-j722s-evm-u-boot.dtsi index cb5e8e53c0..55f70ef969 100644 --- a/arch/arm/dts/k3-j722s-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-j722s-evm-u-boot.dtsi @@ -33,3 +33,20 @@ bootph-pre-ram; }; }; + +&usbss0 { + bootph-pre-ram; +}; + +&usb0 { + dr_mode = "peripheral"; + bootph-pre-ram; +}; + +&usbss1 { + status = "disabled"; +}; + +&usb1 { + status = "disabled"; +}; diff --git a/arch/arm/dts/k3-j722s-evm.dts b/arch/arm/dts/k3-j722s-evm.dts index 193ce9a551..799d623e81 100644 --- a/arch/arm/dts/k3-j722s-evm.dts +++ b/arch/arm/dts/k3-j722s-evm.dts @@ -12,6 +12,8 @@ #include "k3-j722s.dtsi" #include #include +#include +#include / { compatible = "ti,j722s-evm", "ti,j722s"; @@ -22,6 +24,8 @@ serial2 = &main_uart0; mmc0 = &sdhci0; mmc1 = &sdhci1; + usb0 = &usb0; + usb1 = &usb1; }; chosen { @@ -283,6 +287,12 @@ J722S_IOPAD(0x0244, PIN_INPUT, 7) /* (A24) MMC1_SDWP */ >; }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */ + >; + }; }; &main_gpio1 { @@ -486,3 +496,42 @@ memory-region = <&c7x_1_dma_memory_region>, <&c7x_1_memory_region>; }; + +&serdes0_ln_ctrl { + idle-states = ; +}; + +&serdes0 { + status = "okay"; + serdes0_usb_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + +&usb0 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usbss1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; + ti,vbus-divider; +}; + +&usb1 { + dr_mode = "host"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h index 91ea9633c0..fbe008619d 100644 --- a/include/dt-bindings/mux/ti-serdes.h +++ b/include/dt-bindings/mux/ti-serdes.h @@ -179,4 +179,7 @@ #define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2 #define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3 +/* J722S */ +#define J722S_SERDES0_LANE0_USB 0x0 + #endif /* _DT_BINDINGS_MUX_TI_SERDES */ -- cgit v1.2.3 From 705deacde1513138d2ff54235b29e8e5f2a1d26f Mon Sep 17 00:00:00 2001 From: Ravi Gunasekaran Date: Wed, 14 Feb 2024 16:22:03 +0530 Subject: configs: j722s_evm_r5_usbdfu: Add USB DFU config fragment Add config fragment to enable USB DFU support Signed-off-by: Ravi Gunasekaran --- configs/j722s_evm_r5_usbdfu.config | 44 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 configs/j722s_evm_r5_usbdfu.config diff --git a/configs/j722s_evm_r5_usbdfu.config b/configs/j722s_evm_r5_usbdfu.config new file mode 100644 index 0000000000..2e6243b8eb --- /dev/null +++ b/configs/j722s_evm_r5_usbdfu.config @@ -0,0 +1,44 @@ +# CONFIG_DM_GPIO is not set +# CONFIG_SPL_SPI is not set +# CONFIG_DMA is not set +# CONFIG_TI_K3_NAVSS_UDMA is not set +# CONFIG_MMC_HS400_SUPPORT is not set +# CONFIG_MMC_HS200_SUPPORT is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SDHCI_ADMA is not set +# CONFIG_SPL_MMC_SDHCI_ADMA is not set +# CONFIG_MMC_SDHCI_AM654 is not set +# CONFIG_MTD is not set +# CONFIG_DM_MTD is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_TI_K3_NAVSS_RINGACC is not set +# CONFIG_TI_PRUSS is not set +# CONFIG_SPI is not set +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y +CONFIG_SPL_DFU_RAM=y +CONFIG_SPL_ENV_IS_NOWHERE=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_DFU_OVER_USB=y +CONFIG_DFU_RAM=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_SPL_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_AM62=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 -- cgit v1.2.3 From fc23cf83e915c5814a220baf90db629250d1f29d Mon Sep 17 00:00:00 2001 From: Ravi Gunasekaran Date: Wed, 14 Feb 2024 16:22:04 +0530 Subject: configs: j722s_evm_r5_usbmsc: Add USB MSC config fragment Add config fragment to enable USB MSC boot. USB Host boot is supported only from USB0 port. By default USB0 is configured in peripheral mode to support DFU. Inorder to support USB Host boot, "dr_mode" property needs to be changed from "peripheral" to "host" in the device tree. Signed-off-by: Ravi Gunasekaran --- configs/j722s_evm_r5_usbmsc.config | 43 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 configs/j722s_evm_r5_usbmsc.config diff --git a/configs/j722s_evm_r5_usbmsc.config b/configs/j722s_evm_r5_usbmsc.config new file mode 100644 index 0000000000..8d8a133f96 --- /dev/null +++ b/configs/j722s_evm_r5_usbmsc.config @@ -0,0 +1,43 @@ +# CONFIG_DM_GPIO is not set +# CONFIG_SPL_SPI is not set +# CONFIG_DMA is not set +# CONFIG_TI_K3_NAVSS_UDMA is not set +# CONFIG_MMC_HS400_SUPPORT is not set +# CONFIG_MMC_HS200_SUPPORT is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SDHCI_ADMA is not set +# CONFIG_SPL_MMC_SDHCI_ADMA is not set +# CONFIG_MMC_SDHCI_AM654 is not set +# CONFIG_MTD is not set +# CONFIG_DM_MTD is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_TI_K3_NAVSS_RINGACC is not set +# CONFIG_TI_PRUSS is not set +# CONFIG_SPI is not set +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_ENV_IS_NOWHERE=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_USB=y +CONFIG_SPL_USB_HOST=y +CONFIG_SPL_USB_STORAGE=y +CONFIG_USB_HOST=y +CONFIG_USB_STORAGE=y +CONFIG_SPL_USB_GADGET=y +CONFIG_DM_USB=y +CONFIG_SPL_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_AM62=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 -- cgit v1.2.3 From 96387ef0215ae1310b9b874166adb56993f1aee0 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Thu, 15 Feb 2024 15:24:33 +0530 Subject: board: ti: j784s4: Update Resource Management configs Update rm-cfg.yaml and tifs-rm-cfg.yaml to account for the latest changes added in the K3 Resource Partitioning Tool. The change enables resource sharing between A72_2 and MAIN_0_R5_0 for the BCDMA CSI RX and TX channels, J784S4 supports upto 12 CSI cameras and 16 channels would not be enough for all such use cases for RTOS and Linux, thus sharing of resources in needed. Signed-off-by: Vaishnav Achath --- board/ti/j784s4/rm-cfg.yaml | 24 ++++++++++++------------ board/ti/j784s4/tifs-rm-cfg.yaml | 24 ++++++++++++------------ 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/board/ti/j784s4/rm-cfg.yaml b/board/ti/j784s4/rm-cfg.yaml index fcd005c3bd..56a5bf141f 100644 --- a/board/ti/j784s4/rm-cfg.yaml +++ b/board/ti/j784s4/rm-cfg.yaml @@ -432,56 +432,56 @@ rm-cfg: - start_resource: 16 - num_resource: 16 + num_resource: 32 type: 17998 host_id: 12 reserved: 0 - - start_resource: 32 - num_resource: 16 + start_resource: 16 + num_resource: 32 type: 17998 host_id: 35 reserved: 0 - start_resource: 0 - num_resource: 8 + num_resource: 16 type: 17999 host_id: 12 reserved: 0 - - start_resource: 8 - num_resource: 8 + start_resource: 0 + num_resource: 16 type: 17999 host_id: 35 reserved: 0 - start_resource: 0 - num_resource: 16 + num_resource: 32 type: 18017 host_id: 12 reserved: 0 - - start_resource: 16 - num_resource: 16 + start_resource: 0 + num_resource: 32 type: 18017 host_id: 35 reserved: 0 - start_resource: 0 - num_resource: 8 + num_resource: 16 type: 18018 host_id: 12 reserved: 0 - - start_resource: 8 - num_resource: 8 + start_resource: 0 + num_resource: 16 type: 18018 host_id: 35 reserved: 0 diff --git a/board/ti/j784s4/tifs-rm-cfg.yaml b/board/ti/j784s4/tifs-rm-cfg.yaml index 80e374c750..ecaea70683 100644 --- a/board/ti/j784s4/tifs-rm-cfg.yaml +++ b/board/ti/j784s4/tifs-rm-cfg.yaml @@ -249,56 +249,56 @@ tifs-rm-cfg: resasg_entries: - start_resource: 16 - num_resource: 16 + num_resource: 32 type: 17998 host_id: 12 reserved: 0 - - start_resource: 32 - num_resource: 16 + start_resource: 16 + num_resource: 32 type: 17998 host_id: 35 reserved: 0 - start_resource: 0 - num_resource: 8 + num_resource: 16 type: 17999 host_id: 12 reserved: 0 - - start_resource: 8 - num_resource: 8 + start_resource: 0 + num_resource: 16 type: 17999 host_id: 35 reserved: 0 - start_resource: 0 - num_resource: 16 + num_resource: 32 type: 18017 host_id: 12 reserved: 0 - - start_resource: 16 - num_resource: 16 + start_resource: 0 + num_resource: 32 type: 18017 host_id: 35 reserved: 0 - start_resource: 0 - num_resource: 8 + num_resource: 16 type: 18018 host_id: 12 reserved: 0 - - start_resource: 8 - num_resource: 8 + start_resource: 0 + num_resource: 16 type: 18018 host_id: 35 reserved: 0 -- cgit v1.2.3 From 61ea32c0eb0c2d827a7ebc52a2befe8dfbd1de56 Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:19:46 +0530 Subject: dma: ti: k3-udma: Use ring_idx to pair k3 nav rings Use ring_idx to pair rings. ring_idx will be same as tx flow_id for all non-negative flow_ids. For negative flow_ids, ring_idx will be tchan->id added with bchan_cnt. Signed-off-by: MD Danish Anwar --- drivers/dma/ti/k3-udma.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index a018f70c54..bdaadc9e78 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -875,13 +875,20 @@ static int udma_alloc_tx_resources(struct udma_chan *uc) { struct k3_nav_ring_cfg ring_cfg; struct udma_dev *ud = uc->ud; - int ret; + struct udma_tchan *tchan; + int ring_idx, ret; ret = udma_get_tchan(uc); if (ret) return ret; - ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, uc->tchan->id, -1, + tchan = uc->tchan; + if (tchan->tflow_id >= 0) + ring_idx = tchan->tflow_id; + else + ring_idx = ud->bchan_cnt + tchan->id; + + ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1, &uc->tchan->t_ring, &uc->tchan->tc_ring); if (ret) { -- cgit v1.2.3 From 4f1b39c775e45b8c820e302b0c0268ffff04340e Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:19:47 +0530 Subject: misc: fs-loader: Use fw_storage_interface instead of storage_interface The fs-loader driver reads env storage_interface and uses it to load firmware file into memory using the medium set by env. Update the driver to use env fw_storage_interface as this variable is only used to load firmwares. This is to keep all variables used by fs-loader driver with 'fw_' prefix. All other variables have 'fw_' prefix except for storage_interface. The env storage_interface will act as fallback so that the existing implementations do not break. Also update the FS Loader documentation accordingly. Signed-off-by: MD Danish Anwar --- doc/develop/driver-model/fs_firmware_loader.rst | 5 ++++- drivers/misc/fs_loader.c | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/doc/develop/driver-model/fs_firmware_loader.rst b/doc/develop/driver-model/fs_firmware_loader.rst index b0823700a9..3dc3b58c6f 100644 --- a/doc/develop/driver-model/fs_firmware_loader.rst +++ b/doc/develop/driver-model/fs_firmware_loader.rst @@ -98,8 +98,11 @@ through the U-boot environment variable during run time. For examples: +fw_storage_interface: + Firmware storage interface, it can be "mmc", "usb", "sata" or "ubi". storage_interface: - Storage interface, it can be "mmc", "usb", "sata" or "ubi". + Storage interface, it can be "mmc", "usb", "sata" or "ubi". This acts + as a fallback if fw_storage_interface is not set. fw_dev_part: Block device number and its partition, it can be "0:1". fw_ubi_mtdpart: diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c index ccf5c7a803..2336180fc0 100644 --- a/drivers/misc/fs_loader.c +++ b/drivers/misc/fs_loader.c @@ -153,7 +153,10 @@ static int fw_get_filesystem_firmware(struct udevice *dev) char *storage_interface, *dev_part, *ubi_mtdpart, *ubi_volume; int ret; - storage_interface = env_get("storage_interface"); + storage_interface = env_get("fw_storage_interface"); + if (!storage_interface) + storage_interface = env_get("storage_interface"); + dev_part = env_get("fw_dev_part"); ubi_mtdpart = env_get("fw_ubi_mtdpart"); ubi_volume = env_get("fw_ubi_volume"); -- cgit v1.2.3 From 2764be4345d266a5013657f9c4583d6c335a9af3 Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:19:48 +0530 Subject: remoteproc: uclass: Add methods to load firmware to rproc and boot rproc Add APIs to set a firmware_name to a rproc and boot the rproc with the same firmware. Clients can call rproc_set_firmware() API to set firmware_name for a rproc whereas rproc_boot() will load the firmware set by rproc_set_firmware() to a buffer by calling request_firmware_into_buf(). rproc_boot() will then load the firmware file to the remote processor and start the remote processor. Also include "fs-loader.h" and make remoteproc driver select FS_LOADER in Kconfig so that we can call request_firmware_into_buf() from remoteproc driver. Signed-off-by: MD Danish Anwar --- drivers/remoteproc/Kconfig | 8 +++ drivers/remoteproc/rproc-uclass.c | 102 ++++++++++++++++++++++++++++++++++++++ include/remoteproc.h | 34 +++++++++++++ 3 files changed, 144 insertions(+) diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index a7740954c0..3e921b981b 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -10,6 +10,7 @@ menu "Remote Processor drivers" # All users should depend on DM config REMOTEPROC bool + select FS_LOADER depends on DM # Please keep the configuration alphabetically sorted. @@ -113,4 +114,11 @@ config REMOTEPROC_TI_IPU help Say 'y' here to add support for TI' K3 remoteproc driver. +config REMOTEPROC_MAX_FW_SIZE + hex "Maximum size of firmware that needs to be loaded to rproc" + default 0x10000 + help + Maximum size of the firmware file (elf, binary) that needs to be + loaded to th rproc core. + endmenu diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c index 50bcc9030e..da8f6d5dd9 100644 --- a/drivers/remoteproc/rproc-uclass.c +++ b/drivers/remoteproc/rproc-uclass.c @@ -11,8 +11,11 @@ #include #include #include +#include +#include #include #include +#include #include #include #include @@ -960,3 +963,102 @@ unsigned long rproc_parse_resource_table(struct udevice *dev, struct rproc *cfg) return 1; } + +int rproc_set_firmware(struct udevice *rproc_dev, const char *fw_name) +{ + struct dm_rproc_uclass_pdata *uc_pdata; + int len; + char *p; + + if (!rproc_dev || !fw_name) + return -EINVAL; + + uc_pdata = dev_get_uclass_plat(rproc_dev); + if (!uc_pdata) + return -EINVAL; + + len = strcspn(fw_name, "\n"); + if (!len) { + debug("invalid firmware name\n"); + return -EINVAL; + } + + p = strndup(fw_name, len); + if (!p) + return -ENOMEM; + + uc_pdata->fw_name = p; + + return 0; +} + +int rproc_boot(struct udevice *rproc_dev) +{ + struct dm_rproc_uclass_pdata *uc_pdata; + struct udevice *fs_loader; + int core_id, ret = 0; + char *firmware; + void *addr; + + if (!rproc_dev) + return -EINVAL; + + uc_pdata = dev_get_uclass_plat(rproc_dev); + if (!uc_pdata) + return -EINVAL; + + core_id = dev_seq(rproc_dev); + firmware = uc_pdata->fw_name; + + if (!firmware) { + debug("No firmware set for rproc core %d\n", core_id); + return -EINVAL; + } + + /* Initialize all rproc cores */ + if (!rproc_is_initialized()) { + ret = rproc_init(); + if (ret) { + debug("rproc_init() failed: %d\n", ret); + return ret; + } + } + + /* Loading firmware to a given address */ + ret = get_fs_loader(&fs_loader); + if (ret) { + debug("could not get fs loader: %d\n", ret); + return ret; + } + + if (CONFIG_REMOTEPROC_MAX_FW_SIZE) { + addr = malloc(CONFIG_REMOTEPROC_MAX_FW_SIZE); + if (!addr) + return -ENOMEM; + } else { + debug("CONFIG_REMOTEPROC_MAX_FW_SIZE not defined\n"); + return -EINVAL; + } + + ret = request_firmware_into_buf(fs_loader, firmware, addr, CONFIG_REMOTEPROC_MAX_FW_SIZE, + 0); + if (ret < 0) { + debug("could not request %s: %d\n", firmware, ret); + goto free_buffer; + } + + ret = rproc_load(core_id, (ulong)addr, ret); + if (ret) { + debug("failed to load %s to rproc core %d from addr 0x%08lX err %d\n", + uc_pdata->fw_name, core_id, (ulong)addr, ret); + goto free_buffer; + } + + ret = rproc_start(core_id); + if (ret) + debug("failed to start rproc core %d\n", core_id); + +free_buffer: + free(addr); + return ret; +} diff --git a/include/remoteproc.h b/include/remoteproc.h index f48054de6b..61aa50ac79 100644 --- a/include/remoteproc.h +++ b/include/remoteproc.h @@ -402,6 +402,7 @@ enum rproc_mem_type { * @name: Platform-specific way of naming the Remote proc * @mem_type: one of 'enum rproc_mem_type' * @driver_plat_data: driver specific platform data that may be needed. + * @fw_name: firmware name * * This can be accessed with dev_get_uclass_plat() for any UCLASS_REMOTEPROC * device. @@ -411,6 +412,7 @@ struct dm_rproc_uclass_pdata { const char *name; enum rproc_mem_type mem_type; void *driver_plat_data; + char *fw_name; }; /** @@ -704,6 +706,34 @@ unsigned long rproc_parse_resource_table(struct udevice *dev, struct resource_table *rproc_find_resource_table(struct udevice *dev, unsigned int addr, int *tablesz); +/** + * rproc_set_firmware() - assign a new firmware name + * @rproc_dev: device for which new firmware name is being assigned + * @fw_name: new firmware name to be assigned + * + * This function allows remoteproc drivers or clients to configure a custom + * firmware name. The function does not trigger a remote processor boot, + * only sets the firmware name used for a subsequent boot. + * + * This function sets the fw_name field in uclass pdata of the Remote proc + * + * Return: 0 on success or a negative value upon failure + */ +int rproc_set_firmware(struct udevice *rproc_dev, const char *fw_name); + +/** + * rproc_boot() - boot a remote processor + * @rproc_dev: rproc device to boot + * + * Boot a remote processor (i.e. load its firmware, power it on, ...). + * + * This function first loads the firmware set in the uclass pdata of Remote + * processor to a buffer and then loads firmware to the remote processor + * using rproc_load(). + * + * Return: 0 on success, and an appropriate error value otherwise + */ +int rproc_boot(struct udevice *rproc_dev); #else static inline int rproc_init(void) { return -ENOSYS; } static inline int rproc_dev_init(int id) { return -ENOSYS; } @@ -743,6 +773,10 @@ static inline int rproc_elf_load_rsc_table(struct udevice *dev, ulong fw_addr, ulong fw_size, ulong *rsc_addr, ulong *rsc_size) { return -ENOSYS; } +static inline int rproc_set_firmware(struct udevice *rproc_dev, const char *fw_name) +{ return -ENOSYS; } +static inline int rproc_boot(struct udevice *rproc_dev) +{ return -ENOSYS; } #endif #endif /* _RPROC_H_ */ -- cgit v1.2.3 From 29d81629840df6ef0cdbe84a203b027067159ae3 Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:19:49 +0530 Subject: net: ti: icssg: Add Firmware Interface for ICSSG Ethernet driver. Add firmware interface related headers and macros for ICSSG Ethernet driver. These macros will be later used by the ICSSG ethernet driver. Signed-off-by: MD Danish Anwar --- drivers/net/ti/icssg_switch_map.h | 209 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 209 insertions(+) create mode 100644 drivers/net/ti/icssg_switch_map.h diff --git a/drivers/net/ti/icssg_switch_map.h b/drivers/net/ti/icssg_switch_map.h new file mode 100644 index 0000000000..b62c51407b --- /dev/null +++ b/drivers/net/ti/icssg_switch_map.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Texas Instruments ICSSG Ethernet driver + * + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#ifndef __NET_TI_ICSSG_SWITCH_MAP_H +#define __NET_TI_ICSSG_SWITCH_MAP_H + +/*Time after which FDB entries are checked for aged out values. Value in nanoseconds*/ +#define FDB_AGEING_TIMEOUT_OFFSET 0x0014 + +/*default VLAN tag for Host Port*/ +#define HOST_PORT_DF_VLAN_OFFSET 0x001C + +/*Same as HOST_PORT_DF_VLAN_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET HOST_PORT_DF_VLAN_OFFSET + +/*default VLAN tag for P1 Port*/ +#define P1_PORT_DF_VLAN_OFFSET 0x0020 + +/*Same as P1_PORT_DF_VLAN_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET P1_PORT_DF_VLAN_OFFSET + +/*default VLAN tag for P2 Port*/ +#define P2_PORT_DF_VLAN_OFFSET 0x0024 + +/*Same as P2_PORT_DF_VLAN_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET P2_PORT_DF_VLAN_OFFSET + +/*VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000*/ +#define VLAN_STATIC_REG_TABLE_OFFSET 0x0100 + +/*VLAN-FID Table offset for EMAC*/ +#define EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET VLAN_STATIC_REG_TABLE_OFFSET + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC0_HI 0x2104 + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC0_LO 0x2F6C + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC1_HI 0x3DD4 + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC1_LO 0x4C3C + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC0_HI 0x5AA4 + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC0_LO 0x5F0C + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC1_HI 0x6374 + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC1_LO 0x67DC + +/*special packet descriptor Q reserved memory*/ +#define HOST_SPPD0 0x7AAC + +/*special packet descriptor Q reserved memory*/ +#define HOST_SPPD1 0x7EAC + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_CYCLECOUNT_OFFSET 0x83EC + +/*IEP count hi roll over count*/ +#define TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET 0x83F4 + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET 0x83F8 + +/*Set clock descriptor*/ +#define TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET 0x83FC + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET 0x843C + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_COUNT_OFFSET 0x8440 + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET 0x8444 + +/*Control variable to generate SYNC1*/ +#define TIMESYNC_FW_WC_ISOM_PIN_SIGNAL_EN_OFFSET 0x844C + +/*SystemTime Sync0 periodicity*/ +#define TIMESYNC_FW_ST_SYNCOUT_PERIOD_OFFSET 0x8450 + +/*pktTxDelay for P1 = link speed dependent p1 mac delay + p1 phy delay*/ +#define TIMESYNC_FW_WC_PKTTXDELAY_P1_OFFSET 0x8454 + +/*pktTxDelay for P2 = link speed dependent p2 mac delay + p2 phy delay*/ +#define TIMESYNC_FW_WC_PKTTXDELAY_P2_OFFSET 0x8458 + +/*Set clock operation done signal for next task*/ +#define TIMESYNC_FW_SIG_PNFW_OFFSET 0x845C + +/*Set clock operation done signal for next task*/ +#define TIMESYNC_FW_SIG_TIMESYNCFW_OFFSET 0x8460 + +/*New list is copied at this time*/ +#define TAS_CONFIG_CHANGE_TIME 0x000C + +/*config change error counter*/ +#define TAS_CONFIG_CHANGE_ERROR_COUNTER 0x0014 + +/*TAS List update pending flag*/ +#define TAS_CONFIG_PENDING 0x0018 + +/*TAS list update trigger flag*/ +#define TAS_CONFIG_CHANGE 0x0019 + +/*List length for new TAS schedule*/ +#define TAS_ADMIN_LIST_LENGTH 0x001A + +/*Currently active TAS list index*/ +#define TAS_ACTIVE_LIST_INDEX 0x001B + +/*Cycle time for the new TAS schedule*/ +#define TAS_ADMIN_CYCLE_TIME 0x001C + +/*Cycle counts remaining till the TAS list update*/ +#define TAS_CONFIG_CHANGE_CYCLE_COUNT 0x0020 + +/*Base Flow ID for sending packets to Host for Slice0*/ +#define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET 0x0024 + +/*Same as PSI_L_REGULAR_FLOW_ID_BASE_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PSI_L_REGULAR_FLOW_ID_BASE_OFFSET PSI_L_REGULAR_FLOW_ID_BASE_OFFSET + +/*Base Flow ID for sending mgmt and Tx TS to Host for Slice0*/ +#define PSI_L_MGMT_FLOW_ID_OFFSET 0x0026 + +/*Same as PSI_L_MGMT_FLOW_ID_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PSI_L_MGMT_FLOW_ID_BASE_OFFSET PSI_L_MGMT_FLOW_ID_OFFSET + +/*Queue number for Special packets written here*/ +#define SPL_PKT_DEFAULT_PRIORITY 0x0028 + +/*Express Preemptible Queue Mask*/ +#define EXPRESS_PRE_EMPTIVE_Q_MASK 0x0029 + +/*Port1/Port2 Default Queue number for untagged packets, only 1B is used*/ +#define QUEUE_NUM_UNTAGGED 0x002A + +/*Stores the table used for priority regeneration. 1B per PCP/Queue*/ +#define PORT_Q_PRIORITY_REGEN_OFFSET 0x002C + +/* For marking Packet as priority/express (this feature is disabled) or + * cut-through/S&F. + */ +#define EXPRESS_PRE_EMPTIVE_Q_MAP 0x0034 + +/*Stores the table used for priority mapping. 1B per PCP/Queue*/ +#define PORT_Q_PRIORITY_MAPPING_OFFSET 0x003C + +/*TAS gate mask for windows list0*/ +#define TAS_GATE_MASK_LIST0 0x0100 + +/*TAS gate mask for windows list1*/ +#define TAS_GATE_MASK_LIST1 0x0350 + +/*Memory to Enable/Disable Preemption on TX side*/ +#define PRE_EMPTION_ENABLE_TX 0x05A0 + +/*Active State of Preemption on TX side*/ +#define PRE_EMPTION_ACTIVE_TX 0x05A1 + +/*Memory to Enable/Disable Verify State Machine Preemption*/ +#define PRE_EMPTION_ENABLE_VERIFY 0x05A2 + +/*Verify Status of State Machine*/ +#define PRE_EMPTION_VERIFY_STATUS 0x05A3 + +/*Non Final Fragment Size supported by Link Partner*/ +#define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE 0x05A4 + +/*Non Final Fragment Size supported by Firmware*/ +#define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL 0x05A6 + +/*Time in ms the State machine waits for respond packet*/ +#define PRE_EMPTION_VERIFY_TIME 0x05A8 + +/*Memory used for R30 related management commands*/ +#define MGR_R30_CMD_OFFSET 0x05AC + +/*HW Buffer Pool0 base address*/ +#define BUFFER_POOL_0_ADDR_OFFSET 0x05BC + +/*16B for Host Egress MSMC Q (Pre-emptible) context*/ +#define HOST_RX_Q_PRE_CONTEXT_OFFSET 0x0684 + +/*Buffer for 8 FDB entries to be added by 'Add Multiple FDB entries IOCTL*/ +#define FDB_CMD_BUFFER 0x0894 + +/*16B for Host Egress MSMC Q (Express) context*/ +#define HOST_RX_Q_EXP_CONTEXT_OFFSET 0x0940 + +/*Start of 32 bits PA_STAT counters*/ +#define PA_STAT_32b_START_OFFSET 0x0080 + +#endif +/* __NET_TI_ICSSG_SWITCH_MAP_H */ -- cgit v1.2.3 From 13adda78fbbf6fcba7595a530f232e498ee936cb Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:19:50 +0530 Subject: net: ti: icssg: Add Firmware config and classification APIs. Add icssg_config.h / .c and icssg_classifier.c files. These are firmware configuration and classification related files. Add MII helper APIs and MACROs. These APIs and MACROs will be later used by ICSSG Ethernet driver. Also introduce icssg_prueth.h which has definition of prueth related structures. Signed-off-by: MD Danish Anwar --- drivers/net/ti/icss_mii_rt.h | 192 ++++++++++++++++++ drivers/net/ti/icssg_classifier.c | 376 ++++++++++++++++++++++++++++++++++++ drivers/net/ti/icssg_config.c | 397 ++++++++++++++++++++++++++++++++++++++ drivers/net/ti/icssg_config.h | 177 +++++++++++++++++ drivers/net/ti/icssg_prueth.h | 77 ++++++++ 5 files changed, 1219 insertions(+) create mode 100644 drivers/net/ti/icss_mii_rt.h create mode 100644 drivers/net/ti/icssg_classifier.c create mode 100644 drivers/net/ti/icssg_config.c create mode 100644 drivers/net/ti/icssg_config.h create mode 100644 drivers/net/ti/icssg_prueth.h diff --git a/drivers/net/ti/icss_mii_rt.h b/drivers/net/ti/icss_mii_rt.h new file mode 100644 index 0000000000..6b2449e736 --- /dev/null +++ b/drivers/net/ti/icss_mii_rt.h @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* PRU-ICSS MII_RT register definitions + * + * Copyright (C) 2015-2020 Texas Instruments Incorporated - http://www.ti.com + */ + +#ifndef __NET_PRUSS_MII_RT_H__ +#define __NET_PRUSS_MII_RT_H__ + +#include + +/* PRUSS_MII_RT Registers */ +#define PRUSS_MII_RT_RXCFG0 0x0 +#define PRUSS_MII_RT_RXCFG1 0x4 +#define PRUSS_MII_RT_TXCFG0 0x10 +#define PRUSS_MII_RT_TXCFG1 0x14 +#define PRUSS_MII_RT_TX_CRC0 0x20 +#define PRUSS_MII_RT_TX_CRC1 0x24 +#define PRUSS_MII_RT_TX_IPG0 0x30 +#define PRUSS_MII_RT_TX_IPG1 0x34 +#define PRUSS_MII_RT_PRS0 0x38 +#define PRUSS_MII_RT_PRS1 0x3c +#define PRUSS_MII_RT_RX_FRMS0 0x40 +#define PRUSS_MII_RT_RX_FRMS1 0x44 +#define PRUSS_MII_RT_RX_PCNT0 0x48 +#define PRUSS_MII_RT_RX_PCNT1 0x4c +#define PRUSS_MII_RT_RX_ERR0 0x50 +#define PRUSS_MII_RT_RX_ERR1 0x54 + +/* PRUSS_MII_RT_RXCFG0/1 bits */ +#define PRUSS_MII_RT_RXCFG_RX_ENABLE BIT(0) +#define PRUSS_MII_RT_RXCFG_RX_DATA_RDY_MODE_DIS BIT(1) +#define PRUSS_MII_RT_RXCFG_RX_CUT_PREAMBLE BIT(2) +#define PRUSS_MII_RT_RXCFG_RX_MUX_SEL BIT(3) +#define PRUSS_MII_RT_RXCFG_RX_L2_EN BIT(4) +#define PRUSS_MII_RT_RXCFG_RX_BYTE_SWAP BIT(5) +#define PRUSS_MII_RT_RXCFG_RX_AUTO_FWD_PRE BIT(6) +#define PRUSS_MII_RT_RXCFG_RX_L2_EOF_SCLR_DIS BIT(9) + +/* PRUSS_MII_RT_TXCFG0/1 bits */ +#define PRUSS_MII_RT_TXCFG_TX_ENABLE BIT(0) +#define PRUSS_MII_RT_TXCFG_TX_AUTO_PREAMBLE BIT(1) +#define PRUSS_MII_RT_TXCFG_TX_EN_MODE BIT(2) +#define PRUSS_MII_RT_TXCFG_TX_BYTE_SWAP BIT(3) +#define PRUSS_MII_RT_TXCFG_TX_MUX_SEL BIT(8) +#define PRUSS_MII_RT_TXCFG_PRE_TX_AUTO_SEQUENCE BIT(9) +#define PRUSS_MII_RT_TXCFG_PRE_TX_AUTO_ESC_ERR BIT(10) +#define PRUSS_MII_RT_TXCFG_TX_32_MODE_EN BIT(11) +#define PRUSS_MII_RT_TXCFG_TX_IPG_WIRE_CLK_EN BIT(12) /* SR2.0 onwards */ + +#define PRUSS_MII_RT_TXCFG_TX_START_DELAY_SHIFT 16 +#define PRUSS_MII_RT_TXCFG_TX_START_DELAY_MASK GENMASK(25, 16) + +#define PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_SHIFT 28 +#define PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_MASK GENMASK(30, 28) + +/* PRUSS_MII_RT_TX_IPG0/1 bits */ +#define PRUSS_MII_RT_TX_IPG_IPG_SHIFT 0 +#define PRUSS_MII_RT_TX_IPG_IPG_MASK GENMASK(9, 0) + +/* PRUSS_MII_RT_PRS0/1 bits */ +#define PRUSS_MII_RT_PRS_COL BIT(0) +#define PRUSS_MII_RT_PRS_CRS BIT(1) + +/* PRUSS_MII_RT_RX_FRMS0/1 bits */ +#define PRUSS_MII_RT_RX_FRMS_MIN_FRM_SHIFT 0 +#define PRUSS_MII_RT_RX_FRMS_MIN_FRM_MASK GENMASK(15, 0) + +#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_SHIFT 16 +#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_MASK GENMASK(31, 16) + +/* Min/Max in MII_RT_RX_FRMS */ +/* For EMAC and Switch */ +#define PRUSS_MII_RT_RX_FRMS_MAX (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) +#define PRUSS_MII_RT_RX_FRMS_MIN_FRM (64) + +/* for HSR and PRP */ +#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_LRE (PRUSS_MII_RT_RX_FRMS_MAX + \ + ICSS_LRE_TAG_RCT_SIZE) +/* PRUSS_MII_RT_RX_PCNT0/1 bits */ +#define PRUSS_MII_RT_RX_PCNT_MIN_PCNT_SHIFT 0 +#define PRUSS_MII_RT_RX_PCNT_MIN_PCNT_MASK GENMASK(3, 0) + +#define PRUSS_MII_RT_RX_PCNT_MAX_PCNT_SHIFT 4 +#define PRUSS_MII_RT_RX_PCNT_MAX_PCNT_MASK GENMASK(7, 4) + +/* PRUSS_MII_RT_RX_ERR0/1 bits */ +#define PRUSS_MII_RT_RX_ERR_MIN_PCNT_ERR BIT(0) +#define PRUSS_MII_RT_RX_ERR_MAX_PCNT_ERR BIT(1) +#define PRUSS_MII_RT_RX_ERR_MIN_FRM_ERR BIT(2) +#define PRUSS_MII_RT_RX_ERR_MAX_FRM_ERR BIT(3) + +#define ICSSG_CFG_OFFSET 0 +#define RGMII_CFG_OFFSET 4 + +/* Constant to choose between MII0 and MII1 */ +#define ICSS_MII0 0 +#define ICSS_MII1 1 + +/* ICSSG_CFG Register bits */ +#define ICSSG_CFG_SGMII_MODE BIT(16) +#define ICSSG_CFG_TX_PRU_EN BIT(11) +#define ICSSG_CFG_RX_SFD_TX_SOF_EN BIT(10) +#define ICSSG_CFG_RTU_PRU_PSI_SHARE_EN BIT(9) +#define ICSSG_CFG_IEP1_TX_EN BIT(8) +#define ICSSG_CFG_MII1_MODE GENMASK(6, 5) +#define ICSSG_CFG_MII1_MODE_SHIFT 5 +#define ICSSG_CFG_MII0_MODE GENMASK(4, 3) +#define ICSSG_CFG_MII0_MODE_SHIFT 3 +#define ICSSG_CFG_RX_L2_G_EN BIT(2) +#define ICSSG_CFG_TX_L2_EN BIT(1) +#define ICSSG_CFG_TX_L1_EN BIT(0) + +enum mii_mode { MII_MODE_MII = 0, MII_MODE_RGMII, MII_MODE_SGMII }; + +/* RGMII CFG Register bits */ +#define RGMII_CFG_INBAND_EN_MII0 BIT(16) +#define RGMII_CFG_GIG_EN_MII0 BIT(17) +#define RGMII_CFG_INBAND_EN_MII1 BIT(20) +#define RGMII_CFG_GIG_EN_MII1 BIT(21) +#define RGMII_CFG_FULL_DUPLEX_MII0 BIT(18) +#define RGMII_CFG_FULL_DUPLEX_MII1 BIT(22) +#define RGMII_CFG_SPEED_MII0 GENMASK(2, 1) +#define RGMII_CFG_SPEED_MII1 GENMASK(6, 5) +#define RGMII_CFG_SPEED_MII0_SHIFT 1 +#define RGMII_CFG_SPEED_MII1_SHIFT 5 +#define RGMII_CFG_FULLDUPLEX_MII0 BIT(3) +#define RGMII_CFG_FULLDUPLEX_MII1 BIT(7) +#define RGMII_CFG_FULLDUPLEX_MII0_SHIFT 3 +#define RGMII_CFG_FULLDUPLEX_MII1_SHIFT 7 +#define RGMII_CFG_SPEED_10M 0 +#define RGMII_CFG_SPEED_100M 1 +#define RGMII_CFG_SPEED_1G 2 + +static inline void icssg_mii_update_ipg(struct regmap *mii_rt, int mii, u32 ipg) +{ + u32 val; + + if (mii == ICSS_MII0) { + regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG0, ipg); + } else { + /* Errata workaround: IEP1 is not read by h/w unless IEP0 is written */ + regmap_read(mii_rt, PRUSS_MII_RT_TX_IPG0, &val); + regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG1, ipg); + regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG0, val); + } +} + +static inline void icssg_update_rgmii_cfg(struct regmap *miig_rt, int speed, + bool full_duplex, int slice, struct prueth *priv) +{ + u32 gig_en_mask, gig_val = 0, full_duplex_mask, full_duplex_val = 0; + u32 inband_en_mask, inband_val = 0; + + gig_en_mask = (slice == ICSS_MII0) ? RGMII_CFG_GIG_EN_MII0 : + RGMII_CFG_GIG_EN_MII1; + if (speed == SPEED_1000) + gig_val = gig_en_mask; + regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, gig_en_mask, gig_val); + + inband_en_mask = (slice == ICSS_MII0) ? RGMII_CFG_INBAND_EN_MII0 : + RGMII_CFG_INBAND_EN_MII1; + if (speed == SPEED_10 && phy_interface_is_rgmii(priv->phydev)) + inband_val = inband_en_mask; + regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, inband_en_mask, inband_val); + + full_duplex_mask = (slice == ICSS_MII0) ? RGMII_CFG_FULL_DUPLEX_MII0 : + RGMII_CFG_FULL_DUPLEX_MII1; + if (full_duplex) + full_duplex_val = full_duplex_mask; + regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, full_duplex_mask, + full_duplex_val); +} + +static inline void icssg_miig_set_interface_mode(struct regmap *miig_rt, int mii, int phy_if) +{ + u32 val, mask, shift; + + mask = mii == ICSS_MII0 ? ICSSG_CFG_MII0_MODE : ICSSG_CFG_MII1_MODE; + shift = mii == ICSS_MII0 ? ICSSG_CFG_MII0_MODE_SHIFT : ICSSG_CFG_MII1_MODE_SHIFT; + + val = MII_MODE_RGMII; + if (phy_if == PHY_INTERFACE_MODE_MII) + val = MII_MODE_MII; + + val <<= shift; + regmap_update_bits(miig_rt, ICSSG_CFG_OFFSET, mask, val); + regmap_read(miig_rt, ICSSG_CFG_OFFSET, &val); +} + +#endif /* __NET_PRUSS_MII_RT_H__ */ diff --git a/drivers/net/ti/icssg_classifier.c b/drivers/net/ti/icssg_classifier.c new file mode 100644 index 0000000000..df7383f1fa --- /dev/null +++ b/drivers/net/ti/icssg_classifier.c @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Texas Instruments ICSSG Ethernet Driver + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com/ + * + */ + +#include +#include + +#define ICSSG_NUM_CLASSIFIERS 16 +#define ICSSG_NUM_FT1_SLOTS 8 +#define ICSSG_NUM_FT3_SLOTS 16 + +#define ICSSG_NUM_CLASSIFIERS_IN_USE 1 + +/* Filter 1 - FT1 */ +#define FT1_NUM_SLOTS 8 +#define FT1_SLOT_SIZE 0x10 /* bytes */ + +/* offsets from FT1 slot base i.e. slot 1 start */ +#define FT1_DA0 0x0 +#define FT1_DA1 0x4 +#define FT1_DA0_MASK 0x8 +#define FT1_DA1_MASK 0xc + +#define FT1_N_REG(slize, n, reg) (offs[slice].ft1_slot_base + FT1_SLOT_SIZE * (n) + (reg)) + +#define FT1_LEN_MASK GENMASK(19, 16) +#define FT1_LEN_SHIFT 16 +#define FT1_LEN(len) (((len) << FT1_LEN_SHIFT) & FT1_LEN_MASK) + +#define FT1_START_MASK GENMASK(14, 0) +#define FT1_START(start) ((start) & FT1_START_MASK) + +#define FT1_MATCH_SLOT(n) (GENMASK(23, 16) & (BIT(n) << 16)) + +enum ft1_cfg_type { + FT1_CFG_TYPE_DISABLED = 0, + FT1_CFG_TYPE_EQ, + FT1_CFG_TYPE_GT, + FT1_CFG_TYPE_LT, +}; + +#define FT1_CFG_SHIFT(n) (2 * (n)) +#define FT1_CFG_MASK(n) (0x3 << FT1_CFG_SHIFT((n))) + +/* Filter 3 - FT3 */ +#define FT3_NUM_SLOTS 16 +#define FT3_SLOT_SIZE 0x20 /* bytes */ + +/* offsets from FT3 slot n's base */ +#define FT3_START 0 +#define FT3_START_AUTO 0x4 +#define FT3_START_OFFSET 0x8 +#define FT3_JUMP_OFFSET 0xc +#define FT3_LEN 0x10 +#define FT3_CFG 0x14 +#define FT3_T 0x18 +#define FT3_T_MASK 0x1c + +#define FT3_N_REG(slize, n, reg) \ + (offs[slice].ft3_slot_base + FT3_SLOT_SIZE * (n) + (reg)) + +/* offsets from rx_class n's base */ +#define RX_CLASS_AND_EN 0 +#define RX_CLASS_OR_EN 0x4 + +#define RX_CLASS_NUM_SLOTS 16 +#define RX_CLASS_EN_SIZE 0x8 /* bytes */ + +#define RX_CLASS_N_REG(slice, n, reg) \ + (offs[slice].rx_class_base + RX_CLASS_EN_SIZE * (n) + (reg)) + +/* RX Class Gates */ +#define RX_CLASS_GATES_SIZE 0x4 /* bytes */ + +#define RX_CLASS_GATES_N_REG(slice, n) \ + (offs[slice].rx_class_gates_base + RX_CLASS_GATES_SIZE * (n)) + +#define RX_CLASS_GATES_ALLOW_MASK BIT(6) +#define RX_CLASS_GATES_RAW_MASK BIT(5) +#define RX_CLASS_GATES_PHASE_MASK BIT(4) + +/* RX Class traffic data matching bits */ +#define RX_CLASS_FT_UC BIT(31) +#define RX_CLASS_FT_MC BIT(30) +#define RX_CLASS_FT_BC BIT(29) +#define RX_CLASS_FT_FW BIT(28) +#define RX_CLASS_FT_RCV BIT(27) +#define RX_CLASS_FT_VLAN BIT(26) +#define RX_CLASS_FT_DA_P BIT(25) +#define RX_CLASS_FT_DA_I BIT(24) +#define RX_CLASS_FT_FT1_MATCH_MASK GENMASK(23, 16) +#define RX_CLASS_FT_FT1_MATCH_SHIFT 16 +#define RX_CLASS_FT_FT3_MATCH_MASK GENMASK(15, 0) +#define RX_CLASS_FT_FT3_MATCH_SHIFT 0 + +#define RX_CLASS_FT_FT1_MATCH(slot) \ + ((BIT(slot) << RX_CLASS_FT_FT1_MATCH_SHIFT) & \ + RX_CLASS_FT_FT1_MATCH_MASK) + +enum rx_class_sel_type { + RX_CLASS_SEL_TYPE_OR = 0, + RX_CLASS_SEL_TYPE_AND = 1, + RX_CLASS_SEL_TYPE_OR_AND_AND = 2, + RX_CLASS_SEL_TYPE_OR_OR_AND = 3, +}; + +#define FT1_CFG_SHIFT(n) (2 * (n)) +#define FT1_CFG_MASK(n) (0x3 << FT1_CFG_SHIFT((n))) + +#define RX_CLASS_SEL_SHIFT(n) (2 * (n)) +#define RX_CLASS_SEL_MASK(n) (0x3 << RX_CLASS_SEL_SHIFT((n))) + +#define ICSSG_CFG_OFFSET 0 +#define MAC_INTERFACE_0 0x18 +#define MAC_INTERFACE_1 0x1c + +#define ICSSG_CFG_RX_L2_G_EN BIT(2) + +/* these are register offsets per PRU */ +struct miig_rt_offsets { + u32 mac0; + u32 mac1; + u32 ft1_start_len; + u32 ft1_cfg; + u32 ft1_slot_base; + u32 ft3_slot_base; + u32 ft3_p_base; + u32 ft_rx_ptr; + u32 rx_class_base; + u32 rx_class_cfg1; + u32 rx_class_cfg2; + u32 rx_class_gates_base; + u32 rx_green; + u32 rx_rate_cfg_base; + u32 rx_rate_src_sel0; + u32 rx_rate_src_sel1; + u32 tx_rate_cfg_base; + u32 stat_base; + u32 tx_hsr_tag; + u32 tx_hsr_seq; + u32 tx_vlan_type; + u32 tx_vlan_ins; +}; + +static struct miig_rt_offsets offs[] = { + /* PRU0 */ + { + 0x8, + 0xc, + 0x80, + 0x84, + 0x88, + 0x108, + 0x308, + 0x408, + 0x40c, + 0x48c, + 0x490, + 0x494, + 0x4d4, + 0x4e4, + 0x504, + 0x508, + 0x50c, + 0x54c, + 0x63c, + 0x640, + 0x644, + 0x648, + }, + /* PRU1 */ + { + 0x10, + 0x14, + 0x64c, + 0x650, + 0x654, + 0x6d4, + 0x8d4, + 0x9d4, + 0x9d8, + 0xa58, + 0xa5c, + 0xa60, + 0xaa0, + 0xab0, + 0xad0, + 0xad4, + 0xad8, + 0xb18, + 0xc08, + 0xc0c, + 0xc10, + 0xc14, + }, +}; + +static inline u32 addr_to_da0(const u8 *addr) +{ + return (u32)(addr[0] | addr[1] << 8 | + addr[2] << 16 | addr[3] << 24); +}; + +static inline u32 addr_to_da1(const u8 *addr) +{ + return (u32)(addr[4] | addr[5] << 8); +}; + +static void rx_class_ft1_set_start_len(struct regmap *miig_rt, int slice, + u16 start, u8 len) +{ + u32 offset, val; + + offset = offs[slice].ft1_start_len; + val = FT1_LEN(len) | FT1_START(start); + regmap_write(miig_rt, offset, val); +} + +static void rx_class_ft1_set_da(struct regmap *miig_rt, int slice, + int n, const u8 *addr) +{ + u32 offset; + + offset = FT1_N_REG(slice, n, FT1_DA0); + regmap_write(miig_rt, offset, addr_to_da0(addr)); + offset = FT1_N_REG(slice, n, FT1_DA1); + regmap_write(miig_rt, offset, addr_to_da1(addr)); +} + +static void rx_class_ft1_set_da_mask(struct regmap *miig_rt, int slice, + int n, const u8 *addr) +{ + u32 offset; + + offset = FT1_N_REG(slice, n, FT1_DA0_MASK); + regmap_write(miig_rt, offset, addr_to_da0(addr)); + offset = FT1_N_REG(slice, n, FT1_DA1_MASK); + regmap_write(miig_rt, offset, addr_to_da1(addr)); +} + +static void rx_class_ft1_cfg_set_type(struct regmap *miig_rt, int slice, int n, + enum ft1_cfg_type type) +{ + u32 offset; + + offset = offs[slice].ft1_cfg; + regmap_update_bits(miig_rt, offset, FT1_CFG_MASK(n), + type << FT1_CFG_SHIFT(n)); +} + +static void rx_class_sel_set_type(struct regmap *miig_rt, int slice, int n, + enum rx_class_sel_type type) +{ + u32 offset; + + offset = offs[slice].rx_class_cfg1; + regmap_update_bits(miig_rt, offset, RX_CLASS_SEL_MASK(n), + type << RX_CLASS_SEL_SHIFT(n)); +} + +static void rx_class_set_and(struct regmap *miig_rt, int slice, int n, + u32 data) +{ + u32 offset; + + offset = RX_CLASS_N_REG(slice, n, RX_CLASS_AND_EN); + regmap_write(miig_rt, offset, data); +} + +static void rx_class_set_or(struct regmap *miig_rt, int slice, int n, + u32 data) +{ + u32 offset; + + offset = RX_CLASS_N_REG(slice, n, RX_CLASS_OR_EN); + regmap_write(miig_rt, offset, data); +} + +void icssg_class_set_host_mac_addr(struct regmap *miig_rt, u8 *mac) +{ + regmap_write(miig_rt, MAC_INTERFACE_0, addr_to_da0(mac)); + regmap_write(miig_rt, MAC_INTERFACE_1, addr_to_da1(mac)); +} + +void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac) +{ + regmap_write(miig_rt, offs[slice].mac0, addr_to_da0(mac)); + regmap_write(miig_rt, offs[slice].mac1, addr_to_da1(mac)); +} + +void icssg_class_disable_n(struct regmap *miig_rt, int slice, int n) +{ + u32 data, offset; + + /* AND_EN = 0 */ + rx_class_set_and(miig_rt, slice, n, 0); + /* OR_EN = 0 */ + rx_class_set_or(miig_rt, slice, n, 0); + + /* set CFG1 to OR */ + rx_class_sel_set_type(miig_rt, slice, n, RX_CLASS_SEL_TYPE_OR); + + /* configure gate */ + offset = RX_CLASS_GATES_N_REG(slice, n); + regmap_read(miig_rt, offset, &data); + /* clear class_raw so we go through filters */ + data &= ~RX_CLASS_GATES_RAW_MASK; + /* set allow and phase mask */ + data |= RX_CLASS_GATES_ALLOW_MASK | RX_CLASS_GATES_PHASE_MASK; + regmap_write(miig_rt, offset, data); +} + +/* disable all RX traffic */ +void icssg_class_disable(struct regmap *miig_rt, int slice) +{ + int n; + + /* Enable RX_L2_G */ + regmap_update_bits(miig_rt, ICSSG_CFG_OFFSET, ICSSG_CFG_RX_L2_G_EN, + ICSSG_CFG_RX_L2_G_EN); + + for (n = 0; n < ICSSG_NUM_CLASSIFIERS; n++) + icssg_class_disable_n(miig_rt, slice, n); + + /* FT1 Disabled */ + for (n = 0; n < ICSSG_NUM_FT1_SLOTS; n++) { + u8 addr[] = { 0, 0, 0, 0, 0, 0, }; + + rx_class_ft1_cfg_set_type(miig_rt, slice, n, + FT1_CFG_TYPE_DISABLED); + rx_class_ft1_set_da(miig_rt, slice, n, addr); + rx_class_ft1_set_da_mask(miig_rt, slice, n, addr); + } + + /* clear CFG2 */ + regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0); +} + +void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti) +{ + u32 data; + + /* defaults */ + icssg_class_disable(miig_rt, slice); + + /* Setup Classifier */ + /* match on Broadcast or MAC_PRU address */ + data = RX_CLASS_FT_BC | RX_CLASS_FT_DA_P; + + /* multicast? */ + if (allmulti) + data |= RX_CLASS_FT_MC; + + rx_class_set_or(miig_rt, slice, 0, data); + + /* set CFG1 for OR_OR_AND for classifier */ + rx_class_sel_set_type(miig_rt, slice, 0, + RX_CLASS_SEL_TYPE_OR_OR_AND); + + /* clear CFG2 */ + regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0); +} + +/* required for SR2 for SAV check */ +void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr) +{ + u8 mask_addr[] = { 0, 0, 0, 0, 0, 0, }; + + rx_class_ft1_set_start_len(miig_rt, slice, 6, 6); + rx_class_ft1_set_da(miig_rt, slice, 0, mac_addr); + rx_class_ft1_set_da_mask(miig_rt, slice, 0, mask_addr); + rx_class_ft1_cfg_set_type(miig_rt, slice, 0, FT1_CFG_TYPE_EQ); +} diff --git a/drivers/net/ti/icssg_config.c b/drivers/net/ti/icssg_config.c new file mode 100644 index 0000000000..a21d2d17ce --- /dev/null +++ b/drivers/net/ti/icssg_config.c @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: GPL-2.0 +/* ICSSG Ethernet driver + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com + */ + +#include +#include "icssg_prueth.h" +#include "icssg_switch_map.h" +#include "icss_mii_rt.h" +#include + +/* TX IPG Values to be set for 100M and 1G link speeds. These values are + * in ocp_clk cycles. So need change if ocp_clk is changed for a specific + * h/w design. + */ + +/* SR2.0 IPG is in rgmii_clk (125MHz) clock cycles + 1 */ +#define MII_RT_TX_IPG_100M 0x17 +#define MII_RT_TX_IPG_1G 0xb + +#define ICSSG_QUEUES_MAX 64 +#define ICSSG_QUEUE_OFFSET 0xd00 +#define ICSSG_QUEUE_PEEK_OFFSET 0xe00 +#define ICSSG_QUEUE_CNT_OFFSET 0xe40 +#define ICSSG_QUEUE_RESET_OFFSET 0xf40 + +#define ICSSG_NUM_TX_QUEUES 8 + +#define RECYCLE_Q_SLICE0 16 +#define RECYCLE_Q_SLICE1 17 + +#define ICSSG_NUM_OTHER_QUEUES 5 /* port, host and special queues */ + +#define PORT_HI_Q_SLICE0 32 +#define PORT_LO_Q_SLICE0 33 +#define HOST_HI_Q_SLICE0 34 +#define HOST_LO_Q_SLICE0 35 +#define HOST_SPL_Q_SLICE0 40 /* Special Queue */ + +#define PORT_HI_Q_SLICE1 36 +#define PORT_LO_Q_SLICE1 37 +#define HOST_HI_Q_SLICE1 38 +#define HOST_LO_Q_SLICE1 39 +#define HOST_SPL_Q_SLICE1 41 /* Special Queue */ + +#define MII_RXCFG_DEFAULT (PRUSS_MII_RT_RXCFG_RX_ENABLE | \ + PRUSS_MII_RT_RXCFG_RX_DATA_RDY_MODE_DIS | \ + PRUSS_MII_RT_RXCFG_RX_L2_EN | \ + PRUSS_MII_RT_RXCFG_RX_L2_EOF_SCLR_DIS) + +#define MII_TXCFG_DEFAULT (PRUSS_MII_RT_TXCFG_TX_ENABLE | \ + PRUSS_MII_RT_TXCFG_TX_AUTO_PREAMBLE | \ + PRUSS_MII_RT_TXCFG_TX_32_MODE_EN | \ + PRUSS_MII_RT_TXCFG_TX_IPG_WIRE_CLK_EN) + +#define ICSSG_CFG_DEFAULT (ICSSG_CFG_TX_L1_EN | \ + ICSSG_CFG_TX_L2_EN | ICSSG_CFG_RX_L2_G_EN | \ + ICSSG_CFG_TX_PRU_EN | /* SR2.0 only */ \ + ICSSG_CFG_SGMII_MODE) + +#define FDB_GEN_CFG1 0x60 +#define SMEM_VLAN_OFFSET 8 +#define SMEM_VLAN_OFFSET_MASK GENMASK(25, 8) + +#define FDB_GEN_CFG2 0x64 +#define FDB_VLAN_EN BIT(6) +#define FDB_HOST_EN BIT(2) +#define FDB_PRU1_EN BIT(1) +#define FDB_PRU0_EN BIT(0) +#define FDB_EN_ALL (FDB_PRU0_EN | FDB_PRU1_EN | \ + FDB_HOST_EN | FDB_VLAN_EN) + +struct map { + int queue; + u32 pd_addr_start; + u32 flags; + bool special; +}; + +struct map hwq_map[2][ICSSG_NUM_OTHER_QUEUES] = { + { + { PORT_HI_Q_SLICE0, PORT_DESC0_HI, 0x200000, 0 }, + { PORT_LO_Q_SLICE0, PORT_DESC0_LO, 0, 0 }, + { HOST_HI_Q_SLICE0, HOST_DESC0_HI, 0x200000, 0 }, + { HOST_LO_Q_SLICE0, HOST_DESC0_LO, 0, 0 }, + { HOST_SPL_Q_SLICE0, HOST_SPPD0, 0x400000, 1 }, + }, + { + { PORT_HI_Q_SLICE1, PORT_DESC1_HI, 0xa00000, 0 }, + { PORT_LO_Q_SLICE1, PORT_DESC1_LO, 0x800000, 0 }, + { HOST_HI_Q_SLICE1, HOST_DESC1_HI, 0xa00000, 0 }, + { HOST_LO_Q_SLICE1, HOST_DESC1_LO, 0x800000, 0 }, + { HOST_SPL_Q_SLICE1, HOST_SPPD1, 0xc00000, 1 }, + }, +}; + +static void icssg_config_mii_init(struct prueth *prueth, int slice) +{ + struct regmap *mii_rt = prueth->mii_rt; + u32 txcfg_reg, pcnt_reg; + u32 txcfg; + + txcfg_reg = (slice == ICSS_MII0) ? PRUSS_MII_RT_TXCFG0 : + PRUSS_MII_RT_TXCFG1; + pcnt_reg = (slice == ICSS_MII0) ? PRUSS_MII_RT_RX_PCNT0 : + PRUSS_MII_RT_RX_PCNT1; + + txcfg = MII_TXCFG_DEFAULT; + + if (prueth->phy_interface == PHY_INTERFACE_MODE_MII && slice == ICSS_MII0) + txcfg |= PRUSS_MII_RT_TXCFG_TX_MUX_SEL; + else if (prueth->phy_interface != PHY_INTERFACE_MODE_MII && slice == ICSS_MII1) + txcfg |= PRUSS_MII_RT_TXCFG_TX_MUX_SEL; + + regmap_write(mii_rt, txcfg_reg, txcfg); + regmap_write(mii_rt, pcnt_reg, 0x1); +} + +static void icssg_miig_queues_init(struct prueth *prueth, int slice) +{ + void __iomem *smem = (void __iomem *)prueth->shram.pa; + struct regmap *miig_rt = prueth->miig_rt; + int queue = 0, i, j; + u8 pd[ICSSG_SPECIAL_PD_SIZE]; + u32 *pdword; + + /* reset hwqueues */ + if (slice) + queue = ICSSG_NUM_TX_QUEUES; + + for (i = 0; i < ICSSG_NUM_TX_QUEUES; i++) { + regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, queue); + queue++; + } + + queue = slice ? RECYCLE_Q_SLICE1 : RECYCLE_Q_SLICE0; + regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, queue); + + for (i = 0; i < ICSSG_NUM_OTHER_QUEUES; i++) { + regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, + hwq_map[slice][i].queue); + } + + /* initialize packet descriptors in SMEM */ + /* push pakcet descriptors to hwqueues */ + + pdword = (u32 *)pd; + for (j = 0; j < ICSSG_NUM_OTHER_QUEUES; j++) { + struct map *mp; + int pd_size, num_pds; + u32 pdaddr; + + mp = &hwq_map[slice][j]; + if (mp->special) { + pd_size = ICSSG_SPECIAL_PD_SIZE; + num_pds = ICSSG_NUM_SPECIAL_PDS; + } else { + pd_size = ICSSG_NORMAL_PD_SIZE; + num_pds = ICSSG_NUM_NORMAL_PDS; + } + + for (i = 0; i < num_pds; i++) { + memset(pd, 0, pd_size); + + pdword[0] &= cpu_to_le32(ICSSG_FLAG_MASK); + pdword[0] |= cpu_to_le32(mp->flags); + pdaddr = mp->pd_addr_start + i * pd_size; + + memcpy_toio(smem + pdaddr, pd, pd_size); + queue = mp->queue; + regmap_write(miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, + pdaddr); + } + } +} + +void icssg_config_ipg(struct prueth *prueth, int speed, int mii) +{ + switch (speed) { + case SPEED_1000: + icssg_mii_update_ipg(prueth->mii_rt, mii, MII_RT_TX_IPG_1G); + break; + case SPEED_100: + icssg_mii_update_ipg(prueth->mii_rt, mii, MII_RT_TX_IPG_100M); + break; + default: + /* Other links speeds not supported */ + pr_err("Unsupported link speed\n"); + return; + } +} + +static void emac_r30_cmd_init(struct prueth *prueth) +{ + int i; + struct icssg_r30_cmd *p; + + p = (struct icssg_r30_cmd *)(prueth->dram.pa + MGR_R30_CMD_OFFSET); + + for (i = 0; i < 4; i++) + writel(EMAC_NONE, &p->cmd[i]); +} + +static int emac_r30_is_done(struct prueth *prueth) +{ + const struct icssg_r30_cmd *p; + int i; + u32 cmd; + + p = (const struct icssg_r30_cmd *)(prueth->dram.pa + MGR_R30_CMD_OFFSET); + + for (i = 0; i < 4; i++) { + cmd = readl(&p->cmd[i]); + if (cmd != EMAC_NONE) + return 0; + } + + return 1; +} + +static int prueth_emac_buffer_setup(struct prueth *prueth) +{ + struct icssg_buffer_pool_cfg *bpool_cfg; + struct icssg_rxq_ctx *rxq_ctx; + int slice = prueth->slice; + u32 addr; + int i; + + /* Layout to have 64KB aligned buffer pool + * |BPOOL0|BPOOL1|RX_CTX0|RX_CTX1| + */ + + addr = lower_32_bits(prueth->sram_pa); + if (slice) + addr += PRUETH_NUM_BUF_POOLS * PRUETH_EMAC_BUF_POOL_SIZE; + + if (addr % SZ_64K) { + dev_warn(prueth->dev, "buffer pool needs to be 64KB aligned\n"); + return -EINVAL; + } + + bpool_cfg = (struct icssg_buffer_pool_cfg *)(prueth->dram.pa + BUFFER_POOL_0_ADDR_OFFSET); + /* workaround for f/w bug. bpool 0 needs to be initilalized */ + bpool_cfg[0].addr = cpu_to_le32(addr); + bpool_cfg[0].len = 0; + + for (i = PRUETH_EMAC_BUF_POOL_START; + i < (PRUETH_EMAC_BUF_POOL_START + PRUETH_NUM_BUF_POOLS); + i++) { + bpool_cfg[i].addr = cpu_to_le32(addr); + bpool_cfg[i].len = cpu_to_le32(PRUETH_EMAC_BUF_POOL_SIZE); + addr += PRUETH_EMAC_BUF_POOL_SIZE; + } + + if (!slice) + addr += PRUETH_NUM_BUF_POOLS * PRUETH_EMAC_BUF_POOL_SIZE; + else + addr += PRUETH_EMAC_RX_CTX_BUF_SIZE * 2; + + rxq_ctx = (struct icssg_rxq_ctx *)(prueth->dram.pa + HOST_RX_Q_PRE_CONTEXT_OFFSET); + + for (i = 0; i < 3; i++) + rxq_ctx->start[i] = cpu_to_le32(addr); + + addr += PRUETH_EMAC_RX_CTX_BUF_SIZE; + rxq_ctx->end = cpu_to_le32(addr); + + /* Express RX buffer queue */ + rxq_ctx = (struct icssg_rxq_ctx *)(prueth->dram.pa + HOST_RX_Q_EXP_CONTEXT_OFFSET); + for (i = 0; i < 3; i++) + rxq_ctx->start[i] = cpu_to_le32(addr); + + addr += PRUETH_EMAC_RX_CTX_BUF_SIZE; + rxq_ctx->end = cpu_to_le32(addr); + + return 0; +} + +static void icssg_init_emac_mode(struct prueth *prueth) +{ + u8 mac[6] = { 0 }; + + regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, SMEM_VLAN_OFFSET_MASK, 0); + regmap_write(prueth->miig_rt, FDB_GEN_CFG2, 0); + /* Clear host MAC address */ + icssg_class_set_host_mac_addr(prueth->miig_rt, mac); +} + +int icssg_config(struct prueth *prueth) +{ + void *config = (void *)(prueth->dram.pa + ICSSG_CONFIG_OFFSET); + u8 *cfg_byte_ptr = config; + struct icssg_flow_cfg *flow_cfg; + u32 mask; + int ret; + + int slice = prueth->slice; + + icssg_init_emac_mode(prueth); + + memset_io(config, 0, TAS_GATE_MASK_LIST0); + icssg_miig_queues_init(prueth, slice); + + prueth->speed = SPEED_1000; + prueth->duplex = DUPLEX_FULL; + if (!phy_interface_is_rgmii(prueth->phydev)) { + prueth->speed = SPEED_100; + prueth->duplex = DUPLEX_FULL; + } + + regmap_update_bits(prueth->miig_rt, ICSSG_CFG_OFFSET, + ICSSG_CFG_DEFAULT, ICSSG_CFG_DEFAULT); + icssg_miig_set_interface_mode(prueth->miig_rt, ICSS_MII0, prueth->phy_interface); + icssg_miig_set_interface_mode(prueth->miig_rt, ICSS_MII1, prueth->phy_interface); + icssg_config_mii_init(prueth, slice); + + icssg_config_ipg(prueth, SPEED_1000, slice); + icssg_update_rgmii_cfg(prueth->miig_rt, SPEED_1000, true, slice, prueth); + + /* set GPI mode */ + pruss_cfg_gpimode(prueth->pruss, slice, PRUSS_GPI_MODE_MII); + + /* enable XFR shift for PRU and RTU */ + mask = PRUSS_SPP_XFER_SHIFT_EN | PRUSS_SPP_RTU_XFR_SHIFT_EN; + pruss_cfg_update(prueth->pruss, PRUSS_CFG_SPP, mask, mask); + + flow_cfg = config + PSI_L_REGULAR_FLOW_ID_BASE_OFFSET; + flow_cfg->rx_base_flow = prueth->dma_rx.id; + flow_cfg->mgm_base_flow = 0; + *(cfg_byte_ptr + SPL_PKT_DEFAULT_PRIORITY) = 0; + *(cfg_byte_ptr + QUEUE_NUM_UNTAGGED) = 0x0; + + ret = prueth_emac_buffer_setup(prueth); + + if (ret) + return ret; + + emac_r30_cmd_init(prueth); + return 0; +} + +/* commands to program ICSSG R30 registers */ +static struct icssg_r30_cmd emac_r32_bitmask[] = { + {{0xffff0004, 0xffff0100, 0xffff0004, EMAC_NONE}}, /* EMAC_PORT_DISABLE */ + {{0xfffb0040, 0xfeff0200, 0xfeff0200, EMAC_NONE}}, /* EMAC_PORT_BLOCK */ + {{0xffbb0000, 0xfcff0000, 0xdcfb0000, EMAC_NONE}}, /* EMAC_PORT_FORWARD */ + {{0xffbb0000, 0xfcff0000, 0xfcff2000, EMAC_NONE}}, /* EMAC_PORT_FORWARD_WO_LEARNING */ + {{0xffff0001, EMAC_NONE, EMAC_NONE, EMAC_NONE}}, /* ACCEPT ALL */ + {{0xfffe0002, EMAC_NONE, EMAC_NONE, EMAC_NONE}}, /* ACCEPT TAGGED */ + {{0xfffc0000, EMAC_NONE, EMAC_NONE, EMAC_NONE}}, /* ACCEPT UNTAGGED and PRIO */ + {{EMAC_NONE, 0xffff0020, EMAC_NONE, EMAC_NONE}}, /* TAS Trigger List change */ + {{EMAC_NONE, 0xdfff1000, EMAC_NONE, EMAC_NONE}}, /* TAS set state ENABLE*/ + {{EMAC_NONE, 0xefff2000, EMAC_NONE, EMAC_NONE}}, /* TAS set state RESET*/ + {{EMAC_NONE, 0xcfff0000, EMAC_NONE, EMAC_NONE}}, /* TAS set state DISABLE*/ + {{EMAC_NONE, EMAC_NONE, 0xffff0400, EMAC_NONE}}, /* UC flooding ENABLE*/ + {{EMAC_NONE, EMAC_NONE, 0xfbff0000, EMAC_NONE}}, /* UC flooding DISABLE*/ + {{EMAC_NONE, EMAC_NONE, 0xffff0800, EMAC_NONE}}, /* MC flooding ENABLE*/ + {{EMAC_NONE, EMAC_NONE, 0xf7ff0000, EMAC_NONE}}, /* MC flooding DISABLE*/ + {{EMAC_NONE, 0xffff4000, EMAC_NONE, EMAC_NONE}}, /* Preemption on Tx ENABLE*/ + {{EMAC_NONE, 0xbfff0000, EMAC_NONE, EMAC_NONE}} /* Preemption on Tx DISABLE*/ +}; + +int emac_set_port_state(struct prueth *prueth, + enum icssg_port_state_cmd cmd) +{ + struct icssg_r30_cmd *p; + int ret = -ETIMEDOUT; + int timeout = 10; + int i; + + p = (struct icssg_r30_cmd *)(prueth->dram.pa + MGR_R30_CMD_OFFSET); + + if (cmd >= ICSSG_EMAC_PORT_MAX_COMMANDS) { + dev_err(prueth->dev, "invalid port command\n"); + return -EINVAL; + } + + for (i = 0; i < 4; i++) + writel(emac_r32_bitmask[cmd].cmd[i], &p->cmd[i]); + + /* wait for done */ + while (timeout) { + if (emac_r30_is_done(prueth)) { + ret = 0; + break; + } + + udelay(2000); + timeout--; + } + + if (ret == -ETIMEDOUT) + dev_err(prueth->dev, "timeout waiting for command done\n"); + + return ret; +} diff --git a/drivers/net/ti/icssg_config.h b/drivers/net/ti/icssg_config.h new file mode 100644 index 0000000000..412dbf51c7 --- /dev/null +++ b/drivers/net/ti/icssg_config.h @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Texas Instruments ICSSG Ethernet driver + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com/ + * + */ + +#ifndef __NET_TI_ICSSG_CONFIG_H +#define __NET_TI_ICSSG_CONFIG_H + +struct icssg_buffer_pool_cfg { + __le32 addr; + __le32 len; +} __packed; + +struct icssg_flow_cfg { + __le16 rx_base_flow; + __le16 mgm_base_flow; +} __packed; + +/* Config area lies in shared RAM */ +#define ICSSG_CONFIG_OFFSET_SLICE0 0 +#define ICSSG_CONFIG_OFFSET_SLICE1 0x8000 + +/* pstate speed/duplex command to set speed and duplex settings + * in firmware. + * Command format : 0x8102ssPN. ss - sequence number: currently not + * used by driver, P - port number: For switch, N - Speed/Duplex state + * - Possible values of N: + * 0x0 - 10Mbps/Half duplex ; + * 0x8 - 10Mbps/Full duplex ; + * 0x2 - 100Mbps/Half duplex; + * 0xa - 100Mbps/Full duplex; + * 0xc - 1Gbps/Full duplex; + * NOTE: The above are same as bits [3..1](slice 0) or bits [8..6](slice 1) of + * RGMII CFG register. So suggested to read the register to populate the command + * bits. + */ +#define ICSSG_PSTATE_SPEED_DUPLEX_CMD 0x81020000 +#define ICSSG_PSTATE_FULL_DUPLEX BIT(3) +#define ICSSG_PSTATE_SPEED_100 BIT(1) +#define ICSSG_PSTATE_SPEED_1000 BIT(2) + +/* Flow IDs used in config structure to firmware. Should match with + * flow_id in struct dma for rx channels. + */ +#define ICSSG_RX_CHAN_FLOW_ID 0 /* flow id for host port */ +#define ICSSG_RX_MGM_CHAN_FLOW_ID 1 /* flow id for command response */ + +/* Used to notify the FW of the current link speed */ +#define PORT_LINK_SPEED_OFFSET 0x00A8 + +#define FW_LINK_SPEED_1G (0x00) +#define FW_LINK_SPEED_100M (0x01) +#define FW_LINK_SPEED_10M (0x02) +#define FW_LINK_SPEED_HD (0x80) + +#define PRUETH_PKT_TYPE_CMD 0x10 +#define PRUETH_NAV_PS_DATA_SIZE 16 /* Protocol specific data size */ +#define PRUETH_NAV_SW_DATA_SIZE 16 /* SW related data size */ +#define PRUETH_MAX_RX_FLOWS 1 /* excluding default flow */ +#define PRUETH_RX_FLOW_DATA 0 /* FIXME: f/w bug to change to highest priority flow */ + +#define PRUETH_EMAC_BUF_POOL_SIZE SZ_8K +#define PRUETH_EMAC_POOLS_PER_SLICE 24 +#define PRUETH_EMAC_BUF_POOL_START 8 +#define PRUETH_NUM_BUF_POOLS 8 +#define PRUETH_EMAC_RX_CTX_BUF_SIZE SZ_16K /* per slice */ +#define MSMC_RAM_SIZE (2 * (PRUETH_EMAC_BUF_POOL_SIZE * PRUETH_NUM_BUF_POOLS + \ + PRUETH_EMAC_RX_CTX_BUF_SIZE)) + +struct icssg_rxq_ctx { + __le32 start[3]; + __le32 end; +} __packed; + +/* Load time Fiwmware Configuration */ + +#define ICSSG_FW_MGMT_CMD_HEADER 0x81 +#define ICSSG_FW_MGMT_FDB_CMD_TYPE 0x03 +#define ICSSG_FW_MGMT_CMD_TYPE 0x04 +#define ICSSG_FW_MGMT_PKT 0x80000000 + +struct icssg_r30_cmd { + u32 cmd[4]; +} __packed; + +enum icssg_port_state_cmd { + ICSSG_EMAC_PORT_DISABLE = 0, + ICSSG_EMAC_PORT_BLOCK, + ICSSG_EMAC_PORT_FORWARD, + ICSSG_EMAC_PORT_FORWARD_WO_LEARNING, + ICSSG_EMAC_PORT_ACCEPT_ALL, + ICSSG_EMAC_PORT_ACCEPT_TAGGED, + ICSSG_EMAC_PORT_ACCEPT_UNTAGGED_N_PRIO, + ICSSG_EMAC_PORT_TAS_TRIGGER, + ICSSG_EMAC_PORT_TAS_ENABLE, + ICSSG_EMAC_PORT_TAS_RESET, + ICSSG_EMAC_PORT_TAS_DISABLE, + ICSSG_EMAC_PORT_UC_FLOODING_ENABLE, + ICSSG_EMAC_PORT_UC_FLOODING_DISABLE, + ICSSG_EMAC_PORT_MC_FLOODING_ENABLE, + ICSSG_EMAC_PORT_MC_FLOODING_DISABLE, + ICSSG_EMAC_PORT_PREMPT_TX_ENABLE, + ICSSG_EMAC_PORT_PREMPT_TX_DISABLE, + ICSSG_EMAC_PORT_MAX_COMMANDS +}; + +#define EMAC_NONE 0xffff0000 +#define EMAC_PRU0_P_DI 0xffff0004 +#define EMAC_PRU1_P_DI 0xffff0040 +#define EMAC_TX_P_DI 0xffff0100 + +#define EMAC_PRU0_P_EN 0xfffb0000 +#define EMAC_PRU1_P_EN 0xffbf0000 +#define EMAC_TX_P_EN 0xfeff0000 + +#define EMAC_P_BLOCK 0xffff0040 +#define EMAC_TX_P_BLOCK 0xffff0200 +#define EMAC_P_UNBLOCK 0xffbf0000 +#define EMAC_TX_P_UNBLOCK 0xfdff0000 +#define EMAC_LEAN_EN 0xfff70000 +#define EMAC_LEAN_DI 0xffff0008 + +#define EMAC_ACCEPT_ALL 0xffff0001 +#define EMAC_ACCEPT_TAG 0xfffe0002 +#define EMAC_ACCEPT_PRIOR 0xfffc0000 + +/* Config area lies in DRAM */ +#define ICSSG_CONFIG_OFFSET 0x0 + +#define ICSSG_NUM_NORMAL_PDS 64 +#define ICSSG_NUM_SPECIAL_PDS 16 + +#define ICSSG_NORMAL_PD_SIZE 8 +#define ICSSG_SPECIAL_PD_SIZE 20 + +#define ICSSG_FLAG_MASK 0xff00ffff + +struct icssg_setclock_desc { + u8 request; + u8 restore; + u8 acknowledgment; + u8 cmp_status; + u32 margin; + u32 cyclecounter0_set; + u32 cyclecounter1_set; + u32 iepcount_set; + u32 rsvd1; + u32 rsvd2; + u32 CMP0_current; + u32 iepcount_current; + u32 difference; + u32 cyclecounter0_new; + u32 cyclecounter1_new; + u32 CMP0_new; +} __packed; + +#define ICSSG_CMD_POP_SLICE0 56 +#define ICSSG_CMD_POP_SLICE1 60 + +#define ICSSG_CMD_PUSH_SLICE0 57 +#define ICSSG_CMD_PUSH_SLICE1 61 + +#define ICSSG_RSP_POP_SLICE0 58 +#define ICSSG_RSP_POP_SLICE1 62 + +#define ICSSG_RSP_PUSH_SLICE0 56 +#define ICSSG_RSP_PUSH_SLICE1 60 + +#define ICSSG_TS_POP_SLICE0 59 +#define ICSSG_TS_POP_SLICE1 63 + +#define ICSSG_TS_PUSH_SLICE0 40 +#define ICSSG_TS_PUSH_SLICE1 41 + +#endif /* __NET_TI_ICSSG_CONFIG_H */ diff --git a/drivers/net/ti/icssg_prueth.h b/drivers/net/ti/icssg_prueth.h new file mode 100644 index 0000000000..c902a6eb87 --- /dev/null +++ b/drivers/net/ti/icssg_prueth.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com/ + * + */ + +#ifndef __NET_TI_ICSSG_PRUETH_H +#define __NET_TI_ICSSG_PRUETH_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "icssg_config.h" +#include "icssg_switch_map.h" + +void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac); +void icssg_class_set_host_mac_addr(struct regmap *miig_rt, u8 *mac); +void icssg_class_disable(struct regmap *miig_rt, int slice); +void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti); +void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr); + +enum prueth_mac { + PRUETH_MAC0 = 0, + PRUETH_MAC1, + PRUETH_NUM_MACS, +}; + +enum prueth_port { + PRUETH_PORT_HOST = 0, /* host side port */ + PRUETH_PORT_MII0, /* physical port MII 0 */ + PRUETH_PORT_MII1, /* physical port MII 1 */ +}; + +struct prueth { + struct udevice *dev; + struct udevice *pruss; + struct regmap *miig_rt; + struct regmap *mii_rt; + fdt_addr_t mdio_base; + struct pruss_mem_region shram; + struct pruss_mem_region dram; + phys_addr_t tmaddr; + struct mii_dev *bus; + u32 port_id; + u32 sram_pa; + struct phy_device *phydev; + bool has_phy; + ofnode phy_node; + u32 phy_addr; + ofnode eth_node[PRUETH_NUM_MACS]; + u32 mdio_freq; + int phy_interface; + struct clk mdiofck; + struct dma dma_tx; + struct dma dma_rx; + struct dma dma_rx_mgm; + u32 rx_next; + u32 rx_pend; + int slice; + bool mdio_manual_mode; + int speed; + int duplex; +}; + +/* config helpers */ +void icssg_config_ipg(struct prueth *prueth, int speed, int mii); +int icssg_config(struct prueth *prueth); +int emac_set_port_state(struct prueth *prueth, enum icssg_port_state_cmd cmd); + +#endif /* __NET_TI_ICSSG_PRUETH_H */ -- cgit v1.2.3 From 5b4760df4d25088abd1a008971f6068a849935bc Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:19:51 +0530 Subject: net: ti: icssg: Add icssg queues APIs and macros Add icssg_queue.c file. This file introduces macros and APIs related to ICSSG queues. These will be used by ICSSG Ethernet driver. Signed-off-by: MD Danish Anwar --- drivers/net/ti/icssg_prueth.h | 5 +++++ drivers/net/ti/icssg_queues.c | 51 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 drivers/net/ti/icssg_queues.c diff --git a/drivers/net/ti/icssg_prueth.h b/drivers/net/ti/icssg_prueth.h index c902a6eb87..97b6b191fa 100644 --- a/drivers/net/ti/icssg_prueth.h +++ b/drivers/net/ti/icssg_prueth.h @@ -74,4 +74,9 @@ void icssg_config_ipg(struct prueth *prueth, int speed, int mii); int icssg_config(struct prueth *prueth); int emac_set_port_state(struct prueth *prueth, enum icssg_port_state_cmd cmd); +/* Buffer queue helpers */ +int icssg_queue_pop(struct prueth *prueth, u8 queue); +void icssg_queue_push(struct prueth *prueth, int queue, u16 addr); +u32 icssg_queue_level(struct prueth *prueth, int queue); + #endif /* __NET_TI_ICSSG_PRUETH_H */ diff --git a/drivers/net/ti/icssg_queues.c b/drivers/net/ti/icssg_queues.c new file mode 100644 index 0000000000..fc4d33dbb2 --- /dev/null +++ b/drivers/net/ti/icssg_queues.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* ICSSG Buffer queue helpers + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com + */ + +#include +#include +#include "icssg_prueth.h" + +#define ICSSG_QUEUES_MAX 64 +#define ICSSG_QUEUE_OFFSET 0xd00 +#define ICSSG_QUEUE_PEEK_OFFSET 0xe00 +#define ICSSG_QUEUE_CNT_OFFSET 0xe40 +#define ICSSG_QUEUE_RESET_OFFSET 0xf40 + +int icssg_queue_pop(struct prueth *prueth, u8 queue) +{ + u32 val, cnt; + + if (queue >= ICSSG_QUEUES_MAX) + return -EINVAL; + + regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, &cnt); + if (!cnt) + return -EINVAL; + + regmap_read(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, &val); + + return val; +} + +void icssg_queue_push(struct prueth *prueth, int queue, u16 addr) +{ + if (queue >= ICSSG_QUEUES_MAX) + return; + + regmap_write(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, addr); +} + +u32 icssg_queue_level(struct prueth *prueth, int queue) +{ + u32 reg; + + if (queue >= ICSSG_QUEUES_MAX) + return 0; + + regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, ®); + + return reg; +} -- cgit v1.2.3 From 9fb26e8d8971aca3698893ab0dbef9f4bf90af1b Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:19:52 +0530 Subject: net: ti: icssg: Add ICSSG ethernet driver This is the PURSS Ethernet driver for TI AM654 Sr2.0 and laterSoCs with the ICSSG PRU Sub-system running EMAC firmware. This driver caters to either of the slices of the icssg subsystem. One and exactly one of the slices is supported as the u-boot ethernet supports probing one interface at a time. Signed-off-by: MD Danish Anwar --- drivers/net/ti/Kconfig | 8 + drivers/net/ti/Makefile | 1 + drivers/net/ti/icssg_prueth.c | 781 ++++++++++++++++++++++++++++++++++++++++++ drivers/net/ti/icssg_prueth.h | 3 + 4 files changed, 793 insertions(+) create mode 100644 drivers/net/ti/icssg_prueth.c diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index 02660e4fbb..62ef8e9d89 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -49,3 +49,11 @@ config TI_AM65_CPSW_NUSS help This driver supports TI K3 MCU CPSW Nuss Ethernet controller in Texas Instruments K3 AM65x SoCs. + +config TI_ICSSG_PRUETH + bool "TI Gigabit PRU Ethernet driver" + depends on ARCH_K3 + select PHYLIB + help + Support Gigabit Ethernet ports over the ICSSG PRU Subsystem + This subsystem is available starting with the AM65 platform. diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile index 8d3808bb4b..cb54e5fc3d 100644 --- a/drivers/net/ti/Makefile +++ b/drivers/net/ti/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o obj-$(CONFIG_TI_AM65_CPSW_NUSS) += am65-cpsw-nuss.o cpsw_mdio.o +obj-$(CONFIG_TI_ICSSG_PRUETH) += icssg_prueth.o cpsw_mdio.o icssg_classifier.o icssg_config.o icssg_queues.o diff --git a/drivers/net/ti/icssg_prueth.c b/drivers/net/ti/icssg_prueth.c new file mode 100644 index 0000000000..e78584763d --- /dev/null +++ b/drivers/net/ti/icssg_prueth.c @@ -0,0 +1,781 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments K3 AM65 PRU Ethernet Driver + * + * Copyright (C) 2018-2024, Texas Instruments, Incorporated + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cpsw_mdio.h" +#include "icssg_prueth.h" +#include "icss_mii_rt.h" + +#define ICSS_SLICE0 0 +#define ICSS_SLICE1 1 + +#ifdef PKTSIZE_ALIGN +#define UDMA_RX_BUF_SIZE PKTSIZE_ALIGN +#else +#define UDMA_RX_BUF_SIZE ALIGN(1522, ARCH_DMA_MINALIGN) +#endif + +#ifdef PKTBUFSRX +#define UDMA_RX_DESC_NUM PKTBUFSRX +#else +#define UDMA_RX_DESC_NUM 4 +#endif + +/* Config region lies in shared RAM */ +#define ICSS_CONFIG_OFFSET_SLICE0 0 +#define ICSS_CONFIG_OFFSET_SLICE1 0x8000 + +/* Firmware flags */ +#define ICSS_SET_RUN_FLAG_VLAN_ENABLE BIT(0) /* switch only */ +#define ICSS_SET_RUN_FLAG_FLOOD_UNICAST BIT(1) /* switch only */ +#define ICSS_SET_RUN_FLAG_PROMISC BIT(2) /* MAC only */ +#define ICSS_SET_RUN_FLAG_MULTICAST_PROMISC BIT(3) /* MAC only */ + +/* CTRLMMR_ICSSG_RGMII_CTRL register bits */ +#define ICSSG_CTRL_RGMII_ID_MODE BIT(24) + +/* Management packet type */ +#define PRUETH_PKT_TYPE_CMD 0x10 + +/* Number of PRU Cores per Slice */ +#define ICSSG_NUM_PRU_CORES 3 + +static int icssg_phy_init(struct udevice *dev) +{ + struct prueth *priv = dev_get_priv(dev); + struct phy_device *phydev; + u32 supported = PHY_GBIT_FEATURES; + int ret; + + phydev = phy_connect(priv->bus, + priv->phy_addr, + priv->dev, + priv->phy_interface); + + if (!phydev) { + dev_err(dev, "phy_connect() failed\n"); + return -ENODEV; + } + + /* disable unsupported features */ + supported &= ~(PHY_10BT_FEATURES | + SUPPORTED_100baseT_Half | + SUPPORTED_1000baseT_Half | + SUPPORTED_Pause | + SUPPORTED_Asym_Pause); + + phydev->supported &= supported; + phydev->advertising = phydev->supported; + + if (IS_ENABLED(CONFIG_DM_ETH)) + if (ofnode_valid(priv->phy_node)) + phydev->node = priv->phy_node; + + priv->phydev = phydev; + ret = phy_config(phydev); + if (ret < 0) + pr_err("phy_config() failed: %d", ret); + + return ret; +} + +static ofnode prueth_find_mdio(ofnode parent) +{ + ofnode node; + + ofnode_for_each_subnode(node, parent) + if (ofnode_device_is_compatible(node, "ti,davinci_mdio")) + return node; + + return ofnode_null(); +} + +static int prueth_mdio_setup(struct udevice *dev) +{ + struct prueth *priv = dev_get_priv(dev); + struct udevice *mdio_dev; + ofnode mdio; + int ret; + + mdio = prueth_find_mdio(dev_ofnode(priv->pruss)); + if (!ofnode_valid(mdio)) + return 0; + + /* + * The MDIO controller is represented in the DT binding by a + * subnode of the MAC controller. + * + * We don't have a DM driver for the MDIO device yet, and thus any + * pinctrl setting on its node will be ignored. + * + * However, we do need to make sure the pins states tied to the + * MDIO node are configured properly. Fortunately, the core DM + * does that for use when we get a device, so we can work around + * that whole issue by just requesting a dummy MDIO driver to + * probe, and our pins will get muxed. + */ + ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, &mdio_dev); + if (ret) + return ret; + + return 0; +} + +static int icssg_mdio_init(struct udevice *dev) +{ + struct prueth *prueth = dev_get_priv(dev); + int ret; + + ret = prueth_mdio_setup(dev); + if (ret) + return ret; + + prueth->bus = cpsw_mdio_init(dev->name, prueth->mdio_base, + prueth->mdio_freq, + clk_get_rate(&prueth->mdiofck), + prueth->mdio_manual_mode); + if (!prueth->bus) + return -EFAULT; + + return 0; +} + +static void icssg_config_set_speed(struct prueth *priv, int speed) +{ + u8 fw_speed; + + switch (speed) { + case SPEED_1000: + fw_speed = FW_LINK_SPEED_1G; + break; + case SPEED_100: + fw_speed = FW_LINK_SPEED_100M; + break; + case SPEED_10: + fw_speed = FW_LINK_SPEED_10M; + break; + default: + /* Other links speeds not supported */ + dev_err(priv->dev, "Unsupported link speed\n"); + return; + } + + writeb(fw_speed, priv->dram.pa + PORT_LINK_SPEED_OFFSET); +} + +static int icssg_update_link(struct prueth *priv) +{ + struct phy_device *phy = priv->phydev; + bool gig_en = false, full_duplex = false; + + if (phy->link) { /* link up */ + if (phy->speed == SPEED_1000) + gig_en = true; + if (phy->duplex == DUPLEX_FULL) + full_duplex = true; + /* Set the RGMII cfg for gig en and full duplex */ + icssg_update_rgmii_cfg(priv->miig_rt, phy->speed, full_duplex, + priv->slice, priv); + /* update the Tx IPG based on 100M/1G speed */ + icssg_config_ipg(priv, phy->speed, priv->slice); + + /* Send command to firmware to update Speed setting */ + icssg_config_set_speed(priv, phy->speed); + + /* Enable PORT FORWARDING */ + emac_set_port_state(priv, ICSSG_EMAC_PORT_FORWARD); + + printf("link up on port %d, speed %d, %s duplex\n", + priv->slice, phy->speed, + (phy->duplex == DUPLEX_FULL) ? "full" : "half"); + } else { + emac_set_port_state(priv, ICSSG_EMAC_PORT_DISABLE); + printf("link down on port %d\n", priv->slice); + } + + return phy->link; +} + +struct icssg_firmwares { + char *pru; + char *rtu; + char *txpru; +}; + +static struct icssg_firmwares icssg_emac_firmwares[] = { + { + .pru = "/lib/firmware/ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + .rtu = "/lib/firmware/ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + .txpru = "/lib/firmware/ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + }, + { + .pru = "/lib/firmware/ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + .rtu = "/lib/firmware/ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + .txpru = "/lib/firmware/ti-pruss/am65x-sr2-txpru1-prueth-fw.elf", + } +}; + +static int icssg_start_pru_cores(struct udevice *dev) +{ + struct prueth *prueth = dev_get_priv(dev); + struct icssg_firmwares *firmwares; + struct udevice *rproc_dev = NULL; + int ret, slice; + u32 phandle; + u8 index; + + slice = prueth->slice; + index = slice * ICSSG_NUM_PRU_CORES; + firmwares = icssg_emac_firmwares; + + ofnode_read_u32_index(dev_ofnode(dev), "ti,prus", index, &phandle); + ret = uclass_get_device_by_phandle_id(UCLASS_REMOTEPROC, phandle, &rproc_dev); + if (ret) { + dev_err(dev, "Unknown remote processor with phandle '0x%x' requested(%d)\n", + phandle, ret); + return ret; + } + + prueth->pru_core_id = dev_seq(rproc_dev); + ret = rproc_set_firmware(rproc_dev, firmwares[slice].pru); + if (ret) + return ret; + + ret = rproc_boot(rproc_dev); + if (ret) { + dev_err(dev, "failed to boot PRU%d: %d\n", slice, ret); + return -EINVAL; + } + + ofnode_read_u32_index(dev_ofnode(dev), "ti,prus", index + 1, &phandle); + ret = uclass_get_device_by_phandle_id(UCLASS_REMOTEPROC, phandle, &rproc_dev); + if (ret) { + dev_err(dev, "Unknown remote processor with phandle '0x%x' requested(%d)\n", + phandle, ret); + goto halt_pru; + } + + prueth->rtu_core_id = dev_seq(rproc_dev); + ret = rproc_set_firmware(rproc_dev, firmwares[slice].rtu); + if (ret) + goto halt_pru; + + ret = rproc_boot(rproc_dev); + if (ret) { + dev_err(dev, "failed to boot RTU%d: %d\n", slice, ret); + goto halt_pru; + } + + ofnode_read_u32_index(dev_ofnode(dev), "ti,prus", index + 2, &phandle); + ret = uclass_get_device_by_phandle_id(UCLASS_REMOTEPROC, phandle, &rproc_dev); + if (ret) { + dev_err(dev, "Unknown remote processor with phandle '0x%x' requested(%d)\n", + phandle, ret); + goto halt_rtu; + } + + prueth->txpru_core_id = dev_seq(rproc_dev); + ret = rproc_set_firmware(rproc_dev, firmwares[slice].txpru); + if (ret) + goto halt_rtu; + + ret = rproc_boot(rproc_dev); + if (ret) { + dev_err(dev, "failed to boot TXPRU%d: %d\n", slice, ret); + goto halt_rtu; + } + + return 0; + +halt_rtu: + rproc_stop(prueth->rtu_core_id); + +halt_pru: + rproc_stop(prueth->pru_core_id); + return ret; +} + +static int icssg_stop_pru_cores(struct udevice *dev) +{ + struct prueth *prueth = dev_get_priv(dev); + + rproc_stop(prueth->pru_core_id); + rproc_stop(prueth->rtu_core_id); + rproc_stop(prueth->txpru_core_id); + + return 0; +} + +static int prueth_start(struct udevice *dev) +{ + struct ti_udma_drv_chan_cfg_data *dma_rx_cfg_data; + struct eth_pdata *pdata = dev_get_plat(dev); + struct prueth *priv = dev_get_priv(dev); + struct icssg_flow_cfg *flow_cfg; + u8 *hwaddr = pdata->enetaddr; + char chn_name[16]; + void *config; + int ret, i; + + icssg_class_set_mac_addr(priv->miig_rt, priv->slice, hwaddr); + icssg_ft1_set_mac_addr(priv->miig_rt, priv->slice, hwaddr); + icssg_class_default(priv->miig_rt, priv->slice, 0); + + /* Set Load time configuration */ + icssg_config(priv); + + ret = icssg_start_pru_cores(dev); + if (ret) + return ret; + + /* To differentiate channels for SLICE0 vs SLICE1 */ + snprintf(chn_name, sizeof(chn_name), "tx%d-0", priv->slice); + + ret = dma_get_by_name(dev, chn_name, &priv->dma_tx); + if (ret) + dev_err(dev, "TX dma get failed %d\n", ret); + + snprintf(chn_name, sizeof(chn_name), "rx%d", priv->slice); + ret = dma_get_by_name(dev, chn_name, &priv->dma_rx); + if (ret) + dev_err(dev, "RX dma get failed %d\n", ret); + + for (i = 0; i < UDMA_RX_DESC_NUM; i++) { + ret = dma_prepare_rcv_buf(&priv->dma_rx, + net_rx_packets[i], + UDMA_RX_BUF_SIZE); + if (ret) + dev_err(dev, "RX dma add buf failed %d\n", ret); + } + + ret = dma_enable(&priv->dma_tx); + if (ret) { + dev_err(dev, "TX dma_enable failed %d\n", ret); + goto tx_fail; + } + + ret = dma_enable(&priv->dma_rx); + if (ret) { + dev_err(dev, "RX dma_enable failed %d\n", ret); + goto rx_fail; + } + + /* check if the rx_flow_id of dma_rx is as expected since + * driver hardcode that value in config struct to firmware + * in probe. Just add this sanity check to catch any change + * to rx channel assignment in the future. + */ + dma_get_cfg(&priv->dma_rx, 0, (void **)&dma_rx_cfg_data); + config = (void *)(priv->dram.pa + ICSSG_CONFIG_OFFSET); + flow_cfg = config + PSI_L_REGULAR_FLOW_ID_BASE_OFFSET; + writew(dma_rx_cfg_data->flow_id_base, &flow_cfg->rx_base_flow); + writew(0, &flow_cfg->mgm_base_flow); + + dev_info(dev, "K3 ICSSG: rflow_id_base: %u, chn_name = %s\n", + dma_rx_cfg_data->flow_id_base, chn_name); + + ret = emac_fdb_flow_id_updated(priv); + if (ret) { + dev_err(dev, "Failed to update Rx Flow ID %d", ret); + goto phy_fail; + } + + ret = phy_startup(priv->phydev); + if (ret) { + dev_err(dev, "phy_startup failed\n"); + goto phy_fail; + } + + ret = icssg_update_link(priv); + if (!ret) { + ret = -ENODEV; + goto phy_shut; + } + + return 0; + +phy_shut: + phy_shutdown(priv->phydev); +phy_fail: + dma_disable(&priv->dma_rx); + dma_free(&priv->dma_rx); +rx_fail: + dma_disable(&priv->dma_tx); + dma_free(&priv->dma_tx); + +tx_fail: + icssg_class_disable(priv->miig_rt, priv->slice); + + return ret; +} + +static int prueth_send(struct udevice *dev, void *packet, int length) +{ + struct prueth *priv = dev_get_priv(dev); + int ret; + + ret = dma_send(&priv->dma_tx, packet, length, NULL); + + return ret; +} + +static int prueth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct prueth *priv = dev_get_priv(dev); + int ret; + + /* try to receive a new packet */ + ret = dma_receive(&priv->dma_rx, (void **)packetp, NULL); + + return ret; +} + +static int prueth_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct prueth *priv = dev_get_priv(dev); + int ret = 0; + + if (length > 0) { + u32 pkt = priv->rx_next % UDMA_RX_DESC_NUM; + + dev_dbg(dev, "%s length:%d pkt:%u\n", __func__, length, pkt); + + ret = dma_prepare_rcv_buf(&priv->dma_rx, + net_rx_packets[pkt], + UDMA_RX_BUF_SIZE); + priv->rx_next++; + } + + return ret; +} + +static void prueth_stop(struct udevice *dev) +{ + struct prueth *priv = dev_get_priv(dev); + + phy_shutdown(priv->phydev); + + dma_disable(&priv->dma_tx); + dma_disable(&priv->dma_rx); + + icssg_stop_pru_cores(dev); + + dma_free(&priv->dma_tx); + dma_free(&priv->dma_rx); +} + +static const struct eth_ops prueth_ops = { + .start = prueth_start, + .send = prueth_send, + .recv = prueth_recv, + .free_pkt = prueth_free_pkt, + .stop = prueth_stop, +}; + +static int icssg_ofdata_parse_phy(struct udevice *dev, ofnode port_np) +{ + struct prueth *priv = dev_get_priv(dev); + struct ofnode_phandle_args out_args; + int ret = 0; + + priv->phy_interface = ofnode_read_phy_mode(port_np); + + if (priv->phy_interface == PHY_INTERFACE_MODE_NA) { + dev_err(dev, "Invalid PHY mode '%s'\n", + phy_string_for_interface(priv->phy_interface)); + ret = -EINVAL; + goto out; + } + + ret = ofnode_parse_phandle_with_args(port_np, "phy-handle", + NULL, 0, 0, &out_args); + if (ret) { + dev_err(dev, "can't parse phy-handle port (%d)\n", ret); + ret = 0; + } + + priv->phy_node = out_args.node; + ret = ofnode_read_u32(priv->phy_node, "reg", &priv->phy_addr); + if (ret) + dev_err(dev, "failed to get phy_addr port (%d)\n", ret); + +out: + return ret; +} + +static const struct soc_attr k3_mdio_soc_data[] = { + { .family = "AM62X", .revision = "SR1.0" }, + { .family = "AM64X", .revision = "SR1.0" }, + { .family = "AM64X", .revision = "SR2.0" }, + { .family = "AM65X", .revision = "SR1.0" }, + { .family = "AM65X", .revision = "SR2.0" }, + { .family = "J7200", .revision = "SR1.0" }, + { .family = "J7200", .revision = "SR2.0" }, + { .family = "J721E", .revision = "SR1.0" }, + { .family = "J721E", .revision = "SR1.1" }, + { .family = "J721S2", .revision = "SR1.0" }, + { /* sentinel */ }, +}; + +static int prueth_probe(struct udevice *dev) +{ + ofnode node, pruss_node, mdio_node, sram_node, curr_sram_node; + ofnode eth_ports_node, eth0_node, eth1_node, eth_node; + struct prueth *prueth = dev_get_priv(dev); + u32 phandle, err, sp, prev_end_addr; + struct udevice **prussdev = NULL; + int ret = 0; + + prueth = dev_get_priv(dev); + prueth->dev = dev; + err = ofnode_read_u32(dev_ofnode(dev), "ti,prus", &phandle); + if (err) + return err; + + node = ofnode_get_by_phandle(phandle); + if (!ofnode_valid(node)) + return -EINVAL; + + pruss_node = ofnode_get_parent(node); + ret = device_get_global_by_ofnode(pruss_node, prussdev); + if (ret) + dev_err(dev, "error getting the pruss dev\n"); + prueth->pruss = *prussdev; + + ret = pruss_request_mem_region(*prussdev, PRUSS_MEM_SHRD_RAM2, + &prueth->shram); + if (ret) + return ret; + + ret = pruss_request_tm_region(*prussdev, &prueth->tmaddr); + if (ret) + return ret; + + eth_ports_node = dev_read_subnode(dev, "ethernet-ports"); + if (!ofnode_valid(eth_ports_node)) + return -ENOENT; + + ofnode_for_each_subnode(eth_node, eth_ports_node) { + const char *node_name; + u32 reg; + + node_name = ofnode_get_name(eth_node); + ret = ofnode_read_u32(eth_node, "reg", ®); + if (ret) + dev_err(dev, "%s: error reading port_id (%d)\n", node_name, ret); + + if (reg >= PRUETH_NUM_MACS) { + dev_err(dev, "%s: invalid port_id (%d)\n", node_name, reg); + return -EINVAL; + } + + if (reg == 0) + eth0_node = eth_node; + else if (reg == 1) + eth1_node = eth_node; + else + dev_err(dev, "port reg should be 0 or 1\n"); + } + + /* one node must be present and available else we fail */ + if (!ofnode_is_enabled(eth0_node) && !ofnode_is_enabled(eth1_node)) { + dev_err(dev, "neither port@0 nor port@1 node available\n"); + return -ENODEV; + } + + /* + * Uboot ethernet framework does not support two interfaces in a single + * probe. If the eth0_node is enabled in DT, we'll only probe eth0_node. + * If the eth0_node is not enabled in DT, we'll check for eth1_node and + * probe the eth1_node if enabled. + */ + if (ofnode_is_enabled(eth0_node)) { + if (ofnode_valid(eth0_node) && ofnode_is_enabled(eth0_node)) { + prueth->slice = 0; + icssg_ofdata_parse_phy(dev, eth0_node); + prueth->eth_node[PRUETH_MAC0] = eth0_node; + dev_dbg(dev, "Using port0\n"); + } + } else if (ofnode_is_enabled(eth1_node)) { + if (ofnode_valid(eth1_node) && ofnode_is_enabled(eth1_node)) { + prueth->slice = 1; + icssg_ofdata_parse_phy(dev, eth1_node); + prueth->eth_node[PRUETH_MAC0] = eth1_node; + dev_dbg(dev, "Using port1\n"); + } + } + + ret = pruss_request_mem_region(*prussdev, + prueth->slice ? PRUSS_MEM_DRAM1 : PRUSS_MEM_DRAM0, + &prueth->dram); + if (ret) { + dev_err(dev, "could not request DRAM%d region\n", prueth->slice); + return ret; + } + + prueth->miig_rt = syscon_regmap_lookup_by_phandle(dev, "ti,mii-g-rt"); + if (!prueth->miig_rt) { + dev_err(dev, "couldn't get mii-g-rt syscon regmap\n"); + return -ENODEV; + } + + prueth->mii_rt = syscon_regmap_lookup_by_phandle(dev, "ti,mii-rt"); + if (!prueth->mii_rt) { + dev_err(dev, "couldn't get mii-rt syscon regmap\n"); + return -ENODEV; + } + + ret = ofnode_read_u32(dev_ofnode(dev), "sram", &sp); + if (ret) { + dev_err(dev, "sram node fetch failed %d\n", ret); + return ret; + } + + sram_node = ofnode_get_by_phandle(sp); + if (!ofnode_valid(sram_node)) + return -EINVAL; + + prev_end_addr = ofnode_get_addr(sram_node); + + ofnode_for_each_subnode(curr_sram_node, sram_node) { + u32 start_addr, size, end_addr, avail; + const char *name; + + name = ofnode_get_name(curr_sram_node); + start_addr = ofnode_get_addr(curr_sram_node); + size = ofnode_get_size(curr_sram_node); + end_addr = start_addr + size; + avail = start_addr - prev_end_addr; + + if (avail > MSMC_RAM_SIZE) + break; + + prev_end_addr = end_addr; + } + + prueth->sram_pa = prev_end_addr; + if (prueth->sram_pa % SZ_64K != 0) { + /* This is constraint for SR2.0 firmware */ + dev_err(dev, "sram address needs to be 64KB aligned\n"); + return -EINVAL; + } + dev_dbg(dev, "sram: addr %x size %x\n", prueth->sram_pa, MSMC_RAM_SIZE); + + if (prueth->phy_interface != PHY_INTERFACE_MODE_MII && + prueth->phy_interface < PHY_INTERFACE_MODE_RGMII && + prueth->phy_interface > PHY_INTERFACE_MODE_RGMII_TXID) { + dev_err(prueth->dev, "PHY mode unsupported %s\n", + phy_string_for_interface(prueth->phy_interface)); + return -EINVAL; + } + + /* AM65 SR2.0 has TX Internal delay always enabled by hardware + * and it is not possible to disable TX Internal delay. The below + * switch case block describes how we handle different phy modes + * based on hardware restriction. + */ + switch (prueth->phy_interface) { + case PHY_INTERFACE_MODE_RGMII_ID: + prueth->phy_interface = PHY_INTERFACE_MODE_RGMII_RXID; + break; + case PHY_INTERFACE_MODE_RGMII_TXID: + prueth->phy_interface = PHY_INTERFACE_MODE_RGMII; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_RXID: + dev_err(prueth->dev, "RGMII mode without TX delay is not supported"); + return -EINVAL; + default: + break; + } + + mdio_node = ofnode_find_subnode(pruss_node, "mdio"); + prueth->mdio_base = ofnode_get_addr(mdio_node); + ofnode_read_u32(mdio_node, "bus_freq", &prueth->mdio_freq); + + ret = clk_get_by_name_nodev(mdio_node, "fck", &prueth->mdiofck); + if (ret) { + dev_err(dev, "failed to get clock %d\n", ret); + return ret; + } + + ret = clk_enable(&prueth->mdiofck); + if (ret) { + dev_err(dev, "clk_enable failed %d\n", ret); + return ret; + } + + prueth->mdio_manual_mode = false; + if (soc_device_match(k3_mdio_soc_data)) + prueth->mdio_manual_mode = true; + + ret = icssg_mdio_init(dev); + if (ret) + return ret; + + ret = icssg_phy_init(dev); + if (ret) { + dev_err(dev, "phy_init failed\n"); + goto out; + } + + return 0; +out: + cpsw_mdio_free(prueth->bus); + clk_disable(&prueth->mdiofck); + + return ret; +} + +static const struct udevice_id prueth_ids[] = { + { .compatible = "ti,am654-icssg-prueth" }, + { .compatible = "ti,am642-icssg-prueth" }, + { } +}; + +U_BOOT_DRIVER(prueth) = { + .name = "prueth", + .id = UCLASS_ETH, + .of_match = prueth_ids, + .probe = prueth_probe, + .ops = &prueth_ops, + .priv_auto = sizeof(struct prueth), + .plat_auto = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + +static const struct udevice_id prueth_mdio_ids[] = { + { .compatible = "ti,davinci_mdio" }, + { } +}; + +U_BOOT_DRIVER(prueth_mdio) = { + .name = "prueth_mdio", + .id = UCLASS_MDIO, + .of_match = prueth_mdio_ids, +}; diff --git a/drivers/net/ti/icssg_prueth.h b/drivers/net/ti/icssg_prueth.h index 97b6b191fa..326ad23c0b 100644 --- a/drivers/net/ti/icssg_prueth.h +++ b/drivers/net/ti/icssg_prueth.h @@ -67,6 +67,9 @@ struct prueth { bool mdio_manual_mode; int speed; int duplex; + u8 pru_core_id; + u8 rtu_core_id; + u8 txpru_core_id; }; /* config helpers */ -- cgit v1.2.3 From fc4ba1d97ec8d6e69b9ed93d7c36af2405c8aa5d Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:19:53 +0530 Subject: net: ti: icssg: Add support sending FDB command to update rx_flow_id ICSSG firmware supports FDB commands. Add support to send FDB commands from driver. Once rx_flow_id is obtained from dma, let firmware know that we are using this rx_flow_id by sending a FDB command. Signed-off-by: MD Danish Anwar --- drivers/net/ti/icssg_config.c | 66 +++++++++++++++++++++++++++++++++++++++++++ drivers/net/ti/icssg_config.h | 18 ++++++++++++ drivers/net/ti/icssg_prueth.h | 6 ++++ 3 files changed, 90 insertions(+) diff --git a/drivers/net/ti/icssg_config.c b/drivers/net/ti/icssg_config.c index a21d2d17ce..43ce6e15da 100644 --- a/drivers/net/ti/icssg_config.c +++ b/drivers/net/ti/icssg_config.c @@ -9,6 +9,7 @@ #include "icssg_switch_map.h" #include "icss_mii_rt.h" #include +#include /* TX IPG Values to be set for 100M and 1G link speeds. These values are * in ocp_clk cycles. So need change if ocp_clk is changed for a specific @@ -395,3 +396,68 @@ int emac_set_port_state(struct prueth *prueth, return ret; } + +int icssg_send_fdb_msg(struct prueth *prueth, struct mgmt_cmd *cmd, + struct mgmt_cmd_rsp *rsp) +{ + int slice = prueth->slice; + int ret, addr; + + addr = icssg_queue_pop(prueth, slice == 0 ? + ICSSG_CMD_POP_SLICE0 : ICSSG_CMD_POP_SLICE1); + if (addr < 0) + return addr; + + /* First 4 bytes have FW owned buffer linking info which should + * not be touched + */ + memcpy_toio((void __iomem *)prueth->shram.pa + addr + 4, cmd, sizeof(*cmd)); + icssg_queue_push(prueth, slice == 0 ? + ICSSG_CMD_PUSH_SLICE0 : ICSSG_CMD_PUSH_SLICE1, addr); + ret = read_poll_timeout(icssg_queue_pop, addr, addr >= 0, + 2000, 20000000, prueth, slice == 0 ? + ICSSG_RSP_POP_SLICE0 : ICSSG_RSP_POP_SLICE1); + + if (ret) { + dev_err(prueth->dev, "Timedout sending HWQ message\n"); + return ret; + } + + memcpy_fromio(rsp, (void __iomem *)prueth->shram.pa + addr, sizeof(*rsp)); + /* Return buffer back for to pool */ + icssg_queue_push(prueth, slice == 0 ? + ICSSG_RSP_PUSH_SLICE0 : ICSSG_RSP_PUSH_SLICE1, addr); + + return 0; +} + +int emac_fdb_flow_id_updated(struct prueth *prueth) +{ + struct mgmt_cmd_rsp fdb_cmd_rsp = { 0 }; + int slice = prueth->slice; + struct mgmt_cmd fdb_cmd = { 0 }; + int ret = 0; + + fdb_cmd.header = ICSSG_FW_MGMT_CMD_HEADER; + fdb_cmd.type = ICSSG_FW_MGMT_FDB_CMD_TYPE_RX_FLOW; + fdb_cmd.seqnum = ++(prueth->icssg_hwcmdseq); + fdb_cmd.param = 0; + + fdb_cmd.param |= (slice << 4); + fdb_cmd.cmd_args[0] = 0; + + ret = icssg_send_fdb_msg(prueth, &fdb_cmd, &fdb_cmd_rsp); + if (ret) + return ret; + + if (fdb_cmd.seqnum != fdb_cmd_rsp.seqnum) { + dev_err(prueth->dev, "seqnum doesn't match, cmd.seqnum %d != rsp.seqnum %d\n", + fdb_cmd.seqnum, fdb_cmd_rsp.seqnum); + return -EINVAL; + } + + if (fdb_cmd_rsp.status == 1) + return 0; + + return -EINVAL; +} diff --git a/drivers/net/ti/icssg_config.h b/drivers/net/ti/icssg_config.h index 412dbf51c7..0dcf025358 100644 --- a/drivers/net/ti/icssg_config.h +++ b/drivers/net/ti/icssg_config.h @@ -80,6 +80,7 @@ struct icssg_rxq_ctx { #define ICSSG_FW_MGMT_FDB_CMD_TYPE 0x03 #define ICSSG_FW_MGMT_CMD_TYPE 0x04 #define ICSSG_FW_MGMT_PKT 0x80000000 +#define ICSSG_FW_MGMT_FDB_CMD_TYPE_RX_FLOW 0x05 struct icssg_r30_cmd { u32 cmd[4]; @@ -156,6 +157,23 @@ struct icssg_setclock_desc { u32 CMP0_new; } __packed; +struct mgmt_cmd { + u8 param; + u8 seqnum; + u8 type; + u8 header; + u32 cmd_args[3]; +} __packed; + +struct mgmt_cmd_rsp { + u32 reserved; + u8 status; + u8 seqnum; + u8 type; + u8 header; + u32 cmd_args[3]; +} __packed; + #define ICSSG_CMD_POP_SLICE0 56 #define ICSSG_CMD_POP_SLICE1 60 diff --git a/drivers/net/ti/icssg_prueth.h b/drivers/net/ti/icssg_prueth.h index 326ad23c0b..4b876e4a85 100644 --- a/drivers/net/ti/icssg_prueth.h +++ b/drivers/net/ti/icssg_prueth.h @@ -70,6 +70,7 @@ struct prueth { u8 pru_core_id; u8 rtu_core_id; u8 txpru_core_id; + u8 icssg_hwcmdseq; }; /* config helpers */ @@ -82,4 +83,9 @@ int icssg_queue_pop(struct prueth *prueth, u8 queue); void icssg_queue_push(struct prueth *prueth, int queue, u16 addr); u32 icssg_queue_level(struct prueth *prueth, int queue); +/* FDB helpers */ +int icssg_send_fdb_msg(struct prueth *prueth, struct mgmt_cmd *cmd, + struct mgmt_cmd_rsp *rsp); +int emac_fdb_flow_id_updated(struct prueth *prueth); + #endif /* __NET_TI_ICSSG_PRUETH_H */ -- cgit v1.2.3 From 7a011098ab7d62c62fa05a03849073baa882cabd Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:19:54 +0530 Subject: net: ti: icssg: Enforce pinctrl state on the MDIO child node The binding represents the MDIO controller as a child device tree node of the MAC device tree node. The U-Boot driver mostly ignores that child device tree node and just hardcodes the resources it uses to support both the MAC and MDIO in a single driver. However, some resources like pinctrl muxing states are thus ignored. This has been a problem with some device trees that will put some pinctrl states on the MDIO device tree node. Let's rework the driver a bit to create a dummy MDIO driver that we will then get during our initialization to force the core to select the right muxing. Signed-off-by: MD Danish Anwar --- drivers/net/ti/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index 62ef8e9d89..92b06b6b99 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -53,6 +53,7 @@ config TI_AM65_CPSW_NUSS config TI_ICSSG_PRUETH bool "TI Gigabit PRU Ethernet driver" depends on ARCH_K3 + imply DM_MDIO select PHYLIB help Support Gigabit Ethernet ports over the ICSSG PRU Subsystem -- cgit v1.2.3 From bde43158dd3ed58b362b002d16178ad80ebc37f0 Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:19:55 +0530 Subject: arm: dts: k3-am654: add needed regs to udmap nodes There are a few missing registers ranges in the udmap nodes need to properly setup DMA for the am65x. A fix has been added to the Linux kernel [0] to add these ranges and merged. To keep DMA operational until the next DT sync from Linux, these ranges were added to the *-u-boot.dtsi in the upstream u-boot [1]. Porting these DMA changes to ti-u-boot as these are needed for ICSSG Ethernet driver to work. And additional config register was added to the ringacc node in upstream u-boot as part of DT sync from linux 6.7-rc1 [2]. Porting those changes as well to ti-u-boot as those are also needed for ICSSG Ethernet driver to work. [0] https://lore.kernel.org/r/20231213135138.929517-2-vigneshr@ti.com [1] https://source.denx.de/u-boot/u-boot/-/commit/5e00547e583f6d4349f3908d3491bf6ce0a8818c [2] https://source.denx.de/u-boot/u-boot/-/commit/4dbdc84754ea2ad392ef7328da6d429cd8fd3c0a Signed-off-by: MD Danish Anwar --- arch/arm/dts/k3-am65-main.dtsi | 5 ++-- arch/arm/dts/k3-am65-mcu.dtsi | 6 +++-- arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 34 ++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index ba4e5d3e1e..634d447925 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -603,8 +603,9 @@ reg = <0x0 0x3c000000 0x0 0x400000>, <0x0 0x38000000 0x0 0x400000>, <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x33000000 0x0 0x40000>, + <0x0 0x31080000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <818>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi index c93ff1520a..ab7f206185 100644 --- a/arch/arm/dts/k3-am65-mcu.dtsi +++ b/arch/arm/dts/k3-am65-mcu.dtsi @@ -129,8 +129,10 @@ reg = <0x0 0x2b800000 0x0 0x400000>, <0x0 0x2b000000 0x0 0x400000>, <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", + "proxy_target", "cfg"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index e4cbc47c2a..64f34bdee1 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -81,3 +81,37 @@ &mcu_r5fss0 { ti,cluster-mode = <0>; }; + +/* + * The DMA driver requires a few extra register ranges + * which are missing for the am65x. A patch has been + * sent and merged to linux and will be synced with + * upstream u-boot in the next DT sync. + */ +&main_udmap { + reg = <0x0 0x31150000 0x0 0x100>, + <0x0 0x34000000 0x0 0x100000>, + <0x0 0x35000000 0x0 0x100000>, + <0x0 0x30b00000 0x0 0x10000>, + <0x0 0x30c00000 0x0 0x10000>, + <0x0 0x30d00000 0x0 0x8000>; + reg-names = "gcfg", "rchanrt", "tchanrt", + "tchan", "rchan", "rflow"; +}; + +/* + * The DMA driver requires a few extra register ranges + * which are missing for the am65x. A patch has been + * sent and merged to linux and will be synced with + * upstream u-boot in the next DT sync. + */ +&mcu_udmap { + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x2aa00000 0x0 0x40000>, + <0x0 0x284a0000 0x0 0x4000>, + <0x0 0x284c0000 0x0 0x4000>, + <0x0 0x28400000 0x0 0x2000>; + reg-names = "gcfg", "rchanrt", "tchanrt", + "tchan", "rchan", "rflow"; +}; -- cgit v1.2.3 From 1ab862d0d96acc0faa93ed26aecb21d9c04ee854 Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:19:56 +0530 Subject: arm: dts: k3-am65-main: Add ICSSG IEP nodes The ICSSG IP on AM65x SoCs have two Industrial Ethernet Peripherals (IEPs) to manage/generate Industrial Ethernet functions such as time stamping. Each IEP sub-module is sourced from an internal clock mux that can be sourced from either of the IP instance's ICSSG_IEP_GCLK or ICSSG_ICLK. Add the IEP nodes for all the ICSSG instances. Signed-off-by: MD Danish Anwar --- arch/arm/dts/k3-am65-main.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index 634d447925..7c276d7c21 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -965,6 +965,18 @@ }; }; + icssg0_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + + icssg0_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + icssg0_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; @@ -1106,6 +1118,18 @@ }; }; + icssg1_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + + icssg1_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + icssg1_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; @@ -1247,6 +1271,18 @@ }; }; + icssg2_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg2_iepclk_mux>; + }; + + icssg2_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg2_iepclk_mux>; + }; + icssg2_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; -- cgit v1.2.3 From 31b2df073b793ed626773eb21c1bd0f0164e29bf Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:19:57 +0530 Subject: arm: dts: k3-am654-base-board: Add ICSSG2 Ethernet support ICSSG2 provides dual Gigabit Ethernet support. Add ICSSG2 ethernet node to an overlay k3-am654-icssg2.dts Signed-off-by: MD Danish Anwar --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/k3-am654-icssg2.dts | 145 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 148 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-am654-icssg2.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6c719ade1a..4beef8cdb3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1259,7 +1259,9 @@ dtb-$(CONFIG_SOC_K3_AM654) += \ k3-am6528-iot2050-basic.dtb \ k3-am6528-iot2050-basic-pg2.dtb \ k3-am6548-iot2050-advanced.dtb \ - k3-am6548-iot2050-advanced-pg2.dtb + k3-am6548-iot2050-advanced-pg2.dtb \ + k3-am654-icssg2.dtbo + dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ k3-j721e-r5-common-proc-board.dtb \ k3-j7200-common-proc-board.dtb \ diff --git a/arch/arm/dts/k3-am654-icssg2.dts b/arch/arm/dts/k3-am654-icssg2.dts new file mode 100644 index 0000000000..faefa2febc --- /dev/null +++ b/arch/arm/dts/k3-am654-icssg2.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for enabling ICSSG2 on AM654 EVM + * + * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/icssg2-eth/ethernet-ports/port@0"; + ethernet2 = "/icssg2-eth/ethernet-ports/port@1"; + }; + + /* Ethernet node on PRU-ICSSG2 */ + icssg2_eth: icssg2-eth { + compatible = "ti,am654-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg2_rgmii_pins_default>; + sram = <&msmc_ram>; + ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>, + <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>; + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ti,mii-g-rt = <&icssg2_mii_g_rt>; + ti,mii-rt = <&icssg2_mii_rt>; + ti,iep = <&icssg2_iep0>, <&icssg2_iep1>; + + interrupt-parent = <&icssg2_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + + dmas = <&main_udmap 0xc300>, /* egress slice 0 */ + <&main_udmap 0xc301>, /* egress slice 0 */ + <&main_udmap 0xc302>, /* egress slice 0 */ + <&main_udmap 0xc303>, /* egress slice 0 */ + <&main_udmap 0xc304>, /* egress slice 1 */ + <&main_udmap 0xc305>, /* egress slice 1 */ + <&main_udmap 0xc306>, /* egress slice 1 */ + <&main_udmap 0xc307>, /* egress slice 1 */ + <&main_udmap 0x4300>, /* ingress slice 0 */ + <&main_udmap 0x4301>; /* ingress slice 1 */ + + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + icssg2_emac0: port@0 { + reg = <0>; + phy-handle = <&icssg2_phy0>; + phy-mode = "rgmii-id"; + ti,syscon-rgmii-delay = <&scm_conf 0x4120>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + icssg2_emac1: port@1 { + reg = <1>; + phy-handle = <&icssg2_phy1>; + phy-mode = "rgmii-id"; + ti,syscon-rgmii-delay = <&scm_conf 0x4124>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; +}; + +&main_pmx0 { + + icssg2_mdio_pins_default: icssg2-mdio-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x0094, PIN_INPUT, 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */ + AM65X_IOPAD(0x00c8, PIN_OUTPUT, 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */ + >; + }; + + icssg2_rgmii_pins_default: icssg2-rgmii-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x00ac, PIN_INPUT, 2) /* (AH15) PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */ + AM65X_IOPAD(0x00b0, PIN_INPUT, 2) /* (AC16) PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */ + AM65X_IOPAD(0x00b4, PIN_INPUT, 2) /* (AD17) PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */ + AM65X_IOPAD(0x00b8, PIN_INPUT, 2) /* (AH14) PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */ + AM65X_IOPAD(0x00cc, PIN_OUTPUT, 2) /* (AD15) PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */ + AM65X_IOPAD(0x00d0, PIN_OUTPUT, 2) /* (AF14) PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */ + AM65X_IOPAD(0x00d4, PIN_OUTPUT, 2) /* (AC15) PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */ + AM65X_IOPAD(0x00d8, PIN_OUTPUT, 2) /* (AD14) PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */ + AM65X_IOPAD(0x00dc, PIN_INPUT, 2) /* (AE14) PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */ + AM65X_IOPAD(0x00c4, PIN_OUTPUT, 2) /* (AC17) PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */ + AM65X_IOPAD(0x00c0, PIN_INPUT, 2) /* (AG15) PRG2_PRU1_GPO5.PRG2_RGMII2_RXC */ + AM65X_IOPAD(0x00bc, PIN_INPUT, 2) /* (AG14) PRG2_PRU1_GPO4.PRG2_RGMII2_RX_CTL */ + + AM65X_IOPAD(0x0078, PIN_INPUT, 2) /* (AF18) PRG2_PRU0_GPO0.PRG2_RGMII1_RD0 */ + AM65X_IOPAD(0x007c, PIN_INPUT, 2) /* (AE18) PRG2_PRU0_GPO1.PRG2_RGMII1_RD1 */ + AM65X_IOPAD(0x0080, PIN_INPUT, 2) /* (AH17) PRG2_PRU0_GPO2.PRG2_RGMII1_RD2 */ + AM65X_IOPAD(0x0084, PIN_INPUT, 2) /* (AG18) PRG2_PRU0_GPO3.PRG2_RGMII1_RD3 */ + AM65X_IOPAD(0x0098, PIN_OUTPUT, 2) /* (AH16) PRG2_PRU0_GPO8.PRG2_RGMII1_TD0 */ + AM65X_IOPAD(0x009c, PIN_OUTPUT, 2) /* (AG16) PRG2_PRU0_GPO9.PRG2_RGMII1_TD1 */ + AM65X_IOPAD(0x00a0, PIN_OUTPUT, 2) /* (AF16) PRG2_PRU0_GPO10.PRG2_RGMII1_TD2 */ + AM65X_IOPAD(0x00a4, PIN_OUTPUT, 2) /* (AE16) PRG2_PRU0_GPO11.PRG2_RGMII1_TD3 */ + AM65X_IOPAD(0x00a8, PIN_INPUT, 2) /* (AD16) PRG2_PRU0_GPO16.PRG2_RGMII1_TXC */ + AM65X_IOPAD(0x0090, PIN_OUTPUT, 2) /* (AE17) PRG2_PRU0_GPO6.PRG2_RGMII1_TX_CTL */ + AM65X_IOPAD(0x008c, PIN_INPUT, 2) /* (AF17) PRG2_PRU0_GPO5.PRG2_RGMII1_RXC */ + AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */ + >; + }; +}; + +&icssg2_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg2_mdio_pins_default>; + #address-cells = <1>; + #size-cells = <0>; + + icssg2_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; + + icssg2_phy1: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; -- cgit v1.2.3 From f3de07ca61570355f8b55c7ce98339ad5829ed9c Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:19:58 +0530 Subject: arm: dts: k3-am65x-binman: Add ICSSG2 overlay and configuration Add ICSSG2 overlay and configuration to tispl and u-boot images. Signed-off-by: MD Danish Anwar --- arch/arm/dts/k3-am65x-binman.dtsi | 65 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 61 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/k3-am65x-binman.dtsi b/arch/arm/dts/k3-am65x-binman.dtsi index 90ea220a2f..c0c664b97e 100644 --- a/arch/arm/dts/k3-am65x-binman.dtsi +++ b/arch/arm/dts/k3-am65x-binman.dtsi @@ -212,6 +212,8 @@ #define UBOOT_NODTB "u-boot-nodtb.bin" #define AM654_EVM_DTB "u-boot.dtb" +#define AM654_EVM_ICSSG2_DTBO "arch/arm/dts/k3-am654-icssg2.dtbo" + &binman { ti-spl { filename = "tispl.bin"; @@ -299,6 +301,20 @@ filename = SPL_AM654_EVM_DTB; }; }; + + fdt-1 { + description = "k3-am654-icssg2 overlay"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&spl_am65x_evm_icssg2_dtb>; + keyfile = "custMpk.pem"; + }; + spl_am65x_evm_icssg2_dtb: blob-ext { + filename = AM654_EVM_ICSSG2_DTBO; + }; + }; }; configurations { @@ -308,7 +324,7 @@ description = "k3-am654-base-board"; firmware = "atf"; loadables = "tee", "dm", "spl"; - fdt = "fdt-0"; + fdt = "fdt-0", "fdt-1"; }; }; }; @@ -360,6 +376,24 @@ }; }; + fdt-1 { + description = "k3-am654-icssg2 overlay"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&am65x_evm_icssg2_dtb>; + keyfile = "custMpk.pem"; + + }; + am65x_evm_icssg2_dtb: blob-ext { + filename = AM654_EVM_ICSSG2_DTBO; + }; + hash { + algo = "crc32"; + }; + }; + }; configurations { @@ -369,7 +403,7 @@ description = "k3-am654-base-board"; firmware = "uboot"; loadables = "uboot"; - fdt = "fdt-0"; + fdt = "fdt-0", "fdt-1"; }; }; }; @@ -448,6 +482,16 @@ filename = SPL_AM654_EVM_DTB; }; }; + + fdt-1 { + description = "k3-am654-icssg2 overlay"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = AM654_EVM_ICSSG2_DTBO; + }; + }; }; configurations { @@ -457,7 +501,7 @@ description = "k3-am654-base-board"; firmware = "atf"; loadables = "tee", "dm", "spl"; - fdt = "fdt-0"; + fdt = "fdt-0", "fdt-1"; }; }; }; @@ -500,6 +544,19 @@ algo = "crc32"; }; }; + + fdt-1 { + description = "k3-am654-icssg2"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob { + filename = AM654_EVM_ICSSG2_DTBO; + }; + hash { + algo = "crc32"; + }; + }; }; configurations { @@ -509,7 +566,7 @@ description = "k3-am654-base-board"; firmware = "uboot"; loadables = "uboot"; - fdt = "fdt-0"; + fdt = "fdt-0", "fdt-1"; }; }; }; -- cgit v1.2.3 From 97f9e10552daddf22f2a5dca200c65195efff0e9 Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:19:59 +0530 Subject: configs: am65x_evm_a53: Enable ICSSG Driver Enable ICSSG driver in am65x_evm_a53_defconfig Signed-off-by: MD Danish Anwar --- configs/am65x_evm_a53_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index c10b2c34af..cca8c34883 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -128,6 +128,7 @@ CONFIG_E1000=y CONFIG_CMD_E1000=y CONFIG_TI_AM65_CPSW_NUSS=y CONFIG_PCI=y +CONFIG_TI_ICSSG_PRUETH=y CONFIG_PCI_KEYSTONE=y CONFIG_PHY=y CONFIG_SPL_PHY=y -- cgit v1.2.3 From 01bbd99357b96b6b048d94987703da063342f139 Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:20:00 +0530 Subject: configs: am65x_evm_a53: add SPL_LOAD_FIT_APPLY_OVERLAY We want SPL to apply DTB overlays (e.g. ICSSG2 overlay) so enable SPL_LOAD_FIT_APPLY_OVERLAY. Signed-off-by: MD Danish Anwar --- configs/am65x_evm_a53_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index cca8c34883..2f7cd66218 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -74,6 +74,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y CONFIG_CMD_USB=y CONFIG_CMD_TIME=y CONFIG_CMD_UBI=y -- cgit v1.2.3 From ae7327276552c35387c44c9fe8dabd103fc28104 Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:20:01 +0530 Subject: board: ti: am65x: Add check for k3-am654-icssg2 in board_fit_config_match() When CONFIG_TI_ICSSG_PRUETH is enabled, add config name check for the icssg2 overlay in board_fit_config_match() API. Signed-off-by: MD Danish Anwar --- board/ti/am65x/evm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index 5743bb4f4d..48dc1af9aa 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -65,10 +65,11 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { -#ifdef CONFIG_TARGET_AM654_A53_EVM - if (!strcmp(name, "k3-am654-base-board")) + if (IS_ENABLED(CONFIG_TI_ICSSG_PRUETH) && !strcmp(name, "k3-am654-icssg2")) + return 0; + + if (IS_ENABLED(CONFIG_TARGET_AM654_A53_EVM) && !strcmp(name, "k3-am654-base-board")) return 0; -#endif return -1; } -- cgit v1.2.3 From 533a4f0f4807ac71eb929b41cab9d4187f157c1e Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:20:02 +0530 Subject: board: ti: am65x: Set fw_storage_interface and fw_dev_part ENVs When ICSSG driver is enabled (CONFIG_TI_ICSSG_PRUETH=y) set fw_storage_interface and fw_dev_part env variables. These variables need be set appropriately in order to load differnet ICSSG firmwares needed for ICSSG driver. By default the storage interface is mmc and the partition is 1:2. User can modify this based on their needs. Signed-off-by: MD Danish Anwar --- board/ti/am65x/am65x.env | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/ti/am65x/am65x.env b/board/ti/am65x/am65x.env index 036f475283..61cac49754 100644 --- a/board/ti/am65x/am65x.env +++ b/board/ti/am65x/am65x.env @@ -30,3 +30,7 @@ get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt} args_ubi=setenv bootargs console=${console} ${optargs} rootfstype=ubifs root=ubi0:rootfs rw ubi.mtd=ospi.rootfs +#if CONFIG_TI_ICSSG_PRUETH +fw_storage_interface=mmc +fw_dev_part=1:2 +#endif -- cgit v1.2.3 From 3a2148a01dd45283962515875e44b477ea69f8ef Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:20:03 +0530 Subject: remoteproc: pru: Add support for AM64x PRU / RTU cores Add support for AM64x PRU cores by adding compatibles for AM64x. Signed-off-by: MD Danish Anwar --- drivers/remoteproc/pru_rproc.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index 924070a76b..6a8ef67bfb 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -399,10 +399,12 @@ static void pru_set_id(struct pru_privdata *priv, struct udevice *dev) { u32 mask2 = 0x38000; - if (device_is_compatible(dev, "ti,am654-rtu")) + if (device_is_compatible(dev, "ti,am654-rtu") || + device_is_compatible(dev, "ti,am642-rtu")) mask2 = 0x6000; - if (device_is_compatible(dev, "ti,am654-tx-pru")) + if (device_is_compatible(dev, "ti,am654-tx-pru") || + device_is_compatible(dev, "ti,am642-tx-pru")) mask2 = 0xc000; if ((priv->pru_iram & mask2) == mask2) @@ -448,6 +450,9 @@ static const struct udevice_id pru_ids[] = { { .compatible = "ti,am654-pru"}, { .compatible = "ti,am654-rtu"}, { .compatible = "ti,am654-tx-pru" }, + { .compatible = "ti,am642-pru"}, + { .compatible = "ti,am642-rtu"}, + { .compatible = "ti,am642-tx-pru" }, {} }; -- cgit v1.2.3 From 00196980918b21e6f703658077dc562204f1f646 Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:20:04 +0530 Subject: soc: ti: pruss: Add support for AM64x Add support for AM64x by adding it's compatible in pruss driver. Signed-off-by: MD Danish Anwar --- drivers/soc/ti/pruss.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index 461390925d..5317b8335b 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -205,6 +205,7 @@ static int pruss_probe(struct udevice *dev) static const struct udevice_id pruss_ids[] = { { .compatible = "ti,am654-icssg"}, + { .compatible = "ti,am642-icssg"}, {} }; -- cgit v1.2.3 From 764d60ac434f3fab639a64c3e4e7a5faa2cfbee9 Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:20:05 +0530 Subject: arm: dts: k3-am64-main: Add ICSSG IEP nodes The ICSSG IP on AM64x SoCs have two Industrial Ethernet Peripherals (IEPs) to manage/generate Industrial Ethernet functions such as time stamping. Each IEP sub-module is sourced from an internal clock mux that can be derived from either of the IP instance's ICSSG_IEP_GCLK or from another internal ICSSG CORE_CLK mux. Add both the IEP nodes for both the ICSSG instances. The IEP clock is currently configured to be derived indirectly from the ICSSG_ICLK running at 250 MHz. Signed-off-by: MD Danish Anwar --- arch/arm/dts/k3-am64-main.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi index f8d8b9e85d..17be4bf3e2 100644 --- a/arch/arm/dts/k3-am64-main.dtsi +++ b/arch/arm/dts/k3-am64-main.dtsi @@ -1085,6 +1085,18 @@ }; }; + icssg0_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + + icssg0_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + icssg0_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; @@ -1226,6 +1238,18 @@ }; }; + icssg1_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + + icssg1_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + icssg1_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; -- cgit v1.2.3 From 8af39a75c3705004445b8b4d86c69cc304e2ffbf Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:20:06 +0530 Subject: arm: dts: k3-am642-evm: Add ICSSG1 Ethernet support ICSSG1 provides dual Gigabit Ethernet support. Add ICSSG1 ethernet node to am64x device tree. Signed-off-by: MD Danish Anwar --- arch/arm/dts/k3-am642-evm-u-boot.dtsi | 44 +++++++++++++++ arch/arm/dts/k3-am642-evm.dts | 100 ++++++++++++++++++++++++++++++++++ 2 files changed, 144 insertions(+) diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi index e56bdea3d7..88a1e224df 100644 --- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi @@ -27,6 +27,50 @@ }; }; +&pru0_0 { + remoteproc-name = "pru0_0"; +}; + +&rtu0_0 { + remoteproc-name = "rtu0_0"; +}; + +&tx_pru0_0 { + remoteproc-name = "tx_pru0_0"; +}; + +&pru0_1 { + remoteproc-name = "pru0_1"; +}; + +&rtu0_1 { + remoteproc-name = "rtu0_1"; +}; + +&tx_pru0_1 { + remoteproc-name = "tx_pru0_1"; +}; + +&pru1_0 { + remoteproc-name = "pru1_0"; +}; + +&rtu1_0 { + remoteproc-name = "rtu1_0"; +}; + +&tx_pru1_0 { + remoteproc-name = "tx_pru1_0"; +}; + +&pru1_1 { + remoteproc-name = "pru1_1"; +}; + +&rtu1_1 { + remoteproc-name = "rtu1_1"; +}; + &main_conf { bootph-pre-ram; chipid@14 { diff --git a/arch/arm/dts/k3-am642-evm.dts b/arch/arm/dts/k3-am642-evm.dts index dcd8f7ba4c..a1f57670a6 100644 --- a/arch/arm/dts/k3-am642-evm.dts +++ b/arch/arm/dts/k3-am642-evm.dts @@ -21,6 +21,12 @@ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; + aliases { + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + ethernet2 = &icssg1_emac0; + }; + memory@80000000 { device_type = "memory"; /* 2G RAM */ @@ -198,6 +204,64 @@ max-bitrate = <5000000>; standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; }; + + icssg1_eth: icssg1-eth { + compatible = "ti,am642-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_rgmii1_pins_default>; + sram = <&oc_sram>; + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; + firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + ti,mii-g-rt = <&icssg1_mii_g_rt>; + ti,mii-rt = <&icssg1_mii_rt>; + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; + interrupt-parent = <&icssg1_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ + <&main_pktdma 0xc201 15>, /* egress slice 0 */ + <&main_pktdma 0xc202 15>, /* egress slice 0 */ + <&main_pktdma 0xc203 15>, /* egress slice 0 */ + <&main_pktdma 0xc204 15>, /* egress slice 1 */ + <&main_pktdma 0xc205 15>, /* egress slice 1 */ + <&main_pktdma 0xc206 15>, /* egress slice 1 */ + <&main_pktdma 0xc207 15>, /* egress slice 1 */ + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ + <&main_pktdma 0x4201 15>; /* ingress slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + icssg1_emac0: port@0 { + reg = <0>; + phy-handle = <&icssg1_phy1>; + phy-mode = "rgmii-id"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + icssg1_emac1: port@1 { + reg = <1>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + }; + }; + }; }; &main_pmx0 { @@ -329,6 +393,30 @@ AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ >; }; + + icssg1_mdio1_pins_default: icssg1-mdio1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */ + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */ + >; + }; + + icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins{ + pinctrl-single,pins = < + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ + AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ + AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ + AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ + AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ + AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ + >; + }; }; &main_uart0 { @@ -655,3 +743,15 @@ pinctrl-0 = <&main_mcan1_pins_default>; phys = <&transceiver2>; }; + +&icssg1_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_mdio1_pins_default>; + + icssg1_phy1: ethernet-phy@f { + reg = <0xf>; + tx-internal-delay-ps = <250>; + rx-internal-delay-ps = <2000>; + }; +}; -- cgit v1.2.3 From f098809ffefcb5f358a02c731d7eaf5c47bcc4a2 Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:20:07 +0530 Subject: configs: am64x_evm_a53: Enable ICSSG Driver Enable ICSSG driver, DP83869 phy driver, REMOTEPROC and PRU_REMOTEPROC in am64x_evm_a53_defconfig. All these configs are needed for ICSSG driver. Signed-off-by: MD Danish Anwar --- configs/am64x_evm_a53_defconfig | 5 +++++ configs/am64x_evm_r5_defconfig | 2 ++ 2 files changed, 7 insertions(+) diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index a6cccd06a4..396385f9cb 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -146,8 +146,10 @@ CONFIG_SPI_FLASH_MTD=y CONFIG_MULTIPLEXER=y CONFIG_MUX_MMIO=y CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_TI_DP83869=y CONFIG_PHY_FIXED=y CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_TI_ICSSG_PRUETH=y CONFIG_PHY=y CONFIG_SPL_PHY=y CONFIG_PHY_CADENCE_TORRENT=y @@ -164,11 +166,14 @@ CONFIG_DM_REGULATOR_TPS65219=y CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_REMOTEPROC_TI_K3_R5F=y +CONFIG_REMOTEPROC_TI_PRU=y +CONFIG_CMD_REMOTEPROC=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y CONFIG_SOC_DEVICE_TI_K3=y CONFIG_SOC_TI=y +CONFIG_TI_PRUSS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index 8a7d6a1b3a..09b300b4de 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -121,6 +121,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y +CONFIG_SPL_FS_LOADER=y CONFIG_ESM_K3=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y @@ -137,6 +138,7 @@ CONFIG_SPI_FLASH_S28HX_T=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MT35XU=y CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_TI_DP83869=y CONFIG_TI_AM65_CPSW_NUSS=y CONFIG_PHY=y CONFIG_SPL_PHY=y -- cgit v1.2.3 From 654724bbe4dae24cf91a085f2182f734b7db0554 Mon Sep 17 00:00:00 2001 From: MD Danish Anwar Date: Thu, 15 Feb 2024 15:20:08 +0530 Subject: board: ti: am64x: Set fw_storage_interface and fw_dev_part ENVs When ICSSG driver is enabled (CONFIG_TI_ICSSG_PRUETH=y) set fw_storage_interface and fw_dev_part env variables. These variables need be set appropriately in order to load differnet ICSSG firmwares needed for ICSSG driver. By default the storage interface is mmc and the partition is 1:2. User can modify this based on their needs. Signed-off-by: MD Danish Anwar --- board/ti/am64x/am64x.env | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/board/ti/am64x/am64x.env b/board/ti/am64x/am64x.env index cdb01bb6a1..53c7d8d679 100644 --- a/board/ti/am64x/am64x.env +++ b/board/ti/am64x/am64x.env @@ -56,3 +56,8 @@ usbboot=setenv boot usb; run get_kern_usb; run get_fdt_usb; run run_kern; + +#if CONFIG_TI_ICSSG_PRUETH +fw_storage_interface=mmc +fw_dev_part=1:2 +#endif -- cgit v1.2.3 From 6dc37a530cc2b642dc1d587e9c0b6d7d897bc455 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 15 Feb 2024 10:52:30 -0600 Subject: ram: k3-ddrss: limit only the am64x addressable range The AM64x and some of the AM62xx family of devices use the same 16b controller though only the AM64x is limited to 2GB addressable. Annoyingly the address alias detection machinery defaults to the full 8GB for the AM64x. Reset this value to 2GB only if we're initializin DDR on an am64x device Signed-off-by: Bryan Brattlof --- drivers/ram/k3-ddrss/k3-ddrss.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index a7a0b8bca9..2254ecc085 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -781,11 +781,11 @@ static int k3_ddrss_probe(struct udevice *dev) if (ret) return ret; -#ifdef CONFIG_K3_AM64_DDRSS - /* AM64x supports only up to 2 GB SDRAM */ - writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG); - writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG); -#endif + if (IS_ENABLED(CONFIG_SOC_K3_AM642)) { + /* AM64x supports only up to 2 GB SDRAM */ + writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG); + writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG); + } ddrss->driverdt = lpddr4_getinstance(); -- cgit v1.2.3 From 4cee7c94e8700ec1a3abd7efd2be4ca090938393 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 15 Feb 2024 10:52:31 -0600 Subject: ram: k3-ddrss: ram_ops should be a constant I do not think the R5 SPL will initialize non static variables (I didn't find and evidence of it) so we want to ensure this is a constant. Signed-off-by: Bryan Brattlof --- drivers/ram/k3-ddrss/k3-ddrss.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 2254ecc085..87741d3943 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -843,7 +843,7 @@ static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info) return 0; } -static struct ram_ops k3_ddrss_ops = { +static const struct ram_ops k3_ddrss_ops = { .get_info = k3_ddrss_get_info, }; -- cgit v1.2.3 From 8b666eba49a92d9abac144867a6a6e274d45ddd2 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 15 Feb 2024 10:52:32 -0600 Subject: arm: dts: k3-am62p-lp4: update to latest DDR configs After a little bit of debugging and characterization at different IO voltages, some of these values will need to change. Update to these latest settings to improve stability at higher IO voltages. Signed-off-by: Bryan Brattlof --- arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi | 128 +++++++++++++++-------------- 1 file changed, 65 insertions(+), 63 deletions(-) diff --git a/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi index b5fdba46a0..f664352015 100644 --- a/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi +++ b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62Px SysConfig DDR Subsystem Register Configuration Tool v0.09.10 - * Wed Aug 23 2023 17:48:42 GMT-0500 (Central Daylight Time) + * AM62Px SysConfig DDR Subsystem Register Configuration Tool v0.10.02 + * Thu Jan 25 2024 10:43:46 GMT-0600 (Central Standard Time) * DDR Type: LPDDR4 * F0 = 50MHz F1 = NA F2 = 1600MHz * Density (per channel): 16Gb @@ -12,6 +12,8 @@ #define DDRSS_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_1 800000000 #define DDRSS_PLL_FREQUENCY_2 800000000 +#define DDRSS_SDRAM_IDX 17 +#define DDRSS_REGION_IDX 17 #define DDRSS_CTL_0_DATA 0x00000B00 #define DDRSS_CTL_1_DATA 0x00000000 @@ -55,9 +57,9 @@ #define DDRSS_CTL_39_DATA 0x00000000 #define DDRSS_CTL_40_DATA 0x0000040C #define DDRSS_CTL_41_DATA 0x00000000 -#define DDRSS_CTL_42_DATA 0x00001040 +#define DDRSS_CTL_42_DATA 0x00000E38 #define DDRSS_CTL_43_DATA 0x00000000 -#define DDRSS_CTL_44_DATA 0x00001040 +#define DDRSS_CTL_44_DATA 0x00000E38 #define DDRSS_CTL_45_DATA 0x00000000 #define DDRSS_CTL_46_DATA 0x05000804 #define DDRSS_CTL_47_DATA 0x00000700 @@ -224,20 +226,20 @@ #define DDRSS_CTL_208_DATA 0x00000004 #define DDRSS_CTL_209_DATA 0x00000000 #define DDRSS_CTL_210_DATA 0x00000000 -#define DDRSS_CTL_211_DATA 0x00000064 -#define DDRSS_CTL_212_DATA 0x00000036 +#define DDRSS_CTL_211_DATA 0x00000054 +#define DDRSS_CTL_212_DATA 0x0000002D #define DDRSS_CTL_213_DATA 0x00000000 -#define DDRSS_CTL_214_DATA 0x00000064 -#define DDRSS_CTL_215_DATA 0x00000036 +#define DDRSS_CTL_214_DATA 0x00000054 +#define DDRSS_CTL_215_DATA 0x0000002D #define DDRSS_CTL_216_DATA 0x00000000 #define DDRSS_CTL_217_DATA 0x00000004 #define DDRSS_CTL_218_DATA 0x00000000 #define DDRSS_CTL_219_DATA 0x00000000 -#define DDRSS_CTL_220_DATA 0x00000064 -#define DDRSS_CTL_221_DATA 0x00000036 +#define DDRSS_CTL_220_DATA 0x00000054 +#define DDRSS_CTL_221_DATA 0x0000002D #define DDRSS_CTL_222_DATA 0x00000000 -#define DDRSS_CTL_223_DATA 0x00000064 -#define DDRSS_CTL_224_DATA 0x00000036 +#define DDRSS_CTL_223_DATA 0x00000054 +#define DDRSS_CTL_224_DATA 0x0000002D #define DDRSS_CTL_225_DATA 0x00000000 #define DDRSS_CTL_226_DATA 0x00000000 #define DDRSS_CTL_227_DATA 0x00000029 @@ -399,13 +401,13 @@ #define DDRSS_CTL_383_DATA 0x01000101 #define DDRSS_CTL_384_DATA 0x01010001 #define DDRSS_CTL_385_DATA 0x00010101 -#define DDRSS_CTL_386_DATA 0x010A0A03 +#define DDRSS_CTL_386_DATA 0x01080803 #define DDRSS_CTL_387_DATA 0x05020201 -#define DDRSS_CTL_388_DATA 0x0C081C1C -#define DDRSS_CTL_389_DATA 0x0008030C -#define DDRSS_CTL_390_DATA 0x0B12030E -#define DDRSS_CTL_391_DATA 0x0B120315 -#define DDRSS_CTL_392_DATA 0x12120815 +#define DDRSS_CTL_388_DATA 0x0C081818 +#define DDRSS_CTL_389_DATA 0x0008040C +#define DDRSS_CTL_390_DATA 0x0B100406 +#define DDRSS_CTL_391_DATA 0x0B100406 +#define DDRSS_CTL_392_DATA 0x10100806 #define DDRSS_CTL_393_DATA 0x01000000 #define DDRSS_CTL_394_DATA 0x06030601 #define DDRSS_CTL_395_DATA 0x04000103 @@ -417,8 +419,8 @@ #define DDRSS_CTL_401_DATA 0x00000200 #define DDRSS_CTL_402_DATA 0x00000693 #define DDRSS_CTL_403_DATA 0x00000E9C -#define DDRSS_CTL_404_DATA 0x03050202 -#define DDRSS_CTL_405_DATA 0x32200201 +#define DDRSS_CTL_404_DATA 0x03000202 +#define DDRSS_CTL_405_DATA 0x32200404 #define DDRSS_CTL_406_DATA 0x000030B0 #define DDRSS_CTL_407_DATA 0x00000200 #define DDRSS_CTL_408_DATA 0x00000200 @@ -426,8 +428,8 @@ #define DDRSS_CTL_410_DATA 0x00000200 #define DDRSS_CTL_411_DATA 0x0000DB18 #define DDRSS_CTL_412_DATA 0x0001E6E0 -#define DDRSS_CTL_413_DATA 0x131F0402 -#define DDRSS_CTL_414_DATA 0x32200C0D +#define DDRSS_CTL_413_DATA 0x0F160402 +#define DDRSS_CTL_414_DATA 0x32200A07 #define DDRSS_CTL_415_DATA 0x000030B0 #define DDRSS_CTL_416_DATA 0x00000200 #define DDRSS_CTL_417_DATA 0x00000200 @@ -435,8 +437,8 @@ #define DDRSS_CTL_419_DATA 0x00000200 #define DDRSS_CTL_420_DATA 0x0000DB18 #define DDRSS_CTL_421_DATA 0x0001E6E0 -#define DDRSS_CTL_422_DATA 0x131F0402 -#define DDRSS_CTL_423_DATA 0x00200C0D +#define DDRSS_CTL_422_DATA 0x0F160402 +#define DDRSS_CTL_423_DATA 0x00200A07 #define DDRSS_CTL_424_DATA 0x00000000 #define DDRSS_CTL_425_DATA 0x02000A00 #define DDRSS_CTL_426_DATA 0x00050003 @@ -447,7 +449,7 @@ #define DDRSS_CTL_431_DATA 0x02000201 #define DDRSS_CTL_432_DATA 0x02010000 #define DDRSS_CTL_433_DATA 0x06000200 -#define DDRSS_CTL_434_DATA 0x00002222 +#define DDRSS_CTL_434_DATA 0x00001E1E #define DDRSS_PI_0_DATA 0x00000B00 #define DDRSS_PI_1_DATA 0x00000000 #define DDRSS_PI_2_DATA 0x00000000 @@ -628,13 +630,13 @@ #define DDRSS_PI_177_DATA 0x00F000F0 #define DDRSS_PI_178_DATA 0x00202001 #define DDRSS_PI_179_DATA 0x00000034 -#define DDRSS_PI_180_DATA 0x0000005B -#define DDRSS_PI_181_DATA 0x0002005B +#define DDRSS_PI_180_DATA 0x00000057 +#define DDRSS_PI_181_DATA 0x00020057 #define DDRSS_PI_182_DATA 0x02000200 #define DDRSS_PI_183_DATA 0x00000004 -#define DDRSS_PI_184_DATA 0x0000100C -#define DDRSS_PI_185_DATA 0x00104000 -#define DDRSS_PI_186_DATA 0x00400000 +#define DDRSS_PI_184_DATA 0x00000E0C +#define DDRSS_PI_185_DATA 0x000E3800 +#define DDRSS_PI_186_DATA 0x00380000 #define DDRSS_PI_187_DATA 0x00000013 #define DDRSS_PI_188_DATA 0x000000BB #define DDRSS_PI_189_DATA 0x00000260 @@ -647,15 +649,15 @@ #define DDRSS_PI_196_DATA 0x01000100 #define DDRSS_PI_197_DATA 0x00000100 #define DDRSS_PI_198_DATA 0x00000000 -#define DDRSS_PI_199_DATA 0x050A0A03 -#define DDRSS_PI_200_DATA 0x01011C1C +#define DDRSS_PI_199_DATA 0x05080803 +#define DDRSS_PI_200_DATA 0x01011818 #define DDRSS_PI_201_DATA 0x01010101 #define DDRSS_PI_202_DATA 0x000C0C0A #define DDRSS_PI_203_DATA 0x00000000 #define DDRSS_PI_204_DATA 0x00000000 #define DDRSS_PI_205_DATA 0x04000000 -#define DDRSS_PI_206_DATA 0x0C021414 -#define DDRSS_PI_207_DATA 0x0404020C +#define DDRSS_PI_206_DATA 0x0A021010 +#define DDRSS_PI_207_DATA 0x0404020A #define DDRSS_PI_208_DATA 0x00090031 #define DDRSS_PI_209_DATA 0x00190041 #define DDRSS_PI_210_DATA 0x00190041 @@ -683,14 +685,14 @@ #define DDRSS_PI_232_DATA 0x00000190 #define DDRSS_PI_233_DATA 0x00001900 #define DDRSS_PI_234_DATA 0x32000056 -#define DDRSS_PI_235_DATA 0x06000301 -#define DDRSS_PI_236_DATA 0x00250204 -#define DDRSS_PI_237_DATA 0x3212005C -#define DDRSS_PI_238_DATA 0x17000301 -#define DDRSS_PI_239_DATA 0x00250C14 -#define DDRSS_PI_240_DATA 0x3212005C -#define DDRSS_PI_241_DATA 0x17000301 -#define DDRSS_PI_242_DATA 0x00000C14 +#define DDRSS_PI_235_DATA 0x06000101 +#define DDRSS_PI_236_DATA 0x00230204 +#define DDRSS_PI_237_DATA 0x3212005A +#define DDRSS_PI_238_DATA 0x13000101 +#define DDRSS_PI_239_DATA 0x00230A10 +#define DDRSS_PI_240_DATA 0x3212005A +#define DDRSS_PI_241_DATA 0x13000101 +#define DDRSS_PI_242_DATA 0x00000A10 #define DDRSS_PI_243_DATA 0x05030900 #define DDRSS_PI_244_DATA 0x00040900 #define DDRSS_PI_245_DATA 0x0000062B @@ -785,16 +787,16 @@ #define DDRSS_PI_334_DATA 0x00000000 #define DDRSS_PI_335_DATA 0x20002B27 #define DDRSS_PI_336_DATA 0x00000000 -#define DDRSS_PI_337_DATA 0x00000064 -#define DDRSS_PI_338_DATA 0x00000036 +#define DDRSS_PI_337_DATA 0x00000054 +#define DDRSS_PI_338_DATA 0x0000002D #define DDRSS_PI_339_DATA 0x000000A9 #define DDRSS_PI_340_DATA 0x00000000 #define DDRSS_PI_341_DATA 0x00000000 #define DDRSS_PI_342_DATA 0x35000000 #define DDRSS_PI_343_DATA 0x20152B27 #define DDRSS_PI_344_DATA 0x00000000 -#define DDRSS_PI_345_DATA 0x00000064 -#define DDRSS_PI_346_DATA 0x00000036 +#define DDRSS_PI_345_DATA 0x00000054 +#define DDRSS_PI_346_DATA 0x0000002D #define DDRSS_PI_347_DATA 0x000000A9 #define DDRSS_PI_348_DATA 0x00000000 #define DDRSS_PI_349_DATA 0x00000000 @@ -809,16 +811,16 @@ #define DDRSS_PI_358_DATA 0x00000000 #define DDRSS_PI_359_DATA 0x20002B27 #define DDRSS_PI_360_DATA 0x00000000 -#define DDRSS_PI_361_DATA 0x00000064 -#define DDRSS_PI_362_DATA 0x00000036 +#define DDRSS_PI_361_DATA 0x00000054 +#define DDRSS_PI_362_DATA 0x0000002D #define DDRSS_PI_363_DATA 0x000000A9 #define DDRSS_PI_364_DATA 0x00000000 #define DDRSS_PI_365_DATA 0x00000000 #define DDRSS_PI_366_DATA 0x35000000 #define DDRSS_PI_367_DATA 0x20152B27 #define DDRSS_PI_368_DATA 0x00000000 -#define DDRSS_PI_369_DATA 0x00000064 -#define DDRSS_PI_370_DATA 0x00000036 +#define DDRSS_PI_369_DATA 0x00000054 +#define DDRSS_PI_370_DATA 0x0000002D #define DDRSS_PI_371_DATA 0x000000A9 #define DDRSS_PI_372_DATA 0x00000000 #define DDRSS_PI_373_DATA 0x00000000 @@ -833,16 +835,16 @@ #define DDRSS_PI_382_DATA 0x00000000 #define DDRSS_PI_383_DATA 0x20002B27 #define DDRSS_PI_384_DATA 0x00000000 -#define DDRSS_PI_385_DATA 0x00000064 -#define DDRSS_PI_386_DATA 0x00000036 +#define DDRSS_PI_385_DATA 0x00000054 +#define DDRSS_PI_386_DATA 0x0000002D #define DDRSS_PI_387_DATA 0x000000A9 #define DDRSS_PI_388_DATA 0x00000000 #define DDRSS_PI_389_DATA 0x00000000 #define DDRSS_PI_390_DATA 0x35000000 #define DDRSS_PI_391_DATA 0x20152B27 #define DDRSS_PI_392_DATA 0x00000000 -#define DDRSS_PI_393_DATA 0x00000064 -#define DDRSS_PI_394_DATA 0x00000036 +#define DDRSS_PI_393_DATA 0x00000054 +#define DDRSS_PI_394_DATA 0x0000002D #define DDRSS_PI_395_DATA 0x000000A9 #define DDRSS_PI_396_DATA 0x00000000 #define DDRSS_PI_397_DATA 0x00000000 @@ -857,16 +859,16 @@ #define DDRSS_PI_406_DATA 0x00000000 #define DDRSS_PI_407_DATA 0x20002B27 #define DDRSS_PI_408_DATA 0x00000000 -#define DDRSS_PI_409_DATA 0x00000064 -#define DDRSS_PI_410_DATA 0x00000036 +#define DDRSS_PI_409_DATA 0x00000054 +#define DDRSS_PI_410_DATA 0x0000002D #define DDRSS_PI_411_DATA 0x000000A9 #define DDRSS_PI_412_DATA 0x00000000 #define DDRSS_PI_413_DATA 0x00000000 #define DDRSS_PI_414_DATA 0x35000000 #define DDRSS_PI_415_DATA 0x20152B27 #define DDRSS_PI_416_DATA 0x00000000 -#define DDRSS_PI_417_DATA 0x00000064 -#define DDRSS_PI_418_DATA 0x00000036 +#define DDRSS_PI_417_DATA 0x00000054 +#define DDRSS_PI_418_DATA 0x0000002D #define DDRSS_PI_419_DATA 0x000000A9 #define DDRSS_PI_420_DATA 0x00000000 #define DDRSS_PI_421_DATA 0x00000000 @@ -952,7 +954,7 @@ #define DDRSS_PHY_77_DATA 0x00000401 #define DDRSS_PHY_78_DATA 0x00000000 #define DDRSS_PHY_79_DATA 0x01CC0B01 -#define DDRSS_PHY_80_DATA 0x1003CC0C +#define DDRSS_PHY_80_DATA 0x1003CC0B #define DDRSS_PHY_81_DATA 0x20000140 #define DDRSS_PHY_82_DATA 0x07FF0200 #define DDRSS_PHY_83_DATA 0x0000DD01 @@ -1208,7 +1210,7 @@ #define DDRSS_PHY_333_DATA 0x00000401 #define DDRSS_PHY_334_DATA 0x00000000 #define DDRSS_PHY_335_DATA 0x01CC0B01 -#define DDRSS_PHY_336_DATA 0x1003CC0C +#define DDRSS_PHY_336_DATA 0x1003CC0B #define DDRSS_PHY_337_DATA 0x20000140 #define DDRSS_PHY_338_DATA 0x07FF0200 #define DDRSS_PHY_339_DATA 0x0000DD01 @@ -1464,7 +1466,7 @@ #define DDRSS_PHY_589_DATA 0x00000401 #define DDRSS_PHY_590_DATA 0x00000000 #define DDRSS_PHY_591_DATA 0x01CC0B01 -#define DDRSS_PHY_592_DATA 0x1003CC0C +#define DDRSS_PHY_592_DATA 0x1003CC0B #define DDRSS_PHY_593_DATA 0x20000140 #define DDRSS_PHY_594_DATA 0x07FF0200 #define DDRSS_PHY_595_DATA 0x0000DD01 @@ -1720,7 +1722,7 @@ #define DDRSS_PHY_845_DATA 0x00000401 #define DDRSS_PHY_846_DATA 0x00000000 #define DDRSS_PHY_847_DATA 0x01CC0B01 -#define DDRSS_PHY_848_DATA 0x1003CC0C +#define DDRSS_PHY_848_DATA 0x1003CC0B #define DDRSS_PHY_849_DATA 0x20000140 #define DDRSS_PHY_850_DATA 0x07FF0200 #define DDRSS_PHY_851_DATA 0x0000DD01 @@ -2789,7 +2791,7 @@ #define DDRSS_PHY_1914_DATA 0x0089FF00 #define DDRSS_PHY_1915_DATA 0x000C3F11 #define DDRSS_PHY_1916_DATA 0x01990000 -#define DDRSS_PHY_1917_DATA 0x000C3F11 +#define DDRSS_PHY_1917_DATA 0x000C3F91 #define DDRSS_PHY_1918_DATA 0x01990000 #define DDRSS_PHY_1919_DATA 0x3F0DFF11 #define DDRSS_PHY_1920_DATA 0x00EF0000 -- cgit v1.2.3 From d46ffd005dd5185bd14b212905fe6823d10adc67 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 15 Feb 2024 10:52:33 -0600 Subject: arm: dts: k3-am62a-lp4: update to latest output from the emif tool After a little debugging on the am62px some of these values will need to be changed. Update to these new values to improve stability at higher IO voltages. Signed-off-by: Bryan Brattlof --- arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi | 42 +++++++++++++++------------- 1 file changed, 22 insertions(+), 20 deletions(-) diff --git a/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi b/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi index 9f50d7eae6..d6d8736dde 100644 --- a/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi +++ b/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62A SysConfig DDR Subsystem Register Configuration Tool v0.09.01 - * Wed Aug 10 2022 17:34:54 GMT-0500 (Central Daylight Time) + * AM62Ax SysConfig DDR Subsystem Register Configuration Tool v0.10.02 + * Thu Jan 25 2024 10:38:48 GMT-0600 (Central Standard Time) * DDR Type: LPDDR4 * F0 = 50MHz F1 = NA F2 = 1866MHz * Density (per channel): 8Gb @@ -12,6 +12,8 @@ #define DDRSS_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_1 933000000 #define DDRSS_PLL_FREQUENCY_2 933000000 +#define DDRSS_SDRAM_IDX 16 +#define DDRSS_REGION_IDX 17 #define DDRSS_CTL_0_DATA 0x00000B00 #define DDRSS_CTL_1_DATA 0x00000000 @@ -402,10 +404,10 @@ #define DDRSS_CTL_386_DATA 0x01090903 #define DDRSS_CTL_387_DATA 0x05020201 #define DDRSS_CTL_388_DATA 0x0E081B1B -#define DDRSS_CTL_389_DATA 0x0008030E -#define DDRSS_CTL_390_DATA 0x0B12030E -#define DDRSS_CTL_391_DATA 0x0B120314 -#define DDRSS_CTL_392_DATA 0x12120814 +#define DDRSS_CTL_389_DATA 0x0008040E +#define DDRSS_CTL_390_DATA 0x0B120406 +#define DDRSS_CTL_391_DATA 0x0B120406 +#define DDRSS_CTL_392_DATA 0x12120806 #define DDRSS_CTL_393_DATA 0x01000000 #define DDRSS_CTL_394_DATA 0x07030701 #define DDRSS_CTL_395_DATA 0x04000103 @@ -417,8 +419,8 @@ #define DDRSS_CTL_401_DATA 0x00000200 #define DDRSS_CTL_402_DATA 0x00000693 #define DDRSS_CTL_403_DATA 0x00000E9C -#define DDRSS_CTL_404_DATA 0x03050202 -#define DDRSS_CTL_405_DATA 0x37200201 +#define DDRSS_CTL_404_DATA 0x03000202 +#define DDRSS_CTL_405_DATA 0x37200404 #define DDRSS_CTL_406_DATA 0x000038C8 #define DDRSS_CTL_407_DATA 0x00000200 #define DDRSS_CTL_408_DATA 0x00000200 @@ -426,8 +428,8 @@ #define DDRSS_CTL_410_DATA 0x00000200 #define DDRSS_CTL_411_DATA 0x0000FF84 #define DDRSS_CTL_412_DATA 0x000237D0 -#define DDRSS_CTL_413_DATA 0x111F0402 -#define DDRSS_CTL_414_DATA 0x37200C0D +#define DDRSS_CTL_413_DATA 0x111A0402 +#define DDRSS_CTL_414_DATA 0x37200C09 #define DDRSS_CTL_415_DATA 0x000038C8 #define DDRSS_CTL_416_DATA 0x00000200 #define DDRSS_CTL_417_DATA 0x00000200 @@ -435,8 +437,8 @@ #define DDRSS_CTL_419_DATA 0x00000200 #define DDRSS_CTL_420_DATA 0x0000FF84 #define DDRSS_CTL_421_DATA 0x000237D0 -#define DDRSS_CTL_422_DATA 0x111F0402 -#define DDRSS_CTL_423_DATA 0x00200C0D +#define DDRSS_CTL_422_DATA 0x111A0402 +#define DDRSS_CTL_423_DATA 0x00200C09 #define DDRSS_CTL_424_DATA 0x00000000 #define DDRSS_CTL_425_DATA 0x02000A00 #define DDRSS_CTL_426_DATA 0x00050003 @@ -964,7 +966,7 @@ #define DDRSS_PHY_89_DATA 0x00100010 #define DDRSS_PHY_90_DATA 0x00100010 #define DDRSS_PHY_91_DATA 0x00100010 -#define DDRSS_PHY_92_DATA 0x02040010 +#define DDRSS_PHY_92_DATA 0x02000010 #define DDRSS_PHY_93_DATA 0x00000005 #define DDRSS_PHY_94_DATA 0x51516042 #define DDRSS_PHY_95_DATA 0x31C06000 @@ -1220,7 +1222,7 @@ #define DDRSS_PHY_345_DATA 0x00100010 #define DDRSS_PHY_346_DATA 0x00100010 #define DDRSS_PHY_347_DATA 0x00100010 -#define DDRSS_PHY_348_DATA 0x02040010 +#define DDRSS_PHY_348_DATA 0x02000010 #define DDRSS_PHY_349_DATA 0x00000005 #define DDRSS_PHY_350_DATA 0x51516042 #define DDRSS_PHY_351_DATA 0x31C06000 @@ -1476,7 +1478,7 @@ #define DDRSS_PHY_601_DATA 0x00100010 #define DDRSS_PHY_602_DATA 0x00100010 #define DDRSS_PHY_603_DATA 0x00100010 -#define DDRSS_PHY_604_DATA 0x02040010 +#define DDRSS_PHY_604_DATA 0x02000010 #define DDRSS_PHY_605_DATA 0x00000005 #define DDRSS_PHY_606_DATA 0x51516042 #define DDRSS_PHY_607_DATA 0x31C06000 @@ -1732,7 +1734,7 @@ #define DDRSS_PHY_857_DATA 0x00100010 #define DDRSS_PHY_858_DATA 0x00100010 #define DDRSS_PHY_859_DATA 0x00100010 -#define DDRSS_PHY_860_DATA 0x02040010 +#define DDRSS_PHY_860_DATA 0x02000010 #define DDRSS_PHY_861_DATA 0x00000005 #define DDRSS_PHY_862_DATA 0x51516042 #define DDRSS_PHY_863_DATA 0x31C06000 @@ -2699,7 +2701,7 @@ #define DDRSS_PHY_1824_DATA 0x0F0F0804 #define DDRSS_PHY_1825_DATA 0x00800120 #define DDRSS_PHY_1826_DATA 0x00041B42 -#define DDRSS_PHY_1827_DATA 0x00005201 +#define DDRSS_PHY_1827_DATA 0x00004201 #define DDRSS_PHY_1828_DATA 0x00000000 #define DDRSS_PHY_1829_DATA 0x00000000 #define DDRSS_PHY_1830_DATA 0x00000000 @@ -2760,7 +2762,7 @@ #define DDRSS_PHY_1885_DATA 0x00000002 #define DDRSS_PHY_1886_DATA 0x00000000 #define DDRSS_PHY_1887_DATA 0x00000000 -#define DDRSS_PHY_1888_DATA 0x00000AC4 +#define DDRSS_PHY_1888_DATA 0x0001F7C4 #define DDRSS_PHY_1889_DATA 0x04000004 #define DDRSS_PHY_1890_DATA 0x00000000 #define DDRSS_PHY_1891_DATA 0x00001142 @@ -2789,10 +2791,10 @@ #define DDRSS_PHY_1914_DATA 0x0089FF00 #define DDRSS_PHY_1915_DATA 0x000C3F11 #define DDRSS_PHY_1916_DATA 0x01990000 -#define DDRSS_PHY_1917_DATA 0x000C3F11 +#define DDRSS_PHY_1917_DATA 0x000C3F91 #define DDRSS_PHY_1918_DATA 0x01990000 #define DDRSS_PHY_1919_DATA 0x3F0DFF11 #define DDRSS_PHY_1920_DATA 0x00EF0000 #define DDRSS_PHY_1921_DATA 0x00018011 #define DDRSS_PHY_1922_DATA 0x0089FF00 -#define DDRSS_PHY_1923_DATA 0x20040004 +#define DDRSS_PHY_1923_DATA 0x20040006 -- cgit v1.2.3 From 26addd010d29b7662177bfa791fc66b93d2099a2 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 15 Feb 2024 10:52:34 -0600 Subject: arm: dts: k3-am62x-ddr: update to latest output from emif tool The output from the emif tool hasn't changes in a long while however there are some differences. Update to these latest settings. Signed-off-by: Bryan Brattlof --- arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi index d92e3ce048..b5f0e40c16 100644 --- a/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi +++ b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.08.60 - * Wed Mar 16 2022 17:41:20 GMT-0500 (Central Daylight Time) + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.07 + * Tue Feb 28 2023 14:47:40 GMT-0600 (Central Standard Time) * DDR Type: DDR4 * Frequency = 800MHz (1600MTs) * Density: 16Gb @@ -334,7 +334,7 @@ #define DDRSS_CTL_318_DATA 0x3FFF0000 #define DDRSS_CTL_319_DATA 0x000FFF00 #define DDRSS_CTL_320_DATA 0xFFFFFFFF -#define DDRSS_CTL_321_DATA 0x000FFF00 +#define DDRSS_CTL_321_DATA 0x00FFFF00 #define DDRSS_CTL_322_DATA 0x0A000000 #define DDRSS_CTL_323_DATA 0x0001FFFF #define DDRSS_CTL_324_DATA 0x01010101 @@ -901,7 +901,7 @@ #define DDRSS_PHY_117_DATA 0x00800080 #define DDRSS_PHY_118_DATA 0x00800080 #define DDRSS_PHY_119_DATA 0x01000080 -#define DDRSS_PHY_120_DATA 0x01A00000 +#define DDRSS_PHY_120_DATA 0x01000000 #define DDRSS_PHY_121_DATA 0x00000000 #define DDRSS_PHY_122_DATA 0x00000000 #define DDRSS_PHY_123_DATA 0x00080200 @@ -1157,7 +1157,7 @@ #define DDRSS_PHY_373_DATA 0x00800080 #define DDRSS_PHY_374_DATA 0x00800080 #define DDRSS_PHY_375_DATA 0x01000080 -#define DDRSS_PHY_376_DATA 0x01A00000 +#define DDRSS_PHY_376_DATA 0x01000000 #define DDRSS_PHY_377_DATA 0x00000000 #define DDRSS_PHY_378_DATA 0x00000000 #define DDRSS_PHY_379_DATA 0x00080200 @@ -2152,7 +2152,7 @@ #define DDRSS_PHY_1368_DATA 0x00000002 #define DDRSS_PHY_1369_DATA 0x00000100 #define DDRSS_PHY_1370_DATA 0x00000000 -#define DDRSS_PHY_1371_DATA 0x0001F7C0 +#define DDRSS_PHY_1371_DATA 0x0001F7C2 #define DDRSS_PHY_1372_DATA 0x00020002 #define DDRSS_PHY_1373_DATA 0x00000000 #define DDRSS_PHY_1374_DATA 0x00001142 -- cgit v1.2.3 From 7ef03ff8bf93205f73ac94238cd74d58e5c53c43 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 15 Feb 2024 10:52:35 -0600 Subject: arm: dts: k3-am62x-lp4: update to latest emif tool output The output from the emif tool hasn't changed for a while now, however there is still a difference from what we use. Signed-off-by: Bryan Brattlof --- arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi | 34 +++++++++++++-------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi b/arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi index 74693d12e1..c255ae6530 100644 --- a/arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi +++ b/arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi @@ -1,15 +1,16 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.08.61 - * Tue Mar 22 2022 17:03:08 GMT-0500 (Central Daylight Time) + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.07 + * Wed Mar 01 2023 17:52:11 GMT-0600 (Central Standard Time) * DDR Type: LPDDR4 - * F0 = 50MHz F1 = 800MHz F2 = 800MHz + * F0 = 50MHz F1 = NA F2 = 800MHz * Density (per channel): 16Gb + * Write DBI: Enable * Number of Ranks: 1 */ -#define DDRSS_PLL_FHS_CNT 6 +#define DDRSS_PLL_FHS_CNT 3 #define DDRSS_PLL_FREQUENCY_1 400000000 #define DDRSS_PLL_FREQUENCY_2 400000000 @@ -283,10 +284,10 @@ #define DDRSS_CTL_267_DATA 0x0000000F #define DDRSS_CTL_268_DATA 0x0000000F #define DDRSS_CTL_269_DATA 0x00000000 -#define DDRSS_CTL_270_DATA 0x00000000 +#define DDRSS_CTL_270_DATA 0x00001000 #define DDRSS_CTL_271_DATA 0x00000015 #define DDRSS_CTL_272_DATA 0x00000015 -#define DDRSS_CTL_273_DATA 0x00000000 +#define DDRSS_CTL_273_DATA 0x00000010 #define DDRSS_CTL_274_DATA 0x00000015 #define DDRSS_CTL_275_DATA 0x00000015 #define DDRSS_CTL_276_DATA 0x00000020 @@ -334,7 +335,7 @@ #define DDRSS_CTL_318_DATA 0x3FFF0000 #define DDRSS_CTL_319_DATA 0x000FFF00 #define DDRSS_CTL_320_DATA 0xFFFFFFFF -#define DDRSS_CTL_321_DATA 0x000FFF00 +#define DDRSS_CTL_321_DATA 0x00FFFF00 #define DDRSS_CTL_322_DATA 0x0B000000 #define DDRSS_CTL_323_DATA 0x0001FFFF #define DDRSS_CTL_324_DATA 0x01010101 @@ -448,7 +449,7 @@ #define DDRSS_PI_9_DATA 0x00000000 #define DDRSS_PI_10_DATA 0x00000000 #define DDRSS_PI_11_DATA 0x00000002 -#define DDRSS_PI_12_DATA 0x00000007 +#define DDRSS_PI_12_DATA 0x00000005 #define DDRSS_PI_13_DATA 0x00010001 #define DDRSS_PI_14_DATA 0x08000000 #define DDRSS_PI_15_DATA 0x00010300 @@ -479,7 +480,7 @@ #define DDRSS_PI_40_DATA 0x000000A9 #define DDRSS_PI_41_DATA 0x000000A9 #define DDRSS_PI_42_DATA 0x000000B5 -#define DDRSS_PI_43_DATA 0x01000000 +#define DDRSS_PI_43_DATA 0x00000000 #define DDRSS_PI_44_DATA 0x00000000 #define DDRSS_PI_45_DATA 0x00010100 #define DDRSS_PI_46_DATA 0x00000015 @@ -507,7 +508,7 @@ #define DDRSS_PI_68_DATA 0x00000034 #define DDRSS_PI_69_DATA 0x00000000 #define DDRSS_PI_70_DATA 0x00000000 -#define DDRSS_PI_71_DATA 0x0001FFFF +#define DDRSS_PI_71_DATA 0x0000FFFF #define DDRSS_PI_72_DATA 0x00000000 #define DDRSS_PI_73_DATA 0x00000000 #define DDRSS_PI_74_DATA 0x00000000 @@ -740,7 +741,7 @@ #define DDRSS_PI_301_DATA 0x00000000 #define DDRSS_PI_302_DATA 0x00000000 #define DDRSS_PI_303_DATA 0x00000000 -#define DDRSS_PI_304_DATA 0x00000F27 +#define DDRSS_PI_304_DATA 0x00100F27 #define DDRSS_PI_305_DATA 0x00000000 #define DDRSS_PI_306_DATA 0x00000024 #define DDRSS_PI_307_DATA 0x00000012 @@ -764,7 +765,7 @@ #define DDRSS_PI_325_DATA 0x00000000 #define DDRSS_PI_326_DATA 0x00000000 #define DDRSS_PI_327_DATA 0x00000000 -#define DDRSS_PI_328_DATA 0x00000F27 +#define DDRSS_PI_328_DATA 0x00100F27 #define DDRSS_PI_329_DATA 0x00000000 #define DDRSS_PI_330_DATA 0x00000024 #define DDRSS_PI_331_DATA 0x00000012 @@ -901,7 +902,7 @@ #define DDRSS_PHY_117_DATA 0x00800080 #define DDRSS_PHY_118_DATA 0x00800080 #define DDRSS_PHY_119_DATA 0x01800080 -#define DDRSS_PHY_120_DATA 0x01A00001 +#define DDRSS_PHY_120_DATA 0x01000000 #define DDRSS_PHY_121_DATA 0x00000000 #define DDRSS_PHY_122_DATA 0x00000000 #define DDRSS_PHY_123_DATA 0x00080200 @@ -1157,7 +1158,7 @@ #define DDRSS_PHY_373_DATA 0x00800080 #define DDRSS_PHY_374_DATA 0x00800080 #define DDRSS_PHY_375_DATA 0x01800080 -#define DDRSS_PHY_376_DATA 0x01A00001 +#define DDRSS_PHY_376_DATA 0x01000000 #define DDRSS_PHY_377_DATA 0x00000000 #define DDRSS_PHY_378_DATA 0x00000000 #define DDRSS_PHY_379_DATA 0x00080200 @@ -2152,7 +2153,7 @@ #define DDRSS_PHY_1368_DATA 0x00000002 #define DDRSS_PHY_1369_DATA 0x00000000 #define DDRSS_PHY_1370_DATA 0x00000000 -#define DDRSS_PHY_1371_DATA 0x0001F7C0 +#define DDRSS_PHY_1371_DATA 0x0001F7C2 #define DDRSS_PHY_1372_DATA 0x00020002 #define DDRSS_PHY_1373_DATA 0x00000000 #define DDRSS_PHY_1374_DATA 0x00001142 @@ -2183,8 +2184,7 @@ #define DDRSS_PHY_1399_DATA 0x000C3F11 #define DDRSS_PHY_1400_DATA 0x01990000 #define DDRSS_PHY_1401_DATA 0x3F0DFF11 -#define DDRSS_PHY_1402_DATA 0x019900E0 +#define DDRSS_PHY_1402_DATA 0x01990000 #define DDRSS_PHY_1403_DATA 0x00018011 #define DDRSS_PHY_1404_DATA 0x0089FF00 #define DDRSS_PHY_1405_DATA 0x20040004 - -- cgit v1.2.3 From 7d050099177240f6cdf8992310f2cf4941e954af Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Thu, 15 Feb 2024 23:15:42 +0530 Subject: board: ti: j721s2: Move order of AVS probing AVS driver was getting probed with base device tree, which leads i2c of derivative board (AM68) in bad state. Moving AVS probe after detection of right device tree. Fixes: eaa184009775 ("arm: k3: j721s2: Enable AVS") Reported-by: Minas Hambardzumyan Cc: Manorit Chawdhry Cc: Vignesh Raghavendra Cc: Praneeth Bajjuri Signed-off-by: Udit Kumar --- arch/arm/mach-k3/j721s2_init.c | 6 ------ board/ti/j721s2/evm.c | 9 +++++++++ 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c index 6995099a21..90324ce096 100644 --- a/arch/arm/mach-k3/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2_init.c @@ -208,12 +208,6 @@ void k3_spl_init(void) /* Output System Firmware version info */ k3_sysfw_print_ver(); - if (IS_ENABLED(CONFIG_K3_AVS0)) { - ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs), - &dev); - if (ret) - printf("AVS init failed: %d\n", ret); - } } bool check_rom_loaded_sysfw(void) diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index 3847587961..1bde20a17d 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -447,10 +447,19 @@ void do_dt_magic(void) #ifdef CONFIG_SPL_BUILD void board_init_f(ulong dummy) { + struct udevice *dev; + int ret; k3_spl_init(); #if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT) do_dt_magic(); #endif k3_mem_init(); + + if (IS_ENABLED(CONFIG_K3_AVS0) && board_is_j721s2_som()) { + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs), + &dev); + if (ret) + printf("AVS init failed: %d\n", ret); + } } #endif -- cgit v1.2.3 From 1a59dc85127fb25edf78be85495cac15da5f3a1e Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Fri, 16 Feb 2024 16:34:21 +0530 Subject: dma: ti: k3-udma: Fix ring_idx to pair k3 nav rings" OSPI boot was broken due to wrong pairing of DMA Fixes: 61ea32c0eb0c ("dma: ti: k3-udma: Use ring_idx to pair k3 nav rings") Reported-by: Minas Hambardzumyan Cc: MD Danish Anwar Cc: Vignesh Raghavendra Cc: Praneeth Bajjuri Signed-off-by: Udit Kumar --- drivers/dma/ti/k3-udma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index bdaadc9e78..0bcf03b26d 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -883,10 +883,10 @@ static int udma_alloc_tx_resources(struct udma_chan *uc) return ret; tchan = uc->tchan; - if (tchan->tflow_id >= 0) + if (tchan->tflow_id > 0) ring_idx = tchan->tflow_id; else - ring_idx = ud->bchan_cnt + tchan->id; + ring_idx = tchan->id; ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1, &uc->tchan->t_ring, -- cgit v1.2.3 From 932fe2b754628ad6a271e92a2a76ab785386e59a Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Mon, 19 Feb 2024 14:11:39 +0530 Subject: configs: j784s4_evm: Update offset for emmc and OSPI On AM69 board, build image was going beyond wrt defined offsets. So increasing offset for eMMC and OSPI boot. Along with update in corresponding device tree. Cc: Neha Francis Cc: Vaishnav Achath Cc: Apurva Nandan Signed-off-by: Udit Kumar Reviewed-by: Neha Malcom Francis Tested-by: Beleswar Padhi --- arch/arm/dts/k3-am69-sk.dts | 18 +++++++++--------- arch/arm/dts/k3-j784s4-evm.dts | 36 ++++++++++++++++++------------------ configs/j784s4_evm_a72_defconfig | 6 +++--- configs/j784s4_evm_r5_defconfig | 6 +++--- 4 files changed, 33 insertions(+), 33 deletions(-) diff --git a/arch/arm/dts/k3-am69-sk.dts b/arch/arm/dts/k3-am69-sk.dts index 508fbee411..f49721039f 100644 --- a/arch/arm/dts/k3-am69-sk.dts +++ b/arch/arm/dts/k3-am69-sk.dts @@ -272,27 +272,27 @@ partition@0 { label = "ospi.tiboot3"; - reg = <0x0 0x80000>; + reg = <0x0 0x100000>; }; - partition@80000 { + partition@100000 { label = "ospi.tispl"; - reg = <0x80000 0x200000>; + reg = <0x100000 0x200000>; }; - partition@280000 { + partition@300000 { label = "ospi.u-boot"; - reg = <0x280000 0x400000>; + reg = <0x300000 0x400000>; }; - partition@680000 { + partition@700000 { label = "ospi.env"; - reg = <0x680000 0x40000>; + reg = <0x700000 0x40000>; }; - partition@6c0000 { + partition@740000 { label = "ospi.env.backup"; - reg = <0x6c0000 0x40000>; + reg = <0x740000 0x40000>; }; partition@800000 { diff --git a/arch/arm/dts/k3-j784s4-evm.dts b/arch/arm/dts/k3-j784s4-evm.dts index e936a82002..539471c805 100644 --- a/arch/arm/dts/k3-j784s4-evm.dts +++ b/arch/arm/dts/k3-j784s4-evm.dts @@ -718,27 +718,27 @@ partition@0 { label = "ospi.tiboot3"; - reg = <0x0 0x80000>; + reg = <0x0 0x100000>; }; - partition@80000 { + partition@100000 { label = "ospi.tispl"; - reg = <0x80000 0x200000>; + reg = <0x100000 0x200000>; }; - partition@280000 { + partition@300000 { label = "ospi.u-boot"; - reg = <0x280000 0x400000>; + reg = <0x300000 0x400000>; }; - partition@680000 { + partition@700000 { label = "ospi.env"; - reg = <0x680000 0x40000>; + reg = <0x700000 0x40000>; }; - partition@6c0000 { + partition@740000 { label = "ospi.env.backup"; - reg = <0x6c0000 0x40000>; + reg = <0x740000 0x40000>; }; partition@800000 { @@ -773,27 +773,27 @@ partition@0 { label = "ospi_nand.tiboot3"; - reg = <0x0 0x80000>; + reg = <0x0 0x100000>; }; - partition@80000 { + partition@100000 { label = "ospi_nand.tispl"; - reg = <0x80000 0x200000>; + reg = <0x100000 0x200000>; }; - partition@280000 { + partition@300000 { label = "ospi_nand.u-boot"; - reg = <0x280000 0x400000>; + reg = <0x300000 0x400000>; }; - partition@680000 { + partition@700000 { label = "ospi_nand.env"; - reg = <0x680000 0x40000>; + reg = <0x700000 0x40000>; }; - partition@6c0000 { + partition@740000 { label = "ospi_nand.env.backup"; - reg = <0x6c0000 0x40000>; + reg = <0x740000 0x40000>; }; partition@2000000 { diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index 73a47c9074..4c958a959c 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -45,7 +45,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" @@ -53,7 +53,7 @@ CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_MTD_LOAD=y -CONFIG_SYS_MTD_U_BOOT_OFFS=0x280000 +CONFIG_SYS_MTD_U_BOOT_OFFS=0x300000 CONFIG_SPL_NAND_SPI_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y # CONFIG_SPL_NOR_SUPPORT=y @@ -64,7 +64,7 @@ CONFIG_SPL_RAM_DEVICE=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x300000 CONFIG_SPL_THERMAL=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index e892603118..3b8f032094 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -17,7 +17,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_SPL_SIZE_LIMIT=0x80000 +CONFIG_SPL_SIZE_LIMIT=0x100000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y @@ -53,7 +53,7 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y @@ -72,7 +72,7 @@ CONFIG_SPL_REMOTEPROC=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SPL_THERMAL=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y -- cgit v1.2.3 From 8712298323f049c73a4a3b5ba017865d75bb678d Mon Sep 17 00:00:00 2001 From: Santhosh Kumar K Date: Wed, 21 Feb 2024 13:07:07 +0530 Subject: board: ti: am6*x: evm: Fix up incorrect RAM size for AM62A and AM62P The fixup_memory_node() does no change in AM64, AM62A and AM62P when ECC is not enabled. Instead, it causes an issue of fixing up the RAM size as 2GB instead of 4GB and 8GB for AM62A and AM62P because the fix up is done by the R5 SPL and R5 being a 32-bit processor, the gd->bd->bi_dram[bank].start and gd->bd->bi_dram[bank].size values are restricted to 32-bits. So, remove the fixup_memory_node() from spl_perform_fixups() in AM64, AM62A and AM62P's evm files. Fixes: 410888e38c7e ("board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled") Signed-off-by: Santhosh Kumar K Reviewed-by: Neha Malcom Francis --- board/ti/am62ax/evm.c | 2 -- board/ti/am62px/evm.c | 2 -- board/ti/am64x/evm.c | 2 -- 3 files changed, 6 deletions(-) diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c index 8b3fced0a2..6e6dc3dce5 100644 --- a/board/ti/am62ax/evm.c +++ b/board/ti/am62ax/evm.c @@ -35,8 +35,6 @@ void spl_perform_fixups(struct spl_image_info *spl_image) { if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) fixup_ddr_driver_for_ecc(spl_image); - else - fixup_memory_node(spl_image); } #endif diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c index 3cbada5405..6e06003f21 100644 --- a/board/ti/am62px/evm.c +++ b/board/ti/am62px/evm.c @@ -55,8 +55,6 @@ void spl_perform_fixups(struct spl_image_info *spl_image) { if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) fixup_ddr_driver_for_ecc(spl_image); - else - fixup_memory_node(spl_image); } static int video_setup(void) diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index e990ba0d43..89b7c7524a 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -105,8 +105,6 @@ void spl_perform_fixups(struct spl_image_info *spl_image) { if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) fixup_ddr_driver_for_ecc(spl_image); - else - fixup_memory_node(spl_image); #if CONFIG_IS_ENABLED(USB_STORAGE) fixup_usb_boot(spl_image->fdt_addr); -- cgit v1.2.3 From 02979f683f6809270142628e5c5055e2e9512208 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Wed, 21 Feb 2024 14:07:04 -0600 Subject: arm: dts: k3-am62x-sip-lp4: update to latest emif output Nothing much has changed between the versions of the emif output. Some changes to the PHY_PAD_CAL_IO_CFG_0, PHY PAD RST DRIVE, and PHY_CAL_CLK_SELECT_0 should add some minor stability improvements. Nonetheless, update to the latest characterization developments. Signed-off-by: Bryan Brattlof --- arch/arm/dts/k3-am62x-sip-ddr-lp4-50-800.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/dts/k3-am62x-sip-ddr-lp4-50-800.dtsi b/arch/arm/dts/k3-am62x-sip-ddr-lp4-50-800.dtsi index 04c9a78fba..61894ee3ae 100644 --- a/arch/arm/dts/k3-am62x-sip-ddr-lp4-50-800.dtsi +++ b/arch/arm/dts/k3-am62x-sip-ddr-lp4-50-800.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.03 - * Mon Nov 21 2022 09:04:01 GMT-0600 (Central Standard Time) + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.10 + * Mon Oct 16 2023 09:44:16 GMT-0500 (Central Daylight Time) * DDR Type: LPDDR4 * F0 = 50MHz F1 = NA F2 = 800MHz * Density (per channel): 4Gb @@ -827,7 +827,7 @@ #define DDRSS_PHY_41_DATA 0x00005555 #define DDRSS_PHY_42_DATA 0x01000100 #define DDRSS_PHY_43_DATA 0x00800180 -#define DDRSS_PHY_44_DATA 0x00000000 // [SWAP] PHY_CALVL_VREF_DRIVING_SLICE_0 //0x00000001 Normal +#define DDRSS_PHY_44_DATA 0x00000000 #define DDRSS_PHY_45_DATA 0x00000000 #define DDRSS_PHY_46_DATA 0x00000000 #define DDRSS_PHY_47_DATA 0x00000000 @@ -886,7 +886,7 @@ #define DDRSS_PHY_100_DATA 0x000001CC #define DDRSS_PHY_101_DATA 0x20100200 #define DDRSS_PHY_102_DATA 0x00000005 -#define DDRSS_PHY_103_DATA 0x56743210 // [SWIZZLE] PHY_DQ_DM_SWIZZLE0_0 //0x76543210 Swizzle DV +#define DDRSS_PHY_103_DATA 0x56743210 #define DDRSS_PHY_104_DATA 0x00000008 #define DDRSS_PHY_105_DATA 0x034C034C #define DDRSS_PHY_106_DATA 0x034C034C @@ -1083,7 +1083,7 @@ #define DDRSS_PHY_297_DATA 0x00005555 #define DDRSS_PHY_298_DATA 0x01000100 #define DDRSS_PHY_299_DATA 0x00800180 -#define DDRSS_PHY_300_DATA 0x00000001 // [SWAP] PHY_CALVL_VREF_DRIVING_SLICE_1 //0x00000000 Normal +#define DDRSS_PHY_300_DATA 0x00000001 #define DDRSS_PHY_301_DATA 0x00000000 #define DDRSS_PHY_302_DATA 0x00000000 #define DDRSS_PHY_303_DATA 0x00000000 @@ -1142,7 +1142,7 @@ #define DDRSS_PHY_356_DATA 0x000001CC #define DDRSS_PHY_357_DATA 0x20100200 #define DDRSS_PHY_358_DATA 0x00000005 -#define DDRSS_PHY_359_DATA 0x01324567 // [SWIZZLE] PHY_DQ_DM_SWIZZLE0_1 //0x76543210 //Normal +#define DDRSS_PHY_359_DATA 0x01324567 #define DDRSS_PHY_360_DATA 0x00000008 #define DDRSS_PHY_361_DATA 0x034C034C #define DDRSS_PHY_362_DATA 0x034C034C @@ -2142,7 +2142,7 @@ #define DDRSS_PHY_1356_DATA 0x00000000 #define DDRSS_PHY_1357_DATA 0x00000000 #define DDRSS_PHY_1358_DATA 0x00000000 -#define DDRSS_PHY_1359_DATA 0x76543201 // [SWAP] PHY_DATA_BYTE_ORDER_SEL //0x76543210 //Normal +#define DDRSS_PHY_1359_DATA 0x76543201 #define DDRSS_PHY_1360_DATA 0x00040198 #define DDRSS_PHY_1361_DATA 0x00000000 #define DDRSS_PHY_1362_DATA 0x00000000 @@ -2154,7 +2154,7 @@ #define DDRSS_PHY_1368_DATA 0x00000002 #define DDRSS_PHY_1369_DATA 0x00000000 #define DDRSS_PHY_1370_DATA 0x00000000 -#define DDRSS_PHY_1371_DATA 0x00000AC3 +#define DDRSS_PHY_1371_DATA 0x0001F7C2 #define DDRSS_PHY_1372_DATA 0x00020002 #define DDRSS_PHY_1373_DATA 0x00000000 #define DDRSS_PHY_1374_DATA 0x00001142 @@ -2182,10 +2182,10 @@ #define DDRSS_PHY_1396_DATA 0x0089FF00 #define DDRSS_PHY_1397_DATA 0x000C3F11 #define DDRSS_PHY_1398_DATA 0x01990000 -#define DDRSS_PHY_1399_DATA 0x000C3F11 +#define DDRSS_PHY_1399_DATA 0x000C3F91 #define DDRSS_PHY_1400_DATA 0x01990000 #define DDRSS_PHY_1401_DATA 0x3F0DFF11 #define DDRSS_PHY_1402_DATA 0x01990000 #define DDRSS_PHY_1403_DATA 0x00018011 #define DDRSS_PHY_1404_DATA 0x0089FF00 -#define DDRSS_PHY_1405_DATA 0x20040002 +#define DDRSS_PHY_1405_DATA 0x20040004 -- cgit v1.2.3 From 55af8c9749e26cae5157e2e52afc61f65065e087 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Wed, 21 Feb 2024 14:07:05 -0600 Subject: board: ti: common: remove debounce config from rtc commit d36ad81d25a99 ("board: ti: common: add rtc setup to common folder") I had mistakenly copied over the gpio debounce configuration into the external 32k rtc crystal setup. Unfortunately this causing issues with the DSP on the AM62Ax SoC family. Because we have no need to configure debounce on our SK boards, let's just rip this out for now. Signed-off-by: Bryan Brattlof --- board/ti/common/rtc.c | 16 ---------------- board/ti/common/rtc.h | 8 -------- 2 files changed, 24 deletions(-) diff --git a/board/ti/common/rtc.c b/board/ti/common/rtc.c index 65c1f75c89..44e0d989a3 100644 --- a/board/ti/common/rtc.c +++ b/board/ti/common/rtc.c @@ -23,20 +23,4 @@ void board_rtc_init(void) /* Make sure to mux up to take the SoC 32k from the crystal */ writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); - - /* Setup debounce conf registers - arbitrary values. - * Times are approx - */ - /* 1.9ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG1, 0x1); - /* 5ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG2, 0x5); - /* 20ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG3, 0x14); - /* 46ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG4, 0x18); - /* 100ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG5, 0x1c); - /* 156ms debounce @ 32k */ - writel(WKUP_CTRLMMR_DBOUNCE_CFG6, 0x1f); } diff --git a/board/ti/common/rtc.h b/board/ti/common/rtc.h index 57737829b6..fce45c4217 100644 --- a/board/ti/common/rtc.h +++ b/board/ti/common/rtc.h @@ -8,14 +8,6 @@ #ifndef __RTC_H #define __RTC_H -/* Debounce configuration register*/ -#define WKUP_CTRLMMR_DBOUNCE_CFG1 0x04504084 -#define WKUP_CTRLMMR_DBOUNCE_CFG2 0x04504088 -#define WKUP_CTRLMMR_DBOUNCE_CFG3 0x0450408c -#define WKUP_CTRLMMR_DBOUNCE_CFG4 0x04504090 -#define WKUP_CTRLMMR_DBOUNCE_CFG5 0x04504094 -#define WKUP_CTRLMMR_DBOUNCE_CFG6 0x04504098 - /** * board_rtc_init() - Enable the external 32k crystal and configure debounce * registers. -- cgit v1.2.3 From 70bd8c81928f9284062a7c6b6c663b6802f7e471 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Thu, 15 Feb 2024 15:26:15 -0600 Subject: arm: dts: k3-am62a-main: Add sdhci2 instance Add sdhci2 DT node in k3-am62a-main for mmc2. Add otap/itap values according to the datasheet[0], Refer to Table 7-97. [0] https://www.ti.com/lit/ds/symlink/am62a3.pdf Signed-off-by: Judith Mendez --- arch/arm/dts/k3-am62a-main.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi index 41aec3a82e..8ab4aa4520 100644 --- a/arch/arm/dts/k3-am62a-main.dtsi +++ b/arch/arm/dts/k3-am62a-main.dtsi @@ -384,6 +384,30 @@ status = "disabled"; }; + sdhci2: mmc@fa20000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>; + interrupts = ; + power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; + clock-names = "clk_ahb", "clk_xin"; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + no-1-8-v; + status = "disabled"; + }; + usbss0: dwc3-usb@f900000 { compatible = "ti,am62-usb"; reg = <0x00 0x0f900000 0x00 0x800>; -- cgit v1.2.3 From 3c0e3007ffd476358d2d94a1c69d6d72ffeb6264 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Thu, 15 Feb 2024 15:26:16 -0600 Subject: arm: dts: k3-am64-main: Fix ITAP/OTAP values for MMC Update MMC0/MMC1 OTAP/ITAP values according to the datasheet [0], refer to Table 7-68 for MMC0 and Table 7-77 for MMC1. Move ITAPDLY values after OTAPDLY values to make MMC nodes more uniform across devices. [0] https://www.ti.com/lit/ds/symlink/am6442.pdf Signed-off-by: Judith Mendez --- arch/arm/dts/k3-am64-main.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi index 17be4bf3e2..0d1801330d 100644 --- a/arch/arm/dts/k3-am64-main.dtsi +++ b/arch/arm/dts/k3-am64-main.dtsi @@ -473,13 +473,13 @@ mmc-ddr-1_8v; mmc-hs200-1_8v; ti,trm-icp = <0x2>; - ti,itap-del-sel-legacy = <0x10>; - ti,itap-del-sel-mmc-hs = <0xA>; - ti,itap-del-sel-ddr52 = <0x3>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x6>; ti,otap-del-sel-hs200 = <0x7>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xA>; + ti,itap-del-sel-ddr52 = <0x3>; }; sdhci1: mmc@fa00000 { @@ -490,17 +490,17 @@ clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; clock-names = "clk_ahb", "clk_xin"; ti,trm-icp = <0x2>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-sdr104 = <0x6>; ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; ti,clkbuf-sel = <0x7>; }; -- cgit v1.2.3 From e3c6ca4edd240d68cdb497a357e23b8907cd88c4 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Thu, 15 Feb 2024 15:26:17 -0600 Subject: arm: dts: k3-am62a-main: Fix ITAP/OTAP values for MMC Update MMC0/MMC1 OTAP/ITAP delay values according to the datasheet [0], refer to Table 7-79 for MMC0 and Table 7-97 for MMC1. [0] https://www.ti.com/lit/ds/symlink/am62a7.pdf Signed-off-by: Judith Mendez --- arch/arm/dts/k3-am62a-main.dtsi | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi index 8ab4aa4520..eb354b173b 100644 --- a/arch/arm/dts/k3-am62a-main.dtsi +++ b/arch/arm/dts/k3-am62a-main.dtsi @@ -354,7 +354,6 @@ ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x9>; ti,otap-del-sel-hs200 = <0x6>; }; @@ -373,11 +372,10 @@ ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-sdr104 = <0x6>; ti,otap-del-sel-ddr50 = <0x9>; - ti,itap-del-sel-legacy = <0xA>; - ti,itap-del-sel-sd-hs = <0x1>; - ti,itap-del-sel-sdr12 = <0xA>; - ti,itap-del-sel-sdr25 = <0x1>; - ti,itap-del-sel-ddr50 = <0x0>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; ti,clkbuf-sel = <0x7>; bus-width = <4>; no-1-8-v; -- cgit v1.2.3 From 80ed6ea5ad3d7ace8f3ebbc457d7ff77e895397e Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Thu, 15 Feb 2024 15:26:18 -0600 Subject: arm: dts: k3-am62p-main: Fix ITAP/OTAP values for MMC Update MMC OTAP/ITAP values according to the datasheet [0], refer to Table 7-79 for MMC0 and Table 7-97 for MMC1/MMC2. [0] https://www.ti.com/lit/ds/symlink/am62p.pdf Signed-off-by: Judith Mendez --- arch/arm/dts/k3-am62p-main.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/k3-am62p-main.dtsi b/arch/arm/dts/k3-am62p-main.dtsi index 90427985ee..cff4c4e28e 100644 --- a/arch/arm/dts/k3-am62p-main.dtsi +++ b/arch/arm/dts/k3-am62p-main.dtsi @@ -588,8 +588,8 @@ ti,otap-del-sel-legacy = <0x1>; ti,otap-del-sel-mmc-hs = <0x1>; ti,otap-del-sel-ddr52 = <0x6>; - ti,otap-del-sel-hs200 = <0x6>; - ti,otap-del-sel-hs400 = <0x6>; + ti,otap-del-sel-hs200 = <0x8>; + ti,otap-del-sel-hs400 = <0x5>; ti,itap-del-sel-legacy = <0x10>; ti,itap-del-sel-mmc-hs = <0xa>; ti,itap-del-sel-ddr52 = <0x3>; @@ -608,12 +608,14 @@ ti,trm-icp = <0x8>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0x9>; ti,otap-del-sel-sdr104 = <0x6>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; @@ -630,12 +632,14 @@ ti,trm-icp = <0x8>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0x9>; ti,otap-del-sel-sdr104 = <0x6>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; -- cgit v1.2.3 From 3db09a8436bf4b2b6cb98926f945dabd7e2cb676 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Thu, 15 Feb 2024 15:26:19 -0600 Subject: arm: dts: k3-am6*: Remove DLL properties for soft PHYs Remove DLL properties which are not applicable for soft PHYs since these PHYs do not have a DLL to enable. Signed-off-by: Judith Mendez --- arch/arm/dts/k3-am62-main.dtsi | 3 --- arch/arm/dts/k3-am625-beagleplay.dts | 3 --- arch/arm/dts/k3-am625-sk.dts | 2 -- arch/arm/dts/k3-am62a-main.dtsi | 2 -- arch/arm/dts/k3-am62a7-sk.dts | 2 -- arch/arm/dts/k3-am62p-main.dtsi | 2 -- arch/arm/dts/k3-am62p5-sk.dts | 1 - arch/arm/dts/k3-am62x-sk-common.dtsi | 2 -- arch/arm/dts/k3-am64-main.dtsi | 1 - arch/arm/dts/k3-am642-evm.dts | 1 - arch/arm/dts/k3-am642-r5-evm.dts | 1 - arch/arm/dts/k3-am642-r5-sk.dts | 1 - arch/arm/dts/k3-am642-sk.dts | 1 - 13 files changed, 22 deletions(-) diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi index bdfda77586..1da42deb4f 100644 --- a/arch/arm/dts/k3-am62-main.dtsi +++ b/arch/arm/dts/k3-am62-main.dtsi @@ -503,7 +503,6 @@ assigned-clock-parents = <&k3_clks 57 8>; mmc-ddr-1_8v; mmc-hs200-1_8v; - ti,trm-icp = <0x2>; bus-width = <8>; ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; @@ -522,7 +521,6 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0x0>; @@ -546,7 +544,6 @@ power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0x0>; diff --git a/arch/arm/dts/k3-am625-beagleplay.dts b/arch/arm/dts/k3-am625-beagleplay.dts index 0bc609fd00..e3a3505884 100644 --- a/arch/arm/dts/k3-am625-beagleplay.dts +++ b/arch/arm/dts/k3-am625-beagleplay.dts @@ -670,7 +670,6 @@ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&emmc_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; status = "okay"; }; @@ -682,7 +681,6 @@ vmmc-supply = <&vdd_3v3_sd>; vqmmc-supply = <&vdd_sd_dv>; - ti,driver-strength-ohm = <50>; disable-wp; cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; cd-debounce-delay-ms = <100>; @@ -699,7 +697,6 @@ ti,fails-without-test-cd; cap-power-off-card; keep-power-in-suspend; - ti,driver-strength-ohm = <50>; assigned-clocks = <&k3_clks 157 158>; assigned-clock-parents = <&k3_clks 157 160>; #address-cells = <1>; diff --git a/arch/arm/dts/k3-am625-sk.dts b/arch/arm/dts/k3-am625-sk.dts index 859f038c37..823e4320c3 100644 --- a/arch/arm/dts/k3-am625-sk.dts +++ b/arch/arm/dts/k3-am625-sk.dts @@ -442,7 +442,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -453,7 +452,6 @@ vqmmc-supply = <&vdd_sd_dv>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi index eb354b173b..88607a1f49 100644 --- a/arch/arm/dts/k3-am62a-main.dtsi +++ b/arch/arm/dts/k3-am62a-main.dtsi @@ -349,7 +349,6 @@ assigned-clock-parents = <&k3_clks 57 8>; mmc-ddr-1_8v; mmc-hs200-1_8v; - ti,trm-icp = <0x2>; bus-width = <8>; ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; @@ -364,7 +363,6 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts index f727b5f825..8b5c25431d 100644 --- a/arch/arm/dts/k3-am62a7-sk.dts +++ b/arch/arm/dts/k3-am62a7-sk.dts @@ -370,7 +370,6 @@ vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -378,7 +377,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; diff --git a/arch/arm/dts/k3-am62p-main.dtsi b/arch/arm/dts/k3-am62p-main.dtsi index cff4c4e28e..3d707981b7 100644 --- a/arch/arm/dts/k3-am62p-main.dtsi +++ b/arch/arm/dts/k3-am62p-main.dtsi @@ -605,7 +605,6 @@ clock-names = "clk_ahb", "clk_xin"; bus-width = <4>; ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; @@ -629,7 +628,6 @@ clock-names = "clk_ahb", "clk_xin"; bus-width = <4>; ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; diff --git a/arch/arm/dts/k3-am62p5-sk.dts b/arch/arm/dts/k3-am62p5-sk.dts index 1843ea59d3..e18c33fead 100644 --- a/arch/arm/dts/k3-am62p5-sk.dts +++ b/arch/arm/dts/k3-am62p5-sk.dts @@ -587,7 +587,6 @@ vqmmc-supply = <&vddshv_sdio>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; bootph-all; }; diff --git a/arch/arm/dts/k3-am62x-sk-common.dtsi b/arch/arm/dts/k3-am62x-sk-common.dtsi index 49f3c280e0..209114c8d2 100644 --- a/arch/arm/dts/k3-am62x-sk-common.dtsi +++ b/arch/arm/dts/k3-am62x-sk-common.dtsi @@ -267,7 +267,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -276,7 +275,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi index 0d1801330d..0b556abaeb 100644 --- a/arch/arm/dts/k3-am64-main.dtsi +++ b/arch/arm/dts/k3-am64-main.dtsi @@ -489,7 +489,6 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; diff --git a/arch/arm/dts/k3-am642-evm.dts b/arch/arm/dts/k3-am642-evm.dts index a1f57670a6..9e7a30ab77 100644 --- a/arch/arm/dts/k3-am642-evm.dts +++ b/arch/arm/dts/k3-am642-evm.dts @@ -517,7 +517,6 @@ pinctrl-names = "default"; bus-width = <4>; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts index 534c6b9dc8..2e3eb7684c 100644 --- a/arch/arm/dts/k3-am642-r5-evm.dts +++ b/arch/arm/dts/k3-am642-r5-evm.dts @@ -278,7 +278,6 @@ /delete-property/ power-domains; clocks = <&clk_200mhz>; clock-names = "clk_xin"; - ti,driver-strength-ohm = <50>; disable-wp; pinctrl-0 = <&main_mmc1_pins_default>; }; diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts index 6701e754bb..7959a85f64 100644 --- a/arch/arm/dts/k3-am642-r5-sk.dts +++ b/arch/arm/dts/k3-am642-r5-sk.dts @@ -224,7 +224,6 @@ /delete-property/ power-domains; clocks = <&clk_200mhz>; clock-names = "clk_xin"; - ti,driver-strength-ohm = <50>; disable-wp; pinctrl-0 = <&main_mmc1_pins_default>; }; diff --git a/arch/arm/dts/k3-am642-sk.dts b/arch/arm/dts/k3-am642-sk.dts index cbb10a4964..989bde64ac 100644 --- a/arch/arm/dts/k3-am642-sk.dts +++ b/arch/arm/dts/k3-am642-sk.dts @@ -406,7 +406,6 @@ pinctrl-names = "default"; bus-width = <4>; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; -- cgit v1.2.3 From 797e3de694d6dcf853a92e7449f80580ec13fa20 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Thu, 15 Feb 2024 15:26:20 -0600 Subject: arm: dts: k3-am6*: Fix ti,clkbuf-sel property in MMC nodes Move ti,clkbuf-sel property above the OTAP/ITAP delay values. While there is no error with where it is currently at, it is easier to read the MMC node if ti,clkbuf-sel is located above the OTAP/ITAP delay values consistently across MMC nodes. Add missing ti,clkbuf-sel DTS property for sdhci0 in k3-am64-main. Signed-off-by: Judith Mendez --- arch/arm/dts/k3-am62-main.dtsi | 4 ++-- arch/arm/dts/k3-am62a-main.dtsi | 2 +- arch/arm/dts/k3-am64-main.dtsi | 3 ++- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi index 1da42deb4f..2f1caa06e3 100644 --- a/arch/arm/dts/k3-am62-main.dtsi +++ b/arch/arm/dts/k3-am62-main.dtsi @@ -521,6 +521,7 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0x0>; @@ -532,7 +533,6 @@ ti,itap-del-sel-sd-hs = <0x1>; ti,itap-del-sel-sdr12 = <0xA>; ti,itap-del-sel-sdr25 = <0x1>; - ti,clkbuf-sel = <0x7>; bus-width = <4>; status = "disabled"; }; @@ -544,6 +544,7 @@ power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0x0>; @@ -555,7 +556,6 @@ ti,itap-del-sel-sd-hs = <0x1>; ti,itap-del-sel-sdr12 = <0xA>; ti,itap-del-sel-sdr25 = <0x1>; - ti,clkbuf-sel = <0x7>; status = "disabled"; }; diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi index 88607a1f49..6c5dca659a 100644 --- a/arch/arm/dts/k3-am62a-main.dtsi +++ b/arch/arm/dts/k3-am62a-main.dtsi @@ -363,6 +363,7 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; @@ -374,7 +375,6 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; - ti,clkbuf-sel = <0x7>; bus-width = <4>; no-1-8-v; status = "disabled"; diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi index 0b556abaeb..dc009245d1 100644 --- a/arch/arm/dts/k3-am64-main.dtsi +++ b/arch/arm/dts/k3-am64-main.dtsi @@ -472,6 +472,7 @@ clock-names = "clk_ahb", "clk_xin"; mmc-ddr-1_8v; mmc-hs200-1_8v; + ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x2>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; @@ -489,6 +490,7 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; clock-names = "clk_ahb", "clk_xin"; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; @@ -500,7 +502,6 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; - ti,clkbuf-sel = <0x7>; }; cpsw3g: ethernet@8000000 { -- cgit v1.2.3 From e0f9f14cb88a3977b232a839e2781c76f3839375 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Thu, 15 Feb 2024 15:26:21 -0600 Subject: arm: dts: k3-am6*: Fix bus-width property in MMC nodes Move bus-width property to *main.dtsi, above the OTAP/ITAP delay values. While there is no error with where it is currently at, it is easier to read the MMC node if the bus-width property is located above the OTAP/ITAP delay values consistently across MMC nodes. Add missing bus-width DTS property for sdchi2 in k3-am62-main. Signed-off-by: Judith Mendez --- arch/arm/dts/k3-am62-main.dtsi | 5 +++-- arch/arm/dts/k3-am625-beagleplay.dts | 1 - arch/arm/dts/k3-am62a-main.dtsi | 4 ++-- arch/arm/dts/k3-am64-main.dtsi | 2 ++ arch/arm/dts/k3-am642-evm.dts | 2 -- arch/arm/dts/k3-am642-sk.dts | 1 - 6 files changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi index 2f1caa06e3..db6574740c 100644 --- a/arch/arm/dts/k3-am62-main.dtsi +++ b/arch/arm/dts/k3-am62-main.dtsi @@ -501,9 +501,9 @@ clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 57 6>; assigned-clock-parents = <&k3_clks 57 8>; + bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; - bus-width = <8>; ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; @@ -521,6 +521,7 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; + bus-width = <4>; ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; @@ -533,7 +534,6 @@ ti,itap-del-sel-sd-hs = <0x1>; ti,itap-del-sel-sdr12 = <0xA>; ti,itap-del-sel-sdr25 = <0x1>; - bus-width = <4>; status = "disabled"; }; @@ -544,6 +544,7 @@ power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; + bus-width = <4>; ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; diff --git a/arch/arm/dts/k3-am625-beagleplay.dts b/arch/arm/dts/k3-am625-beagleplay.dts index e3a3505884..58f88ebaf6 100644 --- a/arch/arm/dts/k3-am625-beagleplay.dts +++ b/arch/arm/dts/k3-am625-beagleplay.dts @@ -692,7 +692,6 @@ vmmc-supply = <&wlan_en>; pinctrl-names = "default"; pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>; - bus-width = <4>; non-removable; ti,fails-without-test-cd; cap-power-off-card; diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi index 6c5dca659a..52df26f776 100644 --- a/arch/arm/dts/k3-am62a-main.dtsi +++ b/arch/arm/dts/k3-am62a-main.dtsi @@ -347,9 +347,9 @@ clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 57 6>; assigned-clock-parents = <&k3_clks 57 8>; + bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; - bus-width = <8>; ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; @@ -363,6 +363,7 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; + bus-width = <4>; ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; @@ -375,7 +376,6 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; - bus-width = <4>; no-1-8-v; status = "disabled"; }; diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi index dc009245d1..f7bc7cd31a 100644 --- a/arch/arm/dts/k3-am64-main.dtsi +++ b/arch/arm/dts/k3-am64-main.dtsi @@ -470,6 +470,7 @@ power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; clock-names = "clk_ahb", "clk_xin"; + bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; ti,clkbuf-sel = <0x7>; @@ -490,6 +491,7 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; clock-names = "clk_ahb", "clk_xin"; + bus-width = <4>; ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; diff --git a/arch/arm/dts/k3-am642-evm.dts b/arch/arm/dts/k3-am642-evm.dts index 9e7a30ab77..a71684dec7 100644 --- a/arch/arm/dts/k3-am642-evm.dts +++ b/arch/arm/dts/k3-am642-evm.dts @@ -505,7 +505,6 @@ &sdhci0 { /* emmc */ - bus-width = <8>; non-removable; ti,driver-strength-ohm = <50>; disable-wp; @@ -515,7 +514,6 @@ /* SD/MMC */ vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; - bus-width = <4>; pinctrl-0 = <&main_mmc1_pins_default>; disable-wp; }; diff --git a/arch/arm/dts/k3-am642-sk.dts b/arch/arm/dts/k3-am642-sk.dts index 989bde64ac..2e75dadf9d 100644 --- a/arch/arm/dts/k3-am642-sk.dts +++ b/arch/arm/dts/k3-am642-sk.dts @@ -404,7 +404,6 @@ /* SD/MMC */ vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; - bus-width = <4>; pinctrl-0 = <&main_mmc1_pins_default>; disable-wp; }; -- cgit v1.2.3 From 4d4730eec616b24e9802ab217c466b18295d151b Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Fri, 16 Feb 2024 17:14:06 +0530 Subject: arm: dts: k3-*-binman: Make default DM file optional The default DM firmware path is non-optional as of now. Make it optional so that users that choose to provide DM via TI_DM argument instead of BINMAN_INDIRS can do so without build errors. Cc: Chirag Shilwant Signed-off-by: Neha Malcom Francis Tested-by: Chirag Shilwant --- arch/arm/dts/k3-am625-sk-binman.dtsi | 1 + arch/arm/dts/k3-am62a-sk-binman.dtsi | 1 + arch/arm/dts/k3-am62p-sk-binman.dtsi | 1 + arch/arm/dts/k3-j7200-binman.dtsi | 1 + arch/arm/dts/k3-j721e-binman.dtsi | 1 + arch/arm/dts/k3-j721s2-binman.dtsi | 1 + arch/arm/dts/k3-j722s-binman.dtsi | 1 + arch/arm/dts/k3-j784s4-binman.dtsi | 1 + 8 files changed, 8 insertions(+) diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index 9bb9662f25..3eab152266 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -152,6 +152,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index 777630f2b8..dde27698fa 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -155,6 +155,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi index 6bc5ef7582..4d968cd928 100644 --- a/arch/arm/dts/k3-am62p-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -113,6 +113,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index 1e1b3d8a36..7149275d9d 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -194,6 +194,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi index b6f6ad4068..c545f4dd59 100644 --- a/arch/arm/dts/k3-j721e-binman.dtsi +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -310,6 +310,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi index 890504ca7f..34d1d1edca 100644 --- a/arch/arm/dts/k3-j721s2-binman.dtsi +++ b/arch/arm/dts/k3-j721s2-binman.dtsi @@ -157,6 +157,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { diff --git a/arch/arm/dts/k3-j722s-binman.dtsi b/arch/arm/dts/k3-j722s-binman.dtsi index d5ccfdd939..53474764c6 100644 --- a/arch/arm/dts/k3-j722s-binman.dtsi +++ b/arch/arm/dts/k3-j722s-binman.dtsi @@ -112,6 +112,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi index 0926bc631f..35ffeec60b 100644 --- a/arch/arm/dts/k3-j784s4-binman.dtsi +++ b/arch/arm/dts/k3-j784s4-binman.dtsi @@ -160,6 +160,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { -- cgit v1.2.3 From d1857c85e2ddf1c4d05c7e873a02fdf2f6e166a3 Mon Sep 17 00:00:00 2001 From: Guillaume La Roque Date: Thu, 22 Feb 2024 15:19:57 +0100 Subject: environment: ti: mmc_android: update metadata partition To fix vts_fs_test and be compliance with google requirements we need to move on f2fs partition type. fastboot format metadata fail with actual size so update it to 64MB. Signed-off-by: Guillaume La Roque --- include/environment/ti/mmc_android.env | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/environment/ti/mmc_android.env b/include/environment/ti/mmc_android.env index 7981d54396..2201846150 100644 --- a/include/environment/ti/mmc_android.env +++ b/include/environment/ti/mmc_android.env @@ -15,11 +15,11 @@ partitions+=name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b}; partitions+=name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta_a}; partitions+=name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta_b}; partitions+=name=super,size=4608M,uuid=${uuid_gpt_super}; -partitions+=name=metadata,size=16M,uuid=${uuid_gpt_metadata}; +partitions+=name=metadata,size=64M,uuid=${uuid_gpt_metadata}; partitions+=name=persist,size=32M,uuid=${uuid_gpt_persist}; partitions+=name=userdata,size=-,uuid=${uuid_gpt_userdata} -fastboot.partition-type:metadata=ext4 +fastboot.partition-type:metadata=f2fs mmcdev=0 force_avb=0 envboot=run distro_bootcmd -- cgit v1.2.3 From bc8e096e814ad044be30a6b517d07def55328e76 Mon Sep 17 00:00:00 2001 From: Guillaume La Roque Date: Thu, 22 Feb 2024 15:19:58 +0100 Subject: environment: ti: mmc_android: add frp partition Add new partition to support factory reset protection with android 14. It's needed to be able to do factory reset. Signed-off-by: Guillaume La Roque --- include/environment/ti/mmc_android.env | 1 + 1 file changed, 1 insertion(+) diff --git a/include/environment/ti/mmc_android.env b/include/environment/ti/mmc_android.env index 2201846150..6a29c39eee 100644 --- a/include/environment/ti/mmc_android.env +++ b/include/environment/ti/mmc_android.env @@ -4,6 +4,7 @@ partitions= name=bootloader,start=5M,size=8M,uuid=${uuid_gpt_bootloader}; partitions+=name=tiboot3,start=4M,size=1M,uuid=${uuid_gpt_tiboot3}; partitions+=name=misc,start=13824K,size=512K,uuid=${uuid_gpt_misc}; +partitions+=name=frp,size=512K,uuid=${uuid_gpt_frp}; partitions+=name=boot_a,size=40M,uuid=${uuid_gpt_boot_a}; partitions+=name=boot_b,size=40M,uuid=${uuid_gpt_boot_b}; partitions+=name=vendor_boot_a,size=32M,uuid=${uuid_gpt_vendor_boot_a}; -- cgit v1.2.3 From ed30ae315c83e1ed2db76b2f740859e5289737a1 Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Fri, 23 Feb 2024 13:54:58 +0530 Subject: board: ti: am62p: Fix compilation warning for implicit declaration Fixes below warning by including cpu_funcs.h: "board/ti/am62px/evm.c: In function `spl_board_init`: board/ti/am62px/evm.c:83:9: warning: implicit declaration of function `enable_caches` [-Wimplicit-function-declaration] 83 | enable_caches();" | ^~~~~~~~~~~~~ While at it, also sort the include headers by placing video.h at the end. Fixes: a7e8f56abf9 ("board: ti: am62p: Add splash screen support") Reviewed-by: Kamlesh Gurudasani Signed-off-by: Devarsh Thakkar --- board/ti/am62px/evm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c index 6e06003f21..5ab56260a4 100644 --- a/board/ti/am62px/evm.c +++ b/board/ti/am62px/evm.c @@ -9,13 +9,13 @@ #include #include #include +#include #include #include #include #include -#include #include - +#include #include "../common/rtc.h" #include "../common/k3-ddr-init.h" -- cgit v1.2.3 From eaac957014d13a5b3d040b06a1c66933d1adb65a Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Fri, 23 Feb 2024 13:54:59 +0530 Subject: configs: am62px: r5: Bump up malloc length to 3MiB Bump up malloc length to 3MiB for R5 SPL, as the size of tispl.bin is increased now after introduction of splash and caching support and with display-cluster enabled DM firmware, R5 SPL fails to load tispl.bin with below issue : "U-Boot SPL 2023.04-g7d05009917 (Feb 15 2024 - 18:08:11 +0000) SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.1--v09.02.01 (Kool Koala)') SPL initial stack usage: 17072 bytes Trying to boot from MMC2 alloc space exhausted SPL: failed to boot from all boot devices" Fixes: a7e8f56abf9 ("board: ti: am62p: Add splash screen support") Reviewed-by: Kamlesh Gurudasani Signed-off-by: Devarsh Thakkar --- configs/am62px_evm_r5_defconfig | 2 +- configs/am62px_evm_r5_usbdfu_defconfig | 2 +- configs/am62px_evm_r5_usbmsc_defconfig | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig index e31f06402f..d38548f3d7 100644 --- a/configs/am62px_evm_r5_defconfig +++ b/configs/am62px_evm_r5_defconfig @@ -40,7 +40,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_SPL_MALLOC=y CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y diff --git a/configs/am62px_evm_r5_usbdfu_defconfig b/configs/am62px_evm_r5_usbdfu_defconfig index bd56b77c12..f44ea782de 100644 --- a/configs/am62px_evm_r5_usbdfu_defconfig +++ b/configs/am62px_evm_r5_usbdfu_defconfig @@ -37,7 +37,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_SPL_MALLOC=y CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y diff --git a/configs/am62px_evm_r5_usbmsc_defconfig b/configs/am62px_evm_r5_usbmsc_defconfig index a5da903c3c..05771b9a9c 100644 --- a/configs/am62px_evm_r5_usbmsc_defconfig +++ b/configs/am62px_evm_r5_usbmsc_defconfig @@ -37,7 +37,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_SPL_MALLOC=y CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -- cgit v1.2.3 From 2cecfd8dbc3ded38d1a1f50ef5938b534f7112d0 Mon Sep 17 00:00:00 2001 From: Mattijs Korpershoek Date: Tue, 27 Feb 2024 17:02:30 +0100 Subject: board: ti: am62x: beagleplay: android: Fix metadata partition size commit d1857c85e2d ("environment: ti: mmc_android: update metadata partition") switched the metadata partition to use f2fs file system. This requires a size increase of the partition to avoid the following flash error: Flashing metadata partition Warning: skip copying metadata image avb footer (metadata partition size: 16777216, metadata image size: 63963136). Sending 'metadata' (62464 KB) OKAY [ 2.477s] Writing 'metadata' FAILED (remote: 'too large for partition') fastboot: error: Command failed Increase the metadata partition size for Beagle Play as well. Fixes: d1857c85e2d ("environment: ti: mmc_android: update metadata partition") Signed-off-by: Mattijs Korpershoek --- board/ti/am62x/am625_beagleplay_android.env | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/ti/am62x/am625_beagleplay_android.env b/board/ti/am62x/am625_beagleplay_android.env index ae3f95187b..9e0cfde52a 100644 --- a/board/ti/am62x/am625_beagleplay_android.env +++ b/board/ti/am62x/am625_beagleplay_android.env @@ -16,7 +16,7 @@ partitions+=name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b}; partitions+=name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta_a}; partitions+=name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta_b}; partitions+=name=super,size=4608M,uuid=${uuid_gpt_super}; -partitions+=name=metadata,size=16M,uuid=${uuid_gpt_metadata}; +partitions+=name=metadata,size=64M,uuid=${uuid_gpt_metadata}; partitions+=name=persist,size=32M,uuid=${uuid_gpt_persist}; partitions+=name=userdata,size=-,uuid=${uuid_gpt_userdata} -- cgit v1.2.3 From 4344396aa304879b65df86167d80bd9b4c40ba08 Mon Sep 17 00:00:00 2001 From: Mattijs Korpershoek Date: Tue, 27 Feb 2024 17:02:31 +0100 Subject: board: ti: am62x: beagleplay: android: Add frp partition Factory Reset Protection (frp) is a required Android partition in order to support factory reset via the SystemUI. It's been added to am62x SK EVM partition list in commit bc8e096e814 ("environment: ti: mmc_android: add frp partition") Add it to the Beagle Play partitioning table as well. Signed-off-by: Mattijs Korpershoek --- board/ti/am62x/am625_beagleplay_android.env | 1 + 1 file changed, 1 insertion(+) diff --git a/board/ti/am62x/am625_beagleplay_android.env b/board/ti/am62x/am625_beagleplay_android.env index 9e0cfde52a..b3f75b0ae7 100644 --- a/board/ti/am62x/am625_beagleplay_android.env +++ b/board/ti/am62x/am625_beagleplay_android.env @@ -5,6 +5,7 @@ partitions= name=bootloader,start=5M,size=8M,uuid=${uuid_gpt_bootloader}; partitions+=name=misc,start=13824K,size=512K,uuid=${uuid_gpt_misc}; +partitions+=name=frp,size=512K,uuid=${uuid_gpt_frp}; partitions+=name=boot_a,size=40M,uuid=${uuid_gpt_boot_a}; partitions+=name=boot_b,size=40M,uuid=${uuid_gpt_boot_b}; partitions+=name=vendor_boot_a,size=32M,uuid=${uuid_gpt_vendor_boot_a}; -- cgit v1.2.3 From 0822c70e575b19506287c1e62b3bf5d2794cd40e Mon Sep 17 00:00:00 2001 From: Guillaume La Roque Date: Tue, 27 Feb 2024 17:02:32 +0100 Subject: environment: ti: mmc_android: add vbmeta_vendor_dlkm partition Add new partition to support avb on vendor_dlkm partition. Add for both Beagle Play and AM62X SK EVM. Signed-off-by: Guillaume La Roque [mkorpershoek: added beagle play bits] Signed-off-by: Mattijs Korpershoek --- board/ti/am62x/am625_beagleplay_android.env | 2 ++ include/environment/ti/mmc_android.env | 2 ++ 2 files changed, 4 insertions(+) diff --git a/board/ti/am62x/am625_beagleplay_android.env b/board/ti/am62x/am625_beagleplay_android.env index b3f75b0ae7..a598046d86 100644 --- a/board/ti/am62x/am625_beagleplay_android.env +++ b/board/ti/am62x/am625_beagleplay_android.env @@ -16,6 +16,8 @@ partitions+=name=dtbo_a,size=8M,uuid=${uuid_gpt_dtbo_a}; partitions+=name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b}; partitions+=name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta_a}; partitions+=name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta_b}; +partitions+=name=vbmeta_vendor_dlkm_a,size=64K,uuid=${uuid_gpt_vbmeta_vendor_dlkm_a}; +partitions+=name=vbmeta_vendor_dlkm_b,size=64K,uuid=${uuid_gpt_vbmeta_vendor_dlkm_b}; partitions+=name=super,size=4608M,uuid=${uuid_gpt_super}; partitions+=name=metadata,size=64M,uuid=${uuid_gpt_metadata}; partitions+=name=persist,size=32M,uuid=${uuid_gpt_persist}; diff --git a/include/environment/ti/mmc_android.env b/include/environment/ti/mmc_android.env index 6a29c39eee..9fbc2516a6 100644 --- a/include/environment/ti/mmc_android.env +++ b/include/environment/ti/mmc_android.env @@ -15,6 +15,8 @@ partitions+=name=dtbo_a,size=8M,uuid=${uuid_gpt_dtbo_a}; partitions+=name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b}; partitions+=name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta_a}; partitions+=name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta_b}; +partitions+=name=vbmeta_vendor_dlkm_a,size=64K,uuid=${uuid_gpt_vbmeta_vendor_dlkm_a}; +partitions+=name=vbmeta_vendor_dlkm_b,size=64K,uuid=${uuid_gpt_vbmeta_vendor_dlkm_b}; partitions+=name=super,size=4608M,uuid=${uuid_gpt_super}; partitions+=name=metadata,size=64M,uuid=${uuid_gpt_metadata}; partitions+=name=persist,size=32M,uuid=${uuid_gpt_persist}; -- cgit v1.2.3 From 3610dbfc37e32d0d6fe38440d74f4ebbc9fcdc69 Mon Sep 17 00:00:00 2001 From: Santhosh Kumar K Date: Tue, 27 Feb 2024 11:50:52 +0530 Subject: ram: k3-ddrss: Set SDRAM_IDX using device private data, ddr_ram_size The SDRAM_IDX in DDRSS_V2A_CTL_REG describes the number of address bits minus 16 that are used to determine the mask used to detect memory rollover and prevent aliasing and false coherency issues. Set SDRAM_IDX using the device private data, ddr_ram_size for AM64x, AM62x and AM62x SIP. Signed-off-by: Santhosh Kumar K Acked-by: Bryan Brattlof --- drivers/ram/k3-ddrss/k3-ddrss.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 87741d3943..322e8e86de 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -781,9 +781,13 @@ static int k3_ddrss_probe(struct udevice *dev) if (ret) return ret; - if (IS_ENABLED(CONFIG_SOC_K3_AM642)) { + k3_ddrss_ddr_bank_base_size_calc(ddrss); + + if (IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM642)) { + /* AM62x SIP supports only up to 512 MB SDRAM */ /* AM64x supports only up to 2 GB SDRAM */ - writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG); + writel((((ilog2(ddrss->ddr_ram_size) - 16) << 5) | 0xF), + ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG); writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG); } @@ -799,8 +803,6 @@ static int k3_ddrss_probe(struct udevice *dev) k3_lpddr4_start(ddrss); - k3_ddrss_ddr_bank_base_size_calc(ddrss); - if (ddrss->ti_ecc_enabled) { if (!ddrss->ddrss_ss_cfg) { printf("%s: ss_cfg is required if ecc is enabled but not provided.", -- cgit v1.2.3 From b66b203247a28e067fd3e0f2c291dc73ad258457 Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Tue, 5 Mar 2024 18:14:06 +0530 Subject: video: Fill video handoff in video post probe Fill video handoff fields in video_post_probe as at this point we have full framebuffer-related information. Also fill all the fields available in video hand-off struct as those were missing earlier and U-boot framework expects them to be filled for some of the functionalities. While filling framebuffer size in video hand-off structure use the actual framebuffer region size as derived from gd->video_top and gd->video_bottom instead of directly using the size populated in video_uc_plat as it contains unaligned size. Reported-by: Simon Glass Reviewed-by: Simon Glass Signed-off-by: Devarsh Thakkar --- drivers/video/video-uclass.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 4576eb73d5..fdfab2baa8 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -125,16 +125,6 @@ int video_reserve(ulong *addrp) debug("Video frame buffers from %lx to %lx\n", gd->video_bottom, gd->video_top); - if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(BLOBLIST)) { - struct video_handoff *ho; - - ho = bloblist_add(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho), 0); - if (!ho) - return log_msg_ret("blf", -ENOENT); - ho->fb = *addrp; - ho->size = size; - } - return 0; } @@ -472,6 +462,26 @@ static int video_post_probe(struct udevice *dev) priv->fb_size = priv->line_length * priv->ysize; + /* + * Set up video handoff fields for passing video blob to next stage + * NOTE: + * This assumes that reserved video memory only uses a single framebuffer + */ + if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(BLOBLIST)) { + struct video_handoff *ho; + + ho = bloblist_add(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho), 0); + if (!ho) + return log_msg_ret("blf", -ENOENT); + ho->fb = gd->video_bottom; + /* Fill aligned size here as calculated in video_reserve() */ + ho->size = gd->video_top - gd->video_bottom; + ho->xsize = priv->xsize; + ho->ysize = priv->ysize; + ho->line_length = priv->line_length; + ho->bpix = priv->bpix; + } + if (CONFIG_IS_ENABLED(VIDEO_COPY) && plat->copy_base) priv->copy_fb = map_sysmem(plat->copy_base, plat->size); -- cgit v1.2.3 From 0ce6ae5b2e7a4a6635e7ccc9ea71a61d7cb33987 Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Tue, 5 Mar 2024 18:14:07 +0530 Subject: video: Assume video to be active if SPL is passing video hand-off If SPL is passing video handoff structure to U-boot then it is safe to assume that SPL has already enabled video and that's why it is passing video handoff structure to U-boot so that U-boot can preserve the framebuffer. Signed-off-by: Devarsh Thakkar --- drivers/video/video-uclass.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index fdfab2baa8..9895cfff1f 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -324,6 +324,10 @@ bool video_is_active(void) { struct udevice *dev; + if (IS_ENABLED(CONFIG_SPL_VIDEO) && spl_phase() > PHASE_SPL && + CONFIG_IS_ENABLED(BLOBLIST)) + return true; + for (uclass_find_first_device(UCLASS_VIDEO, &dev); dev; uclass_find_next_device(&dev)) { -- cgit v1.2.3 From c2acebf996fadd2395921e5c9e6409dfbbee4068 Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Tue, 5 Mar 2024 18:14:08 +0530 Subject: common: fdt_simplefb: Enumerate framebuffer info from video handoff Enable and update simple-framebuffer node using the video handoff bloblist if video was enabled at SPL stage and corresponding video bloblist was received at u-boot proper with necessary parameters. Signed-off-by: Devarsh Thakkar --- common/fdt_simplefb.c | 35 ++++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/common/fdt_simplefb.c b/common/fdt_simplefb.c index 282c34fe0b..c50cd7a66f 100644 --- a/common/fdt_simplefb.c +++ b/common/fdt_simplefb.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -26,15 +28,30 @@ static int fdt_simplefb_configure_node(void *blob, int off) struct udevice *dev; int ret; - ret = uclass_first_device_err(UCLASS_VIDEO, &dev); - if (ret) - return ret; - uc_priv = dev_get_uclass_priv(dev); - plat = dev_get_uclass_plat(dev); - xsize = uc_priv->xsize; - ysize = uc_priv->ysize; - bpix = uc_priv->bpix; - fb_base = plat->base; + if (IS_ENABLED(CONFIG_SPL_VIDEO) && spl_phase() > PHASE_SPL && + CONFIG_IS_ENABLED(BLOBLIST)) { + struct video_handoff *ho; + + ho = bloblist_find(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho)); + if (!ho) + return log_msg_ret("Missing video bloblist", -ENOENT); + + xsize = ho->xsize; + ysize = ho->ysize; + bpix = ho->bpix; + fb_base = ho->fb; + } else { + ret = uclass_first_device_err(UCLASS_VIDEO, &dev); + if (ret) + return ret; + uc_priv = dev_get_uclass_priv(dev); + plat = dev_get_uclass_plat(dev); + xsize = uc_priv->xsize; + ysize = uc_priv->ysize; + bpix = uc_priv->bpix; + fb_base = plat->base; + } + switch (bpix) { case 4: /* VIDEO_BPP16 */ name = "r5g6b5"; -- cgit v1.2.3 From e34654f67059401280dd8fd696e48f03a49f9733 Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Tue, 5 Mar 2024 18:14:09 +0530 Subject: common: Move framebuffer reservation to separate helper Create separate helper for just reserving framebuffer region without creating or enabling simple-framebuffer node. This is useful for scenarios where user want to preserve the bootloader splash screen till OS boots up and display server gets started without displaying anything else in between and thus not requiring simple-framebuffer. Signed-off-by: Devarsh Thakkar --- common/fdt_simplefb.c | 12 +----------- common/fdt_support.c | 21 +++++++++++++++++++++ include/fdt_support.h | 2 ++ 3 files changed, 24 insertions(+), 11 deletions(-) diff --git a/common/fdt_simplefb.c b/common/fdt_simplefb.c index c50cd7a66f..2c0ff5d5f9 100644 --- a/common/fdt_simplefb.c +++ b/common/fdt_simplefb.c @@ -102,7 +102,6 @@ int fdt_simplefb_enable_existing_node(void *blob) #if IS_ENABLED(CONFIG_VIDEO) int fdt_simplefb_enable_and_mem_rsv(void *blob) { - struct fdt_memory mem; int ret; /* nothing to do when video is not active */ @@ -113,15 +112,6 @@ int fdt_simplefb_enable_and_mem_rsv(void *blob) if (ret) return ret; - /* nothing to do when the frame buffer is not defined */ - if (gd->video_bottom == gd->video_top) - return 0; - - /* reserved with no-map tag the video buffer */ - mem.start = gd->video_bottom; - mem.end = gd->video_top - 1; - - return fdtdec_add_reserved_memory(blob, "framebuffer", &mem, NULL, 0, NULL, - FDTDEC_RESERVED_MEMORY_NO_MAP); + return fdt_add_fb_mem_rsv(blob); } #endif diff --git a/common/fdt_support.c b/common/fdt_support.c index dbceec6f2d..0e2f12bd09 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -21,6 +21,9 @@ #include #include #include +#include + +DECLARE_GLOBAL_DATA_PTR; /** * fdt_getprop_u32_default_node - Return a node's property or a default @@ -1970,6 +1973,24 @@ int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width, return 0; } +#if IS_ENABLED(CONFIG_VIDEO) +int fdt_add_fb_mem_rsv(void *blob) +{ + struct fdt_memory mem; + + /* nothing to do when the frame buffer is not defined */ + if (gd->video_bottom == gd->video_top) + return 0; + + /* reserved with no-map tag the video buffer */ + mem.start = gd->video_bottom; + mem.end = gd->video_top - 1; + + return fdtdec_add_reserved_memory(blob, "framebuffer", &mem, NULL, 0, NULL, + FDTDEC_RESERVED_MEMORY_NO_MAP); +} +#endif + /* * Update native-mode in display-timings from display environment variable. * The node to update are specified by path. diff --git a/include/fdt_support.h b/include/fdt_support.h index 5638bd4f16..de687bfed9 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -395,6 +395,8 @@ int arch_fixup_memory_node(void *blob); int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width, u32 height, u32 stride, const char *format); +int fdt_add_fb_mem_rsv(void *blob); + int fdt_overlay_apply_verbose(void *fdt, void *fdto); int fdt_valid(struct fdt_header **blobp); -- cgit v1.2.3 From 75fe309112ce61ec6b4a4dc3e8850f547a2407d3 Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Tue, 5 Mar 2024 18:14:10 +0530 Subject: board: ti: am62x: am62px: evm: Update simple-framebuffer node in device-tree Update simple-framebuffer device-tree node by enumerating framebuffer related information in existing simple-framebuffer node in Linux device-tree file and enabling it. While at it, ignore error return value for framebuffer related DT node updates as a non-zero return value for ft_board_setup is treated as a fatal error causing board reset. In case there is no simple-framebuffer stub detected in Linux kernel device-tree and video is still active, then update the device-tree to reserve the framebuffer region for the active splash screen. This helps preserve the splash screen till the display server takes over after OS is booted. In case the simplefb node update or the framebuffer reservation fails we treat it as a non-fatal error and avoid returning error to parent function as the non-zero return value of ft_board_setup is treated as fatal error which leads to board reset Signed-off-by: Devarsh Thakkar --- board/ti/am62px/evm.c | 21 +++++++++++++++++++++ board/ti/am62x/evm.c | 21 +++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c index 5ab56260a4..060c150b56 100644 --- a/board/ti/am62px/evm.c +++ b/board/ti/am62px/evm.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -83,3 +84,23 @@ void spl_board_init(void) splash_display(); } #endif + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + int ret = -1; + + if (IS_ENABLED(CONFIG_VIDEO)) { + if (IS_ENABLED(CONFIG_FDT_SIMPLEFB)) + ret = fdt_simplefb_enable_and_mem_rsv(blob); + + /* If simplefb is not enabled and video is active, then at least reserve + * the framebuffer region to preserve the splash screen while OS is booting + */ + if (ret && video_is_active()) + fdt_add_fb_mem_rsv(blob); + } + + return 0; +} +#endif diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index 6a5a7804b1..9146361b3a 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -400,3 +401,23 @@ int board_late_init(void) return 0; } #endif + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + int ret = -1; + + if (IS_ENABLED(CONFIG_VIDEO)) { + if (IS_ENABLED(CONFIG_FDT_SIMPLEFB)) + ret = fdt_simplefb_enable_and_mem_rsv(blob); + + /* If simplefb is not enabled and video is active, then at least reserve + * the framebuffer region to preserve the splash screen while OS is booting + */ + if (ret && video_is_active()) + fdt_add_fb_mem_rsv(blob); + } + + return 0; +} +#endif -- cgit v1.2.3 From b475266f961f6bfbe59787680806f0b700830bef Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Tue, 5 Mar 2024 18:14:11 +0530 Subject: configs: am62x: am62px: Sort the A53 defconfigs Run `make savedefconfig` to sort the A53 defconfig files for AM62x and AM62p. Signed-off-by: Devarsh Thakkar --- configs/am62px_evm_a53_defconfig | 13 ++----------- configs/am62x_evm_a53_defconfig | 16 +++------------- 2 files changed, 5 insertions(+), 24 deletions(-) diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig index 4dc85af7f9..07fdf652a1 100644 --- a/configs/am62px_evm_a53_defconfig +++ b/configs/am62px_evm_a53_defconfig @@ -1,9 +1,9 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y CONFIG_TI_SECURE_DEVICE=y -CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_BOARD_HAS_32K_RTC_CRYSTAL=y +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -70,20 +70,12 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SPL_BMP=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_CLK=y -CONFIG_CMD_DDRSS=y -CONFIG_CMD_DFU=y CONFIG_CMD_DM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_BMP=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_DDRSS=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y @@ -124,7 +116,6 @@ CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_I2C_EEPROM=y CONFIG_SPL_I2C_EEPROM=y -CONFIG_FS_LOADER=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_SPL_MMC_IO_VOLTAGE=y diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index 4478d362f4..fad7c7ad90 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -1,11 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y CONFIG_TI_SECURE_DEVICE=y -CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_BOARD_HAS_32K_RTC_CRYSTAL=y CONFIG_TI_I2C_BOARD_DETECT=y +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_GPIO=y -CONFIG_BOARD_HAS_32K_RTC_CRYSTAL=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 @@ -73,19 +73,11 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SPL_BMP=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_CLK=y -CONFIG_CMD_DDRSS=y -CONFIG_CMD_DFU=y CONFIG_CMD_DM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_BMP=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_DDRSS=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y @@ -97,7 +89,6 @@ CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y @@ -121,7 +112,6 @@ CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_I2C_EEPROM=y CONFIG_SPL_I2C_EEPROM=y -CONFIG_FS_LOADER=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_SPL_MMC_IO_VOLTAGE=y -- cgit v1.2.3 From dbb6e4280dfa53faaa1c04f5ddd22f9f068d0428 Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Tue, 5 Mar 2024 18:14:12 +0530 Subject: configs: am62x: am62px: Enable simple-framebuffer Enable simple-framebuffer support for AM62x and AM62p platforms which have early splash screen enabled. This updates the simple-framebuffer node in Linux device-tree on the fly with framebuffer address and meta-data and also reserves framebuffer region in device-tree. Also disable the simple-framebuffer support in am62p's prune splashscreen config fragment as it is not required without splashscreen support. Signed-off-by: Devarsh Thakkar --- configs/am62px_evm_a53_defconfig | 2 ++ configs/am62px_evm_prune_splashscreen.config | 1 + configs/am62x_evm_a53_defconfig | 2 ++ 3 files changed, 5 insertions(+) diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig index 07fdf652a1..4362d40d98 100644 --- a/configs/am62px_evm_a53_defconfig +++ b/configs/am62px_evm_a53_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_SPI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_OF_BOARD_SETUP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" CONFIG_BLOBLIST=y @@ -67,6 +68,7 @@ CONFIG_SPL_USB_STORAGE=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_FDT_SIMPLEFB=y CONFIG_SPL_BMP=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_CLK=y diff --git a/configs/am62px_evm_prune_splashscreen.config b/configs/am62px_evm_prune_splashscreen.config index b45a7b347f..1ff1eaa177 100644 --- a/configs/am62px_evm_prune_splashscreen.config +++ b/configs/am62px_evm_prune_splashscreen.config @@ -26,3 +26,4 @@ CONFIG_BLOBLIST=n # CONFIG_SPL_SIZE_LIMIT is not set # CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK is not set CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 +CONFIG_FDT_SIMPLEFB=n diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index fad7c7ad90..cf02498663 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_SPI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_OF_BOARD_SETUP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" CONFIG_BOARD_LATE_INIT=y @@ -70,6 +71,7 @@ CONFIG_SPL_USB_STORAGE=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_FDT_SIMPLEFB=y CONFIG_SPL_BMP=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_CLK=y -- cgit v1.2.3 From eca83814a2d66bfdd58cfd09ab34a20dd5ae73e7 Mon Sep 17 00:00:00 2001 From: Ravi Gunasekaran Date: Wed, 6 Mar 2024 19:17:27 +0530 Subject: HACK: arm: mach-k3: Fix R5 build error commit 2764be4345 ("remoteproc: uclass: Add methods to load firmware to rproc and boot rproc") selects FS_LOADER in Kconfig and this breaks R5 build for some defconfigs across multiple platforms. Enabling CONFIG_SPL_FS_LOADER does not help for all cases. Signed-off-by: Ravi Gunasekaran Tested-by: MD Danish Anwar --- arch/arm/mach-k3/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 9e535d04d2..23ec1f26e8 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -224,7 +224,7 @@ int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr) char *name = NULL; int size = 0; - if (!IS_ENABLED(CONFIG_FS_LOADER)) + if (!CONFIG_IS_ENABLED(FS_LOADER)) return 0; *loadaddr = 0; -- cgit v1.2.3 From b84cf0957282951802b4c20df9ab316e17f16685 Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Fri, 8 Mar 2024 00:15:41 +0530 Subject: configs: j784s4_evm: Update offset OSPI NAND Update size of tiboot3.bin is exceeding allocated area of 512KB, 1MB assigned to tiboot3.bin. Default offset for tispl.bin will not work for OSPI NAND. Add config for tispl.bin offset. Signed-off-by: Apurva Nandan --- configs/j784s4_evm_r5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index 3b8f032094..9d3d55a732 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -61,6 +61,7 @@ CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_MTD_LOAD=y +CONFIG_SYS_MTD_U_BOOT_OFFS=0x100000 CONFIG_SPL_NAND_SPI_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y # CONFIG_SPL_NOR_SUPPORT=y -- cgit v1.2.3 From b27c44375c13f8f22c159eee378578bb0e62f600 Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Mon, 11 Mar 2024 18:53:24 +0530 Subject: HACK: common: splash_source: Don't compile NAND util functions for SPL The NAND flash utility functions under CONFIG_CMD_NAND should not be compiled at SPL stage as the underlying functions are under separate Kconfigs viz. CONFIG_ENV_IS_IN_NAND and hence are not supported at SPL stage right now for splash screen. Long term, the NAND flash utility functions and their dependencies need to be tied with splash screen specific Kconfigs too as splash logo file can be present in NAND storage before bootup. Signed-off-by: Devarsh Thakkar --- common/splash_source.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/splash_source.c b/common/splash_source.c index a17a797fbd..64337b106f 100644 --- a/common/splash_source.c +++ b/common/splash_source.c @@ -48,7 +48,7 @@ static int splash_sf_read_raw(u32 bmp_load_addr, int offset, size_t read_size) } #endif -#ifdef CONFIG_CMD_NAND +#if defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD) static int splash_nand_read_raw(u32 bmp_load_addr, int offset, size_t read_size) { struct mtd_info *mtd = get_nand_dev_by_index(nand_curr_device); -- cgit v1.2.3 From 7673c19f5b969ddda80f3f8f6ebe2e30c570feba Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Mon, 11 Mar 2024 18:53:25 +0530 Subject: arm64: dts: ti: k3-am62x-lp-sk: Enable Microtips OLDI Panel for splash screen Enable microtips mf101hie OLDI panel and link it with DSS ports to enable splash screen on AM62x LP SK. Signed-off-by: Devarsh Thakkar --- arch/arm/dts/k3-am62-lp-sk.dts | 56 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/dts/k3-am62-lp-sk.dts b/arch/arm/dts/k3-am62-lp-sk.dts index fb4024071c..f7bfb1359f 100644 --- a/arch/arm/dts/k3-am62-lp-sk.dts +++ b/arch/arm/dts/k3-am62-lp-sk.dts @@ -70,6 +70,41 @@ states = <1800000 0x0>, <3300000 0x1>; }; + + panel_lvds: panel-lvds { + bootph-pre-ram; + compatible = "simple-panel"; + status= "okay"; + width-mm = <217>; + height-mm = <136>; + data-mapping = "vesa-24"; + panel-timings { + bootph-pre-ram; + clock-frequency = <150274>; + hactive = <1920>; + vactive = <1200>; + hback-porch = <32>; + hfront-porch = <52>; + vback-porch = <24>; + vfront-porch = <8>; + hsync-len = <24>; + vsync-len = <3>; + de-active = <1>; + }; + port@0 { + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_out0>; + }; + }; + + port@1 { + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_out1>; + }; + }; + }; }; &main_pmx0 { @@ -315,3 +350,24 @@ status = "okay"; dr_mode = "peripheral"; }; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + /* VP1: LVDS Output (OLDI TX 0) */ + port@0 { + reg = <0>; + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; + + /* VP1: LVDS Output (OLDI TX 1) */ + port@2 { + reg = <2>; + oldi_out1: endpoint { + remote-endpoint = <&lcd_in1>; + }; + }; + +}; -- cgit v1.2.3 From ae2c40a4bf9441e66c4d4fa29aefe444c7550f57 Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Mon, 11 Mar 2024 18:53:26 +0530 Subject: configs: am62x_lpsk_a53_defconfig: Sort the defconfig Run `make savedefconfig` to sort the defconfig. Signed-off-by: Devarsh Thakkar --- configs/am62x_lpsk_a53_defconfig | 58 +++++++++++++++------------------------- 1 file changed, 22 insertions(+), 36 deletions(-) diff --git a/configs/am62x_lpsk_a53_defconfig b/configs/am62x_lpsk_a53_defconfig index 652327b3fe..24e40946b3 100644 --- a/configs/am62x_lpsk_a53_defconfig +++ b/configs/am62x_lpsk_a53_defconfig @@ -1,10 +1,9 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_SYS_K3_SPL_ATF=y CONFIG_TI_SECURE_DEVICE=y -CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_TI_I2C_BOARD_DETECT=y +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -14,6 +13,7 @@ CONFIG_K3_ATF_LOAD_ADDR=0x9e780000 CONFIG_TARGET_AM625_A53_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000 +CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-am62-lp-sk" @@ -21,17 +21,6 @@ CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y -CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 -CONFIG_SYS_NAND_PAGE_SIZE=0x1000 -CONFIG_SYS_NAND_OOBSIZE=0x100 -CONFIG_SYS_NAND_MAX_CHIPS=1 -CONFIG_SYS_NAND_SELF_INIT=y -# CONFIG_SPL_NAND_AM33XX_BCH is not set -CONFIG_SYS_NAND_U_BOOT_OFFS=0x600000 -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y -CONFIG_NAND_BOOT=y -CONFIG_ENV_SIZE=0x20000 CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y @@ -41,6 +30,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_NAND_BOOT=y CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 @@ -55,14 +45,15 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MEMORY=y CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD_LOAD=y +CONFIG_SYS_MTD_U_BOOT_OFFS=0x280000 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_NAND_IDENT=y -CONFIG_SPL_MTD_LOAD=y -CONFIG_SYS_MTD_U_BOOT_OFFS=0x280000 CONFIG_SPL_NAND_SPI_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER_DOMAIN=y @@ -77,22 +68,14 @@ CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_CLK=y -CONFIG_CMD_DDRSS=y -CONFIG_CMD_DFU=y CONFIG_CMD_DM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_UBI=y -CONFIG_CMD_NAND=y -CONFIG_TI_GPMC=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_DDRSS=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y @@ -104,19 +87,17 @@ CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y -CONFIG_DFU=y CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y -CONFIG_DFU_SF=y CONFIG_DFU_MTD=y CONFIG_DFU_NAND=y CONFIG_DFU_NAND_TRIMFFS=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 CONFIG_DMA_CHANNELS=y @@ -127,9 +108,12 @@ CONFIG_DA8XX_GPIO=y CONFIG_DM_PCA953X=y CONFIG_SPL_DM_PCA953X=y CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y +CONFIG_MEMORY=y +CONFIG_TI_GPMC=y CONFIG_I2C_EEPROM=y CONFIG_SPL_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y @@ -145,14 +129,17 @@ CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_GPMC=y CONFIG_NAND_OMAP_ELM=y +CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 +CONFIG_SYS_NAND_PAGE_COUNT=0x40 +CONFIG_SYS_NAND_PAGE_SIZE=0x1000 +CONFIG_SYS_NAND_OOBSIZE=0x100 +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x600000 +# CONFIG_SPL_NAND_AM33XX_BCH is not set CONFIG_MTD_SPI_NAND=y CONFIG_DM_SPI_FLASH=y -CONFIG_MEMORY=y -CONFIG_SPL_MEMORY=y CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_SOFT_RESET=y @@ -178,7 +165,6 @@ CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_REMOTEPROC_TI_K3_M4F=y CONFIG_RESET_TI_SCI=y -CONFIG_DM_I2C_GPIO=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y CONFIG_SOC_DEVICE_TI_K3=y -- cgit v1.2.3 From 4d5d626c9422b2ad62ae4fff0d9d24fdb76921c9 Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Mon, 11 Mar 2024 18:53:27 +0530 Subject: configs: am62x_lpsk_a53_defconfig: Enable splashscreen for A53 SPL - Enable BMP and Splash screen related configs - Enable bloblist support to pass video blob from SPL stage to U-boot proper. - Use same memory map for enabling splash screen as used for AM62x[1] : -> Create space for loading bmp image file by moving the malloc area and BSS region down to 0x80b80000 and 0x80c80000 respectively -> Increase the SPL size limit and SPL stack size to 512 KiB and 2KiB respectively to accommodate splash support -> Set stack above the malloc region and report stack overflow by setting CONFIG_SPL_SYS_REPORT_STACK_F_USAGE - Enable simple malloc() for A53 SPL - Enable simplefb and fb reservation for A53 SPL Signed-off-by: Devarsh Thakkar --- configs/am62x_lpsk_a53_defconfig | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/configs/am62x_lpsk_a53_defconfig b/configs/am62x_lpsk_a53_defconfig index 24e40946b3..55e29c0b35 100644 --- a/configs/am62x_lpsk_a53_defconfig +++ b/configs/am62x_lpsk_a53_defconfig @@ -22,6 +22,8 @@ CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SIZE_LIMIT=0x80000 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -29,16 +31,22 @@ CONFIG_SPL_SPI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_OF_BOARD_SETUP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NAND_BOOT=y CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_BLOBLIST=y +CONFIG_BLOBLIST_ADDR=0x80D00000 +CONFIG_SPL_MAX_SIZE=0x80000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80c80000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_ENV_SUPPORT=y @@ -66,6 +74,8 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_FDT_SIMPLEFB=y +CONFIG_SPL_BMP=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_CLK=y CONFIG_CMD_DM=y @@ -73,6 +83,7 @@ CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_BMP=y CONFIG_CMD_DDRSS=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y @@ -190,5 +201,23 @@ CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_TIDSS=y +CONFIG_SPL_VIDEO_TIDSS=y +CONFIG_VIDEO_BMP_GZIP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_SPL_VIDEO=y +CONFIG_SPL_SPLASH_SCREEN=y +CONFIG_SPL_SYS_WHITE_ON_BLACK=y +CONFIG_SPL_SPLASH_SCREEN_ALIGN=y +CONFIG_SPL_SPLASH_SOURCE=y +CONFIG_SPL_VIDEO_BMP_GZIP=y +CONFIG_SPL_BMP_24BPP=y +CONFIG_SPL_BMP_32BPP=y +CONFIG_SPL_HIDE_LOGO_VERSION=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_SPL_GZIP=y CONFIG_OF_LIBFDT_OVERLAY=y -- cgit v1.2.3 From 5e206ba8dbcfb348ae2566887d2746ea60e3fdf8 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Wed, 13 Mar 2024 16:37:19 +0530 Subject: arm: dts: k3-j721e-binman: Add support for HSSE2.0 and HSFS1.1 J721E has SR1.1 and SR2.0 having three variants of each GP, HS-FS and HS-SE. Current build does not generate HS-SE SR2.0 and HS-FS SR1.1 so add support for them. Reported-by: Suman Anna Signed-off-by: Neha Malcom Francis Reviewed-by: Suman Anna --- arch/arm/dts/k3-j721e-binman.dtsi | 201 +++++++++++++++++++++++++++++++++++++- 1 file changed, 200 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi index c545f4dd59..ed7f4ec521 100644 --- a/arch/arm/dts/k3-j721e-binman.dtsi +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-binman.dtsi" @@ -118,6 +118,205 @@ }; }; +&binman { + tiboot3-j721e_sr2-hs-evm.bin { + filename = "tiboot3-j721e_sr2-hs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_sr2>; + core = "public"; + core-opts = <2>; + load = ; + keyfile = "custMpk.pem"; + }; + u_boot_spl_sr2: u-boot-spl { + no-expanded; + }; + }; + sysfw_sr2 { + filename = "sysfw.bin_sr2"; + ti-secure-rom { + content = <&ti_fs_cert_sr2>; + core = "secure"; + load = <0x40000>; + keyfile = "custMpk.pem"; + countersign; + }; + ti_fs_cert_sr2: ti-fs-cert.bin { + filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + ti-fs-firmware-j721e_sr2-hs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + itb_sr2 { + filename = "sysfw-j721e_sr2-hs-evm.itb"; + fit { + description = "SYSFW and Config fragments"; + #address-cells = <1>; + images { + sysfw.bin { + description = "sysfw"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "sysfw.bin_sr2"; + }; + }; + board-cfg.bin { + description = "board-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&board_cfg_sr2>; + keyfile = "custMpk.pem"; + }; + board_cfg_sr2: board-cfg { + filename = "board-cfg.bin"; + type = "blob-ext"; + }; + + }; + pm-cfg.bin { + description = "pm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&pm_cfg_sr2>; + keyfile = "custMpk.pem"; + }; + pm_cfg_sr2: pm-cfg { + filename = "pm-cfg.bin"; + type = "blob-ext"; + }; + }; + rm-cfg.bin { + description = "rm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&rm_cfg_sr2>; + keyfile = "custMpk.pem"; + }; + rm_cfg_sr2: rm-cfg { + filename = "rm-cfg.bin"; + type = "blob-ext"; + }; + }; + sec-cfg.bin { + description = "sec-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + ti-secure { + content = <&sec_cfg_sr2>; + keyfile = "custMpk.pem"; + }; + sec_cfg_sr2: sec-cfg { + filename = "sec-cfg.bin"; + type = "blob-ext"; + }; + }; + }; + }; + }; +}; + +&binman { + tiboot3-j721e_sr1_1-hs-fs-evm.bin { + filename = "tiboot3-j721e_sr1_1-hs-fs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_fs_sr1_1>; + core = "public"; + core-opts = <2>; + load = ; + keyfile = "custMpk.pem"; + }; + u_boot_spl_fs_sr1_1: u-boot-spl { + no-expanded; + }; + }; + sysfw_fs_sr1_1 { + filename = "sysfw.bin_fs_sr1_1"; + ti-fs-cert-fs.bin { + filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + ti-fs-firmware-j721e-hs-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + itb_fs_sr1_1 { + filename = "sysfw-j721e_sr1_1-hs-fs-evm.itb"; + fit { + description = "SYSFW and Config fragments"; + #address-cells = <1>; + images { + sysfw.bin { + description = "sysfw"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "sysfw.bin_fs_sr1_1"; + }; + }; + board-cfg.bin { + description = "board-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + board-cfg { + filename = "board-cfg.bin"; + type = "blob-ext"; + }; + + }; + pm-cfg.bin { + description = "pm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + pm-cfg { + filename = "pm-cfg.bin"; + type = "blob-ext"; + }; + }; + rm-cfg.bin { + description = "rm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + rm-cfg { + filename = "rm-cfg.bin"; + type = "blob-ext"; + }; + }; + sec-cfg.bin { + description = "sec-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + sec-cfg { + filename = "sec-cfg.bin"; + type = "blob-ext"; + }; + }; + }; + }; + }; +}; + &binman { tiboot3-j721e_sr2-hs-fs-evm.bin { filename = "tiboot3-j721e_sr2-hs-fs-evm.bin"; -- cgit v1.2.3 From 3760cb997fa9022a380818799ceafb0d24778d7c Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Wed, 13 Mar 2024 16:37:20 +0530 Subject: arm: dts: k3-j7200-binman: Add support for HSSE1.0 and HSFS1.0 J7200 has SR1.0 and SR2.0 having three variants of each GP, HS-FS and HS-SE. Current build does not generate HS-SE SR1.0 and HS-FS SR1.0 so add support for them. Reported-by: Suman Anna Reported-by: Aniket Limaye Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-j7200-binman.dtsi | 95 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 94 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index 7149275d9d..11ddf22c5d 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-binman.dtsi" @@ -47,6 +47,52 @@ config = "pm-cfg_j7200.yaml"; }; +&binman { + tiboot3-j7200-hs-evm.bin { + filename = "tiboot3-j7200-hs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_sr1>, <&ti_fs_enc_sr1>, <&combined_tifs_cfg_sr1>, + <&combined_dm_cfg_sr1>, <&sysfw_inner_cert_sr1>; + combined; + dm-data; + core-opts = <2>; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_sr1>; + content-sysfw = <&ti_fs_enc_sr1>; + content-sysfw-data = <&combined_tifs_cfg_sr1>; + content-sysfw-inner-cert = <&sysfw_inner_cert_sr1>; + content-dm-data = <&combined_dm_cfg_sr1>; + load = <0x41c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x7f000>; + load-dm-data = <0x41c80000>; + }; + u_boot_spl_sr1: u-boot-spl { + no-expanded; + }; + ti_fs_enc_sr1: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j7200-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_sr1: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert_sr1: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-j7200-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg_sr1: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + &binman { tiboot3-j7200_sr2-hs-evm.bin { filename = "tiboot3-j7200_sr2-hs-evm.bin"; @@ -93,6 +139,53 @@ }; }; +&binman { + tiboot3-j7200-hs-fs-evm.bin { + filename = "tiboot3-j7200-hs-fs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_fs_sr1>, <&ti_fs_enc_fs_sr1>, + <&combined_tifs_cfg_fs_sr1>, <&combined_dm_cfg_fs_sr1>, + <&sysfw_inner_cert_fs_sr1>; + combined; + dm-data; + core-opts = <2>; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_fs_sr1>; + content-sysfw = <&ti_fs_enc_fs_sr1>; + content-sysfw-data = <&combined_tifs_cfg_fs_sr1>; + content-sysfw-inner-cert = <&sysfw_inner_cert_fs_sr1>; + content-dm-data = <&combined_dm_cfg_fs_sr1>; + load = <0x41c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x7f000>; + load-dm-data = <0x41c80000>; + }; + u_boot_spl_fs_sr1: u-boot-spl { + no-expanded; + }; + ti_fs_enc_fs_sr1: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j7200-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_fs_sr1: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert_fs_sr1: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-j7200-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg_fs_sr1: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + &binman { tiboot3-j7200_sr2-hs-fs-evm.bin { filename = "tiboot3-j7200_sr2-hs-fs-evm.bin"; -- cgit v1.2.3 From d2612223375a25f81068d7a7abd86c08cd129a2c Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Wed, 13 Mar 2024 23:26:09 +0530 Subject: arm: dts: k3-am62p-binman: Move to using ti-dm entry type Move the DM entry in tispl.bin FIT image from default fetching an external blob entry to fetching using ti-dm entry type. This way, the DM entry will be populated by the TI_DM pathname if provided. Else it will resort to the ti-dm.bin file. Signed-off-by: Vignesh Raghavendra Reviewed-by: Neha Malcom Francis --- arch/arm/dts/k3-am62p-sk-binman.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi index 4d968cd928..6ec23c7310 100644 --- a/arch/arm/dts/k3-am62p-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -235,7 +235,7 @@ content = <&dm>; keyfile = "custMpk.pem"; }; - dm: blob-ext { + dm: ti-dm { filename = "ti-dm.bin"; }; }; @@ -420,7 +420,7 @@ os = "DM"; load = <0x89000000>; entry = <0x89000000>; - blob-ext { + ti-dm { filename = "ti-dm.bin"; }; }; -- cgit v1.2.3