From aa3407cb914966af389b77f5043916e67c0085b0 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Thu, 12 Nov 2015 18:36:57 +0100 Subject: colibri_imx7.c: remove unused subsystems --- board/toradex/colibri_imx7/colibri_imx7.c | 432 ------------------------------ 1 file changed, 432 deletions(-) diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 6449268808..f9977e45b5 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -24,10 +24,6 @@ #include #include #endif -#if defined(CONFIG_MXC_EPDC) -#include -#include -#endif #include #ifdef CONFIG_VIDEO_MXS @@ -80,7 +76,6 @@ DECLARE_GLOBAL_DATA_PTR; #define WEAK_PULLDOWN (PAD_CTL_PUS_PU47KOHM | PAD_CTL_PUE | \ | PAD_CTL_HYS | PAD_CTL_SRE_SLOW | PAD_CTL_DSE_3P3V_49OHM) -#define EPDC_PAD_CTRL 0x0 #ifdef CONFIG_SYS_I2C_MXC #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -120,10 +115,6 @@ int dram_init(void) return 0; } -static iomux_v3_cfg_t const wdog_pads[] = { - MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - static iomux_v3_cfg_t const uart1_pads[] = { MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), @@ -138,152 +129,8 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { - MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -#define IOX_SDI IMX_GPIO_NR(1, 9) -#define IOX_STCP IMX_GPIO_NR(1, 12) -#define IOX_SHCP IMX_GPIO_NR(1, 13) - -static iomux_v3_cfg_t const iox_pads[] = { - /* IOX_SDI */ - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* IOX_STCP */ - MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* IOX_SHCP */ - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -/* - * PCIE_DIS_B --> Q0 - * PCIE_RST_B --> Q1 - * HDMI_RST_B --> Q2 - * PERI_RST_B --> Q3 - * SENSOR_RST_B --> Q4 - * ENET_RST_B --> Q5 - * PERI_3V3_EN --> Q6 - * LCD_PWR_EN --> Q7 - */ -enum qn { - PCIE_DIS_B, - PCIE_RST_B, - HDMI_RST_B, - PERI_RST_B, - SENSOR_RST_B, - ENET_RST_B, - PERI_3V3_EN, - LCD_PWR_EN, -}; - -enum qn_func { - qn_reset, - qn_enable, - qn_disable, -}; - -enum qn_level { - qn_low = 0, - qn_high = 1, -}; - -static enum qn_level seq[3][2] = { - {0, 1}, {1, 1}, {0, 0} -}; - -static enum qn_func qn_output[8] = { - qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable, - qn_enable -}; - -void iox74lv_init(void) -{ - int i; - - for (i = 7; i >= 0; i--) { - gpio_direction_output(IOX_SHCP, 0); - gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); - udelay(500); - gpio_direction_output(IOX_SHCP, 1); - udelay(500); - } - - gpio_direction_output(IOX_STCP, 0); - udelay(500); - /* - * shift register will be output to pins - */ - gpio_direction_output(IOX_STCP, 1); - - for (i = 7; i >= 0; i--) { - gpio_direction_output(IOX_SHCP, 0); - gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); - udelay(500); - gpio_direction_output(IOX_SHCP, 1); - udelay(500); - } - gpio_direction_output(IOX_STCP, 0); - udelay(500); - /* - * shift register will be output to pins - */ - gpio_direction_output(IOX_STCP, 1); -}; - -void iox74lv_set(int index) -{ - int i; - for (i = 7; i >= 0; i--) { - gpio_direction_output(IOX_SHCP, 0); - - if (i == index) - gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); - else - gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); - udelay(500); - gpio_direction_output(IOX_SHCP, 1); - udelay(500); - } - - gpio_direction_output(IOX_STCP, 0); - udelay(500); - /* - * shift register will be output to pins - */ - gpio_direction_output(IOX_STCP, 1); - - for (i = 7; i >= 0; i--) { - gpio_direction_output(IOX_SHCP, 0); - gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); - udelay(500); - gpio_direction_output(IOX_SHCP, 1); - udelay(500); - } - - gpio_direction_output(IOX_STCP, 0); - udelay(500); - /* - * shift register will be output to pins - */ - gpio_direction_output(IOX_STCP, 1); }; - #ifdef CONFIG_SYS_USE_NAND static iomux_v3_cfg_t const gpmi_pads[] = { MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), @@ -471,28 +318,6 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -#ifdef CONFIG_FSL_QSPI -static iomux_v3_cfg_t const quadspi_pads[] = { - MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), - MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), - MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), - MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), - MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), - MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), -}; - -int board_qspi_init(void) -{ - /* Set the iomux */ - imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); - - /* Set the clock */ - set_clk_qspi(); - - return 0; -} -#endif - #ifdef CONFIG_FSL_ESDHC #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) @@ -674,249 +499,6 @@ int board_phy_config(struct phy_device *phydev) } #endif -#ifdef CONFIG_MXC_EPDC -static iomux_v3_cfg_t const epdc_enable_pads[] = { - MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), -}; - -static iomux_v3_cfg_t const epdc_disable_pads[] = { - MX7D_PAD_EPDC_DATA00__GPIO2_IO0, - MX7D_PAD_EPDC_DATA01__GPIO2_IO1, - MX7D_PAD_EPDC_DATA02__GPIO2_IO2, - MX7D_PAD_EPDC_DATA03__GPIO2_IO3, - MX7D_PAD_EPDC_DATA04__GPIO2_IO4, - MX7D_PAD_EPDC_DATA05__GPIO2_IO5, - MX7D_PAD_EPDC_DATA06__GPIO2_IO6, - MX7D_PAD_EPDC_DATA07__GPIO2_IO7, - MX7D_PAD_EPDC_SDCLK__GPIO2_IO16, - MX7D_PAD_EPDC_SDLE__GPIO2_IO17, - MX7D_PAD_EPDC_SDOE__GPIO2_IO18, - MX7D_PAD_EPDC_SDSHR__GPIO2_IO19, - MX7D_PAD_EPDC_SDCE0__GPIO2_IO20, - MX7D_PAD_EPDC_SDCE1__GPIO2_IO21, - MX7D_PAD_EPDC_GDCLK__GPIO2_IO24, - MX7D_PAD_EPDC_GDOE__GPIO2_IO25, - MX7D_PAD_EPDC_GDRL__GPIO2_IO26, - MX7D_PAD_EPDC_GDSP__GPIO2_IO27, - MX7D_PAD_EPDC_BDR0__GPIO2_IO28, - MX7D_PAD_EPDC_BDR1__GPIO2_IO29, -}; - -vidinfo_t panel_info = { - .vl_refresh = 85, - .vl_col = 1024, - .vl_row = 758, - .vl_pixclock = 40000000, - .vl_left_margin = 12, - .vl_right_margin = 76, - .vl_upper_margin = 4, - .vl_lower_margin = 5, - .vl_hsync = 12, - .vl_vsync = 2, - .vl_sync = 0, - .vl_mode = 0, - .vl_flag = 0, - .vl_bpix = 3, - .cmap = 0, -}; - -struct epdc_timing_params panel_timings = { - .vscan_holdoff = 4, - .sdoed_width = 10, - .sdoed_delay = 20, - .sdoez_width = 10, - .sdoez_delay = 20, - .gdclk_hp_offs = 524, - .gdsp_offs = 327, - .gdoe_offs = 0, - .gdclk_offs = 19, - .num_ce = 1, -}; - -static void setup_epdc_power(void) -{ - /* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */ - struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs - = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; - - clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], - IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0); - - /* Setup epdc voltage */ - - /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ - imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | - MUX_PAD_CTRL(EPDC_PAD_CTRL)); - gpio_direction_input(IMX_GPIO_NR(2, 31)); - - /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ - imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | - MUX_PAD_CTRL(EPDC_PAD_CTRL)); - - /* Set as output */ - gpio_direction_output(IMX_GPIO_NR(4, 14), 1); - - /* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */ - imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 | - MUX_PAD_CTRL(EPDC_PAD_CTRL)); - /* Set as output */ - gpio_direction_output(IMX_GPIO_NR(2, 23), 1); - - /* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */ - imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 | - MUX_PAD_CTRL(EPDC_PAD_CTRL)); - /* Set as output */ - gpio_direction_output(IMX_GPIO_NR(2, 30), 1); -} - -int setup_waveform_file(ulong waveform_buf) -{ - char *fs_argv[5]; - char addr[17]; - ulong file_len, mmc_dev; - - if (!check_mmc_autodetect()) - mmc_dev = getenv_ulong("mmcdev", 10, 0); - else - mmc_dev = mmc_get_env_devno(); - - sprintf(addr, "%lx", waveform_buf); - - fs_argv[0] = "fatload"; - fs_argv[1] = "mmc"; - fs_argv[2] = simple_itoa(mmc_dev); - fs_argv[3] = addr; - fs_argv[4] = getenv("epdc_waveform"); - - if (!fs_argv[4]) - fs_argv[4] = "epdc_splash.bin"; - - if (do_fat_fsload(NULL, 0, 5, fs_argv)) { - printf("File %s not found on MMC Device %lu \n", fs_argv[4], mmc_dev); - return -1; - } - - file_len = getenv_hex("filesize", 0); - if (!file_len) - return -1; - - flush_cache((ulong)addr, file_len); - - return 0; -} - -static void epdc_enable_pins(void) -{ - /* epdc iomux settings */ - imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, - ARRAY_SIZE(epdc_enable_pads)); -} - -static void epdc_disable_pins(void) -{ - /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ - imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, - ARRAY_SIZE(epdc_disable_pads)); -} - -static void setup_epdc(void) -{ - /*** epdc Maxim PMIC settings ***/ - - /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ - imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | - MUX_PAD_CTRL(EPDC_PAD_CTRL)); - - /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ - imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | - MUX_PAD_CTRL(EPDC_PAD_CTRL)); - - /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */ - imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 | - MUX_PAD_CTRL(EPDC_PAD_CTRL)); - - /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */ - imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 | - MUX_PAD_CTRL(EPDC_PAD_CTRL)); - - /* Set pixel clock rates for EPDC in clock.c */ - - panel_info.epdc_data.wv_modes.mode_init = 0; - panel_info.epdc_data.wv_modes.mode_du = 1; - panel_info.epdc_data.wv_modes.mode_gc4 = 3; - panel_info.epdc_data.wv_modes.mode_gc8 = 2; - panel_info.epdc_data.wv_modes.mode_gc16 = 2; - panel_info.epdc_data.wv_modes.mode_gc32 = 2; - - panel_info.epdc_data.epdc_timings = panel_timings; - - setup_epdc_power(); -} - -void epdc_power_on(void) -{ - unsigned int reg; - struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; - - /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ - gpio_set_value(IMX_GPIO_NR(2, 30), 1); - udelay(1000); - - /* Enable epdc signal pin */ - epdc_enable_pins(); - - /* Set PMIC Wakeup to high - enable Display power */ - gpio_set_value(IMX_GPIO_NR(2, 23), 1); - - /* Wait for PWRGOOD == 1 */ - while (1) { - reg = readl(&gpio_regs->gpio_psr); - if (!(reg & (1 << 31))) - break; - - udelay(100); - } - - /* Enable VCOM */ - gpio_set_value(IMX_GPIO_NR(4, 14), 1); - - udelay(500); -} - -void epdc_power_off(void) -{ - /* Set PMIC Wakeup to low - disable Display power */ - gpio_set_value(IMX_GPIO_NR(2, 23), 0); - - /* Disable VCOM */ - gpio_set_value(IMX_GPIO_NR(4, 14), 0); - - epdc_disable_pins(); - - /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ - gpio_set_value(IMX_GPIO_NR(2, 30), 0); -} -#endif - int board_early_init_f(void) { setup_iomux_uart(); @@ -934,10 +516,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); - - iox74lv_init(); - #ifdef CONFIG_FEC_MXC setup_fec(); #endif @@ -950,12 +528,6 @@ int board_init(void) board_qspi_init(); #endif -#ifdef CONFIG_MXC_EPDC - qn_output[5] = qn_disable; - iox74lv_set(5); - setup_epdc(); -#endif - return 0; } @@ -988,10 +560,6 @@ int board_late_init(void) board_late_mmc_init(); #endif - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); - return 0; } -- cgit v1.2.3