From a5731ef9d6b610f3f8a075e60958aa07a36ac31e Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 15 Feb 2024 10:52:35 -0600 Subject: arm: dts: k3-am62x-lp4: update to latest emif tool output The output from the emif tool hasn't changed for a while now, however there is still a difference from what we use. Signed-off-by: Bryan Brattlof --- arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi | 34 +++++++++++++-------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi b/arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi index 74693d12e1..c255ae6530 100644 --- a/arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi +++ b/arch/arm/dts/k3-am62x-ddr-lp4-50-800-800.dtsi @@ -1,15 +1,16 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.08.61 - * Tue Mar 22 2022 17:03:08 GMT-0500 (Central Daylight Time) + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.07 + * Wed Mar 01 2023 17:52:11 GMT-0600 (Central Standard Time) * DDR Type: LPDDR4 - * F0 = 50MHz F1 = 800MHz F2 = 800MHz + * F0 = 50MHz F1 = NA F2 = 800MHz * Density (per channel): 16Gb + * Write DBI: Enable * Number of Ranks: 1 */ -#define DDRSS_PLL_FHS_CNT 6 +#define DDRSS_PLL_FHS_CNT 3 #define DDRSS_PLL_FREQUENCY_1 400000000 #define DDRSS_PLL_FREQUENCY_2 400000000 @@ -283,10 +284,10 @@ #define DDRSS_CTL_267_DATA 0x0000000F #define DDRSS_CTL_268_DATA 0x0000000F #define DDRSS_CTL_269_DATA 0x00000000 -#define DDRSS_CTL_270_DATA 0x00000000 +#define DDRSS_CTL_270_DATA 0x00001000 #define DDRSS_CTL_271_DATA 0x00000015 #define DDRSS_CTL_272_DATA 0x00000015 -#define DDRSS_CTL_273_DATA 0x00000000 +#define DDRSS_CTL_273_DATA 0x00000010 #define DDRSS_CTL_274_DATA 0x00000015 #define DDRSS_CTL_275_DATA 0x00000015 #define DDRSS_CTL_276_DATA 0x00000020 @@ -334,7 +335,7 @@ #define DDRSS_CTL_318_DATA 0x3FFF0000 #define DDRSS_CTL_319_DATA 0x000FFF00 #define DDRSS_CTL_320_DATA 0xFFFFFFFF -#define DDRSS_CTL_321_DATA 0x000FFF00 +#define DDRSS_CTL_321_DATA 0x00FFFF00 #define DDRSS_CTL_322_DATA 0x0B000000 #define DDRSS_CTL_323_DATA 0x0001FFFF #define DDRSS_CTL_324_DATA 0x01010101 @@ -448,7 +449,7 @@ #define DDRSS_PI_9_DATA 0x00000000 #define DDRSS_PI_10_DATA 0x00000000 #define DDRSS_PI_11_DATA 0x00000002 -#define DDRSS_PI_12_DATA 0x00000007 +#define DDRSS_PI_12_DATA 0x00000005 #define DDRSS_PI_13_DATA 0x00010001 #define DDRSS_PI_14_DATA 0x08000000 #define DDRSS_PI_15_DATA 0x00010300 @@ -479,7 +480,7 @@ #define DDRSS_PI_40_DATA 0x000000A9 #define DDRSS_PI_41_DATA 0x000000A9 #define DDRSS_PI_42_DATA 0x000000B5 -#define DDRSS_PI_43_DATA 0x01000000 +#define DDRSS_PI_43_DATA 0x00000000 #define DDRSS_PI_44_DATA 0x00000000 #define DDRSS_PI_45_DATA 0x00010100 #define DDRSS_PI_46_DATA 0x00000015 @@ -507,7 +508,7 @@ #define DDRSS_PI_68_DATA 0x00000034 #define DDRSS_PI_69_DATA 0x00000000 #define DDRSS_PI_70_DATA 0x00000000 -#define DDRSS_PI_71_DATA 0x0001FFFF +#define DDRSS_PI_71_DATA 0x0000FFFF #define DDRSS_PI_72_DATA 0x00000000 #define DDRSS_PI_73_DATA 0x00000000 #define DDRSS_PI_74_DATA 0x00000000 @@ -740,7 +741,7 @@ #define DDRSS_PI_301_DATA 0x00000000 #define DDRSS_PI_302_DATA 0x00000000 #define DDRSS_PI_303_DATA 0x00000000 -#define DDRSS_PI_304_DATA 0x00000F27 +#define DDRSS_PI_304_DATA 0x00100F27 #define DDRSS_PI_305_DATA 0x00000000 #define DDRSS_PI_306_DATA 0x00000024 #define DDRSS_PI_307_DATA 0x00000012 @@ -764,7 +765,7 @@ #define DDRSS_PI_325_DATA 0x00000000 #define DDRSS_PI_326_DATA 0x00000000 #define DDRSS_PI_327_DATA 0x00000000 -#define DDRSS_PI_328_DATA 0x00000F27 +#define DDRSS_PI_328_DATA 0x00100F27 #define DDRSS_PI_329_DATA 0x00000000 #define DDRSS_PI_330_DATA 0x00000024 #define DDRSS_PI_331_DATA 0x00000012 @@ -901,7 +902,7 @@ #define DDRSS_PHY_117_DATA 0x00800080 #define DDRSS_PHY_118_DATA 0x00800080 #define DDRSS_PHY_119_DATA 0x01800080 -#define DDRSS_PHY_120_DATA 0x01A00001 +#define DDRSS_PHY_120_DATA 0x01000000 #define DDRSS_PHY_121_DATA 0x00000000 #define DDRSS_PHY_122_DATA 0x00000000 #define DDRSS_PHY_123_DATA 0x00080200 @@ -1157,7 +1158,7 @@ #define DDRSS_PHY_373_DATA 0x00800080 #define DDRSS_PHY_374_DATA 0x00800080 #define DDRSS_PHY_375_DATA 0x01800080 -#define DDRSS_PHY_376_DATA 0x01A00001 +#define DDRSS_PHY_376_DATA 0x01000000 #define DDRSS_PHY_377_DATA 0x00000000 #define DDRSS_PHY_378_DATA 0x00000000 #define DDRSS_PHY_379_DATA 0x00080200 @@ -2152,7 +2153,7 @@ #define DDRSS_PHY_1368_DATA 0x00000002 #define DDRSS_PHY_1369_DATA 0x00000000 #define DDRSS_PHY_1370_DATA 0x00000000 -#define DDRSS_PHY_1371_DATA 0x0001F7C0 +#define DDRSS_PHY_1371_DATA 0x0001F7C2 #define DDRSS_PHY_1372_DATA 0x00020002 #define DDRSS_PHY_1373_DATA 0x00000000 #define DDRSS_PHY_1374_DATA 0x00001142 @@ -2183,8 +2184,7 @@ #define DDRSS_PHY_1399_DATA 0x000C3F11 #define DDRSS_PHY_1400_DATA 0x01990000 #define DDRSS_PHY_1401_DATA 0x3F0DFF11 -#define DDRSS_PHY_1402_DATA 0x019900E0 +#define DDRSS_PHY_1402_DATA 0x01990000 #define DDRSS_PHY_1403_DATA 0x00018011 #define DDRSS_PHY_1404_DATA 0x0089FF00 #define DDRSS_PHY_1405_DATA 0x20040004 - -- cgit v1.2.3