From 7d71154703be65ebb48676427780f69b72160acb Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Fri, 24 Oct 2014 16:43:09 +0200 Subject: arm: vf610: improve DDR initialization With the new JEDEC standardized initialization parameter, the initialization takes longer than 200us. Use the status bit to determine whether the memory initialization was completed. Also use recommended JEDEC defaults for t_INIT. --- arch/arm/imx-common/ddr-vf610.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/imx-common/ddr-vf610.c b/arch/arm/imx-common/ddr-vf610.c index 1ab5af058b..ffcc3d2dd8 100644 --- a/arch/arm/imx-common/ddr-vf610.c +++ b/arch/arm/imx-common/ddr-vf610.c @@ -105,7 +105,7 @@ void ddr_ctrl_init(int tref, int trfc, int col_diff, int row_diff) struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR; writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); - writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]); + writel(DDRMC_CR02_DRAM_TINIT(5), &ddrmr->cr[2]); writel(DDRMC_CR10_TRST_PWRON(80000), &ddrmr->cr[10]); writel(DDRMC_CR11_CKE_INACTIVE(200000), &ddrmr->cr[11]); @@ -237,6 +237,6 @@ void ddr_ctrl_init(int tref, int trfc, int col_diff, int row_diff) writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]); - udelay(200); + while (!(readl(&ddrmr->cr[80]) && 0x100)) + udelay(10); } - -- cgit v1.2.3