From 56c5b506f71dfe063807c6e837ce06c265a6df65 Mon Sep 17 00:00:00 2001 From: Jingchang Lu Date: Tue, 3 Jul 2012 13:21:44 +0800 Subject: Add eSDHC support for Vybrid platform On some platform, such as vybrid, there is no scr register, but the dis-order excution may wrongly excute the register write. The barrier used to prevent this. Signed-off-by: Jason Jin --- drivers/mmc/fsl_esdhc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index a2f35e3e99..e8b304ab2f 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc + * Copyright 2007, 2010-2012 Freescale Semiconductor, Inc * Andy Fleming * * Based vaguely on the pxa mmc code: @@ -428,8 +428,11 @@ static int esdhc_init(struct mmc *mmc) udelay(1000); /* Enable cache snooping */ - if (cfg && !cfg->no_snoop) + + if (cfg && !cfg->no_snoop) { + asm volatile("" ::: "memory"); esdhc_write32(®s->scr, 0x00000040); + } esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); @@ -542,6 +545,9 @@ int fsl_esdhc_mmc_init(bd_t *bis) cfg = malloc(sizeof(struct fsl_esdhc_cfg)); memset(cfg, 0, sizeof(struct fsl_esdhc_cfg)); cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; +#ifdef CONFIG_ESDHC_NO_SNOOP + cfg->no_snoop = 1; +#endif return fsl_esdhc_initialize(bis, cfg); } -- cgit v1.2.3