From 11efa9a0c5e3bef3098ac974d0b036c82692b647 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Sat, 29 Sep 2018 13:39:24 +0800 Subject: MLK-19777-01: imx8mm: rename the lpddr4_ddrphy_train file For LPDDR4 or DDR4, the ddr phy train flow is the same. So rename the 'lpddr4_ddrphy_train.c' to 'ddrphy_train.c'. make it more common for reuse and move it to driver/ddr/imx8m/. Signed-off-by: Bai Ping (cherry picked from commit 258db72309ec47b99cec89c06f6b4491f9951b27) --- arch/arm/include/asm/arch-imx8m/imx8m_ddr.h | 2 +- drivers/ddr/imx8m/Makefile | 4 +- drivers/ddr/imx8m/ddrphy_train.c | 87 ++++++++++++ drivers/ddr/imx8m/lpddr4/Makefile | 7 - drivers/ddr/imx8m/lpddr4/lpddr4_ddrphy_train.c | 87 ------------ drivers/ddr/imx8m/lpddr4/lpddr4_init.c | 186 ------------------------- drivers/ddr/imx8m/lpddr4_init.c | 186 +++++++++++++++++++++++++ 7 files changed, 276 insertions(+), 283 deletions(-) create mode 100644 drivers/ddr/imx8m/ddrphy_train.c delete mode 100644 drivers/ddr/imx8m/lpddr4/Makefile delete mode 100644 drivers/ddr/imx8m/lpddr4/lpddr4_ddrphy_train.c delete mode 100644 drivers/ddr/imx8m/lpddr4/lpddr4_init.c create mode 100644 drivers/ddr/imx8m/lpddr4_init.c diff --git a/arch/arm/include/asm/arch-imx8m/imx8m_ddr.h b/arch/arm/include/asm/arch-imx8m/imx8m_ddr.h index e5180e85f7..9ea4d588a4 100644 --- a/arch/arm/include/asm/arch-imx8m/imx8m_ddr.h +++ b/arch/arm/include/asm/arch-imx8m/imx8m_ddr.h @@ -52,7 +52,7 @@ extern struct dram_timing_info lpddr4_timing; void ddr_load_train_firmware(enum fw_type type); void ddr_init(struct dram_timing_info *timing_info); -void lpddr4_cfg_phy(struct dram_timing_info *timing_info); +void ddr_cfg_phy(struct dram_timing_info *timing_info); void load_lpddr4_phy_pie(void); void ddrphy_trained_csr_save(struct dram_cfg_param *, unsigned int); void dram_config_save(struct dram_timing_info *, unsigned long); diff --git a/drivers/ddr/imx8m/Makefile b/drivers/ddr/imx8m/Makefile index a90a4e4b5c..9e4a6992a1 100644 --- a/drivers/ddr/imx8m/Makefile +++ b/drivers/ddr/imx8m/Makefile @@ -5,6 +5,6 @@ # ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o -obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4/ +obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_init.o endif diff --git a/drivers/ddr/imx8m/ddrphy_train.c b/drivers/ddr/imx8m/ddrphy_train.c new file mode 100644 index 0000000000..310099d7c4 --- /dev/null +++ b/drivers/ddr/imx8m/ddrphy_train.c @@ -0,0 +1,87 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include + +void ddr_cfg_phy(struct dram_timing_info *dram_timing) +{ + struct dram_cfg_param *dram_cfg; + struct dram_fsp_msg *fsp_msg; + unsigned int num; + int i = 0; + int j = 0; + + /* initialize PHY configuration */ + dram_cfg = dram_timing->ddrphy_cfg; + num = dram_timing->ddrphy_cfg_num; + for (i = 0; i < num; i++) { + /* config phy reg */ + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* load the frequency setpoint message block config */ + fsp_msg = dram_timing->fsp_msg; + for (i = 0; i < dram_timing->fsp_msg_num; i++) { + printf("DRAM PHY training for %dMTS\n", fsp_msg->drate); + /* set dram PHY input clocks to desired frequency */ + ddrphy_init_set_dfi_clk(fsp_msg->drate); + + /* load the dram training firmware image */ + dwc_ddrphy_apb_wr(0xd0000,0x0); + ddr_load_train_firmware(fsp_msg->fw_type); + + /* load the frequency set point message block parameter */ + dram_cfg = fsp_msg->fsp_cfg; + num = fsp_msg->fsp_cfg_num; + for (j = 0; j < num; j++) { + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* + * -------------------- excute the firmware -------------------- + * Running the firmware is a simply process to taking the + * PMU out of reset and stall, then the firwmare will be run + * 1. reset the PMU; + * 2. begin the excution; + * 3. wait for the training done; + * 4. read the message block result. + * ------------------------------------------------------------- + */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); + dwc_ddrphy_apb_wr(0xd0099, 0x9); + dwc_ddrphy_apb_wr(0xd0099, 0x1); + dwc_ddrphy_apb_wr(0xd0099, 0x0); + + /* Wait for the training firmware to complete */ + wait_ddrphy_training_complete(); + + /* Halt the microcontroller. */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); + + /* Read the Message Block results */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + ddrphy_init_read_msg_block(fsp_msg->fw_type); + dwc_ddrphy_apb_wr(0xd0000, 0x1); + + fsp_msg++; + } + + /* Load PHY Init Engine Image */ + dram_cfg = dram_timing->ddrphy_pie; + num = dram_timing->ddrphy_pie_num; + for (i = 0; i < num; i++) { + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* save the ddr PHY trained CSR in memory for low power use */ + ddrphy_trained_csr_save(dram_timing->ddrphy_trained_csr, + dram_timing->ddrphy_trained_csr_num); +} diff --git a/drivers/ddr/imx8m/lpddr4/Makefile b/drivers/ddr/imx8m/lpddr4/Makefile deleted file mode 100644 index 1710bac652..0000000000 --- a/drivers/ddr/imx8m/lpddr4/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright 2018 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_SPL_BUILD) += lpddr4_init.o lpddr4_ddrphy_train.o diff --git a/drivers/ddr/imx8m/lpddr4/lpddr4_ddrphy_train.c b/drivers/ddr/imx8m/lpddr4/lpddr4_ddrphy_train.c deleted file mode 100644 index 976ccb908c..0000000000 --- a/drivers/ddr/imx8m/lpddr4/lpddr4_ddrphy_train.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright 2018 NXP - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include - -void lpddr4_cfg_phy(struct dram_timing_info *dram_timing) -{ - struct dram_cfg_param *dram_cfg; - struct dram_fsp_msg *fsp_msg; - unsigned int num; - int i = 0; - int j = 0; - - /* initialize PHY configuration */ - dram_cfg = dram_timing->ddrphy_cfg; - num = dram_timing->ddrphy_cfg_num; - for (i = 0; i < num; i++) { - /* config phy reg */ - dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); - dram_cfg++; - } - - /* load the frequency setpoint message block config */ - fsp_msg = dram_timing->fsp_msg; - for (i = 0; i < dram_timing->fsp_msg_num; i++) { - printf("DRAM PHY training for %dMTS\n", fsp_msg->drate); - /* set dram PHY input clocks to desired frequency */ - ddrphy_init_set_dfi_clk(fsp_msg->drate); - - /* load the dram training firmware image */ - dwc_ddrphy_apb_wr(0xd0000,0x0); - ddr_load_train_firmware(fsp_msg->fw_type); - - /* load the frequency set point message block parameter */ - dram_cfg = fsp_msg->fsp_cfg; - num = fsp_msg->fsp_cfg_num; - for (j = 0; j < num; j++) { - dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); - dram_cfg++; - } - - /* - * -------------------- excute the firmware -------------------- - * Running the firmware is a simply process to taking the - * PMU out of reset and stall, then the firwmare will be run - * 1. reset the PMU; - * 2. begin the excution; - * 3. wait for the training done; - * 4. read the message block result. - * ------------------------------------------------------------- - */ - dwc_ddrphy_apb_wr(0xd0000, 0x1); - dwc_ddrphy_apb_wr(0xd0099, 0x9); - dwc_ddrphy_apb_wr(0xd0099, 0x1); - dwc_ddrphy_apb_wr(0xd0099, 0x0); - - /* Wait for the training firmware to complete */ - wait_ddrphy_training_complete(); - - /* Halt the microcontroller. */ - dwc_ddrphy_apb_wr(0xd0099, 0x1); - - /* Read the Message Block results */ - dwc_ddrphy_apb_wr(0xd0000, 0x0); - ddrphy_init_read_msg_block(fsp_msg->fw_type); - dwc_ddrphy_apb_wr(0xd0000, 0x1); - - fsp_msg++; - } - - /* Load PHY Init Engine Image */ - dram_cfg = dram_timing->ddrphy_pie; - num = dram_timing->ddrphy_pie_num; - for (i = 0; i < num; i++) { - dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); - dram_cfg++; - } - - /* save the ddr PHY trained CSR in memory for low power use */ - ddrphy_trained_csr_save(dram_timing->ddrphy_trained_csr, - dram_timing->ddrphy_trained_csr_num); -} diff --git a/drivers/ddr/imx8m/lpddr4/lpddr4_init.c b/drivers/ddr/imx8m/lpddr4/lpddr4_init.c deleted file mode 100644 index d143eeb6b7..0000000000 --- a/drivers/ddr/imx8m/lpddr4/lpddr4_init.c +++ /dev/null @@ -1,186 +0,0 @@ -/* -* Copyright 2018 NXP -* -* SPDX-License-Identifier: GPL-2.0+ -*/ - -#include -#include -#include -#include -#include -#include -#include -#include - -void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) -{ - int i = 0; - - for (i = 0; i < num; i++) { - reg32_write(ddrc_cfg->reg, ddrc_cfg->val); - ddrc_cfg++; - } -} - -void ddr_init(struct dram_timing_info *dram_timing) -{ - unsigned int tmp; - - printf("DDRINFO: start lpddr4 ddr init\n"); - /* step 1: reset */ - if (is_imx8mq()) { - reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F); - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); - reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000); - } else { - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F); - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); - } - - mdelay(100); - - debug("DDRINFO: reset done\n"); - /* change the clock source of dram_apb_clk_root: source 4 800MHz /4 = 200MHz */ - clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | - CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); - - /* disable iso */ - reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ - reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ - - debug("DDRINFO: cfg clk\n"); - dram_pll_init(DRAM_PLL_OUT_750M); - - /* - * release [0]ddr1_preset_n, [1]ddr1_core_reset_n, - * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n - */ - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); - - /*step2 Configure uMCTL2's registers */ - debug("DDRINFO: ddrc config start\n"); - lpddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); - debug("DDRINFO: ddrc config done\n"); - - /* - * step3 de-assert all reset - * RESET: DEASSERTED - * RESET: for Port 0 DEASSERT(0)ED - */ - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); - - reg32_write(DDRC_DBG1(0), 0x00000000); - /* step4 */ - /* [0]dis_auto_refresh=1 */ - reg32_write(DDRC_RFSHCTL3(0), 0x00000011); - - /* [8]--1: lpddr4_sr allowed; [5]--1: software entry to SR */ - reg32_write(DDRC_PWRCTL(0), 0x000000a8); - - do { - tmp = reg32_read(DDRC_STAT(0)); - } while ((tmp & 0x33f) != 0x223); - - reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ - - /* step5 */ - reg32_write(DDRC_SWCTL(0), 0x00000000); - - /* step6 */ - tmp = reg32_read(DDRC_MSTR2(0)); - if (tmp == 0x2) { - reg32_write(DDRC_DFIMISC(0), 0x00000210); - } else if (tmp == 0x1) { - reg32_write(DDRC_DFIMISC(0), 0x00000110); - } else { - reg32_write(DDRC_DFIMISC(0), 0x00000010); - } - - /* step7 [0]--1: disable quasi-dynamic programming */ - reg32_write(DDRC_SWCTL(0), 0x00000001); - - /* step8 Configure LPDDR4 PHY's registers */ - debug("DDRINFO:ddrphy config start\n"); - lpddr4_cfg_phy(dram_timing); - debug("DDRINFO: ddrphy config done\n"); - - /* - * step14 CalBusy.0 =1, indicates the calibrator is actively - * calibrating. Wait Calibrating done. - */ - do { - tmp = reg32_read(DDRPHY_CalBusy(0)); - } while ((tmp & 0x1)); - - printf("DDRINFO:ddrphy calibration done\n"); - - /* step15 [0]--0: to enable quasi-dynamic programming */ - reg32_write(DDRC_SWCTL(0), 0x00000000); - - /* step16 */ - tmp = reg32_read(DDRC_MSTR2(0)); - if (tmp == 0x2) { - reg32_write(DDRC_DFIMISC(0), 0x00000230); - } else if (tmp == 0x1) { - reg32_write(DDRC_DFIMISC(0), 0x00000130); - } else { - reg32_write(DDRC_DFIMISC(0), 0x00000030); - } - - /* step17 [0]--1: disable quasi-dynamic programming */ - reg32_write(DDRC_SWCTL(0), 0x00000001); - /* step18 wait DFISTAT.dfi_init_complete to 1 */ - do { - tmp = reg32_read(DDRC_DFISTAT(0)); - } while ((tmp & 0x1) == 0x0); - - /* step19 */ - reg32_write(DDRC_SWCTL(0), 0x00000000); - - /* step20~22 */ - tmp = reg32_read(DDRC_MSTR2(0)); - if (tmp == 0x2) { - reg32_write(DDRC_DFIMISC(0), 0x00000210); - /* set DFIMISC.dfi_init_complete_en again */ - reg32_write(DDRC_DFIMISC(0), 0x00000211); - } else if (tmp == 0x1) { - reg32_write(DDRC_DFIMISC(0), 0x00000110); - /* set DFIMISC.dfi_init_complete_en again */ - reg32_write(DDRC_DFIMISC(0), 0x00000111); - } else { - /* clear DFIMISC.dfi_init_complete_en */ - reg32_write(DDRC_DFIMISC(0), 0x00000010); - /* set DFIMISC.dfi_init_complete_en again */ - reg32_write(DDRC_DFIMISC(0), 0x00000011); - } - - /* step23 [5]selfref_sw=0; */ - reg32_write(DDRC_PWRCTL(0), 0x00000008); - /* step24 sw_done=1 */ - reg32_write(DDRC_SWCTL(0), 0x00000001); - - /* step25 wait SWSTAT.sw_done_ack to 1 */ - do { - tmp = reg32_read(DDRC_SWSTAT(0)); - } while ((tmp & 0x1) == 0x0); - -#ifdef DFI_BUG_WR - reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001); -#endif - /* wait STAT.operating_mode([1:0] for ddr3) to normal state */ - do { - tmp = reg32_read(DDRC_STAT(0)); - } while ((tmp & 0x3) != 0x1); - - /* step26 */ - reg32_write(DDRC_RFSHCTL3(0), 0x00000010); - - /* enable port 0 */ - reg32_write(DDRC_PCTRL_0(0), 0x00000001); - printf("DDRINFO: ddrmix config done\n"); - - /* save the dram timing config into memory */ - dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); -} diff --git a/drivers/ddr/imx8m/lpddr4_init.c b/drivers/ddr/imx8m/lpddr4_init.c new file mode 100644 index 0000000000..ee6a8dc686 --- /dev/null +++ b/drivers/ddr/imx8m/lpddr4_init.c @@ -0,0 +1,186 @@ +/* +* Copyright 2018 NXP +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) +{ + int i = 0; + + for (i = 0; i < num; i++) { + reg32_write(ddrc_cfg->reg, ddrc_cfg->val); + ddrc_cfg++; + } +} + +void ddr_init(struct dram_timing_info *dram_timing) +{ + unsigned int tmp; + + printf("DDRINFO: start lpddr4 ddr init\n"); + /* step 1: reset */ + if (is_imx8mq()) { + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000); + } else { + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); + } + + mdelay(100); + + debug("DDRINFO: reset done\n"); + /* change the clock source of dram_apb_clk_root: source 4 800MHz /4 = 200MHz */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); + + /* disable iso */ + reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ + + debug("DDRINFO: cfg clk\n"); + dram_pll_init(DRAM_PLL_OUT_750M); + + /* + * release [0]ddr1_preset_n, [1]ddr1_core_reset_n, + * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n + */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + + /*step2 Configure uMCTL2's registers */ + debug("DDRINFO: ddrc config start\n"); + lpddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); + debug("DDRINFO: ddrc config done\n"); + + /* + * step3 de-assert all reset + * RESET: DEASSERTED + * RESET: for Port 0 DEASSERT(0)ED + */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + + reg32_write(DDRC_DBG1(0), 0x00000000); + /* step4 */ + /* [0]dis_auto_refresh=1 */ + reg32_write(DDRC_RFSHCTL3(0), 0x00000011); + + /* [8]--1: lpddr4_sr allowed; [5]--1: software entry to SR */ + reg32_write(DDRC_PWRCTL(0), 0x000000a8); + + do { + tmp = reg32_read(DDRC_STAT(0)); + } while ((tmp & 0x33f) != 0x223); + + reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ + + /* step5 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* step6 */ + tmp = reg32_read(DDRC_MSTR2(0)); + if (tmp == 0x2) { + reg32_write(DDRC_DFIMISC(0), 0x00000210); + } else if (tmp == 0x1) { + reg32_write(DDRC_DFIMISC(0), 0x00000110); + } else { + reg32_write(DDRC_DFIMISC(0), 0x00000010); + } + + /* step7 [0]--1: disable quasi-dynamic programming */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + + /* step8 Configure LPDDR4 PHY's registers */ + debug("DDRINFO:ddrphy config start\n"); + ddr_cfg_phy(dram_timing); + debug("DDRINFO: ddrphy config done\n"); + + /* + * step14 CalBusy.0 =1, indicates the calibrator is actively + * calibrating. Wait Calibrating done. + */ + do { + tmp = reg32_read(DDRPHY_CalBusy(0)); + } while ((tmp & 0x1)); + + printf("DDRINFO:ddrphy calibration done\n"); + + /* step15 [0]--0: to enable quasi-dynamic programming */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* step16 */ + tmp = reg32_read(DDRC_MSTR2(0)); + if (tmp == 0x2) { + reg32_write(DDRC_DFIMISC(0), 0x00000230); + } else if (tmp == 0x1) { + reg32_write(DDRC_DFIMISC(0), 0x00000130); + } else { + reg32_write(DDRC_DFIMISC(0), 0x00000030); + } + + /* step17 [0]--1: disable quasi-dynamic programming */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + /* step18 wait DFISTAT.dfi_init_complete to 1 */ + do { + tmp = reg32_read(DDRC_DFISTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* step19 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* step20~22 */ + tmp = reg32_read(DDRC_MSTR2(0)); + if (tmp == 0x2) { + reg32_write(DDRC_DFIMISC(0), 0x00000210); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000211); + } else if (tmp == 0x1) { + reg32_write(DDRC_DFIMISC(0), 0x00000110); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000111); + } else { + /* clear DFIMISC.dfi_init_complete_en */ + reg32_write(DDRC_DFIMISC(0), 0x00000010); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000011); + } + + /* step23 [5]selfref_sw=0; */ + reg32_write(DDRC_PWRCTL(0), 0x00000008); + /* step24 sw_done=1 */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + + /* step25 wait SWSTAT.sw_done_ack to 1 */ + do { + tmp = reg32_read(DDRC_SWSTAT(0)); + } while ((tmp & 0x1) == 0x0); + +#ifdef DFI_BUG_WR + reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001); +#endif + /* wait STAT.operating_mode([1:0] for ddr3) to normal state */ + do { + tmp = reg32_read(DDRC_STAT(0)); + } while ((tmp & 0x3) != 0x1); + + /* step26 */ + reg32_write(DDRC_RFSHCTL3(0), 0x00000010); + + /* enable port 0 */ + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + printf("DDRINFO: ddrmix config done\n"); + + /* save the dram timing config into memory */ + dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); +} -- cgit v1.2.3