From 08972759fde2309f36e3c12a482098c9222d12cc Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Thu, 30 Aug 2018 11:05:43 +0200 Subject: imx: imx-common: do not zero out outside of regions There are two issues with the zeroing out code currently: The cache flush does not take the zeroed out section into account! The M4 firmware is started right after copying the firmware, and might use the memory area. Since the M4 and the A7 (where U-Boot is running) are not cache coherent, flushing cache could overwrite the M4's variable at any point in time, leading to crashes of the M4 firmware... Secondly, the program header of a Cortex-M4 firmware might look like this: LOAD off 0x00007240 vaddr 0x20000240 paddr 0x1fffdcdc align 2**12 filesz 0x000001d0 memsz 0x000055c4 flags rw- The code uses paddr as base, and zeros out everything which is beyond file size. This might overlap into the next section! It seems that memsz is in vaddr space and not paddr... Since zeroing out is not strictly necessary (the firmwares C initialization code should do that anyway) better play safe and don't initialize the empty bytes... Signed-off-by: Stefan Agner Acked-by: Marcel Ziswiler --- arch/arm/imx-common/imx_bootaux.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/imx-common/imx_bootaux.c b/arch/arm/imx-common/imx_bootaux.c index 365c32f3dd..793961098f 100644 --- a/arch/arm/imx-common/imx_bootaux.c +++ b/arch/arm/imx-common/imx_bootaux.c @@ -80,9 +80,7 @@ static unsigned long load_elf_image_phdr(unsigned long addr) i, dst, phdr->p_filesz); if (phdr->p_filesz) memcpy(dst, src, phdr->p_filesz); - if (phdr->p_filesz != phdr->p_memsz) - memset(dst + phdr->p_filesz, 0x00, - phdr->p_memsz - phdr->p_filesz); + flush_cache((unsigned long)dst & ~(CONFIG_SYS_CACHELINE_SIZE-1), ALIGN(phdr->p_filesz, CONFIG_SYS_CACHELINE_SIZE)); } -- cgit v1.2.3