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2023-02-09arch: arm: colibri_imx6: set specific soc typeMax Krummenacher
This indirectly enables ARM errata 751472, 794072, 761320, 845369 which all apply to Colibri iMX6. Upstream-Status: Backport [f27ffe4177a7cc09614e2f87012234c1e260c8f2] Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2022-06-27mx6: ddr: Fix disabling on-die terminationFrancesco Dolcini
In case rtt_nom is set to 0 keep ODT disabled (MMDC MPODTCTRL = 0). No changes required for DDR MR1 Rtt_Nom impedance register, 0 value is already handled correctly. No board is currently affected by this change (rtt_nom != 0 on all i.MX6 ddr3 boards), this will be used by a follow-up change. Fixes: fe0f7f7842e1 ("mx6: add mmdc configuration for MX6Q/MX6DL") Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2022-06-27mx6: ddr: Wait before issuing the first MRS cmdFrancesco Dolcini
Upstream commit aa42894471ae6a4e57692f6912690489a1587019 Wait 1ms before issuing the first MRS command to write DDR3 Mode registers. There is a requirement to wait a minimum time before issuing command to the DDR3 device, according to the JEDEC standard this time is 500us (after RESET_n is de-asserted until CKE becomes active) + tXPR (Reset CKE Exit time, maximum value 360ns). It seems that for some reason this is not enforced by the MMDC controller. Without this change we experienced random memory initialization failures with about 2% boot failure rate on specific problematic boards, after this change we were able to do more than 10.000 power-cycle without a single failure. Fixes: fe0f7f7842e1 ("mx6: add mmdc configuration for MX6Q/MX6DL") Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-27mx6: ddr: Restore ralat/walat in write level calibrationFrancesco Dolcini
Upstream commit 09dbac8174c47c6d547c7ab84601fc3424c71dc8 The current DDR write level calibration routine always overwrite the ralat/walat fields to their maximum value, just save the existing values at the beginning of the calibration routine and restore it at the end. In case the delay is estimated by the user to be more than one cycle the walat should be configured according to that, this is not automatically done. From the i.MX6 RM: The user should read the results of the associated delay-line at MPWLDECTRL#[WL_DL_ABS_OFFSET#] and in case the user estimates that the reasonable delay may be above 1 cycle then the user should indicate it at MPWLDECTRL#[WL_CYC_DEL#]. Moreover the user should indicate it in MDMISC[WALAT] field. For example, if the result of the write leveling calibration is 100/256 parts of a cycle, but the user estimates that the delay is above 2 cycles then MPWLDECTRL#[WL_CYC_DEL#] should be configured to 2, so the total delay will be 2 and 100/256 parts of a cycle Probably it would just possible to not overwrite the mdmisc register in the first place, since this is not present in the write_level_calib() example in NXP AN4467 nor in the i.MX6 RM (44.11.6.1 Hardware Write Leveling Calibration). Fixes: d339f16911c7 ("arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL") Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-10imx: mx6ull: fix REFTOP_VBGADJ settingDario Binacchi
[ Upstream commit c1af358cf51a85ed8c47fc576d3cae34196ec47f ] The previous code wrote the contents of the fuse as is in the REFTOP_VBGADJ[2:0], but this was wrong if you consider the contents of the table in the code comment. This table is also different from the table in the commit description. But then, which of the two is correct? If it is assumed that an unprogrammed fuse has a value of 0 then for backward compatibility of the code REFTOP_VBGADJ[2:0] must be set to 6 (b'110). Therefore, the table in the code comment can be considered correct as well as this patch. Fixes: 97c16dc8bf098 ("imx: mx6ull: update the REFTOP_VBGADJ setting") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2021-12-28board: colibri-imx6ull: fix detecting ethernet phyPhilippe Schenker
now that it is possible to use regulator-fixed-clock make use of it. This makes U-Boot detect the PHY on first cold-boot. This commit also adjusts the code in setup_fec and follows how it is done in mx6ullevk.c This commit also slows down the boot-process by about 150ms as it now waits for the regulator-fixed-clock voltage that drives the PHY to go up. If you rely on very fast boot-speeds and don't need ethernet for your boot-process you can safely revert the changes on imx6ull-colibri.dtsi Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
2021-09-20ARM: dts: colibri-imx6ull: fix mac address passingFrancesco Dolcini
colibri-imx6ull ethernet device is fec2, while the optional secondary ethernet is fec1, update the ethernet aliases in the .dts file so that ethaddr is set to fec2 and eth1addr to fec1. Without this change the ethernet interfaces have a different mac address between Linux and U-Boot. Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2021-07-29colibri-imx6ull: add emmc variantMax Krummenacher
Add code to build the eMMC variant of the Colibri iMX6ULL, i.e. the 'Colibri iMX6ULL 1GB' which has a eMMC instead of the raw NAND used on other SKUs. Related-to: ELB-4056, ELB-4057 Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2021-06-10mach-imx: Makefile: append 10k 0x00 at the end of u-boot-nand.imxPhilippe Schenker
Since NXPs 5.4. release zeros are needed at the end of the bootloader. Assume that never more than 10k of padding is needed and skip the shell magic to get a correct size. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
2021-05-26colibri-imx7: full support of tezi-recovery imageOleksandr Suvorov
The recovery image needs to support both Colibri-iMX7 NAND and Colibri-iMX7 eMMC modules. Forward port the solution for this from u-boot 2016.11, originally developed by Stefan Agner <stefan.agner@toradex.com>. Related-to: TEI-775 Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-05-25arm: dts: imx7: Fix error in coresight TPIU graph connectionIlko Iliev
OF graph endpoint connections must be bidirectional and dtc warn if they are not. i.MX7 based DTs have an error and generate warnings: arch/arm/dts/imx7d-sdb.dtb: Warning (graph_endpoint): /replicator/ports/port@0/endpoint: graph connection to node '/soc/tpiu@30087000/port/endpoint' is not bidirectional arch/arm/dts/imx7d-sdb.dtb: Warning (graph_endpoint): /soc/tpiu@30087000/port/endpoint: graph connection to node '/replicator/ports/port@1/endpoint' is not bidirectional Signed-off-by: Ilko Iliev <iliev@ronetix.at>
2021-05-18Makefile: add u-boot-nand.imx targetOleksandr Suvorov
NAND modules (Colibri Vybrid, iMX7, iMX6ULL) require the images with 1024 prepending bytes. Add the u-boot-nand.imx target which enables with CONFIG_IMX_NAND option. Related-to: TEI-775 Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-02-19imx_bootaux: fix elf loadingMax Krummenacher
imx-bootaux loads an elf file linked for an auxilary core. Thus the loader function requires address translation from the auxilary core's address space to where those are mapped into U-Boot's address space. So the elf loader is specific and must not be replaced with a generic loader which doesn't provide the address translation functionality. Fixes commit 805b3cac1e0 ("lib: elf: Move the generic elf loading/validating functions to lib") Related-to: ELB-3520 Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2020-07-20ARM: dts: imx8mm-verdin: eeprom nodes adjustmentsIgor Opaniuk
Rename EEPROM nodes. Create aliases for EEPROM to unify their order: eeprom0 - on-module EEPROM eeprom1 - carrier-board EEPROM eeprom2 - MIPI-DSI to HDMI adapter EEPROM Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-07-20imx: mx7: fix DDRC size in A7-M4 mapping tableIgor Opaniuk
According to i.MX 7Solo Applications Processor Reference Manual, 2.1.3 Cortex-M4 Memory Map, M4 can address only 1536MB of DDRC (Start Address: 0x8000_0000; End Address: 0xDFFF_FFFF). Correct DDRC size to 0x60000000. Fixes: c0f037f6("mach-imx: bootaux: elf firmware support") Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-07-15ARM: dts: imx7-colibri: multiple node updatesIgor Opaniuk
1. Move u-boot specific nodes to u-boot dts include: legacy lcdif node and aliases. 2. Add iomux configuration for LCD. 3. Drop un-needed u-boot,dm-pre-reloc for alias node. 4. Fix display-timings, use the one from Toradex downstream kernel [1] [1]: https://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi?h=toradex_4.9-2.3.x-imx#n206 Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-07-15ARM: dts: imx6ull-colibri: move u-boot specific nodeIgor Opaniuk
1. Move aliases and legacy lcdif node to the u-boot specific dts include. 2. Provide proper display timings, as in the downstream Toradex kernel [1]. [1]: https://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi?h=toradex_4.9-2.3.x-imx#n183 Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-07-05sandbox, test: add test for GPIO_HOG functionHeiko Schocher
currently gpio hog function is not tested with "ut dm gpio" so add some basic tests for gpio hog functionality. For this enable GPIO_HOG in sandbox_defconfig, add in DTS some gpio hog entries, and add testcase in "ut dm gpio" command. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-03riscv: use log functions in fdt_fixupHeinrich Schuchardt
Replace printf() and debug() by log_err() and log_debug(). "No reserved memory region found in source FDT\n" is not an error but a debug information. %s/can not/cannot/ - use the more common spelling. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-07-03riscv: sifive: fu540: enable all cache ways from U-Boot properPragnesh Patel
Add L2 cache node to enable all cache ways from U-Boot proper. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-03riscv: Use optimized version of fdtdec_get_addr_size_no_parentAtish Patra
fdtdec_get_addr_size_no_parent is not an optimized version if parent node is already available with the caller. Use fdtdec_get_addr_size_auto_parent to read the "reg" property Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-03riscv: Do not return error if reserved node already existsAtish Patra
Not all errors are fatal. If a reserved memory node already exists in the destination device tree, we can continue to boot without failing. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-03riscv: Do not build reset.c if SYSRESET is onBin Meng
SYSRESET uclass driver already provides all the reset APIs, hence exclude our own ad-hoc reset.c implementation. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-02riscv: Enable CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATEBin Meng
Starting from OpenSBI v0.7, the SBI firmware inserts/fixes up the reserved memory node for PMP protected memory regions. All RISC-V boards need to copy the reserved memory node from the device tree provided by the firmware to the device tree used by U-Boot. Turn on CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-07-02riscv: Expand the DT size before copy reserved memory nodeBin Meng
The FDT blob might not have sufficient space to hold a copy of reserved memory node. Expand it before the copy. Reported-by: Rick Chen <rick@andestech.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-07-02riscv: Avoid the reserved memory fixup if src and dst point to the same placeBin Meng
The copy of reserved memory node from source dtb to destination dtb can be avoided if they point to the same place. This is useful when OF_PRIOR_STAGE is used. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-07-02riscv: fu540: dts: Correct reg size of otp and dmc nodesBin Meng
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-02riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc nodeBin Meng
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-06-28Merge tag 'u-boot-rockchip-20200628' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - rk3188 cpu init and APLL fix; - rk3399: Add BOOTENV_SF command; - rk3288 correct vop0 vop1 setting;
2020-06-27rockchip: rk3188: Fix back to BROM bootAlexander Kochetkov
Move the setting for noc remap out of SPL code. Changing noc remap inside SPL results in breaking back to BROM boot. Fixes commit c14fe2a8e192 ("rockchip: rk3188: Move SoC one time setting into arch_cpu_init()"). Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-26arm: socfpga: misc_s10: Fix EMAC register address calculationLey Foon Tan
Fix EMAC register address calculation, address need to multiply with sizeof(u32) or 4. This fixes write to invalid address. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-06-25ARM: dts: imx6q-tbs2910: Fix Ethernet regressionFabio Estevam
Since commit: commit 6333cbb3817ed551cd7d4e92f7359c73ccc567fc Author: Michael Walle <michael@walle.cc> Date: Thu May 7 00:11:58 2020 +0200 phy: atheros: ar8035: remove static clock config We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> , the clock output setting for the AR803x driver is removed from being hardcoded in the PHY driver and should be passed via device tree instead. Update the device tree with the "qca,clk-out-frequency" property so that Ethernet can work again. Reported-by: Soeren Moch <smoch@web.de> Signed-off-by: Fabio Estevam <festevam@gmail.com> Tested-by: Soeren Moch <smoch@web.de>
2020-06-23mx6cuboxi: enable MMC and eMMC in DT for SPLWalter Lozano
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
2020-06-23arm: dts: imx: fsl-imx8qm.dtsi: fix gpio aliasesYe Li
Current aliases missed gpio0 node, and this node shoud be aliased to gpio index 0 to align with i.MX8QXP. Otherwise, we will get below message when running "gpio status" command, and see the reason by "dm uclass". => gpio status Device 'gpio@5d090000': seq 0 is in use by 'gpio@5d080000' Device 'gpio@5d0a0000': seq 1 is in use by 'gpio@5d090000' Device 'gpio@5d0b0000': seq 2 is in use by 'gpio@5d0a0000' => dm uclass uclass 36: gpio 0 * gpio@5d080000 @ fbaefb90, seq 0, (req -1) 1 * gpio@5d090000 @ fbaefc70, seq 1, (req 0) 2 * gpio@5d0a0000 @ fbaefd50, seq 2, (req 1) 3 * gpio@5d0b0000 @ fbaefe30, seq 5, (req 2) 4 * gpio@5d0c0000 @ fbaeff10, seq 3, (req 3) 5 * gpio@5d0d0000 @ fbaefff0, seq 4, (req 4) 6 * gpio@5d0e0000 @ fbaf00d0, seq 6, (req 5) 7 * gpio@5d0f0000 @ fbaf01b0, seq 7, (req 6) Signed-off-by: Ye Li <ye.li@nxp.com>
2020-06-22ARM: imx: soc: Select default TEXT_BASE for MX7Marek Vasut
Select default U-Boot and SPL text base for the MX7 SoC. The U-Boot text base is picked as the one used by various MX7 boards. The SPL text base however is different. The SPL text base is set to 0x912000 instead of the usual 0x911000, that is because the 0x911000 value cannot work. Using 0x911000 as a SPL text base will result in the DCD header being placed below the 0x911000 address, which is a reserved SRAM area which must not be used. This will actually trigger eMMC boot failure on MX7D at least. Hence the increment. Update all boards affected by this SPL problem to the new SPL_TEXT_BASE. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2020-06-22ARM: imx: soc: Switch BOARD_EARLY_INIT_F to imply on MX7Marek Vasut
There are systems where board_early_init_f() is plain empty. Switch the config option from "select" to "imply", to permit user to unset the BOARD_EARLY_INIT_F if it were to be empty. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2020-06-22ARM: imx: ddr: Fill in missing DDRC ZQCTLx on i.MX7Marek Vasut
The iMX7 defines further DDRC ZQCTLx registers, however those were thus far missing from the list of registers and not programmed. On systems with LPDDR2 or DDR3, those registers must be programmed with correct values, otherwise the DRAM may not work. However, existing systems which worked without programming these registers before are now setting those registers to 0, which is the default value, so no functional change there. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2020-06-22ARM: dts: imx6qdl-sabresd: Fix AR8031 phy-modeFabio Estevam
As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode) the correct phy-mode should be "rgmii-id", so fix it accordingly to fix the Ethernet regression. This problem has been exposed by commit: commit 13114f38e2ccea9386726d8b9831dfc310589548 Author: Vladimir Oltean <vladimir.oltean@nxp.com> Date: Thu May 7 00:11:51 2020 +0200 phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-06-22ARM: dts: imx6qdl-sabreauto: Fix AR8031 phy-modeFabio Estevam
As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode) the correct phy-mode should be "rgmii-id", so fix it accordingly to fix the Ethernet regression. This problem has been exposed by commit: commit 13114f38e2ccea9386726d8b9831dfc310589548 Author: Vladimir Oltean <vladimir.oltean@nxp.com> Date: Thu May 7 00:11:51 2020 +0200 phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Fix the phy-mode accordingly to fix the regression. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-06-22ARM: dts: imx6qdl-sr-som: Sync with kernel 5.8-rc1Fabio Estevam
Sync the device tree with 5.8-rc1. It basically contains the following extra kernel commit: commit 86b08bd5b99480b79a25343f24c1b8c4ddcb5c09 Author: Russell King <rmk+kernel@armlinux.org.uk> Date: Wed Apr 15 16:44:17 2020 +0100 ARM: dts: imx6-sr-som: add ethernet PHY configuration Add ethernet PHY configuration ahead of removing the quirk that configures the clocking mode for the PHY. The RGMII delay is already set correctly. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> , which passes the 'qca,clk-out-frequency' property and it is important to specify the correct frequency generated by the AR8035. Signed-off-by: Fabio Estevam <festevam@gmail.com> Tested-by: Tom Rini <trini@konsulko.com>
2020-06-19Merge tag 'u-boot-stm32-20200619' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - fix SD card cart detect on DHCOM and ST boards
2020-06-19ARM: dts: stm32: Reinstate card detect behavior on ST boardsPatrick Delaunay
The cd-gpios with (GPIO_ACTIVE_LOW | GPIO_PULL_UP) gpio is thus far unsupported, reinstate the old cd-gpios behavior until this handling is fully implemented. This avoid potential issue for SDCard boot: the card detect fails with floating gpio. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-06-19ARM: dts: stm32: Reinstate card detect behavior on DHSOMMarek Vasut
The cd-gpios with (GPIO_ACTIVE_LOW | GPIO_PULL_UP) gpio is thus far unsupported, reinstate the old cd-gpios behavior until this handling is fully implemented. This permits the DHSOM to boot from SD again, without this patch the card detect fails. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-06-18ARM: tegra: Enable PSCI support for Tegra210 and Tegra186Jon Hunter
The PSCI nodes are currently not populated for the Tegra210 and Tegra186 devices. This prevents the PSCI driver from being able to identify the PSCI method used by these devices and causes the probe of the PSCI driver to fail. Since commit 81ea00838c68 ("efi_loader: PSCI reset and shutdown") was added, which moves the PSCI EFI system reset handler into the PSCI driver, this has prevented the EFI system reset from working for Tegra210 and Tegra186. Therefore, populating these nodes is necessary to fix the EFI system reset for Tegra210 and Tegra186. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
2020-06-16dts: ARM: stm32mp15: add OP-TEE node in u-boot DTSIEtienne Carriere
Add OP-TEE firmware node in stm32mp15 U-Boot DTSI. This node is needed since commit [1] that changed U-Boot/stm32mp15 to detect OP-TEE availability by probing the resource instead of relying on U-Boot configuration. The software sequence implemented by [1] is fine but U-Boot DTS/DTSI files were not updated accordingly since, hence OP-TEE presence is never detected by U-Boot, preventing Linux kernel from using OP-TEE resources. For consistency and to synchronize stm32mp15 DTSI files (excluding U-Boot specific DTSI files) with the Linux kernel ones, this change also moves the OP-TEE reserved memory nodes from board generic DTSI files to U-Boot specific board DTSI files. Link: [1] commit 43df0a159df6 ("stm32mp1: dynamically detect op-tee presence") Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-06-16board: stm32mp1: fix handling of DT OP-TEE reserved memory nodesEtienne Carriere
Fix the sequence in stm32mp1 fdt.c that disables OP-TEE resources defined in FDT when U-boot detects OP-TEE firmware is not present. Before this change, helper function stm32_fdt_disable_optee() set property status to "disabled" for the OP-TEE reserved memory nodes but this has no impact since Linux kernel does not consider the status property for reserved-memory subnodes. This change make U-Boot to attempt to delete the node instead. Fixes: 4a1b975dac02 ("board: stm32mp1: reserve memory for OP-TEE in device tree") Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-06-15Merge tag 'mmc-2020-6-15' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini
- fsl_esdhc sdr104 and hs200 fix and error path fix - fsl_esdhc workaround 3.3v io issue - ca_dw_mmc cleanup - presidio-asic emmc DT update.
2020-06-15board: presidio-asic: update eMMC DT informationAlex Nemirovsky
Change DT compatibility name to match change in driver's name. Remove unused io_ds and fifo_mode fields from DT. Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Peng Fan <peng.fan@nxp.com> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Tom Rini <trini@konsulko.com>
2020-06-14Merge https://gitlab.denx.de/u-boot/custodians/u-boot-socfpgaTom Rini
- cyclone5 bugfix
2020-06-14arm: dts: socfpga: cyclone5: Update i2c-scl-falling-time-nsLey Foon Tan
Commit e71b6f6622d6 ("i2c: designware_i2c: Rewrite timing calculation") change the hcnt and lcnt timing calculation. New timing calculation is based on calculation from Designware i2c databook. After this new timing calculation, hcnt will have negative value with i2c-scl-falling-time-ns 5000 that set in socfpga_cyclone5_socdk.dts. This patch overwrite i2c-scl-falling-time-ns to 300ns (default SCL fall time used in Designware i2c driver) for Uboot. Before the fix: => i2c dev 0 Setting bus to 0 Failure changing bus number (-22) After the fix: => i2c dev 0 Setting bus to 0 => i2c probe Valid chip addresses: 17 51 55 5B 5C 5E 66 68 70 Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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